DVD4250D_Service_Man DVD4250

User Manual: DVD4250

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1
DVD4250D
DVD PLAYER
SERVICE MANUAL
2
1. GENERAL DESCRIPTION
1.1 ES66x8
The ES66x8 Vibratto II processor is a highly integrated single-chip DVD solution that integrates read
channel, ECC, Servo DSP, MCU, and MPEG-2/MPEG-4/DivX decoder that has a state-of-the-art 480p/576p
progressive-scan video feature to provide brilliant and sharp, flicker-free video output to the display, and with
built-in gamma correction and S/PDIF input and output support. The 66x8 performs audio/video stream data
processing, TV encoding, Macrovision copy protection, DVD system navigation, system control, and
housekeeping functions.
The Vibratto II DVD processor is built on the ESS proprietary dual CPU Programmable Multimedia
Processor (PMP) core consisting of 32-bit RISC and 64-bit DSP processors and offers the best DVD feature set.
These features can be listed as follows:
General Features:
− Single -chip DVD processor incorporating all front-end and back-end functions.
− Unified memory architecture.
− Built-in ADCs and DACs for servo control signals .
− DVD-Video, DVD-VR, VCD 1.1 and 2.0 and SVCD
− Proven ECC, EFM/EFM+ demodulation, and EDC circuit.
− Direct interface of 16-bit DRAM up to 128-Mb capacity.
− Direct interface of 8- or 16-bit SDRAM up to 128-Mb capacity.
− Direct interface for up to 4 banks of 8-bit EPROM or Flash EPROM for up to 4 MB per bank.
− Direct interface to the ES6603 servo AFE chip.
Video Related Features:
− Integrated NTSC/PAL encoder with pixel-adaptive de-interlacer and five 10-bit 54 MHz video DACs .
− DivX and MPEG-4 Advanced Simple Profile at full screen.
− Media playback with CD-ROM, CD-R/RW, DVD-R/RW and DVD+R/RW.
− Macrovision 7.1 for NTSC/PAL interlaced video.
− Macrovision NTSC/PAL (480p/576p) progressive scan video.
− Simultaneous composite, S-video and YUV outputs.
− CCIR656/601 YUV 4:2:2 output.
− OSD controller supports 256 colors in 8 degrees of transparency.
− JPEG digital photo CD support ( Kodak Picture CD and Fujifilm FujiColor CD ).
3
Audio Related Features:
− Full DVD-Audio support including MLP and LPCM decode, CPPM decryption, and watermark detection.
− Up to 7.1 channel audio outputs .
− Bass management.
− Dolby Digital ( AC-3 ), Dolby Pro Logic, and Pro Logic II.
− DTS surround ( ES6698 only ).
− S/PDIF digital audio input and output.
− SRS TruSurround.
− Professional karaoke with full scoring scheme.
1.2 MEMORY
1.2.1 System SRAM Interface
The system SRAM interface controls access to optional external SRAM, which can be used for RISC
code, stack, and data. The SRAM bus supports four independent address spaces, each having programmable bus
width and wait states. The interface can support not only SRAM, but also
ROM/EPROM and memory-mapped I/O ports for standalone applications are supported.
1.2.2 DRAM Memory Interface
The Vibratto II provides a glueless 16-bit interface to DRAM memory devices used as video memory
for a DVD player. The maximum amount of memory supported is 16 MB of Synchronous DRAM (SDRAM).
The memory interface is configurable in depth to support 128-Mb addressing. The memory interface controls
access to both external SDRAM or EDO memories, which can be the sole unified external read/write memory
acting as program and data memory as well as various decoding and display buffers.
1.3 FRONT PANEL
The front panel is based around an Futaba VFD and a common front panel controller chip, (uPT6311).
The ES66x8 controls the uPT6311 using several control signals, (clock, data, chip select). The infrared remote
control signal is passed directly to the ES66x8 for decoding.
1.4 REAR PANEL
A typical rear panel is included in the reference design. This rear panel supports:
- six channel and two channel audio outputs
- Optical and coax S/PDIF outputs.
- Composite, S-Video, and SCART outputs
The six-video signals used to provide CVBS, S-Video, and RGB are generated by the ES66x8’s internal video
DAC. The video signals are buffered by external circuitry.
Six channel audio output by the ES66x8 in the form of three I
2S (or similar) data streams. The S/PDIF serial
stream is also generated by the ES66x8 output by the rear panel. A six channel audio DAC are used for six
channel audio output with ES66x8, and similarly one Audio DAC is used for two channel audio output with
ES66x8.
4
2. System Block Diagram and ES66x8 Pin Description
2.1 ES66x8 Pin Description
5
6
7
8
9
2.1 SYSTEM BLOCK DIAGRAM
A sample system block diagram for the ES66x8 Vibratto II DVD player board design is shown in the
following figure:
10
3. AUDIO OUTPUT
The ES66x8 supports two-channel analog audio output while ES66x8 supports six-channel analog audio output.
In a system configuration with six analog outputs, the front left and right channels can be configured to provide
the stereo (2 channel) outputs and Dolby Surround, or the left and right front channels for a 5.1 channel surround
system.
The ES6008 also provides digital output in S/PDIF format. The board supports both optical and coaxial S/PDIF
outputs.
3. AUDIO DACS
The ES66x8 supports several variations of an I
2S type bus, varying the order of the data bits (leading or no
leading zero bit, left or right alignment within frame, and MSB or LSB first) is possible using the ES66x8
internal configuration registers. The I2S format uses four stereo data lines and three clock lines. The I2S data and
clock lines can be connected directly to one or more audio DAC to generate analog audio output.
The two-channel DAC is an CS4392. The DACs support up to 192kHz sampling rate.
The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuits
use National LM833 op-amps to perform the low-pass filtering and the buffering.
5 VIDEO INTERFACE
5.1 Video Display Output
The video output section controls the transfer of video frames stored in memory to the internal TV encoder of the
Vibratto II. The output section consists of a programmable CRT controller capable of operating either in Master
or Slave mode.
11
The video output section features internal line buffers which allow the outgoing luminance and chrominance data
to match the internal clock rates with external pixel clock rates, easily facilitating YUV4:2:2 to YUV4:2:0
component and sample conversion. A polyphase filter achieves arbitrary horizontal decimation and interpolation.
Video Bus
The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in CCIR1656 pixel
format (4:2:2). In this format, there are half as many chrominance (U or V) pixels per line as luminance (Y)
pixels; there are as many chrominance lines as luminance.
Video Post-Processing
The Vibratto II video post-processing circuitry provides support for the color conversion, scaling, and filtering
functions through a combination of special hardware and software. Horizontal up-sampling and filtering is done
with a programmable, 7-tap polyphase filter bank for accurate
non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in accordance with the
applicable scaling ratio.
Video Timing
The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock. The
double clock typically is used for TV displays, the single for computer displays.
6 SDRAM MEMORY
The memory bus interface generates all the control signals to interface with external memory. The Vibratto II
supports different configurations using the memory configuration bits SDCFG[1:0] (bits 12:11), the SD8BIT bit
(bit 14), and SD64M bit (bit 15) in the BUSCON_DRAM_CONTROL register. Configurations can be
implemented in many ways. The following table lists the typical SDRAM configurations used by the Vibratto II.
Typical SDRAM Configurations:
The memory interface controls access to both external SDRAM or EDO memories, which can be the sole unified
external read/write me mory acting as program and data memory as well as various decoding and display buffers.
At high clock speeds, the Vibratto II memory bus interface
12
has sufficient bandwidth to support the decoding and displaying of CCIR1656/601 resolution images at full
fra me rate.
7 FLASH MEMORY
The decoder board supports AMD class Flash memories. Currently 4 configurations are supported:
FLASH_512K_8b
FLASH_1024K_8b
FLASH_512Kx2_8b
FLASH_512Kx2_16b
The Vibratto II permits both 8- and 16-bit common memory I/O accesses with a removable storage card via the
host interface.
8 SERIAL EEPROM MEMORY
An I2C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup,
etc.) and software configuration.. Industry standard EEPROM range in size from 1kbit to 256kbit and share the
same IC footprint and pinout. The default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or
equivalent.
9 AUDIO INTERFACE AUDIO SAMPLING RATE AND PLL COMPONENT
CONFIGURATION
The ES66x8 Vibratto II audio mode configuration is selectable, allowing it to interface directly with
low-cost audio DACs and ADCs. The audio port provides a standard I2S interface input and output and S/PDIF
(IEC958) audio output. Stereo mode is in I2S format while six channels Dolby Digital (5.1 channel) audio output
can be channeled through the S/PDIF. The S/PDIF interface consists of a bi-phase mark encoder, which has low
skew. The transmit I
2S interface supports the 128, 192, 256, 384, and 512 sampling frequency formats, where
sampling frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the I2S
transmit interface can be 16, 18, 20, 24, and 32-bit samples.
For Linear PCM audio stream format, the Vibratto II supports 48 kHz and 96 kHz. Dolby Digital audio
only supports 48 kHz. The ES6008/18 Vibratto II incorporates a built-in programmable analog PLL in the device
architecture in order to generate a master audio clock. The MCLK pin is for the audio DAC clock and can either
be an output from or an input to the ES66x8 Vibratto II . Audio data out (TSD) and audio frame sync (TWS) are
clocked out of the Vibratto II based on the audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is
used to clock in audio data in (RSD) and audio receive frame sync (RWS).
10 FRONT PANEL
10.1 VFD CONTROLLER
The VFD controller is a PTC PT6311. This controller is not a processor, but does include a simple state
machine which scans the VFD and reads the front panel button matrix. The 6311 also includes RAM so it can
store the current state of all the VFD icons and segments. Therefore, the 6311 need only be accessed when the
VFD status changes and when the button status is read. The ES66x8 can control this chip directly using PIO pins
or can allow the front panel PIC to control the VFD.
11 MISCELLANEOUS FUNCTIONS
11.1 RESET CIRCUITRY
Two different chips are supported to provide the power-on-reset and pushbutton reset function:
AAT3521 or V6300.
13
12 CONNECTORS
12.1 SCART CONNECTORS
Pinout of the scart connector:
1 ? Audio Right Out
2 ? Audio Right In
3 ? Audio Left / Monu Out
4 ? Audio Gnd
5 ? Blue Gnd
6 ? Audio Left / Mono In
7 ? Blue
8 ? Control Voltage
9 ? Green Gnd
10 ? Comms Data 2
11 ? Green
12 ? Comms Data 1
13 ? Red Gnd
14 ? Comms Data Gnd
15 ? Red
16 ? Fast Blanking
17 ? Video Gnd
18 ? Fast Blanking Gnd
19 ? Composite Video In
20 ? Composite Video Out
21 ? Shield
Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable lengths. For
longer lengths, shielded coax cable become essential.
Scart Signals:
Audio signals
0.5V RMS, <1K output impedance, >10K input impedance.
Red, Green, Blue
0.7Vpp ?2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the
S-VHS Chrominance signal, which is 0.3V.
Composite Video / CSync
1Vpp including sync, ?2dB, 75R input and output impedance.Bandwidth = 25Hz to 4.8MHz for normal TV
Video de-emphasis to CCIR 405.1 (625-line TV)
Fast Blanking
75R input and output impedance. This control voltage allows devices to over-ride the composite video input with
RGB inputs, for example when inserting closed caption text. It is called fast because this can be done at the same
speeds as other video signals, which is why it requires the same 75R impedances.
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0 to 0.4V: TV is driven by the composite video input signal (pin 19).
Left unconnected, it is pulled to 0V by its 75R termination.
1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the
TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such as home
computers with TV-compatible frame rates. Tying the signal to 5V via 100R forms a potential divider
with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V)
negative sync pulse is available, this will be high during the display periods, so this can drive the
blanking signal via a suitable resistor.
Control Voltage
0 to 2V = TV, Normal.
5 to 8V = TV wide screen
9.5 to 12V = AV mode
13. CIRCUIT DESCRIPTION
13.1 POWER SUPPLY:
− Socket PL2 is the 220VAC input.
− Socket PL3 is used for the power button on the front panel.
− 3.15A fuse F1 is used to protect the device against short circuit.
− Voltage is rectified by using diodes D1, D2, D3 and D4. Using capacitor C33 (47?f) a DC voltage is
produced. (310- 320VDC).
− The current in the primary side of the transformer TR2 comes to the SMPS IC (TNY267P). It has a built-in
oscillator, over current and thermal protection circuitry and runs at 133kHz. It starts with the current from
the primary side of the transformer and follows the current from the feedback winding.
− Voltages on the secondary side are as follows: 12 Volts at pin11 at C42, 5 Volts at C40,3.3 Volts at C38,
-22Volts at C44,-12 Volts at D22.
− D14 TL431 is a constant current regulator. TL431 watches the 5 volts and supplies the required current to
IC2. There are a LED and a photo transistor in IC2. The LED inside the IC2 transmits the value of the
current from D25 to phototransistor. Depending on the current gain of the phototransistor IC3 keeps the
voltage on the 5-volt-winding constant.
− –22 Volts is used to feed the VFD (Vacuum Fluorescent Display) driver IC on the front panel.
15
Functional Block Diagram of Switcher
13.2 FRONT PANEL:
− All the functions on the front panel are controlled by U1 (ES66x8) on the mainboard.
− U1 sends the commands to IC2 PT6311 via socket J2 (pins 3,4 and 5).
− There are 48 keys scanning function, 5 LED outputs, 1 Stand-by output and VFD drivers on PT6311.
− Vacuum fluorescent display is specially designed for DVD.
− The scanned keys are transmitted via PT6311 to U1 on the mainboard.
− IR remote control receiver module sends the commands from the remote control directly to U1.
13.3 BACK PANEL:
− There are 1 SCART connector (con24), 2 pieces RCA audio jacks for audio output, 1 coaxial digital audio
output and 1 laser digital audio output on the back panel.
− MOFT3C2 is used for laser output.
− Left and right audio outputs are on RCA Conn 6.
− LUMA and CHROMA signals of S-Video are transmitted to P1 via transistors Q39 and Q37 respectively.
16
CD Update Procedure of 4250D
1. Download the update file from the convenient link according to your default language choice.
2. While there is no CD in the DVD (No Disc Mode) , press “Menu 1 3 5 7” buttons on the remote control
in order to reach the Service Menu of DVD Player:
2.1. Note the software version described as “b.xx “ to be able to compare the sw. Version after update
process.
3. Copy the update file to the desktop and rename it according to the update file name in the hidden menu of
the device.
For example If C2M1AS__ is written then rename it like C2M1AS__.rom
If P6M1AS__ is written then rename it like P6M1AS__.rom
(If you receive the update file already renamed (with addition of .rom) from the customer technical support
department by giving the SAP code of the product then burn the already renamed file with nero program as
it is shown below.)
4. Burn the renamed files by Nero program with below set up.
5. After burning process is completed, place the update CD into the DVD tray and press play button.
6. Wait to see the update process steps as shown below. When the sw. Update is completed unit will switch
itself to standby mode.
7. Finally, press the eject button and take out the update CD while DVD Player remains at stand by Mode.
8. Updating process has been completed. To check whether it is updated correctly or not, repeat the first step
for comparing software version
9. If the previous and letter names are different, CD is update has completed successfully. If the name remains
same than go through the steps from the beginning.
IMPORTANT NOTE: If the AC source breaks down while the updating the unit (main board) will be
totally out of order. This kind of units/boards is out of Warranty.
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Brief Information of Naming the File
Software version differs from each other depending on front models. 23xx and 24xx are called Old VFD and
25xx and 26xx are called Mini VFD. Each character in the file name is an abbreviation of a description as
illustrated below.
C2M1AS__
Progressive Option (with progressive : P, without progressive: _ )
DMR option (with DMR:R, without DMR:_ )
Loader Type (S loader:s W loader:w)
Flash Type ( AMD:A, Intel:I )
Language group
VFD type
DAC channel (2, 6)
DAC Type
18
Pay attention the left side. Select CD and CD_ROM (ISO) on the upper left side of screen
19
Select No Multisession
20
Format is Mode 1
21
22
Leave the dates as it is
23
Leave it as it is
24
Click the “New” on the upper right corner of the screen
25
Select your file from file browser then you will see your file in the “Name” section on the right side and then
copy the files to under “Name” section on the left side.(this is just an example you will see your file name when
you are doing this process)
26
Click the “Burns the current compilation”
27
Then you will see this screen and click the “Burn” on the right upper side of screen
28
You will see this screen and tray will open itself on computer ,then place the CD in CD-ROM
And it will start writing. At the end you will see “burn complited”
.
TMS28F400Axy
4-PIN EXTENSION FOR ROM EMULATOR INTERFACE
32/64MBIT SDRAM
EM-MARIN
RESET IC
SERIAL EEPROM
reserved 5
0
4.25
114.75
121.5
bypass
1
4.25
0
PLL0
108
0 1
162
1
11
NA
0135
S-CHIP
0
NA
3.75
PLL2
1
Frequency
0
4148.5
4
1121.5
0
101.25
reserved
1 27bypass
06
DEFAULTPLL1
5.5
DEFAULT
1
4.75
4.501
MULTI
0S-CHIP 114.75
1
1
128.25
108
3.5
4.5
NA
94.5
0
0
PLL3
0
CLK SOURCE
1
CRSTAL OSC
DCLK INPUT
Vibratto-II
FLASHR34, R68
EPROM
R32, R35
INSTALL REMOVE TYPE
R34, R68 R32, R35
YG
B
C
CVBS CVBS
YDAC
B
FDACU
S-VIDEO + RGB
Y
CVBS
CDAC
U
VDAC
C
Y
CVBS + S-VIDEO
or CVBS + YUV
CVBS
CVBS + RGB
VIDEO OUTPUT TABLE
VG
CVBS
R R
CVBS + YUV
V
UDAC
SERVO MCU
DEBUG
HEADER
VFD-DATA
GND
IR
+5V
VFD-CS
VFD-CLK
V6300 OPEN
AAT35210
R37
0
U10OPEN
R36
AM5868 BA5954
CC280.015U7.5nF
VESTEL-4250H-A1
A1
Vibratto-ll ES66X8
VESTEL
C
2 5Wednesday, March 03, 2004
Title
SizeDocument Number Rev
Date: Sheet of
SLDC
DEFCT
SPDON
LA16
LA11
LA19
DWE#
SFGIN
DB6
DB1
LD1
LA12
VCC33V
LA13
FOCUS
RFRP
XFLAG2
MA8
MA1
LD6
LA4
LA18
SCLK
LA6
SLEGP
DIP
DB12
MA2
WRLL#
MA6
SPINDLE
LA3
SCSJ
LD1LA1
FEI
XFLAG3
RFO
MA5
MA11
MA4
LA17
LA2
SPDON
TR1
DB3
LD0LA6
LA7
LA19
WRLL#
LA14
RFO
SBAD
MA0
LA1
SDATA
FOCUS
LCS3#
LD5
LA15
LA10
WRLL#
LCS2#
DB14
DB10
DB5
LA21
MA7
LA0
LA5
LA11
LA8
DIN
DSCK
VFD-CLK
MA10
XFLAG1
LD5
LD2
LA10
SPINDLE
LD3
LA5
LA3
MA9
MA0
MA8
TESTAD
FEI
DQM
DB15
DB13
DB9
MA6
MA2
LOE#
LD0
CAS#
RAS1#
MA10
LD7
RESET#
SVREF15
LA17
LOE#
LA12
SLEGN
DB11
RESET#
LA9
TRACK
XFLAG0
LD4
LA14
LA9
RAS0#
TEI
MA5
MIRR
LA7
VFD-CS
IR
DOE#
DB8
MA3 DB4
DB0
LD3
LD7
LD6
LD2
LA4
LA2
LA0
LA18
RAS2#
MA4
DB2
MA9
LD4
DA
DA
TEI
CEI
DIN
CEI
VFD-DATA
CS0#
MA7
MA3
LA8
TRACK
MA1
DB7
MA11
LA13
LA15
LA16
DIP
RFRP
LA13
DSCK
RAS0#
DMA3
SLEGP WRLL#
LA4
DB15
RESET#
DEFCT
RXD
LD4
LCS3#
RFGND
FDAC1
SLDC
TR1
TXD
TBCK
LA0
LA3
LA6
LA10
LA11
LA17
DB1
DMA6
DB3
DB0
DMA1
SPDIF
FDAC1
DQM
DOE#
RAS2#
TSD0
COMP
LD1
LD0
LCS2#
LA21
DB10
DB6
TR2
UDAC1
VS33_PL2
LOE#
LA7
DB8
DMA10
XSDATA
SFGIN
TR2
SVREF15
LD7
LA15
DB12
DB5
DWE#
DMA5
SVREF15
UDAC1
LA5
LA12
DB11
CAS#
DMA2
DMA0
TSD1
TWS
GNDV
RSET
VREF
VD33_PL1
LD3
VDAC1
DCLK
TESTAD
XFLAG2
LA14
DB14
RAS1#
DMA4
YDAC1
SPDON
XSCSJ
XFLAG1
LA2
LA18
LA19
DB13
DB4
CS0#
DMA11
CDAC1
LD5
LA8
DB2
DMA9
DMA7
SVREF15
CDAC1
XFLAG3
VDAC1
LA1
DB9
XOUT
XFLAG0
MCLK
YDAC1
VCC33V
LA9
LA16
DB7
DMA8
XSCLK
TSD2
LD6
LD2
XIN
LA20
LA20
LA20
RXD
RS232_DET
TXD
VFD-CS
VFD-CLK
VCC
VFD-DATA
IR
RESET#
SLEGN
LCS2#
RS232_DET
RS232_DET
SVREF21
SVREF21
SVREF09
EAUX40
EAUX41
EAUX43
EAUX42
TESTAD
RFRP
LCS3#
SPINDLE(3)
SDEFCT (3)
SPDON (3)
OPEN(3)
SLDC (3)
FOCUS(3)
SVREF15(3)
TRACK(3)
SLEGN(3)
MIRR(3)
TEI(3)
RFO(3)
CEI(3)
DIN(3)
FEI(3)
DIP(3)
SBAD(3)
SCSJ(3)
SDATA(3) SCLK(3) INSW(3)
HOMESW(3) CLOSE(3) OUTSW(3) DRVSB(3)
UDAC (5)
YDAC (5)
VDAC (5)
FDAC (5)
SPDIF (5)
TBCK (4)
MCLK (4)
TSD2 (4)
TSD1 (4)
TSD0 (4)
TWS (4)
NN(5)
SCART-ON(5)
EAUX41(4) EAUX42(4)
EAUX40(4)
EAUX43(4)
CDAC (5)
MOCTL(3)
SVREF21(3)
RESET# (3)
ATR_OP(3)
PLL33V
RF33V
VCC33
VCC
GND
VCC33
GND
VCC
GND
GNDV
GNDV
GNDVGNDV
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV VCCV
VCCV
VCCV
VCCV
VCCV
GND GNDGND
GND
VCC
VCCV VCC
GND
VCC20
VCC33V
RFGND
RFGND
RFGND
VCC33
GND
GND
PLLGNDRFGND
GNDV
GNDV
GNDV
GNDV
VCC20
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
VCC33
VCC
GND
GND
VCC
GND
VCC
VCC
GNDGND GNDGND GND
VCC33
VCC33 VCC33VCC33VCC33
D13
1N6263
2 1
D1
1N6263
2 1
R41 33
R42 100K
U7
ROM EMULATOR SOCKET
1 2
3 4
RESET CLK/CE1
WE ADDR/CE1
CC31
0.015U
CC14
0.1U
R68 0 OHM
RR22 6.8K
L2 2.4UH
CC32
0.015U
R6
75 OHM
R52
1K
CC12 1U
R47 33
R61
75 OHM
CC22
0.1U
D10
1N6263
2 1
C4
470PF
CC20
1U
CC15
0.1U
CC46 1U
RR96 0
C11
470PF
Y1
27M
RR27 33
L5 2.4UH
R31 33
TP19
CEI
TP4
FLAG3
RN3 10x4
1 8
2 7
3 6
4 5
R34 0 OHM
R48 0
R43
0
R10
4.7K
TP20
XSPDON
CC55
4700P
TP5
RFO
TP15
SSPINDLE
R32 OPEN
CC8 4.7U
R45 OPEN
CC58
4700P
RR10 0
TP1
FLAG0
R54 33
CC25
47P
RR3 3.3K
RR24 5.1K
R17 0
L3 2.4UH
TP38
XS
C9
470PF
RR17 10K
R19 100K
D8
1N6263
2 1
R50 0 OHM
RN2 10x4
1 8
2 7
3 6
4 5
U10
AAT3521 SOT-23(5pin)
1
2
3
4
5
RESET
GND
NC
EN
VCC
R1
OPEN
FB4
3.3UH
RR14 R
R53
1K
U11
AAT3520 SOT-23(3pin)
1
2
3
GND
RESET
VCC
CC24
0.1U U2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
VPP
DU/WP
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1 A0
E
GND
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A_1
GND
BYTE
A16
C3
470PF
RR1 4.7K
TP9
DIP
CC59
C
CC30
560P
R26 33
C6
470PF
R40 33
CC17
6800P
RR87 0
CC19
C
R35 OPEN
RR6 3.3K
R5
4.7K
TP2
FLAG1
CC5
0.1U
R2
OPEN
CC37
33P
TP36
XS
TP21
FGIN
C1
470PF
RR4 3.3K
CC1
1000P
D11
1N6263
2 1
TP6
TESTAD
RR8 68K
D3
1N6263
2 1
R37
OPEN\0
C7 0.1U
R3
OPEN
R44 33
CC23
560P
D2
1N6263
2 1
FB2
FERB
D4
1N6263
2 1
R36
OPEN\0
RR18 5.1K
RR16 1.2K
R51 0
R60 4.7K
C12
470PF
CC33
560P
CC28
0.015U
CC13
0.1U
R62
75 OHM
TP12
SFOCUS L1 2.4UH
R63
75 OHM
R11
75 OHM
TP16
MIRR
J2
HDR6-100
1
2
3
4
5
6
CC21
0.047U
CC2
1000P
R4
OPEN
TP17
TEI TP18
FEI
C5
470PF
RR21 6.8K
CC16
CL4 2.4UH
CC3
1000P
TP14
SSLEGN
R69 33
CC18
C
RR12 R
R59 390
C10
470PF
RR2 4.7K
R55 33
U1
ES66x8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VD33
XIN
XOUT
DCLK
DMA0
DMA1
DMA2
DMA3
VS33
VD33
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
DMA10
VS33
VD33
DMA11
DCAS
DCS0
DCS1
DRAS0
DBANK0/ DRAS1
VSS
VDD
DBANK1/ DRAS2
DCKE/DOE/TDMTSC
DWE
DB0
DB1
DB2
VS33
VD33
DB3
DB4
DB5
DB6
DB7
DB15
DB14
VS33
VD33
DB13
DB12
DB11
DB10
DB9
DB8
DSCK
VS33
VD33
DQM
LA21
LA20
LA19
LA18
LA17
LA16
VS33
VD33
LA15
LA14
LA13
LA12
LA11
LA10
LA9
VSS
VDD
LA8
LA7
LA6
LA5
LA4
LA3
VS33
VD33
LA2
LA1
LA0
LCS0
LCS1
LCS2
VSS
VDD
LCS3
LWRLL
LOE
LD0
LD1
LD2
LD3
VS33
VD33
LD4
LD5
LD6
LD7
RSD/TDMDR
RBCK/TDMCLK
RWS/TDMFS
VD33_PLL
VS33_PL
YUV1/VREF
YUV3/COMP
YUV4/RSET
YUV7/FDAC
YUV6/VDAC
VD33_DA
VS33_DA
YUV5/YDAC
YUV2/CDAC
YUV0/UDAC
TWS/SEL_PLL2
TSD0/SEL_PLL0
TSD1/SEL_PLL1
VS33
TSD2
TSD3
MCLK
TBCK
SPDIF/SEL_PLL3
SPDIFIN
VD33
VS33
XSWBLCLK
XSWBL
XSLG
XSIP2
XSIP1
XSFLAG[0]
XSFLAG[1]
XSFLAG[2]
XSFLAG[3]
VSS
VDD
XSTEXI
XSTESTAD
XSSBAD
XSFEI
AVSS_AD
XSCEI
XSTEI
XSRFRP
AVDD3_AD
XSVREF[21]
XSVREF[09]
XSVREF[15]
XSIREF
AVDD3_DS
XSIPIN
XSRFIN
XSRFIP
XSDSSLV
AVSS_DS
AVSS_PL
XSPDOFTR1
XSFDO
XSFTROPI
AVDD3_PL
XSPLLFTR1
XSPLLFTR2
XSVREF0
XSAWRC
AVSS_DA
XSRFRPCTR
XSTRAY
AVDD3_DA
XSSPINDLE
XSFOCUS
XSSLEGP
XSSLEGN
XSTRACK
XSTESTDA
XSFGIN
XSPHOI
SXCSJ
XSDATA
XSCLK
XSDFCT
XSLDC
XSSPDON
VD33
VS33
XGPIO[9]
XGPIO[8]
XGPIO[7]
XGPIO[6]
XGPIO[5]
XGPIO[4]
EAUX03
EAUX02
EAUX01
EAUX00
VSS
VDD
AUX0
AUX1
AUX2/ HSYNC
AUX3/ VSYNC
AUX4
AUX5
AUX6
AUX7
RESET
VS33
CC4
1000P
CC61
C
R23 33
TP37
XS
RR5 3.3K
CC27
0.1U
CC35
33P
RN4
10x4
18 27 36 45
C13
27PF
U3
24C01A
1
2
3
4 5
6
7
8
S0
S1
S2
GND SDA
SCL
WC
VCC
C2
470PF
D12
1N6263
2 1
CC36
33P
R33 33
RR9 20K
R56 33
U5
4Mx16 SDRAM (9ns)
1
2
4
6
5
7
3
8
10
12
11
13
9
15
16
17
18
19
35
22
23
24
25
26
14
28
29
30
31
32
33
34
36
37
38
39
40
43
42
44
46
45
47
49
48
50
52
51
53
41
20
21
27
54
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
DQML
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
VSS
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
DQMH
NC
VCCQ
DQ8
DQ9
VSSQ
DQ10
DQ11
VCCQ
DQ12
DQ13
VSSQ
DQ14
DQ15
VSS
BA0
BA1
VCC
VSS
TP11
STRACK
RR15 33K
R7
4.7K
RR28 33
R46 33
R9
4.7K
C8 0.1U
R8
4.7K
R57 33
RR26 6.8K
RR29 33
U4
27C040/080-90
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
13
14
15
17
18
19
20
21
2
22
24
31
30
1
32
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
A16
CE
OE
A18
A17
A19
VCC
GND
D9
1N6263
2 1
TP13
SSLEGP
CC26
0.1U
RN1 10x4
1 8
2 7
3 6
4 5
FB1
FERB
JJ1
RS232 CONNECTOR 2.54MM
1
2
3
4
5
TP3
FLAG2
R58 33
R65 33
RR25 6.8K
JP1
1
2
3
RR7 10K
C14
27PF
R18 OPEN
R64 33
TP8
RFRP
C15
1000PF
TP10
DIN
TP7
DA
VESTEL-4250H-A1
A1
ES6603 & Motor Drivers
VESTEL
C
3 5Wednesday, March 03, 2004
Title
SizeDocument Number Rev
Date: Sheet of
TRACK+
TRACK1
SLED+
FOCUS1
SLED-
CON2
FOCUS-1
LOAD+/DCMO+
TRACK-1
STBY
CON1
FOCUS+
FOCUS-
RF50V
SBA
SVREF15
SCLK
CDMDI
SCSJ
PVC
CE
RF50V
FE
SDATA
DVDMDI
TE
D
C
A
RF50V
CDLD
DVDLD
DVDLDO
RFGND
RF50V
RF50V
LINK
SVREF21
SCLK
SCSJ
SVREF15
SDATA
SBA
MEVO
OP2IN+
OP2OUT
OP2IN-
DCLOAD+
LOAD-/DCMO-
DCLOAD-
LOAD-/DCMO-
RFGND
DCLOAD-
DCLOAD+
HOMESW
SLED+
SLED-
SLED+
SLED-
LOAD+/DCMO+
LOAD-/DCMO-
SPINDLE1
OPEN
CLOSE-1
RFOUT
B
F
E
TRACK-
LOAD+/DCMO+
TRACK-DCLOAD-
DCLOAD+
SVREF15
OPEN
FOCUS-
CLOSE-1
OP2OUT
A
C
TRACK-
TRACK+
RFOUT
PVC
D
DVDLDO
CDMDI
FOCUS+
DVDMDI
E
FOCUS-
B
CDLDO
F
CDLDO
SVREF15
LINK
MEVO
SLEGN(2)
TRACK (2)
FOCUS(2)
SDATA (2)
DIN (2)
MIRR (2)
SCSJ (2)
SLDC (2)
SCLK (2)
SDEFCT (2)
DIP (2)
RFO (2)
TEI (2)
FEI (2)
CEI (2)
SBAD (2)
MOCTL (2)
SPINDLE (2)
SVREF15(2)
CLOSE (2)
OPEN (2)
INSW (2)
OUTSW (2)
HOMESW (2)
SPDON(2)
SVREF21(2)
DRVSB(2)
SVREF21(2)
ATR_OP (2)
BEFR_OP (2)
RF33V
RF50V
RF50V
RF50V
S12V
RFGND
RFGND
RFGND
RFGND
RFGND
RFGND
MGND
MGND
MGND
MGND
MGND
MGND
MGND
MGND
MGND
MVCC
MVCC
MVCC
MVCC
RFGND
RFGND
MVCC
MVCC
MVCC
MGND
MVCC
MVCC
MGND
RFGND
RF50V
RFGND
RR76
4.7K
RR11 56K
LL10FB (0805)
RR56 1K
RR35 100
CC40
0.1U
RR74
22K
RR102 0
RR73 1M
TP24
DEFCT
UU3
BA5954FP/AM5868(OPEN)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
29
30
VINFC
CFCERR1
CFCERR2
VINSL+
VINSL-
VOSL
VNFFC
VCC
PVCC1
PGND
VOSL-
VOSL+
VOFC-
VOFC+
STBY
BIAS
VINTK
CTKERR1
CTKERR2
VINLD
PREGND
PVCC2
VNFTK
PGND
VOLD-
VOLD+
VOTK-
VOTK+
GND
GND
DD1 IN4148
1
RR52
33
CC85
C
CC6
0.1U RR75
R
RR47 33K
RR37 3.3K
CC84
C
LL13FB (0805)
+
-
UU4B
TL3472
5
67
84
TP23
MNTR RR108 0
RR58 0
RR109 0(OPEN)
CC45
0.01U
RR107 0(OPEN)
DD5 OPEN
1
RR41 0
RR85
R
RR83 10K
RR59 0
CC67
0.01U
CC82
C
RR80
R
LL6 FB
1 2
CC53
2200P
CC68
100U/16V
RR51 33K
CC75
0.1U
RR81 0
CC69
100U/16V
CC43
470P
RR67 1(0805)RR66 1(0805)
RR78
OPEN
CC44
0.1U
RR46 10
CC60
0.1U
CC42
0.1U
RR97 R
CC54
0.047U
CC48
820P
CC65
160P
RR88 1K
DD3 IN4148
1
RR101 OPEN
+
-
UU4A
TL3472
3
21
8 4
TP33
SCLK
RR34 12K(1%)
TP32
SCSJ
CC50
0.1U
DD2
OPEN
1
RR60 0
CC51
2200P
CC56
2200P
CC39
0.1U
RR43 1K
RR98 R
QQ1
2SB11321
3 2
RR113 OPEN
CC34 33P
RR105 0
RR68 1(0805)
RR112 OPEN
RR36 100
RR89 1K
CC70
100P
RR79
1.5K
RR114 0
RR106 0(OPEN) CC77
0.1U
RR115 OPEN
TP30
SBAD
UU5
BA6287F ROHM
1
2
3
4 5
6
7
8
OUT1
VM
VCC
FIN RIN
VREF
OUT2
GND
CC73
4700P
RR55 3.3K
RR72 R
RR70
10K
CC9
100U/16V CC29
0.47U
JJ2
2.0MM
1
2
1
2
CC64
1000P
TP31
SDATA
RR71
1.5K
RR54 47K
RR53
12K
CC72
100P
RR40 R
CC41
470P
QQ2
2SB11321
32
CC66
33000P
RR49 47K
CC71
1000P
RR104 OPEN
RR45 10
CC57
120P
+
CC78
100U/10V
CC38
0.1U
RR48 22K
RR103 0
UU2
ES6603
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DVDFRP
DVDRFN
A2
B2
C2
D2
CP
CN
D
C
B
A
CD_D
CD_C
CD_B
CD_A
CD_F
CD_E
VPB
VC
DVDLD
CDLD
DVDPD
CDPD
VNB
LDON
MIRR
MP
MB
MLPF
MIN
MEVO
RFDC
RFSIN
ATOP
ATON
AIN
AIP
VPA
RFAC
BYP
DIN
DIP
FNP
FNN
VNA
MEV
RX
SDEN
SDATA
SCLK
V33
LCP
LCN
MNTR
CE
FE
TE
PI
V25
V125
TPH
DFT
LINK
CC62
0.1U
RR84 470K
CC80
0.1U
CC81
0.1U
DD4 OPEN
1
RR77
10K
TP34
SVREF09
CC52
2200P
TP35
SVREF15
RR39 3.3K
RR116 0
CC10
0
RR69 1(0805)
TP25
LINK
RR50 5.1K
RR82
22K
CC63
0.22U
CN1
HOP-1200 PUH (JP24-0.5MM)
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25 2627 28
TR-
TR+
FO-
FO+
PD(MONITOR)
VCC
VR
GND
LD(DVD)
LD(CD)
VR
GND(NC)
PD
GND
RFOUT
C
B
A
D
F
E
VCC
VS(VCC)
GND
GND GNDGND GND
J12
2.0MM
1
2
3
4
5
6
7
8
9
10
11
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
3.3V REGUALTOR
EZ1085
No need to install
EZ1085 circuitry if
J12 provide +3.3V
ES66x8
ADJ
(100UF)
24C01
OUT
SDRAM
ESS CONFIDENTIAL
The information has been checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies. Circuit diagrams are provided as a means of illustrating typical applications; consequently complete information for construction purposes is not necessarily given. ESS reserves the right to make changes at any time in order to improve the design.
INP
FRONT
(EZ1085)
2-CHANNEL AUDIO OUT
WOLFSON 2-CHANNEL AUDIODAC
WOLFSON 6-CHANNEL AUDIODAC
6-CHANNEL AUDIO OUT
TYP 2.5V ( 2.3V -- 2.7V )
VESTEL-4250H-A1
A1
MISC
VESTEL
C
4 5Wednesday, March 03, 2004
Title
SizeDocument Number Rev
Date: Sheet of
U2
EAUX40 EAUX42
EAUX43
MCLK
TBCK
TWS
U2
U1
U2
U1
TSD1
TSD0
U1
U1
TSD2
EAUX41
TBCK(2) TWS(2) MCLK(2)
TSD0(2)
AOUT0R- (5)
AOUT0L+ (5)
AOUT0R+ (5)
AOUT0L- (5)
EAUX41(2) EAUX40(2)
EAUX42(2)
EAUX43(2)
MCLK(2) TWS(2) TBCK(2)
EAUX42(2)
EAUX40(2) EAUX41(2)
EAUX43(2) TSD0(2) AOUT0L- (5)
AOUT0R- (5)
TWS(2)
TSD1(2) TSD0(2)
TBCK(2) TSD2(2)
MCLK(2)
EAUX43(2) EAUX42(2)
EAUX40(2) EAUX41(2)
AOUT0R- (5)
AOUT1L- (5)
AOUT1R- (5)
AOUT0L- (5)
AOUT2R- (5)
AOUT2L- (5)
AOUT2L- (5)
AOUT0L- (5)
AOUT2R- (5)
AOUT1L- (5)
AOUT1R- (5)
AOUT0R- (5)
GND
GND
GND
GND
VCC
GND
GND
VCC33
GND
VCC
VCC33
VCC VCC33
GNDA
+12VVCC33
GND
VCCA
-12V+5V
VCC
GNDAGND
+3.3VVCCA
VCC20
RF50V +5V
GNDAGNDA GNDA
+3.3V
GNDA GNDA
GNDA
GNDA
VCCA
GND
MGND GND GND
GND
GNDA
GND GND GND
S12V
VCC33VCC33V
VCC33RF33V
VCC33PLL33V
VCC20
VCC33
GND
MVCC
RFGNDRFGND
RFGND
GND
GNDGNDV
RFGND
VCCA
GNDA
GNDA
VCCA
GNDA
VCCA
GNDA GNDA GNDA
U38
CS4392
7
6
5
12
8
19
201
2
14
15
18
17
16
3
4
9
10
13
11
M3
MCLK
LRCK
CMOUT
M2
AUTA-
AMUTECRST
VL
AOUTB-
AOUTB+
AUTA+
VA
GND
SDATA
SCLK
M1
M0
BMUTEC
FILT+
LL1
FERB
2
B37
0.1UF
LL8 OPEN
2
C256
0.1UF
B55
10UF
B29
0.1UF
C23
OPEN
(10UF)
LL5
FERB
2
CC126
0.1
B51
10UF
JS3
2.54MM
1
2
3
4
5
6
7
8
R71 33
CC125
0.1
B43
0.1UF
B4
220UF
D23
IN4148
1
B28
0.1UF
B61
0.1UF
U31
CS4360
7
6
5
12
8
19
20
1
2
14 15
18
17
16
3
4
9
10
13
11
26
25
24
23
22
21
28
27
MCLK
LRCK
SCLK
DIF0
VD
AOUTB3
AOUTA3
VLS
SDIN1
VLC M2
MUTEC3
VQ
FILT+
SDIN2
SDIN3
GND
RST
M1
DIF1
AOUTB1
MUTC2
AOUTA2
AOUTB2
VA
GND
MUTC1
AOUTA1
B60
0.1UF
B15
0.1UF
B22
0.1UF
B36
0.1UF
U9
AMS1117
32
1
4INOUT
ADJ
OUT
B20
0.1UF
+
CC7
100/10
LL12FERB
2
B41
0.1UF
B16
0.1UF
B30
0.1UF
B40
10UF
R67
412(1%)
LL2
FERB
2
U30
CS4340
8
7
12
4
6
9
10
11
1
2
3
5
16
13
15
14
DEM0
DIF0
AOUTR
LRCK
DIF1
FILT+
VQ
REF-GND
RST
SDATA
SCLK/DEM1
MCLK
MUTEC
VSS
AOUTL
VCCA
CC129
0.1
B45
0.1UF
LL14FERB
2
LL15
FERB
2
R66
250(1%)
C272
0.1UF
B21
0.1UF
B17
0.1UF
D24
IN4148
1
B23
0.1UF
C258
10UF C259
10UF
R39
OPEN
1%
(681 OHM)
B62
10UF
LL7 OPEN
2
B24
0.1UF
B18
0.1UF B2
OPEN
B1
220UF
CC11
0.1
C273
0.1UF
CC127
0.1
B19
0.1UF
CC128
0.1
B35
0.1UF
B50
0.1UF
C16
0.1UF(OPEN)
T3
TP
B3
220UF
B38
0.1UF
Q2 OPEN
3 2
1
IN OUT
ADJ
T2
TP
B34
0.1UF
T1
TP
B25
0.1UF
U32
PCM1606
7
6
5
12
8
19
201
2
14
15
18
17
16
3
4
9
10
13
11
AGND
ZEROA
FMT2
VOUT3
VOUT5
BCK
SCKIDATA1
DATA2
VCOM
VCC
LRCK
DEMP1
DEMP0
DATA3
FMT1
VOUT6
VOUT1
VOUT4
VOUT2
B33
10UF
C260
10UF
T4
TP
B31
10UF
B32
10UF
+
CC130
100U
C274
0.1UF
LL3 OPEN
2
LL11FERB
2
R38
OPEN
1%
(412 OHM)
LL9 OPEN
2
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
VESTEL-4250H-A1
A1
OUTPUT
VESTEL
C
5 5Wednesday, March 03, 2004
Title
SizeDocument Number Rev
Date: Sheet of
QUIET0
QUIET0
CHROMA-OUT
CVBS-OUT
LUMA-OUT
FR
B-OUT
CVBS-OUT
FL
CVBS-OUT LUMA-OUT
R-OUT
G-OUT
CHROMA-OUT
G-OUT
R-OUT
QUIET0
FR
FR
LS
FL
RS
CC
SUB
FL
B-OUT
CC
RS
QUIET0
QUIET0
QUIET0
Rs_OUT
LS
SUB
QUIET0
LFE_OUT
Ls_OUT
C_OUT
SPDIF(2)
AOUT0R+(4)
AOUT0L-(4)
AOUT0L+(4)
AOUT0R-(4)
NN(2)
SCART-ON (2)
SCART-ON(2)
UDAC(2)
FDAC(2)
YDAC(2)VDAC(2)
CDAC(2)
AOUT1L-(4)
AOUT1R+(4)
AOUT2R-(4)
AOUT1R-(4)
AOUT2L-(4)
AOUT2R+(4)
AOUT1L+(4)
AOUT2L+(4)
+12V
-12V
+12V
-12V
-12V
+12V
GNDV
+12V
-12V
VCC
GND
VCC
GND
+5VA
+5VA
+5VA
+5VA
+12V
+12V
GND
GND GND
GND
GND
GND
VCCV
GNDVGNDV GNDVGNDV
VCCV
GNDVGNDV
VCCV
GNDVGNDV
VCCV
GND
+5VA
GND
GNDV
VCCV
GNDV
+12V
-12V
-12V
+12V
+12V
+12V
-12V
-12V
C285
10UF
C211
680PF
R424
75
1
D25
IN4148
1
R337
680
C291
3300PF
R170 1K
1
C300
100uF/25
1
Q33
8550
2
1 3
C170
10UF
R412
10K
1
R171
1K
1
P1
6
5
4
3
2 1
6
5
4
3
2 1
C281
10UF
R167
2.2K
1
R433
1K8
1
R164
470
1
R418680
1
C228
0.1UF
C217
22PF
R15 680
1
R400
10K
1
R437
1K8
1
Q37
BC848B
2
1 3
R197
680
1
C290
680PF
C176
10UF
R21
680
1
R27
680
1
R172 1M
1
R160
100K
1
R29
10 OHM
1
R436
75
1
C292
10UF
C180 680PF
R419
10K
1
C263
10UF
Q36
BC848B
2
1 3
R148
10 OHM
1
R162
470
1
R13
10K
1
R432
75
1
C227
220uF/25
1
C169
10UF
Q20
2SC3327
2
1 3
C286
680PF
V+
V-
U24-1
OPA2134UA
3
21
84
C173
0.1UF
C214
10UF
R414
10K
1
R22
10K
1
C172
680PF
R423
1K8
1
R407
10K
1
R401
10K
1
Q27
2N3904
2
1 3
C282
680PF
R16 10K
1
C236
0.1UF
C277
680PF
R156
10 OHM
1
Q25
8550
2
13
C289
10UF
R151
100K
1
R421
2K2
1
C218
22PF
R163
470
1
R429
2K2
1
R176
470
1
R187
68 OHM
1
P2
MOFT3C2
1
2
3
VIN
VCC
GND
R410
680
1
C262
10UF
C189
open
C298
100uF/25
1
R161
100K
1
R12
10K
1
C184
680PF
C191
0.1UF
R178
330 OHM
1
Q23
2SC3327
2
1 3
R399
680
1
C223
22PF
R425
1K8
1
R402
10K
1
R397
680
1
R152
470
1
R406
10K 1
C288
10UF
V+
V-
U25-1
OPA2134UA
3
21
84
L21
47UH
P3
RCA CONN 6
1
2
5
6
9
7
8
3
4
R438
2K2
1
C221
10UF
R415
680
1
R441
75
1
C275
680PF
C284
10UF
Q24
2SC3327
2
1 3
Q30
8550
2
1 3
R428
75
1
C232
0.1UF
C188
680PF
Q38
BC848B
2
1 3
U27E
7404
11 10
R405
100K
1
C235
open
P9
RCA CONN
1
2
3
4
C226
470uF
1
C215
10UF
R154
10K
1
R416
10K
1
R434
75
1
R149
100K
1
C276
3300PF
C178
680PF
R409
10K
1
R427
75
1
R404
10K
1
C224
22PF
R175
10K
1
C230
0.1UF
R150
100K
1
R398
10K
1
C216
22PF
R157
10 OHM
1
R173
OPEN
1
Q13
2SC3327
2
1 3
C280
0.1UF
12
C177
open
Q35
2N3904
2
1 3
D6
IN4148
1
C297
100uF/25
1
R430
2K2
1
R174
100K
1
R338 10K
Q31
2N3904
2
1 3
V+
V-
U23-1
OPA2134UA
3
21
84
Q34
2N3904
2
1 3
U27D
7404
9 8
U27F
7404
13 12
C225
22PF
C174
0.1UF
R186
680
1
C193
0.1UF
C295
3300PF
V+
V-
U25-2
OPA2134UA
5
67
84
Q22
2SC3327
2
1 3
R159
100K
1
C299
100uF/25
1
R153
470
1
Q32
8550
2
1 3
D7
IN4148
1
R25
680
1
R30
10 OHM
1
R445
75
1
R431
1K8
1
Q26
8550
2
13
R166
10M
1
C294
680PF
R420
10K
1
C181
open
R408
10K 1
C190
open
Q40
BC848B
2
1 3
R165
6.8K
1
R179
91 OHM
1
R158
10 OHM
1
Q39
BC848B
2
1 3
C287
3300PF
R155
470
1
R339
10K
C128
0.1UF
U27A
7404
1 2
R435
75
1
R426
75
1
C213
10UF
R24
10K
1
R20
10K
1
C261
10UF
C283
3300PF
C279
10UF
R14
10K
1
C278
3300PF R444
75
1
U27C
7404
5 6
J1
CON24
1
2
3
4
5
6
7
8
9
10
11
R28
10K
1
V+
V-
U24-2
OPA2134UA
5
67
84
R417
10K
1
C301
100uF/25
1
R413
1.2K
1
C219
10UF
R195
10K
1
U27B
7404
3 4
Q21
2SC3327
2
1 3
C293
10UF
D5
IN4148
1
R353
10K
R422
2K2
1
R411
820
1
C175
10UF
V+
V-
U23-2
OPA2134UA
5
67
84
C296
10UF
R403
330 1
C185
open
C220
10UF
R331
10K
FB3 FB
2
R196
11K
1

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