DW1000 USER MANUAL DWM1000
User Manual:
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- List of Figures
- List of Tables
- 1 Introduction
- 2 Overview of the DW1000
- 2.1 Introduction
- 2.2 Interfacing to the DW1000
- 2.3 DW1000 Operational States
- 2.4 Power On Reset (POR)
- 2.5 Default Configuration on Power Up
- 3 Message Transmission
- 4 Message Reception
- 5 Media Access Control (MAC) hardware features
- 6 Other features of the DW1000
- 7 The DW1000 register set
- 7.1 Register map overview
- 7.2 Detailed register description
- 7.2.1 Terminology
- 7.2.2 Register file: 0x00 – Device Identifier
- 7.2.3 Register file: 0x01 – Extended Unique Identifier
- 7.2.4 Register file: 0x02 – Reserved
- 7.2.5 Register file: 0x03 – PAN Identifier and Short Address
- 7.2.6 Register file: 0x04 – System Configuration
- 7.2.7 Register file: 0x05 – Reserved
- 7.2.8 Register file: 0x06 – System Time Counter
- 7.2.9 Register file: 0x07 – Reserved
- 7.2.10 Register file: 0x08 – Transmit Frame Control
- 7.2.11 Register file: 0x09 – Transmit Data Buffer
- 7.2.12 Register file: 0x0A – Delayed Send or Receive Time
- 7.2.13 Register file: 0x0B – Reserved
- 7.2.14 Register file: 0x0C – Receive Frame Wait Timeout Period
- 7.2.15 Register file: 0x0D – System Control Register
- 7.2.16 Register file: 0x0E – System Event Mask Register
- 7.2.17 Register file: 0x0F – System Event Status Register
- 7.2.18 Register file: 0x10 – RX Frame Information Register
- 7.2.19 Register file: 0x11 – RX Frame Buffer
- 7.2.20 Register file: 0x12 – Rx Frame Quality Information
- 7.2.21 Register file: 0x13 – Receiver Time Tracking Interval
- 7.2.22 Register file: 0x14 – Receiver Time Tracking Offset
- 7.2.23 Register file: 0x15 – Receive Time Stamp
- 7.2.24 Register file: 0x16 – Reserved
- 7.2.25 Register file: 0x17 – Transmit Time Stamp
- 7.2.26 Register file: 0x18 – Transmitter Antenna Delay
- 7.2.27 Register file: 0x19 – Reserved
- 7.2.28 Register file: 0x1A – Acknowledgement time and response time
- 7.2.29 Register files: 0x1B and 0x1C – Reserved
- 7.2.30 Register file: 0x1D – SNIFF Mode
- 7.2.31 Register file: 0x1E – Transmit Power Control
- 7.2.32 Register file: 0x1F – Channel Control
- 7.2.33 Register file: 0x20 – Reserved
- 7.2.34 Register file: 0x21 – User defined SFD sequence
- 7.2.35 Register file: 0x22 – Reserved
- 7.2.36 Register file: 0x23 –AGC configuration and control
- 7.2.36.1 Sub-Register 0x23:00 – AGC_RES1
- 7.2.36.2 Sub-Register 0x23:02 – AGC_CTRL1
- 7.2.36.3 Sub-Register 0x23:04 – AGC_TUNE1
- 7.2.36.4 Sub-Register 0x23:06 – AGC_RES2
- 7.2.36.5 Sub-Register 0x23:0C – AGC_TUNE2
- 7.2.36.6 Sub-Register 0x23:10 – AGC_RES3
- 7.2.36.7 Sub-Register 0x23:12 – AGC_TUNE3
- 7.2.36.8 Sub-Register 0x23:14 – AGC_RES4
- 7.2.36.9 Sub-Register 0x23:1E – AGC_STAT1
- 7.2.37 Register file: 0x24 – External Synchronisation Control
- 7.2.38 Register file: 0x25 – Accumulator CIR memory
- 7.2.39 Register file: 0x26 – GPIO control and status
- 7.2.39.1 Sub-Register 0x26:00 – GPIO_MODE
- 7.2.39.2 Sub-Register 0x26:04 – Reserved
- 7.2.39.3 Sub-Register 0x26:08 – GPIO_DIR
- 7.2.39.4 Sub-Register 0x26:0C – GPIO_DOUT
- 7.2.39.5 Sub-Register 0x26:10 – GPIO_IRQE
- 7.2.39.6 Sub-Register 0x26:14 – GPIO_ISEN
- 7.2.39.7 Sub-Register 0x26:18 – GPIO_IMODE
- 7.2.39.8 Sub-Register 0x26:1C – GPIO_IBES
- 7.2.39.9 Sub-Register 0x26:20 – GPIO_ICLR
- 7.2.39.10 Sub-Register 0x26:24 – GPIO_IDBE
- 7.2.39.11 Sub-Register 0x26:28 – GPIO_RAW
- 7.2.40 Register file: 0x27 – Digital receiver configuration
- 7.2.40.1 Sub-Register 0x27:00 – DRX_RES1
- 7.2.40.2 Sub-Register 0x27:02 – DRX_TUNE0b
- 7.2.40.3 Sub-Register 0x27:04 – DRX_TUNE1a
- 7.2.40.4 Sub-Register 0x27:06 – DRX_TUNE1b
- 7.2.40.5 Sub-Register 0x27:08 – DRX_TUNE2
- 7.2.40.6 Sub-Register 0x27:0C – DRX_RES2
- 7.2.40.7 Sub-Register 0x27:20 – DRX_SFDTOC
- 7.2.40.8 Sub-Register 0x27:22 – DRX_RES3
- 7.2.40.9 Sub-Register 0x27:24 – DRX_PRETOC
- 7.2.40.10 Sub-Register 0x27:26 – DRX_TUNE4H
- 7.2.40.11 Sub-Register 0x27:28 – DRX_CAR_INT
- 7.2.40.12 Sub-Register 0x27:2C – RXPACC_NOSAT
- 7.2.41 Register file: 0x28 – Analog RF configuration block
- 7.2.41.1 Sub-Register 0x28:00 – RF_CONF
- 7.2.41.2 Sub-Register 0x28:00 – RF_CONF
- 7.2.41.3 Sub-Register Manual TX Power Control – RF_RES1
- 7.2.41.4 Sub-Register 0x28:0B– RF_RXCTRLH
- 7.2.41.5 Sub-Register 0x28:0C– RF_TXCTRL
- 7.2.41.6 Sub-Register 0x28:10 – RF_RES2
- 7.2.41.7 Sub-Register 0x28:2C – RF_STATUS
- 7.2.41.8 Sub-Register 0x28:30 – LDOTUNE
- 7.2.42 Register file: 0x29 – Reserved
- 7.2.43 Register file: 0x2A – Transmitter Calibration block
- 7.2.44 Register file: 0x2B – Frequency synthesiser control block
- 7.2.45 Register file: 0x2C – Always-on system control interface
- 7.2.45.1 Sub-Register 0x2C:00 – AON_WCFG
- 7.2.45.2 Sub-Register 0x2C:02 – AON_CTRL
- 7.2.45.3 Sub-Register 0x2C:03 – AON_RDAT
- 7.2.45.4 Reading from a specified address within AON memory
- 7.2.45.5 Sub-Register 0x2C:04 – AON_ADDR
- 7.2.45.6 Sub-Register 0x2C:05 – AON_RES1
- 7.2.45.7 Sub-Register 0x2C:06 – AON_CFG0
- 7.2.45.8 Sub-Register 0x2C:0A – AON_CFG1
- 7.2.46 Register file: 0x2D – OTP Memory Interface
- 7.2.46.1 Sub-Register 0x2D:00 – OTP_WDAT
- 7.2.46.2 Sub-Register 0x2D:04 – OTP_ADDR
- 7.2.46.3 Sub-Register 0x2D:06 – OTP_CTRL
- 7.2.46.4 Sub-Register 0x2D:08 – OTP_STAT
- 7.2.46.5 Sub-Register 0x2D:0A – OTP_RDAT
- 7.2.46.6 Sub-Register 0x2D:0E – OTP_SRDAT
- 7.2.46.7 Sub-Register 0x2D:12 – OTP_SF
- 7.2.46.8 Receiver operating parameter sets
- 7.2.47 Register file: 0x2E – Leading Edge Detection Interface
- 7.2.47.1 Sub-Register 0x2E:0000 – LDE_THRESH
- 7.2.47.2 Sub-Register 0x2E:0806 – LDE_CFG1
- 7.2.47.3 Sub-Register 0x2E:1000 – LDE_PPINDX
- 7.2.47.4 Sub-Register 0x2E:1002 – LDE_PPAMPL
- 7.2.47.5 Sub-Register 0x2E:1804 – LDE_RXANTD
- 7.2.47.6 Sub-Register 0x2E:1806– LDE_CFG2
- 7.2.47.7 Sub-Register 0x2E:2804 – LDE_REPC
- 7.2.48 Register file: 0x2F – Digital Diagnostics Interface
- 7.2.48.1 Sub-Register 0x2F:00 – Event Counter Control
- 7.2.48.2 Sub-Register 0x2F:04 – PHR Error Counter
- 7.2.48.3 Sub-Register 0x2F:06 – RSD Error Counter
- 7.2.48.4 Sub-Register 0x2F:08 – FCS Good Counter
- 7.2.48.5 Sub-Register 0x2F:0A – FCS Error Counter
- 7.2.48.6 Sub-Register 0x2F:0C – Frame Filter Rejection Counter
- 7.2.48.7 Sub-Register 0x2F:0E – RX Overrun Error Counter
- 7.2.48.8 Sub-Register 0x2F:10 – SFD Timeout Error Counter
- 7.2.48.9 Sub-Register 0x2F:12 – Preamble Detection Timeout Event Counter
- 7.2.48.10 Sub-Register 0x2F:14 – RX Frame Wait Timeout Event Counter
- 7.2.48.11 Sub-Register 0x2F:16 – TX Frame Sent Counter
- 7.2.48.12 Sub-Register 0x2F:18 – Half Period Warning Counter
- 7.2.48.13 Sub-Register 0x2F:1A – Transmitter Power-Up Warning Counter
- 7.2.48.14 Sub-Register 0x2F:1C – EVC_RES1
- 7.2.48.15 Sub-Register 0x2F:24 – Digital Diagnostics Test Mode Control
- 7.2.49 Register files: 0x30 to 0x35 – Reserved
- 7.2.50 Register file: 0x36 – Power Management and System Control
- 7.2.51 Register files: 0x37 to 0x3F – Reserved
- 8 DW1000 Calibration
- 9 Operational design choices when employing the DW1000
- 10 APPENDIX 1: The IEEE 802.15.4 UWB physical layer
- 11 APPENDIX 2: The IEEE 802.15.4 MAC layer
- 12 APPENDIX 3: Two-Way Ranging
- 13 APPENDIX 4: Abbreviations and acronyms
- 14 APPENDIX 5: References
- [1] IEEE 802.15.4-2011 or “IEEE Std 802.15.4™‐2011” (Revision of IEEE Std 802.15.4-2006). IEEE Standard for Local and metropolitan area networks – Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs). IEEE Computer Society Sponsored by the...
- 15 Document History
- 16 Change Log
- 17 FURTHER INFORMATION