Intel® Atom™ C3XXX Product Family Firmware Support Package (Intel® FSP) Integration Guide Denverton NSFsp

• Intel® Atom® C3XXX Product Family Intel® Firmware Support Package (Intel® FSP)
  • 1 Introduction
    • 1.1 Purpose
    • 1.2 Intended Audience
    • 1.3 Related Documents
    • 1.4 Acronyms and Terminology
  • 2 Intel® FSP Overview
    • 2.1 Technical Overview
    • 2.2 Intel® FSP Distribution Package
      • 2.2.1 Package Layout
  • 3 Intel® FSP Integration
    • 3.1 Assumptions Used in this Document
    • 3.2 Boot Flow
    • 3.3 FSP Component Extraction
    • 3.4 Intel® FSP Information Header
    • 3.5 FSP Image ID and Revision
    • 3.6 Intel® FSP APIs
      • 3.6.1 TempRamInit API
      • 3.6.2 FspMemoryInit API
      • 3.6.3 TempRamExit API
      • 3.6.4 FspSiliconInit API
      • 3.6.5 NotifyPhase API
        • 3.6.5.1 PostPciBusEnumeration Notification
        • 3.6.5.2 ReadyToBoot Notification
        • 3.6.5.3 EndOfFirmware Notification
  • 4 Intel® FSP Output
    • 4.1 SMRAM Resource Descriptor HOB
    • 4.2 FIA MUX HOB
    • 4.3 SMBIOS INFO HOB
    • 4.4 MarginCheckerTestReport HOB
  • 5 Intel® FSP Configuration Firmware File
    • 5.1 UPD Data Structure
      • 5.1.1 FSP Configuration Data
        • 5.1.1.1 FSP-T UPD Structure
        • 5.1.1.2 Detailed Description
      • 5.1.2 FSP-T UPD Data Region
        • 5.1.2.1 FSP-M UPD Data Region
        • 5.1.2.2 FSP-S UPD Data Region
  • A Memory Down
  • B FIA MUX Configuration Structure
  • C EMMC* DLL Configuration Structure