ES7243 User Guide ä¿®æfl¹ NewLisax
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ES7243 ES7243 User Guide ES7243 User Guide (Rev.1.00) Rev.1.00 1 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide OVERVIEW ES7243 is a high performance stereo audio ADC, and it supports LRCK frequency range from 8 kHz to 192 kHz. It has two differential inputs, AINLP-AINLN and AINRP-AINRN, followed by a stereo microphone amplifier with programmable gain. Also, it has TDM mode to cascade multiple ES7243 devices. Its TDM cascading mode makes it easy to connect with DSP. ES7243 is easy to use, utilizing the differential inputs and the internal PGA to interface with microphone and boost the microphone signal level. One ES7243 can interface with two microphones. It also can be interfaced with line input if the internal PGA gain is +1dB. ES7243 supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and some common non standard audio clocks (25 MHz, 26 MHz, etc). According to the serial audio data sampling frequency (Fs), the device can work in three speed modes: single speed mode, double speed mode and Quad Speed mode. In single speed mode, Fs normally range from 8 kHz to 48 kHz, and in double speed mode, Fs normally ranges from 64 kHz to 96 kHz. In quad speed mode, Fs normally range from 96 kHz to 192 kHz. ES7243 can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. ES7243 is very suitable for music and voice application, such as Microphone Array, Conference system, Sound bar, Audio Interface, DVR, NVR, etc. Its input circuit and TDM mode makes it ideal for microphone array application. FEATURES 1. 2. 3. 4. 5. 6. Supports I2S, Left Justified and DSP-A/B digital format, supports Master or Slave mode. Supports 256 or 384 LRCK ratio. Also, it supports non standard LRCK ratio without obvious performance degraded. Has one stereo differential line input or microphone input, followed by a stereo PGA with gain range from +1dB to +27dB. Has I2C controls port to read/write internal register. Has TDM mode to cascade multiple ES7243 for microphone array application or conference system. Has standby capability to save power consumption. ADC PERFORMANCE 1. 2. 3. 4. -88dB THD+N 103dB SNR @ +1dB PGA gain, 92dB SNR @ +27dB PGA gain 24-bit, 8 to 200 kHz sampling frequency Stereo differential line inputs or microphone inputs PACKAGE OUTLINE 1. ES7241 QFN-20, 3mm × 3mm Rev.1.00 2 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 1 2 3 4 5 6 BLOCK DIAGRAM................................................................................................................................................................................................................................................ 4 RECOMMENDED OPERATING CONDITION ......................................................................................................................................................................................................... 4 APPLICATION CIRCUIT AND PCB LAYOUT GUIDE ............................................................................................................................................................................................... 4 3.1 ES7243 APPLICATION CIRCUIT ........................................................................................................................................................................................................... 4 3.2 PCB LAYOUT GUIDE ............................................................................................................................................................................................................................ 5 3.2.1 THE POWER SUPPLY, GROUNDING DECOUPLING AND FILTERS ................................................................................................................................................. 5 3.2.2 THE THERMAL PAD OF ES7243 ................................................................................................................................................................................................... 5 3.3 MICROPHONE CIRCUIT ...................................................................................................................................................................................................................... 6 3.4 LINE INPUT ......................................................................................................................................................................................................................................... 6 3.5 THE CIRCUIT SCHEMATIC FOR I2S ...................................................................................................................................................................................................... 6 3.6 THE CIRCUIT SCHEMATIC OF I2C ........................................................................................................................................................................................................ 7 3.7 TDMIN PIN ......................................................................................................................................................................................................................................... 7 ES7243 APPLICATION ......................................................................................................................................................................................................................................... 7 4.1 REGISTER MAP ................................................................................................................................................................................................................................... 8 4.2 I2C CONTROL PORT ............................................................................................................................................................................................................................ 8 4.3 SOFTWARE MODE .............................................................................................................................................................................................................................. 9 4.4 MASTER OR SLAVE MODE .................................................................................................................................................................................................................. 9 4.5 SPEED MODE...................................................................................................................................................................................................................................... 9 4.6 INTERNAL CLOCK DIAGRAM ............................................................................................................................................................................................................... 9 4.7 SERIAL DIGITAL AUDIO FORMAT ...................................................................................................................................................................................................... 11 4.8 TDM MODE ...................................................................................................................................................................................................................................... 12 4.8.1 APPLICATION CIRCUIT OF TDM MODE ..................................................................................................................................................................................... 12 4.8.2 DIAGRAM AND TIMING OF TDM CASCADING MODE .............................................................................................................................................................. 13 4.8.3 PHASE DIFFERENCE BETWEEN MULTIPLE ADCs ....................................................................................................................................................................... 14 4.9 ANALOG INPUT ................................................................................................................................................................................................................................ 15 4.10 POWER CONTROL ............................................................................................................................................................................................................................ 16 4.11 SOFT RESET ...................................................................................................................................................................................................................................... 16 4.12 MUTE AND AUTO MUTE .................................................................................................................................................................................................................. 17 EFFECT OF ANTI-ALIASING FILTER .................................................................................................................................................................................................................... 17 REGISTER CONFIGURATION FOR ES7243 ......................................................................................................................................................................................................... 18 6.1 THE SEQUENCE FOR STARTUP-SLAVE MODE................................................................................................................................................................................... 18 6.2 THE SEQUENCE FOR STARTUP- MASTER MODE .............................................................................................................................................................................. 18 6.3 THE SEQUENCE FOR CASCADING MODE (SLAVE MODE) ................................................................................................................................................................. 18 6.4 THE SEQUENCE FOR STANDBY MODE ............................................................................................................................................................................................. 18 Rev.1.00 3 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 1 BLOCK DIAGRAM ES7243 Block Diagram SIGNAL PATH ES7243 has stereo differential inputs, AINLP-AINLN and AINRP-AINRN, followed by a stereo PGA with gain range from +1dB to +27dB. Then, the internal high performance multi-bit delta-sigma audio ADC does analog to digital converting. At last digital signal should be outputted on ASDOUT pin. The maximum input level of these line inputs is 1Vrms. 2 RECOMMENDED OPERATING CONDITION The following Table shows the recommended operating condition of ES7243. 3 APPLICATION CIRCUIT AND PCB LAYOUT GUIDE This section provides some guideline about circuit schematic and PCB layout. 3.1 ES7243 APPLICATION CIRCUIT Below circuit schematic shows the details about microphone interface, I2C, ground and power supply. AU_GND VCC_MICA 1 1 R542 10K R543 10K Rev.1.00 2 2 R544 10K 1 AU_GND AU_GND 1 J408 2 10V C555 1uF 2 AU_GND C552 1 1uF C554 1uF 1 C549 1uF AU_GND 2 C551 1uF R537 2k 1 220R 2 MICBIAS2k 1 2 2 AU_GND R536 R535 2 2 C548 1uF 1 1 1 1 1 2 2 C550 1uF 1 19 18 17 8 C547 1uF 2 2 2 C557 20pF 20 7 6 3 C546 100nF 2 2 R545 22R 2 R546 22R C556 20pF 4 VCC_MICA VCC_MICA 2 2 1 AU_GND C553 1uF 2 P N J409 MICROPHONE P N MICROPHONE AU_GND 1 1 1 1 1 I2C_SCL I2C_SDA 2 AU_GND 2 2 2 1 I2S0_MCLK I2S0_LRCK_TX I2S0_SCLK I2S0_SDI2 1 R538 22R 1 R539 22R 1 R540 22R R541 22R 1 5 U504 ES7243 QFN20_3R00X3R00X0R85_T 12 VDDP VDDA VDDD 21 PAD 13 GNDD GNDA 16 1 AINRP 15 MCLK AINRN LRCK 9 1 SCLK AINLP 10 SDOUT AINLN 14 CCLK REFP 11 CDATA REFQ AD0 2 AD1 TDMIN I2C Chip ID = 0x20 2 C545 100nF 2 1 VCC_MICA I2C_AD0 I2C_AD1 R547 1 10K 1 R548 10K AU_GND 2 2 AU_GND SY S_GND AU_GND 4 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 3.2 PCB LAYOUT GUIDE As with any high-resolution audio converter, designing with ES7243 requires careful attention to PCB layout if its potential performance is to be realized. 3.2.1 THE POWER SUPPLY, GROUNDING DECOUPLING AND FILTERS The power supply of ES7243 must be isolate from system power supply. A LDO specified for ES7243 is recommended in order to get the best audio performance. Usually, GNDD and GNDA must be connect to the same analog ground plane, and then join into system ground at a single point nearby the power supply. It is important to prevent high frequency noise or high current noise from going into audio ground plane. Below diagram illustrates ES7243 power supply and grounding. VSYS LDO AUD_GND SYS_GND AUD_GND C1 0.1uF AUD_GND C2 0.1uF AUD_GND DVDD PVDD VIO AVDD PVDD C5 J1 AINLx CPU ES724X I2C 1uF AINRx LINE IN JACK 1uF I2S DGND 2 3 C6 I2C I2S 1 AUD_GND AGND REFP SYS_GND REFQ C3 1uF C4 1uF AUD_GND AUD_GND AUD_GND AUD_GND There need some decoupling and filter capacitors on VDDD, VDDA, REFP and REFQ pins. These decoupling and filter capacitors must be as near to ES7243 package as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from REFP and REFQ in order to avoid unwanted coupling to ADC modulators. The filter capacitors on REFP and REFQ pins, especially 0.1uF capacitor, must be positioned to minimize the electronic path from these reference pins to GND. 3.2.2 THE THERMAL PAD OF ES7243 There is a thermal pad on the bottom of ES7243 package. The following drawing shows this thermal pad. In practical system, the thermal pad must be connected to ground plane by via.The following picture illustrates how the thermal pad is connected to ground plane. Rev.1.00 5 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 3.3 MICROPHONE CIRCUIT ES7243 has two differential inputs, AINLP-AINLN and AINRP-AINRN, which can be used as microphone interface. Usually, AINLP and AINLN is a differential route. AINRP and AINRN is another differential route. It is important note here that the analog input capacitors, such as C550, C551, C552 and C553, must be near to the microphone. 1 2 2 AU_GND AU_GND J408 2 C553 1uF P 2 N J409 MICROPHONE P 1 AU_GND 2 N MICROPHONE AU_GND 1 R544 10K 1 2 10V C555 1uF 2 AU_GND C552 1 1uF C554 1uF 2 AU_GND 2 C551 1uF 1 AU_GND R537 2k C549 1uF 2 2 C550 1uF 220R 2 C548 1uF 2 C547 1uF R536 MICBIAS2k 1 2 1 R535 1 1 1 1 C546 100nF 2 19 18 17 8 VCC_MICA 1 20 7 6 3 VCC_MICA 1 4 U504 ES7243 QFN20_3R00X3R00X0R85_T 12 VDDP VDDA VDDD 21 PAD 13 GNDD GNDA 16 1 AINRP 15 MCLK AINRN LRCK 9 1 SCLK AINLP 10 SDOUT AINLN 14 CCLK REFP 11 CDATA REFQ AD0 2 AD1 TDMIN I2C Chip ID = 0x20 2 1 5 AU_GND ES7243 doesn’t have microphone bias voltage, so an external microphone bias circuit is used to supply for microphones. Usually, an R-C filter, for example 220Ω and 1uF, is used to generate microphone bias voltage from ES7243 power supply. Below picture shows how to generate MICBIAS voltage from ES7243 power supply. VCC_MICA R535 1 2 1 1 MICBIAS C549 1uF 2 220R 2 C548 1uF AU_GND AU_GND 3.4 LINE INPUT If the internal PGA gain is 1dB, the differential inputs of ES7243 can also be used as line inputs. Following circuit schematic illustrates the line input of ES7243. It is important note here that the analog input capacitors, such as C563, C565, C564 and C566, must be near to the line input jack. J410 1 1 2 C565 1uF 1 1 2 2 BNC AU_GND 10V AU_GND J411 2 C564 1uF 1 2 1 C567 1uF 2 AU_GND AU_GND 2 BNC C566 1uF AU_GND 1 R558 10K 1 C568 1uF 2 2 19 18 17 8 C560 1uF 1 20 7 6 3 C559 100nF 1 4 2 C563 1uF VCC_MICA 2 1 5 U505 ES7243 QFN20_3R00X3R00X0R85_T 12 VDDP VDDA VDDD 21 PAD 13 GNDD GNDA 16 AINRP 15 MCLK AINRN LRCK 9 SCLK AINLP 10 SDOUT AINLN 14 CCLK REFP 11 CDATA REFQ AD0 2 AD1 TDMIN I2C Chip ID = 0x20 1 AU_GND 3.5 THE CIRCUIT SCHEMATIC FOR I2S If the length of I2S clock is larger than 10cm, please use 30pF capacitors between I2S clock route and ground. For example, Rev.1.00 6 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 3.6 THE CIRCUIT SCHEMATIC OF I2C ES7243 has I2C control port to read / write internal register. Below schematic shows the circuit of I2C port. The R-C low pass filter is generally recommended for I2C bus to avoid high frequency noise. The I2C route must be shielded by ground. Pin17 (AD0) and Pin8 (AD1) are used to select the I2C chip address of ES7243. Following Table shows the definition of I2C chip address. ES7243 I2C Chip Address The Level of AD[1:0] pin 0x20 (8bit) / 0x10 (7bit) 0x22 (8bit) / 0x11(7bit) 0x24 (8bit) / 0x12 (7bit) 0x26(8bit) / 0x13(7bit) AD1 =1, AD0 = 1 AD1 = 1, AD0 = 0 AD1 =0, AD0 = 1 AD1 = 0, AD0 = 0 1 5 4 20 7 6 3 2 R556 22R 2 R557 22R C569 20pF C570 20pF 2 2 1 1 1 1 I2C_SCL I2C_SDA 19 18 17 8 U505 ES7243 QFN20_3R00X3R00X0R85_T 12 VDDP VDDA VDDD 21 PAD 13 GNDD GNDA 16 AINRP 15 MCLK AINRN LRCK 9 SCLK AINLP 10 SDOUT AINLN 14 CCLK REFP 11 CDATA REFQ AD0 2 AD1 TDMIN I2C Chip ID = 0x20 AU_GND VCC_MICA 1 1 R559 10K R561 10K 2 2 I2C_AD0 I2C_AD1 R560 1 10K 1 2 2 R562 10K AU_GND 3.7 TDMIN PIN ES7243 has TDM mode to cascade multiple ES7243 devices. The TDMIN pin of ES7243 device must be pulled down to GND by 10kΩ resister whether TDM mode enabled or not. 4 ES7243 APPLICATION ES7243 operates in software mode, and it communicates with host device by I2C port. In ES7243, some internal registers are used for power control, PGA gain control, serial digital audio format selection, master or slave mode selection, TDM mode enable/disable and LRCK ratio selection, etc. Multiple ES7243 can be cascaded for microphone array application. This TDM cascading mode is very useful in speech recognition, speech localization and conference system. It is important note here that the TDMIN pin must be pulled down to GND by 10KΩ resister even if TDM mode is disabled. Rev.1.00 7 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 4.1 REGISTER MAP Register Addr B7 B6 B5 ///////////////// B4 B3 B2 B1 B0 default MS_MODE WORK_MODE 0x00 Reg.00 0x00 Reg.01 0x01 Reg.02 0x02 Reg.03 0x03 Reg.04 0x04 Reg.05 0x05 Reg.06 0x06 Reg.07 0x07 Reg.08 0x08 ///////////////// Reg.09 0x09 ANA_PDN Reg.10 0x0A CHIPINI_CON 0xC0 Reg.11 0x0B POWERUP_CON 0xC0 Reg.12 0x0C Reg.13 0x0D Reg.14 0x0E MCLK_DIV / TDM_ENA SP_BCLKINV ADC_HPF_DIS SPEED_MODE SP_LRP SP_WL 0x00 SP_PROTOCAL 0x10 LRCKDIV ///////////////// ///////////////// / / ///////////////// ///////////////// / / ///////////////// ///////////////// / / SP_TRI MCLK_DIS VMIDSEL ////////////////// ////////////////// AUTOMUTE_DETED ADC_MUTE_SIZE ADC_SDP_MUTE SEQ_DIS RST_DIG RST_ADCDIG PDN_ADCVREFGEN MODTOP_RST PDN_MODL VMIDLOW ///////////////// / / ADC_NOISETHD ADC_LP_VCMMOD PDN_MODR PDN_PGAL GAIN_SW[1:0] ADC_LP_PGA ADCBIAS_SWH ADC_LP_INT1 SRATIO_DIV ADC_CSM ADC_AUTOMUTE ADC_OSR 0x13 0x00 FORCE_CSM INPUT_SEL2 ADC_LP_VRP 0x02 CLK_ADC_DIV GAIN_SW[4:2] ///////////////// 0x04 BCLKDIV PDN_PGAR 0x3F INPUT_SEL 0x11 ADC_LP_FLASH 0x80 0x12 0xA0 0x40 CHIP_ID 4.2 I2C CONTROL PORT ES7243 supports standard I2C interface with maximum 400kbps rate. External host device can completely configure this device through writing to internal registers. The transfer rate of I2C can be up to 400kbps. The following drawing illustrates the timing of I2C. ES7243 has two chip address pins, AD1 and AD0, to set I2C chip address. The following table shows the chip address definition, State of AD[1:0] pins Rev.1.00 Chip Address 8 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 00 0x13(7bit) / 0x26 (8bit) 01 0x12(7bit) / 0x24 (8bit) 10 0x11(7bit) / 0x22 (8bit) 11 0x10(7bit) / 0x20 (8bit) 4.3 SOFTWARE MODE ES7243 operates in software mode. WORK_MODE (bit0 of register 0x00) must be set to 1 to enable software mode. WORK_MODE = 0 ES7243 In Hardware Mode WORK_MODE = 1 ES7243 In Software Mode 4.4 MASTER OR SLAVE MODE ES7243 can operate in master mode or slave mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. In slave mode, ES7243 detects MCLK/LRCK ratio automatically. In master mode, ES7243 generates LRCK and SCLK from MCLK according to the setting of LRCKDIV and BCLKDIV. MS_MODE (Bit1 of register 0x00) is used to select master or slave mode. MS_MODE = 0 ES7243 In Slave Mode MS _MODE = 1 ES7243 In Master Mode 4.5 SPEED MODE ES7243 supports three speed modes: single speed mode, double speed mode and quad speed mode. In single speed mode, LRCK frequency normally ranges from 8kHz to 48kHz; In double speed mode, LRCK frequency normally ranges from 64kHz to 96kHz; In quad speed mode, LRCK frequency normally ranges from 96kHz to 192kHz. In slave mode, ES7243 detects speed mode automatically. In master mode, Bit[3:2] of register 0x00 is used to select proper speed mode. 4.6 INTERNAL CLOCK DIAGRAM The following diagram illustrates internal clock diagram in master mode. It is important note here that ES7243 can detect LRCK ratio automatically in slave mode MCLK MCLK_DIV Reg0x00.bit[6:5] Internal MCLK LRCKDIV MS_MODE =1 Reg0x00.bit1 Reg0x02 MS_MODE =1 BCLK DIV Reg0x03.bit[5:0] CLK_ADC_DIV Reg0x04.bit[3:0] Rev.1.00 LRCK SCLK Reg0x00.bit1 Internal ADC clock 9 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide Following is the register definition for internal clock management. B7 Reg0x00 B6 ////////////////// B5 MCLK_DIV B4 B3 ADC_HPF_DIS Reg0x02 B2 SPEED_MODE B1 B0 default MS_MODE WORK_MODE 0x00 LRCKDIV Reg0x03 ////////////////// ////////////////// Reg0x04 ////////////////// ////////////////// Reg0x0D 0x10 BCLKDIV ////////////////// ADC_CSM ////////////////// 0x04 CLK_ADC_DIV 0x02 ADC_OSR 0xA0 1. MCLK_DIV DEFINITION MCLK_DIV = 00 Internal MCLK = MCLK /1 MCLK_DIV = 01 Internal MCLK = MCLK /2 MCLK_DIV = 10 Internal MCLK = MCLK /3 MCLK_DIV = 11 Internal MCLK = MCLK /4 2. LRCKDIV DEFINITION 3. BCLKDIV DEFINITION Rev.1.00 10 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 4.7 SERIAL DIGITAL AUDIO FORMAT ES7243 supports I2S, Left Justified, DSP-A and DSP-B serial digital audio format with resolution from 16bits to 32bits. Only DSP-A or DSP-B format is supported in TDM cascading mode. The following is the register definition of serial digital audio format, Reg0x01 B7 B6 B5 TDM_ENA SP_BCLKINV SP_LRP B4 B3 B2 SP_WL B1 B0 default SP_PROTOCAL LRC polarity For I2S/Left Justify: 0 – L/R normal 1. Enable TDMIN for Cascading mode 0. Disable TDMIN SP_BCLKINV = 0, normal mode, SP_BCLKINV=1, BCLK Inverted polarity 1 – L/R invert The data format of serial data port 000 – 24-bit 001 – 20-bit polarity 010 – 18-bit For DSP mode case: 011 – 16-bit 0 – Mode A, 100 – 32-bit The protocol of serial data port 00 – I2S 0x00 01 – LJ 10 – not allowed 11 – DSP 1 – Mode B, The following diagram illustrates the timing of serial digital audio format. Rev.1.00 11 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 4.8 TDM MODE ES7243 supports TDM mode to cascade multiple ES7243 devices. In TDM mode, up to 4 ES7243 devices can be cascaded, and up to 8 channels ADC data will be presented in one LRCK cycle. No Phase difference exists between these ADC data. Its TDM mode makes it ideal for microphone array application. Two critical issues must be considered in microphone array application. One is the number of microphone. Another is the phase difference between ADC data .Usually more than one microphone will be used to form a microphone array. Ideally, all ADCs in microphone array do analog-to-digital conversion at the same time, so that there isn’t phase difference between ADC data. If this microphone array consists of two microphones, there only needs one ES7243 device. If the array is made by more than two microphones, there should need two or more ES7243 devices, and these ES7243 devices should be cascaded. In TDM mode, the serial digital audio format must be DSP-A or DSP-B. CPU will get incorrect data if I2S or Left justified format is used in TDM mode. TDM_ENA (Bit7 of Register 0x01) is used to enable or disable TDM mode. TDM_ENA = 0 TDM Mode Disable TDM_ENA = 1 TDM Mode Enable It is important note here that the TDMIN pin of ES7243 must be pulled down to ground by 10kΩ even if TDM mode is disabled. 4.8.1 APPLICATION CIRCUIT OF TDM MODE Below schematic shows four ES7243 devices cascaded in TDM mode. Rev.1.00 12 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 2 20 7 6 3 15% R0402 15% R0402 1 C621 20pF X5R 50V C0402 2 1 22R 2 22R 2 2 2 R596 10K 5% R0402 2 R604 R605 R595 1 10K 1 5% R0402 I2C1_SCL I2C1_SDA 19 18 17 8 C622 20pF X5R 50V C0402 1 2 2 1 1 2 C614 1uF X5R 10V C0603 N J413 MICROPHONE P N 1 2 2 C583 1uF X5R 10V C0603 1 C588 1uF X5R C0402 2 2 2 1 1 1 C594 1uF X5R 10V C0603 R582 2k R0402 5% R583 2k R0402 5% 2 C595 1 1uF X5R 10V C0402 2 C600 1 1uF X5R C0402 10V 1 2 J416 MICROPHONE P NJ417 P N MICROPHONE R591 2k R0402 5% R592 2k R0402 5% 2 C605 1uF X5R 10V C0603 1 2 2 2 R599 220R 5% R0402 R576 2k R0402 5% J414 1 P 2 N J415 MICROPHONE 1 P 2 N MICROPHONE 1 1 C604 1uF X5R 10V C0603 2 R580 220R 5% R0402 2 1 1 2 C613 1uF X5R 10V C0603 J412 P R575 2k R0402 5% 1 1 2 R574 220R 5% R0402 1 1 2 2 1 2 2 C608 1uF X5R 10V C0603 1 2 2 1 2 1 1uF 2 X5R C0402 10V 1uF 2 X5R C0402 10V C603 1uF X5R 10V C0603 VCC_MICA 1 2 C590 10V 1uF 2 X5R 1 C0402 10V VCC_MICA R565 2k R0402 5% MICROPHONE C592 1uF X5R 10V C0603 SDO4 2 10V C579 1uF X5R C0402 10V 2 C602 1uF X5R 10V C0603 1 2 1 2 C581 1uF X5R 10V C0603 2 1 1 2 2 1 2 C607 100nF X5R 10V C0402 2 R563 220R 5% R0402 R564 2k R0402 C575 5% 1uF X5R 10V C0603 1 4 R0402 U509 ES7243 QFN20_3R00X3R00X0R85_T5% 12 VDDP VDDA VDDD 21 PAD 13 GNDD GNDA C609 16 1 AINRP 15 MCLK AINRN C611 LRCK 9 1 SCLK AINLP 10 SDOUT AINLN 14 CCLK REFP 11 CDATA REFQ AD0 2 1 AD1 TDMIN R597 I2C Chip ID = 0x26 10K R0402 5% C591 1uF X5R 10V C0603 2R598 22R R0402 5% 1 1 1 5 SDO4 R590 10K 1 2 VCC_MICA C606 100nF X5R 10V C0402 C580 1uF X5R 10V C0603 1 C620 20pF X5R 50V C0402 1 19 18 17 8 1 1 C619 20pF X5R 50V C0402 2 2 2 R589 10K 5% R0402 15% R0402 15% R0402 1 R588 1 10K 1 5% R0402 22R 2 22R 2 2 VCC_MICA R602 R603 1uF 2 X5R C0402 10V 1uF 2 X5R C0402 10V 2 20 7 6 3 1 1 2 4 C597 100nF X5R 10V C0402 2 1 5 C596 100nF X5R 10V C0402 U508 ES7243 QFN20_3R00X3R00X0R85_T 12 VDDP VDDA VDDD 21 PAD 13 GNDD GNDA C599 16 1 AINRP 15 MCLK AINRN C601 LRCK 9 1 SCLK AINLP 10 SDOUT AINLN 14 CCLK REFP 11 CDATA REFQ AD0 2 AD1 TDMIN I2C Chip ID = 0x24 1C574 1uF X5R 10V C0603 2R584 SDO3 VCC_MICA 22R 1C593 R0402 5% 1uF VCC_MICA X5R C598 10V 1uF C0603 X5R 10V C0603 1 VCC_MICA SDO3 1 2 C618 20pF X5R 50V C0402 2 1 C617 20pF X5R 50V C0402 19 18 17 8 1 15% R0402 15% R0402 1 22R 2 22R 2 R600 R601 2 R0402 2 R0402 2 VCC_MICA R578 10K 5% 1 R579 1 10K 5% 2 SDO2 VCC_MICA C578 1uF X5R C0402 2 20 7 6 3 1 4 2 1 5 VCC_MICA C573 1uF X5R 10V C0603 2 SDO2 VCC_MICA R573 22R 1C582 5% R0402 1uF VCC_MICA X5R C585 C586 10V 100nF 1uF C0603 X5R X5R 10V 10V C0402 C0603 U507 ES7243 QFN20_3R00X3R00X0R85_T 12 VDDP VDDA VDDD 21 PAD 13 GNDD GNDA C587 1uF 16 1 2 X5R AINRP 15 C0402 10V MCLK AINRN C589 1uF LRCK 9 1 2X5R SCLK AINLP 10 10V C0402 SDOUT AINLN 14 CCLK REFP 11 CDATA REFQ AD0 2 AD1 TDMIN I2C Chip ID = 0x22 R581 10K R0402 1 5% 1 VCC_MICA C584 100nF X5R 10V C0402 2 C616 20pF X5R 50V C0402 2 C615 20pF X5R 50V C0402 19 18 17 8 1 15% R0402 15% R0402 2 22R 2 22R 2 1 R570 R586 10K 5% R0402R587 2 2 R571 10K R0402 5% 1 20 7 6 3 R0402 R0402 R0402 R0402 2 2 2 2 2 2 1 1 1 1 1 1 1 2 VCC_MICA 5% 5% 5% 5% 4 1 22R 22R 22R 22R 1 R566 R567 R568 R569 2 I2S0_MCLK I2S0_LRCK_TX I2S0_SCLK I2S0_SDO 1 5 C571 100nF X5R 10V C0402 1 180R-100M L0603 1.5A 25% U506 ES7243 QFN20_3R00X3R00X0R85_T 12 C572 VDDP VDDA 100nF VDDD 21 X5R PAD 13 10V GNDD GNDA C576 1uF C0402 16 1 2 X5R AINRP 15 C0402 10V MCLK AINRN C577 1uF LRCK 9 1 2X5R SCLK AINLP 10 10V C0402 SDOUT AINLN 14 CCLK REFP 11 CDATA REFQ AD0 2 AD1 TDMIN I2C Chip ID = 0x20 R572 10K R0402 1 5% 2 VCC_MICA 2 2 1 VCC_MICA FB402 1 2 VDD_ADC 2 C610 1 1uF X5R 10V C0402 2 C612 1 1uF X5R C0402 10V 1 2 1 2 J418 MICROPHONE P NJ419 P N MICROPHONE 4.8.2 DIAGRAM AND TIMING OF TDM CASCADING MODE Below diagram illustrates the TDM cascading mode of ES7243. CPU / SOC I2C/PCM CLK I2S/PCM DATA IN ASDOUT TDMIN ES7243 1# ASDOUT TDMIN ASDOUT TDMIN ASDOUT TDMIN ES7243 2# ES7243 3# ES7243 4# GND I2C Bus MIC1 MIC2 MIC3 MIC4 MIC5 MIC6 MIC7 MIC8 The following drawing shows the timing of TDM cascading mode. Rev.1.00 13 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide LRCK SCLK 4# SDOUT L4R4 3# SDOUT L3R3 L4R4 2# SDOUT L2R2 L3R3 L4R4 1# SDOUT L1R1 L2R2 L3R3 L4R4 4.8.3 PHASE DIFFERENCE BETWEEN MULTIPLE ADCs In TDM mode, there isn’t phase difference existing between the data of multiple ES7243 devices. Please use audio software, for example Cooledit, to analysis the phase difference of multiple ADC data. Following picture shows the analysis result of Cooledit. It shows that no phase difference exists between 8 channels TDM cascading data. Rev.1.00 14 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 4.9 ANALOG INPUT Below diagram shows the analog input path of ES7243. AINLP AINLN 4:1 D2SEL PGAL Reg0x08 Bit[0] Left ADC Reg0x08 Bit[6:4] Bit[2:1] AINRP AINRN D2SER 4:1 Right ADC PGAR In ES7243, there is a stereo differential analog input, AINLP-AINLN and AINRP-AINRN, followed by a stereo PGA with gain range from +1dB to +27dB. INPUT_SEL (bit0 of register 0x08) is used to enable or disable these differential inputs. If INPUT_SEL = 1’b, the differential inputs is enabled. In register 0x08, Bit[6:4] and Bit[2:1] are used to set the PGA gain. Below table shows the definition of PGA gain. Rev.1.00 Bit6 Bit5 Bit4 Bit2 Bit1 Gain (dB) 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 +1 +3.5 +18 +20.5 +22.5 +24.5 +25 +27 15 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide 4.10 POWER CONTROL In ES7243, some registers are used for power control. The following shows the power control register definition. 4.11 SOFT RESET In ES7243, some internal registers can be used for soft reset. If the reset bit is set to 1, the device will be in standby mode Rev.1.00 16 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide and has minimum power consumption. The following table shows the soft reset register definition. 4.12 MUTE AND AUTO MUTE ES7243 has mute control which can mute ADC output. When mute control is set to 1, ADC always outputs all 0 or 1. Also, ES7243 has auto mute feature. If auto mute is enabled, ES7243 detect the input level automatically. ADC will be mute if the input level is lower than the threshold within a long duration. User can decide the threshold level and duration time. 5 EFFECT OF ANTI-ALIASING FILTER Usually, the bandwidth of audio ADC is lower than FS/2, where FS is sample rate. The signal whose spectrum is higher than Rev.1.00 17 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide FS/2 is not interested by ADC. So there need a low-pass filter to restrict the bandwidth of a signal to approximately or completely satisfy the sampling theorem over the band of interest. This low-pass filter is also named by anti-aliasing filter. ES7243 has a proper anti-aliasing filter, so that the signal bandwidth is restricted to completely satisfy the sampling theorem. The out band voice doesn’t have influence on the output spectrum of ADC. So ES7243 is ideal for microphone array application. Below picture shows the output spectrum of ES7243, where LRCK is 16kHz and the signal range from 20Hz to 20kHz. Please verify the effect of anti-aliasing filter before using it in microphone array. 6 REGISTER CONFIGURATION FOR ES7243 The Register configuration includes ADC start up, ADC Standby and ADC Cascading mode, etc. 6.1 THE SEQUENCE FOR STARTUP-SLAVE MODE WriteReg(0x00, 0x01); WriteReg(0x06, 0x00); WriteReg(0x05, 0x1B); WriteReg(0x01, 0x0C); WriteReg(0x08, 0x43); WriteReg(0x05, 0x13); //slave mode, software mode //Mute ADC //i2s -16bit //enable AIN, PGA GAIN = 27DB //un Mute ADC 6.2 THE SEQUENCE FOR STARTUP- MASTER MODE WriteReg(0x00, 0x03); WriteReg(0x05, 0x1B); WriteReg(0x06 0x10); WriteReg(0x01, 0x0C); WriteReg(0x02, 0x10); WriteReg(0x03, 0x04); WriteReg(0x04, 0x02); WriteReg(0x0D, 0Xa0); WriteReg(0x08, 0x43); WriteReg(0x06 0x00); WriteReg(0x05, 0x13); //master mode, software mode, single speed mode, mclk div = 1 //Mute ADC //RESET ADC //i2s -16bit //MCLK / LRCK = 256 //MCLK / BCLK = 4 //CLK_ADC_DIV=2 //CSM in normal mode, OSR = 32 //enable AIN, PGA GAIN = 27DB //UN RESET ADC //un Mute ADC 6.3 THE SEQUENCE FOR CASCADING MODE (SLAVE MODE) WriteReg(0x00, 0x01); WriteReg(0x06, 0x00); WriteReg(0x05, 0x1B); WriteReg(0x01, 0x8F); WriteReg(0x08, 0x43); WriteReg(0x05, 0x13); //slave mode, software mode //Mute ADC //DSP-A, TDM ENABLE //enable AIN, PGA GAIN = 27DB //un Mute ADC 6.4 THE SEQUENCE FOR STANDBY MODE WriteReg(0x06, 0x05); WriteReg(0x05, 0x1B); Rev.1.00 18 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018 ES7243 ES7243 User Guide WriteReg(0x06, 0x5C); WriteReg(0x07, 0x3F); WriteReg(0x08 0x4B); WriteReg(0x09 0x9F); Rev.1.00 19 Latest datasheet: www.everest-semi.com or info@everest-semi.com September 2018
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