TMS320F2837xD Dual Core Delfino Microcontrollers Technical Reference Manual (Rev. G) F28379D

F28379D%20Technical%20Reference%20Manual

TMS320F2837xD%20Dual-Core%20Delfino%20Microcontrollers%20Technical%20Reference%20Manual%20(Rev.%20G)

TMS320_User_manual

F28379D%20Technical%20Reference%20Manual

User Manual:

Open the PDF directly: View PDF .
Page Count: 2668

Download
Open PDF In Browser	View PDF

TMS320F2837xD Dual-Core Delfino
Microcontrollers

Technical Reference Manual

Literature Number: SPRUHM8G
December 2013 – Revised September 2017

Contents
Preface....................................................................................................................................... 81
1

C28x Processor .................................................................................................................. 82
1.1

2

83
83
83
84

System Control .................................................................................................................. 85
2.1
2.2

2.3

2.4

2.5

2.6

2.7

2

Overview.....................................................................................................................
1.1.1 Floating-Point Unit ................................................................................................
1.1.2 Trigonometric Math Unit .........................................................................................
1.1.3 Viterbi, Complex Math, and CRC Unit II (VCU-II) ............................................................

Introduction .................................................................................................................. 86
System Control Functional Description .................................................................................. 86
2.2.1 Device Identification .............................................................................................. 86
2.2.2 Device Configuration Registers ................................................................................. 87
Resets ....................................................................................................................... 87
2.3.1 Reset Sources ..................................................................................................... 87
2.3.2 External Reset (XRS) ............................................................................................. 88
2.3.3 Power-On Reset (POR) .......................................................................................... 88
2.3.4 Debugger Reset (SYSRS) ....................................................................................... 88
2.3.5 Watchdog Reset (WDRS) ........................................................................................ 89
2.3.6 NMI Watchdog Reset (NMIWDRS) ............................................................................. 89
2.3.7 DCSM Safe Code Copy Reset (SCCRESET) ................................................................. 89
2.3.8 Hibernate Reset (HIBRESET) ................................................................................... 89
2.3.9 Hardware BIST Reset (HWBISTRS)............................................................................ 89
2.3.10 Test Reset (TRST) ............................................................................................... 89
Peripheral Interrupts ....................................................................................................... 89
2.4.1 Interrupt Concepts................................................................................................. 90
2.4.2 Interrupt Architecture.............................................................................................. 90
2.4.3 Interrupt Entry Sequence ......................................................................................... 91
2.4.4 Configuring and Using Interrupts ................................................................................ 92
2.4.5 PIE Channel Mapping ............................................................................................ 95
2.4.6 Vector Tables ...................................................................................................... 96
Exceptions and Non-Maskable Interrupts ............................................................................. 102
2.5.1 Configuring and Using NMIs ................................................................................... 102
2.5.2 Emulation Considerations ...................................................................................... 102
2.5.3 NMI Sources ...................................................................................................... 103
2.5.4 Illegal Instruction Trap (ITRAP) ................................................................................ 103
Safety Features ........................................................................................................... 103
2.6.1 Write Protection on Registers .................................................................................. 103
2.6.2 Missing Clock Detection Logic ................................................................................. 104
2.6.3 PLLSLIP Detection .............................................................................................. 105
2.6.4 CPU1 and CPU2 PIE Vector Address Validity Check ...................................................... 105
2.6.5 NMIWDs .......................................................................................................... 106
2.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 106
2.6.7 ECC Enabled Flash Memory ................................................................................... 106
2.6.8 ERRORSTS Pin.................................................................................................. 106
Clocking ................................................................................................................... 107
2.7.1 Clock Sources .................................................................................................... 109

Contents

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

2.8
2.9

2.10

2.11
2.12

2.13

2.14
2.15

2.7.2 Derived Clocks ...................................................................................................
2.7.3 Device Clock Domains ..........................................................................................
2.7.4 XCLKOUT.........................................................................................................
2.7.5 Clock Connectivity ...............................................................................................
2.7.6 Clock Source and PLL Setup ..................................................................................
32-Bit CPU Timers 0/1/2 .................................................................................................
Watchdog Timers .........................................................................................................
2.9.1 Servicing the Watchdog Timer .................................................................................
2.9.2 Minimum Window Check .......................................................................................
2.9.3 Watchdog Reset or Watchdog Interrupt Mode ...............................................................
2.9.4 Watchdog Operation in Low Power Modes ..................................................................
2.9.5 Emulation Considerations ......................................................................................
Low Power Modes ........................................................................................................
2.10.1 IDLE ..............................................................................................................
2.10.2 STANDBY .......................................................................................................
2.10.3 HALT .............................................................................................................
2.10.4 HIB ................................................................................................................
Memory Controller Module ..............................................................................................
2.11.1 Functional Description .........................................................................................
Flash and OTP Memory .................................................................................................
2.12.1 Features..........................................................................................................
2.12.2 Flash Tools ......................................................................................................
2.12.3 Default Flash Configuration ...................................................................................
2.12.4 Flash Bank, OTP and Pump ..................................................................................
2.12.5 Flash Module Controller (FMC) ...............................................................................
2.12.6 Flash and OTP Power-Down Modes and Wakeup .........................................................
2.12.7 Flash and OTP Performance ..................................................................................
2.12.8 Flash Read Interface ...........................................................................................
2.12.9 Erase/Program Flash ...........................................................................................
2.12.10 Error Correction Code (ECC) Protection ...................................................................
2.12.11 Reserved Locations Within Flash and OTP ...............................................................
2.12.12 Procedure to Change the Flash Control Registers .......................................................
2.12.13 Flash Pump Ownership Semaphore ........................................................................
Dual Code Security Module (DCSM) ...................................................................................
2.13.1 Functional Description .........................................................................................
2.13.2 CSM Impact on Other On-Chip Resources .................................................................
2.13.3 Incorporating Code Security in User Applications ..........................................................
JTAG .......................................................................................................................
Registers ...................................................................................................................
2.15.1 Base Addresses ................................................................................................
2.15.2 CPUTIMER_REGS Registers .................................................................................
2.15.3 PIE_CTRL_REGS Registers ..................................................................................
2.15.4 WD_REGS Registers ..........................................................................................
2.15.5 NMI_INTRUPT_REGS Registers .............................................................................
2.15.6 XINT_REGS Registers .........................................................................................
2.15.7 DMA_CLA_SRC_SEL_REGS Registers ....................................................................
2.15.8 FLASH_PUMP_SEMAPHORE_REGS Registers ..........................................................
2.15.9 DEV_CFG_REGS Registers ..................................................................................
2.15.10 CLK_CFG_REGS Registers .................................................................................
2.15.11 CPU_SYS_REGS Registers .................................................................................
2.15.12 ROM_PREFETCH_REGS Registers .......................................................................
2.15.13 DCSM_Z1_OTP Registers ...................................................................................
2.15.14 DCSM_Z2_OTP Registers ...................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Contents

111
111
112
113
114
117
119
119
120
120
121
121
122
122
122
123
123
125
125
133
133
133
134
134
134
135
137
137
139
140
144
144
144
146
146
152
153
157
159
159
160
167
219
225
238
247
254
256
323
346
386
388
395
3

www.ti.com

2.15.15
2.15.16
2.15.17
2.15.18
2.15.19
2.15.20
2.15.21
2.15.22
2.15.23
2.15.24
2.15.25

3

3.8

3.9

Introduction ................................................................................................................
Device Boot Philosophy ..................................................................................................
Device Boot Modes .......................................................................................................
Configuring Boot Mode Pins ............................................................................................
Configuring Get Boot Options ...........................................................................................
Configuring Emulation Boot Options ...................................................................................
Device Boot Flow Diagrams .............................................................................................
3.7.1 Emulation Boot Flow Diagrams ................................................................................
3.7.2 Standalone and Hibernate Boot Flow Diagrams .............................................................
Device Reset and Exception Handling .................................................................................
3.8.1 Reset Causes and Handling....................................................................................
3.8.2 Exceptions and Interrupts Handling ...........................................................................
Boot ROM Description ...................................................................................................
3.9.1 Entry Points .......................................................................................................
3.9.2 Wait Points........................................................................................................
3.9.3 Memory Maps ....................................................................................................
3.9.4 Boot Modes .......................................................................................................
3.9.5 Boot Data Stream Structure ....................................................................................
3.9.6 GPIO Assignments ..............................................................................................
3.9.7 Boot IPC ..........................................................................................................
3.9.8 Clock Initializations ..............................................................................................
3.9.9 Wait State Configuration ........................................................................................
3.9.10 Boot Status information ........................................................................................
3.9.11 ROM Version ....................................................................................................

583
583
583
584
585
586
588
589
591
593
593
594
594
594
595
595
598
611
613
615
618
619
619
621

Direct Memory Access (DMA) ............................................................................................. 623
4.1
4.2

4.3
4.4
4.5

4.6
4.7
4.8

4

402
422
442
449
497
520
537
539
548
571
573

ROM Code and Peripheral Booting ..................................................................................... 582
3.1
3.2
3.3
3.4
3.5
3.6
3.7

4

DCSM_Z1_REGS Registers .................................................................................
DCSM_Z2_REGS Registers .................................................................................
DCSM_COMMON_REGS Registers .......................................................................
MEM_CFG_REGS Registers ................................................................................
ACCESS_PROTECTION_REGS Registers ...............................................................
MEMORY_ERROR_REGS Registers ......................................................................
ROM_WAIT_STATE_REGS Registers .....................................................................
FLASH_CTRL_REGS Registers ............................................................................
FLASH_ECC_REGS Registers .............................................................................
CPU_ID_REGS Registers ...................................................................................
UID_REGS Registers .........................................................................................

Introduction ................................................................................................................
Architecture ................................................................................................................
4.2.1 Block Diagram ....................................................................................................
4.2.2 Common Peripheral Architecture ..............................................................................
4.2.3 Peripheral Interrupt Event Trigger Sources ..................................................................
4.2.4 DMA Bus ..........................................................................................................
Pipeline Timing and Throughput ........................................................................................
CPU Arbitration ...........................................................................................................
Channel Priority ...........................................................................................................
4.5.1 Round-Robin Mode ..............................................................................................
4.5.2 Channel 1 High Priority Mode ..................................................................................
Address Pointer and Transfer Control .................................................................................
Overrun Detection Feature ..............................................................................................
Register Descriptions.....................................................................................................
4.8.1 DMA Control Register (DMACTRL) — EALLOW Protected ...............................................
4.8.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected ..........................................

Contents

624
625
625
625
627
632
632
633
634
634
635
636
640
642
643
644

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

Revision Register (REVISION).................................................................................
Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected ..................................
Priority Status Register (PRIORITYSTAT) ...................................................................
Mode Register (MODE) — EALLOW Protected .............................................................
Control Register (CONTROL) — EALLOW Protected ......................................................
Burst Size Register (BURST_SIZE) — EALLOW Protected ...............................................
BURST_COUNT Register ......................................................................................
Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected ......................
Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected .................
Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected .....................................
Transfer Count Register (TRANSFER_COUNT) ..........................................................
Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected .............
Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected ........
Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected) .........
Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) ...............................
Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected .
Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected ............
4.8.20 Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR) .......................................................................
4.8.21 Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected ..........................
4.8.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) .......
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
4.8.8
4.8.9
4.8.10
4.8.11
4.8.12
4.8.13
4.8.14
4.8.15
4.8.16
4.8.17
4.8.18
4.8.19

5

657
657
658
658

Control Law Accelerator (CLA) ........................................................................................... 659
5.1
5.2

5.3

5.4

5.5

5.6

5.7

6

644
645
646
647
649
651
651
652
653
653
654
654
655
655
656
656

Control Law Accelerator (CLA) Overview .............................................................................
CLA Interface ..............................................................................................................
5.2.1 CLA Memory .....................................................................................................
5.2.2 CLA Memory Bus ................................................................................................
5.2.3 Shared Peripherals and EALLOW Protection ................................................................
5.2.4 CLA Tasks and Interrupt Vectors ..............................................................................
5.2.5 CLA Software Interrupt to CPU ................................................................................
CLA and CPU Arbitration ................................................................................................
5.3.1 CLA and CPU Arbitration .......................................................................................
5.3.2 CLA Message RAM .............................................................................................
CLA Configuration and Debug ..........................................................................................
5.4.1 Building a CLA Application .....................................................................................
5.4.2 Typical CLA Initialization Sequence ...........................................................................
5.4.3 Debugging CLA Code ...........................................................................................
5.4.4 CLA Illegal Opcode Behavior ..................................................................................
5.4.5 Resetting the CLA ...............................................................................................
Pipeline .....................................................................................................................
5.5.1 Pipeline Overview ................................................................................................
5.5.2 CLA Pipeline Alignment .........................................................................................
5.5.3 Parallel Instructions ..............................................................................................
Instruction Set .............................................................................................................
5.6.1 Instruction Descriptions .........................................................................................
5.6.2 Addressing Modes and Encoding..............................................................................
5.6.3 Instructions .......................................................................................................
Registers ...................................................................................................................
5.7.1 CLA Base Addresses............................................................................................
5.7.2 CLA_REGS Registers ...........................................................................................
5.7.3 CLA_SOFTINT_REGS Registers ..............................................................................

660
662
662
663
663
664
666
666
666
666
668
668
668
670
671
671
672
672
672
675
677
677
679
681
792
792
793
828

Inter-Processor Communication (IPC) ................................................................................. 833

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Contents

5

www.ti.com

6.1
6.2
6.3
6.4
6.5
6.6
6.7

7

7.5
7.6
7.7
7.8
7.9

8.3

9.2

1138
1139
1139
1142
1143
1145
1145
1146
1165
1178
1271

Analog Subsystem ......................................................................................................
9.1.1 Features ........................................................................................................
9.1.2 Block Diagram ..................................................................................................
9.1.3 Lock Registers ..................................................................................................
Registers .................................................................................................................
9.2.1 Analog Subsystem Base Addresses .........................................................................
9.2.2 ANALOG_SUBSYS_REGS Registers .......................................................................

1373
1373
1373
1376
1377
1377
1378

Analog-to-Digital Converter (ADC)..................................................................................... 1387
10.1

6

GPIO Input X-BAR ......................................................................................................
ePWM and GPIO Output X-BAR ......................................................................................
8.2.1 ePWM X-BAR ...................................................................................................
8.2.2 GPIO Output X-BAR ...........................................................................................
8.2.3 X-BAR Flags ....................................................................................................
X-BAR Registers ........................................................................................................
8.3.1 X-BAR Base Addresses .......................................................................................
8.3.2 INPUT_XBAR_REGS Registers .............................................................................
8.3.3 XBAR_REGS Registers .......................................................................................
8.3.4 EPWM_XBAR_REGS Registers .............................................................................
8.3.5 OUTPUT_XBAR_REGS Registers ..........................................................................

Analog Subsystem .......................................................................................................... 1372
9.1

10

GPIO Overview ........................................................................................................... 906
Configuration Overview .................................................................................................. 907
Digital General-Purpose I/O Control.................................................................................... 907
Input Qualification ......................................................................................................... 909
7.4.1 No Synchronization (Asynchronous Input) ................................................................... 909
7.4.2 Synchronization to SYSCLKOUT Only........................................................................ 909
7.4.3 Qualification Using a Sampling Window ...................................................................... 909
USB Signals ............................................................................................................... 912
SPI Signals ................................................................................................................ 912
GPIO and Peripheral Muxing ............................................................................................ 914
Internal Pullup Configuration Requirements........................................................................... 919
Registers ................................................................................................................... 921
7.9.1 GPIO Base Addresses .......................................................................................... 921
7.9.2 GPIO_CTRL_REGS Registers ................................................................................. 922
7.9.3 GPIO_DATA_REGS Registers ............................................................................... 1087

Crossbar (X-BAR)............................................................................................................ 1137
8.1
8.2

9

834
835
835
835
836
837
838
838
839
872

General-Purpose Input/Output (GPIO) ................................................................................. 905
7.1
7.2
7.3
7.4

8

Inter-Processor Communication ........................................................................................
Message RAMs ...........................................................................................................
IPC Flags and Interrupts .................................................................................................
IPC Command Registers ................................................................................................
Free-Running Counter ...................................................................................................
IPC Communication Protocol............................................................................................
Registers ...................................................................................................................
6.7.1 IPC Base Addresses ............................................................................................
6.7.2 IPC_REGS_CPU1 Registers ...................................................................................
6.7.3 IPC_REGS_CPU2 Registers ...................................................................................

Analog-to-Digital Converter (ADC) ....................................................................................
10.1.1 Features ........................................................................................................
10.1.2 ADC Block Diagram ...........................................................................................
10.1.3 ADC Configurability ...........................................................................................
10.1.4 SOC Principle of Operation ..................................................................................

Contents

1388
1388
1388
1389
1393

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

10.2
10.3

10.4

11

Buffered Digital to Analog Converter (DAC)
11.1

11.2
11.3
11.4

12

1396
1398
1401
1403
1403
1406
1407
1407
1408
1408
1413
1413
1417
1418
1418
1420
1421
1421
1422
1560

....................................................................... 1581

Buffered Digital to Analog Converter (DAC) Overview .............................................................
11.1.1 Features ........................................................................................................
11.1.2 Block Diagram .................................................................................................
Using the DAC ...........................................................................................................
Lock Registers ...........................................................................................................
Registers .................................................................................................................
11.4.1 DAC Base Addresses ........................................................................................
11.4.2 DAC_REGS Registers ........................................................................................

1582
1582
1582
1582
1583
1583
1583
1584

Comparator Subsystem (CMPSS) ...................................................................................... 1592
12.1

12.2
12.3
12.4
12.5
12.6

13

10.1.5 SOC Configuration Examples ...............................................................................
10.1.6 ADC Conversion Priority .....................................................................................
10.1.7 Burst Mode .....................................................................................................
10.1.8 EOC and Interrupt Operation ................................................................................
10.1.9 Post-Processing Blocks ......................................................................................
10.1.10 Opens/Shorts Detection Circuit (OSDETECT) ...........................................................
10.1.11 Power-Up Sequence ........................................................................................
10.1.12 ADC Calibration ..............................................................................................
ADC Timings .............................................................................................................
10.2.1 ADC Timing Diagrams ........................................................................................
Additional Information ...................................................................................................
10.3.1 Ensuring Synchronous Operation ...........................................................................
10.3.2 Choosing an Acquisition Window Duration ................................................................
10.3.3 Achieving Simultaneous Sampling ..........................................................................
10.3.4 Designing an External Reference Circuit ..................................................................
10.3.5 Internal Temperature Sensor ................................................................................
Registers .................................................................................................................
10.4.1 ADC Base Addresses ........................................................................................
10.4.2 ADC_REGS Registers ........................................................................................
10.4.3 ADC_RESULT_REGS Registers............................................................................

CMPSS Overview .......................................................................................................
12.1.1 Features ........................................................................................................
12.1.2 Block Diagram .................................................................................................
Comparator...............................................................................................................
Internal DAC .............................................................................................................
Ramp Generator .........................................................................................................
Digital Filter ..............................................................................................................
Registers .................................................................................................................
12.6.1 CMPSS Base Addresses.....................................................................................
12.6.2 CMPSS_REGS Registers ....................................................................................

1593
1593
1593
1594
1594
1595
1596
1598
1598
1599

Sigma Delta Filter Module (SDFM) ..................................................................................... 1624
13.1

13.2
13.3
13.4
13.5

13.6
13.7
13.8

SDFM Module Overview ...............................................................................................
13.1.1 SDFM Features ................................................................................................
13.1.2 Block Diagram .................................................................................................
Configuring Device Pins ................................................................................................
Input Control Unit ........................................................................................................
Comparator Unit .........................................................................................................
Data Filter Unit ...........................................................................................................
13.5.1 32-bit or 16-bit Data Filter Output Representation ........................................................
13.5.2 Data Rate and Latency of the Sinc Filter ..................................................................
Interrupt Unit .............................................................................................................
Register Descriptions ...................................................................................................
Registers .................................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Contents

1625
1625
1626
1627
1628
1629
1630
1632
1633
1634
1636
1637
7

www.ti.com

13.8.1 SDFM Base Addresses....................................................................................... 1637
13.8.2 SDFM_REGS Registers ...................................................................................... 1638

14

Enhanced Pulse Width Modulator (ePWM) ......................................................................... 1674
14.1
14.2
14.3
14.4

14.5

14.6

14.7

14.8

14.9

14.10
14.11

14.12
14.13

8

Introduction ...............................................................................................................
14.1.1 Submodule Overview .........................................................................................
Configuring Device Pins ................................................................................................
Overview..................................................................................................................
Time-Base (TB) Submodule ...........................................................................................
14.4.1 Purpose of the Time-Base Submodule .....................................................................
14.4.2 Controlling and Monitoring the Time-Base Submodule ..................................................
14.4.3 Calculating PWM Period and Frequency ..................................................................
14.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules.....................................
14.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules ....................
14.4.6 Time-Base Counter Modes and Timing Waveforms ......................................................
14.4.7 Global Load ....................................................................................................
Counter-Compare (CC) Submodule ..................................................................................
14.5.1 Purpose of the Counter-Compare Submodule ............................................................
14.5.2 Controlling and Monitoring the Counter-Compare Submodule ..........................................
14.5.3 Operational Highlights for the Counter-Compare Submodule ...........................................
14.5.4 Count Mode Timing Waveforms ............................................................................
Action-Qualifier (AQ) Submodule .....................................................................................
14.6.1 Purpose of the Action-Qualifier Submodule ...............................................................
14.6.2 Action-Qualifier Submodule Control and Status Register Definitions ..................................
14.6.3 Action-Qualifier Event Priority ...............................................................................
14.6.4 AQCTLA and AQCTLB Shadow Mode Operations .......................................................
14.6.5 Waveforms for Common Configurations ...................................................................
Dead-Band Generator (DB) Submodule .............................................................................
14.7.1 Purpose of the Dead-Band Submodule ....................................................................
14.7.2 Dead-band Submodule Additional Operating Modes .....................................................
14.7.3 Operational Highlights for the Dead-Band Submodule ...................................................
PWM Chopper (PC) Submodule .....................................................................................
14.8.1 Purpose of the PWM Chopper Submodule ................................................................
14.8.2 Operational Highlights for the PWM Chopper Submodule...............................................
14.8.3 Waveforms .....................................................................................................
Trip-Zone (TZ) Submodule .............................................................................................
14.9.1 Purpose of the Trip-Zone Submodule ......................................................................
14.9.2 Operational Highlights for the Trip-Zone Submodule .....................................................
14.9.3 Generating Trip Event Interrupts ............................................................................
Event-Trigger (ET) Submodule........................................................................................
14.10.1 Operational Overview of the ePWM Type 4 Event-Trigger Submodule ..............................
Digital Compare (DC) Submodule ....................................................................................
14.11.1 Purpose of the Digital Compare Submodule .............................................................
14.11.2 Enhanced Trip Action .......................................................................................
14.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis .........................................
14.11.4 Operation Highlights of the Digital Compare Submodule ..............................................
EPWM X-BAR ...........................................................................................................
Applications to Power Topologies ....................................................................................
14.13.1 Overview of Multiple Modules .............................................................................
14.13.2 Key Configuration Capabilities .............................................................................
14.13.3 Controlling Multiple Buck Converters With Independent Frequencies ................................
14.13.4 Controlling Multiple Buck Converters With Same Frequencies ........................................
14.13.5 Controlling Multiple Half H-Bridge (HHB) Converters ...................................................
14.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) .....................................

Contents

1675
1677
1682
1682
1684
1684
1685
1686
1690
1690
1691
1693
1695
1695
1695
1696
1698
1701
1702
1702
1705
1706
1708
1714
1715
1715
1716
1721
1721
1721
1722
1725
1725
1725
1728
1730
1731
1736
1737
1738
1738
1738
1744
1745
1745
1746
1747
1750
1751
1753

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

14.13.7 Practical Applications Using Phase Control Between PWM Modules ................................
14.13.8 Controlling a 3-Phase Interleaved DC/DC Converter ...................................................
14.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter...................................
14.13.10 Controlling a Peak Current Mode Controlled Buck Module ...........................................
14.13.11 Controlling H-Bridge LLC Resonant Converter.........................................................
14.14 Registers .................................................................................................................
14.14.1 EPWM Base Addresses ....................................................................................
14.14.2 EPWM_REGS Registers ...................................................................................
14.14.3 EPWM_XBAR_REGS Registers ...........................................................................
14.14.4 SYNC_SOC_REGS Registers .............................................................................

15

High-Resolution Pulse Width Modulator (HRPWM) .............................................................. 2001
15.1
15.2

15.3

16

Introduction ...............................................................................................................
Operational Description of HRPWM ..................................................................................
15.2.1 Controlling the HRPWM Capabilities .......................................................................
15.2.2 Configuring the HRPWM .....................................................................................
15.2.3 Configuring Hi-Res in Deadband Rising Edge and Falling Edge Delay ...............................
15.2.4 Principle of Operation .........................................................................................
15.2.5 Deadband High Resolution Operation .....................................................................
15.2.6 Scale Factor Optimizing Software (SFO) ..................................................................
15.2.7 HRPWM Examples Using Optimized Assembly Code. ..................................................
Appendix A: SFO Library Software - SFO_TI_Build_V7.lib........................................................
15.3.1 Scale Factor Optimizer Function - int SFO() ..............................................................
15.3.2 Software Usage ...............................................................................................

2002
2004
2004
2007
2008
2008
2018
2019
2019
2025
2025
2026

Enhanced Capture (eCAP) ................................................................................................ 2028
16.1
16.2
16.3
16.4
16.5

16.6

16.7
16.8

17

1755
1756
1759
1760
1761
1763
1763
1764
1900
1993

Introduction ...............................................................................................................
Description ...............................................................................................................
Configuring Device Pins for the eCAP ...............................................................................
Capture and APWM Operating Mode ................................................................................
Capture Mode Description .............................................................................................
16.5.1 Event Prescaler ................................................................................................
16.5.2 Edge Polarity Select and Qualifier ..........................................................................
16.5.3 Continuous/One-Shot Control ...............................................................................
16.5.4 32-Bit Counter and Phase Control ..........................................................................
16.5.5 CAP1-CAP4 Registers .......................................................................................
16.5.6 Using SWSYNC with the ECAP Module ...................................................................
16.5.7 Interrupt Control ...............................................................................................
16.5.8 Shadow Load and Lockout Control .........................................................................
16.5.9 APWM Mode Operation ......................................................................................
Application of the ECAP Module .....................................................................................
16.6.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger ....................................
16.6.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ......................
16.6.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger ..................................
16.6.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger ....................
Application of the APWM Mode .......................................................................................
16.7.1 Example 1 - Simple PWM Generation (Independent Channel/s) .......................................
Registers .................................................................................................................
16.8.1 eCAP Base Addresses .......................................................................................
16.8.2 ECAP_REGS Registers ......................................................................................

2029
2029
2029
2030
2031
2032
2033
2033
2034
2035
2035
2036
2038
2038
2039
2039
2042
2044
2046
2048
2048
2050
2050
2051

Enhanced QEP (eQEP) ..................................................................................................... 2068
17.1
17.2
17.3

Introduction ...............................................................................................................
Configuring Device Pins ................................................................................................
Description ...............................................................................................................
17.3.1 EQEP Inputs ...................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Contents

2069
2071
2071
2071
9

www.ti.com

17.3.2 Functional Description ........................................................................................
17.3.3 eQEP Memory Map ...........................................................................................
17.4 Quadrature Decoder Unit (QDU) ......................................................................................
17.4.1 Position Counter Input Modes ...............................................................................
17.4.2 eQEP Input Polarity Selection ...............................................................................
17.4.3 Position-Compare Sync Output .............................................................................
17.5 Position Counter and Control Unit (PCCU) ..........................................................................
17.5.1 Position Counter Operating Modes .........................................................................
17.5.2 Position Counter Latch .......................................................................................
17.5.3 Position Counter Initialization ................................................................................
17.5.4 eQEP Position-compare Unit ................................................................................
17.6 eQEP Edge Capture Unit ..............................................................................................
17.7 eQEP Watchdog .........................................................................................................
17.8 Unit Timer Base .........................................................................................................
17.9 eQEP Interrupt Structure ...............................................................................................
17.10 Registers .................................................................................................................
17.10.1 eQEP Base Addresses .....................................................................................
17.10.2 EQEP_REGS Registers ....................................................................................

18

Serial Peripheral Interface (SPI) ........................................................................................ 2124
18.1

18.2

18.3

18.4

18.5

19

SPI Module Overview ...................................................................................................
18.1.1 Features ........................................................................................................
18.1.2 CPU Interface ..................................................................................................
System-Level Integration ...............................................................................................
18.2.1 SPI Module Signals ...........................................................................................
18.2.2 Configuring Device Pins ......................................................................................
18.2.3 SPI Interrupts ..................................................................................................
18.2.4 DMA Support ..................................................................................................
SPI Operation ............................................................................................................
18.3.1 Introduction to Operation .....................................................................................
18.3.2 Master Mode ...................................................................................................
18.3.3 Slave Mode ....................................................................................................
18.3.4 Data Format ....................................................................................................
18.3.5 Baud Rate Selection .........................................................................................
18.3.6 SPI Clocking Schemes .......................................................................................
18.3.7 SPI FIFO Description .........................................................................................
18.3.8 SPI DMA Transfers ...........................................................................................
18.3.9 SPI High-Speed Mode ........................................................................................
18.3.10 SPI 3-Wire Mode Description ..............................................................................
Programming Procedure ...............................................................................................
18.4.1 Initialization Upon Reset .....................................................................................
18.4.2 Configuring the SPI ...........................................................................................
18.4.3 Configuring the SPI for High-Speed Mode .................................................................
18.4.4 Data Transfer Example .......................................................................................
18.4.5 SPI STEINV Bit in Digital Audio Transfers .................................................................
Registers .................................................................................................................
18.5.1 SPI Base Addresses ..........................................................................................
18.5.2 SPI_REGS Registers .........................................................................................

Serial Communications Interface (SCI)
19.1
19.2
19.3
19.4
19.5

10

2072
2073
2074
2074
2077
2077
2077
2077
2079
2081
2082
2083
2087
2087
2088
2089
2089
2090

.............................................................................. 2164

Enhanced SCI Module Overview ......................................................................................
Architecture ..............................................................................................................
SCI Module Signal Summary ..........................................................................................
Configuring Device Pins ................................................................................................
Multiprocessor and Asynchronous Communication Modes........................................................

Contents

2125
2125
2125
2126
2126
2127
2127
2129
2130
2130
2131
2132
2133
2134
2135
2136
2137
2138
2138
2139
2139
2140
2140
2141
2142
2144
2144
2145
2165
2166
2167
2167
2167

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

19.6
19.7

19.8

19.9
19.10

19.11
19.12
19.13

19.14

20

2168
2168
2169
2169
2169
2169
2170
2170
2170
2171
2171
2171
2172
2173
2173
2174
2174
2175
2175
2176
2177
2178
2178
2179

Inter-Integrated Circuit Module (I2C) .................................................................................. 2199
20.1

20.2
20.3

20.4

20.5
20.6

21

SCI Programmable Data Format ......................................................................................
SCI Multiprocessor Communication ..................................................................................
19.7.1 Recognizing the Address Byte ..............................................................................
19.7.2 Controlling the SCI TX and RX Features ..................................................................
19.7.3 Receipt Sequence.............................................................................................
Idle-Line Multiprocessor Mode.........................................................................................
19.8.1 Idle-Line Mode Steps .........................................................................................
19.8.2 Block Start Signal .............................................................................................
19.8.3 Wake-UP Temporary (WUT) Flag ..........................................................................
19.8.4 Receiver Operation ...........................................................................................
Address-Bit Multiprocessor Mode .....................................................................................
19.9.1 Sending an Address ..........................................................................................
SCI Communication Format ...........................................................................................
19.10.1 Receiver Signals in Communication Modes..............................................................
19.10.2 Transmitter Signals in Communication Modes...........................................................
SCI Port Interrupts ......................................................................................................
SCI Baud Rate Calculations ...........................................................................................
SCI Enhanced Features................................................................................................
19.13.1 SCI FIFO Description .......................................................................................
19.13.2 SCI Auto-Baud ...............................................................................................
19.13.3 Autobaud-Detect Sequence ................................................................................
Registers .................................................................................................................
19.14.1 SCI Base Addresses ........................................................................................
19.14.2 SCI_REGS Registers .......................................................................................
Introduction to the I2C Module ........................................................................................
20.1.1 Features ........................................................................................................
20.1.2 Features Not Supported ......................................................................................
20.1.3 Functional Overview ..........................................................................................
20.1.4 Clock Generation ..............................................................................................
20.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) ..................................................
Configuring Device Pins ................................................................................................
I2C Module Operational Details .......................................................................................
20.3.1 Input and Output Voltage Levels ............................................................................
20.3.2 Data Validity ...................................................................................................
20.3.3 Operating Modes ..............................................................................................
20.3.4 I2C Module START and STOP Conditions ................................................................
20.3.5 Serial Data Formats...........................................................................................
20.3.6 NACK Bit Generation .........................................................................................
20.3.7 Clock Synchronization ........................................................................................
20.3.8 Arbitration ......................................................................................................
20.3.9 Digital Loopback Mode .......................................................................................
Interrupt Requests Generated by the I2C Module ..................................................................
20.4.1 Basic I2C Interrupt Requests ................................................................................
20.4.2 I2C FIFO Interrupts ...........................................................................................
Resetting or Disabling the I2C Module ...............................................................................
Registers .................................................................................................................
20.6.1 I2C Base Addresses ..........................................................................................
20.6.2 I2C_REGS Registers .........................................................................................

2200
2200
2200
2201
2202
2203
2204
2204
2204
2204
2204
2205
2206
2208
2209
2209
2210
2211
2211
2212
2213
2214
2214
2215

Multichannel Buffered Serial Port (McBSP) ........................................................................ 2239
21.1

Overview.................................................................................................................. 2240
21.1.1 Features of the McBSPs ..................................................................................... 2240
21.1.2 McBSP Pins/Signals .......................................................................................... 2241

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Contents

11

www.ti.com

21.2
21.3

21.4

21.5

21.6

21.7

21.8

12

Configuring Device Pins ................................................................................................
McBSP Operation .......................................................................................................
21.3.1 Data Transfer Process of McBSPs .........................................................................
21.3.2 Companding (Compressing and Expanding) Data........................................................
21.3.3 Clocking and Framing Data ..................................................................................
21.3.4 Frame Phases .................................................................................................
21.3.5 McBSP Reception .............................................................................................
21.3.6 McBSP Transmission .........................................................................................
21.3.7 Interrupts and DMA Events Generated by a McBSP .....................................................
McBSP Sample Rate Generator ......................................................................................
21.4.1 Block Diagram .................................................................................................
21.4.2 Frame Synchronization Generation in the Sample Rate Generator ....................................
21.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock .................................
21.4.4 Reset and Initialization Procedure for the Sample Rate Generator ....................................
McBSP Exception/Error Conditions ...................................................................................
21.5.1 Types of Errors ................................................................................................
21.5.2 Overrun in the Receiver ......................................................................................
21.5.3 Unexpected Receive Frame-Synchronization Pulse .....................................................
21.5.4 Overwrite in the Transmitter .................................................................................
21.5.5 Underflow in the Transmitter .................................................................................
21.5.6 Unexpected Transmit Frame-Synchronization Pulse .....................................................
Multichannel Selection Modes .........................................................................................
21.6.1 Channels, Blocks, and Partitions ............................................................................
21.6.2 Multichannel Selection ........................................................................................
21.6.3 Configuring a Frame for Multichannel Selection ..........................................................
21.6.4 Using Two Partitions ..........................................................................................
21.6.5 Using Eight Partitions .........................................................................................
21.6.6 Receive Multichannel Selection Mode......................................................................
21.6.7 Transmit Multichannel Selection Modes ...................................................................
21.6.8 Using Interrupts Between Block Transfers .................................................................
SPI Operation Using the Clock Stop Mode ..........................................................................
21.7.1 SPI Protocol ....................................................................................................
21.7.2 Clock Stop Mode ..............................................................................................
21.7.3 Bits Used to Enable and Configure the Clock Stop Mode ...............................................
21.7.4 Clock Stop Mode Timing Diagrams .........................................................................
21.7.5 Procedure for Configuring a McBSP for SPI Operation ..................................................
21.7.6 McBSP as the SPI Master ...................................................................................
21.7.7 McBSP as an SPI Slave......................................................................................
Receiver Configuration .................................................................................................
21.8.1 Programming the McBSP Registers for the Desired Receiver Operation .............................
21.8.2 Resetting and Enabling the Receiver .......................................................................
21.8.3 Set the Receiver Pins to Operate as McBSP Pins .......................................................
21.8.4 Enable/Disable the Digital Loopback Mode ................................................................
21.8.5 Enable/Disable the Clock Stop Mode.......................................................................
21.8.6 Enable/Disable the Receive Multichannel Selection Mode ..............................................
21.8.7 Choose One or Two Phases for the Receive Frame .....................................................
21.8.8 Set the Receive Word Length(s) ............................................................................
21.8.9 Set the Receive Frame Length ..............................................................................
21.8.10 Enable/Disable the Receive Frame-Synchronization Ignore Function ................................
21.8.11 Set the Receive Companding Mode ......................................................................
21.8.12 Set the Receive Data Delay ................................................................................
21.8.13 Set the Receive Sign-Extension and Justification Mode ...............................................
21.8.14 Set the Receive Interrupt Mode ............................................................................

Contents

2242
2242
2243
2244
2245
2248
2250
2251
2252
2252
2253
2256
2256
2258
2259
2259
2259
2261
2263
2264
2265
2267
2267
2268
2268
2268
2270
2271
2271
2273
2274
2274
2275
2275
2276
2278
2278
2280
2281
2281
2282
2282
2283
2283
2284
2284
2285
2285
2286
2287
2288
2290
2291

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

21.9

21.10

21.11

21.12

21.13
21.14

21.8.15 Set the Receive Frame-Synchronization Mode ..........................................................
21.8.16 Set the Receive Frame-Synchronization Polarity........................................................
21.8.17 Set the Receive Clock Mode ...............................................................................
21.8.18 Set the Receive Clock Polarity .............................................................................
21.8.19 Set the SRG Clock Divide-Down Value...................................................................
21.8.20 Set the SRG Clock Synchronization Mode ...............................................................
21.8.21 Set the SRG Clock Mode (Choose an Input Clock) .....................................................
21.8.22 Set the SRG Input Clock Polarity ..........................................................................
Transmitter Configuration ..............................................................................................
21.9.1 Programming the McBSP Registers for the Desired Transmitter Operation ..........................
21.9.2 Resetting and Enabling the Transmitter ....................................................................
21.9.3 Set the Transmitter Pins to Operate as McBSP Pins ....................................................
21.9.4 Enable/Disable the Digital Loopback Mode ................................................................
21.9.5 Enable/Disable the Clock Stop Mode.......................................................................
21.9.6 Enable/Disable Transmit Multichannel Selection .........................................................
21.9.7 Choose One or Two Phases for the Transmit Frame ....................................................
21.9.8 Set the Transmit Word Length(s) ...........................................................................
21.9.9 Set the Transmit Frame Length .............................................................................
21.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function ...............................
21.9.11 Set the Transmit Companding Mode ......................................................................
21.9.12 Set the Transmit Data Delay ...............................................................................
21.9.13 Set the Transmit DXENA Mode ............................................................................
21.9.14 Set the Transmit Interrupt Mode ...........................................................................
21.9.15 Set the Transmit Frame-Synchronization Mode .........................................................
21.9.16 Set the Transmit Frame-Synchronization Polarity .......................................................
21.9.17 Set the SRG Frame-Synchronization Period and Pulse Width ........................................
21.9.18 Set the Transmit Clock Mode ..............................................................................
21.9.19 Set the Transmit Clock Polarity ............................................................................
Emulation and Reset Considerations ................................................................................
21.10.1 McBSP Emulation Mode ....................................................................................
21.10.2 Resetting and Initializing McBSPs .........................................................................
Data Packing Examples ................................................................................................
21.11.1 Data Packing Using Frame Length and Word Length ..................................................
21.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function ...............
Interrupt Generation ....................................................................................................
21.12.1 McBSP Receive Interrupt Generation .....................................................................
21.12.2 McBSP Transmit Interrupt Generation ....................................................................
21.12.3 Error Flags ...................................................................................................
McBSP Modes...........................................................................................................
McBSP Registers ......................................................................................................
21.14.1 McBSP Base Addresses ....................................................................................
21.14.2 Data Receive Registers (DRR[1,2]) .......................................................................
21.14.3 Data Transmit Registers (DXR[1,2]) ......................................................................
21.14.4 Serial Port Control Registers (SPCR[1,2]) ...............................................................
21.14.5 Receive Control Registers (RCR[1, 2]) ..................................................................
21.14.6 Transmit Control Registers (XCR1 and XCR2) ..........................................................
21.14.7 Sample Rate Generator Registers (SRGR1 and SRGR2) .............................................
21.14.8 Multichannel Control Registers (MCR[1,2]) ..............................................................
21.14.9 Pin Control Register (PCR) .................................................................................
21.14.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF,
RCERG, RCERH) ..............................................................................................
21.14.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF,
XCERG, XCERH) ..............................................................................................
21.14.12 McBSP Interrupt Enable Register ........................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Contents

2291
2293
2295
2296
2298
2298
2299
2300
2300
2300
2301
2302
2302
2302
2303
2305
2305
2306
2307
2308
2309
2311
2311
2312
2313
2314
2315
2315
2316
2317
2317
2319
2319
2321
2321
2322
2322
2323
2323
2325
2325
2326
2326
2327
2332
2334
2337
2339
2344
2346
2348
2350
13

www.ti.com

22

Controller Area Network (CAN) ......................................................................................... 2351
22.1

22.2
22.3
22.4

22.5
22.6

22.7
22.8
22.9
22.10

22.11

22.12

22.13

22.14

22.15

14

Overview..................................................................................................................
22.1.1 Features .......................................................................................................
22.1.2 Functional Description .......................................................................................
22.1.3 Block Diagram ................................................................................................
Configuring Device Pins ................................................................................................
Address/Data Bus Bridge ..............................................................................................
Operating Modes ........................................................................................................
22.4.1 Initialization ....................................................................................................
22.4.2 CAN Message Transfer (Normal Operation) ..............................................................
22.4.3 Test Modes ....................................................................................................
Multiple Clock Source ..................................................................................................
Interrupt Functionality ..................................................................................................
22.6.1 Message Object Interrupts ..................................................................................
22.6.2 Status Change Interrupts ....................................................................................
22.6.3 Error Interrupts ................................................................................................
22.6.4 PIE Nomenclature for DCAN Interrupts ....................................................................
Parity Check Mechanism ..............................................................................................
22.7.1 Behavior on Parity Error .....................................................................................
Debug Mode ............................................................................................................
Module Initialization ....................................................................................................
Configuration of Message Objects ...................................................................................
22.10.1 Configuration of a Transmit Object for Data Frames ...................................................
22.10.2 Configuration of a Transmit Object for Remote Frames ...............................................
22.10.3 Configuration of a Single Receive Object for Data Frames ...........................................
22.10.4 Configuration of a Single Receive Object for Remote Frames .......................................
22.10.5 Configuration of a FIFO Buffer ............................................................................
Message Handling .....................................................................................................
22.11.1 Message Handler Overview ...............................................................................
22.11.2 Receive/Transmit Priority ..................................................................................
22.11.3 Transmission of Messages in Event Driven CAN Communication ...................................
22.11.4 Updating a Transmit Object ...............................................................................
22.11.5 Changing a Transmit Object ...............................................................................
22.11.6 Acceptance Filtering of Received Messages ............................................................
22.11.7 Reception of Data Frames .................................................................................
22.11.8 Reception of Remote Frames .............................................................................
22.11.9 Reading Received Messages .............................................................................
22.11.10 Requesting New Data for a Receive Object ...........................................................
22.11.11 Storing Received Messages in FIFO Buffers ..........................................................
22.11.12 Reading from a FIFO Buffer .............................................................................
CAN Bit Timing .........................................................................................................
22.12.1 Bit Time and Bit Rate .......................................................................................
22.12.2 Configuration of the CAN Bit Timing .....................................................................
Message Interface Register Sets ....................................................................................
22.13.1 Message Interface Register Sets 1 and 2 ...............................................................
22.13.2 IF3 Register Set .............................................................................................
Message RAM ..........................................................................................................
22.14.1 Structure of Message Objects .............................................................................
22.14.2 Addressing Message Objects in RAM ...................................................................
22.14.3 Message RAM Representation in Debug Mode ........................................................
Registers .................................................................................................................
22.15.1 CAN Base Addresses .......................................................................................
22.15.2 CAN_REGS Registers ......................................................................................

Contents

2352
2352
2352
2353
2354
2354
2355
2355
2356
2357
2360
2360
2360
2360
2360
2361
2361
2361
2361
2362
2362
2362
2363
2363
2363
2364
2364
2364
2364
2365
2365
2365
2366
2366
2366
2367
2367
2367
2367
2368
2369
2373
2376
2377
2378
2378
2378
2380
2381
2383
2383
2384

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

23

Universal Serial Bus (USB) Controller................................................................................ 2445
23.1
23.2

23.3

23.4

23.5
23.6

Introduction ...............................................................................................................
Features ..................................................................................................................
23.2.1 Block Diagram .................................................................................................
23.2.2 Signal Description .............................................................................................
23.2.3 VBus Recommendations .....................................................................................
Functional Description ..................................................................................................
23.3.1 Operation as a Device ........................................................................................
23.3.2 Operation as a Host...........................................................................................
23.3.3 DMA Operation ................................................................................................
23.3.4 Address/Data Bus Bridge ....................................................................................
Initialization and Configuration.........................................................................................
23.4.1 Pin Configuration ..............................................................................................
23.4.2 Endpoint Configuration .......................................................................................
Register Map .............................................................................................................
Register Descriptions ...................................................................................................
23.6.1 USB Device Functional Address Register (USBFADDR), offset 0x000................................
23.6.2 USB Power Management Register (USBPOWER), offset 0x001 .......................................
23.6.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002 .....................................
23.6.4 USB Receive Interrupt Status Register (USBRXIS), offset 0x004 ......................................
23.6.5 USB Transmit Interrupt Enable Register (USBTXIE), offset 0x006 ....................................
23.6.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008 .....................................
23.6.7 USB General Interrupt Status Register (USBIS), offset 0x00A .........................................
23.6.8 USB Interrupt Enable Register (USBIE), offset 0x00B ...................................................
23.6.9 USB Frame Value Register (USBFRAME), offset 0x00C ................................................
23.6.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E .............................................
23.6.11 USB Test Mode Register (USBTEST), offset 0x00F ....................................................
23.6.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[15]) ..........................................
23.6.13 USB Device Control Register (USBDEVCTL), offset 0x060 ...........................................
23.6.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062......................
23.6.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063 ......................
23.6.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064......................
23.6.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066 ......................
23.6.18 USB Connect Timing Register (USBCONTIM), offset 0x07A ..........................................
23.6.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset
0x07D ............................................................................................................
23.6.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset
0x07E ............................................................................................................
23.6.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]USBTXFUNCADDR[15]) ......................................................................................
23.6.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]USBTXHUBADDR[15]) ........................................................................................
23.6.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[15]) ...
23.6.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]USBRXFUNCADDR[15]) ......................................................................................
23.6.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]USBRXHUBADDR[15]) ........................................................................................
23.6.26 USB Receive Hub Port Endpoint n Registers (USBRXHUBPORT[1]-USBRXHUBPORT[15]) ....
23.6.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[15]) .......
23.6.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102 .....................
23.6.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103 ....................
23.6.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108 .......................
23.6.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A ...........................................
23.6.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B ................................................
23.6.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Contents

2446
2446
2446
2447
2447
2448
2448
2452
2455
2455
2457
2457
2457
2458
2473
2473
2474
2476
2478
2480
2482
2484
2486
2488
2488
2489
2491
2492
2494
2495
2496
2497
2498
2499
2499
2500
2501
2502
2503
2504
2505
2506
2507
2509
2510
2510
2511
15

www.ti.com

USBTXCSRL[15]) ..............................................................................................
23.6.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]USBTXCSRH[15]) ..............................................................................................
23.6.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[15]) .......
23.6.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]USBRXCSRL[15)] ..............................................................................................
23.6.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]USBRXCSRH[15]) .............................................................................................
23.6.38 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[15]) ........
23.6.39 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[15]) ...
23.6.40 USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[15]) .
23.6.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[15]) ...
23.6.42 USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[1]USBRXINTERVAL[15]) ........................................................................................
23.6.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]USBRQPKTCOUNT[15]) ......................................................................................
23.6.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340 .....
23.6.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342 ....
23.6.46 USB External Power Control Register (USBEPC), offset 0x400 ......................................
23.6.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404 ........
23.6.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408 .................
23.6.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C .
23.6.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410 .................
23.6.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414 ....................
23.6.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418 ...........
23.6.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C ....................
23.6.54 USB DMA Select Register (USBDMASEL), offset 0x450 ..............................................

24

Universal Parallel Port (uPP)
24.1
24.2
24.3

24.4

24.5

25

2515
2517
2518
2520
2522
2523
2524
2525
2526
2527
2528
2530
2531
2533
2534
2535
2536
2537
2538
2539
2540

............................................................................................ 2542

Introduction ...............................................................................................................
24.1.1 Features Supported ...........................................................................................
Configuring Device Pins ................................................................................................
Functional Description ..................................................................................................
24.3.1 Functional Block Diagram ....................................................................................
24.3.2 Data Flow ......................................................................................................
24.3.3 Clock Generation and Control ...............................................................................
IO Interface and System Requirements ..............................................................................
24.4.1 Pin Multiplexing ................................................................................................
24.4.2 Internal DMA Controller Description ........................................................................
24.4.3 Protocol Description ..........................................................................................
24.4.4 Data Format ....................................................................................................
24.4.5 Reset Considerations .........................................................................................
24.4.6 Interrupt Support ..............................................................................................
24.4.7 Emulation Considerations ....................................................................................
24.4.8 Transmit and Receive FIFOs ................................................................................
24.4.9 Transmit and Receive Data (MSG) RAM ..................................................................
24.4.10 Initialization and Operation .................................................................................
Registers .................................................................................................................
24.5.1 UPP Base Addresses .........................................................................................
24.5.2 UPP_REGS Registers ........................................................................................

2543
2543
2544
2544
2544
2544
2545
2547
2547
2547
2549
2552
2552
2553
2554
2554
2554
2555
2557
2557
2558

External Memory Interface (EMIF) ..................................................................................... 2593
25.1

16

2512

Introduction ...............................................................................................................
25.1.1 Purpose of the Peripheral ....................................................................................
25.1.2 Features ........................................................................................................
25.1.3 Functional Block Diagram ....................................................................................

Contents

2594
2595
2595
2595

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

25.2
25.3

25.4

25.5

Configuring Device Pins ................................................................................................
EMIF Module Architecture .............................................................................................
25.3.1 EMIF Clock Control ...........................................................................................
25.3.2 EMIF Requests ................................................................................................
25.3.3 EMIF Signal Descriptions ....................................................................................
25.3.4 EMIF Signal Multiplexing Control ...........................................................................
25.3.5 SDRAM Controller and Interface ............................................................................
25.3.6 Asynchronous Controller and Interface ....................................................................
25.3.7 Data Bus Parking..............................................................................................
25.3.8 Reset and Initialization Considerations .....................................................................
25.3.9 Interrupt Support ..............................................................................................
25.3.10 DMA Event Support .........................................................................................
25.3.11 EMIF Signal Multiplexing ...................................................................................
25.3.12 Memory Map .................................................................................................
25.3.13 Priority and Arbitration ......................................................................................
25.3.14 System Considerations .....................................................................................
25.3.15 Power Management .........................................................................................
25.3.16 Emulation Considerations ..................................................................................
Example Configuration .................................................................................................
25.4.1 Hardware Interface ............................................................................................
25.4.2 Software Configuration .......................................................................................
Registers .................................................................................................................
25.5.1 EMIF Base Addresses ........................................................................................
25.5.2 EMIF_REGS Registers .......................................................................................
25.5.3 EMIF1_CONFIG_REGS Registers .........................................................................
25.5.4 EMIF2_CONFIG_REGS Registers .........................................................................

2596
2596
2596
2596
2597
2598
2598
2611
2623
2623
2623
2624
2624
2624
2625
2626
2627
2627
2628
2628
2628
2636
2636
2637
2657
2662

Revision History ...................................................................................................................... 2666

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Contents

17

www.ti.com

List of Figures
Device Interrupt Architecture

2-2.

Interrupt Propagation Path ................................................................................................ 92

2-3.

Missing Clock Detection Logic .......................................................................................... 105

2-4.

ERRORSTS Pin Diagram

2-5.

Clocking System .......................................................................................................... 108

2-6.

Single-ended 3.3V External Clock ...................................................................................... 109

2-7.

External Crystal ........................................................................................................... 110

2-8.

External Resonator ....................................................................................................... 110

2-9.

AUXCLKIN ................................................................................................................. 110

2-10.

CPU-Timers

2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.
2-26.
2-27.
2-28.
2-29.
2-30.
2-31.
2-32.
2-33.
2-34.
2-35.
2-36.
2-37.
2-38.
2-39.
2-40.
2-41.
2-42.
2-43.
2-44.
2-45.
2-46.
2-47.
18

.............................................................................................

2-1.

...............................................................................................

...............................................................................................................
CPU-Timer Interrupts Signals and Output Signal ....................................................................
CPU Watchdog Timer Module .........................................................................................
Memory Architecture .....................................................................................................
Arbitration Scheme on Global Shared Memories .....................................................................
Arbitration Scheme on Local Shared Memories ......................................................................
FMC Interface with Core, Bank and Pump ............................................................................
Flash Prefetch Mode .....................................................................................................
ECC Logic Inputs and Outputs..........................................................................................
Flash Pump Semaphore (PUMPREQUEST) States and State Transitions .......................................
Clock Configuration Semaphore (CLKSEM) State Transitions .....................................................
Storage of Zone-Select Bits in OTP ...................................................................................
Location of Zone-Select Block Based on Link-Pointer ...............................................................
CSM Password Match Flow (PMF) .....................................................................................
ECSL Password Match Flow (PMF) ....................................................................................
TIM Register ...............................................................................................................
PRD Register ..............................................................................................................
TCR Register ..............................................................................................................
TPR Register ..............................................................................................................
TPRH Register ............................................................................................................
PIECTRL Register ........................................................................................................
PIEACK Register..........................................................................................................
PIEIER1 Register .........................................................................................................
PIEIFR1 Register .........................................................................................................
PIEIER2 Register .........................................................................................................
PIEIFR2 Register .........................................................................................................
PIEIER3 Register .........................................................................................................
PIEIFR3 Register .........................................................................................................
PIEIER4 Register .........................................................................................................
PIEIFR4 Register .........................................................................................................
PIEIER5 Register .........................................................................................................
PIEIFR5 Register .........................................................................................................
PIEIER6 Register .........................................................................................................
PIEIFR6 Register .........................................................................................................
PIEIER7 Register .........................................................................................................
PIEIFR7 Register .........................................................................................................
PIEIER8 Register .........................................................................................................
PIEIFR8 Register .........................................................................................................

List of Figures

90

107

117
118
119
125
127
128
135
138
141
145
145
149
150
154
156
161
162
163
165
166
169
170
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

2-48.

PIEIER9 Register ......................................................................................................... 203

2-49.

PIEIFR9 Register ......................................................................................................... 205

2-50.

PIEIER10 Register........................................................................................................ 207

2-51.

PIEIFR10 Register ........................................................................................................ 209

2-52.

PIEIER11 Register........................................................................................................ 211

2-53.

PIEIFR11 Register ........................................................................................................ 213

2-54.

PIEIER12 Register........................................................................................................ 215

2-55.

PIEIFR12 Register ........................................................................................................ 217

2-56.

SCSR Register ............................................................................................................ 220

2-57.

WDCNTR Register

2-58.

WDKEY Register.......................................................................................................... 222

2-59.

WDCR Register ........................................................................................................... 223

2-60.

WDWCR Register

2-61.

NMICFG Register ......................................................................................................... 226

2-62.

NMIFLG Register ......................................................................................................... 227

2-63.

NMIFLGCLR Register .................................................................................................... 229

2-64.

NMIFLGFRC Register .................................................................................................... 232

2-65.

NMIWDCNT Register

2-66.

NMIWDPRD Register .................................................................................................... 235

2-67.

NMISHDFLG Register.................................................................................................... 236

2-68.

XINT1CR Register ........................................................................................................ 239

2-69.

XINT2CR Register ........................................................................................................ 240

2-70.

XINT3CR Register ........................................................................................................ 241

2-71.

XINT4CR Register ........................................................................................................ 242

2-72.

XINT5CR Register ........................................................................................................ 243

2-73.

XINT1CTR Register ...................................................................................................... 244

2-74.

XINT2CTR Register ...................................................................................................... 245

2-75.

XINT3CTR Register ...................................................................................................... 246

2-76.

CLA1TASKSRCSELLOCK Register

2-77.
2-78.
2-79.
2-80.
2-81.
2-82.
2-83.
2-84.
2-85.
2-86.
2-87.
2-88.
2-89.
2-90.
2-91.
2-92.
2-93.
2-94.
2-95.
2-96.

.......................................................................................................

........................................................................................................

....................................................................................................

...................................................................................
DMACHSRCSELLOCK Register .......................................................................................
CLA1TASKSRCSEL1 Register .........................................................................................
CLA1TASKSRCSEL2 Register .........................................................................................
DMACHSRCSEL1 Register .............................................................................................
DMACHSRCSEL2 Register .............................................................................................
PUMPREQUEST Register...............................................................................................
DEVCFGLOCK1 Register ...............................................................................................
PARTIDL_1 Register .....................................................................................................
PARTIDH_1 Register.....................................................................................................
REVID Register ...........................................................................................................
DC0_1 Register ...........................................................................................................
DC1_1 Register ...........................................................................................................
DC2_1 Register ...........................................................................................................
DC3_1 Register ...........................................................................................................
DC4_1 Register ...........................................................................................................
DC5_1 Register ...........................................................................................................
DC6_1 Register ...........................................................................................................
DC7_1 Register ...........................................................................................................
DC8_1 Register ...........................................................................................................
DC9_1 Register ...........................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

221

224

234

248
249
250
251
252
253
255
258
260
262
263
264
265
266
267
269
270
271
272
273
274
19

www.ti.com

2-97.

DC10_1 Register.......................................................................................................... 275

2-98.

DC11_1 Register.......................................................................................................... 276

2-99.

DC12_1 Register.......................................................................................................... 277

2-100. DC13_1 Register.......................................................................................................... 278
2-101. DC14_1 Register.......................................................................................................... 279
2-102. DC15_1 Register.......................................................................................................... 280
2-103. DC17_1 Register.......................................................................................................... 282
2-104. DC18_1 Register.......................................................................................................... 283
2-105. DC19_1 Register.......................................................................................................... 284
2-106. DC20_1 Register.......................................................................................................... 285
2-107. PERCNF1_1 Register .................................................................................................... 287
2-108. FUSEERR Register....................................................................................................... 288
289

2-110. SOFTPRES1 Register

290

2-111.

291

2-112.
2-113.
2-114.
2-115.
2-116.
2-117.
2-118.
2-119.
2-120.
2-121.
2-122.
2-123.
2-124.
2-125.
2-126.
2-127.
2-128.
2-129.
2-130.
2-131.
2-132.
2-133.
2-134.
2-135.
2-136.
2-137.
2-138.
2-139.
2-140.
2-141.
2-142.
2-143.
2-144.
2-145.
20

...................................................................................................
...................................................................................................
SOFTPRES2 Register ...................................................................................................
SOFTPRES3 Register ...................................................................................................
SOFTPRES4 Register ...................................................................................................
SOFTPRES6 Register ...................................................................................................
SOFTPRES7 Register ...................................................................................................
SOFTPRES8 Register ...................................................................................................
SOFTPRES9 Register ...................................................................................................
SOFTPRES11 Register ..................................................................................................
SOFTPRES13 Register ..................................................................................................
SOFTPRES14 Register ..................................................................................................
SOFTPRES16 Register ..................................................................................................
CPUSEL0 Register .......................................................................................................
CPUSEL1 Register .......................................................................................................
CPUSEL2 Register .......................................................................................................
CPUSEL3 Register .......................................................................................................
CPUSEL4 Register .......................................................................................................
CPUSEL5 Register .......................................................................................................
CPUSEL6 Register .......................................................................................................
CPUSEL7 Register .......................................................................................................
CPUSEL8 Register .......................................................................................................
CPUSEL9 Register .......................................................................................................
CPUSEL11 Register ......................................................................................................
CPUSEL12 Register ......................................................................................................
CPUSEL14 Register ......................................................................................................
CPU2RESCTL Register..................................................................................................
RSTSTAT Register .......................................................................................................
LPMSTAT Register .......................................................................................................
SYSDBGCTL Register ...................................................................................................
CLKSEM Register ........................................................................................................
CLKCFGLOCK1 Register ................................................................................................
CLKSRCCTL1 Register ..................................................................................................
CLKSRCCTL2 Register ..................................................................................................
CLKSRCCTL3 Register ..................................................................................................
SYSPLLCTL1 Register ...................................................................................................
SYSPLLMULT Register ..................................................................................................

2-109. SOFTPRES0 Register

List of Figures

293
294
295
296
297
298
299
300
301
302
303
305
306
307
308
309
310
311
312
313
314
316
318
319
320
321
322
325
326
328
330
332
333
334

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

2-146. SYSPLLSTS Register .................................................................................................... 335
2-147. AUXPLLCTL1 Register

..................................................................................................

336

2-148. AUXPLLMULT Register .................................................................................................. 337
2-149. AUXPLLSTS Register .................................................................................................... 338
2-150. SYSCLKDIVSEL Register ............................................................................................... 339
2-151. AUXCLKDIVSEL Register ............................................................................................... 340
2-152. PERCLKDIVSEL Register ............................................................................................... 341
2-153. XCLKOUTDIVSEL Register ............................................................................................. 342

........................................................................................................
MCDCR Register .........................................................................................................
X1CNT Register...........................................................................................................
CPUSYSLOCK1 Register ...............................................................................................
HIBBOOTMODE Register ...............................................................................................
IORESTOREADDR Register ............................................................................................
PIEVERRADDR Register ................................................................................................
PCLKCR0 Register .......................................................................................................
PCLKCR1 Register .......................................................................................................
PCLKCR2 Register .......................................................................................................
PCLKCR3 Register .......................................................................................................
PCLKCR4 Register .......................................................................................................
PCLKCR6 Register .......................................................................................................
PCLKCR7 Register .......................................................................................................
PCLKCR8 Register .......................................................................................................
PCLKCR9 Register .......................................................................................................
PCLKCR10 Register .....................................................................................................
PCLKCR11 Register .....................................................................................................
PCLKCR12 Register .....................................................................................................
PCLKCR13 Register .....................................................................................................
PCLKCR14 Register .....................................................................................................
PCLKCR16 Register .....................................................................................................
SECMSEL_1 Register....................................................................................................
LPMCR Register ..........................................................................................................
GPIOLPMSEL0 Register.................................................................................................
GPIOLPMSEL1 Register.................................................................................................
TMR2CLKCTL Register ..................................................................................................
RESC Register ............................................................................................................
ROMPREFETCH Register...............................................................................................
Z1OTP_LINKPOINTER1 Register ......................................................................................
Z1OTP_LINKPOINTER2 Register ......................................................................................
Z1OTP_LINKPOINTER3 Register ......................................................................................
Z1OTP_PSWDLOCK Register ..........................................................................................
Z1OTP_CRCLOCK Register ............................................................................................
Z1OTP_BOOTCTRL Register...........................................................................................
Z2OTP_LINKPOINTER1 Register ......................................................................................
Z2OTP_LINKPOINTER2 Register ......................................................................................
Z2OTP_LINKPOINTER3 Register ......................................................................................
Z2OTP_PSWDLOCK Register ..........................................................................................
Z2OTP_CRCLOCK Register ............................................................................................
Z2OTP_BOOTCTRL Register...........................................................................................

2-154. LOSPCP Register

343

2-155.

344

2-156.
2-157.
2-158.
2-159.
2-160.
2-161.
2-162.
2-163.
2-164.
2-165.
2-166.
2-167.
2-168.
2-169.
2-170.
2-171.
2-172.
2-173.
2-174.
2-175.
2-176.
2-177.
2-178.
2-179.
2-180.
2-181.
2-182.
2-183.
2-184.
2-185.
2-186.
2-187.
2-188.
2-189.
2-190.
2-191.
2-192.
2-193.
2-194.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

345
348
351
352
353
354
356
357
359
361
362
363
364
365
366
367
368
369
370
372
373
374
376
379
382
384
387
389
390
391
392
393
394
396
397
398
399
400
401
21

www.ti.com

2-195. Z1_LINKPOINTER Register ............................................................................................. 403
2-196. Z1_OTPSECLOCK Register

............................................................................................

404

2-197. Z1_BOOTCTRL Register ................................................................................................ 405
2-198. Z1_LINKPOINTERERR Register ....................................................................................... 406
2-199. Z1_CSMKEY0 Register .................................................................................................. 407
2-200. Z1_CSMKEY1 Register .................................................................................................. 408
2-201. Z1_CSMKEY2 Register .................................................................................................. 409
2-202. Z1_CSMKEY3 Register .................................................................................................. 410
2-203. Z1_CR Register ........................................................................................................... 411
2-204. Z1_GRABSECTR Register .............................................................................................. 412
2-205. Z1_GRABRAMR Register ............................................................................................... 415
2-206. Z1_EXEONLYSECTR Register ......................................................................................... 417
2-207. Z1_EXEONLYRAMR Register .......................................................................................... 420
2-208. Z2_LINKPOINTER Register ............................................................................................. 423
2-209. Z2_OTPSECLOCK Register

............................................................................................

424

2-210. Z2_BOOTCTRL Register ................................................................................................ 425
2-211. Z2_LINKPOINTERERR Register ....................................................................................... 426
2-212. Z2_CSMKEY0 Register .................................................................................................. 427
2-213. Z2_CSMKEY1 Register .................................................................................................. 428
2-214. Z2_CSMKEY2 Register .................................................................................................. 429
2-215. Z2_CSMKEY3 Register .................................................................................................. 430
2-216. Z2_CR Register ........................................................................................................... 431
2-217. Z2_GRABSECTR Register .............................................................................................. 432
2-218. Z2_GRABRAMR Register ............................................................................................... 435
2-219. Z2_EXEONLYSECTR Register ......................................................................................... 437
2-220. Z2_EXEONLYRAMR Register .......................................................................................... 440
443

2-222. SECTSTAT Register

444

2-223.

447

2-224.
2-225.
2-226.
2-227.
2-228.
2-229.
2-230.
2-231.
2-232.
2-233.
2-234.
2-235.
2-236.
2-237.
2-238.
2-239.
2-240.
2-241.
2-242.
2-243.
22

..........................................................................................................
.....................................................................................................
RAMSTAT Register.......................................................................................................
DxLOCK Register .........................................................................................................
DxCOMMIT Register .....................................................................................................
DxACCPROT0 Register .................................................................................................
DxTEST Register .........................................................................................................
DxINIT Register ...........................................................................................................
DxINITDONE Register ...................................................................................................
LSxLOCK Register .......................................................................................................
LSxCOMMIT Register ....................................................................................................
LSxMSEL Register .......................................................................................................
LSxCLAPGM Register ...................................................................................................
LSxACCPROT0 Register ................................................................................................
LSxACCPROT1 Register ................................................................................................
LSxTEST Register ........................................................................................................
LSxINIT Register ..........................................................................................................
LSxINITDONE Register ..................................................................................................
GSxLOCK Register .......................................................................................................
GSxCOMMIT Register ...................................................................................................
GSxMSEL Register .......................................................................................................
GSxACCPROT0 Register ...............................................................................................
GSxACCPROT1 Register ...............................................................................................

2-221. FLSEM Register

List of Figures

451
452
453
454
455
456
457
459
461
463
464
466
467
469
470
471
474
477
479
481

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

...............................................................................................
GSxACCPROT3 Register ...............................................................................................
GSxTEST Register .......................................................................................................
GSxINIT Register .........................................................................................................
GSxINITDONE Register .................................................................................................
MSGxTEST Register .....................................................................................................
MSGxINIT Register .......................................................................................................
MSGxINITDONE Register ...............................................................................................
NMAVFLG Register ......................................................................................................
NMAVSET Register ......................................................................................................
NMAVCLR Register ......................................................................................................
NMAVINTEN Register....................................................................................................
NMCPURDAVADDR Register ..........................................................................................
NMCPUWRAVADDR Register ..........................................................................................
NMCPUFAVADDR Register .............................................................................................
NMDMAWRAVADDR Register .........................................................................................
NMCLA1RDAVADDR Register .........................................................................................
NMCLA1WRAVADDR Register .........................................................................................
NMCLA1FAVADDR Register............................................................................................
MAVFLG Register ........................................................................................................
MAVSET Register ........................................................................................................
MAVCLR Register ........................................................................................................
MAVINTEN Register .....................................................................................................
MCPUFAVADDR Register...............................................................................................
MCPUWRAVADDR Register ............................................................................................
MDMAWRAVADDR Register ...........................................................................................
UCERRFLG Register.....................................................................................................
UCERRSET Register.....................................................................................................
UCERRCLR Register ....................................................................................................
UCCPUREADDR Register ..............................................................................................
UCDMAREADDR Register ..............................................................................................
UCCLA1READDR Register .............................................................................................
CERRFLG Register.......................................................................................................
CERRSET Register.......................................................................................................
CERRCLR Register ......................................................................................................
CCPUREADDR Register ................................................................................................
CERRCNT Register ......................................................................................................
CERRTHRES Register ...................................................................................................
CEINTFLG Register ......................................................................................................
CEINTCLR Register ......................................................................................................
CEINTSET Register ......................................................................................................
CEINTEN Register........................................................................................................
ROMWAITSTATE Register ..............................................................................................
FRDCNTL Register .......................................................................................................
FBAC Register ............................................................................................................
FBFALLBACK Register ..................................................................................................
FBPRDY Register ........................................................................................................
FPAC1 Register ...........................................................................................................
FMSTAT Register .........................................................................................................

2-244. GSxACCPROT2 Register
2-245.
2-246.
2-247.
2-248.
2-249.
2-250.
2-251.
2-252.
2-253.
2-254.
2-255.
2-256.
2-257.
2-258.
2-259.
2-260.
2-261.
2-262.
2-263.
2-264.
2-265.
2-266.
2-267.
2-268.
2-269.
2-270.
2-271.
2-272.
2-273.
2-274.
2-275.
2-276.
2-277.
2-278.
2-279.
2-280.
2-281.
2-282.
2-283.
2-284.
2-285.
2-286.
2-287.
2-288.
2-289.
2-290.
2-291.
2-292.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

483
485
487
490
492
494
495
496
499
501
503
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
538
540
541
542
543
544
545
23

www.ti.com

2-293. FRD_INTF_CTRL Register .............................................................................................. 547
2-294. ECC_ENABLE Register.................................................................................................. 550
2-295. SINGLE_ERR_ADDR_LOW Register.................................................................................. 551
2-296. SINGLE_ERR_ADDR_HIGH Register ................................................................................. 552
2-297. UNC_ERR_ADDR_LOW Register...................................................................................... 553
2-298. UNC_ERR_ADDR_HIGH Register ..................................................................................... 554
2-299. ERR_STATUS Register.................................................................................................. 555
2-300. ERR_POS Register....................................................................................................... 557
2-301. ERR_STATUS_CLR Register ........................................................................................... 558
2-302. ERR_CNT Register ....................................................................................................... 559
2-303. ERR_THRESHOLD Register............................................................................................ 560
2-304. ERR_INTFLG Register ................................................................................................... 561
2-305. ERR_INTCLR Register

..................................................................................................

562

2-306. FDATAH_TEST Register ................................................................................................ 563
2-307. FDATAL_TEST Register ................................................................................................. 564
2-308. FADDR_TEST Register .................................................................................................. 565
2-309. FECC_TEST Register .................................................................................................... 566
2-310. FECC_CTRL Register.................................................................................................... 567
2-311. FOUTH_TEST Register .................................................................................................. 568
2-312. FOUTL_TEST Register .................................................................................................. 569
2-313. FECC_STATUS Register ................................................................................................ 570
2-314. CPUID_1 Register ........................................................................................................ 572
2-315. UID_PSRAND0 Register................................................................................................. 574
2-316. UID_PSRAND1 Register................................................................................................. 575
2-317. UID_PSRAND2 Register................................................................................................. 576
2-318. UID_PSRAND3 Register................................................................................................. 577
2-319. UID_PSRAND4 Register................................................................................................. 578
2-320. UID_PSRAND5 Register................................................................................................. 579
2-321. UID_UNIQUE Register ................................................................................................... 580
2-322. UID_CHECKSUM Register .............................................................................................. 581
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
24

......................................................................................
CPU1 Device Boot Flow .................................................................................................
CPU2 Device Boot Flow .................................................................................................
CPU1 Emulation Boot Flow .............................................................................................
CPU2 Emulation Boot Flow .............................................................................................
CPU1 Standalone and Hibernate Boot Flow ..........................................................................
CPU2 Standalone and Hibernate Boot Flow ..........................................................................
Overview of SCI Bootloader Operation ................................................................................
Overview of SCI Boot Function .........................................................................................
SPI Loader .................................................................................................................
Data Transfer From EEPROM Flow ....................................................................................
EEPROM Device at Address 0x50 .....................................................................................
Overview of I2C Boot Function .........................................................................................
Random Read .............................................................................................................
Sequential Read ..........................................................................................................
Overview of Parallel GPIO Bootloader Operation ....................................................................
Parallel GPIO Bootloader Handshake Protocol .......................................................................
Parallel GPIO Mode Overview ..........................................................................................
Parallel GPIO Mode - Host Transfer Flow .............................................................................
Z1 and Z2 BOOTCTRL Selection

List of Figures

585
588
589
590
591
592
593
599
600
600
602
602
603
604
605
605
606
606
607

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

3-20.

8-Bit Parallel GetWord Function ........................................................................................ 608

3-21.

Overview of CAN-A Bootloader Operation ............................................................................ 609

3-22.

USB Boot Flow ............................................................................................................ 610

4-1.

DMA Block Diagram ...................................................................................................... 625

4-2.

Common Peripheral Architecture ....................................................................................... 626

4-3.

DMA Trigger Architecture ................................................................................................ 628

4-4.

Peripheral Interrupt Trigger Input Diagram

4-5.

4-Stage Pipeline DMA Transfer ......................................................................................... 633

4-6.

4-Stage Pipeline With One Read Stall (McBSP as source) ......................................................... 633

4-7.

DMA State Diagram ...................................................................................................... 639

4-8.

Overrun Detection Logic ................................................................................................. 641

4-9.

DMA Control Register (DMACTRL) .................................................................................... 643

4-10.

Debug Control Register (DEBUGCTRL)

4-11.

Revision Register (REVISION).......................................................................................... 644

4-12.

Priority Control Register 1 (PRIORITYCTRL1) ....................................................................... 645

4-13.

Priority Status Register (PRIORITYSTAT)

4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.

...........................................................................

..............................................................................

............................................................................
Mode Register (MODE) .................................................................................................
Control Register (CONTROL) ..........................................................................................
Burst Size Register (BURST_SIZE) ....................................................................................
Burst Size Register (BURST_COUNT) ................................................................................
Source Burst Step Size Register (SRC_BURST_STEP) ............................................................
Destination Burst Step Register Size (DST_BURST_STEP) .......................................................
Transfer Size Register (TRANSFER_SIZE) ...........................................................................
Transfer Count Register (TRANSFER_COUNT) .....................................................................
Source Transfer Step Size Register (SRC_TRANSFER_STEP) ..................................................
Destination Transfer Step Size Register (DST_TRANSFER_STEP) .............................................
Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) ...............................................
Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) .........................................
Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) ......................................

629

644

646
647
649
651
651
652
653
653
654
654
655
655
656
656

4-27.

Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) ..................................................... 657

4-28.

Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR)

4-29.

Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) ................................................................... 658

4-30.

Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) ................. 658

5-1.

CLA Block Diagram ....................................................................................................... 661

5-2.

MVECT1 Register

795

5-3.

MVECT2 Register

796

5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.

.......

........................................................................................................
........................................................................................................
MVECT3 Register ........................................................................................................
MVECT4 Register ........................................................................................................
MVECT5 Register ........................................................................................................
MVECT6 Register ........................................................................................................
MVECT7 Register ........................................................................................................
MVECT8 Register ........................................................................................................
MCTL Register ............................................................................................................
MIFR Register .............................................................................................................
MIOVF Register ...........................................................................................................
MIFRC Register ...........................................................................................................
MICLR Register ...........................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

657

797
798
799
800
801
802
803
804
806
808
810
25

www.ti.com

5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
6-22.
6-23.
6-24.
6-25.
6-26.
6-27.
6-28.
6-29.
6-30.
6-31.
6-32.
6-33.
6-34.
6-35.
6-36.
26

.....................................................................................................
MIER Register .............................................................................................................
MIRUN Register...........................................................................................................
_MPC Register ............................................................................................................
_MAR0 Register ..........................................................................................................
_MAR1 Register ..........................................................................................................
_MSTF Register...........................................................................................................
_MR0 Register ............................................................................................................
_MR1 Register ............................................................................................................
_MR2 Register ............................................................................................................
_MR3 Register ............................................................................................................
SOFTINTEN Register ....................................................................................................
SOFTINTFRC Register ..................................................................................................
IPC Module Architecture .................................................................................................
Messaging with IPC Flags and Interrupts .............................................................................
IPCACK Register .........................................................................................................
IPCSTS Register ..........................................................................................................
IPCSET Register ..........................................................................................................
IPCCLR Register..........................................................................................................
IPCFLG Register ..........................................................................................................
IPCCOUNTERL Register ................................................................................................
IPCCOUNTERH Register ................................................................................................
IPCSENDCOM Register .................................................................................................
IPCSENDADDR Register ................................................................................................
IPCSENDDATA Register ................................................................................................
IPCREMOTEREPLY Register...........................................................................................
IPCRECVCOM Register .................................................................................................
IPCRECVADDR Register ................................................................................................
IPCRECVDATA Register ................................................................................................
IPCLOCALREPLY Register .............................................................................................
IPCBOOTSTS Register ..................................................................................................
IPCBOOTMODE Register ...............................................................................................
IPCACK Register .........................................................................................................
IPCSTS Register ..........................................................................................................
IPCSET Register ..........................................................................................................
IPCCLR Register..........................................................................................................
IPCFLG Register ..........................................................................................................
IPCCOUNTERL Register ................................................................................................
IPCCOUNTERH Register ................................................................................................
IPCRECVCOM Register .................................................................................................
IPCRECVADDR Register ................................................................................................
IPCRECVDATA Register ................................................................................................
IPCLOCALREPLY Register .............................................................................................
IPCSENDCOM Register .................................................................................................
IPCSENDADDR Register ................................................................................................
IPCSENDDATA Register ................................................................................................
IPCREMOTEREPLY Register...........................................................................................
IPCBOOTSTS Register ..................................................................................................
IPCBOOTMODE Register ...............................................................................................
MICLROVF Register

List of Figures

812
814
816
818
819
820
821
824
825
826
827
829
831
834
835
840
843
848
851
856
860
861
862
863
864
865
866
867
868
869
870
871
873
876
881
884
889
893
894
895
896
897
898
899
900
901
902
903
904

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

7-1.

GPIO Logic for a Single Pin ............................................................................................. 906

7-2.

Input Qualification Using a Sampling Window ........................................................................ 909

7-3.

Input Qualifier Clock Cycles ............................................................................................. 912

7-4.

GPACTRL Register ....................................................................................................... 926

7-5.

GPAQSEL1 Register ..................................................................................................... 927

7-6.

GPAQSEL2 Register ..................................................................................................... 929

7-7.

GPAMUX1 Register ...................................................................................................... 931

7-8.

GPAMUX2 Register ...................................................................................................... 933

7-9.

GPADIR Register ......................................................................................................... 935

7-10.

GPAPUD Register ........................................................................................................ 937

7-11.

GPAINV Register ......................................................................................................... 939

7-12.

GPAODR Register ........................................................................................................ 941

7-13.

GPAGMUX1 Register .................................................................................................... 943

7-14.

GPAGMUX2 Register .................................................................................................... 944

7-15.

GPACSEL1 Register ..................................................................................................... 945

7-16.

GPACSEL2 Register ..................................................................................................... 946

7-17.

GPACSEL3 Register ..................................................................................................... 947

7-18.

GPACSEL4 Register ..................................................................................................... 948

7-19.

GPALOCK Register

7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.

...................................................................................................... 949
GPACR Register .......................................................................................................... 951
GPBCTRL Register ....................................................................................................... 953
GPBQSEL1 Register ..................................................................................................... 954
GPBQSEL2 Register ..................................................................................................... 956
GPBMUX1 Register ...................................................................................................... 958
GPBMUX2 Register ...................................................................................................... 960
GPBDIR Register ......................................................................................................... 962
GPBPUD Register ........................................................................................................ 964
GPBINV Register ......................................................................................................... 966
GPBODR Register ........................................................................................................ 968
GPBAMSEL Register..................................................................................................... 970
GPBGMUX1 Register .................................................................................................... 972
GPBGMUX2 Register .................................................................................................... 973
GPBCSEL1 Register ..................................................................................................... 974
GPBCSEL2 Register ..................................................................................................... 975
GPBCSEL3 Register ..................................................................................................... 976
GPBCSEL4 Register ..................................................................................................... 977
GPBLOCK Register ...................................................................................................... 978
GPBCR Register .......................................................................................................... 980
GPCCTRL Register....................................................................................................... 982
GPCQSEL1 Register ..................................................................................................... 983
GPCQSEL2 Register ..................................................................................................... 985
GPCMUX1 Register ...................................................................................................... 987
GPCMUX2 Register ...................................................................................................... 989
GPCDIR Register ......................................................................................................... 991
GPCPUD Register ........................................................................................................ 993
GPCINV Register ......................................................................................................... 995
GPCODR Register........................................................................................................ 997
GPCGMUX1 Register .................................................................................................... 999
GPCGMUX2 Register .................................................................................................. 1000

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

27

www.ti.com

7-50.

GPCCSEL1 Register.................................................................................................... 1001

7-51.

GPCCSEL2 Register.................................................................................................... 1002

7-52.

GPCCSEL3 Register.................................................................................................... 1003

7-53.

GPCCSEL4 Register.................................................................................................... 1004

7-54.

GPCLOCK Register ..................................................................................................... 1005

7-55.

GPCCR Register ........................................................................................................ 1007

7-56.

GPDCTRL Register ..................................................................................................... 1009

7-57.

GPDQSEL1 Register

1010

7-58.

GPDQSEL2 Register

1012

7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
7-76.
7-77.
7-78.
7-79.
7-80.
7-81.
7-82.
7-83.
7-84.
7-85.
7-86.
7-87.
7-88.
7-89.
7-90.
7-91.
7-92.
7-93.
7-94.
7-95.
7-96.
7-97.
7-98.
28

...................................................................................................
...................................................................................................
GPDMUX1 Register.....................................................................................................
GPDMUX2 Register.....................................................................................................
GPDDIR Register .......................................................................................................
GPDPUD Register ......................................................................................................
GPDINV Register........................................................................................................
GPDODR Register ......................................................................................................
GPDGMUX1 Register ..................................................................................................
GPDGMUX2 Register ..................................................................................................
GPDCSEL1 Register....................................................................................................
GPDCSEL2 Register....................................................................................................
GPDCSEL3 Register....................................................................................................
GPDCSEL4 Register....................................................................................................
GPDLOCK Register .....................................................................................................
GPDCR Register ........................................................................................................
GPECTRL Register .....................................................................................................
GPEQSEL1 Register....................................................................................................
GPEQSEL2 Register....................................................................................................
GPEMUX1 Register .....................................................................................................
GPEMUX2 Register .....................................................................................................
GPEDIR Register........................................................................................................
GPEPUD Register.......................................................................................................
GPEINV Register ........................................................................................................
GPEODR Register ......................................................................................................
GPEGMUX1 Register ...................................................................................................
GPEGMUX2 Register ...................................................................................................
GPECSEL1 Register ....................................................................................................
GPECSEL2 Register ....................................................................................................
GPECSEL3 Register ....................................................................................................
GPECSEL4 Register ....................................................................................................
GPELOCK Register .....................................................................................................
GPECR Register ........................................................................................................
GPFCTRL Register .....................................................................................................
GPFQSEL1 Register ....................................................................................................
GPFMUX1 Register .....................................................................................................
GPFDIR Register ........................................................................................................
GPFPUD Register .......................................................................................................
GPFINV Register ........................................................................................................
GPFODR Register ......................................................................................................
GPFGMUX1 Register ...................................................................................................
GPFCSEL1 Register ....................................................................................................

List of Figures

1014
1016
1018
1020
1022
1024
1026
1028
1030
1031
1032
1033
1034
1036
1038
1039
1041
1043
1045
1047
1049
1051
1053
1055
1057
1059
1060
1061
1062
1063
1065
1067
1068
1070
1072
1074
1076
1078
1080
1081

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

7-99.

GPFCSEL2 Register .................................................................................................... 1082

7-100. GPFLOCK Register ..................................................................................................... 1083
7-101. GPFCR Register

........................................................................................................

1085

7-102. GPADAT Register ....................................................................................................... 1089
7-103. GPASET Register ....................................................................................................... 1091
7-104. GPACLEAR Register ................................................................................................... 1093
7-105. GPATOGGLE Register ................................................................................................. 1095
7-106. GPBDAT Register ....................................................................................................... 1097
7-107. GPBSET Register ....................................................................................................... 1099
7-108. GPBCLEAR Register ................................................................................................... 1101
7-109. GPBTOGGLE Register ................................................................................................. 1103
7-110. GPCDAT Register ....................................................................................................... 1105
7-111. GPCSET Register ....................................................................................................... 1107
7-112. GPCCLEAR Register ................................................................................................... 1109
7-113. GPCTOGGLE Register ................................................................................................. 1111
7-114. GPDDAT Register ....................................................................................................... 1113
7-115. GPDSET Register ....................................................................................................... 1115
7-116. GPDCLEAR Register ................................................................................................... 1117
7-117. GPDTOGGLE Register ................................................................................................. 1119
7-118. GPEDAT Register ....................................................................................................... 1121
7-119. GPESET Register ....................................................................................................... 1123
7-120. GPECLEAR Register ................................................................................................... 1125
7-121. GPETOGGLE Register ................................................................................................. 1127
7-122. GPFDAT Register ....................................................................................................... 1129
7-123. GPFSET Register ....................................................................................................... 1131

...................................................................................................
GPFTOGGLE Register .................................................................................................
Input X-BAR ..............................................................................................................
ePWM Architecture - Single Output...................................................................................
GPIO Output X-BAR Architecture .....................................................................................
ePWM and Output X-BARs Architectures ...........................................................................
INPUT1SELECT Register ..............................................................................................
INPUT2SELECT Register ..............................................................................................
INPUT3SELECT Register ..............................................................................................
INPUT4SELECT Register ..............................................................................................
INPUT5SELECT Register ..............................................................................................
INPUT6SELECT Register ..............................................................................................
INPUT7SELECT Register ..............................................................................................
INPUT8SELECT Register ..............................................................................................
INPUT9SELECT Register ..............................................................................................
INPUT10SELECT Register ............................................................................................
INPUT11SELECT Register ............................................................................................
INPUT12SELECT Register ............................................................................................
INPUT13SELECT Register ............................................................................................
INPUT14SELECT Register ............................................................................................
INPUTSELECTLOCK Register ........................................................................................
XBARFLG1 Register ....................................................................................................
XBARFLG2 Register ....................................................................................................
XBARFLG3 Register ....................................................................................................

7-124. GPFCLEAR Register

1133

7-125.

1135

8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

1138
1140
1142
1144
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1166
1168
1170
29

www.ti.com

8-23.

XBARCLR1 Register .................................................................................................... 1172

8-24.

XBARCLR2 Register .................................................................................................... 1174

8-25.

XBARCLR3 Register .................................................................................................... 1176

8-26.

TRIP4MUX0TO15CFG Register

8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
8-39.
8-40.
8-41.
8-42.
8-43.
8-44.
8-45.
8-46.
8-47.
8-48.
8-49.
8-50.
8-51.
8-52.
8-53.
8-54.
8-55.
8-56.
8-57.
8-58.
8-59.
8-60.
8-61.
8-62.
8-63.
8-64.
8-65.
8-66.
8-67.
8-68.
8-69.
8-70.
8-71.
30

......................................................................................
TRIP4MUX16TO31CFG Register .....................................................................................
TRIP5MUX0TO15CFG Register ......................................................................................
TRIP5MUX16TO31CFG Register .....................................................................................
TRIP7MUX0TO15CFG Register ......................................................................................
TRIP7MUX16TO31CFG Register .....................................................................................
TRIP8MUX0TO15CFG Register ......................................................................................
TRIP8MUX16TO31CFG Register .....................................................................................
TRIP9MUX0TO15CFG Register ......................................................................................
TRIP9MUX16TO31CFG Register .....................................................................................
TRIP10MUX0TO15CFG Register .....................................................................................
TRIP10MUX16TO31CFG Register ...................................................................................
TRIP11MUX0TO15CFG Register .....................................................................................
TRIP11MUX16TO31CFG Register ...................................................................................
TRIP12MUX0TO15CFG Register .....................................................................................
TRIP12MUX16TO31CFG Register ...................................................................................
TRIP4MUXENABLE Register ..........................................................................................
TRIP5MUXENABLE Register ..........................................................................................
TRIP7MUXENABLE Register ..........................................................................................
TRIP8MUXENABLE Register ..........................................................................................
TRIP9MUXENABLE Register ..........................................................................................
TRIP10MUXENABLE Register ........................................................................................
TRIP11MUXENABLE Register ........................................................................................
TRIP12MUXENABLE Register ........................................................................................
TRIPOUTINV Register..................................................................................................
TRIPLOCK Register ....................................................................................................
OUTPUT1MUX0TO15CFG Register .................................................................................
OUTPUT1MUX16TO31CFG Register ................................................................................
OUTPUT2MUX0TO15CFG Register .................................................................................
OUTPUT2MUX16TO31CFG Register ................................................................................
OUTPUT3MUX0TO15CFG Register .................................................................................
OUTPUT3MUX16TO31CFG Register ................................................................................
OUTPUT4MUX0TO15CFG Register .................................................................................
OUTPUT4MUX16TO31CFG Register ................................................................................
OUTPUT5MUX0TO15CFG Register .................................................................................
OUTPUT5MUX16TO31CFG Register ................................................................................
OUTPUT6MUX0TO15CFG Register .................................................................................
OUTPUT6MUX16TO31CFG Register ................................................................................
OUTPUT7MUX0TO15CFG Register .................................................................................
OUTPUT7MUX16TO31CFG Register ................................................................................
OUTPUT8MUX0TO15CFG Register .................................................................................
OUTPUT8MUX16TO31CFG Register ................................................................................
OUTPUT1MUXENABLE Register .....................................................................................
OUTPUT2MUXENABLE Register .....................................................................................
OUTPUT3MUXENABLE Register .....................................................................................
OUTPUT4MUXENABLE Register .....................................................................................

List of Figures

1180
1183
1186
1189
1192
1195
1198
1201
1204
1207
1210
1213
1216
1219
1222
1225
1228
1233
1238
1243
1248
1253
1258
1263
1268
1270
1273
1276
1279
1282
1285
1288
1291
1294
1297
1300
1303
1306
1309
1312
1315
1318
1321
1326
1331
1336

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

8-72.

OUTPUT5MUXENABLE Register ..................................................................................... 1341

8-73.

OUTPUT6MUXENABLE Register ..................................................................................... 1346

8-74.

OUTPUT7MUXENABLE Register ..................................................................................... 1351

8-75.

OUTPUT8MUXENABLE Register ..................................................................................... 1356

8-76.

OUTPUTLATCH Register .............................................................................................. 1361

8-77.

OUTPUTLATCHCLR Register......................................................................................... 1363

8-78.

OUTPUTLATCHFRC Register

1365

8-79.

OUTPUTLATCHENABLE Register

1367

8-80.
8-81.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.

........................................................................................
...................................................................................
OUTPUTINV Register ..................................................................................................
OUTPUTLOCK Register ...............................................................................................
Analog Subsystem Block Diagram (337-Ball ZWT) .................................................................
Analog Subsystem Block Diagram (176-Pin PTP) ..................................................................
Analog Subsystem Block Diagram (100-Pin PZP) ..................................................................
INTOSC1TRIM Register ................................................................................................
INTOSC2TRIM Register ................................................................................................
TSNSCTL Register ......................................................................................................
LOCK Register...........................................................................................................
ANAREFTRIMA Register...............................................................................................
ANAREFTRIMB Register...............................................................................................
ANAREFTRIMC Register ..............................................................................................
ANAREFTRIMD Register ..............................................................................................
ADC Module Block Diagram ...........................................................................................
SOC Block Diagram.....................................................................................................
Single-Ended Input Model ..............................................................................................
Differential Input Model .................................................................................................
Round Robin Priority Example ........................................................................................
High Priority Example ...................................................................................................
Burst Priority Example ..................................................................................................
ADC EOC Interrupts ....................................................................................................
ADC PPB Block Diagram ..............................................................................................
ADC PPB Interrupt Event ..............................................................................................
Opens/Shorts Detection Circuit ........................................................................................
ADC Timings for 12-bit Mode in Early Interrupt Mode .............................................................
ADC Timings for 12-bit Mode in Late Interrupt Mode ..............................................................
ADC Timings for 16-bit Mode in Early Interrupt Mode .............................................................
ADC Timings for 16-bit Mode in Late Interrupt Mode (SYSCLK Cycles) ........................................
Example: Basic Synchronous Operation .............................................................................
Example: Synchronous Operation with Multiple Trigger Sources.................................................
Example: Synchronous Operation with Uneven SOC Numbers ..................................................
Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow ..........................
Example: Asynchronous Operation with Different Resolutions ...................................................
Example: Synchronous Operation with Different Resolutions .....................................................
Example: Synchronous Equivalent Operation with Non-Overlapping Conversions ............................
ADC Reference System ................................................................................................
ADC Shared Reference System.......................................................................................
ADCCTL1 Register ......................................................................................................
ADCCTL2 Register ......................................................................................................
ADCBURSTCTL Register ..............................................................................................
ADCINTFLG Register ...................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

1369
1371
1374
1375
1376
1379
1380
1381
1382
1383
1384
1385
1386
1389
1393
1394
1394
1399
1400
1402
1403
1404
1405
1406
1409
1410
1411
1412
1414
1415
1416
1416
1416
1417
1417
1419
1420
1425
1427
1428
1430
31

www.ti.com

10-29. ADCINTFLGCLR Register ............................................................................................. 1432
10-30. ADCINTOVF Register

..................................................................................................

1434

10-31. ADCINTOVFCLR Register ............................................................................................. 1436
10-32. ADCINTSEL1N2 Register .............................................................................................. 1437
10-33. ADCINTSEL3N4 Register .............................................................................................. 1439
10-34. ADCSOCPRICTL Register ............................................................................................. 1441
1444

10-36. ADCINTSOCSEL2 Register

1446

10-37.

1448

10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
10-51.
10-52.
10-53.
10-54.
10-55.
10-56.
10-57.
10-58.
10-59.
10-60.
10-61.
10-62.
10-63.
10-64.
10-65.
10-66.
10-67.
10-68.
10-69.
10-70.
10-71.
10-72.
10-73.
10-74.
10-75.
10-76.
10-77.
32

...........................................................................................
...........................................................................................
ADCSOCFLG1 Register ................................................................................................
ADCSOCFRC1 Register ...............................................................................................
ADCSOCOVF1 Register ...............................................................................................
ADCSOCOVFCLR1 Register ..........................................................................................
ADCSOC0CTL Register ................................................................................................
ADCSOC1CTL Register ................................................................................................
ADCSOC2CTL Register ................................................................................................
ADCSOC3CTL Register ................................................................................................
ADCSOC4CTL Register ................................................................................................
ADCSOC5CTL Register ................................................................................................
ADCSOC6CTL Register ................................................................................................
ADCSOC7CTL Register ................................................................................................
ADCSOC8CTL Register ................................................................................................
ADCSOC9CTL Register ................................................................................................
ADCSOC10CTL Register ..............................................................................................
ADCSOC11CTL Register ..............................................................................................
ADCSOC12CTL Register ..............................................................................................
ADCSOC13CTL Register ..............................................................................................
ADCSOC14CTL Register ..............................................................................................
ADCSOC15CTL Register ..............................................................................................
ADCEVTSTAT Register ................................................................................................
ADCEVTCLR Register..................................................................................................
ADCEVTSEL Register ..................................................................................................
ADCEVTINTSEL Register..............................................................................................
ADCCOUNTER Register ...............................................................................................
ADCREV Register .......................................................................................................
ADCOFFTRIM Register ................................................................................................
ADCPPB1CONFIG Register ...........................................................................................
ADCPPB1STAMP Register ............................................................................................
ADCPPB1OFFCAL Register ...........................................................................................
ADCPPB1OFFREF Register...........................................................................................
ADCPPB1TRIPHI Register ............................................................................................
ADCPPB1TRIPLO Register............................................................................................
ADCPPB2CONFIG Register ...........................................................................................
ADCPPB2STAMP Register ............................................................................................
ADCPPB2OFFCAL Register ...........................................................................................
ADCPPB2OFFREF Register...........................................................................................
ADCPPB2TRIPHI Register ............................................................................................
ADCPPB2TRIPLO Register............................................................................................
ADCPPB3CONFIG Register ...........................................................................................
ADCPPB3STAMP Register ............................................................................................

10-35. ADCINTSOCSEL1 Register

List of Figures

1453
1458
1462
1466
1469
1472
1475
1478
1481
1484
1487
1490
1493
1496
1499
1502
1505
1508
1511
1514
1516
1518
1520
1522
1523
1524
1525
1527
1528
1529
1530
1531
1532
1534
1535
1536
1537
1538
1539
1541

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

10-78. ADCPPB3OFFCAL Register ........................................................................................... 1542
10-79. ADCPPB3OFFREF Register........................................................................................... 1543
10-80. ADCPPB3TRIPHI Register

............................................................................................

1544

10-81. ADCPPB3TRIPLO Register............................................................................................ 1545
10-82. ADCPPB4CONFIG Register ........................................................................................... 1546
10-83. ADCPPB4STAMP Register ............................................................................................ 1548
10-84. ADCPPB4OFFCAL Register ........................................................................................... 1549
10-85. ADCPPB4OFFREF Register........................................................................................... 1550

............................................................................................
10-87. ADCPPB4TRIPLO Register............................................................................................
10-88. ADCINLTRIM1 Register ................................................................................................
10-89. ADCINLTRIM2 Register ................................................................................................
10-90. ADCINLTRIM3 Register ................................................................................................
10-91. ADCINLTRIM4 Register ................................................................................................
10-92. ADCINLTRIM5 Register ................................................................................................
10-93. ADCINLTRIM6 Register ................................................................................................
10-94. ADCRESULT0 Register ................................................................................................
10-95. ADCRESULT1 Register ................................................................................................
10-96. ADCRESULT2 Register ................................................................................................
10-97. ADCRESULT3 Register ................................................................................................
10-98. ADCRESULT4 Register ................................................................................................
10-99. ADCRESULT5 Register ................................................................................................
10-100. ADCRESULT6 Register ...............................................................................................
10-101. ADCRESULT7 Register ...............................................................................................
10-102. ADCRESULT8 Register ...............................................................................................
10-103. ADCRESULT9 Register ...............................................................................................
10-104. ADCRESULT10 Register .............................................................................................
10-105. ADCRESULT11 Register .............................................................................................
10-106. ADCRESULT12 Register .............................................................................................
10-107. ADCRESULT13 Register .............................................................................................
10-108. ADCRESULT14 Register .............................................................................................
10-109. ADCRESULT15 Register .............................................................................................
10-110. ADCPPB1RESULT Register .........................................................................................
10-111. ADCPPB2RESULT Register .........................................................................................
10-112. ADCPPB3RESULT Register .........................................................................................
10-113. ADCPPB4RESULT Register .........................................................................................
11-1. DAC Module Block Diagram ...........................................................................................
11-2. DACREV Register .......................................................................................................
11-3. DACCTL Register .......................................................................................................
11-4. DACVALA Register .....................................................................................................
11-5. DACVALS Register .....................................................................................................
11-6. DACOUTEN Register ...................................................................................................
11-7. DACLOCK Register .....................................................................................................
11-8. DACTRIM Register ......................................................................................................
12-1. CMPSS Module Block Diagram .......................................................................................
12-2. Comparator Digital Output .............................................................................................
12-3. DAC Reference Select..................................................................................................
12-4. Output Voltage Calculation.............................................................................................
12-5. Ramp Generator .........................................................................................................
10-86. ADCPPB4TRIPHI Register

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

1551
1552
1553
1554
1555
1556
1557
1558
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1582
1585
1586
1587
1588
1589
1590
1591
1593
1594
1594
1594
1595
33

www.ti.com

12-6.

Ramp Generator Behavior ............................................................................................. 1596

12-7.

Digital Filter Behavior ................................................................................................... 1596

12-8.

COMPCTL Register ..................................................................................................... 1601

12-9.

COMPHYSCTL Register ............................................................................................... 1603

12-10. COMPSTS Register..................................................................................................... 1604
12-11. COMPSTSCLR Register ............................................................................................... 1605
12-12. COMPDACCTL Register ............................................................................................... 1606
1608

12-14. DACHVALA Register

1609

12-15.

1610

12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
34

...................................................................................................
...................................................................................................
RAMPMAXREFA Register .............................................................................................
RAMPMAXREFS Register .............................................................................................
RAMPDECVALA Register..............................................................................................
RAMPDECVALS Register..............................................................................................
RAMPSTS Register .....................................................................................................
DACLVALS Register ....................................................................................................
DACLVALA Register ....................................................................................................
RAMPDLYA Register ...................................................................................................
RAMPDLYS Register ...................................................................................................
CTRIPLFILCTL Register ...............................................................................................
CTRIPLFILCLKCTL Register ..........................................................................................
CTRIPHFILCTL Register ...............................................................................................
CTRIPHFILCLKCTL Register ..........................................................................................
COMPLOCK Register ..................................................................................................
Sigma Delta Filter Module (SDFM) CPU Interface .................................................................
Sigma Delta Filter Module (SDFM) Block Diagram .................................................................
Block Diagram of One Filter Module ..................................................................................
Typical PWM Interface to Sigma Delta Filter Module ..............................................................
Operation Diagrams.....................................................................................................
Comparator Filter Resolution ..........................................................................................
Frequency Response of Various Sinc Filters ........................................................................
Data Filter Resolution ...................................................................................................
SDFM Interrupt Unit .....................................................................................................
SDIFLG Register ........................................................................................................
SDIFLGCLR Register ...................................................................................................
SDCTL Register .........................................................................................................
SDMFILEN Register ....................................................................................................
SDCTLPARM1 Register ................................................................................................
SDDFPARM1 Register .................................................................................................
SDDPARM1 Register ...................................................................................................
SDCMPH1 Register .....................................................................................................
SDCMPL1 Register .....................................................................................................
SDCPARM1 Register ...................................................................................................
SDDATA1 Register .....................................................................................................
SDCTLPARM2 Register ................................................................................................
SDDFPARM2 Register .................................................................................................
SDDPARM2 Register ...................................................................................................
SDCMPH2 Register .....................................................................................................
SDCMPL2 Register .....................................................................................................
SDCPARM2 Register ...................................................................................................

12-13. DACHVALS Register

List of Figures

1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1625
1626
1627
1627
1629
1630
1631
1632
1635
1640
1642
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

.....................................................................................................
SDCTLPARM3 Register ................................................................................................
SDDFPARM3 Register .................................................................................................
SDDPARM3 Register ...................................................................................................
SDCMPH3 Register .....................................................................................................
SDCMPL3 Register .....................................................................................................
SDCPARM3 Register ...................................................................................................
SDDATA3 Register .....................................................................................................
SDCTLPARM4 Register ................................................................................................
SDDFPARM4 Register .................................................................................................
SDDPARM4 Register ...................................................................................................
SDCMPH4 Register .....................................................................................................
SDCMPL4 Register .....................................................................................................
SDCPARM4 Register ...................................................................................................
SDDATA4 Register .....................................................................................................
Multiple ePWM Modules................................................................................................
Submodules and Signal Connections for an ePWM Module ......................................................
ePWM Submodules and Critical Internal Signal Interconnects ...................................................
Time-Base Submodule .................................................................................................
Time-Base Submodule Signals and Registers ......................................................................
Time-Base Frequency and Period ....................................................................................
Time-Base Counter Synchronization Scheme .......................................................................
Time-Base Up-Count Mode Waveforms .............................................................................
Time-Base Down-Count Mode Waveforms ..........................................................................
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event ...
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ......
Global Load: Signals and Registers ..................................................................................
Counter-Compare Submodule .........................................................................................
Detailed View of the Counter-Compare Submodule ................................................................
Counter-Compare Event Waveforms in Up-Count Mode ..........................................................
Counter-Compare Events in Down-Count Mode ....................................................................

13-27. SDDATA2 Register
13-28.
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
13-38.
13-39.
13-40.
13-41.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.

1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1678
1679
1681
1684
1685
1687
1689
1691
1692
1692
1693
1694
1695
1696
1699
1700

14-17. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event ................................................................................................. 1701
14-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ..................................................................................................................... 1701
14-19. Action-Qualifier Submodule ............................................................................................ 1702
14-20. Action-Qualifier Submodule Inputs and Outputs .................................................................... 1703

.........................................
AQCTLR[SHDWAQAMODE] .........................................................................................
AQCTLR[SHDWAQBMODE] ..........................................................................................
Up-Down-Count Mode Symmetrical Waveform .....................................................................

14-21. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs

1704

14-22.

1707

14-23.
14-24.

1707
1709

14-25. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................. 1710
14-26. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 1711
14-27. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 1712
14-28. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 1712
14-29. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary .......................................................................................... 1713
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

35

www.ti.com

14-30. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................ 1713

.....................................
Dead_Band Submodule ................................................................................................
Configuration Options for the Dead-Band Submodule .............................................................
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)..................................................
PWM Chopper Submodule.............................................................................................
PWM Chopper Submodule Operational Details .....................................................................
Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only ...............................
PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ......

14-31. Up-Down-Count, PWM Waveform Generation Utilizing T1 and T2 Events
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.

1714
1714
1717
1719
1721
1722
1722
1723

14-39. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 1724
14-40. Trip-Zone Submodule ................................................................................................... 1725
14-41. Trip-Zone Submodule Mode Control Logic .......................................................................... 1729
14-42. Trip-Zone Submodule Interrupt Logic................................................................................. 1730
14-43. Event-Trigger Submodule .............................................................................................. 1731
14-44. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 1732
14-45. Event-Trigger Interrupt Generator ..................................................................................... 1734
1735

14-47. Event-Trigger SOCB Pulse Generator

1735

14-48.

1736

14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
36

...............................................................................
...............................................................................
Digital-Compare Submodule High-Level Block Diagram ...........................................................
ePWM Trip Input Connectivity .........................................................................................
DCAEVT1 Event Triggering ............................................................................................
DCAEVT2 Event Triggering ............................................................................................
DCBEVT1 Event Triggering ............................................................................................
DCBEVT2 Event Triggering ............................................................................................
Event Filtering ...........................................................................................................
Blanking Window Timing Diagram ....................................................................................
Valley Switching .........................................................................................................
EPWM X-BAR ...........................................................................................................
Simplified ePWM Module...............................................................................................
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .....................................
Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ..................................................
Buck Waveforms for (Note: Only three bucks shown here) .......................................................
Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1) ............................................................
Buck Waveforms for (Note: FPWM2 = FPWM1))...........................................................................
Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1) ..........................................................
Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ) ..........................................................
3-Phase Inverter Waveforms (Only One Inverter Shown) .........................................................
Configuring Two PWM Modules for Phase Control .................................................................
Timing Waveforms Associated With Phase Control Between Two Modules ....................................
Control of a 3-Phase Interleaved DC/DC Converter ................................................................
3-Phase Interleaved DC/DC Converter Waveforms for ...........................................................
Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ...................................................................
ZVS Full-H Bridge Waveforms ........................................................................................
Peak Current Mode Control of a Buck Converter ...................................................................
Peak Current Mode Control Waveforms for .........................................................................
Control of Two Resonant Converter Stages .........................................................................
H-Bridge LLC Resonant Converter PWM Waveforms..............................................................

14-46. Event-Trigger SOCA Pulse Generator

List of Figures

1737
1740
1740
1741
1741
1742
1742
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1760
1761
1761
1762

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

.........................................................................................................
14-78. TBCTL2 Register ........................................................................................................
14-79. EPWMSYNCINSEL Register ..........................................................................................
14-80. TBCTR Register .........................................................................................................
14-81. TBSTS Register .........................................................................................................
14-82. EPWMSYNCOUTEN Register.........................................................................................
14-83. CMPCTL Register .......................................................................................................
14-84. CMPCTL2 Register .....................................................................................................
14-85. DBCTL Register .........................................................................................................
14-86. DBCTL2 Register........................................................................................................
14-87. AQCTL Register .........................................................................................................
14-88. AQTSRCSEL Register..................................................................................................
14-89. PCCTL Register .........................................................................................................
14-90. VCAPCTL Register .....................................................................................................
14-91. VCNTCFG Register .....................................................................................................
14-92. HRCNFG Register ......................................................................................................
14-93. HRPWR Register ........................................................................................................
14-94. HRMSTEP Register .....................................................................................................
14-95. HRCNFG2 Register .....................................................................................................
14-96. HRPCTL Register .......................................................................................................
14-97. TRREM Register ........................................................................................................
14-98. GLDCTL Register .......................................................................................................
14-99. GLDCFG Register .......................................................................................................
14-100. EPWMXLINK Register ................................................................................................
14-101. EPWMREV Register ...................................................................................................
14-102. AQCTLA Register ......................................................................................................
14-103. AQCTLA2 Register ....................................................................................................
14-104. AQCTLB Register ......................................................................................................
14-105. AQCTLB2 Register ....................................................................................................
14-106. AQSFRC Register .....................................................................................................
14-107. AQCSFRC Register ...................................................................................................
14-108. DBREDHR Register ...................................................................................................
14-109. DBRED Register .......................................................................................................
14-110. DBFEDHR Register ...................................................................................................
14-111. DBFED Register .......................................................................................................
14-112. TBPHS Register........................................................................................................
14-113. TBPRDHR Register ...................................................................................................
14-114. TBPRD Register .......................................................................................................
14-115. CMPA Register .........................................................................................................
14-116. CMPB Register .........................................................................................................
14-117. CMPC Register .........................................................................................................
14-118. CMPD Register .........................................................................................................
14-119. GLDCTL2 Register ....................................................................................................
14-120. SWVDELVAL Register ................................................................................................
14-121. TZSEL Register ........................................................................................................
14-122. TZDCSEL Register ....................................................................................................
14-123. TZCTL Register ........................................................................................................
14-124. TZCTL2 Register .......................................................................................................
14-125. TZCTLDCA Register ..................................................................................................
14-77. TBCTL Register

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

1767
1770
1771
1772
1773
1774
1776
1778
1780
1783
1784
1786
1787
1789
1791
1793
1795
1796
1797
1798
1800
1801
1803
1805
1809
1810
1812
1814
1816
1818
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1836
1838
1840
1842
37

www.ti.com

1844

14-127.

1846

14-128.
14-129.
14-130.
14-131.
14-132.
14-133.
14-134.
14-135.
14-136.
14-137.
14-138.
14-139.
14-140.
14-141.
14-142.
14-143.
14-144.
14-145.
14-146.
14-147.
14-148.
14-149.
14-150.
14-151.
14-152.
14-153.
14-154.
14-155.
14-156.
14-157.
14-158.
14-159.
14-160.
14-161.
14-162.
14-163.
14-164.
14-165.
14-166.
14-167.
14-168.
14-169.
14-170.
14-171.
14-172.
14-173.
14-174.
38

..................................................................................................
TZEINT Register .......................................................................................................
TZFLG Register ........................................................................................................
TZCBCFLG Register ..................................................................................................
TZOSTFLG Register ..................................................................................................
TZCLR Register ........................................................................................................
TZCBCCLR Register ..................................................................................................
TZOSTCLR Register ..................................................................................................
TZFRC Register ........................................................................................................
ETSEL Register ........................................................................................................
ETPS Register .........................................................................................................
ETFLG Register ........................................................................................................
ETCLR Register ........................................................................................................
ETFRC Register........................................................................................................
ETINTPS Register .....................................................................................................
ETSOCPS Register ....................................................................................................
ETCNTINITCTL Register .............................................................................................
ETCNTINIT Register ..................................................................................................
DCTRIPSEL Register .................................................................................................
DCACTL Register ......................................................................................................
DCBCTL Register ......................................................................................................
DCFCTL Register ......................................................................................................
DCCAPCTL Register ..................................................................................................
DCFOFFSET Register ................................................................................................
DCFOFFSETCNT Register ...........................................................................................
DCFWINDOW Register ...............................................................................................
DCFWINDOWCNT Register ..........................................................................................
DCCAP Register .......................................................................................................
DCAHTRIPSEL Register ..............................................................................................
DCALTRIPSEL Register ..............................................................................................
DCBHTRIPSEL Register ..............................................................................................
DCBLTRIPSEL Register ..............................................................................................
EPWMLOCK Register .................................................................................................
HWVDELVAL Register ................................................................................................
VCNTVAL Register ....................................................................................................
TRIP4MUX0TO15CFG Register .....................................................................................
TRIP4MUX16TO31CFG Register ...................................................................................
TRIP5MUX0TO15CFG Register .....................................................................................
TRIP5MUX16TO31CFG Register ...................................................................................
TRIP7MUX0TO15CFG Register .....................................................................................
TRIP7MUX16TO31CFG Register ...................................................................................
TRIP8MUX0TO15CFG Register .....................................................................................
TRIP8MUX16TO31CFG Register ...................................................................................
TRIP9MUX0TO15CFG Register .....................................................................................
TRIP9MUX16TO31CFG Register ...................................................................................
TRIP10MUX0TO15CFG Register ...................................................................................
TRIP10MUX16TO31CFG Register ..................................................................................
TRIP11MUX0TO15CFG Register ...................................................................................
TRIP11MUX16TO31CFG Register ..................................................................................

14-126. TZCTLDCB Register

List of Figures

1847
1849
1851
1853
1855
1857
1859
1860
1863
1866
1867
1868
1869
1870
1872
1873
1874
1876
1878
1880
1881
1883
1884
1885
1886
1887
1888
1890
1892
1894
1896
1898
1899
1902
1905
1908
1911
1914
1917
1920
1923
1926
1929
1932
1935
1938
1941

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

...................................................................................
14-176. TRIP12MUX16TO31CFG Register ..................................................................................
14-177. TRIP4MUXENABLE Register ........................................................................................
14-178. TRIP5MUXENABLE Register ........................................................................................
14-179. TRIP7MUXENABLE Register ........................................................................................
14-180. TRIP8MUXENABLE Register ........................................................................................
14-181. TRIP9MUXENABLE Register ........................................................................................
14-182. TRIP10MUXENABLE Register .......................................................................................
14-183. TRIP11MUXENABLE Register .......................................................................................
14-184. TRIP12MUXENABLE Register .......................................................................................
14-185. TRIPOUTINV Register ................................................................................................
14-186. TRIPLOCK Register ...................................................................................................
14-187. SYNCSELECT Register...............................................................................................
14-188. ADCSOCOUTSELECT Register .....................................................................................
14-189. SYNCSOCLOCK Register ............................................................................................
15-1. Resolution Calculations for Conventionally Generated PWM .....................................................
15-2. Operating Logic Using MEP ...........................................................................................
15-3. HRPWM Extension Registers and Memory Configuration .........................................................
15-4. HRPWM System Interface .............................................................................................
15-5. HRPWM Block Diagram ................................................................................................
15-6. Required PWM Waveform for a Requested Duty = 40.5% ........................................................
15-7. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) ...........................................
15-8. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) ..........................................
15-9. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) .........................................
15-10. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) ..................................
15-11. Simple Buck Controlled Converter Using a Single PWM ..........................................................
15-12. PWM Waveform Generated for Simple Buck Controlled Converter ..............................................
15-13. Simple Reconstruction Filter for a PWM-based DAC ..............................................................
15-14. PWM Waveform Generated for the PWM DAC Function ..........................................................
16-1. Capture and APWM Modes of Operation ............................................................................
16-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode ......................................
16-3. Capture Function Diagram .............................................................................................
16-4. Event Prescale Control .................................................................................................
16-5. Prescale Function Waveforms .........................................................................................
16-6. Details of the Continuous/One-shot Block ...........................................................................
16-7. Details of the Counter and Synchronization Block ..................................................................
16-8. Time-Base Counter Synchronization Scheme 4 ....................................................................
16-9. Interrupts in eCAP Module .............................................................................................
16-10. PWM Waveform Details Of APWM Mode Operation ...............................................................
16-11. Time-Base Frequency and Period Calculation ......................................................................
16-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect...........................................
16-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect ............................
16-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect .......................................
16-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect ........................
16-16. PWM Waveform Details of APWM Mode Operation................................................................
16-17. TSCTR Register .........................................................................................................
16-18. CTRPHS Register .......................................................................................................
16-19. CAP1 Register ...........................................................................................................
16-20. CAP2 Register ...........................................................................................................
14-175. TRIP12MUX0TO15CFG Register

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

1944
1947
1950
1955
1960
1965
1970
1975
1980
1985
1990
1992
1994
1997
2000
2002
2004
2005
2006
2007
2009
2012
2014
2014
2015
2020
2020
2022
2022
2030
2031
2032
2033
2033
2034
2035
2036
2037
2038
2039
2040
2042
2044
2046
2048
2052
2053
2054
2055
39

www.ti.com

16-21. CAP3 Register ........................................................................................................... 2056
16-22. CAP4 Register ........................................................................................................... 2057
16-23. ECCTL1 Register........................................................................................................ 2058
16-24. ECCTL2 Register........................................................................................................ 2060
16-25. ECEINT Register ........................................................................................................ 2062
16-26. ECFLG Register ......................................................................................................... 2064
16-27. ECCLR Register ......................................................................................................... 2066
16-28. ECFRC Register ......................................................................................................... 2067
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
17-32.
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
17-41.
40

...................................................................................................
QEP Encoder Output Signal for Forward/Reverse Movement ....................................................
Index Pulse Example ...................................................................................................
Functional Block Diagram of the eQEP Peripheral .................................................................
Functional Block Diagram of Decoder Unit ..........................................................................
Quadrature Decoder State Machine ..................................................................................
Quadrature-clock and Direction Decoding ...........................................................................
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F) ..............
Position Counter Underflow/Overflow (QPOSMAX = 4) ...........................................................
Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) ...............................................
Strobe Event Latch (QEPCTL[SEL] = 1) .............................................................................
eQEP Position-compare Unit ..........................................................................................
eQEP Position-compare Event Generation Points ..................................................................
eQEP Position-compare Sync Output Pulse Stretcher .............................................................
eQEP Edge Capture Unit ..............................................................................................
Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) .................................
eQEP Edge Capture Unit - Timing Details ...........................................................................
eQEP Watchdog Timer .................................................................................................
eQEP Unit Time Base ..................................................................................................
EQEP Interrupt Generation ............................................................................................
QPOSCNT Register.....................................................................................................
QPOSINIT Register .....................................................................................................
QPOSMAX Register ....................................................................................................
QPOSCMP Register ....................................................................................................
QPOSILAT Register ....................................................................................................
QPOSSLAT Register ...................................................................................................
QPOSLAT Register .....................................................................................................
QUTMR Register ........................................................................................................
QUPRD Register ........................................................................................................
QWDTMR Register .....................................................................................................
QWDPRD Register ......................................................................................................
QDECCTL Register .....................................................................................................
QEPCTL Register .......................................................................................................
QCAPCTL Register .....................................................................................................
QPOSCTL Register .....................................................................................................
QEINT Register ..........................................................................................................
QFLG Register...........................................................................................................
QCLR Register ..........................................................................................................
QFRC Register ..........................................................................................................
QEPSTS Register .......................................................................................................
QCTMR Register ........................................................................................................
Optical Encoder Disk

List of Figures

2069
2069
2070
2072
2074
2075
2076
2078
2079
2080
2081
2082
2083
2083
2085
2085
2086
2087
2088
2088
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2105
2108
2109
2110
2112
2114
2116
2118
2120

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

17-42. QCPRD Register ........................................................................................................ 2121
17-43. QCTMRLAT Register ................................................................................................... 2122
17-44. QCPRDLAT Register ................................................................................................... 2123
18-1.

SPI CPU Interface ....................................................................................................... 2126

18-2.

SPI Interrupt Flags and Enable Logic Generation .................................................................. 2129

18-3.

SPI DMA Trigger Diagram ............................................................................................. 2130

18-4.

SPI Master/Slave Connection

18-5.

SPI Module Master Configuration ..................................................................................... 2132

18-6.

SPI Module Slave Configuration

18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.

.........................................................................................

......................................................................................
SPICLK Signal Options .................................................................................................
SPI: SPICLK-LSPCLK Characteristic When (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1 .........
SPI 3-wire Master Mode ................................................................................................
SPI 3-wire Slave Mode .................................................................................................
Five Bits per Character .................................................................................................
SPI Digital Audio Receiver Configuration Using 2 SPIs............................................................
Standard Right-Justified Digital Audio Data Format ................................................................
SPICCR Register ........................................................................................................
SPICTL Register ........................................................................................................
SPISTS Register ........................................................................................................
SPIBRR Register ........................................................................................................
SPIRXEMU Register ....................................................................................................
SPIRXBUF Register ....................................................................................................
SPITXBUF Register .....................................................................................................
SPIDAT Register ........................................................................................................
SPIFFTX Register .......................................................................................................
SPIFFRX Register.......................................................................................................
SPIFFCT Register .......................................................................................................
SPIPRI Register .........................................................................................................
SCI CPU Interface ......................................................................................................
Serial Communications Interface (SCI) Module Block Diagram ..................................................
Typical SCI Data Frame Formats .....................................................................................
Idle-Line Multiprocessor Communication Format ...................................................................
Double-Buffered WUT and TXSHF ...................................................................................
Address-Bit Multiprocessor Communication Format................................................................
SCI Asynchronous Communications Format ........................................................................
SCI RX Signals in Communication Modes ...........................................................................
SCI TX Signals in Communications Mode ...........................................................................
SCI FIFO Interrupt Flags and Enable Logic .........................................................................
SCICCR Register........................................................................................................
SCICTL1 Register .......................................................................................................
SCIHBAUD Register ....................................................................................................
SCILBAUD Register ....................................................................................................
SCICTL2 Register .......................................................................................................
SCIRXST Register ......................................................................................................
SCIRXEMU Register ....................................................................................................
SCIRXBUF Register ....................................................................................................
SCITXBUF Register.....................................................................................................
SCIFFTX Register .......................................................................................................
SCIFFRX Register ......................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

2131
2133
2136
2136
2139
2139
2142
2143
2143
2146
2148
2150
2152
2153
2154
2155
2156
2157
2159
2161
2162
2165
2166
2168
2170
2170
2172
2172
2173
2173
2176
2180
2182
2184
2185
2186
2188
2190
2191
2192
2193
2195
41

www.ti.com

19-22. SCIFFCT Register....................................................................................................... 2197
19-23. SCIPRI Register ......................................................................................................... 2198
20-1.

Multiple I2C Modules Connected ...................................................................................... 2200

20-2.

I2C Module Conceptual Block Diagram .............................................................................. 2202

20-3.

Clocking Diagram for the I2C Module ................................................................................ 2202

20-4.

The Roles of the Clock Divide-Down Values (ICCL and ICCH) ................................................... 2203

20-5.

Bit Transfer on the I2C-Bus ............................................................................................ 2204

20-6.

I2C Module START and STOP Conditions .......................................................................... 2206

20-7.

I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown) ........................... 2206

20-8.

I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR)

20-9.

I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR) ........................................... 2207

............................................

2206

20-10. I2C Module Free Data Format (FDF = 1 in I2CMDR) .............................................................. 2207
20-11. Repeated START Condition (in This Case, 7-Bit Addressing Format) ........................................... 2208
20-12. Synchronization of Two I2C Clock Generators During Arbitration ................................................ 2209
20-13. Arbitration Procedure Between Two Master-Transmitters ......................................................... 2210
20-14. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ..................................... 2210
20-15. Enable Paths of the I2C Interrupt Requests ......................................................................... 2212
20-16. I2COAR Register ........................................................................................................ 2216
20-17. I2CIER Register ......................................................................................................... 2217
20-18. I2CSTR Register

........................................................................................................

2218

20-19. I2CCLKL Register ....................................................................................................... 2223
20-20. I2CCLKH Register....................................................................................................... 2224
20-21. I2CCNT Register ........................................................................................................ 2225
20-22. I2CDRR Register ........................................................................................................ 2226
20-23. I2CSAR Register ........................................................................................................ 2227
20-24. I2CDXR Register ........................................................................................................ 2228
20-25. I2CMDR Register........................................................................................................ 2229
20-26. I2CISRC Register ....................................................................................................... 2233
20-27. I2CEMDR Register ...................................................................................................... 2234
20-28. I2CPSC Register ........................................................................................................ 2235
20-29. I2CFFTX Register ....................................................................................................... 2236
20-30. I2CFFRX Register ....................................................................................................... 2238
21-1.

Conceptual Block Diagram of the McBSP ........................................................................... 2242

21-2.

McBSP Data Transfer Paths ........................................................................................... 2243

21-3.

Companding Processes ................................................................................................ 2244

21-4.

μ-Law Transmit Data Companding Format .......................................................................... 2244

21-5.

A-Law Transmit Data Companding Format .......................................................................... 2244

21-6.

Two Methods by Which the McBSP Can Compand Internal Data ................................................ 2245

21-7.

Example - Clock Signal Control of Bit Transfer Timing

21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
42

............................................................
McBSP Operating at Maximum Packet Frequency .................................................................
Single-Phase Frame for a McBSP Data Transfer ...................................................................
Dual-Phase Frame for a McBSP Data Transfer .....................................................................
Implementing the AC97 Standard With a Dual-Phase Frame .....................................................
Timing of an AC97-Standard Data Transfer Near Frame Synchronization ......................................
McBSP Reception Physical Data Path ...............................................................................
McBSP Reception Signal Activity .....................................................................................
McBSP Transmission Physical Data Path ...........................................................................
McBSP Transmission Signal Activity .................................................................................
Conceptual Block Diagram of the Sample Rate Generator ........................................................

List of Figures

2245
2247
2248
2249
2249
2250
2250
2250
2251
2251
2253

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

............................................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ...........................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ...........................
Overrun in the McBSP Receiver ......................................................................................
Overrun Prevented in the McBSP Receiver .........................................................................
Possible Responses to Receive Frame-Synchronization Pulses .................................................
An Unexpected Frame-Synchronization Pulse During a McBSP Reception ....................................
Proper Positioning of Frame-Synchronization Pulses ..............................................................
Data in the McBSP Transmitter Overwritten and Thus Not Transmitted.........................................
Underflow During McBSP Transmission .............................................................................
Underflow Prevented in the McBSP Transmitter ....................................................................
Possible Responses to Transmit Frame-Synchronization Pulses ................................................
An Unexpected Frame-Synchronization Pulse During a McBSP Transmission ................................
Proper Positioning of Frame-Synchronization Pulses ..............................................................
Alternating Between the Channels of Partition A and the Channels of Partition B .............................
Reassigning Channel Blocks Throughout a McBSP Data Transfer ..............................................
McBSP Data Transfer in the 8-Partition Mode ......................................................................
Activity on McBSP Pins for the Possible Values of XMCM ........................................................
Typical SPI Interface ....................................................................................................
SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 0, and CLKRP = 0 ...........................
SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1 .....................................
SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0 ...........................
SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1 .....................................
SPI Interface with McBSP Used as Master ..........................................................................
SPI Interface With McBSP Used as Slave ...........................................................................
Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0 ....................................................
Unexpected Frame-Synchronization Pulse With (R/X)FIG = 1 ....................................................
Companding Processes for Reception and for Transmission ....................................................
Range of Programmable Data Delay .................................................................................
2-Bit Data Delay Used to Skip a Framing Bit ........................................................................
Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge ..
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods .......................................
Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge ..
Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0 ...................................................
Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1 ...................................................
Companding Processes for Reception and for Transmission .....................................................
μ-Law Transmit Data Companding Format ..........................................................................
A-Law Transmit Data Companding Format ..........................................................................
Range of Programmable Data Delay .................................................................................
2-Bit Data Delay Used to Skip a Framing Bit ........................................................................
Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge ..
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods .......................................
Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge ..
Four 8-Bit Data Words Transferred To/From the McBSP ..........................................................
One 32-Bit Data Word Transferred To/From the McBSP ..........................................................
8-Bit Data Words Transferred at Maximum Packet Frequency ...................................................
Configuring the Data Stream of as a Continuous 32-Bit Word ....................................................
Receive Interrupt Generation ..........................................................................................
Transmit Interrupt Generation .........................................................................................

21-18. Possible Inputs to the Sample Rate Generator and the Polarity Bits

2255

21-19.

2257

21-20.
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
21-54.
21-55.
21-56.
21-57.
21-58.
21-59.
21-60.
21-61.
21-62.
21-63.
21-64.
21-65.
21-66.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

2258
2260
2261
2261
2262
2263
2263
2264
2265
2265
2266
2267
2269
2270
2271
2274
2275
2277
2277
2277
2277
2279
2280
2287
2287
2288
2289
2289
2294
2295
2297
2307
2307
2308
2308
2309
2310
2310
2314
2314
2316
2320
2320
2321
2321
2322
2322
43

www.ti.com

21-67. Data Receive Registers (DRR2 and DRR1) ......................................................................... 2326
2326

21-69. Serial Port Control 1 Register (SPCR1)

2327

21-70.

2330

21-71.
21-72.
21-73.
21-74.
21-75.
21-76.
21-77.
21-78.
21-79.
21-80.
21-81.
21-82.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
44

........................................................................
.............................................................................
Serial Port Control 2 Register (SPCR2) .............................................................................
Receive Control Register 1 (RCR1) ..................................................................................
Receive Control Register 2 (RCR2) ..................................................................................
Transmit Control 1 Register (XCR1) ..................................................................................
Transmit Control 2 Register (XCR2) .................................................................................
Sample Rate Generator 1 Register (SRGR1) .......................................................................
Sample Rate Generator 2 Register (SRGR2) .......................................................................
Multichannel Control 1 Register (MCR1) ............................................................................
Multichannel Control 2 Register (MCR2) .............................................................................
Pin Control Register (PCR) ...........................................................................................
Receive Channel Enable Registers (RCERA...RCERH) ...........................................................
Transmit Channel Enable Registers (XCERA...XCERH) ..........................................................
McBSP Interrupt Enable Register (MFFINT) ........................................................................
CAN Block Diagram .....................................................................................................
CAN Core in Silent Mode ..............................................................................................
CAN Core in Loopback Mode .........................................................................................
CAN Core in External Loopback Mode ...............................................................................
CAN Core in Loopback Combined with Silent Mode ...............................................................
Initialization of a Transmit Object .....................................................................................
Initialization of a single Receive Object for Data Frames ..........................................................
Initialization of a single Receive Object for Remote Frames ......................................................
CPU Handling of a FIFO Buffer (Interrupt Driven) ..................................................................
Bit Timing .................................................................................................................
The Propagation Time Segment ......................................................................................
Synchronization on Late and Early Edges ...........................................................................
Filtering of Short Dominant Spikes ....................................................................................
Structure of the CAN Core's CAN Protocol Controller .............................................................
Data Transfer Between IF1 / IF2 Registers and Message RAM ..................................................
Structure of a Message Object ........................................................................................
Message RAM Representation in Debug Mode .....................................................................
CAN_CTL Register ......................................................................................................
CAN_ES Register .......................................................................................................
CAN_ERRC Register ...................................................................................................
CAN_BTR Register .....................................................................................................
CAN_INT Register ......................................................................................................
CAN_TEST Register ....................................................................................................
CAN_PERR Register ...................................................................................................
CAN_RAM_INIT Register ..............................................................................................
CAN_GLB_INT_EN Register ..........................................................................................
CAN_GLB_INT_FLG Register .........................................................................................
CAN_GLB_INT_CLR Register.........................................................................................
CAN_ABOTR Register .................................................................................................
CAN_TXRQ_X Register ................................................................................................
CAN_TXRQ_21 Register ...............................................................................................
CAN_NDAT_X Register ................................................................................................
CAN_NDAT_21 Register ...............................................................................................

21-68. Data Transmit Registers (DXR2 and DXR1)

List of Figures

2332
2333
2335
2336
2338
2338
2340
2342
2344
2346
2348
2350
2353
2357
2358
2359
2359
2362
2363
2363
2368
2369
2370
2372
2373
2374
2377
2378
2382
2386
2389
2391
2392
2394
2395
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

22-34. CAN_IPEN_X Register ................................................................................................. 2407
22-35. CAN_IPEN_21 Register ................................................................................................ 2408
22-36. CAN_MVAL_X Register ................................................................................................ 2409
22-37. CAN_MVAL_21 Register ............................................................................................... 2410
22-38. CAN_IP_MUX21 Register .............................................................................................. 2411
22-39. CAN_IF1CMD Register ................................................................................................. 2412
22-40. CAN_IF1MSK Register ................................................................................................. 2416
22-41. CAN_IF1ARB Register ................................................................................................. 2417

...............................................................................................
CAN_IF1DATA Register ................................................................................................
CAN_IF1DATB Register ................................................................................................
CAN_IF2CMD Register .................................................................................................
CAN_IF2MSK Register .................................................................................................
CAN_IF2ARB Register .................................................................................................
CAN_IF2MCTL Register ...............................................................................................
CAN_IF2DATA Register ................................................................................................
CAN_IF2DATB Register ................................................................................................
CAN_IF3OBS Register .................................................................................................
CAN_IF3MSK Register .................................................................................................
CAN_IF3ARB Register .................................................................................................
CAN_IF3MCTL Register ...............................................................................................
CAN_IF3DATA Register ................................................................................................
CAN_IF3DATB Register ................................................................................................
CAN_IF3UPD Register .................................................................................................
USB Block Diagram .....................................................................................................
USB Scheme.............................................................................................................
Function Address Register (USBFADDR) ...........................................................................
Power Management Register (USBPOWER) in Host Mode.......................................................
Power Management Register (USBPOWER) in Device Mode ....................................................
USB Transmit Interrupt Status Register (USBTXIS) ................................................................
USB Transmit Interrupt Status Register (USBRXIS) ...............................................................
USB Transmit Interrupt Status Enable Register (USBTXIE) ......................................................
USB Transmit Interrupt Status Enable Register (USBRXIE) ......................................................
USB General Interrupt Status Register (USBIS) in Host Mode ...................................................
USB General Interrupt Status Register (USBIS) in Device Mode ................................................
USB Interrupt Enable Register (USBIE) in Host Mode .............................................................
USB Interrupt Enable Register (USBIE) in Device Mode ..........................................................
Frame Number Register (FRAME) ....................................................................................
USB Endpoint Index Register (USBEPIDX) .........................................................................
USB Test Mode Register (USBTEST) in Host Mode ...............................................................
USB Test Mode Register (USBTEST) in Device Mode ............................................................
USB FIFO Endpoint n Register (USBFIFO[n]) ......................................................................
USB Device Control Register (USBDEVCTL) .......................................................................
USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) .................................................
USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) ..................................................
USB Transmit FIFO Start Address Register (USBTXFIFOADDR]) ...............................................
USB Receive FIFO Start Address Register (USBRXFIFOADDR) ................................................
USB Connect Timing Register (USBCONTIM) ......................................................................
USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) ...........................

22-42. CAN_IF1MCTL Register

2419

22-43.

2422

22-44.
22-45.
22-46.
22-47.
22-48.
22-49.
22-50.
22-51.
22-52.
22-53.
22-54.
22-55.
22-56.
22-57.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

2423
2424
2428
2429
2431
2434
2435
2436
2438
2439
2440
2442
2443
2444
2446
2447
2473
2474
2474
2476
2478
2480
2482
2484
2485
2486
2487
2488
2488
2489
2489
2491
2492
2494
2495
2496
2497
2498
2499
45

www.ti.com

23-26. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) ........................... 2499
23-27. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) ............................ 2500
23-28. USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[n])...................................... 2501
23-29. USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[n]) ........................................... 2502
23-30. USB Receive Functional Address Endpoint n Registers (USBFIFO[n])

.........................................

2503

23-31. USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[n]) ...................................... 2504
23-32. USB Transmit Hub Port Endpoint n Registers (USBRXHUBPORT[n])

..........................................

2505

23-33. USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[n]) ......................................... 2506
23-34. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Host Mode ................................ 2507
23-35. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode ............................. 2508
23-36. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode ............................... 2509
23-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode ............................ 2509
23-38. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0)................................................... 2510
23-39. USB Type Endpoint 0 Register (USBTYPE0) ....................................................................... 2510
23-40. USB NAK Limit Register (USBNAKLMT)

............................................................................

2511

23-41. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode ................ 2512
23-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode ............. 2513
23-43. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode ............... 2515
23-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode ............ 2516
23-45. USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[n]) ......................................... 2517
23-46. USB Receive Control and Status Endpoint n Low Register (USBCSRL[n]) in Host Mode .................... 2518
23-47. USB Control and Status Endpoint n Low Register (USBCSRL[n]) in Device Mode ............................ 2519
23-48. USB Receive Control and Status Endpoint n High Register (USBCSRH[n]) in Host Mode ................... 2520
23-49. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Device Mode ........................... 2521
23-50. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n]) ....................................... 2522
23-51. USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[n]) .................................... 2523
2524

23-53. USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[n])

2525

23-54.

2526

23-55.
23-56.
23-57.
23-58.
23-59.
23-60.
23-61.
23-62.
23-63.
23-64.
23-65.
23-66.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
46

.......................................
....................................
USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[n]) ...............................
USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) ..............
USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) .................................
USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) ................................
USB External Power Control Register (USBEPC) ..................................................................
USB External Power Control Raw Interrupt Status Register (USBEPCRIS) ....................................
USB External Power Control Interrupt Mask Register (USBEPCIM) .............................................
USB External Power Control Interrupt Status and Clear Register (USBEPCISC) ..............................
USB Device RESUME Raw Interrupt Status Register (USBDRRIS) .............................................
USB Device RESUME Raw Interrupt Status Register (USBDRRIS) .............................................
USB Device RESUME Interrupt Status and Clear Register (USBDRISC).......................................
USB General-Purpose Control and Status Register (USBGPCS) ................................................
USB DMA Select Register (USBDMASEL) ..........................................................................
uPP Integration ..........................................................................................................
Functional Block Diagram ..............................................................................................
RX in SDR or DDR (non-demux) Mode ..............................................................................
RX in DDR (demux) Mode .............................................................................................
TX in SDR (non-interleave) or DDR (non-demux) Mode ...........................................................
TX in SDR (interleave) or DDR (demux) Mode .....................................................................
IO Output Clock Generation for TX Mode............................................................................
IO Input clock for RX Mode ............................................................................................

23-52. USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[n])

List of Figures

2527
2528
2530
2531
2533
2534
2535
2536
2537
2538
2539
2540
2543
2544
2545
2545
2545
2545
2546
2546

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

24-9.

Structure of DMA Window and Lines in Memory.................................................................... 2548

24-10. uPP Receive in SDR Mode ............................................................................................ 2550
24-11. uPP Transmit in SDR Mode

...........................................................................................

2551

24-12. uPP Transmit in SDR Mode – Interleaving .......................................................................... 2551
24-13. uPP Receive DDR Case

...............................................................................................

2551

24-14. uPP Transmit DDR Case ............................................................................................... 2551
24-15. uPP Tx Data Pattern in Non-Interleaved Mode

.....................................................................

2552

24-16. uPP Rx Data Pattern in Non-Interleaved Mode ..................................................................... 2552

.............................................................................................................
PERCTL Register .......................................................................................................
CHCTL Register .........................................................................................................
IFCFG Register ..........................................................................................................
IFIVAL Register ..........................................................................................................
THCFG Register .........................................................................................................
RAWINTST Register ....................................................................................................
ENINTST Register ......................................................................................................
INTENSET Register.....................................................................................................
INTENCLR Register ....................................................................................................
CHIDESC0 Register ....................................................................................................
CHIDESC1 Register ....................................................................................................
CHIDESC2 Register ....................................................................................................
CHIST0 Register ........................................................................................................
CHIST1 Register ........................................................................................................
CHIST2 Register ........................................................................................................
CHQDESC0 Register ...................................................................................................
CHQDESC1 Register ...................................................................................................
CHQDESC2 Register ...................................................................................................
CHQST0 Register .......................................................................................................
CHQST1 Register .......................................................................................................
CHQST2 Register .......................................................................................................
GINTEN Register ........................................................................................................
GINTFLG Register ......................................................................................................
GINTCLR Register ......................................................................................................
DLYCTL Register........................................................................................................
EMIF Module Overview .................................................................................................
EMIF Functional Block Diagram .......................................................................................
Timing Waveform of SDRAM PRE Command ......................................................................
EMIF to 2M × 16 × 4 bank SDRAM Interface .......................................................................
EMIF to 512K × 16 × 2 bank SDRAM Interface .....................................................................
Timing Waveform for Basic SDRAM Read Operation ..............................................................
Timing Waveform for Basic SDRAM Write Operation ..............................................................
EMIF Asynchronous Interface .........................................................................................
EMIF to 8-bit/16-bit Memory Interface ................................................................................
Common Asynchronous Interface .....................................................................................
Timing Waveform of an Asynchronous Read Cycle in Normal Mode ............................................
Timing Waveform of an Asynchronous Write Cycle in Normal Mode ............................................
Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ....................................
Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode .....................................
Example Configuration Interface ......................................................................................

24-17. PID Register

2560

24-18.

2561

24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Figures

2563
2564
2566
2567
2569
2571
2573
2575
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2594
2596
2599
2600
2600
2608
2609
2611
2612
2612
2616
2618
2620
2622
2629
47

www.ti.com

25-16. SDRAM Timing Register (SDRAM_TR) .............................................................................. 2630
25-17. SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) .................................................. 2631
25-18. SDRAM Refresh Control Register (SDRAM_RCR) ................................................................. 2632
25-19. SDRAM Configuration Register (SDRAM_CR)...................................................................... 2632
25-20. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms ........................................................ 2633
25-21. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms ........................................................ 2634
25-22. Asynchronous m Configuration Register (m = 1, 2) (ASYNC_CSn_CR(n = 2, 3)) ............................. 2635
25-23. RCSR Register .......................................................................................................... 2638
25-24. ASYNC_WCCR Register ............................................................................................... 2639
25-25. SDRAM_CR Register ................................................................................................... 2640
25-26. SDRAM_RCR Register ................................................................................................. 2642
2643

25-28. ASYNC_CS3_CR Register

2645

25-29.

2647

25-30.
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
25-43.
25-44.

48

............................................................................................
............................................................................................
ASYNC_CS4_CR Register ............................................................................................
SDRAM_TR Register ...................................................................................................
TOTAL_SDRAM_AR Register .........................................................................................
TOTAL_SDRAM_ACTR Register .....................................................................................
SDR_EXT_TMNG Register ............................................................................................
INT_RAW Register ......................................................................................................
INT_MSK Register ......................................................................................................
INT_MSK_SET Register ...............................................................................................
INT_MSK_CLR Register ...............................................................................................
EMIF1LOCK Register ...................................................................................................
EMIF1COMMIT Register ...............................................................................................
EMIF1MSEL Register ...................................................................................................
EMIF1ACCPROT0 Register ...........................................................................................
EMIF2LOCK Register ...................................................................................................
EMIF2COMMIT Register ...............................................................................................
EMIF2ACCPROT0 Register ...........................................................................................

25-27. ASYNC_CS2_CR Register

List of Figures

2649
2650
2651
2652
2653
2654
2655
2656
2658
2659
2660
2661
2663
2664
2665

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

List of Tables
1-1.

TMU Supported Instructions .............................................................................................. 83

1-2.

Viterbi Decode Performance .............................................................................................. 84

1-3.

Complex Math Performance .............................................................................................. 84

2-1.

Reset Signals ............................................................................................................... 87

2-2.

PIE Channel Mapping

2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.
2-26.
2-27.
2-28.
2-29.
2-30.
2-31.
2-32.
2-33.
2-34.
2-35.
2-36.
2-37.
2-38.
2-39.
2-40.
2-41.
2-42.
2-43.
2-44.

..................................................................................................... 95
CPU Interrupt Vectors ..................................................................................................... 96
PIE Interrupt Vectors ....................................................................................................... 97
Access to EALLOW-Protected Registers .............................................................................. 104
Clock Connections Sorted by Clock Domain .......................................................................... 113
Clock Connections Sorted by Module Name .......................................................................... 114
Example Watchdog Key Sequences ................................................................................... 119
Local Shared RAM........................................................................................................ 126
Global Shared RAM ...................................................................................................... 126
Error Handling in Different Scenarios .................................................................................. 131
Mapping of ECC Bits in Read Data from ECC/Parity Address Map ............................................... 132
Mapping of Parity Bits in Read Data from ECC/Parity Address Map .............................................. 132
RAM Status ................................................................................................................ 146
Security Levels ............................................................................................................ 147
System Control Base Address Table................................................................................... 159
CPUTIMER_REGS Registers ........................................................................................... 160
CPUTIMER_REGS Access Type Codes .............................................................................. 160
TIM Register Field Descriptions ........................................................................................ 161
PRD Register Field Descriptions ....................................................................................... 162
TCR Register Field Descriptions........................................................................................ 163
TPR Register Field Descriptions ........................................................................................ 165
TPRH Register Field Descriptions ...................................................................................... 166
PIE_CTRL_REGS Registers ............................................................................................ 167
PIE_CTRL_REGS Access Type Codes ............................................................................... 167
PIECTRL Register Field Descriptions .................................................................................. 169
PIEACK Register Field Descriptions ................................................................................... 170
PIEIER1 Register Field Descriptions ................................................................................... 171
PIEIFR1 Register Field Descriptions ................................................................................... 173
PIEIER2 Register Field Descriptions ................................................................................... 175
PIEIFR2 Register Field Descriptions ................................................................................... 177
PIEIER3 Register Field Descriptions ................................................................................... 179
PIEIFR3 Register Field Descriptions ................................................................................... 181
PIEIER4 Register Field Descriptions ................................................................................... 183
PIEIFR4 Register Field Descriptions ................................................................................... 185
PIEIER5 Register Field Descriptions ................................................................................... 187
PIEIFR5 Register Field Descriptions ................................................................................... 189
PIEIER6 Register Field Descriptions ................................................................................... 191
PIEIFR6 Register Field Descriptions ................................................................................... 193
PIEIER7 Register Field Descriptions ................................................................................... 195
PIEIFR7 Register Field Descriptions ................................................................................... 197
PIEIER8 Register Field Descriptions ................................................................................... 199
PIEIFR8 Register Field Descriptions ................................................................................... 201
PIEIER9 Register Field Descriptions ................................................................................... 203

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

49

www.ti.com

2-45.

PIEIFR9 Register Field Descriptions ................................................................................... 205

2-46.

PIEIER10 Register Field Descriptions ................................................................................. 207

2-47.

PIEIFR10 Register Field Descriptions

2-48.

PIEIER11 Register Field Descriptions ................................................................................. 211

2-49.

PIEIFR11 Register Field Descriptions

2-50.

PIEIER12 Register Field Descriptions ................................................................................. 215

2-51.

PIEIFR12 Register Field Descriptions

2-52.

WD_REGS Registers

2-53.
2-54.
2-55.
2-56.
2-57.
2-58.
2-59.
2-60.
2-61.
2-62.
2-63.
2-64.
2-65.
2-66.
2-67.
2-68.
2-69.
2-70.
2-71.
2-72.
2-73.
2-74.
2-75.
2-76.
2-77.
2-78.
2-79.
2-80.
2-81.
2-82.
2-83.
2-84.
2-85.
2-86.
2-87.
2-88.
2-89.
2-90.
2-91.
2-92.
2-93.
50

.................................................................................
.................................................................................

.................................................................................
....................................................................................................
WD_REGS Access Type Codes ........................................................................................
SCSR Register Field Descriptions ......................................................................................
WDCNTR Register Field Descriptions .................................................................................
WDKEY Register Field Descriptions ...................................................................................
WDCR Register Field Descriptions .....................................................................................
WDWCR Register Field Descriptions ..................................................................................
NMI_INTRUPT_REGS Registers .......................................................................................
NMI_INTRUPT_REGS Access Type Codes ..........................................................................
NMICFG Register Field Descriptions ..................................................................................
NMIFLG Register Field Descriptions ...................................................................................
NMIFLGCLR Register Field Descriptions..............................................................................
NMIFLGFRC Register Field Descriptions .............................................................................
NMIWDCNT Register Field Descriptions ..............................................................................
NMIWDPRD Register Field Descriptions ..............................................................................
NMISHDFLG Register Field Descriptions .............................................................................
XINT_REGS Registers ...................................................................................................
XINT_REGS Access Type Codes ......................................................................................
XINT1CR Register Field Descriptions..................................................................................
XINT2CR Register Field Descriptions..................................................................................
XINT3CR Register Field Descriptions..................................................................................
XINT4CR Register Field Descriptions..................................................................................
XINT5CR Register Field Descriptions..................................................................................
XINT1CTR Register Field Descriptions ................................................................................
XINT2CTR Register Field Descriptions ................................................................................
XINT3CTR Register Field Descriptions ................................................................................
DMA_CLA_SRC_SEL_REGS Registers ..............................................................................
DMA_CLA_SRC_SEL_REGS Access Type Codes ..................................................................
CLA1TASKSRCSELLOCK Register Field Descriptions .............................................................
DMACHSRCSELLOCK Register Field Descriptions .................................................................
CLA1TASKSRCSEL1 Register Field Descriptions ...................................................................
CLA1TASKSRCSEL2 Register Field Descriptions ...................................................................
DMACHSRCSEL1 Register Field Descriptions .......................................................................
DMACHSRCSEL2 Register Field Descriptions .......................................................................
FLASH_PUMP_SEMAPHORE_REGS Registers ....................................................................
FLASH_PUMP_SEMAPHORE_REGS Access Type Codes .......................................................
PUMPREQUEST Register Field Descriptions ........................................................................
DEV_CFG_REGS Registers ............................................................................................
DEV_CFG_REGS Access Type Codes ...............................................................................
DEVCFGLOCK1 Register Field Descriptions .........................................................................
PARTIDL_1 Register Field Descriptions ...............................................................................
PARTIDH_1 Register Field Descriptions ..............................................................................

List of Tables

209
213
217
219
219
220
221
222
223
224
225
225
226
227
229
232
234
235
236
238
238
239
240
241
242
243
244
245
246
247
247
248
249
250
251
252
253
254
254
255
256
257
258
260
262

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

2-94.

REVID Register Field Descriptions ..................................................................................... 263

2-95.

DC0_1 Register Field Descriptions ..................................................................................... 264

2-96.

DC1_1 Register Field Descriptions ..................................................................................... 265

2-97.

DC2_1 Register Field Descriptions ..................................................................................... 266

2-98.

DC3_1 Register Field Descriptions ..................................................................................... 267

2-99.

DC4_1 Register Field Descriptions ..................................................................................... 269

2-100. DC5_1 Register Field Descriptions ..................................................................................... 270
2-101. DC6_1 Register Field Descriptions ..................................................................................... 271
2-102. DC7_1 Register Field Descriptions ..................................................................................... 272
2-103. DC8_1 Register Field Descriptions ..................................................................................... 273
2-104. DC9_1 Register Field Descriptions ..................................................................................... 274
2-105. DC10_1 Register Field Descriptions ................................................................................... 275
2-106. DC11_1 Register Field Descriptions ................................................................................... 276
2-107. DC12_1 Register Field Descriptions ................................................................................... 277
2-108. DC13_1 Register Field Descriptions ................................................................................... 278
2-109. DC14_1 Register Field Descriptions ................................................................................... 279
2-110. DC15_1 Register Field Descriptions ................................................................................... 280
2-111. DC17_1 Register Field Descriptions ................................................................................... 282
2-112. DC18_1 Register Field Descriptions ................................................................................... 283
2-113. DC19_1 Register Field Descriptions ................................................................................... 284
2-114. DC20_1 Register Field Descriptions ................................................................................... 285
2-115. PERCNF1_1 Register Field Descriptions.............................................................................. 287
2-116. FUSEERR Register Field Descriptions ................................................................................ 288
2-117. SOFTPRES0 Register Field Descriptions ............................................................................. 289
2-118. SOFTPRES1 Register Field Descriptions ............................................................................. 290
2-119. SOFTPRES2 Register Field Descriptions ............................................................................. 291
2-120. SOFTPRES3 Register Field Descriptions ............................................................................. 293
2-121. SOFTPRES4 Register Field Descriptions ............................................................................. 294
2-122. SOFTPRES6 Register Field Descriptions ............................................................................. 295
2-123. SOFTPRES7 Register Field Descriptions ............................................................................. 296
2-124. SOFTPRES8 Register Field Descriptions ............................................................................. 297
2-125. SOFTPRES9 Register Field Descriptions ............................................................................. 298
2-126. SOFTPRES11 Register Field Descriptions............................................................................ 299
2-127. SOFTPRES13 Register Field Descriptions............................................................................ 300
2-128. SOFTPRES14 Register Field Descriptions............................................................................ 301
2-129. SOFTPRES16 Register Field Descriptions............................................................................ 302
2-130. CPUSEL0 Register Field Descriptions ................................................................................. 303
2-131. CPUSEL1 Register Field Descriptions ................................................................................. 305
2-132. CPUSEL2 Register Field Descriptions ................................................................................. 306
2-133. CPUSEL3 Register Field Descriptions ................................................................................. 307
2-134. CPUSEL4 Register Field Descriptions ................................................................................. 308
2-135. CPUSEL5 Register Field Descriptions ................................................................................. 309
2-136. CPUSEL6 Register Field Descriptions ................................................................................. 310
2-137. CPUSEL7 Register Field Descriptions ................................................................................. 311
2-138. CPUSEL8 Register Field Descriptions ................................................................................. 312
2-139. CPUSEL9 Register Field Descriptions ................................................................................. 313

...............................................................................
...............................................................................
CPUSEL14 Register Field Descriptions ...............................................................................

2-140. CPUSEL11 Register Field Descriptions

314

2-141. CPUSEL12 Register Field Descriptions

316

2-142.

318

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

51

www.ti.com

2-143. CPU2RESCTL Register Field Descriptions ........................................................................... 319
2-144. RSTSTAT Register Field Descriptions ................................................................................. 320
2-145. LPMSTAT Register Field Descriptions ................................................................................. 321
2-146. SYSDBGCTL Register Field Descriptions ............................................................................. 322
2-147. CLK_CFG_REGS Registers

............................................................................................

323

2-148. CLK_CFG_REGS Access Type Codes ................................................................................ 323
2-149. CLKSEM Register Field Descriptions .................................................................................. 325
2-150. CLKCFGLOCK1 Register Field Descriptions ......................................................................... 326
2-151. CLKSRCCTL1 Register Field Descriptions............................................................................ 328
2-152. CLKSRCCTL2 Register Field Descriptions............................................................................ 330
2-153. CLKSRCCTL3 Register Field Descriptions............................................................................ 332
2-154. SYSPLLCTL1 Register Field Descriptions ............................................................................ 333
2-155. SYSPLLMULT Register Field Descriptions............................................................................ 334
2-156. SYSPLLSTS Register Field Descriptions .............................................................................. 335
2-157. AUXPLLCTL1 Register Field Descriptions ............................................................................ 336

...........................................................................
AUXPLLSTS Register Field Descriptions..............................................................................
SYSCLKDIVSEL Register Field Descriptions .........................................................................
AUXCLKDIVSEL Register Field Descriptions .........................................................................
PERCLKDIVSEL Register Field Descriptions .........................................................................
XCLKOUTDIVSEL Register Field Descriptions .......................................................................
LOSPCP Register Field Descriptions ..................................................................................
MCDCR Register Field Descriptions ...................................................................................
X1CNT Register Field Descriptions ....................................................................................
CPU_SYS_REGS Registers ............................................................................................
CPU_SYS_REGS Access Type Codes ................................................................................
CPUSYSLOCK1 Register Field Descriptions .........................................................................
HIBBOOTMODE Register Field Descriptions .........................................................................
IORESTOREADDR Register Field Descriptions......................................................................
PIEVERRADDR Register Field Descriptions ..........................................................................
PCLKCR0 Register Field Descriptions .................................................................................
PCLKCR1 Register Field Descriptions .................................................................................
PCLKCR2 Register Field Descriptions .................................................................................
PCLKCR3 Register Field Descriptions .................................................................................
PCLKCR4 Register Field Descriptions .................................................................................
PCLKCR6 Register Field Descriptions .................................................................................
PCLKCR7 Register Field Descriptions .................................................................................
PCLKCR8 Register Field Descriptions .................................................................................
PCLKCR9 Register Field Descriptions .................................................................................
PCLKCR10 Register Field Descriptions ...............................................................................
PCLKCR11 Register Field Descriptions ...............................................................................
PCLKCR12 Register Field Descriptions ...............................................................................
PCLKCR13 Register Field Descriptions ...............................................................................
PCLKCR14 Register Field Descriptions ...............................................................................
PCLKCR16 Register Field Descriptions ...............................................................................
SECMSEL_1 Register Field Descriptions .............................................................................
LPMCR Register Field Descriptions ....................................................................................
GPIOLPMSEL0 Register Field Descriptions ..........................................................................
GPIOLPMSEL1 Register Field Descriptions ..........................................................................

2-158. AUXPLLMULT Register Field Descriptions
2-159.
2-160.
2-161.
2-162.
2-163.
2-164.
2-165.
2-166.
2-167.
2-168.
2-169.
2-170.
2-171.
2-172.
2-173.
2-174.
2-175.
2-176.
2-177.
2-178.
2-179.
2-180.
2-181.
2-182.
2-183.
2-184.
2-185.
2-186.
2-187.
2-188.
2-189.
2-190.
2-191.
52

List of Tables

337
338
339
340
341
342
343
344
345
346
346
348
351
352
353
354
356
357
359
361
362
363
364
365
366
367
368
369
370
372
373
374
376
379

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

...........................................................................
RESC Register Field Descriptions ......................................................................................
ROM_PREFETCH_REGS Registers...................................................................................
ROM_PREFETCH_REGS Access Type Codes ......................................................................
ROMPREFETCH Register Field Descriptions ........................................................................
DCSM_Z1_OTP Registers ..............................................................................................
DCSM_Z1_OTP Access Type Codes ..................................................................................
Z1OTP_LINKPOINTER1 Register Field Descriptions ...............................................................
Z1OTP_LINKPOINTER2 Register Field Descriptions ...............................................................
Z1OTP_LINKPOINTER3 Register Field Descriptions ...............................................................
Z1OTP_PSWDLOCK Register Field Descriptions ...................................................................
Z1OTP_CRCLOCK Register Field Descriptions ......................................................................
Z1OTP_BOOTCTRL Register Field Descriptions ....................................................................
DCSM_Z2_OTP Registers ..............................................................................................
DCSM_Z2_OTP Access Type Codes ..................................................................................
Z2OTP_LINKPOINTER1 Register Field Descriptions ...............................................................
Z2OTP_LINKPOINTER2 Register Field Descriptions ...............................................................
Z2OTP_LINKPOINTER3 Register Field Descriptions ...............................................................
Z2OTP_PSWDLOCK Register Field Descriptions ...................................................................
Z2OTP_CRCLOCK Register Field Descriptions ......................................................................
Z2OTP_BOOTCTRL Register Field Descriptions ....................................................................
DCSM_Z1_REGS Registers ............................................................................................
DCSM_Z1_REGS Access Type Codes ................................................................................
Z1_LINKPOINTER Register Field Descriptions ......................................................................
Z1_OTPSECLOCK Register Field Descriptions ......................................................................
Z1_BOOTCTRL Register Field Descriptions ..........................................................................
Z1_LINKPOINTERERR Register Field Descriptions .................................................................
Z1_CSMKEY0 Register Field Descriptions............................................................................
Z1_CSMKEY1 Register Field Descriptions............................................................................
Z1_CSMKEY2 Register Field Descriptions............................................................................
Z1_CSMKEY3 Register Field Descriptions............................................................................
Z1_CR Register Field Descriptions.....................................................................................
Z1_GRABSECTR Register Field Descriptions ........................................................................
Z1_GRABRAMR Register Field Descriptions .........................................................................
Z1_EXEONLYSECTR Register Field Descriptions...................................................................
Z1_EXEONLYRAMR Register Field Descriptions ....................................................................
DCSM_Z2_REGS Registers ............................................................................................
DCSM_Z2_REGS Access Type Codes ................................................................................
Z2_LINKPOINTER Register Field Descriptions ......................................................................
Z2_OTPSECLOCK Register Field Descriptions ......................................................................
Z2_BOOTCTRL Register Field Descriptions ..........................................................................
Z2_LINKPOINTERERR Register Field Descriptions .................................................................
Z2_CSMKEY0 Register Field Descriptions............................................................................
Z2_CSMKEY1 Register Field Descriptions............................................................................
Z2_CSMKEY2 Register Field Descriptions............................................................................
Z2_CSMKEY3 Register Field Descriptions............................................................................
Z2_CR Register Field Descriptions.....................................................................................
Z2_GRABSECTR Register Field Descriptions ........................................................................
Z2_GRABRAMR Register Field Descriptions .........................................................................

2-192. TMR2CLKCTL Register Field Descriptions

382

2-193.

384

2-194.
2-195.
2-196.
2-197.
2-198.
2-199.
2-200.
2-201.
2-202.
2-203.
2-204.
2-205.
2-206.
2-207.
2-208.
2-209.
2-210.
2-211.
2-212.
2-213.
2-214.
2-215.
2-216.
2-217.
2-218.
2-219.
2-220.
2-221.
2-222.
2-223.
2-224.
2-225.
2-226.
2-227.
2-228.
2-229.
2-230.
2-231.
2-232.
2-233.
2-234.
2-235.
2-236.
2-237.
2-238.
2-239.
2-240.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

386
386
387
388
388
389
390
391
392
393
394
395
395
396
397
398
399
400
401
402
402
403
404
405
406
407
408
409
410
411
412
415
417
420
422
422
423
424
425
426
427
428
429
430
431
432
435
53

www.ti.com

2-241. Z2_EXEONLYSECTR Register Field Descriptions................................................................... 437
2-242. Z2_EXEONLYRAMR Register Field Descriptions .................................................................... 440
2-243. DCSM_COMMON_REGS Registers ................................................................................... 442
2-244. DCSM_COMMON_REGS Access Type Codes ...................................................................... 442
2-245. FLSEM Register Field Descriptions .................................................................................... 443
2-246. SECTSTAT Register Field Descriptions ............................................................................... 444
2-247. RAMSTAT Register Field Descriptions ................................................................................ 447
2-248. MEM_CFG_REGS Registers

...........................................................................................

449

2-249. MEM_CFG_REGS Access Type Codes ............................................................................... 449
2-250. DxLOCK Register Field Descriptions

..................................................................................

451

2-251. DxCOMMIT Register Field Descriptions ............................................................................... 452
2-252. DxACCPROT0 Register Field Descriptions ........................................................................... 453
2-253. DxTEST Register Field Descriptions ................................................................................... 454
2-254. DxINIT Register Field Descriptions ..................................................................................... 455
2-255. DxINITDONE Register Field Descriptions ............................................................................. 456
2-256. LSxLOCK Register Field Descriptions ................................................................................. 457
2-257. LSxCOMMIT Register Field Descriptions.............................................................................. 459
2-258. LSxMSEL Register Field Descriptions ................................................................................. 461
2-259. LSxCLAPGM Register Field Descriptions ............................................................................. 463
2-260. LSxACCPROT0 Register Field Descriptions .......................................................................... 464
2-261. LSxACCPROT1 Register Field Descriptions .......................................................................... 466
2-262. LSxTEST Register Field Descriptions.................................................................................. 467
2-263. LSxINIT Register Field Descriptions

...................................................................................

469

2-264. LSxINITDONE Register Field Descriptions............................................................................ 470
2-265. GSxLOCK Register Field Descriptions................................................................................. 471
2-266. GSxCOMMIT Register Field Descriptions ............................................................................. 474
2-267. GSxMSEL Register Field Descriptions................................................................................. 477
2-268. GSxACCPROT0 Register Field Descriptions ......................................................................... 479
2-269. GSxACCPROT1 Register Field Descriptions ......................................................................... 481
2-270. GSxACCPROT2 Register Field Descriptions ......................................................................... 483
2-271. GSxACCPROT3 Register Field Descriptions ......................................................................... 485
2-272. GSxTEST Register Field Descriptions ................................................................................. 487
2-273. GSxINIT Register Field Descriptions ................................................................................... 490
2-274. GSxINITDONE Register Field Descriptions ........................................................................... 492
2-275. MSGxTEST Register Field Descriptions ............................................................................... 494
2-276. MSGxINIT Register Field Descriptions................................................................................. 495
2-277. MSGxINITDONE Register Field Descriptions ......................................................................... 496
2-278. ACCESS_PROTECTION_REGS Registers ........................................................................... 497
2-279. ACCESS_PROTECTION_REGS Access Type Codes .............................................................. 497
2-280. NMAVFLG Register Field Descriptions ................................................................................ 499
2-281. NMAVSET Register Field Descriptions ................................................................................ 501
2-282. NMAVCLR Register Field Descriptions ................................................................................ 503
2-283. NMAVINTEN Register Field Descriptions ............................................................................. 505
2-284. NMCPURDAVADDR Register Field Descriptions .................................................................... 506
2-285. NMCPUWRAVADDR Register Field Descriptions

...................................................................

507

2-286. NMCPUFAVADDR Register Field Descriptions ...................................................................... 508
2-287. NMDMAWRAVADDR Register Field Descriptions ................................................................... 509
2-288. NMCLA1RDAVADDR Register Field Descriptions ................................................................... 510
2-289. NMCLA1WRAVADDR Register Field Descriptions
54

List of Tables

..................................................................

511

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

2-290. NMCLA1FAVADDR Register Field Descriptions ..................................................................... 512
2-291. MAVFLG Register Field Descriptions .................................................................................. 513
2-292. MAVSET Register Field Descriptions .................................................................................. 514
2-293. MAVCLR Register Field Descriptions .................................................................................. 515
2-294. MAVINTEN Register Field Descriptions ............................................................................... 516
2-295. MCPUFAVADDR Register Field Descriptions ........................................................................ 517
2-296. MCPUWRAVADDR Register Field Descriptions

.....................................................................

518

2-297. MDMAWRAVADDR Register Field Descriptions ..................................................................... 519
2-298. MEMORY_ERROR_REGS Registers.................................................................................. 520
2-299. MEMORY_ERROR_REGS Access Type Codes ..................................................................... 520
2-300. UCERRFLG Register Field Descriptions .............................................................................. 521
2-301. UCERRSET Register Field Descriptions .............................................................................. 522
2-302. UCERRCLR Register Field Descriptions .............................................................................. 523
2-303. UCCPUREADDR Register Field Descriptions ........................................................................ 524
2-304. UCDMAREADDR Register Field Descriptions ........................................................................ 525
2-305. UCCLA1READDR Register Field Descriptions ....................................................................... 526
2-306. CERRFLG Register Field Descriptions ................................................................................ 527
2-307. CERRSET Register Field Descriptions ................................................................................ 528
2-308. CERRCLR Register Field Descriptions ................................................................................ 529
2-309. CCPUREADDR Register Field Descriptions .......................................................................... 530
2-310. CERRCNT Register Field Descriptions ................................................................................ 531
2-311. CERRTHRES Register Field Descriptions ............................................................................ 532
2-312. CEINTFLG Register Field Descriptions ................................................................................ 533
2-313. CEINTCLR Register Field Descriptions ................................................................................ 534
2-314. CEINTSET Register Field Descriptions ................................................................................ 535
2-315. CEINTEN Register Field Descriptions ................................................................................. 536
2-316. ROM_WAIT_STATE_REGS Registers ................................................................................ 537

...................................................................
.......................................................................
FLASH_CTRL_REGS Registers ........................................................................................
FLASH_CTRL_REGS Access Type Codes ...........................................................................
FRDCNTL Register Field Descriptions.................................................................................
FBAC Register Field Descriptions ......................................................................................
FBFALLBACK Register Field Descriptions ............................................................................
FBPRDY Register Field Descriptions ..................................................................................
FPAC1 Register Field Descriptions ....................................................................................
FMSTAT Register Field Descriptions ..................................................................................
FRD_INTF_CTRL Register Field Descriptions........................................................................
FLASH_ECC_REGS Registers .........................................................................................
FLASH_ECC_REGS Access Type Codes ............................................................................
ECC_ENABLE Register Field Descriptions ...........................................................................
SINGLE_ERR_ADDR_LOW Register Field Descriptions ...........................................................
SINGLE_ERR_ADDR_HIGH Register Field Descriptions ...........................................................
UNC_ERR_ADDR_LOW Register Field Descriptions ...............................................................
UNC_ERR_ADDR_HIGH Register Field Descriptions ...............................................................
ERR_STATUS Register Field Descriptions ...........................................................................
ERR_POS Register Field Descriptions ................................................................................
ERR_STATUS_CLR Register Field Descriptions ....................................................................
ERR_CNT Register Field Descriptions ................................................................................

2-317. ROM_WAIT_STATE_REGS Access Type Codes

537

2-318. ROMWAITSTATE Register Field Descriptions

538

2-319.

539

2-320.
2-321.
2-322.
2-323.
2-324.
2-325.
2-326.
2-327.
2-328.
2-329.
2-330.
2-331.
2-332.
2-333.
2-334.
2-335.
2-336.
2-337.
2-338.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

539
540
541
542
543
544
545
547
548
548
550
551
552
553
554
555
557
558
559
55

www.ti.com

2-339. ERR_THRESHOLD Register Field Descriptions ..................................................................... 560
2-340. ERR_INTFLG Register Field Descriptions ............................................................................ 561
2-341. ERR_INTCLR Register Field Descriptions ............................................................................ 562
2-342. FDATAH_TEST Register Field Descriptions .......................................................................... 563
564

2-344. FADDR_TEST Register Field Descriptions

565

2-345.
2-346.
2-347.
2-348.
2-349.
2-350.
2-351.
2-352.
2-353.
2-354.
2-355.
2-356.
2-357.
2-358.
2-359.
2-360.
2-361.
2-362.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
56

..........................................................................
...........................................................................
FECC_TEST Register Field Descriptions .............................................................................
FECC_CTRL Register Field Descriptions .............................................................................
FOUTH_TEST Register Field Descriptions ...........................................................................
FOUTL_TEST Register Field Descriptions ............................................................................
FECC_STATUS Register Field Descriptions ..........................................................................
CPU_ID_REGS Registers ...............................................................................................
CPU_ID_REGS Access Type Codes ..................................................................................
CPUID_1 Register Field Descriptions ..................................................................................
UID_REGS Registers ....................................................................................................
UID_REGS Access Type Codes........................................................................................
UID_PSRAND0 Register Field Descriptions ..........................................................................
UID_PSRAND1 Register Field Descriptions ..........................................................................
UID_PSRAND2 Register Field Descriptions ..........................................................................
UID_PSRAND3 Register Field Descriptions ..........................................................................
UID_PSRAND4 Register Field Descriptions ..........................................................................
UID_PSRAND5 Register Field Descriptions ..........................................................................
UID_UNIQUE Register Field Descriptions ............................................................................
UID_CHECKSUM Register Field Descriptions........................................................................
ROM Memory .............................................................................................................
Boot ROM Philosophy ....................................................................................................
Device Default Boot Modes for CPU1 .................................................................................
All Available Boot Modes ................................................................................................
BOOTCTRL Register Bit Fields for CPU1 .............................................................................
BOOTCTRL Register Bit Fields for CPU2 .............................................................................
Get Mode Decoding on CPU1 ..........................................................................................
Get Mode Decoding on CPU2 ..........................................................................................
Emulation Boot Options ..................................................................................................
Boot ROM Reset Causes and Actions .................................................................................
Boot ROM Exceptions and Actions .....................................................................................
Entry Point Addresses for CPU1 and CPU2 ..........................................................................
Wait Point Addresses for CPU1 ........................................................................................
Wait Point Addresses for CPU2 ........................................................................................
CPU1 Boot ROM Memory Map .........................................................................................
CPU2 Boot ROM Memory Map .........................................................................................
CLA Data ROM Memory Map ...........................................................................................
Reserved RAM and Flash Memory Map for CPU1 ...................................................................
Reserved RAM and Flash Memory Map for CPU2 ...................................................................
CLA Data ROM Tables...................................................................................................
SPI 8-Bit Data Stream ...................................................................................................
I2C 8-Bit Data Stream ...................................................................................................
Parallel GPIO Boot 8-Bit Data Stream .................................................................................
Bit-Rate Value for Internal Oscillators ..................................................................................
CAN 8-Bit Data Stream ..................................................................................................

2-343. FDATAL_TEST Register Field Descriptions

List of Tables

566
567
568
569
570
571
571
572
573
573
574
575
576
577
578
579
580
581
583
583
584
584
584
585
586
586
586
593
594
595
595
595
595
596
596
597
597
597
601
604
605
609
609

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

3-26.
3-27.
3-28.
3-29.
3-30.
3-31.
3-32.
3-33.
3-34.
3-35.
3-36.
3-37.
3-38.
3-39.
3-40.
3-41.
3-42.
3-43.
3-44.
3-45.
3-46.
3-47.
3-48.
3-49.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.

..................................................................................................
LSB/MSB Loading Sequence in 8-Bit Data Stream ..................................................................
SCI Boot Options .........................................................................................................
CAN Boot Options ........................................................................................................
I2C Boot Options ..........................................................................................................
USB Boot Options ........................................................................................................
RAM Boot Options ........................................................................................................
Flash Boot Options .......................................................................................................
Wait Boot Options ........................................................................................................
SPI Boot Options .........................................................................................................
Parallel Boot Options .....................................................................................................
C2TOC1IPC Commands Table ........................................................................................
C1TOC2IPC Commands Table .........................................................................................
CPU2 Error Command Values ..........................................................................................
Boot Clock Sources ......................................................................................................
Clock State After Boot ROM ............................................................................................
ROM Wait States .........................................................................................................
CPU1 Boot Status Address..............................................................................................
CPU1 Boot Status Bit Fields ............................................................................................
CPU2 Boot ROM Status Address ......................................................................................
CPU Booting Status ......................................................................................................
CPU1 IPC NAK Status Bit Fields .......................................................................................
CPU2 IPC NAK Status Bit Fields .......................................................................................
Boot ROM Version Information for CPU1 and CPU2 ................................................................
Peripheral Interrupt Trigger Source Options ..........................................................................
DMA Register Summary ................................................................................................
DMA Control Register (DMACTRL) Field Descriptions ..............................................................
Debug Control Register (DEBUGCTRL) Field Descriptions ........................................................
Revision Register (REVISION) Field Descriptions ...................................................................
Priority Control Register 1 (PRIORITYCTRL1) Field Descriptions .................................................
Priority Status Register (PRIORITYSTAT) Field Descriptions ......................................................
Mode Register (MODE) Field Descriptions ............................................................................
Control Register (CONTROL) Field Descriptions .....................................................................
Burst Size Register (BURST_SIZE) Field Descriptions..............................................................
Burst Count Register (BURST_COUNT) Field Descriptions ........................................................
Source Burst Step Size Register (SRC_BURST_STEP) Field Descriptions......................................
Destination Burst Step Register Size (DST_BURST_STEP) Field Descriptions .................................
Transfer Size Register (TRANSFER_SIZE) Field Descriptions ....................................................
Transfer Count Register (TRANSFER_COUNT) Field Descriptions ...............................................
Source Transfer Step Size Register (SRC_TRANSFER_STEP) Field Descriptions ............................
Destination Transfer Step Size Register (DST_TRANSFER_STEP) Field Descriptions ........................
Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) Field Descriptions .........................
Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) Field Descriptions ....................
Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) Field Descriptions .................
USB 8-Bit Data Stream

Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) Field Descriptions

..............................

610
612
614
614
614
614
614
614
614
614
615
615
616
618
618
619
619
619
619
620
620
621
621
622
629
642
643
644
644
645
646
647
649
651
651
652
653
653
654
654
655
655
656
656
657

4-22.

Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR) Field
Descriptions ............................................................................................................... 657

4-23.

Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) Field Descriptions ............................................. 658

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

57

www.ti.com

4-24.

Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) Field
Descriptions ............................................................................................................... 658

5-1.

Configuration Options .................................................................................................... 664

5-2.

Write Followed by Read - Read Occurs First

673

5-3.

Write Followed by Read - Write Occurs First

673

5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
5-28.
5-29.
5-30.
5-31.
5-32.
5-33.
5-34.
5-35.
5-36.
5-37.
5-38.
5-39.
5-40.
5-41.
5-42.
5-43.
5-44.
5-45.
5-46.
5-47.
58

........................................................................
........................................................................
ADC to CLA Early Interrupt Response ................................................................................
Operand Nomenclature ..................................................................................................
INSTRUCTION dest, source1, source2 Short Description ..........................................................
Addressing Modes ........................................................................................................
Shift Field Encoding ......................................................................................................
Operand Encoding ........................................................................................................
Condition Field Encoding ................................................................................................
General Instructions ......................................................................................................
Pipeline Activity For MBCNDD, Branch Not Taken ..................................................................
Pipeline Activity For MBCNDD, Branch Taken .......................................................................
Pipeline Activity For MCCNDD, Call Not Taken .....................................................................
Pipeline Activity For MCCNDD, Call Taken ..........................................................................
Pipeline Activity For MMOV16 MARx, MRa , #16I ...................................................................
Pipeline Activity For MMOV16 MAR0/MAR1, mem16 ...............................................................
Pipeline Activity For MMOVI16 MAR0/MAR1, #16I ..................................................................
Pipeline Activity For MRCNDD, Return Not Taken ..................................................................
Pipeline Activity For MRCNDD, Return Taken .......................................................................
Pipeline Activity For MSTOP ............................................................................................
CLA Base Address Table ................................................................................................
CLA_REGS Registers ....................................................................................................
CLA_REGS Access Type Codes .......................................................................................
MVECT1 Register Field Descriptions ..................................................................................
MVECT2 Register Field Descriptions ..................................................................................
MVECT3 Register Field Descriptions ..................................................................................
MVECT4 Register Field Descriptions ..................................................................................
MVECT5 Register Field Descriptions ..................................................................................
MVECT6 Register Field Descriptions ..................................................................................
MVECT7 Register Field Descriptions ..................................................................................
MVECT8 Register Field Descriptions ..................................................................................
MCTL Register Field Descriptions ......................................................................................
MIFR Register Field Descriptions.......................................................................................
MIOVF Register Field Descriptions.....................................................................................
MIFRC Register Field Descriptions.....................................................................................
MICLR Register Field Descriptions .....................................................................................
MICLROVF Register Field Descriptions ...............................................................................
MIER Register Field Descriptions ......................................................................................
MIRUN Register Field Descriptions ....................................................................................
_MPC Register Field Descriptions ......................................................................................
_MAR0 Register Field Descriptions ....................................................................................
_MAR1 Register Field Descriptions ....................................................................................
_MSTF Register Field Descriptions ....................................................................................
_MR0 Register Field Descriptions ......................................................................................
_MR1 Register Field Descriptions ......................................................................................
_MR2 Register Field Descriptions ......................................................................................

List of Tables

675
677
678
679
680
680
680
681
696
696
702
702
734
737
751
773
773
777
792
793
793
795
796
797
798
799
800
801
802
803
804
806
808
810
812
814
816
818
819
820
821
824
825
826

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

5-48.

_MR3 Register Field Descriptions ...................................................................................... 827

5-49.

CLA_SOFTINT_REGS Registers ....................................................................................... 828

5-50.

CLA_SOFTINT_REGS Access Type Codes .......................................................................... 828

5-51.

SOFTINTEN Register Field Descriptions .............................................................................. 829

5-52.

SOFTINTFRC Register Field Descriptions ............................................................................ 831

6-1.

IPC Message RAM Read/Write Access

6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
6-22.
6-23.
6-24.
6-25.
6-26.
6-27.
6-28.
6-29.
6-30.
6-31.
6-32.
6-33.
6-34.
6-35.
6-36.
6-37.
6-38.
6-39.
6-40.
6-41.
7-1.
7-2.
7-3.

...............................................................................
IPC Command Registers ................................................................................................
IPC Base Addresses .....................................................................................................
IPC_REGS_CPU1 Registers ............................................................................................
IPC_REGS_CPU1 Access Type Codes ...............................................................................
IPCACK Register Field Descriptions ...................................................................................
IPCSTS Register Field Descriptions ...................................................................................
IPCSET Register Field Descriptions ...................................................................................
IPCCLR Register Field Descriptions ...................................................................................
IPCFLG Register Field Descriptions ...................................................................................
IPCCOUNTERL Register Field Descriptions ..........................................................................
IPCCOUNTERH Register Field Descriptions .........................................................................
IPCSENDCOM Register Field Descriptions ...........................................................................
IPCSENDADDR Register Field Descriptions .........................................................................
IPCSENDDATA Register Field Descriptions ..........................................................................
IPCREMOTEREPLY Register Field Descriptions ....................................................................
IPCRECVCOM Register Field Descriptions ...........................................................................
IPCRECVADDR Register Field Descriptions .........................................................................
IPCRECVDATA Register Field Descriptions ..........................................................................
IPCLOCALREPLY Register Field Descriptions .......................................................................
IPCBOOTSTS Register Field Descriptions ............................................................................
IPCBOOTMODE Register Field Descriptions .........................................................................
IPC_REGS_CPU2 Registers ............................................................................................
IPC_REGS_CPU2 Access Type Codes ...............................................................................
IPCACK Register Field Descriptions ...................................................................................
IPCSTS Register Field Descriptions ...................................................................................
IPCSET Register Field Descriptions ...................................................................................
IPCCLR Register Field Descriptions ...................................................................................
IPCFLG Register Field Descriptions ...................................................................................
IPCCOUNTERL Register Field Descriptions ..........................................................................
IPCCOUNTERH Register Field Descriptions .........................................................................
IPCRECVCOM Register Field Descriptions ...........................................................................
IPCRECVADDR Register Field Descriptions .........................................................................
IPCRECVDATA Register Field Descriptions ..........................................................................
IPCLOCALREPLY Register Field Descriptions .......................................................................
IPCSENDCOM Register Field Descriptions ...........................................................................
IPCSENDADDR Register Field Descriptions .........................................................................
IPCSENDDATA Register Field Descriptions ..........................................................................
IPCREMOTEREPLY Register Field Descriptions ....................................................................
IPCBOOTSTS Register Field Descriptions ............................................................................
IPCBOOTMODE Register Field Descriptions .........................................................................
Sampling Period ..........................................................................................................
Sampling Frequency .....................................................................................................
Case 1: Three-Sample Sampling Window Width .....................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

835
836
838
839
839
840
843
848
851
856
860
861
862
863
864
865
866
867
868
869
870
871
872
872
873
876
881
884
889
893
894
895
896
897
898
899
900
901
902
903
904
910
910
911
59

www.ti.com

7-4.

Case 2: Six-Sample Sampling Window Width ........................................................................ 911

7-5.

USB I/O Signal Muxing

7-6.

High-Speed SPI-Enabled GPIOs ....................................................................................... 912

7-7.

GPIO Configuration for High-Speed SPI

7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
60

..................................................................................................

..............................................................................
GPIO Muxed Pins.........................................................................................................
GPIO and Peripheral Muxing ............................................................................................
Peripheral Muxing (multiple pins assigned) ...........................................................................
Pullup Resistors for 176-pin Packages ...............................................................................
Pullup Resistors for 100-pin Packages ................................................................................
GPIO Base Address Table ..............................................................................................
Specific vs Generic Termilogy for Registers ..........................................................................
GPIO_CTRL_REGS Registers ..........................................................................................
GPIO_CTRL_REGS Access Type Codes .............................................................................
GPACTRL Register Field Descriptions ................................................................................
GPAQSEL1 Register Field Descriptions ...............................................................................
GPAQSEL2 Register Field Descriptions ...............................................................................
GPAMUX1 Register Field Descriptions ................................................................................
GPAMUX2 Register Field Descriptions ................................................................................
GPADIR Register Field Descriptions ...................................................................................
GPAPUD Register Field Descriptions ..................................................................................
GPAINV Register Field Descriptions ...................................................................................
GPAODR Register Field Descriptions .................................................................................
GPAGMUX1 Register Field Descriptions ..............................................................................
GPAGMUX2 Register Field Descriptions ..............................................................................
GPACSEL1 Register Field Descriptions ...............................................................................
GPACSEL2 Register Field Descriptions ...............................................................................
GPACSEL3 Register Field Descriptions ...............................................................................
GPACSEL4 Register Field Descriptions ...............................................................................
GPALOCK Register Field Descriptions ................................................................................
GPACR Register Field Descriptions....................................................................................
GPBCTRL Register Field Descriptions ................................................................................
GPBQSEL1 Register Field Descriptions ...............................................................................
GPBQSEL2 Register Field Descriptions ...............................................................................
GPBMUX1 Register Field Descriptions ................................................................................
GPBMUX2 Register Field Descriptions ................................................................................
GPBDIR Register Field Descriptions ...................................................................................
GPBPUD Register Field Descriptions ..................................................................................
GPBINV Register Field Descriptions ...................................................................................
GPBODR Register Field Descriptions .................................................................................
GPBAMSEL Register Field Descriptions ..............................................................................
GPBGMUX1 Register Field Descriptions ..............................................................................
GPBGMUX2 Register Field Descriptions ..............................................................................
GPBCSEL1 Register Field Descriptions ...............................................................................
GPBCSEL2 Register Field Descriptions ...............................................................................
GPBCSEL3 Register Field Descriptions ...............................................................................
GPBCSEL4 Register Field Descriptions ...............................................................................
GPBLOCK Register Field Descriptions ................................................................................
GPBCR Register Field Descriptions....................................................................................
GPCCTRL Register Field Descriptions ................................................................................

List of Tables

912
913
914
917
919
919
920
921
921
922
924
926
927
929
931
933
935
937
939
941
943
944
945
946
947
948
949
951
953
954
956
958
960
962
964
966
968
970
972
973
974
975
976
977
978
980
982

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

7-53.

GPCQSEL1 Register Field Descriptions............................................................................... 983

7-54.

GPCQSEL2 Register Field Descriptions............................................................................... 985

7-55.

GPCMUX1 Register Field Descriptions ................................................................................ 987

7-56.

GPCMUX2 Register Field Descriptions ................................................................................ 989

7-57.

GPCDIR Register Field Descriptions ................................................................................... 991

7-58.

GPCPUD Register Field Descriptions.................................................................................. 993

7-59.

GPCINV Register Field Descriptions ................................................................................... 995

7-60.

GPCODR Register Field Descriptions ................................................................................. 997

7-61.

GPCGMUX1 Register Field Descriptions .............................................................................. 999

7-62.

GPCGMUX2 Register Field Descriptions ............................................................................ 1000

7-63.

GPCCSEL1 Register Field Descriptions ............................................................................. 1001

7-64.

GPCCSEL2 Register Field Descriptions ............................................................................. 1002

7-65.

GPCCSEL3 Register Field Descriptions ............................................................................. 1003

7-66.

GPCCSEL4 Register Field Descriptions ............................................................................. 1004

7-67.

GPCLOCK Register Field Descriptions

7-68.

GPCCR Register Field Descriptions .................................................................................. 1007

7-69.

GPDCTRL Register Field Descriptions ............................................................................... 1009

7-70.

GPDQSEL1 Register Field Descriptions ............................................................................. 1010

7-71.

GPDQSEL2 Register Field Descriptions ............................................................................. 1012

7-72.

GPDMUX1 Register Field Descriptions .............................................................................. 1014

7-73.

GPDMUX2 Register Field Descriptions .............................................................................. 1016

7-74.

GPDDIR Register Field Descriptions ................................................................................. 1018

7-75.

GPDPUD Register Field Descriptions ................................................................................ 1020

7-76.

GPDINV Register Field Descriptions ................................................................................. 1022

7-77.

GPDODR Register Field Descriptions ................................................................................ 1024

7-78.

GPDGMUX1 Register Field Descriptions ............................................................................ 1026

7-79.

GPDGMUX2 Register Field Descriptions ............................................................................ 1028

7-80.

GPDCSEL1 Register Field Descriptions ............................................................................. 1030

7-81.

GPDCSEL2 Register Field Descriptions ............................................................................. 1031

7-82.

GPDCSEL3 Register Field Descriptions ............................................................................. 1032

7-83.

GPDCSEL4 Register Field Descriptions ............................................................................. 1033

7-84.

GPDLOCK Register Field Descriptions

7-85.

GPDCR Register Field Descriptions .................................................................................. 1036

7-86.

GPECTRL Register Field Descriptions ............................................................................... 1038

7-87.

GPEQSEL1 Register Field Descriptions ............................................................................. 1039

7-88.

GPEQSEL2 Register Field Descriptions ............................................................................. 1041

7-89.

GPEMUX1 Register Field Descriptions

1043

7-90.

GPEMUX2 Register Field Descriptions

1045

7-91.
7-92.
7-93.
7-94.
7-95.
7-96.
7-97.
7-98.
7-99.
7-100.
7-101.

..............................................................................

..............................................................................

..............................................................................
..............................................................................
GPEDIR Register Field Descriptions .................................................................................
GPEPUD Register Field Descriptions ................................................................................
GPEINV Register Field Descriptions .................................................................................
GPEODR Register Field Descriptions ................................................................................
GPEGMUX1 Register Field Descriptions ............................................................................
GPEGMUX2 Register Field Descriptions ............................................................................
GPECSEL1 Register Field Descriptions .............................................................................
GPECSEL2 Register Field Descriptions .............................................................................
GPECSEL3 Register Field Descriptions .............................................................................
GPECSEL4 Register Field Descriptions .............................................................................
GPELOCK Register Field Descriptions...............................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

1005

1034

1047
1049
1051
1053
1055
1057
1059
1060
1061
1062
1063
61

www.ti.com

7-102. GPECR Register Field Descriptions .................................................................................. 1065
7-103. GPFCTRL Register Field Descriptions ............................................................................... 1067
7-104. GPFQSEL1 Register Field Descriptions

.............................................................................

1068

7-105. GPFMUX1 Register Field Descriptions............................................................................... 1070
1072

7-107. GPFPUD Register Field Descriptions

1074

7-108.
7-109.
7-110.
7-111.
7-112.
7-113.
7-114.
7-115.
7-116.
7-117.
7-118.
7-119.
7-120.
7-121.
7-122.
7-123.
7-124.
7-125.
7-126.
7-127.
7-128.
7-129.
7-130.
7-131.
7-132.
7-133.
7-134.
7-135.
7-136.
7-137.
7-138.
7-139.
7-140.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
62

.................................................................................
................................................................................
GPFINV Register Field Descriptions..................................................................................
GPFODR Register Field Descriptions ................................................................................
GPFGMUX1 Register Field Descriptions ............................................................................
GPFCSEL1 Register Field Descriptions..............................................................................
GPFCSEL2 Register Field Descriptions..............................................................................
GPFLOCK Register Field Descriptions ...............................................................................
GPFCR Register Field Descriptions ..................................................................................
GPIO_DATA_REGS Registers ........................................................................................
GPIO_DATA_REGS Access Type Codes ...........................................................................
GPADAT Register Field Descriptions.................................................................................
GPASET Register Field Descriptions .................................................................................
GPACLEAR Register Field Descriptions .............................................................................
GPATOGGLE Register Field Descriptions ...........................................................................
GPBDAT Register Field Descriptions.................................................................................
GPBSET Register Field Descriptions .................................................................................
GPBCLEAR Register Field Descriptions .............................................................................
GPBTOGGLE Register Field Descriptions ...........................................................................
GPCDAT Register Field Descriptions ................................................................................
GPCSET Register Field Descriptions.................................................................................
GPCCLEAR Register Field Descriptions .............................................................................
GPCTOGGLE Register Field Descriptions...........................................................................
GPDDAT Register Field Descriptions ................................................................................
GPDSET Register Field Descriptions.................................................................................
GPDCLEAR Register Field Descriptions .............................................................................
GPDTOGGLE Register Field Descriptions...........................................................................
GPEDAT Register Field Descriptions.................................................................................
GPESET Register Field Descriptions .................................................................................
GPECLEAR Register Field Descriptions .............................................................................
GPETOGGLE Register Field Descriptions ...........................................................................
GPFDAT Register Field Descriptions .................................................................................
GPFSET Register Field Descriptions .................................................................................
GPFCLEAR Register Field Descriptions .............................................................................
GPFTOGGLE Register Field Descriptions ...........................................................................
Input X-BAR Destinations ..............................................................................................
ePWM X-BAR Mux Configuration Table ............................................................................
Output X-Bar Mux Configuration Table ...............................................................................
X-BAR Base Address Table ...........................................................................................
INPUT_XBAR_REGS Registers ......................................................................................
INPUT_XBAR_REGS Access Type Codes ..........................................................................
INPUT1SELECT Register Field Descriptions........................................................................
INPUT2SELECT Register Field Descriptions........................................................................
INPUT3SELECT Register Field Descriptions........................................................................
INPUT4SELECT Register Field Descriptions........................................................................

7-106. GPFDIR Register Field Descriptions

List of Tables

1076
1078
1080
1081
1082
1083
1085
1087
1087
1089
1091
1093
1095
1097
1099
1101
1103
1105
1107
1109
1111
1113
1115
1117
1119
1121
1123
1125
1127
1129
1131
1133
1135
1139
1141
1143
1145
1146
1146
1147
1148
1149
1150

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

8-11.

INPUT5SELECT Register Field Descriptions........................................................................ 1151

8-12.

INPUT6SELECT Register Field Descriptions........................................................................ 1152

8-13.

INPUT7SELECT Register Field Descriptions........................................................................ 1153

8-14.

INPUT8SELECT Register Field Descriptions........................................................................ 1154

8-15.

INPUT9SELECT Register Field Descriptions........................................................................ 1155

8-16.

INPUT10SELECT Register Field Descriptions ...................................................................... 1156

8-17.

INPUT11SELECT Register Field Descriptions ...................................................................... 1157

8-18.

INPUT12SELECT Register Field Descriptions ...................................................................... 1158

8-19.

INPUT13SELECT Register Field Descriptions ...................................................................... 1159

8-20.

INPUT14SELECT Register Field Descriptions ...................................................................... 1160

8-21.

INPUTSELECTLOCK Register Field Descriptions .................................................................. 1161

8-22.

XBAR_REGS Registers ................................................................................................ 1165

8-23.

XBAR_REGS Access Type Codes

8-24.

XBARFLG1 Register Field Descriptions.............................................................................. 1166

8-25.

XBARFLG2 Register Field Descriptions.............................................................................. 1168

8-26.

XBARFLG3 Register Field Descriptions.............................................................................. 1170

8-27.

XBARCLR1 Register Field Descriptions

1172

8-28.

XBARCLR2 Register Field Descriptions

1174

8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
8-39.
8-40.
8-41.
8-42.
8-43.
8-44.
8-45.
8-46.
8-47.
8-48.
8-49.
8-50.
8-51.
8-52.
8-53.
8-54.
8-55.
8-56.
8-57.
8-58.
8-59.

...................................................................................

.............................................................................
.............................................................................
XBARCLR3 Register Field Descriptions .............................................................................
EPWM_XBAR_REGS Registers ......................................................................................
EPWM_XBAR_REGS Access Type Codes .........................................................................
TRIP4MUX0TO15CFG Register Field Descriptions ................................................................
TRIP4MUX16TO31CFG Register Field Descriptions...............................................................
TRIP5MUX0TO15CFG Register Field Descriptions ................................................................
TRIP5MUX16TO31CFG Register Field Descriptions...............................................................
TRIP7MUX0TO15CFG Register Field Descriptions ................................................................
TRIP7MUX16TO31CFG Register Field Descriptions...............................................................
TRIP8MUX0TO15CFG Register Field Descriptions ................................................................
TRIP8MUX16TO31CFG Register Field Descriptions...............................................................
TRIP9MUX0TO15CFG Register Field Descriptions ................................................................
TRIP9MUX16TO31CFG Register Field Descriptions...............................................................
TRIP10MUX0TO15CFG Register Field Descriptions...............................................................
TRIP10MUX16TO31CFG Register Field Descriptions .............................................................
TRIP11MUX0TO15CFG Register Field Descriptions...............................................................
TRIP11MUX16TO31CFG Register Field Descriptions .............................................................
TRIP12MUX0TO15CFG Register Field Descriptions...............................................................
TRIP12MUX16TO31CFG Register Field Descriptions .............................................................
TRIP4MUXENABLE Register Field Descriptions ...................................................................
TRIP5MUXENABLE Register Field Descriptions ...................................................................
TRIP7MUXENABLE Register Field Descriptions ...................................................................
TRIP8MUXENABLE Register Field Descriptions ...................................................................
TRIP9MUXENABLE Register Field Descriptions ...................................................................
TRIP10MUXENABLE Register Field Descriptions ..................................................................
TRIP11MUXENABLE Register Field Descriptions ..................................................................
TRIP12MUXENABLE Register Field Descriptions ..................................................................
TRIPOUTINV Register Field Descriptions ...........................................................................
TRIPLOCK Register Field Descriptions ..............................................................................
OUTPUT_XBAR_REGS Registers ...................................................................................
OUTPUT_XBAR_REGS Access Type Codes .......................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

1165

1176
1178
1178
1180
1183
1186
1189
1192
1195
1198
1201
1204
1207
1210
1213
1216
1219
1222
1225
1228
1233
1238
1243
1248
1253
1258
1263
1268
1270
1271
1271
63

www.ti.com

8-60.

OUTPUT1MUX0TO15CFG Register Field Descriptions ........................................................... 1273

8-61.

OUTPUT1MUX16TO31CFG Register Field Descriptions.......................................................... 1276

8-62.

OUTPUT2MUX0TO15CFG Register Field Descriptions ........................................................... 1279

8-63.

OUTPUT2MUX16TO31CFG Register Field Descriptions.......................................................... 1282

8-64.

OUTPUT3MUX0TO15CFG Register Field Descriptions ........................................................... 1285

8-65.

OUTPUT3MUX16TO31CFG Register Field Descriptions.......................................................... 1288

8-66.

OUTPUT4MUX0TO15CFG Register Field Descriptions ........................................................... 1291

8-67.

OUTPUT4MUX16TO31CFG Register Field Descriptions.......................................................... 1294

8-68.

OUTPUT5MUX0TO15CFG Register Field Descriptions ........................................................... 1297

8-69.

OUTPUT5MUX16TO31CFG Register Field Descriptions.......................................................... 1300

8-70.

OUTPUT6MUX0TO15CFG Register Field Descriptions ........................................................... 1303

8-71.

OUTPUT6MUX16TO31CFG Register Field Descriptions.......................................................... 1306

8-72.

OUTPUT7MUX0TO15CFG Register Field Descriptions ........................................................... 1309

8-73.

OUTPUT7MUX16TO31CFG Register Field Descriptions.......................................................... 1312

8-74.

OUTPUT8MUX0TO15CFG Register Field Descriptions ........................................................... 1315

8-75.

OUTPUT8MUX16TO31CFG Register Field Descriptions.......................................................... 1318

8-76.

OUTPUT1MUXENABLE Register Field Descriptions

1321

8-77.

OUTPUT2MUXENABLE Register Field Descriptions

1326

8-78.
8-79.
8-80.
8-81.
8-82.
8-83.
8-84.
8-85.
8-86.
8-87.
8-88.
8-89.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
64

..............................................................
..............................................................
OUTPUT3MUXENABLE Register Field Descriptions ..............................................................
OUTPUT4MUXENABLE Register Field Descriptions ..............................................................
OUTPUT5MUXENABLE Register Field Descriptions ..............................................................
OUTPUT6MUXENABLE Register Field Descriptions ..............................................................
OUTPUT7MUXENABLE Register Field Descriptions ..............................................................
OUTPUT8MUXENABLE Register Field Descriptions ..............................................................
OUTPUTLATCH Register Field Descriptions ........................................................................
OUTPUTLATCHCLR Register Field Descriptions ..................................................................
OUTPUTLATCHFRC Register Field Descriptions ..................................................................
OUTPUTLATCHENABLE Register Field Descriptions .............................................................
OUTPUTINV Register Field Descriptions ............................................................................
OUTPUTLOCK Register Field Descriptions .........................................................................
Analog Subsystem Base Address Table .............................................................................
ANALOG_SUBSYS_REGS Registers ................................................................................
ANALOG_SUBSYS_REGS Access Type Codes ...................................................................
INTOSC1TRIM Register Field Descriptions .........................................................................
INTOSC2TRIM Register Field Descriptions .........................................................................
TSNSCTL Register Field Descriptions ...............................................................................
LOCK Register Field Descriptions ....................................................................................
ANAREFTRIMA Register Field Descriptions ........................................................................
ANAREFTRIMB Register Field Descriptions ........................................................................
ANAREFTRIMC Register Field Descriptions ........................................................................
ANAREFTRIMD Register Field Descriptions ........................................................................
ADC Options and Configuration Levels ..............................................................................
Analog to 12-bit Digital Formulas .....................................................................................
Analog to 16-bit Digital Formulas .....................................................................................
12-Bit Digital-to-Analog Formulas ....................................................................................
16-Bit Digital-to-Analog Formulas ....................................................................................
Channel Selection of Input Pins .......................................................................................
Example Requirements for Multiple Signal Sampling ..............................................................
Example Connections for Multiple Signal Sampling ................................................................

List of Tables

1331
1336
1341
1346
1351
1356
1361
1363
1365
1367
1369
1371
1377
1378
1378
1379
1380
1381
1382
1383
1384
1385
1386
1389
1392
1392
1392
1392
1395
1397
1397

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

10-9.

DETECTCFG Settings .................................................................................................. 1407

10-10. ADC Timings in 12-bit Mode (SYSCLK Cycles) ..................................................................... 1412
10-11. ADC Timings in 16-bit Mode ........................................................................................... 1413
10-12. ADC Base Address Table .............................................................................................. 1421
10-13. ADC_REGS Registers .................................................................................................. 1422
10-14. ADC_REGS Access Type Codes ..................................................................................... 1423

...............................................................................
...............................................................................
ADCBURSTCTL Register Field Descriptions ........................................................................
ADCINTFLG Register Field Descriptions ............................................................................
ADCINTFLGCLR Register Field Descriptions .......................................................................
ADCINTOVF Register Field Descriptions ............................................................................
ADCINTOVFCLR Register Field Descriptions .......................................................................
ADCINTSEL1N2 Register Field Descriptions........................................................................
ADCINTSEL3N4 Register Field Descriptions........................................................................
ADCSOCPRICTL Register Field Descriptions ......................................................................
ADCINTSOCSEL1 Register Field Descriptions .....................................................................
ADCINTSOCSEL2 Register Field Descriptions .....................................................................
ADCSOCFLG1 Register Field Descriptions .........................................................................
ADCSOCFRC1 Register Field Descriptions .........................................................................
ADCSOCOVF1 Register Field Descriptions .........................................................................
ADCSOCOVFCLR1 Register Field Descriptions ....................................................................
ADCSOC0CTL Register Field Descriptions .........................................................................
ADCSOC1CTL Register Field Descriptions .........................................................................
ADCSOC2CTL Register Field Descriptions .........................................................................
ADCSOC3CTL Register Field Descriptions .........................................................................
ADCSOC4CTL Register Field Descriptions .........................................................................
ADCSOC5CTL Register Field Descriptions .........................................................................
ADCSOC6CTL Register Field Descriptions .........................................................................
ADCSOC7CTL Register Field Descriptions .........................................................................
ADCSOC8CTL Register Field Descriptions .........................................................................
ADCSOC9CTL Register Field Descriptions .........................................................................
ADCSOC10CTL Register Field Descriptions ........................................................................
ADCSOC11CTL Register Field Descriptions ........................................................................
ADCSOC12CTL Register Field Descriptions ........................................................................
ADCSOC13CTL Register Field Descriptions ........................................................................
ADCSOC14CTL Register Field Descriptions ........................................................................
ADCSOC15CTL Register Field Descriptions ........................................................................
ADCEVTSTAT Register Field Descriptions ..........................................................................
ADCEVTCLR Register Field Descriptions ...........................................................................
ADCEVTSEL Register Field Descriptions............................................................................
ADCEVTINTSEL Register Field Descriptions .......................................................................
ADCCOUNTER Register Field Descriptions.........................................................................
ADCREV Register Field Descriptions ................................................................................
ADCOFFTRIM Register Field Descriptions ..........................................................................
ADCPPB1CONFIG Register Field Descriptions.....................................................................
ADCPPB1STAMP Register Field Descriptions ......................................................................
ADCPPB1OFFCAL Register Field Descriptions ....................................................................
ADCPPB1OFFREF Register Field Descriptions ....................................................................

10-15. ADCCTL1 Register Field Descriptions

1425

10-16. ADCCTL2 Register Field Descriptions

1427

10-17.

1428

10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
10-51.
10-52.
10-53.
10-54.
10-55.
10-56.
10-57.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

1430
1432
1434
1436
1437
1439
1441
1444
1446
1448
1453
1458
1462
1466
1469
1472
1475
1478
1481
1484
1487
1490
1493
1496
1499
1502
1505
1508
1511
1514
1516
1518
1520
1522
1523
1524
1525
1527
1528
1529
65

www.ti.com

10-58. ADCPPB1TRIPHI Register Field Descriptions ...................................................................... 1530
10-59. ADCPPB1TRIPLO Register Field Descriptions ..................................................................... 1531
10-60. ADCPPB2CONFIG Register Field Descriptions..................................................................... 1532
10-61. ADCPPB2STAMP Register Field Descriptions ...................................................................... 1534
10-62. ADCPPB2OFFCAL Register Field Descriptions

....................................................................

1535

10-63. ADCPPB2OFFREF Register Field Descriptions .................................................................... 1536
10-64. ADCPPB2TRIPHI Register Field Descriptions ...................................................................... 1537
10-65. ADCPPB2TRIPLO Register Field Descriptions ..................................................................... 1538
10-66. ADCPPB3CONFIG Register Field Descriptions..................................................................... 1539
10-67. ADCPPB3STAMP Register Field Descriptions ...................................................................... 1541

....................................................................
10-69. ADCPPB3OFFREF Register Field Descriptions ....................................................................
10-70. ADCPPB3TRIPHI Register Field Descriptions ......................................................................
10-71. ADCPPB3TRIPLO Register Field Descriptions .....................................................................
10-72. ADCPPB4CONFIG Register Field Descriptions.....................................................................
10-73. ADCPPB4STAMP Register Field Descriptions ......................................................................
10-74. ADCPPB4OFFCAL Register Field Descriptions ....................................................................
10-75. ADCPPB4OFFREF Register Field Descriptions ....................................................................
10-76. ADCPPB4TRIPHI Register Field Descriptions ......................................................................
10-77. ADCPPB4TRIPLO Register Field Descriptions .....................................................................
10-78. ADCINLTRIM1 Register Field Descriptions ..........................................................................
10-79. ADCINLTRIM2 Register Field Descriptions ..........................................................................
10-80. ADCINLTRIM3 Register Field Descriptions ..........................................................................
10-81. ADCINLTRIM4 Register Field Descriptions ..........................................................................
10-82. ADCINLTRIM5 Register Field Descriptions ..........................................................................
10-83. ADCINLTRIM6 Register Field Descriptions ..........................................................................
10-84. ADC_RESULT_REGS Registers......................................................................................
10-85. ADC_RESULT_REGS Access Type Codes .........................................................................
10-86. ADCRESULT0 Register Field Descriptions ..........................................................................
10-87. ADCRESULT1 Register Field Descriptions ..........................................................................
10-88. ADCRESULT2 Register Field Descriptions ..........................................................................
10-89. ADCRESULT3 Register Field Descriptions ..........................................................................
10-90. ADCRESULT4 Register Field Descriptions ..........................................................................
10-91. ADCRESULT5 Register Field Descriptions ..........................................................................
10-92. ADCRESULT6 Register Field Descriptions ..........................................................................
10-93. ADCRESULT7 Register Field Descriptions ..........................................................................
10-94. ADCRESULT8 Register Field Descriptions ..........................................................................
10-95. ADCRESULT9 Register Field Descriptions ..........................................................................
10-96. ADCRESULT10 Register Field Descriptions ........................................................................
10-97. ADCRESULT11 Register Field Descriptions ........................................................................
10-98. ADCRESULT12 Register Field Descriptions ........................................................................
10-99. ADCRESULT13 Register Field Descriptions ........................................................................
10-100. ADCRESULT14 Register Field Descriptions .......................................................................
10-101. ADCRESULT15 Register Field Descriptions .......................................................................
10-102. ADCPPB1RESULT Register Field Descriptions ...................................................................
10-103. ADCPPB2RESULT Register Field Descriptions ...................................................................
10-104. ADCPPB3RESULT Register Field Descriptions ...................................................................
10-105. ADCPPB4RESULT Register Field Descriptions ...................................................................
11-1. DAC Base Address Table ..............................................................................................
10-68. ADCPPB3OFFCAL Register Field Descriptions

66

List of Tables

1542
1543
1544
1545
1546
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1560
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1583

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

11-2.

DAC_REGS Registers .................................................................................................. 1584

11-3.

DAC_REGS Access Type Codes ..................................................................................... 1584

11-4.

DACREV Register Field Descriptions

11-5.

DACCTL Register Field Descriptions ................................................................................. 1586

11-6.

DACVALA Register Field Descriptions ............................................................................... 1587

11-7.

DACVALS Register Field Descriptions ............................................................................... 1588

11-8.

DACOUTEN Register Field Descriptions

11-9.

DACLOCK Register Field Descriptions............................................................................... 1590

................................................................................

............................................................................

...............................................................................
CMPSS Base Address Table ..........................................................................................
CMPSS_REGS Registers ..............................................................................................
CMPSS_REGS Access Type Codes .................................................................................
COMPCTL Register Field Descriptions ..............................................................................
COMPHYSCTL Register Field Descriptions .........................................................................
COMPSTS Register Field Descriptions ..............................................................................
COMPSTSCLR Register Field Descriptions .........................................................................
COMPDACCTL Register Field Descriptions .........................................................................
DACHVALS Register Field Descriptions .............................................................................
DACHVALA Register Field Descriptions .............................................................................
RAMPMAXREFA Register Field Descriptions .......................................................................
RAMPMAXREFS Register Field Descriptions .......................................................................
RAMPDECVALA Register Field Descriptions .......................................................................
RAMPDECVALS Register Field Descriptions .......................................................................
RAMPSTS Register Field Descriptions...............................................................................
DACLVALS Register Field Descriptions..............................................................................
DACLVALA Register Field Descriptions..............................................................................
RAMPDLYA Register Field Descriptions .............................................................................
RAMPDLYS Register Field Descriptions .............................................................................
CTRIPLFILCTL Register Field Descriptions .........................................................................
CTRIPLFILCLKCTL Register Field Descriptions ....................................................................
CTRIPHFILCTL Register Field Descriptions.........................................................................
CTRIPHFILCLKCTL Register Field Descriptions ...................................................................
COMPLOCK Register Field Descriptions ............................................................................
Modulator Clock Modes ................................................................................................
Peak Data Values for Different OSR/Filter Combinations .........................................................
Peak Data Values for Different DOSR/Filter Combinations .......................................................
Number of Incorrect Samples Tabulated .............................................................................
Shift Control Bit Configuration Settings ..............................................................................
General Registers .......................................................................................................
Filter 1 Registers ........................................................................................................
Filter 2 Registers ........................................................................................................
Filter 3 Registers ........................................................................................................
Filter 4 Registers ........................................................................................................
SDFM Base Address Table ............................................................................................
SDFM_REGS Registers ................................................................................................
SDFM_REGS Access Type Codes ...................................................................................
SDIFLG Register Field Descriptions ..................................................................................
SDIFLGCLR Register Field Descriptions ............................................................................
SDCTL Register Field Descriptions ...................................................................................

11-10. DACTRIM Register Field Descriptions
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

1585

1589
1591
1598
1599
1599
1601
1603
1604
1605
1606
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1628
1630
1631
1632
1633
1636
1636
1636
1636
1637
1637
1638
1638
1640
1642
1644
67

www.ti.com

13-17. SDMFILEN Register Field Descriptions .............................................................................. 1645
13-18. SDCTLPARM1 Register Field Descriptions

.........................................................................

1646

13-19. SDDFPARM1 Register Field Descriptions ........................................................................... 1647
13-20. SDDPARM1 Register Field Descriptions ............................................................................. 1648
13-21. SDCMPH1 Register Field Descriptions

..............................................................................

1649

13-22. SDCMPL1 Register Field Descriptions ............................................................................... 1650
13-23. SDCPARM1 Register Field Descriptions ............................................................................. 1651
13-24. SDDATA1 Register Field Descriptions ............................................................................... 1652

.........................................................................
SDDFPARM2 Register Field Descriptions ...........................................................................
SDDPARM2 Register Field Descriptions .............................................................................
SDCMPH2 Register Field Descriptions ..............................................................................
SDCMPL2 Register Field Descriptions ...............................................................................
SDCPARM2 Register Field Descriptions .............................................................................
SDDATA2 Register Field Descriptions ...............................................................................
SDCTLPARM3 Register Field Descriptions .........................................................................
SDDFPARM3 Register Field Descriptions ...........................................................................
SDDPARM3 Register Field Descriptions .............................................................................
SDCMPH3 Register Field Descriptions ..............................................................................
SDCMPL3 Register Field Descriptions ...............................................................................
SDCPARM3 Register Field Descriptions .............................................................................
SDDATA3 Register Field Descriptions ...............................................................................
SDCTLPARM4 Register Field Descriptions .........................................................................
SDDFPARM4 Register Field Descriptions ...........................................................................
SDDPARM4 Register Field Descriptions .............................................................................
SDCMPH4 Register Field Descriptions ..............................................................................
SDCMPL4 Register Field Descriptions ...............................................................................
SDCPARM4 Register Field Descriptions .............................................................................
SDDATA4 Register Field Descriptions ...............................................................................
Submodule Configuration Parameters................................................................................
Key Time-Base Signals .................................................................................................
Action-Qualifier Submodule Possible Input Events .................................................................
Action-Qualifier Event Priority for Up-Down-Count Mode ..........................................................
Action-Qualifier Event Priority for Up-Count Mode..................................................................
Action-Qualifier Event Priority for Down-Count Mode ..............................................................
Behavior if CMPA/CMPB is Greater than the Period ...............................................................
Classical Dead-Band Operating Modes .............................................................................
Additional Dead-Band Operating Modes .............................................................................
Dead-Band Delay Values in μS as a Function of DBFED and DBRED .........................................
Possible Pulse Width Values for EPWMCLK = 80 MHz ...........................................................
Possible Actions On a Trip Event .....................................................................................
EPWM Base Address Table ...........................................................................................
EPWM_REGS Registers ...............................................................................................
EPWM_REGS Access Type Codes ..................................................................................
TBCTL Register Field Descriptions ...................................................................................
TBCTL2 Register Field Descriptions..................................................................................
EPWMSYNCINSEL Register Field Descriptions ....................................................................
TBCTR Register Field Descriptions ...................................................................................
TBSTS Register Field Descriptions ...................................................................................

13-25. SDCTLPARM2 Register Field Descriptions
13-26.
13-27.
13-28.
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
13-38.
13-39.
13-40.
13-41.
13-42.
13-43.
13-44.
13-45.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
68

List of Tables

1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1682
1685
1703
1705
1705
1705
1706
1718
1718
1720
1723
1727
1763
1764
1766
1767
1770
1771
1772
1773

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

14-21. EPWMSYNCOUTEN Register Field Descriptions .................................................................. 1774
14-22. CMPCTL Register Field Descriptions................................................................................. 1776
14-23. CMPCTL2 Register Field Descriptions ............................................................................... 1778
14-24. DBCTL Register Field Descriptions ................................................................................... 1780
14-25. DBCTL2 Register Field Descriptions ................................................................................. 1783
14-26. AQCTL Register Field Descriptions ................................................................................... 1784
14-27. AQTSRCSEL Register Field Descriptions ........................................................................... 1786
14-28. PCCTL Register Field Descriptions ................................................................................... 1787
14-29. VCAPCTL Register Field Descriptions ............................................................................... 1789
14-30. VCNTCFG Register Field Descriptions............................................................................... 1791
14-31. HRCNFG Register Field Descriptions ................................................................................ 1793

.................................................................................
..............................................................................
HRCNFG2 Register Field Descriptions...............................................................................
HRPCTL Register Field Descriptions .................................................................................
TRREM Register Field Descriptions ..................................................................................
GLDCTL Register Field Descriptions .................................................................................
GLDCFG Register Field Descriptions ................................................................................
EPWMXLINK Register Field Descriptions ...........................................................................
EPWMREV Register Field Descriptions ..............................................................................
AQCTLA Register Field Descriptions .................................................................................
AQCTLA2 Register Field Descriptions ...............................................................................
AQCTLB Register Field Descriptions .................................................................................
AQCTLB2 Register Field Descriptions ...............................................................................
AQSFRC Register Field Descriptions ................................................................................
AQCSFRC Register Field Descriptions ..............................................................................
DBREDHR Register Field Descriptions ..............................................................................
DBRED Register Field Descriptions ..................................................................................
DBFEDHR Register Field Descriptions...............................................................................
DBFED Register Field Descriptions ..................................................................................
TBPHS Register Field Descriptions ...................................................................................
TBPRDHR Register Field Descriptions...............................................................................
TBPRD Register Field Descriptions ..................................................................................
CMPA Register Field Descriptions ....................................................................................
CMPB Register Field Descriptions ....................................................................................
CMPC Register Field Descriptions ....................................................................................
CMPD Register Field Descriptions ....................................................................................
GLDCTL2 Register Field Descriptions ...............................................................................
SWVDELVAL Register Field Descriptions ...........................................................................
TZSEL Register Field Descriptions ...................................................................................
TZDCSEL Register Field Descriptions ...............................................................................
TZCTL Register Field Descriptions ...................................................................................
TZCTL2 Register Field Descriptions ..................................................................................
TZCTLDCA Register Field Descriptions..............................................................................
TZCTLDCB Register Field Descriptions..............................................................................
TZEINT Register Field Descriptions ..................................................................................
TZFLG Register Field Descriptions ...................................................................................
TZCBCFLG Register Field Descriptions .............................................................................
TZOSTFLG Register Field Descriptions..............................................................................

14-32. HRPWR Register Field Descriptions

1795

14-33. HRMSTEP Register Field Descriptions

1796

14-34.

1797

14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

1798
1800
1801
1803
1805
1809
1810
1812
1814
1816
1818
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1836
1838
1840
1842
1844
1846
1847
1849
1851
69

www.ti.com

14-70. TZCLR Register Field Descriptions ................................................................................... 1853
14-71. TZCBCCLR Register Field Descriptions ............................................................................. 1855
14-72. TZOSTCLR Register Field Descriptions

.............................................................................

1857

14-73. TZFRC Register Field Descriptions ................................................................................... 1859
14-74. ETSEL Register Field Descriptions ................................................................................... 1860
14-75. ETPS Register Field Descriptions..................................................................................... 1863
14-76. ETFLG Register Field Descriptions ................................................................................... 1866
14-77. ETCLR Register Field Descriptions ................................................................................... 1867
14-78. ETFRC Register Field Descriptions ................................................................................... 1868
14-79. ETINTPS Register Field Descriptions ................................................................................ 1869
14-80. ETSOCPS Register Field Descriptions ............................................................................... 1870
14-81. ETCNTINITCTL Register Field Descriptions

........................................................................

1872

14-82. ETCNTINIT Register Field Descriptions.............................................................................. 1873

............................................................................
14-84. DCACTL Register Field Descriptions .................................................................................
14-85. DCBCTL Register Field Descriptions .................................................................................
14-86. DCFCTL Register Field Descriptions .................................................................................
14-87. DCCAPCTL Register Field Descriptions .............................................................................
14-88. DCFOFFSET Register Field Descriptions ...........................................................................
14-89. DCFOFFSETCNT Register Field Descriptions ......................................................................
14-90. DCFWINDOW Register Field Descriptions ..........................................................................
14-91. DCFWINDOWCNT Register Field Descriptions .....................................................................
14-92. DCCAP Register Field Descriptions ..................................................................................
14-93. DCAHTRIPSEL Register Field Descriptions .........................................................................
14-94. DCALTRIPSEL Register Field Descriptions .........................................................................
14-95. DCBHTRIPSEL Register Field Descriptions .........................................................................
14-96. DCBLTRIPSEL Register Field Descriptions .........................................................................
14-97. EPWMLOCK Register Field Descriptions ............................................................................
14-98. HWVDELVAL Register Field Descriptions ...........................................................................
14-99. VCNTVAL Register Field Descriptions ...............................................................................
14-100. EPWM_XBAR_REGS Registers .....................................................................................
14-101. EPWM_XBAR_REGS Access Type Codes ........................................................................
14-102. TRIP4MUX0TO15CFG Register Field Descriptions ...............................................................
14-103. TRIP4MUX16TO31CFG Register Field Descriptions .............................................................
14-104. TRIP5MUX0TO15CFG Register Field Descriptions ...............................................................
14-105. TRIP5MUX16TO31CFG Register Field Descriptions .............................................................
14-106. TRIP7MUX0TO15CFG Register Field Descriptions ...............................................................
14-107. TRIP7MUX16TO31CFG Register Field Descriptions .............................................................
14-108. TRIP8MUX0TO15CFG Register Field Descriptions ...............................................................
14-109. TRIP8MUX16TO31CFG Register Field Descriptions .............................................................
14-110. TRIP9MUX0TO15CFG Register Field Descriptions ...............................................................
14-111. TRIP9MUX16TO31CFG Register Field Descriptions .............................................................
14-112. TRIP10MUX0TO15CFG Register Field Descriptions .............................................................
14-113. TRIP10MUX16TO31CFG Register Field Descriptions ............................................................
14-114. TRIP11MUX0TO15CFG Register Field Descriptions .............................................................
14-115. TRIP11MUX16TO31CFG Register Field Descriptions ............................................................
14-116. TRIP12MUX0TO15CFG Register Field Descriptions .............................................................
14-117. TRIP12MUX16TO31CFG Register Field Descriptions ............................................................
14-118. TRIP4MUXENABLE Register Field Descriptions ..................................................................
14-83. DCTRIPSEL Register Field Descriptions

70

List of Tables

1874
1876
1878
1880
1881
1883
1884
1885
1886
1887
1888
1890
1892
1894
1896
1898
1899
1900
1900
1902
1905
1908
1911
1914
1917
1920
1923
1926
1929
1932
1935
1938
1941
1944
1947
1950

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

14-119. TRIP5MUXENABLE Register Field Descriptions .................................................................. 1955
14-120. TRIP7MUXENABLE Register Field Descriptions .................................................................. 1960
14-121. TRIP8MUXENABLE Register Field Descriptions .................................................................. 1965
14-122. TRIP9MUXENABLE Register Field Descriptions .................................................................. 1970

................................................................
................................................................
14-125. TRIP12MUXENABLE Register Field Descriptions ................................................................
14-126. TRIPOUTINV Register Field Descriptions ..........................................................................
14-127. TRIPLOCK Register Field Descriptions .............................................................................
14-128. SYNC_SOC_REGS Registers .......................................................................................
14-129. SYNC_SOC_REGS Access Type Codes ..........................................................................
14-130. SYNCSELECT Register Field Descriptions ........................................................................
14-131. ADCSOCOUTSELECT Register Field Descriptions ..............................................................
14-132. SYNCSOCLOCK Register Field Descriptions......................................................................
15-1. Resolution for PWM and HRPWM ....................................................................................
15-2. Relationship Between MEP Steps, PWM Frequency and Resolution ............................................
15-3. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right).......................................................
15-4. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles ..............................................
15-5. SFO Library Features ...................................................................................................
15-6. Factor Values ............................................................................................................
16-1. eCAP Base Address Table ............................................................................................
16-2. ECAP_REGS Registers ................................................................................................
16-3. ECAP_REGS Access Type Codes ...................................................................................
16-4. TSCTR Register Field Descriptions ...................................................................................
16-5. CTRPHS Register Field Descriptions.................................................................................
16-6. CAP1 Register Field Descriptions.....................................................................................
16-7. CAP2 Register Field Descriptions.....................................................................................
16-8. CAP3 Register Field Descriptions.....................................................................................
16-9. CAP4 Register Field Descriptions.....................................................................................
16-10. ECCTL1 Register Field Descriptions .................................................................................
16-11. ECCTL2 Register Field Descriptions .................................................................................
16-12. ECEINT Register Field Descriptions ..................................................................................
16-13. ECFLG Register Field Descriptions ...................................................................................
16-14. ECCLR Register Field Descriptions ..................................................................................
16-15. ECFRC Register Field Descriptions ..................................................................................
17-1. EQEP Memory Map ....................................................................................................
17-2. Quadrature Decoder Truth Table .....................................................................................
17-3. eQEP Base Address Table ............................................................................................
17-4. EQEP_REGS Registers ................................................................................................
17-5. EQEP_REGS Access Type Codes ...................................................................................
17-6. QPOSCNT Register Field Descriptions ..............................................................................
17-7. QPOSINIT Register Field Descriptions ...............................................................................
17-8. QPOSMAX Register Field Descriptions ..............................................................................
17-9. QPOSCMP Register Field Descriptions ..............................................................................
17-10. QPOSILAT Register Field Descriptions ..............................................................................
17-11. QPOSSLAT Register Field Descriptions .............................................................................
17-12. QPOSLAT Register Field Descriptions ...............................................................................
17-13. QUTMR Register Field Descriptions ..................................................................................
17-14. QUPRD Register Field Descriptions ..................................................................................
14-123. TRIP10MUXENABLE Register Field Descriptions

1975

14-124. TRIP11MUXENABLE Register Field Descriptions

1980

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

1985
1990
1992
1993
1993
1994
1997
2000
2003
2009
2010
2013
2025
2026
2050
2051
2051
2052
2053
2054
2055
2056
2057
2058
2060
2062
2064
2066
2067
2073
2075
2089
2090
2090
2092
2093
2094
2095
2096
2097
2098
2099
2100
71

www.ti.com

17-15. QWDTMR Register Field Descriptions ............................................................................... 2101
17-16. QWDPRD Register Field Descriptions

...............................................................................

2102

17-17. QDECCTL Register Field Descriptions ............................................................................... 2103
17-18. QEPCTL Register Field Descriptions ................................................................................. 2105
17-19. QCAPCTL Register Field Descriptions ............................................................................... 2108
17-20. QPOSCTL Register Field Descriptions ............................................................................... 2109
17-21. QEINT Register Field Descriptions

...................................................................................

2110

17-22. QFLG Register Field Descriptions .................................................................................... 2112
17-23. QCLR Register Field Descriptions .................................................................................... 2114
17-24. QFRC Register Field Descriptions .................................................................................... 2116
17-25. QEPSTS Register Field Descriptions ................................................................................. 2118
17-26. QCTMR Register Field Descriptions .................................................................................. 2120
17-27. QCPRD Register Field Descriptions .................................................................................. 2121
17-28. QCTMRLAT Register Field Descriptions ............................................................................. 2122
17-29. QCPRDLAT Register Field Descriptions ............................................................................. 2123
18-1.

SPI Module Signal Summary .......................................................................................... 2126

18-2.

High-Speed SPI Capable GPIOs ...................................................................................... 2127

18-3.

SPI Interrupt Flag Modes ............................................................................................... 2129

18-4.

SPI Clocking Scheme Selection Guide ............................................................................... 2135

18-5.

4-wire vs. 3-wire SPI Pin Functions ................................................................................... 2138

18-6.

3-Wire SPI Pin Configuration .......................................................................................... 2139

18-7.

SPI Base Address Table ............................................................................................... 2144

18-8.

SPI_REGS Registers ................................................................................................... 2145

18-9.

SPI_REGS Access Type Codes

18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
72

......................................................................................
SPICCR Register Field Descriptions .................................................................................
SPICTL Register Field Descriptions ..................................................................................
SPISTS Register Field Descriptions ..................................................................................
SPIBRR Register Field Descriptions..................................................................................
SPIRXEMU Register Field Descriptions..............................................................................
SPIRXBUF Register Field Descriptions ..............................................................................
SPITXBUF Register Field Descriptions ..............................................................................
SPIDAT Register Field Descriptions ..................................................................................
SPIFFTX Register Field Descriptions.................................................................................
SPIFFRX Register Field Descriptions ................................................................................
SPIFFCT Register Field Descriptions ................................................................................
SPIPRI Register Field Descriptions ...................................................................................
SCI Module Signal Summary ..........................................................................................
Programming the Data Format Using SCICCR .....................................................................
Asynchronous Baud Register Values for Common SCI Bit Rates ................................................
SCI Interrupt Flags ......................................................................................................
SCI Base Address Table ...............................................................................................
SCI_REGS Registers ...................................................................................................
SCI_REGS Access Type Codes ......................................................................................
SCICCR Register Field Descriptions .................................................................................
SCICTL1 Register Field Descriptions.................................................................................
SCIHBAUD Register Field Descriptions ..............................................................................
SCILBAUD Register Field Descriptions ..............................................................................
SCICTL2 Register Field Descriptions.................................................................................
SCIRXST Register Field Descriptions ................................................................................

List of Tables

2145
2146
2148
2150
2152
2153
2154
2155
2156
2157
2159
2161
2162
2167
2168
2174
2176
2178
2179
2179
2180
2182
2184
2185
2186
2188

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

.............................................................................
SCIRXBUF Register Field Descriptions ..............................................................................
SCITXBUF Register Field Descriptions ..............................................................................
SCIFFTX Register Field Descriptions ................................................................................
SCIFFRX Register Field Descriptions ................................................................................
SCIFFCT Register Field Descriptions ................................................................................
SCIPRI Register Field Descriptions ...................................................................................
Dependency of Delay d on the Divide-Down Value IPSC .........................................................
Operating Modes of the I2C Module ..................................................................................
Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR ..............
How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR ...........................
Ways to Generate a NACK Bit ........................................................................................
Descriptions of the Basic I2C Interrupt Requests ...................................................................
I2C Base Address Table ...............................................................................................
I2C_REGS Registers ...................................................................................................
I2C_REGS Access Type Codes.......................................................................................
I2COAR Register Field Descriptions..................................................................................
I2CIER Register Field Descriptions ...................................................................................
I2CSTR Register Field Descriptions ..................................................................................
I2CCLKL Register Field Descriptions .................................................................................
I2CCLKH Register Field Descriptions ................................................................................
I2CCNT Register Field Descriptions ..................................................................................
I2CDRR Register Field Descriptions..................................................................................
I2CSAR Register Field Descriptions ..................................................................................
I2CDXR Register Field Descriptions ..................................................................................
I2CMDR Register Field Descriptions .................................................................................
I2CISRC Register Field Descriptions .................................................................................
I2CEMDR Register Field Descriptions ...............................................................................
I2CPSC Register Field Descriptions ..................................................................................
I2CFFTX Register Field Descriptions .................................................................................
I2CFFRX Register Field Descriptions ................................................................................
McBSP Interface Pins/Signals .........................................................................................
Register Bits That Determine the Number of Phases, Words, and Bits .........................................
Interrupts and DMA Events Generated by a McBSP ...............................................................
Effects of DLB and CLKSTP on Clock Modes.......................................................................
Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits ..............
Polarity Options for the Input to the Sample Rate Generator ....................................................
Input Clock Selection for Sample Rate Generator ..................................................................
Block - Channel Assignment ...........................................................................................
2-Partition Mode .........................................................................................................
8-Partition mode .........................................................................................................
Receive Channel Assignment and Control With Eight Receive Partitions .......................................
Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used .......................
Selecting a Transmit Multichannel Selection Mode With the XMCM Bits........................................
Bits Used to Enable and Configure the Clock Stop Mode .........................................................
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme .................................................
Bit Values Required to Configure the McBSP as an SPI Master ................................................
Bit Values Required to Configure the McBSP as an SPI Slave ...................................................
Register Bits Used to Reset or Enable the McBSP Receiver Field Descriptions ...............................

19-14. SCIRXEMU Register Field Descriptions

2190

19-15.

2191

19-16.
19-17.
19-18.
19-19.
19-20.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

2192
2193
2195
2197
2198
2203
2205
2205
2207
2208
2211
2214
2215
2215
2216
2217
2218
2223
2224
2225
2226
2227
2228
2229
2233
2234
2235
2236
2238
2241
2248
2252
2254
2254
2255
2258
2267
2268
2268
2270
2271
2272
2275
2276
2279
2280
2282
73

www.ti.com

21-19. Reset State of Each McBSP Pin ...................................................................................... 2282
21-20. Register Bit Used to Enable/Disable the Digital Loopback Mode ................................................. 2283
21-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode .................................... 2283
21-22. Register Bits Used to Enable/Disable the Clock Stop Mode ...................................................... 2283
21-23. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme ................................................. 2284
21-24. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode ............................... 2284
21-25. Register Bit Used to Choose One or Two Phases for the Receive Frame ...................................... 2284
21-26. Register Bits Used to Set the Receive Word Length(s) ............................................................ 2285
21-27. Register Bits Used to Set the Receive Frame Length .............................................................. 2285
21-28. How to Calculate the Length of the Receive Frame ................................................................ 2286
21-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function .................. 2286
21-30. Register Bits Used to Set the Receive Companding Mode ........................................................ 2287
21-31. Register Bits Used to Set the Receive Data Delay ................................................................. 2288
21-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode................................. 2290
21-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh..................................................... 2290
21-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh ................................................. 2290
21-35. Register Bits Used to Set the Receive Interrupt Mode ............................................................. 2291
21-36. Register Bits Used to Set the Receive Frame Synchronization Mode

..........................................

2291

21-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect on the FSR Pin..... 2292
21-38. Register Bit Used to Set Receive Frame-Synchronization Polarity ............................................... 2293
21-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width ......................... 2294
21-40. Register Bits Used to Set the Receive Clock Mode

...............................................................

2295

21-41. Receive Clock Signal Source Selection .............................................................................. 2296
21-42. Register Bit Used to Set Receive Clock Polarity .................................................................... 2296
21-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value ..................... 2298
2298

21-45.

2299

21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
21-54.
21-55.
21-56.
21-57.
21-58.
21-59.
21-60.
21-61.
21-62.
21-63.
21-64.
21-65.
21-66.
21-67.
74

.................................................
Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock) ......................................
Register Bits Used to Set the SRG Input Clock Polarity ...........................................................
Register Bits Used to Place Transmitter in Reset Field Descriptions ............................................
Register Bit Used to Enable/Disable the Digital Loopback Mode .................................................
Receive Signals Connected to Transmit Signals in Digital Loopback Mode ....................................
Register Bits Used to Enable/Disable the Clock Stop Mode ......................................................
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme .................................................
Register Bits Used to Enable/Disable Transmit Multichannel Selection .........................................
Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame ............................................
Register Bits Used to Set the Transmit Word Length(s) ...........................................................
Register Bits Used to Set the Transmit Frame Length .............................................................
How to Calculate Frame Length .......................................................................................
Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore Function .................
Register Bits Used to Set the Transmit Companding Mode .......................................................
Register Bits Used to Set the Transmit Data Delay ................................................................
Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode ......................................
Register Bits Used to Set the Transmit Interrupt Mode ............................................................
Register Bits Used to Set the Transmit Frame-Synchronization Mode ..........................................
How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses .......................
Register Bit Used to Set Transmit Frame-Synchronization Polarity ..............................................
Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width ..............................
Register Bit Used to Set the Transmit Clock Mode .................................................................
How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX pin .........

21-44. Register Bit Used to Set the SRG Clock Synchronization Mode

List of Tables

2300
2301
2302
2302
2302
2303
2304
2305
2305
2306
2306
2307
2308
2309
2311
2311
2312
2312
2313
2314
2315
2315

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

21-68. Register Bit Used to Set Transmit Clock Polarity ................................................................... 2315
21-69. McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2.................................... 2317
21-70. Reset State of Each McBSP Pin ...................................................................................... 2317

..............................................................................
Transmit Interrupt Sources and Signals ..............................................................................
Error Flags ...............................................................................................................
McBSP Mode Selection ................................................................................................
McBSP Base Address Table...........................................................................................
McBSP Register Summary.............................................................................................
Serial Port Control 1 Register (SPCR1) Field Descriptions .......................................................
Serial Port Control 2 Register (SPCR2) Field Descriptions........................................................
Receive Control Register 1 (RCR1) Field Descriptions ............................................................
Frame Length Formula for Receive Control 1 Register (RCR1) ..................................................
Receive Control Register 2 (RCR2) Field Descriptions ............................................................
Frame Length Formula for Receive Control 2 Register (RCR2) ..................................................
Transmit Control 1 Register (XCR1) Field Descriptions ...........................................................
Frame Length Formula for Transmit Control 1 Register (XCR1) .................................................
Transmit Control 2 Register (XCR2) Field Descriptions ...........................................................
Frame Length Formula for Transmit Control 2 Register (XCR2) .................................................
Sample Rate Generator 1 Register (SRGR1) Field Descriptions .................................................
Sample Rate Generator 2 Register (SRGR2) Field Descriptions .................................................
Multichannel Control 1 Register (MCR1) Field Descriptions ......................................................
Multichannel Control 2 Register (MCR2) Field Descriptions ......................................................
Pin Control Register (PCR) Field Descriptions ......................................................................
Pin Configuration .......................................................................................................
Receive Channel Enable Registers (RCERA...RCERH) Field Descriptions.....................................
Use of the Receive Channel Enable Registers .....................................................................
Transmit Channel Enable Registers (XCERA...XCERH) Field Descriptions ....................................
Use of the Transmit Channel Enable Registers ....................................................................
McBSP Interrupt Enable Register (MFFINT) Field Descriptions ..................................................
CAN Register Access From Software ................................................................................
CAN Register Access From CCS .....................................................................................
PIE Nomenclature for Interrupts .......................................................................................
Programmable Ranges Required by CAN Protocol ................................................................
Message Object Field Descriptions ...................................................................................
Message RAM Addressing in Debug Mode .........................................................................
CAN Base Addresses Table ...........................................................................................
CAN_REGS Registers ..................................................................................................
CAN_REGS Access Type Codes .....................................................................................
CAN_CTL Register Field Descriptions ...............................................................................
CAN_ES Register Field Descriptions .................................................................................
CAN_ERRC Register Field Descriptions .............................................................................
CAN_BTR Register Field Descriptions ...............................................................................
CAN_INT Register Field Descriptions ................................................................................
CAN_TEST Register Field Descriptions..............................................................................
CAN_PERR Register Field Descriptions .............................................................................
CAN_RAM_INIT Register Field Descriptions ........................................................................
CAN_GLB_INT_EN Register Field Descriptions ....................................................................
CAN_GLB_INT_FLG Register Field Descriptions ..................................................................

21-71. Receive Interrupt Sources and Signals
21-72.
21-73.
21-74.
21-75.
21-76.
21-77.
21-78.
21-79.
21-80.
21-81.
21-82.
21-83.
21-84.
21-85.
21-86.
21-87.
21-88.
21-89.
21-90.
21-91.
21-92.
21-93.
21-94.
21-95.
21-96.
21-97.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

2322
2322
2323
2323
2325
2325
2327
2330
2332
2333
2333
2334
2335
2335
2336
2337
2338
2339
2340
2342
2344
2346
2346
2347
2348
2349
2350
2354
2355
2361
2369
2378
2381
2383
2384
2385
2386
2389
2391
2392
2394
2395
2397
2398
2399
2400
75

www.ti.com

22-20. CAN_GLB_INT_CLR Register Field Descriptions .................................................................. 2401
22-21. CAN_ABOTR Register Field Descriptions ........................................................................... 2402
22-22. CAN_TXRQ_X Register Field Descriptions .......................................................................... 2403
2404

22-24.

2405

22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
22-39.
22-40.
22-41.
22-42.
22-43.
22-44.
22-45.
22-46.
22-47.
22-48.
22-49.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
76

........................................................................
CAN_NDAT_X Register Field Descriptions ..........................................................................
CAN_NDAT_21 Register Field Descriptions.........................................................................
CAN_IPEN_X Register Field Descriptions ...........................................................................
CAN_IPEN_21 Register Field Descriptions ..........................................................................
CAN_MVAL_X Register Field Descriptions ..........................................................................
CAN_MVAL_21 Register Field Descriptions.........................................................................
CAN_IP_MUX21 Register Field Descriptions .......................................................................
CAN_IF1CMD Register Field Descriptions ..........................................................................
CAN_IF1MSK Register Field Descriptions ...........................................................................
CAN_IF1ARB Register Field Descriptions ...........................................................................
CAN_IF1MCTL Register Field Descriptions .........................................................................
CAN_IF1DATA Register Field Descriptions .........................................................................
CAN_IF1DATB Register Field Descriptions .........................................................................
CAN_IF2CMD Register Field Descriptions ..........................................................................
CAN_IF2MSK Register Field Descriptions ...........................................................................
CAN_IF2ARB Register Field Descriptions ...........................................................................
CAN_IF2MCTL Register Field Descriptions .........................................................................
CAN_IF2DATA Register Field Descriptions .........................................................................
CAN_IF2DATB Register Field Descriptions .........................................................................
CAN_IF3OBS Register Field Descriptions ...........................................................................
CAN_IF3MSK Register Field Descriptions ...........................................................................
CAN_IF3ARB Register Field Descriptions ...........................................................................
CAN_IF3MCTL Register Field Descriptions .........................................................................
CAN_IF3DATA Register Field Descriptions .........................................................................
CAN_IF3DATB Register Field Descriptions .........................................................................
CAN_IF3UPD Register Field Descriptions ...........................................................................
USB Memory Access From Software .................................................................................
USB Memory Access From CCS......................................................................................
Universal Serial Bus (USB) Controller Register Map ..............................................................
Function Address Register (USBFADDR) Field Descriptions .....................................................
Power Management Register (USBPOWER) in Host Mode Field Descriptions ................................
Power Management Register (USBPOWER) in Device Mode Field Descriptions..............................
USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions .........................................
USB Transmit Interrupt Status Register (USBRXIS) Field Descriptions .........................................
USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions .........................................
USB Transmit Interrupt Status Register (USBRXIE) Field Descriptions .........................................
USB General Interrupt Status Register (USBIS) in Host Mode Field Descriptions .............................
USB General Interrupt Status Register (USBIS) in Device Mode Field Descriptions ..........................
USB Interrupt Enable Register (USBIE) in Host Mode Field Descriptions ......................................
USB Interrupt Enable Register (USBIE) in Device Mode Field Descriptions ....................................
Frame Number Register (FRAME) Field Descriptions .............................................................
USB Endpoint Index Register (USBEPIDX) Field Descriptions ...................................................
USB Test Mode Register (USBTEST) in Host Mode Field Descriptions.........................................
USB Test Mode Register (USBTEST) in Device Mode Field Descriptions ......................................
USB FIFO Endpoint n Register (USBFIFO[n]) Field Descriptions ................................................

22-23. CAN_TXRQ_21 Register Field Descriptions

List of Tables

2406
2407
2408
2409
2410
2411
2412
2416
2417
2419
2422
2423
2424
2428
2429
2431
2434
2435
2436
2438
2439
2440
2442
2443
2444
2455
2456
2458
2473
2474
2474
2476
2478
2480
2482
2484
2485
2486
2487
2488
2488
2489
2489
2491

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

23-20. USB Device Control Register (USBDEVCTL) Field Descriptions ................................................. 2492
23-21. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) Field Descriptions ........................... 2494
23-22. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) Field Descriptions ............................ 2495
23-23. USB Transmit FIFO Start Address Register (USBTXFIFOADDR) Field Descriptions ......................... 2496
23-24. USB Receive FIFO Start Address Register (USBRXFIFOADDR) Field Descriptions .......................... 2497
23-25. USB Connect Timing Register (USBCONTIM) Field Descriptions................................................ 2498
23-26. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) Field Descriptions ..... 2499
23-27. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) Field Descriptions..... 2499
23-28. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) Field Descriptions ...... 2500
23-29. USB Transmit Hub Address Endpoint n Registers(USBTXHUBADDR[n]) Field Descriptions ................ 2501
23-30. USB Transmit Hub Port Endpoint n Registers(USBTXHUBPORT[n]) Field Descriptions ..................... 2502
23-31. USB Recieve Functional Address Endpoint n Registers(USBFIFO[n]) Field Descriptions .................... 2503
23-32. USB Receive Hub Address Endpoint n Registers(USBRXHUBADDR[n]) Field Descriptions

................

2504

23-33. USB Transmit Hub Port Endpoint n Registers(USBRXHUBPORT[n]) Field Descriptions ..................... 2505
23-34. USB Maximum Transmit Data Endpoint n Registers(USBTXMAXP[n]) Field Descriptions ................... 2506

..........
USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode Field Descriptions .......
USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode Field Descriptions.........
USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode Field Descriptions ......
USB Receive Byte Count Endpoint 0 Register (USBCOUNT0) Field Descriptions ............................
USB Type Endpoint 0 Register (USBTYPE0) Field Descriptions .................................................
USB NAK Limit Register (USBNAKLMT) Field Descriptions ......................................................

23-35. USB Control and Status Endpoint 0 Low Register(USBCSRL0) in Host Mode Field Descriptions

2507

23-36.

2508

23-37.
23-38.
23-39.
23-40.
23-41.

2509
2509
2510
2510
2511

23-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode Field
Descriptions .............................................................................................................. 2512
23-43. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode Field
Descriptions .............................................................................................................. 2513
23-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode Field
Descriptions .............................................................................................................. 2515
23-45. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode Field
Descriptions .............................................................................................................. 2516
23-46. USB Maximum Receive Data Endpoint n Registers (USBTXMAXP[n]) Field Descriptions ................... 2517
23-47. USB Control and Status Endpoint n Low Register(USBCSRL[n]) in Host Mode Field Descriptions ......... 2518
23-48. USB Control and Status Endpoint 0 Low Register(USBCSRL[n]) in Device Mode Field Descriptions ...... 2519
23-49. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Host Mode Field Descriptions ....... 2520
23-50. USB Control and Status Endpoint 0 High Register(USBCSRH[n]) in Device Mode Field Descriptions ..... 2521
23-51. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n]) Field Descriptions ................. 2522
23-52. USB Host Transmit Configure Type Endpoint n Register(USBTXTYPE[n]) Field Descriptions

..............

2523

23-53. USBTXINTERVAL[n] Frame Numbers ............................................................................... 2524
23-54. USB Host Transmit Interval Endpoint n Register(USBTXINTERVAL[n]) Field Descriptions .................. 2524
23-55. USB Host Configure Receive Type Endpoint n Register(USBRXTYPE[n]) Field Descriptions ............... 2525
23-56. USBRXINTERVAL[n] Frame Numbers ............................................................................... 2526
23-57. USB Host Receive Polling Interval Endpoint n Register(USBRXINTERVAL[n]) Field Descriptions.......... 2526
23-58. USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) Field
Descriptions .............................................................................................................. 2527
23-59. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) Field Descriptions .......... 2528
23-60. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) Field Descriptions .......... 2530
23-61. USB External Power Control Register (USBEPC) Field Descriptions ............................................ 2531
23-62. USB External Power Control Raw Interrupt Status Register (USBEPCRIS) Field Descriptions .............. 2533
23-63. USB External Power Control Interrupt Mask Register (USBEPCIM) Field Descriptions....................... 2534
23-64. USB External Power Control Interrupt Status and Clear Register (USBEPCISC) Field Descriptions ....... 2535
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

77

www.ti.com

23-65. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions....................... 2536
23-66. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions....................... 2537
23-67. USB Device RESUME Interrupt Status and Clear Register (USBDRISC) Field Descriptions ................ 2538
23-68. USB General-Purpose Control and Status Register (USBGPCS) Field Descriptions .......................... 2539
23-69. USB DMA Select Register (USBDMASEL) Field Descriptions .................................................... 2540
24-1.

uPP Signal Description ................................................................................................. 2547

24-2.

CPU/CLA/uPP-DMA Address Map.................................................................................... 2554

24-3.

CPU/CLA/uPP-DMA Address Map.................................................................................... 2555

24-4.

uPP Parameters Useful for System Tuning .......................................................................... 2556

24-5.

UPP Base Address Table .............................................................................................. 2557

24-6.

UPP_REGS Registers .................................................................................................. 2558

24-7.

UPP_REGS Access Type Codes ..................................................................................... 2558

24-8.

PID Register Field Descriptions ....................................................................................... 2560

24-9.

PERCTL Register Field Descriptions ................................................................................. 2561

24-10. CHCTL Register Field Descriptions ................................................................................... 2563
24-11. IFCFG Register Field Descriptions.................................................................................... 2564
2566

24-13. THCFG Register Field Descriptions

2567

24-14.

2569

24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
78

...................................................................................
..................................................................................
RAWINTST Register Field Descriptions..............................................................................
ENINTST Register Field Descriptions ................................................................................
INTENSET Register Field Descriptions ..............................................................................
INTENCLR Register Field Descriptions ..............................................................................
CHIDESC0 Register Field Descriptions ..............................................................................
CHIDESC1 Register Field Descriptions ..............................................................................
CHIDESC2 Register Field Descriptions ..............................................................................
CHIST0 Register Field Descriptions ..................................................................................
CHIST1 Register Field Descriptions ..................................................................................
CHIST2 Register Field Descriptions ..................................................................................
CHQDESC0 Register Field Descriptions .............................................................................
CHQDESC1 Register Field Descriptions .............................................................................
CHQDESC2 Register Field Descriptions .............................................................................
CHQST0 Register Field Descriptions .................................................................................
CHQST1 Register Field Descriptions .................................................................................
CHQST2 Register Field Descriptions .................................................................................
GINTEN Register Field Descriptions .................................................................................
GINTFLG Register Field Descriptions ................................................................................
GINTCLR Register Field Descriptions ................................................................................
DLYCTL Register Field Descriptions .................................................................................
Configuration for EMIF1 and EMIF2 Modules .......................................................................
EMIF Pins Used to Access Both SDRAM and Asynchronous Memories ........................................
EMIF Pins Specific to SDRAM ........................................................................................
EMIF Pins Specific to Asynchronous Memory ......................................................................
EMIF SDRAM Commands .............................................................................................
Truth Table for SDRAM Commands ..................................................................................
16-bit EMIF Address Pin Connections................................................................................
Description of the SDRAM Configuration Register (SDRAM_CR) ................................................
Description of the SDRAM Refresh Control Register (SDRAM_RCR) ...........................................
Description of the SDRAM Timing Register (SDRAM_TR) ........................................................
Description of the SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) ............................

24-12. IFIVAL Register Field Descriptions

List of Tables

2571
2573
2575
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2594
2597
2597
2598
2598
2599
2600
2602
2602
2603
2603

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

www.ti.com

25-12. SDRAM LOAD MODE REGISTER Command ...................................................................... 2604
25-13. Refresh Urgency Levels ................................................................................................ 2605
25-14. Mapping from Logical Address to EMIF Pins for 32-bit SDRAM .................................................. 2610
25-15. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM .................................................. 2610
25-16. Normal Mode vs. Select Strobe Mode ................................................................................ 2611
25-17. Description of the Asynchronous m Configuration Register (ASYNC_CSn_CR) ............................... 2613
25-18. Description of the Asynchronous Wait Cycle Configuration Register (ASYNC_WCCR)

......................

2614

25-19. Description of EMIF Interrupt Mask Set Register (INT_MSK_SET) .............................................. 2614
25-20. Description of EMIF Interrupt Mast Clear Register (INT_MSK_CLR) ............................................ 2614
25-21. Asynchronous Read Operation in Normal Mode .................................................................... 2615
25-22. Asynchronous Write Operation in Normal Mode .................................................................... 2617
25-23. Asynchronous Read Operation in Select Strobe Mode ............................................................ 2619
25-24. Asynchronous Write Operation in Select Strobe Mode

............................................................

2621

25-25. Interrupt Monitor and Control Bit Fields .............................................................................. 2624
25-26. SR Field Value For EMIF to K4S641632H-TC(L)70 Interface..................................................... 2628
25-27. SDRAM_TR Field Calculations for EMIF to K4S641632H-TC(L)70 Interface................................... 2630

.....................................................
.....................................................
SDRAM_CR Field Values For EMIF to K4S641632H-TC(L)70 Interface ........................................
AC Characteristics for a Read Access ...............................................................................
AC Characteristics for a Write Access ...............................................................................
EMIF Base Address Table .............................................................................................
EMIF_REGS Registers .................................................................................................
EMIF_REGS Access Type Codes ....................................................................................
RCSR Register Field Descriptions ....................................................................................
ASYNC_WCCR Register Field Descriptions ........................................................................
SDRAM_CR Register Field Descriptions ............................................................................
SDRAM_RCR Register Field Descriptions...........................................................................
ASYNC_CS2_CR Register Field Descriptions ......................................................................
ASYNC_CS3_CR Register Field Descriptions ......................................................................
ASYNC_CS4_CR Register Field Descriptions ......................................................................
SDRAM_TR Register Field Descriptions .............................................................................
TOTAL_SDRAM_AR Register Field Descriptions ..................................................................
TOTAL_SDRAM_ACTR Register Field Descriptions ...............................................................
SDR_EXT_TMNG Register Field Descriptions ......................................................................
INT_RAW Register Field Descriptions ...............................................................................
INT_MSK Register Field Descriptions ................................................................................
INT_MSK_SET Register Field Descriptions .........................................................................
INT_MSK_CLR Register Field Descriptions .........................................................................
EMIF1_CONFIG_REGS Registers ...................................................................................
EMIF1_CONFIG_REGS Access Type Codes .......................................................................
EMIF1LOCK Register Field Descriptions ............................................................................
EMIF1COMMIT Register Field Descriptions .........................................................................
EMIF1MSEL Register Field Descriptions ............................................................................
EMIF1ACCPROT0 Register Field Descriptions .....................................................................
EMIF2_CONFIG_REGS Registers ...................................................................................
EMIF2_CONFIG_REGS Access Type Codes .......................................................................
EMIF2LOCK Register Field Descriptions ............................................................................
EMIF2COMMIT Register Field Descriptions .........................................................................

25-28. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface

2631

25-29. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface

2631

25-30.

2632

25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
25-43.
25-44.
25-45.
25-46.
25-47.
25-48.
25-49.
25-50.
25-51.
25-52.
25-53.
25-54.
25-55.
25-56.
25-57.
25-58.
25-59.
25-60.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

List of Tables

2633
2633
2636
2637
2637
2638
2639
2640
2642
2643
2645
2647
2649
2650
2651
2652
2653
2654
2655
2656
2657
2657
2658
2659
2660
2661
2662
2662
2663
2664
79

www.ti.com

25-61. EMIF2ACCPROT0 Register Field Descriptions ..................................................................... 2665

80

List of Tables

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Preface
SPRUHM8G – December 2013 – Revised September 2017

Read This First
About This Manual
This Technical Reference Manual (TRM) details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data manual, rather a companion guide that should
be used alongside the device-specific data manual to understand the details to program the device. The
primary purpose of the TRM is to abstract the programming details of the device from the data manual.
This allows the data manual to outline the high-level features of the device without unnecessary
information about register descriptions or programming models.

Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers may be shown with the suffix h or the prefix 0x. For example, the following
number is 40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties with default reset value below. A legend explains the notation used for the
properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be
avoided.

Glossary
TI Glossary — This glossary lists and explains terms, acronyms, and definitions.

Related Documentation From Texas Instruments
For a complete listing of related documentation and development-support tools for these devices, visit the
Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x CPU and Instruction Set
Reference Guide (SPRU430) and TMS320C28x Floating Point Unit and Instruction Set Reference Guide
(SPRUEO2) must be used in conjunction with this TRM.

Trademarks
controlSUITE, Code Composer Studio are trademarks of Texas Instruments.
USB Specification Revision 2.0 is a trademark of Compaq Computer Corp.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Read This First

81

Chapter 1
SPRUHM8G – December 2013 – Revised September 2017

C28x Processor
This chapter contains a modified description of the C28x Processor and provides links to access their
respective references guides.
Topic

1.1

82

...........................................................................................................................

Page

Overview ........................................................................................................... 83

C28x Processor

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Overview

www.ti.com

1.1

Overview
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and
tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and
unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and
data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this
over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction
Set Reference Guide (literature number SPRU430). For more information on the C28x Floating Point Unit
(FPU), Trigonometric Math Unit, and Viterbi, Complex Math, and CRC Unit II (VCU-II) instruction sets, see
the TMS320C28x Extended Instruction Sets Technical Reference Guide (literature number SPRUHS1). A
brief overview of the FPU, TMU, and VCU-II are provided here.

1.1.1 Floating-Point Unit
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU
by adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point
unit registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be
used in high-priority interrupts for fast context save and restore of the floating-point registers.

1.1.2 Trigonometric Math Unit
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in
Table 1-1.
Table 1-1. TMU Supported Instructions
INSTRUCTIONS

C EQUIVALENT OPERATION

PIPELINE CYCLES

MPY2PIF32 RaH,RbH

a = b * 2pi

2/3

DIV2PIF32 RaH,RbH

a = b / 2pi

2/3

DIVF32 RaH,RbH,RcH

a = b/c

5

SQRTF32 RaH,RbH

a = sqrt(b)

5

SINPUF32 RaH,RbH

a = sin(b*2pi)

4

COSPUF32 RaH,RbH

a = cos(b*2pi)

4

ATANPUF32 RaH,RbH

a = atan(b)/2pi

4

QUADF32 RaH,RbH,RcH,RdH

Operation to assist in calculating ATANPU2

5

No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU
instructions use the existing FPU register set (R0H to R7H) to carry out their operations.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

C28x Processor

83

Overview

www.ti.com

1.1.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)
The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The
VCU-II extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the
performance of FFTs and communications-based algorithms. The C28x+VCU-II supports the following
algorithm types:
• Viterbi Decoding
Viterbi decoding is commonly used in baseband communications applications. The Viterbi decode
algorithm consists of three main parts: branch metric calculations, compare-select (Viterbi butterfly),
and a traceback operation. Table 1-2 shows a summary of the VCU performance for each of these
operations.
Table 1-2. Viterbi Decode Performance
VITERBI OPERATION

(1)
(2)

•

•

VCU CYCLES

Branch Metric Calculation (code rate = 1/2)

1

Branch Metric Calculation (code rate = 1/3)

2p

Viterbi Butterfly (add-compare-select)

2 (1)

Traceback per Stage

3 (2)

C28x CPU takes 15 cycles per butterfly.
C28x CPU takes 22 cycles per stage.

Cyclic Redundancy Check
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity
over large data blocks, communication packets, or code sections. The C28x+VCU can perform 8-bit,
16-bit, 24-bit, and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10
bytes in 10 cycles. A CRC result register contains the current CRC, which is updated whenever a CRC
instruction is executed.
Complex Math
Complex math is used in many applications, a few of which are:
– Fast Fourier Transform (FFT)
The complex FFT is used in spread spectrum communications, as well as in many signal
processing algorithms.
– Complex filters
Complex filters improve data reliability, transmission distance, and power efficiency. The
C28x+VCU can perform a complex I and Q multiply with coefficients (four multiplies) in a single
cycle. In addition, the C28x+VCU can read/write the real and imaginary parts of 16-bit complex data
to memory in a single cycle.
Table 1-3. Complex Math Performance
COMPLEX MATH OPERATION

VCU CYCLES

NOTES

Add or Subtract

1

32 +/- 32 = 32-bit (Useful for filters)

Add or Subtract

1

16 +/- 32 = 15-bit (Useful for FFT)

Multiply

2p

16 x 16 = 32-bit

Multiply and Accumulate (MAC)

2p

32 + 32 = 32-bit, 16 x 16 = 32-bit

RPT MAC

2p+N

Repeat MAC. Single cycle after the first operation.

NOTE: Only the CRC-related VCU instructions will be supported in future devices. FFT algorithms
are available for the C28x+FPU.

84

C28x Processor

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 2
SPRUHM8G – December 2013 – Revised September 2017

System Control
This chapter explains system control and interrupts found on this MCU. The system control module
configures and manages the overall operation of the device and provides information about the device
status. Configurable features in system control include reset control, NMI operation, power control, clock
control, and low-power modes.
Topic

2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15

...........................................................................................................................

Page

Introduction ....................................................................................................... 86
System Control Functional Description................................................................. 86
Resets .............................................................................................................. 87
Peripheral Interrupts ........................................................................................... 89
Exceptions and Non-Maskable Interrupts ............................................................ 102
Safety Features ................................................................................................ 103
Clocking ......................................................................................................... 107
32-Bit CPU Timers 0/1/2 ..................................................................................... 117
Watchdog Timers ............................................................................................. 119
Low Power Modes ............................................................................................ 122
Memory Controller Module ................................................................................ 125
Flash and OTP Memory ..................................................................................... 133
Dual Code Security Module (DCSM) .................................................................... 146
JTAG............................................................................................................... 157
Registers ......................................................................................................... 159

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

85

Introduction

2.1

www.ti.com

Introduction
On this device, the CPU1 subsystem acts as a master, and by default (upon reset), it owns all the
configuration and control. Through software running on CPU1, peripherals and I/Os can be configured to
be accessible by the CPU2 subsystem and the configuration so chosen could be locked.
The PLL clock configuration is also owned by the CPU1 subsystem by default, but a clock control
semaphore is provided by which CPU2 can grab access to the clock configuration registers.
Each CPU has its own NMI module to handle different exceptions during run time. If the NMI was on
CPU1, any NMI exception that is unhandled before the NMI Watchdog (NMIWD) timer expiration will reset
the entire device. If the NMI was on the CPU2 subsystem, then the CPU2 subsystem alone will be reset,
in which case the CPU1 subsystem will be informed by another NMI that the CPU2 subsystem was reset
because of NMIWD timer expiration.
Each CPU subsystem has its own watchdog timer module for software to use. Watchdog timer expiration
on CPU2 will reset the CPU2 subsystem alone when configured to generate a reset, but watchdog timer
expiration on CPU1 will reset the entire device.
Except for a CPU2 standalone internal reset such as CPU2.NMIWD or CPU2.WD each time the device is
reset, the CPU2 subsystem will be held under reset until the CPU1 subsystem brings it out of reset. This
is done by the boot ROM software running on the CPU1 core.
The register space of the device system control module is divided into three categories and will be
explained further in this chapter. They are:
1. System Control Device Configuration Registers (DEV_CFG_REGS). These registers are mapped to
CPU1 only. The base address of these registers on the CPU1 address space begins at 0x5D000.
2. System Control Clock Configuration Registers (CLK_CFG_REGS). These registers are mapped to
both CPU1 and CPU2 address space but access control is based on a Clock Control Semaphore
register. The base address of these registers on both the CPU subsystems begins at 0x5D200.
3. System control CPU Subsystem Registers (CPU_SYS_REGS). These registers are mapped to both
the CPU subsystems. The base address of these registers on both the CPU subsystems begins at
0x5D300.
This chapter explains the system control module on both the CPU subsystems.

2.2

System Control Functional Description
The system control module provides the following capabilities:
• Device identification and configuration registers
• Reset control
• Exceptions and Interrupt control
• Safety and error handling features of the device
• Power control
• Clock control
• Low Power modes
• Security module
• Inter-Processor Communication (IPC)

2.2.1 Device Identification
Device identification registers provide information on device class, device family, revision, part number, pin
count, operating temperature range, package type, pin count, and device qualification status.
All of the device information is part of the DEV_CFG_REGS space and is accessible only by the software
running on the CPU1 subsystem.
The control subsystem device identification registers are: PARTIDL, PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
86

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control Functional Description

www.ti.com

•
•
•
•

UID_PSRAND0-5: 192 bits of pseudo-random data
UID_UNIQUE: 32-bit unique data, the value in this register will be unique across all devices with the
same PARTIDH
UID_CHECKSUM: 32-bit fletcher checksum of UID_PSRAND0-5 and UID_UNIQUE
CPU ID: 16-bit location in OTP. The value at this location provides the information about CPU (CPU1
or CPU20. Please refer to the device datasheet, for more detail.

2.2.2 Device Configuration Registers
Several registers provide users with configuration information for debug and identification purposes on this
MCU. This information includes the features of the peripheral and how much RAM and FLASH memory is
available on this part.
These registers are part of DEV_CFG_REGS space and are accessible only by the software running on
the CPU1 subsystem.
• DC0 – DC20: Device Configuration or Capabilities registers.
If a particular bit in these registers is set to ‘1’ then the associated/feature or module is available in the
device.
• PERCNF: Peripheral configuration register.
This register configures ADC capabilities, and enables or disables the USB internal PHY.
• CPUID: CPU identification register
This register is available for software to identify on which CPU it is executing.

2.3

Resets
This section explains the types and effects of the different resets on this device.

2.3.1 Reset Sources
Table 2-1 summarizes the various reset signals and their effect on the device.
Table 2-1. Reset Signals
Reset Source

CPU1
CPU1
CPU2
CPU2
CPU2 Held
Core
Peripheral
Core
Peripheral
In Reset
Reset
s Reset
Reset
s Reset
(C28x,
(C28x,
TMU, FPU,
TMU, FPU,
VCU)
VCU)

JTAG /
Debug
Logic
Reset

IOs

XRS
Output

POR

Yes

Yes

Yes

Yes

Yes

Yes

Hi-Z

Yes

XRS Pin

Yes

Yes

Yes

Yes

Yes

No

Hi-Z

-

CPU1.WDRS

Yes

Yes

Yes

Yes

Yes

No

Hi-Z

Yes

CPU1.NMIWDRS

Yes

Yes

Yes

Yes

Yes

No

Hi-Z

Yes

CPU1.SYSRS
(Debugger Reset)

Yes

Yes

Yes

Yes

Yes

No

Hi-Z

No

CPU1.SCCRESET

Yes

Yes

Yes

Yes

Yes

No

Hi-Z

No

CPU2.SYSRS
(Debugger Reset)

No

No

Yes

Yes

No

No

-

No

CPU2.WDRS

No

No

Yes

Yes

No

No

-

No

CPU2.NMIWDRS

No

No

Yes

Yes

No

No

-

No

CPU2.SCCRESET

No

No

Yes

Yes

No

No

-

No

HIBRESET

Yes

Yes

Yes

Yes

Yes

Yes

Isolated

No

CPU1.HWBISTRS

Yes

No

No

No

No

No

-

No

CPU2.HWBISTRS

No

No

Yes

No

No

No

-

No

TRST

No

No

No

No

No

Yes

-

No

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

87

Resets

www.ti.com

The resets can be divided into a few groups:
• Chip-level resets (XRS, POR, CPU1.WDRS, and CPU1.NMIWDRS), which reset all or almost all of the
device.
• System resets (CPU1.SYSRS and CPU1.SCCRESET), which reset a large subset of the device but
maintain some system-level configuration.
• CPU2 subsystem resets (CPU2.SYSRS, CPU2.WDRS, CPU2.NMIWDRS, and CPU2.SCCRESET),
which reset only CPU2 and its peripherals.
• Special resets (HIBRESET, CPU1.HWBISTRS, CPU2.HWBISTRS, and TRST), which enable specific
device functions.
Whenever the CPU1 subsystem is reset, CPU2 and its peripherals are also reset, and CPU2 is held in
reset. CPU1 brings it out of reset by writing to the CPU2RESCTL register. This is normally done by the
boot ROM. For more details on the boot process, refer to the ROM Code and Peripheral Booting chapter.
After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register
maintain their state across multiple resets. They can only be cleared by a power-on reset (POR) or by
writing ones to the register. Each CPU has its own RESC register, referred to as CPU1.RESC and
CPU2.RESC.
Many peripheral modules have individual resets accessible through the system control registers. For
information about a module's reset state, refer to the appropriate chapter for that module.
After a POR, XRS, CPU1.WDRS, CPU1.NMIWDRS, or HIBRESET, the boot ROMs will clear all of the
system and message RAMs on both CPUs. After a CPU2.WDRS or CPU2.NMIWDRS, CPU2's boot ROM
will clear all of the CPU2 system and message RAMs.

2.3.2 External Reset (XRS)
The external reset (XRS) is the main chip-level reset for the device. It resets both CPUs , all peripherals
and I/O pin configurations, and most of the system control registers. It also holds CPU2 in reset. There is
a dedicated open-drain pin for XRS. This pin may be used to drive reset pins for other ICs in the
application, and may itself be driven by an external source. The XRS is driven internally during watchdog,
NMI, and power-on resets. In hibernate mode, toggling XRS will produce a HIBRESET.
The XRSn bit in the RESC register will be set whenever XRS is driven low for any reason. This bit is then
cleared by the boot ROM.

2.3.3 Power-On Reset (POR)
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up,
suppressing glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most
applications, XRS is held low long enough to reset other system ICs, but some applications may require a
longer pulse. In these cases, XRS can be driven low externally to provide the correct reset duration. A
POR resets everything that XRS does, along with a few other registers – the reset cause register (RESC),
the NMI shadow flag register (NMISHDFLG), the X1 clock counter register (X1CNT), and the hibernate
configuration registers (HIBBOOTMODE, IORESTOREADDR, and LPMCR.M0M1MODE).
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.

2.3.4 Debugger Reset (SYSRS)
During development, it is sometimes necessary to reset the CPU and its peripherals without disconnecting
the debugger or disrupting the system-level configuration. To facilitate this, each CPU has its own
subsystem reset, which can be triggered by a debugger using Code Composer Studio. CPU2's subsystem
reset (CPU2.SYSRS) resets only CPU2, its peripherals, and its clock gating and LPM configuration. It
does not hold CPU2 in reset. CPU1's subsystem reset (CPU1.SYSRS) resets CPU1, its peripherals, many
system control registers (including its clock gating and LPM configuration and the peripherals' CPU
ownership), and all I/O pin configurations. It also produces a CPU2.SYSRS and holds CPU2 in reset.
Neither SYSRS resets the ICEPick debug module, the device capability registers, the clock source and
PLL configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI
flags, the analog trims, or anything reset only by a POR (see Section 2.3.3).
88

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Resets

www.ti.com

2.3.5 Watchdog Reset (WDRS)
Each CPU has a watchdog timer that can optionally trigger a reset that lasts for 512 INTOSC1 cycles.
CPU1's watchdog reset (CPU1.WDRS) produces an XRS. CPU2's watchdog reset (CPU2.WDRS)
produces a CPU2.SYSRS and triggers an NMI on CPU1.
After a watchdog reset, the WDRSn bit in RESC is set.

2.3.6 NMI Watchdog Reset (NMIWDRS)
Each CPU has a non-maskable interrupt (NMI) module that detects hardware errors in the system. Each
NMI module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a
user-specified amount of time. CPU1's NMI watchdog reset (CPU1.NMIWDRS) produces an XRS. CPU2's
NMI watchdog reset (CPU2.NMIWDRS) produces a CPU2.SYSRS and triggers an NMI on CPU1.
After an NMI watchdog reset, the NMIWDRSn bit in RESC is set.

2.3.7 DCSM Safe Code Copy Reset (SCCRESET)
Each CPU has a dual-zone code security module (DCSM) that blocks read access to certain areas of the
flash memory. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely
access those memory areas. To prevent security breaches, interrupts must be disabled before calling
these functions. If a vector fetch occurs in a safe copy or CRC function, the DCSM triggers a reset.
CPU1's security reset (CPU1.SCCRESET) is similar to a CPU1.SYSRS, and CPU2's security reset
(CPU2.SCCRESET) is similar to a CPU2.SYSRS. However, the security reset also resets the debug logic
to deny access to a potential attacker.
After a security reset, the SCCRESETn bit in RESC is set.

2.3.8 Hibernate Reset (HIBRESET)
Hibernate is a chip-level low-power mode that gates power to large portions of the device. Waking up from
hibernate involves a special reset (HIBRESET). This reset is similar to a POR except that the I/O pins
remain isolated and the XRS pin is not toggled. (An external XRS toggle during hibernate will trigger a
HIBRESET). I/O isolation is disabled in software as part of a special boot ROM flow. For more information
on hibernate, refer to Section 2.10.
After a hibernate reset, the HIBRESETn bit in RESC is set. This bit is then cleared by the boot ROM.

2.3.9 Hardware BIST Reset (HWBISTRS)
Each CPU has a Hardware Built-In Self Test (HWBIST) module that tests the functionality of the CPU. At
the end of the test, it resets the CPU to return it to a working state. This reset (HWBISTRS) only affects
the CPU itself. The peripherals and system control remain as previously configured. The CPU state is
restored in software as part of a special boot ROM flow. For more information on the HWBIST flow,
contact your local TI representative.
After a HWBIST reset, the HWBISTn bit in RESC is set. This bit is then cleared by the boot ROM.

2.3.10 Test Reset (TRST)
The ICEPick debug module and associated JTAG logic has its own reset (TRST) which is controlled by a
dedicated pin. This reset is normally active unless the user connects a debugger to the device. For more
information on the debug module, see the TI Processors Wiki page on ICEPick:
http://processors.wiki.ti.com/index.php/ICEPICK.
The TRST does not have a normal RESC bit, but the TRSTn_pin_status bit indicates the state of the pin.

2.4

Peripheral Interrupts
This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered
in Section 2.5. Software interrupts and emulation interrupts are not covered in this document. For
information on those, see the TMS320C28x CPU and Instruction Set Reference Guide (SPRU430).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

89

Peripheral Interrupts

www.ti.com

2.4.1 Interrupt Concepts
An interrupt is a signal that causes the CPU to pause its current execution and branch to a different piece
of code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral
events, and involves less CPU overhead or program complexity than register polling. However, because
interrupts are asynchronous to the program flow, care must be taken to avoid conflicts over resources that
are accessed both in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until it is processed. The enable registers block the propagation of the interrupt. When an
interrupt signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the
vector table.

2.4.2 Interrupt Architecture
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected
directly to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt
signals through the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened
version). The PIE multiplexes up to sixteen peripheral interrupts into each CPU interrupt line. It also
expands the vector table to allow each interrupt to have its own ISR. This allows the CPU to support a
large number of peripherals.
An interrupt path is divided into three stages – the peripheral, the PIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are
pending, implement and prioritize nested interrupts in software, and disable interrupts during certain
critical tasks.
Figure 2-1 shows the interrupt architecture for this device.
Figure 2-1. Device Interrupt Architecture
CPU1.TIMER0
LPM Logic
CPU1.WD

CPU1.LPMINT

CPU1.TINT0
CPU1.W AKEINT
CPU1.NMIWD

NMI

CPU1.W DINT

CPU1
GPIO0
GPIO1
...
...
GPIOx

INPUTXBAR4

Input
X-BAR

INPUTXBAR5
INPUTXBAR6
INPUTXBAR13
INPUTXBAR14

CPU1.XINT1 Control
CPU1.XINT2 Control
CPU1.XINT3 Control
CPU1.XINT4 Control
CPU1.XINT5 Control

INT1
to
INT12

CPU1.
ePIE

CPU1.TIMER1
CPU1.TIMER2

IPC
4 Interrupts

CPU1.TINT1
CPU1.TINT2

INT13
INT14

Peripherals
CPU1.NMIWD

CPU2.XINT1 Control
CPU2.XINT2 Control
CPU2.XINT3 Control
CPU2.XINT4 Control
CPU2.XINT5 Control
LPM Logic
CPU2.WD

System Control

INT1
to
INT12

CPU2
ePIE

CPU2.W AKEINT
CPU2.TIMER2

CPU2.W DINT
CPU2.TIMER0

90

CPU2

CPU2.TIMER1

CPU2 .LPMINT

NMI

CPU2.TINT1
CPU2.TINT2

INT13
INT14

CPU2.TINT0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Peripheral Interrupts

www.ti.com

2.4.2.1

Peripheral Stage

Each peripheral has its own unique interrupt configuration, which is described in that peripheral's chapter.
Some peripherals allow multiple events to trigger the same interrupt signal. For example, a
communications peripheral might use the same interrupt to indicate that data has been received or that
there has been a transmission error. The cause of the interrupt can be determined by reading the
peripheral's status register. Often, the bits in the status register must be cleared manually before another
interrupt will be generated.
2.4.2.2

PIE Stage

The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which
are sometimes called PIE channels. These channels are grouped according to their associated CPU
interrupt. Each PIE group has one 16-bit enable register (PIEIERx), one 16-bit flag register (PIEIFRx), and
one bit in the PIE acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt
mask for the entire PIE group.
When the CPU receives an interrupt, it fetches the address of the ISR from the PIE. The PIE returns the
vector for the lowest-numbered channel in the group that is both flagged and enabled. This gives lowernumbered interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition will not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 2.4.4
contains procedures for safely modifying the PIE configuration once interrupts have been enabled.
2.4.2.3

CPU Stage

Like the PIE, the CPU provides flag and enable register bits for each of its interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared
using the CPU's SETC instruction. In C code, controlSUITE's DINT and EINT macros can be used for this
purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is cleared, the next instruction in the
pipeline will run with interrupts disabled. No software delays are needed.
2.4.2.4

Dual-CPU Interrupt Handling

Each CPU has its own PIE. Both PIEs must be configured independently.
Some interrupts come from shared peripherals that can be owned by either CPU, such as the ADCs and
SPIs. These interrupts are sent to both PIEs regardless of the peripheral's ownership. Thus, a peripheral
owned by one CPU can cause an interrupt on the other CPU if that interrupt is enabled in the other CPU's
PIE.

2.4.3 Interrupt Entry Sequence
Figure 2-2 shows how peripheral interrupts propagate to the CPU.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

91

Peripheral Interrupts

www.ti.com

Figure 2-2. Interrupt Propagation Path
PIEIERx.1
Peripheral
Interrupt
A

0

PIEIFRx.1
Latch

1

PIEIERx.2
Peripheral
Interrupt
B

Set

0

PIEIFRx.2
Latch

1

PIEACK.x

IER.x

1

ST1.INTM
1

0
0

IFR.x
Latch

1

0

CPU
Interrupt
Logic

PIEIERx.16
Peripheral
Interrupt
P

0

PIEIFRx.16
Latch

1

When a peripheral generates an interrupt (on PIE group x, channel y), it triggers the following sequence of
events:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier
stages are flushed.
8. The CPU saves its context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.
The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction
entering the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles.
Wait states on the ISR or stack memories will add to the latency. External interrupts add a minimum of two
SYSCLK cycles for GPIO synchronization plus extra time for input qualification (if used). Loops created
using the C28x RPT instruction cannot be interrupted.

2.4.4 Configuring and Using Interrupts
At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is
set. The application code is responsible for configuring and enabling all peripheral interrupts.
2.4.4.1

Enabling Interrupts

To
1.
2.
3.

enable a peripheral interrupt, perform the following steps:
Disable interrupts globally (DINT or SETC INTM).
Enable the PIE by setting the ENPIE bit of the PIECTRL register.
Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be
found in Table 2-2.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be
92

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Peripheral Interrupts

www.ti.com

found in Table 2-2.
5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
2.4.4.2

Handling Interrupts

ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the
TMS320C28x Optimizing C/C++ Compiler v6.2.4 User's Guide (SPRU514). For information on writing
assembly code to handle interrupts, see the Standard Operation for Maskable Interrupts section of the
TMS320C28x CPU and Instruction Set Reference Guide (SPRU430).
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at
the end of the ISR. If the PIEACK bit is not cleared, the CPU will not receive any further interrupts from
that group. This does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.
2.4.4.3

Disabling Interrupts

To disable all interrupts, set the CPU's global interrupt mask via DINT or SETC INTM. It is not necessary
to add NOPs after setting INTM or modifying IER – the next instruction will execute with interrupts
disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, it may reach the
CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no
special procedure is needed.
PIEIFR bits must never be cleared in software since the read/modify/write operation may cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The
following procedure can be used to bypass the normal ISR:
1. Disable interrupts globally (DINT or SETC INTM).
2. Modify the PIE vector table to map the PIEIFR bit's interrupt vector to an empty ISR. This ISR will only
contain a return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
4. Enable interrupts globally (EINT or CLRC INTM).
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to its original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

93

Peripheral Interrupts

2.4.4.4

www.ti.com

Nesting Interrupts

By default, interrupts do not nest. It is possible to nest and prioritize interrupts via software control of the
IER and PIEIERx registers. Documentation and example code can be found in controlSUITE and on the TI
Processors wiki:
http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

94

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Peripheral Interrupts

www.ti.com

2.4.5 PIE Channel Mapping
Table 2-2 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within
that group. When multiple interrupts are pending, the lowest-numbered channel is the lowest-numbered group is serviced first. Thus, the interrupts
at the top of the table have the highest priority, and the interrupts at the bottom have the lowest priority.
Table 2-2. PIE Channel Mapping
INTx.1

INTx.2

INTx.3

INTx.4

INTx.5

INTx.6

INTx.7

INTx.8

INTx.9

INTx.10

INTx.11

INTx.12

INTx.13

INTx.14

INTx.15

INTx.16

INT1.y

ADCA1

ADCB1

ADCC1

XINT1

XINT2

ADCD1

TIMER0

WAKE

-

-

-

-

IPC0

IPC1

IPC2

IPC3

INT2.y

EPWM1_
TZ

EPWM2_
TZ

EPWM3_
TZ

EPWM4_
TZ

EPWM5_
TZ

EPWM6_
TZ

EPWM7_
TZ

EPWM8_
TZ

EPWM9_
TZ

EPWM10_
TZ

EPWM11_
TZ

EPWM12_
TZ

-

-

-

-

INT3.y

EPWM1

EPWM2

EPWM3

EPWM4

EPWM5

EPWM6

EPWM7

EPWM8

EPWM9

EPWM10

EPWM11

EPWM12

-

-

-

-

INT4.y

ECAP1

ECAP2

ECAP3

ECAP4

ECAP5

ECAP6

-

-

-

-

-

-

-

-

-

-

INT5.y

EQEP1

EQEP2

EQEP3

-

-

-

-

-

SD1

SD2

-

-

-

-

-

-

INT6.y

SPIA_RX

SPIA_TX

SPIB_RX

SPIB_TX

MCBSPA_
RX

MCBSPA_
TX

MCBSPB_
RX

MCBSPB_
TX

SPIC_RX

SPIC_TX

-

-

-

-

-

-

INT7.y

DMA_CH1

DMA_CH2

DMA_CH3

DMA_CH4

DMA_CH5

DMA_CH6

-

-

-

-

-

-

-

-

-

-

INT8.y

I2CA

I2CA_
FIFO

I2CB

I2CB_
FIFO

SCIC_RX

SCIC_TX

SCID_RX

SCID_TX

-

-

-

-

-

-

UPPA
(CPU1 only)

-

INT9.y

SCIA_RX

SCIA_TX

SCIB_RX

SCIB_TX

CANA_0

CANA_1

CANB_0

CANB_1

-

-

-

-

-

-

USBA
(CPU1 only)

-

INT10.y

ADCA_
EVT

ADCA2

ADCA3

ADCA4

ADCB_EVT

ADCB2

ADCB3

ADCB4

ADCC_EVT

ADCC2

ADCC3

ADCC4

ADCD_EVT

ADCD2

ADCD3

ADCD4

INT11.y

CLA1_1

CLA1_2

CLA1_3

CLA1_4

CLA1_5

CLA1_6

CLA1_7

CLA1_8

-

-

-

-

-

-

-

-

INT12.y

XINT3

XINT4

XINT5

-

-

VCU

FPU_OVER
FLOW

FPU_
UNDER
FLOW

EMIF_
ERROR

RAM_COR
RECTABLE
_ERROR

FLASH_CO
RRECTABL
E_ERROR

RAM_ACCE
SS_VIOLAT
ION

SYS_PLL_
SLIP

AUX_PLL_
SLIP

CLA OVER
FLOW

CLA
UNDER
FLOW

Note: Cells marked "-" are Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

System Control
Copyright © 2013–2017, Texas Instruments Incorporated

95

Peripheral Interrupts

www.ti.com

2.4.6 Vector Tables
Table 2-3 shows the CPU interrupt vector table. The vectors for INT1 – INT12 are not used in this device.
The reset vector is fetched from the boot ROM instead of from this table.
Table 2-3. CPU Interrupt Vectors

96

Name

Vector ID

Address

Size (x16)

Description

Core priority

ePIE group
Priority

Reset

0

0x0000 0D00

2

Reset is always fetched from
location 0x003F_FFC0 in Boot
ROM

1 (Highest)

-

INT1

1

0x0000 0D02

2

Not used. See PIE Group 1

5

-

INT2

2

0x0000 0D04

2

Not used. See PIE Group 2

6

-

INT3

3

0x0000 0D06

2

Not used. See PIE Group 3

7

-

INT4

4

0x0000 0D08

2

Not used. See PIE Group 4

8

-

INT5

5

0x0000 0D0A

2

Not used. See PIE Group 5

9

-

INT6

6

0x0000 0D0C

2

Not used. See PIE Group 6

10

-

INT7

7

0x0000 0D0E

2

Not used. See PIE Group 7

11

-

INT8

8

0x0000 0D10

2

Not used. See PIE Group 8

12

-

INT9

9

0x0000 0D12

2

Not used. See PIE Group 9

13

-

INT10

10

0x0000 0D14

2

Not used. See PIE Group 10

14

-

INT11

11

0x0000 0D16

2

Not used. See PIE Group 11

15

-

INT12

12

0x0000 0D18

2

Not used. See PIE Group 12

16

-

INT13

13

0x0000 0D1A

2

CPU TIMER1 Interrupt

17

-

INT14

14

0x0000 0D1C

2

CPU TIMER2 Interrupt (for
TI/RTOS use)

18

-

DATALOG

15

0x0000 0D1E

2

CPU Data Logging Interrupt

19 (lowest)

-

RTOSINT

16

0x0000 0D20

2

CPU Real-Time OS Interrupt

4

-

EMUINT

17

0x0000 0D22

2

CPU Emulation Interrupt

2

-

NMI

18

0x0000 0D24

2

Non-Maskable Interrupt

3

-

ILLEGAL

19

0x0000 0D26

2

Illegal Instruction (ITRAP)

-

-

USER 1

20

0x0000 0D28

2

User-Defined Trap

-

-

USER 2

21

0x0000 0D2A

2

User-Defined Trap

-

-

USER 3

22

0x0000 0D2C

2

User-Defined Trap

-

-

USER 4

23

0x0000 0D2E

2

User-Defined Trap

-

-

USER 5

24

0x0000 0D30

2

User-Defined Trap

-

-

USER 6

25

0x0000 0D32

2

User-Defined Trap

-

-

USER 7

26

0x0000 0D34

2

User-Defined Trap

-

-

USER 8

27

0x0000 0D36

2

User-Defined Trap

-

-

USER 9

28

0x0000 0D38

2

User-Defined Trap

-

-

USER 10

29

0x0000 0D3A

2

User-Defined Trap

-

-

USER 11

30

0x0000 0D3C

2

User-Defined Trap

-

-

USER 12

31

0x0000 0D3E

2

User-Defined Trap

-

-

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Peripheral Interrupts

www.ti.com

Table 2-4 shows the Pie vector table.
Table 2-4. PIE Interrupt Vectors
Name

Vector ID

Address

Size (x16)

Description

Core priority

ePIE group
Priority

ADCA1 interrupt

5

1 (Highest)

PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1

32

0x0000 0D40

2

INT1.2

33

0x0000 0D42

2

ADCB1 interrupt

5

2

INT1.3

34

0x0000 0D44

2

ADCC1 interrupt

5

3

INT1.4

35

0x0000 0D46

2

XINT1 interrupt

5

4

INT1.5

36

0x0000 0D48

2

XINT2 interrupt

5

5

INT1.6

37

0x0000 0D4A

2

ADCD1 interrupt

5

6

INT1.7

38

0x0000 0D4C

2

TIMER0 interrupt

5

7

INT1.8

39

0x0000 0D4E

2

WAKE interrupt

5

8

INT1.9

128

0x0000 0E00

2

Reserved

5

9

INT1.10

129

0x0000 0E02

2

Reserved

5

10

INT1.11

130

0x0000 0E04

2

Reserved

5

11

INT1.12

131

0x0000 0E06

2

Reserved

5

12

INT1.13

132

0x0000 0E08

2

IPC1 interrupt

5

13

INT1.14

133

0x0000 0E0A

2

IPC2 interrupt

5

14

INT1.15

134

0x0000 0E0C

2

IPC3 interrupt

5

15

INT1.16

135

0x0000 0E0E

2

IPC4 interrupt

5

16 (Lowest)

PIE Group 2 Vectors - Muxed into CPU INT2
INT2.1

40

0x0000 0D50

2

EPWM1_TZ
interrupt

6

1 (Highest)

INT2.2

41

0x0000 0D52

2

EPWM2_TZ
interrupt

6

2

INT2.3

42

0x0000 0D54

2

EPWM3_TZ
interrupt

6

3

INT2.4

43

0x0000 0D56

2

EPWM4_TZ
interrupt

6

4

INT2.5

44

0x0000 0D58

2

EPWM5_TZ
interrupt

6

5

INT2.6

45

0x0000 0D5A

2

EPWM6_TZ
interrupt

6

6

INT2.7

46

0x0000 0D5C

2

EPWM7_TZ
interrupt

6

7

INT2.8

47

0x0000 0D5E

2

EPWM8_TZ
interrupt

6

8

INT2.9

136

0x0000 0E10

2

EPWM9_TZ
interrupt

6

9

INT2.10

137

0x0000 0E12

2

EPWM10_TZ
interrupt

6

10

INT2.11

138

0x0000 0E14

2

EPWM11_TZ
interrupt

6

11

INT2.12

139

0x0000 0E16

2

EPWM12_TZ
interrupt

6

12

INT2.13

140

0x0000 0E18

2

Reserved

6

13

INT2.14

141

0x0000 0E1A

2

Reserved

6

14

INT2.15

142

0x0000 0E1C

2

Reserved

6

15

INT2.16

143

0x0000 0E1E

2

Reserved

6

16 (Lowest)

PIE Group 3 Vectors - Muxed into CPU INT3
INT3.1

48

0x0000 0D60

2

EPWM1 interrupt

7

1 (Highest)

INT3.2

49

0x0000 0D62

2

EPWM2 interrupt

7

2

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

97

Peripheral Interrupts

www.ti.com

Table 2-4. PIE Interrupt Vectors (continued)
Name

Vector ID

Address

Size (x16)

Description

Core priority

ePIE group
Priority

INT3.3

50

0x0000 0D64

2

EPWM3 interrupt

7

3

INT3.4

51

0x0000 0D66

2

EPWM4 interrupt

7

4

INT3.5

52

0x0000 0D68

2

EPWM5 interrupt

7

5

INT3.6

53

0x0000 0D6A

2

EPWM6 interrupt

7

6

INT3.7

54

0x0000 0D6C

2

EPWM7 interrupt

7

7

INT3.8

55

0x0000 0D6E

2

EPWM8 interrupt

7

8

INT3.9

144

0x0000 0E20

2

EPWM9 interrupt

7

9

INT3.10

145

0x0000 0E22

2

EPWM10
interrupt

7

10

INT3.11

146

0x0000 0E24

2

EPWM11
interrupt

7

11

INT3.12

147

0x0000 0E26

2

EPWM12
interrupt

7

12

INT3.13

148

0x0000 0E28

2

Reserved

7

13

INT3.14

149

0x0000 0E2A

2

Reserved

7

14

INT3.15

150

0x0000 0E2C

2

Reserved

7

15

INT3.16

151

0x0000 0E2E

2

Reserved

7

16 (Lowest)

PIE Group 4 Vectors - Muxed into CPU INT4
INT4.1

56

0x0000 0D70

2

ECAP1 interrupt

8

1 (Highest)

INT4.2

57

0x0000 0D72

2

ECAP2 interrupt

8

2

INT4.3

58

0x0000 0D74

2

ECAP3 interrupt

8

3

INT4.4

59

0x0000 0D76

2

ECAP4 interrupt

8

4

INT4.5

60

0x0000 0D78

2

ECAP5 interrupt

8

5

INT4.6

61

0x0000 0D7A

2

ECAP6 interrupt

8

6

INT4.7

62

0x0000 0D7C

2

Reserved

8

7

INT4.8

63

0x0000 0D7E

2

Reserved

8

8

INT4.9

152

0x0000 0E30

2

Reserved

8

9

INT4.10

153

0x0000 0E32

2

Reserved

8

10

INT4.11

154

0x0000 0E34

2

Reserved

8

11

INT4.12

155

0x0000 0E36

2

Reserved

8

12

INT4.13

156

0x0000 0E38

2

Reserved

8

13

INT4.14

157

0x0000 0E3A

2

Reserved

8

14

INT4.15

158

0x0000 0E3C

2

Reserved

8

15

INT4.16

159

0x0000 0E3E

2

Reserved

8

16 (Lowest)

PIE Group 5 Vectors - Muxed into CPU INT5

98

INT5.1

64

0x0000 0D80

2

EQEP1 interrupt

9

1 (Highest)

INT5.2

65

0x0000 0D82

2

EQEP2 interrupt

9

2

INT5.3

66

0x0000 0D84

2

EQEP3 interrupt

9

3

INT5.4

67

0x0000 0D86

2

Reserved

9

4

INT5.5

68

0x0000 0D88

2

Reserved

9

5

INT5.6

69

0x0000 0D8A

2

Reserved

9

6

INT5.7

70

0x0000 0D8C

2

Reserved

9

7

INT5.8

71

0x0000 0D8E

2

Reserved

9

8

INT5.9

160

0x0000 0E40

2

SD1 interrupt

9

9

INT5.10

161

0x0000 0E42

2

SD2 interrupt

9

10

INT5.11

162

0x0000 0E44

2

Reserved

9

11

INT5.12

163

0x0000 0E46

2

Reserved

9

12

INT5.13

164

0x0000 0E48

2

Reserved

9

13

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Peripheral Interrupts

www.ti.com

Table 2-4. PIE Interrupt Vectors (continued)
Name

Vector ID

Address

Size (x16)

Description

Core priority

ePIE group
Priority

INT5.14
INT5.15

165

0x0000 0E4A

2

Reserved

9

14

166

0x0000 0E4C

2

Reserved

9

INT5.16

15

167

0x0000 0E4E

2

Reserved

9

16 (Lowest)

PIE Group 6 Vectors - Muxed into CPU INT6
INT6.1

72

0x0000 0D90

2

SPIA_RX
interrupt

10

1 (Highest)

INT6.2

73

0x0000 0D92

2

SPIA_TX
interrupt

10

2

INT6.3

74

0x0000 0D94

2

SPIB_RX
interrupt

10

3

INT6.4

75

0x0000 0D96

2

SPIB_TX
interrupt

10

4

INT6.5

76

0x0000 0D98

2

MCBSPA_RX
interrupt

10

5

INT6.6

77

0x0000 0D9A

2

MCBSPA_TX
interrupt

10

6

INT6.7

78

0x0000 0D9C

2

MCBSPB_RX
interrupt

10

7

INT6.8

79

0x0000 0D9E

2

MCBSPB_TX
interrupt

10

8

INT6.9

168

0x0000 0E50

2

SPIC_RX
interrupt

10

9

INT6.10

169

0x0000 0E52

2

SPIC_TX
interrupt

10

10

INT6.11

170

0x0000 0E54

2

Reserved

10

11

INT6.12

171

0x0000 0E56

2

Reserved

10

12

INT6.13

172

0x0000 0E58

2

Reserved

10

13

INT6.14

173

0x0000 0E5A

2

Reserved

10

14

INT6.15

174

0x0000 0E5C

2

Reserved

10

15

INT6.16

175

0x0000 0E5E

2

Reserved

10

16 (Lowest)

PIE Group 7 Vectors - Muxed into CPU INT7
INT7.1

80

0x0000 0DA0

2

DMA_CH1
interrupt

11

1 (Highest)

INT7.2

81

0x0000 0DA2

2

DMA_CH2
interrupt

11

2

INT7.3

82

0x0000 0DA4

2

DMA_CH3
interrupt

11

3

INT7.4

83

0x0000 0DA6

2

DMA_CH4
interrupt

11

4

INT7.5

84

0x0000 0DA8

2

DMA_CH5
interrupt

11

5

INT7.6

85

0x0000 0DAA

2

DMA_CH6
interrupt

11

6

INT7.7

86

0x0000 0DAC

2

Reserved

11

7

INT7.8

87

0x0000 0DAE

2

Reserved

11

8

INT7.9

176

0x0000 0E60

2

Reserved

11

9

INT7.10

177

0x0000 0E62

2

Reserved

11

10

INT7.11

178

0x0000 0E64

2

Reserved

11

11

INT7.12

179

0x0000 0E66

2

Reserved

11

12

INT7.13

180

0x0000 0E68

2

Reserved

11

13

INT7.14

181

0x0000 0E6A

2

Reserved

11

14

INT7.15

182

0x0000 0E6C

2

Reserved

11

15

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

99

Peripheral Interrupts

www.ti.com

Table 2-4. PIE Interrupt Vectors (continued)
Name

Vector ID

Address

Size (x16)

Description

Core priority

ePIE group
Priority

INT7.16

183

0x0000 0E6E

2

Reserved

11

16 (Lowest)

PIE Group 8 Vectors - Muxed into CPU INT8
INT8.1

88

0x0000 0DB0

2

I2CA interrupt

12

1 (Highest)

INT8.2

89

0x0000 0DB2

2

I2CA_FIFO
interrupt

12

2

INT8.3

90

0x0000 0DB4

2

I2CB interrupt

12

3

INT8.4

91

0x0000 0DB6

2

I2CB_FIFO
interrupt

12

4

INT8.5

92

0x0000 0DB8

2

SCIC_RX
interrupt

12

5

INT8.6

93

0x0000 0DBA

2

SCIC_TX
interrupt

12

6

INT8.7

94

0x0000 0DBC

2

SCID_RX
interrupt

12

7

INT8.8

95

0x0000 0DBE

2

SCID_TX
interrupt

12

8

INT8.9

184

0x0000 0E70

2

Reserved

12

9

INT8.10

185

0x0000 0E72

2

Reserved

12

10

INT8.11

186

0x0000 0E74

2

Reserved

12

11

INT8.12

187

0x0000 0E76

2

Reserved

12

12

INT8.13

188

0x0000 0E78

2

Reserved

12

13

INT8.14

189

0x0000 0E7A

2

Reserved

12

14

INT8.15

190

0x0000 0E7C

2

UPPA interrupt
(CPU1 only)

12

15

INT8.16

191

0x0000 0E7E

2

Reserved

12

16 (Lowest)

PIE Group 9 Vectors - Muxed into CPU INT9
INT9.1

96

0x0000 0DC0

2

SCIA_RX
interrupt

13

1 (Highest)

INT9.2

97

0x0000 0DC2

2

SCIA_TX
interrupt

13

2

INT9.3

98

0x0000 0DC4

2

SCIB_RX
interrupt

13

3

INT9.4

99

0x0000 0DC6

2

SCIB_TX
interrupt

13

4

INT9.5

100

0x0000 0DC8

2

CANA interrupt 0

13

5

INT9.6

101

0x0000 0DCA

2

CANA interrupt 1

13

6

INT9.7

102

0x0000 0DCC

2

CANB interrupt 0

13

7

INT9.8

103

0x0000 0DCE

2

CANB interrupt 1

13

8

INT9.9

192

0x0000 0E80

2

Reserved

13

9

INT9.10

193

0x0000 0E82

2

Reserved

13

10

INT9.11

194

0x0000 0E84

2

Reserved

13

11

INT9.12

195

0x0000 0E86

2

Reserved

13

12

INT9.13

196

0x0000 0E88

2

Reserved

13

13

INT9.14

197

0x0000 0E8A

2

Reserved

13

14

INT9.15

198

0x0000 0E8C

2

USBA interrupt
(CPU1 only)

13

15

INT9.16

199

0x0000 0E8E

2

Reserved

13

16 (Lowest)

PIE Group 10 Vectors - Muxed into CPU INT10
INT10.1

104

0x0000 0DD0

2

ADCA_EVT
interrupt

14

1 (Highest)

INT10.2

105

0x0000 0DD2

2

ADCA2 interrupt

14

2

100 System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Peripheral Interrupts

www.ti.com

Table 2-4. PIE Interrupt Vectors (continued)
Name

Vector ID

Address

Size (x16)

Description

Core priority

ePIE group
Priority

INT10.3

106

0x0000 0DD4

2

ADCA3 interrupt

14

3

INT10.4

107

0x0000 0DD6

2

ADCA4 interrupt

14

4

INT10.5

108

0x0000 0DD8

2

ADCB_EVT
interrupt

14

5

INT10.6

109

0x0000 0DDA

2

ADCB2 interrupt

14

6

INT10.7

110

0x0000 0DDC

2

ADCB3 interrupt

14

7

INT10.8

111

0x0000 0DDE

2

ADCB4 interrupt

14

8

INT10.9

200

0x0000 0E90

2

ADCC_EVT
interrupt

14

9

INT10.10

201

0x0000 0E92

2

ADCC2 interrupt

14

10

INT10.11

202

0x0000 0E94

2

ADCC3 interrupt

14

11

INT10.12

203

0x0000 0E96

2

ADCC4 interrupt

14

12

INT10.13

204

0x0000 0E98

2

ADCD_EVT
interrupt

14

13

INT10.14

205

0x0000 0E9A

2

ADCD2 interrupt

14

14

INT10.15

206

0x0000 0E9C

2

ADCD3 interrupt

14

15

INT10.16

207

0x0000 0E9E

2

ADCD4 interrupt

14

16 (Lowest)

PIE Group 11 Vectors - Muxed into CPU INT11
INT11.1

112

0x0000 0DE0

2

CLA1_1 interrupt

15

1 (Highest)

INT11.2

113

0x0000 0DE2

2

CLA1_2 interrupt

15

2

INT11.3

114

0x0000 0DE4

2

CLA1_3 interrupt

15

3

INT11.4

115

0x0000 0DE6

2

CLA1_4 interrupt

15

4

INT11.5

116

0x0000 0DE8

2

CLA1_5 interrupt

15

5

INT11.6

117

0x0000 0DEA

2

CLA1_6 interrupt

15

6

INT11.7

118

0x0000 0DEC

2

CLA1_7 interrupt

15

7

INT11.8

119

0x0000 0DEE

2

CLA1_8 interrupt

15

8

INT11.9

208

0x0000 0EA0

2

Reserved

15

9

INT11.10

209

0x0000 0EA2

2

Reserved

15

10

INT11.11

210

0x0000 0EA4

2

Reserved

15

11

INT11.12

211

0x0000 0EA6

2

Reserved

15

12

INT11.13

212

0x0000 0EA8

2

Reserved

15

13

INT11.14

213

0x0000 0EAA

2

Reserved

15

14

INT11.15

214

0x0000 0EAC

2

Reserved

15

15

INT11.16

215

0x0000 0EAE

2

Reserved

15

16 (Lowest)

PIE Group 12 Vectors - Muxed into CPU INT12
INT12.1

120

0x0000 0DF0

2

XINT3 interrupt

16

1 (Highest)

INT12.2

121

0x0000 0DF2

2

XINT4 interrupt

16

2

INT12.3

122

0x0000 0DF4

2

XINT5 interrupt

16

3

INT12.4

123

0x0000 0DF6

2

Reserved

16

4

INT12.5

124

0x0000 0DF8

2

Reserved

16

5

INT12.6

125

0x0000 0DFA

2

VCU interrupt

16

6

INT12.7

126

0x0000 0DFC

2

FPU_OVERFLO
W interrupt

16

7

INT12.8

127

0x0000 0DFE

2

FPU_UNDERFL
OW interrupt

16

8

INT12.9

216

0x0000 0EB0

2

EMIF_ERROR
interrupt

16

9

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control 101

Exceptions and Non-Maskable Interrupts

www.ti.com

Table 2-4. PIE Interrupt Vectors (continued)

2.5

Name

Vector ID

Address

Size (x16)

Description

Core priority

ePIE group
Priority

INT12.10

217

0x0000 0EB2

2

RAM_CORREC
TABLE_ERROR
interrupt

16

10

INT12.11

218

0x0000 0EB4

2

FLASH_CORRE
CTABLE_ERRO
R interrupt

16

11

INT12.12

219

0x0000 0EB6

2

RAM_ACCESS_
VIOLATION
interrupt

16

12

INT12.13

220

0x0000 0EB8

2

SYS_PLL_SLIP
interrupt

16

13

INT12.14

221

0x0000 0EBA

2

AUX_PLL_SLIP
interrupt

16

14

INT12.15

222

0x0000 0EBC

2

CLA_OVERFLO
W interrupt

16

15

INT12.16

223

0x0000 0EBE

2

CLA_UNDERFL
OW interrupt

16

16 (Lowest)

Exceptions and Non-Maskable Interrupts
This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.

2.5.1 Configuring and Using NMIs
Each CPU has its own NMI module. An incoming NMI sets a status bit in the NMIFLG register and starts
the NMI watchdog counter. This counter is clocked by the SYSCLK, and if it reaches the value in the
NMIWDPRD register, it triggers an NMI watchdog reset (NMIWDRS). To prevent this, the NMI handler
must clear the flag bit using the NMIFLGCLR register. Once all flag bits are clear, the NMIINT bit in the
NMIFLG register may also be cleared to allow future NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI
handler vector must be written to the PIE vector table.

2.5.2 Emulation Considerations
The NMI watchdog counter behaves as follows under debug conditions:
CPU Suspended
Run-Free Mode
Real-Time Single-Step Mode

Real-Time Run-Free Mode

102

System Control

When the CPU is suspended, the NMI watchdog counter will
be suspended.
When the CPU is placed in run-free mode, the NMI watchdog
counter will resume operation as normal.
When the CPU is in real-time single-step mode, the NMI
watchdog counter will be suspended. The counter remains
suspended even within real-time interrupts.
When the CPU is in real-time run-free mode, the NMI
watchdog counter operates as normal.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Exceptions and Non-Maskable Interrupts

www.ti.com

2.5.3 NMI Sources
There are several types of hardware errors that can trigger an NMI. Additional information about the error
is usually available from the module that detects it.
2.5.3.1

Missing Clock Detection

The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and NMIs are fired to both CPUs. For more information on
missing clock detection, see Section 2.6.2.
2.5.3.2

RAM Uncorrectable ECC Error

A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read will
trigger an NMI. This applies to CPU, CLA, and DMA reads. Single-bit ECC data errors do not trigger an
NMI, but can optionally trigger a normal peripheral interrupt. For more information on RAM error detection,
see Section 2.11.1.8.
2.5.3.3

Flash Uncorrectable ECC Error

A double-bit ECC data error or single-bit ECC address error in a flash read will trigger an NMI. Single-bit
ECC data errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt. For more
information on flash error detection, see Section 2.12.10.
2.5.3.4

NMI Vector Fetch Mismatch

Each CPU's Peripheral Interrupt Expansion module (PIE) has redundant vector tables. If a mismatch in
these tables is detected during a vector fetch, a user-specified error handler is run instead of the ISR. If
the vector fetch was caused by an NMI, a second NMI is fired to the other CPU. Mismatches for other
interrupts do not trigger an NMI. For more information about the vector address check, see Section 2.6.4.
2.5.3.5

CPU2 Watchdog or NMI Watchdog Reset

A watchdog reset or NMI watchdog reset on CPU2 will trigger an NMI on CPU1. Since a CPU1 reset also
resets CPU2, this NMI source is not available on CPU2.
Watchdog interrupts do not trigger an NMI.

2.5.4 Illegal Instruction Trap (ITRAP)
If the CPU tries to execute an illegal instruction, it generates a special interrupt called an illegal instruction
trap (ITRAP). This interrupt is non-maskable and has its own vector in the PIE vector table. For more
information about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and
Instruction Set Reference Guide (SPRU430).
NOTE: A RAM fetch access violation will trigger an ITRAP in addition to the normal peripheral
interrupt for RAM access violations. The CPU will handle the ITRAP first.

2.6

Safety Features
This section gives details on features that monitor device operation during run-time to detect any error in
operation.

2.6.1 Write Protection on Registers
2.6.1.1

LOCK Protection on System Configuration Registers

Several system configuration registers are protected from spurious CPU writes by “LOCK” registers. Once
these associated LOCK register bits are set the respective locked registers can no longer be modified by
software. See specific register descriptions for details.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

103

Safety Features

2.6.1.2

www.ti.com

EALLOW Protection

Several control registers are protected from spurious CPU writes by the EALLOW protection mechanism.
The EALLOW bit in status register 1 (ST1) indicates the state of protection as shown in Table 2-5.
Table 2-5. Access to EALLOW-Protected Registers

(1)

EALLOW Bit

CPU Writes

CPU Reads

JTAG Writes

JTAG Reads

0

Ignored

Allowed

Allowed (1)

Allowed

1

Allowed

Allowed

Allowed

Allowed

The EALLOW bit is overridden via the JTAG port, allowing full access of protected registers during debug from the Code
Composer Studio interface.

At reset, the EALLOW bit is cleared, enabling EALLOW protection. While protected, all writes to protected
registers by the CPU are ignored and only CPU reads, JTAG reads, and JTAG writes are allowed. If this
bit is set, by executing the EALLOW instruction, the CPU is allowed to write freely to protected registers.
After modifying registers, they can once again be protected by executing the EDIS instruction to clear the
EALLOW bit.

2.6.2 Missing Clock Detection Logic
The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock
source. This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift
on the OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10 MHz clock provided by the INTOSC1
(secondary clock) as a backup clock. This circuit functions as below:
1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter
is asynchronously reset with XRS.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This
counter is asynchronously reset with XRS.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or not
slower than INTOSC1 by a factor of 64, MCDSCNT will never overflow.
4. If OSCCLK stops for some reason, or is slower than INTOSC1 by at least a factor of 64, the
MCDSCNT will overflow and a missing clock condition will be detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making
the MCLKOFF bit 1)
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCDSTS flag is set
• The MCDSCNT counter is frozen to prevent further missing clock detection
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs
to CPU1.NMIWD and CPU2.NMIWD.
• PLL is forcefully bypassed and OSCCLK is switched to INTOSC1 (after the PLLSYSCLK divider).
PLLMULT is zeroed out automatically in this case.
• While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically
7. If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit will be cleared and OSCCLK source will
be decided by the OSCCLKSRCSEL bits. Writing to MCLKCLR will also clear the MCDPCNT and
MCDSCNT counters to allow the circuit re-evaluate missing clock detection. If user wants to lock the
PLL after missing clock detection, he needs to first switch the clock source to INTOSC1 (using
OSCCLKSRCSEL register), do a MCLKCLR and re-lock the PLL.
8. The MCD is enabled at power up. There is no support for missing clock detection if INTOSC2 is failed
from the device power-up.
Figure 2-3 shows the missing clock logic functional flow.
104

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Safety Features

www.ti.com

Figure 2-3. Missing Clock Detection Logic
Secondary Clock

INTOSC1
Primary Clock

INTOSC2

CLOCKFAIL

Missing
Clock
Detect
(MCD)
Logic

OSCCLK
Source
Select
Ckt

INTOSC1

Low
Power
Mode
Ckt

OSCCLK

X1/X2

CLKSRCCTL1.OSCCLRSRCSEL
SYSPLL
PLLRAWCLK

PLL Locking
Control
Ckt

Registers

Switch
Ckt
Mux
(glitchfree)

/1,
/2,
/4
..
/124
/126

PLLSYSCLK

Clock Dividers

SYSPLLCTL1/2/3,
SYSPLLMULT,
SYSPLLSTS

Clock Sources

2.6.3 PLLSLIP Detection
The PLL SLIP detection on this device can detect if the PLL reference clock goes too high or too slow
while PLL is locked. An interrupt to both the CPUs is triggered as shown in the ePIE table in Section 2.4.
Apart from the interrupt to both the CPUs, the PLLSTS.SLIP bit is set for user software to check the error.
The SLIP detection is available on both SYSPLL and AUXPLL.

2.6.4 CPU1 and CPU2 PIE Vector Address Validity Check
The ePIE vector table on each CPU is duplicated into these two parts:
• Main ePIE Vector Table mapped from 0xD00 to 0xEFF in the C28x memory space
• Redundant ePIE Vector Table mapped from 0x1000D00 to 0x1000EFF in the C28x memory space
Following is the behavior of accesses to the ePIE memories:
• Data Writes to Main Vector Table: Writes to both memories
• Data Writes to Redundant Vector Table: Writes only to the Redundant Vector Table
• Vector Fetch: Data from both the vector tables are compared
• Data Read: Can read the Main and Redundant vector table separately
On every vector fetch from the ePIE, a hardware comparison (no cycle penalty is incurred to do the
comparison) of both the vector table outputs is performed and if there is a mismatch between the two
vector table outputs, the following occurs:
1. If the PIEVERRADDR register (default value 0x3F FFFF) is not initialized, the default error handler at
address 0x3FFFBE gets executed.
But, when the PIEVERRADDR register is initialized to the address of the user-defined routine, the
user-defined routine is executed instead of the default error handler.
Note: Each CPU has its own copy of the PIE Vector Fetch Error Handler register
(CPU1.PIEVERRADDR and CPU2.PIEVERRADDR).
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

105

Safety Features

www.ti.com

2. Hardware also generates EPWM Trip signals which will trip the PWM outputs using TRIPIN15.
3. An NMI to the other CPU is sent if the current mismatch is during a vector fetch. For example, on an
NMI vector fetch error for CPU2, an NMI is also fired to CPU1.NMIWD.
If there is no mismatch, the correct vector is jammed onto the C28 program control.

2.6.5 NMIWDs
Each CPU has user-programmable NMIWD period registers, in which users can set a limit on how much
time they want to allocate for the device to acknowledge the NMI. If the NMI is not acknowledged, it will
cause a device reset.

2.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection
Each CPU subsystem has different RAM blocks. Few RAM blocks are ECC-enabled and others are parityenabled. All single-bit errors in ECC RAM are auto-corrected and an error counter is incremented every
time a single bit error is detected. If the error counter reaches a predefined user configured limit, an
interrupt is generated to the corresponding CPU. Refer to Section 2.11 for more details on RAM errors.
All uncorrectable double-bit errors end up triggering an NMI to corresponding CPUs.

2.6.7 ECC Enabled Flash Memory
When ECC is programmed and enabled, flash single-bit errors are corrected automatically by ECC logic
before giving data to the CPU, but they are not corrected in flash memory. Flash memory will still contain
wrong data until another erase/program operation happens to correct the flash contents. Irrespective of
whether the error interrupt is enabled or disabled, single-bit errors are always corrected before giving data
to the CPU. When the interrupt is disabled, users can check the single-bit error counter register for any
single-bit error occurrences. The error counter stops incrementing once its value is equal to the
threshold+1. It is always suggested to set the threshold register to a non-zero value so that the error
counter can increment. It is up to the user to decide the threshold value at which they have to reprogram
the flash with the correct data.
When ECC is programmed and enabled, flash uncorrectable errors end up triggering an NMI to the
respective CPU. Please refer to Section 2.11 for more details on flash error correction and error catching
mechanisms.

2.6.8 ERRORSTS Pin
The ERRORSTS pin is an ‘always output’ pin and remains low until an error is detected inside the chip.
On an error, the ERRORSTS pin goes high until the corresponding internal error status flag for that error
source is cleared. Figure 2-4 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin will be tri-stated until the chip power rails ramp up to the lower operational limit. As
the ERRORSTS pin is an active-high pin, users who care about the state of this pin during power-up
should connect an external pull-down on this pin.

106

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Clocking

www.ti.com

Figure 2-4. ERRORSTS Pin Diagram
CPU1's NMIWD Shadow flags

CPU1.NMIWD.NMISHDFLG.Bit-0

CPU1.NMIWD.NMISHDFLG.Bit-1

CPU1.NMIWD.NMISHDFLG.Bit-15

CPU2's NMIWD Shadow flags
ERROR
CPU2.NMIWD.NMISHDFLG.Bit-0

CPU2.NMIWD.NMISHDFLG.Bit-1

CPU2.NMIWD.NMISHDFLG.Bit-15

2.7

Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 2-5 provides an overview of the device's clocking system.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

107

Clocking

www.ti.com

Figure 2-5. Clocking System
INTOSC1

WDCLK

CLKSRCCTL1

INTOSC2

SYSPLLCTL1

SYSCLKDIVSEL

SYSCLK
Divider

OSCCLK
X1 (XTAL)

System PLL

To watchdog timers

PLLRAWCLK

PLLSYSCLK

To GS RAMs, GPIOs,
NMIWDs, and IPC

CPU1.SYSCLK

CPU1

CPU1.CPUCLK

To local memories

CPU2.SYSCLK

CPU2

CPU2.CPUCLK

To local memories

CPU1.SYSCLK
CPU2.SYSCLK

To ePIEs, LS RAMs,
CLA message RAMs,
and DCSMs

PERx.SYSCLK

To peripherals

PERx.LSPCLK

To SCIs, SPIs, and
McBSPs

EPWMCLK

To ePWMs

One per SYSCLK peripheral
CPUSELx

CPU1.PCLKCRx

CPU2.PCLKCRx
One per LSPCLK peripheral
LOSPCP

CPUSELx

CPU1.PCLKCRx
LSP
Divider
CPU2.PCLKCRx

One per ePWM
EPWMCLKDIV
PLLSYSCLK

CPU1.PCLKCRx

CPUSELx

/1
/2
CPU2.PCLKCRx
HRPWM
CPU1.PCLKCRx

HRPWMCLK

To HRPWM Registers

CAN Bit Clock

To CANs

AUXPLLCLK

To USB bit clock

One per CAN module
CPUSELx

CLKSRCCTL2

AUXCLKIN

CLKSRCCTL2

AUXPLLCTL1

AUXOSCCLK
Auxiliary PLL

108

System Control

AUXPLLRAWCLK

AUXCLKDIVSEL

AUXCLK
Divider

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Clocking

www.ti.com

Note: The default/2 divider for ePWMs and EMIFs is not shown.

2.7.1 Clock Sources
All of the clocks in the device are derived from one of four clock sources.
2.7.1.1

Primary Internal Oscillator (INTOSC2)

At power-up, the device is clocked from an on-chip 10 MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source, and is the default system clock at reset. It is used to run the boot ROM and can be
used as the system clock source for the application. Note that INTOSC2's frequency tolerance is too loose
to meet the timing requirements for CAN and USB, so an external clock must be used to support those
features.
2.7.1.2

Backup Internal Oscillator (INTOSC1)

The device also includes a redundant on-chip 10 MHz oscillator (INTOSC1). INTOSC1 is a backup clock
source that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is
enabled and a missing system clock is detected, the system PLL is bypassed and all system clocks are
connected to INTOSC1 automatically. INTOSC1 may also be manually selected as the system and
auxiliary clock source for debug purposes.
2.7.1.3

External Oscillator (XTAL)

The dedicated X1 and X2 pins support an external clock source (XTAL), which can be used as the main
system and auxiliary clock source. Frequency limits and timing requirements can be found in the device
datasheet. Three types of external clock sources are supported:
• A single-ended 3.3V external clock. The clock signal should be connected to X1 while X2 is left
unconnected, as shown in Figure 2-6.
Figure 2-6. Single-ended 3.3V External Clock

VDDOSC

X1

X2

NC

3.3V
3.3V

VSSOSC

Clk

VDD

OUT

GND
3.3V Oscillator

•

An external crystal. The crystal should be connected across X1 and X2 with its load capacitors
connected to VSSOSC as shown in Figure 2-7.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

109

Clocking

www.ti.com

Figure 2-7. External Crystal

VDDOSC X1

VSSOSC

X2

3.3V
Crystal

RD

•

CL2

CL1

An external resonator. The resonator should be connected across X1 and X2 with its ground
connected to VSSOSC as shown in Figure 2-8.
Figure 2-8. External Resonator

VDDOSC X1

VSSOSC

X2

3.3V
Resonator

2.7.1.4

Auxiliary Clock Input (AUXCLKIN)

An additional external clock source is supported on GPIO133 (AUXCLKIN). This must be a single-ended
3.3V external clock. It can be used as the source for the USB and CAN bit clocks. Frequency limits and
timing requirements can be found in the device datasheet. The external clock should be connected directly
to the GPIO133 pin, as shown in Figure 2-9.
Figure 2-9. AUXCLKIN

110

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Clocking

www.ti.com

2.7.2 Derived Clocks
The clock sources discussed in the previous section can be multiplied (via PLL) and divided down to
produce the desired clock frequencies for the application. This process produces a set of derived clocks,
which are described in this section.
2.7.2.1

Oscillator Clock (OSCCLK)

One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the master reference clock (OSCCLK) for the
CPU and most of the peripherals. OSCCLK may be used directly or fed through the system PLL to reach
a higher frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.
2.7.2.2

System PLL Output Clock (PLLRAWCLK)

The system PLL allows the device to run at its maximum rated operating frequency, and in most
applications will generate the main system clock. This PLL uses OSCCLK as a reference, and features a
fractional multiplier and slip detection. For configuration instructions, see Section 2.7.6.
2.7.2.3

Auxiliary Oscillator Clock (AUXOSCCLK)

One of INTOSC2, XTAL, or AUXCLKIN may be chosen to be the auxiliary reference clock (AUXOSCCLK)
for the USB module. (This selection does not affect the CAN bit clock, which uses AUXCLKIN directly).
AUXOSCCLK may be used directly or fed through the auxiliary PLL to reach a higher frequency. At reset,
AUXOSCCLK is connected to INTOSC2, but only an external oscillator can meet the USB timing
requirements.
2.7.2.4

Auxiliary PLL Output Clock (AUXPLLRAWCLK)

The auxiliary PLL is used to generate a 60 MHz clock for the USB module. This PLL uses AUXOSCCLK
as a reference, and features a fractional multiplier and slip detection. For configuration instructions, see
Section 2.7.6.

2.7.3 Device Clock Domains
The device clock domains feed the clock inputs of the various modules in the device. They are connected
to the derived clocks, either directly or through an additional divider.
2.7.3.1

System Clock (PLLSYSCLK)

The system control registers, GS RAMs, IPC module, GPIO qualification, and NMI watchdog timers have
their own clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK may be connected to the system
PLL (PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider, which is
configured via the SYSCLKDIVSEL register. PLLSYSCLK is gated in HALT mode.
2.7.3.2

CPU Clock (CPUCLK)

Each CPU has its own clock (CPU1.CPUCLK and CPU2.CPUCLK) which is used to clock the CPU, its
coprocessors, its private RAMs (M0, M1, D0, and D1), and its boot ROM and flash wrapper. This clock is
identical to PLLSYSCLK, but is gated when the CPU enters IDLE, STANDBY, or HALT mode.
2.7.3.3

CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)

Each CPU provides a clock (CPU1.SYSCLK and CPU2.SYSCLK) to its CLA, DMA, and most owned
peripherals. This clock is identical to PLLSYSCLK, but is gated when the CPU enters STANDBY or HALT
mode.
Each peripheral clock can be connected to either CPU1.SYSCLK or CPU2.SYSCLK. This selection is
made by CPU1 via the CPUSELx registers. Each peripheral clock also has its own independent clock
gating which is controlled by the CPU's PCLKCRx registers. By default, the ePWM, EMIF1, and EMIF2
clocks each have an additional /2 divider, which is required to support CPU frequencies over 100 MHz. At
slower CPU frequencies, these dividers can be disabled via the PERCLKDIVSEL register.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

111

Clocking

2.7.3.4

www.ti.com

Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)

The SCI, SPI, and McBSP modules can communicate at bit rates that are much slower than the CPU
frequency. These modules are connected to a shared clock divider, which generates a low-speed
peripheral clock (LSPCLK) derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can
be changed via the LOSPCP register. Each SCI, SPI, and McBSP module's clock (PERx.LSPCLK) can be
gated independently via the PCLKCRx registers.
2.7.3.5

USB Auxiliary Clock (AUXPLLCLK)

The USB module requires a fixed 60 MHz clock for bit sampling. Since the main system clock is usually
not a multiple of 60 MHz, the correct frequency cannot be achieved with a simple divider. Instead, the
USB clock is provided through an auxiliary clock path (AUXPLLCLK), which can use an independent clock
source and PLL to generate the correct frequency.
USB clock tolerances are very tight. As stated in section 7.1.11 of the USB 2.0 specification, low-speed
devices (1.50 Mb/s) have a tolerance of +/- 1.5% , while high-speed devices (12.000 Mb/s) have a
tolerance of +/- 0.25%. Typically these tolerances are achieved by using an external crystal or resonator
as the source for AUXOSCCLK.
2.7.3.6

CAN Bit Clock

The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network
configuration, and can be as tight as 0.1%. Since the main system clock (in the form of PERx.SYSCLK)
may not be precise enough, the bit clock can also be connected to XTAL or AUXCLKIN via the
CLKSRCCTL2 register. There is an independent selection for each CAN module.
2.7.3.7

CPU Timer2 Clock (TIMER2CLK)

CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default,
but may also be connected to INTOSC1, INTOSC2, XTAL, or AUXPLLCLK via the TMR2CLKCTL register.
This register also provides a separate prescale divider for timer 2. If a source other than SYSCLK is used,
the SYSCLK frequency must be at least twice the source frequency to ensure correct sampling. Each
CPU has its own independent CPU timers and TMR2CLKCTL register.
The main reason to use a non-SYSCLK source would be for internal frequency measurement. In most
applications, timer 2 will run off of the SYSCLK.

2.7.4 XCLKOUT
It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock
output (XCLKOUT) feature supports this by connecting a clock to an external pin, GPIO73. The available
clock sources are PLLSYSCLK, PLLRAWCLK, CPU1.SYSCLK, CPU2.SYSCLK, AUXPLLRAWCLK,
INTOSC1, and INTOSC2.
To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired
output divider via the XCLKOUTDIVSEL register. Finally, connect GPIO73 to mux channel 3 using the
GPIO configuration registers.

112

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Clocking

www.ti.com

2.7.5 Clock Connectivity
The tables below provide details on the clock connections of every module present in the device.
Table 2-6. Clock Connections Sorted by Clock Domain
Clock Domain
CPUx.CPUCLK

CPUx.SYSCLK

PLLSYSCLK

CPU1 Subsystem

CPU2 Subsystem

CPU1

CPU2

CPU1.VCU

CPU2.VCU

CPU1.FPU

CPU2.FPU

CPU1.TMU

CPU2.TMU

CPU1.M0 - M1 RAMs

CPU2.M0 - M1 RAMs

CPU1.D0 - D1 RAMs

CPU2.D0 - D1 RAMs

CPU1.BootROM

CPU2.BootROM

CPU1.Flash

CPU2.Flash

CPU1.ePIE

CPU2.ePIE

CPU1.LS0 - LS5 RAMs

CPU2.LS0 - LS5 RAMs

CPU1.CLA1 Message RAMs

CPU2.CLA1 Message RAMs

CPU1.DCSM

CPU2.DCSM

CPU1.NMIWD

CPU2.NMIWD

EMIF1

Shared Modules

GS0 - GS15 RAMs
GPIO Input Sync and Qual
IPC

PERx.SYSCLK

CPU1.CLA1

CPU2.CLA1

ADCA - D

CPU1.DMA

CPU2.DMA

CMPSS1 - 8

CPU1.Timer0 - 2

CPU2.Timer0 - 2

DACA - C

EMIF2

ePWM1 - 12

uPP A

eCAP1 - 6
eQEP1 - 3
I2CA - B
McBSPA - B
SDFM1 - 8

PERx.LSPCLK

McBSPA - B
SCIA - D
SPIA - C

CAN Bit Clock

CANA - B

AUXPLLCLK

USB

WDCLK (INTOSC1)

CPU1.Watchdog

CPU2.Watchdog

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control 113

Clocking

www.ti.com

Table 2-7. Clock Connections Sorted by Module Name
Module Name

Clock Domain

ADCA - D

PERx.SYSCLK

Boot ROM

CPUx.CPUCLK

CANA - B

CAN Bit Clock

CLA

PERx.SYSCLK

CLA Message RAMs

CPUx.SYSCLK

CMPSS1 - 8

PERx.SYSCLK

CPU

CPUx.CPUCLK

CPU Timers

PERx.SYSCLK

D0 - D1 RAMs

CPUx.CPUCLK

DACA - C

PERx.SYSCLK

DCSM

CPUx.SYSCLK

DMA

PERx.SYSCLK

eCAP1 - 6

PERx.SYSCLK

EMIF1

PLLSYSCLK

EMIF2

PERx.SYSCLK

ePIE

CPUx.SYSCLK

ePWM

PERx.SYSCLK

eQEP1 - 3

PERx.SYSCLK

Flash

CPUx.CPUCLK

FPU

CPUx.CPUCLK

GS0 - GS15 RAMs

PLLSYSCLK

I2CA - B

PERx.SYSCLK

IPC

PLLSYSCLK

LS0 - LS5 RAMs

CPUx.SYSCLK

M0 - M1 RAMs

CPUx.CPUCLK

McBSPA - B

PERx.LSPCLK

NMIWD

PLLSYSCLK

SCIA - D

PERx.LSPCLK

SDFM1 - 8

PERx.SYSCLK

SPIA - C

PERx.LSPCLK

TMU

CPUx.CPUCLK

uPP

PERx.SYSCLK

USB

AUXPLLCLK

VCU

CPUx.CPUCLK

Watchdog Timer

WDCLK (INTOSC1)

2.7.6 Clock Source and PLL Setup
The needs of the application are what ultimately determine the clock configuration. Specific concerns such
as application performance, power consumption, total system cost, and EMC are beyond the scope of this
document, but they should provide answers to the following questions:
1. What is the desired CPU frequency?
2. Is CAN required?
3. Is USB required?
4. What types of external oscillators or clock sources are available?

114

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Clocking

www.ti.com

If CAN or USB is required, an external clock source with a precise frequency must be used as a reference
clock. Otherwise, it may be possible to use only INTOSC2 and avoid the need for more external
components.
2.7.6.1

Choosing PLL Settings

There are two settings to configure for each PLL – a multiplier and a divider. They obey the formulas:
fPLLSYSCLK = fOSCCLK * (SYSPLLMULT.IMULT + SYSPLLMULT.FMULT) / SYSCLKDIVSEL.PLLSYSCLKDIV
fAUXPLLCLK = fAUXOSCCLK * (AUXPLLMULT.IMULT + AUXPLLMULT.FMULT) / AUXCLKDIVSEL.AUXPLLDIV
where fOSCCLK is the system oscillator clock frequency, fAUXOSCCLK is the auxiliary oscillator clock frequency,
IMULT and FMULT are the integral and fractional parts of the multipliers, PLLSYSCLKDIV is the system
clock divider, and AUXPLLDIV is the auxiliary clock divider. For the permissible values of the multipliers
and dividers, see the documentation for their respective registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the
product of the reference clock frequency and the multiplier (known as the VCO frequency) must be in the
range specified in the data manual.
NOTE: The system clock frequency (PLLSYSCLK) may not exceed the limit specified in the
datasheet. This limit does not allow for oscillator tolerance.

The clock source and PLL configuration registers are shared between the two CPUs. Register access is
controlled via a semaphore, which is described in the Inter-Processor Communication chapter.
2.7.6.2

System Clock Setup

Once the application requirements are understood, a specific clock configuration can be determined. The
default configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1.
The following procedure should be used to set up the desired application configuration:
1. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL.
2. Set up the system PLL: (see the InitSysPll() function in your devices controlSUITE installation for an
example):
a. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN].
b. Set the system clock divider to /1 to ensure the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
c. Set the integral and fractional multipliers by simultaneously writing them both to SYSPLLMULT.
This will automatically enable the PLL. Be sure that the product of OSCCLK and the multiplier is in
the range specified in the data manual.
d. Lock the PLL five times (see your device errata for details). This number can be increased
depending on application requirements. A higher number of lock attempts helps to ensure a
successful PLL start
e. Set the system clock divider one setting higher than the final desired value. For example
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1. This limits the current increase
when switching to the PLL.
f. Set up the watchdog to reset the device. Note that the SCRS[WDOVERRIDE] bit should not be
cleared prior to locking the PLL.
g. Set the SYSDBGCTL[BIT_0] bit. This bit is only reset by a POR reset. If the watchdog has to reset
the device due to an issue with switching to the PLL, this bit can be checked in the reset handler to
determine the reset was caused by a PLL error.
h. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].
i. Clear the SYSDBGCTL[BIT_0] bit.
j. Change the divider to the appropriate value.
k. Reconfigure the watchdog as needed for the application.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

115

Clocking

www.ti.com

NOTE: If the CPU2 changes the OSCCLK source, it will not automatically bypass the PLL. The
CPU2 must manually bypass the PLL first by writing a 0 to SYSPLLCTL1.PLLCLKEN.

2.7.6.3

USB Auxiliary Clock Setup

See the InitAuxPll() function in your device’s controlSUITE installation for an example.
If USB functionality is needed, the auxiliary clock (AUXPLLCLK) must be configured to produce 60 MHz.
The procedure is similar to the system clock setup:
1. Select the reference clock source (AUXOSCCLK) by writing to CLKSRCCTL2.AUXOSCCLKSRCSEL.
2. Wait two AUXOSCCLK cycles.
3. Set up the auxiliary PLL. If the PLL is not needed, bypass it and power it down by writing a 0 to
AUXPLLCTL1.PLLEN. To use the PLL:
a. Set the desired auxiliary clock divider by writing to AUXCLKDIVSEL.AUXPLLDIV.
b. ) Configure CPU Timer 2 to be clocked from AUXPLL. Keep the counter frozen.
c. ) Power down the AUXPLL by clearing AUXPLLCTL1[PLLEN].
d. Set the integral and fractional multipliers simultaneously. This will automatically enable the PLL. Be
sure that the product of AUXOSCCLK and the multiplier is in the range specified in the data
manual..
e. Wait for the PLL to lock by polling the AUXPLLSTS.LOCKS bit. This will take 16 µs plus 1024
AUXOSCCLK cycles.
f. Connect the auxiliary PLL output clock (AUXPLLRAWCLK) to AUXPLLCLK by writing a 1 to
AUXPLLCTL1.PLLCLKEN.
g. Start CPU Timer 2. In a large for() loop, continue polling the TCR[TIF] overflow flag. If it sets, the
AUXPLL started correctly. If not, repeat steps (c) through (g). The auxiliary clock configuration can
be changed at run time. Changing the AUXOSCCLK source will automatically bypass the PLL and
set the multiplier to zero. Changing the multiplier from one non-zero value to another will
temporarily bypass the PLL until it re-locks.
The auxiliary clock configuration can be changed at run time. Changing the AUXOSCCLK source will
automatically bypass the PLL and set the multiplier to zero. Changing the multiplier from one non-zero
value to another will temporarily bypass the PLL until it re-locks.
NOTE: If the AUXOSCCLK source is changed on the same AUXOSCCLK cycle as the multiplier, the
PLL will be disabled but the AUXPLLMULT register will show the written value. This can
happen when the system PLL is enabled before configuring the auxiliary PLL (CPUCLK >>
AUXOSCCLK). To avoid this issue, wait two AUXOSCCLK cycles between changing the
clock source and writing to AUXPLLMULT.

2.7.6.4

Clock Configuration Examples

Example 1: Using a crystal (15 MHz) as a reference, generate a CPU frequency of 100 MHz and a USB
clock of 60 MHz:
CLKSRCCTL1.OSCCLKSRCSEL = 0x1
SYSPLLMULT.IMULT = 26 (0x1A)
SYSPLLMULT.FMULT = .50 (0x2)
SYSCLKDIVSEL.PLLSYSCLKDIV = 4 (0x2)
SYSPLLCTL1.PLLCLKEN = 1
PERCLKDIVSEL.EPWMCLKDIV = 1 (0x0)
PERCLKDIVSEL.EMIF1CLKDIV = 1 (0x0)
PERCLKDIVSEL.EMIF2CLKDIV = 1 (0x0)
CLKSRCCTL2.AUXOSCCLKSRCSEL = 0x1
116

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

32-Bit CPU Timers 0/1/2

www.ti.com

AUXPLLMULT.IMULT = 8 (0x08)
AUXPLLMULT.FMULT = .00 (0x0)
AUXCLKDIVSEL.AUXPLLDIV = 2 (0x1)
AUXPLLCTL1.PLLCLKEN = 1
This gives a PLLRAWCLK of 397.5 MHz and an AUXPLLRAWCLK of 120 MHz, both of which are in the
acceptable range. The CPU frequency is 99.375 MHz. Crystals have tight frequency tolerances, which
should keep the system clock from exceeding 100 MHz. The USB frequency is exactly 60 MHz. Since the
CPU frequency is less than 100 MHz, the ePWM and EMIF clock dividers can be set to /1.
Example 2: Using INTOSC2 (10 MHz) as a reference, generate a CPU frequency of 200 MHz - 3%:
CLKSRCCTL1.OSCCLKSRCSEL = 0x0
SYSPLLMULT.IMULT = 38 (0x26)
SYSPLLMULT.FMULT = .75 (0x3)
SYSCLKDIVSEL.PLLSYSCLKDIV = 2 (0x1)
SYSPLLCTL1.PLLCLKEN = 1

2.8

32-Bit CPU Timers 0/1/2
This section describes the three 32-bit CPU-Timers (TIMER0/1/2) shown in Figure 2-10.
CPU-Timer0 and CPU-Timer1 can be used in user applications. CPU-Timer2 is reserved for real-time
operating system uses (for example, TI-RTOS). If the application is not using an operating system that
utilizes this timer, then CPU-Timer2 can be used in the application. CPU-Timer0 and CPU-Timer1 run off
of SYSCLK. CPU-Timer2 normally runs off of SYSCLK, but can also use INTOSC1, INTOSC2, XTAL, and
AUXPLLCLK. The CPU-Timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
Figure 2-11.
Figure 2-10. CPU-Timers

Reset
Timer reload
16-bit timer divide-down
TDDRH:TDDR

32-bit timer period
PRDH:PRD

16-bit prescale counter
PSCH:PSC

SYSCLKOUT
TCR.4
(Timer start status)

Borrow

32-bit counter
TIMH:TIM
Borrow

TINT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

117

32-Bit CPU Timers 0/1/2

www.ti.com

Figure 2-11. CPU-Timer Interrupts Signals and Output Signal

INT1
to
INT12

PIE

TINT0
TIMER0

28x
CPU
TINT1
TIMER1

INT13

TINT2
INT14

TIMER2

A

The timer registers are connected to the memory bus of the C28x processor.

B

The CPU Timers are synchronized to SYSCLKOUT.

The general operation of the CPU-Timer is as follows:
• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD
• The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles, where
TDDRH:TDDR is the timer divider.
• When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 2.15 are used to configure the timers.

118

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Watchdog Timers

www.ti.com

2.9

Watchdog Timers
The watchdog module generates an output pulse 512 watchdog clocks (WDCLKs) wide whenever the 8bit watchdog up counter has reached its maximum value. The watchdog clock source is INTOSC1.
Software must periodically write a 0x55 + 0xAA sequence into the watchdog key register to reset the
watchdog counter. The counter can also be disabled. Figure 2-12 shows the various functional blocks
within the watchdog module.
Figure 2-12. CPU Watchdog Timer Module
WDCR(WDPS(2:0))

WDCR(WDDIS)
WDCNTR(7:0)

WDCLK
(INTOSC1)

Watchdog
Prescaler

/512

SYSRSn

8-bit
Watchdog
Counter

Overflow

1-count
delay

Clear
Count

WDWCR(MIN(7:0))
WDKEY(7:0)

Watchdog
Key Detector
55 + AA

WDRSTn
WDINTn

Good Key

Out of Window

Watchdog
Window
Detector

Bad Key

Generate
512-WDCLK
Output Pulse

Watchdog Timeout

SCSR(WDENINT)

2.9.1 Servicing the Watchdog Timer
The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register
before the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is
written to the WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is
reset. Any value written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55
and 0xAA values can be written to the WDKEY without causing a system reset; only a write of 0x55
followed by a write of 0xAA to the WDKEY resets the WDCNTR.
Table 2-8. Example Watchdog Key Sequences
Step

Value Written to WDKEY

Result

1

0xAA

No action

2

0xAA

No action

3

0x55

WDCNTR is enabled to be reset if next value is 0xAA.

4

0x55

WDCNTR is enabled to be reset if next value is 0xAA.

5

0x55

WDCNTR is enabled to be reset if next value is 0xAA.

6

0xAA

WDCNTR is reset.

7

0xAA

No action

8

0x55

WDCNTR is enabled to be reset if next value is 0xAA.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control 119

Watchdog Timers

www.ti.com

Table 2-8. Example Watchdog Key Sequences (continued)
Step

Value Written to WDKEY

9

0xAA

WDCNTR is reset.

Result

10

0x55

WDCNTR is enabled to be reset if next value is 0xAA.

11

0x32

Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.

12

0xAA

No action due to previous invalid value.

13

0x55

WDCNTR is enabled to be reset if next value is 0xAA.

14

0xAA

WDCNTR is reset.

Step 3 in Table 2-8 is the first action that enables the WDCNTR to be reset. The WDCNTR is not actually
reset until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR. Step
10 again re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes no action, however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now
has no effect.
If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to
the WDCR[WDCHK] bits will reset the device and set the watchdog flag (WDRSn) in the reset cause
register (RESC). After a reset, the program can read the state of this flag to determine whether the reset
was caused by the watchdog. After doing this, the program should clear WDRSn to allow subsequent
watchdog resets to be detected. Watchdog resets are not prevented when the flag is set.

2.9.2 Minimum Window Check
To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that
bypass large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This
value will take effect after the next WDKEY sequence. From then on, any attempt to service the watchdog
when WDCNTR is less than WDWCR will trigger a watchdog interrupt or reset. When WDCNTR is greater
than or equal to WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.

2.9.3 Watchdog Reset or Watchdog Interrupt Mode
The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an
interrupt (WDINT) if the watchdog counter reaches its maximum value. The behavior of each condition is
described below:
• Reset mode:
If the watchdog is configured to reset the device, then the WDRST signal will pull the device reset
(XRS) pin low for 512 OSCCLK cycles when the watchdog counter reaches its maximum value.
Note: After a CPU1 watchdog reset, the boot ROMs will clear all of the system and message RAMs on
both CPUs. After a CPU2 watchdog reset, CPU2's boot ROM will clear all of the CPU2 system and
message RAMs.
• Interrupt mode:
When the watchdog counter expires, it will assert an interrupt by driving the WDINT signal low for 512
OSCCLK cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE if it is enabled.
Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active will not produce a
duplicate interrupt.
To avoid unexpected behavior, software should not change the configuration of the watchdog while
WDINT is active. For example, changing from interrupt mode to reset mode while WDINT is active will
immediately reset the device. Disabling the watchdog while WDINT is active will cause a duplicate
interrupt if the watchdog is later re-enabled. If a debug reset is issued while WDINT is active, the reset
cause register (RESC) will show a watchdog reset. The WDINTS bit in the SCSR register can be read
to determine the current state of WDINT.
120

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Watchdog Timers

www.ti.com

2.9.4 Watchdog Operation in Low Power Modes
In IDLE mode, the watchdog interrupt (WDINT) signal can generate an interrupt to the CPU to take the
CPU out of IDLE mode. As with any other peripheral, the watchdog interrupt will trigger a WAKEINT
interrupt in the PIE during IDLE mode. User software must determine which peripheral caused the
interrupt.
In STANDBY mode, all of the clocks to the peripherals are turned off within the CPU subsystem. The only
peripheral that remains functional is the watchdog since the watchdog module runs off the oscillator clock
(OSCCLK). The WDINT signal is fed to the Low Power Modes (LPM) block so that it can be used to wake
the CPU from STANDBY low power mode. This feature is enabled by setting LPMCR.WDINTE = 1. See
Section 2.10 for details.
Note: If the watchdog interrupt is used to wake-up from an IDLE or STANDBY low power mode condition,
software must make sure that the WDINT signal goes back high before attempting to reenter the IDLE or
STANDBY mode. The WDINT signal will be held low for 512 OSCCLK cycles when the watchdog interrupt
is generated. The current state of WDINT can be determined by reading the watchdog interrupt status bit
(WDINTS) bit in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.
In HALT mode, the internal oscillators and CPU1 watchdog are kept active if the user sets
CLKSRCCTL1.WDHALTI = 1. A watchdog reset can wake the system from HALT mode, but a watchdog
interrupt cannot.

2.9.5 Emulation Considerations
The watchdog module behaves as follows under various debug conditions:
CPU Suspended:
Run-Free Mode:
Real-Time Single-Step
Mode:
Real-Time Run-Free
Mode:

When the CPU is suspended, the watchdog clock (WDCLK) is suspended
When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
When the CPU is in real-time single-step mode, the watchdog clock
(WDCLK) is suspended. The watchdog remains suspended even within realtime interrupts.
When the CPU is in real-time run-free mode, the watchdog operates as
normal.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

121

Low Power Modes

www.ti.com

2.10 Low Power Modes
This device has three clock-gating, low-power modes and a special power-gating mode. All low-power
modes are entered by setting the LPMCR register and executing the IDLE instruction. More information
about this instruction can be found in the TMS320C28x CPU and Instruction Set Reference Guide
(SPRU430).
Low-power modes should not be entered into while a flash program or erase is ongoing.
The application should verify the following before entering STANDBY or HALT Mode:
1. Check the value of the GPIODAT register of the pin selected for STANDBY or HALT wake-up
(GPIOLPMSEL0/1) prior to entering the Low-Power mode to ensure that the wake event has not
already been asserted.
2. The LPMCR.QUALSTDBY register should be set to a value greater than the ratio of
INTOSC1/PLLSYSCLK to ensure proper wake up. This is applicable to STANDBY only.

2.10.1 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral
clocks are left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral
events. When one CPU is in IDLE, there is no effect on the other CPU subsystem.
Any enabled interrupt will wake the CPU up from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.

2.10.2 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU's SYSCLK. The watchdog however, is left active. Like IDLE, this mode affects only
one CPU subsystem. The other CPU subsystem and all of its peripherals are unaffected. STANDBY is
best suited for an application where the wake-up signal will come from an external system (or CPU
subsystem) rather than a peripheral input.
IPC interrupt 1 (flag 0), an NMI fired to the other CPU, or (optionally) a watchdog interrupt, will wake the
CPU subsystem up from STANDBY mode. Any of GPIO0-63 can also be configured to wake up the
subsystem when they are driven active low. Upon wakeup, the CPU receives a WAKEINT interrupt, even
if it was woken by an IPCINT1 signal.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from Standby mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; it must remain low for the number of OSCCLK cycles specified in
the QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count
restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt
is latched in the PIE block. The WAKEINT interrupt can also triggered by IPCINT1 sent from the other
CPU and a watchdog interrupt.
The CPU is now out of STANDBY mode and can resume normal execution.

122

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Low Power Modes

www.ti.com

If CPU2 is in STANDBY mode, writing a 1 to the RESET bit of the CPU2RESCTL register will have no
effect. CPU2 may be reset by any Chip-level reset (POR, XRSn, CPU1.WDRSn, or CPU1.NMIWDRSn) or
HIBRESETn. Alternately CPU2 may be woken up by any configured wake-up event.
If CPU2 is in STANDBY mode and the debugger is connected, executing a debug reset on CPU2 will
have no effect. In order to wake the CPU2 with the debugger, Click Run, Single Step, or Step over in the
Debug toolbar. CCS will prompt the user requesting to bring the CPU out of the low-power mode. Click
Yes. This will wake CPU2 from STANDBY and continue execution.

2.10.3 HALT
HALT is a global low-power mode that gates almost all system clocks and allows for power-down of
oscillators and analog blocks. This mode affects both CPU subsystems. HALT can be used for additional
power savings over putting both CPU subsystems in STANDBY, although the options for wakeup are
more limited.
Similar to STANDBY, any of GPIO0-63 can be configured to wake up the system from HALT. No other
wakeup option is available. However, CPU1's watchdog may still be clocked, and can be configured to
produce a watchdog reset if a timeout mechanism is needed. On wakeup, both CPUs receive a WAKEINT
interrupt.
To enter HALT mode:
1. Disable all interrupts with the exception of the WAKEINT interrupt on both CPUs. The other interrupts
can be reenabled after the device is brought out of HALT mode.
2. Put CPU2 into IDLE mode. (Using STANDBY will cause a duplicate WAKEINT on CPU2). CPU1
should verify this by checking the LPMSTAT register.
3. Set LPMCR.LPM to 0x2. Set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the
LPM module.
4. Set CLKSRCCTL1.WDHALTI to 1 to keep the CPU1 watchdog active and INTOSC1 and INTOSC2
powered up in HALT.
5. Set CLKSRCCTL1.WDHALTI to 0 to disable the CPU1 watchdog and power down INTOSC1 and
INTOSC2 in HALT.
6. Execute the IDLE instruction on CPU1 to enter HALT.
If an interrupt or NMI is received while the IDLE instruction is in the pipeline, the system will begin
executing the WAKEINT ISR. After HALT wakeup, ISR execution will resume where it left off.
NOTE: Before entering HALT mode, if the system PLL is locked (SYSPLL.LOCKS = 1), it must also be
connected to the system clock (PLLCTL1.PLLCLKEN = 1). Otherwise, the device will never wake up.
To wake up from HALT mode:
1. Drive the selected GPIO low for a minimum 5us. This will activate the CPU1.WAKEINT and
CPU2.WAKEINT PIE interrupts.
2. Drive the wake-up GPIO high again to initiate the powering up of the SYSPLL and AUXPLL
3. Wait 16us plus 1024 OSCLK cycles to allow the PLLs to lock and the WAKEINT ISR to be latched.
4. Execute the WAKEINT ISR.
The device is now out of HALT mode and can resume normal execution.

2.10.4 HIB
Hibernate (HIB) is a global low-power mode that gates the supply voltages to most of the system. This
mode affects both CPU subsystems. HIB is essentially a controlled power-down with remote wakeup
capability, and can be used to save power during long periods of inactivity. Because gating the supply
voltage corrupts the state of the logic, a reset is required to exit HIB. To prevent external systems from
being affected by the reset, HIB provides isolation of the I/O pin states as well as low-power data retention
via the M0 and M1 memories.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

123

Low Power Modes

www.ti.com

Unlike the clock-gating modes, HIB does not have a true wakeup. Instead, GPIO41 becomes HIBWAKE,
an asynchronous reset signal. When the boot ROM detects a HIB wakeup, it will avoid clearing M0 and
M1 and call a user-specified I/O restore function. To prevent glitches on internal and external signals, XRS
will also generate a HIBWAKE signal during HIB. The I/O restore function should set up the GPIO control
registers to match their pre-HIB state, then write a 1 to LPMCR.IOISODIS to deactivate I/O isolation. If the
restore function does not disable isolation, the boot ROM will do it.
To enter HIB mode:
1. Save any necessary state to the M0 and M1 memories of both CPUs.
2. Put all I/Os in the desired state for isolation and deactivate any analog modules in use.
3. Write the address of the I/O restore function for each CPU to its IORESTOREADDR register.
4. Put CPU2 in reset, IDLE, or STANDBY.
5. Bypass the PLL by setting PLLCLKEN to 0.
6. Set CPU1's LPMCR.LPM to 0x3 and execute the IDLE instruction.
Any debugger connection will be lost on HIB entry since the JTAG logic is powered down.
Due to the loss of system state on HIB entry, it is possible for error information to be lost if an NMI is
triggered while the IDLE instruction is in the pipeline. The ERRORSTS pin will be set and remain set until
I/O isolation is disabled, but there will be no way to tell what caused the error.
To wake the device from HIB mode:
1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the power-up of the device clock
sources.
2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the rest of the device.
3. Boot ROM code will execute on HIB wake-up. Boot ROM will read CPU1.RESC.HIBRESTn bit to
determine this is a wakeup from HIB.
4. Boot ROM calls the I/O context restore routine. This I/O restore function should reconfigure the I/O
configuration and do any other necessary application setup.
Since waking up from HIB mode is a type of reset, the device will enter the main function. The device is
now out of HIB mode and can normal execution.
NOTE: The bootROM uses locations 0x02-0x122 on CPU1’s M0 RAM and locations 0x02-0x80 on
CPU2’s M0 RAM. To prevent losing any data during HIB wake-up, avoid saving any critical
data to these locations.

NOTE:

124

The application must bypass the PLL before executing the IDLE instruction to enter HIB. If
the PLL is not bypassed when entering HIB, there will be a brief current spike on the Vdd
supply that may cause the device to reset.

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Memory Controller Module

www.ti.com

2.11 Memory Controller Module
For these devices, the RAMs have different characteristics. Some are:
• dedicated to each CPU (M0, M1, and Dx RAMs),
• shared between the CPU and its own CLA (LSx RAM),
• shared between the CPU and DMA of both subsystems (GSx RAM), and
• used to send and receive messages between processors (MSGRAM).
All these RAMs are highly configurable to achieve control for write access and fetch access from different
masters. There are also RAMs - called IPC MSGRAMs - that are used for interprocessor communication.
All dedicated RAMs are enabled with the ECC feature (both data and address) and shared RAMs, as well
as IPC MSGRAMs, are enabled with the PARITY (both data and address) feature. Some of the dedicated
memories are secure memory as well. Refer to Section 2.13 for more details. Each RAM has its own
controller which takes care of the access protection/security related checks and ECC/Parity features for
that RAM. Figure 2-13 shows the configuration of these RAMs.
Figure 2-13. Memory Architecture
CPU1.LSx RAM

CPU1.CLA1

CPU2.LSx RAM

GSx RAM

CPU1 TO
CPU1.CLA1
MSGRAM

CPU2 TO
CPU2.CLA1
MSGRAM

CPU1.CLA1 TO
CPU1 MSGRAM

CPU2.CLA1

CPU2.CLA1 TO
CPU2 MSGRAM
CPU1.DMA

CPU2.DMA

CPU1

CPU2

CPU1.M0 RAM

CPU2.M0 RAM

CPU2 TO CPU1
MSGRAM
CPU1.M1 RAM

CPU2.M1 RAM

CPU1 TO CPU2
MSGRAM

CPU1.Dx RAM

CPU2.Dx RAM

NOTE: All RAMs on these devices are SRAMs.

2.11.1 Functional Description
This section further defines and discusses the dedicated RAMs, shared RAMs, and MSG RAMs on this
device.
2.11.1.1 Dedicated RAM (Dx RAM)
Each CPU subsystem has four dedicated RAM blocks: M0, M1, D0, and D1. M0/M1 memories are small
blocks of memory which are tightly coupled with the CPU. Only the CPU has access to these memories.
No other masters (including DMA) have any access to these memories.
All dedicated RAMs have the ECC feature. All dedicated memories (except for M0/M1) are secure
memory and also have the access protection (CPU write protection/CPU fetch protection) feature. Each
type of access protection for each RAM block can be enabled/disabled by configuring the specific bit in the
access protection register, allocated to each subsystem (DxACCPROT).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

125

Memory Controller Module

www.ti.com

2.11.1.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are
called local shared RAMs (LSx RAMs). All such memories are secure memory and have the parity feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these
memories with the CLA by appropriately configuring the MSEL_LSx bit field in the LSxMSEL register.
Further, when these memories are shared between the CPU and CLA, the user could choose to use these
memories as CLA program memory by configuring the CLAPGM_LSx bit field in the LSxCLAPGM
registers. CPU access to all memory blocks, which are programmed as CLA program memory, are
blocked.
All these RAMs have the access protection (CPU write/CPU fetch) feature. Each type of access protection
for each RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM
access protection registers, mapped to each CPU subsystem. Table 2-9 shows the LSx RAM features.
Table 2-9. Local Shared RAM
MSEL_LSx

CLAPGM_LSx

CPUx Allowed
Access

CPUx.CLA1 Allowed
Access

Comment

00

X

All

-

LSx memory is configured as CPU
dedicated RAM

01

0

All

Data Read
Data Write

LSx memory is shared between
CPU and CLA1

01

1

Emulation Read
Emulation Write

Fetch Only

LSx memory is CLA1 program
memory

2.11.1.3 Global Shared RAM (GSx RAM)
RAM blocks which are accessible from both the CPU and their respective DMA are called global shared
RAMs (GSx RAMs). Each shared RAM can be owned by either CPU subsystem based on the
configuration of their respective bits (one bit for each GSx memory) in the GSxMSEL register. When a
particular GSx RAM block is owned by the CPU1 subsystem, CPU1 and CPU1.DMA have full access to
that RAM block, whereas CPU2 and CPU2.DMA have only read access to it (no fetch/write access).
Similarly, when a particular GSx RAM block is owned by the CPU2 subsystem, CPU1 and CPU1.DMA will
have only read access (no fetch/write access) to that RAM block, whereas CPU2 and CPU2.DMA will
have full access to it. Table 2-10 shows the features of the GSx RAM.
Table 2-10. Global Shared RAM
GSxMSEL

CPU1

CPU1

CPU1

Fetch

Read

Write

CPU1.DMA CPU1.DMA
Read

Write

CPU2

CPU2

CPU2

Fetch

Read

Write

0

Yes

Yes

Yes

Yes

1

No

Yes

No

Yes

CPU2.DMA CPU2.DMA
Read

Yes

No

Yes

No

Yes

No

No

Yes

Yes

Yes

Yes

Yes

Write

Like other shared RAM, these RAMs also have a different levels of access protection which can be
enabled or disabled by configuring specific bits in the GSxACCPROT registersmapped in each subsystem.
Master select and access protection configuration for each GSx RAM block can be individually locked by
the user to prevent further update to these bit fields. The user can also choose to permanently lock the
configuration to individual bit fields by setting the specific bit fields in the GSxCOMMIT register (refer to
the register description for more details). Once configuration is committed for a particular GSx RAM block,
it can not be changed further until CPUx.SYSRS is issued. Only the CPU1 SW can change the master
select configuration by writing into the GSxMSEL register, mapped on the CPU1. The GSxMSEL register,
which is mapped to the CPU2 subsystem, is a status register which can only be used by CPU2 SW to
know the master ownership for each GSx RAM block.

126

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Memory Controller Module

www.ti.com

2.11.1.4 CPU Message RAM (CPU MSG RAM)
These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for
interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU/DMA
read/write access from its own CPU subsystem, and CPU/DMA read only access from the other
subsystem.
This RAM has parity.
2.11.1.5 CLA Message RAM (CLA MSGRAM)
These RAM blocks are be used to share data between the CPU and CLA. The CLA has read and write
access to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA
MSGRAM." The CPU and CLA both have read access to both MSGRAMs.
This RAM has parity.
2.11.1.6 Access Arbitration
For a shared RAM, multiple accesses can happen at a given time. The maximum number of accesses to
any shared RAM at any given time depends on the type of shared RAM. On this device, a combination of
a fixed and round robin scheme is followed to arbitrate multiple access at any given time. Accesses from
the same masters are arbitrated in a fixed priority manner, but the accesses from different masters are
arbitrated using the round robin scheme.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch
Figure 2-14 represents the arbitration scheme on global shared memories:
Figure 2-14. Arbitration Scheme on Global Shared Memories
Round Robin Arbitration
CPU1-DWRITE
CPU1-DREAD
CPU1-PREAD/FETCH

CPU1
Fixed
Priority
Arbiter

Granted CPU1 Access

RR-CPU1

CPU1.DMA READ/WRITE

RR-CPU2.DMA
CPU2-DWRITE
CPU2-DREAD
CPU2-PREAD/FETCH

CPU2
Fixed
Priority
Arbiter

RR-CPU1.DMA

Granted CPU2 Access

RR-CPU2
CPU2.DMA READ/WRITE

Figure 2-15 represents the arbitration scheme on local shared memories.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

127

Memory Controller Module

www.ti.com

Figure 2-15. Arbitration Scheme on Local Shared Memories

CPU-DWRITE
CPU-DREAD
CPU-PREAD/FETCH

CLA-DWRITE
CLA-DREAD

Round Robin Arbitration
CPU
Fixed
Priority
Arbiter

Granted CPU1 Access

CLA
Fixed
Priority
Arbiter

Granted CLA Access

RR-CPU

RR-CPU.CLA

2.11.1.7 Access Protection
All RAM blocks except for M0/M1 on both subsystems have different levels of protection. This feature
allows the user to enable or disable specific access to individual RAM blocks from individual masters.
There is no protection for read accesses, hence reads are always allowed from all the masters which have
access to that RAM block.
The following sections describe the different kinds of protection available for RAM blocks on this device.
Note: For debug accesses, all the protections are disabled.
2.11.1.7.1 CPU Fetch Protection
A CPU has execution permission from a memory, only if that memory is dedicated to that CPU or its
respective subsystem is master for that memory (in case of GSx memory). When fetch accesses are
allowed based on the mastership, it can be further protected by setting the FETCHPROTx bit of the
specific register to ‘1.’ If fetch access is done by the CPU to a memory where CPU fetch protection is
enabled, a fetch protection violation occurs.
There are two types of fetch protection violations:
• Non-master CPU fetch protection violation
• Master CPU fetch protection violation
If a fetch access is made to a memory by a non-master CPU, it is called a non-master fetch protection
violation. If a fetch access is made to a dedicated or shared memory by the master CPU, and
FETCHPROTx is set to ‘1’ for that memory, the violation is called a master CPU fetch protection violation.
If a fetch protection violation occurs, it results in an ITRAP for CPU. A flag gets set into the appropriate
access violation flag register, and the memory address for which the access violation occurred, get
latched into the appropriate CPU fetch access violation address register.
2.11.1.7.2 CPU Write Protection
A CPU has write permission to a memory only if that memory is dedicated to that CPU, or if its respective
subsystem is the master for that memory (in case of GSx memory). When write accesses are allowed
based on the mastership, it can be further protected by setting the CPUWRPROTx bit of the specific
register to ‘1.’ If write access is done by a CPU to memory where it is protected, a write protection
violation occurs.
There are two types of CPU write protection violations:
• Non-master CPU write protection violation
• Master CPU write protection violation
If a write access is made to a dedicated or shared memory by the master CPU and CPUWRPROTx is
set to ‘1’ for that memory, it’s called a master CPU write protection violation.
128

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Memory Controller Module

www.ti.com

If a write protection violation occurs, write gets ignored, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CPU write access violation address register. Also, an access violation interrupt is
generated if enabled in the interrupt enable register.
2.11.1.7.3 CPU Read Protection
For local shared RAM, if memory is shared between the CPU and its CLA, the CPU will only have access
if the memory is configured as data RAM for the CLA. If it is programmed as program RAM, all the access
from the CPU, including a read, will be blocked and the violation will be considered as a non-master
access violation.
If a read protection violation occurs, a flag gets set into the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched into the appropriate CPU read
access violation address register. Also, an access violation interrupt is generated, if enabled in the
interrupt enable register.
2.11.1.7.4 CLA Fetch Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as data RAM for the
CLA, any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation,
which is a non-master access violation.
If a CLA fetch protection violation occurs, it results in a MSTOP, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CLA fetch access violation address register. Also, an access violation interrupt is
generated to the master CPU if enabled in the interrupt enable register.
2.11.1.7.5 CLA Write Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for
the CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection
violation, which is a non-master access violation.
If a CLA write protection violation occurs, write gets ignored, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CLA write access violation address register. Also, an access violation interrupt is
generated to the master CPU if enabled in the interrupt enable register.
2.11.1.7.6 CLA Read Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for
the CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection
violation, which is a non-master access violation.
If a CLA read protection violation occurs, a flag gets set into the appropriate access violation flag register,
and the memory address for which the access violation occurred, gets latched into the appropriate CLA
read access violation address register. Also, an access violation interrupt is generated to the master CPU
if enabled in the interrupt enable register.
2.11.1.7.7 DMA Write Protection
The CPU1 or CPU2 DMA has write permission to a GSx memory only if its respective subsystem is
master for that memory. When write accesses from a DMA are allowed based on the mastership, it can be
further protected by setting the DMAWRPROTx bit of a specific register to ‘1.’ If write access is done by
the DMA to protected memory, a write protection violation occurs.
There are two types of DMA write protection violations:
• Non-master DMA write protection violation (only applicable to Sx memories)
• Master DMA write protection violation

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

129

Memory Controller Module

www.ti.com

If a write access is made to GSx memory by a non-master DMA, it is called a non-master write protection
violation. If a write access is made to a dedicated or shared memory by a master DMA, and
DMAWRPROTx is set to ‘1’ for that memory, it is called a master DMA write protection violation.
If a write protection violation occurs on CPU1, write is ignored and a DMAERR interrupt gets generated,
whereas in the case of CPU2, a write is ignored and an access violation interrupt is generated if enabled
in the interrupt enable register. A flag gets set in the DMA access violation flag register, and the memory
address where the violation happened gets latched in the DMA fetch access violation address register.
These are dedicated registers for each subsystem.
Note 1:

Note 2:
Note 3:

All access protections are ignored during debug accesses. Write access to a protected
memory will go through when it is done via the debugger, irrespective of the write protection
configuration for that memory.
Access protection is not implemented for M0 and M1 memories.
In the case of local shared RAM, if memory is shared between the CPU and its CLA, the
CPU will only have access if the memory is configured as data RAM for the CLA. If it is
programmed as program RAM, all the access from the CPU (including read) and data access
from the CLA will be blocked, and violation will be considered as a non-master access
violation. If the memory is configured as dedicated to the CPU, all access from the CLA will
be blocked and the violation will be considered a non-master access violation.

2.11.1.8 Memory Error Detection, Correction and Error Handling
These devices have memory error detection and correction features to satisfy safety standards
requirements. These requirements warrant the addition of detection mechanisms for finite dangerous
failures.
In this device, all dedicated RAMs support error correction code (ECC) protection and the shared RAMs
have parity protection. The ECC scheme used is Single Error Correction Double Error Detection
(SECDED). The parity scheme used is even parity. ECC/Parity will cover the data bits stored in memory
as well as address.
ECC/Parity calculation is done inside the memory controller module and then calculated. ECC/Parity is
written into the memory along with the data. ECC/Parity is computed for 16-bit data; hence, for each 32-bit
data, there will be three 7-bit ECC codes (or 3-bit parity), two of which are for data and a third one for the
address.
2.11.1.8.1 Error Detection and Correction
Error detection is done while reading the data from memory. The error detection is performed for data as
well as address. For parity memory, only a single-bit error gets detected, whereas in case of ECC
memory, along with a single-bit error, a double-bit error also gets detected. These errors are called
correctable error and uncorrectable errors. The following are characteristics of these errors:
• Parity errors are always uncorrectable errors
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors
• Address ECC errors are also uncorrectable errors
Correctable errors get corrected by the memory controller module and then correct data is given back as
read data to the master. It is also written back into the memory to prevent double-bit error due to another
single-bit error at the same memory address.

130

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Memory Controller Module

www.ti.com

2.11.1.8.2 Error Handling
For each correctable error, the count in the correctable error count register will increment by one. When
the value in this count register becomes equal to the value configured into the correctable error threshold
register, an interrupt is generated to the respective CPU, that is, if the interrupt is enabled in the
correctable interrupt enable register. The user needs to configure the correctable error threshold register
based on the system requirements. Also, the address for which the error occurred, gets latched into the
master-specific status register and a flag gets set. Each of these registers are dedicated for each CPU
subsystem.
If there are uncorrectable errors, an NMI gets generated for the respective CPU. In this case, the address
for which the error occurred, also gets latched into the master-specific address status register, and a flag
gets set.
Table 2-11 summarizes different error situations that can arise. These need to be handled appropriately in
the software, using the status and interrupt indications provided.
Table 2-11. Error Handling in Different Scenarios
Access
Type

Error Found In

Error Type

Reads

Data read from
memory

Uncorrectable
Error
(Single-bit error
for Parity RAMs
OR
Double bit Error
for ECC RAMs)

Reads

Data read from
memory

Reads

Address

Status Indication
Yes -CPUx/CPUx.DMA/CPUx.CLA1
CPU/DMA/CLA Read Error Address
Register Data returned to
CPUx/CPUx.DMA/CPUx.CLA1 is
incorrect

Single-bit error for Yes - CPUx/CPUx.DMA CPU/DMA
ECC RAMs
Read Error Address Register
Increment single error counter
Address error

Yes - CPUx/CPUx.DMA/CPUx.CLA1
CPU/DMA/CLA Read Address Error
Register Data returned to
CPUx/CPUx.DMA/CPUx.CLA1 is
incorrect

Error Notification
NMI for CPUx access
NMI for CPUx.DMA access
NMI to CPU for CPUx.CLA1 access

Interrupt when error counter reaches
the user programmable threshold for
single errors
NMI to CPU for CPUx access
NMI to CPU for CPUx.DMA access
NMI to CPU for CPUx.CLA1 access

NOTE: In the case of an uncorrectable error during fetch on the CPU, there is the possibility of
getting an ITRAP before an NMI exception, since garbage instructions enter into the CPU
pipeline before the NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.

2.11.1.9 Application Test Hooks for Error Detection and Correction
Since error detection and correction logic is part of safety critical logic, safety applications may need to
ensure that the logic is always working fine (during run time also). To enable this, a test mode is provided,
in which a user can modify the data bits (without modifying the ECC/Parity bits) or ECC/Parity bits directly.
Using this feature, an ECC/Parity error could be injected into data.
NOTE:

The memory map for ECC/Parity bits and data bits are the same. The user must choose a
different test mode to access ECC/Parity bits.

The following table shows the bit mapping for the ECC/Parity bits when they are read in RAMTEST mode
using their respective addresses.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control 131

Memory Controller Module

www.ti.com

Table 2-12. Mapping of ECC Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data
6:0

Content (ECC Memory)
ECC Code for lower 16 bits of data

7

Not Used

14:8

ECC Code for upper 16 bits of data

15

Not Used

22:16

ECC Code for address

31:23

Not Used

Table 2-13. Mapping of Parity Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data
0
7:1
8
15:9
16
31:17

Content (Parity Memory)
Parity for lower 16 bits of data
Not Used
Parity for upper 16 bits of data
Not Used
Parity for address
Not Used

2.11.1.10 RAM Initialization
To ensure that read/fetch from uninitialized RAM locations do not cause ECC or parity errors, the
RAM_INIT feature is provided for each memory block. Using this feature, any RAM block can be initialized
with 0x0 data and respective ECC/Parity bits accordingly. This can be initiated by setting the INIT bit to ‘1’
for the specific RAM block in INIT registers. To check the status of RAM initialization, SW should poll for
the INITDONE bit for that RAM block in the INITDONE register to be set. Unless this bit gets set, no
access should be made to that RAM memory block.
In the case of GSx memory, only the CPU of the subsystem that is configured as the master for the
particular GSx RAM block can initiate the RAM initialization.
NOTE:

132

None of the masters should access the memory while initialization is taking place. If memory
is accessed before RAMINITDONE is set, the memory read/write as well as initialization will
not happen correctly.

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Flash and OTP Memory

www.ti.com

2.12 Flash and OTP Memory
Flash is an electrically erasable/programmable nonvolatile memory that can be programmed and erased
many times to ease code development. Flash memory can be used primarily as a program memory for the
core, and secondarily as static data memory.
This section describes the proper sequence to configure the wait states and operating mode of flash. It
also includes information on flash and OTP power modes, how to improve flash performance by enabling
the flash prefetch/cache mode, and the SECDED safety feature.

2.12.1 Features
Features of flash memory include:
• Dedicated flash bank in the CPU1 subsystem (refer to the device data manual for the size of flash
bank)
• Dedicated flash bank in the CPU2 subsystem (refer to the device data manual for the size of flash
bank)
• Dedicated flash module controller (FMC) in the CPU1 and CPU2 subsystems for each bank
• 128 bits (bank width) can be programmed at a time along with ECC
• Multiple sectors providing the option of leaving some sectors programmed and only erasing specific
sectors
• User-programmable OTP locations for configuring security, OTP boot-mode and boot-mode select pins
(if the user is unable to use the factory-default boot-mode select pins)
• Single-flash pump shared by the CPU1 and CPU2 subsystems
• Hardware flash pump semaphore to control ownership of the pump between the two FMCs.
• Enhanced performance using the code-prefetch mechanism and data cache in CPU1-FMC and CPU2FMC
• Configurable wait states to give the best performance for a given execution speed
• Safety Features
– SECDED-single error correction and double error detection is supported in both FMCs
– Address bits are included in ECC
– Test mode to check the health of ECC logic
• Supports low-power modes for flash bank and pump for power savings
• Built-in power mode control logic
• Integrated flash program/erase state machine (FSM) in both FMCs
– Simple flash API algorithms
– Fast erase and program times (refer to the device data manual for details)
• Code Security Module (CSM) to prevent access to the flash by unauthorized persons (refer to
Section 2.13 for details)

2.12.2 Flash Tools
Texas Instruments provides the following tools for flash:
• Code Composer Studio (CCS) - the development environment with integrated flash plugin
• F021 Flash API Library - a set of software peripheral functions to erase/program flash
• UniFlash - standalone tool to erase/program/verify the flash content through JTAG. No CCS is
required.
• CCS On-Chip Flash Plugin and UniFlash tools developed for these devices support
AutoEccGeneration (see TMS320F2837xD Flash API Version 1.54 Reference Guide , SPNU629). But
they do not support the program of ECC generated by the linker -ecc options.
• Users must check and install available updates for CCS On-Chip Flash Plugin and UniFlash tools.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

133

Flash and OTP Memory

www.ti.com

2.12.3 Default Flash Configuration
The following are flash module configuration settings at power-up in both CPU1 and CPU2 subsystems:
• Dedicated flash banks are in sleep power mode
• Shared pump is in sleep mode
• ECC is enabled
• Wait-states are set to the maximum (0xF)
• Code-prefetch mechanism and data cache are disabled in both FMCs
During the boot process, the boot ROM performs a dummy read of the Code Security Module (CSM)
password locations in the OTP. This read is performed to unlock a new (or erased) device that has no
password stored in it, so that flash programming or loading of code into CSM-protected SARAM can be
performed. On devices with a password, this read has no effect and the device remains locked. One effect
of this read is that the flash will transition from the sleep (reset) state to the active state.
User application software must initialize wait-states using the FRDCNTL register, and configure
cache/prefetch features using the RD_INTF_CTRL register, to achieve optimum system performance.
Software that configures flash settings like wait-states, cache/prefetch features, and so on, must be
executed only from RAM memory, not from flash memory.
NOTE: Before initializing wait-states, turn off the pre-fetch and data caching in the FRD_INTF_CTRL
register.

2.12.4 Flash Bank, OTP and Pump
There is a dedicated flash bank in the CPU1 subsystem called the CPU1 flash bank and a dedicated flash
bank in the CPU2 subsystem called the CPU2 flash bank. Also, there is a one-time programmable (OTP)
memory on the CPU1 subsystem called USER OTP, which the user can program only once and cannot
erase. Flash and OTP are uniformly mapped in both program and data memory space.
Both the CPU1 subsystem and CPU2 subsystem have a TI-OTP which contains manufacturing
information like settings used by the flash state machine for erase and program operations, and so on.
Users may read TI-OTP but it cannot be programmed or erased. For memory map and size information of
the CPU1-Bank, CPU1 TI-OTP, CPU1 USER OTP, CPU2 flash bank, CPU2 TI-OTP, CPU2 USER-OTP
and corresponding ECC locations, please refer to the device data manual.
The CPU1 flash bank/USER OTP and CPU2 flash bank/USER OTP share a common flash pump. A
hardware semaphore, called the flash pump semaphore, is provided to control the access of the flash
pump between the CPU1 subsystem and CPU2 subsystem.
Figure 2-22 depicts the user-programmable OTP locations in CPU1 USER-OTP and CPU2 USER-OTP.
For more information on the functionality of these fields, please refer to Section 2.13 and the ROM Code
and Peripheral Booting chapter.

2.12.5 Flash Module Controller (FMC)
There is a dedicated flash module controller in both the CPU1 subsystem (CPU1-FMC) and the CPU2
subsystem (CPU2-FMC). The CPU1 in the CPU1 subsystem interfaces with the CPU1 flash module
controller (CPU1-FMC), which in turn, interfaces with the CPU1 flash bank and shared pump to perform
erase/program operations as well as to read data/execute code from the CPU1 flash bank.

134

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Flash and OTP Memory

www.ti.com

Figure 2-16. FMC Interface with Core, Bank and Pump

CPU2-Bank

CPU2 System Clock

CPU2 Core

CPU2-FMC

Pump
CPU1-FMC
CPU1 Core

Pump Semaphore
CPU1 System Clock

CPU1-Bank

The CPU2 in the CPU2 subsystem interfaces with the CPU2 flash module controller (CPU2-FMC) which in
turn, interfaces with the CPU2 flash bank and shared pump to perform erase/program operations as well
as to read data/execute code from the CPU2 flash bank. Control signals to the flash pump will be
controlled by either CPU2-FMC or CPU1-FMC, depending on who gains the flash pump semaphore.
There is a state machine in both CPU1-FMC and CPU2-FMC which generates the erase/program
sequences in hardware. This simplifies the Flash API software which configures control registers in the
FMC to perform flash erase and program operations (see TMS320F2837xD Flash API Version 1.54
Reference Guide , SPNU629, for details on Flash API).
Section 2.12.6 through Section 2.12.10 describe FMC in detail.

2.12.6 Flash and OTP Power-Down Modes and Wakeup
The flash bank and pump consume a significant amount of power when active. The flash module provides
a mechanism to power-down flash banks and pump. Special timers automatically sequence the power-up
of the CPU1 flash bank and CPU2 flash bank independently of each other. The shared charge pump
module has its own independent power-up timer as well.
The flash bank and OTP operate in three power modes: Sleep (lowest power), Standby, and Active
(highest power)
• Sleep State
This is the state after a device reset. In this state, a CPU data read or opcode fetch will automatically
initiate a change in power mode to the standby state and then to the active state. During this transition
time to the active state, the CPU will automatically be stalled.
• Standby State
This state uses more power than the sleep state, but takes a shorter time to transition to the active or
read state. In this state, a CPU data read or opcode fetch will automatically initiate a change in power
mode to the active state. During this transition time to the active state, the CPU will automatically be
stalled. Once the flash/OTP has reached the active state, the CPU access will complete as normal.
• Active or Read State
In this state, the bank and pump are in active power mode state (highest power)
The charge pump operates in two power modes:
• Sleep (lowest power)
• Active (highest power)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

135

Flash and OTP Memory

www.ti.com

Any access to any flash bank/OTP causes the charge pump to go into active mode, if it is in sleep mode.
An erase or program command causes the charge pump and bank to become active. If any bank is in
active or in standby mode, the charge pump will be in active mode, independent of the pump power mode
control configuration (PMPPWR bit field in the FPAC1 register).
To power down the Flash pump, both the CPU1 and CPU2 must each power down the Flash Pump
without any Flash accesses in between. The Flash Pump will not enter low-power mode if the below
sequence is not followed.
1. When the system is ready to power down the Flash completely, synchronize CPU1 and CPU2. CPU2
will enter its Flash power-down phase (steps 2, 3, 4, and 5) while the CPU1 will be waiting for it to
complete.
2. Acquire the Pump Semaphore with the CPU2.
3. Assign a value of 0x14 to CPU2 VREADST (refer to the FBAC register) to ensure the requisite delay
needed for the flash pump/bank to come out of low-power mode later: FBAC.VREADST = 0x14
4. Change the CPU2 Flash Bank Fall Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
5. Change the CPU2 Flash Charge Pump Fall Back power mode to Sleep: FPAC1.PMPPWR = 0. CPU2
should notify CPU1 that it has completed the above sequence. It should wait until CPU1 completes
steps 6, 7, 8, 9 and 10.
6. Acquire the Pump Semaphore with the CPU1.
7. Assign a value of 0x14 to CPU1 VREADST (refer to FBAC register) to ensure the requisite delay
needed for the flash pump/bank to come out of low-power mode later: FBAC.VREADST = 0x14
8. Change the CPU1 Flash Bank Fall Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
9. Change the CPU1 Flash Charge Pump Fall Back power mode to Sleep: FPAC1.PMPPWR = 0.
10. Release the Pump Semaphore from the CPU1. CPU1 should notify CPU2 that it has completed the
power-down sequence so that both subsystems may continue.
The above listed procedure should be executed from RAM and not from Flash. Note that exclusive control
of the Flash pump should be gained by a CPU (using Flash pump semaphore PUMPREQUEST) before
configuring the PMPPWR bit field of the FPAC1 register as shown in the above sequence. As the charge
pump is shared between CPU1-FMC and CPU2-FMC, the effective PMPPWR value used when powering
down the pump will be of the FMC (out of CPU1-FMC and CPU2-FMC) which owns the pump. The
application software can check the current power mode of the flash bank by reading the FBPRDY register.
The PUMPRDY bit in the FBPRDY register in CPU1-FMC and CPU2-FMC together reflect the power
mode of the charge pump. A value of 0 in the PUMPRDY bit in both CPU1-FMC and CPU2-FMC indicates
that the charge pump is in sleep mode. A value of 1 in the PUMPRDY bit in either CPU1-FMC or CPU2FMC or in both CPU1-FMC and CPU2-FMC indicates that the charge pump is in active mode. Refer to the
register descriptions, Section 2.15, for detailed information.
While the pump is in sleep state, a charge pump sleep down counter holds a user configurable value
(PSLEEP bit field in the FPAC1 register) and when the charge pump exits sleep power mode, the down
counter delays from 0 to PSLEEP prescaled SYSCLK clock cycles (prescaled clock is SYSCLK/2) before
putting the charge pump into active power mode. Note that the configured PSLEEP value should yield at
least a delay of 20us for the pump to go to active mode. Refer to the register descriptions, Section 2.15,
for detailed information.
Below are the number of cycles it will take for the Bank and pump to wake up from low power modes.
1. Pump sleep to active = PSLEEP * (SYSCLK/2) cycles
2. Bank sleep to standby = 425 Flash clock cycles
3. Bank standby to active = 90 Flash clock cycles
Where in Flash clock = SYSCLK/(RWAIT+1)

136

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Flash and OTP Memory

www.ti.com

2.12.7 Flash and OTP Performance
Once the flash bank and pump are in the active power state, a read or fetch access can be classified as a
flash access (access to an address location in flash) or an OTP access (access to an address location in
OTP). Once the CPU throws an access to a flash memory address, data is returned after RWAIT+1
number of SYSCLK cycles. For a USER-OTP access, data is returned after 11 SYSCLK cycles.
RWAIT defines the number of random access wait-states and is configurable using the RWAIT bit-field in
the FRDCNTL register. At reset, the RWAIT bit-field defaults to a worst-case wait-state count (15), and
therefore needs to be initialized for the appropriate number of wait states to improve performance, based
on the CPU clock rate and the access time of the flash. The flash supports 0-wait accesses when the
RWAIT bits are set to zero. This assumes that the CPU speed is low enough to accommodate the access
time.
For a given system clock frequency, RWAIT has to be configured using below formula:
RWAIT = ceiling[(SYSCLK/FCLK)-1]

where SYSCLK is the system operating frequency
FCLK is flash clock frequency. FCLK should be ≤ FCLKmax, allowed maximum flash clock frequency at
RWAIT=0.
If RWAIT results in a fractional value when calculated using the above formula, RWAIT has to be rounded
up to the nearest integer.

2.12.8 Flash Read Interface
This section provides details about the data read modes to access flash bank/OTP and the configuration
registers which control the read interface. In addition to a standard read mode, the FMC has a built-in
prefetch and cache mechanism to allow increased clock speeds and CPU throughput wherever applicable.
2.12.8.1 FMC Flash Read Interface
2.12.8.1.1 Standard Read Mode
Standard read mode is defined as the read mode in effect when code prefetch-mechanism and data
cache are disabled. It is also the default read mode after reset. During this mode, each read access to
flash is decoded by the flash wrapper to fetch the data from the addressed location and the data is
returned after the RWAIT+1 number of cycles.
Prefetch buffers associated with prefetch mechanism and data cache are bypassed in standard read
mode; therefore, every access to the flash/OTP is used by the CPU immediately, and every access
creates a unique flash bank access.
Standard read mode is the recommended mode for lower system frequency operation in which RWAIT
can be set to zero to provide single-cycle access operation. The FMC can operate at higher frequencies
using standard read mode at the expense of adding wait states. At higher system frequencies, it is
recommended to enable cache and prefetch mechanisms to improve performance. Refer to the device
specific data manual to determine the maximum flash frequency allowed in standard read mode (that is,
maximum flash clock frequency with RWAIT=0, FCLKMAX).
2.12.8.1.2 Prefetch Mode
Flash memory is typically used to store application code. During code execution, instructions are fetched
from sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code
that resides in sequential addresses makes up the majority of the application code and is referred to as
linear code. To improve the performance of linear code execution, a flash prefetch-mechanism has been
implemented in the FMC. Figure 2-17 illustrates how this mode functions.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

137

Flash and OTP Memory

www.ti.com

Figure 2-17. Flash Prefetch Mode
Flash and OTP
16-bit

Flash prefetch

Instruction buffer

Flash or OTP Read (128-bit)
128-bit 128-bit
buffer buffer
Instruction fetch

CPU

128-bit
Data cache

M
32-bit U
X

Data read from data memory

This prefetch mechanism does a look-ahead prefetch on linear address increments starting from the
address of the last instruction fetch. The flash prefetch mechanism is disabled by default. Setting the
PREFETCH_EN bit in the FRD_INTF_CTRL register enables this prefetch mode.
An instruction fetch from the flash or OTP reads out 128 bits per access. The starting address of the
access from flash is automatically aligned to a 128-bit boundary, such that the instruction location is within
the 128 bits to be fetched. With the flash prefetch mode enabled, the 128 bits read from the instruction
fetch are stored in a 128-bit wide by 2-level deep instruction prefetch buffer. The contents of this prefetch
buffer are then sent to the CPU for processing as required.
Up to four 32-bit or eight 16-bit instructions can reside within a single 128-bit access. The majority of C28x
instructions are 16 bits, so for every 128-bit instruction fetch from the flash bank, it is likely that there are
up to eight instructions in the prefetch buffer ready to process through the CPU. During the time it takes to
process these instructions, the flash prefetch mechanism automatically initiates another access to the
flash bank to prefetch the next 128 bits. In this manner, the flash prefetch mechanism works in the
background to keep the instruction prefetch buffers as full as possible. Using this technique, the overall
efficiency of sequential code execution from flash or OTP is improved significantly. If the prefetch
mechanism is enabled, then the last row of 128 bits in the bank should not be used, because the prefetch
logic which does a look-ahead prefetch, will try to fetch from outside the bank and would result in an ECC
error.
The flash prefetch is aborted only on a PC discontinuity caused by executing an instruction such as a
branch, BANZ, call, or loop. When this occurs, the prefetch mechanism is aborted and the contents of the
prefetch buffer are flushed. There are two possible scenarios when this occurs:
1. If the destination address is within the flash or OTP, the prefetch aborts and then resumes at the
destination address.
2. If the destination address is outside of the flash and OTP, the prefetch is aborted and begins again
only when a branch is made back into the flash or OTP. The flash prefetch mechanism only applies to
instruction fetches from program space. Data reads from data memory and from program memory do
not utilize the prefetch buffer capability and thus bypass the prefetch buffer. For example, instructions
such as MAC, DMAC, and PREAD read a data value from program memory. When this read happens,
138

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Flash and OTP Memory

www.ti.com

the prefetch buffer is bypassed but the buffer is not flushed. If an instruction prefetch is already in
progress when a data read operation is initiated, then the data read will be stalled until the prefetch
completes.
Note that the prefetch mechanism gets bypassed when RWAIT is configured as zero.
2.12.8.1.2.1 Data Cache
Along with the prefetch mechanism, a data cache of 128 bits wide is also implemented to improve dataspace read performance. This data cache will not be filled by the prefetch mechanism. When any kind of
data-space read is made by the CPU from an address in the bank, and if the data corresponding to the
requested address is not in the data cache, then 128 bits of data will be read from the bank and loaded in
the data cache. This data is eventually sent to the CPU for processing. The starting address of the access
from flash is automatically aligned to a 128-bit boundary such that the requested address location is within
the 128 bits to be read from the bank. By default, this data cache is disabled and can be enabled by
setting DATA_CACHE_EN bit in the FRD_INTF_CTRL register. Note that the data cache gets bypassed
when RWAIT is configured as zero.
Some other points to keep in mind when working with flash/ OTP:
• Reads of the USER OTP locations are hardwired for 10 wait states. The RWAIT bits have no effect on
these locations.
• CPU writes to the flash or OTP memory map areas are ignored. They complete in a single cycle.
• If a security zone is in the locked state and the respective password lock bits are not all 1s, then,
– Data reads to Zx-CSMPSWD will return 0
– Program space reads to Zx-CSMPSWD will return 0
– Program fetches to Zx-CSMPSWD will return 0
.
• When the Code Security Module (CSM) is secured, reads to the flash/OTP memory map area from
outside the secure zone take the same number of cycles as a normal access. However, the read
operation returns a zero.
• The arbitration scheme in FMC prioritizes CPU accesses in the fixed priority order of data read
(highest priority), program space read and program fetches/program prefetches (lowest priority).
• When FSM interface is active for erase/program operations, data in the prefetch buffers and data
cache in FMC will be flushed.
• When data cache is enabled, the debugger memory window open to Flash/OTP space will invoke data
caching. Hence, debugger memory window should not be left open for Flash/OTP space when
benchmarking the code for performance.

2.12.9 Erase/Program Flash
Flash memory may be programmed either by using the CCS Flash plugin or by using Uniflash. If these
methods are not feasible in an application, the API may be used. The Flash memory should be
programmed, erased, and verified only by using the F021 Flash API library. These functions are written,
compiled and validated by Texas Instruments. The flash module contains a flash state machine (FSM) to
perform program and erase operations. This section only provides a high level description for these
operations, therefore, refer to the TMS320F2837xD Flash API Version 1.54 Reference Guide (SPNU629)
for more information. Note that Flash API execution is interruptible. However, there should not be any
read/fetch access from the Flash bank on which an erase/program operation is in progress. Flash API
must be executed from RAM.
A typical flow to program flash is:
Erase → Program → Verify
Always refer to the device-specific support folder in controlSUITE™ for the latest Flash API library.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

139

Flash and OTP Memory

www.ti.com

2.12.9.1 Erase
When the target flash is erased, it reads as all 1's. This state is called 'blank.' The erase function must be
executed before programming. The user should NOT skip erase on sectors that read as 'blank' because
these sectors may require additional erasing due to marginally erased bits columns. The FSM provides an
“Erase Sector” command to erase the target sector. The erase function erases the data and the ECC
together. This command is implemented by the following Flash API function:
Fapi_issueAsyncCommandWithAddress();
The Flash API provides the following function to determine if the flash bank is 'blank':
Fapi_doBlankCheck();
2.12.9.2 Program
The FSM provides a command to program the USER OTP and Flash. This command is also used to
program ECC check bits.
This command is implemented by the following Flash API function:
Fapi_issueProgrammingCommand();
The Program function provides the options to program data without ECC, data along with user-provided
ECC data, data along with ECC calculated by API software , and to program ECC only.
2.12.9.3 Verify
After programming, the user must perform verify using API function Fapi_doVerify(). This function verifies
the flash contents against supplied data.
Application software typically perform a CRC check of the Flash memory contents during power-up and at
regular intervals during runtime (as needed). Apart from this, ECC logic, when enabled (enabled by
default), catches single-bit errors, double-bit errors, and address errors whenever the CPU reads/fetches
from a Flash address.

2.12.10 Error Correction Code (ECC) Protection
CPU1-FMC and CPU2-FMC contain an embedded single error correction and double error detection
(SECDED) module. SECDED, when enabled, provides the capability to screen out memory faults.
SECDED can detect and correct single-bit data errors and detect address errors/double-bit data errors.
For every 64 bits of flash/OTP data (aligned on a 64-bit memory boundary) that is programmed, eight ECC
check bits have to be calculated and programmed in ECC memory space. Refer to the device data
manual for the Flash/OTP ECC memory map. SECDED works with a total of eight user-calculated error
correction code (ECC) check bits associated with each 64-bit wide data word and its corresponding 128bit memory-aligned address. Users must program ECC check bits along with flash data. TI recommends
using the AutoEccGeneration option available in Plugin/API to program ECC. Users can use the F021
Flash API to calculate and program ECC data along with flash data. Flash API uses hardware ECC logic
in the device to generate the ECC data for the given Flash data. The Flash Plugin, the Flash programming
tool integrated with Code Composer Studio, uses Flash API to generate and program ECC data).
Figure 2-18 illustrates the ECC logic inputs and outputs.

140

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Flash and OTP Memory

www.ti.com

Figure 2-18. ECC Logic Inputs and Outputs
Single-bit data error
Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED

ECC[15:8]

Data[127:64]

128-bit aligned 19-bit CPU address
Flash
and
OTP
Single-bit data error
Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED

Data[63:0]

ECC[7:0]

During an instruction fetch or a data read operation, the 19 most significant address bits (three least
significant bits of address are not considered), together with the 64-bit data/8-bit ECC read-out of flash
banks/ECC memory map area, pass through the SECDED logic and the eight checkbits are produced in
FMC. These eight calculated ECC check bits are then XORed with the stored check bits (user
programmed check bits) associated with the address and the read data. The 8-bit output is decoded inside
the SECDED module to determine one of three conditions:
• No error occurred
• A correctable error (single bit data error) occurred
• A non-correctable error (double bit data error or address error) occurred
If the SECDED logic finds a single-bit error in the address field, then it is considered to be a noncorrectable error.
NOTE: Since ECC is calculated for an entire 64-bit data, a non 64-bit read such as a byte read or a
half-word read will still force the entire 64-bit data to be read and calculated, but only the
byte or half-word will be actually used by the CPU.

This ECC (SECDED) feature is enabled at reset. The ECC_ENABLE register can be used to configure(
enable/disable) the ECC feature. The ECC for the application code must be programmed.. There are two
SECDED modules in each FMC. Out of the 128-bit data (aligned on a 128-bit memory boundary) read
from the bank/OTP address, the lower 64-bits of data and corresponding 8 ECC bits (read from user
programmable ECC memory area) are fed as inputs to one SECDED module along with 128-bit aligned
19-bit address from where data has been read. The upper 64- bits of data and corresponding 8 ECC bits
are fed as inputs to another SECDED module in parallel, along with 128-bit aligned 19-bit address. Each
of the SECDED modules evaluate their inputs and determine if there is any single-bit data error or doublebit data error/address error.
ECC logic will be bypassed when the 64 data bits and the associated ECC bits fetched from the bank are
either all ones or zeros.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

141

Flash and OTP Memory

www.ti.com

2.12.10.1 Single-Bit Data Error
This section provides information for both single-bit data errors and single-bit ECC check bit errors. If
there is a single bit flip (0 to 1 or 1 to 0) in flash data or in ECC data, then it is considered as a single-bit
data error. The SECDED module detects and corrects single-bit errors, if any, in the 64-bit flash data or
eight ECC check bits read from the flash/ECC memory map before the read data is provided to the CPU.
When SECDED finds and corrects single bit data errors, the following information is logged in the ECC
registers if the ECC feature is enabled:
• Address where the error occurred – if the single-bit error occurs in the lower 64-bits of a 128-bit
memory-aligned data, the lower 64-bit memory-aligned address will be captured in the
SINGLE_ERR_ADDR_LOW register. If the single-bit error occurs in the upper 64-bits of a 128-bit
memory-aligned data, the upper 64-bit memory-aligned address will be captured in the
SINGLE_ERR_ADDR_HIGH register.
• Whether the error occurred in data bits or ECC bits – the ERR_TYPE_L and ERR_TYPE_H bit fields in
the ERR_POS register indicate whether the error occurred in data bits or ECC bits of the lower 64-bits,
or the upper 64-bits respectively, of a 128-bit memory-aligned data.
• Bit position at which error occurred – the ERR_POS_L and ERR_POS_H bit fields in the ERR_POS
register indicate the bit position of the error in the lower 64-bits/lower 8-bit ECC, or the upper 64bits/upper 8-bit ECC respectively, of a 128-bit memory-aligned data.
• Whether the corrected value is 0 (FAIL_0_L, FAIL_0_H flags in ERR_STATUS register)
• Whether the corrected value is 1 (FAIL_1_L, FAIL_1_H flags in ERR_STATUS register)
• A single bit error counter that increments on every single bit error occurrence (ERR_CNT register) until
a user-configurable threshold (see ERR_THRESHOLD) is met
• A flag that gets set when one or more single-bit errors occurs after ERR_CNT equals
ERR_THRESHOLD (SINGLE_ERR_INT_FLG flag in the ERR_INTFLG register)
When the ERR_CNT value equals THRESHOLD+1 value and a single bit error occurs, the
SINGLE_ERR_INT flag is set, and an interrupt (FLASH_CORRECTABLE_ERR on C28x PIE has to be
enabled for interrupt, if needed) is fired. The SINGLE_ERR interrupt will not be fired again until the
SINGLE_ERR_INTFLG is cleared. If the single error interrupt flag is not cleared using the corresponding
error interrupt clear bit in the ERR_INTCLR register, the error interrupt will not come again, as this is an
edge-based interrupt.
When multiple single-bit errors get caught by ECC logic, Flash ECC registers will hold the information
related to the latest ECC error. When multiple single-bit errors get caught, both FAIL_0_L and FAIL_1_L
(and/or FAIL_0_H and FAIL_1_H) might get set, indicating that single-bit fail0/fail1 occurred in different 64bit aligned addresses.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash
memory will cause the single-bit error flag to get set when there is a single-bit error in both or in either one
of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data.
2.12.10.2 Uncorrectable Error
Uncorrectable errors include address errors and double-bit errors in data/ECC. When SECDED finds
uncorrectable errors, the following information is logged in ECC registers if the ECC feature is enabled:
• Address where the error occurred – if the uncorrectable error occurs in the lower 64-bits of a 128-bit
memory-aligned data, the lower 64-bit memory-aligned address will be captured in the
UNC_ERR_ADDR_LOW register. If the uncorrectable error occurs in the upper 64-bits of a 128-bit
memory-aligned data, the upper 64-bit memory-aligned address will be captured in the
UNC_ERR_ADDR_HIGH register.
• A flag is set indicating that an uncorrectable error occurred – the UNC_ERR_L and UNC_ERR_H flags
in the ERR_STATUS register indicate the uncorrectable error occurrence in the lower 64-bits/lower 8bit ECC, or the upper 64-bits/upper 8-bit ECC, respectively, of a 128-bit memory-aligned data.
• A flag is set indicating that an uncorrectable error interrupt is fired (UNC_ERR_INTFLG in
ERR_INTFLG register)

142

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Flash and OTP Memory

www.ti.com

When an uncorrectable error occurs, the UNC_ERR_INTFLG bit is set and an uncorrectable error interrupt
is fired. This uncorrectable error interrupt generates an NMI, if enabled. If an uncorrectable error interrupt
flag is not cleared using the corresponding error interrupt clear bit in the ERR_INTCLR register, an error
interrupt will not come again, as this is an edge based interrupt.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash
memory will cause the uncorrectable error flag to get set when there is a uncorrectable error in both or in
either one of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data. NMI
will occur on the CPU for a read of any address location within a 128-bit aligned Flash memory, when
there is an uncorrectable error in both or in either one of the lower 64 and upper 64 bits (or corresponding
ECC check bits) of that 128-bit data.
2.12.10.3 SECDED Logic Correctness Check
Since error detection and correction logic are part of safety-critical logic, safety applications may need to
ensure that the SECDED logic is always working properly. For these safety concerns, in order to ensure
the correctness of the SECDED logic, an ECC test mode is provided to test the correctness of ECC logic
periodically. In this ECC test mode, data/ECC and address inputs to the ECC logic are controlled by the
ECC test mode registers FDATAH_TEST, FDATAL_TEST, FECC_TEST, and FADDR_TEST,
respectively. Using this test mode, users can introduce single-bit errors, double-bit errors, or address
errors and check whether or not SECDED logic is catching those errors. Users can also check if SECDED
logic is reporting any false errors when no errors are introduced.
This ECC test mode can be enabled by setting the ECC_TEST_EN bit in the FECC_CTRL register. When
ECC test mode is enabled, the CPU cannot read the data from flash and instead the CPU gets data from
the ECC test mode registers (FDATAH_TEST/FDATAL_TEST). This is because ECC test mode registers
(FDATAH_TEST, FDATAL_TEST, FECC_TEST) are multiplexed with data from the flash. Hence, the CPU
should not read/fetch from Flash when ECC test mode is enabled. For this reason, ECC test mode code
should be executed from RAM and not from flash.
Only one of the SECDED modules (out of the two SECDED modules that work on lower 64 bits and upper
64 bits of a read 128-bit data) at a time can be tested. The ECC_SELECT bit in the FECC_CTRL register
can be configured by users to select one of the SECDED modules for test.
To test the ECC logic using ECC test mode, users can follow the steps below:
1. Obtain the ECC for a given Flash address (128-bit aligned) and 64-bit data by using the Auto ECC
generation option provided in Flash API .
2. Develop an application to test ECC logic using the above data. In this application
• Write the 128-bit aligned 19-bit Flash address in FADDR_TEST
• Write 64-bit data in FDATAx_TEST (FDATAL_TEST or FDATAH_TEST depending on which ECC
logic the user wants to test) register
• Write the corresponding 8-bit ECC in the FECC_TEST register
• In any of the above three steps, users can insert errors (single-bit data error or double-bit data
error or address error or single-bit ECC error or double-bit ECC error) so that they can check
whether or not ECC logic is able to catch the errors
• Select the ECC logic block (lower 64-bits or upper 64-bits) which needs to be tested using the
ECC_SELECT bit in the FECC_CTRL register
• Enable ECC test mode usingthe ECC_TEST_EN bit in FECC_CTRL register
• Write a value of 1 in the DO_ECC_CALC bit in FECC_CTRL register to enable ECC test logic for a
single cycle to evaluate the address, data, ECC in FADDR_TEST, FDATAx_TEST and
FECC_TEST registers for ECC errors
Once the above ECC test mode registers are written by the user:
• The FECC_OUTH register holds the data output bits 63:32 from the SECDED block under test
• The FECC_OUTL register holds the data output bits 31:0 from the SECDED block under test
• The FECC_STATUS register holds the status of single-bit error occurrence, uncorrectable error
occurrence, and error position of single- bit error in data/check bits

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

143

Flash and OTP Memory

www.ti.com

2.12.10.4 Reading ECC Memory From a Higher Address Space
In these devices, ECC memory for Flash and OTP is allocated at a higher address space (address width
more than 22 bits). C2000 Codegen tools (6.2 and onwards) are updated to include the below intrinsics to
read ECC space.
For 16-bit read:
unsigned int variable = __addr32_read_uint16(unsigned long address);
For 32-bit read:
unsigned long variable = __addr32_read_uint32(unsigned long address);

2.12.11 Reserved Locations Within Flash and OTP
When allocating code and data to flash and OTP memory, keep the following reserved locations in mind:
• The entire OTP has reserved user-configurable locations for security and boot process. For more
details on the functionality of these fields, please refer to Section 2.13, and the ROM Code and
Peripheral Booting chapter.
• Refer to the ROM Code and Peripheral Booting chapter for reserved locations in flash for real-time
operating system usage and a boot-to-flash entry point. A boot-to-flash entry point is reserved for an
entry-into-flash branch instruction. When the boot-to-flash boot option is used, the boot ROM will jump
to this address in flash. If the user programs a branch instruction here, that will then redirect code
execution to the entry point of the application.

2.12.12 Procedure to Change the Flash Control Registers
During flash configuration, no accesses to the flash or OTP can be in progress. This includes instructions
still in the CPU pipeline, data reads, and instruction prefetch operations. To be sure that no access takes
place during the configuration change, you should follow the procedure shown below for any code that
modifies the flash control registers.
1. Start executing application code from RAM/Flash/OTP.
2. Branch to or call the flash configuration code (that writes to flash control registers) in RAM. This is
required to properly flush the CPU pipeline before the configuration change. The function that changes
the flash configuration cannot execute from the Flash or OTP. It must reside in RAM.
3. Execute the flash configuration code (should be located in RAM) that writes to flash control registers
like FRDCNTL, FRD_INTF_CTRL, and so on.
4. At the end of the flash configuration code execution, wait eight cycles to let the write instructions
propagate through the CPU pipeline. This must be done before the return-from-function call is made.
5. Return to the calling function which might reside in RAM or Flash/OTP and continue execution.

2.12.13 Flash Pump Ownership Semaphore
Each CPU subsystem has its own flash bank, which it can read, program, and erase. Both flash banks
share a single charge pump for program and erase operations. Hence, only one CPU can program or
erase its flash at any given time. A CPU can read data and execute code from its flash even when the
other CPU is programming or erasing. The flash pump ownership semaphore allows one CPU to take
control of the pump without being interrupted by the other CPU.
The pump ownership semaphore is implemented as a two-bit field in a PUMPREQUEST register with
special write protections. This register requires a key field to be written at the same time as the
semaphore bits. The possible semaphore states are:
00 or 11
01
10

144

System Control

Either CPU may write to the semaphore. CPU1 has control of the resource by
default. 00 is the reset state.
CPU2 has exclusive control of the resource and exclusive write access to the
semaphore.
CPU1 has exclusive control of the resource and exclusive write access to the
semaphore.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Flash and OTP Memory

www.ti.com

Each CPU is only allowed to take control of the pump for itself. Direct transfer between the 01 and 10
states is not allowed. However, CPU1 may force both semaphores into the default state (00) at any time
by putting CPU2 into reset. Figure 2-19 shows the allowed states and state transitions.
Figure 2-19. Flash Pump Semaphore (PUMPREQUEST) States and State Transitions
CPU1 should write 10 to gain pump
control before erasing or programming
its flash bank.

Semaphore state 00 or 11

CPU2 should write 01 to gain pump
control before erasing or programming
its flash bank.

Pump controlled by CPU1
Default at reset

CPU1 should write 00 to relinquish
pump control once the erase or
program is complete.

CPU2 should write 00 to relinquish
pump control once the erase or
program is complete.

Semaphore state 10

Semaphore state 01
Not allowed

Pump controlled by CPU1

Pump controlled by CPU2
Not allowed

CPU2 cannot take control of the pump in this
state.

CPU1 cannot take control of the pump in this
state.

2.12.13.1 Clock Configuration Semaphore
Both CPUs can access the PLL and peripheral clock configuration registers. The clock configuration
semaphore allows one CPU to access the registers without being interrupted by the other CPU.
The clock configuration semaphore is implemented as a two-bit field in a register with special write
protections. This register requires a key field to be written at the same time as the semaphore bits. The
possible semaphore states are:
00 or 11

Either CPU may write to the semaphore. CPU1 has control of the clock
configuration registers by default. 00 is the reset state.
CPU2 has exclusive control of the clock configuration registers and exclusive
write access to the semaphore.
CPU1 has exclusive control of the clock configuration registers and exclusive
write access to the semaphore.

01
10

Each CPU is only allowed to take control of the clock configuration registers for itself. However, CPU1
may force both semaphores into the default state (00) at any time by putting CPU2 into reset. Figure 2-20
shows the allowed states and state transitions.
Figure 2-20. Clock Configuration Semaphore (CLKSEM) State Transitions
CPU1 should write 10 to gain
mastership of the clock configuration
registers.

Semaphore state 00 or 11

CPU2 should write 01 to gain
mastership of the clock configuration
registers.

Clock configuration registers
are controlled by CPU1
CPU1 should write 00 to relinquish
mastership once configuration is
complete.

Default at reset

CPU2 should write 00 to relinquish
mastership once configuration is
complete.

Semaphore state 10

Semaphore state 01
Not allowed

Clock configuration registers
are controlled by CPU1

Clock configuration registers
are controlled by CPU2

Not allowed

CPU2 cannot take control of the pump in this
state

CPU1 cannot take control of the pump in this
state

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

145

Dual Code Security Module (DCSM)

www.ti.com

2.13 Dual Code Security Module (DCSM)
The dual code security module (DCSM) is a security feature incorporated in this device. It prevents access
and visibility to on-chip secure memories (and other secure resources) to unauthorized persons. It also
prevents duplication and reverse engineering of proprietary code. The term “secure” implies access to onchip secure memories and resources are blocked. The term “unsecure” implies access is allowed (the
contents of the memory could be read by any means); for example, through a debugging tool such as
Code Composer Studio™.
There are two CPUs on this device and each CPU subsystem has its own CSM for code protection. Each
CPU subsystem’s CSM has dual-zone security, which means the CPU1 subsystem has two zones
(zone1/zone2) and CPU2 also has two zones (zone1/zone2).

2.13.1 Functional Description
The security module restricts the CPU access to on-chip secure memory and resources without
interrupting or stalling CPU execution. When a read occurs to a secure memory location, the read returns
a zero value and CPU execution continues with the next instruction. This, in effect, blocks read and write
access to secure memories through the JTAG port or external peripherals.
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
mechanism for both the zones is identical. Each zone has its own dedicated secure resource and
allocated secure resource. The following are different secure resources available on this device:
• OTP: Each zone has its own dedicated secure OTP (USER OTP). This contains the security
configurations for the individual zone. If a zone is secure, its USER OTP content (including CSM
passwords) can be read (execution not allowed) only if the zone is unlocked using the password match
flow (PMF).
• CLA: The CLA is a secure resource which can be allocated to either zone by configuring the
GRABRAM location in the USER OTP. CLA configuration can only be performed by code running from
the zone to which it has been allocated. The CLA message RAMs also belong to the same zone.
• RAM: All Dx and LSx RAMs can be secure RAM on this device. These RAMs can be allocated to
either zone by configuring the respective GRABRAM location in the USER OTP.
• Flash Sectors: Flash Sectors can be secure on this device. Each Flash sector can be allocated to
either zone by configuring the respective GRABSECT location in the USER OTP.
• Secure ROM: This device also has secure ROM which is EXEONLY-protected. This ROM contains
specific function for the user, provided by TI.
Table 2-14 shows the status of a RAM block based on the configuration in GRABRAM register.
Table 2-14. RAM Status
GRAM_RAMx Bits in Z1_GRABRAMR
Register

GRAM_RAMx Bits in Z2_GRABRAMR
Register

00

XX

GRAM_RAMx is inaccessible

Ownership

XX

00

GRAM_RAMx is inaccessible

Differential Value (01/10)

Differential Value (01/10)

GRAM_RAMx is inaccessible

Differential Value (01/10)

11

GRAM_RAMx belongs to Z1

11

Differential Value (01/10)

GRAM_RAMx belongs to Z2

11

11

GRAM_RAMx is Non-Secure

The security of each zone is ensured by its own 128-bit (four 32-bit words) password (CSM password).
The password for each zone is stored in its dedicated OTP location based on a zone-specific link pointer.
A zone can be unsecured by executing the password match flow (PMF), described in Section 2.13.3.3.2.
There are three types of accesses: data/program reads, JTAG access, and instruction fetches (calls,
jumps, code executions, ISRs). Instruction fetches are never blocked. JTAG accesses are always blocked
when a memory is secure. Data reads to a secure memory are always blocked unless the program is
executing from a memory which belongs to the same zone. Data reads to unsecure memory are always
allowed. Table 2-15 shows the levels of security.
146

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Dual Code Security Module (DCSM)

www.ti.com

Table 2-15. Security Levels
PMF Executed With Correct
Password?

Operating Mode of the Zone

Program Fetch Location

Security Description

No

Secure

Outside secure memory

Only instruction fetches by the
CPU are allowed to secure
memory. In other words, code
can still be executed, but not
read.

No

Secure

Inside secure memory

CPU has full access (except for
EXEONLY memories where
read is not allowed). JTAG port
cannot read the secured
memory contents.

Yes

Non-Secure

Anywhere

Full access for CPU and JTAG
port to secure memory of that
zone.

If the password locations of a zone have all 128 bits as ones, the zone is considered unsecure. Since new
Flash devices have erased Flash (all ones), only a read of the password locations is required to bring any
zone into unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is
secure, regardless of the contents of the CSMKEY registers. This means the zone can’t be unlocked using
PMF, the password match flow described in Section 2.13.3.3.2. Therefore, the user should never use all
zeros as a password. A password of all zeros will prevent debug of secure code or reprogramming the
Flash.
CSMKEY registers are user-accessible registers that are used to unsecure the zones.
2.13.1.1 Emulation Code Security Logic (ECSL)
In addition to the CSM, the emulation code security logic (ECSL) has been implemented using a 64-bit
password (part of existing CSM password) for each zone to prevent unauthorized users from stepping
through secure code. A halt in secure code while the emulator is connected will trip the ECSL and break
the emulation connection to the specific CPU subsystem for which the ECSL violation occurred. To allow
emulation of secure code, while maintaining the CSM protection against secure memory reads, the user
must write the correct 64-bit password into the CSMKEY (0/1) registers, which matches the password
value stored in the USER OTP of that zone. This will disable the ECSL for the specific zone.
When initially debugging a device with the password locations in OTP programmed (secured), the
emulator takes some time to take control of the CPU. During this time, the CPU will start running and may
execute an instruction that performs an access to a protected ECSL area and ifthe CPU is halted when
the program counter (PC) is pointing to a secure location, the ECSL will trip and cause the emulator
connection to be broken.
The solution to this problem is:
• Use the Wait Boot Mode boot option. In this mode, the CPU will be in a loop and hence will not jump to
the user application code. Using this BOOTMODE, the user can connect to CCS and debug the code.
2.13.1.2 CPU Secure Logic
The CPU Secure Logic (CPUSL) on this device prevents a hacker from reading the CPU registers in a
watch window while code is running in a secure zone. All accesses to CPU registers when the PC points
to a secure location are blocked by this logic. The only exception to this is read access to the PC. It is
highly recommended not to write into the CPU register in this case, because proper code execution may
get affected. If the CSM is unlocked using the CSM password match flow, the CPUSL logic also gets
disabled.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

147

Dual Code Security Module (DCSM)

www.ti.com

2.13.1.3 Execute-Only Protection
To achieve a higher level of security on secure Flash sectors and RAM blocks that store critical user code
(instruction opcodes), the Execute-Only protection feature is provided. When the Execute-Only protection
is turned on for any secure Flash sector or RAM block, data reads to that Flash sectors are disallowed
from any code (even from secure code). Execute-only protection for a Flash sector and RAM block can be
turned on by configuring the bit field associated for that particular sector/RAM block in the zone's (which
has ownership of that sector/RAM block) EXEONLYSECT and EXEONLYRAM register, respectively.
2.13.1.4 Password Lock
The password locations for each zone can be locked by programming the zone’s PSWDLOCK field with
any value other than “1111” (0xF) at the PSWDLOCK location in OTP. Until the passwords of a zone are
locked, password locations will not be secure and can be read from the debugger as well as code running
from non-secure memory. This feature can be used by the user to avoid accidental locking of the zone
while programming the Flash sectors during the software development phase. On a fresh device the value
for password lock fields for all zones at the PSWDLOCK location in OTP will be “1111” which means the
password for all zones will be unlocked.
NOTE: Password unlock only makes password locations non-secure. All other secure memories and
other locations of Flash sectors, which contain a password, remains secure as per security
settings. But since passwords are non-secure, anyone can read the password and make the
zone non-secure by running through PMF.

2.13.1.5 Link Pointer and Zone Select
For each of the two security zones of each CPU subsystem on this device, a dedicated OTP block exists
that holds the configuration related to zone’s security. The following are the available programmed
configurations:
• Zx-LINKPOINTER1
• Zx-LINKPOINTER2
• Zx-LINKPOINTER3
• Zx-PSWDLOCK
• Zx-CRCLOCK
• Zx-BOOTCTRL
• Zx-EXEONLYRAM
• Zx-EXEONLYSECT
• Zx-GRABRAM
• Zx-GRABSECT
• Zx-CSMPASSWORD
Since OTP can’t be erased, to provide flexibility of configuring some of the security settings like CSM
passwords, allocation of RAM/Flash sectors and their attributes, multiple times by the user, the following
configurations are placed in zone select regions of each zone’s OTP Flash.
• Zx-EXEONLYRAM
• Zx-EXEONLYSECT
• Zx-GRABRAM
• Zx-GRABSECT
• Zx-CSMPASSWORD
The location of the zone select region in OTP is decided based on the value of three 29-bit link pointers
(Zx-LINKPOINTERx) programmed in the OTP of each zone of both CPU subsystems. All OTP locations
except link pointer locations are protected with ECC. Since the link pointer locations are not protected with
ECC, three link pointers are provided that need to be programmed with the same value. The final value of
the link pointer is resolved in hardware when a dummy read is done to all the link pointers by comparing
148

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Dual Code Security Module (DCSM)

www.ti.com

all the three values (bit-wise voting logic). Since in OTP, a ‘1’ can be flipped by the user to ‘0’ but ‘0’ can’t
be flipped to ‘1’ (no erase operation for OTP), the most significant bit position in the resolved link pointer
which is ‘0’, defines the valid base address for the zone select region. While generating the final link
pointer value, if the bit patterns is not one of those listed in Figure 2-21, the final link pointer value
becomes All_1 (0xFFFF_FFFF) which selects the Zone-Select-Block1 (also known as the default zone
select block).
Figure 2-21. Storage of Zone-Select Bits in OTP
Zx-LINKPOINTER
32’bxxx11111111111111111111111111111
32’bxxx1111111111111111111111111111
0
32’bxxx111111111111111111111111111
0x
32’bxxx11111111111111111111111111
0xx
32’bxxx1111111111111111111111111
0xxx
32’bxxx111111111111111111111111
0xxxx
32’bxxx11111111111111111111111
0xxxxx
32’bxxx1111111111111111111111
0xxxxxx
32’bxxx111111111111111111111
0xxxxxxx
32’bxxx11111111111111111111
0xxxxxxxx
32’bxxx1111111111111111111 0xxxxxxxxx
32’bxxx111111111111111111 0xxxxxxxxxx
32’bxxx11111111111111111 0xxxxxxxxxxx
32’bxxx1111111111111111 0xxxxxxxxxxxx
32’bxxx111111111111111 0xxxxxxxxxxxxx
32’bxxx11111111111111 0xxxxxxxxxxxxxx
32’bxxx1111111111111 0xxxxxxxxxxxxxxx
32’bxxx111111111111 0xxxxxxxxxxxxxxxx
32’bxxx11111111111 0xxxxxxxxxxxxxxxxx
32’bxxx1111111111 0xxxxxxxxxxxxxxxxxx
32’bxxx111111111 0xxxxxxxxxxxxxxxxxxx
32’bxxx11111111 0xxxxxxxxxxxxxxxxxxxx
32’bxxx1111111 0xxxxxxxxxxxxxxxxxxxxx
32’bxxx111111 0xxxxxxxxxxxxxxxxxxxxxx
32’bxxx11111 0xxxxxxxxxxxxxxxxxxxxxxx
32’bxxx1111 0xxxxxxxxxxxxxxxxxxxxxxxx
32’bxxx111 0xxxxxxxxxxxxxxxxxxxxxxxxx
32’bxxx11 0xxxxxxxxxxxxxxxxxxxxxxxxxx
32’bxxx10xxxxxxxxxxxxxxxxxxxxxxxxxxx
32’bxxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxx

Addr Offset Of
Zone-Select
Block
0x20
0x30
0x40
0x50
0x60
0x70
0x80
0x90
0xa0
0xb0
0xc0
0xd0
0xe0
0xf0
0x100
0x110
0x120
0x130
0x140
0x150
0x160
0x170
0x180
0x190
0x1a0
0x1b0
0x1c0
0x1d0
0x1e0
0x1f0

Zone Select Block
Addr Offset

32-Bit Content

0x0

Zx-EXEONLYRAM

0x2

Zx-EXEONLYSECT

0x4

Zx-GRABRAM

0x6

Zx-GRABSECT

0x8

Zx-CSMPSWD0

0xa

Zx-CSMPSWD1

0xc

Zx-CSMPSWD2

0xe

Zx-CSMPSWD3

NOTE: Address locations for other security settings (PSWDLOCK/CRCLOCK) that are not part of
Zone Select blocks) can be programmed only once; therefore, the user should program them
towards end of the development cycle.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

149

Dual Code Security Module (DCSM)

www.ti.com

Figure 2-22. Location of Zone-Select Block Based on Link-Pointer
Zone 1 OTP Flash
0x78000

Zone 2 OTP Flash

Z1-LINKPOINTER 1

0x78200

Z2-LINKPOINTER 1

0x78002

Reserved

0x78202

Reserved

0x78004

Z1-LINKPOINTER 2

0x78204

Z2-LINKPOINTER 2

0x78006

Reserved

0x78206

Reserved

0x78008

Z1-LINKPOINTER 3

0x78208

Z2-LINKPOINTER 3

Reserved

0x7820A

Reserved

0x78210

Z2 PSWDLOCK

0x78212

Reserved

0x7800A
0x78010

Z1-PSWDLOCK

0x78012
0x78014

Zone Select Block

Reserved
Addr
Offset

Z1-CRCLOCK

0x78016

Reserved

0x78018

Reserved

32-Bit Content
0x78214

0x0

Zx-EXEONLYRAM

0x2

Zx-EXEONLYSECT

0x4

Zx-GRABRAM

0x7801A

Reserved

0x7801E

Z1-BOOTCTRL

0x78020

ZoneSelectBlock1
(16x16Bits)

0x6

Zx-GRABSECT

0x8

Zx-CSMPSWD0

0x78030

ZoneSelectBlock2
(16x16Bits)

0xa

Zx-CSMPSWD1

0xc

Zx-CSMPSWD2

0xe

Zx-CSMPSWD3

.
.
0x781F0

Z2-CRCLOCK

0x78216

Reserved

0x78218

Reserved

0x7821A

Reserved

0x7821E

Z2-BOOTCTRL

0x78220

ZoneSelectBlock1
(16x16Bits)

0x78230

ZoneSelectBlock2
(16x16Bits)
.
.

ZoneSelectBlockn
(16x16Bits)

0x783F0

ZoneSelectBlockn
(16x16Bits)

2.13.1.5.1 C Code Example to get Zone Select Block Addr for Zone1
unsigned long LinkPointer;
unsigned long *Zone1SelBlockPtr;
int Bitpos = 28;
int ZeroFound = 0;
// Read Z1-Linkpointer register of DCSM module.
LinkPointer = *(unsigned long *)0x5F000;
// Bits 31 30 and 29 as most-sigificant 0 are reserved LinkPointer options
LinkPointer = LinkPointer << 2;
while ((ZeroFound == 0) && (bitpos > -1))
{
if ((LinkPointer & 0x80000000) == 0)
{
ZeroFound = 1;
Zone1SelBlockPtr = (unsigned long *)(0x78000 + ((bitpos + 3)*16));
} else
{
bitpos--;
LinkPointer = LinkPointer << 1;
}
}
if (ZeroFound == 0)
{

150

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Dual Code Security Module (DCSM)

www.ti.com
//Default in case there is no zero found.
Zone1SelBlockPtr = (unsigned long *)0x78020;
}

2.13.1.6 Flash and OTP Erase/Program
On this device, OTP as well as normal Flash, are secure resources. Each zone has its own dedicated
OTP, whereas normal Flash sectors can be allocated to any zone based on the value programmed in the
GRABSECT location in OTP. Each zone has its own CSM passwords; read and write accesses are not
allowed to resources owned by Z1 from code running from memory allocated to Z2 and vice versa. Before
programming any secure Flash sector, the user must either unlock the zone to which that particular sector
belongs, using PMF or execute the Flash programming code from secure memory which belongs to the
same zone. The same is the case for erasing any secure Flash sector. To program the security settings in
OTP Flash, the user must unlock the CSM of the respective zone. Unless the zone is unlocked, security
settings in OTP Flash cannot be updated. The OTP content cannot be erased.
This device has only one Flash pump used for erase/program operation of normal Flash and OTP Flash. A
semaphore mechanism is provided to avoid the conflict between Zone1 and Zone2. A zone needs to grab
this semaphore to successfully complete the erase/program operation on the Flash sectors allocated to
that zone. A semaphore can be grabbed by a zone by writing the appropriate value in the SEM field of the
FLSEM register. For further details of this field, see the register description.
NOTE: If there is a loss of power or a reset of any nature during the flash programming operation,
there is high probability of some (or possibly all) of the 128 bits in the corresponding 128-bit
aligned address getting corrupted. If this happens while programming the password locations
in USER OTP, the passwords may get corrupted.

2.13.1.7 Safe Copy Code
In some applications, the user may want to copy the code from secure Flash to secure RAM for better
performance. The user cannot do this for EXEONLY flash sectors because EXEONLY secure memories
cannot be read from anywhere. TI provides specific “Safe Copy Code” library functions for each zone to
enable the user to copy content from EXEONLY secure flash sectors to EXEONLY RAM blocks. These
functions do the copy-code operation in a highly secure environment and allow a copy to be performed
only when the following conditions are met:
• The secure RAM block and the secure flash sector belong to the same zone.
• Both the secure RAM block and the secure flash sector have EXEONLY protection enabled.
For further usage of these library functions, see the device-specific Boot ROM documentation.
2.13.1.8 SafeCRC
Since reads from EXEONLY memories are not allowed, the user cannot calculate the CRC for content in
EXEONLY memories using the VCU-II. But in some safety-critical applications, the user may have to
calculate the CRC on these memories as well. To enable this without compromising on security, TI
provides specific “SafeCRC” library functions for each zone. These functions do the CRC calculation in
highly secure environment and allow a CRC calculation to be performed only when the following
conditions are met:
• The source address should be modulo the number of words (based on length_id) for which the CRC
needs to be calculated.
• The destination address should belong to the same zone as the source address.
For further usage of these library functions, see the device-specific Boot ROM documentation.
NOTE: The user must disable all the interrupts before calling the safe copy code and the safeCRC
function. If there is a vector fetch during copy code operation, the CPU gets reset
immediately.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

151

Dual Code Security Module (DCSM)

www.ti.com

Disclaimer: Code Security Module Disclaimer The Code Security Module (CSM) included on this device
was designed to password protect the data stored in the associated memory and is warranted by Texas
Instruments (TI), in accordance with its standard terms and conditions, to conform to TI's published
specifications for the warranty period applicable for this device. TI DOES NOT, HOWEVER, WARRANT
OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE
DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER
MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO
EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR
PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM
OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

2.13.2 CSM Impact on Other On-Chip Resources
On this device, M0/M1 and GSx memories are not secure. To avoid any potential hacking when the device
is in the default state (post reset), accesses (all types) to all memories (secure as well as non-secure,
except BOOT-ROM and OTP ) are disabled until proper security initialization is done. This means that
after reset none of the memory resources except BOOT_ROM and OTP is accessible to the user.
The following steps are required after reset (any type of reset) to initialize the security on each CPU
subsystem.
• Dummy Read to address location of SECDC (0x703F0, TI-reserved register) in TI OTP
• Dummy Read to address location of Z1_LINKPOINTER1 in Z1 OTP
• Dummy Read to address location of Z1_LINKPOINTER2 in Z1 OTP
• Dummy Read to address location of Z1_LINKPOINTER3 in Z1 OTP
• Dummy Read to address location of Z1_PSWDLOCK in Z1 OTP
• Dummy Read to address location of Z1_CRCLOCK in Z1 OTP
• Dummy Read to address location 0x78018 in Z1 OTP
• Dummy Read to address location of Z1_BOOTCTRL in Z1 OTP
• Read to memory map register of Z1_LINKPOINTER in DCSM module to calculate the address of zone
select block for Z1
• Dummy read to address location of Z1_EXEONLYRAM in Z1 OTP
• Dummy read to address location of Z1_EXEONLYSECT in Z1 OTP
• Dummy read to address location of Z1_GRABRAM in Z1 OTP
• Dummy read to address location of Z1_GRABSECT in Z1 OTP
• Dummy Read to address location of Z2_LINKPOINTER1 in Z2 OTP
• Dummy Read to address location of Z2_LINKPOINTER2 in Z2 OTP
• Dummy Read to address location of Z2_LINKPOINTER3 in Z2 OTP
• Dummy Read to address location of Z2_PSWDLOCK in Z2 OTP
• Dummy Read to address location of Z2_CRCLOCK in Z2 OTP
• Dummy Read to address location 0x78218 in Z2 OTP
• Dummy Read to address location of Z2_BOOTCTRL in Z2 OTP
• Read to memory map register of Z2_LINKPOINTER in DCSM module to calculate the address of zone
select block for Z2
• Dummy read to address location of Z2_EXEONLYRAM in Z2 OTP
• Dummy read to address location of Z2_EXEONLYSECT in Z2 OTP
• Dummy read to address location of Z2_GRABRAM in Z2 OTP
• Dummy read to address location of Z2_GRABSECT in Z2 OTP

152

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Dual Code Security Module (DCSM)

www.ti.com

2.13.3 Incorporating Code Security in User Applications
Code security is typically not required in the development phase of a project. However, security is needed
once a robust code is developed for a zone. Before such a code is programmed in the Flash memory, a
CSM password should be chosen to secure the zone. Once a CSM password is in place for a zone, the
zone is secured (programming a password at the appropriate locations and either performing a device
reset or setting the FORCESEC bit (Zx_CR.15) is the action that secures the device). From that time on,
access to debug the contents of secure memory by any means (via JTAG, code running off external/onchip memory, and so forth) requires a valid password. A password is not needed to run the code out of
secure memory (such as in a typical end-user usage); however, access to secure memory contents for
debug purposes, requires a password.
2.13.3.1 Environments That Require Security Unlocking
The following are the typical situations under which unsecuring can be required:
• Code development using debuggers (such as Code Composer Studio). This is the most common
environment during the design phase of a product.
• Flash programming using TI's Flash utilities such as Code Composer Studio On-Chip Flash
Programmer plug-in or the Uniflash tool. Flash programming is common during code development and
testing. Once the user supplies the necessary password, the flash utilities disable the security logic
before attempting to program the Flash. The flash utilities can disable the code security logic in new
devices without any authorization, since new devices come with an erased Flash. However,
reprogramming devices that already contain a custom password require the password to be supplied to
the flash utilities in order to unlock the device to enable programming. In custom programming
solutions that use the Flash API supplied by TI, unlocking the CSM can be avoided by executing the
Flash programming algorithms from secure memory.
• Custom environment defined by the application
In addition to the above, access to secure memory contents can be required in situations such as:
– Using the on-chip bootloader to load code or data into secure SARAM or to erase and program the
Flash.
– Executing code from on-chip unsecure memory and requiring access to secure memory for the
lookup table. This is not a suggested operating condition as supplying the password from external
code could compromise code security.
The unsecuring sequence is identical in all the above situations. This sequence is referred to as the
password match flow (PMF) for simplicity. Figure 2-23 explains the sequence of operation that is required
every time the user attempts to unsecure a particular zone. A code example is listed for clarity.
2.13.3.2 CSM Password Match Flow
Password match flow (PMF) is essentially a sequence of four dummy reads from password locations
(PWL) followed by four writes (32-bit writes) to CSMKEY(0/1/2/3) registers. Figure 2-23 shows how PMF
helps to initialize the security logic registers and disable security logic.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

153

Dual Code Security Module (DCSM)

www.ti.com

Figure 2-23. CSM Password Match Flow (PMF)
START

Zone secure after reset
or runtime

Dummy Read of CSM PWL
of the secure zone, which
needs to be unsecure

Are CSM
PWL = All
Fs?

YES

NO

Write the CSM Password of
that zone into CSMKEYx
registers

NO

Correct
Password?

YES

Zone Unsecure

2.13.3.3 Unsecuring Considerations for Zones With and Without Code Security
Case 1 and Case 2 provide unsecuring considerations for zones with and without code security.
• Case 1: Zone With Code Security
A zone with code security should have a predetermined password stored in the password locations of
that zone. The following are steps to unsecure any secure zone:
154

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Dual Code Security Module (DCSM)

www.ti.com

•

1. Perform a dummy read of the password locations of that zone.
2. Write the password into the CSMKEY registers.
3. If the password is correct, the zone becomes unsecure; otherwise, it stays secure.
Case 2: Zone Without Code Security
A zone without code security should have 0x FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF (128
bits of all ones) stored in the password locations. The following are steps to use this zone:
1. At reset, the CSM will lock memory regions protected by the CSM.
2. Perform a dummy read of the password locations.
3. Since the password is all ones, this alone will unlock the zone and all the secure memories
dedicated to that zone are fully accessible immediately after this operation is completed.
NOTE: Even if a zone is not protected with a password (all password locations all ones), the CSM
will lock at reset. Thus, a dummy read operation must still be performed on these zones prior
to reading, writing, or programming secure memory if the code performing the access is
executing from outside of the CSM protected memory region. The Boot ROM code does this
dummy read for convenience.

2.13.3.3.1 C Code Example to Unsecure C28x Zone1
volatile long int *CSM = (volatile long int *)0x5F010;
//CSM register file
volatile long int *CSMPWL = (volatile long int *)0x78028; //CSM Password location (assuming
default Zone sel block)
volatile int tmp;
int I;
// Read the 128-bits of the CSM password locations (PWL)
//
for (I=0;I<4; I++) tmp = *CSMPWL++;
// If the password locations (CSMPWL) are all = ones (0xFFFF),
// then the zone will now be unsecure. If the password
// is not all ones (0xFFFF), then the code below is required
// to unsecure the CSM.
// Write the 128-bit password to the CSMKEY registers
// If this password matches that stored in the
// CSLPWL then the CSM will become unsecure. If it does not
// match, then the zone will remain secure.
// An example password of:
// 0x11112222333344445555666677778888 is used.
*CSM++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010
*CSM++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F012
*CSM++ = 0x66665555; // Register Z1_CSMKEY2 at 0x5F014
*CSM++ = 0x88887777; // Register Z1_CSMKEY3 at 0x5F016

2.13.3.3.2 C Code Example to Resecure C28x Zone1
volatile int *Z1_CR = 0x5F019; //CSMSCR register
//Set FORCESEC bit
*Z1_CR = 0x8000;

2.13.3.4 Environments That Require ECSL Unlocking
The following are the typical situations under which unsecuring can be required:
• The user develops some main IP, and then outsources peripheral functions to a subcontractor who
must be able to run the user code during debug and may halt while main IP code is running. If ECSL is
not unlocked, then Code Composer Studio connections will get disconnected, which can be
inconvenient for the user. Note that unlocking ECSL doesn’t enable access to secure code but only
avoids disconnection of CCS (JTAG).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

155

Dual Code Security Module (DCSM)

www.ti.com

2.13.3.5 ECSL Password Match Flow
A password match flow (PMF) is essentially a sequence of eight dummy reads from password locations
(PWL) followed by two writes to KEY registers. Figure 2-24 shows how the PMF helps to initialize the
security logic registers and disable security logic.
Figure 2-24. ECSL Password Match Flow (PMF)
START

Zone’s ECSL LOCK after
reset or runtime

Dummy read of ECSL PWL
of the secure zone, which
ECSL needs to be unlocked

Are ECSL
PWL = All
Fs?

YES

NO

Write the ECSL Password of
that zone into ECSLKEYx
registers

NO

Correct
Password?

YES

Zone ECSL Unlock

156

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

JTAG

www.ti.com

2.13.3.6 ECSL Disable Considerations for any Zone
A zone with ECSL enabled should have a predetermined ECSL password stored in the ECSL password
locations in Flash (same as lower 64 bits of CSM passwords). The following are steps to disable the ECSL
for any particular zone:
• Perform a dummy read of CAM password locations of that Zone
• Write the password into the CSMKEYx registers, corresponding to that Zone.
• If the password is correct, the ECSL gets disabled; otherwise, it stays enabled.
2.13.3.6.1 C Code Example to Disable ECSL for C28x-Zone1
volatile long int *ECSL = (volatile int *)0x5F010;
//ECSL register file
volatile long int *ECSLPWL = (volatile int *)0x78028; //ECSL Password location (assuming default
Zone sel block)
volatile int tmp;
int I;
// Read the 64-bits of the password locations (PWL)
.
for (I=0;I<2; I++) tmp = *ECSLPWL++;
// If the ECSL password locations (ECSLPWL) are all = ones (0xFFFF),
// then the ECSL will now be disable. If the password
// is not all ones (0xFFFF), then the code below is required
// to disable the ECSL.
// Write the 64-bit password to the CSMKEYx registers
// If this password matches that stored in the
// CSMPWL then ECSL will get disable. If it does not
// match, then the zone will remain secure.
// An example password of:
// 0x1111222233334444 is used.
*ECSL++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010
*ECSL++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F012

2.13.3.7 Device Unique ID
The CPU1 OTP contains a 256-bit value that is made up of both random and sequential parts. This value
can be used as a seed for code encryption. The starting address of the value is 0x703C0. The first 192
bits are random, the next 32 bits are sequential, and the last 32 bits are a checksum value.

2.14 JTAG
Gel files perform certain initialization tasks. This helps the users in a debug environment. However, when
executed standalone (without the emulator connected) the application may not work as expected, since
there is no gel file to perform those initializations. For example, gel file disables watchdog. If user code
does not service the watchdog in the application (or fails to disable it), there will be a difference in how the
application behaves with the debugger and without.
Common tasks performed by the gel files (but not boot-ROM)
On Reset:
• Disable Flash ECC on some devices.
– Disabling ECC only when using Flash API functions, see the Flash API User Guide for details.
Otherwise, TI suggests to always program ECC and enable ECC-check.
• Disable Watchdog
• Enable CLA clock
• Select real-time mode or C28x mode
On Restart:
• Select real-time mode or C28x mode
• Clear IER and IFR
On Target Connect:
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

157

JTAG

www.ti.com

•

158

Select real-time mode or C28x mode

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15 Registers
2.15.1 Base Addresses
Table 2-16. System Control Base Address Table
Start Address

End Address

CpuTimer0Regs

Device Registers

CPUTIMER_REGS

0x0000_0C00

0x0000_0C07

CpuTimer1Regs

CPUTIMER_REGS

0x0000_0C08

0x0000_0C0F

CpuTimer2Regs

CPUTIMER_REGS

0x0000_0C10

0x0000_0C17

PieCtrlRegs

PIE_CTRL_REGS

0x0000_0CE0

0x0000_0CFF

WdRegs

WD_REGS

0x0000_7000

0x0000_703F

NmiIntruptRegs

NMI_INTRUPT_REGS

0x0000_7060

0x0000_706F

XintRegs

XINT_REGS

0x0000_7070

0x0000_707F

DmaClaSrcSelRegs

DMA_CLA_SRC_SEL_REGS

0x0000_7980

0x0000_79BF

FlashPumpSemaphoreRegs

FLASH_PUMP_SEMAPHORE_RE
GS

0x0005_0024

0x0005_0025

DevCfgRegs (1)

DEV_CFG_REGS

0x0005_D000

0x0005_D17F

ClkCfgRegs

CLK_CFG_REGS

0x0005_D200

0x0005_D2FF

CpuSysRegs

CPU_SYS_REGS

0x0005_D300

0x0005_D3FF

RomPrefetchRegs (1)

ROM_PREFETCH_REGS

0x0005_E608

0x0005_E609

DcsmZ1Regs

DCSM_Z1_REGS

0x0005_F000

0x0005_F02F

DcsmZ2Regs

DCSM_Z2_REGS

0x0005_F040

0x0005_F05F

DcsmCommonRegs

DCSM_COMMON_REGS

0x0005_F070

0x0005_F07F

MemCfgRegs

MEM_CFG_REGS

0x0005_F400

0x0005_F47F

AccessProtectionRegs

ACCESS_PROTECTION_REGS

0x0005_F4C0

0x0005_F4FF

MemoryErrorRegs

MEMORY_ERROR_REGS

0x0005_F500

0x0005_F53F

RomWaitStateRegs (1)

ROM_WAIT_STATE_REGS

0x0005_F540

0x0005_F541

Flash0CtrlRegs

FLASH_CTRL_REGS

0x0005_F800

0x0005_FAFF

Flash0EccRegs

FLASH_ECC_REGS

0x0005_FB00

0x0005_FB3F

(1)

Register Name

Only available on CPU1.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

159

Registers

www.ti.com

2.15.2 CPUTIMER_REGS Registers
Table 2-17 lists the memory-mapped registers for the CPUTIMER_REGS. All register offset addresses not
listed in Table 2-17 should be considered as reserved locations and the register contents should not be
modified.
Table 2-17. CPUTIMER_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

TIM

CPU-Timer, Counter Register

Go

2h

PRD

CPU-Timer, Period Register

Go

4h

TCR

CPU-Timer, Control Register

Go

6h

TPR

CPU-Timer, Prescale Register

Go

7h

TPRH

CPU-Timer, Prescale Register High

Go

Complex bit access types are encoded to fit into small table cells. Table 2-18 shows the codes that are
used for access types in this section.
Table 2-18. CPUTIMER_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

W

Write

W1C

1C
W

1 to clear
Write

Read Type
R
Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

160

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.2.1 TIM Register (Offset = 0h) [reset = FFFFh]
TIM is shown in Figure 2-25 and described in Table 2-19.
Return to Summary Table.
CPU-Timer, Counter Register
Figure 2-25. TIM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MSW
R/W-0h

9

8 7 6
LSW
R/W-FFFFh

5

4

3

2

1

0

Table 2-19. TIM Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

MSW

R/W

0h

CPU-Timer Counter Registers
The TIMH register holds the high 16 bits of the current 32-bit count
of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained in
the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

15-0

LSW

R/W

FFFFh

CPU-Timer Counter Registers
The TIM register holds the low 16 bits of the current 32-bit count of
the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained in
the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

161

Registers

www.ti.com

2.15.2.2 PRD Register (Offset = 2h) [reset = 0001FFFFh]
PRD is shown in Figure 2-26 and described in Table 2-20.
Return to Summary Table.
CPU-Timer, Period Register
Figure 2-26. PRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MSW
R/W-1h

9

8 7 6
LSW
R/W-FFFFh

5

4

3

2

1

0

Table 2-20. PRD Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

MSW

R/W

1h

CPU-Timer Period Registers
The PRDH register holds the high 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

15-0

LSW

R/W

FFFFh

CPU-Timer Period Registers
The PRD register holds the low 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

162

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.2.3 TCR Register (Offset = 4h) [reset = 1h]
TCR is shown in Figure 2-27 and described in Table 2-21.
Return to Summary Table.
CPU-Timer, Control Register
Figure 2-27. TCR Register
15
TIF
R/W1C-0h

14
TIE
R/W-0h

13

7

6

5
TRB
R/W-0h

RESERVED
R-0h

12
RESERVED
R-0h
4
TSS
R/W-0h

11
FREE
R/W-0h

10
SOFT
R/W-0h

9

3

2

1

8
RESERVED
R-0h
0

RESERVED
R-1h

Table 2-21. TCR Register Field Descriptions
Bit

Field

Type

Reset

Description

15

TIF

R/W1C

0h

CPU-Timer Overflow Flag.
TIF indicates whether a timer overflow has happened since TIF was
last cleared. TIF is not cleared automatically and does not need to
be cleared to enable the next timer interrupt.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1h (R/W) = This flag gets set when the CPU-timer decrements to
zero.
Writing a 1 to this bit clears the flag.

14

13-12
11

TIE

R/W

0h

CPU-Timer Interrupt Enable.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer interrupt is disabled.
1h (R/W) = The CPU-Timer interrupt is enabled. If the timer
decrements to zero, and TIE is set, the timer asserts its interrupt
request.

RESERVED

R

0h

Reserved

FREE

R/W

0h

If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run. If FREE is 0, then the SOFT bit controls the
emulation behavior.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop)
1h (R/W) = Stop after the TIMH:TIM decrements to 0 (soft stop)
In the SOFT STOP mode, the timer generates an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
2h (R/W) = Free run
3h (R/W) = Free run

10

SOFT

R/W

0h

If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run (that is, free runs). In this case, SOFT is a
don't care. But if FREE is 0, then SOFT takes effect. In this case, if
SOFT = 0, the timer halts the next time the TIMH:TIM decrements. If
the SOFT bit is 1, then the timer halts when the TIMH:TIM
has decremented to zero.
Reset type: SYSRSn

9-6

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

163

Registers

www.ti.com

Table 2-21. TCR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5

TRB

R/W

0h

Timer reload
Reset type: SYSRSn
0h (R/W) = The TRB bit is always read as zero. Writes of 0 are
ignored.
1h (R/W) = When you write a 1 to TRB, the TIMH:TIM is loaded with
the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in
the timer dividedown
register (TDDRH:TDDR).

4

TSS

R/W

0h

CPU-Timer stop status bit.
TSS is a 1-bit flag that stops or starts the CPU-timer.
Reset type: SYSRSn
0h (R/W) = Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is
cleared to 0 and the
CPU-timer immediately starts.
1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.

3-0

164

RESERVED

System Control

R

1h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.2.4 TPR Register (Offset = 6h) [reset = 0h]
TPR is shown in Figure 2-28 and described in Table 2-22.
Return to Summary Table.
CPU-Timer, Prescale Register
Figure 2-28. TPR Register
15

14

13

12

11

10

9

8

3

2

1

0

PSC
R-0h
7

6

5

4
TDDR
R/W-0h

Table 2-22. TPR Register Field Descriptions
Bit

Field

Type

Reset

Description

15-8

PSC

R

0h

CPU-Timer Prescale Counter.
These bits hold the current prescale count for the timer. For every
timer clock source cycle that the PSCH:PSC value is greater than 0,
the PSCH:PSC decrements by one. One timer clock (output of the
timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and
the timer counter register (TIMH:TIM) decrements by one. The
PSCH:PSC is also reloaded whenever the timer reload bit (TRB) is
set by software. The PSCH:PSC can be checked by reading the
register, but it cannot be set directly. It must get its value from the
timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
Reset type: SYSRSn

7-0

TDDR

R/W

0h

CPU-Timer Divide-Down.
Every (TDDRH:TDDR + 1) timer clock source cycles, the timer
counter register (TIMH:TIM) decrements by one. At reset, the
TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC) value
is 0, one timer clock source cycle later, the contents of the
TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC
whenever the timer reload bit (TRB) is set by software.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

165

Registers

www.ti.com

2.15.2.5 TPRH Register (Offset = 7h) [reset = 0h]
TPRH is shown in Figure 2-29 and described in Table 2-23.
Return to Summary Table.
CPU-Timer, Prescale Register High
Figure 2-29. TPRH Register
15

14

13

12

11

10

9

8

3

2

1

0

PSCH
R-0h
7

6

5

4
TDDRH
R/W-0h

Table 2-23. TPRH Register Field Descriptions

166

Bit

Field

Type

Reset

Description

15-8

PSCH

R

0h

See description of TIMERxTPR.
Reset type: SYSRSn

7-0

TDDRH

R/W

0h

See description of TIMERxTPR.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3 PIE_CTRL_REGS Registers
Table 2-24 lists the memory-mapped registers for the PIE_CTRL_REGS. All register offset addresses not
listed in Table 2-24 should be considered as reserved locations and the register contents should not be
modified.
Table 2-24. PIE_CTRL_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

PIECTRL

ePIE Control Register

Go

1h

PIEACK

Interrupt Acknowledge Register

Go

2h

PIEIER1

Interrupt Group 1 Enable Register

Go

3h

PIEIFR1

Interrupt Group 1 Flag Register

Go

4h

PIEIER2

Interrupt Group 2 Enable Register

Go

5h

PIEIFR2

Interrupt Group 2 Flag Register

Go

6h

PIEIER3

Interrupt Group 3 Enable Register

Go

7h

PIEIFR3

Interrupt Group 3 Flag Register

Go

8h

PIEIER4

Interrupt Group 4 Enable Register

Go

9h

PIEIFR4

Interrupt Group 4 Flag Register

Go

Ah

PIEIER5

Interrupt Group 5 Enable Register

Go

Bh

PIEIFR5

Interrupt Group 5 Flag Register

Go

Ch

PIEIER6

Interrupt Group 6 Enable Register

Go

Dh

PIEIFR6

Interrupt Group 6 Flag Register

Go

Eh

PIEIER7

Interrupt Group 7 Enable Register

Go

Fh

PIEIFR7

Interrupt Group 7 Flag Register

Go

10h

PIEIER8

Interrupt Group 8 Enable Register

Go

11h

PIEIFR8

Interrupt Group 8 Flag Register

Go

12h

PIEIER9

Interrupt Group 9 Enable Register

Go

13h

PIEIFR9

Interrupt Group 9 Flag Register

Go

14h

PIEIER10

Interrupt Group 10 Enable Register

Go

15h

PIEIFR10

Interrupt Group 10 Flag Register

Go

16h

PIEIER11

Interrupt Group 11 Enable Register

Go

17h

PIEIFR11

Interrupt Group 11 Flag Register

Go

18h

PIEIER12

Interrupt Group 12 Enable Register

Go

19h

PIEIFR12

Interrupt Group 12 Flag Register

Go

Complex bit access types are encoded to fit into small table cells. Table 2-25 shows the codes that are
used for access types in this section.
Table 2-25. PIE_CTRL_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

167

Registers

www.ti.com

Table 2-25. PIE_CTRL_REGS Access Type
Codes (continued)
Access Type

168

System Control

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.1 PIECTRL Register (Offset = 0h) [reset = 0h]
PIECTRL is shown in Figure 2-30 and described in Table 2-26.
Return to Summary Table.
ePIE Control Register
Figure 2-30. PIECTRL Register
15

14

13

12

11

10

9

8

3

2

1

0
ENPIE
R/W-0h

PIEVECT
R-0h
7

6

5

4
PIEVECT
R-0h

Table 2-26. PIECTRL Register Field Descriptions
Bit
15-1

Field

Type

Reset

Description

PIEVECT

R

0h

These bits indicate the vector address of the vector fetched from the
ePIE vector table. The least significant bit of the address is ignored
and only bits 1 to 15 of the address are shown. The vector value can
be read by the user to determine which interrupt generated the
vector fetch.
Note: When a NMI is serviced, the PIEVECT bit-field does not reflect
the vector as it does for other interrupts.
Reset type: SYSRSn

0

ENPIE

R/W

0h

Enable vector fetching from ePIE block. This bit must be set to 1 for
peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR,
PIEIER) can be accessed even when the ePIE block is disabled.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

169

Registers

www.ti.com

2.15.3.2 PIEACK Register (Offset = 1h) [reset = 0h]
PIEACK is shown in Figure 2-31 and described in Table 2-27.
Return to Summary Table.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is
set. This prevents other interrupts in that group from propagating to the CPU while the first interrupt is
handled. Writing a 1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to
propagate. ISRs for PIE interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.
Figure 2-31. PIEACK Register
15

14

13

12

11
ACK12
R/W=1-0h

10
ACK11
R/W=1-0h

9
ACK10
R/W=1-0h

8
ACK9
R/W=1-0h

5
ACK6
R/W=1-0h

4
ACK5
R/W=1-0h

3
ACK4
R/W=1-0h

2
ACK3
R/W=1-0h

1
ACK2
R/W=1-0h

0
ACK1
R/W=1-0h

RESERVED
R=0-0h
7
ACK8
R/W=1-0h

6
ACK7
R/W=1-0h

Table 2-27. PIEACK Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

11

ACK12

R/W=1

0h

Acknowledge PIE Interrupt Group 12
Reset type: SYSRSn

10

ACK11

R/W=1

0h

Acknowledge PIE Interrupt Group 11
Reset type: SYSRSn

9

ACK10

R/W=1

0h

Acknowledge PIE Interrupt Group 10
Reset type: SYSRSn

8

ACK9

R/W=1

0h

Acknowledge PIE Interrupt Group 9
Reset type: SYSRSn

7

ACK8

R/W=1

0h

Acknowledge PIE Interrupt Group 8
Reset type: SYSRSn

6

ACK7

R/W=1

0h

Acknowledge PIE Interrupt Group 7
Reset type: SYSRSn

5

ACK6

R/W=1

0h

Acknowledge PIE Interrupt Group 6
Reset type: SYSRSn

4

ACK5

R/W=1

0h

Acknowledge PIE Interrupt Group 5
Reset type: SYSRSn

3

ACK4

R/W=1

0h

Acknowledge PIE Interrupt Group 4
Reset type: SYSRSn

2

ACK3

R/W=1

0h

Acknowledge PIE Interrupt Group 3
Reset type: SYSRSn

1

ACK2

R/W=1

0h

Acknowledge PIE Interrupt Group 2
Reset type: SYSRSn

0

ACK1

R/W=1

0h

Acknowledge PIE Interrupt Group 1
Reset type: SYSRSn

15-12

170

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.3 PIEIER1 Register (Offset = 2h) [reset = 0h]
PIEIER1 is shown in Figure 2-32 and described in Table 2-28.
Return to Summary Table.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-32. PIEIER1 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-28. PIEIER1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 1.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 1.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 1.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 1.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 1.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 1.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 1.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 1.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 1.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 1.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 1.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 1.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 1.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 1.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

171

Registers

www.ti.com

Table 2-28. PIEIER1 Register Field Descriptions (continued)

172

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 1.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 1.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.4 PIEIFR1 Register (Offset = 3h) [reset = 0h]
PIEIFR1 is shown in Figure 2-33 and described in Table 2-29.
Return to Summary Table.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-33. PIEIFR1 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-29. PIEIFR1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 1.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 1.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 1.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 1.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 1.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 1.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 1.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 1.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 1.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 1.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 1.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 1.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 1.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

173

Registers

www.ti.com

Table 2-29. PIEIFR1 Register Field Descriptions (continued)

174

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 1.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 1.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 1.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.5 PIEIER2 Register (Offset = 4h) [reset = 0h]
PIEIER2 is shown in Figure 2-34 and described in Table 2-30.
Return to Summary Table.
Interrupt Group 2 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-34. PIEIER2 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-30. PIEIER2 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 2.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 2.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 2.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 2.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 2.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 2.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 2.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 2.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 2.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 2.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 2.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 2.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 2.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 2.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

175

Registers

www.ti.com

Table 2-30. PIEIER2 Register Field Descriptions (continued)

176

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 2.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 2.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.6 PIEIFR2 Register (Offset = 5h) [reset = 0h]
PIEIFR2 is shown in Figure 2-35 and described in Table 2-31.
Return to Summary Table.
Interrupt Group 2 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-35. PIEIFR2 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-31. PIEIFR2 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 2.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 2.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 2.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 2.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 2.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 2.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 2.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 2.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 2.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 2.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 2.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 2.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 2.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

177

Registers

www.ti.com

Table 2-31. PIEIFR2 Register Field Descriptions (continued)

178

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 2.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 2.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 2.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.7 PIEIER3 Register (Offset = 6h) [reset = 0h]
PIEIER3 is shown in Figure 2-36 and described in Table 2-32.
Return to Summary Table.
Interrupt Group 3 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-36. PIEIER3 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-32. PIEIER3 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 3.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 3.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 3.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 3.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 3.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 3.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 3.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 3.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 3.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 3.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 3.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 3.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 3.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 3.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

179

Registers

www.ti.com

Table 2-32. PIEIER3 Register Field Descriptions (continued)

180

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 3.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 3.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.8 PIEIFR3 Register (Offset = 7h) [reset = 0h]
PIEIFR3 is shown in Figure 2-37 and described in Table 2-33.
Return to Summary Table.
Interrupt Group 3 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-37. PIEIFR3 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-33. PIEIFR3 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 3.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 3.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 3.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 3.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 3.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 3.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 3.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 3.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 3.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 3.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 3.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 3.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 3.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

181

Registers

www.ti.com

Table 2-33. PIEIFR3 Register Field Descriptions (continued)

182

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 3.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 3.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 3.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.9 PIEIER4 Register (Offset = 8h) [reset = 0h]
PIEIER4 is shown in Figure 2-38 and described in Table 2-34.
Return to Summary Table.
Interrupt Group 4 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-38. PIEIER4 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-34. PIEIER4 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 4.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 4.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 4.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 4.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 4.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 4.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 4.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 4.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 4.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 4.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 4.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 4.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 4.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 4.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

183

Registers

www.ti.com

Table 2-34. PIEIER4 Register Field Descriptions (continued)

184

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 4.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 4.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.10 PIEIFR4 Register (Offset = 9h) [reset = 0h]
PIEIFR4 is shown in Figure 2-39 and described in Table 2-35.
Return to Summary Table.
Interrupt Group 4 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-39. PIEIFR4 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-35. PIEIFR4 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 4.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 4.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 4.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 4.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 4.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 4.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 4.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 4.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 4.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 4.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 4.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 4.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 4.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

185

Registers

www.ti.com

Table 2-35. PIEIFR4 Register Field Descriptions (continued)

186

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 4.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 4.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 4.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.11 PIEIER5 Register (Offset = Ah) [reset = 0h]
PIEIER5 is shown in Figure 2-40 and described in Table 2-36.
Return to Summary Table.
Interrupt Group 5 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-40. PIEIER5 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-36. PIEIER5 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 5.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 5.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 5.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 5.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 5.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 5.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 5.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 5.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 5.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 5.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 5.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 5.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 5.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 5.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

187

Registers

www.ti.com

Table 2-36. PIEIER5 Register Field Descriptions (continued)

188

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 5.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 5.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.12 PIEIFR5 Register (Offset = Bh) [reset = 0h]
PIEIFR5 is shown in Figure 2-41 and described in Table 2-37.
Return to Summary Table.
Interrupt Group 5 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-41. PIEIFR5 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-37. PIEIFR5 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 5.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 5.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 5.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 5.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 5.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 5.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 5.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 5.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 5.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 5.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 5.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 5.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 5.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

189

Registers

www.ti.com

Table 2-37. PIEIFR5 Register Field Descriptions (continued)

190

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 5.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 5.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 5.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.13 PIEIER6 Register (Offset = Ch) [reset = 0h]
PIEIER6 is shown in Figure 2-42 and described in Table 2-38.
Return to Summary Table.
Interrupt Group 6 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-42. PIEIER6 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-38. PIEIER6 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 6.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 6.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 6.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 6.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 6.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 6.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 6.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 6.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 6.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 6.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 6.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 6.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 6.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 6.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

191

Registers

www.ti.com

Table 2-38. PIEIER6 Register Field Descriptions (continued)

192

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 6.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 6.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.14 PIEIFR6 Register (Offset = Dh) [reset = 0h]
PIEIFR6 is shown in Figure 2-43 and described in Table 2-39.
Return to Summary Table.
Interrupt Group 6 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-43. PIEIFR6 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-39. PIEIFR6 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 6.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 6.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 6.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 6.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 6.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 6.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 6.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 6.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 6.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 6.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 6.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 6.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 6.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

193

Registers

www.ti.com

Table 2-39. PIEIFR6 Register Field Descriptions (continued)

194

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 6.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 6.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 6.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.15 PIEIER7 Register (Offset = Eh) [reset = 0h]
PIEIER7 is shown in Figure 2-44 and described in Table 2-40.
Return to Summary Table.
Interrupt Group 7 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-44. PIEIER7 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-40. PIEIER7 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 7.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 7.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 7.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 7.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 7.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 7.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 7.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 7.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 7.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 7.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 7.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 7.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 7.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 7.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

195

Registers

www.ti.com

Table 2-40. PIEIER7 Register Field Descriptions (continued)

196

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 7.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 7.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.16 PIEIFR7 Register (Offset = Fh) [reset = 0h]
PIEIFR7 is shown in Figure 2-45 and described in Table 2-41.
Return to Summary Table.
Interrupt Group 7 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-45. PIEIFR7 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-41. PIEIFR7 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 7.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 7.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 7.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 7.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 7.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 7.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 7.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 7.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 7.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 7.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 7.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 7.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 7.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

197

Registers

www.ti.com

Table 2-41. PIEIFR7 Register Field Descriptions (continued)

198

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 7.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 7.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 7.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.17 PIEIER8 Register (Offset = 10h) [reset = 0h]
PIEIER8 is shown in Figure 2-46 and described in Table 2-42.
Return to Summary Table.
Interrupt Group 8 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-46. PIEIER8 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-42. PIEIER8 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 8.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 8.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 8.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 8.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 8.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 8.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 8.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 8.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 8.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 8.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 8.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 8.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 8.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 8.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

199

Registers

www.ti.com

Table 2-42. PIEIER8 Register Field Descriptions (continued)

200

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 8.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 8.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.18 PIEIFR8 Register (Offset = 11h) [reset = 0h]
PIEIFR8 is shown in Figure 2-47 and described in Table 2-43.
Return to Summary Table.
Interrupt Group 8 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-47. PIEIFR8 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-43. PIEIFR8 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 8.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 8.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 8.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 8.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 8.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 8.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 8.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 8.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 8.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 8.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 8.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 8.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 8.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

201

Registers

www.ti.com

Table 2-43. PIEIFR8 Register Field Descriptions (continued)

202

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 8.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 8.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 8.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.19 PIEIER9 Register (Offset = 12h) [reset = 0h]
PIEIER9 is shown in Figure 2-48 and described in Table 2-44.
Return to Summary Table.
Interrupt Group 9 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-48. PIEIER9 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-44. PIEIER9 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 9.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 9.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 9.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 9.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 9.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 9.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 9.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 9.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 9.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 9.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 9.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 9.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 9.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 9.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

203

Registers

www.ti.com

Table 2-44. PIEIER9 Register Field Descriptions (continued)

204

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 9.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 9.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.20 PIEIFR9 Register (Offset = 13h) [reset = 0h]
PIEIFR9 is shown in Figure 2-49 and described in Table 2-45.
Return to Summary Table.
Interrupt Group 9 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-49. PIEIFR9 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-45. PIEIFR9 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 9.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 9.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 9.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 9.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 9.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 9.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 9.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 9.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 9.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 9.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 9.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 9.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 9.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

205

Registers

www.ti.com

Table 2-45. PIEIFR9 Register Field Descriptions (continued)

206

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 9.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 9.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 9.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.21 PIEIER10 Register (Offset = 14h) [reset = 0h]
PIEIER10 is shown in Figure 2-50 and described in Table 2-46.
Return to Summary Table.
Interrupt Group 10 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-50. PIEIER10 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-46. PIEIER10 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 10.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 10.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 10.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 10.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 10.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 10.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 10.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 10.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 10.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 10.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 10.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 10.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 10.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 10.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

207

Registers

www.ti.com

Table 2-46. PIEIER10 Register Field Descriptions (continued)

208

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 10.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 10.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.22 PIEIFR10 Register (Offset = 15h) [reset = 0h]
PIEIFR10 is shown in Figure 2-51 and described in Table 2-47.
Return to Summary Table.
Interrupt Group 10 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-51. PIEIFR10 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-47. PIEIFR10 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 10.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 10.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 10.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 10.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 10.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 10.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 10.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 10.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 10.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 10.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 10.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 10.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 10.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

209

Registers

www.ti.com

Table 2-47. PIEIFR10 Register Field Descriptions (continued)

210

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 10.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 10.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 10.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.23 PIEIER11 Register (Offset = 16h) [reset = 0h]
PIEIER11 is shown in Figure 2-52 and described in Table 2-48.
Return to Summary Table.
Interrupt Group 11 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-52. PIEIER11 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-48. PIEIER11 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 11.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 11.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 11.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 11.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 11.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 11.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 11.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 11.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 11.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 11.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 11.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 11.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 11.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 11.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

211

Registers

www.ti.com

Table 2-48. PIEIER11 Register Field Descriptions (continued)

212

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 11.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 11.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.24 PIEIFR11 Register (Offset = 17h) [reset = 0h]
PIEIFR11 is shown in Figure 2-53 and described in Table 2-49.
Return to Summary Table.
Interrupt Group 11 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-53. PIEIFR11 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-49. PIEIFR11 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 11.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 11.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 11.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 11.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 11.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 11.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 11.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 11.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 11.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 11.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 11.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 11.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 11.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

213

Registers

www.ti.com

Table 2-49. PIEIFR11 Register Field Descriptions (continued)

214

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 11.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 11.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 11.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.25 PIEIER12 Register (Offset = 18h) [reset = 0h]
PIEIER12 is shown in Figure 2-54 and described in Table 2-50.
Return to Summary Table.
Interrupt Group 12 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-54. PIEIER12 Register
15
INTx16
R/W-0h

14
INTx15
R/W-0h

13
INTx14
R/W-0h

12
INTx13
R/W-0h

11
INTx12
R/W-0h

10
INTx11
R/W-0h

9
INTx10
R/W-0h

8
INTx9
R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-50. PIEIER12 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Enable for Interrupt 12.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Enable for Interrupt 12.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Enable for Interrupt 12.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Enable for Interrupt 12.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Enable for Interrupt 12.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Enable for Interrupt 12.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Enable for Interrupt 12.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Enable for Interrupt 12.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Enable for Interrupt 12.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Enable for Interrupt 12.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Enable for Interrupt 12.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Enable for Interrupt 12.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Enable for Interrupt 12.4
Reset type: SYSRSn

2

INTx3

R/W

0h

Enable for Interrupt 12.3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

215

Registers

www.ti.com

Table 2-50. PIEIER12 Register Field Descriptions (continued)

216

Bit

Field

Type

Reset

Description

1

INTx2

R/W

0h

Enable for Interrupt 12.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Enable for Interrupt 12.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.3.26 PIEIFR12 Register (Offset = 19h) [reset = 0h]
PIEIFR12 is shown in Figure 2-55 and described in Table 2-51.
Return to Summary Table.
Interrupt Group 12 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-55. PIEIFR12 Register
15
INTx16

14
INTx15

13
INTx14

12
INTx13

11
INTx12

10
INTx11

9
INTx10

8
INTx9

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

7
INTx8
R/W-0h

6
INTx7
R/W-0h

5
INTx6
R/W-0h

4
INTx5
R/W-0h

3
INTx4
R/W-0h

2
INTx3
R/W-0h

1
INTx2
R/W-0h

0
INTx1
R/W-0h

Table 2-51. PIEIFR12 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

INTx16

R/W

0h

Flag for Interrupt 12.16
Reset type: SYSRSn

14

INTx15

R/W

0h

Flag for Interrupt 12.15
Reset type: SYSRSn

13

INTx14

R/W

0h

Flag for Interrupt 12.14
Reset type: SYSRSn

12

INTx13

R/W

0h

Flag for Interrupt 12.13
Reset type: SYSRSn

11

INTx12

R/W

0h

Flag for Interrupt 12.12
Reset type: SYSRSn

10

INTx11

R/W

0h

Flag for Interrupt 12.11
Reset type: SYSRSn

9

INTx10

R/W

0h

Flag for Interrupt 12.10
Reset type: SYSRSn

8

INTx9

R/W

0h

Flag for Interrupt 12.9
Reset type: SYSRSn

7

INTx8

R/W

0h

Flag for Interrupt 12.8
Reset type: SYSRSn

6

INTx7

R/W

0h

Flag for Interrupt 12.7
Reset type: SYSRSn

5

INTx6

R/W

0h

Flag for Interrupt 12.6
Reset type: SYSRSn

4

INTx5

R/W

0h

Flag for Interrupt 12.5
Reset type: SYSRSn

3

INTx4

R/W

0h

Flag for Interrupt 12.4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

217

Registers

www.ti.com

Table 2-51. PIEIFR12 Register Field Descriptions (continued)

218

Bit

Field

Type

Reset

Description

2

INTx3

R/W

0h

Flag for Interrupt 12.3
Reset type: SYSRSn

1

INTx2

R/W

0h

Flag for Interrupt 12.2
Reset type: SYSRSn

0

INTx1

R/W

0h

Flag for Interrupt 12.1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.4 WD_REGS Registers
Table 2-52 lists the memory-mapped registers for the WD_REGS. All register offset addresses not listed
in Table 2-52 should be considered as reserved locations and the register contents should not be
modified.
Table 2-52. WD_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

22h

SCSR

System Control & Status Register

EALLOW

Go

23h

WDCNTR

Watchdog Counter Register

EALLOW

Go

25h

WDKEY

Watchdog Reset Key Register

EALLOW

Go

29h

WDCR

Watchdog Control Register

EALLOW

Go

2Ah

WDWCR

Watchdog Windowed Control Register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 2-53 shows the codes that are
used for access types in this section.
Table 2-53. WD_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W1C

1C
W

1 to clear
Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

219

Registers

www.ti.com

2.15.4.1 SCSR Register (Offset = 22h) [reset = 5h]
SCSR is shown in Figure 2-56 and described in Table 2-54.
Return to Summary Table.
It is recommended to only use 16 bit accesses to write to this register. Use a read-modify-write instruction
may inadvertently clear other bits.
Figure 2-56. SCSR Register
15

14

13

12

11

10

9

8

3

2
WDINTS
R-1h

1
WDENINT
R/W-0h

0
WDOVERRIDE
R/W1C-1h

RESERVED
R=0-0h
7

6

5
RESERVED
R=0-0h

4

Table 2-54. SCSR Register Field Descriptions
Bit
15-3
2

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

WDINTS

R

1h

Watchdog interrupt (WDINTn) status signal. This is a read only bit
reflecting the current state of the WDINTn signal from the watchdog
block (after synchronization with SYSCLKOUT). If this bit is 1, the
watchdog interrupt is not active. If this bit is 0, then the watchdog
interrupt is active.
Note: ,If the WDINTn signal is used to wake up from IDLE or
STANDBY condition, then the user should make sure that the
WDINTn signal goes back high again before attempting to go back
into IDLE or STANDBY mode. Reading this bit will tell the user the
current state of this signal.
Reset type: SYSRSn

220

1

WDENINT

R/W

0h

If this bit is set to 1, the watchdog reset (WDRSTn) output signal is
disabled and the watchdog interrupt (WDINTn) output signal is
enabled. If this bit is zero, then the WDRSTn output signal is
enabled and the WDINTn output signal is disabled. This is the
default state on system reset (SYSRSn).
Reset type: SYSRSn

0

WDOVERRIDE

R/W1C

1h

If this bit is set to 1, the user is allowed to change the state of the
Watchdog disable (WDDIS) bit in the Watchdog Control (WDCR)
register. If the WDOVERRIDE bit is cleared, by writing a 1 the
WDDIS bit cannot be modified by the user. Writing a 0 will have no
effect. If this bit is cleared, then it will remain in this state until a reset
occurs. The current state of this bit is readable by the user.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.4.2 WDCNTR Register (Offset = 23h) [reset = 0h]
WDCNTR is shown in Figure 2-57 and described in Table 2-55.
Return to Summary Table.
Watchdog Counter Register
Figure 2-57. WDCNTR Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R=0-0h
7

6

5

4
WDCNTR
R-0h

Table 2-55. WDCNTR Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7-0

WDCNTR

R

0h

These bits contain the current value of the WD counter. The 8-bit
counter continually increments at the WDCLK rate. If the counter
overflows, then a watchdog output pulse (WDOUTn) is generated. If
the WDKEY register is written with a valid combination, then the
counter is reset to zero.
Reset type: IORSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

221

Registers

www.ti.com

2.15.4.3 WDKEY Register (Offset = 25h) [reset = 0h]
WDKEY is shown in Figure 2-58 and described in Table 2-56.
Return to Summary Table.
Watchdog Reset Key Register
Figure 2-58. WDKEY Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R=0-0h
7

6

5

4
WDKEY
R/W-0h

Table 2-56. WDKEY Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7-0

WDKEY

R/W

0h

Writing 0x55 followed by 0xAA will cause the WDCNTR bits to be
cleared.
Note:
[1] Reads from the WDKEY return the value of WDCR register.
Reset type: IORSn

222

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.4.4 WDCR Register (Offset = 29h) [reset = 0h]
WDCR is shown in Figure 2-59 and described in Table 2-57.
Return to Summary Table.
Watchdog Control Register
Figure 2-59. WDCR Register
15

14

13

12

11

10

9

8

3

2

1
WDPS
R/W-0h

0

RESERVED
R=0-0h
7
RESERVED
R-0h

6
WDDIS
R/W-0h

5

4
WDCHK
R=0/W-0h

Table 2-57. WDCR Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

WDDIS

R/W

0h

Writing a 1 to this bit will disable the watchdog module. Writing a 0
will enable the module. This bit can only be modified if the
WDOVERRIDE bit in the SCSR2 register is set to 1. On reset, the
watchdog module is enabled.
Reset type: IORSn

5-3

WDCHK

R=0/W

0h

The user must ALWAYS write 1,0,1 to these bits whenever a write to
this register is performed. Writing any other value will cause an
immediate reset to the core (if WD enabled).
Reset type: IORSn

2-0

WDPS

R/W

0h

These bits configure the watchdog counter clock (WDCLK) rate
relative to INTOSC1/512:
000 WDCLK = INTOSC1/512/1
001 WDCLK = INTOSC1/512/1
010 WDCLK = INTOSC1/512/2
011 WDCLK = INTOSC1/512/4
100 WDCLK = INTOSC1/512/8
101 WDCLK = INTOSC1/512/16
110 WDCLK = INTOSC1/512/32
111 WDCLK = INTOSC1/512/64
Reset type: IORSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

223

Registers

www.ti.com

2.15.4.5 WDWCR Register (Offset = 2Ah) [reset = 0h]
WDWCR is shown in Figure 2-60 and described in Table 2-58.
Return to Summary Table.
Watchdog Windowed Control Register
Figure 2-60. WDWCR Register
15

14

13

12
RESERVED
R=0-0h

11

10

9

8
FIRSTKEY
R-0h

7

6

5

4

3

2

1

0

MIN
R/W-0h

Table 2-58. WDWCR Register Field Descriptions
Bit
15-9
8

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

FIRSTKEY

R

0h

This bit indicates if the 1st valid WDKEY (0x55 + 0xAA) got detected
after MIN was configured to a non-zero value
0: First Valid Key after non-zero MIN configuration has not happened
yet
1: First Valid key after non-zero MIN configuration got detected
Notes:
[1] If MIN = 0, this bit is never set
[2] If MIN is changed back to 0x0 from a non-zero value, this bit is
auto-cleared
[3] This bit is added for debug purposes only
Reset type: IORSn

7-0

224

MIN

System Control

R/W

0h

These bits define the lower limt of the Windowed functionality
Reset type: IORSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.5 NMI_INTRUPT_REGS Registers
Table 2-59 lists the memory-mapped registers for the NMI_INTRUPT_REGS. All register offset addresses
not listed in Table 2-59 should be considered as reserved locations and the register contents should not
be modified.
Table 2-59. NMI_INTRUPT_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

NMICFG

NMI Configuration Register

EALLOW

1h

NMIFLG

NMI Flag Register (XRSn Clear)

2h

NMIFLGCLR

NMI Flag Clear Register

EALLOW

Go

3h

NMIFLGFRC

NMI Flag Force Register

EALLOW

Go

4h

NMIWDCNT

NMI Watchdog Counter Register

5h

NMIWDPRD

NMI Watchdog Period Register

6h

NMISHDFLG

NMI Shadow Flag Register

Go
Go

Go
EALLOW

Go
Go

Complex bit access types are encoded to fit into small table cells. Table 2-60 shows the codes that are
used for access types in this section.
Table 2-60. NMI_INTRUPT_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

225

Registers

www.ti.com

2.15.5.1 NMICFG Register (Offset = 0h) [reset = 0h]
NMICFG is shown in Figure 2-61 and described in Table 2-61.
Return to Summary Table.
NMI Configuration Register
Figure 2-61. NMICFG Register
15

14

13

12

11

10

9

8

3

2

1

0
NMIE
R/W=1-0h

RESERVED
R=0-0h
7

6

5

4
RESERVED
R=0-0h

Table 2-61. NMICFG Register Field Descriptions
Bit
15-1
0

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

NMIE

R/W=1

0h

When set to 1 any condition will generate an NMI interrupt to the
C28 CPU and kick off the NMI watchdog counter. As part of boot
sequence this bit should be set after the device security related
initialization is complete.
0 NMI disabled
1 NMI enabled
Reset type: SYSRSn

226

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.5.2 NMIFLG Register (Offset = 1h) [reset = 0h]
NMIFLG is shown in Figure 2-62 and described in Table 2-62.
Return to Summary Table.
NMI Flag Register (XRSn Clear)
Figure 2-62. NMIFLG Register
15

14

13
RESERVED

11
RESERVED

R=0-0h
7
RESERVED

6
PIEVECTERR

R-0h

R-0h

12

5
CPU2HWBIST
ERR
R-0h

4
CPU1HWBIST
ERR
R-0h

9
CPU2WDRSn

8
RESERVED

R-0h

10
CPU2NMIWDR
Sn
R-0h

R-0h

R-0h

3
FLUNCERR

2
RAMUNCERR

1
CLOCKFAIL

0
NMIINT

R-0h

R-0h

R-0h

R-0h

Table 2-62. NMIFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

15-12

RESERVED

R=0

0h

Reserved

11

RESERVED

R

0h

Reserved

10

CPU2NMIWDRSn

R

0h

CPU2 NMIWDRSn Reset Indication Flag: This bits indicates if
CPU2s NMIWDRSn was fired or not.
0 No CPU2.NMIWDRsn was fired
1 CPU2.NMIWDRSn was fired to CPU2
Note:
[1] This bits is reserved for CPU2.NMIFLG register
Reset type: XRSn

9

CPU2WDRSn

R

0h

CPU2 WDRSn Reset Indication Flag: This bits indicates if CPU2s
WDRSn was fired or not.
0 No CPU2.WDRsn was fired
1 CPU2.WDRSn was fired to CPU2
Note:
[1] This bits is reserved for CPU2.NMIFLG register
Reset type: XRSn

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

PIEVECTERR

R

0h

PIE Vector Fetch Error Flag: This bit indicates if an error occurred on
an Vector Fect by the other CPU in the device. For example,
CPU1.NMIWD gets an NMI on an Vector fetch Error on CPU2. This
bit can only be cleared by the user writing to the corresponding clear
bit in the NMIFLGCLR register or by an XRSn reset:
0,No Vector Fetch Error condition (on the other CPU) pending
1,Vector Fetch error condition (on the other CPU) generated
Reset type: XRSn

5

CPU2HWBISTERR

R

0h

HW BIST Error NMI Flag: This bit indicates if the time out error or a
signature mismatch error condition during hardware BIST of C28
CPU2 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

227

Registers

www.ti.com

Table 2-62. NMIFLG Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

CPU1HWBISTERR

R

0h

HW BIST Error NMI Flag: This bit indicates if the time out error or a
signature mismatch error condition during hardware BIST of C28
CPU1 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: XRSn

3

FLUNCERR

R

0h

Flash Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a C28 Flash access and that
condition is latched. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 Flash uncorrectable error condition pending
1,C28 Flash uncorrectable error condition generated
Reset type: XRSn

2

RAMUNCERR

R

0h

RAM Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a RAM access (by any master) and
that condition is latched. This bit can only be cleared by the user
writing to the corresponding clear bit in the NMIFLGCLR register or
by an XRSn reset:
0,No RAM uncorrectable error condition pending
1,RAM uncorrectable error condition generated
Reset type: XRSn

1

CLOCKFAIL

R

0h

Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL
condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by an
XRSn reset:
0,No CLOCKFAIL Condition Pending
1,CLOCKFAIL Condition Generated
Reset type: XRSn

0

NMIINT

R

0h

NMI Interrupt Flag: This bit indicates if an NMI interrupt was
generated. This bit can only be cleared by the user writing to the
respective bit in the NMIFLGCLR register or by an XRSn reset:
0 No NMI Interrupt Generated
1 NMI Interrupt Generated
No further NMI interrupts pulses are generated until this flag is
cleared by the user.
Reset type: XRSn

228

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.5.3 NMIFLGCLR Register (Offset = 2h) [reset = 0h]
NMIFLGCLR is shown in Figure 2-63 and described in Table 2-63.
Return to Summary Table.
NMI Flag Clear Register
Figure 2-63. NMIFLGCLR Register
15

14

13
RESERVED

11
OVF

R=0-0h
7
RESERVED

6
PIEVECTERR

R-0h

R=0/W=1-0h

12

5
CPU2HWBIST
ERR
R=0/W=1-0h

4
CPU1HWBIST
ERR
R=0/W=1-0h

9
CPU2WDRSn

8
RESERVED

R=0/W=1-0h

10
CPU2NMIWDR
Sn
R=0/W=1-0h

R=0/W=1-0h

R-0h

3
FLUNCERR

2
RAMUNCERR

1
CLOCKFAIL

0
NMIINT

R=0/W=1-0h

R=0/W=1-0h

R=0/W=1-0h

R=0/W=1-0h

Table 2-63. NMIFLGCLR Register Field Descriptions
Bit
15-12
11

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

OVF

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

10

CPU2NMIWDRSn

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

9

CPU2WDRSn

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
[3] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

229

Registers

www.ti.com

Table 2-63. NMIFLGCLR Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

PIEVECTERR

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

5

CPU2HWBISTERR

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

4

CPU1HWBISTERR

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

3

FLUNCERR

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

2

RAMUNCERR

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

1

CLOCKFAIL

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

230

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-63. NMIFLGCLR Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

NMIINT

R=0/W=1

0h

Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

231

Registers

www.ti.com

2.15.5.4 NMIFLGFRC Register (Offset = 3h) [reset = 0h]
NMIFLGFRC is shown in Figure 2-64 and described in Table 2-64.
Return to Summary Table.
NMI Flag Force Register
Figure 2-64. NMIFLGFRC Register
15

14

13
RESERVED

11
OVF

R=0-0h
7
RESERVED

6
PIEVECTERR

R-0h

R=0/W=1-0h

12

5
CPU2HWBIST
ERR
R=0/W=1-0h

4
CPU1HWBIST
ERR
R=0/W=1-0h

9
CPU2WDRSn

8
RESERVED

R=0/W=1-0h

10
CPU2NMIWDR
Sn
R=0/W=1-0h

R=0/W=1-0h

R-0h

3
FLUNCERR

2
RAMUNCERR

1
CLOCKFAIL

0
RESERVED

R=0/W=1-0h

R=0/W=1-0h

R=0/W=1-0h

R=0-0h

Table 2-64. NMIFLGFRC Register Field Descriptions
Bit
15-12

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

11

OVF

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

10

CPU2NMIWDRSn

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Note:
[1] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn

9

CPU2WDRSn

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Note:
[1] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn

232

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

PIEVECTERR

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

5

CPU2HWBISTERR

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-64. NMIFLGFRC Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4

CPU1HWBISTERR

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

3

FLUNCERR

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

2

RAMUNCERR

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

1

CLOCKFAIL

R=0/W=1

0h

Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

0

RESERVED

R=0

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

233

Registers

www.ti.com

2.15.5.5 NMIWDCNT Register (Offset = 4h) [reset = 0h]
NMIWDCNT is shown in Figure 2-65 and described in Table 2-65.
Return to Summary Table.
NMI Watchdog Counter Register
Figure 2-65. NMIWDCNT Register
15

14

13

12

11

10

9

8
7
NMIWDCNT
R-0h

6

5

4

3

2

1

0

Table 2-65. NMIWDCNT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

NMIWDCNT

R

0h

NMI Watchdog Counter: This 16-bit incremental counter will start
incrementing whenever any one of the enabled FAIL flags are set. If
the counter reaches the period value, an NMIRSn signal is fired
which will then resets the system. The counter will reset to zero
when it reaches the period value and will then restart counting if any
of the enabled FAIL flags are set.
If no enabled FAIL flag is set, then the counter will reset to zero and
remain at zero until an enabled FAIL flag is set.
Normally, the software would respond to the NMI interrupt generated
and clear the offending FLAG(s) before the NMI watchdog triggers a
reset. In some situations, the software may decide to allow the
watchdog to reset the device anyway.
The counter is clocked at the SYSCLKOUT rate.
Reset type: SYSRSn

234

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.5.6 NMIWDPRD Register (Offset = 5h) [reset = FFFFh]
NMIWDPRD is shown in Figure 2-66 and described in Table 2-66.
Return to Summary Table.
NMI Watchdog Period Register
Figure 2-66. NMIWDPRD Register
15

14

13

12

11

10

9

8
7
NMIWDPRD
R/W-FFFFh

6

5

4

3

2

1

0

Table 2-66. NMIWDPRD Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

NMIWDPRD

R/W

FFFFh

NMI Watchdog Period: This 16-bit value contains the period value at
which a reset is generated when the watchdog counter matches. At
reset this value is set at the maximum. The software can decrease
the period value at initialization time.
Writing a PERIOD value that is smaller then the current counter
value will automatically force an NMIRSn and hence reset the
watchdog counter.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

235

Registers

www.ti.com

2.15.5.7 NMISHDFLG Register (Offset = 6h) [reset = 0h]
NMISHDFLG is shown in Figure 2-67 and described in Table 2-67.
Return to Summary Table.
NMI Shadow Flag Register
Figure 2-67. NMISHDFLG Register
15

14

13
RESERVED

11
OVF

R=0-0h
7
RESERVED

6
PIEVECTERR

R-0h

R-0h

12

5
CPU2HWBIST
ERR
R-0h

4
CPU1HWBIST
ERR
R-0h

9
CPU2WDRSn

8
RESERVED

R-0h

10
CPU2NMIWDR
Sn
R-0h

R-0h

R-0h

3
FLUNCERR

2
RAMUNCERR

1
CLOCKFAIL

0
RESERVED

R-0h

R-0h

R-0h

R=0-0h

Table 2-67. NMISHDFLG Register Field Descriptions
Bit
15-12
11

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

OVF

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn

10

CPU2NMIWDRSn

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn

9

CPU2WDRSn

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: PORn

236

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-67. NMISHDFLG Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

PIEVECTERR

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn

5

CPU2HWBISTERR

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn

4

CPU1HWBISTERR

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn

3

FLUNCERR

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn

2

RAMUNCERR

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn

1

CLOCKFAIL

R

0h

Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn

0

RESERVED

R=0

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

237

Registers

www.ti.com

2.15.6 XINT_REGS Registers
Table 2-68 lists the memory-mapped registers for the XINT_REGS. All register offset addresses not listed
in Table 2-68 should be considered as reserved locations and the register contents should not be
modified.
Table 2-68. XINT_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

XINT1CR

XINT1 configuration register

Go

1h

XINT2CR

XINT2 configuration register

Go

2h

XINT3CR

XINT3 configuration register

Go

3h

XINT4CR

XINT4 configuration register

Go

4h

XINT5CR

XINT5 configuration register

Go

8h

XINT1CTR

XINT1 counter register

Go

9h

XINT2CTR

XINT2 counter register

Go

Ah

XINT3CTR

XINT3 counter register

Go

Complex bit access types are encoded to fit into small table cells. Table 2-69 shows the codes that are
used for access types in this section.
Table 2-69. XINT_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

Write

Read Type

Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

238

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.6.1 XINT1CR Register (Offset = 0h) [reset = 0h]
XINT1CR is shown in Figure 2-68 and described in Table 2-70.
Return to Summary Table.
XINT1 configuration register
Figure 2-68. XINT1CR Register
15

14

13

12

11

10

9

8

2

1
RESERVED
R=0-0h

0
ENABLE
R/W-0h

RESERVED
R=0-0h
7

6

5

4

3

RESERVED
R=0-0h

POLARITY
R/W-0h

Table 2-70. XINT1CR Register Field Descriptions
Field

Type

Reset

Description

15-4

Bit

RESERVED

R=0

0h

Reserved

3-2

POLARITY

R/W

0h

00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn

1

RESERVED

R=0

0h

Reserved

0

ENABLE

R/W

0h

0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

239

Registers

www.ti.com

2.15.6.2 XINT2CR Register (Offset = 1h) [reset = 0h]
XINT2CR is shown in Figure 2-69 and described in Table 2-71.
Return to Summary Table.
XINT2 configuration register
Figure 2-69. XINT2CR Register
15

14

13

12

11

10

9

8

2

1
RESERVED
R=0-0h

0
ENABLE
R/W-0h

RESERVED
R=0-0h
7

6

5

4

3

RESERVED
R=0-0h

POLARITY
R/W-0h

Table 2-71. XINT2CR Register Field Descriptions
Field

Type

Reset

Description

15-4

Bit

RESERVED

R=0

0h

Reserved

3-2

POLARITY

R/W

0h

00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn

1

RESERVED

R=0

0h

Reserved

0

ENABLE

R/W

0h

0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

240

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.6.3 XINT3CR Register (Offset = 2h) [reset = 0h]
XINT3CR is shown in Figure 2-70 and described in Table 2-72.
Return to Summary Table.
XINT3 configuration register
Figure 2-70. XINT3CR Register
15

14

13

12

11

10

9

8

2

1
RESERVED
R=0-0h

0
ENABLE
R/W-0h

RESERVED
R=0-0h
7

6

5

4

3

RESERVED
R=0-0h

POLARITY
R/W-0h

Table 2-72. XINT3CR Register Field Descriptions
Field

Type

Reset

Description

15-4

Bit

RESERVED

R=0

0h

Reserved

3-2

POLARITY

R/W

0h

00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn

1

RESERVED

R=0

0h

Reserved

0

ENABLE

R/W

0h

0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

241

Registers

www.ti.com

2.15.6.4 XINT4CR Register (Offset = 3h) [reset = 0h]
XINT4CR is shown in Figure 2-71 and described in Table 2-73.
Return to Summary Table.
XINT4 configuration register
Figure 2-71. XINT4CR Register
15

14

13

12

11

10

9

8

2

1
RESERVED
R=0-0h

0
ENABLE
R/W-0h

RESERVED
R=0-0h
7

6

5

4

3

RESERVED
R=0-0h

POLARITY
R/W-0h

Table 2-73. XINT4CR Register Field Descriptions
Field

Type

Reset

Description

15-4

Bit

RESERVED

R=0

0h

Reserved

3-2

POLARITY

R/W

0h

00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn

1

RESERVED

R=0

0h

Reserved

0

ENABLE

R/W

0h

0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

242

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.6.5 XINT5CR Register (Offset = 4h) [reset = 0h]
XINT5CR is shown in Figure 2-72 and described in Table 2-74.
Return to Summary Table.
XINT5 configuration register
Figure 2-72. XINT5CR Register
15

14

13

12

11

10

9

8

2

1
RESERVED
R=0-0h

0
ENABLE
R/W-0h

RESERVED
R=0-0h
7

6

5

4

3

RESERVED
R=0-0h

POLARITY
R/W-0h

Table 2-74. XINT5CR Register Field Descriptions
Field

Type

Reset

Description

15-4

Bit

RESERVED

R=0

0h

Reserved

3-2

POLARITY

R/W

0h

00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn

1

RESERVED

R=0

0h

Reserved

0

ENABLE

R/W

0h

0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

243

Registers

www.ti.com

2.15.6.6 XINT1CTR Register (Offset = 8h) [reset = 0h]
XINT1CTR is shown in Figure 2-73 and described in Table 2-75.
Return to Summary Table.
XINT1 counter register
Figure 2-73. XINT1CTR Register
15

14

13

12

11

10

9

8
7
INTCTR
R-0h

6

5

4

3

2

1

0

Table 2-75. XINT1CTR Register Field Descriptions
Bit
15-0

244

Field

Type

Reset

Description

INTCTR

R

0h

This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until the
next valid interrupt edge is detected. The counter must only be reset
by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.6.7 XINT2CTR Register (Offset = 9h) [reset = 0h]
XINT2CTR is shown in Figure 2-74 and described in Table 2-76.
Return to Summary Table.
XINT2 counter register
Figure 2-74. XINT2CTR Register
15

14

13

12

11

10

9

8
7
INTCTR
R-0h

6

5

4

3

2

1

0

Table 2-76. XINT2CTR Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

INTCTR

R

0h

This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until the
next valid interrupt edge is detected. The counter must only be reset
by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

245

Registers

www.ti.com

2.15.6.8 XINT3CTR Register (Offset = Ah) [reset = 0h]
XINT3CTR is shown in Figure 2-75 and described in Table 2-77.
Return to Summary Table.
XINT3 counter register
Figure 2-75. XINT3CTR Register
15

14

13

12

11

10

9

8
7
INTCTR
R-0h

6

5

4

3

2

1

0

Table 2-77. XINT3CTR Register Field Descriptions
Bit
15-0

246

Field

Type

Reset

Description

INTCTR

R

0h

This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until the
next valid interrupt edge is detected. The counter must only be reset
by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.7 DMA_CLA_SRC_SEL_REGS Registers
Table 2-78 lists the memory-mapped registers for the DMA_CLA_SRC_SEL_REGS. All register offset
addresses not listed in Table 2-78 should be considered as reserved locations and the register contents
should not be modified.
Table 2-78. DMA_CLA_SRC_SEL_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

CLA1TASKSRCSELLOCK

CLA1 Task Trigger Source Select Lock Register

EALLOW

Go

4h

DMACHSRCSELLOCK

DMA Channel Triger Source Select Lock
Register

EALLOW

Go

6h

CLA1TASKSRCSEL1

CLA1 Task Trigger Source Select Register-1

EALLOW

Go

8h

CLA1TASKSRCSEL2

CLA1 Task Trigger Source Select Register-2

EALLOW

Go

16h

DMACHSRCSEL1

DMA Channel Trigger Source Select Register-1

EALLOW

Go

18h

DMACHSRCSEL2

DMA Channel Trigger Source Select Register-2

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 2-79 shows the codes that are
used for access types in this section.
Table 2-79. DMA_CLA_SRC_SEL_REGS Access Type
Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

247

Registers

www.ti.com

2.15.7.1 CLA1TASKSRCSELLOCK Register (Offset = 0h) [reset = 0h]
CLA1TASKSRCSELLOCK is shown in Figure 2-76 and described in Table 2-80.
Return to Summary Table.
CLA1 Task Trigger Source Select Lock Register
Figure 2-76. CLA1TASKSRCSELLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
CLA1TASKSR
CSEL2
R/WSOnce-0h

0
CLA1TASKSR
CSEL1
R/WSOnce-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-80. CLA1TASKSRCSELLOCK Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

CLA1TASKSRCSEL2

R/WSOnce

0h

CLA1TASKSRCSEL2 Register Lock bit:

1

0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0

CLA1TASKSRCSEL1

R/WSOnce

0h

CLA1TASKSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

248

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.7.2 DMACHSRCSELLOCK Register (Offset = 4h) [reset = 0h]
DMACHSRCSELLOCK is shown in Figure 2-77 and described in Table 2-81.
Return to Summary Table.
DMA Channel Triger Source Select Lock Register
Figure 2-77. DMACHSRCSELLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

1
0
DMACHSRCSE DMACHSRCSE
L2
L1
R/WSOnce-0h R/WSOnce-0h

Table 2-81. DMACHSRCSELLOCK Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

DMACHSRCSEL2

R/WSOnce

0h

DMACHSRCSEL2 Register Lock bit:

1

0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0

DMACHSRCSEL1

R/WSOnce

0h

DMACHSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

249

Registers

www.ti.com

2.15.7.3 CLA1TASKSRCSEL1 Register (Offset = 6h) [reset = 0h]
CLA1TASKSRCSEL1 is shown in Figure 2-78 and described in Table 2-82.
Return to Summary Table.
CLA1 Task Trigger Source Select Register-1
Figure 2-78. CLA1TASKSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TASK4
TASK3
TASK2
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5

4 3 2
TASK1
R/W-0h

1

0

Table 2-82. CLA1TASKSRCSEL1 Register Field Descriptions
Bit

250

Field

Type

Reset

Description

31-24

TASK4

R/W

0h

Selects the Trigger Source for TASK4 of CLA1
Reset type: SYSRSn

23-16

TASK3

R/W

0h

Selects the Trigger Source for TASK3 of CLA1
Reset type: SYSRSn

15-8

TASK2

R/W

0h

Selects the Trigger Source for TASK2 of CLA1
Reset type: SYSRSn

7-0

TASK1

R/W

0h

Selects the Trigger Source for TASK1 of CLA1
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.7.4 CLA1TASKSRCSEL2 Register (Offset = 8h) [reset = 0h]
CLA1TASKSRCSEL2 is shown in Figure 2-79 and described in Table 2-83.
Return to Summary Table.
CLA1 Task Trigger Source Select Register-2
Figure 2-79. CLA1TASKSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TASK8
TASK7
TASK6
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5

4 3 2
TASK5
R/W-0h

1

0

Table 2-83. CLA1TASKSRCSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

TASK8

R/W

0h

Selects the Trigger Source for TASK8 of CLA1
Reset type: SYSRSn

23-16

TASK7

R/W

0h

Selects the Trigger Source for TASK7 of CLA1
Reset type: SYSRSn

15-8

TASK6

R/W

0h

Selects the Trigger Source for TASK6 of CLA1
Reset type: SYSRSn

7-0

TASK5

R/W

0h

Selects the Trigger Source for TASK5 of CLA1
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

251

Registers

www.ti.com

2.15.7.5 DMACHSRCSEL1 Register (Offset = 16h) [reset = 0h]
DMACHSRCSEL1 is shown in Figure 2-80 and described in Table 2-84.
Return to Summary Table.
DMA Channel Trigger Source Select Register-1
Figure 2-80. DMACHSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CH4
CH3
CH2
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5

4 3 2
CH1
R/W-0h

1

0

Table 2-84. DMACHSRCSEL1 Register Field Descriptions

252

Bit

Field

Type

Reset

Description

31-24

CH4

R/W

0h

Selects the Trigger and Sync Source CH4 of DMA
Reset type: SYSRSn

23-16

CH3

R/W

0h

Selects the Trigger and Sync Source CH3 of DMA
Reset type: SYSRSn

15-8

CH2

R/W

0h

Selects the Trigger and Sync Source CH2 of DMA
Reset type: SYSRSn

7-0

CH1

R/W

0h

Selects the Trigger and Sync Source CH1 of DMA
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.7.6 DMACHSRCSEL2 Register (Offset = 18h) [reset = 0h]
DMACHSRCSEL2 is shown in Figure 2-81 and described in Table 2-85.
Return to Summary Table.
DMA Channel Trigger Source Select Register-2
Figure 2-81. DMACHSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CH6
R=0-0h
R/W-0h

9

8

7

6

5

4 3 2
CH5
R/W-0h

1

0

Table 2-85. DMACHSRCSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-8

CH6

R/W

0h

Selects the Trigger and Sync Source CH6 of DMA
Reset type: SYSRSn

7-0

CH5

R/W

0h

Selects the Trigger and Sync Source CH5 of DMA
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

253

Registers

www.ti.com

2.15.8 FLASH_PUMP_SEMAPHORE_REGS Registers
Table 2-86 lists the memory-mapped registers for the FLASH_PUMP_SEMAPHORE_REGS. All register
offset addresses not listed in Table 2-86 should be considered as reserved locations and the register
contents should not be modified.
Table 2-86. FLASH_PUMP_SEMAPHORE_REGS Registers
Offset
0h

Acronym

Register Name

Write Protection

PUMPREQUEST

Flash programming semaphore PUMP request
register

EALLOW

Section
Go

Complex bit access types are encoded to fit into small table cells. Table 2-87 shows the codes that are
used for access types in this section.
Table 2-87. FLASH_PUMP_SEMAPHORE_REGS
Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

Write

Read Type

Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

254

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.8.1 PUMPREQUEST Register (Offset = 0h) [reset = 0h]
PUMPREQUEST is shown in Figure 2-82 and described in Table 2-88.
Return to Summary Table.
Flash programming semaphore PUMP request register
Figure 2-82. PUMPREQUEST Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

KEY
R=0/W-0h
23

22

21

20
KEY
R=0/W-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

1
0
PUMP_OWNERSHIP
R/W-0h

Table 2-88. PUMPREQUEST Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

KEY

R=0/W

0h

In order to write to the semaphore bits, 0x5a5a must be written to
these key bits at the same time. Otherwise, writes are ignored. The
key is cleared immediately after writing, so it must be written again
for every semaphore change.
Reset type: CPU1.SYSRSn

15-2

RESERVED

R=0

0h

Reserved

1-0

PUMP_OWNERSHIP

R/W

0h

These bits configure which CPU has control of the flash pump, which
allows write access to the flash memory. The possible values are:
00 or 11: Read-only state. CPU1 has control of the pump, but CPU2
may seize control at any time.
01: CPU2 has exclusive control of the pump and of these
semaphore bits. CPU2 can relinquish control by setting the bits back
to 00 or 11.
10: CPU1 has exclusive control of the pump and of these
semaphore bits. CPU1 can relinquish control by setting the bits back
to 00 or 11.
Going from 01->10 or 10->01 is not allowed. Going from 00->11 or
11->00 is allowed, but has no effect. The semaphore bits [1:0] must
be written along with the correct key in bits [31:16].
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

255

Registers

www.ti.com

2.15.9 DEV_CFG_REGS Registers
Table 2-89 lists the memory-mapped registers for the DEV_CFG_REGS. All register offset addresses not
listed in Table 2-89 should be considered as reserved locations and the register contents should not be
modified.
Table 2-89. DEV_CFG_REGS Registers
Offset

256

Acronym

Register Name

Write Protection

Section

0h

DEVCFGLOCK1

Lock bit for CPUSELx registers

EALLOW

8h

PARTIDL_1

Lower 32-bit of Device PART Identification
Number

Go

Ah

PARTIDH_1

Upper 32-bit of Device PART Identification
Number

Go

Go

Ch

REVID

Device Revision Number

Go

10h

DC0_1

Device Capability: Device Information

Go

12h

DC1_1

Device Capability: Processing Block
Customization

Go

14h

DC2_1

Device Capability: EMIF Customization

Go

16h

DC3_1

Device Capability: Peripheral Customization

Go

18h

DC4_1

Device Capability: Peripheral Customization

Go

1Ah

DC5_1

Device Capability: Peripheral Customization

Go

1Ch

DC6_1

Device Capability: Peripheral Customization

Go

1Eh

DC7_1

Device Capability: Peripheral Customization

Go

20h

DC8_1

Device Capability: Peripheral Customization

Go

22h

DC9_1

Device Capability: Peripheral Customization

Go

24h

DC10_1

Device Capability: Peripheral Customization

Go

26h

DC11_1

Device Capability: Peripheral Customization

Go

28h

DC12_1

Device Capability: Peripheral Customization

Go

2Ah

DC13_1

Device Capability: Peripheral Customization

Go

2Ch

DC14_1

Device Capability: Analog Modules
Customization

Go

2Eh

DC15_1

Device Capability: Analog Modules
Customization

Go

32h

DC17_1

Device Capability: Analog Modules
Customization

Go

34h

DC18_1

Device Capability: CPU1 Lx SRAM
Customization

Go

36h

DC19_1

Device Capability: CPU2 Lx SRAM
Customization

Go

38h

DC20_1

Device Capability: GSx SRAM Customization

Go

60h

PERCNF1_1

Peripheral Configuration register

Go

74h

FUSEERR

e-Fuse error Status register

82h

SOFTPRES0

Processing Block Software Reset register

EALLOW

Go

84h

SOFTPRES1

EMIF Software Reset register

EALLOW

Go

86h

SOFTPRES2

Peripheral Software Reset register

EALLOW

Go

88h

SOFTPRES3

Peripheral Software Reset register

EALLOW

Go

8Ah

SOFTPRES4

Peripheral Software Reset register

EALLOW

Go

8Eh

SOFTPRES6

Peripheral Software Reset register

EALLOW

Go

90h

SOFTPRES7

Peripheral Software Reset register

EALLOW

Go

92h

SOFTPRES8

Peripheral Software Reset register

EALLOW

Go

94h

SOFTPRES9

Peripheral Software Reset register

EALLOW

Go

98h

SOFTPRES11

Peripheral Software Reset register

EALLOW

Go

9Ch

SOFTPRES13

Peripheral Software Reset register

EALLOW

Go

System Control

Go

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-89. DEV_CFG_REGS Registers (continued)
Offset

Acronym

Register Name

Write Protection

9Eh

SOFTPRES14

Peripheral Software Reset register

EALLOW

Section
Go

A2h

SOFTPRES16

Peripheral Software Reset register

EALLOW

Go

D6h

CPUSEL0

CPU Select register for common peripherals

EALLOW

Go

D8h

CPUSEL1

CPU Select register for common peripherals

EALLOW

Go

DAh

CPUSEL2

CPU Select register for common peripherals

EALLOW

Go

DCh

CPUSEL3

CPU Select register for common peripherals

EALLOW

Go

DEh

CPUSEL4

CPU Select register for common peripherals

EALLOW

Go

E0h

CPUSEL5

CPU Select register for common peripherals

EALLOW

Go

E2h

CPUSEL6

CPU Select register for common peripherals

EALLOW

Go

E4h

CPUSEL7

CPU Select register for common peripherals

EALLOW

Go

E6h

CPUSEL8

CPU Select register for common peripherals

EALLOW

Go

E8h

CPUSEL9

CPU Select register for common peripherals

EALLOW

Go

ECh

CPUSEL11

CPU Select register for common peripherals

EALLOW

Go

EEh

CPUSEL12

CPU Select register for common peripherals

EALLOW

Go

F2h

CPUSEL14

CPU Select register for common peripherals

EALLOW

Go

122h

CPU2RESCTL

CPU2 Reset Control Register

EALLOW

Go

124h

RSTSTAT

Reset Status register for secondary C28x CPUs

Go

125h

LPMSTAT

LPM Status Register for secondary C28x CPUs

Go

12Ch

SYSDBGCTL

System Debug Control register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 2-90 shows the codes that are
used for access types in this section.
Table 2-90. DEV_CFG_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

WOnce

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

257

Registers

www.ti.com

2.15.9.1 DEVCFGLOCK1 Register (Offset = 0h) [reset = 0h]
DEVCFGLOCK1 is shown in Figure 2-83 and described in Table 2-91.
Return to Summary Table.
Lock bit for CPUSELx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any
bit of this register has no effect
Figure 2-83. DEVCFGLOCK1 Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15
RESERVED
R=0-0h

14
CPUSEL14
R/WSOnce-0h

13
CPUSEL13
R/WSOnce-0h

12
CPUSEL12
R/WSOnce-0h

11
CPUSEL11
R/WSOnce-0h

10
CPUSEL10
R/WSOnce-0h

9
CPUSEL9
R/WSOnce-0h

8
CPUSEL8
R/WSOnce-0h

7
CPUSEL7
R/WSOnce-0h

6
CPUSEL6
R/WSOnce-0h

5
CPUSEL5
R/WSOnce-0h

4
CPUSEL4
R/WSOnce-0h

3
CPUSEL3
R/WSOnce-0h

2
CPUSEL2
R/WSOnce-0h

1
CPUSEL1
R/WSOnce-0h

0
CPUSEL0
R/WSOnce-0h

Table 2-91. DEVCFGLOCK1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15

RESERVED

R=0

0h

Reserved

14

CPUSEL14

R/WSOnce

0h

Lock bit for CPUSEL14 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

13

CPUSEL13

R/WSOnce

0h

Lock bit for CPUSEL13 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

12

CPUSEL12

R/WSOnce

0h

Lock bit for CPUSEL12 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

11

CPUSEL11

R/WSOnce

0h

Lock bit for CPUSEL11 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

10

CPUSEL10

R/WSOnce

0h

Lock bit for CPUSEL10 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

258

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-91. DEVCFGLOCK1 Register Field Descriptions (continued)
Bit
9

Field

Type

Reset

Description

CPUSEL9

R/WSOnce

0h

Lock bit for CPUSEL9 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

8

CPUSEL8

R/WSOnce

0h

Lock bit for CPUSEL8 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

7

CPUSEL7

R/WSOnce

0h

Lock bit for CPUSEL7 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

6

CPUSEL6

R/WSOnce

0h

Lock bit for CPUSEL6 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

5

CPUSEL5

R/WSOnce

0h

Lock bit for CPUSEL5 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

4

CPUSEL4

R/WSOnce

0h

Lock bit for CPUSEL4 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

3

CPUSEL3

R/WSOnce

0h

Lock bit for CPUSEL3 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

2

CPUSEL2

R/WSOnce

0h

Lock bit for CPUSEL2 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

1

CPUSEL1

R/WSOnce

0h

Lock bit for CPUSEL1 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

0

CPUSEL0

R/WSOnce

0h

Lock bit for CPUSEL0 register:
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

259

Registers

www.ti.com

2.15.9.2 PARTIDL_1 Register (Offset = 8h) [reset = X]
PARTIDL_1 is shown in Figure 2-84 and described in Table 2-92.
Return to Summary Table.
Lower 32-bit of Device PART Identification Number
Figure 2-84. PARTIDL_1 Register
31

30
29
PARTID_FORMAT_REVISION
R/WOnce-X

23

22

28

27

26

25

24

RESERVED
R/WOnce-X

21

20

19

18

17

16

FLASH_SIZE
R/WOnce-X
15
RESERVED
R/WOnce-X

14

7

6

13

12
RESERVED
R-0h

11
RESERVED
R-0h

10

9
PIN_COUNT
R/WOnce-X

8

5
RESERVED
R/WOnce-X

4

3

2

1
RESERVED
R-0h

0

INSTASPIN
R/WOnce-X

QUAL
R/WOnce-X

RESERVED
R-0h

Table 2-92. PARTIDL_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

PARTID_FORMAT_REVI
SION

R/WOnce

X

Revision of the PARTID format
Reset type: XRSn

27-24

RESERVED

R/WOnce

X

Reserved

23-16

FLASH_SIZE

R/WOnce

X

0x7 - 512KB
0x6 - 256KB
Note: This field shows flash size on CPU1 (see datasheet for flash
size available)
Reset type: XRSn

15

RESERVED

R/WOnce

X

Reserved

14-13

INSTASPIN

R/WOnce

X

0 = Reserved for future
1 = Reserved for future
2 = Reserved for future
3 = NONE
Reset type: XRSn

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10-8

PIN_COUNT

R/WOnce

X

0 = reserved for future
1 = reserved for future
2 = reserved for future
3 = reserved for future
4 = reserved for future
5 = 100 pin
6 = 176 pin
7 = 337 pin
Reset type: XRSn

260

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-92. PARTIDL_1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

QUAL

R/WOnce

X

0 = Engineering sample.(TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)
Reset type: XRSn

5

RESERVED

R/WOnce

X

Reserved

4-3

RESERVED

R

0h

Reserved

2-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

261

Registers

www.ti.com

2.15.9.3 PARTIDH_1 Register (Offset = Ah) [reset = X]
PARTIDH_1 is shown in Figure 2-85 and described in Table 2-93.
Return to Summary Table.
Upper 32-bit of Device PART Identification Number
Figure 2-85. PARTIDH_1 Register
31

30

29

15

14

13

28
27
26
DEVICE_CLASS_ID
R/WOnce-X
12
11
FAMILY
R/WOnce-X

10

25

24

23

22

21

20
19
PARTNO
R/WOnce-X

18

17

16

9

8

7

6

5

4
3
RESERVED
R/WOnce-X

2

1

0

Table 2-93. PARTIDH_1 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DEVICE_CLASS_ID

R/WOnce

X

Reserved
Reset type: XRSn

23-16

PARTNO

R/WOnce

X

Refer to Datasheet for Device Part Number
Reset type: XRSn

15-8

FAMILY

R/WOnce

X

Device Family
0x3 - DELFINO DUAL CORE
0x4 - DELFINO SINGLE CORE
0x5 - PICCOLO SINGLE CORE
Other values Reserved
Reset type: XRSn

7-0

262

RESERVED

System Control

R/WOnce

X

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.4 REVID Register (Offset = Ch) [reset = X]
REVID is shown in Figure 2-86 and described in Table 2-94.
Return to Summary Table.
Device Revision Number
Figure 2-86. REVID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
REVID
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-94. REVID Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

REVID

R

X

These 32-bits specify the silicon revision. See your device specific
datasheet for details.
Reset type: N/A

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

263

Registers

www.ti.com

2.15.9.5 DC0_1 Register (Offset = 10h) [reset = X]
DC0_1 is shown in Figure 2-87 and described in Table 2-95.
Return to Summary Table.
Device Capability: Device Information
Figure 2-87. DC0_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
SINGLE_CORE
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-95. DC0_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-1

RESERVED

R=0

0h

Reserved

SINGLE_CORE

R/WOnce

X

Single Core vs Dual Core

0

0: Single Core
1: Dual Core
Reset type: XRSn

264

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.6 DC1_1 Register (Offset = 12h) [reset = X]
DC1_1 is shown in Figure 2-88 and described in Table 2-96.
Return to Summary Table.
Device Capability: Processing Block Customization
Figure 2-88. DC1_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

12

11

10

9
RESERVED
R-0h

8
CPU2_CLA1
R/WOnce-X

4
RESERVED

3
CPU2_VCU

2
CPU1_VCU

R=0-0h

R/WOnce-X

R/WOnce-X

1
CPU2_FPU_T
MU
R/WOnce-X

0
CPU1_FPU_T
MU
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13
RESERVED
R=0-0h

7
RESERVED

6
CPU1_CLA1

R-0h

R/WOnce-X

5

Table 2-96. DC1_1 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-10

RESERVED

R=0

0h

Reserved

9

RESERVED

R

0h

Reserved

8

CPU2_CLA1

R/WOnce

X

0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn

7

RESERVED

R

0h

Reserved

6

CPU1_CLA1

R/WOnce

X

0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn

5-4

RESERVED

R=0

0h

Reserved

3

CPU2_VCU

R/WOnce

X

0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn

2

CPU1_VCU

R/WOnce

X

0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn

1

CPU2_FPU_TMU

R/WOnce

X

0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn

0

CPU1_FPU_TMU

R/WOnce

X

0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

265

Registers

www.ti.com

2.15.9.7 DC2_1 Register (Offset = 14h) [reset = X]
DC2_1 is shown in Figure 2-89 and described in Table 2-97.
Return to Summary Table.
Device Capability: EMIF Customization
Figure 2-89. DC2_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
EMIF2
R/WOnce-X

0
EMIF1
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-97. DC2_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

EMIF2

R/WOnce

X

EMIF2 :

1

0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0

EMIF1

R/WOnce

X

EMIF1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

266

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.8 DC3_1 Register (Offset = 16h) [reset = X]
DC3_1 is shown in Figure 2-90 and described in Table 2-98.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-90. DC3_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
EPWM12
R/WOnce-X

10
EPWM11
R/WOnce-X

9
EPWM10
R/WOnce-X

8
EPWM9
R/WOnce-X

7
EPWM8
R/WOnce-X

6
EPWM7
R/WOnce-X

5
EPWM6
R/WOnce-X

4
EPWM5
R/WOnce-X

3
EPWM4
R/WOnce-X

2
EPWM3
R/WOnce-X

1
EPWM2
R/WOnce-X

0
EPWM1
R/WOnce-X

Table 2-98. DC3_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

EPWM12

R/WOnce

X

EPWM12 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

10

EPWM11

R/WOnce

X

EPWM11 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

9

EPWM10

R/WOnce

X

EPWM10 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

8

EPWM9

R/WOnce

X

EPWM9 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

7

EPWM8

R/WOnce

X

EPWM8 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

267

Registers

www.ti.com

Table 2-98. DC3_1 Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

EPWM7

R/WOnce

X

EPWM7 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

5

EPWM6

R/WOnce

X

EPWM6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

4

EPWM5

R/WOnce

X

EPWM5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

3

EPWM4

R/WOnce

X

EPWM4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

2

EPWM3

R/WOnce

X

EPWM3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

EPWM2

R/WOnce

X

EPWM2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

EPWM1

R/WOnce

X

EPWM1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

268

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.9 DC4_1 Register (Offset = 18h) [reset = X]
DC4_1 is shown in Figure 2-91 and described in Table 2-99.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-91. DC4_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
ECAP4
R/WOnce-X

2
ECAP3
R/WOnce-X

1
ECAP2
R/WOnce-X

0
ECAP1
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R-0h

6
RESERVED
R-0h

5
ECAP6
R/WOnce-X

4
ECAP5
R/WOnce-X

Table 2-99. DC4_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

ECAP6

R/WOnce

X

ECAP6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

4

ECAP5

R/WOnce

X

ECAP5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

3

ECAP4

R/WOnce

X

ECAP4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

2

ECAP3

R/WOnce

X

ECAP3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

ECAP2

R/WOnce

X

ECAP2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

ECAP1

R/WOnce

X

ECAP1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

269

Registers

www.ti.com

2.15.9.10 DC5_1 Register (Offset = 1Ah) [reset = X]
DC5_1 is shown in Figure 2-92 and described in Table 2-100.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-92. DC5_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
EQEP3
R/WOnce-X

1
EQEP2
R/WOnce-X

0
EQEP1
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-100. DC5_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

EQEP3

R/WOnce

X

EQEP3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

EQEP2

R/WOnce

X

EQEP2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

EQEP1

R/WOnce

X

EQEP1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

270

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.11 DC6_1 Register (Offset = 1Ch) [reset = X]
DC6_1 is shown in Figure 2-93 and described in Table 2-101.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-93. DC6_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
CLB4
R/WOnce-X

2
CLB3
R/WOnce-X

1
CLB2
R/WOnce-X

0
CLB1
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R-0h

6
RESERVED
R-0h

5
RESERVED
R-0h

4
RESERVED
R-0h

Table 2-101. DC6_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

CLB4

R/WOnce

X

CLB4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

2

CLB3

R/WOnce

X

CLB3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

CLB2

R/WOnce

X

CLB2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

CLB1

R/WOnce

X

CLB1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

271

Registers

www.ti.com

2.15.9.12 DC7_1 Register (Offset = 1Eh) [reset = X]
DC7_1 is shown in Figure 2-94 and described in Table 2-102.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-94. DC7_1 Register
31

30

29

28

27

26

25

15

14

13

12
11
RESERVED

10

9

R=0-0h

24
23
RESERVED
R=0-0h
8

7
RESE
RVED
R-0h

22

21

20

19

18

17

16

6
RESE
RVED
R-0h

5
RESE
RVED
R-0h

4
RESE
RVED
R-0h

3
RESE
RVED
R-0h

2
RESE
RVED
R-0h

1
SD2

0
SD1

R/WO
nce-X

R/WO
nce-X

Table 2-102. DC7_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

SD2

R/WOnce

X

SD2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

SD1

R/WOnce

X

SD1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

272

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.13 DC8_1 Register (Offset = 20h) [reset = X]
DC8_1 is shown in Figure 2-95 and described in Table 2-103.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-95. DC8_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
SCI_D
R/WOnce-X

2
SCI_C
R/WOnce-X

1
SCI_B
R/WOnce-X

0
SCI_A
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-103. DC8_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

SCI_D

R/WOnce

X

SCI_D :

3

0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2

SCI_C

R/WOnce

X

SCI_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

SCI_B

R/WOnce

X

SCI_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

SCI_A

R/WOnce

X

SCI_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

273

Registers

www.ti.com

2.15.9.14 DC9_1 Register (Offset = 22h) [reset = X]
DC9_1 is shown in Figure 2-96 and described in Table 2-104.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-96. DC9_1 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
RESERVED
R-0h

11

10

9

8

3
RESERVED
R-0h

2
SPI_C
R/WOnce-X

1
SPI_B
R/WOnce-X

0
SPI_A
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-104. DC9_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

SPI_C

R/WOnce

X

SPI_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

SPI_B

R/WOnce

X

SPI_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

SPI_A

R/WOnce

X

SPI_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

274

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.15 DC10_1 Register (Offset = 24h) [reset = X]
DC10_1 is shown in Figure 2-97 and described in Table 2-105.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-97. DC10_1 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
RESERVED
R-0h

11

10

9

8

3

2

1
I2C_B
R/WOnce-X

0
I2C_A
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-105. DC10_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

I2C_B

R/WOnce

X

I2C_B :

1

0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0

I2C_A

R/WOnce

X

I2C_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

275

Registers

www.ti.com

2.15.9.16 DC11_1 Register (Offset = 26h) [reset = X]
DC11_1 is shown in Figure 2-98 and described in Table 2-106.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-98. DC11_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
RESERVED
R-0h

1
CAN_B
R/WOnce-X

0
CAN_A
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-106. DC11_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

CAN_B

R/WOnce

X

CAN_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

CAN_A

R/WOnce

X

CAN_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

276

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.17 DC12_1 Register (Offset = 28h) [reset = X]
DC12_1 is shown in Figure 2-99 and described in Table 2-107.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-99. DC12_1 Register
31

30

29

28

27

26

25

18

17

24

RESERVED
R=0-0h
23

22

21

20

19

RESERVED
R=0-0h
15

14

RESERVED
R-0h
13

12

16
USB_A
R/WOnce-X

11

10

9

8

3

2

1
McBSP_B
R/WOnce-X

0
McBSP_A
R/WOnce-X

RESERVED
R=0-0h
7

6

5

4
RESERVED
R=0-0h

Table 2-107. DC12_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

RESERVED

R=0

0h

Reserved

19-18

RESERVED

R

0h

Reserved

17-16

USB_A

R/WOnce

X

Capability of the USB_A Module:
2'b00: No USB function
2'b01: Device Only
2'b10: Device or Host
2'b11: OTG
Reset type: XRSn

15-2
1

RESERVED

R=0

0h

Reserved

McBSP_B

R/WOnce

X

McBSP_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

McBSP_A

R/WOnce

X

McBSP_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

277

Registers

www.ti.com

2.15.9.18 DC13_1 Register (Offset = 2Ah) [reset = X]
DC13_1 is shown in Figure 2-100 and described in Table 2-108.
Return to Summary Table.
Device Capability: Peripheral Customization
Figure 2-100. DC13_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
RESERVED
R-0h

0
uPP_A
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-108. DC13_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

1

RESERVED

R

0h

Reserved

0

uPP_A

R/WOnce

X

uPP_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

278

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.19 DC14_1 Register (Offset = 2Ch) [reset = X]
DC14_1 is shown in Figure 2-101 and described in Table 2-109.
Return to Summary Table.
Device Capability: Analog Modules Customization
Figure 2-101. DC14_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
ADC_D
R/WOnce-X

2
ADC_C
R/WOnce-X

1
ADC_B
R/WOnce-X

0
ADC_A
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-109. DC14_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

ADC_D

R/WOnce

X

ADC_D :

3

0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
2

ADC_C

R/WOnce

X

ADC_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

ADC_B

R/WOnce

X

ADC_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

ADC_A

R/WOnce

X

ADC_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

279

Registers

www.ti.com

2.15.9.20 DC15_1 Register (Offset = 2Eh) [reset = X]
DC15_1 is shown in Figure 2-102 and described in Table 2-110.
Return to Summary Table.
Device Capability: Analog Modules Customization
Figure 2-102. DC15_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
CMPSS4
R/WOnce-X

2
CMPSS3
R/WOnce-X

1
CMPSS2
R/WOnce-X

0
CMPSS1
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
CMPSS8
R/WOnce-X

6
CMPSS7
R/WOnce-X

5
CMPSS6
R/WOnce-X

4
CMPSS5
R/WOnce-X

Table 2-110. DC15_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

CMPSS8

R/WOnce

X

CMPSS8 :

7

0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
6

CMPSS7

R/WOnce

X

CMPSS7 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

5

CMPSS6

R/WOnce

X

CMPSS6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

4

CMPSS5

R/WOnce

X

CMPSS5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

3

CMPSS4

R/WOnce

X

CMPSS4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

2

CMPSS3

R/WOnce

X

CMPSS3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

280

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-110. DC15_1 Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

CMPSS2

R/WOnce

X

CMPSS2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

CMPSS1

R/WOnce

X

CMPSS1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

281

Registers

www.ti.com

2.15.9.21 DC17_1 Register (Offset = 32h) [reset = X]
DC17_1 is shown in Figure 2-103 and described in Table 2-111.
Return to Summary Table.
Device Capability: Analog Modules Customization
Figure 2-103. DC17_1 Register
31

30

29

28

27

26

25

24

19
RESERVED
R-0h

18
DAC_C
R/WOnce-X

17
DAC_B
R/WOnce-X

16
DAC_A
R/WOnce-X

11

10

9

8

3
RESERVED
R-0h

2
RESERVED
R-0h

1
RESERVED
R-0h

0
RESERVED
R-0h

RESERVED
R=0-0h
23

22

21

20

13

12

RESERVED
R=0-0h
15

14

RESERVED
R=0-0h
7

6

5

4

RESERVED
R=0-0h

Table 2-111. DC17_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

RESERVED

R=0

0h

Reserved

19

RESERVED

R

0h

Reserved

18

DAC_C

R/WOnce

X

Buffered-DAC_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

17

DAC_B

R/WOnce

X

Buffered-DAC_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

16

DAC_A

R/WOnce

X

Buffered-DAC_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

282

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.22 DC18_1 Register (Offset = 34h) [reset = X]
DC18_1 is shown in Figure 2-104 and described in Table 2-112.
Return to Summary Table.
Device Capability: CPU1 Lx SRAM Customization
Figure 2-104. DC18_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
LS3_1
R/WOnce-X

2
LS2_1
R/WOnce-X

1
LS1_1
R/WOnce-X

0
LS0_1
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6
RESERVED
R=0-0h

5
LS5_1
R/WOnce-X

4
LS4_1
R/WOnce-X

Table 2-112. DC18_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-6

RESERVED

R=0

0h

Reserved

LS5_1

R/WOnce

X

LS5_1 :

5

0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
4

LS4_1

R/WOnce

X

LS4_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

3

LS3_1

R/WOnce

X

LS3_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

2

LS2_1

R/WOnce

X

LS2_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

LS1_1

R/WOnce

X

LS1_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

LS0_1

R/WOnce

X

LS0_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

283

Registers

www.ti.com

2.15.9.23 DC19_1 Register (Offset = 36h) [reset = X]
DC19_1 is shown in Figure 2-105 and described in Table 2-113.
Return to Summary Table.
Device Capability: CPU2 Lx SRAM Customization
Figure 2-105. DC19_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
LS3_2
R/WOnce-X

2
LS2_2
R/WOnce-X

1
LS1_2
R/WOnce-X

0
LS0_2
R/WOnce-X

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6
RESERVED
R=0-0h

5
LS5_2
R/WOnce-X

4
LS4_2
R/WOnce-X

Table 2-113. DC19_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-6

RESERVED

R=0

0h

Reserved

LS5_2

R/WOnce

X

LS5_2 :

5

0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
4

LS4_2

R/WOnce

X

LS4_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

3

LS3_2

R/WOnce

X

LS3_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

2

LS2_2

R/WOnce

X

LS2_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

LS1_2

R/WOnce

X

LS1_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

LS0_2

R/WOnce

X

LS0_2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

284

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.24 DC20_1 Register (Offset = 38h) [reset = X]
DC20_1 is shown in Figure 2-106 and described in Table 2-114.
Return to Summary Table.
Device Capability: GSx SRAM Customization
Figure 2-106. DC20_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15
GS15
R/WOnce-X

14
GS14
R/WOnce-X

13
GS13
R/WOnce-X

12
GS12
R/WOnce-X

11
GS11
R/WOnce-X

10
GS10
R/WOnce-X

9
GS9
R/WOnce-X

8
GS8
R/WOnce-X

7
GS7
R/WOnce-X

6
GS6
R/WOnce-X

5
GS5
R/WOnce-X

4
GS4
R/WOnce-X

3
GS3
R/WOnce-X

2
GS2
R/WOnce-X

1
GS1
R/WOnce-X

0
GS0
R/WOnce-X

Table 2-114. DC20_1 Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

GS15

R/WOnce

X

GS15 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

14

GS14

R/WOnce

X

GS14 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

13

GS13

R/WOnce

X

GS13 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

12

GS12

R/WOnce

X

GS12 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

11

GS11

R/WOnce

X

GS11 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

10

GS10

R/WOnce

X

GS10 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

285

Registers

www.ti.com

Table 2-114. DC20_1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

9

GS9

R/WOnce

X

GS9 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

8

GS8

R/WOnce

X

GS8 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

7

GS7

R/WOnce

X

GS7 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

6

GS6

R/WOnce

X

GS6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

5

GS5

R/WOnce

X

GS5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

4

GS4

R/WOnce

X

GS4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

3

GS3

R/WOnce

X

GS3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

2

GS2

R/WOnce

X

GS2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

1

GS1

R/WOnce

X

GS1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

0

GS0

R/WOnce

X

GS0 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn

286

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.25 PERCNF1_1 Register (Offset = 60h) [reset = X]
PERCNF1_1 is shown in Figure 2-107 and described in Table 2-115.
Return to Summary Table.
Peripheral Configuration register
Figure 2-107. PERCNF1_1 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
USB_A_PHY
R/WOnce-X

11

10

9

8

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

3
2
1
0
ADC_D_MODE ADC_C_MODE ADC_B_MODE ADC_A_MODE
R/WOnce-X
R/WOnce-X
R/WOnce-X
R/WOnce-X

Table 2-115. PERCNF1_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

USB_A_PHY

R/WOnce

X

Internal PHY is present present or not for the USB_A module:
0: Internal USB PHY Module is not present
1: Internal USB PHY Module is present.
Reset type: XRSn

15-4
3

RESERVED

R=0

0h

Reserved

ADC_D_MODE

R/WOnce

X

0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn

2

ADC_C_MODE

R/WOnce

X

0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn

1

ADC_B_MODE

R/WOnce

X

0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn

0

ADC_A_MODE

R/WOnce

X

0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

287

Registers

www.ti.com

2.15.9.26 FUSEERR Register (Offset = 74h) [reset = 0h]
FUSEERR is shown in Figure 2-108 and described in Table 2-116.
Return to Summary Table.
e-Fuse error Status register
Figure 2-108. FUSEERR Register
31

30

29

28

27

26

25

15

14

13

12

11
10
RESERVED
R=0-0h

9

24
23
RESERVED
R=0-0h
8

7

22

21

20

19

18

17

16

6

5
ERR
R-0h

4

3

2
ALERR
R-0h

1

0

Table 2-116. FUSEERR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-6

RESERVED

R=0

0h

Reserved

ERR

R

0h

Efuse Self Test Error Status set by hardware after fuse self test
completes, in case of self test error

5

0: No error during fuse self test
1: Fuse self test error
Reset type: XRSn
4-0

ALERR

R

0h

Efuse Autoload Error Status set by hardware after fuse auto load
completes
00000: No error in auto load
Other: Non zero value indicates error in autoload
Reset type: XRSn

288

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.27 SOFTPRES0 Register (Offset = 82h) [reset = 0h]
SOFTPRES0 is shown in Figure 2-109 and described in Table 2-117.
Return to Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-109. SOFTPRES0 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
CPU2_CLA1
R/W-0h

1
RESERVED
R-0h

0
CPU1_CLA1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-117. SOFTPRES0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

CPU2_CLA1

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

1

RESERVED

R

0h

Reserved

0

CPU1_CLA1

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

289

Registers

www.ti.com

2.15.9.28 SOFTPRES1 Register (Offset = 84h) [reset = 0h]
SOFTPRES1 is shown in Figure 2-110 and described in Table 2-118.
Return to Summary Table.
EMIF Software Reset register
Figure 2-110. SOFTPRES1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
EMIF2
R/W-0h

0
EMIF1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-118. SOFTPRES1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

EMIF2

R/W

0h

When this bit is set, only the control logic of the respective EMIF2 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register.

1

This bit must be manually cleared after being set.
1: EMIF2 is under SOFTRESET
0: Module reset is determined by the device Reset Network
Reset type: CPU1.SYSRSn
0

EMIF1

R/W

0h

When this bit is set, only the control logic of the respective EMIF1 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register.
This bit must be manually cleared after being set.
1: EMIF1 is under SOFTRESET
0: Module reset is determined by the device Reset Network
Reset type: CPU1.SYSRSn

290

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.29 SOFTPRES2 Register (Offset = 86h) [reset = 0h]
SOFTPRES2 is shown in Figure 2-111 and described in Table 2-119.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-111. SOFTPRES2 Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
EPWM12
R/W-0h

10
EPWM11
R/W-0h

9
EPWM10
R/W-0h

8
EPWM9
R/W-0h

7
EPWM8
R/W-0h

6
EPWM7
R/W-0h

5
EPWM6
R/W-0h

4
EPWM5
R/W-0h

3
EPWM4
R/W-0h

2
EPWM3
R/W-0h

1
EPWM2
R/W-0h

0
EPWM1
R/W-0h

Table 2-119. SOFTPRES2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

EPWM12

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

10

EPWM11

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

9

EPWM10

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

8

EPWM9

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

7

EPWM8

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

6

EPWM7

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

5

EPWM6

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

291

Registers

www.ti.com

Table 2-119. SOFTPRES2 Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

EPWM5

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

3

EPWM4

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

2

EPWM3

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

1

EPWM2

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

EPWM1

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

292

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.30 SOFTPRES3 Register (Offset = 88h) [reset = 0h]
SOFTPRES3 is shown in Figure 2-112 and described in Table 2-120.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-112. SOFTPRES3 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
ECAP4
R/W-0h

2
ECAP3
R/W-0h

1
ECAP2
R/W-0h

0
ECAP1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R-0h

6
RESERVED
R-0h

5
ECAP6
R/W-0h

4
ECAP5
R/W-0h

Table 2-120. SOFTPRES3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

ECAP6

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

4

ECAP5

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

3

ECAP4

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

2

ECAP3

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

1

ECAP2

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

ECAP1

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

293

Registers

www.ti.com

2.15.9.31 SOFTPRES4 Register (Offset = 8Ah) [reset = 0h]
SOFTPRES4 is shown in Figure 2-113 and described in Table 2-121.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-113. SOFTPRES4 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
EQEP3
R/W-0h

1
EQEP2
R/W-0h

0
EQEP1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-121. SOFTPRES4 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

EQEP3

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

1

EQEP2

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

EQEP1

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

294

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.32 SOFTPRES6 Register (Offset = 8Eh) [reset = 0h]
SOFTPRES6 is shown in Figure 2-114 and described in Table 2-122.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-114. SOFTPRES6 Register
31

30

29

28

27

26

25

15

14

13

12
11
RESERVED

10

9

R=0-0h

24
23
RESERVED
R=0-0h
8

7
RESE
RVED
R-0h

22

21

20

19

18

17

16

6
RESE
RVED
R-0h

5
RESE
RVED
R-0h

4
RESE
RVED
R-0h

3
RESE
RVED
R-0h

2
RESE
RVED
R-0h

1
SD2

0
SD1

R/W0h

R/W0h

Table 2-122. SOFTPRES6 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

SD2

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

SD1

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

295

Registers

www.ti.com

2.15.9.33 SOFTPRES7 Register (Offset = 90h) [reset = 0h]
SOFTPRES7 is shown in Figure 2-115 and described in Table 2-123.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-115. SOFTPRES7 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
SCI_D
R/W-0h

2
SCI_C
R/W-0h

1
SCI_B
R/W-0h

0
SCI_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-123. SOFTPRES7 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

SCI_D

R/W

0h

1: Module is under reset

3

0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2

SCI_C

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

1

SCI_B

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

SCI_A

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

296

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.34 SOFTPRES8 Register (Offset = 92h) [reset = 0h]
SOFTPRES8 is shown in Figure 2-116 and described in Table 2-124.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-116. SOFTPRES8 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
RESERVED
R-0h

11

10

9

8

3
RESERVED
R-0h

2
SPI_C
R/W-0h

1
SPI_B
R/W-0h

0
SPI_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-124. SOFTPRES8 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

SPI_C

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

1

SPI_B

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

SPI_A

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

297

Registers

www.ti.com

2.15.9.35 SOFTPRES9 Register (Offset = 94h) [reset = 0h]
SOFTPRES9 is shown in Figure 2-117 and described in Table 2-125.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-117. SOFTPRES9 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
RESERVED
R-0h

11

10

9

8

3

2

1
I2C_B
R/W-0h

0
I2C_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-125. SOFTPRES9 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

I2C_B

R/W

0h

1: Module is under reset

1

0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0

I2C_A

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

298

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.36 SOFTPRES11 Register (Offset = 98h) [reset = 0h]
SOFTPRES11 is shown in Figure 2-118 and described in Table 2-126.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-118. SOFTPRES11 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
USB_A
R/W-0h

11

10

9

8

3

2

1
McBSP_B
R/W-0h

0
McBSP_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-126. SOFTPRES11 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

USB_A

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

15-2
1

RESERVED

R=0

0h

Reserved

McBSP_B

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

McBSP_A

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

299

Registers

www.ti.com

2.15.9.37 SOFTPRES13 Register (Offset = 9Ch) [reset = 0h]
SOFTPRES13 is shown in Figure 2-119 and described in Table 2-127.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-119. SOFTPRES13 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
ADC_D
R/W-0h

2
ADC_C
R/W-0h

1
ADC_B
R/W-0h

0
ADC_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-127. SOFTPRES13 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

ADC_D

R/W

0h

1: Module is under reset

3

0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2

ADC_C

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

1

ADC_B

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

ADC_A

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

300

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.38 SOFTPRES14 Register (Offset = 9Eh) [reset = 0h]
SOFTPRES14 is shown in Figure 2-120 and described in Table 2-128.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-120. SOFTPRES14 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
CMPSS4
R/W-0h

2
CMPSS3
R/W-0h

1
CMPSS2
R/W-0h

0
CMPSS1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
CMPSS8
R/W-0h

6
CMPSS7
R/W-0h

5
CMPSS6
R/W-0h

4
CMPSS5
R/W-0h

Table 2-128. SOFTPRES14 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

CMPSS8

R/W

0h

1: Module is under reset

7

0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
6

CMPSS7

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

5

CMPSS6

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

4

CMPSS5

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

3

CMPSS4

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

2

CMPSS3

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

1

CMPSS2

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

0

CMPSS1

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

301

Registers

www.ti.com

2.15.9.39 SOFTPRES16 Register (Offset = A2h) [reset = 0h]
SOFTPRES16 is shown in Figure 2-121 and described in Table 2-129.
Return to Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-121. SOFTPRES16 Register
31

30

29

28

27

26

25

24

19
RESERVED
R-0h

18
DAC_C
R/W-0h

17
DAC_B
R/W-0h

16
DAC_A
R/W-0h

11

10

9

8

3
RESERVED
R-0h

2
RESERVED
R-0h

1
RESERVED
R-0h

0
RESERVED
R-0h

RESERVED
R=0-0h
23

22

21

20

13

12

RESERVED
R=0-0h
15

14

RESERVED
R=0-0h
7

6

5

4

RESERVED
R=0-0h

Table 2-129. SOFTPRES16 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

RESERVED

R=0

0h

Reserved

19

RESERVED

R

0h

Reserved

18

DAC_C

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

17

DAC_B

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

16

DAC_A

R/W

0h

1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

302

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.40 CPUSEL0 Register (Offset = D6h) [reset = 0h]
CPUSEL0 is shown in Figure 2-122 and described in Table 2-130.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-122. CPUSEL0 Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
EPWM12
R/W-0h

10
EPWM11
R/W-0h

9
EPWM10
R/W-0h

8
EPWM9
R/W-0h

7
EPWM8
R/W-0h

6
EPWM7
R/W-0h

5
EPWM6
R/W-0h

4
EPWM5
R/W-0h

3
EPWM4
R/W-0h

2
EPWM3
R/W-0h

1
EPWM2
R/W-0h

0
EPWM1
R/W-0h

Table 2-130. CPUSEL0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

EPWM12

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

10

EPWM11

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

9

EPWM10

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

8

EPWM9

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

7

EPWM8

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

6

EPWM7

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

303

Registers

www.ti.com

Table 2-130. CPUSEL0 Register Field Descriptions (continued)
Bit
5

Field

Type

Reset

Description

EPWM6

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

4

EPWM5

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

3

EPWM4

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

2

EPWM3

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

1

EPWM2

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

0

EPWM1

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

304

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.41 CPUSEL1 Register (Offset = D8h) [reset = 0h]
CPUSEL1 is shown in Figure 2-123 and described in Table 2-131.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-123. CPUSEL1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
ECAP4
R/W-0h

2
ECAP3
R/W-0h

1
ECAP2
R/W-0h

0
ECAP1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R-0h

6
RESERVED
R-0h

5
ECAP6
R/W-0h

4
ECAP5
R/W-0h

Table 2-131. CPUSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

ECAP6

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

4

ECAP5

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

3

ECAP4

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

2

ECAP3

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

1

ECAP2

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

0

ECAP1

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

305

Registers

www.ti.com

2.15.9.42 CPUSEL2 Register (Offset = DAh) [reset = 0h]
CPUSEL2 is shown in Figure 2-124 and described in Table 2-132.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-124. CPUSEL2 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
EQEP3
R/W-0h

1
EQEP2
R/W-0h

0
EQEP1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-132. CPUSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

EQEP3

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

1

EQEP2

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

0

EQEP1

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

306

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.43 CPUSEL3 Register (Offset = DCh) [reset = 0h]
CPUSEL3 is shown in Figure 2-125 and described in Table 2-133.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-125. CPUSEL3 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
RESERVED
R-0h

1
RESERVED
R-0h

0
RESERVED
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R-0h

6
RESERVED
R-0h

5
RESERVED
R-0h

4
RESERVED
R-0h

Table 2-133. CPUSEL3 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

307

Registers

www.ti.com

2.15.9.44 CPUSEL4 Register (Offset = DEh) [reset = 0h]
CPUSEL4 is shown in Figure 2-126 and described in Table 2-134.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-126. CPUSEL4 Register
31

30

29

15

14

13

28

27

26

25

12

11

10

9

RESERVED
R=0-0h

24
23
RESERVED
R=0-0h
8

22

21

20

19

18

17

16

7

6

5

4

3

2

1

0

RESE
RVED
R-0h

RESE
RVED
R-0h

RESE
RVED
R-0h

RESE
RVED
R-0h

RESE
RVED
R-0h

RESE
RVED
R-0h

SD2

SD1

R/W0h

R/W0h

Table 2-134. CPUSEL4 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

SD2

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

0

SD1

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

308

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.45 CPUSEL5 Register (Offset = E0h) [reset = 0h]
CPUSEL5 is shown in Figure 2-127 and described in Table 2-135.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-127. CPUSEL5 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
SCI_D
R/W-0h

2
SCI_C
R/W-0h

1
SCI_B
R/W-0h

0
SCI_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-135. CPUSEL5 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

SCI_D

R/W

0h

0: Connected to CPU1

3

1: Connected to CPU2
Reset type: CPU1.SYSRSn
2

SCI_C

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

1

SCI_B

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

0

SCI_A

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

309

Registers

www.ti.com

2.15.9.46 CPUSEL6 Register (Offset = E2h) [reset = 0h]
CPUSEL6 is shown in Figure 2-128 and described in Table 2-136.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-128. CPUSEL6 Register
31

30

29

28

27

26

19

18

25

24

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12

17

16

RESERVED
R-0h

RESERVED
R-0h

11

10

9

8

3
RESERVED
R-0h

2
SPI_C
R/W-0h

1
SPI_B
R/W-0h

0
SPI_A
R/W-0h

RESERVED
R=0-0h
7

6

5

4

RESERVED
R=0-0h

Table 2-136. CPUSEL6 Register Field Descriptions
Field

Type

Reset

Description

31-18

Bit

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

SPI_C

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

1

SPI_B

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

0

SPI_A

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

310

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.47 CPUSEL7 Register (Offset = E4h) [reset = 0h]
CPUSEL7 is shown in Figure 2-129 and described in Table 2-137.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-129. CPUSEL7 Register
31

30

29

28

27

26

19

18

25

24

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12

17

16

RESERVED
R-0h

RESERVED
R-0h

11

10

9

8

3

2

1
I2C_B
R/W-0h

0
I2C_A
R/W-0h

RESERVED
R=0-0h
7

6

5

4
RESERVED
R=0-0h

Table 2-137. CPUSEL7 Register Field Descriptions
Field

Type

Reset

Description

31-18

Bit

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

I2C_B

R/W

0h

0: Connected to CPU1

1

1: Connected to CPU2
Reset type: CPU1.SYSRSn
0

I2C_A

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

311

Registers

www.ti.com

2.15.9.48 CPUSEL8 Register (Offset = E6h) [reset = 0h]
CPUSEL8 is shown in Figure 2-130 and described in Table 2-138.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-130. CPUSEL8 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
RESERVED
R-0h

1
CAN_B
R/W-0h

0
CAN_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-138. CPUSEL8 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

CAN_B

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

0

CAN_A

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

312

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.49 CPUSEL9 Register (Offset = E8h) [reset = 0h]
CPUSEL9 is shown in Figure 2-131 and described in Table 2-139.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-131. CPUSEL9 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
McBSP_B
R/W-0h

0
McBSP_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-139. CPUSEL9 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

McBSP_B

R/W

0h

0: Connected to CPU1

1

1: Connected to CPU2
Reset type: CPU1.SYSRSn
0

McBSP_A

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

313

Registers

www.ti.com

2.15.9.50 CPUSEL11 Register (Offset = ECh) [reset = 0h]
CPUSEL11 is shown in Figure 2-132 and described in Table 2-140.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-132. CPUSEL11 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
ADC_D
R/W-0h

2
ADC_C
R/W-0h

1
ADC_B
R/W-0h

0
ADC_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-140. CPUSEL11 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

ADC_D

R/W

0h

0: Connected to CPU1

3

1: Connected to CPU2
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on the
mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
Reset type: CPU1.SYSRSn
2

ADC_C

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on the
mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
Reset type: CPU1.SYSRSn

314

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-140. CPUSEL11 Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

ADC_B

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on the
mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
Reset type: CPU1.SYSRSn

0

ADC_A

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on the
mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

315

Registers

www.ti.com

2.15.9.51 CPUSEL12 Register (Offset = EEh) [reset = 0h]
CPUSEL12 is shown in Figure 2-133 and described in Table 2-141.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-133. CPUSEL12 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
CMPSS4
R/W-0h

2
CMPSS3
R/W-0h

1
CMPSS2
R/W-0h

0
CMPSS1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
CMPSS8
R/W-0h

6
CMPSS7
R/W-0h

5
CMPSS6
R/W-0h

4
CMPSS5
R/W-0h

Table 2-141. CPUSEL12 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

CMPSS8

R/W

0h

0: Connected to CPU1

7

1: Connected to CPU2
Reset type: CPU1.SYSRSn
6

CMPSS7

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

5

CMPSS6

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

4

CMPSS5

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

3

CMPSS4

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

2

CMPSS3

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

1

CMPSS2

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

316

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-141. CPUSEL12 Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

CMPSS1

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

317

Registers

www.ti.com

2.15.9.52 CPUSEL14 Register (Offset = F2h) [reset = 0h]
CPUSEL14 is shown in Figure 2-134 and described in Table 2-142.
Return to Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-134. CPUSEL14 Register
31

30

29

28

27

26

25

24

RESERVED
R=0-0h
23

22

21

20

RESERVED
R=0-0h
15

14

13

19

18

17

16

RESERVED
R-0h

DAC_C
R/W-0h

DAC_B
R/W-0h

DAC_A
R/W-0h

11

10

9

8

3
RESERVED
R-0h

2
RESERVED
R-0h

1
RESERVED
R-0h

0
RESERVED
R-0h

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-142. CPUSEL14 Register Field Descriptions
Field

Type

Reset

Description

31-20

Bit

RESERVED

R=0

0h

Reserved

19

RESERVED

R

0h

Reserved

18

DAC_C

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

17

DAC_B

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

16

DAC_A

R/W

0h

0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

318

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.53 CPU2RESCTL Register (Offset = 122h) [reset = 1h]
CPU2RESCTL is shown in Figure 2-135 and described in Table 2-143.
Return to Summary Table.
CPU2 Reset Control Register
Figure 2-135. CPU2RESCTL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
RESET
R/W-1h

KEY
R=0/W-0h
23

22

21

20
KEY
R=0/W-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-143. CPU2RESCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

KEY

R=0/W

0h

Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: N/A

15-1
0

RESERVED

R=0

0h

Reserved

RESET

R/W

1h

This bit controls the reset input of CPU2 core.
1: CPU2 is held in reset (CPU2.RSn = 0)
0: CPU2 reset is deactivated (CPU2.RSn = 1)
Note:
[1] If CPU2 is not used at-all by an application, it's advisable to put
CPU2 in STANDBY mode rather than in reset to save on active
power component on the CPU2 subsystem. This is because, all
clocks keep toggling when reset is active on the CPU2 sub-system.
[2] Note: If CPU2 is in Standby mode, writing to this bit will have no
effect. CPU2 may be reset by any Chip-level reset (POR, XRSn,
CPU1.WDRSn, or CPU1.NMIWDRSn) or HIBRESETn. Alternately
CPU2 may be woken up by any configured wake-up event.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

319

Registers

www.ti.com

2.15.9.54 RSTSTAT Register (Offset = 124h) [reset = 0h]
RSTSTAT is shown in Figure 2-136 and described in Table 2-144.
Return to Summary Table.
Reset Status register for secondary C28x CPUs
Figure 2-136. RSTSTAT Register
15

14

13

12

11

10

9

8

3
CPU2HWBIST
RST1
R/W=1-0h

2
CPU2HWBIST
RST0
R/W=1-0h

1
CPU2NMIWDR
ST
R/W=1-0h

0
CPU2RES

RESERVED
R=0-0h
7

6

5

4

RESERVED
R=0-0h

R-0h

Table 2-144. RSTSTAT Register Field Descriptions
Bit
15-4
3

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

CPU2HWBISTRST1

R/W=1

0h

CPU2HWBISTRST0 and CPU2HWBISTRST1 together indicates
whether a HWBIST reset was issued to CPU2 or not
00: CPU2 was not reset by the CPU2 HWBIST
11: CPU2 was reset due to CPU2 HWBIST reset
This status bit is a latched flag. This flag can be cleared by the
CPU1 by writing a 1
Reset type: CPU1.SYSRSn

2

CPU2HWBISTRST0

R/W=1

0h

CPU2HWBISTRST0 and CPU2HWBISTRST1 together indicates
whether a HWBIST reset was issued to CPU2 or not
00: CPU2 was not reset by the CPU2 HWBIST
11: CPU2 was reset due to CPU2 HWBIST reset
This status bit is a latched flag. This flag can be cleared by the
CPU1 by writing a 1
Reset type: CPU1.SYSRSn

1

CPU2NMIWDRST

R/W=1

0h

Indicates whether a CPU2.NMIWD reset was issued to CPU2 or not
0: CPU2 was not reset by the CPU2.NMIWD
1: CPU2 was reset due to CPU2.NMIWD reset
This status bit is a latched flag.This flag can be cleared by the CPU1
by writing a 1
Reset type: CPU1.SYSRSn

0

CPU2RES

R

0h

Reset status of CPU2 to CPU1
0: CPU2 core is in reset
1: CPU2 core is out of reset
Reset type: CPU1.SYSRSn

320

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.9.55 LPMSTAT Register (Offset = 125h) [reset = 0h]
LPMSTAT is shown in Figure 2-137 and described in Table 2-145.
Return to Summary Table.
LPM Status Register for secondary C28x CPUs
Figure 2-137. LPMSTAT Register
15

14

13

12

11

10

9

3

2

1

8

RESERVED
R=0-0h
7

6

5

4
RESERVED
R=0-0h

0
CPU2LPMSTAT
R-0h

Table 2-145. LPMSTAT Register Field Descriptions
Field

Type

Reset

Description

15-2

Bit

RESERVED

R=0

0h

Reserved

1-0

CPU2LPMSTAT

R

0h

These bits indicate the power mode CPU2
00: CPU2 is in ACTIVE mode
01: CPU2 is in IDLE mode
10: CPU2 is in STANDBY mode
11: Reserved
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

321

Registers

www.ti.com

2.15.9.56 SYSDBGCTL Register (Offset = 12Ch) [reset = 0h]
SYSDBGCTL is shown in Figure 2-138 and described in Table 2-146.
Return to Summary Table.
System Debug Control register
Figure 2-138. SYSDBGCTL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
BIT_0
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-146. SYSDBGCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-1

RESERVED

R=0

0h

Reserved

BIT_0

R/W

0h

This bit is for use in PLL startup and is only reset by POR.
Reset type: PORn

0

322

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10 CLK_CFG_REGS Registers
Table 2-147 lists the memory-mapped registers for the CLK_CFG_REGS. All register offset addresses not
listed in Table 2-147 should be considered as reserved locations and the register contents should not be
modified.
Table 2-147. CLK_CFG_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

CLKSEM

Clock Control Semaphore Register

EALLOW

Go

2h

CLKCFGLOCK1

Lock bit for CLKCFG registers

EALLOW

Go

8h

CLKSRCCTL1

Clock Source Control register-1

EALLOW

Go

Ah

CLKSRCCTL2

Clock Source Control register-2

EALLOW

Go

Ch

CLKSRCCTL3

Clock Source Control register-3

EALLOW

Go

Eh

SYSPLLCTL1

SYSPLL Control register-1

EALLOW

Go

14h

SYSPLLMULT

SYSPLL Multiplier register

EALLOW

Go

16h

SYSPLLSTS

SYSPLL Status register

18h

AUXPLLCTL1

AUXPLL Control register-1

EALLOW

Go

1Eh

AUXPLLMULT

AUXPLL Multiplier register

EALLOW

Go

20h

AUXPLLSTS

AUXPLL Status register

22h

SYSCLKDIVSEL

System Clock Divider Select register

EALLOW

Go

24h

AUXCLKDIVSEL

Auxillary Clock Divider Select register

EALLOW

Go

26h

PERCLKDIVSEL

Peripheral Clock Divider Selet register

EALLOW

Go

28h

XCLKOUTDIVSEL

XCLKOUT Divider Select register

EALLOW

Go

2Ch

LOSPCP

Low Speed Clock Source Prescalar

EALLOW

Go

2Eh

MCDCR

Missing Clock Detect Control Register

EALLOW

Go

30h

X1CNT

10-bit Counter on X1 Clock

Go

Go

Go

Complex bit access types are encoded to fit into small table cells. Table 2-148 shows the codes that are
used for access types in this section.
Table 2-148. CLK_CFG_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

323

Registers

www.ti.com

Table 2-148. CLK_CFG_REGS Access Type
Codes (continued)
Access Type
y

324

System Control

Code

Description
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10.1 CLKSEM Register (Offset = 0h) [reset = 0h]
CLKSEM is shown in Figure 2-139 and described in Table 2-149.
Return to Summary Table.
Clock Control Semaphore Register
Figure 2-139. CLKSEM Register
31

30

29

28

27

26

25

24

23
KEY
R=0/W-0h

15

14

13

12

11

10

9
8
RESERVED
R=0-0h

7

22

21

20

19

18

17

16

6

5

4

3

2

1

0

SEM
R/W-0h

Table 2-149. CLKSEM Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

KEY

R=0/W

0h

Writing the value 0xa5a5 will allow the writing of the SEM bits, else
writes are ignored. Reads will return 0.
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: N/A

15-2

RESERVED

R=0

0h

Reserved

1-0

SEM

R/W

0h

This register provides a mechanism to acquire all the CLKCFG
registers (except this register) by CPU1 or CPU2. A CPU can
perform read/writes to any of the CLKCFG registers (except this
register) only if it owns the semaphore. Otherwise, writes are ignored
and reads will return 0x0.
Semaphore State Transitions:
A value of 00, 10, 11 gives ownership to CPU1
A value of 01 gives ownership to CPU2.
The following are the only state transitions allowed on these bits.
00,11 <-> 01 (allowed by CPU2)
00,11 <-> 10 (allowed by CPU1)
If a CPU doesn't own the CLK_CFG_REGS set of registers (as
defined by the state of this semaphore), reads from that CPU to all
those registers return 0x0 and writes are ignore. Note that this is not
true of CLKSEM register. The CLKSEM register's reads and writes
are always allowed from both CPU1 and CPU2.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

325

Registers

www.ti.com

2.15.10.2 CLKCFGLOCK1 Register (Offset = 2h) [reset = 0h]
CLKCFGLOCK1 is shown in Figure 2-140 and described in Table 2-150.
Return to Summary Table.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed
Figure 2-140. CLKCFGLOCK1 Register
31

30

29

28

27

26

25

24

19

18

17

16

13
12
11
PERCLKDIVSE AUXCLKDIVSE SYSCLKDIVSE
L
L
L
R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h

10
AUXPLLMULT

9
RESERVED

8
RESERVED

R/WSOnce-0h

R=0-0h

R=0-0h

5
SYSPLLCTL3
R/WSOnce-0h

2
CLKSRCCTL3
R/WSOnce-0h

1
CLKSRCCTL2
R/WSOnce-0h

0
CLKSRCCTL1
R/WSOnce-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15
LOSPCP

14
RESERVED

R/WSOnce-0h

R=0-0h

7
AUXPLLCTL1
R/WSOnce-0h

6
SYSPLLMULT
R/WSOnce-0h

4
SYSPLLCTL2
R/WSOnce-0h

3
SYSPLLCTL1
R/WSOnce-0h

Table 2-150. CLKCFGLOCK1 Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

LOSPCP

R/WSOnce

0h

Lock bit for LOSPCP register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

14

RESERVED

R=0

0h

Reserved

13

PERCLKDIVSEL

R/WSOnce

0h

Lock bit for PERCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

12

AUXCLKDIVSEL

R/WSOnce

0h

Lock bit for AUXCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

11

SYSCLKDIVSEL

R/WSOnce

0h

Lock bit for SYSCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

10

AUXPLLMULT

R/WSOnce

0h

Lock bit for AUXPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

9

326

RESERVED

System Control

R=0

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-150. CLKCFGLOCK1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8

RESERVED

R=0

0h

Reserved

7

AUXPLLCTL1

R/WSOnce

0h

Lock bit for AUXPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

6

SYSPLLMULT

R/WSOnce

0h

Lock bit for SYSPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

5

SYSPLLCTL3

R/WSOnce

0h

Lock bit for SYSPLLCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

4

SYSPLLCTL2

R/WSOnce

0h

Lock bit for SYSPLLCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

3

SYSPLLCTL1

R/WSOnce

0h

Lock bit for SYSPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

2

CLKSRCCTL3

R/WSOnce

0h

Lock bit for CLKSRCCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

1

CLKSRCCTL2

R/WSOnce

0h

Lock bit for CLKSRCCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

0

CLKSRCCTL1

R/WSOnce

0h

Lock bit for CLKSRCCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

327

Registers

www.ti.com

2.15.10.3 CLKSRCCTL1 Register (Offset = 8h) [reset = 0h]
CLKSRCCTL1 is shown in Figure 2-141 and described in Table 2-151.
Return to Summary Table.
Clock Source Control register-1
Figure 2-141. CLKSRCCTL1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
INTOSC2OFF
R/W-0h

2
RESERVED
R=0-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6
RESERVED
R=0-0h

5
WDHALTI
R/W-0h

4
XTALOFF
R/W-0h

1
0
OSCCLKSRCSEL
R/W-0h

Table 2-151. CLKSRCCTL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-6

RESERVED

R=0

0h

Reserved

WDHALTI

R/W

0h

Watchdog HALT Mode Ignore Bit: This bit determines if CPU1.WD is
functional in the HALT mode or not.

5

0 = CPU1.WD is not functional in the HALT mode. Clock to
CPU1.WD is gated when system enters HALT mode. Additionally,
INTOSC1 and INTOSC2 are powered-down when system enters
HALT mode
1 = CPU1.WD is functional in the HALT mode. Clock to CPU1.WD is
not gated and INTOSC1/2 are not powered-down when system
enters HALT mode
Notes:
[1] Clock to CPU2.WD clocks is always gated in the HALT mode.
Reset type: XRSn
4

XTALOFF

R/W

0h

Crystal (External) Oscillator Off Bit: This bit turns external oscillator
off:
0 = Crystal (External) Oscillator On (default on reset)
1 = Crystal (External) Oscillator Off
NOTE: Ensure no resources are using a clock source prior to
disabling it. For example OSCCLKSRCSEL (SYSPLL),
AUXOSCCLKSRCSEL (AUXPLL), CANxBCLKSEL (CAN Clock),
TMR2CLKSRCSEL (CPUTIMER2) and XCLKOUTSEL(XCLKOUT).
Reset type: XRSn

328

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-151. CLKSRCCTL1 Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

INTOSC2OFF

R/W

0h

Internal Oscillator 2 Off Bit: This bit turns oscillator 2 off:
0 = Internal Oscillator 2 On (default on reset)
1 = Internal Oscillator 2 Off
This bit could be used by the user to turn off the internal oscillator 2
if it is not used.
NOTE: Ensure no resources are using a clock source prior to
disabling it. For example OSCCLKSRCSEL (SYSPLL),
AUXOSCCLKSRCSEL (AUXPLL), TMR2CLKSRCSEL
(CPUTIMER2) and XCLOCKOUT (XCLKOUT).
Reset type: XRSn

2
1-0

RESERVED

R=0

0h

Reserved

OSCCLKSRCSEL

R/W

0h

Oscillator Clock Source Select Bit: This bit selects the source for
OSCCLK.
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = INTOSC1
11 = reserved (default to INTOSC1)
At power-up or after an XRSn, INTOSC2 is selected by default.
Whenever the user changes the clock source using these bits,
the SYSPLLMULT register will be forced to zero and the PLL will
be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the SYSPLLMULT
register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to
SYSPLLMULT
or disabling the previous clock source to allow the change to
complete..
Notes:
[1] Reserved selection defaults to 00 configuration
[2] INTOSC1 is recommended to be used only after missing clock
detection. If user wants to re-lock the PLL with INTOSC1 (the backup clock source) after missing clock is detected, he can do a
MCLKCLR and lock the PLL.
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

329

Registers

www.ti.com

2.15.10.4 CLKSRCCTL2 Register (Offset = Ah) [reset = 0h]
CLKSRCCTL2 is shown in Figure 2-142 and described in Table 2-152.
Return to Summary Table.
Clock Source Control register-2
Figure 2-142. CLKSRCCTL2 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6
RESERVED
R-0h

5

8
RESERVED
R-0h

4
CANBBCLKSEL
R/W-0h

3

2
CANABCLKSEL
R/W-0h

1
0
AUXOSCCLKSRCSEL
R/W-0h

Table 2-152. CLKSRCCTL2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-10

RESERVED

R=0

0h

Reserved

9-8

RESERVED

R

0h

Reserved

7-6

RESERVED

R

0h

Reserved

5-4

CANBBCLKSEL

R/W

0h

CANB Bit-Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn

3-2

CANABCLKSEL

R/W

0h

CANA Bit-Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn

330

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-152. CLKSRCCTL2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

AUXOSCCLKSRCSEL

R/W

0h

Oscillator Clock Source Select Bit: This bit selects the source for
AUXOSCCLK:
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Whenever the user changes the clock source using these bits,
the AUXPLLMULT register will be forced to zero and the PLL will
be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the AUXPLLMULT
register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to
AUXPLLMULT
or disabling the previous clock source to allow the change to
complete.
The missing clock detection circuit does not affect these bits.
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

331

Registers

www.ti.com

2.15.10.5 CLKSRCCTL3 Register (Offset = Ch) [reset = 0h]
CLKSRCCTL3 is shown in Figure 2-143 and described in Table 2-153.
Return to Summary Table.
Clock Source Control register-3
Figure 2-143. CLKSRCCTL3 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
XCLKOUTSEL
R/W-0h

0

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5
RESERVED
R=0-0h

4

Table 2-153. CLKSRCCTL3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-3

RESERVED

R=0

0h

Reserved

2-0

XCLKOUTSEL

R/W

0h

XCLKOUT Source Select Bit: This bit selects the source for
XCLKOUT:
000 = PLLSYSCLK (default on reset)
001 = PLLRAWCLK
010 = CPU1.SYSCLK
011 = CPU2.SYSCLK
100 = AUXPLLRAWCLK
101 = INTOSC1
110 = INTOSC2
111 = Reserved
Reset type: CPU1.SYSRSn

332

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10.6 SYSPLLCTL1 Register (Offset = Eh) [reset = 0h]
SYSPLLCTL1 is shown in Figure 2-144 and described in Table 2-154.
Return to Summary Table.
SYSPLL Control register-1
Figure 2-144. SYSPLLCTL1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
PLLCLKEN
R/W-0h

0
PLLEN
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-154. SYSPLLCTL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

1

PLLCLKEN

R/W

0h

SYSPLL bypassed or included in the PLLSYSCLK path: This bit
decides if the SYSPLL is bypassed when PLLSYSCLK is generated
1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
system.
0 = SYSPLL is bypassed. Clock to system is direct feed from
OSCCLK
Reset type: XRSn

0

PLLEN

R/W

0h

SYSPLL enabled or disabled: This bit decides if the SYSPLL is
enabled or not
1 = SYSPLL is enabled
0 = SYSPLL is powered off. Clock to system is direct feed from
OSCCLK
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

333

Registers

www.ti.com

2.15.10.7 SYSPLLMULT Register (Offset = 14h) [reset = 0h]
SYSPLLMULT is shown in Figure 2-145 and described in Table 2-155.
Return to Summary Table.
SYSPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
Figure 2-145. SYSPLLMULT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R=0-0h

6

5

8
FMULT
R/W-0h

4

3
IMULT
R/W-0h

2

1

0

Table 2-155. SYSPLLMULT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-10

RESERVED

R=0

0h

Reserved

FMULT

R/W

0h

SYSPLL Fractional Multiplier:

9-8

00 Fractional Multiplier = 0
01 Fractional Multiplier = 0.25
10 Fractional Multiplier = 0.5
11 Fractional Multiplier = 0.75
Reset type: XRSn
7
6-0

RESERVED

R=0

0h

Reserved

IMULT

R/W

0h

SYSPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
Reset type: XRSn

334

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10.8 SYSPLLSTS Register (Offset = 16h) [reset = 0h]
SYSPLLSTS is shown in Figure 2-146 and described in Table 2-156.
Return to Summary Table.
SYSPLL Status register
Figure 2-146. SYSPLLSTS Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
SLIPS
R-0h

0
LOCKS
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-156. SYSPLLSTS Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

SLIPS

R

0h

SYSPLL Slip Status Bit: This bit indicates whether the SYSPLL is
out of lock range

1

0 = SYSPLL is not out of lock
1 = SYSPLL is out of loc
The SLIPS bit will only be set on a PLL slip condition after the PLL is
used as the SYSCLK source by seting the
SYSPLLCTL1[PLLCLKEN] bit. Disabling and re-enabling the PLL
with PLLEN is the only way to clear this bit.
Note:
[1] If SYSPLL out of lock condition is detected then interrupts are
fired to CPU1 and CPU2 through their respective ePIE modules.
Software can decide to relock the PLL or switch to PLL bypass mode
in the interrupt handler
Reset type: XRSn
0

LOCKS

R

0h

SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is
locked or not
0 = SYSPLL is not yet locked
1 = SYSPLL is locked
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

335

Registers

www.ti.com

2.15.10.9 AUXPLLCTL1 Register (Offset = 18h) [reset = 0h]
AUXPLLCTL1 is shown in Figure 2-147 and described in Table 2-157.
Return to Summary Table.
AUXPLL Control register-1
Figure 2-147. AUXPLLCTL1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
PLLCLKEN
R/W-0h

0
PLLEN
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-157. AUXPLLCTL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

1

PLLCLKEN

R/W

0h

AUXPLL bypassed or included in the AUXPLLCLK path: This bit
decides if the AUXPLL is bypassed when AUXPLLCLK is generated
1 = AUXPLLCLK is fed from the AUXPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
AUXPLLCLK connected modules.
0 = AUXPLL is bypassed. Clock to modules connected to
AUXPLLCLK is direct feed from AUXOSCCLK
Reset type: XRSn

0

PLLEN

R/W

0h

AUXPLL enabled or disabled: This bit decides if the AUXPLL is
enabled or not
1 = AUXPLL is enabled
0 = AUXPLL is powered off. Clock to system is direct feed from
AUXOSCCLK
Reset type: XRSn

336

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10.10 AUXPLLMULT Register (Offset = 1Eh) [reset = 0h]
AUXPLLMULT is shown in Figure 2-148 and described in Table 2-158.
Return to Summary Table.
AUXPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
Figure 2-148. AUXPLLMULT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R=0-0h

6

5

8
FMULT
R/W-0h

4

3
IMULT
R/W-0h

2

1

0

Table 2-158. AUXPLLMULT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-10

RESERVED

R=0

0h

Reserved

FMULT

R/W

0h

AUXPLL Fractional Multiplier :

9-8

00 Fractional Multiplier = 0
01 Fractional Multiplier = 0.25
10 Fractional Multiplier = 0.5
11 Fractional Multiplier = 0.75
Reset type: XRSn
7
6-0

RESERVED

R=0

0h

Reserved

IMULT

R/W

0h

AUXPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

337

Registers

www.ti.com

2.15.10.11 AUXPLLSTS Register (Offset = 20h) [reset = 0h]
AUXPLLSTS is shown in Figure 2-149 and described in Table 2-159.
Return to Summary Table.
AUXPLL Status register
Figure 2-149. AUXPLLSTS Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
SLIPS
R-0h

0
LOCKS
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-159. AUXPLLSTS Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

SLIPS

R

0h

AUXPLL Slip Status Bit: This bit indicates whether the AUXPLL is
out of lock range

1

0 = AUXPLL is not out of lock
1 = AUXPLL is out of lock
The SLIPS bit will only be set on a PLL slip condition after the PLL is
used as the AUXPLLCLK source by seting the
AUXPLLCTL1[PLLCLKEN] bit. Disabling and re-enabling the PLL
with PLLEN is the only way to clear this bit.
Note:
[1] If AUXPLL out of lock condition is detected then interrupts are
fired to CPU1 and CPU2 through their respective ePIE modules.
Software can decide to relock the PLL or switch to PLL bypass mode
in the interrupt handler
Reset type: XRSn
0

LOCKS

R

0h

AUXPLL Lock Status Bit: This bit indicates whether the AUXPLL is
locked or not
0 = AUXPLL is not yet locked
1 = AUXPLL is locked
Reset type: XRSn

338

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10.12 SYSCLKDIVSEL Register (Offset = 22h) [reset = 2h]
SYSCLKDIVSEL is shown in Figure 2-150 and described in Table 2-160.
Return to Summary Table.
System Clock Divider Select register
Figure 2-150. SYSCLKDIVSEL Register
31

30

29

28

27

26

25

15

14

13

12

11
10
RESERVED
R=0-0h

9

24
23
RESERVED
R=0-0h
8

7

22

21

20

6

5

4

19

18

3
2
PLLSYSCLKDIV
R/W-2h

17

16

1

0

Table 2-160. SYSCLKDIVSEL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-6

RESERVED

R=0

0h

Reserved

5-0

PLLSYSCLKDIV

R/W

2h

PLLSYSCLK Divide Select: This bit selects the divider setting for the
PLLSYSCLK.
000000 = /1
000001 = /2
000010 = /4 (default on reset)
000011 = /6
000100 = /8
......
111111 = /126
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

339

Registers

www.ti.com

2.15.10.13 AUXCLKDIVSEL Register (Offset = 24h) [reset = 1h]
AUXCLKDIVSEL is shown in Figure 2-151 and described in Table 2-161.
Return to Summary Table.
Auxillary Clock Divider Select register
Figure 2-151. AUXCLKDIVSEL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

0
AUXPLLDIV
R/W-1h

Table 2-161. AUXCLKDIVSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

1-0

AUXPLLDIV

R/W

1h

AUXPLLCLK Divide Select: This bit selects the divider setting for the
AUXPLLCK.
00 = /1
01 = /2 (default on reset)
10 = /4
11 = /8
Reset type: XRSn

340

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10.14 PERCLKDIVSEL Register (Offset = 26h) [reset = 51h]
PERCLKDIVSEL is shown in Figure 2-152 and described in Table 2-162.
Return to Summary Table.
Peripheral Clock Divider Selet register
Figure 2-152. PERCLKDIVSEL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R=0-0h

6
EMIF2CLKDIV
R/W-1h

5
RESERVED
R=0-0h

4
EMIF1CLKDIV
R/W-1h

3
RESERVED
R-0h

0
EPWMCLKDIV
R/W-1h

Table 2-162. PERCLKDIVSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-7

RESERVED

R=0

0h

Reserved

EMIF2CLKDIV

R/W

1h

EMIF2 Clock Divide Select: This bit selects whether the EMIF2
module run with a /1 or /2 clock.

6

0: /1 of CPU1.SYSCLK is selected
1: /2 of CPU1.SYSCLK is selected
Reset type: CPU1.SYSRSn
5

RESERVED

R=0

0h

Reserved

4

EMIF1CLKDIV

R/W

1h

EMIF1 Clock Divide Select: This bit selects whether the EMIF1
module run with a /1 or /2 clock.
For single core device
0: /1 of CPU1.SYSCLK is selected
1: /2 of CPU1.SYSCLK is selected
For Dual core device
0: /1 of PLLSYSCLK is selected
1: /2 of PLLSYSCLK is selected
Reset type: CPU1.SYSRSn

3-2

RESERVED

R

0h

Reserved

1-0

EPWMCLKDIV

R/W

1h

EPWM Clock Divide Select: This bit selects whether the EPWM
modules run with a /1 or /2 clock. This divider sits in front of the
PLLSYSCLK
x0 = /1 of PLLSYSCLK
x1 = /2 of PLLSYSLCK (default on reset)
Note: Refer to your device specific datasheet for maximum EPWM
Frequency
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

341

Registers

www.ti.com

2.15.10.15 XCLKOUTDIVSEL Register (Offset = 28h) [reset = 3h]
XCLKOUTDIVSEL is shown in Figure 2-153 and described in Table 2-163.
Return to Summary Table.
XCLKOUT Divider Select register
Figure 2-153. XCLKOUTDIVSEL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

0
XCLKOUTDIV
R/W-3h

Table 2-163. XCLKOUTDIVSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

1-0

XCLKOUTDIV

R/W

3h

XCLKOUT Divide Select: This bit selects the divider setting for the
XCLKOUT.
00 = /1
01 = /2
10 = /4
11 = /8 (default on reset)
Reset type: CPU1.SYSRSn

342

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10.16 LOSPCP Register (Offset = 2Ch) [reset = 2h]
LOSPCP is shown in Figure 2-154 and described in Table 2-164.
Return to Summary Table.
Low Speed Clock Source Prescalar
Figure 2-154. LOSPCP Register
31

30

29

28

27

26

15

14

13

12

11

10

25

24
23
RESERVED
R=0-0h

9
8
RESERVED
R=0-0h

7

22

21

20

19

18

6

5

4

3

2

17

16

1
0
LSPCLKDIV
R/W-2h

Table 2-164. LOSPCP Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-3

RESERVED

R=0

0h

Reserved

2-0

LSPCLKDIV

R/W

2h

These bits configure the low-speed peripheral clock (LSPCLK) rate
relative to SYSCLK of CPU1 and CPU2.
000,LSPCLK = / 1
001,LSPCLK = / 2
010,LSPCLK = / 4 (default on reset)
011,LSPCLK = / 6
100,LSPCLK = / 8
101,LSPCLK = / 10
110,LSPCLK = / 12
111,LSPCLK = / 14
Note:
[1] This clock is used as strobe for the SCI and SPI modules.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

343

Registers

www.ti.com

2.15.10.17 MCDCR Register (Offset = 2Eh) [reset = 0h]
MCDCR is shown in Figure 2-155 and described in Table 2-165.
Return to Summary Table.
Missing Clock Detect Control Register
Figure 2-155. MCDCR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
OSCOFF
R/W-0h

2
MCLKOFF
R/W-0h

1
MCLKCLR
R=0/W=1-0h

0
MCLKSTS
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-165. MCDCR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

OSCOFF

R/W

0h

Oscillator Clock Off Bit:

3

0 = OSCCLK Connected to OSCCLK Counter in MCD module
1 = OSCCLK Disconnected to OSCCLK Counter in MCD module
Reset type: XRSn
2

MCLKOFF

R/W

0h

Missing Clock Detect Off Bit:
0 = Missing Clock Detect Circuit Enabled
1 = Missing Clock Detect Circuit Disabled
Reset type: XRSn

1

MCLKCLR

R=0/W=1

0h

Missing Clock Clear Bit:
Write 1" to this bit to clear MCLKSTS bit and reset the missing clock
detect circuit."
Reset type: XRSn

0

MCLKSTS

R

0h

Missing Clock Status Bit:
0 = OSCCLK Is OK
1 = OSCCLK Detected Missing, CLOCKFAILn Generated
Reset type: XRSn

344

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.10.18 X1CNT Register (Offset = 30h) [reset = 0h]
X1CNT is shown in Figure 2-156 and described in Table 2-166.
Return to Summary Table.
10-bit Counter on X1 Clock
Figure 2-156. X1CNT Register
31

30

29

28

27

26

25

15

14

13
12
RESERVED
R=0-0h

11

10

9

24
23
RESERVED
R=0-0h
8

7

22

21

20

19

18

17

16

6

5

4

3

2

1

0

X1CNT
R-0h

Table 2-166. X1CNT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-10

RESERVED

R=0

0h

Reserved

X1CNT

R

0h

X1 Counter:

9-0

- This counter increments on every X1 CLOCKs positive-edge.
- Once it reaches the values of 0x3ff, it freezes
- Before switching from INTOSC2 to X1, application must check this
counter and make sure that it has saturated. This will guarantee that
the Crystal connected to X1/X2 is powered Up.
Reset type: PORn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

345

Registers

www.ti.com

2.15.11 CPU_SYS_REGS Registers
Table 2-167 lists the memory-mapped registers for the CPU_SYS_REGS. All register offset addresses not
listed in Table 2-167 should be considered as reserved locations and the register contents should not be
modified.
Table 2-167. CPU_SYS_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

CPUSYSLOCK1

Lock bit for CPUSYS registers

EALLOW

Go

6h

HIBBOOTMODE

HIB Boot Mode Register

EALLOW

Go

8h

IORESTOREADDR

IORestore() routine Address Register

EALLOW

Go

Ah

PIEVERRADDR

PIE Vector Fetch Error Address register

EALLOW

Go

22h

PCLKCR0

Peripheral Clock Gating Registers

EALLOW

Go

24h

PCLKCR1

Peripheral Clock Gating Registers

EALLOW

Go

26h

PCLKCR2

Peripheral Clock Gating Registers

EALLOW

Go

28h

PCLKCR3

Peripheral Clock Gating Registers

EALLOW

Go

2Ah

PCLKCR4

Peripheral Clock Gating Registers

EALLOW

Go

2Eh

PCLKCR6

Peripheral Clock Gating Registers

EALLOW

Go

30h

PCLKCR7

Peripheral Clock Gating Registers

EALLOW

Go

32h

PCLKCR8

Peripheral Clock Gating Registers

EALLOW

Go

34h

PCLKCR9

Peripheral Clock Gating Registers

EALLOW

Go

36h

PCLKCR10

Peripheral Clock Gating Registers

EALLOW

Go

38h

PCLKCR11

Peripheral Clock Gating Registers

EALLOW

Go

3Ah

PCLKCR12

Peripheral Clock Gating Registers

EALLOW

Go

3Ch

PCLKCR13

Peripheral Clock Gating Registers

EALLOW

Go

3Eh

PCLKCR14

Peripheral Clock Gating Registers

EALLOW

Go

42h

PCLKCR16

Peripheral Clock Gating Registers

EALLOW

Go

74h

SECMSEL_1

Secondary Master Select register for common
peripherals: Selects between CLA & DMA

EALLOW

Go

76h

LPMCR

LPM Control Register

EALLOW

Go

78h

GPIOLPMSEL0

GPIO LPM Wakeup select registers

EALLOW

Go

7Ah

GPIOLPMSEL1

GPIO LPM Wakeup select registers

EALLOW

Go

7Ch

TMR2CLKCTL

Timer2 Clock Measurement functionality control
register

EALLOW

Go

80h

RESC

Reset Cause register

Go

Complex bit access types are encoded to fit into small table cells. Table 2-168 shows the codes that are
used for access types in this section.
Table 2-168. CPU_SYS_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

346

System Control

Value after reset or the default
value

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-168. CPU_SYS_REGS Access Type
Codes (continued)
Access Type

Code

Description

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

347

Registers

www.ti.com

2.15.11.1 CPUSYSLOCK1 Register (Offset = 0h) [reset = 0h]
CPUSYSLOCK1 is shown in Figure 2-157 and described in Table 2-169.
Return to Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed
Figure 2-157. CPUSYSLOCK1 Register
31

30

29

28

27

26

25

24

RESERVED
R=0-0h
23
22
GPIOLPMSEL1 GPIOLPMSEL0
R/WSOnce-0h R/WSOnce-0h

21
LPMCR
R/WSOnce-0h

20
SECMSEL
R/WSOnce-0h

19
PCLKCR16
R/WSOnce-0h

18
PCLKCR15
R/WSOnce-0h

17
PCLKCR14
R/WSOnce-0h

16
PCLKCR13
R/WSOnce-0h

15
PCLKCR12
R/WSOnce-0h

14
PCLKCR11
R/WSOnce-0h

13
PCLKCR10
R/WSOnce-0h

12
PCLKCR9
R/WSOnce-0h

11
PCLKCR8
R/WSOnce-0h

10
PCLKCR7
R/WSOnce-0h

9
PCLKCR6
R/WSOnce-0h

8
PCLKCR5
R/WSOnce-0h

7
PCLKCR4

6
PCLKCR3

5
PCLKCR2

4
PCLKCR1

3
PCLKCR0

R/WSOnce-0h

R/WSOnce-0h

R/WSOnce-0h

R/WSOnce-0h

R/WSOnce-0h

2
PIEVERRADD
R
R/WSOnce-0h

1
IORESTOREA
DDR
R/WSOnce-0h

0
HIBBOOTMOD
E
R/WSOnce-0h

Table 2-169. CPUSYSLOCK1 Register Field Descriptions
Bit
31-24
23

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

GPIOLPMSEL1

R/WSOnce

0h

Lock bit for GPIOLPMSEL1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

22

GPIOLPMSEL0

R/WSOnce

0h

Lock bit for GPIOLPMSEL0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

21

LPMCR

R/WSOnce

0h

Lock bit for LPMCR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

20

SECMSEL

R/WSOnce

0h

Lock bit for SECMSEL Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

19

PCLKCR16

R/WSOnce

0h

Lock bit for PCLKCR16 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

348

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-169. CPUSYSLOCK1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

18

PCLKCR15

R/WSOnce

0h

Lock bit for PCLKCR15 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

17

PCLKCR14

R/WSOnce

0h

Lock bit for PCLKCR14 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

16

PCLKCR13

R/WSOnce

0h

Lock bit for PCLKCR13 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

15

PCLKCR12

R/WSOnce

0h

Lock bit for PCLKCR12 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

14

PCLKCR11

R/WSOnce

0h

Lock bit for PCLKCR11 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

13

PCLKCR10

R/WSOnce

0h

Lock bit for PCLKCR10 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

12

PCLKCR9

R/WSOnce

0h

Lock bit for PCLKCR9 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

11

PCLKCR8

R/WSOnce

0h

Lock bit for PCLKCR8 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

10

PCLKCR7

R/WSOnce

0h

Lock bit for PCLKCR7 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

9

PCLKCR6

R/WSOnce

0h

Lock bit for PCLKCR6 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

349

Registers

www.ti.com

Table 2-169. CPUSYSLOCK1 Register Field Descriptions (continued)
Bit
8

Field

Type

Reset

Description

PCLKCR5

R/WSOnce

0h

Lock bit for PCLKCR5 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

7

PCLKCR4

R/WSOnce

0h

Lock bit for PCLKCR4 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

6

PCLKCR3

R/WSOnce

0h

Lock bit for PCLKCR3 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

5

PCLKCR2

R/WSOnce

0h

Lock bit for PCLKCR2 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

4

PCLKCR1

R/WSOnce

0h

Lock bit for PCLKCR1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

3

PCLKCR0

R/WSOnce

0h

Lock bit for PCLKCR0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

2

PIEVERRADDR

R/WSOnce

0h

Lock bit for PIEVERRADDR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

1

IORESTOREADDR

R/WSOnce

0h

Lock bit for IORESTOREADDR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

0

HIBBOOTMODE

R/WSOnce

0h

Lock bit for HIBBOOTMODE register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

350

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.2 HIBBOOTMODE Register (Offset = 6h) [reset = Fh]
HIBBOOTMODE is shown in Figure 2-158 and described in Table 2-170.
Return to Summary Table.
HIB Boot Mode Register
Figure 2-158. HIBBOOTMODE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BMODE
R/W-Fh

9

8

7

6

5

4

3

2

1

0

Table 2-170. HIBBOOTMODE Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

BMODE

R/W

Fh

This register defined the boot mode on a HIB Wakeup. Its the
responsibility of user to initialize the appropriate boot mode before
going into HIB mode. Refer to the Boot ROM section for more details
on this register
Reset type: PORn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

351

Registers

www.ti.com

2.15.11.3 IORESTOREADDR Register (Offset = 8h) [reset = 003FFFFFh]
IORESTOREADDR is shown in Figure 2-159 and described in Table 2-171.
Return to Summary Table.
IORestore() routine Address Register
Figure 2-159. IORESTOREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
RESERVED
ADDR
R=0-0h
R/W-003FFFFFh

7

6

5

4

3

2

1

0

Table 2-171. IORESTOREADDR Register Field Descriptions
Bit

352

Field

Type

Reset

Description

31-22

RESERVED

R=0

0h

Reserved

21-0

ADDR

R/W

003FFFFFh

This register defines the address of the restoreIO() routine on a HIB
wakeup. Its the responsibility of user to initialize this register with the
restoreIO() routine address before going into HIB mode. Refer to the
Boot ROM section for more details on this register.
Reset type: PORn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.4 PIEVERRADDR Register (Offset = Ah) [reset = 003FFFFFh]
PIEVERRADDR is shown in Figure 2-160 and described in Table 2-172.
Return to Summary Table.
PIE Vector Fetch Error Address register
Figure 2-160. PIEVERRADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
RESERVED
ADDR
R=0-0h
R/W-003FFFFFh

7

6

5

4

3

2

1

0

Table 2-172. PIEVERRADDR Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

RESERVED

R=0

0h

Reserved

21-0

ADDR

R/W

003FFFFFh

This register defines the address of the PIE Vector Fetch Error
handler routine. Its the responsibility of user to initialize this register.
If this register is not initialized, a default error handler at address
0x3fffbe will get executed. Refer to the Boot ROM section for more
details on this register.
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

353

Registers

www.ti.com

2.15.11.5 PCLKCR0 Register (Offset = 22h) [reset = 38h]
PCLKCR0 is shown in Figure 2-161 and described in Table 2-173.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-161. PCLKCR0 Register
31

30

29

28

27

26

25

24

19
GTBCLKSYNC
R/W-0h

18
TBCLKSYNC
R/W-0h

17
RESERVED
R=0-0h

16
HRPWM
R/W-0h

11

10

9

8

3
CPUTIMER0
R/W-1h

2
DMA
R/W-0h

1
RESERVED
R-0h

0
CLA1
R/W-0h

RESERVED
R=0-0h
23

22

21

20

13

12

RESERVED
R=0-0h
15

14

RESERVED
R=0-0h
7

6
RESERVED
R=0-0h

5
CPUTIMER2
R/W-1h

4
CPUTIMER1
R/W-1h

Table 2-173. PCLKCR0 Register Field Descriptions
Bit
31-20
19

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

GTBCLKSYNC

R/W

0h

EPWM Time Base Clock Global sync: When set by CPU1, PWM
time bases of all modules start counting. The effect of this bit is seen
on all the EPMW modules irrespective of their partitioning based on
CPUSEL
Notes:
1. This bit on the CPU2.PCLKCR0 register has no effect.
2. Writing '1' to this bit overrides the effect of write '1' to the
TBCLKSYNC bit at the same time
Reset type: SYSRSn

18

TBCLKSYNC

R/W

0h

EPWM Time Base Clock sync: When set PWM time bases of all the
PWM modules belonging to the same CPU-Subsystem (as
partitioned using their CPUSEL bits) start counting
Notes:
1. This bit from CPU1.PCLKCR0 or CPU2.PCLKCR0 is selected and
fed to the individual EPWM modules based on their respective
CPUSEL bit.
Reset type: SYSRSn

17

RESERVED

R=0

0h

Reserved

16

HRPWM

R/W

0h

HRPWM Clock Enable Bit: When set, this enables the clock to the
HRPWM module
1: HRPWM clock is enabled
0: HRPWM clock is disabled
Note:
[1] This bit is present only in CPU1.PCLKCR0. This bit is not used
(R/W) in CPU2.PCLKCR0
Reset type: SYSRSn

15-6

354

RESERVED

System Control

R=0

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-173. PCLKCR0 Register Field Descriptions (continued)
Bit
5

Field

Type

Reset

Description

CPUTIMER2

R/W

1h

CPUTIMER2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

4

CPUTIMER1

R/W

1h

CPUTIMER1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

3

CPUTIMER0

R/W

1h

CPUTIMER0 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

2

DMA

R/W

0h

DMA Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

1

RESERVED

R

0h

Reserved

0

CLA1

R/W

0h

CLA1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

355

Registers

www.ti.com

2.15.11.6 PCLKCR1 Register (Offset = 24h) [reset = 0h]
PCLKCR1 is shown in Figure 2-162 and described in Table 2-174.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-162. PCLKCR1 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
EMIF2
R/W-0h

0
EMIF1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-174. PCLKCR1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

EMIF2

R/W

0h

EMIF2 Clock Enable bit:

1

0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn
0

EMIF1

R/W

0h

EMIF1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn

356

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.7 PCLKCR2 Register (Offset = 26h) [reset = 0h]
PCLKCR2 is shown in Figure 2-163 and described in Table 2-175.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-163. PCLKCR2 Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
EPWM12
R/W-0h

10
EPWM11
R/W-0h

9
EPWM10
R/W-0h

8
EPWM9
R/W-0h

7
EPWM8
R/W-0h

6
EPWM7
R/W-0h

5
EPWM6
R/W-0h

4
EPWM5
R/W-0h

3
EPWM4
R/W-0h

2
EPWM3
R/W-0h

1
EPWM2
R/W-0h

0
EPWM1
R/W-0h

Table 2-175. PCLKCR2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

EPWM12

R/W

0h

EPWM12 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

10

EPWM11

R/W

0h

EPWM11 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

9

EPWM10

R/W

0h

EPWM10 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

8

EPWM9

R/W

0h

EPWM9 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

7

EPWM8

R/W

0h

EPWM8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

357

Registers

www.ti.com

Table 2-175. PCLKCR2 Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

EPWM7

R/W

0h

EPWM7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

5

EPWM6

R/W

0h

EPWM6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

4

EPWM5

R/W

0h

EPWM5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

3

EPWM4

R/W

0h

EPWM4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

2

EPWM3

R/W

0h

EPWM3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

1

EPWM2

R/W

0h

EPWM2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

EPWM1

R/W

0h

EPWM1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

358

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.8 PCLKCR3 Register (Offset = 28h) [reset = 0h]
PCLKCR3 is shown in Figure 2-164 and described in Table 2-176.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-164. PCLKCR3 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
ECAP4
R/W-0h

2
ECAP3
R/W-0h

1
ECAP2
R/W-0h

0
ECAP1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
RESERVED
R-0h

6
RESERVED
R-0h

5
ECAP6
R/W-0h

4
ECAP5
R/W-0h

Table 2-176. PCLKCR3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

ECAP6

R/W

0h

ECAP6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

4

ECAP5

R/W

0h

ECAP5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

3

ECAP4

R/W

0h

ECAP4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

2

ECAP3

R/W

0h

ECAP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

1

ECAP2

R/W

0h

ECAP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

359

Registers

www.ti.com

Table 2-176. PCLKCR3 Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

ECAP1

R/W

0h

ECAP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

360

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.9 PCLKCR4 Register (Offset = 2Ah) [reset = 0h]
PCLKCR4 is shown in Figure 2-165 and described in Table 2-177.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-165. PCLKCR4 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
EQEP3
R/W-0h

1
EQEP2
R/W-0h

0
EQEP1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-177. PCLKCR4 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

EQEP3

R/W

0h

EQEP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

1

EQEP2

R/W

0h

EQEP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

EQEP1

R/W

0h

EQEP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

361

Registers

www.ti.com

2.15.11.10 PCLKCR6 Register (Offset = 2Eh) [reset = 0h]
PCLKCR6 is shown in Figure 2-166 and described in Table 2-178.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-166. PCLKCR6 Register
31

30

29

28

27

26

25

15

14

13

12
11
RESERVED

10

9

R=0-0h

24
23
RESERVED
R=0-0h
8

7
RESE
RVED
R-0h

22

21

20

19

18

17

16

6
RESE
RVED
R-0h

5
RESE
RVED
R-0h

4
RESE
RVED
R-0h

3
RESE
RVED
R-0h

2
RESE
RVED
R-0h

1
SD2

0
SD1

R/W0h

R/W0h

Table 2-178. PCLKCR6 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

SD2

R/W

0h

SD2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

SD1

R/W

0h

SD1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

362

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.11 PCLKCR7 Register (Offset = 30h) [reset = 0h]
PCLKCR7 is shown in Figure 2-167 and described in Table 2-179.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-167. PCLKCR7 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
SCI_D
R/W-0h

2
SCI_C
R/W-0h

1
SCI_B
R/W-0h

0
SCI_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-179. PCLKCR7 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

SCI_D

R/W

0h

SCI_D Clock Enable bit:

3

0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2

SCI_C

R/W

0h

SCI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

1

SCI_B

R/W

0h

SCI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

SCI_A

R/W

0h

SCI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

363

Registers

www.ti.com

2.15.11.12 PCLKCR8 Register (Offset = 32h) [reset = 0h]
PCLKCR8 is shown in Figure 2-168 and described in Table 2-180.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-168. PCLKCR8 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
RESERVED
R-0h

11

10

9

8

3
RESERVED
R-0h

2
SPI_C
R/W-0h

1
SPI_B
R/W-0h

0
SPI_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-180. PCLKCR8 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

SPI_C

R/W

0h

SPI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

1

SPI_B

R/W

0h

SPI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

SPI_A

R/W

0h

SPI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

364

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.13 PCLKCR9 Register (Offset = 34h) [reset = 0h]
PCLKCR9 is shown in Figure 2-169 and described in Table 2-181.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-169. PCLKCR9 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
RESERVED
R-0h

11

10

9

8

3

2

1
I2C_B
R/W-0h

0
I2C_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-181. PCLKCR9 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

I2C_B

R/W

0h

I2C_B Clock Enable bit:

1

0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0

I2C_A

R/W

0h

I2C_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

365

Registers

www.ti.com

2.15.11.14 PCLKCR10 Register (Offset = 36h) [reset = 0h]
PCLKCR10 is shown in Figure 2-170 and described in Table 2-182.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-170. PCLKCR10 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
RESERVED
R-0h

1
CAN_B
R/W-0h

0
CAN_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-182. PCLKCR10 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

CAN_B

R/W

0h

CAN_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

CAN_A

R/W

0h

CAN_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

366

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.15 PCLKCR11 Register (Offset = 38h) [reset = 0h]
PCLKCR11 is shown in Figure 2-171 and described in Table 2-183.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-171. PCLKCR11 Register
31

30

29

28

27

26

25

24

19

18

17
RESERVED
R-0h

16
USB_A
R/W-0h

11

10

9

8

3

2

1
McBSP_B
R/W-0h

0
McBSP_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-183. PCLKCR11 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R=0

0h

Reserved

17

RESERVED

R

0h

Reserved

16

USB_A

R/W

0h

USB_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] This bit is not used (R/W) in CPU2.PCLKCR11 register. USB_A
clock enabled is controlled only from CPU1.PCLKCR11 register
Reset type: SYSRSn

15-2
1

RESERVED

R=0

0h

Reserved

McBSP_B

R/W

0h

McBSP_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

McBSP_A

R/W

0h

McBSP_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

367

Registers

www.ti.com

2.15.11.16 PCLKCR12 Register (Offset = 3Ah) [reset = 0h]
PCLKCR12 is shown in Figure 2-172 and described in Table 2-184.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-172. PCLKCR12 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
RESERVED
R-0h

0
uPP_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 2-184. PCLKCR12 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

1

RESERVED

R

0h

Reserved

0

uPP_A

R/W

0h

uPP_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1]] This bit also affects the uPP message RAM wrapper associated
with the respective uPP module
[2] This bit is not used (R/W) in CPU2.PCLKCR12 register. UPP_A
clock enabled is controlled only from CPU1.PCLKCR12 register
Reset type: SYSRSn

368

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.17 PCLKCR13 Register (Offset = 3Ch) [reset = 0h]
PCLKCR13 is shown in Figure 2-173 and described in Table 2-185.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-173. PCLKCR13 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
ADC_D
R/W-0h

2
ADC_C
R/W-0h

1
ADC_B
R/W-0h

0
ADC_A
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

RESERVED
R=0-0h

Table 2-185. PCLKCR13 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-4

RESERVED

R=0

0h

Reserved

ADC_D

R/W

0h

ADC_D Clock Enable bit:

3

0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2

ADC_C

R/W

0h

ADC_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

1

ADC_B

R/W

0h

ADC_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

ADC_A

R/W

0h

ADC_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

369

Registers

www.ti.com

2.15.11.18 PCLKCR14 Register (Offset = 3Eh) [reset = 0h]
PCLKCR14 is shown in Figure 2-174 and described in Table 2-186.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-174. PCLKCR14 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
CMPSS4
R/W-0h

2
CMPSS3
R/W-0h

1
CMPSS2
R/W-0h

0
CMPSS1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
CMPSS8
R/W-0h

6
CMPSS7
R/W-0h

5
CMPSS6
R/W-0h

4
CMPSS5
R/W-0h

Table 2-186. PCLKCR14 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

CMPSS8

R/W

0h

CMPSS8 Clock Enable bit:

7

0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6

CMPSS7

R/W

0h

CMPSS7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

5

CMPSS6

R/W

0h

CMPSS6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

4

CMPSS5

R/W

0h

CMPSS5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

3

CMPSS4

R/W

0h

CMPSS4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

2

CMPSS3

R/W

0h

CMPSS3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

370

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-186. PCLKCR14 Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

CMPSS2

R/W

0h

CMPSS2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

0

CMPSS1

R/W

0h

CMPSS1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

371

Registers

www.ti.com

2.15.11.19 PCLKCR16 Register (Offset = 42h) [reset = 0h]
PCLKCR16 is shown in Figure 2-175 and described in Table 2-187.
Return to Summary Table.
Peripheral Clock Gating Registers
Figure 2-175. PCLKCR16 Register
31

30

29

28

27

26

25

24

19
RESERVED
R-0h

18
DAC_C
R/W-0h

17
DAC_B
R/W-0h

16
DAC_A
R/W-0h

11

10

9

8

3
RESERVED
R-0h

2
RESERVED
R-0h

1
RESERVED
R-0h

0
RESERVED
R-0h

RESERVED
R=0-0h
23

22

21

20

13

12

RESERVED
R=0-0h
15

14

RESERVED
R=0-0h
7

6

5

4

RESERVED
R=0-0h

Table 2-187. PCLKCR16 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

RESERVED

R=0

0h

Reserved

19

RESERVED

R

0h

Reserved

18

DAC_C

R/W

0h

Buffered_DAC_C Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

17

DAC_B

R/W

0h

Buffered_DAC_B Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

16

DAC_A

R/W

0h

Buffered_DAC_A Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

372

15-4

RESERVED

R=0

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.20 SECMSEL_1 Register (Offset = 74h) [reset = 0h]
SECMSEL_1 is shown in Figure 2-176 and described in Table 2-188.
Return to Summary Table.
Secondary Master Select register for common peripherals: Selects between CLA & DMA
Figure 2-176. SECMSEL_1 Register
31

30

29

28

27

26

25

24

19

18

17

16

10

9

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

RESERVED
R=0-0h
7

12

11

RESERVED
R-0h
6

5

RESERVED
R-0h

RESERVED
R-0h
4

3

RESERVED
R-0h

8
RESERVED
R-0h

2
PF2SEL
R/W-0h

1

0
PF1SEL
R/W-0h

Table 2-188. SECMSEL_1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-14

RESERVED

R=0

0h

Reserved

13-12

RESERVED

R

0h

Reserved

11-10

RESERVED

R

0h

Reserved

9-8

RESERVED

R

0h

Reserved

7-6

RESERVED

R

0h

Reserved

5-4

RESERVED

R

0h

Reserved

3-2

PF2SEL

R/W

0h

This bit selects whether the dual ported bridge is connected with
DMA or CLA as the secondary master (C28x is always connected as
primary master)
x0: Bridge is connected to CLA
x1: Bridge is connected to DMA
Reset type: SYSRSn

1-0

PF1SEL

R/W

0h

This bit selects whether the dual ported bridge is connected with
DMA or CLA as the secondary master (C28x is always connected as
primary master)
x0: Bridge is connected to CLA
x1: Bridge is connected to DMA
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

373

Registers

www.ti.com

2.15.11.21 LPMCR Register (Offset = 76h) [reset = FCh]
LPMCR is shown in Figure 2-177 and described in Table 2-189.
Return to Summary Table.
LPM Control Register
Figure 2-177. LPMCR Register
31
IOISODIS
R/W=1-0h

30

29

23

22

21

28

27
RESERVED
R=0-0h

26

25

20

19

18

17

RESERVED
R=0-0h
15
WDINTE
R/W-0h

14

13

7

6

5

24

16
M0M1MODE
R/W-0h

12

11
RESERVED
R=0-0h

10

9

4

3

2

1

QUALSTDBY
R/W-3Fh

8

0
LPM
R/W-0h

Table 2-189. LPMCR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IOISODIS

R/W=1

0h

0: Indicates IO ISOLATION is not turned ON
1: Indicates IO ISOLATION is turned ON. This bit is set one by
hardware ONLY during HIB. This bit cant be set to 1 by software
Writing 0 to this bit has not effect.
Writing 1 to this bit deactivates IO ISOLATION
Notes:
[1] This bit is reserved in the register mapped to CPU2
Reset type: raw-XRSn

30-18

RESERVED

R=0

0h

Reserved

17-16

M0M1MODE

R/W

0h

These bit control the state of CPU1's and CPU2's M0 & M1
memories when Device goes into HIB mode.
00: CPUx's M0 & M1 memories ON with low-leakage mode
01: CPUx's M0 & M1 memories OFF
1x: Reserved
Notes:
[1] Low-leakage mode for M0 & M1 memories uses the "Retention"
feature of the SRAMs.
[2] These bits take effect only when device goes into HIB mode. If
the device is not in HIB mode, the value in this bit doesn't control the
state of CPU1's and CPU2's M0 & M1 memories
Reset type: PORn

15

WDINTE

R/W

0h

When this bit is set to 1, it enables the watchdog interrupt signal to
wake the device from STANDBY mode.
Note:
[1] To use this signal, the user must also enable the WDINTn signal
using the WDENINT bit in the SCSR register. This signal will not
wake the device from HALT mode because the clock to watchdog
module is turned off
Reset type: SYSRSn

14-8
374

RESERVED

System Control

R=0

0h

Reserved
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-189. LPMCR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-2

QUALSTDBY

R/W

3Fh

Select number of OSCCLK clock cycles to qualify the selected inputs
when waking the from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
......
111111 = 65 OSCCLKs
Note: The LPMCR.QUALSTDBY register should be set to a value
greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper
wake up.
Reset type: SYSRSn

1-0

LPM

R/W

0h

These bits set the low power mode for the device. Takes effect when
CPU executes the IDLE instruction (when IDLE instruction is out of
EXE Phase of the Pipeline)
00: IDLE Mode
01: STANDBY Mode
10: HALT Mode (treated as STANDBY for CPU2)
11: HIB Mode (treated as STANDBY for CPU2)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

375

Registers

www.ti.com

2.15.11.22 GPIOLPMSEL0 Register (Offset = 78h) [reset = 0h]
GPIOLPMSEL0 is shown in Figure 2-178 and described in Table 2-190.
Return to Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities
of the selected pin.
Figure 2-178. GPIOLPMSEL0 Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23
R/W-0h

22
GPIO22
R/W-0h

21
GPIO21
R/W-0h

20
GPIO20
R/W-0h

19
GPIO19
R/W-0h

18
GPIO18
R/W-0h

17
GPIO17
R/W-0h

16
GPIO16
R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 2-190. GPIOLPMSEL0 Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

30

GPIO30

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

29

GPIO29

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

28

GPIO28

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

27

GPIO27

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

26

GPIO26

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

25

GPIO25

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

24

GPIO24

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

376

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-190. GPIOLPMSEL0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

23

GPIO23

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

22

GPIO22

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

21

GPIO21

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

20

GPIO20

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

19

GPIO19

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

18

GPIO18

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

17

GPIO17

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

16

GPIO16

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

15

GPIO15

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

14

GPIO14

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

13

GPIO13

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

12

GPIO12

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

11

GPIO11

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

10

GPIO10

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

9

GPIO9

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

8

GPIO8

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

377

Registers

www.ti.com

Table 2-190. GPIOLPMSEL0 Register Field Descriptions (continued)
Bit
7

Field

Type

Reset

Description

GPIO7

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

6

GPIO6

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

5

GPIO5

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

4

GPIO4

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

3

GPIO3

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

2

GPIO2

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

1

GPIO1

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

0

GPIO0

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

378

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.11.23 GPIOLPMSEL1 Register (Offset = 7Ah) [reset = 0h]
GPIOLPMSEL1 is shown in Figure 2-179 and described in Table 2-191.
Return to Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities
of the selected pin.
Figure 2-179. GPIOLPMSEL1 Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55
R/W-0h

22
GPIO54
R/W-0h

21
GPIO53
R/W-0h

20
GPIO52
R/W-0h

19
GPIO51
R/W-0h

18
GPIO50
R/W-0h

17
GPIO49
R/W-0h

16
GPIO48
R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 2-191. GPIOLPMSEL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

30

GPIO62

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

29

GPIO61

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

28

GPIO60

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

27

GPIO59

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

26

GPIO58

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

25

GPIO57

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

24

GPIO56

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

379

Registers

www.ti.com

Table 2-191. GPIOLPMSEL1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

23

GPIO55

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

22

GPIO54

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

21

GPIO53

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

20

GPIO52

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

19

GPIO51

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

18

GPIO50

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

17

GPIO49

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

16

GPIO48

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

15

GPIO47

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

14

GPIO46

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

13

GPIO45

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

12

GPIO44

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

11

GPIO43

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

10

GPIO42

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

9

GPIO41

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

8

GPIO40

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

380

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-191. GPIOLPMSEL1 Register Field Descriptions (continued)
Bit
7

Field

Type

Reset

Description

GPIO39

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

6

GPIO38

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

5

GPIO37

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

4

GPIO36

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

3

GPIO35

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

2

GPIO34

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

1

GPIO33

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

0

GPIO32

R/W

0h

0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

381

Registers

www.ti.com

2.15.11.24 TMR2CLKCTL Register (Offset = 7Ch) [reset = 0h]
TMR2CLKCTL is shown in Figure 2-180 and described in Table 2-192.
Return to Summary Table.
Timer2 Clock Measurement functionality control register
Figure 2-180. TMR2CLKCTL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
TMR2CLKSRCSEL
R/W-0h

0

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
TMR2CLKPRESCALE
R/W-0h

RESERVED
R=0-0h

Table 2-192. TMR2CLKCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-6

RESERVED

R=0

0h

Reserved

5-3

TMR2CLKPRESCALE

R/W

0h

CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale
value for the selected clock source for CPU Timer 2:
0,0,0,/1 (default on reset)
0,0,1,/2,
0,1,0,/4
0,1,1,/8
1,0,0,/16
1,0,1,spare (defaults to /16)
1,1,0,spare (defaults to /16)
1,1,1,spare (defaults to /16)
Note:
[1] The CPU Timer2s Clock sync logic detects an input clock edge
when configured for any clock source other than SYSCLK and
generates an appropriate clock pulse to the CPU timer2. If SYSCLK
is approximately the same or less then the input clock source, then
the user would need to configure the pre-scale value such that
SYSCLK is at least twice as fast as the pre-scaled value.
[2] Pre-scaler is bypassed if SYSCLK is selected as the source of
CPU Timer 2 in TMR2CLKSRCSEL of TMR2CLKCTL.
Reset type: SYSRSn

382

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-192. TMR2CLKCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2-0

TMR2CLKSRCSEL

R/W

0h

CPU Timer 2 Clock Source Select Bit: This bit selects the source for
CPU Timer 2:
000 =SYSCLK Selected (default on reset, pre-scale is bypassed)
001 = INTOSC1
010 = INTOSC2
011 = XTAL
100 = Reserved
101 = Reserved
110 = AUXPLLCLK
111 = reserved
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

383

Registers

www.ti.com

2.15.11.25 RESC Register (Offset = 80h) [reset = X]
RESC is shown in Figure 2-181 and described in Table 2-193.
Return to Summary Table.
Reset Cause register
Figure 2-181. RESC Register
31
TRSTn_pin_sta
tus
R-X

30
XRSn_pin_stat
us
R-X

29

23

22

21

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

11

10

9

8
SCCRESETn
R/W=1-0h

7
RESERVED
R=0-0h

6
HIBRESETn
R/W=1-0h

5
HWBISTn
R/W=1-0h

4
RESERVED
R=0-0h

3
NMIWDRSn
R/W=1-0h

2
WDRSn
R/W=1-0h

1
XRSn
R/W=1-1h

0
POR
R/W=1-1h

Table 2-193. RESC Register Field Descriptions
Bit

Field

Type

Reset

Description

31

TRSTn_pin_status

R

X

Reading this bit provides the current status of TRSTn at the
respective C28x CPUs TRSTn input port. Reset value is reflective of
the pin status.
Reset type: N/A

30

XRSn_pin_status

R

X

Reading this bit provides the current status of the XRSn pin. Reset
value is reflective of the pin status.
Reset type: N/A

29-16

RESERVED

R=0

0h

Reserved

15-9

RESERVED

R=0

0h

Reserved

8

SCCRESETn

R/W=1

0h

If this bit is set, indicates that the device was reset by SCCRESETn
(fired by DCSM).
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORn

7

RESERVED

R=0

0h

Reserved

6

HIBRESETn

R/W=1

0h

If this bit is set, indicates that the device was reset due to a
Hibernate mode Wakeup.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: raw-XRSn

5

HWBISTn

R/W=1

0h

If this bit is set, indicates that the device was reset by HWBIST.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORn

4

384

RESERVED

System Control

R=0

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-193. RESC Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

NMIWDRSn

R/W=1

0h

If this bit is set, indicates that the device was reset by NMIWDRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
To know the exact cause of NMI after the reset, software needs to
read CPU1/2.NMISHDFLG registers
Reset type: PORn

2

WDRSn

R/W=1

0h

If this bit is set, indicates that the device was reset by WDRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORn

1

XRSn

R/W=1

1h

If this bit is set, indicates that the device was reset by XRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORn

0

POR

R/W=1

1h

If this bit is set, indicates that the device was reset by PORn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

385

Registers

www.ti.com

2.15.12 ROM_PREFETCH_REGS Registers
Table 2-194 lists the memory-mapped registers for the ROM_PREFETCH_REGS. All register offset
addresses not listed in Table 2-194 should be considered as reserved locations and the register contents
should not be modified.
Table 2-194. ROM_PREFETCH_REGS Registers
Offset
0h

Acronym

Register Name

Write Protection

ROMPREFETCH

ROM Prefetch Configuration Register

EALLOW

Section
Go

Complex bit access types are encoded to fit into small table cells. Table 2-195 shows the codes that are
used for access types in this section.
Table 2-195. ROM_PREFETCH_REGS Access Type
Codes
Access Type

Code

Description

R

Read

W

Write

Read Type
R
Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

386

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.12.1 ROMPREFETCH Register (Offset = 0h) [reset = 0h]
ROMPREFETCH is shown in Figure 2-182 and described in Table 2-196.
Return to Summary Table.
ROM Prefetch Configuration Register
Figure 2-182. ROMPREFETCH Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
PFENABLE
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-196. ROMPREFETCH Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

0

PFENABLE

R/W

0h

0: Prefetch is disabled for secure ROM and boot ROM.
1: Prefetch is enabled for secure ROM and boot ROM.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

387

Registers

www.ti.com

2.15.13 DCSM_Z1_OTP Registers
Table 2-197 lists the memory-mapped registers for the DCSM_Z1_OTP. All register offset addresses not
listed in Table 2-197 should be considered as reserved locations and the register contents should not be
modified.
Table 2-197. DCSM_Z1_OTP Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

Z1OTP_LINKPOINTER1

Zone 1 Link Pointer1 in Z1 OTP

Go

4h

Z1OTP_LINKPOINTER2

Zone 1 Link Pointer2 in Z1 OTP

Go

8h

Z1OTP_LINKPOINTER3

Zone 1 Link Pointer3 in Z1 OTP

Go

10h

Z1OTP_PSWDLOCK

Secure Password Lock in Z1 OTP

Go

14h

Z1OTP_CRCLOCK

Secure CRC Lock in Z1 OTP

Go

1Eh

Z1OTP_BOOTCTRL

Boot Mode in Z1 OTP

Go

Complex bit access types are encoded to fit into small table cells. Table 2-198 shows the codes that are
used for access types in this section.
Table 2-198. DCSM_Z1_OTP Access Type Codes
Access Type

Code

Description

R

Read

Read Type
R

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

388

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.13.1 Z1OTP_LINKPOINTER1 Register (Offset = 0h) [reset = FFFFFFFFh]
Z1OTP_LINKPOINTER1 is shown in Figure 2-183 and described in Table 2-199.
Return to Summary Table.
Zone 1 Link Pointer1 in Z1 OTP
Figure 2-183. Z1OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1OTP_LINKPOINTER1
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-199. Z1OTP_LINKPOINTER1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Z1OTP_LINKPOINTER1

R

FFFFFFFFh Zone1 Link Pointer 1 location in USER OTP.
Reset type: SYSRSn

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

389

Registers

www.ti.com

2.15.13.2 Z1OTP_LINKPOINTER2 Register (Offset = 4h) [reset = FFFFFFFFh]
Z1OTP_LINKPOINTER2 is shown in Figure 2-184 and described in Table 2-200.
Return to Summary Table.
Zone 1 Link Pointer2 in Z1 OTP
Figure 2-184. Z1OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1OTP_LINKPOINTER2
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-200. Z1OTP_LINKPOINTER2 Register Field Descriptions
Bit
31-0

390

Field

Type

Reset

Z1OTP_LINKPOINTER2

R

FFFFFFFFh Zone1 Link Pointer 2 location in USER OTP.
Reset type: SYSRSn

System Control

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.13.3 Z1OTP_LINKPOINTER3 Register (Offset = 8h) [reset = FFFFFFFFh]
Z1OTP_LINKPOINTER3 is shown in Figure 2-185 and described in Table 2-201.
Return to Summary Table.
Zone 1 Link Pointer3 in Z1 OTP
Figure 2-185. Z1OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1OTP_LINKPOINTER3
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-201. Z1OTP_LINKPOINTER3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Z1OTP_LINKPOINTER3

R

FFFFFFFFh Zone1 Link Pointer 3 location in USER OTP.
Reset type: SYSRSn

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

391

Registers

www.ti.com

2.15.13.4 Z1OTP_PSWDLOCK Register (Offset = 10h) [reset = FFFFFFFFh]
Z1OTP_PSWDLOCK is shown in Figure 2-186 and described in Table 2-202.
Return to Summary Table.
Secure Password Lock in Z1 OTP
Figure 2-186. Z1OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1OTP_PSWDLOCK
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-202. Z1OTP_PSWDLOCK Register Field Descriptions
Bit
31-0

392

Field

Type

Reset

Z1OTP_PSWDLOCK

R

FFFFFFFFh Zone1 password lock location in USER OTP.
Reset type: SYSRSn

System Control

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.13.5 Z1OTP_CRCLOCK Register (Offset = 14h) [reset = FFFFFFFFh]
Z1OTP_CRCLOCK is shown in Figure 2-187 and described in Table 2-203.
Return to Summary Table.
Secure CRC Lock in Z1 OTP
Figure 2-187. Z1OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1OTP_CRCLOCK
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-203. Z1OTP_CRCLOCK Register Field Descriptions
Bit
31-0

Field

Type

Reset

Z1OTP_CRCLOCK

R

FFFFFFFFh Zone1 CRC lock location in USER OTP.
Reset type: SYSRSn

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

393

Registers

www.ti.com

2.15.13.6 Z1OTP_BOOTCTRL Register (Offset = 1Eh) [reset = FFFFFFFFh]
Z1OTP_BOOTCTRL is shown in Figure 2-188 and described in Table 2-204.
Return to Summary Table.
Boot Mode in Z1 OTP
Figure 2-188. Z1OTP_BOOTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1OTP_BOOTCTRL
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-204. Z1OTP_BOOTCTRL Register Field Descriptions
Bit
31-0

394

Field

Type

Reset

Z1OTP_BOOTCTRL

R

FFFFFFFFh Zone1 Boot control location in USER OTP.
Reset type: SYSRSn

System Control

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.14 DCSM_Z2_OTP Registers
Table 2-205 lists the memory-mapped registers for the DCSM_Z2_OTP. All register offset addresses not
listed in Table 2-205 should be considered as reserved locations and the register contents should not be
modified.
Table 2-205. DCSM_Z2_OTP Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

Z2OTP_LINKPOINTER1

Zone 2 Link Pointer1 in Z2 OTP

Go

4h

Z2OTP_LINKPOINTER2

Zone 2 Link Pointer2 in Z2 OTP

Go

8h

Z2OTP_LINKPOINTER3

Zone 2 Link Pointer3 in Z2 OTP

Go

10h

Z2OTP_PSWDLOCK

Secure Password Lock in Z2 OTP

Go

14h

Z2OTP_CRCLOCK

Secure CRC Lock in Z2 OTP

Go

1Eh

Z2OTP_BOOTCTRL

Boot Mode in Z2 OTP

Go

Complex bit access types are encoded to fit into small table cells. Table 2-206 shows the codes that are
used for access types in this section.
Table 2-206. DCSM_Z2_OTP Access Type Codes
Access Type

Code

Description

R

Read

Read Type
R

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

395

Registers

www.ti.com

2.15.14.1 Z2OTP_LINKPOINTER1 Register (Offset = 0h) [reset = FFFFFFFFh]
Z2OTP_LINKPOINTER1 is shown in Figure 2-189 and described in Table 2-207.
Return to Summary Table.
Zone 2 Link Pointer1 in Z2 OTP
Figure 2-189. Z2OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2OTP_LINKPOINTER1
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-207. Z2OTP_LINKPOINTER1 Register Field Descriptions
Bit
31-0

396

Field

Type

Reset

Z2OTP_LINKPOINTER1

R

FFFFFFFFh Zone2 Link Pointer 1 location in USER OTP.
Reset type: SYSRSn

System Control

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.14.2 Z2OTP_LINKPOINTER2 Register (Offset = 4h) [reset = FFFFFFFFh]
Z2OTP_LINKPOINTER2 is shown in Figure 2-190 and described in Table 2-208.
Return to Summary Table.
Zone 2 Link Pointer2 in Z2 OTP
Figure 2-190. Z2OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2OTP_LINKPOINTER2
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-208. Z2OTP_LINKPOINTER2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Z2OTP_LINKPOINTER2

R

FFFFFFFFh Zone2 Link Pointer 2 location in USER OTP.
Reset type: SYSRSn

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

397

Registers

www.ti.com

2.15.14.3 Z2OTP_LINKPOINTER3 Register (Offset = 8h) [reset = FFFFFFFFh]
Z2OTP_LINKPOINTER3 is shown in Figure 2-191 and described in Table 2-209.
Return to Summary Table.
Zone 2 Link Pointer3 in Z2 OTP
Figure 2-191. Z2OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2OTP_LINKPOINTER3
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-209. Z2OTP_LINKPOINTER3 Register Field Descriptions
Bit
31-0

398

Field

Type

Reset

Z2OTP_LINKPOINTER3

R

FFFFFFFFh Zone2 Link Pointer 3 location in USER OTP.
Reset type: SYSRSn

System Control

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.14.4 Z2OTP_PSWDLOCK Register (Offset = 10h) [reset = FFFFFFFFh]
Z2OTP_PSWDLOCK is shown in Figure 2-192 and described in Table 2-210.
Return to Summary Table.
Secure Password Lock in Z2 OTP
Figure 2-192. Z2OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2OTP_PSWDLOCK
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-210. Z2OTP_PSWDLOCK Register Field Descriptions
Bit
31-0

Field

Type

Reset

Z2OTP_PSWDLOCK

R

FFFFFFFFh Zone2 password lock location in USER OTP.
Reset type: SYSRSn

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

399

Registers

www.ti.com

2.15.14.5 Z2OTP_CRCLOCK Register (Offset = 14h) [reset = FFFFFFFFh]
Z2OTP_CRCLOCK is shown in Figure 2-193 and described in Table 2-211.
Return to Summary Table.
Secure CRC Lock in Z2 OTP
Figure 2-193. Z2OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2OTP_CRCLOCK
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-211. Z2OTP_CRCLOCK Register Field Descriptions
Bit
31-0

400

Field

Type

Reset

Z2OTP_CRCLOCK

R

FFFFFFFFh Zone2 CRC lock location in USER OTP.
Reset type: SYSRSn

System Control

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.14.6 Z2OTP_BOOTCTRL Register (Offset = 1Eh) [reset = FFFFFFFFh]
Z2OTP_BOOTCTRL is shown in Figure 2-194 and described in Table 2-212.
Return to Summary Table.
Boot Mode in Z2 OTP
Figure 2-194. Z2OTP_BOOTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2OTP_BOOTCTRL
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-212. Z2OTP_BOOTCTRL Register Field Descriptions
Bit
31-0

Field

Type

Reset

Z2OTP_BOOTCTRL

R

FFFFFFFFh Zone2 Boot control location in USER OTP.
Reset type: SYSRSn

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

401

Registers

www.ti.com

2.15.15 DCSM_Z1_REGS Registers
Table 2-213 lists the memory-mapped registers for the DCSM_Z1_REGS. All register offset addresses not
listed in Table 2-213 should be considered as reserved locations and the register contents should not be
modified.
Table 2-213. DCSM_Z1_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

Z1_LINKPOINTER

Zone 1 Link Pointer

Go

2h

Z1_OTPSECLOCK

Zone 1 OTP Secure JTAG lock

Go

4h

Z1_BOOTCTRL

Boot Mode

Go

6h

Z1_LINKPOINTERERR

Link Pointer Error

Go

10h

Z1_CSMKEY0

Zone 1 CSM Key 0

Go

12h

Z1_CSMKEY1

Zone 1 CSM Key 1

Go

14h

Z1_CSMKEY2

Zone 1 CSM Key 2

Go

16h

Z1_CSMKEY3

Zone 1 CSM Key 3

Go

19h

Z1_CR

Zone 1 CSM Control Register

Go

1Ah

Z1_GRABSECTR

Zone 1 Grab Flash Sectors Register

Go

1Ch

Z1_GRABRAMR

Zone 1 Grab RAM Blocks Register

Go

1Eh

Z1_EXEONLYSECTR

Zone 1 Flash Execute_Only Sector Register

Go

20h

Z1_EXEONLYRAMR

Zone 1 RAM Execute_Only Block Register

Go

Complex bit access types are encoded to fit into small table cells. Table 2-214 shows the codes that are
used for access types in this section.
Table 2-214. DCSM_Z1_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

Write

Read Type

Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

402

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.15.1 Z1_LINKPOINTER Register (Offset = 0h) [reset = E0000000h]
Z1_LINKPOINTER is shown in Figure 2-195 and described in Table 2-215.
Return to Summary Table.
Zone 1 Link Pointer
Figure 2-195. Z1_LINKPOINTER Register
31

30
29
RESERVED
R-7h

15

14

13

28

27

26

25

12

11

10

9

24

23

22
21
LINKPOINTER
R-0h

8
7
LINKPOINTER
R-0h

6

5

20

19

18

17

16

4

3

2

1

0

Table 2-215. Z1_LINKPOINTER Register Field Descriptions
Field

Type

Reset

Description

31-29

Bit

RESERVED

R

7h

Reserved

28-0

LINKPOINTER

R

0h

This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

403

Registers

www.ti.com

2.15.15.2 Z1_OTPSECLOCK Register (Offset = 2h) [reset = FFFh]
Z1_OTPSECLOCK is shown in Figure 2-196 and described in Table 2-216.
Return to Summary Table.
Zone 1 OTP Secure JTAG lock
Figure 2-196. Z1_OTPSECLOCK Register
31

30

29

28

27

26

25

15

14
13
RESERVED
R-0h

12

11

10
9
CRCLOCK
R-Fh

24
23
RESERVED
R-0h
8

7

22

21

6
5
PSWDLOCK
R-Fh

20

19

18

17

16

4

3

2
1
RESERVED
R-0h

0

Table 2-216. Z1_OTPSECLOCK Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-12

RESERVED

R

0h

Reserved

11-8

CRCLOCK

R

Fh

Value in this field gets loaded from Z1_CRCLOCK[11:8] when a read
is issued to address location of Z1_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: SYSRSn

7-4

PSWDLOCK

R

Fh

Value in this field gets loaded from Z1_PSWDLOCK[7:4] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can
be read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: SYSRSn

3-0

404

RESERVED

System Control

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.15.3 Z1_BOOTCTRL Register (Offset = 4h) [reset = 0h]
Z1_BOOTCTRL is shown in Figure 2-197 and described in Table 2-217.
Return to Summary Table.
Boot Mode
Figure 2-197. Z1_BOOTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOOTPIN1
BOOTPIN0
BMODE
R-0h
R-0h
R-0h

9

8

7

6

5

4 3
KEY
R-0h

2

1

0

Table 2-217. Z1_BOOTCTRL Register Field Descriptions
Bit
31-24

Field

Type

Reset

Description

BOOTPIN1

R

0h

This field gets loaded with Z1_BOOTCTRL[31:24] when a dummy
read is issued to address location of Z1_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
2 : Pick GPIO1 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn

23-16

BOOTPIN0

R

0h

This field gets loaded with Z1_BOOTCTRL[23:16] when a dummy
read is issued to address location of Z1_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
2 : Pick GPIO1 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn

15-8

BMODE

R

0h

This field gets loaded with Z1_BOOTCTRL[16:8] when a dummy
read is issued to address location of Z1_BOOTCTRL in OTP.
Reset type: SYSRSn

7-0

KEY

R

0h

This field gets loaded with Z1_BOOTCTRL[7:0] when a dummy read
is issued to address location of Z1_BOOTCTRL in OTP.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

405

Registers

www.ti.com

2.15.15.4 Z1_LINKPOINTERERR Register (Offset = 6h) [reset = FFFFFFFFh]
Z1_LINKPOINTERERR is shown in Figure 2-198 and described in Table 2-218.
Return to Summary Table.
Link Pointer Error
Figure 2-198. Z1_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1_LINKPOINTERERR
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-218. Z1_LINKPOINTERERR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Z1_LINKPOINTERERR

R

FFFFFFFFh These bits indicate errors during formation of the resolved LinkPointer value after the three physical Link-Pointer values loaded of
OTP.

Description

0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

406

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.15.5 Z1_CSMKEY0 Register (Offset = 10h) [reset = 0h]
Z1_CSMKEY0 is shown in Figure 2-199 and described in Table 2-219.
Return to Summary Table.
Zone 1 CSM Key 0
Figure 2-199. Z1_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1_CSMKEY0
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-219. Z1_CSMKEY0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

Z1_CSMKEY0

R

0h

To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

407

Registers

www.ti.com

2.15.15.6 Z1_CSMKEY1 Register (Offset = 12h) [reset = 0h]
Z1_CSMKEY1 is shown in Figure 2-200 and described in Table 2-220.
Return to Summary Table.
Zone 1 CSM Key 1
Figure 2-200. Z1_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1_CSMKEY1
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-220. Z1_CSMKEY1 Register Field Descriptions
Bit
31-0

408

Field

Type

Reset

Description

Z1_CSMKEY1

R

0h

To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.15.7 Z1_CSMKEY2 Register (Offset = 14h) [reset = 0h]
Z1_CSMKEY2 is shown in Figure 2-201 and described in Table 2-221.
Return to Summary Table.
Zone 1 CSM Key 2
Figure 2-201. Z1_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1_CSMKEY2
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-221. Z1_CSMKEY2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

Z1_CSMKEY2

R

0h

To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

409

Registers

www.ti.com

2.15.15.8 Z1_CSMKEY3 Register (Offset = 16h) [reset = 0h]
Z1_CSMKEY3 is shown in Figure 2-202 and described in Table 2-222.
Return to Summary Table.
Zone 1 CSM Key 3
Figure 2-202. Z1_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z1_CSMKEY3
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-222. Z1_CSMKEY3 Register Field Descriptions
Bit
31-0

410

Field

Type

Reset

Description

Z1_CSMKEY3

R

0h

To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.15.9 Z1_CR Register (Offset = 19h) [reset = 8h]
Z1_CR is shown in Figure 2-203 and described in Table 2-223.
Return to Summary Table.
Zone 1 CSM Control Register
Figure 2-203. Z1_CR Register
15
FORCESEC
R=0/W-0h

14

13

12

11
RESERVED
R-0h

10

9

8

7
RESERVED
R-0h

6
ARMED
R-0h

5
UNSECURE
R-0h

4
ALLONE
R-0h

3
ALLZERO
R-1h

2

1
RESERVED
R-0h

0

Table 2-223. Z1_CR Register Field Descriptions
Bit

Field

Type

Reset

Description

15

FORCESEC

R=0/W

0h

A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn

14-8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

ARMED

R

0h

0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn

5

UNSECURE

R

0h

Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn

4

ALLONE

R

0h

Indicates the state of CSM passowrds.
0 : CSM Passwords are not all ones.
1 : CSM Passwords are all ones and zone is in unlock state.
Reset type: SYSRSn

3

ALLZERO

R

1h

Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn

2-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

411

Registers

www.ti.com

2.15.15.10 Z1_GRABSECTR Register (Offset = 1Ah) [reset = 0h]
Z1_GRABSECTR is shown in Figure 2-204 and described in Table 2-224.
Return to Summary Table.
Zone 1 Grab Flash Sectors Register
Figure 2-204. Z1_GRABSECTR Register
31

30

29

RESERVED
R-0h
23

28

27
26
GRAB_SECTN
R-0h

25
24
GRAB_SECTM
R-0h

20

19

17

RESERVED
R-0h
22

21

GRAB_SECTL
R-0h

GRAB_SECTK
R-0h

15
14
GRAB_SECTH
R-0h

13
12
GRAB_SECTG
R-0h

11

7

5

3

6
GRAB_SECTD
R-0h

18
GRAB_SECTJ
R-0h

4
GRAB_SECTC
R-0h

16
GRAB_SECTI
R-0h

10

9

GRAB_SECTF
R-0h

8
GRAB_SECTE
R-0h

2

1

GRAB_SECTB
R-0h

0
GRAB_SECTA
R-0h

Table 2-224. Z1_GRABSECTR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

R

0h

Reserved

29-28

RESERVED

R

0h

Reserved

27-26

GRAB_SECTN

R

0h

Value in this field gets loaded from Z1_GRABSECT[27:26] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector N is inaccessible.
01 : Request to allocate Flash Sector N to Zone1.
10 : Request to allocate Flash Sector N to Zone1.
11 : Request to make Flash sector N Non-Secure.
Reset type: SYSRSn

25-24

GRAB_SECTM

R

0h

Value in this field gets loaded from Z1_GRABSECT[25:24] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector M is inaccessible.
01 : Request to allocate Flash Sector M to Zone1.
10 : Request to allocate Flash Sector M to Zone1.
11 : Request to make Flash sector M Non-Secure.
Reset type: SYSRSn

23-22

GRAB_SECTL

R

0h

Value in this field gets loaded from Z1_GRABSECT[23:22] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector L is inaccessible.
01 : Request to allocate Flash Sector L to Zone1.
10 : Request to allocate Flash Sector L to Zone1.
11 : Request to make Flash sector L Non-Secure.
Reset type: SYSRSn

412

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-224. Z1_GRABSECTR Register Field Descriptions (continued)
Bit
21-20

Field

Type

Reset

Description

GRAB_SECTK

R

0h

Value in this field gets loaded from Z1_GRABSECT[21:20] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector K is inaccessible.
01 : Request to allocate Flash Sector K to Zone1.
10 : Request to allocate Flash Sector K to Zone1.
11 : Request to make Flash sector K Non-Secure.
Reset type: SYSRSn

19-18

GRAB_SECTJ

R

0h

Value in this field gets loaded from Z1_GRABSECT[19:18] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector J is inaccessible.
01 : Request to allocate Flash Sector J to Zone1.
10 : Request to allocate Flash Sector J to Zone1.
11 : Request to make Flash sector J Non-Secure.
Reset type: SYSRSn

17-16

GRAB_SECTI

R

0h

Value in this field gets loaded from Z1_GRABSECT[17:16] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector I is inaccessible.
01 : Request to allocate Flash Sector I to Zone1.
10 : Request to allocate Flash Sector I to Zone1.
11 : Request to make Flash sector I Non-Secure.
Reset type: SYSRSn

15-14

GRAB_SECTH

R

0h

Value in this field gets loaded from Z1_GRABSECT[15:14] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector H is inaccessible.
01 : Request to allocate Flash Sector H to Zone1.
10 : Request to allocate Flash Sector H to Zone1.
11 : Request to make Flash sector H Non-Secure.
Reset type: SYSRSn

13-12

GRAB_SECTG

R

0h

Value in this field gets loaded from Z1_GRABSECT[13:12] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector G is inaccessible.
01 : Request to allocate Flash Sector G to Zone1.
10 : Request to allocate Flash Sector G to Zone1.
11 : Request to make Flash sector G Non-Secure.
Reset type: SYSRSn

11-10

GRAB_SECTF

R

0h

Value in this field gets loaded from Z1_GRABSECT[11:10] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector F is inaccessible.
01 : Request to allocate Flash Sector F to Zone1.
10 : Request to allocate Flash Sector F to Zone1.
11 : Request to make Flash sector F Non-Secure.
Reset type: SYSRSn

9-8

GRAB_SECTE

R

0h

Value in this field gets loaded from Z1_GRABSECT[9:8] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector E is inaccessible.
01 : Request to allocate Flash Sector E to Zone1.
10 : Request to allocate Flash Sector E to Zone1.
11 : Request to make Flash sector E Non-Secure.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

413

Registers

www.ti.com

Table 2-224. Z1_GRABSECTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

GRAB_SECTD

R

0h

Value in this field gets loaded from Z1_GRABSECT[7:6] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector D is inaccessible.
01 : Request to allocate Flash Sector D to Zone1.
10 : Request to allocate Flash Sector D to Zone1.
11 : Request to make Flash sector D Non-Secure.
Reset type: SYSRSn

5-4

GRAB_SECTC

R

0h

Value in this field gets loaded from Z1_GRABSECT[5:4] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector C is inaccessible.
01 : Request to allocate Flash Sector C to Zone1.
10 : Request to allocate Flash Sector C to Zone1.
11 : Request to make Flash sector C Non-Secure.
Reset type: SYSRSn

3-2

GRAB_SECTB

R

0h

Value in this field gets loaded from Z1_GRABSECT[3:2] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector B is inaccessible.
01 : Request to allocate Flash Sector B to Zone1.
10 : Request to allocate Flash Sector B to Zone1.
11 : Request to make Flash sector B Non-Secure.
Reset type: SYSRSn

1-0

GRAB_SECTA

R

0h

Value in this field gets loaded from Z1_GRABSECT[1:0] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector A is inaccessible.
01 : Request to allocate Flash Sector A to Zone1.
10 : Request to allocate Flash Sector A to Zone1.
11 : Request to make Flash sector A Non-Secure.
Reset type: SYSRSn

414

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.15.11 Z1_GRABRAMR Register (Offset = 1Ch) [reset = 0h]
Z1_GRABRAMR is shown in Figure 2-205 and described in Table 2-225.
Return to Summary Table.
Zone 1 Grab RAM Blocks Register
Figure 2-205. Z1_GRABRAMR Register
31

30

29

RESERVED
R-0h
23

28

27

26

25

24

18

17

16

10

9

GRAB_CLA1
R-0h
22

21

RESERVED
R-0h
20

19
RESERVED
R-0h

15

14

13

GRAB_RAM7
R-0h
7

12

11

GRAB_RAM6
R-0h
6

5

GRAB_RAM3
R-0h

GRAB_RAM5
R-0h
4

3

GRAB_RAM2
R-0h

8
GRAB_RAM4
R-0h

2

1

GRAB_RAM1
R-0h

0
GRAB_RAM0
R-0h

Table 2-225. Z1_GRABRAMR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

R

0h

Reserved

29-28

GRAB_CLA1

R

0h

Value in this field gets loaded from Z1_GRABRAM[29:28] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. CLA1 is inaccessible.
01 : Request to allocate CLA1 to Zone1.
10 : Request to allocate CLA1 to Zone1.
11 : Request to make CLA1 Non-Secure.
Reset type: SYSRSn

27-16

RESERVED

R

0h

Reserved

15-14

GRAB_RAM7

R

0h

Value in this field gets loaded from Z1_GRABRAM[15:14] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. D1 RAM is inaccessible.
01 : Request to allocate D1 RAM to Zone1.
10 : Request to allocate D1 RAM to Zone1.
11 : Request to make D1 RAM Non-Secure.
Reset type: SYSRSn

13-12

GRAB_RAM6

R

0h

Value in this field gets loaded from Z1_GRABRAM[13:12] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. D0 RAM is inaccessible.
01 : Request to allocate D0 RAM to Zone1.
10 : Request to allocate D0 RAM to Zone1.
11 : Request to make D0 RAM Non-Secure.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

415

Registers

www.ti.com

Table 2-225. Z1_GRABRAMR Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

GRAB_RAM5

R

0h

Value in this field gets loaded from Z1_GRABRAM[11:10] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS5 RAM is inaccessible.
01 : Request to allocate LS5 RAM to Zone1.
10 : Request to allocate LS5 RAM to Zone1.
11 : Request to make LS5 RAM Non-Secure.
Reset type: SYSRSn

9-8

GRAB_RAM4

R

0h

Value in this field gets loaded from Z1_GRABRAM[9:8] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS4 RAM is inaccessible.
01 : Request to allocate LS4 RAM to Zone1.
10 : Request to allocate LS4 RAM to Zone1.
11 : Request to make LS4 RAM Non-Secure.
Reset type: SYSRSn

7-6

GRAB_RAM3

R

0h

Value in this field gets loaded from Z1_GRABRAM[7:6] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS3 RAM is inaccessible.
01 : Request to allocate LS3 RAM to Zone1.
10 : Request to allocate LS3 RAM to Zone1.
11 : Request to make LS3 RAM Non-Secure.
Reset type: SYSRSn

5-4

GRAB_RAM2

R

0h

Value in this field gets loaded from Z1_GRABRAM[5:4] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS2 RAM is inaccessible.
01 : Request to allocate LS2 RAM to Zone1.
10 : Request to allocate LS2 RAM to Zone1.
11 : Request to make LS2 RAM Non-Secure.
Reset type: SYSRSn

3-2

GRAB_RAM1

R

0h

Value in this field gets loaded from Z1_GRABRAM[3:2] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS1 RAM is inaccessible.
01 : Request to allocate LS1 RAM to Zone1.
10 : Request to allocate LS1 RAM to Zone1.
11 : Request to make LS1 RAM Non-Secure.
Reset type: SYSRSn

1-0

GRAB_RAM0

R

0h

Value in this field gets loaded from Z1_GRABRAM[1:0] when a read
is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. LS0 RAM is inaccessible.
01 : Request to allocate LS0 RAM to Zone1.
10 : Request to allocate LS0 RAM to Zone1.
11 : Request to make LS0 RAM Non-Secure.
Reset type: SYSRSn

416

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.15.12 Z1_EXEONLYSECTR Register (Offset = 1Eh) [reset = 0h]
Z1_EXEONLYSECTR is shown in Figure 2-206 and described in Table 2-226.
Return to Summary Table.
Zone 1 Flash Execute_Only Sector Register
Figure 2-206. Z1_EXEONLYSECTR Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
RESERVED

14
RESERVED
R-0h

13
EXEONLY_SE
CTN
R-0h

12
EXEONLY_SE
CTM
R-0h

11
EXEONLY_SE
CTL
R-0h

10
EXEONLY_SE
CTK
R-0h

9
EXEONLY_SE
CTJ
R-0h

8
EXEONLY_SE
CTI
R-0h

R-0h
7
EXEONLY_SE
CTH
R-0h

6
EXEONLY_SE
CTG
R-0h

5
EXEONLY_SE
CTF
R-0h

4
EXEONLY_SE
CTE
R-0h

3
EXEONLY_SE
CTD
R-0h

2
EXEONLY_SE
CTC
R-0h

1
EXEONLY_SE
CTB
R-0h

0
EXEONLY_SE
CTA
R-0h

Table 2-226. Z1_EXEONLYSECTR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

EXEONLY_SECTN

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[13:13] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector N (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector N (only if it's
allocated to Zone1)
Reset type: SYSRSn

12

EXEONLY_SECTM

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[12:12] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector M (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector M (only if it's
allocated to Zone1)
Reset type: SYSRSn

11

EXEONLY_SECTL

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[11:11] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector L (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector L (only if it's
allocated to Zone1)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

417

Registers

www.ti.com

Table 2-226. Z1_EXEONLYSECTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

10

EXEONLY_SECTK

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[10:10] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector K (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector K (only if it's
allocated to Zone1)
Reset type: SYSRSn

9

EXEONLY_SECTJ

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[9:9] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector J (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector J (only if it's
allocated to Zone1)
Reset type: SYSRSn

8

EXEONLY_SECTI

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[8:8] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector I (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector I (only if it's
allocated to Zone1)
Reset type: SYSRSn

7

EXEONLY_SECTH

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[7:7] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector H (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector H (only if it's
allocated to Zone1)
Reset type: SYSRSn

6

EXEONLY_SECTG

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[6:6] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector G (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector G (only if it's
allocated to Zone1)
Reset type: SYSRSn

5

EXEONLY_SECTF

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[5:5] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector F (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector F (only if it's
allocated to Zone1)
Reset type: SYSRSn

4

EXEONLY_SECTE

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[4:4] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector E (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector E (only if it's
allocated to Zone1)
Reset type: SYSRSn

418

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-226. Z1_EXEONLYSECTR Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

EXEONLY_SECTD

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[3:3] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector D (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector D (only if it's
allocated to Zone1)
Reset type: SYSRSn

2

EXEONLY_SECTC

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[2:2] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector C (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector C (only if it's
allocated to Zone1)
Reset type: SYSRSn

1

EXEONLY_SECTB

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[1:1] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector B (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector B (only if it's
allocated to Zone1)
Reset type: SYSRSn

0

EXEONLY_SECTA

R

0h

Value in this field gets loaded from Z1_EXEONLYSECT[0:0] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector A (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector A (only if it's
allocated to Zone1)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

419

Registers

www.ti.com

2.15.15.13 Z1_EXEONLYRAMR Register (Offset = 20h) [reset = 0h]
Z1_EXEONLYRAMR is shown in Figure 2-207 and described in Table 2-227.
Return to Summary Table.
Zone 1 RAM Execute_Only Block Register
Figure 2-207. Z1_EXEONLYRAMR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
EXEONLY_RA
M3
R-0h

2
EXEONLY_RA
M2
R-0h

1
EXEONLY_RA
M1
R-0h

0
EXEONLY_RA
M0
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7
EXEONLY_RA
M7
R-0h

6
EXEONLY_RA
M6
R-0h

5
EXEONLY_RA
M5
R-0h

4
EXEONLY_RA
M4
R-0h

Table 2-227. Z1_EXEONLYRAMR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-8

RESERVED

R

0h

Reserved

EXEONLY_RAM7

R

0h

Value in this field gets loaded from Z1_EXEONLYRAM[7:7] when a
read is issued to Z1_EXEONLYRAM address location in OTP.

7

0 : Execute-Only protection is enabled for D1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for D1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
6

EXEONLY_RAM6

R

0h

Value in this field gets loaded from Z1_EXEONLYRAM[6:6] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for D0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for D0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

5

EXEONLY_RAM5

R

0h

Value in this field gets loaded from Z1_EXEONLYRAM[5:5] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS5 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS5 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

4

EXEONLY_RAM4

R

0h

Value in this field gets loaded from Z1_EXEONLYRAM[4:4] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS4 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS4 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

420

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-227. Z1_EXEONLYRAMR Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

EXEONLY_RAM3

R

0h

Value in this field gets loaded from Z1_EXEONLYRAM[3:3] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS3 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS3 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

2

EXEONLY_RAM2

R

0h

Value in this field gets loaded from Z1_EXEONLYRAM[2:2] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS2 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS2 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

1

EXEONLY_RAM1

R

0h

Value in this field gets loaded from Z1_EXEONLYRAM[1:1] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

0

EXEONLY_RAM0

R

0h

Value in this field gets loaded from Z1_EXEONLYRAM[0:0] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

421

Registers

www.ti.com

2.15.16 DCSM_Z2_REGS Registers
Table 2-228 lists the memory-mapped registers for the DCSM_Z2_REGS. All register offset addresses not
listed in Table 2-228 should be considered as reserved locations and the register contents should not be
modified.
Table 2-228. DCSM_Z2_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

Z2_LINKPOINTER

Zone 2 Link Pointer

Go

2h

Z2_OTPSECLOCK

Zone 2 OTP Secure JTAG lock

Go

4h

Z2_BOOTCTRL

Boot Mode

Go

6h

Z2_LINKPOINTERERR

Link Pointer Error

Go

10h

Z2_CSMKEY0

Zone 2 CSM Key 0

Go

12h

Z2_CSMKEY1

Zone 2 CSM Key 1

Go

14h

Z2_CSMKEY2

Zone 2 CSM Key 2

Go

16h

Z2_CSMKEY3

Zone 2 CSM Key 3

Go

19h

Z2_CR

Zone 2 CSM Control Register

Go

1Ah

Z2_GRABSECTR

Zone 2 Grab Flash Sectors Register

Go

1Ch

Z2_GRABRAMR

Zone 2 Grab RAM Blocks Register

Go

1Eh

Z2_EXEONLYSECTR

Zone 2 Flash Execute_Only Sector Register

Go

20h

Z2_EXEONLYRAMR

Zone 2 RAM Execute_Only Block Register

Go

Complex bit access types are encoded to fit into small table cells. Table 2-229 shows the codes that are
used for access types in this section.
Table 2-229. DCSM_Z2_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

Write

Read Type

Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

422

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.16.1 Z2_LINKPOINTER Register (Offset = 0h) [reset = E0000000h]
Z2_LINKPOINTER is shown in Figure 2-208 and described in Table 2-230.
Return to Summary Table.
Zone 2 Link Pointer
Figure 2-208. Z2_LINKPOINTER Register
31

30
29
RESERVED
R-7h

15

14

13

28

27

26

25

12

11

10

9

24

23

22
21
LINKPOINTER
R-0h

8
7
LINKPOINTER
R-0h

6

5

20

19

18

17

16

4

3

2

1

0

Table 2-230. Z2_LINKPOINTER Register Field Descriptions
Field

Type

Reset

Description

31-29

Bit

RESERVED

R

7h

Reserved

28-0

LINKPOINTER

R

0h

This is the Resolved Link-Pointer value which is generated by
looking at the three physical Link-Pointer values loaded from OTP.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

423

Registers

www.ti.com

2.15.16.2 Z2_OTPSECLOCK Register (Offset = 2h) [reset = FFFh]
Z2_OTPSECLOCK is shown in Figure 2-209 and described in Table 2-231.
Return to Summary Table.
Zone 2 OTP Secure JTAG lock
Figure 2-209. Z2_OTPSECLOCK Register
31

30

29

28

27

26

25

15

14
13
RESERVED
R-0h

12

11

10
9
CRCLOCK
R-Fh

24
23
RESERVED
R-0h
8

7

22

21

6
5
PSWDLOCK
R-Fh

20

19

18

17

16

4

3

2
1
RESERVED
R-0h

0

Table 2-231. Z2_OTPSECLOCK Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-12

RESERVED

R

0h

Reserved

11-8

CRCLOCK

R

Fh

Value in this field gets loaded from Z2_CRCLOCK[11:8] when a read
is issued to address location of Z2_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: SYSRSn

7-4

PSWDLOCK

R

Fh

Value in this field gets loaded from Z2_PSWDLOCK[7:4] when a
read is issued to address location of Z2_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can
be read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: SYSRSn

3-0

424

RESERVED

System Control

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.16.3 Z2_BOOTCTRL Register (Offset = 4h) [reset = 0h]
Z2_BOOTCTRL is shown in Figure 2-210 and described in Table 2-232.
Return to Summary Table.
Boot Mode
Figure 2-210. Z2_BOOTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOOTPIN1
BOOTPIN0
BMODE
R-0h
R-0h
R-0h

9

8

7

6

5

4 3
KEY
R-0h

2

1

0

Table 2-232. Z2_BOOTCTRL Register Field Descriptions
Bit
31-24

Field

Type

Reset

Description

BOOTPIN1

R

0h

This field gets loaded with Z2_BOOTCTRL[31:24] when a dummy
read is issued to address location of Z2_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
2 : Pick GPIO1 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn

23-16

BOOTPIN0

R

0h

This field gets loaded with Z2_BOOTCTRL[23:16] when a dummy
read is issued to address location of Z2_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
2 : Pick GPIO1 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn

15-8

BMODE

R

0h

This field gets loaded with Z2_BOOTCTRL[16:8] when a dummy
read is issued to address location of Z2_BOOTCTRL in OTP.
Reset type: SYSRSn

7-0

KEY

R

0h

This field gets loaded with Z2_BOOTCTRL[7:0] when a dummy read
is issued to address location of Z2_BOOTCTRL in OTP.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

425

Registers

www.ti.com

2.15.16.4 Z2_LINKPOINTERERR Register (Offset = 6h) [reset = FFFFFFFFh]
Z2_LINKPOINTERERR is shown in Figure 2-211 and described in Table 2-233.
Return to Summary Table.
Link Pointer Error
Figure 2-211. Z2_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2_LINKPOINTERERR
R-FFFFFFFFh

9

8

7

6

5

4

3

2

1

0

Table 2-233. Z2_LINKPOINTERERR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Z2_LINKPOINTERERR

R

FFFFFFFFh These bits indicate errors during formation of the resolved LinkPointer value after the three physical Link-Pointer values loaded of
OTP.

Description

0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

426

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.16.5 Z2_CSMKEY0 Register (Offset = 10h) [reset = 0h]
Z2_CSMKEY0 is shown in Figure 2-212 and described in Table 2-234.
Return to Summary Table.
Zone 2 CSM Key 0
Figure 2-212. Z2_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2_CSMKEY0
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-234. Z2_CSMKEY0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

Z2_CSMKEY0

R

0h

To unclock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

427

Registers

www.ti.com

2.15.16.6 Z2_CSMKEY1 Register (Offset = 12h) [reset = 0h]
Z2_CSMKEY1 is shown in Figure 2-213 and described in Table 2-235.
Return to Summary Table.
Zone 2 CSM Key 1
Figure 2-213. Z2_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2_CSMKEY1
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-235. Z2_CSMKEY1 Register Field Descriptions
Bit
31-0

428

Field

Type

Reset

Description

Z2_CSMKEY1

R

0h

To unclock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.16.7 Z2_CSMKEY2 Register (Offset = 14h) [reset = 0h]
Z2_CSMKEY2 is shown in Figure 2-214 and described in Table 2-236.
Return to Summary Table.
Zone 2 CSM Key 2
Figure 2-214. Z2_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2_CSMKEY2
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-236. Z2_CSMKEY2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

Z2_CSMKEY2

R

0h

To unclock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

429

Registers

www.ti.com

2.15.16.8 Z2_CSMKEY3 Register (Offset = 16h) [reset = 0h]
Z2_CSMKEY3 is shown in Figure 2-215 and described in Table 2-237.
Return to Summary Table.
Zone 2 CSM Key 3
Figure 2-215. Z2_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Z2_CSMKEY3
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-237. Z2_CSMKEY3 Register Field Descriptions
Bit
31-0

430

Field

Type

Reset

Description

Z2_CSMKEY3

R

0h

To unclock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.16.9 Z2_CR Register (Offset = 19h) [reset = 8h]
Z2_CR is shown in Figure 2-216 and described in Table 2-238.
Return to Summary Table.
Zone 2 CSM Control Register
Figure 2-216. Z2_CR Register
15
FORCESEC
R=0/W-0h

14

13

12

11
RESERVED
R=0-0h

10

9

8

7
RESERVED
R-0h

6
ARMED
R-0h

5
UNSECURE
R-0h

4
ALLONE
R-0h

3
ALLZERO
R-1h

2

1
RESERVED
R-0h

0

Table 2-238. Z2_CR Register Field Descriptions
Bit

Field

Type

Reset

Description

15

FORCESEC

R=0/W

0h

A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn

14-8

RESERVED

R=0

0h

Reserved

7

RESERVED

R

0h

Reserved

6

ARMED

R

0h

0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn

5

UNSECURE

R

0h

Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn

4

ALLONE

R

0h

Indicates the state of CSM passowrds.
0 : CSM Passwords are not all ones.
1 : CSM Passwords are all ones and zone is in unlock state.
Reset type: SYSRSn

3

ALLZERO

R

1h

Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn

2-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

431

Registers

www.ti.com

2.15.16.10 Z2_GRABSECTR Register (Offset = 1Ah) [reset = 0h]
Z2_GRABSECTR is shown in Figure 2-217 and described in Table 2-239.
Return to Summary Table.
Zone 2 Grab Flash Sectors Register
Figure 2-217. Z2_GRABSECTR Register
31

30

29

RESERVED
R-0h
23

28

27
26
GRAB_SECTN
R-0h

25
24
GRAB_SECTM
R-0h

20

19

17

RESERVED
R-0h
22

21

GRAB_SECTL
R-0h

GRAB_SECTK
R-0h

15
14
GRAB_SECTH
R-0h

13
12
GRAB_SECTG
R-0h

11

7

5

3

6
GRAB_SECTD
R-0h

18
GRAB_SECTJ
R-0h

4
GRAB_SECTC
R-0h

16
GRAB_SECTI
R-0h

10

9

GRAB_SECTF
R-0h

8
GRAB_SECTE
R-0h

2

1

GRAB_SECTB
R-0h

0
GRAB_SECTA
R-0h

Table 2-239. Z2_GRABSECTR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

R

0h

Reserved

29-28

RESERVED

R

0h

Reserved

27-26

GRAB_SECTN

R

0h

Value in this field gets loaded from Z2_GRABSECT[27:26] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector N is inaccessible.
01 : Request to allocate Flash Sector N to Zone2.
10 : Request to allocate Flash Sector N to Zone2.
11 : Request to make Flash sector N Non-Secure.
Reset type: SYSRSn

25-24

GRAB_SECTM

R

0h

Value in this field gets loaded from Z2_GRABSECT[25:24] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector M is inaccessible.
01 : Request to allocate Flash Sector M to Zone2.
10 : Request to allocate Flash Sector M to Zone2.
11 : Request to make Flash sector M Non-Secure.
Reset type: SYSRSn

23-22

GRAB_SECTL

R

0h

Value in this field gets loaded from Z2_GRABSECT[23:22] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector L is inaccessible.
01 : Request to allocate Flash Sector L to Zone2.
10 : Request to allocate Flash Sector L to Zone2.
11 : Request to make Flash sector L Non-Secure.
Reset type: SYSRSn

432

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-239. Z2_GRABSECTR Register Field Descriptions (continued)
Bit
21-20

Field

Type

Reset

Description

GRAB_SECTK

R

0h

Value in this field gets loaded from Z2_GRABSECT[21:20] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector K is inaccessible.
01 : Request to allocate Flash Sector K to Zone2.
10 : Request to allocate Flash Sector K to Zone2.
11 : Request to make Flash sector K Non-Secure.
Reset type: SYSRSn

19-18

GRAB_SECTJ

R

0h

Value in this field gets loaded from Z2_GRABSECT[19:18] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector J is inaccessible.
01 : Request to allocate Flash Sector J to Zone2.
10 : Request to allocate Flash Sector J to Zone2.
11 : Request to make Flash sector J Non-Secure.
Reset type: SYSRSn

17-16

GRAB_SECTI

R

0h

Value in this field gets loaded from Z2_GRABSECT[17:16] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector I is inaccessible.
01 : Request to allocate Flash Sector I to Zone2.
10 : Request to allocate Flash Sector I to Zone2.
11 : Request to make Flash sector I Non-Secure.
Reset type: SYSRSn

15-14

GRAB_SECTH

R

0h

Value in this field gets loaded from Z2_GRABSECT[15:14] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector H is inaccessible.
01 : Request to allocate Flash Sector H to Zone2.
10 : Request to allocate Flash Sector H to Zone2.
11 : Request to make Flash sector H Non-Secure.
Reset type: SYSRSn

13-12

GRAB_SECTG

R

0h

Value in this field gets loaded from Z2_GRABSECT[13:12] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector G is inaccessible.
01 : Request to allocate Flash Sector G to Zone2.
10 : Request to allocate Flash Sector G to Zone2.
11 : Request to make Flash sector G Non-Secure.
Reset type: SYSRSn

11-10

GRAB_SECTF

R

0h

Value in this field gets loaded from Z2_GRABSECT[11:10] when a
read is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector F is inaccessible.
01 : Request to allocate Flash Sector F to Zone2.
10 : Request to allocate Flash Sector F to Zone2.
11 : Request to make Flash sector F Non-Secure.
Reset type: SYSRSn

9-8

GRAB_SECTE

R

0h

Value in this field gets loaded from Z2_GRABSECT[9:8] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector E is inaccessible.
01 : Request to allocate Flash Sector E to Zone2.
10 : Request to allocate Flash Sector E to Zone2.
11 : Request to make Flash sector E Non-Secure.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

433

Registers

www.ti.com

Table 2-239. Z2_GRABSECTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

GRAB_SECTD

R

0h

Value in this field gets loaded from Z2_GRABSECT[7:6] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector D is inaccessible.
01 : Request to allocate Flash Sector D to Zone2.
10 : Request to allocate Flash Sector D to Zone2.
11 : Request to make Flash sector D Non-Secure.
Reset type: SYSRSn

5-4

GRAB_SECTC

R

0h

Value in this field gets loaded from Z2_GRABSECT[5:4] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector C is inaccessible.
01 : Request to allocate Flash Sector C to Zone2.
10 : Request to allocate Flash Sector C to Zone2.
11 : Request to make Flash sector C Non-Secure.
Reset type: SYSRSn

3-2

GRAB_SECTB

R

0h

Value in this field gets loaded from Z2_GRABSECT[3:2] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector B is inaccessible.
01 : Request to allocate Flash Sector B to Zone2.
10 : Request to allocate Flash Sector B to Zone2.
11 : Request to make Flash sector B Non-Secure.
Reset type: SYSRSn

1-0

GRAB_SECTA

R

0h

Value in this field gets loaded from Z2_GRABSECT[1:0] when a read
is issued to address location of Z2_GRABSECT in OTP.
00 : Invalid. Flash Sector A is inaccessible.
01 : Request to allocate Flash Sector A to Zone2.
10 : Request to allocate Flash Sector A to Zone2.
11 : Request to make Flash sector A Non-Secure.
Reset type: SYSRSn

434

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.16.11 Z2_GRABRAMR Register (Offset = 1Ch) [reset = 0h]
Z2_GRABRAMR is shown in Figure 2-218 and described in Table 2-240.
Return to Summary Table.
Zone 2 Grab RAM Blocks Register
Figure 2-218. Z2_GRABRAMR Register
31

30

29

RESERVED
R-0h
23

28

27

26

25

24

18

17

16

10

9

GRAB_CLA1
R-0h
22

21

RESERVED
R-0h
20

19
RESERVED
R-0h

15

14

13

GRAB_RAM7
R-0h
7

12

11

GRAB_RAM6
R-0h
6

5

GRAB_RAM3
R-0h

GRAB_RAM5
R-0h
4

3

GRAB_RAM2
R-0h

8
GRAB_RAM4
R-0h

2

1

GRAB_RAM1
R-0h

0
GRAB_RAM0
R-0h

Table 2-240. Z2_GRABRAMR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

R

0h

Reserved

29-28

GRAB_CLA1

R

0h

Value in this field gets loaded from Z2_GRABRAM[29:28] when a
read is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. CLA1 is inaccessible.
01 : Request to allocate CLA1 to Zone2.
10 : Request to allocate CLA1 to Zone2.
11 : Request to make CLA1 Non-Secure.
Reset type: SYSRSn

27-16

RESERVED

R

0h

Reserved

15-14

GRAB_RAM7

R

0h

Value in this field gets loaded from Z2_GRABRAM[15:14] when a
read is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. D1 RAM is inaccessible.
01 : Request to allocate D1 RAM to Zone2.
10 : Request to allocate D1 RAM to Zone2.
11 : Request to make D1 RAM Non-Secure.
Reset type: SYSRSn

13-12

GRAB_RAM6

R

0h

Value in this field gets loaded from Z2_GRABRAM[13:12] when a
read is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. D0 RAM is inaccessible.
01 : Request to allocate D0 RAM to Zone2.
10 : Request to allocate D0 RAM to Zone2.
11 : Request to make D0 RAM Non-Secure.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

435

Registers

www.ti.com

Table 2-240. Z2_GRABRAMR Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

GRAB_RAM5

R

0h

Value in this field gets loaded from Z2_GRABRAM[11:10] when a
read is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS5 RAM is inaccessible.
01 : Request to allocate LS5 RAM to Zone2.
10 : Request to allocate LS5 RAM to Zone2.
11 : Request to make LS5 RAM Non-Secure.
Reset type: SYSRSn

9-8

GRAB_RAM4

R

0h

Value in this field gets loaded from Z2_GRABRAM[9:8] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS4 RAM is inaccessible.
01 : Request to allocate LS4 RAM to Zone2.
10 : Request to allocate LS4 RAM to Zone2.
11 : Request to make LS4 RAM Non-Secure.
Reset type: SYSRSn

7-6

GRAB_RAM3

R

0h

Value in this field gets loaded from Z2_GRABRAM[7:6] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS3 RAM is inaccessible.
01 : Request to allocate LS3 RAM to Zone2.
10 : Request to allocate LS3 RAM to Zone2.
11 : Request to make LS3 RAM Non-Secure.
Reset type: SYSRSn

5-4

GRAB_RAM2

R

0h

Value in this field gets loaded from Z2_GRABRAM[5:4] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS2 RAM is inaccessible.
01 : Request to allocate LS2 RAM to Zone2.
10 : Request to allocate LS2 RAM to Zone2.
11 : Request to make LS2 RAM Non-Secure.
Reset type: SYSRSn

3-2

GRAB_RAM1

R

0h

Value in this field gets loaded from Z2_GRABRAM[3:2] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS1 RAM is inaccessible.
01 : Request to allocate LS1 RAM to Zone2.
10 : Request to allocate LS1 RAM to Zone2.
11 : Request to make LS1 RAM Non-Secure.
Reset type: SYSRSn

1-0

GRAB_RAM0

R

0h

Value in this field gets loaded from Z2_GRABRAM[1:0] when a read
is issued to address location of Z2_GRABRAM in OTP.
00 : Invalid. LS0 RAM is inaccessible.
01 : Request to allocate LS0 RAM to Zone2.
10 : Request to allocate LS0 RAM to Zone2.
11 : Request to make LS0 RAM Non-Secure.
Reset type: SYSRSn

436

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.16.12 Z2_EXEONLYSECTR Register (Offset = 1Eh) [reset = 0h]
Z2_EXEONLYSECTR is shown in Figure 2-219 and described in Table 2-241.
Return to Summary Table.
Zone 2 Flash Execute_Only Sector Register
Figure 2-219. Z2_EXEONLYSECTR Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
RESERVED

14
RESERVED
R-0h

13
EXEONLY_SE
CTN
R-0h

12
EXEONLY_SE
CTM
R-0h

11
EXEONLY_SE
CTL
R-0h

10
EXEONLY_SE
CTK
R-0h

9
EXEONLY_SE
CTJ
R-0h

8
EXEONLY_SE
CTI
R-0h

R-0h
7
EXEONLY_SE
CTH
R-0h

6
EXEONLY_SE
CTG
R-0h

5
EXEONLY_SE
CTF
R-0h

4
EXEONLY_SE
CTE
R-0h

3
EXEONLY_SE
CTD
R-0h

2
EXEONLY_SE
CTC
R-0h

1
EXEONLY_SE
CTB
R-0h

0
EXEONLY_SE
CTA
R-0h

Table 2-241. Z2_EXEONLYSECTR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

EXEONLY_SECTN

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[13:13] when
a read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector N (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector N (only if it's
allocated to Zone2)
Reset type: SYSRSn

12

EXEONLY_SECTM

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[12:12] when
a read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector M (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector M (only if it's
allocated to Zone2)
Reset type: SYSRSn

11

EXEONLY_SECTL

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[11:11] when
a read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector L (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector L (only if it's
allocated to Zone2)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

437

Registers

www.ti.com

Table 2-241. Z2_EXEONLYSECTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

10

EXEONLY_SECTK

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[10:10] when
a read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector K (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector K (only if it's
allocated to Zone2)
Reset type: SYSRSn

9

EXEONLY_SECTJ

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[9:9] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector J (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector J (only if it's
allocated to Zone2)
Reset type: SYSRSn

8

EXEONLY_SECTI

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[8:8] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector I (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector I (only if it's
allocated to Zone2)
Reset type: SYSRSn

7

EXEONLY_SECTH

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[7:7] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector H (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector H (only if it's
allocated to Zone2)
Reset type: SYSRSn

6

EXEONLY_SECTG

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[6:6] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector G (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector G (only if it's
allocated to Zone2)
Reset type: SYSRSn

5

EXEONLY_SECTF

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[5:5] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector F (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector F (only if it's
allocated to Zone2)
Reset type: SYSRSn

4

EXEONLY_SECTE

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[4:4] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector E (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector E (only if it's
allocated to Zone2)
Reset type: SYSRSn

438

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-241. Z2_EXEONLYSECTR Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

EXEONLY_SECTD

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[3:3] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector D (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector D (only if it's
allocated to Zone2)
Reset type: SYSRSn

2

EXEONLY_SECTC

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[2:2] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector C (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector C (only if it's
allocated to Zone2)
Reset type: SYSRSn

1

EXEONLY_SECTB

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[1:1] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector B (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector B (only if it's
allocated to Zone2)
Reset type: SYSRSn

0

EXEONLY_SECTA

R

0h

Value in this field gets loaded from Z2_EXEONLYSECT[0:0] when a
read is issued to Z2_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector A (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector A (only if it's
allocated to Zone2)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

439

Registers

www.ti.com

2.15.16.13 Z2_EXEONLYRAMR Register (Offset = 20h) [reset = 0h]
Z2_EXEONLYRAMR is shown in Figure 2-220 and described in Table 2-242.
Return to Summary Table.
Zone 2 RAM Execute_Only Block Register
Figure 2-220. Z2_EXEONLYRAMR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
EXEONLY_RA
M3
R-0h

2
EXEONLY_RA
M2
R-0h

1
EXEONLY_RA
M1
R-0h

0
EXEONLY_RA
M0
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
EXEONLY_RA
M7
R-0h

6
EXEONLY_RA
M6
R-0h

5
EXEONLY_RA
M5
R-0h

4
EXEONLY_RA
M4
R-0h

Table 2-242. Z2_EXEONLYRAMR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

EXEONLY_RAM7

R

0h

Value in this field gets loaded from Z2_EXEONLYRAM[7:7] when a
read is issued to Z2_EXEONLYRAM address location in OTP.

7

0 : Execute-Only protection is enabled for D1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for D1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
6

EXEONLY_RAM6

R

0h

Value in this field gets loaded from Z2_EXEONLYRAM[6:6] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for D0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for D0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

5

EXEONLY_RAM5

R

0h

Value in this field gets loaded from Z2_EXEONLYRAM[5:5] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS5 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS5 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

4

EXEONLY_RAM4

R

0h

Value in this field gets loaded from Z2_EXEONLYRAM[4:4] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS4 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS4 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

440

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-242. Z2_EXEONLYRAMR Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

EXEONLY_RAM3

R

0h

Value in this field gets loaded from Z2_EXEONLYRAM[3:3] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS3 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS3 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

2

EXEONLY_RAM2

R

0h

Value in this field gets loaded from Z2_EXEONLYRAM[2:2] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS2 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS2 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

1

EXEONLY_RAM1

R

0h

Value in this field gets loaded from Z2_EXEONLYRAM[1:1] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

0

EXEONLY_RAM0

R

0h

Value in this field gets loaded from Z2_EXEONLYRAM[0:0] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

441

Registers

www.ti.com

2.15.17 DCSM_COMMON_REGS Registers
Table 2-243 lists the memory-mapped registers for the DCSM_COMMON_REGS. All register offset
addresses not listed in Table 2-243 should be considered as reserved locations and the register contents
should not be modified.
Table 2-243. DCSM_COMMON_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

FLSEM

Flash Wrapper Semaphore Register

Go

2h

SECTSTAT

Sectors Status Register

Go

4h

RAMSTAT

RAM Status Register

Go

Complex bit access types are encoded to fit into small table cells. Table 2-244 shows the codes that are
used for access types in this section.
Table 2-244. DCSM_COMMON_REGS Access Type
Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

Write

Read Type

Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

442

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.17.1 FLSEM Register (Offset = 0h) [reset = 0h]
FLSEM is shown in Figure 2-221 and described in Table 2-245.
Return to Summary Table.
Flash Wrapper Semaphore Register
Figure 2-221. FLSEM Register
31

30

29

28

27

26

25

15

14

13

12

11
KEY
R=0/W-0h

10

9

24
23
RESERVED
R-0h
8

7

22

21

20

19

18

17

16

6

5
4
RESERVED
R-0h

3

2

1

0

SEM
R/W-0h

Table 2-245. FLSEM Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-8

KEY

R=0/W

0h

Writing a value 0xA5 into this field will allow the writing of the SEM
bits, else writes are ignored. Reads will return 0.
Reset type: SYSRSn

7-2

RESERVED

R

0h

Reserved

1-0

SEM

R/W

0h

00 : C28X Flash Wrapper registers can be written by code running
from non-secure zone.
01 : Flash Wrapper registers can be written by code running from
Zone1 security zone only. User must set this value to perform flash
operation on flash sectors of Zone1.
10 : C28X Flash Wrapper registers can be written by code running
from Zone2 security zone only. User must set this value to perform
flash operation on flash sectors of Zone2.
11 : C28X Flash Wrapper registers can be written by code running
from non-secure zone.
Allowed State Transitions in this field.
00 to 11 : Code running from anywhere.
11 to 00 : Not allowed.
00/11 to 01 : Code running from Zone1 only can perform this
transition.
01 to 00/11 : Code running from Zone1 only can perform this
transition.
00/11 to 10 : Code running from Zone2 only can perform this
transition.
10 to 00/11 : Code running from Zone2 can perform this transition
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

443

Registers

www.ti.com

2.15.17.2 SECTSTAT Register (Offset = 2h) [reset = 0h]
SECTSTAT is shown in Figure 2-222 and described in Table 2-246.
Return to Summary Table.
Sectors Status Register
Figure 2-222. SECTSTAT Register
31

30

29

28

RESERVED
R-0h

RESERVED
R-0h

27
26
STATUS_SECTN
R-0h

25
24
STATUS_SECTM
R-0h

23
22
STATUS_SECTL
R-0h

21
20
STATUS_SECTK
R-0h

19
18
STATUS_SECTJ
R-0h

17
16
STATUS_SECTI
R-0h

15
14
STATUS_SECTH
R-0h

13
12
STATUS_SECTG
R-0h

11
10
STATUS_SECTF
R-0h

9
8
STATUS_SECTE
R-0h

7
6
STATUS_SECTD
R-0h

5
4
STATUS_SECTC
R-0h

3
2
STATUS_SECTB
R-0h

1
0
STATUS_SECTA
R-0h

Table 2-246. SECTSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

R

0h

Reserved

29-28

RESERVED

R

0h

Reserved

27-26

STATUS_SECTN

R

0h

Reflects the status of flash sector N.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

25-24

STATUS_SECTM

R

0h

Reflects the status of flash sector M.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

23-22

STATUS_SECTL

R

0h

Reflects the status of flash sector L.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

444

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-246. SECTSTAT Register Field Descriptions (continued)
Bit
21-20

Field

Type

Reset

Description

STATUS_SECTK

R

0h

Reflects the status of flash sector K.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

19-18

STATUS_SECTJ

R

0h

Reflects the status of flash sector J.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

17-16

STATUS_SECTI

R

0h

Reflects the status of flash sector I.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

15-14

STATUS_SECTH

R

0h

Reflects the status of flash sector H.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

13-12

STATUS_SECTG

R

0h

Reflects the status of flash sector G.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

11-10

STATUS_SECTF

R

0h

Reflects the status of flash sector F.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

9-8

STATUS_SECTE

R

0h

Reflects the status of flash sector E.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

445

Registers

www.ti.com

Table 2-246. SECTSTAT Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

STATUS_SECTD

R

0h

Reflects the status of flash sector D.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

5-4

STATUS_SECTC

R

0h

Reflects the status of flash sector C.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

3-2

STATUS_SECTB

R

0h

Reflects the status of flash sector B.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

1-0

STATUS_SECTA

R

0h

Reflects the status of flash sector A.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

446

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.17.3 RAMSTAT Register (Offset = 4h) [reset = 0h]
RAMSTAT is shown in Figure 2-223 and described in Table 2-247.
Return to Summary Table.
RAM Status Register
Figure 2-223. RAMSTAT Register
31

30
RESERVED
R-0h

23

22

29
28
STATUS_CLA1
R-0h
21

27

26

25

24

18

17

16

8

RESERVED
R-0h

20

19
RESERVED
R-0h

15
14
STATUS_RAM7
R-0h

13
12
STATUS_RAM6
R-0h

11
10
STATUS_RAM5
R-0h

9

7

5

3

1

6
STATUS_RAM3
R-0h

4
STATUS_RAM2
R-0h

2
STATUS_RAM1
R-0h

STATUS_RAM4
R-0h
0
STATUS_RAM0
R-0h

Table 2-247. RAMSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

R

0h

Reserved

29-28

STATUS_CLA1

R

0h

Reflects the status of CLA1.
00 : CLA is in-accessible
01 : CLA belongs to Zone1.
10 : CLA belongs to Zone2.
11: CLA is un-secure and code running in both zone have full access
to it.
Reset type: SYSRSn

27-16

RESERVED

R

0h

Reserved

15-14

STATUS_RAM7

R

0h

Reflects the status of D1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

13-12

STATUS_RAM6

R

0h

Reflects the status of D0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

447

Registers

www.ti.com

Table 2-247. RAMSTAT Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

STATUS_RAM5

R

0h

Reflects the status of LS5 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

9-8

STATUS_RAM4

R

0h

Reflects the status of LS4 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

7-6

STATUS_RAM3

R

0h

Reflects the status of LS3 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

5-4

STATUS_RAM2

R

0h

Reflects the status of LS2 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

3-2

STATUS_RAM1

R

0h

Reflects the status of LS1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

1-0

STATUS_RAM0

R

0h

Reflects the status of LS0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

448

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18 MEM_CFG_REGS Registers
Table 2-248 lists the memory-mapped registers for the MEM_CFG_REGS. All register offset addresses
not listed in Table 2-248 should be considered as reserved locations and the register contents should not
be modified.
Table 2-248. MEM_CFG_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

DxLOCK

Dedicated RAM Config Lock Register

EALLOW

Go

2h

DxCOMMIT

Dedicated RAM Config Lock Commit Register

EALLOW

Go

8h

DxACCPROT0

Dedicated RAM Config Register

EALLOW

Go

10h

DxTEST

Dedicated RAM TEST Register

EALLOW

Go

12h

DxINIT

Dedicated RAM Init Register

EALLOW

Go

14h

DxINITDONE

Dedicated RAM InitDone Status Register

20h

LSxLOCK

Local Shared RAM Config Lock Register

EALLOW

Go

22h

LSxCOMMIT

Local Shared RAM Config Lock Commit Register EALLOW

Go

24h

LSxMSEL

Local Shared RAM Master Sel Register

EALLOW

Go

26h

LSxCLAPGM

Local Shared RAM Prog/Exe control Register

EALLOW

Go

Go

28h

LSxACCPROT0

Local Shared RAM Config Register 0

EALLOW

Go

2Ah

LSxACCPROT1

Local Shared RAM Config Register 1

EALLOW

Go

30h

LSxTEST

Local Shared RAM TEST Register

EALLOW

Go

32h

LSxINIT

Local Shared RAM Init Register

EALLOW

Go

34h

LSxINITDONE

Local Shared RAM InitDone Status Register

40h

GSxLOCK

Global Shared RAM Config Lock Register

EALLOW

Go

42h

GSxCOMMIT

Global Shared RAM Config Lock Commit
Register

EALLOW

Go

44h

GSxMSEL

Global Shared RAM Master Sel Register

EALLOW

Go

48h

GSxACCPROT0

Global Shared RAM Config Register 0

EALLOW

Go

Go

4Ah

GSxACCPROT1

Global Shared RAM Config Register 1

EALLOW

Go

4Ch

GSxACCPROT2

Global Shared RAM Config Register 2

EALLOW

Go

4Eh

GSxACCPROT3

Global Shared RAM Config Register 3

EALLOW

Go

50h

GSxTEST

Global Shared RAM TEST Register

EALLOW

Go

52h

GSxINIT

Global Shared RAM Init Register

EALLOW

Go

54h

GSxINITDONE

Global Shared RAM InitDone Status Register

70h

MSGxTEST

Message RAM TEST Register

EALLOW

Go

72h

MSGxINIT

Message RAM Init Register

EALLOW

Go

74h

MSGxINITDONE

Message RAM InitDone Status Register

Go

Go

Complex bit access types are encoded to fit into small table cells. Table 2-249 shows the codes that are
used for access types in this section.
Table 2-249. MEM_CFG_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

449

Registers

www.ti.com

Table 2-249. MEM_CFG_REGS Access Type
Codes (continued)
Access Type

Code

-n

Description
Value after reset or the default
value

Register Array Variables

450

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.1 DxLOCK Register (Offset = 0h) [reset = 0h]
DxLOCK is shown in Figure 2-224 and described in Table 2-250.
Return to Summary Table.
Dedicated RAM Config Lock Register
Figure 2-224. DxLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
LOCK_D1
R/W-0h

2
LOCK_D0
R/W-0h

1

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

0
RESERVED
R-0h

Table 2-250. DxLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

LOCK_D1

R/W

0h

Locks the write to access protection and master select fields for D1
RAM:

3

0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
2

LOCK_D0

R/W

0h

Locks the write to access protection and master select fields for D0
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

1-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

451

Registers

www.ti.com

2.15.18.2 DxCOMMIT Register (Offset = 2h) [reset = 0h]
DxCOMMIT is shown in Figure 2-225 and described in Table 2-251.
Return to Summary Table.
Dedicated RAM Config Lock Commit Register
Figure 2-225. DxCOMMIT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
COMMIT_D1
R/WSOnce-0h

2
COMMIT_D0
R/WSOnce-0h

1

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

0
RESERVED
R-0h

Table 2-251. DxCOMMIT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

3

COMMIT_D1

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for D1 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in DxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

2

COMMIT_D0

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for D0 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in DxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

1-0

452

RESERVED

System Control

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.3 DxACCPROT0 Register (Offset = 8h) [reset = 0h]
DxACCPROT0 is shown in Figure 2-226 and described in Table 2-252.
Return to Summary Table.
Dedicated RAM Config Register
Figure 2-226. DxACCPROT0 Register
31

30

29

28

27

26

25
24
CPUWRPROT_ FETCHPROT_
D1
D1
R/W-0h
R/W-0h

20

19

18

17
16
CPUWRPROT_ FETCHPROT_
D0
D0
R/W-0h
R/W-0h

11

10

9

8

3

2

1

0

RESERVED
R-0h
23

22

21
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-252. DxACCPROT0 Register Field Descriptions
Bit
31-26
25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

CPUWRPROT_D1

R/W

0h

CPU WR Protection For D1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

24

FETCHPROT_D1

R/W

0h

Fetch Protection For D1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

23-18
17

RESERVED

R

0h

Reserved

CPUWRPROT_D0

R/W

0h

CPU WR Protection For D0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn

16

FETCHPROT_D0

R/W

0h

Fetch Protection For D0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

15-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

453

Registers

www.ti.com

2.15.18.4 DxTEST Register (Offset = 10h) [reset = 0h]
DxTEST is shown in Figure 2-227 and described in Table 2-253.
Return to Summary Table.
Dedicated RAM TEST Register
Figure 2-227. DxTEST Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

TEST_D1
R/W-0h

3

TEST_D0
R/W-0h

TEST_M1
R/W-0h

0
TEST_M0
R/W-0h

Table 2-253. DxTEST Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-8

RESERVED

R

0h

Reserved

7-6

TEST_D1

R/W

0h

Selects the defferent modes for D1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

5-4

TEST_D0

R/W

0h

Selects the defferent modes for D0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

3-2

TEST_M1

R/W

0h

Selects the defferent modes for M1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

1-0

TEST_M0

R/W

0h

Selects the defferent modes for M0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

454

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.5 DxINIT Register (Offset = 12h) [reset = 0h]
DxINIT is shown in Figure 2-228 and described in Table 2-254.
Return to Summary Table.
Dedicated RAM Init Register
Figure 2-228. DxINIT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
INIT_D1
R=0/W=1-0h

2
INIT_D0
R=0/W=1-0h

1
INIT_M1
R=0/W=1-0h

0
INIT_M0
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

Table 2-254. DxINIT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

INIT_D1

R=0/W=1

0h

RAM Initialization control for D1 RAM:

3

0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2

INIT_D0

R=0/W=1

0h

RAM Initialization control for D0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

1

INIT_M1

R=0/W=1

0h

RAM Initialization control for M1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

0

INIT_M0

R=0/W=1

0h

RAM Initialization control for M0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

455

Registers

www.ti.com

2.15.18.6 DxINITDONE Register (Offset = 14h) [reset = 0h]
DxINITDONE is shown in Figure 2-229 and described in Table 2-255.
Return to Summary Table.
Dedicated RAM InitDone Status Register
Figure 2-229. DxINITDONE Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
INITDONE_D1
R-0h

2
INITDONE_D0
R-0h

1
INITDONE_M1
R-0h

0
INITDONE_M0
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

Table 2-255. DxINITDONE Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

INITDONE_D1

R

0h

RAM Initialization status for D1 RAM:

3

0: RAM Initialization has completed.
1: RAM Initialization has completed.
Reset type: SYSRSn
2

INITDONE_D0

R

0h

RAM Initialization status for D0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

1

INITDONE_M1

R

0h

RAM Initialization status for M1 RAM:
0: RAM Initialization has completed.
1: RAM Initialization has completed.
Reset type: SYSRSn

0

INITDONE_M0

R

0h

RAM Initialization status for M0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

456

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.7 LSxLOCK Register (Offset = 20h) [reset = 0h]
LSxLOCK is shown in Figure 2-230 and described in Table 2-256.
Return to Summary Table.
Local Shared RAM Config Lock Register
Figure 2-230. LSxLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
LOCK_LS3
R/W-0h

2
LOCK_LS2
R/W-0h

1
LOCK_LS1
R/W-0h

0
LOCK_LS0
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED
R-0h

5
LOCK_LS5
R/W-0h

4
LOCK_LS4
R/W-0h

Table 2-256. LSxLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

5

LOCK_LS5

R/W

0h

Locks the write to access protection and master select fields for LS5
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

4

LOCK_LS4

R/W

0h

Locks the write to access protection and master select fields for LS4
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

3

LOCK_LS3

R/W

0h

Locks the write to access protection and master select fields for LS3
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

2

LOCK_LS2

R/W

0h

Locks the write to access protection and master select fields for LS2
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

1

LOCK_LS1

R/W

0h

Locks the write to access protection and master select fields for LS1
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

457

Registers

www.ti.com

Table 2-256. LSxLOCK Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

LOCK_LS0

R/W

0h

Locks the write to access protection and master select fields for LS0
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

458

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.8 LSxCOMMIT Register (Offset = 22h) [reset = 0h]
LSxCOMMIT is shown in Figure 2-231 and described in Table 2-257.
Return to Summary Table.
Local Shared RAM Config Lock Commit Register
Figure 2-231. LSxCOMMIT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
COMMIT_LS3
R/WSOnce-0h

2
COMMIT_LS2
R/WSOnce-0h

1
COMMIT_LS1
R/WSOnce-0h

0
COMMIT_LS0
R/WSOnce-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED
R-0h

5
COMMIT_LS5
R/WSOnce-0h

4
COMMIT_LS4
R/WSOnce-0h

Table 2-257. LSxCOMMIT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

COMMIT_LS5

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for LS5 RAM:

5

0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
4

COMMIT_LS4

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for LS4 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

3

COMMIT_LS3

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for LS3 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

2

COMMIT_LS2

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for LS2 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

459

Registers

www.ti.com

Table 2-257. LSxCOMMIT Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

COMMIT_LS1

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for LS1 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

0

COMMIT_LS0

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for LS0 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in LSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

460

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.9 LSxMSEL Register (Offset = 24h) [reset = 0h]
LSxMSEL is shown in Figure 2-232 and described in Table 2-258.
Return to Summary Table.
Local Shared RAM Master Sel Register
Figure 2-232. LSxMSEL Register
31

30

29

28

27

26

25

24

19

18

17

16

10

9

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12

11

RESERVED
R-0h
7

6

MSEL_LS5
R/W-0h
5

MSEL_LS3
R/W-0h

4

3

MSEL_LS2
R/W-0h

8
MSEL_LS4
R/W-0h

2
MSEL_LS1
R/W-0h

1

0
MSEL_LS0
R/W-0h

Table 2-258. LSxMSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-12

RESERVED

R

0h

Reserved

11-10

MSEL_LS5

R/W

0h

Master Select for LS5 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

9-8

MSEL_LS4

R/W

0h

Master Select for LS4 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

7-6

MSEL_LS3

R/W

0h

Master Select for LS3 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

5-4

MSEL_LS2

R/W

0h

Master Select for LS2 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

461

Registers

www.ti.com

Table 2-258. LSxMSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-2

MSEL_LS1

R/W

0h

Master Select for LS1 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

1-0

MSEL_LS0

R/W

0h

Master Select for LS0 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

462

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.10 LSxCLAPGM Register (Offset = 26h) [reset = 0h]
LSxCLAPGM is shown in Figure 2-233 and described in Table 2-259.
Return to Summary Table.
Local Shared RAM Prog/Exe control Register
Figure 2-233. LSxCLAPGM Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
CLAPGM_LS3
R/W-0h

2
CLAPGM_LS2
R/W-0h

1
CLAPGM_LS1
R/W-0h

0
CLAPGM_LS0
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED
R-0h

5
CLAPGM_LS5
R/W-0h

4
CLAPGM_LS4
R/W-0h

Table 2-259. LSxCLAPGM Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

CLAPGM_LS5

R/W

0h

Selects LS5 RAM as program vs data memory for CLA:

5

0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
4

CLAPGM_LS4

R/W

0h

Selects LS4 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

3

CLAPGM_LS3

R/W

0h

Selects LS3 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

2

CLAPGM_LS2

R/W

0h

Selects LS2 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

1

CLAPGM_LS1

R/W

0h

Selects LS1 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

0

CLAPGM_LS0

R/W

0h

Selects LS0 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

463

Registers

www.ti.com

2.15.18.11 LSxACCPROT0 Register (Offset = 28h) [reset = 0h]
LSxACCPROT0 is shown in Figure 2-234 and described in Table 2-260.
Return to Summary Table.
Local Shared RAM Config Register 0
Figure 2-234. LSxACCPROT0 Register
31

30

29

28

27

26

25
24
CPUWRPROT_ FETCHPROT_
LS3
LS3
R/W-0h
R/W-0h

20

19

18

17
16
CPUWRPROT_ FETCHPROT_
LS2
LS2
R/W-0h
R/W-0h

12

11

10

9
8
CPUWRPROT_ FETCHPROT_
LS1
LS1
R/W-0h
R/W-0h

4

3

2

1
0
CPUWRPROT_ FETCHPROT_
LS0
LS0
R/W-0h
R/W-0h

RESERVED
R-0h
23

22

21
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7

6

5
RESERVED
R-0h

Table 2-260. LSxACCPROT0 Register Field Descriptions
Bit
31-26
25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

CPUWRPROT_LS3

R/W

0h

CPU WR Protection For LS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

24

FETCHPROT_LS3

R/W

0h

Fetch Protection For LS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

23-18
17

RESERVED

R

0h

Reserved

CPUWRPROT_LS2

R/W

0h

CPU WR Protection For LS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

16

FETCHPROT_LS2

R/W

0h

Fetch Protection For LS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

15-10
9

RESERVED

R

0h

Reserved

CPUWRPROT_LS1

R/W

0h

CPU WR Protection For LS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

464

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-260. LSxACCPROT0 Register Field Descriptions (continued)
Bit
8

Field

Type

Reset

Description

FETCHPROT_LS1

R/W

0h

Fetch Protection For LS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

7-2
1

RESERVED

R

0h

Reserved

CPUWRPROT_LS0

R/W

0h

CPU WR Protection For LS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

0

FETCHPROT_LS0

R/W

0h

Fetch Protection For LS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

465

Registers

www.ti.com

2.15.18.12 LSxACCPROT1 Register (Offset = 2Ah) [reset = 0h]
LSxACCPROT1 is shown in Figure 2-235 and described in Table 2-261.
Return to Summary Table.
Local Shared RAM Config Register 1
Figure 2-235. LSxACCPROT1 Register
31

30

29

28

27

26

25

24

19

18

17

16

12

11

10

9
8
CPUWRPROT_ FETCHPROT_
LS5
LS5
R/W-0h
R/W-0h

4

3

2

1
0
CPUWRPROT_ FETCHPROT_
LS4
LS4
R/W-0h
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7

6

5
RESERVED
R-0h

Table 2-261. LSxACCPROT1 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-10

RESERVED

R

0h

Reserved

CPUWRPROT_LS5

R/W

0h

CPU WR Protection For LS5 RAM:

9

0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8

FETCHPROT_LS5

R/W

0h

Fetch Protection For LS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

7-2
1

RESERVED

R

0h

Reserved

CPUWRPROT_LS4

R/W

0h

CPU WR Protection For LS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

0

FETCHPROT_LS4

R/W

0h

Fetch Protection For LS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

466

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.13 LSxTEST Register (Offset = 30h) [reset = 0h]
LSxTEST is shown in Figure 2-236 and described in Table 2-262.
Return to Summary Table.
Local Shared RAM TEST Register
Figure 2-236. LSxTEST Register
31

30

29

28

27

26

25

24

19

18

17

16

10

9

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12

11

RESERVED
R-0h
7

6

TEST_LS5
R/W-0h
5

TEST_LS3
R/W-0h

4

3

TEST_LS2
R/W-0h

8
TEST_LS4
R/W-0h

2
TEST_LS1
R/W-0h

1

0
TEST_LS0
R/W-0h

Table 2-262. LSxTEST Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-12

RESERVED

R

0h

Reserved

11-10

TEST_LS5

R/W

0h

Selects the defferent modes for LS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

9-8

TEST_LS4

R/W

0h

Selects the defferent modes for LS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

7-6

TEST_LS3

R/W

0h

Selects the defferent modes for LS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

5-4

TEST_LS2

R/W

0h

Selects the defferent modes for LS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

467

Registers

www.ti.com

Table 2-262. LSxTEST Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-2

TEST_LS1

R/W

0h

Selects the defferent modes for LS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

1-0

TEST_LS0

R/W

0h

Selects the defferent modes for LS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

468

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.14 LSxINIT Register (Offset = 32h) [reset = 0h]
LSxINIT is shown in Figure 2-237 and described in Table 2-263.
Return to Summary Table.
Local Shared RAM Init Register
Figure 2-237. LSxINIT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
INIT_LS3
R=0/W=1-0h

2
INIT_LS2
R=0/W=1-0h

1
INIT_LS1
R=0/W=1-0h

0
INIT_LS0
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED
R-0h

5
INIT_LS5
R=0/W=1-0h

4
INIT_LS4
R=0/W=1-0h

Table 2-263. LSxINIT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

INIT_LS5

R=0/W=1

0h

RAM Initialization control for LS5 RAM:

5

0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4

INIT_LS4

R=0/W=1

0h

RAM Initialization control for LS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

3

INIT_LS3

R=0/W=1

0h

RAM Initialization control for LS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

2

INIT_LS2

R=0/W=1

0h

RAM Initialization control for LS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

1

INIT_LS1

R=0/W=1

0h

RAM Initialization control for LS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

0

INIT_LS0

R=0/W=1

0h

RAM Initialization control for LS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

469

Registers

www.ti.com

2.15.18.15 LSxINITDONE Register (Offset = 34h) [reset = 0h]
LSxINITDONE is shown in Figure 2-238 and described in Table 2-264.
Return to Summary Table.
Local Shared RAM InitDone Status Register
Figure 2-238. LSxINITDONE Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED
R-0h

5
4
3
2
1
0
INITDONE_LS5 INITDONE_LS4 INITDONE_LS3 INITDONE_LS2 INITDONE_LS1 INITDONE_LS0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h

Table 2-264. LSxINITDONE Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

INITDONE_LS5

R

0h

RAM Initialization status for LS5 RAM:

5

0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4

INITDONE_LS4

R

0h

RAM Initialization status for LS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

3

INITDONE_LS3

R

0h

RAM Initialization status for LS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

2

INITDONE_LS2

R

0h

RAM Initialization status for LS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

1

INITDONE_LS1

R

0h

RAM Initialization status for LS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

0

INITDONE_LS0

R

0h

RAM Initialization status for LS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

470

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.16 GSxLOCK Register (Offset = 40h) [reset = 0h]
GSxLOCK is shown in Figure 2-239 and described in Table 2-265.
Return to Summary Table.
Global Shared RAM Config Lock Register
Figure 2-239. GSxLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
LOCK_GS15
R/W-0h

14
LOCK_GS14
R/W-0h

13
LOCK_GS13
R/W-0h

12
LOCK_GS12
R/W-0h

11
LOCK_GS11
R/W-0h

10
LOCK_GS10
R/W-0h

9
LOCK_GS9
R/W-0h

8
LOCK_GS8
R/W-0h

7
LOCK_GS7
R/W-0h

6
LOCK_GS6
R/W-0h

5
LOCK_GS5
R/W-0h

4
LOCK_GS4
R/W-0h

3
LOCK_GS3
R/W-0h

2
LOCK_GS2
R/W-0h

1
LOCK_GS1
R/W-0h

0
LOCK_GS0
R/W-0h

Table 2-265. GSxLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15

LOCK_GS15

R/W

0h

Locks the write to access protection and master select fields for
GS15 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

14

LOCK_GS14

R/W

0h

Locks the write to access protection and master select fields for
GS14 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

13

LOCK_GS13

R/W

0h

Locks the write to access protection and master select fields for
GS13 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

12

LOCK_GS12

R/W

0h

Locks the write to access protection and master select fields for
GS12 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

11

LOCK_GS11

R/W

0h

Locks the write to access protection and master select fields for
GS11 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

471

Registers

www.ti.com

Table 2-265. GSxLOCK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

10

LOCK_GS10

R/W

0h

Locks the write to access protection and master select fields for
GS10 RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

9

LOCK_GS9

R/W

0h

Locks the write to access protection and master select fields for GS9
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

8

LOCK_GS8

R/W

0h

Locks the write to access protection and master select fields for GS8
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

7

LOCK_GS7

R/W

0h

Locks the write to access protection and master select fields for GS7
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

6

LOCK_GS6

R/W

0h

Locks the write to access protection and master select fields for GS6
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

5

LOCK_GS5

R/W

0h

Locks the write to access protection and master select fields for GS5
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

4

LOCK_GS4

R/W

0h

Locks the write to access protection and master select fields for GS4
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

3

LOCK_GS3

R/W

0h

Locks the write to access protection and master select fields for GS3
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

2

LOCK_GS2

R/W

0h

Locks the write to access protection and master select fields for GS2
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

1

LOCK_GS1

R/W

0h

Locks the write to access protection and master select fields for GS1
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

472

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-265. GSxLOCK Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

LOCK_GS0

R/W

0h

Locks the write to access protection and master select fields for GS0
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

473

Registers

www.ti.com

2.15.18.17 GSxCOMMIT Register (Offset = 42h) [reset = 0h]
GSxCOMMIT is shown in Figure 2-240 and described in Table 2-266.
Return to Summary Table.
Global Shared RAM Config Lock Commit Register
Figure 2-240. GSxCOMMIT Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
COMMIT_GS1
5
R/WSOnce-0h

14
COMMIT_GS1
4
R/WSOnce-0h

13
COMMIT_GS1
3
R/WSOnce-0h

12
COMMIT_GS1
2
R/WSOnce-0h

11
COMMIT_GS1
1
R/WSOnce-0h

10
COMMIT_GS1
0
R/WSOnce-0h

9
COMMIT_GS9

8
COMMIT_GS8

R/WSOnce-0h

R/WSOnce-0h

7
COMMIT_GS7
R/WSOnce-0h

6
COMMIT_GS6
R/WSOnce-0h

5
COMMIT_GS5
R/WSOnce-0h

4
COMMIT_GS4
R/WSOnce-0h

3
COMMIT_GS3
R/WSOnce-0h

2
COMMIT_GS2
R/WSOnce-0h

1
COMMIT_GS1
R/WSOnce-0h

0
COMMIT_GS0
R/WSOnce-0h

Table 2-266. GSxCOMMIT Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

COMMIT_GS15

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS15 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

14

COMMIT_GS14

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS14 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

13

COMMIT_GS13

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS13 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

12

COMMIT_GS12

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS12 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

11

COMMIT_GS11

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS11 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

474

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-266. GSxCOMMIT Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

10

COMMIT_GS10

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS10 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

9

COMMIT_GS9

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS9 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

8

COMMIT_GS8

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS2 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

7

COMMIT_GS7

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS7 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

6

COMMIT_GS6

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS6 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

5

COMMIT_GS5

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS5 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

4

COMMIT_GS4

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS4 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

3

COMMIT_GS3

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS3 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

2

COMMIT_GS2

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS2 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

475

Registers

www.ti.com

Table 2-266. GSxCOMMIT Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

COMMIT_GS1

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS1 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

0

COMMIT_GS0

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for GS0 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in GSxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

476

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.18 GSxMSEL Register (Offset = 44h) [reset = 0h]
GSxMSEL is shown in Figure 2-241 and described in Table 2-267.
Return to Summary Table.
Global Shared RAM Master Sel Register
Figure 2-241. GSxMSEL Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
MSEL_GS15
R/W-0h

14
MSEL_GS14
R/W-0h

13
MSEL_GS13
R/W-0h

12
MSEL_GS12
R/W-0h

11
MSEL_GS11
R/W-0h

10
MSEL_GS10
R/W-0h

9
MSEL_GS9
R/W-0h

8
MSEL_GS8
R/W-0h

7
MSEL_GS7
R/W-0h

6
MSEL_GS6
R/W-0h

5
MSEL_GS5
R/W-0h

4
MSEL_GS4
R/W-0h

3
MSEL_GS3
R/W-0h

2
MSEL_GS2
R/W-0h

1
MSEL_GS1
R/W-0h

0
MSEL_GS0
R/W-0h

Table 2-267. GSxMSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15

MSEL_GS15

R/W

0h

Master Select for GS15 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

14

MSEL_GS14

R/W

0h

Master Select for GS14 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

13

MSEL_GS13

R/W

0h

Master Select for GS13 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

12

MSEL_GS12

R/W

0h

Master Select for GS12 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

11

MSEL_GS11

R/W

0h

Master Select for GS11 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

10

MSEL_GS10

R/W

0h

Master Select for GS10 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

477

Registers

www.ti.com

Table 2-267. GSxMSEL Register Field Descriptions (continued)
Bit
9

Field

Type

Reset

Description

MSEL_GS9

R/W

0h

Master Select for GS9 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

8

MSEL_GS8

R/W

0h

Master Select for GS8 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

7

MSEL_GS7

R/W

0h

Master Select for GS7 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

6

MSEL_GS6

R/W

0h

Master Select for GS6 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

5

MSEL_GS5

R/W

0h

Master Select for GS5 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

4

MSEL_GS4

R/W

0h

Master Select for GS4 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

3

MSEL_GS3

R/W

0h

Master Select for GS3 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

2

MSEL_GS2

R/W

0h

Master Select for GS2 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

1

MSEL_GS1

R/W

0h

Master Select for GS1 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

0

MSEL_GS0

R/W

0h

Master Select for GS0 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

478

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.19 GSxACCPROT0 Register (Offset = 48h) [reset = 0h]
GSxACCPROT0 is shown in Figure 2-242 and described in Table 2-268.
Return to Summary Table.
Global Shared RAM Config Register 0
Figure 2-242. GSxACCPROT0 Register
31

30

29
RESERVED

28

27

26
25
24
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS3
GS3
GS3
R/W-0h
R/W-0h
R/W-0h

20

19

18
17
16
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS2
GS2
GS2
R/W-0h
R/W-0h
R/W-0h

12

11

10
9
8
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS1
GS1
GS1
R/W-0h
R/W-0h
R/W-0h

4

3

2
1
0
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS0
GS0
GS0
R/W-0h
R/W-0h
R/W-0h

R-0h
23

22

21
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7

6

5
RESERVED
R-0h

Table 2-268. GSxACCPROT0 Register Field Descriptions
Bit
31-27
26

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

DMAWRPROT_GS3

R/W

0h

DMA WR Protection For GS3 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

25

CPUWRPROT_GS3

R/W

0h

CPU WR Protection For GS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

24

FETCHPROT_GS3

R/W

0h

Fetch Protection For GS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

23-19
18

RESERVED

R

0h

Reserved

DMAWRPROT_GS2

R/W

0h

DMA WR Protection For GS2 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

17

CPUWRPROT_GS2

R/W

0h

CPU WR Protection For GS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

479

Registers

www.ti.com

Table 2-268. GSxACCPROT0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

16

FETCHPROT_GS2

R/W

0h

Fetch Protection For GS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

15-11
10

RESERVED

R

0h

Reserved

DMAWRPROT_GS1

R/W

0h

DMA WR Protection For GS1 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

9

CPUWRPROT_GS1

R/W

0h

CPU WR Protection For GS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

8

FETCHPROT_GS1

R/W

0h

Fetch Protection For GS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

7-3
2

RESERVED

R

0h

Reserved

DMAWRPROT_GS0

R/W

0h

DMA WR Protection For GS0 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

1

CPUWRPROT_GS0

R/W

0h

CPU WR Protection For GS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

0

FETCHPROT_GS0

R/W

0h

Fetch Protection For GS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

480

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.20 GSxACCPROT1 Register (Offset = 4Ah) [reset = 0h]
GSxACCPROT1 is shown in Figure 2-243 and described in Table 2-269.
Return to Summary Table.
Global Shared RAM Config Register 1
Figure 2-243. GSxACCPROT1 Register
31

30

29
RESERVED

28

27

26
25
24
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS7
GS7
GS7
R/W-0h
R/W-0h
R/W-0h

20

19

18
17
16
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS6
GS6
GS6
R/W-0h
R/W-0h
R/W-0h

12

11

10
9
8
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS5
GS5
GS5
R/W-0h
R/W-0h
R/W-0h

4

3

2
1
0
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS4
GS4
GS4
R/W-0h
R/W-0h
R/W-0h

R-0h
23

22

21
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7

6

5
RESERVED
R-0h

Table 2-269. GSxACCPROT1 Register Field Descriptions
Bit
31-27
26

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

DMAWRPROT_GS7

R/W

0h

DMA WR Protection For GS7 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

25

CPUWRPROT_GS7

R/W

0h

CPU WR Protection For GS7 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

24

FETCHPROT_GS7

R/W

0h

Fetch Protection For GS7 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

23-19
18

RESERVED

R

0h

Reserved

DMAWRPROT_GS6

R/W

0h

DMA WR Protection For GS6 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

17

CPUWRPROT_GS6

R/W

0h

CPU WR Protection For GS6 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

481

Registers

www.ti.com

Table 2-269. GSxACCPROT1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

16

FETCHPROT_GS6

R/W

0h

Fetch Protection For GS6 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

15-11
10

RESERVED

R

0h

Reserved

DMAWRPROT_GS5

R/W

0h

DMA WR Protection For GS5 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

9

CPUWRPROT_GS5

R/W

0h

CPU WR Protection For GS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

8

FETCHPROT_GS5

R/W

0h

Fetch Protection For GS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

7-3
2

RESERVED

R

0h

Reserved

DMAWRPROT_GS4

R/W

0h

DMA WR Protection For GS4 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

1

CPUWRPROT_GS4

R/W

0h

CPU WR Protection For GS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

0

FETCHPROT_GS4

R/W

0h

Fetch Protection For GS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

482

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.21 GSxACCPROT2 Register (Offset = 4Ch) [reset = 0h]
GSxACCPROT2 is shown in Figure 2-244 and described in Table 2-270.
Return to Summary Table.
Global Shared RAM Config Register 2
Figure 2-244. GSxACCPROT2 Register
31

30

29
RESERVED

28

27

26
25
24
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS11
GS11
GS11
R/W-0h
R/W-0h
R/W-0h

20

19

18
17
16
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS10
GS10
GS10
R/W-0h
R/W-0h
R/W-0h

12

11

10
9
8
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS9
GS9
GS9
R/W-0h
R/W-0h
R/W-0h

4

3

2
1
0
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS8
GS8
GS8
R/W-0h
R/W-0h
R/W-0h

R-0h
23

22

21
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7

6

5
RESERVED
R-0h

Table 2-270. GSxACCPROT2 Register Field Descriptions
Bit
31-27
26

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

DMAWRPROT_GS11

R/W

0h

DMA WR Protection For GS11 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

25

CPUWRPROT_GS11

R/W

0h

CPU WR Protection For GS11 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

24

FETCHPROT_GS11

R/W

0h

Fetch Protection For GS11 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

23-19
18

RESERVED

R

0h

Reserved

DMAWRPROT_GS10

R/W

0h

DMA WR Protection For GS10 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

17

CPUWRPROT_GS10

R/W

0h

CPU WR Protection For GS10 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

483

Registers

www.ti.com

Table 2-270. GSxACCPROT2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

16

FETCHPROT_GS10

R/W

0h

Fetch Protection For GS10 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

15-11
10

RESERVED

R

0h

Reserved

DMAWRPROT_GS9

R/W

0h

DMA WR Protection For GS9 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

9

CPUWRPROT_GS9

R/W

0h

CPU WR Protection For GS9 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

8

FETCHPROT_GS9

R/W

0h

Fetch Protection For GS9 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

7-3
2

RESERVED

R

0h

Reserved

DMAWRPROT_GS8

R/W

0h

DMA WR Protection For GS8 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

1

CPUWRPROT_GS8

R/W

0h

CPU WR Protection For GS8 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

0

FETCHPROT_GS8

R/W

0h

Fetch Protection For GS8 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

484

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.22 GSxACCPROT3 Register (Offset = 4Eh) [reset = 0h]
GSxACCPROT3 is shown in Figure 2-245 and described in Table 2-271.
Return to Summary Table.
Global Shared RAM Config Register 3
Figure 2-245. GSxACCPROT3 Register
31

30

29
RESERVED

28

27

26
25
24
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS15
GS15
GS15
R/W-0h
R/W-0h
R/W-0h

20

19

18
17
16
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS14
GS14
GS14
R/W-0h
R/W-0h
R/W-0h

12

11

10
9
8
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS13
GS13
GS13
R/W-0h
R/W-0h
R/W-0h

4

3

2
1
0
DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS12
GS12
GS12
R/W-0h
R/W-0h
R/W-0h

R-0h
23

22

21
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7

6

5
RESERVED
R-0h

Table 2-271. GSxACCPROT3 Register Field Descriptions
Bit
31-27
26

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

DMAWRPROT_GS15

R/W

0h

DMA WR Protection For GS15 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

25

CPUWRPROT_GS15

R/W

0h

CPU WR Protection For GS15 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

24

FETCHPROT_GS15

R/W

0h

Fetch Protection For GS15 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

23-19
18

RESERVED

R

0h

Reserved

DMAWRPROT_GS14

R/W

0h

DMA WR Protection For GS14 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

17

CPUWRPROT_GS14

R/W

0h

CPU WR Protection For GS14 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

485

Registers

www.ti.com

Table 2-271. GSxACCPROT3 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

16

FETCHPROT_GS14

R/W

0h

Fetch Protection For GS14 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

15-11
10

RESERVED

R

0h

Reserved

DMAWRPROT_GS13

R/W

0h

DMA WR Protection For GS13 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

9

CPUWRPROT_GS13

R/W

0h

CPU WR Protection For GS13 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

8

FETCHPROT_GS13

R/W

0h

Fetch Protection For GS13 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

7-3
2

RESERVED

R

0h

Reserved

DMAWRPROT_GS12

R/W

0h

DMA WR Protection For GS12 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

1

CPUWRPROT_GS12

R/W

0h

CPU WR Protection For GS12 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

0

FETCHPROT_GS12

R/W

0h

Fetch Protection For GS12 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

486

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.23 GSxTEST Register (Offset = 50h) [reset = 0h]
GSxTEST is shown in Figure 2-246 and described in Table 2-272.
Return to Summary Table.
Global Shared RAM TEST Register
Figure 2-246. GSxTEST Register
31

30

29

TEST_GS15
R/W-0h
23

22

21

TEST_GS11
R/W-0h
15

27

14

20

13

19

6

12

5

25

18

11

17

4

10

3

16
TEST_GS8
R/W-0h

9

TEST_GS5
R/W-0h

TEST_GS2
R/W-0h

24
TEST_GS12
R/W-0h

TEST_GS9
R/W-0h

TEST_GS6
R/W-0h

TEST_GS3
R/W-0h

26
TEST_GS13
R/W-0h

TEST_GS10
R/W-0h

TEST_GS7
R/W-0h
7

28
TEST_GS14
R/W-0h

8
TEST_GS4
R/W-0h

2

1

TEST_GS1
R/W-0h

0
TEST_GS0
R/W-0h

Table 2-272. GSxTEST Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

TEST_GS15

R/W

0h

Selects the defferent modes for GS15 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

29-28

TEST_GS14

R/W

0h

Selects the defferent modes for GS14 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

27-26

TEST_GS13

R/W

0h

Selects the defferent modes for GS13 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

25-24

TEST_GS12

R/W

0h

Selects the defferent modes for GS12 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

487

Registers

www.ti.com

Table 2-272. GSxTEST Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

TEST_GS11

R/W

0h

Selects the defferent modes for GS11 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

21-20

TEST_GS10

R/W

0h

Selects the defferent modes for GS10 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

19-18

TEST_GS9

R/W

0h

Selects the defferent modes for GS9 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

17-16

TEST_GS8

R/W

0h

Selects the defferent modes for GS8 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

15-14

TEST_GS7

R/W

0h

Selects the defferent modes for GS7 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

13-12

TEST_GS6

R/W

0h

Selects the defferent modes for GS6 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

11-10

TEST_GS5

R/W

0h

Selects the defferent modes for GS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

9-8

TEST_GS4

R/W

0h

Selects the defferent modes for GS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

488

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-272. GSxTEST Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

TEST_GS3

R/W

0h

Selects the defferent modes for GS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

5-4

TEST_GS2

R/W

0h

Selects the defferent modes for GS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

3-2

TEST_GS1

R/W

0h

Selects the defferent modes for GS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

1-0

TEST_GS0

R/W

0h

Selects the defferent modes for GS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

489

Registers

www.ti.com

2.15.18.24 GSxINIT Register (Offset = 52h) [reset = 0h]
GSxINIT is shown in Figure 2-247 and described in Table 2-273.
Return to Summary Table.
Global Shared RAM Init Register
Figure 2-247. GSxINIT Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
INIT_GS15
R=0/W=1-0h

14
INIT_GS14
R=0/W=1-0h

13
INIT_GS13
R=0/W=1-0h

12
INIT_GS12
R=0/W=1-0h

11
INIT_GS11
R=0/W=1-0h

10
INIT_GS10
R=0/W=1-0h

9
INIT_GS9
R=0/W=1-0h

8
INIT_GS8
R=0/W=1-0h

7
INIT_GS7
R=0/W=1-0h

6
INIT_GS6
R=0/W=1-0h

5
INIT_GS5
R=0/W=1-0h

4
INIT_GS4
R=0/W=1-0h

3
INIT_GS3
R=0/W=1-0h

2
INIT_GS2
R=0/W=1-0h

1
INIT_GS1
R=0/W=1-0h

0
INIT_GS0
R=0/W=1-0h

Table 2-273. GSxINIT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15

INIT_GS15

R=0/W=1

0h

RAM Initialization control for GS15 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

14

INIT_GS14

R=0/W=1

0h

RAM Initialization control for GS14 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

13

INIT_GS13

R=0/W=1

0h

RAM Initialization control for GS13 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

12

INIT_GS12

R=0/W=1

0h

RAM Initialization control for GS12 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

11

INIT_GS11

R=0/W=1

0h

RAM Initialization control for GS11 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

10

INIT_GS10

R=0/W=1

0h

RAM Initialization control for GS10 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

490

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-273. GSxINIT Register Field Descriptions (continued)
Bit
9

Field

Type

Reset

Description

INIT_GS9

R=0/W=1

0h

RAM Initialization control for GS9 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

8

INIT_GS8

R=0/W=1

0h

RAM Initialization control for GS8 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

7

INIT_GS7

R=0/W=1

0h

RAM Initialization control for GS7 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

6

INIT_GS6

R=0/W=1

0h

RAM Initialization control for GS6 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

5

INIT_GS5

R=0/W=1

0h

RAM Initialization control for GS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

4

INIT_GS4

R=0/W=1

0h

RAM Initialization control for GS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

3

INIT_GS3

R=0/W=1

0h

RAM Initialization control for GS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

2

INIT_GS2

R=0/W=1

0h

RAM Initialization control for GS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

1

INIT_GS1

R=0/W=1

0h

RAM Initialization control for GS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

0

INIT_GS0

R=0/W=1

0h

RAM Initialization control for GS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

491

Registers

www.ti.com

2.15.18.25 GSxINITDONE Register (Offset = 54h) [reset = 0h]
GSxINITDONE is shown in Figure 2-248 and described in Table 2-274.
Return to Summary Table.
Global Shared RAM InitDone Status Register
Figure 2-248. GSxINITDONE Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
INITDONE_GS
15
R-0h

14
INITDONE_GS
14
R-0h

13
INITDONE_GS
13
R-0h

12
INITDONE_GS
12
R-0h

11
INITDONE_GS
11
R-0h

10
INITDONE_GS
10
R-0h

9
INITDONE_GS
9
R-0h

8
INITDONE_GS
8
R-0h

7
INITDONE_GS
7
R-0h

6
INITDONE_GS
6
R-0h

5
INITDONE_GS
5
R-0h

4
INITDONE_GS
4
R-0h

3
INITDONE_GS
3
R-0h

2
INITDONE_GS
2
R-0h

1
INITDONE_GS
1
R-0h

0
INITDONE_GS
0
R-0h

Table 2-274. GSxINITDONE Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

INITDONE_GS15

R

0h

RAM Initialization status for GS15 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

14

INITDONE_GS14

R

0h

RAM Initialization status for GS14 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

13

INITDONE_GS13

R

0h

RAM Initialization status for GS13 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

12

INITDONE_GS12

R

0h

RAM Initialization status for GS12 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

11

INITDONE_GS11

R

0h

RAM Initialization status for GS11 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

10

INITDONE_GS10

R

0h

RAM Initialization status for GS10 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

492

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-274. GSxINITDONE Register Field Descriptions (continued)
Bit
9

Field

Type

Reset

Description

INITDONE_GS9

R

0h

RAM Initialization status for GS9 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

8

INITDONE_GS8

R

0h

RAM Initialization status for GS8 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

7

INITDONE_GS7

R

0h

RAM Initialization status for GS7 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

6

INITDONE_GS6

R

0h

RAM Initialization status for GS6 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

5

INITDONE_GS5

R

0h

RAM Initialization status for GS5 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

4

INITDONE_GS4

R

0h

RAM Initialization status for GS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

3

INITDONE_GS3

R

0h

RAM Initialization status for GS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

2

INITDONE_GS2

R

0h

RAM Initialization status for GS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

1

INITDONE_GS1

R

0h

RAM Initialization status for GS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

0

INITDONE_GS0

R

0h

RAM Initialization status for GS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

493

Registers

www.ti.com

2.15.18.26 MSGxTEST Register (Offset = 70h) [reset = 0h]
MSGxTEST is shown in Figure 2-249 and described in Table 2-275.
Return to Summary Table.
Message RAM TEST Register
Figure 2-249. MSGxTEST Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED
R-0h

5
4
TEST_CLA1TOCPU
R/W-0h

8
RESERVED
R-0h

3
2
TEST_CPUTOCLA1
R/W-0h

1
0
TEST_CPUTOCPU
R/W-0h

Table 2-275. MSGxTEST Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-10

RESERVED

R

0h

Reserved

9-8

RESERVED

R

0h

Reserved

7-6

RESERVED

R

0h

Reserved

5-4

TEST_CLA1TOCPU

R/W

0h

Selects the defferent modes for CLA1TOCPU MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

3-2

TEST_CPUTOCLA1

R/W

0h

Selects the defferent modes for CPUTOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

1-0

TEST_CPUTOCPU

R/W

0h

Selects the defferent modes for CPUTOCPU MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

494

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.18.27 MSGxINIT Register (Offset = 72h) [reset = 0h]
MSGxINIT is shown in Figure 2-250 and described in Table 2-276.
Return to Summary Table.
Message RAM Init Register
Figure 2-250. MSGxINIT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

4
RESERVED

3
RESERVED

R-0h

R-0h

2
INIT_CLA1TOC
PU
R=0/W=1-0h

1
INIT_CPUTOC
LA1
R=0/W=1-0h

0
INIT_CPUTOC
PU
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED

5

R-0h

Table 2-276. MSGxINIT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

INIT_CLA1TOCPU

R=0/W=1

0h

RAM Initialization control for CLA1TOCPU MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

1

INIT_CPUTOCLA1

R=0/W=1

0h

RAM Initialization control for CPUTOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

0

INIT_CPUTOCPU

R=0/W=1

0h

RAM Initialization control for CPUTOCPU MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

495

Registers

www.ti.com

2.15.18.28 MSGxINITDONE Register (Offset = 74h) [reset = 0h]
MSGxINITDONE is shown in Figure 2-251 and described in Table 2-277.
Return to Summary Table.
Message RAM InitDone Status Register
Figure 2-251. MSGxINITDONE Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

4
RESERVED

3
RESERVED

R-0h

R-0h

2
INITDONE_CL
A1TOCPU
R-0h

1
INITDONE_CP
UTOCLA1
R-0h

0
INITDONE_CP
UTOCPU
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED

5

R-0h

Table 2-277. MSGxINITDONE Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

INITDONE_CLA1TOCPU

R

0h

RAM Initialization status for CLA1TOCPU MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

1

INITDONE_CPUTOCLA1

R

0h

RAM Initialization status for CPUTOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

0

INITDONE_CPUTOCPU

R

0h

RAM Initialization status for CPUTOCPU MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

496

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19 ACCESS_PROTECTION_REGS Registers
Table 2-278 lists the memory-mapped registers for the ACCESS_PROTECTION_REGS. All register offset
addresses not listed in Table 2-278 should be considered as reserved locations and the register contents
should not be modified.
Table 2-278. ACCESS_PROTECTION_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

NMAVFLG

Non-Master Access Violation Flag Register

2h

NMAVSET

Non-Master Access Violation Flag Set Register

EALLOW

Go

4h

NMAVCLR

Non-Master Access Violation Flag Clear Register EALLOW

Go

6h

NMAVINTEN

Non-Master Access Violation Interrupt Enable
Register

Go

8h

NMCPURDAVADDR

Non-Master CPU Read Access Violation
Address

Go

Go

EALLOW

Ah

NMCPUWRAVADDR

Non-Master CPU Write Access Violation Address

Go

Ch

NMCPUFAVADDR

Non-Master CPU Fetch Access Violation
Address

Go

Eh

NMDMAWRAVADDR

Non-Master DMA Write Access Violation
Address

Go

10h

NMCLA1RDAVADDR

Non-Master CLA1 Read Access Violation
Address

Go

12h

NMCLA1WRAVADDR

Non-Master CLA1 Write Access Violation
Address

Go

14h

NMCLA1FAVADDR

Non-Master CLA1 Fetch Access Violation
Address

Go

20h

MAVFLG

Master Access Violation Flag Register

22h

MAVSET

Master Access Violation Flag Set Register

EALLOW

Go

24h

MAVCLR

Master Access Violation Flag Clear Register

EALLOW

Go

26h

MAVINTEN

Master Access Violation Interrupt Enable
Register

EALLOW

Go

Go

28h

MCPUFAVADDR

Master CPU Fetch Access Violation Address

Go

2Ah

MCPUWRAVADDR

Master CPU Write Access Violation Address

Go

2Ch

MDMAWRAVADDR

Master DMA Write Access Violation Address

Go

Complex bit access types are encoded to fit into small table cells. Table 2-279 shows the codes that are
used for access types in this section.
Table 2-279. ACCESS_PROTECTION_REGS Access
Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

497

Registers

www.ti.com

Table 2-279. ACCESS_PROTECTION_REGS Access
Type Codes (continued)
Access Type

498

System Control

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.1 NMAVFLG Register (Offset = 0h) [reset = 0h]
NMAVFLG is shown in Figure 2-252 and described in Table 2-280.
Return to Summary Table.
Non-Master Access Violation Flag Register
Figure 2-252. NMAVFLG Register
31

30

29

28

27

26

25

24

19

18

17

16

12

11

10

9
RESERVED
R-0h

8
RESERVED
R-0h

4
CLA1READ
R-0h

3
DMAWRITE
R-0h

2
CPUFETCH
R-0h

1
CPUWRITE
R-0h

0
CPUREAD
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7
RESERVED
R-0h

6
CLA1FETCH
R-0h

5
CLA1WRITE
R-0h

Table 2-280. NMAVFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

CLA1FETCH

R

0h

Non Master CLA1 Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

5

CLA1WRITE

R

0h

Non Master CLA1 Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

4

CLA1READ

R

0h

Non Master CLA1 Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

3

DMAWRITE

R

0h

Non Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

2

CPUFETCH

R

0h

Non Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

499

Registers

www.ti.com

Table 2-280. NMAVFLG Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

CPUWRITE

R

0h

Non Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

0

CPUREAD

R

0h

Non Master CPU Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

500

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.2 NMAVSET Register (Offset = 2h) [reset = 0h]
NMAVSET is shown in Figure 2-253 and described in Table 2-281.
Return to Summary Table.
Non-Master Access Violation Flag Set Register
Figure 2-253. NMAVSET Register
31

30

29

28

27

26

25

24

19

18

17

16

12

11

10

9
RESERVED
R-0h

8
RESERVED
R-0h

4
CLA1READ
R=0/W=1-0h

3
DMAWRITE
R=0/W=1-0h

2
CPUFETCH
R=0/W=1-0h

1
CPUWRITE
R=0/W=1-0h

0
CPUREAD
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7
RESERVED
R-0h

6
CLA1FETCH
R=0/W=1-0h

5
CLA1WRITE
R=0/W=1-0h

Table 2-281. NMAVSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

CLA1FETCH

R=0/W=1

0h

0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be
set and interrupt will be generated if enabled..
Reset type: SYSRSn

5

CLA1WRITE

R=0/W=1

0h

0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be
set and interrupt will be generated if enabled..
Reset type: SYSRSn

4

CLA1READ

R=0/W=1

0h

0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be
set and interrupt will be generated if enabled..
Reset type: SYSRSn

3

DMAWRITE

R=0/W=1

0h

0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

2

CPUFETCH

R=0/W=1

0h

0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

1

CPUWRITE

R=0/W=1

0h

0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

501

Registers

www.ti.com

Table 2-281. NMAVSET Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

CPUREAD

R=0/W=1

0h

0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

502

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.3 NMAVCLR Register (Offset = 4h) [reset = 0h]
NMAVCLR is shown in Figure 2-254 and described in Table 2-282.
Return to Summary Table.
Non-Master Access Violation Flag Clear Register
Figure 2-254. NMAVCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

12

11

10

9
RESERVED
R-0h

8
RESERVED
R-0h

4
CLA1READ
R=0/W=1-0h

3
DMAWRITE
R=0/W=1-0h

2
CPUFETCH
R=0/W=1-0h

1
CPUWRITE
R=0/W=1-0h

0
CPUREAD
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7
RESERVED
R-0h

6
CLA1FETCH
R=0/W=1-0h

5
CLA1WRITE
R=0/W=1-0h

Table 2-282. NMAVCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

CLA1FETCH

R=0/W=1

0h

0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

5

CLA1WRITE

R=0/W=1

0h

0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

4

CLA1READ

R=0/W=1

0h

0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

3

DMAWRITE

R=0/W=1

0h

0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

2

CPUFETCH

R=0/W=1

0h

0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

1

CPUWRITE

R=0/W=1

0h

0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

503

Registers

www.ti.com

Table 2-282. NMAVCLR Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

CPUREAD

R=0/W=1

0h

0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

504

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.4 NMAVINTEN Register (Offset = 6h) [reset = 0h]
NMAVINTEN is shown in Figure 2-255 and described in Table 2-283.
Return to Summary Table.
Non-Master Access Violation Interrupt Enable Register
Figure 2-255. NMAVINTEN Register
31

30

29

28

27

26

25

24

19

18

17

16

12

11

10

9
RESERVED
R-0h

8
RESERVED
R-0h

4
CLA1READ
R/W-0h

3
DMAWRITE
R/W-0h

2
CPUFETCH
R/W-0h

1
CPUWRITE
R/W-0h

0
CPUREAD
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7
RESERVED
R-0h

6
CLA1FETCH
R/W-0h

5
CLA1WRITE
R/W-0h

Table 2-283. NMAVINTEN Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

CLA1FETCH

R/W

0h

0: CLA1 Non Master Fetch Access Violation Interrupt is disabled.
1: CLA1 Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

5

CLA1WRITE

R/W

0h

0: CLA1 Non Master Write Access Violation Interrupt is disabled.
1: CLA1 Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn

4

CLA1READ

R/W

0h

0: CLA1 Non Master Read Access Violation Interrupt is disabled.
1: CLA1 Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn

3

DMAWRITE

R/W

0h

0: DMA Non Master Write Access Violation Interrupt is disabled.
1: DMA Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn

2

CPUFETCH

R/W

0h

0: CPU Non Master Fetch Access Violation Interrupt is disabled.
1: CPU Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

1

CPUWRITE

R/W

0h

0: CPU Non Master Write Access Violation Interrupt is disabled.
1: CPU Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn

0

CPUREAD

R/W

0h

0: CPU Non Master Read Access Violation Interrupt is disabled.
1: CPU Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

505

Registers

www.ti.com

2.15.19.5 NMCPURDAVADDR Register (Offset = 8h) [reset = 0h]
NMCPURDAVADDR is shown in Figure 2-256 and described in Table 2-284.
Return to Summary Table.
Non-Master CPU Read Access Violation Address
Figure 2-256. NMCPURDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NMCPURDAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-284. NMCPURDAVADDR Register Field Descriptions
Bit
31-0

506

Field

Type

Reset

Description

NMCPURDAVADDR

R

0h

This register captures the address location for which non master
CPU read access vaiolation occurred.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.6 NMCPUWRAVADDR Register (Offset = Ah) [reset = 0h]
NMCPUWRAVADDR is shown in Figure 2-257 and described in Table 2-285.
Return to Summary Table.
Non-Master CPU Write Access Violation Address
Figure 2-257. NMCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NMCPUWRAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-285. NMCPUWRAVADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

NMCPUWRAVADDR

R

0h

This register captures the address location for which non master
CPU write access vaiolation occurred.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

507

Registers

www.ti.com

2.15.19.7 NMCPUFAVADDR Register (Offset = Ch) [reset = 0h]
NMCPUFAVADDR is shown in Figure 2-258 and described in Table 2-286.
Return to Summary Table.
Non-Master CPU Fetch Access Violation Address
Figure 2-258. NMCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NMCPUFAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-286. NMCPUFAVADDR Register Field Descriptions
Bit
31-0

508

Field

Type

Reset

Description

NMCPUFAVADDR

R

0h

This register captures the address location for which non master
CPU fetch access vaiolation occurred.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.8 NMDMAWRAVADDR Register (Offset = Eh) [reset = 0h]
NMDMAWRAVADDR is shown in Figure 2-259 and described in Table 2-287.
Return to Summary Table.
Non-Master DMA Write Access Violation Address
Figure 2-259. NMDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NMDMAWRAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-287. NMDMAWRAVADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

NMDMAWRAVADDR

R

0h

This register captures the address location for which non master
DMA write access vaiolation occurred.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

509

Registers

www.ti.com

2.15.19.9 NMCLA1RDAVADDR Register (Offset = 10h) [reset = 0h]
NMCLA1RDAVADDR is shown in Figure 2-260 and described in Table 2-288.
Return to Summary Table.
Non-Master CLA1 Read Access Violation Address
Figure 2-260. NMCLA1RDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NMCLA1RDAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-288. NMCLA1RDAVADDR Register Field Descriptions
Bit
31-0

510

Field

Type

Reset

Description

NMCLA1RDAVADDR

R

0h

This register captures the address location for which non master
CLA1 read access vaiolation occurred.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.10 NMCLA1WRAVADDR Register (Offset = 12h) [reset = 0h]
NMCLA1WRAVADDR is shown in Figure 2-261 and described in Table 2-289.
Return to Summary Table.
Non-Master CLA1 Write Access Violation Address
Figure 2-261. NMCLA1WRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NMCLA1WRAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-289. NMCLA1WRAVADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

NMCLA1WRAVADDR

R

0h

This register captures the address location for which non master
CLA1 write access vaiolation occurred.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

511

Registers

www.ti.com

2.15.19.11 NMCLA1FAVADDR Register (Offset = 14h) [reset = 0h]
NMCLA1FAVADDR is shown in Figure 2-262 and described in Table 2-290.
Return to Summary Table.
Non-Master CLA1 Fetch Access Violation Address
Figure 2-262. NMCLA1FAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NMCLA1FAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-290. NMCLA1FAVADDR Register Field Descriptions
Bit
31-0

512

Field

Type

Reset

Description

NMCLA1FAVADDR

R

0h

This register captures the address location for which non master
CLA1 fetch access vaiolation occurred.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.12 MAVFLG Register (Offset = 20h) [reset = 0h]
MAVFLG is shown in Figure 2-263 and described in Table 2-291.
Return to Summary Table.
Master Access Violation Flag Register
Figure 2-263. MAVFLG Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2
DMAWRITE
R-0h

1
CPUWRITE
R-0h

0
CPUFETCH
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5
RESERVED
R-0h

4

Table 2-291. MAVFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-3

RESERVED

R

0h

Reserved

2

DMAWRITE

R

0h

Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

1

CPUWRITE

R

0h

Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

0

CPUFETCH

R

0h

Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

513

Registers

www.ti.com

2.15.19.13 MAVSET Register (Offset = 22h) [reset = 0h]
MAVSET is shown in Figure 2-264 and described in Table 2-292.
Return to Summary Table.
Master Access Violation Flag Set Register
Figure 2-264. MAVSET Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2
DMAWRITE
R=0/W=1-0h

1
CPUWRITE
R=0/W=1-0h

0
CPUFETCH
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5
RESERVED
R-0h

4

Table 2-292. MAVSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-3

RESERVED

R

0h

Reserved

2

DMAWRITE

R=0/W=1

0h

0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

1

CPUWRITE

R=0/W=1

0h

0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

0

CPUFETCH

R=0/W=1

0h

0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn

514

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.14 MAVCLR Register (Offset = 24h) [reset = 0h]
MAVCLR is shown in Figure 2-265 and described in Table 2-293.
Return to Summary Table.
Master Access Violation Flag Clear Register
Figure 2-265. MAVCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2
DMAWRITE
R=0/W=1-0h

1
CPUWRITE
R=0/W=1-0h

0
CPUFETCH
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5
RESERVED
R-0h

4

Table 2-293. MAVCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-3

RESERVED

R

0h

Reserved

2

DMAWRITE

R=0/W=1

0h

0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn

1

CPUWRITE

R=0/W=1

0h

0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be
cleared .
Reset type: SYSRSn

0

CPUFETCH

R=0/W=1

0h

0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

515

Registers

www.ti.com

2.15.19.15 MAVINTEN Register (Offset = 26h) [reset = 0h]
MAVINTEN is shown in Figure 2-266 and described in Table 2-294.
Return to Summary Table.
Master Access Violation Interrupt Enable Register
Figure 2-266. MAVINTEN Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2
DMAWRITE
R/W-0h

1
CPUWRITE
R/W-0h

0
CPUFETCH
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5
RESERVED
R-0h

4

Table 2-294. MAVINTEN Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-3

RESERVED

R

0h

Reserved

2

DMAWRITE

R/W

0h

0: DMA Write Access Violation Interrupt is disabled.
1: DMA Write Access Violation Interrupt is enabled.
Reset type: SYSRSn

1

CPUWRITE

R/W

0h

0: CPU Write Access Violation Interrupt is disabled.
1: CPU Write Access Violation Interrupt is enabled.
Reset type: SYSRSn

0

CPUFETCH

R/W

0h

0: CPU Fetch Access Violation Interrupt is disabled.
1: CPU Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

516

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.16 MCPUFAVADDR Register (Offset = 28h) [reset = 0h]
MCPUFAVADDR is shown in Figure 2-267 and described in Table 2-295.
Return to Summary Table.
Master CPU Fetch Access Violation Address
Figure 2-267. MCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MCPUFAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-295. MCPUFAVADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

MCPUFAVADDR

R

0h

This register captures the address location for which master CPU
fetch access vaiolation occurred.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

517

Registers

www.ti.com

2.15.19.17 MCPUWRAVADDR Register (Offset = 2Ah) [reset = 0h]
MCPUWRAVADDR is shown in Figure 2-268 and described in Table 2-296.
Return to Summary Table.
Master CPU Write Access Violation Address
Figure 2-268. MCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MCPUWRAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-296. MCPUWRAVADDR Register Field Descriptions
Bit
31-0

518

Field

Type

Reset

Description

MCPUWRAVADDR

R

0h

This register captures the address location for which master CPU
write access vaiolation occurred.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.19.18 MDMAWRAVADDR Register (Offset = 2Ch) [reset = 0h]
MDMAWRAVADDR is shown in Figure 2-269 and described in Table 2-297.
Return to Summary Table.
Master DMA Write Access Violation Address
Figure 2-269. MDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MDMAWRAVADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-297. MDMAWRAVADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

MDMAWRAVADDR

R

0h

This register captures the address location for which master DMA
write access vaiolation occurred.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

519

Registers

www.ti.com

2.15.20 MEMORY_ERROR_REGS Registers
Table 2-298 lists the memory-mapped registers for the MEMORY_ERROR_REGS. All register offset
addresses not listed in Table 2-298 should be considered as reserved locations and the register contents
should not be modified.
Table 2-298. MEMORY_ERROR_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

UCERRFLG

Uncorrectable Error Flag Register

2h

UCERRSET

Uncorrectable Error Flag Set Register

EALLOW

Go

4h

UCERRCLR

Uncorrectable Error Flag Clear Register

EALLOW

Go

6h

UCCPUREADDR

Uncorrectable CPU Read Error Address

Go

8h

UCDMAREADDR

Uncorrectable DMA Read Error Address

Go

Ah

UCCLA1READDR

Uncorrectable CLA1 Read Error Address

Go

20h

CERRFLG

Correctable Error Flag Register

Go

22h

CERRSET

Correctable Error Flag Set Register

EALLOW

Go

24h

CERRCLR

Correctable Error Flag Clear Register

EALLOW

Go

26h

CCPUREADDR

Correctable CPU Read Error Address

2Eh

CERRCNT

Correctable Error Count Register

30h

CERRTHRES

Correctable Error Threshold Value Register

32h

CEINTFLG

Correctable Error Interrupt Flag Status Register

34h

CEINTCLR

Correctable Error Interrupt Flag Clear Register

EALLOW

Go

36h

CEINTSET

Correctable Error Interrupt Flag Set Register

EALLOW

Go

38h

CEINTEN

Correctable Error Interrupt Enable Register

EALLOW

Go

Go

Go
Go
EALLOW

Go
Go

Complex bit access types are encoded to fit into small table cells. Table 2-299 shows the codes that are
used for access types in this section.
Table 2-299. MEMORY_ERROR_REGS Access Type
Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

520

System Control

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.20.1 UCERRFLG Register (Offset = 0h) [reset = 0h]
UCERRFLG is shown in Figure 2-270 and described in Table 2-300.
Return to Summary Table.
Uncorrectable Error Flag Register
Figure 2-270. UCERRFLG Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
CLA1RDERR
R-0h

1
DMARDERR
R-0h

0
CPURDERR
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

Table 2-300. UCERRFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

CLA1RDERR

R

0h

CLA1 Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CLA1 read.
Reset type: SYSRSn

1

DMARDERR

R

0h

DMA Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during DMA read.
Reset type: SYSRSn

0

CPURDERR

R

0h

CPU Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CPU read.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

521

Registers

www.ti.com

2.15.20.2 UCERRSET Register (Offset = 2h) [reset = 0h]
UCERRSET is shown in Figure 2-271 and described in Table 2-301.
Return to Summary Table.
Uncorrectable Error Flag Set Register
Figure 2-271. UCERRSET Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
CLA1RDERR
R=0/W=1-0h

1
DMARDERR
R=0/W=1-0h

0
CPURDERR
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

Table 2-301. UCERRSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

CLA1RDERR

R=0/W=1

0h

0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

1

DMARDERR

R=0/W=1

0h

0: No action.
1: DMA Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

0

CPURDERR

R=0/W=1

0h

0: No action.
1: CPU Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

522

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.20.3 UCERRCLR Register (Offset = 4h) [reset = 0h]
UCERRCLR is shown in Figure 2-272 and described in Table 2-302.
Return to Summary Table.
Uncorrectable Error Flag Clear Register
Figure 2-272. UCERRCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
CLA1RDERR
R=0/W=1-0h

1
DMARDERR
R=0/W=1-0h

0
CPURDERR
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

Table 2-302. UCERRCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

CLA1RDERR

R=0/W=1

0h

0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn

1

DMARDERR

R=0/W=1

0h

0: No action.
1: DMA Read Error Flag in UCERRFLG register will be cleared .
Reset type: SYSRSn

0

CPURDERR

R=0/W=1

0h

0: No action.
1: CPU Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

523

Registers

www.ti.com

2.15.20.4 UCCPUREADDR Register (Offset = 6h) [reset = 0h]
UCCPUREADDR is shown in Figure 2-273 and described in Table 2-303.
Return to Summary Table.
Uncorrectable CPU Read Error Address
Figure 2-273. UCCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UCCPUREADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-303. UCCPUREADDR Register Field Descriptions
Bit
31-0

524

Field

Type

Reset

Description

UCCPUREADDR

R

0h

This register captures the address location for which CPU read/fetch
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.20.5 UCDMAREADDR Register (Offset = 8h) [reset = 0h]
UCDMAREADDR is shown in Figure 2-274 and described in Table 2-304.
Return to Summary Table.
Uncorrectable DMA Read Error Address
Figure 2-274. UCDMAREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UCDMAREADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-304. UCDMAREADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

UCDMAREADDR

R

0h

This register captures the address location for which DMA read
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

525

Registers

www.ti.com

2.15.20.6 UCCLA1READDR Register (Offset = Ah) [reset = 0h]
UCCLA1READDR is shown in Figure 2-275 and described in Table 2-305.
Return to Summary Table.
Uncorrectable CLA1 Read Error Address
Figure 2-275. UCCLA1READDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UCCLA1READDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-305. UCCLA1READDR Register Field Descriptions
Bit
31-0

526

Field

Type

Reset

Description

UCCLA1READDR

R

0h

This register captures the address location for which CLA1
read/fetch access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.20.7 CERRFLG Register (Offset = 20h) [reset = 0h]
CERRFLG is shown in Figure 2-276 and described in Table 2-306.
Return to Summary Table.
Correctable Error Flag Register
Figure 2-276. CERRFLG Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
CLA1RDERR
R-0h

1
DMARDERR
R-0h

0
CPURDERR
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

Table 2-306. CERRFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

CLA1RDERR

R

0h

CLA1 Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CLA1 read.
Reset type: SYSRSn

1

DMARDERR

R

0h

DMA Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during DMA read.
Reset type: SYSRSn

0

CPURDERR

R

0h

CPU Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CPU read.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

527

Registers

www.ti.com

2.15.20.8 CERRSET Register (Offset = 22h) [reset = 0h]
CERRSET is shown in Figure 2-277 and described in Table 2-307.
Return to Summary Table.
Correctable Error Flag Set Register
Figure 2-277. CERRSET Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
CLA1RDERR
R=0/W=1-0h

1
DMARDERR
R=0/W=1-0h

0
CPURDERR
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

Table 2-307. CERRSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

CLA1RDERR

R=0/W=1

0h

0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

1

DMARDERR

R=0/W=1

0h

0: No action.
1: DMA Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

0

CPURDERR

R=0/W=1

0h

0: No action.
1: CPU Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

528

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.20.9 CERRCLR Register (Offset = 24h) [reset = 0h]
CERRCLR is shown in Figure 2-278 and described in Table 2-308.
Return to Summary Table.
Correctable Error Flag Clear Register
Figure 2-278. CERRCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
RESERVED
R-0h

2
CLA1RDERR
R=0/W=1-0h

1
DMARDERR
R=0/W=1-0h

0
CPURDERR
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

Table 2-308. CERRCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

CLA1RDERR

R=0/W=1

0h

0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn

1

DMARDERR

R=0/W=1

0h

0: No action.
1: DMA Read Error Flag in CERRFLG register will be cleared .
Reset type: SYSRSn

0

CPURDERR

R=0/W=1

0h

0: No action.
1: CPU Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

529

Registers

www.ti.com

2.15.20.10 CCPUREADDR Register (Offset = 26h) [reset = 0h]
CCPUREADDR is shown in Figure 2-279 and described in Table 2-309.
Return to Summary Table.
Correctable CPU Read Error Address
Figure 2-279. CCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CCPUREADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-309. CCPUREADDR Register Field Descriptions
Bit
31-0

530

Field

Type

Reset

Description

CCPUREADDR

R

0h

This register captures the address location for which CPU read/fetch
access resulted in correctable ECC error.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.20.11 CERRCNT Register (Offset = 2Eh) [reset = 0h]
CERRCNT is shown in Figure 2-280 and described in Table 2-310.
Return to Summary Table.
Correctable Error Count Register
Figure 2-280. CERRCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CERRCNT
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-310. CERRCNT Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CERRCNT

R

0h

This register holds the count of how many times correctable error
occurred.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

531

Registers

www.ti.com

2.15.20.12 CERRTHRES Register (Offset = 30h) [reset = 0h]
CERRTHRES is shown in Figure 2-281 and described in Table 2-311.
Return to Summary Table.
Correctable Error Threshold Value Register
Figure 2-281. CERRTHRES Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CERRTHRES
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 2-311. CERRTHRES Register Field Descriptions
Bit
31-0

532

Field

Type

Reset

Description

CERRTHRES

R/W

0h

When value in CERRCNT register is greater or equal to than value
configured in this register, corretable interrupt gets generated, if
enabled.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.20.13 CEINTFLG Register (Offset = 32h) [reset = 0h]
CEINTFLG is shown in Figure 2-282 and described in Table 2-312.
Return to Summary Table.
Correctable Error Interrupt Flag Status Register
Figure 2-282. CEINTFLG Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
CEINTFLAG
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-312. CEINTFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

0

CEINTFLAG

R

0h

Total corrected error count exceeded threshold Flag
0: Total correctable errors < Threshold value configured in
CERRTHRES register.
1: Total correctable errors >= Threshold value configured in
CERRTHRES register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

533

Registers

www.ti.com

2.15.20.14 CEINTCLR Register (Offset = 34h) [reset = 0h]
CEINTCLR is shown in Figure 2-283 and described in Table 2-313.
Return to Summary Table.
Correctable Error Interrupt Flag Clear Register
Figure 2-283. CEINTCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
CEINTCLR
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-313. CEINTCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

0

CEINTCLR

R=0/W=1

0h

0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be cleared.
Reset type: SYSRSn

534

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.20.15 CEINTSET Register (Offset = 36h) [reset = 0h]
CEINTSET is shown in Figure 2-284 and described in Table 2-314.
Return to Summary Table.
Correctable Error Interrupt Flag Set Register
Figure 2-284. CEINTSET Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
CEINTSET
R=0/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-314. CEINTSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

0

CEINTSET

R=0/W=1

0h

0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be set and interrupt will be generated if enabled.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

535

Registers

www.ti.com

2.15.20.16 CEINTEN Register (Offset = 38h) [reset = 0h]
CEINTEN is shown in Figure 2-285 and described in Table 2-315.
Return to Summary Table.
Correctable Error Interrupt Enable Register
Figure 2-285. CEINTEN Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
CEINTEN
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-315. CEINTEN Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

CEINTEN

R/W

0h

0: Correctable Error Interrupt is disabled.

0

1: Correctable Error Interrupt is enabled.
Reset type: SYSRSn

536

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.21 ROM_WAIT_STATE_REGS Registers
Table 2-316 lists the memory-mapped registers for the ROM_WAIT_STATE_REGS. All register offset
addresses not listed in Table 2-316 should be considered as reserved locations and the register contents
should not be modified.
Table 2-316. ROM_WAIT_STATE_REGS Registers
Offset
0h

Acronym

Register Name

Write Protection

ROMWAITSTATE

ROM Wait State Configuration Register

EALLOW

Section
Go

Complex bit access types are encoded to fit into small table cells. Table 2-317 shows the codes that are
used for access types in this section.
Table 2-317. ROM_WAIT_STATE_REGS Access Type
Codes
Access Type

Code

Description

R

Read

W

Write

Read Type
R
Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

537

Registers

www.ti.com

2.15.21.1 ROMWAITSTATE Register (Offset = 0h) [reset = 0h]
ROMWAITSTATE is shown in Figure 2-286 and described in Table 2-318.
Return to Summary Table.
ROM Wait State Configuration Register
Figure 2-286. ROMWAITSTATE Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
WSDISABLE
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-318. ROMWAITSTATE Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

0

WSDISABLE

R/W

0h

0: ROM Wait State is enabled. CPU accesses to ROM are are 1wait.
1: ROM Wait State is disabled. CPU accesses to ROM are 0-wait.
Reset type: SYSRSn

538

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.22 FLASH_CTRL_REGS Registers
Table 2-319 lists the memory-mapped registers for the FLASH_CTRL_REGS. All register offset addresses
not listed in Table 2-319 should be considered as reserved locations and the register contents should not
be modified.
Table 2-319. FLASH_CTRL_REGS Registers
Offset

Acronym

Register Name

Write Protection

0h

Section

FRDCNTL

Flash Read Control Register

EALLOW

Go

1Eh

FBAC

Flash Bank Access Control Register

EALLOW

Go

20h

FBFALLBACK

Flash Bank Fallback Power Register

EALLOW

Go

22h

FBPRDY

Flash Bank Pump Ready Register

EALLOW

Go

24h

FPAC1

Flash Pump Access Control Register 1

EALLOW

Go

2Ah

FMSTAT

Flash Module Status Register

EALLOW

Go

180h

FRD_INTF_CTRL

Flash Read Interface Control Register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 2-320 shows the codes that are
used for access types in this section.
Table 2-320. FLASH_CTRL_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

Write

Read Type
R
Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

539

Registers

www.ti.com

2.15.22.1 FRDCNTL Register (Offset = 0h) [reset = F00h]
FRDCNTL is shown in Figure 2-287 and described in Table 2-321.
Return to Summary Table.
Flash Read Control Register
Figure 2-287. FRDCNTL Register
31

30

29

28

27

26

25

15

14
13
RESERVED
R-0h

12

11

10
9
RWAIT
R/W-Fh

24
23
RESERVED
R-0h
8

7

22

21

20

19

18

17

16

6

5

4
3
RESERVED
R-0h

2

1

0

Table 2-321. FRDCNTL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-12

RESERVED

R

0h

Reserved

11-8

RWAIT

R/W

Fh

Random read waitstate
These bits indicate how many waitstates are added to a flash read
access. The RWAIT value can be set anywhere from 0 to 0xF. For a
flash access, data is returned in RWAIT+1 SYSCLK cycles.
Note: The required wait states for each SYSCLK frequency can be
found in the device data manual.
Reset type: SYSRSn

7-0

540

RESERVED

System Control

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.22.2 FBAC Register (Offset = 1Eh) [reset = Fh]
FBAC is shown in Figure 2-288 and described in Table 2-322.
Return to Summary Table.
Flash Bank Access Control Register
Figure 2-288. FBAC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
RESERVED
R-0h
R-0h

9

8

7

6

5

4 3 2
VREADST
R/W-Fh

1

0

Table 2-322. FBAC Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-8

RESERVED

R

0h

Reserved

7-0

VREADST

R/W

Fh

This bit-field ensures that the requisite delay is introduced for the
flash pump/bank to come out of low-power mode, so that the
flash/OTP array is ready for CPU accesses. The reset value of this
bit-field is 0xF. Before entering any low-power mode for the flash
bank/pump, this bit-field must be configured as described in the
"Flash and OTP Memory" chapter of the TRM. Applications typically
use the flash bank/pump low-power modes to reduce power (i)
during the device low-power modes such as IDLE/STANDBY/HALT
(ii) while running code off RAM after powering down the flash.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

541

Registers

www.ti.com

2.15.22.3 FBFALLBACK Register (Offset = 20h) [reset = 0h]
FBFALLBACK is shown in Figure 2-289 and described in Table 2-323.
Return to Summary Table.
Flash Bank Fallback Power Register
Figure 2-289. FBFALLBACK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

0
BNKPWR0
R/W-0h

Table 2-323. FBFALLBACK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-2

RESERVED

R

0h

Reserved

1-0

BNKPWR0

R/W

0h

Bank Power Mode Control
00 Sleep (Sense amplifiers and sense reference disabled)
01 Standby (Sense amplifiers disabled, but sense reference
enabled)
10 Reserved
11 Active (Both sense amplifiers and sense reference enabled)
Note: If the bank and pump are not in active mode and an access is
made, the value of this register is automatically changed to active.
Reset type: SYSRSn

542

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.22.4 FBPRDY Register (Offset = 22h) [reset = 0h]
FBPRDY is shown in Figure 2-290 and described in Table 2-324.
Return to Summary Table.
Flash Bank Pump Ready Register
Figure 2-290. FBPRDY Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
PUMPRDY
R-0h

14

13

12

11
RESERVED
R-0h

10

9

8

7

6

5

4
RESERVED
R-0h

3

2

1

0
BANKRDY
R-0h

Table 2-324. FBPRDY Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15

PUMPRDY

R

0h

Pump Ready. This is a read-only bit which allows software to
determine if the pump is ready for flash access before attempting the
actual access. If an access is made to a bank when the pump is not
ready, wait states are asserted until it becomes ready.
0 Pump is not ready.
1 Pump is ready, in active power state.
Reset type: SYSRSn

14-1
0

RESERVED

R

0h

Reserved

BANKRDY

R

0h

Bank Ready. This is a read-only register which allows software to
determine if the bank is ready for Flash access before the access is
attempted.
Note: The user should wait for both the pump and the bank to be
ready before attempting an access.
0 Bank is not ready.
1 Bank is in active power mode and is ready for access.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

543

Registers

www.ti.com

2.15.22.5 FPAC1 Register (Offset = 24h) [reset = 08600000h]
FPAC1 is shown in Figure 2-291 and described in Table 2-325.
Return to Summary Table.
Flash Pump Access Control Register 1
Figure 2-291. FPAC1 Register
31

30

29

28

27

26

RESERVED
R-0h
23

22

25

24

PSLEEP
R/W-860h
21

20

19

18

17

16

11

10

9

8

3

2

1

0
PMPPWR
R/W-0h

PSLEEP
R/W-860h
15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-325. FPAC1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

RESERVED

R

0h

Reserved

27-16

PSLEEP

R/W

860h

Pump sleep. These bits contain the starting count value for the
charge pump sleep down counter. While the charge pump is in sleep
mode, the power mode management logic holds the charge pump
sleep counter at this value. When the charge pump exits sleep
power mode, the down counter delays from 0 to PSLEEP prescaled
SYSCLK clock cycles before putting the charge pump into active
power mode.
Note: The pump sleep down counter uses a prescaled clock which is
divided by 2 of input SYSCLK. The configured PSLEEP value should
yield a delay of at least 20 microseconds for the pump to go to active
mode.
Reset type: SYSRSn

15-1
0

RESERVED

R

0h

Reserved

PMPPWR

R/W

0h

Flash Charge Pump Control Power Mode.
Configures the power mode of the charge pump.
0 Sleep (all pump circuits disabled)
1 Active (all pump circuits active)
Reset type: SYSRSn

544

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.22.6 FMSTAT Register (Offset = 2Ah) [reset = 0h]
FMSTAT is shown in Figure 2-292 and described in Table 2-326.
Return to Summary Table.
Flash Module Status Register
Figure 2-292. FMSTAT Register
31

30

29

28

27

26

25

24

20

19

18

17
RESERVED
R-0h

16
RESERVED
R-0h

RESERVED
R-0h
23

22

21
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
PGV
R-0h

11
RESERVED
R-0h

10
EV
R-0h

9
RESERVED
R-0h

8
BUSY
R-0h

7
ERS
R-0h

6
PGM
R-0h

5
INVDAT
R-0h

4
CSTAT
R-0h

3
VOLTSTAT
R-0h

2
RESERVED
R-0h

1
RESERVED
R-0h

0
RESERVED
R-0h

Table 2-326. FMSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

PGV

R

0h

Program verify When set, indicates that a word is not successfully
programmed after the maximum allowed number of program pulses
are given for program operation.
Reset type: SYSRSn

11

RESERVED

R

0h

Reserved

10

EV

R

0h

Erase verify When set, indicates that a sector is not successfully
erased after the maximum allowed number of erase pulses are given
for erase operation.
Reset type: SYSRSn

9

RESERVED

R

0h

Reserved

8

BUSY

R

0h

When set, this bit indicates that a program, erase, or suspend
operation is being processed.
Reset type: SYSRSn

7

ERS

R

0h

Erase Active. When set, this bit indicates that the flash module is
actively performing an erase operation. This bit is set when erasing
starts and is cleared when erasing is complete. It is also cleared
when the erase is suspended and set when the erase resumes.
Reset type: SYSRSn

6

PGM

R

0h

Program Active. When set, this bit indicates that the flash module is
currently performing a program operation. This bit is set when
programming starts and is cleared when programming is complete. It
is also cleared when programming is suspended and set when
programming is resumed.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

545

Registers

www.ti.com

Table 2-326. FMSTAT Register Field Descriptions (continued)
Bit

546

Field

Type

Reset

Description

5

INVDAT

R

0h

Invalid Data. When set, this bit indicates that the user attempted to
program a "1" where a "0" was already present.
Reset type: SYSRSn

4

CSTAT

R

0h

Command Status. Once the FSM starts any failure will set this bit.
When set, this bit informs the host that the program, erase, or
validate sector command failed and the command was stopped. This
bit is cleared by the Clear Status command. For some errors, this
will be the only indication of an FSM error because the cause does
not fall within the other error bit types.
Reset type: SYSRSn

3

VOLTSTAT

R

0h

Core Voltage Status. When set, this bit indicates that the core
voltage generator of the pump power upply dipped below the lower
limit allowable during a program or erase operation.
Reset type: SYSRSn

2

RESERVED

R

0h

Reserved

1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.22.7 FRD_INTF_CTRL Register (Offset = 180h) [reset = 0h]
FRD_INTF_CTRL is shown in Figure 2-293 and described in Table 2-327.
Return to Summary Table.
Flash Read Interface Control Register
Figure 2-293. FRD_INTF_CTRL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
DATA_CACHE
_EN
R/W-0h

0
PREFETCH_E
N
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 2-327. FRD_INTF_CTRL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-2

RESERVED

R

0h

Reserved

DATA_CACHE_EN

R/W

0h

Data cache enable.

1

0 A value of 0 disables the data cache.
1 A value of 1 enables the data cache.
Reset type: SYSRSn
0

PREFETCH_EN

R/W

0h

Prefetch enable.
0 A value of 0 disables prefetch mechanism.
1 A value of 1 enables pre-fetch mechanism.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

547

Registers

www.ti.com

2.15.23 FLASH_ECC_REGS Registers
Table 2-328 lists the memory-mapped registers for the FLASH_ECC_REGS. All register offset addresses
not listed in Table 2-328 should be considered as reserved locations and the register contents should not
be modified.
Table 2-328. FLASH_ECC_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

ECC_ENABLE

ECC Enable

EALLOW

Go

2h

SINGLE_ERR_ADDR_LOW

Single Error Address Low

EALLOW

Go

4h

SINGLE_ERR_ADDR_HIGH

Single Error Address High

EALLOW

Go

6h

UNC_ERR_ADDR_LOW

Uncorrectable Error Address Low

EALLOW

Go

8h

UNC_ERR_ADDR_HIGH

Uncorrectable Error Address High

EALLOW

Go

Ah

ERR_STATUS

Error Status

EALLOW

Go

Ch

ERR_POS

Error Position

EALLOW

Go

Eh

ERR_STATUS_CLR

Error Status Clear

EALLOW

Go

10h

ERR_CNT

Error Control

EALLOW

Go

12h

ERR_THRESHOLD

Error Threshold

EALLOW

Go

14h

ERR_INTFLG

Error Interrupt Flag

EALLOW

Go

16h

ERR_INTCLR

Error Interrupt Flag Clear

EALLOW

Go

18h

FDATAH_TEST

Data High Test

EALLOW

Go

1Ah

FDATAL_TEST

Data Low Test

EALLOW

Go

1Ch

FADDR_TEST

ECC Test Address

EALLOW

Go

1Eh

FECC_TEST

ECC Test Address

EALLOW

Go

20h

FECC_CTRL

ECC Control

EALLOW

Go

22h

FOUTH_TEST

Test Data Out High

EALLOW

Go

24h

FOUTL_TEST

Test Data Out Low

EALLOW

Go

26h

FECC_STATUS

ECC Status

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 2-329 shows the codes that are
used for access types in this section.
Table 2-329. FLASH_ECC_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

548

System Control

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 2-329. FLASH_ECC_REGS Access Type
Codes (continued)
Access Type

Code

y

Description
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

549

Registers

www.ti.com

2.15.23.1 ECC_ENABLE Register (Offset = 0h) [reset = Ah]
ECC_ENABLE is shown in Figure 2-294 and described in Table 2-330.
Return to Summary Table.
ECC Enable
Figure 2-294. ECC_ENABLE Register
31

30

29

28

27

26

25

15

14

13

12

11

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

7

22

21

20

19

18

17

16

6

5

4

3

2
1
ENABLE
R/W-Ah

0

Table 2-330. ECC_ENABLE Register Field Descriptions
Bit

550

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-4

RESERVED

R

0h

Reserved

3-0

ENABLE

R/W

Ah

ECC enable. A value of 0xA would enable ECC. Any other value
would disable ECC.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.2 SINGLE_ERR_ADDR_LOW Register (Offset = 2h) [reset = 0h]
SINGLE_ERR_ADDR_LOW is shown in Figure 2-295 and described in Table 2-331.
Return to Summary Table.
Single Error Address Low
Figure 2-295. SINGLE_ERR_ADDR_LOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERR_ADDR_L
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 2-331. SINGLE_ERR_ADDR_LOW Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ERR_ADDR_L

R/W

0h

64-bit aligned address at which a single bit error occurred in the
lower 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

551

Registers

www.ti.com

2.15.23.3 SINGLE_ERR_ADDR_HIGH Register (Offset = 4h) [reset = 0h]
SINGLE_ERR_ADDR_HIGH is shown in Figure 2-296 and described in Table 2-332.
Return to Summary Table.
Single Error Address High
Figure 2-296. SINGLE_ERR_ADDR_HIGH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERR_ADDR_H
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 2-332. SINGLE_ERR_ADDR_HIGH Register Field Descriptions
Bit
31-0

552

Field

Type

Reset

Description

ERR_ADDR_H

R/W

0h

64-bit aligned address at which a single bit error occurred in the
upper 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.4 UNC_ERR_ADDR_LOW Register (Offset = 6h) [reset = 0h]
UNC_ERR_ADDR_LOW is shown in Figure 2-297 and described in Table 2-333.
Return to Summary Table.
Uncorrectable Error Address Low
Figure 2-297. UNC_ERR_ADDR_LOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UNC_ERR_ADDR_L
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 2-333. UNC_ERR_ADDR_LOW Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

UNC_ERR_ADDR_L

R/W

0h

64-bit aligned address at which an uncorrectable error occurred in
the lower 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

553

Registers

www.ti.com

2.15.23.5 UNC_ERR_ADDR_HIGH Register (Offset = 8h) [reset = 0h]
UNC_ERR_ADDR_HIGH is shown in Figure 2-298 and described in Table 2-334.
Return to Summary Table.
Uncorrectable Error Address High
Figure 2-298. UNC_ERR_ADDR_HIGH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UNC_ERR_ADDR_H
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 2-334. UNC_ERR_ADDR_HIGH Register Field Descriptions
Bit
31-0

554

Field

Type

Reset

Description

UNC_ERR_ADDR_H

R/W

0h

64-bit aligned address at which an uncorrectable error occurred in
the upper 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.6 ERR_STATUS Register (Offset = Ah) [reset = 0h]
ERR_STATUS is shown in Figure 2-299 and described in Table 2-335.
Return to Summary Table.
Error Status
Figure 2-299. ERR_STATUS Register
31

30

29

28

27

26

25

24

19

18
UNC_ERR_H
R-0h

17
FAIL_1_H
R-0h

16
FAIL_0_H
R-0h

11

10

9

8

3

2
UNC_ERR_L
R-0h

1
FAIL_1_L
R-0h

0
FAIL_0_L
R-0h

RESERVED
R-0h
23

22

21
RESERVED
R-0h

20

15

14

13

12
RESERVED
R-0h

7

6

5
RESERVED
R-0h

4

Table 2-335. ERR_STATUS Register Field Descriptions
Bit
31-19

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

18

UNC_ERR_H

R

0h

Uncorrectable error. A value of 1 indicates that an un-correctable
error occurred in upper 64bits of a 128-bit aligned address. Cleared
by writing a 1 to UNC_ERR_H_CLR bit of ERR_STATUS_CLR
register.
Reset type: SYSRSn

17

FAIL_1_H

R

0h

Fail on 1.
0 Fail on 1 single bit error did not occur in upper 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper
64bits of a 128-bit aligned address and the corrected value was 1.
Cleared by writing a 1 to FAIL_1_H_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn

16

FAIL_0_H

R

0h

Fail on 0.
0 Fail on 0 single bit error did not occur in upper 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper
64bits of a 128-bit aligned address and the corrected value was 0.
Cleared by writing a 1 to FAIL_0_H_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occurred.
Reset type: SYSRSn

15-3

RESERVED

R

0h

Reserved

2

UNC_ERR_L

R

0h

Uncorrectable error. A value of 1 indicates that an un-correctable
error occurred in lower 64bits of a 128-bit aligned address. Cleared
by writing a 1 to UNC_ERR_L_CLR bit of ERR_STATUS_CLR
register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

555

Registers

www.ti.com

Table 2-335. ERR_STATUS Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

FAIL_1_L

R

0h

Fail on 1.
0 Fail on 1 single bit error did not occur in lower 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in lower
64bits of a 128-bit aligned address and the corrected value was 1.
Cleared by writing a 1 to FAIL_1_L_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn

0

FAIL_0_L

R

0h

Fail on 0.
0 Fail on 0 single bit error did not occur in lower 64bits of a 128-bit
aligned address.
1 Would indicate that a single bit error occurred in lower 64bits of a
128-bit aligned address and the corrected value was 0. Cleared by
writing a 1 to FAIL_0_L_CLR bit of ERR_STATUS_CLR register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn

556

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.7 ERR_POS Register (Offset = Ch) [reset = 0h]
ERR_POS is shown in Figure 2-300 and described in Table 2-336.
Return to Summary Table.
Error Position
Figure 2-300. ERR_POS Register
31

23

30

29

28
RESERVED
R-0h

27

22

21

20

19

RESERVED
R-0h
15

7

26

25

24
ERR_TYPE_H
R-0h

18

17

16

10

9

8
ERR_TYPE_L
R-0h

2

1

0

ERR_POS_H
R-0h
14

13

12
RESERVED
R-0h

11

6

5

4

3

RESERVED
R-0h

ERR_POS_L
R-0h

Table 2-336. ERR_POS Register Field Descriptions
Bit
31-25
24

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

ERR_TYPE_H

R

0h

Error type
0 Indicates that a single bit error occured in upper 64 data bits of a
128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of upper
64bits of a 128-bit aligned address.
Reset type: SYSRSn

23-22

RESERVED

R

0h

Reserved

21-16

ERR_POS_H

R

0h

Error position. Bit position of the single bit error in upper 64bits of a
128-bit aligned address. The position is interpreted depending on
whether the ERR_TYPE bit indicates a check bit or a data bit. If
ERR_TYPE indicates a check bit error, the error position could range
from 0 to 7, else it could range from 0 to 63.
Reset type: SYSRSn

15-9

RESERVED

R

0h

Reserved

ERR_TYPE_L

R

0h

Error type

8

0 Indicates that a single bit error occured in lower 64 data bits of a
128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of lower
64bits of a 128-bit aligned address.
Reset type: SYSRSn
7-6

RESERVED

R

0h

Reserved

5-0

ERR_POS_L

R

0h

Error position. Bit position of the single bit error in lower 64bits of a
128-bit aligned address. The position is interpreted depending on
whether the ERR_TYPE bit indicates a check bit or a data bit. If
ERR_TYPE indicates a check bit error, the error position could range
from 0 to 7, else it could range from 0 to 63.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

557

Registers

www.ti.com

2.15.23.8 ERR_STATUS_CLR Register (Offset = Eh) [reset = 0h]
ERR_STATUS_CLR is shown in Figure 2-301 and described in Table 2-337.
Return to Summary Table.
Error Status Clear
Figure 2-301. ERR_STATUS_CLR Register
31

30

29

28

27

26

19

18
UNC_ERR_H_
CLR
R=0/W=1-0h

25

24

RESERVED
R-0h
23

22

21
RESERVED

20

R-0h
15

14

13

12

11

10

3

2
UNC_ERR_L_
CLR
R=0/W=1-0h

17
16
FAIL_1_H_CLR FAIL_0_H_CLR
R=0/W=1-0h

R=0/W=1-0h

9

8

RESERVED
R-0h
7

6

5
RESERVED

4

R-0h

1
0
FAIL_1_L_CLR FAIL_0_L_CLR
R=0/W=1-0h

R=0/W=1-0h

Table 2-337. ERR_STATUS_CLR Register Field Descriptions
Bit
31-19
18

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

UNC_ERR_H_CLR

R=0/W=1

0h

Uncorrectable error clear. Writing a 1 to this bit will clear the
UNC_ERR_H bit of ERR_STATUS
register. Writes of 0 have no effect. Read returns 0.
Reset type: SYSRSn

17

FAIL_1_H_CLR

R=0/W=1

0h

Fail on 1 clear. Writing a 1 to this bit will clear the FAIL_1_H bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn

16

FAIL_0_H_CLR

R=0/W=1

0h

Fail on 0 clear. Writing a 1 to this bit will clear the FAIL_0_H bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn

15-3
2

RESERVED

R

0h

Reserved

UNC_ERR_L_CLR

R=0/W=1

0h

Uncorrectable error clear. Writing a 1 to this bit will clear the
UNC_ERR_L bit of ERR_STATUS
register. Writes of 0 have no effect. Read returns 0.
Reset type: SYSRSn

1

FAIL_1_L_CLR

R=0/W=1

0h

Fail on 1 clear. Writing a 1 to this bit will clear the FAIL_1_L bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn

0

FAIL_0_L_CLR

R=0/W=1

0h

Fail on 0 clear. Writing a 1 to this bit will clear the FAIL_0_L bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn

558

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.9 ERR_CNT Register (Offset = 10h) [reset = 0h]
ERR_CNT is shown in Figure 2-302 and described in Table 2-338.
Return to Summary Table.
Error Control
Figure 2-302. ERR_CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9

8 7 6
ERR_CNT
R/W-0h

5

4

3

2

1

0

Table 2-338. ERR_CNT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-0

ERR_CNT

R/W

0h

Single bit error count. This counter increments with every single bit
ECC error occurrence. Upon reaching the threshold value counter
stops counting on single bit errors. ERR_CNT can be cleared
(irrespective of whether threshold is met or not) using "Single Err Int
Clear" bit. This is applicable for ECC logic test mode and normal
operational mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

559

Registers

www.ti.com

2.15.23.10 ERR_THRESHOLD Register (Offset = 12h) [reset = 0h]
ERR_THRESHOLD is shown in Figure 2-303 and described in Table 2-339.
Return to Summary Table.
Error Threshold
Figure 2-303. ERR_THRESHOLD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
RESERVED
ERR_THRESHOLD
R-0h
R/W-0h

4

3

2

1

0

Table 2-339. ERR_THRESHOLD Register Field Descriptions
Bit

560

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-0

ERR_THRESHOLD

R/W

0h

Single bit error threshold. Sets the threshold for single bit errors.
When the ERR_CNT value equals the THRESHOLD value and a
single bit error occurs, SINGLE_ERR_INT flag is set, and an
interrupt is fired.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.11 ERR_INTFLG Register (Offset = 14h) [reset = 0h]
ERR_INTFLG is shown in Figure 2-304 and described in Table 2-340.
Return to Summary Table.
Error Interrupt Flag
Figure 2-304. ERR_INTFLG Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

1
0
UNC_ERR_INT SINGLE_ERR_
FLG
INTFLG
R-0h
R-0h

Table 2-340. ERR_INTFLG Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-2

RESERVED

R

0h

Reserved

1

UNC_ERR_INTFLG

R

0h

Uncorrectable bit error interrupt flag. When a Un-correctable error
occurs, this bit is set and the UNC_ERR_INT interrupt is fired. When
UNC_ERR_INTCLR bit of ERR_INTCLR register is written a value of
1 this bit is cleared.
Reset type: SYSRSn

0

SINGLE_ERR_INTFLG

R

0h

Single bit error interrupt flag. When the ERR_CNT value equals the
ERR_THRESHOLD value and a single bit error occurs then
SINGLE_ERR_INT flag is set and SINGLE_ERR_INT interrupt is
fired. When SINGLE_ERR_INTCLR bit of ERR_INTCLR register is
written a value of 1 this bit is cleared.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

561

Registers

www.ti.com

2.15.23.12 ERR_INTCLR Register (Offset = 16h) [reset = 0h]
ERR_INTCLR is shown in Figure 2-305 and described in Table 2-341.
Return to Summary Table.
Error Interrupt Flag Clear
Figure 2-305. ERR_INTCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

1
0
UNC_ERR_INT SINGLE_ERR_
CLR
INTCLR
R=0/W=1-0h
R=0/W=1-0h

Table 2-341. ERR_INTCLR Register Field Descriptions
Bit

562

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-2

RESERVED

R

0h

Reserved

1

UNC_ERR_INTCLR

R=0/W=1

0h

Uncorrectable bit error interrupt flag clear. Writing a 1 to this bit will
clear UNC_ERR_INT_FLG. Writes of 0 have no effect.
Reset type: SYSRSn

0

SINGLE_ERR_INTCLR

R=0/W=1

0h

Single bit error interrupt flag clear. Writing a 1 to this bit will clear
SINGLE_ERR_INT_FLG. Writes of 0 have no effect.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.13 FDATAH_TEST Register (Offset = 18h) [reset = 0h]
FDATAH_TEST is shown in Figure 2-306 and described in Table 2-342.
Return to Summary Table.
Data High Test
Figure 2-306. FDATAH_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FDATAH
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 2-342. FDATAH_TEST Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

FDATAH

R/W

0h

High double word of selected 64-bit data. User-configurable bits
63:32 of the selected data block in ECC test mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

563

Registers

www.ti.com

2.15.23.14 FDATAL_TEST Register (Offset = 1Ah) [reset = 0h]
FDATAL_TEST is shown in Figure 2-307 and described in Table 2-343.
Return to Summary Table.
Data Low Test
Figure 2-307. FDATAL_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FDATAL
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 2-343. FDATAL_TEST Register Field Descriptions
Bit
31-0

564

Field

Type

Reset

Description

FDATAL

R/W

0h

Low double word of selected 64-bit data. User-configurable bits 31:0
of the selected data block in ECC test mode.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.15 FADDR_TEST Register (Offset = 1Ch) [reset = 0h]
FADDR_TEST is shown in Figure 2-308 and described in Table 2-344.
Return to Summary Table.
ECC Test Address
Figure 2-308. FADDR_TEST Register
31

30

29

28

27
26
RESERVED
R-0h

15

14

13

12

11

10

25

24

23

22

21

20

19
18
ADDRH
R/W-0h

9
ADDRL
R/W-0h

8

7

6

5

4

3

2

17

16

1
0
RESERVED
R-0h

Table 2-344. FADDR_TEST Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

RESERVED

R

0h

Reserved

21-16

ADDRH

R/W

0h

Address for selected 64-bit data. User-configurable address bits of
the selected data in ECC test mode. Left-shift the address by one bit
(to provide byte address) and ignore the three least significant bits of
the address and write the bits 21:16 in remaining address bits in this
field.
Reset type: SYSRSn

15-3

ADDRL

R/W

0h

Address for selected 64-bit data. User-configurable address bits of
the selected data in ECC test mode. Left-shift the address by one bit
(to provide byte address) and ignore the three least significant bits of
the address and write the bits 15:3 in remaining address bits in this
field.
Reset type: SYSRSn

2-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

565

Registers

www.ti.com

2.15.23.16 FECC_TEST Register (Offset = 1Eh) [reset = 0h]
FECC_TEST is shown in Figure 2-309 and described in Table 2-345.
Return to Summary Table.
ECC Test Address
Figure 2-309. FECC_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
RESERVED
R-0h
R-0h

9

8

7

6

5

4 3 2
ECC
R/W-0h

1

0

Table 2-345. FECC_TEST Register Field Descriptions
Bit

566

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-8

RESERVED

R

0h

Reserved

7-0

ECC

R/W

0h

8-bit ECC for selected 64-bit data. User-configurable ECC bits of the
selected 64-bit data block in ECC test mode.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.17 FECC_CTRL Register (Offset = 20h) [reset = 0h]
FECC_CTRL is shown in Figure 2-310 and described in Table 2-346.
Return to Summary Table.
ECC Control
Figure 2-310. FECC_CTRL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2
DO_ECC_CAL
C
R=0/W=1-0h

1
ECC_SELECT

0
ECC_TEST_E
N
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5
RESERVED

4

R-0h

R/W-0h

Table 2-346. FECC_CTRL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-3

RESERVED

R

0h

Reserved

2

DO_ECC_CALC

R=0/W=1

0h

Enable ECC calculation. ECC logic will calculate ECC in one cycle
for the data and address written in ECC test registers when ECC test
logic is enabled by setting ECC_TEST_EN.
Reset type: SYSRSn

1

ECC_SELECT

R/W

0h

ECC block select.
0 Selects the ECC block on bits [63:0] of bank data.
1 Selects the ECC block on bits [127:64] of bank data.
Reset type: SYSRSn

0

ECC_TEST_EN

R/W

0h

ECC test mode enable.
0 ECC test mode disabled
1 ECC test mode enabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

567

Registers

www.ti.com

2.15.23.18 FOUTH_TEST Register (Offset = 22h) [reset = 0h]
FOUTH_TEST is shown in Figure 2-311 and described in Table 2-347.
Return to Summary Table.
Test Data Out High
Figure 2-311. FOUTH_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATAOUTH
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-347. FOUTH_TEST Register Field Descriptions
Bit
31-0

568

Field

Type

Reset

Description

DATAOUTH

R

0h

High double word test data out. Holds bits 63:32 of the data out of
the selected ECC block.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.23.19 FOUTL_TEST Register (Offset = 24h) [reset = 0h]
FOUTL_TEST is shown in Figure 2-312 and described in Table 2-348.
Return to Summary Table.
Test Data Out Low
Figure 2-312. FOUTL_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATAOUTL
R-0h

9

8

7

6

5

4

3

2

1

0

Table 2-348. FOUTL_TEST Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

DATAOUTL

R

0h

Low double word test data out. Holds bits 31:0 of the data out of the
selected ECC block.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

569

Registers

www.ti.com

2.15.23.20 FECC_STATUS Register (Offset = 26h) [reset = 0h]
FECC_STATUS is shown in Figure 2-313 and described in Table 2-349.
Return to Summary Table.
ECC Status
Figure 2-313. FECC_STATUS Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8
ERR_TYPE
R-0h

3

2

1
UNC_ERR
R-0h

0
SINGLE_ERR
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5
4
DATA_ERR_POS
R-0h

Table 2-349. FECC_STATUS Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-9

RESERVED

R

0h

Reserved

8

ERR_TYPE

R

0h

Test mode ECC single bit error indicator. When 1, indicates that the
single bit error is in check bits. When 0, indicates that the single bit
error is in data bits (If SINGLE_ERR field is also set).
Reset type: SYSRSn

DATA_ERR_POS

R

0h

Test mode single bit error position. Holds the bit position where the
single bit error occurred.

7-2

The position is interpreted depending on whether the CHK_ERR bit
indicates a check bit or a data bit. If CHK_ERR indicates a check bit
error, the error position could range from 0 to 7, or it could range
from 0 to 63.
Reset type: SYSRSn

570

1

UNC_ERR

R

0h

Test mode ECC double bit error. When 1 indicates that the ECC test
resulted in an uncorrectable bit error.
Reset type: SYSRSn

0

SINGLE_ERR

R

0h

Test mode ECC single bit error. When 1 indicates that the ECC test
resulted in a single bit error.
Reset type: SYSRSn

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.24 CPU_ID_REGS Registers
Table 2-350 lists the memory-mapped registers for the CPU_ID_REGS. All register offset addresses not
listed in Table 2-350 should be considered as reserved locations and the register contents should not be
modified.
Table 2-350. CPU_ID_REGS Registers
Offset

Acronym

Register Name

Write Protection

0h

CPUID_1

Indicates CPU1 or CPU2

Section
Go

Complex bit access types are encoded to fit into small table cells. Table 2-351 shows the codes that are
used for access types in this section.
Table 2-351. CPU_ID_REGS Access Type Codes
Access Type

Code

Description

R

Read

Read Type
R

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

571

Registers

www.ti.com

2.15.24.1 CPUID_1 Register (Offset = 0h) [reset = X]
CPUID_1 is shown in Figure 2-314 and described in Table 2-352.
Return to Summary Table.
This register can be used to identify on which CPU the code is executing.
Figure 2-314. CPUID_1 Register
15

14

13

12

11

10

9

8

3

2

1

0

CPUID
R-X
7

6

5

4
RESERVED
R-0h

Table 2-352. CPUID_1 Register Field Descriptions
Bit

572

Field

Type

Reset

Description

15-8

CPUID

R

X

CPUID = 1 for CPU1, 2 for CPU2
Reset type: N/A

7-0

RESERVED

R

0h

Reserved

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.25 UID_REGS Registers
Table 2-353 lists the memory-mapped registers for the UID_REGS. All register offset addresses not listed
in Table 2-353 should be considered as reserved locations and the register contents should not be
modified.
Table 2-353. UID_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

UID_PSRAND0

UID Psuedo-random 192 bit number

Go

2h

UID_PSRAND1

UID Psuedo-random 192 bit number

Go

4h

UID_PSRAND2

UID Psuedo-random 192 bit number

Go

6h

UID_PSRAND3

UID Psuedo-random 192 bit number

Go

8h

UID_PSRAND4

UID Psuedo-random 192 bit number

Go

Ah

UID_PSRAND5

UID Psuedo-random 192 bit number

Go

Ch

UID_UNIQUE

UID Unique 32 bit number

Go

Eh

UID_CHECKSUM

UID Checksum

Go

Complex bit access types are encoded to fit into small table cells. Table 2-354 shows the codes that are
used for access types in this section.
Table 2-354. UID_REGS Access Type Codes
Access Type

Code

Description

R

Read

Read Type
R

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

573

Registers

www.ti.com

2.15.25.1 UID_PSRAND0 Register (Offset = 0h) [reset = X]
UID_PSRAND0 is shown in Figure 2-315 and described in Table 2-355.
Return to Summary Table.
UID Psuedo-random 192 bit number
Figure 2-315. UID_PSRAND0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RandomID
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-355. UID_PSRAND0 Register Field Descriptions
Bit
31-0

574

Field

Type

Reset

Description

RandomID

R

X

Psuedorandom portion of the UID
Reset type: N/A

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.25.2 UID_PSRAND1 Register (Offset = 2h) [reset = X]
UID_PSRAND1 is shown in Figure 2-316 and described in Table 2-356.
Return to Summary Table.
UID Psuedo-random 192 bit number
Figure 2-316. UID_PSRAND1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RandomID
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-356. UID_PSRAND1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RandomID

R

X

Psuedorandom portion of the UID
Reset type: N/A

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

575

Registers

www.ti.com

2.15.25.3 UID_PSRAND2 Register (Offset = 4h) [reset = X]
UID_PSRAND2 is shown in Figure 2-317 and described in Table 2-357.
Return to Summary Table.
UID Psuedo-random 192 bit number
Figure 2-317. UID_PSRAND2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RandomID
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-357. UID_PSRAND2 Register Field Descriptions
Bit
31-0

576

Field

Type

Reset

Description

RandomID

R

X

Psuedorandom portion of the UID
Reset type: N/A

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.25.4 UID_PSRAND3 Register (Offset = 6h) [reset = X]
UID_PSRAND3 is shown in Figure 2-318 and described in Table 2-358.
Return to Summary Table.
UID Psuedo-random 192 bit number
Figure 2-318. UID_PSRAND3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RandomID
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-358. UID_PSRAND3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RandomID

R

X

Psuedorandom portion of the UID
Reset type: N/A

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

577

Registers

www.ti.com

2.15.25.5 UID_PSRAND4 Register (Offset = 8h) [reset = X]
UID_PSRAND4 is shown in Figure 2-319 and described in Table 2-359.
Return to Summary Table.
UID Psuedo-random 192 bit number
Figure 2-319. UID_PSRAND4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RandomID
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-359. UID_PSRAND4 Register Field Descriptions
Bit
31-0

578

Field

Type

Reset

Description

RandomID

R

X

Psuedorandom portion of the UID
Reset type: N/A

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.25.6 UID_PSRAND5 Register (Offset = Ah) [reset = X]
UID_PSRAND5 is shown in Figure 2-320 and described in Table 2-360.
Return to Summary Table.
UID Psuedo-random 192 bit number
Figure 2-320. UID_PSRAND5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RandomID
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-360. UID_PSRAND5 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RandomID

R

X

Psuedorandom portion of the UID
Reset type: N/A

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

579

Registers

www.ti.com

2.15.25.7 UID_UNIQUE Register (Offset = Ch) [reset = X]
UID_UNIQUE is shown in Figure 2-321 and described in Table 2-361.
Return to Summary Table.
UID Unique 32 bit number
Figure 2-321. UID_UNIQUE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UniqueID
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-361. UID_UNIQUE Register Field Descriptions
Bit
31-0

580

Field

Type

Reset

Description

UniqueID

R

X

Unique portion of the UID. This identifier will be unique across all
devices with the same PARTIDH.
Reset type: N/A

System Control

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

2.15.25.8 UID_CHECKSUM Register (Offset = Eh) [reset = X]
UID_CHECKSUM is shown in Figure 2-322 and described in Table 2-362.
Return to Summary Table.
Fletcher checksum of UID_PSRAND and UID_UNIQUE registers
Figure 2-322. UID_CHECKSUM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Checksum
R-X

9

8

7

6

5

4

3

2

1

0

Table 2-362. UID_CHECKSUM Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

Checksum

R

X

Fletcher checksum of UID_PSRANDx and UID_UINIQUE
Reset type: N/A

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System Control

581

Chapter 3
SPRUHM8G – December 2013 – Revised September 2017

ROM Code and Peripheral Booting
This chapter describes the booting functionality of the 2837xD subsystems.

582

Topic

...........................................................................................................................

3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9

Introduction .....................................................................................................
Device Boot Philosophy ....................................................................................
Device Boot Modes ...........................................................................................
Configuring Boot Mode Pins ..............................................................................
Configuring Get Boot Options ............................................................................
Configuring Emulation Boot Options ..................................................................
Device Boot Flow Diagrams ...............................................................................
Device Reset and Exception Handling .................................................................
Boot ROM Description ......................................................................................

ROM Code and Peripheral Booting

Page

583
583
583
584
585
586
588
593
594

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

3.1

Introduction
This chapter explains the boot ROM code functionality including the boot procedure when executed, the
functions and features of the boot ROM code, and details the ROM memory map contents. On every
reset, the device executes a boot sequence in the ROM depending on the reset type and boot
configuration. This sequence will initialize the device to run application code. The boot ROM also contains
peripheral bootloaders which can be used to load an application into RAM. ROM Memory is shown in
Table 3-1.
Table 3-1. ROM Memory

3.2

ROM

CPU1 Size

CPU2 Size

Unsecure boot ROM

64 KB

64 KB

Secure ROM

64 KB

64 KB

CLA Data ROM

8 KB

8 KB

Device Boot Philosophy
The boot philosophy describes the general boot ROM procedure each time the CPU core is reset. For
dual core devices, CPU1 is the master controller and controls the boot process. Each CPU goes through
its own boot procedure, but under the control of CPU1. The exception to this rule is when CPU2 is set to
boot-to-flash, in which CPU1 is not involved.
During booting, the boot ROM code updates a boot status location in RAM that details the actions taken
during this process. Refer to Section 3.9.10 for more details.
Table 3-2. Boot ROM Philosophy
Step

3.3

CPU1 Action

CPU2 Action

1

After reset, the FUSE error register is checked for any errors and are
handled accordingly.

Held in reset.

2

Clock and Flash Configuration

Held in reset.

3

Device configuration registers are programmed from OTP.

Held in reset.

4

All CPU RAMs are initialized.

Held in reset.

5

Any pending NMI is handled by the code.

Held in reset.

6

DCSM initialization and OTPJTAGLOCK sequence is executed.

Held in reset.

7

Bring CPU2 out of reset.

Brought out of reset and performs:
1. Clock and Flash Configuration
2. All CPU RAMs are initialized
3. DCSM initialization

8

Based on the boot mode select GPIO pins and boot mode set in OTP, the Based on the boot mode value read
boot mode is determined, and the appropriate boot sequence is executed. from OTP, the appropriate boot
Refer to Section 3.7 for a flow chart of the device boot sequences.
sequence is executed.

Device Boot Modes
This section explains the boot modes supported on this device. The boot ROM uses the boot select GPIO
pins to determine the boot mode configuration. The device can be configured to boot to RAM, boot to
flash, execute a bootloader, or hold in a wait mode.
Table 3-3 shows the boot mode options available through selection by the default boot mode select pins.
The boot mode select pins’ GPIOs and realized boot mode for when Get boot mode is selected can be
customized through the BOOTCTRL register detailed in Section 3.4.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting 583

Configuring Boot Mode Pins

www.ti.com

Table 3-3. Device Default Boot Modes for CPU1

(1)

Boot Mode

GPIO72
(Default boot mode select pin 1)

GPIO84
(Default boot mode select pin 0)

Parallel IO

0

0

SCI

0

1

Wait

1

0

Get / Flash (1)

1

1

Get boot mode, by default, on an unprogrammed device, or when the BOOTCTRL register contains an invalid key, will boot to flash. Get
boot mode can be programmed on the device to change its default boot mode. Refer to Section 3.5 for more details on using Get boot
mode.

Table 3-4. All Available Boot Modes
Boot Mode

CPU Support

Parallel IO

CPU1 and CPU2

SCI

CPU1 and CPU2

Wait

CPU1 and CPU2

Get

CPU1 and CPU2

SPI

CPU1 and CPU2

I2C

CPU1 and CPU2

CAN

CPU1 and CPU2

RAM

CPU1 and CPU2

Flash

CPU1 and CPU2

USB

CPU1 Only

NOTE: All the peripheral boot modes that are supported use the first instance of the peripheral
module (SCIA, SPIA, I2CA, CANA, and so forth). Whenever these boot modes are referred
to in this chapter, such as SCI boot, it is actually referring to the first module instance,
meaning the SCI boot on the SCIA port. The same applies to the other peripheral boots.

3.4

Configuring Boot Mode Pins
This section details how the boot mode select pins can be customized by the user, by programming the
BOOTCTRL register location in user-configurable DCSM OTP. The BOOTCTRL register, when
programmed with a valid key, allows different GPIOs to be used for the two boot mode select pins.
Additionally, the boot mode select pins allow the same GPIO to be assigned to each pin for single GPIO
use cases. Also within the BOOTCTRL register, the default boot mode for use with Get boot can be
changed. When debugging, EMU_BOOTCTRL is the emulation equivalent of the BOOTCTRL register and
allows users to experiment with different boot modes without writing to OTP. Refer to Section 3.6 for
details on values that can be set in the EMU_BOOTCTRL register.
Table 3-5. BOOTCTRL (1) Register Bit Fields for CPU1

(1)

Bit

Name

Description

31-24

Boot Mode Select Pin 1 (BMSP1)

Set to the GPIO pin to be used during
boot (up to 255).
0 = Default BMSP1
1 = GPIO0; 2 = GPIO1 and so on to 255 =
GPIO254

23-16

Boot Mode Select Pin 0 (BMSP0)

Set to the GPIO pin to be used during
boot (up to 255).
0 = Default BMSP0
1 = GPIO0; 2 = GPIO1 and so on to 255 =
GPIO254

Refer to the DCSM chapter for the address of this register location in the user-configurable DCSM OTP.

584 ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Configuring Get Boot Options

www.ti.com

Table 3-5. BOOTCTRL (1) Register Bit Fields for CPU1 (continued)
Bit

Name

Description

15-8

Boot Mode (BMODE)

Boot mode definition when using Get boot
mode option. Refer to Section 3.5 for valid
BMODE values.

7-0

Key

Write 0x5A to these 8-bits to tell the boot
ROM code that the bits in this register are
valid

Table 3-6. BOOTCTRL (1) Register Bit Fields for CPU2

(1)

Bit

Name

31-24

Reserved

Reserved

Description

23-16

Reserved

Reserved

15-8

Boot Mode (BMODE)

Boot mode definition when using Get boot
mode option. Refer to Section 3.5 for valid
BMODE values.

7- 0

Key

Write 0x5A to these 8-bits to tell the boot
ROM code that the bits in this register are
valid

Refer to the DCSM chapter for the address of this register location in the user-configurable DCSM OTP.

On this device, the DCSM has two zones. Each zone, Z1 and Z2, has its own copy of the BOOTCTRL
register. The boot ROM is designed to be able to read from either location and uses the procedure in
Figure 3-1 to identify which register to use. By default, if the Z1 BOOTCTRL is programmed, then that
register is given the priority. If the Z1 BOOTCTRL isn’t programmed, then the boot ROM will check if Z2
BOOTCTRL is programmed, if not, then the factory default options are used.
Figure 3-1. Z1 and Z2 BOOTCTRL Selection
Get_mode - Boot Option
Decode Zones selection as below

Z1-BOOTCTRL. OTP_KEY =
0x5A?

3.5

NO

Z2-BOOTCTRL. OTP_KEY =
0x5A?

YES

YES

Use Z1 BOOTCTRL
register

Use Z2 BOOTCTRL
register

NO

Use Factory default
Options

Configuring Get Boot Options
In Get boot mode, the boot ROM reads the boot mode (BMODE) bit field in the BOOTCTRL register to
determine which boot procedure to execute. By default, Get boot mode executes flash boot when in
standalone mode or wait boot when an emulator is connected to the device. Table 3-7 lists the values that
can be set to the BMODE field in BOOTCTRL for CPU1 and the corresponding boot mode that they
represent. Table 3-8 lists the acceptable values for CPU2. For additional details on the GPIOs used for
each boot mode, refer to the Section 3.9.6 section. When debugging the device using an emulator and
EMU_BOOTCTRL, the BMODE field has some additional values which can be found in Section 3.6.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

585

Configuring Emulation Boot Options

www.ti.com

Table 3-7. Get Mode Decoding on CPU1
Key

BMODE Value

Realized Boot Mode

!= 0x5A

Don’t Care

Flash Boot / Wait Boot (1)

0x00

Parallel Boot

0x01

SCI Boot 0

= 0x5A

(1)

0x02

Wait Boot

0x04

SPI Boot 0

0x05

I2C Boot 0

0x07

CAN Boot 0

0x0A

RAM Boot

0x0B

Flash Boot

0x0C

USB Boot

0x81

SCI Boot 1

0x84

SPI Boot 1

0x85

I2C Boot 1

0x87

CAN Boot 1

Other

Flash Boot / Wait Boot (1)

When an emulator is connected (TRSTn = 1) to the device, then an invalid key or invalid boot mode value results in wait boot
mode.

Table 3-8. Get Mode Decoding on CPU2

(1)

3.6

Key

BMODE Value

!= 0x5A

Don’t Care

Realized Boot Mode
Wait Boot

= 0x5A

0x0A

Wait Boot / RAM Boot (1)

0x0B

Flash Boot

Other

Wait Boot

Only after a hibernate reset, CPU2 can boot in RAM boot mode. After any other resets, CPU2 will boot to wait boot.

Configuring Emulation Boot Options
When connected to the device using an emulator, the EMU_BOOTCTRL register is used to determine the
boot mode. This register allows the user to experiment with various boot mode settings before writing to
the BOOTCTRL register in the user-configurable DCSM OTP. The values that can be set in the BMODE
field of the EMU_BOOTCTRL register are listed in Section 3.6. Some notable options include being able
to have emulation boot read from the boot mode select pins, emulate standalone boot using the values in
OTP, and boot according to the Get boot value stored in OTP. Refer to Section 3.9.6 for details on the
GPIOs used in the various boot modes.
Table 3-9. Emulation Boot Options
Key

BMODE Value

Realized Boot Mode

CPU Support

!= 0x5A

Don’t Care

Wait Boot

CPU1 and CPU2

0xFE

Boot as per BMSP0 and
BMSP1

CPU1 Only

0xFF

Emulate Standalone boot

CPU1 and CPU2

0x00

Parallel Boot

CPU1 and CPU2

0x01

SCI Boot 0

CPU1 and CPU2

0x02

Wait Boot

CPU1 and CPU2

0x03

Get Mode( read OTP
BOOTCTRL)

CPU1 and CPU2

0x04

SPI Boot 0

CPU1 and CPU2

0x05

I2C Boot 0

CPU1 and CPU2

= 0x5A

586 ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Configuring Emulation Boot Options

www.ti.com

Table 3-9. Emulation Boot Options (continued)
Key

BMODE Value

Realized Boot Mode

CPU Support

0x07

CAN Boot 0

CPU1 and CPU2

0x0A

RAM Boot

CPU1 and CPU2

0x0B

Flash Boot

CPU1 and CPU2

0x0C

USB Boot

CPU1 Only

0x81

SCI Boot 1

CPU1 Only

0x84

SPI Boot 1

CPU1 Only

0x85

I2C Boot 1

CPU1 Only

0x87

CAN Boot 1

CPU1 Only

Other

Wait Boot

CPU1 and CPU2

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

587

Device Boot Flow Diagrams

3.7

www.ti.com

Device Boot Flow Diagrams
Figure 3-2 shows the device boot flow for CPU1 detailing the actions executed by boot ROM after a reset.
Figure 3-3 shows the device boot flow for CPU2.
Figure 3-2. CPU1 Device Boot Flow
Reset
XRSn/POR/NMIWD

No

No

Hibernate

No

Other Resets

or POR resets

HWBIST
RESET

Yes
Branch to
Application

No

Yes

Yes

Clean up Stack
for Boot ROM

-> PLL power up
-> clock dividers config
-> Flash Power up
->PLL configuration
-> Device Config

-> PLL power up
-> clock dividers config
-> Flash Power up
-> PLL configuration
-> Device Config

DCSM INIT

No
Initialized all
RAMs

M0M1
Retention
ON

Initialized all
RAMs

Yes

Initialized all RAMs
except for M0M1

DCSM INIT
DCSM INIT
Bypass PLL
On a single core device
this has no effect

On a single core
device this has
no effect

Bypass PLL

Bring CPU2 out
of RESET

Bring CPU2 out
of RESET

Call application
IORESTORE
function

On a single
core device this
has no effect

Bring CPU2 out
of RESET
Select Boot
Mode
Valid
Hibernate Boot
Key == 0x5A
TRSTn == 1

Yes

Boot as per
Hibernate Boot
Mode

No

Yes

No

EMU Boot

588

Standalone
Boot

ROM Code and Peripheral Booting

Fall Back to
default Boot

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Device Boot Flow Diagrams

www.ti.com

Figure 3-3. CPU2 Device Boot Flow
Reset
XRSn or POR

Hibernate

Other Resets

No

HWBIST RESET

No

Yes
Yes

Yes

No

M0M1
Retention ON

Yes

Branch to
Application
Initialized all RAMs
except for M0M1

Initialized all RAMs
Initialized all RAMs

Clean up Stack for
Boot ROM

DCSM INIT
Call application
IORESTORE
function

DCSM INIT

Hibernate Boot
Key == 0x5A

Yes

Boot as per
Hibernate Boot

No
Fall Back to default
Boot

Select Boot Mode

TRSTn == 1
No
Yes

EMU Boot

Standalone Boot

3.7.1 Emulation Boot Flow Diagrams
shows the device boot flow for CPU1 when running the device in emulation mode.Figure 3-5 shows the
emulation boot flow for CPU2.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

589

Device Boot Flow Diagrams

www.ti.com

Figure 3-4. CPU1 Emulation Boot Flow
32 bit wide register named EMUBOOTCTRL located at 0xD00
Emulation Boot Mode
No

WAIT BOOT MODE
> Init PIE
> Install C2C1IPC Handler
> Disable WatchDOG

Bits 7:0

EMU_KEY ± Use 0x5A to indicate validity of this location
values.

Bits 15:8

EMU_BMODE - Use this field to define upto 256 boot modes

While(1)

Bits 23:16 EMU_BOOTPIN 0
0-> Pick the default boot pin-0 (GPIO 84)
1 -> Pick GPIO0 as boot pin-0
2 -> Pick GPIO1 as boot pin-0
«.
255 -> Pick GPIO255 as boot pin-0

EMUBOOTCTRL.E
MU_KEY == 0x5A?

Yes

Emulate Standalone
Boot Mode sequence

Go to Stand-Alone
Boot Mode flow

31:24

Yes

EMU_BOOTPIN1
0 -> Pick the default boot pin-1 (GPIO 72)
1 -> Pick GPIO0 as boot pin-1
2 -> Pick GPIO1 as boot pin-1
«.
255 -> Pick GPIO255 as boot pin-1

EMUBOOTCTRL.EMU_
BMODE == 0xFF
Valid
EMUBOOTCTRL.
EMUBOOTPIN0

Read EmuBoot pins
No

Yes

EMUBOOTPIN0 =
GPIO84

NO

Valid
EMUBOOTCTRL.
EMUBOOTPIN1

No

EMUBOOTPIN1 =
GPIO72

Yes

EMUBOOTCTRL.EMU
_BMODE == 0xFE
Yes

EMUBOOTPIN1 =
EMUBOOTCTRL.EM
UBOOTPIN1

EMUBOOTPIN0 =
EMUBOOTCTRL.EM
UBOOTPIN0

BootMode =
(*EMUBOOTPIN1 << 1) |
(*EMUBOOTPIN0)

No
-----------------------------------------------------------------------------------------------EMU_BMODE Value | Realized Boot Mode
-----------------------------------------------------------------------------------------------0x00
Parallel Boot
0x01
SCIBOOT(0)
0x02
WAIT BOOT
0x03
GET MODE (OTP)
0x04
SPIBOOT(0)
0x05
I2CBOOT(0)
0x07
CANBOOT(0)
0x0A
RAMBOOT
0x0B
FLASHBOOT
0x0C
USB BOOT
0x81
SCIBOOT(1) ± Alternate IO
0x84
SPIBOOT(1)- Alternate IO
0x85
I2CBOOT(1) ± Alternate IO
0x87
CANBOOT(1) ± Alternate IO
0x47
CANBOOT(TEST)(0) ± TESTMODE
0xC7
CANBOOT(TEST)(1) ± TEESTMODE, Alternate
IO
Other
WAIT BOOT

590

ROM Code and Peripheral Booting

Boot Mode = 0 -> Parallel Boot Mode
Boot Mode = 1 -> SCIBOOT Mode
Boot Mode = 2 -> WAIT BOOT Mode
Boot Mode = 3 -> GET MODE (read OTP Boot
Mode values)

Is Get Mode
No

Yes

Start Boot LOAD

Get Mode

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Device Boot Flow Diagrams

www.ti.com

Figure 3-5. CPU2 Emulation Boot Flow

32 bit wide register named EMUBOOTCTRL located at 0xD00
Bits 7:0

EMU_KEY - Use 0x5A to indicate validity of this location
values.

Bits 15:8

EMU_BMODE - Use this field to define upto 256 boot modes

Bits 31:16

RESERVED

A

GET MODE

B
No

Emu Boot

EMUKEY == 0x5A

Yes

----------------------------------------------------------------------------------------------EMU_BMODE Value | Realized Boot Mode
----------------------------------------------------------------------------------------------0x00
Parallel Boot
0x01
SCIBOOT
0x02
WAIT BOOT
0x03
GET MODE (OTP)
0x04
SPIBOOT
0x05
I2CBOOT
0x07
CANBOOT
FLASHBOOT
0x0
Other
WAIT BOOT

3.7.2 Standalone and Hibernate Boot Flow Diagrams
Figure 3-6 shows the device boot flow for CPU1 when running the device in standalone boot mode or
when booting from hibernate. Figure 3-7 shows the standalone boot flow and hibernate boot flow for
CPU2.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

591

Device Boot Flow Diagrams

www.ti.com

Figure 3-6. CPU1 Standalone and Hibernate Boot Flow
Findout which boot
pins to read ± user
configured or Factory
default

Stand Alone Boot

ZxBOOTCTRL.OTP_K
EY == 0x5A

No

BOOTPIN0 =
GPIO84
BOOTPIN1 =
GPIO72

32 bit wide register named Zx-BOOTCTRL located at 0x7801E for Zone1 and 0x7821E for Zone 2
Bits 7:0

OTP_KEY ± Use 0x5A to indicate validity of this location
values.

Yes
Bits 15:8
BOOTPIN0 =
ZxBOOTCTRL.OTPBOO
TPIN0

ZxBOOTCTRL.OTP_BO
OTPIN0 is valid?

31:24

OTP_BOOTPIN1
0 -> Pick the default boot pin-1 (GPIO 72)
1 -> Pick GPIO0 as boot pin-1
2 -> Pick GPIO1 as boot pin-1
«.
255 -> Pick GPIO255 as boot pin-1

No

BOOTPIN1 =
ZxBOOTCTRL.OTPBOO
TPIN1

Yes

ZxBOOTCTRL.OTP
_BOOTPIN1 is
valid?

OTP_BMODE - Use this field to define upto 256 boot modes

Bits 23:16 OTP_BOOTPIN 0
0-> Pick the default boot pin-0 (GPIO 84)
1 -> Pick GPIO0 as boot pin-0
2 -> Pick GPIO1 as boot pin-0
«.
255 -> Pick GPIO255 as boot pin-0

Yes

BOOTPIN0 =
GPIO84

No
BootMode =
(*BOOTPIN1 <<
1)|(*BOOTPIN0)

BOOTPIN0 =
GPIO72

Yes

GET MODE

Boot Mode = 0 -> Parallel Boot Mode
Boot Mode = 1 -> SCIBOOT Mode
Boot Mode = 2 -> WAIT BOOT Mode
Boot Mode = 3 -> GET MODE (read OTP Boot
Mode values)

Start boot LOAD

Hibernate Boot
GET MODE (boot Mode)

ZxBOOTCTRL.OTP
_KEY == 0x5A

Yes

No
Is Get Mode

Boot to Flash
Enable Watchdog

No

592

ROM Code and Peripheral Booting

BootMode = ZxOTPBOOTCTRL.OT
P_BMODE

-----------------------------------------------------------------------------------------------BootMode Value | Realized Boot Mode
-----------------------------------------------------------------------------------------------0x00
Parallel Boot
0x01
SCIBOOT(0)
0x02
WAIT BOOT
0x04
SPIBOOT(0)
0x05
I2CBOOT(0)
0x07
CANBOOT(0)
0x0A
RAMBOOT
0x0B
FLASHBOOT
0x0C
USB BOOT
0x81
SCIBOOT(1) ± Alternate IO
0x84
SPIBOOT(1)- Alternate IO
0x85
I2CBOOT(1) ± Alternate IO
0x87
CANBOOT(1) ± Alternate IO
0x47
CANBOOT(TEST)(0) ± TESTMODE
0xC7
CANBOOT(TEST)(1) ± TEESTMODE, Alternate IO
Other
FLASHBOOT (if stand Alone) EMUBOOT (if CCS connected)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Device Reset and Exception Handling

www.ti.com

Figure 3-7. CPU2 Standalone and Hibernate Boot Flow

32 bit wide register named EMUBOOTCTRL located at 0xD00
Bits 7:0

EMU_KEY - Use 0x5A to indicate validity of this location
values.

Bits 15:8

EMU_BMODE - Use this field to define upto 256 boot modes

Bits 31:16

RESERVED

A

GET MODE

B
No

Emu Boot

3.8

EMUKEY == 0x5A

Yes

----------------------------------------------------------------------------------------------EMU_BMODE Value | Realized Boot Mode
----------------------------------------------------------------------------------------------0x00
Parallel Boot
0x01
SCIBOOT
0x02
WAIT BOOT
0x03
GET MODE (OTP)
0x04
SPIBOOT
0x05
I2CBOOT
0x07
CANBOOT
FLASHBOOT
0x0
Other
WAIT BOOT

Device Reset and Exception Handling

3.8.1 Reset Causes and Handling
This section explains the actions boot ROM performs upon reset after checking the reset cause.
Table 3-10. Boot ROM Reset Causes and Actions
Reset Source
POR

XRS

CPU1 Boot ROM Action
Adjust clock divider to /1

2.

Device configuration

1.

RAM Initialization

3.

RAM initialization

2.

Continue default boot flow

4.

Continue default boot flow

1.

Adjust clock divider to /1

2.

Device configuration

1.

RAM Initialization

3.

RAM initialization

2.

Continue default boot flow

4.

Continue default boot flow

HWBIST

Branch to application code

Hibernate

1.

Adjust clock divider to /1

2.

Device configuration

3. RAM initialization (Either all RAMS
except for M0M1 or all RAMS)
WDRS (CPU1)

CPU2 Boot ROM Action

1.

Branch to application code
1. RAM initialization (Either all RAMS
except for M0M1 or all RAMS)
2.

Continue default boot flow

4.

Continue default boot flow

1.

Adjust clock divider to /1

2.

Device configuration

1.

RAM initialization

3.

RAM initialization

2.

Continue default boot flow

4.

Continue default boot flow

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

593

Device Reset and Exception Handling

www.ti.com

Table 3-10. Boot ROM Reset Causes and Actions (continued)
Reset Source

CPU1 Boot ROM Action

WDRS (CPU2)

Exception handled by CPU1

NMIWDRS (CPU1)

1.

Adjust clock divider to /1

2.
3.
4.

Continue default boot flow

NMIWDRS (CPU2)

CPU2 Boot ROM Action
1.

Clear boot stack

2.

Continue default boot flow

Device configuration

1.

RAM initialization

RAM initialization

2.

Continue default boot flow

1.

Clear boot stack

2.

Continue default boot flow

Exception handled by CPU1

Debugger (CPU1)

1.

Clear boot stack

2.

Continue default boot flow

No Action

Debugger (CPU2)

Exception handled by CPU1

SCCRESET (CPU1)

1.

Clear boot stack

2.

Continue default boot flow

SCCRESET (CPU2)

1.

Clear boot stack

2.

Continue default boot flow

No Action

Exception handled by CPU1

1.

Clear boot stack

2.

Continue default boot flow

3.8.2 Exceptions and Interrupts Handling
This section explains the actions boot ROM performs if any exceptions that can occur happen during boot.
Table 3-11. Boot ROM Exceptions and Actions
Exception Event Source

3.9

CPU1 Boot ROM Action

CPU2 Boot ROM Action

Event Logged

Single-bit error in FUSEERR

Ignore and continue to boot

Ignore and continue to boot

No

Multi-bit error in FUSEERR

Reset the device

No action required

No

Clock fail condition detected

Clear the NMI and continue to
boot

Clear the NMI and continue to
boot

Yes

Double-bit ECC error from
RAM

Reset the device

Send IPC to CPU1, clear NMI
flag, and wait forever

Yes

Double-bit error from Flash

Reset the device

Send IPC to CPU1, clear NMI
flag, and wait forever

Yes

PIE Vector Error

Ignore and continue to boot

Ignore and continue to boot

Yes

HWBIST Error

Ignore and continue to boot

Send IPC to CPU1, clear NMI
flag, and wait forever

Yes

ITRAP Exception

Provide ROM location where it
will loop

Provide ROM location to CPU1
of where it will loop

Yes

CPU2 NMIWDRST

Ignore and continue to boot

No action required

Yes

CPU2 WDRST

Ignore and continue to boot

No action required

Yes

Any spurious PIE interrupt
occurs

Acknowledge interrupt and
continue to boot

Send IPC to CPU1 and
acknowledge interrupt

No

Boot ROM Description
This section explains the details regarding the device boot ROM.

3.9.1 Entry Points
This section gives details about the entry point addresses for various boot modes. These entry points tell
the boot ROM where to branch to at the end of booting as per the selected boot mode.

594

ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Table 3-12. Entry Point Addresses for CPU1 and CPU2
Entry Point

Address

RAM

0x0000 0000

Flash

0x0008 0000

3.9.2 Wait Points
During boot ROM execution, there are situations where the CPU may enter a wait loop in the code. This
state can occur for a variety of reasons.
Table 3-13 details the address ranges that the CPU1 PC register value will fall between if it has entered
one of these instances. Table 3-14 details the addresses for CPU2.
Table 3-13. Wait Point Addresses for CPU1
Address Range

Description

0x003FE2D4 – 0x003FE2EF

In Wait Boot

0x003FE73E – 0x003FE824

In NMI Handler (startup)

0x003FE35A – 0x003FE468

In NMI Handler (PIE)

0x003FE468 – 0x003FE495

In ITRAP ISR

Table 3-14. Wait Point Addresses for CPU2
Address Range

Description

0x003FE44C – 0x003FE451

In Idle Mode

0x003FDEAA – 0x003FDFC2

In NMI Handler

0x003FDE61 – 0x003FDEAA

In PIE Vector Mismatch Handler

0x003FDFC2 – 0x003FE00B

In ITRAP ISR

3.9.3 Memory Maps
This section details the ROM memory maps.
3.9.3.1

CPU1 Boot ROM Memory Map
Table 3-15. CPU1 Boot ROM Memory Map

3.9.3.2

Memory

Start Address

End Address

Length

ROM Signature

0x003F 8000

0x003F 8001

0x0002

TI-RTOS (ROM)

0x003F 8002

0x003F 9E0F

0x1E0E

PLC Tables 1

0x003F 9E10

0x003F D817

0x3A08

PLC Tables 2

0x003F D818

0x003F DE17

0x0600

Boot

0x003F DE18

0x003F FF31

0x211A

CRC Table

0x003F FF32

0x003F FF39

0x0008

BIST Signature

0x003F FF3A

0x003F FF79

0x0040

Version

0x003F FF7A

0x003F FF7B

0x0002

Checksum

0x003F FF7C

0x003F FFBD

0x0042

Vectors

0x003F FFBE

0x003F FFFF

0x0042

TI-RTOS (Flash)

0x0008 2000

0x0008 3FFF

0x2000

CPU2 Boot ROM Memory Map

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

595

Boot ROM Description

www.ti.com

Table 3-16. CPU2 Boot ROM Memory Map

3.9.3.3

Memory

Start Address

End Address

ROM Signature

0x003F 8000

0x003F 8001

Length
0x0002

TI-RTOS (ROM)

0x003F 8002

0x003F 9E0F

0x1E0E
0x3A08

PLC Tables 1

0x003F 9E10

0x003F D817

PLC Tables 2

0x003F D818

0x003F DE17

0x0600

Boot

0x003F DE18

0x003F FF31

0x211A

CRC Table

0x003F FF32

0x003F FF39

0x0008

BIST Signature

0x003F FF3A

0x003F FF79

0x0040

Version

0x003F FF7A

0x003F FF7B

0x0002

Checksum

0x003F FF7C

0x003F FFBD

0x0042

Vectors

0x003F FFBE

0x003F FFFF

0x0042

TI-RTOS (Flash)

0x0008 2000

0x0008 3FFF

0x2000

CLA Data ROM Memory Map
Table 3-17. CLA Data ROM Memory Map

596

Memory

Start Address

End Address

FFT Tables (Load)

0x0100 1070

0x0100 186F

0x0800

Data (Load)

0x0100 1870

0x0100 1FF9

0x078A

Version (Load)

0x0100 1FFA

0x0100 1FFF

0x0006

ROM Code and Peripheral Booting

Length

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

3.9.3.4

Reserved RAM and Flash Memory Map
Table 3-18. Reserved RAM and Flash Memory Map for CPU1
Memory

Description

Start Address

End Address

Length

RAM

Boot ROM

0x0000 0002

0x0000 0121

0x0120

(1)

0x0000 0780

0x0000 07FF

0x0080

0x0008 2000

0x0008 2823

0x0824

TI-RTOS

TI-RTOS (1) (2)

Flash
(1)
(2)

If the user is not planning on using TI-RTOS in ROM, then these memory locations are free to be used by the application.
For using the TI-RTOS in flash sector A, TI recommends that this sector be made unsecure, or at minimum, the sector should be
verified that there is no secure zone claiming this sector.

Table 3-19. Reserved RAM and Flash Memory Map for CPU2
Memory

Description

Start Address

End Address

Length

RAM

Boot ROM

0x0000 0002

0x0000 00A1

0x00A0

TI-RTOS (1)

0x0000 0780

0x0000 07FF

0x0080

0x0008 2000

0x0008 2823

0x0824

Flash
(1)
(2)

3.9.3.5

TI-RTOS

(1) (2)

If the user is not planning to use TI-RTOS in ROM, then these memory locations are free to be used by the application.
For using the TI-RTOS in flash sector A, TI recommends that this sector be made unsecure, or at minimum, the sector should be
verified that there is no secure zone claiming this sector.

ROM Tables

This section details the boot ROM and CLA ROM symbol tables.
3.9.3.5.1 Boot ROM Tables
The boot ROM symbols and their addresses can be located in the .map file that is included with the
released boot ROM source and header code. Within the .map file, locate the Global Symbols category to
get a list of the boot ROM symbols and addresses present.
3.9.3.5.2 CLA ROM Tables
Table 3-20. CLA Data ROM Tables
Start Address From CLA in Hex

Start Address From CPU in Hex

_CLAatan2HalfPITable

F870

01001870

_CLAINV2PI

F874

01001874

_CLAatan2Table

F876

01001876

_CLAasinHalfPITable

F9fc

010019fc

_CLAatan2TableEnd

F9fc

010019fc

_CLAasinTable

Fa00

01001a00

_CLAacosinHalfPITable

Fb86

01001b86

_CLAasinTableEnd

Fb86

01001b86

_CLAacosinTable

Fb8a

01001b8a

_CLAacosinTableEnd

Fd0a

01001d0a

_CLAsinTable

Fd0a

01001d0a

_CLAsincosTable

Fd0a

01001d0a

_CLAsincosTable_Sin0

Fd0a

01001d0a

_CLAcosTable

Fd4a

01001d4a

_CLAsincosTable_Cos0

Fd4a

01001d4a

_CLAsinTableEnd

Fe0a

01001e0a

_CLAcosTableEnd

Fe4c

01001e4c

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting 597

Boot ROM Description

www.ti.com

Table 3-20. CLA Data ROM Tables (continued)
Start Address From CLA in Hex

Start Address From CPU in Hex

_CLAsincosTable_TABLE_SIZE

Fe4c

01001e4c

_CLAsincosTable_TABLE_SIZEDivTwoPi

Fe4e

01001e4e

_CLAsincosTable_TwoPiDivTABLE_SIZE

Fe50

01001e50

_CLAsincosTable_TABLE_MASK

Fe52

01001e52

_CLAsincosTable_Coef0

Fe54

01001e54

_CLAsincosTable_Coef1

Fe56

01001e56

_CLAsincosTable_Coef1_pos

Fe58

01001e58

_CLAsincosTable_Coef2

Fe5a

01001e5a

_CLAsincosTable_Coef3

Fe5c

01001e5c

_CLAsincosTable_Coef3_neg

Fe5e

01001e5e

_CLALNV2

Fe60

01001e60

_CLAsincosTableEnd

Fe60

01001e60

_CLALNVe

Fe62

01001e62

_CLALNV10

Fe64

01001e64

_CLABIAS

Fe66

01001e66

_CLALN_TABLE_MASK1

Fe68

01001e68

_CLALN_TABLE_MASK2

Fe6a

01001e6a

_CLALnTable

Fe6c

01001e6c

_CLAINV1

Ff32

01001f32

_CLALnTableEnd

Ff32

01001f32

_CLAINV2

Ff34

01001f34

_CLAINV3

Ff36

01001f36

_CLAINV4

Ff38

01001f38

_CLAINV5

Ff3a

01001f3a

_CLAINV6

Ff3c

01001f3c

_CLAINV7

Ff3e

01001f3e

_CLALOG10

Ff40

01001f40

_CLAExpTable

Ff42

01001f42

_CLAExpTableEnd
CROM VERSION

Fff4

01001ff4

FFFA

01001FFA (2 16-bit words)
.word 0x0100
; Boot ROM
Version v1.0
.word 0x0413
; Month/Year:
(ex: 0x0109 = 1/09 = Jan 2009)

3.9.4 Boot Modes
The available boot modes supported on this device are detailed in this section. Each boot mode allows for
various options, providing configurations with different IOs to be used, depending on the application.
3.9.4.1

Wait Boot Mode

The wait boot mode puts the CPU in a loop and does not branch to the user application code. The device
can enter wait boot mode either manually or because an error occurred during boot up. TI recommends
using wait boot when using a debugger to avoid any JTAG complications.
Actions resulting in entering wait boot mode:
• Wait boot is set by the user as the boot mode
• The boot mode is unrecognized and a debugger is connected to the device
• The emulation BOOCTRL key is not equal to 0xA5 or 0x5A
598

ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

•

3.9.4.2

An error occurs during emulation boot and the boot mode pins are decoded with a value not
recognized as a valid boot mode
SCI Boot Mode

The SCI boot mode asynchronously transfers code from SCI-A to internal memory. This boot mode only
supports an incoming 8-bit data stream and follows the data flow as outlined in Example 3-1.
Figure 3-8. Overview of SCI Bootloader Operation
Control
Subsystem
boot ROM

SCIRXDA
SCITXDA

Host
(Data and program
source)

The device communicates with the external host by communication through the SCI-A peripheral. The
autobaud feature of the SCI port is used to lock baud rates with the host. For this reason the SCI loader is
very flexible and you can use a number of different baud rates to communicate with the device.
After each data transfer, the bootloader will echo back the 8-bit character received to the host. This allows
the host to check that each character was received by the bootloader.
At higher baud rates, the slew rate of the incoming data bits can be affected by transceiver and connector
performance. While normal serial communications may work well, this slew rate may limit reliable autobaud detection at higher baud rates (typically beyond 100kbaud) and cause the auto-baud lock feature to
fail. To avoid this, the following is recommended:
1. Achieve a baud-lock between the host and SCI bootloader using a lower baud rate.
2. Load the incoming application or custom loader at this lower baud rate.
3. The host may then handshake with the loaded application to set the SCI baud rate register to the
desired high baud rate.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

599

Boot ROM Description

www.ti.com

Figure 3-9. Overview of SCI Boot Function
SCI_Boot

Enable the SCI-A clock
set the LSPCLK to /4

Echo autobaud character

Enable the SCIA TX and RX pin
functionality and pullups on
TX and RX

Read KeyValue

Valid
KeyValue
(0x08AA)
?

Setup SCI-A for
1 stop, 8-bit character,
no parity, use internal
SC clock, no loopback,
disable Rx/Tx interrupts

Jump to Flash

Yes

Disable SCI FIFOs

Read and discard 8
reserved words

Prime SCI-A baud register

Read EntryPoint address

Enable autobaud detection

Read data in the standard
boot stream format

No

Autobaud
lock
?
Return
EntryPoint

Yes

3.9.4.3

No

SPI Boot Mode

The SPI loader expects an SPI-compatible 16-bit or 24-bit addressable serial EEPROM or serial flash
device to be present on the SPI-A pins as indicated in Figure 3-10. The SPI bootloader supports an 8-bit
data stream. It does not support a 16-bit data stream.
Figure 3-10. SPI Loader

SPIA_SIMO
Control
subsystem

SPIA_SOMI
SPIA_CLK
SPIA_STE

Serial SPI
EEPROM
DIN
DOUT
CLK
CS

The SPI boot ROM loader initializes the SPI module to interface to a serial SPI EEPROM or flash. Devices
of this type include, but are not limited to, the Xicor X25320 (4Kx8) and Xicor X25256 (32Kx8) SPI serial
SPI EEPROMs and the Atmel AT25F1024A serial flash.
600

ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

The SPI boot ROM loader initializes the SPI with the following settings: FIFO enabled, 8-bit character,
internal SPICLK master mode and talk mode, clock phase = 1, polarity = 0, using the slowest baud rate.
If the download is to be performed from an SPI port on another device, then that device must be setup to
operate in the slave mode and mimic a serial SPI EEPROM. Immediately after entering the SPI_Boot
function, the pin functions for the SPI pins are set to primary and the SPI is initialized. The initialization is
done at the slowest speed possible. Once the SPI is initialized and the key value read, you could specify a
change in baud rate or low speed peripheral clock.
Table 3-21. SPI 8-Bit Data Stream
Byte

Contents

1

LSB: AA (KeyValue for memory width = 8-bits)

2

MSB: 08h (KeyValue for memory width = 8-bits)

3

LSB: LOSPCP

4

MSB: SPIBRR

5

LSB: reserved for future use

6

MSB: reserved for future use

...
...

...
Data for this section.
...

17

LSB: reserved for future use

18

MSB: reserved for future use

19

LSB: Upper half (MSW) of Entry point PC[23:16]

20

MSB: Upper half (MSW) of Entry point PC[31:24] (Note: Always 0x00)

21

LSB: Lower half (LSW) of Entry point PC[7:0]

22

MSB: Lower half (LSW) of Entry point PC[15:8]

...
...

....
Data for this section.
...

...

Blocks of data in the format size/destination address/data as shown in the generic
data stream description

...
...

...
Data for this section.
...

n

LSB: 00h

n+1

MSB: 00h - indicates the end of the source

The data transfer is done in "burst" mode from the serial SPI EEPROM. The transfer is carried out entirely
in byte mode (SPI at 8 bits/character). A step-by-step description of the sequence follows:
Step 1. The SPI-A port is initialized
Step 2. The GPIO19 (SPISTE) pin is used as a chip-select for the serial SPI EEPROM or flash
Step 3. The SPI-A outputs a read command for the serial SPI EEPROM or flash
Step 4. The SPI-A sends the serial SPI EEPROM an address 0x0000; that is, the host requires that
the EEPROM or flash must have the downloadable packet starting at address 0x0000 in the
EEPROM or flash. The loader is compatible with both 16-bit addresses and 24-bit addresses.
Step 5. The next word fetched must match the key value for an 8-bit data stream (0x08AA). The least
significant byte of this word is the byte read first and the most significant byte is the next byte
fetched. This is true of all word transfers on the SPI. If the key value does not match, then the
load is aborted and the bootloader jumps to flash.
Step 6. The next 2 bytes fetched can be used to change the value of the low speed peripheral clock
register (LOSPCP) and the SPI baud rate register (SPIBRR). The first byte read is the
LOSPCP value and the second byte read is the SPIBRR value. The next 7 words are
reserved for future enhancements. The SPI bootloader reads these 7 words and discards
them.
Step 7. The next two words makeup the 32-bit entry point address where execution will continue after
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

601

Boot ROM Description

Step 8.

www.ti.com

the boot load process is complete. This is typically the entry point for the program being
downloaded through the SPI port.
Multiple blocks of code and data are then copied into memory from the external serial SPI
EEPROM through the SPI port. The blocks of code are organized in the standard data stream
structure presented earlier. This is done until a block size of 0x0000 is encountered. At that
point in time the entry point address is returned to the calling routine that then exits the
bootloader and resumes execution at the address specified.
Figure 3-11. Data Transfer From EEPROM Flow
SPI_Boot

Enable the SPI-A clock
Set the LSPCLK to 4

Valid
KeyValue
(0x08AA)
?

Enable SPISIMOA,
SPISOMI and SPICLKA
pin functionality and enable
pullups on those pins

No

Jump to Flash

Yes
Read LOSPCP value

Change LOSPCP

Read SPIBRR value

Change SPIBRR

Set up SPI-A for
8-bit character,
Use internal SPI clock,
master mode
Use slowest baud rate (0x7F)
Relinquish SPI-A from reset

Set chip enable high
(GPIO19)

3.9.4.4

Enable EEPROM
Send read command and
start at EEPROM address
0x0000

Read and discard 7
reserved words

Read KeyValue

Read EntryPoint
address

Call CopyData

Return
EntryPoint

I2C Boot Mode

The I2C bootloader expects an 8-bit wide I2C-compatible EEPROM device to be present at address 0x50
on the I2C-A bus as indicated in Figure 3-12. The EEPROM must adhere to conventional I2C EEPROM
protocol, as described in this section, with a 16-bit base address architecture.
Figure 3-12. EEPROM Device at Address 0x50
SDA

Control
subsystem

SCL

I2CA_SDA
I2CA_SCL
SDA
SCL

602

ROM Code and Peripheral Booting

I2C
EEPROM
Slave Address
0x50

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

If the download is to be performed from a device other than an EEPROM, then that device must be set up
to operate in the slave mode and mimic the I2C EEPROM. Immediately after entering the I2C boot
function, the GPIO pins are configured for I2C-A operation and the I2C is initialized. The following
requirements must be met when booting from the I2C module:
• The input frequency to the device must be in the appropriate range.
• The EEPROM must be at slave address 0x50.
Figure 3-13. Overview of I2C Boot Function

NACK
received
?

I2C_Boot

Enable I2CA_SDA and
I2CA_SCL pins
Enable pullups on
I2CA_SDA and I2CA_SCL

Yes
Jump to Flash

No
Read KeyValue

Enable I2C-A clock
Valid
KeyValue
(0x08AA)
?

Set slave address 0x50
I2C prescaler I2CPSC = or 0

No

Yes

100-kHz bit rate

Read I2CPSC value
Read I2CCLKH value
Read 12CCLKL value

Enable TX/RX FIFOs to
receive 2 bytes.

Place I2C in master
transmitter mode
Set EEPROM address
pointer to 0x0000

Jump to Flash

Put 12c-A in Reset
Set I2CPSC value
Set I2CCLKH value
Set I2CCLKL value
Bring I2C-A out of Reset

Read and discard 5
reserved words

Read EntryPoint
address
Read data in standard
boot stream format
Return
EntryPoint

The bit-period prescalers (I2CCLKH and I2CCLKL) are configured by the bootloader to run the I2C at a 50
percent duty cycle at 100-kHz bit rate (standard I2C mode) when the system clock is 10 MHz. These
registers can be modified after receiving the first few bytes from the EEPROM. This allows the
communication to be increased up to a 400-kHz bit rate (fast I2C mode) during the remaining data reads.
Arbitration, bus busy, and slave signals are not checked. Therefore, no other master is allowed to control
the bus during this initialization phase. If the application requires another master during I2C boot mode,
that master must be configured to hold off sending any I2C messages until the application software
signals that it is past the bootloader portion of initialization.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

603

Boot ROM Description

www.ti.com

The non-acknowledgment bit is checked only during the first message sent to initialize the EEPROM base
address. This is to make sure that an EEPROM is present at address 0x50 before continuing. If an
EEPROM is not present, the non-acknowledgment bit is not checked during the address phase of the data
read messages (I2C_Get Word). If a non acknowledgment is received during the data read messages, the
I2C bus will hang. Table 14-1 shows the 8-bit data stream used by the I2C.
Table 3-22. I2C 8-Bit Data Stream
Byte

Contents

1

LSB: AA (KeyValue for memory width = 8 bits)

2

MSB: 08h (KeyValue for memory width = 8 bits)

3

LSB: I2CPSC[7:0]

4

reserved

5

LSB: I2CCLKH[7:0]

6

MSB: I2CCLKH[15:8]

7

LSB: I2CCLKL[7:0]

8

MSB: I2CCLKL[15:8]

...
...

...
Data for this section.
...

17

LSB: Reserved for future use

18

MSB: Reserved for future use

19

LSB: Upper half of entry point PC

20

MSB: Upper half of entry point PC[22:16] (Note: Always 0x00)

21

LSB: Lower half of entry point PC[15:8]

22

MSB: Lower half of entry point PC[7:0]

...
...

...
Data for this section.
...
Blocks of data in the format size/destination address/data as shown in the generic data stream
description.

...
...

...
Data for this section.
...

n

LSB: 00h

n+1

MSB: 00h - indicates the end of the source

The I2C EEPROM protocol required by the I2C bootloader is shown in Figure 3-14 and Figure 3-15. The
first communication, which sets the EEPROM address pointer to 0x0000 and reads the KeyValue
(0x08AA) from it, is shown in Figure 3-14. All subsequent reads are shown in Figure 3-15 and are read
two bytes at a time.

SDA LINE

Address
Pointer, MSB

ROM Code and Peripheral Booting

Address
Pointer, LSB

STOP

NO ACK

ACK

LSB
READ
ACK

MSB

RESTART

ACK

1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00

Device
Address

604

ACK

LSB
WRITE
ACK

MSB

START

Figure 3-14. Random Read

1 01 0 0 0 0 1 0

Device
Address

DATA BYTE 1

DATA BYTE 2

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

SDA LINE

STOP

NO ACK

1 01 0 0 0 0 1 0

Device
Address

3.9.4.5

ACK

READ
ACK

START

Figure 3-15. Sequential Read

DATA BYTE n

DATA BYTE n+1

Parallel Boot Mode

The parallel general purpose I/O (GPIO) boot mode asynchronously transfers code from GPIO58 GPIO63, GPIO64-GPIO65 to internal memory. Each value is 8 bits long and follows the same data flow as
outlined in Figure 3-16.
Figure 3-16. Overview of Parallel GPIO Bootloader Operation
28x control − GPIO69
Host control − GPIO70

boot ROM

8

Host
(data and program
source)

Data GP I/O port GPIO[63-58, 64, 65]

The control subsystem communicates with the external host device by polling/driving the GPIO70 and
GPIO69 lines. The handshake protocol shown in Figure 3-17 must be used to successfully transfer each
word via GPIO [63-58,64,65]. This protocol is very robust and allows for a slower or faster host to
communicate with the master subsystem.
Two consecutive 8-bit words are read to form a single 16-bit word. The most significant byte (MSB) is read
first followed by the least significant byte (LSB). In this case, data is read from GPIO[63-58,64,65].
The 8-bit data stream is shown in Table 3-23.
Table 3-23. Parallel GPIO Boot 8-Bit Data Stream
Bytes

GPIO[63:58,64,
65]
(Byte 1 of 2)

GPIO[63:58,64,
65]
(Byte 2 of 2)

Description

1

2

AA

08

0x08AA (KeyValue for memory width = 16 bits)

3

4

00

00

8 reserved words (words 2 - 9)

...

...

...

...

...

17

18

00

00

Last reserved word

19

20

BB

00

Entry point PC[22:16]

21

22

DD

CC

Entry point PC[15:0] (PC = 0x00BBCCDD)

23

24

NN

MM

Block size of the first block of data to load = 0xMMNN words

25

26

BB

AA

Destination address of first block Addr[31:16]

27

28

DD

CC

Destination address of first block Addr[15:0] (Addr = 0xAABBCCDD)

29

30

BB

AA

First word of the first block in the source being loaded = 0xAABB

...
...

...
Data for this section.
...

.

BB

AA

Last word of the first block of the source being loaded = 0xAABB

.

NN

MM

Block size of the 2nd block to load = 0xMMNN words

.

BB

AA

Destination address of second block Addr[31:16]

.

DD

CC

Destination address of second block Addr[15:0]

.

BB

AA

First word of the second block in the source being loaded

.

…

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting 605

Boot ROM Description

www.ti.com

Table 3-23. Parallel GPIO Boot 8-Bit Data Stream (continued)
Bytes

GPIO[63:58,64,
65]
(Byte 1 of 2)

GPIO[63:58,64,
65]
(Byte 2 of 2)

Description

n

n+1

BB

AA

Last word of the last block of the source being loaded
(More sections if required)

n+2

n+3

00

00

Block size of 0000h - indicates end of the source program

The device first signals the host that it is ready to begin data transfer by pulling the GPIO69 pin low. The
host load then initiates the data transfer by pulling the GPIO70 pin low. The complete protocol is shown in
Figure 3-17:
Figure 3-17. Parallel GPIO Bootloader Handshake Protocol
1

2

3

4

5

6

Host control
GPIO70
Device control
GPIO69

1. The device indicates it is ready to start receiving data by pulling the GPIO69 pin low.
2. The bootloader waits until the host puts data on GPIO [63-58,64,65]. The host signals to the device
that data is ready by pulling the GPIO70 pin low.
3. The device reads the data and signals the host that the read is complete by pulling GPIO69 high.
4. The bootloader waits until the host acknowledges the device by pulling GPIO70 high.
5. The device again indicates it is ready for more data by pulling the GPIO69 pin low.
This process is repeated for each data value to be sent.
Figure 3-18 shows an overview of the Parallel GPIO bootloader flow.
Figure 3-18. Parallel GPIO Mode Overview
Parallel_Boot

Read and discard 8
reserved words

Initialize GP I/O MUX
and Dir registers
GPIO[63-58,64,65] = input
GPIO70 = input
GPIO69 = output
Enable pullups on
GPIO[63-58,64,65]

Read EntryPoint
address

Call
CopyData
No
Return Flash EntryPoint

Valid
KeyValue
(0x08AA)
?
Return
EntryPoint

Yes

606

ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Figure 3-19 shows the transfer flow from the host side. The operating speed of the CPU and host are not
critical in this mode as the host will wait for the device and the device will in turn wait for the host. In this
manner the protocol will work with both a host running faster and a host running slower than the device.
Figure 3-19. Parallel GPIO Mode - Host Transfer Flow
Start transfer

No

Device ready
(GPIO69=0)

?

Yes
Load GPIO[63-58,64,65] with data

No

Device ack
(GPIO69=1)

?

Yes
Signal that data
is ready
(GPIO70=0)

Acknowledge device
(GPIO70=1)

More
data
?

Yes

No
End transfer

Figure 3-20 shows the flow used to read a single word of data from the parallel port.
• 8-bit data stream
The 8-bit routine, shown in Figure 3-20, discards the upper 8 bits of the first read from the port and
treats the lower 8 bits masked with GPIO65 in bit position 7 and GPIO64 in bit position 6 as the least
significant byte (LSB) of the word to be fetched. The routine will then perform a second read to fetch
the most significant byte (MSB). The routine will then perform a second read to fetch the most
significant byte (MSB). It then combines the MSB and LSB into a single 16-bit value to be passed back
to the calling routine.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

607

Boot ROM Description

www.ti.com

Figure 3-20. 8-Bit Parallel GetWord Function
Parallel_GetWordData
8 bit

A

Signal host that device is ready
(GPIO69 = 0)

Data
ready
(GPIO70 = 0)
?

No

Signal host that device
is ready to read MSB
(GPIO69 = 0)

Data
ready
(GPIO70 = 0)
?

Yes

No

Yes

Read word of data
from GPIO[63-58,64,65]

Read GPIO for LSB and
MSB of 16-bit data

Device ack read complete
(GPIO69 = 1)
Device ack read complete
(GPIO69 = 1)
Host
ack
(GPIO70 = 1)
?
Yes

No
Host
ack
(GPIO70 = 1)
?

No

Yes
WordData = MSB:LSB
A
Return WordData

3.9.4.6

CAN Boot Mode

The CAN bootloader asynchronously transfers code from CAN-A to internal memory. The host can be any
CAN node. The communication is first done with 11-bit standard identifiers (with a MSGID of 0x1) using
two bytes per data frame. The host can download a kernel to reconfigure the CAN if higher data
throughput is desired.

608

ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Figure 3-21. Overview of CAN-A Bootloader Operation

CAN bus

28x

CAN
host

28x

The bit timing registers are programmed in such a way that a 100 kbps bit rate is achieved with a 20 MHz
external oscillator, a shown in Table 3-24.
Table 3-24. Bit-Rate Value for Internal Oscillators
OSCCLK

SYSCLK

Bit Rate

20 MHz

10 MHz

100 kbps

The SYSCLKOUT values shown are the reset values with the default PLL setting. The BRP and bit-time
values are hard-coded to 10 and 20, respectively.
NOTE: The CPU1 CAN boot loader uses XTAL as the bit clock source and INTOSC2 as the system
clock source. The CPU2 CAN boot loader does not change either clock source, so CPU1
must configure the clock sources before starting the CPU2 CAN boot loader.

Mailbox 1 is programmed with a standard MSGID of 0x1 for boot-loader communication. The CAN host
should transmit only 2 bytes at a time, LSB first and MSB next. For example, to transmit the word 0x08AA
to the device, transmit AA first, followed by 08. The program flow of the CAN bootloader is identical to the
SCI bootloader. The data sequence for the CAN bootloader is shown in Table 3-25:
Table 3-25. CAN 8-Bit Data Stream
Bytes

Byte 1 of 2

Byte 2 of 2

Description

1

2

AA

08

0x08AA (KeyValue for memory width = 16 bits)

3

4

00

00

reserved

5

6

00

00

reserved

7

8

00

00

reserved

9

10

00

00

reserved

11

12

00

00

reserved

13

14

00

00

reserved

15

16

00

00

reserved

17

18

00

00

reserved

19

20

BB

AA

Entry point PC[22:16]

21

22

DD

CC

Entry point PC[15:0] (PC = 0xAABBCCDD)

23

24

NN

MM

Block size of the first block of data to load = 0xMMNN words

25

26

BB

AA

Destination address of first block Addr[31:16]

27

28

DD

CC

Destination address of first block Addr[15:0] (Addr = 0xAABBCCDD)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting 609

Boot ROM Description

www.ti.com

Table 3-25. CAN 8-Bit Data Stream (continued)
Bytes
29

30

Byte 1 of 2

Byte 2 of 2

BB

AA

...
...

First word of the first block in the source being loaded = 0xAABB
....
Data for this section.
...

.

BB

AA

Last word of the first block of the source being loaded = 0xAABB

.

NN

MM

Block size of the 2nd block to load = 0xMMNN words

.

BB

AA

Destination address of second block Addr[31:16]

.

DD

CC

Destination address of second block Addr[15:0]

.

BB

AA

First word of the second block in the source being loaded

.

3.9.4.7

Description

…

n

n+1

BB

AA

Last word of the last block of the source being loaded
(More sections if required)

n+2

n+3

00

00

Block size of 0000h - indicates end of the source program

USB Boot Mode

In USB boot mode, the device will enumerate with vendor ID 0x1cbe and product ID 0x00ff. The device
descriptor and interface descriptor both show the class as 0xFF (vendor-specific), the subclass as 0x00,
and the protocol as 0x00. After enumeration, the device will wait for data. Data should be sent via bulk
OUT transfers to endpoint 1. The data is interpreted as a series of 8-bit bytes in the standard data stream
format described in Section 3.9.5, shown here in Table 3-26. No reserved bytes are used. Once the data
transfer is complete (block size of 0x0000 sent), the device will disconnect from the USB bus, allowing
other software to make use of the module if desired. Figure 3-22 illustrates the flow for USB boot mode.
Figure 3-22. USB Boot Flow
USB_Boot
Host sends boot
loader data in the
standard stream
format via bulk OUT
transfers to
endpoint 1

Wait for
connection

Enumerate to host
PC with ID 1cbe:00ff

Valid key
(0x08AA)?

Jump to flash

Host PC installs
drivers
MCU loads data into
RAM
MCU waits
for data

MCU disconnects
from the USB bus
Return EntryPoint

Table 3-26. USB 8-Bit Data Stream
Bytes

First Byte
(LSB)

Second Byte Description
(MSB)

1

2

AA

08

0x08AA (KeyValue for memory width = 16bits)

3

4

00

00

reserved

610 ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Table 3-26. USB 8-Bit Data Stream (continued)
Bytes

First Byte
(LSB)

Second Byte Description
(MSB)

5

6

00

00

reserved

7

8

00

00

reserved

9

10

00

00

reserved

11

12

00

00

reserved

13

14

00

00

reserved

15

16

00

00

reserved

17

18

00

00

reserved

19

20

BB

AA

Entry point PC[22:16]

21

22

DD

CC

Entry point PC[15:0] (PC = 0xAABBCCDD)

23

24

NN

MM

Block size of the first block of data to load = 0xMMNN words

25

26

BB

AA

Destination address of first block Addr[31:16]

27

28

DD

CC

Destination address of first block Addr[15:0] (Addr = 0xAABBCCDD)

29

30

BB

AA

First word of the first block in the source being loaded = 0xAABB

...
...

....
Data for this section.
...

.

BB

AA

Last word of the first block of the source being loaded = 0xAABB

.

NN

MM

Block size of the 2nd block to load = 0xMMNN words

.

BB

AA

Destination address of second block Addr[31:16]

.

DD

CC

Destination address of second block Addr[15:0]

.

BB

AA

First word of the second block in the source being loaded

.

…

n

n+1

BB

AA

Last word of the last block of the source being loaded
(More sections if required)

n+2

n+3

00

00

Block size of 0000h - indicates end of the source program

Implementing PC-side USB software is not trivial. It is recommended to use the TI-provided tools and
drivers to load data in USB boot mode. Hex and binary files for loader tools can be generated from COFF
(.out) files using the hex2000 tool. To produce a plain binary file in the boot loader format, use the
following command line:
hex2000 -boot -b Program_to_Load.out -o Binary_Loader_Data.dat
For more information on hex2000, please see the TMS320C28x Assembly Language Tools User's Guide
(SPRU513).

NOTE: INTOSC2 must be enabled before invoking the USB boot loader. If INTOSC2 is not enabled,
the boot loader will hang. A debugger reset or SCC reset will not enable INTOSC2 if it has
been disabled by the application.

3.9.5 Boot Data Stream Structure
This section details the data transfer protocols or stream structures that allow boot data transfer between
boot ROM and host device. This data transfer protocol is compatible to the respective bootloaders on the
Piccolo class of C2000 devices.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

611

Boot ROM Description

3.9.5.1

www.ti.com

Bootloader Data Stream Structure

The following table and associated examples show the structure of the data stream incoming to the
bootloader. The basic structure is the same for all the bootloaders and is based on the C54x source data
stream generated by the C54x hex utility. The C28x hex utility (hex2000.exe) has been updated to support
this structure. The hex2000.exe utility is included with the C2000 code generation tools. All values in the
data stream structure are in hex.
The first 16-bit word in the data stream is known as the key value. The key value is used to tell the
bootloader the width of the incoming stream: 8 or 16 bits. Note that not all bootloaders will accept both 8
and 16-bit streams. Please refer to the detailed information on each loader for the valid data stream width.
For an 8-bit data stream, the key value is 0x08AA and for a 16-bit stream it is 0x10AA. If a bootloader
receives an invalid key value, then the load is aborted.
The next eight words are used to initialize register values or otherwise enhance the bootloader by passing
values to it. If a bootloader does not use these values then they are reserved for future use and the
bootloader simply reads the value and then discards it. Currently only the SPI and I2C and parallel
bootloaders use these words to initialize registers.
The tenth and eleventh words comprise the 22-bit entry point address. This address is used to initialize
the PC after the boot load is complete. This address is most likely the entry point of the program
downloaded by the bootloader.
The twelfth word in the data stream is the size of the first data block to be transferred. The size of the
block is defined as 8-bit data stream format. For example, to transfer a block of 20 8-bit data values from
an 8-bit data stream, the block size would be 0x000A to indicate 10 16-bit words.
The next two words tell the loader the destination address of the block of data. Following the size and
address will be the 16-bit words that makeup that block of data.
This pattern of block size/destination address repeats for each block of data to be transferred. Once all the
blocks have been transferred, a block size of 0x0000 signals to the loader that the transfer is complete. At
this point the loader will return the entry point address to the calling routine which in turn will cleanup and
exit. Execution will then continue at the entry point address as determined by the input data stream
contents.
Table 3-27. LSB/MSB Loading Sequence in 8-Bit Data Stream
Byte

Contents
LSB (First Byte of 2)

MSB (Second Byte of 2)

1

2

LSB: AA (KeyValue for memory width = 8 bits)

MSB: 08h (KeyValue for memory width = 8 bits)

3

4

LSB: Register initialization value or reserved

MSB: Register initialization value or reserved

5

6

LSB: Register initialization value or reserved

MSB: Register initialization value or reserved

7

8

LSB: Register initialization value or reserved

MSB: Register initialization value or reserved

...
...

...
...

...
...

...
...

17

18

LSB: Register initialization value or reserved

MSB: Register initialization value or reserved

19

20

LSB: Upper half of Entry point PC[23:16]

MSB: Upper half of entry point PC[31:24] (Always 0x00)

21

22

LSB: Lower half of Entry point PC[7:0]

MSB: Lower half of Entry point PC[15:8]

23

24

LSB: Block size in words of the first block to load. If the
block size is 0, this indicates the end of the source
program. Otherwise another block follows. For example, a
block size of 0x000A would indicate 10 words or 20 bytes
in the block.

MSB: block size

25

26

LSB: MSW destination address, first block Addr[23:16]

MSB: MSW destination address, first block Addr[31:24]

27

28

LSB: LSW destination address, first block Addr[7:0]

MSB: LSW destination address, first block Addr[15:8]

29

30

LSB: First word of the first block being loaded

MSB: First word of the first block being loaded

...
...

...
...

...
...

...
...

.

.

LSB: Last word of the first block to load

MSB: Last word of the first block to load

.

.

LSB: Block size of the second block

MSB: Block size of the second block

612 ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Table 3-27. LSB/MSB Loading Sequence in 8-Bit Data Stream (continued)
Byte

Contents
LSB (First Byte of 2)

MSB (Second Byte of 2)

.

.

LSB: MSW destination address, second block Addr[23:16]

MSB: MSW destination address, second block
Addr[31:24]

.

.

LSB: LSW destination address, second block Addr[7:0]

MSB: LSW destination address, second block Addr[15:8]

.

.

LSB: First word of the second block being loaded

MSB: First word of the second block being loaded

...
...

...
...

...
...

...
...

.

.

LSB: Last word of the second block

MSB: Last word of the second block

.

.

LSB: Block size of the last block

MSB: Block size of the last block

.

.

LSB: MSW of destination address of last block Addr[23:16] MSB: MSW destination address, last block Addr[31:24]

.

.

LSB: LSW destination address, last block Addr[7:0]

MSB: LSW destination address, last block Addr[15:8]

.

.

LSB: First word of the last block being loaded

MSB: First word of the last block being loaded

...
...

...
...

...
...

...
...

.

.

LSB: Last word of the last block

MSB: Last word of the last block

n

n+1

LSB: 00h

MSB: 00h - indicates the end of the source

Example 3-1. Data Stream Structure 8-bit

AA
00
00
00
00
3F
05
3F
01
02
03
04
05
02
3F
00
25
00

08
00
00
00
00
00
00
00
00
00
00
00
00
00
00
77
76
00

00
00
00
00
00

00
00
00
00
80

10 90

00 80

; 0x08AA 8-bit key value
; 8 reserved words

;
;
;
;

0x003F8000 EntryAddr, starting point after boot load completes
0x0005 - First block consists of 5 16-bit words
0x003F9010 - First block will be loaded starting at 0x3F9010
Data loaded = 0x0001 0x0002 0x0003 0x0004 0x0005

; 0x0002 - 2nd block consists of 2 16-bit words
; 0x003F8000 - 2nd block will be loaded starting at 0x3F8000
; Data loaded = 0x7700 0x7625
; 0x0000 - Size of 0 indicates end of data stream

After load has completed the following memory values will have been initialized as follows:
Location
Value
0x3F9010
0x0001
0x3F9011
0x0002
0x3F9012
0x0003
0x3F9013
0x0004
0x3F9014
0x0005
0x3F8000
0x7700
0x3F8001
0x7625
PC Begins execution at 0x3F8000

3.9.6 GPIO Assignments
This section details the GPIOs and boot options used for each boot mode set in the BMODE bit-field of
the BOOTCTRL register in OTP. Refer to Section 3.4 on the details of the BOOTCTRL fields.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

613

Boot ROM Description

www.ti.com

Table 3-28. SCI Boot Options
Option

BMODE Value

SCITXDA GPIO

SCIRXDA GPIO

CPU Support

0 (default)

0x01

GPIO84

GPIO85

CPU1 and CPU2

1

0x81

GPIO29

GPIO28

CPU1 Only

Table 3-29. CAN Boot Options
Option

BMODE Value

CANTXA GPIO

CANRXA GPIO

CPU Support

0

0x07

GPIO71

GPIO70

CPU1 and CPU2

1

0x87

GPIO63

GPIO62

CPU1 Only

Table 3-30. I2C Boot Options
Option

BMODE Value

SDAA GPIO

SCLA GPIO

CPU Support

0

0x05

GPIO91

GPIO92

CPU1 and CPU2

1

0x85

GPIO32

GPIO33

CPU1 Only

Table 3-31. USB Boot Options
Option

BMODE Value

USBDM GPIO

USBDP GPIO

CPU Support

0

0x0C

GPIO42

GPIO43

CPU1 Only

Table 3-32. RAM Boot Options
Option

BMODE Value

RAM Entry Point
(Address)

CPU Support

0

0x0A

0x0000 0000

CPU1 and CPU2

Table 3-33. Flash Boot Options
Option

BMODE Value

Flash Entry Point
(Address)

Flash Sector

CPU Support

0

0x0B

0x0008 0000

Sector A

CPU1 and CPU2

Table 3-34. Wait Boot Options
Option

BMODE Value

CPU Support

0 (default)

0x02

CPU1 and CPU2

Table 3-35. SPI Boot Options

614

Option

BMODE Value

SPISIMOA

SPISOMIA

SPICLKA

SPISTEA

CPU Support

0

0x04

GPIO58

GPIO59

GPIO60

GPIO61

CPU1 and CPU2

1

0x84

GPIO16

GPIO17

GPIO18

GPIO19

CPU1 Only

ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Table 3-36. Parallel Boot Options
Option

BMODE Value

D0-D7 GPIO

DSP Control GPIO

Host Control GPIO

CPU Support

0 (default)

0x0

D0 - GPIO65

GPIO69

GPIO70

CPU1 and CPU2

D1 - GPIO64
D2 - GPIO58
D3 - GPIO59
D4 - GPIO60
D5 - GPIO61
D6 - GPIO62
D7 - GPIO63

3.9.7 Boot IPC
In order for CPU1 and CPU2 to communicate during the boot process, a set of inter-processor
communication (IPC) registers are used. Each core polls for supported IPC commands which then
determine what specific action should be performed. Actions include performing reads or writes to a
particular memory address, branching to an address, or calling a function. The supported commands differ
depending on the core.
Prior to sending an IPC command to CPU2 boot ROM, the CPU1 application should perform the
necessary GPIO mux configurations for the peripheral IO pins. CPU2 peripheral loaders don’t configure
any of the GPIO mux options and only configure the peripheral as required for the application load. Once
configured, CPU1 can then assign the peripheral to CPU2 through configuration of the CPU select
register.
3.9.7.1

CPU1 IPC Commands

This section details the commands CPU1 boot ROM supports. These commands can be used by CPU2
applications to have CPU1 boot ROM to perform an action such as configure peripherals or IOs. In order
to use these IPC commands, CPU1 boot ROM must be in Wait Boot mode. Additionally, watchdog is
disabled when using IPC.
Table 3-37. C2TOC1IPC Commands Table

(1)
C2TOC1IPCFLG[31]
=?
C2TOC1IPCFLAG[0]
=0

Description

Look at error codes
table

0x01

Illegal command

Data in
C2TOC1IPCDATA
W[15:0]

Data read back from
address after write

0x00 = Command
success

*(address) |= data;

Address of the 32-bit
register

Data;

Data read back from
address after write

Same as above

*(address) |= data;

C2C1_BROM_IPC_CLEAR_BITS_16

Address of the 16-bit
register

Data in
C2TOC1IPCDATA
W[15:0]

Data read back after
write

Same as above

*(address) &= ~data;

4

C2C1_BROM_IPC_CLEAR_BITS_32

Address of the 32-bit
register

Data

Data read back after
write

Same as above

*(address) &= ~data;

5

C2C1_BROM_IPC_DATA_WRITE_16

Address of the 16-bit
register

Data in
MTOCIPCDATAW
[15:0]

Data read back from
the address

Same as above

*(address) = data;

6

C2C1_BROM_IPC_DATA_WRITE_32

Address of the 32-bit
register

Data

Same as above

Same as above

*(address) = data;

7

C2C1_BROM_IPC_DATA_READ_16

Address of the 16-bit
register

--NOT_USED--

Data in
C2TOC1IPCDATAR[1
5:0]

Same as above

C2TOC1IPCDATAR[1
5:0] = *(address);
Only 16 bit read from
address

Value

IPCRECVCOM
(CPU2 - R/W, CPU1- R)

IPCRECVADDR
(CPU2 - R/W, CPU1- R)

IPCRECVDATA
(CPU2 - R/W,
CPU1- R)

IPCLOCALREPLY
(CPU2 - R,
CPU1 - R/W)

0

C2C1_BROM_IPC_COMMAND_ILLEGAL

_NOT-USED_

_NOT-USED_

1

C2C1_BROM_IPC_SET_BITS_16

Address of the 16-bit
register

2

C2C1_BROM_IPC_SET_BITS_32

3

(1)

All 32-bit operations are done in little endian format (C28x is 16-bit addressable).
Example: a 32-bit IPC write is handled as below:
•
Data[15:0] is written in address
•
Data [31:16] is written in address+1

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting 615

Boot ROM Description

www.ti.com

Table 3-37. C2TOC1IPC Commands Table

3.9.7.2

(1)

(continued)

IPCRECVDATA
(CPU2 - R/W,
CPU1- R)

IPCLOCALREPLY
(CPU2 - R,
CPU1 - R/W)

C2TOC1IPCFLG[31]
=?
C2TOC1IPCFLAG[0]
=0

Address of the 32-bit
register

Same as above

32-bit data

Same as above

C2TOC1IPCDATAR[3
1:0] = *(address);
32 bits read from
address

C2C1_BROM_IPC_SET_BITS_
PROTECTED_16

Address of the 16-bit
register

Data in
C2TOC1IPCDATA
W[15:0]

Data read back from
address after write

0x00 = Command
success

EALLOW;
*(address) |= data;
EDIS;

10

C2C1_BROM_IPC_SET_BITS_
PROTECTED_32

Address of the 32-bit
register

Data;

Data read back from
address after write

Same as above

EALLOW;
*(address) |= data;
EDIS;

11

C2C1_BROM_IPC_CLEAR_BITS_
PROTECTED_16

Address of the 16-bit
register

Data in
C2TOC1IPCDATA
W[15:0]

Data read back after
write

Same as above

EALLOW;
*(address) &= ~data;
EDIS;

12

C2C1_BROM_IPC_CLEAR_BITS_
PROTECTED_32

Address of the 32-bit
register

Data

Data read back after
write

Same as above

EALLOW;
*(address) &= ~data;
EDIS;

13

C2C1_BROM_IPC_DATA_WRITE_
PROTECTED_16

Address of the 16-bit
register

Data in
C2TOC1IPCDATA
W[15:0]

Data read back from
the address

Same as above

EALLOW;
*(address) &= ~data;
EDIS;

14

C2C1_BROM_IPC_DATA_WRITE_
PROTECTED_32

Address of the 32-bit
register

Data

Same as above

Same as above

EALLOW;
*(address) &= ~data;
EDIS;

15

C2C1_BROM_IPC_DATA_READ_
PROTECTED_16

Address of the 32-bit
register

--NOT_USED--

Data in
C2TOC1IPCDATAR[1
5:0]

Same as above

EALLOW;
C2TOC1IPCDATAR[1
5:0] = *(address);
EDIS;
Only 16 bit read from
address

16

C2C1_BROM_IPC_DATA_READ_
PROTECTED_32

Address of the 32-bit
register

Data

Same as above

Same as above

EALLOW;
C2TOC1IPCDATAR[3
1:0] = *(address);
EDIS;
32 bits read from
address

Value

IPCRECVCOM
(CPU2 - R/W, CPU1- R)

IPCRECVADDR
(CPU2 - R/W, CPU1- R)

8

C2C1_BROM_IPC_DATA_READ_32

9

Description

CPU2 IPC Commands

This section details the commands that CPU2 boot ROM supports. These commands can be used by
CPU1 applications to have CPU2 perform a specific action. In order to use these IPC commands, CPU2
boot ROM must be in Wait Boot mode.
Table 3-38. C1TOC2IPC Commands Table

616

C1TOC2IPCFLG[31]
=?
C1TOC2IPCFLAG[0]
=0

Description

Look at error codes
table

0x01

Illegal command

Data in
C1TOC2IPCDATAW[
15:0]

Data read back from
address after write

0x00 = Command
success

*(address) |= data;

Address of the 32-bit
register

Data;

Data read back from
address after write

Same as above

*(address) |= data;

C1C2_BROM_IPC_CLEAR_BITS_16

Address of the 16-bit
register

Data in
C1TOC2IPCDATAW[
15:0]

Data read back after
write

Same as above

*(address) &= ~data;

4

C1C2_BROM_IPC_CLEAR_BITS_32

Address of the 32-bit
register

Data

Data read back after
write

Same as above

*(address) &= ~data;

5

C1C2_BROM_IPC_DATA_WRITE_16

Address of the 16-bit
register

Data in
MTOCIPCDATAW[15
:0]

Data read back from
the address

Same as above

*(address) = data;

6

C1C2_BROM_IPC_DATA_WRITE_32

Address of the 32-bit
register

Data

Same as above

Same as above

*(address) = data;

7

C1C2_BROM_IPC_DATA_READ_16

Address of the 16-bit
register

--NOT_USED--

Data in
C1TOC2IPCDATAR[
15:0]

Same as above

C1TOC2IPCDATAR[
15:0] = *(address);
Only 16 bit read from
address

Value

IPCRECVCOM
(CPU1 - R/W, CPU2 R)

IPCRECVADDR
(CPU1 - R/W,
BCPU2- R)

IPCRECVDATA
(CPU1 - R/W, CPU2R)

IPCLOCALREPLY
(CPU1 - R, CPU2 R/W)

0

C1C2_BROM_IPC_COMMAND_ILLEGAL

_NOT-USED_

_NOT-USED_

1

C1C2_BROM_IPC_SET_BITS_16

Address of the 16-bit
register

2

C1C2_BROM_IPC_SET_BITS_32

3

ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Table 3-38. C1TOC2IPC Commands Table (continued)
IPCRECVADDR
(CPU1 - R/W,
BCPU2- R)

IPCRECVDATA
(CPU1 - R/W, CPU2R)

IPCLOCALREPLY
(CPU1 - R, CPU2 R/W)

C1TOC2IPCFLG[31]
=?
C1TOC2IPCFLAG[0]
=0

Value

IPCRECVCOM
(CPU1 - R/W, CPU2 R)

8

C1C2_BROM_IPC_DATA_READ_32

Address of the 32-bit
register

Same as above

32 bit data

Same as above

C1TOC2IPCDATAR[
31:0] = *(address);
32 bits read from
address

9

C1C2_BROM_IPC_SET_BITS_
PROTECTED_16

Address of the 16-bit
register

Data in
C1TOC2IPCDATAW[
15:0]

Data read back from
address after write

0x00 = Command
success

EALLOW;
*(address) |= data;
EDIS;

10

C1C2_BROM_IPC_SET_BITS_
PROTECTED_32

Address of the 32-bit
register

Data;

Data read back from
address after write

Same as above

EALLOW;
*(address) |= data;
EDIS;

11

C1C2_BROM_IPC_CLEAR_BITS_
PROTECTED_16

Address of the 16-bit
register

Data in
C1TOC2IPCDATAW[
15:0]

Data read back after
write

Same as above

EALLOW;
*(address) &= ~data;
EDIS;

12

C1C2_BROM_IPC_CLEAR_BITS_
PROTECTED_32

Address of the 32-bit
register

Data

Data read back after
write

Same as above

EALLOW;
*(address) &= ~data;
EDIS;

13

C1C2_BROM_IPC_DATA_WRITE_
PROTECTED_16

Address of the 16-bit
register

Data in
C1TOC2IPCDATAW[
15:0]

Data read back from
the address

Same as above

EALLOW;
*(address) = data;
EDIS;

14

C1C2_BROM_IPC_DATA_WRITE_
PROTECTED_32

Address of the 32-bit
register

Data

Same as above

Same as above

EALLOW;
*(address) = data;
EDIS;

15

C1C2_BROM_IPC_DATA_READ_
PROTECTED_16

Address of the 16-bit
register

--NOT_USED--

Data in
C1TOC2IPCDATAR[
15:0]

Same as above

EALLOW;
C1TOC2IPCDATAR[
15:0] = *(address);
Only 16 bit read from
address

16

C1C2_BROM_IPC_DATA_READ_
PROTECTED_32

Address of the 32-bit
register

Same as above

32 bit data

Same as above

EALLOW;
C1TOC2IPCDATAR[
31:0] = *(address);
EDIS;
32 bits read from
address

17

C1C2_BROM_IPC_BRANCH_CALL

Address where to
branch to

_NOTUSED_BY_BOOTRO
M
(code at the branch
can use this though)

NOTUSED_BY_BOOTRO
M
(code at the branch
can use this though)

Same as above

C2-BootROM will
jump to the address
in ADDR register and
starts executing the
code from that
address.
PIE will be enabled
when this branch
occurs, it is upto the
application to disable
and reload PIE
interrupt handlers if it
wants to.

18

C1C2_BROM_IPC_FUNCTION_CALL

Address of the
function

Parameter for the
function call

Result of function call
(return value if any
from function)

Same as above

C2-BootROM will
jump to the address
in ADDR register and
starts executing the
code from that
address; Data in
DATAW register can
be used as parameter
to the function call. CBootROM returns
back to where it was
after servicing the
function call.
Function call is
performed from inside
the interrupt service
routine on Aria so
user has to keep this
in mind.

19

C1C2_BROM_IPC_EXECUTE_
BOOTMODE_CMD

--NOT_USED--

--NOT_USED--

--NOT_USED--

Same as above

Execute loaders as
per requested value
in
C1TOC2BOOTMODE
register.

Description

• C1TOC2BOOTMODE = 0xA,
C1C2_BROM_BOOTMODE_
BOOT_FROM_RAM
• C1TOC2BOOTMODE = 0xB,
C1C2_BROM_BOOTMODE_
BOOT_FROM_FLASH
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

617

Boot ROM Description

www.ti.com

Table 3-38. C1TOC2IPC Commands Table (continued)

Value

IPCRECVADDR
(CPU1 - R/W,
BCPU2- R)

IPCRECVCOM
(CPU1 - R/W, CPU2 R)

IPCRECVDATA
(CPU1 - R/W, CPU2R)

IPCLOCALREPLY
(CPU1 - R, CPU2 R/W)

C1TOC2IPCFLG[31]
=?
C1TOC2IPCFLAG[0]
=0

Description

• C1TOC2BOOTMODE = 0x1,
C1C2_BROM_BOOTMODE_
BOOT_FROM_SCI
• C1TOC2BOOTMODE = 0x4,
C1C2_BROM_BOOTMODE_
BOOT_FROM_SPI,
• C1TOC2BOOTMODE = 0x5,
C1C2_BROM_BOOTMODE_
BOOT_FROM_I2C
• C1TOC2BOOTMODE = 0x0,
C1C2_BROM_BOOTMODE_
BOOT_FROM_PARALLEL
• C1TOC2BOOTMODE = 0x7,
C1C2_BROM_BOOTMODE_
BOOT_FROM_CAN

3.9.7.3

CPU2 IPC Error Commands

This section details the commands CPU2 boot ROM supports. These commands can be used by CPU1
applications to have CPU2 perform a specific action. In order to use these IPC commands, CPU2 boot
ROM must be in Wait Boot mode.
Table 3-39. CPU2 Error Command Values
Error Value

Description

Note

0x0000 0000

Invalid Command Value

Default value when starting boot

0xFFFF FFFE

CPU2 has got an ITRAP

Address where ITRAP occurred is placed
in IPCADDR register

0xFFFF FFFD

CPU2 got a spurious PIE interrupt

Interrupt number placed in IPCDATAW
register

0xFFFF FFFC

CPU2 got a PIE vector mismatch error

-

0xFFFF FFFB

CPU2 got an uncorrectable Flash error

-

0xFFFF FFFA

CPU2 got an uncorrectable RAM error

-

3.9.8 Clock Initializations
During boot up, the boot ROM initializes the device clocking, depending upon the reset source, to assist in
faster boot time response. Clock configurations are performed by the boot ROM code only for POR, XRS,
and HIBERNATE reset types. For all other resets, the boot ROM starts executing with the clocks that were
already set up before reset.
Only CPU1 performs the clock configuration for the device during boot up.
Table 3-40. Boot Clock Sources

618

Source

Frequency

INTOSC2

10 MHz

Default clock source

INTOSC1

10 MHz

Set as clock source if missing
clock is detected at power up or
right after device reset

ROM Code and Peripheral Booting

Description

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Table 3-41. Clock State After Boot ROM
Reset Source

Clock State

POR/XRS/HIBERNATE

Bypassed PLL.
PLL multiplier is set to 0x0
Clock divider is set to /1.

All other Resets

Maintain clocks setup before device reset.

NOTE: If the PLL is used during the boot process, it will be bypassed by the boot ROM code before
branching to the user application.

3.9.9 Wait State Configuration
This section details the ROM memory wait state configurations. By default, the ROM memory on this
device is not zero-wait state; it is 1-wait state with pre-fetch disabled. ROM does support pre-fetch enable
and disable configurations in order to provide better execution speeds at varying clock frequencies.
Configuring the wait state enables user applications to adjust for when performing callbacks into ROM or
secure copy code (SCC).
Table 3-42. ROM Wait States
Wait State Disable Bit
(Bit 0 – 0x5F540)

Pre-Fetch Enable Bit
(Bit 0 – 0x5E608)

ROM Configuration

0

0

• Wait state enabled
• Pre-fetch disabled
• Max Frequency: 200MHz

0

1

• Wait state enabled
• Pre-fetch enabled
• Max Frequency: 180MHz

1

Don’t Care

• 0 Wait state
• Pre-fetch disabled
• Max Frequency: 150MHz

3.9.10 Boot Status information
Boot ROM keeps a record of the different events that can occur during boot ROM execution. This is
because NMI and other exceptions are enabled by default in the device, and must be handled accordingly.
Boot ROM stores the boot status information in a RAM location so that the user application can look at
this boot status and take the necessary actions per the application’s needs to handle these events.
3.9.10.1 CPU1 Booting Status
This section details the boot status RAM location and its bit field definitions for CPU1. When the specific
bit field is set, the described event or action has occurred.
Table 3-43. CPU1 Boot Status Address
Description

Address

CPU1 Boot ROM Status

0x0000 002C

Table 3-44. CPU1 Boot Status Bit Fields
Bit

Description

31

CPU1 Boot ROM has finished running

30

Boot ROM detected a missing clock NMI

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting 619

Boot ROM Description

www.ti.com

Table 3-44. CPU1 Boot Status Bit Fields (continued)
Bit

Description

29

Boot ROM detected a RAM bit error NMI

28

Boot ROM detected a Flash bit error NMI

27

Boot ROM detected CPU1 HWBIST error NMI

26

Boot ROM detected CPU2 HWBIST error NMI

25

Boot ROM detected PIE vector error NMI

22

Boot ROM detected CPU2 watchdog reset

21

Boot ROM detected CPU2 NMI watchdog reset

20

Boot ROM detected OVF NMI

19

Boot ROM detected a PIE mismatch

18

Boot ROM detected CPU1 to CPU2 branch

17

Boot ROM detected an ITRAP

15

Boot ROM handled POR

14

Boot ROM handled XRS

13

Boot ROM handled HWBIST reset

12

Boot ROM handled hibernate reset

11

Boot ROM handled all the resets

10

DCSM initialization has completed

9

Flash boot has started

8

CPU1 Boot ROM has started running

3.9.10.2 CPU2 Booting Status
This section details the boot status bit field definitions for CPU2. When the specific bit field is set, the
described event or action has occurred. These status bits can be read from the C2TOC1BOOTSTS
register.
Table 3-45. CPU2 Boot ROM Status Address
Description

Address

CPU2 Boot ROM Status

0x0000 0002

Table 3-46. CPU Booting Status

620 ROM Code and Peripheral Booting

Bit

Description

31

CPU2 Boot ROM has finished running

30

Boot ROM detected a missing clock NMI

29

Boot ROM detected a RAM bit error NMI

28

Boot ROM detected a Flash bit error NMI

27

Boot ROM detected CPU1 HWBIST error NMI

26

Boot ROM detected CPU2 HWBIST error NMI

25

Boot ROM detected PIE vector error NMI

22

Boot ROM detected CPU2 watchdog reset

21

Boot ROM detected CPU2 NMI watchdog reset

20

Boot ROM detected OVF NMI

19

Boot ROM detected a PIE mismatch

18

Boot ROM detected CPU1 to CPU2 branch

17

Boot ROM detected an ITRAP

11

Boot ROM handled all the resets

10

DCSM initialization has completed
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Boot ROM Description

www.ti.com

Table 3-46. CPU Booting Status (continued)
Bit

Description

9

Flash boot has started

8

CPU2 Boot ROM has started running

3-0

0 – Invalid Status. CPU2 hasn’t set a valid status yet
1 – CPU2 Boot ROM has started running
2 – CPU2 Boot ROM has completed and is ready for IPC
commands
3 – CPU2 ACKs the boot command in C1TOC2BOOTMODE
register
4 – CPU2 doesn’t support the command in
C1TOC2BOOTMODE register
5 – CPU2 NAKs the boot command in C1TOC2BOOTMODE
register

3.9.10.3 CPU1 IPC NAK Status
This section details the NAK status information for CPU1, if boot ROM IPC command support is enabled.
These NAK status bits are returned by CPU1 in the C2TOC1IPCDATAR[11:0] register.
Table 3-47. CPU1 IPC NAK Status Bit Fields
Bit

Description

3-0

0 – Invalid Value or value isn’t set
1 – Command not supported
2 – Command not set correctly
3 – CPU is trying to send a second command before the first
one is complete
4 – Command execution resulted in an error
5 – Command cannot be executed in the current state of the
boot ROM

3.9.10.4 CPU2 IPC NAK Status
This section details the NAK status information for CPU2, if boot ROM IPC command support is enabled.
These NAK status bits are returned by CPU1 in the C1TOC2IPCDATAR[11:0] register.
Table 3-48. CPU2 IPC NAK Status Bit Fields
Bit

Description

3-0

0 – Invalid Value or value isn’t set
1 – Command not supported
2 – Command not set correctly
3 – CPU1 is trying to send a second command before the first
one is complete
4 – Command execution resulted in an error
5 – Command cannot be executed in the current state of the
boot ROM

3.9.11 ROM Version
The ROM revision and release date information is stored at the ROM locations specified in this section.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ROM Code and Peripheral Booting

621

Boot ROM Description

www.ti.com

Table 3-49. Boot ROM Version Information for CPU1 and CPU2
Start Address

End Address

Contents

0x003F FF7A

0x003F FF7B

Revision Number

0x003F FF7C

0x003F FF7D

Revision Date

Interpreting the contents:
• Reading a revision value of 0x100 represents version 1.0.
• Reading a revision date value of 0x0715 represents 07/15 or July 2015.

622

ROM Code and Peripheral Booting

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 4
SPRUHM8G – December 2013 – Revised September 2017

Direct Memory Access (DMA)
The direct memory access (DMA) module provides a hardware method of transferring data between
peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other
system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as it is
transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into
blocks for optimal CPU processing.
Topic

...........................................................................................................................

4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8

Introduction .....................................................................................................
Architecture .....................................................................................................
Pipeline Timing and Throughput ........................................................................
CPU Arbitration ................................................................................................
Channel Priority ...............................................................................................
Address Pointer and Transfer Control .................................................................
Overrun Detection Feature .................................................................................
Register Descriptions........................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

Page

624
625
632
633
634
636
640
642

623

Introduction

4.1

www.ti.com

Introduction
The strength of a controller is not measured purely in processor speed, but in total system capabilities. As
a part of the equation, any time the CPU bandwidth for a given function can be reduced, the greater the
system capabilities. Many times applications spend a significant amount of their bandwidth moving data,
whether it is from off-chip memory to on-chip memory, or from a peripheral such as an analog-to-digital
converter (ADC) to RAM, or even from one peripheral to another. Furthermore, many times this data
comes in a format that is not conducive to the optimum processing powers of the CPU. The DMA module
described in this reference guide has the ability to free up CPU bandwidth and rearrange the data into a
pattern for more streamlined processing.
The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start
a DMA transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the
interrupt trigger source, there is no mechanism within the module itself to start memory transfers
periodically. The interrupt trigger source for each of the six DMA channels can be configured separately
and each channel contains its own independent PIE interrupt to let the CPU know when a DMA transfer
has either started or completed. Five of the six channels are exactly the same, while Channel 1 has the
ability to be configured at a higher priority than the others. At the heart of the DMA is a state machine and
tightly coupled address control logic. It is this address control logic that allows for rearrangement of the
block of data during the transfer as well as the process of ping-ponging data between buffers. Each of
these features, along with others, will be discussed in detail in this document.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– McBSPx transmit and receive
– External Interrupts
– CPU Timers
– EPWMxSOC signals
– SPIx transmit and receive
– USBx transmit and receive
– Sigma Delta filter module
– Software trigger
• Data sources and destinations:
– GSx RAM
– CPU message RAM (IPC RAM)
– ADC memory-bus mapped result registers
– ePWMx
– SPI, McBSP, EMIF
• Word Size: 16-bit or 32-bit (SPI and McBSP limited to 16-bit)
• Throughput: 4 cycles/word without arbitration

624

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Architecture

www.ti.com

4.2

Architecture

4.2.1 Block Diagram
Figure 4-1 shows a device-level block diagram of the DMA.
Figure 4-1. DMA Block Diagram
CPU1
TIMER
(3)

Global Shared
16x 4Kx16
GS0-15 RAMs

MSG RAM
1Kx16
CPU2 to CPU1

MSG RAM
1Kx16
CPU1 to CPU2

CPU1.DMA Bus
TINT (0-2)
XINT (1-5)
ADC INT (A-D) (1-4), EVT (A-D)
SDxFLTy (x = 1 to 2, y = 1 to 4)
SOCA (1-12), SOCB (1-12)
MXEVT (A-B), MREVT (A-B)
SPITX (A-C), SPIRX (A-C)

C28x CPU1 Bus

DMA Trigger
Source Selection
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)

DMA
CPU1

DMA Trigger
Source Selection

XINT (1-5)
TINT (0-2)

DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)

DMA
CPU2

DMA_CHx (1-6)

CPU1
XINT
(5)

ADC
RESULTS
(4)

C28x
CPU1
PIE

DMA_CHx (1-6)

ADC
WRAPPER
(4)

C28x
CPU2
PIE

CPU2.DMA Bus
C28x CPU2 Bus

eCAP

eQEP

DAC

CMPSS

DMA Trigger Source
SDFM
(8)

EPWM
(12)

McBSP
(2)

SPI
(3)

EMIF1

CPU2
XINT
(5)

CPU2
TIMER
(3)

CPU and DMA Data Path

4.2.2 Common Peripheral Architecture
There are two CPU subsystems; the CPU1 subsystem and CPU2 subsystem, with each containing a CLA
and a DMA. The architecture allows several peripherals to be common between the two subsystems.
Based on application need, these common peripherals can be attached to one of the two subsystems.
Figure 4-2 shows how the CPUs and subsystems can be connected to the peripherals on peripheral
frames 1 and 2. The clock, clock-enable, and reset muxing for the common peripherals are described in
detail in other sections of this document.
Refer to Section 4.4 for more details on the arbitration scheme for all masters.
NOTE: If the CPU and DMA make an access to the same peripheral frame in the same cycle, the
DMA has priority and the CPU is stalled.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

625

Architecture

www.ti.com

Figure 4-2. Common Peripheral Architecture
CPU1 SYSCLK
CPU1 SYSRSn
CPU1.PCLKRx
CPU1
Arbiter

CPU1 Peripheral Frame 1

CPU1.CLA1
CPU1.DMA
CPU1.SECMSEL

CPU2 SYSCLK
CPU2 SYSRSn
CPU2.PCLKRx

CPU2
CPU2.CLA1

Arbiter

CPU2 Peripheral Frame 1

CPU2.DMA
CPUSELx.PERy
CPU2.SECMSEL

SDFM

ePWM
HRPWM

CMPSS

eQEP

eCAP

DAC

Do not have integrated DMA trigger capability
CPU1 SYSCLK
CPU1 SYSRSn
CPU1.PCLKRx
CPU1
Arbiter
CPU1.CLA1

CPU1 Peripheral Frame 2

CPU1.DMA
CPU1.SECMSEL

CPU2 SYSCLK
CPU2 SYSRSn
CPU2.PCLKRx

CPU2
CPU2.CLA1

Arbiter

CPU2 Peripheral Frame 2

CPU2.DMA
CPUSELx.PERy
CPU2.SECMSEL

SPI
A/B/C

McBSP
A/B

uPP

DMA Access is not supported

A CPUSEL bit associated with each peripheral defines whether the peripheral belongs to the CPU1 or
CPU2 subsystem. If a peripheral belongs to a CPU subsystem, it can be accessed by the CPU and one of
the secondary masters (DMA or CLA1). Refer to CPUSELx register definition for more details. The
secondary master is statically selected using the SECMSEL register mapped to the respective CPU. Refer
to CPUx.SECMSEL register definition for more details. If a secondary master is not selected, all writes
from that master are ignored and all reads return 0x0 to any of the peripherals.
Similarly, if a peripheral does not belong to a CPU subsystem (as defined by the associated CPUSEL bit),
all writes to that peripheral are ignored and all reads to that peripheral return 0x0 from any of the masters
belonging to the unselected CPU subsystem. Note that since the arbiter has no knowledge regarding the
ownership of individual peripherals (as can be seen from Figure 4-2), arbitration will still happen even if
C28x or the selected secondary master tries to access a peripheral which does not belong to its CPU
subsystem. See CPU Arbitration for more information.

626

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Architecture

www.ti.com

4.2.3 Peripheral Interrupt Event Trigger Sources
As shown in Figure 4-3 the peripheral interrupt event trigger can be independently configured as any of
the sources from the DMACHSRCSELx register for each of the six DMA channels. Included in these
sources are five external interrupt signals which can be connected to most of the general-purpose
input/output (GPIO) pins on the device. This adds significant flexibility to the event trigger capabilities. The
DMA trigger source is selected in the DMACHSRCSELx register (Table 2-16), for each channel. The
PERINTSEL in the MODE register of each channel should be set to the channel number (for example,
CH2.MODE.PERINTSEL[4:0] = 2). An active peripheral interrupt trigger will be latched into the
PERINTFLG bit of the CONTROL register, and if the respective interrupt and DMA channel is enabled
(see the MODE.CHx[PERINTE] and CONTROL.CHx[RUNSTS] bits), it will be serviced by the DMA
channel. Upon receipt of a peripheral interrupt event signal, the DMA will automatically send a clear signal
to the interrupt source so that subsequent interrupt events will occur.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

627

Architecture

www.ti.com

Figure 4-3. DMA Trigger Architecture

DMA
DMACHSRCSELx.CH1
256 X 1
Mux

CH1.MODE.PERINTSEL[4:0] = 1

‘1’

0
1

All DMA Trigger
Sources

2

Trigger Source for CH1
(Active Low)

6
7

DMACHSRCSELx.CH2

31

256 X 1
Mux
CH2.MODE.PERINTSEL[4:0] = 2

0
1
2

Trigger Source for CH2
(Active Low)

6
7

31

DMACHSRCSELx.CH6
256 X 1
Mux

CH6.MODE.PERINTSEL[4:0] = 6

0
1
2

6
7

Trigger Source for CH6
(Active Low)

31

NOTE: To use the system level DMA Trigger source selection, the DMA internal trigger source
selection configuration for each channel should be done using the DMACHSRCSELx register
(Table 2-16), and the CHx.MODE.PERINTSEL register as shown here. See Table 4-1 or the
DMACHSRCSELx register definition for a complete list of DMA trigger sources.

628

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Architecture

www.ti.com

Regardless of the value of the MODE.CHx[PERINTSEL] bit field, software can always force a trigger by
using the CONTROL.CHx[PERINTFRC] bit. Likewise, software can always clear a pending DMA trigger
using the CONTROL.CHx[PERINTCLR] bit.
Once a particular interrupt trigger sets a channel’s PERINTFLG bit, the bit stays pending until the priority
logic of the state machine starts the burst transfer for that channel. Once the burst transfer starts, the flag
is cleared. If a new interrupt trigger is generated while a burst is in progress, the burst will complete before
responding to the new interrupt trigger (after proper prioritization). If a third interrupt trigger occurs before
the pending interrupt is serviced, an error flag is set in the CONTROL.CHx[OVRFLG] bit. If a peripheral
interrupt trigger occurs at the same time as the latched flag is being cleared, the peripheral interrupt
trigger has priority and the PERINTFLG will remain set.
Figure 4-4 shows a diagram of the trigger select circuit. See the DMACHSRCSELx register, (Table 2-16)
description for the complete list of peripheral interrupt trigger sources.
Figure 4-4. Peripheral Interrupt Trigger Input Diagram
Clear interrupt
CONTROL.CHx[PERINTFLG]
DMA
channel x
processing
logic

Clear
Peripheral
Int
Latch
MODE.CHx
[PERINTE]

MODE.CHx
[PERINTSEL]

CONTROL.CHx
[PERINTCLR]
(A) (See DMACHSRCSELx
register)

Set

CONTROL.CHx
[PERINTFRC]
Clear peripheral interrupt
trigger flag if appropriate
A

See Figure 4-3.

Table 4-1 shows the interrupt trigger source options that are available for each channel.
Table 4-1. Peripheral Interrupt Trigger Source Options
Select Value (8-bit)

DMA ChTrigger Source

0

No Peripheral

1

ADCA.1

2

ADCA.2

3

ADCA.3

4

ADCA.4

5

ADCAEVT

6

ADCB.1

7

ADCB.2

8

ADCB.3

9

ADCB.4

10

ADCBEVT

11

ADCC.1

12

ADCC.2

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA) 629

Architecture

www.ti.com

Table 4-1. Peripheral Interrupt Trigger Source Options (continued)
Select Value (8-bit)

DMA ChTrigger Source

13

ADCC.3

630 Direct Memory Access (DMA)

14

ADCC.4

15

ADCCEVT

16

ADCD.1

17

ADCD.2

18

ADCD.3

19

ADCD.4

20

ADCDEVT

21

No Peripheral

22

No Peripheral

23

No Peripheral

24

No Peripheral

25

No Peripheral

26

No Peripheral

27

No Peripheral

28

No Peripheral

29

XINT1

30

XINT2

31

XINT3

32

XINT4

33

XINT5

34

No Peripheral

35

No Peripheral

36

EPWM1.SOCA

37

EPWM1.SOCB

38

EPWM2.SOCA

39

EPWM2.SOCB

40

EPWM3.SOCA

41

EPWM3.SOCB

42

EPWM4.SOCA

43

EPWM4.SOCB

44

EPWM5.SOCA

45

EPWM5.SOCB

46

EPWM6.SOCA

47

EPWM6.SOCB

48

EPWM7.SOCA

49

EPWM7.SOCB

50

EPWM8.SOCA

51

EPWM8.SOCB

52

EPWM9.SOCA

53

EPWM9.SOCB

54

EPWM10.SOCA

55

EPWM10.SOCB

56

EPWM11.SOCA

57

EPWM11.SOCB

58

EPWM12.SOCA

59

EPWM12.SOCB

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Architecture

www.ti.com

Table 4-1. Peripheral Interrupt Trigger Source Options (continued)
Select Value (8-bit)

DMA ChTrigger Source

60

No Peripheral

61

No Peripheral

62

No Peripheral

63

No Peripheral

64

No Peripheral

65

No Peripheral

66

No Peripheral

67

No Peripheral

68

TINT0

69

TINT1

70

TINT2

71

MXEVTA

72

MREVTA

73

MXEVTB

74

MREVTB

75

No Peripheral

76

No Peripheral

77

No Peripheral

78

No Peripheral

79

No Peripheral

80

No Peripheral

81

No Peripheral

82

No Peripheral

83

No Peripheral

84

No Peripheral

85

No Peripheral

86

No Peripheral

87

No Peripheral

88

No Peripheral

89

No Peripheral

90

No Peripheral

91

No Peripheral

92

No Peripheral

93

No Peripheral

94

No Peripheral

95

SD1FLT1

96

SD1FLT2

97

SD1FLT3

98

SD1FLT4

99

SD2FLT1

100

SD2FLT2

101

SD2FLT3

102

SD2FLT4

103

No Peripheral

104

No Peripheral

105

No Peripheral

106

No Peripheral

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA) 631

Architecture

www.ti.com

Table 4-1. Peripheral Interrupt Trigger Source Options (continued)
Select Value (8-bit)

DMA ChTrigger Source

107

No Peripheral

108

No Peripheral

109

SPITXDMAA

110

SPIRXDMAA

111

SPITXDMAB

112

SPIRXDMAB

113

SPITXDMAC

114

SPIRXDMAC

115

No Peripheral

116

No Peripheral

117

No Peripheral

118

No Peripheral

119

No Peripheral

120

No Peripheral

121

No Peripheral

122

No Peripheral

123

No Peripheral

124

No Peripheral

125

No Peripheral

126

No Peripheral

127

No Peripheral

128

No Peripheral

129

No Peripheral

130

No Peripheral

131

USBA_EPx_RX1

132

USBA_EPx_TX1

133

USBA_EPx_RX2

134

USBA_EPx_TX2

135

USBA_EPx_RX3

136

USBA_EPx_TX3

137:255

No Peripheral

4.2.4 DMA Bus
The DMA bus architecture consists of a 32-bit address bus, a 32-bit data read bus, and a 32-bit data write
bus. Memories and register locations connected to the DMA bus are via interfaces that sometimes share
resources with the CPU memory or peripheral bus. Arbitration rules are defined in Section 4.4.

4.3

Pipeline Timing and Throughput
The DMA module consists of a 4-stage pipeline as shown in Figure 4-5. The one exception to this is when
a DMA channel is configured to have the McBSP as its data source. A read of a McBSP DRR register
stalls the DMA bus for one cycle during the read portion of the transfer, as shown in Figure 4-6.

632

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CPU Arbitration

www.ti.com

Figure 4-5. 4-Stage Pipeline DMA Transfer
SYSCLK

Addr bus

Write
DST
data
(N)

Read
SRC
data
(N)

Data bus

Generate
address

Out
Out
DST SRC
addr addr
(N+1) (N+2)

Out
Out
DST SRC
addr addr
(N) (N+1)

Out
SRC
addr
(N)

Gen
SRC
addr
(N+1)

Gen
DST
addr
(N+1)

Read
SRC
data
(N+1)
Gen
SRC
addr
(N+2)

Read
SRC
data
(N+2)

Write
DST
data
(N+1)
Gen
DST
addr
(N+2)

Gen
SRC
addr
(N+3)

Figure 4-6. 4-Stage Pipeline With One Read Stall (McBSP as source)
SYSCLK

Addr bus

Out
SRC
addr
(N)
Read
SRC
data
(N)

Data bus

Generate
address

In
•
•
•
•

Out
DST
addr
(N)

Gen
SRC
addr
(N+1)

Out
SRC
addr
(N+1)

Write
DST
data
(N)
Gen
DST
addr
(N+1)

Out
DST
addr
(N+1)
Read
SRC
data
(N+1)

Gen
SRC
addr
(N+2)

Write
DST
data
(N+1)
Gen
DST
addr
(N+2)

addition to the pipeline there are a few other behaviors of the DMA that affect its total throughput:
A 1-cycle delay is added at the beginning of each burst
A 1-cycle delay is added when returning from a CH1 high priority interrupt
Collisions with the CPU may add delay slots (see Section 4.4)
32-bit transfers run at double the speed of a 16-bit transfer (it takes the same amount of time to
transfer a 32-bit word as it does a 16-bit word)

For example, to transfer 128 16-bit words from GS0 RAM to GS15 RAM, a channel can be configured to
transfer 8 bursts of 16 words/burst. This will give:
8 bursts * [(4 cycles/word * 16 words/burst) + 1] = 520 cycles
If instead the channel were configured to transfer the same amount of data 32 bits at a time (the word size
is configured to 32 bits) the transfer would take:
8 bursts * [(4 cycles/word * 8 words/burst) + 1] = 264 cycles

4.4

CPU Arbitration
Typically, DMA activity is independent of the CPU activity. When the DMA and the CPU access a
peripheral register within the same peripheral frame concurrently, an arbitration procedure will occur. Any
combined accesses between the different interfaces, or where the CPU access is outside of the interface
that the DMA is accessing, do not create a conflict.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

633

Channel Priority

www.ti.com

Conflict Example: the CPU is accessing SPI FIFO while the DMA is simultaneously accessing McBSP, it
will create a conflict because both SPI and McBSP reside in a common interface (peripheral frame 2).
Non-conflict Example: the CPU is accessing shared ePWM while the DMA is accessing message
McBSP, there will be no conflict, since these two peripherals are located in different interfaces (peripheral
frame 1 and peripheral frame 2).
The interfaces which internally contain conflicts are:
• Global shared RAMs (GSRAMs)
• CPU message RAM (IPC MSG RAMs)
• USB registers
• EMIF1 registers
• Peripheral frame 1 (ePWM, HRPWM, eCAP, eQEP, DAC, CMPSS, and SDFM)
• Peripheral frame 2 (McBSP, SPI, and uPP)
The ADC result registers are duplicated for each bus master. Therefore, the CPU, DMA, and CLA can all
simultaneously read these registers with no stalls for any master.
If the CPU and the DMA make an access to the same peripheral frame in the same cycle, the DMA has
priority and the CPU is stalled.
A DMA transfer consists of four phases: send source address, read source data, send destination
address, and write destination data (see Section 4.3). In the case of a bulk DMA transfer to and from the
same memory block the CPU is trying to access, the arbitration will stall CPU access until the DMA
completes single access, not the entire bulk transfer.. This arbitration is based on a round robin priority
scheme described in Section 4.5.
The following priority schemes are implemented for the various interfaces on the device.
• On the peripheral register interface, the fixed priority scheme is:
– CLA/DMA Write
– CLA/DMA Read
– CPU Write
– CPU Read
• For ADC result registers (refer to the ADC chapter for more detailed information):
– Parallel access is possible from all masters
• For GSxRAM/IPC MSG RAM (refer to the System Control chapter for more detailed information):
– Round-robin
NOTE: If the CPU is performing a read-modify-write operation and the DMA performs a write to the
same location, the DMA write may be lost if the operation occurs in between the CPU read
and the CPU write. For this reason, it is advised not to mix such CPU accesses with DMA
accesses to the same locations.

4.5

Channel Priority
Two priority schemes exist when determining channel priority: Round-robin mode and Channel 1 highpriority mode.

4.5.1 Round-Robin Mode
In this mode, all channels have equal priority and each enabled channel is serviced in round-robin fashion
as follows:
CH1 → CH2 → CH3 → CH4 → CH5 → CH6 → CH1 → CH2 → …

634

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Channel Priority

www.ti.com

In the case above, after each channel has transferred a burst of words, the next channel is serviced. You
can specify the size of the burst for each channel. Once CH6 (or the last enabled channel) has been
serviced, and no other channels are pending, the round-robin state machine enters an idle state.
From the idle state, channel 1 (if enabled) is always serviced first. However, if the DMA is currently
processing another channel x, all other pending channels between x and the end of the round are serviced
before CH1. It is in this sense that all the channels are of equal priority. For instance, take an example
where CH1, CH4, and CH5 are enabled in round-robin mode and CH4 is currently being processed. Then
CH1 and CH5 both receive an interrupt trigger from their respective peripherals before CH4 completes.
CH1 and CH5 are now both pending. When CH4 completes its burst, CH5 will be serviced next. Only after
CH5 completes will CH1 be serviced. Upon completion of CH1, if there are no more channels pending, the
round-robin state machine will enter an idle state.
A
•
•
•
•
•
•
•
•
•
•

more complicated example is shown below:
Assume all channels are enabled, and the DMA is in an idle state,
Initially a trigger occurs on CH1, CH3, and CH5 on the same cycle,
When the CH1 burst transfer starts, requests from CH3 and CH5 are pending,
Before completion of the CH1 burst, the DMA receives a request from CH2. Now the pending requests
are from CH2, CH3, and CH5,
After completing the CH1 burst, CH2 will be serviced since it is next in the round-robin scheme after
CH1.
After the burst from CH2 is finished, the CH3 burst will be serviced, followed by CH5 burst.
Now while the CH5 burst is being serviced, the DMA receives a request from CH1, CH3, and CH6.
The burst from CH6 will start after the completion of the CH5 burst since it is the next channel after
CH5 in the round-robin scheme.
This will be followed by the CH1 burst and then the CH3 burst
After the CH3 burst finishes, assuming no more triggers have occurred, the round-robin state machine
will enter an idle state.

The round-robin state machine may be reset to the idle state via the DMACTRL[PRIORITYRESET] bit.

4.5.2 Channel 1 High Priority Mode
In this mode, if a CH1 trigger occurs, the current word transfer or the current + 1 word transfer (depends
on which phase of the current DMA transfer the new CH1 trigger occurred) on any other channel is
completed (not the complete burst), execution is halted, and CH1 is serviced for the complete burst count.
When the CH1 burst is complete, execution returns to the channel that was active when the CH1 trigger
occurred. All other channels have equal priority and each enabled channel is serviced in round-robin
fashion as follows:
Higher Priority:
Lower priority:

CH1
CH2 → CH3 → CH4 → CH5 → CH6 → CH2 → …

Given an example where CH1, CH4 and CH5 are enabled in Channel 1 High Priority Mode and CH4 is
currently being processed. Then CH1 and CH5 both receive an interrupt trigger from their respective
peripherals before CH4 completes. CH1 and CH5 are now both pending. When the current CH4 word
transfer is completed, regardless of whether the DMA has completed the entire CH4 burst, CH4 execution
will be suspended and CH1 will be serviced. After the CH1 burst completes, CH4 will resume execution.
Upon completion of CH4, CH5 will be serviced. After CH5 completes, if there are no more channels
pending, the round-robin state machine will enter an idle state.
Typically Channel 1 would be used in this mode for the ADC, since its data rate is so high. However,
Channel 1 High Priority Mode may be used in conjunction with any peripheral.
NOTE: High-priority mode and ONESHOT mode may not be used at the same time on channel 1.
Other channels may use ONESHOT mode when channel 1 is in high-priority mode.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

635

Address Pointer and Transfer Control

4.6

www.ti.com

Address Pointer and Transfer Control
The DMA state machine is, at its most basic level, two nested loops. The inner loop transfers a burst of
data when a peripheral interrupt trigger is received. A burst is the smallest amount of data that can be
transferred at one time and its size is defined by the BURST_SIZE register for each channel. The
BURST_SIZE register allows a maximum of 32 sixteen-bit words to be transferred in one burst. The outer
loop, whose size is set by the TRANSFER_SIZE register for each channel, defines how many bursts are
performed in the entire transfer. Since TRANSFER_SIZE is a 16-bit register, the total size of a transfer
allowed is well beyond any practical requirement. One CPU interrupt is generated, if enabled, for each
transfer. This interrupt can be configured to occur at the beginning or the end of the transfer via the
MODE.CHx[CHINTMODE] bit.
In the default setting of the MODE.CHx[ONESHOT] bit, the DMA transfers one burst of data each time a
peripheral interrupt trigger is received. After the burst is completed, the state machine moves on to the
next pending channel in the priority scheme, even if another trigger for the channel just completed is
pending. This feature keeps any single channel from monopolizing the DMA bus. If a transfer of more than
the maximum number of words per burst is desired for a single trigger, the MODE.CHx[ONESHOT] bit can
be set to complete the entire transfer when triggered. Care is advised when using this mode, since this
can create a condition where one trigger uses up the majority of the DMA bandwidth.
Each DMA channel contains a shadowed address pointer for the source and the destination address.
These pointers, SRC_ADDR and DST_ADDR, can be independently controlled during the state machine
operation. At the beginning of each transfer, the shadowed version of each pointer is copied into its
respective active register. During the burst loop, after each word is transferred, the signed value contained
in the appropriate source or destination BURST_STEP register is added to the active SRC/DST_ADDR
register. During the transfer loop, after each burst is complete, there are two methods that can be used to
modify the active address pointer. The first, and default, method is by adding the signed value contained
in the SRC/DST_TRANSFER_STEP register to the appropriate pointer. The second is via a process
called wrapping, where a wrap address is loaded into the active address pointer. When a wrap procedure
occurs, the associated SRC/DST_TRANSFER_STEP register has no effect.
Address wrapping occurs when a number of bursts specified by the appropriate SRC/DST_WRAP_SIZE
register completes. Each DMA channel contains two shadowed wrap address pointers, SRC_BEG_ADDR
and DST_BEG_ADDR, allowing the source and destination wrapping to be independent of each other.
Like the SRC_ADDR and DST_ADDR registers, the active SRC/DST_BEG_ADDR registers are loaded
from their shadow counterpart at the beginning of a transfer. When the specified number of bursts has
occurred, a two part wrap procedure takes place:
• The appropriate active SRC/DST_BEG_ADDR register is incremented by the signed value contained in
the SRC/DST_WRAP_STEP register, then
• The new active SRC/DST_BEG_ADDR register is loaded into the active SRC/DST_ADDR register.
Additionally the wrap counter (SRC/DST_WRAP_COUNT) register is reloaded with the
SRC/DST_WRAP_SIZE value to setup the next wrap period. This allows the channel to wrap multiple
times within a single transfer. Combined with the first bullet above, this allows the channel to address
multiple buffers within a single transfer.
The DMA contains both an active and shadow set of the following address pointers. When a DMA transfer
begins, the shadow register set is copied to the active working set of registers. This allows you to program
the values of the shadow registers for the next transfer while the DMA works with the active set. It also
allows you to implement Ping-Pong buffer schemes without disrupting the DMA channel execution.
Source/Destination Address Pointers (SRC/DST_ADDR)— The value written into the shadow register
is the start address of the first location where data is read or written to.
At the beginning of a transfer the shadow register is copied into the active register. The active
register performs as the current address pointer.
Source/Destination Begin Address Pointers (SRC/DST_BEG_ADDR)— This is the wrap pointer.
The value written into the shadow register will be loaded into the active register at the start of a
transfer. On a wrap condition, the active register will be incremented by the signed value in the
appropriate SRC/DST_WRAP_STEP register prior to being loaded into the active SRC/DST_ADDR
register.
For each channel, the transfer process can be controlled with the following size values:

636

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Address Pointer and Transfer Control

www.ti.com

Source and Destination Burst Size (BURST_SIZE): — This specifies the number of words to be
transferred in a burst.
This value is loaded into the BURST_COUNT register at the beginning of each burst. The
BURST_COUNT decrements each word that is transferred and when it reaches a zero value, the
burst is complete, indicating that the next channel can be serviced. The behavior of the current
channel is defined by the ONE_SHOT bit in the MODE register. The maximum size of the burst is
dictated by the type of peripheral. For the ADC, the burst size could be all 16 registers (if all 16
registers are used). For a McBSP peripheral, the burst size is limited to 1 since there is no FIFO
and the receive or transmit data register must be loaded or copied every word transferred. For RAM
the burst size can be up to the maximum allowed by the BURST_SIZE register, which is 32.
Source and Destination Transfer Size (TRANSFER_SIZE): — This specifies the number of bursts to be
transferred before per CPU interrupt (if enabled).
Whether this interrupt is generated at the beginning or the end of the transfer is defined in the
CHINTMODE bit in the MODE register. Whether the channel remains enabled or not after the
transfer is completed is defined by the CONTINUOUS bit in the MODE register. The
TRANSFER_SIZE register is loaded into the TRANSFER_COUNT register at the beginning of each
transfer. The TRANSFER_COUNT register keeps track of how many bursts of data the channel has
transferred and when it reaches zero, the DMA transfer is complete.
Source/Destination Wrap Size (SRC/DST_WRAP_SIZE)— This specifies the number of bursts to be
transferred before the current address pointer wraps around to the beginning.
This feature is used to implement a circular addressing type function. This value is loaded into the
appropriate SRC/DST_WRAP_COUNT register at the beginning of each transfer. The
SRC/DST_WRAP_COUNT registers keep track of how many bursts of data the channel has
transferred and when they reaches zero, the wrap procedure is performed on the appropriate
source or destination address pointer. A separate size and count register is allocated for source
and destination pointers. To disable the wrap function, assign the value of these registers to be
larger than the TRANSFER_SIZE.
NOTE: The value written to the SIZE registers is one less than the intended size. So, to transfer
three 16-bit words, the value 2 should be placed in the SIZE register.
Regardless of the state of the DATASIZE bit, the value specified in the SIZE registers are for
16-bit addresses. So, to transfer three 32-bit words, the value 5 should be placed in the SIZE
register.

For each source/destination pointer, the address changes can be controlled with the following step values:
Source/Destination Burst Step (SRC/DST_BURST_STEP)— Within each burst transfer, the address
source and destination step sizes are specified by these registers.
This value is a signed 2's compliment number so that the address pointer can be incremented or
decremented as required. If no increment is desired, such as when accessing the McBSP data
receive or transmit registers, the value of these registers should be set to zero.
Source/Destination Transfer Step (SRC/DST_TRANSFER_STEP)— This specifies the address offset to
start the next burst transfer after completing the current burst transfer.
This is used in cases where registers or data memory locations are spaced at constant intervals.
This value is a signed 2's compliment number so that the address pointer can be incremented or
decremented as required.
Source/Destination Wrap Step (SRC/DST_WRAP_STEP): — When the wrap counter reaches zero, this
value specifies the number of words to add/subtract from the BEG_ADDR pointer and hence sets
the new start address.
This implements a circular type of addressing mode, useful in many applications. This value is a
signed 2's compliment number so that the address pointer can be incremented or decremented as
required.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

637

Address Pointer and Transfer Control

www.ti.com

NOTE: Regardless of the state of the DATASIZE bit, the value specified in the STEP registers are
for 16-bit addresses. So, to increment one 32-bit address, a value of 2 should be placed in
these registers.

Three modes are provided to control the way the state machine behaves during the burst loop and the
transfer loop:
One Shot Mode (ONESHOT)— If one shot mode is enabled when an interrupt event trigger occurs, the
DMA will continue transferring data in bursts until TRANSFER_COUNT is zero. If one shot mode is
disabled, then an interrupt event trigger is required for each burst transfer and this will continue until
TRANSFER_COUNT is zero.
NOTE: When ONESHOT mode is enabled, the DMA will continuously transfer bursts of data on the
given channel until the TRANSFER_COUNT value is zero. This could potentially hog the
bandwidth of a peripheral and cause long CPU stalls to occur. To avoid this, you could
configure a CPU timer (or similar) and disable ONESHOT so as to avoid this situation.
High-priority mode and one-shot mode may not be used at the same time on channel 1.
Other channels may use ONESHOT mode when channel 1 is in high-priority mode

Continuous Mode (CONTINUOUS)— If continuous mode is disabled the RUNSTS bit in the CONTROL
register is cleared at the end of the transfer, disabling the DMA channel.
The channel must be re-enabled by setting the RUN bit in the CONTROL register before another
transfer can be started on that channel. If the continuous mode is enabled the RUNSTS bit is not
cleared at the end of the transfer.
Channel Interrupt Mode (CHINTMODE)— This mode bit selects whether the DMA interrupt from the
respective channel is generated at the beginning of a new transfer or at the end of the transfer.
If implementing a ping-pong buffer scheme with continuous mode of operation, then the interrupt
would be generated at the beginning, just after the working registers are copied to the shadow set.
If the DMA does not operate in continuous mode, then the interrupt is typically generated at the end
when the transfer is complete.
All of the above features and modes are shown in Figure 4-7.

638

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Address Pointer and Transfer Control

www.ti.com

Figure 4-7. DMA State Diagram
Copy all addr shadow registers
to Active Set
TRANSFER_COUNT = TRANSFER_SIZE
WRAP_COUNT = WRAP_SIZE
TRANSFERSTS = 1
Generate DMACHx
interrupt to CPU
at beginning of
transfer (if enabled)

Yes

RUNSTS = 1

Yes

Peripheral
int
?

No

Peripheral
int
?

No

HALT
here

CHINTMODE
== 0
?
No

WRAP_COUNT = WRAP_SIZE
ADDR = BEG_ADDR
SYNCERR = 1

SYNCE == 1 &
SYNCFLG == 1 &
WRAP_COUNT !=
WRAP_SIZE
?

Yes

Yes

HALT
here

No
BURST_COUNT = BURST_SIZE
BURSTSTS = 1
Clear PERINTFLG bit
Clear SYNCFLG bit
Out active SRC_ADDR
Read data
Out active DST_ADDR

Write data

HALT
here
BURST_
COUNT
== 0
?

No

BURST_COUNT-ADDR += BURST_STEP

Yes
ADDR += TRANSFER STEP
Points where state
machine branches
to next channel

BURSTSTS = 0

Yes

TRANSFER_
COUNT == 0
?
No

BEG_ADDR += WRAP_STEP
ADDR = BEG_ADDR
WRAP_COUNT = WRAP_SIZE

WRAP_
COUNT == 0
?

Yes

Yes

No

ONESHOT
== 1
?

WRAP_COUNT--

No

TRANSFER_COUNT-TRANSFERSTS = 0

RUNSTS = 0
No

Generate DMACHx interrupt
to CPU at end of
transfer (if enabled)

Yes

CHINTMODE
== 1
?

No

CONTINUOUS
== 1
?

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Yes

Direct Memory Access (DMA)

639

Overrun Detection Feature

www.ti.com

The following items are in reference to Figure 4-7.
• The HALT points represent where the channel halts operation when interrupted by a high priority
channel 1 trigger, or when the HALT command is set, or when an emulation halt is issued and the
FREE bit is cleared to 0.
• The ADDR registers are not affected by BEG_ADDR at the start of a transfer. BEG_ADDR only affects
the ADDR registers on a wrap or sync error. Following is what happens to each of the ADDR registers
when a transfer first starts:
– BEG_ADDR_SHADOW remains unchanged.
– ADDR_SHADOW remains unchanged.
– BEG_ADDR = BEG_ADDR_SHADOW
– ADDR = ADDR_SHADOW
• The active registers get updated when a wrap occurs. The shadow registers remain unchanged.
Specifically:
– BEG_ADDR_SHADOW remains unchanged.
– ADDR_SHADOW remains unchanged.
– BEG_ADDR += WRAP_STEP
– ADDR = BEG_ADDR
• The active registers get updated when a sync error occurs. The shadow registers remain unchanged.
Specifically:
– BEG_ADDR_SHADOW remains unchanged.
– ADDR_SHADOW remains unchanged.
– BEG_ADDR remains unchanged.
– ADDR = BEG_ADDR
Probably the easiest way to remember all this is that:
• The shadow registers never change except by software.
• The active registers never change except by hardware, and a shadow register is only copied into its
own active register, never an active register by another name.

4.7

Overrun Detection Feature
The DMA contains overrun detection logic. When a peripheral event trigger is received by the DMA, the
PERINTFLG bit in the CONTROL register is set, pending the channel to the DMA state machine. When
the burst for that channel is started, the PERINTFLG is cleared. If however, between the time that the
PERINTFLG bit is set by an event trigger and cleared by the start of the burst, an additional event trigger
arrives, the second trigger will be lost. This condition will set the OVRFLG bit in the CONTROL register as
in Figure 4-8. If the overrun interrupt is enabled then the channel interrupt will be generated to the PIE
module.

640

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Overrun Detection Feature

www.ti.com

Figure 4-8. Overrun Detection Logic

DMA
channel interrupt
PIE
MODE.CHx
[CHINTE]

DMACHx interrupt generated
at beginning or end of transfer
CONTROL.CHx
CONTROL.CHx
[PERINTFLG]
[OVRFLG]
PERx_INT
Latch
MODE.CHx
[OVERNITE]

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CONTROL.CHx
[ERRCLR]

Direct Memory Access (DMA)

641

Register Descriptions

4.8

www.ti.com

Register Descriptions
The complete DMA register set is shown in Table 4-2.
Table 4-2. DMA Register Summary (1)
Address

Acronym

Description

Section

DMA Control, Mode and Status Registers
0x1000

DMACTRL

DMA Control Register

Section 4.8.1

0x1001

DEBUGCTRL

Debug Control Register

Section 4.8.2

0x1002

REVISION

Peripheral Revision Register

Section 4.8.3

0x1003

Reserved

Reserved

0x1004

PRIORITYCTRL1

Priority Control Register 1

0x1005

Reserved

Reserved

0x1006

PRIORITYSTAT

Priority Status Register

0x1007
0x101F

Reserved

Reserved

Section 4.8.4
Table 4-7

DMA Channel 1 Registers
0x1020

MODE

Mode Register

Section 4.8.6

0x1021

CONTROL

Control Register

Section 4.8.7

0x1022

BURST_SIZE

Burst Size Register

Section 4.8.8

0x1023

BURST_COUNT

Burst Count Register

Section 4.8.9

0x1024

SRC_BURST_STEP

Source Burst Step Size Register

Section 4.8.10

0x1025

DST_BURST_STEP

Destination Burst Step Size Register

Section 4.8.11

0x1026

TRANSFER_SIZE

Transfer Size Register

0x1027

TRANSFER_COUNT

Transfer Count Register

Section 4.8.13

0x1028

SRC_TRANSFER_STEP

Source Transfer Step Size Register

Section 4.8.14

0x1029

DST_TRANSFER_STEP

Destination Transfer Step Size Register

Section 4.8.15

0x102A

SRC_WRAP_SIZE

Source Wrap Size Register

Section 4.8.16

0x102B

SRC_WRAP_COUNT

Source Wrap Count Register

Section 4.8.17

0x102C

SRC_WRAP_STEP

Source Wrap Step Size Register

Section 4.8.18

0x102D

DST_WRAP_SIZE

Destination Wrap Size Register

Section 4.8.16

0x102E

DST_WRAP_COUNT

Destination Wrap Count Register

Section 4.8.17

0x102F

DST_WRAP_STEP

Destination Wrap Step Size Register

Section 4.8.18

0x1030

SRC_BEG_ADDR_SHADOW

Shadow Source Begin and Current Address Pointer Registers

Section 4.8.19

0x1032

SRC_ADDR_SHADOW

0x1034

SRC_BEG_ADDR

0x1036

SRC_ADDR

0x1038

DST_BEG_ADDR_SHADOW

Table 4-13

Section 4.8.19
Active Source Begin and Current Address Pointer Registers

Section 4.8.20
Section 4.8.20

0x103A

DST_ADDR_SHADOW

0x103C

DST_BEG_ADDR

0x103E

DST_ADDR

0x103F

Reserved

Shadow Destination Begin and Current Address Pointer
Registers

Section 4.8.21
Section 4.8.21

Active Destination Begin and Current Address Pointer Registers Section 4.8.22
Section 4.8.22
Reserved

DMA Channel 2 Registers
0x1040
0x105F

Same as above

DMA Channel 3 Registers
0x1060
0x107F

Same as above

DMA Channel 4 Registers

(1)

All DMA register writes are EALLOW protected.

642 Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 4-2. DMA Register Summary (1) (continued)
Address
0x1080
0x109F

Acronym

Description

Section

Same as above

DMA Channel 5 Registers
0x10A0
0x10BF

Same as above

DMA Channel 6 Registers
0x10C0
0x10DF

Same as above

4.8.1 DMA Control Register (DMACTRL) — EALLOW Protected
The DMA control register (DMACTRL) is shown in Figure 4-9 and described in Table 4-3.
Figure 4-9. DMA Control Register (DMACTRL)
15

14

13

12

11

10

9

8

3

2

1
PRIORITY
RESET
R0/S-0

0
HARD
RESET
R0/S-0

Reserved
R-0
7

6

5

4
Reserved
R-0

LEGEND: R0/S = Read 0/Set; R = Read only; -n = value after reset

Table 4-3. DMA Control Register (DMACTRL) Field Descriptions
Bit
15-2
1

Field

Value

Reserved
PRIORITYRESET

Description
Reserved

0

The priority reset bit resets the round-robin state machine when a 1 is written. Service starts
from the first enabled channel. Writes of 0 are ignored and this bit always reads back a 0.
When a 1 is written to this bit, any pending burst transfer completes before resetting the
channel priority machine. If CH1 is configured as a high priority channel, and this bit is
written to while CH1 is servicing a burst, the CH1 burst is completed and then any lower
priority channel burst is also completed (if CH1 interrupted in the middle of a burst), before
the state machine is reset.
In case CH1 is high priority, the state machine restarts from CH2 (or the next highest
enabled channel).

0

HARDRESET

0

Writing a 1 to the hard reset bit resets the whole DMA and aborts any current access
(similar to applying a device reset). Writes of 0 are ignored and this bit always reads back a
0.
For a soft reset, a bit is provided for each channel to perform a gentler reset. Refer to the
channel control registers.
When writing to this bit, there is a one cycle delay before it takes effect. Hence at least a
one cycle delay (that is, a NOP instruction) after writing to this bit should be introduced
before attempting an access to any other DMA register.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

643

Register Descriptions

www.ti.com

4.8.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected
The debug control register (DEBUGCTRL) is shown in Figure 4-10 and described in Table 4-4.
Figure 4-10. Debug Control Register (DEBUGCTRL)
15
FREE
R/W-0

14

13

12

11

10

9

8

7
Reserved
R-0

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-4. Debug Control Register (DEBUGCTRL) Field Descriptions
Bit

Field

15

FREE

14-0

Value

Description
Emulation Control Bit: This bit specifies the action when an emulation halt event occurs.

0

DMA runs until the current DMA read-write access is completed and the current status of a DMA is
frozen. See the HALT points in Figure 4-7 for possible halt states.

1

DMA is unaffected by emulation suspend (run free)

Reserved

Reserved

4.8.3 Revision Register (REVISION)
The revision register (REVISION) is shown in Figure 4-11 and described in Table 4-5.
Figure 4-11. Revision Register (REVISION)
15

14

13

12

11

10

9

8

7

6

5

TYPE
R

4

3

2

1

0

REV
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-5. Revision Register (REVISION) Field Descriptions
Bit

Field

15-8

TYPE

7-0

REV

Value

DMA Type Bits. A type change represents a major functional feature difference in a peripheral
module. Within a peripheral type, there may be minor differences between devices which do not
affect the basic functionality of the module. These device-specific differences are listed in the
TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566).
0x0000

This document describes a Type0 DMA.
DMA Silicon Revision Bits: These bits specify the DMA revision and are changed if any bug
fixes are performed.

0x0000

644

Description

Direct Memory Access (DMA)

First release

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

4.8.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected
The priority control register 1 (PRIORITYCTRL1) is shown in Figure 4-12 and described in Table 4-6.
Figure 4-12. Priority Control Register 1 (PRIORITYCTRL1)
15

14

13

12

11

10

9

8
Reserved

7

6

5

4

3

2

1

R-0

0
CH1
PRIOR
ITY
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-6. Priority Control Register 1 (PRIORITYCTRL1) Field Descriptions
Bit
15-1
0

Field

Value

Reserved

Description
Reserved

CH1PRIORITY

DMA Ch1 Priority: This bit selects whether channel 1 has higher priority or not:
0

Same priority as all other channels

1

Highest priority channel
Channel priority can only be changed when all channels are disabled. A priority reset should
be performed before restarting channels after changing priority.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

645

Register Descriptions

www.ti.com

4.8.5 Priority Status Register (PRIORITYSTAT)
The priority status register (PRIORITYSTAT) is shown in Figure 4-13 and described in Table 4-7.
Figure 4-13. Priority Status Register (PRIORITYSTAT)
15

14

13

12

11

10

9

8

3
Reserved
R-0

2

1
ACTIVESTS
R-0

0

Reserved
R-0
7
Reserved
R-0

6

5
ACTIVESTS_SHADOW
R-0

4

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-7. Priority Status Register (PRIORITYSTAT) Field Descriptions
Bit

Field

Value

Description

15-7

Reserved

Reserved

6-4

ACTIVESTS_SH
ADOW

Active Channel Status Shadow Bits: These bits are only useful when CH1 is enabled as a higher
priority channel. When CH1 is serviced, the ACTIVESTS bits are copied to the shadow bits and
indicate which channel was interrupted by CH1. When CH1 service is completed, the shadow bits
are copied back to the ACTIVESTS bits. If this bit field is zero or the same as the ACTIVESTS bit
field, then no channel is pending due to a CH1 interrupt. When CH1 is not a higher priority channel,
these bits should be ignored:

3
2-0

646

0,0,0

No channel pending

0,0,1

CH 1

0,1,0

CH 2

0,1,1

CH 3

1,0,0

CH 4

1,0,1

CH 5

1,1,0

CH 6

Reserved

Reserved

ACTIVESTS

Active Channel Status Bits: These bits indicate which channel is currently active or performing a
transfer:
0,0,0

no channel active

0,0,1

CH 1

0,1,0

CH 2

0,1,1

CH 3

1,0,0

CH 4

1,0,1

CH 5

1,1,0

CH 6

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

4.8.6 Mode Register (MODE) — EALLOW Protected
The mode register (MODE) is shown in Figure 4-14 and described in Table 4-8.
Figure 4-14. Mode Register (MODE)
15
CHINTE
R/W-0
7
OVRINTE
R/W-0

14
DATASIZE
R/W-0
6
Reserved
R-0

13

12
Reserved
R/W-0

5

4

11
CONTINUOUS
R/W-0
3

10
ONESHOT
R/W-0
2
PERINTSEL
R/W-0

9
CHINTMODE
R/W-0
1

8
PERINTE
R/W-0
0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-8. Mode Register (MODE) Field Descriptions
Bit

Field

15

CHINTE

14

Value

Description
Channel Interrupt Enable Bit: This bit enables/disables the respective DMA channel interrupt
to the CPU (via the PIE).

0

Interrupt disabled

1

Interrupt enabled

DATASIZE

Data Size Mode Bit: This bit selects if the DMA channel transfers 16-bits or 32-bits of data at a
time.
0

16-bit data transfer size

1

32-bit data transfer size

NOTE: Regardless of the value of this bit all of the registers in the
DMA refer to 16-bit words. The only effect this bit causes
is whether the databus width is 16 or 32 bits.
It is up to you to configure the pointer step increment and
size to accommodate 32-bit data transfers. See section
Section 4.6 for details.
13-12 Reserved

Reserved

11

CONTINUOUS

Continuous Mode Bit: If this bit is set to 1, then DMA re-initializes when TRANSFER_COUNT
is zero and waits for the next interrupt event trigger. If this bit is 0, then the DMA stops and
clears the RUNSTS bit to 0.

10

ONESHOT

One Shot Mode Bit: If this bit is set to 1, then subsequent burst transfers occur without
additional event triggers after the first event trigger. If this bit is 0 then only one burst transfer
is performed per event trigger.
Note: High-priority mode and One-shot mode may not be used at the same time on CH1.

9

CHINTMODE

Channel Interrupt Generation Mode Bit: This bit specifies when the respective DMA channel
interrupt should be generated to the CPU (via the PIE).

8

7

0

Generate interrupt at beginning of new transfer

1

Generate interrupt at end of transfer.

PERINTE

Peripheral Interrupt Trigger Enable Bit: This bit enables/disables the selected peripheral
interrupt trigger to the DMA.
0

Interrupt trigger disabled. Neither the selected peripheral nor software can start a DMA burst.

1

Interrupt trigger enabled.

OVRINTE

Overflow Interrupt Enable: This bit when set to 1 enables the DMA to generate an interrupt
when an overflow event is detected.
0

Overflow interrupt disabled

1

Overflow interrupt enabled
An overflow interrupt is generated when the PERINTFLG is set and another interrupt event
occurs. The PERINTFLG being set indicates a previous peripheral event is latched and has
not been serviced by the DMA.

6-5

Reserved

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

647

Register Descriptions

www.ti.com

Table 4-8. Mode Register (MODE) Field Descriptions (continued)
Bit

Field

4-0

PERINTSEL

648

Value

Direct Memory Access (DMA)

Description
The Peripheral Interrupt Source Select Bits: These bits should be set to the channel number
(i.e. CH2.MODE.PERINTSEL[4:0] = 2).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

4.8.7 Control Register (CONTROL) — EALLOW Protected
The control register (CONTROL) is shown in Figure 4-15 and described in Table 4-9.
Figure 4-15. Control Register (CONTROL)
15
Reserved

14
OVRFLG

13
RUNSTS

12
BURSTSTS

R-0
7
ERRCLR
R0/S-0

R-0
6

R-0
5

R-0
4
PERINTCLR
R0/S-0

Reserved
R-0

11
TRANSFERST
S
R-0
3
PERINTFRC
R0/S-0

10

9
Reserved
R-0

2
SOFTRESET
R0/S-0

1
HALT
R0/S-0

8
PERINTFLG
R-0
0
RUN
R0/S-0

LEGEND: R0/S = Read 0/Set; R = Read only; -n = value after reset

Table 4-9. Control Register (CONTROL) Field Descriptions
Bit

Field

Value Description

15

Reserved

Reserved

14

OVRFLG

Overflow Flag Bit: This bit indicates if a peripheral interrupt event trigger is received from the
selected peripheral and the PERINTFLG is already set.
0

No overflow event

1

Overflow event
The ERRCLR bit can be used to clear the state of this bit to 0. The OVRFLG bit is not affected
by the PERINTFRC event.

13

12

11

10-9
8

RUNSTS

Run Status Bit: This bit is set to 1 when the RUN bit is written to with a 1. This indicates the DMA
channel is now ready to process peripheral interrupt event triggers. This bit is cleared to 0 when
TRANSFER_COUNT reaches zero and CONTINUOUS mode bit is set to 0. This bit is also
cleared to 0 when either the HARDRESET bit, the SOFTRESET bit, or the HALT bit is activated.
0

Chanel is disabled.

1

Channel is enabled.

BURSTSTS

Burst Status Bit: This bit is set to 1 when a DMA burst transfer begins and the BURST_COUNT
is initialized with the BURST_SIZE. This bit is cleared to zero when BURST_COUNT reaches
zero. This bit is also cleared to 0 when either the HARDRESET or the SOFTRESET bit is
activated.
0

No burst activity

1

The DMA is currently servicing or suspending a burst transfer from this channel.

TRANSFERSTS

Transfer Status Bit: This bit is set to 1 when a DMA transfer begins and the address registers are
copied to the shadow set and the TRANSFER_COUNT is initialized with the TRANSFER_SIZE.
This bit is cleared to zero when TRANSFER_COUNT reaches zero. This bit is also cleared to 0
when either the HARDRESET or the SOFTRESET bit is activated.
0

No transfer activity

1

The channel is currently in the middle of a transfer regardless of whether a burst of data is
actively being transferred or not.

Reserved

Reserved

PERINTFLG

Peripheral Interrupt Trigger Flag Bit: This bit indicates if a peripheral interrupt event trigger has
occurred. This flag is automatically cleared when the first burst transfer begins.
0

No interrupt event trigger

1

Interrupt event trigger
The PERINTFRC bit can be used to set the state of this bit to 1 and force a software DMA event.
The PERINTCLR bit can be used to clear the state of this bit to 0.

7

ERRCLR

6-5

Reserved

0

Error Clear Bit: Writing a 1 to this bit will clear any latched sync error event and clear the
SYNCERR bit. This bit will also clear the OVRFLG bit. This bit would normally be used when
initializing the DMA for the first time or if an overflow condition is detected. If an ADCSYNC error
event or overflow event occurs at the same time as writing to this bit, the ADC or overrun has
priority and the SYNCERR or OVRFLG bit is set.
Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

649

Register Descriptions

www.ti.com

Table 4-9. Control Register (CONTROL) Field Descriptions (continued)
Bit

Field

Value Description

4

PERINTCLR

0

Peripheral Interrupt Clear Bit: Writing a 1 to this bit clears any latched peripheral interrupt event
and clears the PERINTFLG bit. This bit would normally be used when initializing the DMA for the
first time. If a peripheral event occurs at the same time as writing to this bit, the peripheral has
priority and the PERINTFLG bit is set.

3

PERINTFRC

0

Peripheral Interrupt Force Bit: Writing a 1 to this bit latches a peripheral interrupt event trigger
and sets the PERINTFLG bit. If the PERINTE bit is set, this bit can be used like a software force
for a DMA burst transfer.

2

SOFTRESET

0

Channel Soft Reset Bit: Writing a 1 to this bit completes current read-write access and places the
channel into a default state as follows:
RUNSTS = 0
TRANSFERSTS = 0
BURSTSTS = 0
BURST_COUNT = 0
TRANSFER_COUNT = 0
SRC_WRAP_COUNT = 0
DST_WRAP_COUNT = 0
This is a soft reset that basically allows the DMA to complete the current read-write access and
then places the DMA channel into the default reset state.

1

HALT

0

Channel Halt Bit: Writing a 1 to this bit halts the DMA at the current state and any current readwrite access is completed. See Figure 4-7 for the various positions the state machine can be at
when HALTED. The RUNSTS bit is set to 0. To take the device out of HALT, the RUN bit needs
to be activated.

0

RUN

0

Channel Run Bit: Writing a 1 to this bit starts the DMA channel. The RUNSTS bit is set to 1. This
bit is also used to take the device out of HALT.
The RUN bit is typically used to start the DMA running after you have configured the DMA. It will
then wait for the first interrupt event (PERINTFLG == 1) to start operation. The RUN bit can also
be used to take the DMA channel out of a HALT condition See Figure 4-7 for the various
positions the state machine can be at when HALTED.

650

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

4.8.8 Burst Size Register (BURST_SIZE) — EALLOW Protected
The burst size register (BURST_SIZE) is shown in Figure 4-16 and described in Table 4-10.
Figure 4-16. Burst Size Register (BURST_SIZE)
15

14

13

12

11

10
Reserved
R-0

9

8

7

6

5

4

3

2
1
BURSTSIZE
R/W-0

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-10. Burst Size Register (BURST_SIZE) Field Descriptions
Bit

Field

Value

15-5

Reserved

4-0

BURSTSIZE

Description
Reserved
These bits specify the burst transfer size:

0

Transfer 1 word in a burst

1

Transfer 2 words in a burst

...

...

31

Transfer 32 words in a burst

4.8.9 BURST_COUNT Register
The burst count register (BURST_COUNT) is shown in Figure 4-17 and described in Table 4-11.
Figure 4-17. Burst Size Register (BURST_COUNT)
15

14

13

12

11

10
Reserved
R-0

9

8

7

6

5

4

3

2
1
BURSTCOUNT
R/W-0

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-11. Burst Count Register (BURST_COUNT) Field Descriptions
Bit

Field

15-5

Reserved

4-0

BURSTCOUNT

Value

Description
Reserved
These bits indicate the current burst counter value:

0

0 word left in a burst

1

1 word left in a burst

2

2 words left in a burst

...

...

31

31 words left in a burst
The above values represent the state of the counter at the HALT conditions.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

651

Register Descriptions

www.ti.com

4.8.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected
The source burst step size register (SRC_BURST_STEP) is shown in Figure 4-18 and described in
Table 4-12.
Figure 4-18. Source Burst Step Size Register (SRC_BURST_STEP)
15

14

13

12

11

10

9

8
7
SRCBURSTSTEP
R/W-0

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-12. Source Burst Step Size Register (SRC_BURST_STEP) Field Descriptions
Bit
15-0

Field

Value

SRCBURSTSTEP

Description
These bits specify the source address post-increment/decrement step size while
processing a burst of data:

0x0FFF
...

Add 4095 to address
...

0x0002

Add 2 to address

0x0001

Add 1 to address

0x0000

No address change

0xFFFF

Sub 1 from address

0xFFFE

Sub 2 from address

...
0xF000

...
Sub 4096 from address
Only values from -4096 to 4095 are valid.

652

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

4.8.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected
The destination burst step register size (DST_BURST_STEP) is shown in Figure 4-19 and described in
Table 4-13.
Figure 4-19. Destination Burst Step Register Size (DST_BURST_STEP)
15

14

13

12

11

10

9

8
7
DSTBURSTSTEP
R/W-0

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-13. Destination Burst Step Register Size (DST_BURST_STEP) Field Descriptions
Bit
15-0

Field

Value

DSTBURSTSTEP

Description
These bits specify the destination address post-increment/decrement step size while
processing a burst of data:

0x0FFF
...

Add 4095 to address
...

0x0002

Add 2 to address

0x0001

Add 1 to address

0x0000

No address change

0xFFFF

Sub 1 from address

0xFFFE

Sub 2 from address

...

...

0xF000

Sub 4096 from address
Only values from -4096 to 4095 are valid.

4.8.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected
The transfer size register (TRANSFER_SIZE) is shown in Figure 4-20 and described in Table 4-14.
Figure 4-20. Transfer Size Register (TRANSFER_SIZE)
15

14

13

12

11

10

9

8
7
TRANSFERSIZE
R/W-0

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-14. Transfer Size Register (TRANSFER_SIZE) Field Descriptions
Bit
15-0

Field

Value

TRANSFERSIZE

Description
These bits specify the number of bursts to transfer:

0x0000

Transfer 1 burst

0x0001

Transfer 2 bursts

0x0002

Transfer 3 bursts

...
0xFFFF

...
Transfer 65536 bursts

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

653

Register Descriptions

www.ti.com

4.8.13 Transfer Count Register (TRANSFER_COUNT)
The transfer count register (TRANSFER_COUNT) is shown in Figure 4-21 and described in Table 4-15.
Figure 4-21. Transfer Count Register (TRANSFER_COUNT)
15

14

13

12

11

10

9

8
7
TRANSFERCOUNT
R/W-0

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-15. Transfer Count Register (TRANSFER_COUNT) Field Descriptions
Bit
15-0

Field

Value

Description

TRANSFERCOUNT

These bits specify the current transfer counter value:
0x0000

0 bursts left to transfer

0x0001

1 burst left to transfer

0x0002

2 bursts left to transfer

...

...

0xFFFF

65535 bursts left to transfer
The above values represent the state of the counter at the HALT conditions.

4.8.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected
The source transfer step size register (SRC_TRANSFER_STEP) is shown in Figure 4-22 and described in
Table 4-16.
Figure 4-22. Source Transfer Step Size Register (SRC_TRANSFER_STEP)
15

14

13

12

11

10

9

8
7
6
SRCTRANSFERSTEP
R/W-0

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-16. Source Transfer Step Size Register (SRC_TRANSFER_STEP) Field Descriptions
Bit
15-0

Field

Value

SRCTRANSFERSTEP

Description
These bits specify the source address pointer post-increment/decrement step
size after processing a burst of data:

0x0FFF
...

Add 4095 to address
...

0x0002

Add 2 to address

0x0001

Add 1 to address

0x0000

No address change

0xFFFF

Sub 1 from address

0xFFFE

Sub 2 from address

...
0xF000

...
Sub 4096 from address
Only values from -4096 to 4095 are valid.

654

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

4.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected
The destination transfer step size register (DST_TRANSFER_STEP) is shown in Figure 4-23 and
described in Table 4-17.
Figure 4-23. Destination Transfer Step Size Register (DST_TRANSFER_STEP)
15

14

13

12

11

10

9

8
7
6
DSTTRANSFERSTEP
R/W-0

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-17. Destination Transfer Step Size Register (DST_TRANSFER_STEP) Field Descriptions
Bit
15-0

Field

Value

Description

DSTTRANSFERSTEP

These bits specify the destination address pointer post-increment/decrement
step size after processing a burst of data:
0x0FFF

Add 4095 to address

...

...

0x0002

Add 2 to address

0x0001

Add 1 to address

0x0000

No address change

0xFFFF

Sub 1 from address

0xFFFE

Sub 2 from address

...

...

0xF000

Sub 4096 from address
Only values from -4096 to 4095 are valid.

4.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)
The source/destination wrap size register is shown in Figure 4-24 and described in Table 4-18.
Figure 4-24. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE)
15

14

13

12

11

10

9

8
7
WRAPSIZE
R/W-0

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-18. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) Field Descriptions
Bit
15-0

Field

Value

WRAPSIZE

Description
These bits specify the number of bursts to transfer before wrapping back to
begin address pointer:

0x0000

Wrap after 1 burst

0x0001

Wrap after 2 bursts

0x0002

Wrap after 3 bursts

...
0xFFFF

...
Wrap after 65536 bursts
To disable the wrap function, set the WRAPSIZE bit field to a number larger than
the TRANSFERSIZE bit field.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

655

Register Descriptions

www.ti.com

4.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)
The source/destination wrap count register (SCR/DST_WRAP_COUNT) is shown in Figure 4-25 and
described in Table 4-19.
Figure 4-25. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)
15

14

13

12

11

10

9

8
7
WRAPCOUNT
R/W-0

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-19. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) Field Descriptions
Bit
15-0

Field

Value

Description

WRAPCOUNT

These bits indicate the current wrap counter value:
0x0000

Wrap complete

0x0001

1 burst left

0x0002

2 burst left

...

...

0xFFFF

65535 burst left
The above values represent the state of the counter at the HALT conditions.

4.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW
Protected
The source/destination wrap step size register (SRC/DST_WRAP_STEP) are shown in Figure 4-26 and
described in Table 4-20.
Figure 4-26. Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP)
15

14

13

12

11

10

9

8
7
WRAPSTEP
R/W-0

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-20. Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) Field
Descriptions
Bit
15-0

Field

Value

WRAPSTEP

Description
These bits specify the source begin address pointer post-increment/decrement
step size after wrap counter expires:

0x0FFF
...

Add 4095 to address
...

0x0002

Add 2 to address

0x0001

Add 1 to address

0x0000

No address change

0xFFFF

Sub 1 from address

0xFFFE

Sub 2 from address

...
0xF000

...
Sub 4096 from address
Only values from -4096 to 4095 are valid.

656

Direct Memory Access (DMA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

4.8.19 Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected
The shadow source begin and current address pointer registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) are shown in Figure 4-27 and described in
Table 4-21.
Figure 4-27. Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BEGADDR
R/W-0

9

8

7

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-21. Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) Field Descriptions
Bit
31-0

Field

Value

BEGADDR

Description
32-bit address value

4.8.20 Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR)
The active source begin and current address pointer registers (SRC_BEG_ADDR/DST_BEG_ADDR) are
shown in Figure 4-28 and described in Table 4-22.
Figure 4-28. Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BEGADDR
R-0

9

8

7

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-22. Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR) Field Descriptions
Bit
31-0

Field
BEGADDR

Value

Description
32-bit address value

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Direct Memory Access (DMA)

657

Register Descriptions

www.ti.com

4.8.21 Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected
The shadow destination begin and current address pointer registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) are shown in Figure 4-29 and described in Table 4-23.
Figure 4-29. Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
RW-0

9

8

7

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-23. Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) Field Descriptions
Bit

Field

31-0

ADDR

Value

Description
32-bit address value

4.8.22 Active Destination Begin and Current Address Pointer Registers
(SRC_ADDR/DST_ADDR)
The active destination begin and current address pointer registers (SRC_ADDR/DST_ADDR) are shown in
Figure 4-30 and described in Table 4-24.
Figure 4-30. Active Destination Begin and Current Address Pointer Registers
(SRC_ADDR/DST_ADDR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R-0

9

8

7

6

5

4

3

2

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-24. Active Destination Begin and Current Address Pointer Registers
(SRC_ADDR/DST_ADDR) Field Descriptions
Bit

Field

31-0

ADDR

658

Value

Direct Memory Access (DMA)

Description
32-bit address value

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 5
SPRUHM8G – December 2013 – Revised September 2017

Control Law Accelerator (CLA)
The control law accelerator (CLA) Type-1 is an independent, fully-programmable, 32-bit floating-point math
processor that brings concurrent control-loop execution to the C28x family. The low interrupt-latency of the
CLA allows it to read ADC samples "just-in-time." This significantly reduces the ADC sample to output
delay to enable faster system response and higher MHz control loops. By using the CLA to service timecritical control loops, the main CPU is free to perform other system tasks such as communications and
diagnostics. This chapter provides an overview of the architectural structure and components of the
control law accelerator.
Topic

...........................................................................................................................

5.1
5.2
5.3
5.4
5.5
5.6
5.7

Control Law Accelerator (CLA) Overview.............................................................
CLA Interface ...................................................................................................
CLA and CPU Arbitration ...................................................................................
CLA Configuration and Debug ...........................................................................
Pipeline ...........................................................................................................
Instruction Set..................................................................................................
Registers .........................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

Page

660
662
666
668
672
677
792

659

Control Law Accelerator (CLA) Overview

5.1

www.ti.com

Control Law Accelerator (CLA) Overview
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Timecritical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA
enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks
frees up the main CPU to perform other system and communication functions concurrently. The following
is a list of major features of the CLA.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus
(DWAB), and Data Write Data Bus (DWDB)
– Independent eight stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0-MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU via the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus
on which the CLA assumes secondary ownership.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– The CLA, on reset, is the secondary master for all peripherals which can have either the CLA or
DMA as their secondary master.

660

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA) Overview

www.ti.com

Figure 5-1. CLA Block Diagram
CLA Control
Register Set
From
Shared
Peripherals

MPERINT1
to
MPERINT8

SYSCLK
CLA Clock Enable
SYSRSn

MIFR(16)
MIOVF(16)
MICLR(16)
MICLROVF(16)
MIFRC(16)
MIER(16)
MIRUN(16)
MVECT1(16)
MVECT2(16)
MVECT3(16)
MVECT4(16)
MVECT5(16)
MVECT6(16)
MVECT7(16)
MVECT8(16)

CLA_INT1
to
CLA_INT8
INT11
INT12

PIE

C28x
CPU

LVF
LUF

CPU Read/Write Data Bus

CLA Program Bus

CLA Program
Memory (LSx)

MCTL(16)

MPC(16)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
MAR0(16)
MAR1(16)

CLA Data Bus

CLA Execution
Register Set

CLA Data
Memory (LSx)

CPU Data Bus

LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]

CLA Message
RAMs
Shared
Peripherals

MEALLOW

CPU Read Data Bus

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

661

CLA Interface

5.2

www.ti.com

CLA Interface
This chapter describes how the C28x main CPU can interface to the CLA and vice versa.

5.2.1 CLA Memory
The CLA can access three types of memory: program, data and message RAMs. The behavior and
arbitration for each type of memory is described in detail below.
• CLA Program Memory
The CLA program can be loaded to any of the local shared memories (LSxRAM) on the core that it is
tied to. At reset, all memory blocks are mapped to the master CPU. While mapped to the CPU space,
the CPU can copy the CLA program code into the memory block(s). During debug, the block(s) can
also be loaded directly by Code Composer Studio™.
Once the memory is initialized with CLA code, the master CPU maps it to the CLA program space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a code block for the CLA by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit.
When an LSx memory is configured as CLA program memory, only debug accesses are allowed on
cycles that the CLA is not fetching a new instruction. A detailed explanation of the memory
configurations and access arbitration (CPU/CLA/DEBUG) process can be found in Section 2.11.
All CLA program fetches are performed as 32-bit read operations and all opcodes must be aligned to
an even address. Since all CLA opcodes are 32-bits, this alignment naturally occurs.
• CLA Data Memory
Any of the device’s LSxRAMs can serve as data memory blocks to the CLA. At reset, all blocks are
mapped to the master CPU memory space, whereby the master can initialize the memory with data
tables, coefficients, and so on, for the CLA to use.
Once the memory is initialized with CLA data, the master CPU maps it to the CLA data space by :
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a data block for the CLA by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. The value of this bit at reset is 0.
When an LSx memory is configured as a CLA data memory, the CLA read/write access are arbitrated
along with CPU accesses. The user has the option of turning on CPU fetch or write protection to the
memory by writing to the appropriate bits of the MemCfgRegs.LSxACCPROTx registers. A detailed
explanation of the memory configurations and access arbitration (CPU/CLA/DEBUG) process can be
found in Section 2.11.
The CLA RAMs and registers are protected by the security module. Refer to the DCSM chapter of this
manual for more details on the security scheme.
• CLA Shared Message RAMs
There are two small memory blocks for data sharing and communication between the CLA and the
master CPU on each CPU subsystem. The message RAMs are always mapped to both CPU and CLA
memory spaces and are protected by the DCSM. The message RAMs allow data accesses only; no
program fetches can be performed.
– CLA to CPU Message RAM
The CLA can use this block to pass data to the master CPU. This block is both readable and
writable by the CLA. This block is also readable by the master CPU but writes by the master CPU
are ignored
– CPU to CLA Message RAM
The master CPU can use this block to pass data and messages to the CLA. This message RAM is
both readable and writable by the master CPU. The CLA can perform reads but writes by the CLA
are ignored.

662

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CLA Interface

www.ti.com

5.2.2 CLA Memory Bus
The CLA has dedicated bus architecture similar to that of the C28x CPU where there is a program read,
data read, and data write bus. Thus, there can be simultaneous instruction fetch, data read, and data write
in a single cycle. Like the C28x CPU, the CLA expects memory logic to align any 32-bit read or write to an
even address. If the address-generation logic generates an odd address, the CLA will begin reading or
writing at the previous even address. This alignment does not affect the address values generated by the
address-generation logic.
• CLA Program Bus
The CLA program bus has a access range of 32K 32-bit instructions. Since all CLA instructions are 32
bits, this bus always fetches 32 bits at a time and the opcodes must be even-word aligned. The
amount of program space available for the CLA is limited to the number of available LSxRAM blocks.
This number is device-dependent and will be described in the device-specific data manual.
• CLA Data Read Bus
The CLA data read bus has a 64K x 16 address range. The bus can perform 16 or 32-bit reads and
will automatically stall if there are memory access conflicts. The data read bus has access to both the
message RAMs, CLA data memory, and the shared peripherals.
• CLA Data Write Bus
The CLA data write bus has a 64K x 16 address range. This bus can perform 16 or 32-bit writes. The
bus will automatically stall if there are memory access conflicts. The data write bus has access to the
CLA to CPU message RAM, CLA data memory, and the shared peripherals.

5.2.3 Shared Peripherals and EALLOW Protection
For a given CPU subsystem, the CLA and DMA share secondary access to some peripherals. The
secondary ownership of the bus is determined by the CpuSysRegs.SECMSEL[VBUS32_x] bit. If it is set to
0, the CLA is the secondary owner. If it is set to 1, the DMA is the secondary owner. By default, at reset,
the CLA is given the secondary ownership of the bus and, therefore, can access all the peripherals
connected to it.
Note: The CLA read access time to the bus is 2-wait states while write access is 0-wait.
Refer to the device data manual for the list of peripherals connected to the bus.
Several peripheral control registers are protected from spurious 28x CPU writes by the EALLOW
protection mechanism. These same registers are also protected from spurious CLA writes. The EALLOW
bit in the main CPU status register 1 (ST1) indicates the state of protection for the main CPU. Likewise the
MEALLOW bit in the CLA status register (MSTF) indicates the state of write protection for the CLA. The
MEALLOW CLA instruction enables write access by the CLA to EALLOW protected registers. Likewise the
MEDIS CLA instruction will disable write access. This way the CLA can enable/disable write access
independent of the main CPU.
The ADC offers the option to generate an early interrupt pulse at the start of a sample conversion. If this
option is used to start an ADC-triggered CLA task, the user may use the intervening cycles, until the
completion of the conversion, to perform preliminary calculations or loads and stores before finally reading
the ADC value. The CLA pipeline activity for this scenario is shown in Section 5.5.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

663

CLA Interface

www.ti.com

5.2.4 CLA Tasks and Interrupt Vectors
The CLA program code is divided up into tasks or interrupt service routines. Tasks do not have a fixed
starting location or length. The CLA program memory can be divided up as desired. The CLA knows
where a task begins by the content of the associated interrupt vector (MVECT1 to MVECT8) and the end
is indicated by the MSTOP instruction.
The CLA supports eight tasks. Task 1 has the highest priority and task 8 has the lowest priority. A task
can be requested by a peripheral interrupt or by software:
• Peripheral interrupt trigger
Each task can be triggered by up to 256 interrupt sources. The trigger for each task is defined by
writing an appropriate value to the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field. Each of
the possible 256 values specifies an interrupt source from a specific peripheral on the shared bus. The
configuration options are listed in Table 5-1.
Table 5-1. Configuration Options
Select Value (8-bit)

CLA Trigger Source

0

Software Trigger

1

ADCAINT1

2

ADCAINT2

3

ADCAINT3

4

ADCAINT4

5

ADCAEVT

6

ADCBINT1

7

ADCBINT2

8

ADCBINT3

9

ADCBINT4

664 Control Law Accelerator (CLA)

10

ADCBEVT

11

ADCCINT1

12

ADCCINT2

13

ADCCINT3

14

ADCCINT4

15

ADCCEVT

16

ADCDINT1

17

ADCDINT2

18

ADCDINT3

19

ADCDINT4

20

ADCDEVT

28:21

Reserved

29

XINT1

30

XINT2

31

XINT3

32

XINT4

33

XINT5

34

Reserved

35

Reserved

36

EPWM1INT

37

EPWM2INT

38

EPWM3INT

39

EPWM4INT

40

EPWM5INT

41

EPWM6INT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CLA Interface

www.ti.com

Table 5-1. Configuration Options (continued)
Select Value (8-bit)

CLA Trigger Source

42

EPWM7INT

43

EPWM8INT

44

EPWM9INT

45

EPWM10INT

46

EPWM11NT

47

EPWM12INT

67:48

Reserved

68

TINT0

69

TINT1

70

TINT2

71

MXINTA

72

MRINTA

73

MXINTB

74

MRINTB

75

ECAP1INT

76

ECAP2INT

77

ECAP3INT

78

ECAP4INT

79

ECAP5INT

80

ECAP6INT

81

Reserved

82

Reserved

83

EQEP1INT

84

EQEP2INT

85

EQEP3INT

86

Reserved

87

Reserved

88

Reserved

94:89

Reserved

95

SD1INT

96

SD2INT

106:97

Reserved

107

UPP1INT

108

Reserved

109

SPITXINTA

110

SPIRXINTA

111

SPITXINTB

112

SPIRXINTB

113

SPITXINTC

114

SPIRXINTC

255:115

Reserved

For example, task 1 (MVECT1) can be set to trigger on EPWMINT1 by writing 36 to
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1. To disable the triggering of a task by a
peripheral, the user must set the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field to 0. It
should be noted that a CLA task only triggers on a level transition (an edge) of the configured interrupt
source.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

665

CLA Interface

•

www.ti.com

Software Trigger
Tasks can also be started by the main CPU software writing to the MIFRC register or by the IACK
instruction. Using the IACK instruction is more efficient because it does not require you to issue an
EALLOW to set MIFR bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the
operand of the IACK instruction corresponds to a task. For example IACK #0x0001 will set bit 0 in the
MIFR register to start task 1. Likewise IACK #0x0003 will set bits 0 and 1 in the MIFR register to start
task 1 and task 2.

The CLA has its own fetch mechanism and can run and execute a task independent of the main CPU.
Only one task is serviced at a time; there is no nesting of tasks. The task currently running is indicated in
the MIRUN register. Interrupts that have been received but not yet serviced are indicated in the flag
register (MIFR). If an interrupt request from a peripheral is received and that same task is already flagged,
then the overflow flag bit is set. Overflow flags will remain set until they are cleared by the main CPU.
If the CLA is idle (no task is currently running) then the highest priority interrupt request that is both
flagged (MIFR) and enabled (MIER) will start. The flow is as follows:
1. The associated RUN register bit is set (MIRUN) and the flag bit (MIFR) is cleared.
2. The CLA begins execution at the location indicated by the associated interrupt vector (MVECTx).
MVECT contains the absolute 16-bit address of the task in the lower 64K memory space.
3. The CLA executes instructions until the MSTOP instruction is found. This indicates the end of the task.
4. The MIRUN bit is cleared.
5. The task-specific interrupt to the PIE is issued. This informs the main CPU that the task has
completed.
6. The CLA returns to idle.
Once a task completes the next highest-priority pending task is automatically serviced and this sequence
repeats.

5.2.5 CLA Software Interrupt to CPU
The CLA can issue a software interrupt to the C28x CPU (on the same subsystem) at any point in the
code through the use of the CLA1SOFTINTEN and CLA1INTFRC registers. Please see Section 5.7 for a
description of these registers. If a software interrupt is selected for a CLA task, then an end-of-task
interrupt will not be issued to the C28x when that task completes

5.3

CLA and CPU Arbitration
Typically, CLA activity is independent of the CPU activity. Under the circumstance where both the CLA
and the CPU are attempting to access memory or a peripheral register within the same interface
concurrently, an arbitration procedure will occur. This appendix describes this arbitration.

5.3.1 CLA and CPU Arbitration
The Local Shared RAMs can have access from the CPU as well as the DMA. The arbitration is a
combination of fixed and round robin schemes; they are covered in detail in the Section 2.11.

5.3.2 CLA Message RAM
Message RAMs consist of two blocks per CPU subsystem
• CPUx.CLA1 to CPUx – CLA to CPU Message RAM
• CPUx to CPUx.CLA1 – CPU to CLA Message RAM
These blocks are for passing data between the CPU and the CLA. No opcode fetches, from either the
CLA or CPU, are allowed from the message RAMs. A write protection violation will not be generated if the
CLA attempts to write to the CPUx to CPUx.CLA1 message RAM but the write will be ignored. The
arbitration scheme for the message RAMs are the same as those for the shared memories described in
the Section 2.11.
The two message RAMs have the following characteristics:
666

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CLA and CPU Arbitration

www.ti.com

•

•

CPUx.CLA1 to CPUx Message RAM:
The following accesses are allowed:
– CPUx reads
– CPUx.CLA1 data reads and writes
– CPUx debug reads and writes
The following accesses are ignored:
– CPUx writes
CPUx to CPUx.CLA1 Message RAM:
The following accesses are allowed:
– CPUx reads and writes
– CPUx.CLA1 reads
– CPUx debug reads and writes
The following accesses are ignored:
– CPUx.CLA1 writes

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

667

CLA Configuration and Debug

5.4

www.ti.com

CLA Configuration and Debug
This section discusses the steps necessary to configure and debug the CLA.

5.4.1 Building a CLA Application
The control law accelerator can be programmed in either CLA assembly code using the instructions
described in Section 5.6 or a reduced subset of the C language. CLA assembly code resides in the same
project with C28x code. The only restriction is the CLA code must be in its own assembly section. This
can be easily done using the .sect assembly directive. This does not prevent CLA and C28x code from
being linked into the same memory region in the linker command file.
System and CLA initialization are performed by the main CPU. This would typically be done in C or C++
but can also include C28x assembly code. The main CPU will also copy the CLA code to the program
memory and, if needed, initialize the CLA data RAM(s). Once system initialization is complete and the
application begins, the CLA will service its interrupts using the CLA assembly code (or tasks).
Concurrently the main CPU can perform other tasks.
The CLA type 1 requires Codegen V6.2.4 or later with the following switch: --cla_support=cla1.

5.4.2 Typical CLA Initialization Sequence
A typical CLA initialization sequence is performed by the main CPU as described in this section.
1. Copy CLA code into the CLA program RAM
The source for the CLA code can initially reside in the flash or a data stream from a communications
peripheral or anywhere the main CPU can access it. The debugger can also be used to load code
directly to the CLA program RAM during development.
2. Initialize CLA data RAM if necessary
Populate the CLA data RAM with any required data coefficients or constants.
3. Configure the CLA registers
Configure the CLA registers, but keep interrupts disabled until later (leave MIER == 0):
• Enable the CLA clock in the PCLKCR0 register.
PCLKCR0 register is defined in the System Control and Interrupts chapter.
• Populate the CLA task interrupt vectors: MVECT1 to MVECT8.
Each vector needs to be initialized with the start address of the task to be executed when the CLA
receives the associated interrupt. This address is the full 16-bit starting address of the task in the
lower 64K section of memory.
• Select the task interrupt sources
For each task select the interrupt source in the CLA1TASKSRCSELx register. If a task is going to
be generated by software, select no interrupt.
• Enable IACK to start a task from software if desired
To enable the IACK instruction to start a task set the MCTL[IACKE] bit. Using the IACK instruction
avoids having to set and clear the EALLOW bit.
• Map CLA data RAM(s) to CLA space if necessary
Map the data RAM to the CLA space by first, assigning ownership of the memory block to the CLA
by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit and then specifying
the memory block as a CLA data block by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. When an LSx memory is configured as a CLA data
memory, the CLA read/write access are arbitrated along with CPU accesses. The user has the
option of turning on CPU fetch or write protection to the memory by writing to the appropriate bits of
the MemCfgRegs. LSxACCPROTx registers.
• Map CLA program RAM to CLA space
Map the CLA program RAM to CLA space by first, assigning ownership of the memory block to the
CLA by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit and then
specifying the memory block as CLA code memory by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. When an LSx memory is configured as CLA
668

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CLA Configuration and Debug

www.ti.com

program memory, only debug accesses are allowed on cycles that the CLA is not fetching a new
instruction.
4. Initialize the PIE vector table and registers
When a CLA task completes, the associated interrupt in the PIE will be flagged. The CLA overflow and
underflow flags also have associated interrupts within the PIE.
5. Enable CLA tasks/interrupts
Set appropriate bits in the interrupt enable register (MIER) to allow the CLA to service interrupts.
6. Initialize other peripherals
Initialize any peripherals (ePWM, ADC, and others) that will generate an interrupt to the CLA and be
serviced by a CLA task.
The CLA is now ready to service interrupts and the message RAMs can be used to pass data between
the CPU and the CLA. Typically mapping of the CLA program and data RAMs occurs only during the
initialization process. If after some time the you want to re-map these memories back to CPU space
then disable interrupts and make sure all tasks have completed by checking the MIRUN register.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

669

CLA Configuration and Debug

www.ti.com

5.4.3 Debugging CLA Code
Debugging the CLA code is a simple process that occurs independently of the main CPU.
1. Insert a breakpoint in CLA code
Insert a CLA breakpoint (MDEBUGSTOP instruction) into the code where you want the CLA to halt,
then rebuild and reload the code. Because the CLA does not flush its pipeline when you single-step,
the MDEBUGSTOP instruction must be inserted as part of the code. The debugger cannot insert it as
needed.
If CLA breakpoints are not enabled, then the MDEBUGSTOP will be ignored and is treated as a
MNOP. The MDEBUGSTOP instruction can be placed anywhere in the CLA code as long as it is not
within three instructions of a MBCNDD, MCCNDD, or MRCNDD instruction. When programming in C,
the user can use the __mdebugstop() intrinsic instead; the compiler will ensure that the placement of
the MDEBUSTOP instruction in the generated assembly does not violate any of the pipeline
restrictions.
2. Enable CLA breakpoints
First, enable the CLA breakpoints in the debugger. In Code Composer Studio, this is done by
connecting the core from the debug perspective. Breakpoints are disabled when the core is
disconnected.
3. Start the task
There are three ways to start the task:
• The peripheral can assert an interrupt
• The main CPU can execute an IACK instruction, or
• You can manually write to the MIFRC register in the debugger window
When the task starts, the CLA will execute instructions until the MDEBUGSTOP is in the D2 phase of
the pipeline. At this point, the CLA will halt and the pipeline will be frozen. The MPC register will reflect
the address of the MDEBUGSTOP instruction.
4. Single-step the CLA code
Once halted, you can single-step the CLA code one cycle at a time. The behavior of a CLA single-step
is different than the main C28x. When issuing a CLA single-step, the pipeline is clocked only one cycle
and then again frozen. On the 28x CPU, the pipeline is flushed for each single-step.
You can also run to the next MDEBUGSTOP or to the end of the task. If another task is pending, it will
automatically start when you run to the end of the task.
NOTE: A CLA fetch has higher priority than CPU debug reads. For this reason, it is possible for the
CLA to permanently block CPU debug accesses if the CLA is executing in a loop. This might
occur when initially developing CLA code due to a bug that causes an infinite loop. To avoid
locking up the main CPU, the program memory will return all 0x0000 for CPU debug reads
when the CLA is running. When the CLA is halted or idle then normal CPU debug read and
write access to CLA program memory can be performed.
If the CLA gets caught in a infinite loop, you can use a soft or hard reset to exit the condition.
A debugger reset will also exit the condition.

There are special cases that can occur when single-stepping a task such that the program counter,
MPC, reaches the MSTOP instruction at the end of the task.
• MPC halts at or after the MSTOP with a task already pending
If you are single-stepping or halted in "task A" and "task B" comes in before the MPC reaches the
MSTOP, then "task B" will start if you continue to step through the MSTOP instruction. Basically if
"task B" is pending before the MPC reaches MSTOP in "task A" then there is no issue in "task B"
starting and no special action is required.
• MPC halts at or after the MSTOP with no task pending
In this case you have single-stepped or halted in "task A" and the MPC has reached the MSTOP
with no tasks pending. If "task B" comes in at this point, it will be flagged in the MIFR register but it
may or may not start if you continue to single-step through the MSTOP instruction of "task A."
It depends on exactly when the new task comes in. To reliably start "task B" perform a soft reset
670

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CLA Configuration and Debug

www.ti.com

and reconfigure the MIER bits. Once this is done, you can start single-stepping "task B."
This case can be handled slightly differently if there is control over when "task B" comes in (for
example using the IACK instruction to start the task). In this case you have single-stepped or halted
in "task A" and the MPC has reached the MSTOP with no tasks pending. Before forcing "task B,"
run free to force the CLA out of the debug state. Once this is done you can force "task B" and
continue debugging.
5. If desired, disable CLA breakpoints
In Code Composer Studio you can disable the CLA breakpoints by disconnecting the CLA core in the
debug perspective. Make sure to first issue a run or reset; otherwise, the CLA will be halted and no
other tasks will start.

5.4.4 CLA Illegal Opcode Behavior
If the CLA fetches an opcode that does not correspond to a legal instruction, it will behave as follows:
• The CLA will halt with the illegal opcode in the D2 phase of the pipeline as if it were a breakpoint. This
will occur whether CLA breakpoints are enabled or not.
• The CLA will issue the task-specific interrupt to the PIE.
• The MIRUN bit for the task will remain set.
Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation,
issue either a soft or hard reset of the CLA as described in Section 5.4.5.

5.4.5 Resetting the CLA
There may be times when you need to reset the CLA. For example, during code debug the CLA may enter
an infinite loop due to a code bug. The CLA has two types of resets: hard and soft. Both of these resets
can be performed by the debugger or by the main CPU.
• Hard Reset
Writing a 1 to the MCTL[HARDRESET] bit will perform a hard reset of the CLA. The behavior of a hard
reset is the same as a system reset (via XRS or the debugger). In this case all CLA configuration and
execution registers will be set to their default state and CLA execution will halt.
• Soft Reset
Writing a 1 to the MCTL[SOFTRESET] bit performs a soft reset of the CLA. If a task is executing it will
halt and the associated MIRUN bit will be cleared. All bits within the interrupt enable (MIER) register
will also be cleared so that no new tasks start.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

671

Pipeline

5.5

www.ti.com

Pipeline
This section describes the CLA pipeline stages and presents cases where pipeline alignment must be
considered.

5.5.1 Pipeline Overview
The CLA pipeline is very similar to the C28x pipeline. The pipeline has eight stages:
• Fetch 1 (F1)
During the F1 stage the program read address is placed on the CLA program address bus.
• Fetch 2 (F2)
During the F2 stage the instruction is read using the CLA program data bus.
• Decode 1 (D1)
During D1 the instruction is decoded.
• Decode 2 (D2)
Generate the data read address. Changes to MAR0 and MAR1 due to post-increment using indirect
addressing takes place in the D2 phase. Conditional branch decisions are also made at this stage
based on the MSTF register flags.
• Read 1 (R1)
Place the data read address on the CLA data-read address bus. If a memory conflict exists, the R1
stage will be stalled.
• Read 2 (R2)
Read the data value using the CLA data read data bus.
• Execute (EXE)
Execute the operation. Changes to MAR0 and MAR1 due to loading an immediate value or value from
memory take place in this stage.
• Write (W)
Place the write address and write data on the CLA write data bus. If a memory conflict exists, the W
stage will be stalled.

5.5.2 CLA Pipeline Alignment
The majority of the CLA instructions do not require any special pipeline considerations. This section lists
the few operations that do require special consideration.
• Write Followed by Read
In both the C28x and the CLA pipeline the read operation occurs before the write. This means that if a
read operation immediately follows a write, then the read will complete first as shown in Table 5-2. In
most cases this does not cause a problem since the contents of one memory location does not depend
on the state of another. For accesses to peripherals where a write to one location can affect the value
in another location the code must wait for the write to complete before issuing the read as shown in
Table 5-3.
This behavior is different for the 28x CPU. For the 28x CPU any write followed by read to the same
location is protected by what is called write-followed-by-read protection. This protection automatically
stalls the pipeline so that the write will complete before the read. In addition some peripheral frames
are protected such that a 28x CPU write to one location within the frame will always complete before a
read to the frame. The CLA does not have this protection mechanism. Instead the code must wait to
perform the read.

672 Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Pipeline

www.ti.com

Table 5-2. Write Followed by Read - Read Occurs First
Instruction

F1

I1 MMOV16 @Reg1, MR3

I1

I2 MMOV16 MR2, @Reg2

I2

F2

D1

D2

R1

R2

E

W

I1
I2

I1
I2

I1
I2

I1
I2

I1
I2

I1
I2

I1

Table 5-3. Write Followed by Read - Write Occurs First
Instruction

F1

I1 MMOV16 @Reg1, MR3

I1

F2

D1

D2

R1

R2

E

I2

I2

I1

I3

I3

I2

I1

I4

I4

I3

I2

I1

I5 MMOV16 MR2, @Reg2

I5

I4

I3

I2

I1

I5

I4

I3

I2

I1

I5

I4

I3

I2

I1

I5

I4

I3

I2

I5

I4

I3

I5

I4

W

I1

I5

•

Delayed Conditional instructions: MBCNDD, MCCNDD and MRCNDD
Referring to Example 5-1, the following applies to delayed conditional instructions:
– I1
I1 is the last instruction that can effect the CNDF flags for the branch, call or return instruction. The
CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is made whether to
branch or not when MBCNDD, MCCNDD or MRCNDD is in the D2 phase.
– I2, I3 and I4
The three instructions preceding MBCNDD can change MSTF flags but will have no effect on
whether the MBCNDD instruction branches or not. This is because the flag modification will occur
after the D2 phase of the branch, call or return instruction. These three instructions must not be a
MSTOP, MDEBUGSTOP, MBCNDD, MCCNDD or MRCNDD.
– I5, I6 and I7
The three instructions following a branch, call or return are always executed irrespective of whether
the condition is true or not. These instructions must not be MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD or MRCNDD.
For a more detailed description refer to the functional description for MBCNDD, MCCNDD and
MRCNDD.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

673

Pipeline

www.ti.com

Example 5-1. Code Fragment For MBCNDD, MCCNDD or MRCNDD



; I1 Last instruction that can affect flags for
;
the branch, call or return operation





; I2 Cannot be stop, branch, call or return
; I3 Cannot be stop, branch, call or return
; I4 Cannot be stop, branch, call or return



; MBCNDD, MCCNDD or MRCNDD
; I5-I7: Three instructions after are always
; executed whether the branch/call or return is
; taken or not





; I5 Cannot be stop, branch, call or return
; I6 Cannot be stop, branch, call or return
; I7 Cannot be stop, branch, call or return



....

; I8
; I9

•

•

Stop or Halting a Task: MSTOP and MDEBUGSTOP
The MSTOP and MDEBUGSTOP instructions cannot be placed three instructions before or after a
conditional branch, call or return instruction (MBCNDD, MCCNDD or MRCNDD). Refer to Example 5-1.
To single-step through a branch/call or return, insert the MDEBUGSTOP at least four instructions back
and step from there.
Loading MAR0 or MAR1
A load of auxiliary register MAR0 or MAR1 will occur in the EXE phase of the pipeline. Any post
increment of MAR0 or MAR1 using indirect addressing will occur in the D2 phase of the pipeline.
Referring to Example 5-2, the following applies when loading the auxiliary registers:
– I1 and I2
The two instructions following the load instruction will use the value in MAR0 or MAR1 before the
update occurs.
– I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-increment
addressing occur in the D2 phase. Thus I3 cannot use the auxiliary register or there will be a
conflict. In the case of a conflict, the update due to address-mode post increment will win and the
auxiliary register will not be updated with #_X.
– I4
Starting with the 4th instruction MAR0 or MAR1 will have the new value.

Example 5-2. Code Fragment for Loading MAR0 or MAR1
; Assume MAR0 is 50 and #_X is 20
MMOVI16 MAR0, #_X





....

674

;
;
;
;
;
;

Load MAR0 with address of
I1 Will use the old value
I2 Will use the old value
I3 Cannot use MAR0
I4 Will use the new value
I5 Will use the new value

Control Law Accelerator (CLA)

X (20)
of MAR0 (50)
of MAR0 (50)
of MAR0 (20)
of MAR0 (20

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Pipeline

www.ti.com

5.5.2.1

ADC Early Interrupt to CLA Response

The ADC offers the option to generate an early interrupt pulse when the ADC begins conversion. This
option is selected by setting the ADCCTL1[INTPULSEPOS] bit as documented in the Analog-to-Digital
Converter and Comparator section in this manual. If this option is used to start a CLA task then the CLA
will be able to read the result as soon as the conversion completes and the ADC result register updates.
This just-in-time sampling along with the low interrupt response of the CLA enable faster system response
and higher frequency control loops.
The timing for the ADC conversion is shown in the ADC Reference Guide timing diagrams. If the ADCCLK
is a divided down version of the SYSCLK, the user will have to account for the conversion time in
SYSCLK cycles. For example, if using the 12-bit ADC with ADCCLK at ¼ SYSCLK, it would take 10.5
ADCCLK (42 SYSCLK) cycles to complete a conversion. If using the ADC in 16-bit mode at the same
ADCCLK, it would take 29.5 ADCCLK (118 SYSCLK) cycles, and so on.
From a CLA perspective, the pipeline activity is shown in Table 5-4 an n-cycle (SYSCLK) conversion. The
nth-2 instruction is in the R2 phase just in time to read the result register. While the previous n-3
instructions in the task (I1 to In-3) will enter the R2 phase of the pipeline too soon to read the conversion,
they can be efficiently used for pre-processing calculations needed by the task.
Table 5-4. ADC to CLA Early Interrupt Response
ADC Activity

CLA Activity

F1

F2

D1

D2

R1

R2

...

...

...

E

W

Sample
Sample
...
Sample
Conversion (1)

Interrupt Received

Conversion (2)

Task Startup

Conversion (3)

Task Startup

Conversion (4)

I1

I1

Conversion (5)

I2

I2

I1

Conversion (6)

I3

I3

I2

I1

Conversion (7)

...

...

...

...

Conversion (n-6)

I(n-6)

I(n-6)

Conversion (n-5)

I(n-5)

I(n-5)

I(n-6)

Conversion (n-4)

I(n-4)

I(n-4)

I(n-5)

I(n-6)

Conversion (n-3)

I(n-3)

I(n-3)

I(n-4)

I(n-5)

I(n-6)

Conversion (n-2)

l(n-2) Read ADC RESULT

l(n-2)

I(n-3)

I(n-4)

I(n-5)

I(n-6)

l(n-2

I(n-3)

I(n-4)

I(n-5)

I(n-6)

l(n-2)

I(n-3)

I(n-4)

I(n-5)

l(n-2)

I(n-3)

I(n-4)

l(n-2)

I(n-3)

Conversion (n-1)
Conversion (n)
Conversion Complete
RESULT Latched
RESULT Available

I(n-2)

5.5.3 Parallel Instructions
Parallel instructions are single opcodes that perform two operations in parallel. The following types of
parallel instructions are available: math operation in parallel with a move operation, or two math
operations in parallel. Both operations complete in a single cycle and there are no special pipeline
alignment requirements.
Example 5-3. Math Operation with Parallel Load

;
;
;

MADDF32 || MMOV32 instruction: 32-bit floating-point add with parallel move
MADDF32 is a 1 cycle operation
MMOV32 is a 1 cycle operation
MADDF32
MR0, MR1, #2
; MR0 = MR1 + 2,

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

675

Pipeline

www.ti.com

Example 5-3. Math Operation with Parallel Load (continued)
|| MMOV32

MR1,

@Val

MMPYF32 MR0, MR0, MR1

;
;
;
;

MR1
<-<-Any

gets the contents of Val
MMOV32 completes here (MR1 is valid)
DDF32 completes here (MR0 is valid)
instruction, can use MR1 and/or MR0

Example 5-4. Multiply with Parallel Add

;
;
;

MMPYF32 || MADDF32 instruction: 32-bit floating-point multiply with parallel add
MMPYF32 is a 1 cycle operation
MADDF32 is a 1 cycle operation
MMPYF32 MR0, MR1, MR3
; MR0 = MR1 * MR3
|| MADDF32 MR1, MR2, MR0
; MR1 = MR2 + MR0 (Uses value of MR0 before MMPYF32)
; <-- MMPYF32 and MADDF32 complete here (MR0 and MR1 are valid)
MMPYF32 MR1, MR1, MR0
; Any instruction, can use MR1 and/or MR0

676

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

5.6

Instruction Set
This section describes the assembly language instructions of the control law accelerator. Also described
are parallel operations, conditional operations, resource constraints, and addressing modes. The
instructions listed here are independent from C28x and C28x+FPU instruction sets.

5.6.1 Instruction Descriptions
This section gives detailed information on the instruction set. Each instruction may present the following
information:
• Operands
• Opcode
• Description
• Exceptions
• Pipeline
• Examples
• See also
The example INSTRUCTION is shown to familiarize you with the way each instruction is described. The
example describes the kind of information you will find in each part of the individual instruction description
and where to obtain more information. CLA instructions follow the same format as the C28x; the source
operand(s) are always on the right and the destination operand(s) are on the left.
The explanations for the syntax of the operands used in the instruction descriptions for the C28x CLA are
given in Table 5-5.
Table 5-5. Operand Nomenclature
Symbol

Description

#16FHi

16-bit immediate (hex or float) value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.

#16FHiHex

16-bit immediate hex value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.

#16FLoHex

A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit floating-point value

#32Fhex

32-bit immediate value that represents an IEEE 32-bit floating-point value

#32F

Immediate float value represented in floating-point representation

#0.0

Immediate zero

#SHIFT

Immediate value of 1 to 32 used for arithmetic and logical shifts.

addr

Opcode field indicating the addressing mode

CNDF

Condition to test the flags in the MSTF register

FLAG

Selected flags from MSTF register (OR) 8 bit mask indicating which floating-point status flags to change

MAR0

auxiliary register 0

MAR1

auxiliary register 1

MARx

Either MAR0 or MAR1

mem16

16-bit memory location accessed using direct, indirect, or offset addressing modes

mem32

32-bit memory location accessed using direct, indirect, or offset addressing modes

MRa

MR0 to MR3 registers

MRb

MR0 to MR3 registers

MRc

MR0 to MR3 registers

MRd

MR0 to MR3 registers

MRe

MR0 to MR3 registers

MRf

MR0 to MR3 registers

MSTF

CLA Floating-point Status Register

shift

Opcode field indicating the number of bits to shift.

VALUE

Flag value of 0 or 1 for selected flag (OR) 8 bit mask indicating the flag value; 0 or 1

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA) 677

Instruction Set

www.ti.com

Each instruction has a table that gives a list of the operands and a short description. Instructions always
have their destination operand(s) first followed by the source operand(s).
Table 5-6. INSTRUCTION dest, source1, source2 Short Description
Description

678

dest1

Description for the 1st operand for the instruction

source1

Description for the 2nd operand for the instruction

source2

Description for the 3rd operand for the instruction

Opcode

This section shows the opcode for the instruction

Description

Detailed description of the instruction execution is described. Any constraints on the operands imposed by
the processor or the assembler are discussed.

Restrictions

Any constraints on the operands or use of the instruction imposed by the processor are discussed.

Pipeline

This section describes the instruction in terms of pipeline cycles as described in Section 5.5

Example

Examples of instruction execution. If applicable, register and memory values are given before and after
instruction execution. Some examples are code fragments while other examples are full tasks that assume
the CLA is correctly configured and the main CPU has passed it data.

Operands

Each instruction has a table that gives a list of the operands and a short description. Instructions always
have their destination operand(s) first followed by the source operand(s).

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

5.6.2 Addressing Modes and Encoding
The CLA uses the same address to access data and registers as the main CPU. For example if the main
CPU accesses an ePWM register at address 0x00 6800, then the CLA will access it using address
0x6800. Since all CLA accessible memory and registers are within the low 64k x 16 of memory, only the
low 16-bits of the address are used by the CLA.
To address the CLA data memory, message RAMs and shared peripherals, the CLA supports two
addressing modes:
• Direct addressing mode: Uses the address of the variable or register directly.
• Indirect addressing with 16-bit post increment. This mode uses either XAR0 or XAR1.
The CLA does not use a data page pointer or a stack pointer. The two addressing modes are encoded as
shown Table 5-7.
Table 5-7. Addressing Modes
Addressing Mode

'addr' Opcode
Field
Encode (1)

Description

@dir

0000

Direct Addressing Mode
Example 1: MMOV32 MR1, @_VarA
Example 2: MMOV32 MR1, @_EPwm1Regs.CMPA.all
In this case the 'mmmm mmmm mmmm mmmm' opcode field will be populated with the
16-bit address of the variable. This is the low 16-bits of the address that you would use to
access the variable using the main CPU.
For example @_VarA will populate the address of the variable VarA. and
@_EPwm1Regs.CMPA.all will populate the address of the CMPA register.

*MAR0[#imm16]++

0001

MAR0 Indirect Addressing with 16-bit Immediate Post Increment

*MAR1[#imm16]++

0010

MAR1 Indirect Addressing with 16-bit Immediate Post Increment
addr = MAR0 (or MAR1)
MAR0 (or MAR1) +=
#imm16

Access memory using the address stored in MAR0 (or MAR1).
Then post increment MAR0 (or MAR1) by #imm16.

Example 1: MMOV32 MR0, *MAR0[2]++
Example 2: MMOV32 MR1, *MAR1[-2]++
For a post increment of 0 the assembler will accept both *MAR0 and *MAR0[0]++.
The 'mmmm mmmm mmmm mmmm' opcode field will be populated with the signed 16-bit
pointer offset. For example if #imm16 is 2, then the opcode field will be 0x0002. Likewise if
#imm16 is -2, then the opcode field will be 0xFFFE.
If addition of the 16-bit immediate causes overflow, then the value will wrap around on a
16-bit boundary.
*MAR0+[#imm16]

0101

MAR0 Offset Addressing with 16-bit Immediate Offset

*MAR1+[#imm16]

0110

MAR1 Offset Addressing with 16-bit Immediate Offset
addr = MAR0
(or MAR1) + #imm16to
the base

Add the offset #imm16
address stored in MAR0(MAR1) to access the desired memory
location

Example 1: MMOV32 MR0, *MAR0+[2]
Example 1: MMOV32 MR1, *MAR1+[-2]
The ‘mmmm mmmm mmmm mmmm’ opcode field will be populated with the signed 16-bit
pointer offset. For example if #imm16 is 2, then the opcode field will be 0x0002. Likewise if
#imm16 is -2, then the opcode field will be 0xFFFE.
If the addition of the 16-bit immediate causes overflow, the value will wrap around on a 16bit boundary.
(1)

Values not shown are reserved.

Encoding for the shift fields in the MASR32, MLSR32 and MLSL32 instructions is shown in Table 5-8

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

679

Instruction Set

www.ti.com

Table 5-8. Shift Field Encoding
Shift Value

'shift' Opcode
Field Encode

1

0000

2

0001

3

0010

....

....

32

1111

Table 5-10 shows the condition field encoding for conditional instructions such as MNEGF, MSWAPF,
MBCNDD, MCCNDD, and MRCNDD.
For instructions that use MRx (where x could be 'a' through 'f') as operands, the trailing alphabet appears
in the opcode as a two-bit field.
For example,
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
whose opcode is
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0000 0000
the two-bit field specifies one of four working registers according to the following table:
Table 5-9. Operand Encoding
Two-bit Field

Working Register

b'00

MR0

b'01

MR1

b'10

MR2

b'11

MR3

Table 5-10. Condition Field Encoding
Encode

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

1111

UNCF

Unconditional with flag modification

None

(1)
(2)

680

(1)

(2)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to be modified when a
conditional operation is executed. All other conditions will not modify these flags.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

5.6.3 Instructions
The instructions are listed alphabetically, preceded by a summary.
Table 5-11. General Instructions
Title

......................................................................................................................................

MABSF32 MRa, MRb — 32-Bit Floating-Point Absolute Value ...................................................................
MADD32 MRa, MRb, MRc — 32-Bit Integer Add ...................................................................................
MADDF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Addition ................................................................
MADDF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Addition .................................................................
MADDF32 MRa, MRb, MRc — 32-Bit Floating-Point Addition ....................................................................
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa — 32-Bit Floating-Point Addition with Parallel Move ...............
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Addition with Parallel Move ...............
MAND32 MRa, MRb, MRc — Bitwise AND ..........................................................................................
MASR32 MRa, #SHIFT — Arithmetic Shift Right ...................................................................................
MBCNDD 16BitDest {, CNDF} — Branch Conditional Delayed ..................................................................
MCCNDD 16BitDest {, CNDF} — Call Conditional Delayed ......................................................................
MCMP32 MRa, MRb — 32-Bit Integer Compare for Equal, Less Than or Greater Than......................................
MCMPF32 MRa, MRb — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than ............................
MCMPF32 MRa, #16FHi — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than .........................
MDEBUGSTOP — Debug Stop Task ................................................................................................
MEALLOW — Enable CLA Write Access to EALLOW Protected Registers ...................................................
MEDIS — Disable CLA Write Access to EALLOW Protected Registers .......................................................
MEINVF32 MRa, MRb — 32-Bit Floating-Point Reciprocal Approximation ......................................................
MEISQRTF32 MRa, MRb — 32-Bit Floating-Point Square-Root Reciprocal Approximation ..................................
MF32TOI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer ..............................................
MF32TOI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round ..............................
MF32TOI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Integer ..............................................
MF32TOUI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer ...............................
MF32TOUI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round ................
MF32TOUI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer ...............................
MFRACF32 MRa, MRb — Fractional Portion of a 32-Bit Floating-Point Value .................................................
MI16TOF32 MRa, MRb — Convert 16-Bit Integer to 32-Bit Floating-Point Value .............................................
MI16TOF32 MRa, mem16 — Convert 16-Bit Integer to 32-Bit Floating-Point Value ..........................................
MI32TOF32 MRa, mem32 — Convert 32-Bit Integer to 32-Bit Floating-Point Value ..........................................
MI32TOF32 MRa, MRb — Convert 32-Bit Integer to 32-Bit Floating-Point Value .............................................
MLSL32 MRa, #SHIFT — Logical Shift Left .........................................................................................
MLSR32 MRa, #SHIFT — Logical Shift Right .......................................................................................
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply and Accumulate
with Parallel Move ............................................................................................................
MMAXF32 MRa, MRb — 32-Bit Floating-Point Maximum .........................................................................
MMAXF32 MRa, #16FHi — 32-Bit Floating-Point Maximum ......................................................................
MMINF32 MRa, MRb — 32-Bit Floating-Point Minimum ...........................................................................
MMINF32 MRa, #16FHi — 32-Bit Floating-Point Minimum ........................................................................
MMOV16 MARx, MRa, #16I — Load the Auxiliary Register with MRa + 16-bit Immediate Value ...........................
MMOV16 MARx, mem16 — Load MAR1 with 16-bit Value .......................................................................
MMOV16 mem16, MARx — Move 16-Bit Auxiliary Register Contents to Memory .............................................
MMOV16 mem16, MRa — Move 16-Bit Floating-Point Register Contents to Memory ........................................
MMOV32 mem32, MRa — Move 32-Bit Floating-Point Register Contents to Memory .......................................
MMOV32 mem32, MSTF — Move 32-Bit MSTF Register to Memory ...........................................................
MMOV32 MRa, mem32 {, CNDF} — Conditional 32-Bit Move ...................................................................
MMOV32 MRa, MRb {, CNDF} — Conditional 32-Bit Move .......................................................................
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

Page
683
684
685
686
688
689
690
692
693
694
699
703
704
705
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
728
730
731
733
734
737
739
740
742
743
744
746
681

Instruction Set

www.ti.com

Table 5-11. General Instructions (continued)
MMOV32 MSTF, mem32 — Move 32-Bit Value from Memory to the MSTF Register .........................................
MMOVD32 MRa, mem32 — Move 32-Bit Value from Memory with Data Copy ................................................
MMOVF32 MRa, #32F — Load the 32-Bits of a 32-Bit Floating-Point Register ................................................
MMOVI16 MARx, #16I — Load the Auxiliary Register with the 16-Bit Immediate Value ......................................
MMOVI32 MRa, #32FHex — Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate .....................
MMOVIZ MRa, #16FHi — Load the Upper 16-Bits of a 32-Bit Floating-Point Register .......................................
MMOVZ16 MRa, mem16 — Load MRx With 16-bit Value .........................................................................
MMOVXI MRa, #16FLoHex — Move Immediate to the Low 16-Bits of a Floating-Point Register ...........................
MMPYF32 MRa, MRb, MRc — 32-Bit Floating-Point Multiply.....................................................................
MMPYF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Multiply .................................................................
MMPYF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Multiply .................................................................
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Add .............
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply with Parallel Move ...............
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Multiply with Parallel Move ...............
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Subtract .......
MNEGF32 MRa, MRb{, CNDF} — Conditional Negation ..........................................................................
MNOP — No Operation ..............................................................................................................
MOR32 MRa, MRb, MRc — Bitwise OR .............................................................................................
MRCNDD {CNDF} — Return Conditional Delayed .................................................................................
MSETFLG FLAG, VALUE — Set or Clear Selected Floating-Point Status Flags .............................................
MSTOP — Stop Task ..................................................................................................................
MSUB32 MRa, MRb, MRc — 32-Bit Integer Subtraction ..........................................................................
MSUBF32 MRa, MRb, MRc — 32-Bit Floating-Point Subtraction ...............................................................
MSUBF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Subtraction .............................................................
MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Subtraction with Parallel Move ..........
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Subtraction with Parallel Move ..........
MSWAPF MRa, MRb {, CNDF} — Conditional Swap .............................................................................
MTESTTF CNDF — Test MSTF Register Flag Condition ..........................................................................
MUI16TOF32 MRa, mem16 — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value ............................
MUI16TOF32 MRa, MRb — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value ................................
MUI32TOF32 MRa, mem32 — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value ............................
MUI32TOF32 MRa, MRb — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value ................................
MXOR32 MRa, MRb, MRc — Bitwise Exclusive Or ................................................................................

682

Control Law Accelerator (CLA)

748
749
750
751
752
753
754
755
756
757
759
761
763
765
766
767
769
770
771
775
776
778
779
780
781
782
783
785
787
788
789
790
791

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MABSF32 MRa, MRb 32-Bit Floating-Point Absolute Value
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0010 0000

Description

The absolute value of MRb is loaded into MRa. Only the sign bit of the operand is
modified by the MABSF32 instruction.
if (MRb < 0) {MRa = -MRb};
else {MRa = MRb};

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified as follows:
NF = 0;
ZF = 0;
if ( MRa(30:23) == 0) ZF = 1;

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ MR0, #-2.0 ; MR0 = -2.0 (0xC0000000)
MABSF32 MR0, MR0 ; MR0 = 2.0 (0x40000000), ZF = NF = 0
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MABSF32 MR0, MR0 ; MR0 = 5.0 (0x40A00000), ZF = NF = 0
MMOVIZ MR0, #0.0 ; MR0 = 0.0
MABSF32 MR0, MR0 ; MR0 = 0.0 ZF = 1, NF = 0

See also

MNEGF32 MRa, MRb {, CNDF}

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

683

Instruction Set

www.ti.com

MADD32 MRa, MRb, MRc 32-Bit Integer Add
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point destination register (MR0 to MR3)

MRc

CLA floating-point destination register (MR0 to MR3)

Opcode

LSW: 0000 0000 000cc bbaa
MSW: 0111 1110 1100 0000

Description

32-bit integer addition of MRb and MRc.
MRa(31:0) = MRb(31:0) + MRc(31:0);

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; };

Pipeline

This is a single-cycle instruction.

Example

; Given A = (int32)1
;
B = (int32)2
;
C = (int32)-7
;
; Calculate Y2 = A + B + C
;
_Cla1Task1:
MMOV32 MR0, @_A
MMOV32 MR1, @_B
MMOV32 MR2, @_C
MADD32 MR3, MR0, MR1
MADD32 MR3, MR2, MR3
MMOV32 @_y2, MR3
MSTOP

See also

684

;
;
;
;
;
;
;

MR0 = 1 (0x00000001)
MR1 = 2 (0x00000002)
MR2 = -7 (0xFFFFFFF9)
A + B
A + B + C = -4 (0xFFFFFFFC)
Store y2
end of task

MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MADDF32 MRa, #16FHi, MRb 32-Bit Floating-Point Addition
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description

Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, MRb, #16FHi.
Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example

; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, #2.0, MR1
; MR0 = 2.0 + MR1
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, #-2.5, MR3
; MR2 = -2.5 + MR3
; Add to MR3 the value 0x3FC00000 (1.5)
; Store the result in MR3
MADDF32 MR3, #0x3FC0, MR3 ; MR3 = 1.5 + MR3

See also

MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

685

Instruction Set

www.ti.com

MADDF32 MRa, MRb, #16FHi 32-Bit Floating-Point Addition
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description

Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, #16FHi, MRb.
This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example 1

; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store it in Result
;
_Cla1Task1:
MMOVI16
MAR1,#_X
; Start address
MUI16TOF32 MR0, @_len
; Length of the array
MNOP
; delay for MAR1 load
MNOP
; delay for MAR1 load
MMOV32
MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32
MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32
MR1, MR2
; MR1 = MAX(MR1, MR2)
MADDF32
MR0, MR0, #-1.0 ; Decrement the counter
MCMPF32
MR0 #0.0
; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ
; Branch if not equal to zero
MMOV32 @_Result, MR1
; Always executed
MNOP
; Always executed
MNOP
; Always executed
MSTOP
; End of task

686

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Example 2

; Show the basic operation of MADDF32
;
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, MR1, #2.0
; MR0 = MR1 + 2.0
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, MR3, #-2.5
; MR2 = MR3 + (-2.5)
; Add to MR0 the value 0x3FC00000 (1.5)
; Store the result in MR0
MADDF32 MR0, MR0, #0x3FC0 ; MR0 = MR0 + 1.5

See also

MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

687

Instruction Set

www.ti.com

MADDF32 MRa, MRb, MRc 32-Bit Floating-Point Addition
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

MRc

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 000 0000 00cc bbaa
MSW: 0111 1100 0010 0000

Description

Add the contents of MRc to the contents of MRb and load the result into MRa.
MRa = MRb + MRc;

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example

; Given M1, X1 and B1 are 32-bit floating point numbers
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0,@M1
; Load MR0 with M1
MMOV32 MR1,@X1
; Load MR1 with X1
MMPYF32 MR1,MR1,MR0 ; Multiply M1*X1
|| MMOV32 MR0,@B1
; and in parallel load MR0 with B1
MADDF32 MR1,MR1,MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1,MR1
; Store the result
MSTOP
; end of task

See also

MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

688

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa 32-Bit Floating-Point Addition with Parallel Move
Operands
MRd

CLA floating-point destination register for the MADDF32 (MR0 to MR3)

MRe

CLA floating-point source register for the MADDF32 (MR0 to MR3)

MRf

CLA floating-point source register for the MADDF32 (MR0 to MR3)

mem32

32-bit memory location accessed using one of the available addressing modes. This
will be the destination of the MMOV32.

MRa

CLA floating-point source register for the MMOV32 (MR0 to MR3)

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0101 ffee ddaa addr

Description

Perform an MADDF32 and a MMOV32 in parallel. Add MRf to the contents of MRe and
store the result in MRd. In parallel move the contents of MRa to the 32-bit location
mem32.
MRd = MRe + MRf;
[mem32] = MRa;

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline

Both MADDF32 and MMOV32 complete in a single cycle.

Example

; Given A, B and C are 32-bit
; Calculate Y2 = (A * B)
;
Y3 = (A * B) + C
;
_Cla1Task2:
MMOV32
MR0, @_A
;
MMOV32
MR1, @_B
;
MMPYF32 MR1, MR1, MR0
;
|| MMOV32
MR0, @_C
;
MADDF32 MR1, MR1, MR0
;
|| MMOV32
@_Y2, MR1
;
MMOV32
@_Y3, MR1
;
MSTOP
;

See also

floating-point numbers

Load MR0 with A
Load MR1 with B
Multiply A*B
and in parallel load MR0 with C
Add (A*B) to C
and in parallel store A*B
Store the A*B + C
end of task

MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

689

Instruction Set

www.ti.com

MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Addition with Parallel Move
Operands
MRd

CLA floating-point destination register for the MADDF32 (MR0 to MR3).
MRd cannot be the same register as MRa.

MRe

CLA floating-point source register for the MADDF32 (MR0 to MR3)

MRf

CLA floating-point source register for the MADDF32 (MR0 to MR3)

MRa

CLA floating-point destination register for the MMOV32 (MR0 to MR3).
MRa cannot be the same register as MRd.

mem32

32-bit memory location accessed using one of the available addressing modes. This is
the source for the MMOV32.

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0001 ffee ddaa addr

Description

Perform an MADDF32 and a MMOV32 operation in parallel. Add MRf to the contents of
MRe and store the result in MRd. In parallel move the contents of the 32-bit location
mem32 to MRa.
MRd = MRe + MRf;
MRa = [mem32];

Restrictions

The destination register for the MADDF32 and the MMOV32 must be unique. That is,
MRa and MRd cannot be the same register.

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
The MMOV32 Instruction will set the NF and ZF flags as follows:
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; };

Pipeline

The MADDF32 and the MMOV32 both complete in a single cycle.

Example 1

; Given A, B and C are 32-bit floating-point numbers
; Calculate Y1 = A + 4B
;
Y2 = A + C
;
_Cla1Task1:
MMOV32 MR0, @A
; Load MR0 with A
MMOV32 MR1, @B
; Load MR1 with B
MMPYF32 MR1, MR1, #4.0 ; Multiply 4 * B
|| MMOV32 MR2, @C
and in parallel load C
MADDF32 MR3, MR0, MR1 ; Add A + 4B
MADDF32 MR3, MR0, MR2 ; Add A + C
|| MMOV32 @Y1, MR3
; and in parallel store A+4B
MMOV32 @Y2, MR3
; store A + C MSTOP
; end of task

690

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Example 2

See also

; Given A, B and C are 32-bit
; Calculate Y3 = (A + B)
;
Y4 = (A + B) * C
;
_Cla1Task2:
MMOV32 MR0, @A
;
MMOV32 MR1, @B
;
MADDF32 MR1, MR1, MR0 ;
||
MMOV32 MR0, @C
;
MMPYF32 MR1, MR1, MR0 ;
||
MMOV32 @Y3, MR1
;
MMOV32 @Y4, MR1
;
MSTOP
;

floating-point numbers

Load MR0 with A
Load MR1 with B
Add A+B
and in parallel load MR0 with C
Multiply (A+B) by C
and in parallel store A+B
Store the (A+B) * C
end of task

MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

691

Instruction Set

www.ti.com

MAND32 MRa, MRb, MRc Bitwise AND
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

MRc

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0110 0000

Description

Bitwise AND of MRb with MRc.
MRa(31:0) = MRb(31:0) AND MRc(31:0);

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MMOVXI

MR0,
MR0,

#0x5555
#0xAAAA

; MR0 = 0x5555AAAA

MMOVIZ
MMOVXI

MR1,
MR1,

#0x5432
#0xFEDC

; MR1 = 0x5432FEDC

;
;
;
;
;
;
;
;

0101
0101
0101
0101
1010
1010
1010
1010

AND
AND
AND
AND
AND
AND
AND
AND

0101
0100
0011
0010
1111
1110
1101
1100

=
=
=
=
=
=
=
=

0101
0100
0001
0000
1010
1010
1000
1000

(5)
(4)
(1)
(0)
(A)
(A)
(8)
(8)

MAND32 MR2, MR1, MR0

See also

692

; MR3 = 0x5410AA88

MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MASR32 MRa, #SHIFT Arithmetic Shift Right
Operands
MRa

CLA floating-point source/destination register (MR0 to MR3)

#SHIFT

Number of bits to shift (1 to 32)

Opcode

LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 0100 0000

Description

Arithmetic shift right of MRa by the number of bits indicated. The number of bits can be 1
to 32.
MARa(31:0) = Arithmetic Shift(MARa(31:0) by #SHIFT bits);

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline

This is a single-cycle instruction.

Example

; Given m2 = (int32)32
;
x2 = (int32)64
;
b2 = (int32)-128
;
; Calculate
;
m2 = m2/2
;
x2 = x2/4
;
b2 = b2/8
;
_Cla1Task2:
MMOV32 MR0, @_m2 ; MR0 =
MMOV32 MR1, @_x2 ; MR1 =
MMOV32 MR2, @_b2 ; MR2 =
MASR32 MR0, #1
; MR0 =
MASR32 MR1, #2
; MR1 =
MASR32 MR2, #3
; MR2 =
MMOV32 @_m2, MR0 ; store
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

See also

32 (0x00000020)
64 (0x00000040)
-128 (0xFFFFFF80)
16 (0x00000010)
16 (0x00000010)
-16 (0xFFFFFFF0)
results

MADD32 MRa, MRb, MRc
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

693

Instruction Set

www.ti.com

MBCNDD 16BitDest {, CNDF} Branch Conditional Delayed
Operands
16BitDest

16-bit destination if condition is true

CNDF

Optional condition tested

Opcode

LSW: dest dest dest dest
MSW: 0111 1001 1000 cndf

Description

If the specified condition is true, then branch by adding the signed 16BitDest value to the
MPC value. Otherwise, continue without branching. If the address overflows, it wraps
around. Therefore a value of "0xFFFE" will put the MPC back to the MBCNDD
instruction.
Please refer to the pipeline section for important information regarding this instruction.
if (CNDF == TRUE) MPC += 16BitDest;

CNDF is one of the following conditions:
Encode

(1)

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

1111

UNCF

Unconditional with flag
modification

None

(1)
(2)

(2)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Restrictions

The MBCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD or MRCNDD instruction. Refer to the pipeline section for more information.

Flags

This instruction does not modify flags in the MSTF register.

Pipeline

694

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

The MBCNDD instruction by itself is a single-cycle instruction. As shown in Table 5-12
for each branch 6 instruction slots are executed; three before the branch instruction (I2I4) and three after the branch instruction (I5-I7). The total number of cycles for a branch
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled. The
effective number of cycles for a branch can, therefore, range from 1 to 7 cycles. The
number of cycles for a branch taken may not be the same as for a branch not taken.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Referring to Table 5-12 and Table 5-13, the instructions before and after MBCNDD have
the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MBCNDD
instruction. The CNDF flags are tested in the D2 phase of the pipeline. That is, a
decision is made whether to branch or not when MBCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3 and I4
– The three instructions proceeding MBCNDD can change MSTF flags but will have
no effect on whether the MBCNDD instruction branches or not. This is because
the flag modification will occur after the D2 phase of the MBCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.
• I5, I6 and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.


;
;

;

;

;
MBCNDD _Skip, NEQ ;
;
;

;

;

;

;

;
....
_Skip:
 ;
 ;
 ;
....
....
MSTOP
....

I1 Last instruction that can affect flags for
the MBCNDD operation
I2 Cannot be stop, branch, call or return
I3 Cannot be stop, branch, call or return
I4 Cannot be stop, branch, call or return
Branch to Skip if not eqal to zero
Three instructions after MBCNDD are always
executed whether the branch is taken or not
I5 Cannot be stop, branch, call or return
I6 Cannot be stop, branch, call or return
I7 Cannot be stop, branch, call or return
I8
I9

d1 Can be any instruction
d2
d3

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

695

Instruction Set

www.ti.com

Table 5-12. Pipeline Activity For MBCNDD, Branch Not Taken
Instruction

F1

I1

I1

F2

D1

D2

R1

R2

E

I2

I2

I1

I3

I3

I2

I1

I4

I4

I3

I2

I1

MBCNDD

MBCNDD

I4

I3

I2

I1

I5

I5

MBCNDD

I4

I3

I2

I1

I6

I6

I5

MBCNDD

I4

I3

I2

I1

I7

I7

I6

I5

MBCNDD

I4

I3

I2

I8

I8

I7

I6

I5

-

I4

I3

I9

I9

I8

I7

I6

I5

-

I4

I10

I10

I9

I8

I7

I6

I5

-

I10

I9

I8

I7

I6

I5

I10

I9

I8

I7

I6

I10

I9

I8

I7

I10

I9

I8

I10

I9

W

I10

Table 5-13. Pipeline Activity For MBCNDD, Branch Taken
Instruction

F1

I1

I1

F2

D1

D2

R1

R2

E

I2

I2

I1

I3

I3

I2

I1

I4

I4

I3

I2

I1

MBCNDD

MBCNDD

I4

I3

I2

I1

I5

I5

MBCNDD

I4

I3

I2

I1

I6

I6

I5

MBCNDD

I4

I3

I2

I1

I7

I7

I6

I5

MBCNDD

I4

I3

I2

d1

d1

I7

I6

I5

-

I4

I3

d2

d2

d1

I7

I6

I5

-

I4

d3

d3

d2

d1

I7

I6

I5

-

d3

d2

d1

I7

I6

I5

d3

d2

d1

I7

I6

d3

d2

d1

I7

d3

d2

d1

d3

d2

W

d3

696

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Example 1

; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task1:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1
; Affects flags for 1st MBCNDD (A)
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ
; (A) If State != 0.1, go to Skip1
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @RampState
; Execute if (A) branch not taken
MMOVXI MR2, #RAMPMASK
; Execute if (A) branch not taken
MOR32 MR1, MR2
; Execute if (A) branch not taken
MMOV32 @RampState, MR1
; Execute if (A) branch not taken
MSTOP
; end of task if (A) branch not taken
Skip1:
MCMPF32 MR0,#0.01
; Affects flags for 2nd MBCNDD (B)
MNOP
MNOP
MNOP
MBCNDD Skip2,NEQ
; (B) If State != 0.01, go to Skip2
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @CoastState ; Execute if (B) branch not taken
MMOVXI MR2, #COASTMASK
; Execute if (B) branch not taken
MOR32 MR1, MR2
; Execute if (B) branch not taken
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP
Skip2:
MMOV32 MR3, @SteadyState ; Executed if (B) branch taken
MMOVXI MR2, #STEADYMASK ; Executed if (B) branch taken
MOR32 MR3, MR2
; Executed if (B) branch taken
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

697

Instruction Set
Example 2

www.ti.com
; This example is the same as Example 1, except
; the code is optimized to take advantage of delay slots
;
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1
; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01
; Check used by 2nd MBCNDD (B)
MTESTTF EQ
; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD Skip1, NEQ
; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @RampState
; Always executed
MMOVXI MR2, #RAMPMASK
; Always executed
MOR32 MR1, MR2
; Always executed
MMOV32 @RampState, MR1
; Execute if (A) branch not taken
MSTOP
; end of task if (A) branch not taken
Skip1:
MMOV32 MR3, @SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD Skip2, NTF
MMOV32 MR1, @CoastState
MMOVXI MR2, #COASTMASK
MOR32 MR1, MR2
MMOV32 @CoastState, MR1
MSTOP
Skip2:
MMOV32 @SteadyState, MR3
MSTOP

See also

698

;
;
;
;
;
;

(B) if State != .01, go to Skip2
Always executed
Always executed
Always executed
Execute if (B) branch not taken
end of task if (B) branch not taken

; Executed if (B) branch taken

MCCNDD 16BitDest, CNDF
MRCNDD CNDF

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MCCNDD 16BitDest {, CNDF} Call Conditional Delayed
Operands
16BitDest

16-bit destination if condition is true

CNDF

Optional condition to be tested

Opcode

LSW: dest dest dest dest
MSW: 0111 1001 1001 cndf

Description

If the specified condition is true, then store the return address in the RPC field of MSTF
and make the call by adding the signed 16BitDest value to the MPC value. Otherwise,
continue code execution without making the call. If the address overflows, it wraps
around. Therefore a value of "0xFFFE" will put the MPC back to the MCCNDD
instruction.
Please refer to the pipeline section for important information regarding this instruction.
if (CNDF == TRUE)
{
RPC = return address;
MPC += 16BitDest;
};

CNDF is one of the following conditions:
Encode

(3)

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

1111

UNCF

Unconditional with flag
modification

None

(3)
(4)

(4)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

Restrictions

The MCCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more details.

Flags

This instruction does not modify flags in the MSTF register.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

699

Instruction Set
Pipeline

www.ti.com

The MCCNDD instruction by itself is a single-cycle instruction. As shown in Table 5-14,
for each call 6 instruction slots are executed; three before the call instruction (I2-I4) and
three after the call instruction (I5-I7). The total number of cycles for a call taken or not
taken depends on the usage of these slots. That is, the number of cycles depends on
how many slots are filled with a MNOP as well as which slots are filled. The effective
number of cycles for a call can, therefore, range from 1 to 7 cycles. The number of
cycles for a call taken may not be the same as for a call not taken.
Referring to the following code fragment and the pipeline diagrams in Table 5-14 and
Table 5-15, the instructions before and after MCCNDD have the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MCCNDD
instruction. The CNDF flags are tested in the D2 phase of the pipeline. That is, a
decision is made whether to branch or not when MCCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3 and I4
– The three instructions proceeding MCCNDD can change MSTF flags but will have
no effect on whether the MCCNDD instruction makes the call or not. This is
because the flag modification will occur after the D2 phase of the MCCNDD
instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.
• I5, I6 and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.

700

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com





;
;
;
;
;

I1 Last instruction that can affect flags for
the MCCNDD operation
I2 Cannot be stop, branch, call or return
I3 Cannot be stop, branch, call or return
I4 Cannot be stop, branch, call or return

MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not

6>
7>
8>



1>
2>
3>
4>

;
;
;
;
;
;
;
;

I5
I6
I7
I8

Cannot be stop, branch, call or return
Cannot be stop, branch, call or return
Cannot be stop, branch, call or return
The address of this instruction is saved
in the RPC field of the MSTF register.
Upon return this value is loaded into MPC
and fetching continues from this point.

;
;
;
;
;

d1 Can be any instruction
d2
d3
d4 Last instruction that can affect flags for
the MRCNDD operation

I9





; d5 Cannot be stop, branch, call or return
; d6 Cannot be stop, branch, call or return
; d7 Cannot be stop, branch, call or return

MRCNDD UNC

; Return to , unconditional
; Three instructions after MRCNDD are always
; executed whether the return is taken or not


9>
10>
11>

;
;
;
;

d8 Cannot be stop, branch, call or return
d9 Cannot be stop, branch, call or return
d10 Cannot be stop, branch, call or return
d11

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

701

Instruction Set

www.ti.com

Table 5-14. Pipeline Activity For MCCNDD, Call Not Taken
Instruction

F1

I1

I1

F2

I2

I2

I1

I3

I3

I2

I1

I4

I4

I3

I2

I1

MCCNDD

MCCNDD

I4

I3

I2

I1

I5

I5

MCCNDD

I4

I3

I2

I1

I6

I6

I5

MCCNDD

I4

I3

I2

I1

I7

I7

I6

I5

MCCNDD

I4

I3

I2

I8

I8

I7

I6

I5

-

I4

I3

I9

I9

I8

I7

I6

I5

-

I4

I10

I10

I9

I8

I7

I6

I5

-

I10

I9

I8

I7

I6

I5

I10

I9

I8

I7

I6

I10

I9

I8

I7

I10

I9

I8

I10

I9

etc ....
....

D1

....

D2

R1

....

R2

E

W

I10

Table 5-15. Pipeline Activity For MCCNDD, Call Taken
Instruction

F1

I1

I1

I2

I2

I1

I3

I3

I2

I1

I4

I4

I3

I2

I1

MCCNDD

MCCNDD

I4

I3

I2

I1

I5

I5

MCCNDD

I4

I3

I2

I1

I6

I6

I5

MCCNDD

I4

I3

I2

I1

I7

I6

I5

MCCNDD

I4

I3

I2

d1

d1

I7

I6

I5

-

I4

I3

d2

d2

d1

I7

I6

I5

-

I4

d3

d3

d2

d1

I7

I6

I5

-

d3

d2

d1

I7

I6

I5

d3

d2

d1

I7

I6

d3

d2

d1

I7

d3

d2

d1

d3

d2

I7

(1)

etc ....

F2

....
....

D1

D2

R1

....

R2

E

W

d3
(1)

The RPC value in the MSTF register will point to the instruction following I7 (instruction I8).

Example

;

See also

MBCNDD #16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32
MRCNDD CNDF

702

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MCMP32 MRa, MRb 32-Bit Integer Compare for Equal, Less Than or Greater Than
Operands
MRa

CLA floating-point source register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0010 0000

Description

Set ZF and NF flags on the result of MRa - MRb where MRa and MRb are 32-bit
integers. For a floating point compare refer to MCMPF32.

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
If(MRa ==
MRb) {ZF=1; NF=0;}
If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline

This is a single-cycle instruction.

Example

; Behavior of ZF and NF flags for different comparisons
;
; Given A = (int32)1
;
B = (int32)2
;
C = (int32)-7
;
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MCMP32 MR2, MR2 ; NF = 0, ZF = 1
MCMP32 MR0, MR1 ; NF = 1, ZF = 0
MCMP32 MR1, MR0 ; NF = 0, ZF = 0

See also

MADD32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

703

Instruction Set

www.ti.com

MCMPF32 MRa, MRb 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than
Operands
MRa

CLA floating-point source register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0000 0000

Description

Set ZF and NF flags on the result of MRa - MRb. The MCMPF32 instruction is performed
as a logical compare operation. This is possible because of the IEEE format offsetting
the exponent. Basically the bigger the binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero will be treated as positive zero.
• A denormalized value will be treated as positive zero.
• Not-a-Number (NaN) will be treated as infinity.
This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified as follows:
If(MRa == MRb)
{ZF=1; NF=0;}
If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline

This is a single-cycle instruction.

Example

; Behavior of ZF and NF flags for different comparisons
MMOVIZ
MMOVIZ
MCMPF32
MCMPF32
MCMPF32

See also

704

MR1,
MR0,
MR1,
MR0,
MR0,

#-2.0
#5.0
MR0
MR1
MR0

;
;
;
;
;

MR1 = -2.0 (0xC0000000)
MR0 = 5.0 (0x40A00000)
ZF = 0, NF = 1
ZF = 0, NF = 0
ZF = 1, NF = 0

MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MCMPF32 MRa, #16FHi 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than
Operands
MRa

CLA floating-point source register (MR0 to MR3)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 1000 1100 00aa

Description

Compare the value in MRa with the floating-point value represented by the immediate
operand. Set the ZF and NF flags on (MRa - #16FHi:0).
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler will accept either a hex or float as the immediate
value. That is, -1.5 can be represented as #-1.5 or #0xBFC0.
The MCMPF32 instruction is performed as a logical compare operation. This is possible
because of the IEEE floating-point format offsets the exponent. Basically the bigger the
binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero will be treated as positive zero.
• Denormalized value will be treated as positive zero.
• Not-a-Number (NaN) will be treated as infinity.

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified as follows:
If(MRa == #16FHi:0)
{ZF=1, NF=0;}
If(MRa > #16FHi:0) {ZF=0, NF=0;}
If(MRa < #16FHi:0) {ZF=0, NF=1;}

Pipeline

This is a single-cycle instruction

Example 1

; Behavior of ZF and NF flags for different comparisons
MMOVIZ
MMOVIZ
MCMPF32
MCMPF32
MCMPF32

MR1,
MR0,
MR1,
MR0,
MR0,

#-2.0
#5.0
#-2.2
#6.5
#5.0

;
;
;
;
;

MR1 = -2.0 (0xC0000000)
MR0 = 5.0 (0x40A00000)
ZF = 0, NF = 0
ZF = 0, NF = 1
ZF = 1, NF = 0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

705

Instruction Set
Example 2

www.ti.com
; X is an array of 32-bit floating-point values
; and has len elements. Find the maximum value in
; the array and store it in Result
;
; Note: MCMPF32 and MSWAPF can be replaced with MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X
; Start address
MUI16TOF32 MR0, @_len
; Length of the array
MNOP
; delay for MAR1 load
MNOP
; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++
MCMPF32 MR2, MR1
MSWAPF MR1, MR2, GT
MADDF32 MR0, MR0, #-1.0
MCMPF32 MR0 #0.0
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ
MMOV32 @_Result, MR1
MNOP
MNOP
MSTOP

See also

706

;
;
;
;
;

MR2 = next element
Compare MR2 with MR1
MR1 = MAX(MR1, MR2)
Decrememt the counter
Set/clear flags for MBCNDD

;
;
;
;
;

Branch
Always
Always
Always
End of

if not equal to zero
executed
executed
executed
task

MCMPF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MDEBUGSTOP

Debug Stop Task

Operands
none

This instruction does not have any operands

Opcode

LSW: 0000 0000 0000 0000
MSW: 0111 1111 0110 0000

Description

When CLA breakpoints are enabled, the MDEBUGSTOP instruction is used to halt a
task so that it can be debugged. That is, MDEBUGSTOP is the CLA breakpoint. If CLA
breakpoints are not enabled, the MDEBUGSTOP instruction behaves like a MNOP.
Unlike the MSTOP, the MIRUN flag is not cleared and an interrupt is not issued. A
single-step or run operation will continue execution of the task.

Restrictions

The MDEBUGSTOP instruction cannot be placed 3 instructions before or after a
MBCNDD, MCCNDD or MRCNDD instruction.

Flags

This instruction does not modify flags in the MSTF register.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

;

See also

MSTOP

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

707

Instruction Set

MEALLOW

www.ti.com

Enable CLA Write Access to EALLOW Protected Registers

Operands
none

This instruction does not have any operands

Opcode

LSW: 0000 0000 0000 0000
MSW: 0111 1111 1001 0000

Description

This instruction sets the MEALLOW bit in the CLA status register MSTF. When this bit is
set, the CLA is allowed write access to EALLOW protected registers. To again protect
against CLA writes to protected registers, use the MEDIS instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the
CLA while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden via the JTAG port, allowing full control
of register accesses during debug from Code Composer Studio.
This instruction does not modify flags in the MSTF register.

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW
; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS
; Disallow CLA write access
...
...
MSTOP

See also

MEDIS

708

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MEDIS

Disable CLA Write Access to EALLOW Protected Registers

Operands
none

This instruction does not have any operands

Opcode

LSW: 0000 0000 0000 0000
MSW: 0111 1111 1011 0000

Description

This instruction clears the MEALLOW bit in the CLA status register MSTF. When this bit
is clear, the CLA is not allowed write access to EALLOW-protected registers. To enable
CLA writes to protected registers, use the MEALLOW instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the
CLA while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden via the JTAG port, allowing full control
of register accesses during debug from Code Composer Studio.

Flags

This instruction does not modify flags in the MSTF register.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW
; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS
; Disallow CLA write access
...
...
MSTOP

See also

MEALLOW

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

709

Instruction Set

www.ti.com

MEINVF32 MRa, MRb 32-Bit Floating-Point Reciprocal Approximation
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0000 0000

Description

This operation generates an estimate of 1/X in 32-bit floating-point format accurate to
approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:
Ye = Estimate(1/X);
Ye = Ye*(2.0 - Ye*X);
Ye = Ye*(2.0 - Ye*X);

After two iterations of the Newton-Raphson algorithm, you will get an exact answer
accurate to the 32-bit floating-point format. On each iteration the mantissa bit accuracy
approximately doubles. The MEINVF32 operation will not generate a negative zero,
DeNorm or NaN value.
MRa = Estimate of 1/MRb;

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MEINVF32 generates an underflow condition.
• LVF = 1 if MEINVF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example

; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den
; MR1 = Den
MEINVF32 MR2, MR1
; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num
; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den
; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ
; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0
; Store result
MSTOP
; end of task

See also

MEISQRTF32 MRa, MRb

710

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MEISQRTF32 MRa, MRb 32-Bit Floating-Point Square-Root Reciprocal Approximation
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0100 0000

Description

This operation generates an estimate of 1/sqrt(X) in 32-bit floating-point format accurate
to approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:
Ye = Estimate(1/sqrt(X));
Ye = Ye*(1.5 - Ye*Ye*X/2.0);
Ye = Ye*(1.5 - Ye*Ye*X/2.0);

After 2 iterations of the Newton-Raphson algorithm, you will get an exact answer
accurate to the 32-bit floating-point format. On each iteration the mantissa bit accuracy
approximately doubles. The MEISQRTF32 operation will not generate a negative zero,
DeNorm or NaN value.
MRa = Estimate of 1/sqrt (MRb);

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MEISQRTF32 generates an underflow condition.
• LVF = 1 if MEISQRTF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example

; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x
;
MEISQRTF32 MR1, MR0
;
MMOV32 MR1, @_x, EQ
;
MMPYF32 MR3, MR0, #0.5
;
MMPYF32 MR2, MR1, MR3
;
MMPYF32 MR2, MR1, MR2
;
MSUBF32 MR2, #1.5, MR2
;
MMPYF32 MR1, MR1, MR2
;
MMPYF32 MR2, MR1, MR3
;
MMPYF32 MR2, MR1, MR2
;
MSUBF32 MR2, #1.5, MR2
;
MMPYF32 MR1, MR1, MR2
;
MMPYF32 MR0, MR1, MR0
;
MMOV32 @_y, MR0
;
MSTOP
;

See also

MR0 = X
MR1 = Ye = Estimate(1/sqrt(X))
if(X == 0.0) Ye = 0.0
MR3 = X*0.5
MR2 = Ye*X*0.5
MR2 = Ye*Ye*X*0.5
MR2 = 1.5 - Ye*Ye*X*0.5
MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MR2 = Ye*X*0.5
MR2 = Ye*Ye*X*0.5
MR2 = 1.5 - Ye*Ye*X*0.5
MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MR0 = Y = Ye*X
Store Y = sqrt(X)
end of task

MEINVF32 MRa, MRb

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

711

Instruction Set

www.ti.com

MF32TOI16 MRa, MRb Convert 32-Bit Floating-Point Value to 16-Bit Integer
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1110 0000

Description

Convert a 32-bit floating point value in MRb to a 16-bit integer and truncate. The result
will be stored in MRa.
MRa(15:0) = F32TOI16(MRb);
MRa(31:16) = sign extension of MRa(15);

This instruction does not affect any flags:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MF32TOI16

MR0, #5.0
MR1, MR0

MMOVIZ
MF32TOI16

MR2, #-5.0
MR3, MR2

See also

712

;
;
;
;
;
;

MR0
MR1(15:0)
MR1(31:16)
MR2
MR3(15:0)
MR3(31:16)

=
=
=
=
=
=

5.0 (0x40A00000)
MF32TOI16(MR0) = 0x0005
Sign extension of MR1(15) = 0x0000
-5.0 (0xC0A00000)
MF32TOI16(MR2) = -5 (0xFFFB)
Sign extension of MR3(15) = 0xFFFF

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MF32TOI16R MRa, MRb Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0110 0000

Description

Convert the 32-bit floating point value in MRb to a 16-bit integer and round to the nearest
even value. The result is stored in MRa.
MRa(15:0) = F32TOI16round(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ MR0, #0x3FD9
MMOVXI MR0, #0x999A
MF32TOI16R MR1, MR0
MMOVF32 MR2, #-1.7
MF32TOI16R MR3, MR2

See also

;
;
;
;
;
;
;
;

MR0(31:16) = 0x3FD9
MR0(15:0) = 0x999A
MR0 = 1.7 (0x3FD9999A)
MR1(15:0) = MF32TOI16round (MR0) = 2 (0x0002)
MR1(31:16) = Sign extension of MR1(15) = 0x0000
MR2 = -1.7 (0xBFD9999A)
MR3(15:0) = MF32TOI16round (MR2) = -2 (0xFFFE)
MR3(31:16) = Sign extension of MR2(15) = 0xFFFF

MF32TOI16 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

713

Instruction Set

www.ti.com

MF32TOI32 MRa, MRb Convert 32-Bit Floating-Point Value to 32-Bit Integer
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0110 0000

Description

Convert the 32-bit floating-point value in MRb to a 32-bit integer value and truncate.
Store the result in MRa.
MRa = F32TOI32(MRb);

This instruction does not affect any flags:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example 1

MMOVF32
MF32TOI32
MMOVF32
MF32TOI32

Example 2

; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X and B from IQ24 to float
;
_Cla1Task2:
MI32TOF32 MR0, @_M
; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X
; MR1 = 0x4C200000
MI32TOF32 MR2, @_B
; MR2 = 0xCB000000
MMPYF32
MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32
MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32
MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32
MR3, MR0, MR1
; M*X
MADDF32
MR2, MR2, MR3
; Y=MX+B = 3.25 (0x40500000)

MR2,
MR3,
MR0,
MR1,

#11204005.0
MR2
#-11204005.0
MR0

;
;
;
;

MR2
MR3
MR0
MR1

; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80
;
MF32TOI32 MR2, MR2
;
MMOV32 @_Y, MR2
;
MSTOP
;

See also

714

=
=
=
=

11204005.0 (0x4B2AF5A5)
MF32TOI32(MR2) = 11204005 (0x00AAF5A5)
-11204005.0 (0xCB2AF5A5)
MF32TOI32(MR0) = -11204005 (0xFF550A5B)

Y * 1*2^24
IQ24(Y) = 0x03400000
store result
end of task

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MF32TOUI16 MRa, MRb Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1010 0000

Description

Convert the 32-bit floating point value in MRb to an unsigned 16-bit integer value and
truncate to zero. The result will be stored in MRa. To instead round the integer to the
nearest even value use the MF32TOUI16R instruction.
MRa(15:0) = F32TOUI16(MRb);
MRa(31:16) = 0x0000;

Flags

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MF32TOUI16

MR0, #9.0
MR1, MR0

MMOVIZ
MF32TOUI16

MR2, #-9.0
MR3, MR2

See also

;
;
;
;
;
;

MR0 = 9.0 (0x41100000)
MR1(15:0) = MF32TOUI16(MR0) = 9 (0x0009)
MR1(31:16) = 0x0000
MR2 = -9.0 (0xC1100000)
MR3(15:0) = MF32TOUI16(MR2) = 0 (0x0000)
MR3(31:16) = 0x0000

MF32TOI16 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

715

Instruction Set

www.ti.com

MF32TOUI16R MRa, MRb Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1100 0000

Description

Convert the 32-bit floating-point value in MRb to an unsigned 16-bit integer and round to
the closest even value. The result will be stored in MRa. To instead truncate the
converted value, use the MF32TOUI16 instruction.
MRa(15:0) = MF32TOUI16round(MRb);
MRa(31:16) = 0x0000;

This instruction does not affect any flags:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MMOVXI
MF32TOUI16R

MR0, #0x412C
MR0, #0xCCCD
MR1, MR0

MMOVF32
MF32TOUI16R

MR2, #-10.8
MR3, MR2

See also

716

;
;
;
;
;
;
;

MR0 = 0x412C
MR0 = 0xCCCD ; MR0 = 10.8 (0x412CCCCD)
MR1(15:0) = MF32TOUI16round(MR0) = 11 (0x000B)
MR1(31:16) = 0x0000
MR2 = -10.8 (0x0xC12CCCCD)
MR3(15:0) = MF32TOUI16round(MR2) = 0 (0x0000)
MR3(31:16) = 0x0000

MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MF32TOUI32 MRa, MRb Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1010 0000

Description

Convert the 32-bit floating-point value in MRb to an unsigned 32-bit integer and store the
result in MRa.
MRa = F32TOUI32(MRb);

Flags

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MF32TOUI32
MMOVIZ
MF32TOUI32

See also

MF32TOI32 MRa, MRb
MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

MR0,
MR0,
MR1,
MR2,

#12.5
MR0
#-6.5
MR1

;
;
;
;

MR0
MR0
MR1
MR2

=
=
=
=

12.5 (0x41480000)
MF32TOUI32 (MR0) = 12 (0x0000000C)
-6.5 (0xC0D00000)
MF32TOUI32 (MR1) = 0.0 (0x00000000)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

717

Instruction Set

www.ti.com

MFRACF32 MRa, MRb Fractional Portion of a 32-Bit Floating-Point Value
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0000 0000

Description

Returns in MRa the fractional portion of the 32-bit floating-point value in MRb

Flags

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MFRACF32

MR2, #19.625 ; MR2 = 19.625 (0x419D0000)
MR3, MR2
; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0)

See also

718

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MI16TOF32 MRa, MRb Convert 16-Bit Integer to 32-Bit Floating-Point Value
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1000 0000

Description

Convert the 16-bit signed integer in MRb to a 32-bit floating point value and store the
result in MRa.
MRa = MI16TOF32(MRb);

Flags

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MMOVXI
MI16TOF32

MR0, #0x0000
MR0, #0x0004
MR1, MR0

; MR0(31:16) = 0.0 (0x0000)
; MR0(15:0) = 4.0 (0x0004)
; MR1 = MI16TOF32 (MR0) = 4.0 (0x40800000)

MMOVIZ
MMOVXI
MI16TOF32
MSTOP

MR2, #0x0000
MR2, #0xFFFC
MR3, MR2

; MR2(31:16) = 0.0 (0x0000)
; MR2(15:0) = -4.0 (0xFFFC)
; MR3 = MI16TOF32 (MR2) = -4.0 (0xC0800000)

See also

MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

719

Instruction Set

www.ti.com

MI16TOF32 MRa, mem16 Convert 16-Bit Integer to 32-Bit Floating-Point Value
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

mem16

16-bit source memory location to be converted

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 00aa addr

Description

Convert the 16-bit signed integer indicated by the mem16 pointer to a 32-bit floatingpoint value and store the result in MRa.
MRa = MI16TOF32[mem16];

This instruction does not affect any flags:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction:

Example

; Assume A = 4 (0x0004)
;
B = -4 (0xFFFC)
MI16TOF32 MR0, @_A ; MR0 = MI16TOF32(A) = 4.0 (0x40800000)
MI16TOF32 MR1, @_B ; MR1 = MI16TOF32(B) = -4.0 (0xC0800000

See also

720

MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MI32TOF32 MRa, mem32 Convert 32-Bit Integer to 32-Bit Floating-Point Value
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

mem32

32-bit memory source for the MMOV32 operation.

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 01aa addr

Description

Convert the 32-bit signed integer indicated by mem32 to a 32-bit floating point value and
store the result in MRa.
MRa = MI32TOF32[mem32];

Flags

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

;
;
;
;
;
;
;
;
;

Given X, M and
X = IQ24(+2.5)
M = IQ24(+1.5)
B = IQ24(-0.5)

B
=
=
=

are IQ24 numbers:
0x02800000
0x01800000
0xFF800000

Calculate Y = X * M + B
Convert M, X and B from IQ24 to float

_Cla1Task3:
MI32TOF32 MR0, @_M
MI32TOF32 MR1, @_X
MI32TOF32 MR2, @_B
MMPYF32 MR0, MR0, #0x3380
MMPYF32 MR1, MR1, #0x3380
MMPYF32 MR2, MR2, #0x3380
MMPYF32 MR3, MR0, MR1
MADDF32 MR2, MR2, MR3

;
;
;
;
;
;
;
;

MR0 = 0x4BC00000
MR1 = 0x4C200000
MR2 = 0xCB000000
M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
M*X
Y=MX+B = 3.25 (0x40500000)

; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2
; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2
; store result
MSTOP
; end of task

See also

MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

721

Instruction Set

www.ti.com

MI32TOF32 MRa, MRb Convert 32-Bit Integer to 32-Bit Floating-Point Value
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1000 0000

Description

Convert the signed 32-bit integer in MRb to a 32-bit floating-point value and store the
result in MRa.
MRa = MI32TOF32(MRb);

This instruction does not affect any flags:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

; Example1:
;
MMOVIZ
MMOVXI

MR2, #0x1111 ;
MR2, #0x1111 ;
;
MI32TOF32 MR3, MR2
;

See also

722

MR2(31:16) = 4369 (0x1111)
MR2(15:0) = 4369 (0x1111)
MR2 = +286331153 (0x11111111)
MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888)

MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MLSL32 MRa, #SHIFT Logical Shift Left
Operands
MRa

CLA floating-point source/destination register (MR0 to MR3)

#SHIFT

Number of bits to shift (1 to 32)

Opcode

LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1100 0000

Description

Logical shift left of MRa by the number of bits indicated. The number of bits can be 1 to
32.
MARa(31:0) = Logical Shift Left(MARa(31:0) by #SHIFT bits);

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline

This is a single-cycle instruction.

Example

; Given m2 = (int32)32
;
x2 = (int32)64
;
b2 = (int32)-128
;
; Calculate:
;
m2 = m2*2
;
x2 = x2*4
;
b2 = b2*8
;
_Cla1Task3:
MMOV32 MR0, @_m2
; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2
; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2
; MR2 = -128 (0xFFFFFF80)
MLSL32 MR0, #1
; MR0 = 64 (0x00000040)
MLSL32 MR1, #2
; MR1 = 256 (0x00000100)
MLSL32 MR2, #3
; MR2 = -1024 (0xFFFFFC00)
MMOV32 @_m2, MR0
; Store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP
; end of task

See also

MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

723

Instruction Set

www.ti.com

MLSR32 MRa, #SHIFT Logical Shift Right
Operands
MRa

CLA floating-point source/destination register (MR0 to MR3)

#SHIFT

Number of bits to shift (1 to 32)

Opcode

LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1000 0000

Description

Logical shift right of MRa by the number of bits indicated. The number of bits can be 1 to
32. Unlike the arithmetic shift (MASR32), the logical shift does not preserve the number's
sign bit. Every bit in the operand is moved the specified number of bit positions, and the
vacant bit-positions are filled in with zeros
MARa(31:0) = Logical Shift Right(MARa(31:0) by #SHIFT bits);

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1;}

Pipeline

This is a single-cycle instruction.

Example

; Illustrate the difference between MASR32 and MLSR32

See also

724

MMOVIZ MR0, #0xAAAA
MMOVXI MR0, #0x5555

; MR0 = 0xAAAA5555

MMOV32 MR1, MR0
MMOV32 MR2, MR0

; MR1 = 0xAAAA5555
; MR2 = 0xAAAA5555

MASR32 MR1, #1
MLSR32 MR2, #1

; MR1 = 0xD5552AAA
; MR2 = 0x55552AAA

MASR32 MR1, #1
MLSR32 MR2, #1

; MR1 = 0xEAAA9555
; MR2 = 0x2AAA9555

MASR32 MR1, #6
MLSR32 MR2, #6

; MR1 = 0xFFAAAA55
; MR2 = 0x00AAAA55

MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Multiply and
Accumulate with Parallel Move
Operands
MR3

floating-point destination/source register MR3 for the add operation

MR2

CLA floating-point source register MR2 for the add operation

MRd

CLA floating-point destination register (MR0 to MR3) for the multiply operation
MRd cannot be the same register as MRa

MRe

CLA floating-point source register (MR0 to MR3) for the multiply operation

MRf

CLA floating-point source register (MR0 to MR3) for the multiply operation

MRa

CLA floating-point destination register for the MMOV32 operation (MR0 to MR3).
MRa cannot be MR3 or the same register as MRd.

mem32

32-bit source for the MMOV32 operation

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0011 ffee ddaa addr

Description

Multiply and accumulate the contents of floating-point registers and move from register
to memory. The destination register for the MMOV32 cannot be the same as the
destination registers for the MMACF32.
MR3 = MR3 + MR2;
MRd = MRe * MRf;
MRa = [mem32];

Restrictions

The destination registers for the MMACF32 and the MMOV32 must be unique. That is,
MRa cannot be MR3 and MRa cannot be the same register as MRd.

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MMACF32 (add or multiply) generates an underflow condition.
• LVF = 1 if MMACF32 (add or multiply) generates an overflow condition.
MMOV32 sets the NF and ZF flags as follows:
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline

MMACF32 and MMOV32 complete in a single cycle.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

725

Instruction Set
Example 1

www.ti.com
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X
; MAR0 points to X array
MMOVI16 MAR1, #_Y
; MAR1 points to Y array
MNOP
; Delay for MAR0, MAR1 load
MNOP
; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++
; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++
; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1
|| MMOV32 MR0, *MAR0[2]++
MMOV32 MR1, *MAR1[2]++

; MR2 = A = X0 * Y0
; In parallel MR0 = X1, MAR0 += 2
; MR1 = Y1, MAR1 += 2

MMPYF32 MR3, MR0, MR1
|| MMOV32 MR0, *MAR0[2]++
MMOV32 MR1, *MAR1[2]++

; MR3 = B = X1 * Y1
; In parallel MR0 = X2, MAR0 += 2
; MR1 = Y2, MAR2 += 2

MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++
; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++
; MR1 = Y3 M
MACF32 MR3, MR2, MR2, MR0, MR1
|| MMOV32 MR0, *MAR0
MMOV32 MR1, *MAR1

; MR3 = (A + B) + C, MR2 = D = X3 * Y3
; In parallel MR0 = X4
; MR1 = Y4

MMPYF32 MR2, MR0, MR1
|| MADDF32 MR3, MR3, MR2

; MR2 = E = X4 * Y4
; in parallel MR3 = (A + B + C) + D

MADDF32 MR3, MR3, MR2
MMOV32 @_Result, MR3
MSTOP

726

Control Law Accelerator (CLA)

; MR3 = (A + B + C + D) + E
; Store the result
; end of task

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Example 2

; sum = X0*B0 +
;
;
X2 = X1
;
X1 = X0
;
Y2 = Y1
;
_ClaTask2:
MMOV32
MMOV32
MMPYF32
|| MMOV32
MMOVD32
MMPYF32
|| MMOV32
MMOVD32
;
;

X1*B1 + X2*B2 + Y1*A1 + Y2*B2

; Y1 = sum

MR0,
MR1,
MR2,
MR0,
MR1,
MR3,
MR0,
MR1,

@_B2
@_X2
MR1, MR0
@_B1
@_X1
MR1, MR0
@_B0
@_X0

=
=
=
=
=
=
=
=

B2
X2
X2*B2
B1
X1, X2 = X1
X1*B1
B0
X0, X1 = X0

; MR1 = Y2

MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1
MADDF32 MR3, MR3, MR2
|| MMPYF32 MR2, MR1, MR0
MADDF32 MR3, MR3, MR2
MMOV32 @_Y1, MR3
MSTOP

See also

MR0
MR1
MR2
MR0
MR1
MR3
MR0
MR1

MR3 = X1*B1 + X2*B2, MR2 = X0*B0
MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2 M
MOV32 MR1, @_Y2

;
;

;
;
;
;
;
;
;
;

;
;
;
;
;
;

MR1 = Y1, Y2 = Y1
MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
MR2 = Y1*A1
MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
Y1 = MR3
end of task

MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

727

Instruction Set

www.ti.com

MMAXF32 MRa, MRb 32-Bit Floating-Point Maximum
Operands
MRa

CLA floating-point source/destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0010 0000

Description

if(MRa < MRb) MRa = MRb;

Special cases for the output from the MMAXF32 operation:
• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.
This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == MRb) {ZF=1; NF=0;}
if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline

This is a single-cycle instruction.

Example 1

MMOVIZ
MMOVIZ
MMOVIZ
MMAXF32
MMAXF32
MMAXF32
MAXF32

Example 2

; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store it in Result
;
_Cla1Task1:
MMOVI16
MAR1,#_X
; Start address
MUI16TOF32 MR0, @_len
; Length of the array
MNOP
; delay for MAR1 load
MNOP
; delay for MAR1 load
MMOV32
MR1, *MAR1[2]++
; MR1 = X0
LOOP
MMOV32
MR2, *MAR1[2]++
; MR2 = next element
MMAXF32
MR1, MR2
; MR1 = MAX(MR1, MR2)
MADDF32
MR0, MR0, #-1.0
; Decrememt the counter
MCMPF32
MR0 #0.0
; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD
LOOP, NEQ
; Branch if not equal to zero
MMOV32
@_Result, MR1
; Always executed
MNOP
; Always executed
MNOP
; Always executed
MSTOP
; End of task

728

Control Law Accelerator (CLA)

MR0, #5.0
MR1, #-2.0
MR2, #-1.5
MR2, MR1
MR1, MR2
MR2, MR0
MR0, MR2

;
;
;
;
;
;
;

MR0
MR1
MR2
MR2
MR1
MR2
MR2

=
=
=
=
=
=
=

5.0
-2.0
-1.5
-1.5,
-1.5,
5.0,
5.0,

(0x40A00000)
(0xC0000000)
(0xBFC00000)
ZF = NF = 0
ZF = 0, NF = 1
ZF = 0, NF = 1
ZF = 1, NF = 0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

See also

MCMPF32 MRa, MRb
MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

729

Instruction Set

www.ti.com

MMAXF32 MRa, #16FHi 32-Bit Floating-Point Maximum
Operands
MRa

CLA floating-point source/destination register (MR0 to MR3)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 1001 0000 00aa

Description

Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is larger, then load it into MRa.
if(MRa < #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler will accept either a hex or float as the immediate
value. That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMAXF32 operation:
• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.
This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == #16FHi:0) {ZF=1; NF=0;}
if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MMOVIZ
MMOVIZ
MMAXF32
MMAXF32
MMAXF32
MMAXF32

See also

730

MR0,
MR1,
MR2,
MR0,
MR1,
MR2,
MR2,

#5.0
#4.0
#-1.5
#5.5
#2.5
#-1.0
#-1.0

;
;
;
;
;
;
;

MR0
MR1
MR2
MR0
MR1
MR2
MR2

= 5.0
= 4.0
= -1.5
= 5.5,
= 4.0,
= -1.0,
= -1.5,

(0x40A00000)
(0x40800000)
(0xBFC00000)
ZF = 0, NF =
ZF = 0, NF =
ZF = 0, NF =
ZF = 1, NF =

1
0
1
0

MMAXF32 MRa, MRb
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMINF32 MRa, MRb 32-Bit Floating-Point Minimum
Operands
MRa

CLA floating-point source/destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0100 0000

Description

if(MRa > MRb) MRa = MRb;

Special cases for the output from the MMINF32 operation:
• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.
Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == MRb) {ZF=1; NF=0;}
if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline

This is a single-cycle instruction.

Example 1

MMOVIZ MR0, #5.0
MMOVIZ MR1, #4.0
MMOVIZ MR2, #-1.5
MMINF32 MR0, MR1
MMINF32 MR1, MR2
MMINF32 MR2, MR1
MMINF32 MR1, MR0

Example 2

;
; X is an array of 32-bit floating-point values
; Find the minimum value in an array X
; and store it in Result
;

;
;
;
;
;
;
;

MR0
MR1
MR2
MR0
MR1
MR2
MR2

=
=
=
=
=
=
=

5.0 (0x40A00000)
4.0 (0x40800000)
-1.5 (0xBFC00000)
4.0, ZF = 0, NF = 0
-1.5, ZF = 0, NF = 0
-1.5, ZF = 1, NF = 0
-1.5, ZF = 0, NF = 1

_Cla1Task1:
MMOVI16
MAR1,#_X
MUI16TOF32 MR0, @_len
MNOP
MNOP
MMOV32
MR1, *MAR1[2]++
LOOP
MMOV32
MR2, *MAR1[2]++
MMINF32
MR1, MR2
MADDF32
MR0, MR0, #-1.0
MCMPF32
MR0 #0.0
MNOP
MNOP
MNOP
MBCNDD
LOOP, NEQ
MMOV32
@_Result, MR1
MNOP
MNOP
MSTOP

;
;
;
;
;

Start address
Length of the array
delay for MAR1 load
delay for MAR1 load
MR1 = X0

;
;
;
;

MR2 = next element
MR1 = MAX(MR1, MR2)
Decrememt the counter
Set/clear flags for MBCNDD

;
;
;
;
;

Branch
Always
Always
Always
End of

if not equal to zero
executed
executed
executed
task

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

731

Instruction Set
See also

732

www.ti.com

MMAXF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMINF32 MRa, #16FHi

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMINF32 MRa, #16FHi 32-Bit Floating-Point Minimum
Operands
MRa

floating-point source/destination register (MR0 to MR3)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 1001 0100 00aa

Description

Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is smaller, then load it into MRa.
if(MRa > #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler will accept either a hex or float as the immediate
value. That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMINF32 operation:
• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.
Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == #16FHi:0)
{ZF=1; NF=0;}
if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MMOVIZ
MMOVIZ
MMINF32
MMINF32
MMINF32
MMINF32

See also

MR0,
MR1,
MR2,
MR0,
MR1,
MR2,
MR2,

#5.0
#4.0
#-1.5
#5.5
#2.5
#-1.0
#-1.5

;
;
;
;
;
;
;

MR0
MR1
MR2
MR0
MR1
MR2
MR2

= 5.0
= 4.0
= -1.5
= 5.0,
= 2.5,
= -1.5,
= -1.5,

(0x40A00000)
(0x40800000)
(0xBFC00000)
ZF = 0, NF =
ZF = 0, NF =
ZF = 0, NF =
ZF = 1, NF =

1
0
1
0

MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, MRb

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

733

Instruction Set

www.ti.com

MMOV16 MARx, MRa, #16I Load the Auxiliary Register with MRa + 16-bit Immediate Value
Operands

Opcode

MARx

Auxiliary register MAR0 or MAR1

MRa

CLA Floating-point register (MR0 to MR3)

#16I

16-bit immediate value

LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR0, MRa, #16I)
MSW: 0111 1111 1101 00AA
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR1, MRa, #16I)
MSW: 0111 1111 1111 00AA

Description

Load the auxiliary register, MAR0 or MAR1, with MRa(15:0) + 16-bit immediate value.
Refer to the pipeline section for important information regarding this instruction.
MARx = MRa(15:0) + #16I;

Flags

Pipeline

This instruction does not modify flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

This is a single-cycle instruction. The load of MAR0 or MAR1 will occur in the EXE
phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing
will occur in the D2 phase of the pipeline. Therefore the following applies when loading
the auxiliary registers:
• I1 and I2
The two instructions following MMOV16 will use MAR0/MAR1 before the update
occurs. Thus these two instructions will use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to postincrement addressing occur in the D2 phase. Thus I3 cannot use the auxiliary
register or there will be a conflict. In the case of a conflict, the update due to addressmode post increment will win and the auxiliary register will not be updated with #_X.
• I4
Starting with the 4th instruction MAR0 or MAR1 will be the new value loaded with
MMOVI16.
; Assume MAR0 is 50, MR0 is 10, and #_X is 20
MMOV16 MAR0,

2>
3>
4>
5>

;
;
;
;
;

I1
I2
I3
I4
I5

; Load MAR0 with address
Will use the old value of
Will use the old value of
Cannot use MAR0
Will use the new value of

of X (20) + MR0 (10)
MAR0 (50)
MAR0 (50)
MAR0 (30)

Table 5-16. Pipeline Activity For MMOV16 MARx, MRa , #16I

734

Instruction

F1

F2

D1

D2

R1

R2

MMOV16 MAR0, MR0, #_X

MMOV16

I1

I1

MMOV16

I2

I2

I1

MMOV16

I3

I3

I2

I1

MMOV16

I4

I4

I3

I2

I1

MMOV16

I5

I5

I4

I3

I2

I1

MMOV16

I6

I6

I5

I4

I3

I2

I1

E

W

MMOV1
6

Control Law Accelerator (CLA)
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Example 1

; Calculate an offset into a sin/cos table
;
_Cla1Task1:
MMOV32 MR0,@_rad
; MR0 =
MMOV32 MR1,@_TABLE_SIZEDivTwoPi ; MR1 =
MMPYF32 MR1,MR0,MR1
; MR1 =
|| MMOV32 MR2,@_TABLE_MASK
; MR2 =
MF32TOI32 MR3,MR1
; MR3 =
MAND32 MR3,MR3,MR2
; MR3 =
MLSL32 MR3,#1
; MR3 =

||

Example 2

rad
TABLE_SIZE/(2*Pi)
rad* TABLE_SIZE/(2*Pi)
TABLE_MASK
K=int(rad*TABLE_SIZE/(2*Pi))
K & TABLE_MASK
K * 2

MMOV16 MAR0,MR3,#_Cos0
MFRACF32 MR1,MR1
MMOV32 MR0,@_TwoPiDivTABLE_SIZE
MMPYF32 MR1,MR1,MR0
MMOV32 MR0,@_Coef3

;
;
;
;

MAR0 K*2+addr of table.Cos0
I1
I2
I3

MMOV32 MR2,*MAR0[#-64]++
...
...
MSTOP ; end of task

; MR2 = *MAR0, MAR0 += (-64)

; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
;
T_sys = 1/200MHz = 5ns
;
T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg
0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval
N + 1, N
.break
N = 28
.endloop
MMOVZ16
MR0, @_ConversionCount
;I29 Current Conversion
MMOV16
MAR1, MR0, #_VoltageCLA
;I30 Next array location
MUI16TOF32 MR0, MR0
;I31 Convert count to float32
MADDF32
MR0, MR0, #1.0
;I32 Add 1 to conversion count
MCMPF32
MR0, #NUM_DATA_POINTS.0
;I33 Compare count to max
MF32TOUI16 MR0, MR0
;I34 Convert count to Uint16
MNOP
;I35 Wait till I36 to read result
MMOVZ16
MR2, @_AdcaResultRegs.ADCRESULT1
;I36 Read ADCRESULT1
MMOV16
*MAR1, MR2
; Store ADCRESULT1
MBCNDD
_RestartCount, GEQ
; If count >= NUM_DATA_POINTS
MMOVIZ
MR1, #0.0
; Always executed: MR1=0
MNOP
MNOP
MMOV16
@_ConversionCount, MR0
; If branch not taken
MSTOP
; store current count

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

735

Instruction Set

www.ti.com
_RestartCount
MMOV16
@_ConversionCount, MR1
MSTOP

; If branch taken, restart count
; end of task

; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ
MR0, #0.0
MMOV16
@_ConversionCount, MR0
MSTOP
_ClaT8End:

See also

736

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMOV16 MARx, mem16 Load MAR1 with 16-bit Value
Operands

Opcode

MARx

CLA auxiliary register MAR0 or MAR1

mem16

16-bit destination memory accessed using one of the available addressing modes

LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR0, mem16)
MSW: 0111 0110 0000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR1, mem16)
MSW: 0111 0110 0100 addr

Description

Load MAR0 or MAR1 with the 16-bit value pointed to by mem16. Refer to the pipeline
section for important information regarding this instruction.
MAR1 = [mem16];

Flags

Pipeline

No flags MSTF flags are affected.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

This is a single-cycle instruction. The load of MAR0 or MAR1 will occur in the EXE
phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing
will occur in the D2 phase of the pipeline. Therefore the following applies when loading
the auxiliary registers:
• I1 and I2
The two instructions following MMOV16 will use MAR0/MAR1 before the update
occurs. Thus these two instructions will use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to postincrement addressing occur in the D2 phase. Thus I3 cannot use the auxiliary
register or there will be a conflict. In the case of a conflict, the update due to addressmode post increment will win send the auxiliary register will not be updated with #_X.
• I4
Starting with the 4th instruction MAR0 or MAR1 will be the new value loaded with
MMOV16.
; Assume MAR0 is 50 and @_X is 20
MMOV16 MAR0,

2>
3>
4>
5>

;
;
;
;
;
;

Load MAR0 with the contents of X (20)
I1 Will use the old value of MAR0 (50)
I2 Will use the old value of MAR0 (50)
I3 Cannot use MAR0
I4 Will use the new value of MAR0 (20)
I5

Table 5-17. Pipeline Activity For MMOV16 MAR0/MAR1, mem16
Instruction

F1

MMOV16 MAR0, @_X

MMOV16

F2

D1

D2

I1

I1

MMOV16

I2

I2

I1

MMOV16

I3

I3

I2

I1

MMOV16

I4

I4

I3

I2

I1

MMOV16

I5

I5

I4

I3

I2

I1

MMOV16

I6

I6

I5

I4

I3

I2

I1

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

R1

R2

E

W

MMOV1
6

Control Law Accelerator (CLA) 737

Instruction Set
Example

www.ti.com
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
;
T_sys = 1/200MHz = 5ns
;
T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg
0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval
N + 1, N
.break
N = 28
.endloop
MMOVZ16
MR0, @_ConversionCount
;I29 Current Conversion
MMOV16
MAR1, MR0, #_VoltageCLA
;I30 Next array location
MUI16TOF32 MR0, MR0
;I31 Convert count to float32
MADDF32
MR0, MR0, #1.0
;I32 Add 1 to conversion count
MCMPF32
MR0, #NUM_DATA_POINTS.0
;I33 Compare count to max
MF32TOUI16 MR0, MR0
;I34 Convert count to Uint16
MNOP
;I35 Wait till I36 to read result
MMOVZ16
MR2, @_AdcaResultRegs.ADCRESULT1
;I36 Read ADCRESULT1
MMOV16
*MAR1, MR2
; Store ADCRESULT1
MBCNDD
_RestartCount, GEQ
; If count >= NUM_DATA_POINTS
MMOVIZ
MR1, #0.0
; Always executed: MR1=0
MNOP
MNOP
MMOV16
@_ConversionCount, MR0
; If branch not taken
MSTOP
; store current count
_RestartCount
MMOV16
@_ConversionCount, MR1
MSTOP

; If branch taken, restart count
; end of task

; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ
MR0, #0.0
MMOV16
@_ConversionCount, MR0
MSTOP
_ClaT8End:

See also

738

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMOV16 mem16, MARx Move 16-Bit Auxiliary Register Contents to Memory
Operands

Opcode

mem16

16-bit destination memory accessed using one of the available addressing modes

MARx

CLA auxiliary register MAR0 or MAR1

LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR0)
MSW: 0111 0110 1000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR1)
MSW: 0111 0110 1100 addr

Description

Store the contents of MAR0 or MAR1 in the 16-bit memory location pointed to by
mem16.
[mem16] = MAR0;

Flags

Pipeline

No flags MSTF flags are affected.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

This is a single-cycle instruction.

Example
See also

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

739

Instruction Set

www.ti.com

MMOV16 mem16, MRa Move 16-Bit Floating-Point Register Contents to Memory
Operands
mem16

16-bit destination memory accessed using one of the available addressing modes

MRa

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 11aa addr

Description

Move 16-bit value from the lower 16-bits of the floating-point register (MRa(15:0)) to the
location pointed to by mem16.
[mem16] = MRa(15:0);

No flags MSTF flags are affected.

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
;
T_sys = 1/200MHz = 5ns
;
T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg
0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval
N + 1, N
.break
N = 28
.endloop
MMOVZ16
MR0, @_ConversionCount
;I29 Current Conversion
MMOV16
MAR1, MR0, #_VoltageCLA
;I30 Next array location
MUI16TOF32 MR0, MR0
;I31 Convert count to float32
MADDF32
MR0, MR0, #1.0
;I32 Add 1 to conversion count
MCMPF32
MR0, #NUM_DATA_POINTS.0
;I33 Compare count to max
MF32TOUI16 MR0, MR0
;I34 Convert count to Uint16
MNOP
;I35 Wait till I36 to read result
MMOVZ16
MR2, @_AdcaResultRegs.ADCRESULT1
;I36 Read ADCRESULT1
MMOV16
*MAR1, MR2
; Store ADCRESULT1
MBCNDD
_RestartCount, GEQ
; If count >= NUM_DATA_POINTS
MMOVIZ
MR1, #0.0
; Always executed: MR1=0
MNOP
MNOP
MMOV16
@_ConversionCount, MR0
; If branch not taken
MSTOP
; store current count

740

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

_RestartCount
MMOV16
@_ConversionCount, MR1
MSTOP

; If branch taken, restart count
; end of task

; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ
MR0, #0.0
MMOV16
@_ConversionCount, MR0
MSTOP
_ClaT8End:

See also

MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

741

Instruction Set

www.ti.com

MMOV32 mem32, MRa Move 32-Bit Floating-Point Register Contents to Memory
Operands
MRa

floating-point register (MR0 to MR3)

mem32

32-bit destination memory accessed using one of the available addressing modes

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 11aa addr

Description

Move from MRa to 32-bit memory location indicated by mem32.
[mem32] = MRa;

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

No flags affected.
Pipeline

This is a single-cycle instruction.

Example

; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating point arrays;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16
MAR0, #_X
; MAR0 points to X array
MMOVI16
MAR1, #_Y
; MAR1 points to Y array
MNOP
; Delay for MAR0, MAR1 load
MNOP
; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32
MR0, *MAR0[2]++
; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32
MR1, *MAR1[2]++
; MR1 = Y0, MAR1 += 2
MMPYF32
MR2, MR0, MR1
; MR2 = A = X0 * Y0
|| MMOV32
MR0, *MAR0[2]++
; In parallel MR0 = X1, MAR0 += 2
MMOV32
MR1, *MAR1[2]++
; MR1 = Y1, MAR1 += 2
MMPYF32
MR3, MR0, MR1
; MR3 = B = X1 * Y1
|| MMOV32
MR0, *MAR0[2]++
; In parallel MR0 = X2, MAR0 += 2
MMOV32
MR1, *MAR1[2]++
; MR1 = Y2, MAR2 += 2

See also

742

MMACF32
|| MMOV32
MMOV32

MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
MR0, *MAR0[2]++
; In parallel MR0 = X3
MR1, *MAR1[2]++
; MR1 = Y3

MMACF32
|| MMOV32
MMOV32
MMPYF32
|| MADDF32
MADDF32
MMOV32

MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
MR0, *MAR0
; In parallel MR0 = X4
MR1, *MAR1
; MR1 = Y4
MR2, MR0, MR1
; MR2 = E = X4 * Y4
MR3, MR3, MR2
; in parallel MR3 = (A + B + C) + D
MR3, MR3, MR2
; MR3 = (A + B + C + D) + E
@_Result, MR3
; Store the result MSTOP ; end of task

MMOV32 mem32, MSTF

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMOV32 mem32, MSTF Move 32-Bit MSTF Register to Memory
Operands
MSTF

floating-point status register

mem32

32-bit destination memory

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0100 addr

Description

Copy the CLA's floating-point status register, MSTF, to memory.
[mem32] = MSTF;

Flags

Pipeline

This instruction does not modify flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

This is a single-cycle instruction.

Example
See also

MMOV32 mem32, MRa

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

743

Instruction Set

www.ti.com

MMOV32 MRa, mem32 {, CNDF} Conditional 32-Bit Move
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

mem32

32-bit memory location accessed using one of the available addressing modes

CNDF

optional condition.

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 00cn dfaa addr

Description

If the condition is true, then move the 32-bit value referenced by mem32 to the floatingpoint register indicated by MRa.
if (CNDF == TRUE) MRa = [mem32];

CNDF is one of the following conditions:
Encode

(1)

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

1111

UNCF

Unconditional with flag
modification

None

(1)
(2)

(2)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

if(CNDF == UNCF)
{
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }
}
else No flags modified;

Pipeline

744

This is a single-cycle instruction.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Example

; Given A, B, X, M1 and M2 are 32-bit floating-point
; numbers
;
; if(A == B) calculate Y = X*M1
; if(A! = B) calculate Y = X*M2
;
_Cla1Task5:
MMOV32
MR0, @_A
MMOV32
MR1, @_B
MCMPF32
MR0, MR1
MMOV32
MR2, @_M1, EQ ; if A == B, MR2 = M1
;
Y = M1*X
MMOV32
MR2, @_M2, NEQ ; if A! = B, MR2 = M2
;
Y = M2*X
MMOV32
MR3, @_X
MMPYF32
MR3, MR2, MR3 ; Calculate Y
MMOV32
@_Y, MR3
; Store Y
MSTOP
; end of task

See also

MMOV32 MRa, MRb {, CNDF}
MMOVD32 MRa, mem32

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

745

Instruction Set

www.ti.com

MMOV32 MRa, MRb {, CNDF} Conditional 32-Bit Move
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

CNDF

optional condition.

Opcode

LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1100 0000

Description

If the condition is true, then move the 32-bit value in MRb to the floating-point register
indicated by MRa.
if (CNDF == TRUE) MRa = MRb;

CNDF is one of the following conditions:
Encode

(3)

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

1111

UNCF

Unconditional with flag
modification

None

(3)
(4)

(4)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF, and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

if(CNDF == UNCF)
{
NF = MRa(31); ZF = 0;
if(MRa(30:23) == 0) {ZF = 1; NF = 0;}
}
else No flags modified;

Pipeline

746

This is a single-cycle instruction.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Example

See also

; Given: X = 8.0
;
Y = 7.0
;
A = 2.0
;
B = 5.0
; _ClaTask1
MMOV32
MR3,
MMOV32
MR0,
MMAXF32 MR3,
MMOV32
MR1,
MMOV32
MR1,
MMOV32
MR2,
MMOV32
MR2,
MSTOP

@_X
@_Y
MR0
@_A,
@_B,
MR1,
MR0,

GT
LT
GT
LT

;
;
;
;
;
;
;

MR3 = X = 8.0
MR0 = Y = 7.0
ZF = 0, NF = 0,
true, MR1 = A =
false, does not
true, MR2 = MR1
false, does not

MR3 = 8.0
2.0
load MR1
= 2.0
load MR2

MMOV32 MRa, mem32 {,CNDF}

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

747

Instruction Set

www.ti.com

MMOV32 MSTF, mem32 Move 32-Bit Value from Memory to the MSTF Register
Operands
MSTF

CLA status register

mem32

32-bit source memory location

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0000 addr

Description

Move from memory to the CLA's status register MSTF. This instruction is most useful
when nesting function calls (via MCCNDD).
MSTF = [mem32];

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

Yes

Yes

Yes

Yes

Yes

Loading the status register will overwrite all flags and the RPC field. The MEALLOW field
is not affected.
Pipeline

This is a single-cycle instruction.

Example
See also

748

MMOV32 mem32, MSTF

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMOVD32 MRa, mem32 Move 32-Bit Value from Memory with Data Copy
Operands
MRa

CLA floating-point register (MR0 to MR3)

mem32

32-bit memory location accessed using one of the available addressing modes

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 00aa addr

Description

Move the 32-bit value referenced by mem32 to the floating-point register indicated by
MRa.
MRa = [mem32];
[mem32+2] = [mem32];

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0){ ZF = 1; NF = 0; }

Pipeline

This is a single-cycle instruction.

Example

; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
;
X2 = X1
;
X1 = X0
;
Y2 = Y1
;
Y1 = sum
;
_Cla1Task2:
MMOV32 MR0, @_B2
; MR0 = B2
MMOV32 MR1, @_X2
; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1
; MR0 = B1
MMOVD32 MR1, @_X1
; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0
; MR0 = B0
MMOVD32 MR1, @_X0
; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2
MMOV32 MR1, @_Y2

; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1

||

See also

MMOVD32 MR1,@_Y1
MADDF32 MR3, MR3, MR2
MMPYF32 MR2, MR1, MR0
MADDF32 MR3, MR3, MR2
MMOV32 @_Y1, MR3
MSTOP

;
;
;
;
;
;

MR1 = Y1, Y2 = Y1
MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
MR2 = Y1*A1
MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
Y1 = MR3
end of task

MMOV32 MRa, mem32 {,CNDF}

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

749

Instruction Set

www.ti.com

MMOVF32 MRa, #32F Load the 32-Bits of a 32-Bit Floating-Point Register
Operands

This instruction is an alias for MMOVIZ and MMOVXI instructions. The second operand
is translated by the assembler such that the instruction becomes:
MMOVIZ MRa, #16FHiHex MMOVXI MRa, #16FLoHex
MRa
CLA floating-point destination register (MR0 to MR3)
#32F

immediate float value represented in floating-point representation

Opcode

LSW:
MSW:
LSW:
MSW:

Description

Note: This instruction accepts the immediate operand only in floating-point
representation. To specify the immediate value as a hex value (IEEE 32-bit floatingpoint format) use the MOVI32 MRa, #32FHex instruction.

IIII
0111
IIII
0111

IIII
1000
IIII
1000

IIII
0100
IIII
1000

IIII (opcode of MMOVIZ MRa, #16FHiHex)
00aa
IIII (opcode of MMOVXI MRa, #16FLoHex)
00aa

Load the 32-bits of MRa with the immediate float value represented by #32F.
#32F is a float value represented in floating-point representation. The assembler will only
accept a float value represented in floating-point representation. That is, 3.0 can only be
represented as #3.0. #0x40400000 will result in an error.
MRa = #32F;

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

Depending on #32FH, this instruction takes one or two cycles. If all of the lower 16-bits
of the IEEE 32-bit floating-point format of #32F are zeros, then the assembler will
convert MMOVF32 into only MMOVIZ instruction. If the lower 16-bits of the IEEE 32-bit
floating-point format of #32F are not zeros, then the assembler will convert MMOVF32
into MMOVIZ and MMOVXI instructions.

Example

MMOVF32 MR1, #3.0

; MR1 = 3.0 (0x40400000)
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040

MMOVF32 MR2, #0.0

; MR2 = 0.0 (0x00000000)
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0

MMOVF32 MR3, #12.265 ;
;
;
;

See also

750

MR3 = 12.625 (0x41443D71)
Assembler converts this instruction as
MMOVIZ MR3, #0x4144
MMOVXI MR3, #0x3D71

MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex
MMOVI32 MRa, #32FHex

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMOVI16 MARx, #16I Load the Auxiliary Register with the 16-Bit Immediate Value
Operands

Opcode

MARx

Auxiliary register MAR0 or MAR1

#16I

16-bit immediate value

LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR0, #16I)
MSW: 0111 1111 1100 0000
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR1, #16I)
MSW: 0111 1111 1110 0000

Description

Load the auxiliary register, MAR0 or MAR1, with a 16-bit immediate value. Refer to the
pipeline section for important information regarding this instruction.
MARx = #16I;

Flags

Pipeline

This instruction does not modify flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

This is a single-cycle instruction. The immediate load of MAR0 or MAR1 will occur in the
EXE phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect
addressing will occur in the D2 phase of the pipeline. Therefore the following applies
when loading the auxiliary registers:
• I1 and I2
The two instructions following MMOVI16 will use MAR0/MAR1 before the update
occurs. Thus these two instructions will use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to postincrement addressing occur in the D2 phase. Thus I3 cannot use the auxiliary
register or there will be a conflict. In the case of a conflict, the update due to addressmode post increment will win snd the auxiliary register will not be updated with #_X.
• I4
Starting with the 4th instruction MAR0 or MAR1 will be the new value loaded with
MMOVI16.
;

Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X





....

;
;
;
;
;

I1
I2
I3
I4
I5

; Load MAR0 with address
Will use the old value of
Will use the old value of
Cannot use MAR0
Will use the new value of

of X (20)
MAR0 (50)
MAR0 (50)
MAR0 (20)

Table 5-18. Pipeline Activity For MMOVI16 MAR0/MAR1, #16I
Instruction

F1

MMOVI16 MAR0, #_X

MMOVI16

F2

D1

D2

I1

I1

MMOVI16

I2

I2

I1

MMOVI16

I3

I3

I2

I1

MMOVI16

I4

I4

I3

I2

I1

MMOVI16

I5

I5

I4

I3

I2

I1

MMOVI16

I6

I6

I5

I4

I3

I2

I1

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

R1

R2

E

W

MMOVI
16

Control Law Accelerator (CLA)

751

Instruction Set

www.ti.com

MMOVI32 MRa, #32FHex Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate
Operands
MRa

floating-point register (MR0 to MR3)

#32FHex

A 32-bit immediate value that represents an IEEE 32-bit floating-point value.

This instruction is an alias for MMOVIZ and MMOVXI instructions. The second operand
is translated by the assembler such that the instruction becomes:
MMOVIZ MRa, #16FHiHex
MMOVXI MRa, #16FLoHex

Opcode

LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description

Note: This instruction only accepts a hex value as the immediate operand. To specify the
immediate value with a floating-point representation use the MMOVF32 MRa, #32F
instruction.
Load the 32-bits of MRa with the immediate 32-bit hex value represented by #32Fhex.
#32Fhex is a 32-bit immediate hex value that represents the IEEE 32-bit floating-point
value of a floating-point number. The assembler will only accept a hex immediate value.
That is, 3.0 can only be represented as #0x40400000. #3.0 will result in an error.
MRa = #32FHex;

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

Depending on #32FHex, this instruction takes one or two cycles. If all of the lower 16bits of #32FHex are zeros, then assembler will convert MOVI32 to the MMOVIZ
instruction. If the lower 16-bits of #32FHex are not zeros, then assembler will convert
MOVI32 to a MMOVIZ and a MMOVXI instruction.

Example

MOVI32

See also

752

MR1, #0x40400000 ; MR1 = 0x40400000
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040

MOVI32

MR2, #0x00000000

; MR2 = 0x00000000
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0

MOVI32

MR3, #0x40004001

;
;
;
;

MR3 = 0x40004001
Assembler converts this instruction as
MMOVIZ MR3, #0x4000
MMOVXI MR3, #0x4001

MOVI32

MR0, #0x00004040

;
;
;
;

MR0 = 0x00004040
Assembler converts this instruction as
MMOVIZ MR0, #0x0000
MMOVXI MR0, #0x4040

MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex
MMOVF32 MRa, #32F

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMOVIZ MRa, #16FHi Load the Upper 16-Bits of a 32-Bit Floating-Point Register
Operands
MRa

floating-point register (MR0 to MR3)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 1000 0100 00aa

Description

Load the upper 16-bits of MRa with the immediate value #16FHi and clear the low 16bits of MRa.
#16FHiHex is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. The
assembler will only accept a decimal or hex immediate value. That is, -1.5 can be
represented as #-1.5 or #0xBFC0.
By itself, MMOVIZ is useful for loading a floating-point register with a constant in which
the lowest 16-bits of the mantissa are 0. Some examples are 2.0 (0x40000000), 4.0
(0x40800000), 0.5 (0x3F000000), and -1.5 (0xBFC00000). If a constant requires all 32bits of a floating-point register to be iniitalized, then use MMOVIZ along with the
MMOVXI instruction.
MRa(31:16) = #16FHi;
MRa(15:0) = 0;

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

; Load MR0 and MR1 with -1.5 (0xBFC00000)
MMOVIZ
MR0, #0xBFC0
; MR0 = 0xBFC00000 (1.5)
MMOVIZ
MR1, #-1.5
; MR1 = -1.5 (0xBFC00000)
; Load MR2 with pi = 3.141593 (0x40490FDB)
MMOVIZ
MR2, #0x4049
; MR2 = 0x40490000
MMOVXI
MR2, #0x0FDB
; MR2 = 0x40490FDB

See also

MMOVF32 MRa, #32F
MMOVI32 MRa, #32FHex
MMOVXI MRa, #16FLoHex

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

753

Instruction Set

www.ti.com

MMOVZ16 MRa, mem16 Load MRx With 16-bit Value
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

mem16

16-bit source memory location

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 10aa addr

Description

Move the 16-bit value referenced by mem16 to the floating-point register indicated by
MRa.
MRa(31:16) = 0;
MRa(15:0) = [mem16];

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
NF = 0;
if (MRa(31:0)== 0) { ZF = 1; }

Pipeline

754

This is a single-cycle instruction.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMOVXI MRa, #16FLoHex Move Immediate to the Low 16-Bits of a Floating-Point Register
Operands
MRa

CLA floating-point register (MR0 to MR3)

#16FLoHex

A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit
floating-point value. The upper 16-bits will not be modified.

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 1000 1000 00aa

Description

Load the low 16-bits of MRa with the immediate value #16FLoHex. #16FLoHex
represents the lower 16-bits of an IEEE 32-bit floating-point value. The upper 16-bits of
MRa will not be modified. MMOVXI can be combined with the MMOVIZ instruction to
initialize all 32-bits of a MRa register.
MRa(15:0) = #16FLoHex;
MRa(31:16) = Unchanged;

Flags
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

; Load MR0 with pi = 3.141593 (0x40490FDB)
MMOVIZ
MR0,#0x4049
; MR0 = 0x40490000
MMOVXI
MR0,#0x0FDB
; MR0 = 0x40490FDB

See also

MMOVIZ MRa, #16FHi

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

755

Instruction Set

www.ti.com

MMPYF32 MRa, MRb, MRc 32-Bit Floating-Point Multiply
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

MRc

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0000 0000

Description

Multiply the contents of two floating-point registers.
MRa = MRb * MRc;

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example

; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32
MR1, @_Den
; MR1 = Den
MEINVF32
MR2, MR1
; MR2 = Ye = Estimate(1/Den)
MMPYF32
MR3, MR2, MR1
; MR3 = Ye*Den
MSUBF32
MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32
MR2, MR2, MR3
; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32
MR3, MR2, MR1
; MR3 = Ye*Den
|| MMOV32
MR0, @_Num
; MR0 = Num
MSUBF32
MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32
MR2, MR2, MR3
; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32
MR1, @_Den
; Reload Den To Set Sign
MNEGF32
MR0, MR0, EQ
; if(Den == 0.0) Change Sign Of Num
MMPYF32
MR0, MR2, MR0
; MR0 = Y = Ye*Num
MMOV32
@_Dest, MR0
; Store result
MSTOP
; end of task

See also

MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

756

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMPYF32 MRa, #16FHi, MRb 32-Bit Floating-Point Multiply
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

MRc

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 baaa

Description

Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, MRb, #16FHi.
Flags

This instruction modifies the following flags in the MSTF register:.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example 1

; Same as example 2 but #16FHi
MMOVIZ
MR3, #2.0
;
MMPYF32
MR0, #3.0, MR3 ;
MMOV32
@_X, MR0
;

Example 2

; Same as example 1 but #16FHi is
MMOVIZ
MR3, #2.0
;
MMPYF32
MR0, #0x4040, MR3 ;
MMOV32
@_X, MR0
;

is represented in float
MR3 = 2.0 (0x40000000)
MR0 = 3.0 * MR3 = 6.0 (0x40C00000)
Save the result in variable X
represented in Hex
MR3 = 2.0 (0x40000000)
MR0 = 0x4040 * MR3 = 6.0 (0x40C00000)
Save the result in variable X

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

757

Instruction Set

www.ti.com

Example 3

; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
;
_Cla1Task2:
;
; Convert M, X and B from IQ24 to float
MI32TOF32
MR0, @_M
; MR0 = 0x4BC00000
MI32TOF32
MR1, @_X
; MR1 = 0x4C200000
MI32TOF32
MR2, @_B
; MR2 = 0xCB000000
MMPYF32
MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32
MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32
MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32
MR3, MR0, MR1
; M*X
MADDF32
MR2, MR2, MR3
; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32
MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32
MR2, MR2
; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2
; store result
MSTOP
; end of task

See also

MMPYF32 MRa, MRb, #16FHi
MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

758

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMPYF32 MRa, MRb, #16FHi 32-Bit Floating-Point Multiply
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 baaa

Description

Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = MRb * #16FHi:0;

This instruction can also be writen as MMPYF32 MRa, #16FHi, MRb.
Flags

This instruction modifies the following flags in the MSTF register:.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example 1

;Same as example 2
MMOVIZ
MR3,
MMPYF32
MR0,
MMOV32
@_X,

Example 2

;Same as above example but #16FHi is represented in Hex
MMOVIZ
MR3, #2.0
; MR3 = 2.0 (0x40000000)
MMPYF32
MR0, MR3, #0x4040 ; MR0 = MR3 * 0x4040 = 6.0 (0x40C00000)
MMOV32
@_X, MR0
; Save the result in variable X

but #16FHi
#2.0
MR3, #3.0
MR0

is represented in float
; MR3 = 2.0 (0x40000000)
; MR0 = MR3 * 3.0 = 6.0 (0x40C00000)
; Save the result in variable X

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

759

Instruction Set
Example 3

www.ti.com
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
_Cla1Task2:
;
; Convert M, X and B from IQ24 to float
MI32TOF32
MR0, @_M
; MR0 = 0x4BC00000
MI32TOF32
MR1, @_X
; MR1 = 0x4C200000
MI32TOF32
MR2, @_B
; MR2 = 0xCB000000
MMPYF32
MR0, #0x3380, MR0 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32
MR1, #0x3380, MR1 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32
MR2, #0x3380, MR2 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32
MR3, MR0, MR1
; M*X
MADDF32
MR2, MR2, MR3
; Y=MX+B = 3.25 (0x40500000)
; Convert Y from
MMPYF32
MF32TOI32
MMOV32
MSTOP

See also

760

float32 to IQ24
MR2, #0x4B80, MR2 ; Y * 1*2^24
MR2, MR2
; IQ24(Y) = 0x03400000
@_Y, MR2
; store result
; end of task

MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf 32-Bit Floating-Point Multiply with Parallel
Add
Operands
MRa

CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd

MRb

CLA floating-point source register for MMPYF32 (MR0 to MR3)

MRc

CLA floating-point source register for MMPYF32 (MR0 to MR3)

MRd

CLA floating-point destination register for MADDF32 (MR0 to MR3)
MRd cannot be the same register as MRa

MRe

CLA floating-point source register for MADDF32 (MR0 to MR3)

MRf

CLA floating-point source register for MADDF32 (MR0 to MR3)

Opcode

LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0000 0000

Description

Multiply the contents of two floating-point registers with parallel addition of two registers.
MRa = MRb * MRc;
MRd = MRe + MRf;

Restrictions

The destination register for the MMPYF32 and the MADDF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MMPYF32 or MADDF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MADDF32 generates an overflow condition.
Pipeline

Both MMPYF32 and MADDF32 complete in a single cycle.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

761

Instruction Set
Example

www.ti.com
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16
MAR0, #_X
; MAR0 points to X array
MMOVI16
MAR1, #_Y
; MAR1 points to Y array
MNOP
; Delay for MAR0, MAR1 load
MNOP
; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32
MR0, *MAR0[2]++
; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32
MR1, *MAR1[2]++
; MR1 = Y0, MAR1 += 2

||

MMPYF32
MMOV32
MMOV32

MR2, MR0, MR1
MR0, *MAR0[2]++
MR1, *MAR1[2]++

; MR2 = A = X0 * Y0
; In parallel MR0 = X1, MAR0 += 2
; MR1 = Y1, MAR1 += 2

||

MMPYF32
MMOV32
MMOV32

MR3, MR0, MR1
MR0, *MAR0[2]++
MR1, *MAR1[2]++

; MR3 = B = X1 * Y1
; In parallel MR0 = X2, MAR0 += 2
; MR1 = Y2, MAR2 += 2

||

MMACF32
MMOV32
MMOV32

MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
MR0, *MAR0[2]++
; In parallel MR0 = X3
MR1, *MAR1[2]++
; MR1 = Y3

||

MMACF32
MMOV32
MMOV32

MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
MR0, *MAR0
; In parallel MR0 = X4
MR1, *MAR1
; MR1 = Y4

MMPYF32
MADDF32

MR2, MR0, MR1
MR3, MR3, MR2

; MR2 = E = X4 * Y4
; in parallel MR3 = (A + B + C) + D

MADDF32
MMOV32
MSTOP

MR3, MR3, MR2
@_Result, MR3

; MR3 = (A + B + C + D) + E
; Store the result
; end of task

||

See also

762

MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Multiply with Parallel Move
Operands
MRd

CLA floating-point destination register for the MMPYF32 (MR0 to MR3)
MRd cannot be the same register as MRa

MRe

CLA floating-point source register for the MMPYF32 (MR0 to MR3)

MRf

CLA floating-point source register for the MMPYF32 (MR0 to MR3)

MRa

CLA floating-point destination register for the MMOV32 (MR0 to MR3)
MRa cannot be the same register as MRd

mem32

32-bit memory location accessed using one of the available addressing modes. This
will be the source of the MMOV32.

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0000 ffee ddaa addr

Description

Multiply the contents of two floating-point registers and load another.
MRd = MRe * MRf;
MRa = [mem32];

Restrictions

The destination register for the MMPYF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags

This instruction modifies the following flags in the MSTF register:.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
The MMOV32 Instruction will set the NF and ZF flags as follows:
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline

Both MMPYF32 and MMOV32 complete in a single cycle.

Example 1

; Given M1, X1 and B1 are 32-bit
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32
MR0, @M1
;
MMOV32
MR1, @X1
;
MMPYF32
MR1, MR1, MR0
;
|| MMOV32
MR0, @B1
;
MADDF32
MR1, MR1, MR0
;
MMOV32
@Y1, MR1
;
MSTOP
;

floating point

Load MR0 with M1
Load MR1 with X1
Multiply M1*X1
and in parallel load MR0 with B1
Add M*X1 to B1 and store in MR1
Store the result
end of task

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

763

Instruction Set

www.ti.com

Example 2

; Given A, B and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
;
Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32
MR0, @A
; Load MR0 with A
MMOV32
MR1, @B
; Load MR1 with B
MMPYF32
MR1, MR1, MR0 ; Multiply A*B
|| MMOV32
MR0, @C
; and in parallel load MR0 with C
MMPYF32
MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32
@Y2, MR1
; and in parallel store A*B
MMOV32
@Y3, MR1
; Store the result
MSTOP
; end of task

See also

MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

764

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa 32-Bit Floating-Point Multiply with Parallel Move
Operands
MRd

CLA floating-point destination register for the MMPYF32 (MR0 to MR3)

MRe

CLA floating-point source register for the MMPYF32 (MR0 to MR3)

MRf

CLA floating-point source register for the MMPYF32 (MR0 to MR3)

mem32

32-bit memory location accessed using one of the available addressing modes. This
will be the destination of the MMOV32.

MRa

CLA floating-point source register for the MMOV32 (MR0 to MR3)

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0100 ffee ddaa addr

Description

Multiply the contents of two floating-point registers and move from memory to register.
MRd = MRe * MRf;
[mem32] = MRa;

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
Pipeline

MMPYF32 and MMOV32 both complete in a single cycle.

Example

; Given A, B and C are 32-bit
; Calculate Y2 = (A * B)
;
Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32
MR0, @A
MMOV32
MR1, @B
MMPYF32
MR1, MR1, MR0
||
MMOV32
MR0, @C
MMPYF32
MR1, MR1, MR0
||
MMOV32
@Y2, MR1
MMOV32
@Y3, MR1
MSTOP

See also

floating-point numbers

;
;
;
;
;
;
;
;

Load MR0 with A
Load MR1 with B
Multiply A*B
and in parallel load MR0 with C
Multiply (A*B) by C
and in parallel store A*B
Store the result
end of task

MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

765

Instruction Set

www.ti.com

MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf 32-Bit Floating-Point Multiply with Parallel
Subtract
Operands
MRa

CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd

MRb

CLA floating-point source register for MMPYF32 (MR0 to MR3)

MRc

CLA floating-point source register for MMPYF32 (MR0 to MR3)

MRd

CLA floating-point destination register for MSUBF32 (MR0 to MR3)
MRd cannot be the same register as MRa

MRe

CLA floating-point source register for MSUBF32 (MR0 to MR3)

MRf

CLA floating-point source register for MSUBF32 (MR0 to MR3)

Opcode

LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0100 0000

Description

Multiply the contents of two floating-point registers with parallel subtraction of two
registers.
MRa = MRb * MRc;
MRd = MRe - MRf;

Restrictions

The destination register for the MMPYF32 and the MSUBF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags

This instruction modifies the following flags in the MSTF register:.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MMPYF32 or MSUBF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MSUBF32 generates an overflow condition.
Pipeline

MMPYF32 and MSUBF32 both complete in a single cycle.

Example

; Given A, B and C are 32-bit
; Calculate Y2 = (A * B)
;
Y3 = (A - B)
;
_Cla1Task2:
MMOV32
MR0, @A
MMOV32
MR1, @B
MMPYF32 MR2, MR0, MR1
||
MSUBF32 MR3, MR0, MR1
MMOV32
@Y2, MR2
MMOV32
@Y3, MR3
MSTOP

See also

766

floating-point numbers

;
;
;
;
;
;
;

Load MR0 with A
Load MR1 with B
Multiply (A*B)
and in parallel Sub (A-B)
Store A*B
Store A-B
end of task

MSUBF32 MRa, MRb, MRc
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MNEGF32 MRa, MRb{, CNDF} Conditional Negation
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

CNDF

condition tested

Opcode

LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1000 0000

Description

if (CNDF == true) {MRa = - MRb; }
else {MRa = MRb; }

CNDF is one of the following conditions:
Encode

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

1111

UNCF

Unconditional with flag
modification

None

(5)
(6)

Flags

Pipeline

(5)

(6)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF, and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

This is a single-cycle instruction.

Example 1
; Show the basic operation of
;
MMOVIZ
MR0, #5.0
MMOVIZ
MR1, #4.0
MMOVIZ
MR2, #-1.5
MMPYF32
MR3, MR1, MR2
MMPYF32
MR0, MR0, MR1
MMOVIZ
MR1, #0.0
MCMPF32
MR3, MR1
MNEGF32
MR3, MR3, LT
MCMPF32
MR0, MR1
MNEGF32
MR0, MR0, GEQ

MNEGF32
;
;
;
;
;

MR0
MR1
MR2
MR3
MR0

;
;
;
;

NF
if
NF
if

=
=
=
=
=

5.0 (0x40A00000)
4.0 (0x40800000)
-1.5 (0xBFC00000)
-6.0
20.0

= 1
NF = 1, MR3 = 6.0
= 0
NF = 0, MR0 = -20.0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

767

Instruction Set

www.ti.com

Example 2

; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32
MR1, @_Den
; MR1 = Den
MEINVF32 MR2, MR1
; MR2 = Ye = Estimate(1/Den)
MMPYF32
MR3, MR2, MR1
; MR3 = Ye*Den
MSUBF32
MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32
MR2, MR2, MR3
; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32
MR3, MR2, MR1
; MR3 = Ye*Den
|| MMOV32
MR0, @_Num
; MR0 = Num
MSUBF32
MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32
MR2, MR2, MR3
; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32
MR1, @_Den
; Reload Den To Set Sign
MNEGF32
MR0, MR0, EQ
; if(Den == 0.0) Change Sign Of Num
MMPYF32
MR0, MR2, MR0
; MR0 = Y = Ye*Num
MMOV32
@_Dest, MR0
; Store result
MSTOP
; end of task

See also

MABSF32 MRa, MRb

768

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MNOP

No Operation

Operands
none

This instruction does not have any operands

Opcode

LSW: 0000 0000 0000 0000
MSW: 0111 1111 1010 0000

Description

Do nothing. This instruction is used to fill required pipeline delay slots when other
instructions are not available to fill the slots.

Flags

This instruction does not modify flags in the MSTF register.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store it in Result
;
_Cla1Task1:
MMOVI16
MAR1,#_X
; Start address
MUI16TOF32 MR0, @_len
; Length of the array
MNOP
; delay for MAR1 load
MNOP
; delay for MAR1 load
MMOV32
MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32
MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32
MR1, MR2
; MR1 = MAX(MR1, MR2)
MADDF32
MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32
MR0 #0.0
; Set/clear flags for MBCNDD
MNOP
; Too late to affect MBCNDD
MNOP
; Too late to affect MBCNDD
MNOP
; Too late to affect MBCNDD
MBCNDD
LOOP, NEQ
; Branch if not equal to zero
MMOV32
@_Result, MR1
; Always executed
MNOP
; Pad to seperate MBCNDD and MSTOP
MNOP
; Pad to seperate MBCNDD and MSTOP
MSTOP
; End of task

See also

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

769

Instruction Set

www.ti.com

MOR32 MRa, MRb, MRc Bitwise OR
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

MRc

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1000 0000

Description

Bitwise OR of MRb with MRc.
MARa(31:0) = MARb(31:0) OR MRc(31:0);

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline

This is a single-cycle instruction.

Example
MMOVIZ
MMOVXI

MR0, #0x5555 ; MR0 = 0x5555AAAA
MR0, #0xAAAA

MMOVIZ
MMOVXI

MR1, #0x5432 ; MR1 = 0x5432FEDC
MR1, #0xFEDC

MOR32 MR2, MR1, MR0

See also

770

;
;
;
;
;
;
;
;
;

0101 OR 0101 = 0101
0101 OR 0100 = 0101
0101 OR 0011 = 0111
0101 OR 0010 = 0111
1010 OR 1111 = 1111
1010 OR 1110 = 1110
1010 OR 1101 = 1111
1010 OR 1100 = 1110
MR3 = 0x5555FEFE

(5)
(5)
(7)
(7)
(F)
(E)
(F)
(E)

MAND32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MRCNDD {CNDF}

Return Conditional Delayed

Operands
CNDF

optional condition.

Opcode

LSW: 0000 0000 0000 0000
MSW: 0111 1001 1010 cndf

Description

If the specified condition is true, then the RPC field of MSTF is loaded into MPC and
fetching continues from that location. Otherwise program fetches will continue without
the return.
Please refer to the pipeline section for important information regarding this instruction.
if (CNDF == TRUE) MPC = RPC;

CNDF is one of the following conditions:
Encode

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

1111

UNCF

Unconditional with flag
modification

None

(7)
(8)

Flags

(7)

(8)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

This instruction does not modify flags in the MSTF register.
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

771

Instruction Set
Pipeline

www.ti.com

The MRCNDD instruction by itself is a single-cycle instruction. As shown in Table 5-19,
for each return 6 instruction slots are executed; three before the return instruction (d5d7) and three after the return instruction (d8-d10). The total number of cycles for a return
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled. The
effective number of cycles for a return can, therefore, range from 1 to 7 cycles. The
number of cycles for a return taken may not be the same as for a return not taken.
Referring to the following code fragment and the pipeline diagrams in Table 5-19 and
Table 5-20, the instructions before and after MRCNDD have the following properties:
;
;




MCCNDD _func, NEQ


6>
7>
8>


10>

1>
2>
3>
4>




MRCNDD NEQ


9>
10>
11>
12>

;
;
;
;
;

I1 Last instruction that can affect flags for
the MCCNDD operation
I2 Cannot be stop, branch, call or return
I3 Cannot be stop, branch, call or return
I4 Cannot be stop, branch, call or return

;
;
;
;
;
;
;
;
;
;
;
;

Call to func if not eqal to zero
Three instructions after MCCNDD are always
executed whether the call is taken or not
I5 Cannot be stop, branch, call or return
I6 Cannot be stop, branch, call or return
I7 Cannot be stop, branch, call or return
I8 The address of this instruction is saved
in the RPC field of the MSTF register.
Upon return this value is loaded into MPC
and fetching continues from this point.
I9
I10

;
;
;
;
;
;
;
;

d1 Can be any instruction
d2
d3
d4 Last instruction that can affect flags for
the MRCNDD operation
d5 Cannot be stop, branch, call or return
d6 Cannot be stop, branch, call or return
d7 Cannot be stop, branch, call or return

;
;
;
;
;
;
;
;

Return to  if not equal to zero
Three instructions after MRCNDD are always
executed whether the return is taken or not
d8 Cannot be stop, branch, call or return
d9 Cannot be stop, branch, call or return
d10 Cannot be stop, branch, call or return
d11
d12

d4
– d4 is the last instruction that can effect the CNDF flags for the MRCNDD
instruction. The CNDF flags are tested in the D2 phase of the pipeline. That is, a
decision is made whether to return or not when MRCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for d4.
d5, d6 and d7
– The three instructions proceeding MRCNDD can change MSTF flags but will have
no effect on whether the MRCNDD instruction makes the return or not. This is

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

•

because the flag modification will occur after the D2 phase of the MRCNDD
instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.
d8, d9 and d10
– The three instructions following MRCNDD are always executed irrespective of
whether the return is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP,
MBCNDD, MCCNDD or MRCNDD.
Table 5-19. Pipeline Activity For MRCNDD, Return Not Taken

Instruction

F1

F2

D1

D2

R1

R2

E

d4

d4

d3

d2

d1

I7

I6

I5

d5

d5

d4

d3

d2

d1

I7

I6

d6

d6

d5

d4

d3

d2

d1

i7

d7

d7

d6

d5

d4

d3

d2

d1

MRCNDD

MRCNDD

d7

d6

d5

d4

d3

d2

d8

d8

MRCNDD

d7

d6

d5

d4

d3

d9

d9

d8

MRCNDD

d7

d6

d5

d4

d10

d10

d9

d8

MRCNDD

d7

d6

d5

d11

d11

d10

d9

d8

-

d7

d6

d12

d12

d11

d10

d9

d8

-

d7

etc....

....

d12

d11

d10

d9

d8

-

....

....

....

d12

d11

d10

d9

d8

....

....

....

....

d12

d11

d10

d9

d12

d11

d10

d12

d11

W

d12

Table 5-20. Pipeline Activity For MRCNDD, Return Taken
Instruction

F1

F2

D1

D2

R1

R2

E

d4

d4

d3

d2

d1

I7

I6

I5

d5

d5

d4

d3

d2

d1

I7

I6

d6

d6

d5

d4

d3

d2

d1

i7

d7

d7

d6

d5

d4

d3

d2

d1

MRCNDD

MRCNDD

d7

d6

d5

d4

d3

d2

d8

d8

MRCNDD

d7

d6

d5

d4

d3

d9

d9

d8

MRCNDD

d7

d6

d5

d4

d10

d10

d9

d8

MRCNDD

d7

d6

d5

I8

I8

d10

d9

d8

-

d7

d6

I9

I9

I8

d10

d9

d8

-

d7

I10

I10

I9

I8

d10

d9

d8

-

etc....

....

I10

I9

I8

d10

d9

d8

....

....

I10

I9

I8

d10

d9

....

....

I10

I9

I8

d10

I10

I9

I8

I10

I9

W

I10

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

773

Instruction Set

www.ti.com

Example

;

See also

MBCNDD #16BitDest, CNDF
MCCNDD 16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

774

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MSETFLG FLAG, VALUE Set or Clear Selected Floating-Point Status Flags
Operands
FLAG

8 bit mask indicating which floating-point status flags to change.

VALUE

8 bit mask indicating the flag value; 0 or 1.

Opcode

LSW: FFFF FFFF VVVV VVVV
MSW: 0111 1001 1100 0000

Description

The MSETFLG instruction is used to set or clear selected floating-point status flags in
the MSTF register. The FLAG field is an 11-bit value that indicates which flags will be
changed. That is, if a FLAG bit is set to 1 it indicates that flag will be changed; all other
flags will not be modified. The bit mapping of the FLAG field is shown below:
RNDF3
2

reserve
d

reserve
d

TF

reserve
d

reserved

ZF

NF

LUF

LVF

9

8

7

6

5

4

3

2

1

0

The VALUE field indicates the value the flag should be set to; 0 or 1.
Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

Yes

Yes

Yes

Yes

Yes

Any flag can be modified by this instruction. The MEALLOW and RPC fields cannot be
modified with this instruction.
Pipeline

This is a single-cycle instruction.

Example

To make it easier and legible, the assembler accepts a FLAG=VALUE syntax for the
MSTFLG operation as shown below:
MSETFLG RNDF32=0, TF=0, NF=1; FLAG = 11000100; VALUE = 00XXX1XX;

See also

MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

775

Instruction Set

MSTOP

www.ti.com

Stop Task

Operands
none

This instruction does not have any operands

Opcode

LSW: 0000 0000 0000 0000
MSW: 0111 1111 1000 0000

Description

The MSTOP instruction must be placed to indicate the end of each task. In addition,
placing MSTOP in unused memory locations within the CLA program RAM can be useful
for debugging and preventing run away CLA code. When MSTOP enters the D2 phase
of the pipeline, the MIRUN flag for the task is cleared and the associated interrupt is
flagged in the PIE vector table.
There are three special cases that can occur when single-stepping a task such that the
MPC reaches the MSTOP instruction.
1. If you are single-stepping or halted in "task A" and "task B" comes in before the MPC
reaches the MSTOP, then "task B" will start if you continue to step through the
MSTOP instruction. Basically if "task B" is pending before the MPC reaches MSTOP
in "task A" then there is no issue in "task B" starting and no special action is required.
2. In this case you have single-stepped or halted in "task A" and the MPC has reached
the MSTOP with no tasks pending. If "task B" comes in at this point, it will be flagged
in the MIFR register but it may or may not start if you continue to single-step through
the MSTOP instruction of "task A". It depends on exactly when the new task comes
in. To reliably start "task B" perform a soft reset and reconfigure the MIER bits. Once
this is done, you can start single-stepping "task B".
3. Case 2 can be handled slightly differently if there is control over when "task B" comes
in (for example using the IACK instruction to start the task). In this case you have
single-stepped or halted in "task A" and the MPC has reached the MSTOP with no
tasks pending. Before forcing "task B", run free to force the CLA out of the debug
state. Once this is done you can force "task B" and continue debugging.

Restrictions

The MSTOP instruction cannot be placed 3 instructions before or after a MBCNDD,
MCCNDD or MRCNDD instruction.

Flags

This instruction does not modify flags in the MSTF register.

Pipeline

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

This is a single-cycle instruction. Table 5-21 shows the pipeline behavior of the MSTOP
instruction. The MSTOP instruction cannot be placed with 3 instructions of a MBCNDD,
MCCNDD or MRCNDD instruction.

776 Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

Table 5-21. Pipeline Activity For MSTOP
Instruction

F1

I1

I1

F2

D1

D2

R1

R2

E

I2

I2

I1

I3

I3

I2

I1

MSTOP

MSTOP

I3

I2

I1

I4

I4

MSTOP

I3

I2

I1

I5

I5

I4

MSTOP

I3

I2

I1

I6

I6

I5

I4

MSTOP

I3

I2

I1

New Task Arbitrated and Piroitized

-

-

-

-

-

I3

I2

New Task Arbitrated and Piroitized

-

-

-

-

-

-

I3

I1

I1

-

-

-

-

-

-

I2

I2

I1

-

-

-

-

-

I3

I3

I2

I1

-

-

-

-

I4

I4

I3

I2

I1

-

-

-

I5

I5

I4

I3

I2

I1

-

-

I6

I6

I5

I4

I3

I2

I1

-

I7

I7

I6

I5

I4

I3

I2

I1

W

etc ....

Example

See also

; Given A =
;
B =
;
C =
;
; Calculate
_Cla1Task3:
MMOV32
MMOV32
MMOV32
MSUB32
MSUB32
MMOV32
MSTOP

(int32)1
(int32)2
(int32)-7
Y2 = A - B - C
MR0, @_A
; MR0 = 1 (0x00000001)
MR1, @_B
; MR1 = 2 (0x00000002)
MR2, @_C
; MR2 = -7 (0xFFFFFFF9)
MR3, MR0, MR1 ; A + B
MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
@_y2, MR3
; Store y2
; End of task

MDEBUGSTOP

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

777

Instruction Set

www.ti.com

MSUB32 MRa, MRb, MRc 32-Bit Integer Subtraction
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point destination register (MR0 to MR3)

MRc

CLA floating-point destination register (MR0 to MR3)

Opcode

LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1110 0000

Description

32-bit integer addition of MRb and MRc.
MARa(31:0) = MARb(31:0) - MRc(31:0);

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified as follows:
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline

This is a single-cycle instruction.

Example

; Given A = (int32)1
;
B = (int32)2
;
C = (int32)-7
;
;
Calculate Y2 = A - B - C
;
_Cla1Task3:
MMOV32
MR0, @_A
MMOV32
MR1, @_B
MMOV32
MR2, @_C
MSUB32
MR3, MR0, MR1
MSUB32
MR3, MR3, MR2
MMOV32
@_y2, MR3
MSTOP

See also

778

;
;
;
;
;
;
;

MR0 = 1 (0x00000001)
MR1 = 2 (0x00000002)
MR2 = -7 (0xFFFFFFF9)
A + B
A + B + C = 6 (0x0000006)
Store y2
End of task

MADD32 MRa, MRb, MRc
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MSUBF32 MRa, MRb, MRc 32-Bit Floating-Point Subtraction
Operands
MRa

CLA floating-point destination register (MR0 to R1)

MRb

CLA floating-point source register (MR0 to R1)

MRc

CLA floating-point source register (MR0 to R1)

Opcode

LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0100 0000

Description

Subtract the contents of two floating-point registers
MRa = MRb - MRc;

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example
; Given A, B and C are
; Calculate Y2 = A + B
;
_Cla1Task5:
MMOV32
MR0, @_A
MMOV32
MR1, @_B
MADDF32
MR0, MR1,
|| MMOV32
MR1, @_C
MSUBF32
MR0, MR0,
MMOV32
@Y, MR0
MSTOP

See also

32-bit floating-point numbers
- C

;
;
MR0 ;
;
MR1 ;
;
;

Load MR0 with A
Load MR1 with B
Add A + B
and in parallel load C
Subtract C from (A + B)
(A+B) - C
end of task

MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

779

Instruction Set

www.ti.com

MSUBF32 MRa, #16FHi, MRb 32-Bit Floating-Point Subtraction
Operands
MRa

CLA floating-point destination register (MR0 to R1)

#16FHi

A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.

MRb

CLA floating-point source register (MR0 to R1)

Opcode

LSW: IIII IIII IIII IIII
MSW: 0111 1000 0000 baaa

Description

Subtract MRb from the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler will accept either a hex or float as the immediate value.
That is, the value -1.5 can be represented as #-1.5 or #0xBFC0.
MRa = #16FHi:0 - MRb;

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline

This is a single-cycle instruction.

Example

; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32
MR0, @_x
MEISQRTF32 MR1, MR0
MMOV32
MR1, @_x, EQ
MMPYF32
MR3, MR0, #0.5
MMPYF32
MR2, MR1, MR3
MMPYF32
MR2, MR1, MR2
MSUBF32
MR2, #1.5, MR2
MMPYF32
MR1, MR1, MR2
MMPYF32
MR2, MR1, MR3
MMPYF32
MR2, MR1, MR2
MSUBF32
MR2, #1.5, MR2
MMPYF32
MR1, MR1, MR2
MMPYF32
MR0, MR1, MR0
MMOV32
@_y, MR0
MSTOP

See also

780

;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

MR0 = X
MR1 = Ye = Estimate(1/sqrt(X))
if(X == 0.0) Ye = 0.0
MR3 = X*0.5
MR2 = Ye*X*0.5
MR2 = Ye*Ye*X*0.5
MR2 = 1.5 - Ye*Ye*X*0.5
MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MR2 = Ye*X*0.5
MR2 = Ye*Ye*X*0.5
MR2 = 1.5 - Ye*Ye*X*0.5
MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MR0 = Y = Ye*X
Store Y = sqrt(X)
end of task

MSUBF32 MRa, MRb, MRc
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Subtraction with Parallel
Move
Operands
MRd

CLA floating-point destination register (MR0 to MR3) for the MSUBF32 operation
MRd cannot be the same register as MRa

MRe

CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation

MRf

CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation

MRa

CLA floating-point destination register (MR0 to MR3) for the MMOV32 operation
MRa cannot be the same register as MRd

mem32

32-bit memory location accessed using one of the available addressing modes. Source
for the MMOV32 operation.

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0010 ffee ddaa addr

Description

Subtract the contents of two floating-point registers and move from memory to a floatingpoint register.
MRd = MRe - MRf;
MRa = [mem32];

Restrictions

The destination register for the MSUBF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
The MMOV32 Instruction will set the NF and ZF flags as follows:
Pipeline

Both MSUBF32 and MMOV32 complete in a single cycle.

Example

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

See also

MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

781

Instruction Set

www.ti.com

MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa 32-Bit Floating-Point Subtraction with Parallel
Move
Operands
MRd

CLA floating-point destination register (MR0 to MR3) for the MSUBF32 operation

MRe

CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation

MRf

CLA floating-point source register (MR0 to MR3) for the MSUBF32 operation

mem32

32-bit destination memory location for the MMOV32 operation

MRa

CLA floating-point source register (MR0 to MR3) for the MMOV32 operation

Opcode

LSW: mmmm mmmm mmmm mmmm
MSW: 0110 ffee ddaa addr

Description

Subtract the contents of two floating-point registers and move from a floating-point
register to memory.
MRd = MRe - MRf;
[mem32] = MRa;

This instruction modifies the following flags in the MSTF register:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

Yes

Yes

The MSTF register flags are modified as follows:
• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline

Both MSUBF32 and MMOV32 complete in a single cycle.

Example
See also

782

MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MSWAPF MRa, MRb {, CNDF} Conditional Swap
Operands
MRa

CLA floating-point register (MR0 to MR3)

MRb

CLA floating-point register (MR0 to MR3)

CNDF

Optional condition tested based on the MSTF flags

Opcode

LSW: 0000 0000 CNDF bbaa
MSW: 0111 1011 0000 0000

Description

Conditional swap of MRa and MRb.
if (CNDF == true) swap MRa and MRb;

CNDF is one of the following conditions:
Encode

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

1111

UNCF

Unconditional with flag
modification

None

(1)
(2)

Flags

(1)

(2)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

No flags affected
Pipeline

This is a single-cycle instruction.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

783

Instruction Set
Example

www.ti.com
; X is an array of 32-bit floating-point values
; and has len elements. Find the maximum value in
; the array and store it in Result
;
; Note: MCMPF32 and MSWAPF can be replaced by MMAXF32
;
_Cla1Task1:
MMOVI16
MAR1,#_X
; Start address
MUI16TOF32 MR0, @_len
; Length of the array
MNOP
; delay for MAR1 load
MNOP
; delay for MAR1 load
MMOV32
MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32
MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32
MR2, MR1
; Compare MR2 with MR1
MSWAPF
MR1, MR2, GT
; MR1 = MAX(MR1, MR2)
MADDF32
MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32
MR0 #0.0
; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD
LOOP, NEQ
; Branch if not equal to zero
MMOV32
@_Result, MR1
; Always executed
MNOP
; Always executed
MNOP
; Always executed
MSTOP
; End of task

See also

784

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MTESTTF CNDF

Test MSTF Register Flag Condition

Operands
CNDF

condition to test based on MSTF flags

Opcode

LSW: 0000 0000 0000 cndf
MSW: 0111 1111 0100 0000

Description

Test the CLA floating-point condition and if true, set the MSTF[TF] flag. If the condition is
false, clear the MSTF[TF] flag. This is useful for temporarily storing a condition for later
use.
if (CNDF == true) TF = 1;
else TF = 0;

CNDF is one of the following conditions:
Encode

CNDF

Description

MSTF Flags Tested

0000

NEQ

Not equal to zero

ZF == 0

0001

EQ

Equal to zero

ZF == 1

0010

GT

Greater than zero

ZF == 0 AND NF == 0

0011

GEQ

Greater than or equal to zero

NF == 0

0100

LT

Less than zero

NF == 1

0101

LEQ

Less than or equal to zero

ZF == 1 OR NF == 1

1010

TF

Test flag set

TF == 1

1011

NTF

Test flag not set

TF == 0

1100

LU

Latched underflow

LUF == 1

1101

LV

Latched overflow

LVF == 1

1110

UNC

Unconditional

None

Unconditional with flag
modification

None

1111
(3)
(4)

Flags

(3)

UNCF

(4)

Values not shown are reserved.
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to
be modified when a conditional operation is executed. All other conditions will not modify these flags.

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

Yes

No

No

No

No

TF = 0;
if (CNDF == true) TF = 1;

Note: If (CNDF == UNC or UNCF), the TF flag will be set to 1.
Pipeline

This is a single-cycle instruction.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

785

Instruction Set
Example

www.ti.com
; if (State == 0.1)
;
RampState = RampState || RAMPMASK
; else if (State == 0.01)
;
CoastState = CoastState || COASTMASK
; else
;
SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32
MR0, @_State
MCMPF32
MR0, #0.1
; Affects flags for 1st MBCNDD (A)
MCMPF32
MR0, #0.01
; Check used by 2nd MBCNDD (B)
MTESTTF
EQ
; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD
_Skip1, NEQ
; (A) If State != 0.1, go to Skip1
MMOV32
MR1, @_RampState ; Always executed
MMOVXI
MR2, #RAMPMASK
; Always executed
MOR32
MR1, MR2
; Always executed
MMOV32
@_RampState, MR1 ; Execute if (A) branch not taken
MSTOP
; end of task if (A) branch not taken
_Skip1:
MMOV32
MMOVXI
MOR32
MBCNDD
MMOV32
MMOVXI
MOR32
MMOV32
MSTOP

MR3, @_SteadyState
MR2, #STEADYMASK
MR3, MR2
_Skip2, NTF
;
MR1, @_CoastState ;
MR2, #COASTMASK
;
MR1, MR2
;
@_CoastState, MR1 ;
;

_Skip2:
MMOV32 @_SteadyState, MR3
MSTOP

(B) if State != .01, go to Skip2
Always executed
Always executed
Always executed
Execute if (B) branch not taken
end of task if (B) branch not taken

; Executed if (B) branch taken

See also

786

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MUI16TOF32 MRa, mem16 Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value
Operands

Opcode

MRa

CLA floating-point destination register (MR0 to MR3)

mem16

16-bit source memory location

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 01aa addr

Description

When converting F32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates
to zero while the MF32TOI16R/UI16R operation will round to nearest (even) value.
MRa = UI16TOF32[mem16];

Flags

Pipeline

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

This is a single-cycle instruction.

Example
See also

MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

787

Instruction Set

www.ti.com

MUI16TOF32 MRa, MRb Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value
Operands

Opcode

MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1110 0000

Description

Convert an unsigned 16-bit integer to a 32-bit floating-point value. When converting
float32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to zero while
the MF32TOI16R/UI16R operation will round to nearest (even) value.
MRa = UI16TOF32[MRb];

This instruction does not affect any flags:

Flags

Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVXI MR1, #0x800F ; MR1(15:0) = 32783 (0x800F)
MUI16TOF32 MR0, MR1 ; MR0 = UI16TOF32 (MR1(15:0))
; = 32783.0 (0x47000F00)

See also

MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16

788

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MUI32TOF32 MRa, mem32 Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value
Operands

Opcode

MRa

CLA floating-point destination register (MR0 to MR3)

mem32

32-bit memory location accessed using one of the available addressing modes

LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 10aa addr

Description

MRa = UI32TOF32[mem32];

Flags

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

; Given x2, m2 and b2 are Uint32 numbers:
;
; x2 = Uint32(2) = 0x00000002
; m2 = Uint32(1) = 0x00000001
; b2 = Uint32(3) = 0x00000003
;
; Calculate y2 = x2 * m2 + b2
;
_Cla1Task1:
MUI32TOF32 MR0, @_m2
; MR0 = 1.0 (0x3F800000)
MUI32TOF32 MR1, @_x2
; MR1 = 2.0 (0x40000000)
MUI32TOF32 MR2, @_b2
; MR2 = 3.0 (0x40400000)
MMPYF32
MR3, MR0, MR1 ; M*X
MADDF32
MR3, MR2, MR3 ; Y=MX+B = 5.0 (0x40A00000)
MF32TOUI32 MR3, MR3
; Y = Uint32(5.0) = 0x00000005
MMOV32
@_y2, MR3
; store result
MSTOP
; end of task

See also

MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

789

Instruction Set

www.ti.com

MUI32TOF32 MRa, MRb Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value
Operands

Opcode

MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1100 0000

Description

MRa = UI32TOF32 [MRb];

Flags

This instruction does not affect any flags:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

No

No

No

No

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ
MMOVXI

See also

MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

790

MR3, #0x8000 ;
MR3, #0x1111 ;
;
MUI32TOF32 MR3, MR3
;

Control Law Accelerator (CLA)

MR3(31:16) = 0x8000
MR3(15:0) = 0x1111
MR3 = 2147488017
MR3 = MUI32TOF32 (MR3) = 2147488017.0 (0x4F000011)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Instruction Set

www.ti.com

MXOR32 MRa, MRb, MRc Bitwise Exclusive Or
Operands
MRa

CLA floating-point destination register (MR0 to MR3)

MRb

CLA floating-point source register (MR0 to MR3)

MRc

CLA floating-point source register (MR0 to MR3)

Opcode

LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1010 0000

Description

Bitwise XOR of MRb with MRc.
MARa(31:0) = MARb(31:0) XOR MRc(31:0);

Flags

This instruction modifies the following flags in the MSTF register:
Flag

TF

ZF

NF

LUF

LVF

Modified

No

Yes

Yes

No

No

The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline

This is a single-cycle instruction.

Example

MMOVIZ MR0, #0x5555
; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432
MMOVXI MR1, #0xFEDC
;
;
;
;
;
;
;
;

0101
0101
0101
0101
1010
1010
1010
1010

XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR

0101
0100
0011
0010
1111
1110
1101
1100

=
=
=
=
=
=
=
=

0000
0001
0110
0111
0101
0100
0111
0110

MXOR32 MR2, MR1, MR0

See also

; MR1 = 0x5432FEDC

(0)
(1)
(6)
(7)
(5)
(4)
(7)
(6)

; MR3 = 0x01675476

MAND32 MRa, MRb, MRc
MOR32 MRa, MRb, MRc

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

791

Registers

5.7

www.ti.com

Registers

5.7.1 CLA Base Addresses
Table 5-22. CLA Base Address Table
Device Register

(1)

792

Register Name

Start Address

End Address

Cla1Regs

CLA_REGS

0x0000_1400

0x0000_147F

Cla1SoftIntRegs (1)

CLA_SOFTINT_REGS

0x0000_0CE0

0x0000_0CFF

This register is only accessible from the CLA.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2 CLA_REGS Registers
Table 5-23 lists the memory-mapped registers for the CLA_REGS. All register offset addresses not listed
in Table 5-23 should be considered as reserved locations and the register contents should not be
modified.
Table 5-23. CLA_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

MVECT1

Task Interrupt Vector

EALLOW

Go

1h

MVECT2

Task Interrupt Vector

EALLOW

Go

2h

MVECT3

Task Interrupt Vector

EALLOW

Go

3h

MVECT4

Task Interrupt Vector

EALLOW

Go

4h

MVECT5

Task Interrupt Vector

EALLOW

Go

5h

MVECT6

Task Interrupt Vector

EALLOW

Go

6h

MVECT7

Task Interrupt Vector

EALLOW

Go

7h

MVECT8

Task Interrupt Vector

EALLOW

Go

10h

MCTL

Control Register

EALLOW

Go

20h

MIFR

Interrupt Flag Register

EALLOW

Go

21h

MIOVF

Interrupt Overflow Flag Register

EALLOW

Go

22h

MIFRC

Interrupt Force Register

EALLOW

Go

23h

MICLR

Interrupt Flag Clear Register

EALLOW

Go

24h

MICLROVF

Interrupt Overflow Flag Clear Register

EALLOW

Go

25h

MIER

Interrupt Enable Register

EALLOW

Go

26h

MIRUN

Interrupt Run Status Register

EALLOW

Go

28h

_MPC

CLA Program Counter

Go

2Ah

_MAR0

CLA Auxiliary Register 0

Go

2Bh

_MAR1

CLA Auxiliary Register 1

Go

2Eh

_MSTF

CLA Floating-Point Status Register

Go

30h

_MR0

CLA Floating-Point Result Register 0

Go

34h

_MR1

CLA Floating-Point Result Register 1

Go

38h

_MR2

CLA Floating-Point Result Register 2

Go

3Ch

_MR3

CLA Floating-Point Result Register 3

Go

Complex bit access types are encoded to fit into small table cells. Table 5-24 shows the codes that are
used for access types in this section.
Table 5-24. CLA_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

Write

Read Type
R
Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

793

Registers

www.ti.com

Table 5-24. CLA_REGS Access Type
Codes (continued)
Access Type

794

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.1

MVECT1 Register (Offset = 0h) [reset = 0h]

MVECT1 is shown in Figure 5-2 and described in Table 5-25.
Return to Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 5-2. MVECT1 Register
15

14

13

12

11

10

9

8
7
MVECT
R/W-0h

6

5

4

3

2

1

0

Table 5-25. MVECT1 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

MVECT

R/W

0h

MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K MCLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses
MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

795

Registers

5.7.2.2

www.ti.com

MVECT2 Register (Offset = 1h) [reset = 0h]

MVECT2 is shown in Figure 5-3 and described in Table 5-26.
Return to Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 5-3. MVECT2 Register
15

14

13

12

11

10

9

8
7
MVECT
R/W-0h

6

5

4

3

2

1

0

Table 5-26. MVECT2 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

MVECT

R/W

0h

MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K MCLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses
MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

796

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.3

MVECT3 Register (Offset = 2h) [reset = 0h]

MVECT3 is shown in Figure 5-4 and described in Table 5-27.
Return to Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 5-4. MVECT3 Register
15

14

13

12

11

10

9

8
7
MVECT
R/W-0h

6

5

4

3

2

1

0

Table 5-27. MVECT3 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

MVECT

R/W

0h

MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K MCLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses
MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

797

Registers

5.7.2.4

www.ti.com

MVECT4 Register (Offset = 3h) [reset = 0h]

MVECT4 is shown in Figure 5-5 and described in Table 5-28.
Return to Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 5-5. MVECT4 Register
15

14

13

12

11

10

9

8
7
MVECT
R/W-0h

6

5

4

3

2

1

0

Table 5-28. MVECT4 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

MVECT

R/W

0h

MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K MCLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses
MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

798

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.5

MVECT5 Register (Offset = 4h) [reset = 0h]

MVECT5 is shown in Figure 5-6 and described in Table 5-29.
Return to Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 5-6. MVECT5 Register
15

14

13

12

11

10

9

8
7
MVECT
R/W-0h

6

5

4

3

2

1

0

Table 5-29. MVECT5 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

MVECT

R/W

0h

MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K MCLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses
MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

799

Registers

5.7.2.6

www.ti.com

MVECT6 Register (Offset = 5h) [reset = 0h]

MVECT6 is shown in Figure 5-7 and described in Table 5-30.
Return to Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 5-7. MVECT6 Register
15

14

13

12

11

10

9

8
7
MVECT
R/W-0h

6

5

4

3

2

1

0

Table 5-30. MVECT6 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

MVECT

R/W

0h

MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K MCLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses
MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

800

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.7

MVECT7 Register (Offset = 6h) [reset = 0h]

MVECT7 is shown in Figure 5-8 and described in Table 5-31.
Return to Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 5-8. MVECT7 Register
15

14

13

12

11

10

9

8
7
MVECT
R/W-0h

6

5

4

3

2

1

0

Table 5-31. MVECT7 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

MVECT

R/W

0h

MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K MCLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses
MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

801

Registers

5.7.2.8

www.ti.com

MVECT8 Register (Offset = 7h) [reset = 0h]

MVECT8 is shown in Figure 5-9 and described in Table 5-32.
Return to Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 5-9. MVECT8 Register
15

14

13

12

11

10

9

8
7
MVECT
R/W-0h

6

5

4

3

2

1

0

Table 5-32. MVECT8 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

MVECT

R/W

0h

MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K MCLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses
MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

802

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.9

MCTL Register (Offset = 10h) [reset = 0h]

MCTL is shown in Figure 5-10 and described in Table 5-33.
Return to Summary Table.
Control Register
Figure 5-10. MCTL Register
15

14

13

12

11

10

9

8

3

2
IACKE
R/W-0h

1
SOFTRESET
R/W-0h

0
HARDRESET
R/W-0h

RESERVED
R-0h
7

6

5
RESERVED
R-0h

4

Table 5-33. MCTL Register Field Descriptions
Bit
15-3
2

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

IACKE

R/W

0h

IACK enable
Reset type: SYSRSn
0h (R/W) = The CLA ignores the IACK instruction. (default)
1h (R/W) = Enable the main CPU to use the IACK #16bit instruction
to set MIFR bits in the same manner as writing to the MIFRC
register. Each bit in the operand, #16bit, corresponds to a bit in the
MIFRC register. Using IACK has the advantage of not having to first
set the EALLOW bit. This allows the main CPU to efficiently trigger a
CLA task through software.
Examples IACK #0x0001 Write a 1 to MIFRC bit 0 to force task 1
IACK #0x0003 Write a 1 to MIFRC bit 0 and 1 to force task 1 and
task 2

1

SOFTRESET

R/W

0h

Soft Reset
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a soft reset of the CLA. This will
stop the current task, clear the MIRUN flag and clear all bits in the
MIER register. After a soft reset you must wait at least 1
SYSCLKOUT cycle before reconfiguring the MIER bits. If these two
operations are done back-to-back then the MIER bits will not get set.

0

HARDRESET

R/W

0h

Hard Reset
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a hard reset of the CLA. This will
set all CLA registers to their default state.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

803

Registers

www.ti.com

5.7.2.10 MIFR Register (Offset = 20h) [reset = 0h]
MIFR is shown in Figure 5-11 and described in Table 5-34.
Return to Summary Table.
Each bit in the interrupt flag register corresponds to a CLA task. The corresponding bit is automatically set
when the task request is received from the peripheral interrupt. The bit can also be set by the main CPU
writing to the MIFRC register or using the IACK instruction to start the task. To use the IACK instruction to
begin a task first enable this feature in the MCTL register. If the bit is already set when a new peripheral
interrupt is received, then the corresponding overflow bit will be set in the MIOVF register.
The corresponding MIFR bit is automatically cleared when the task begins execution. This will occur if the
interrupt is enabled in the MIER register and no other higher priority task is pending. The bits can also be
cleared manually by writing to the MICLR register. Writes to the MIFR register are ignored.
Figure 5-11. MIFR Register
15

14

13

12

11

10

9

8

3
INT4
R-0h

2
INT3
R-0h

1
INT2
R-0h

0
INT1
R-0h

RESERVED
R-0h
7
INT8
R-0h

6
INT7
R-0h

5
INT6
R-0h

4
INT5
R-0h

Table 5-34. MIFR Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

INT8

R

0h

Task 8 Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 8 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 8 interrupt has been received and is pending execution

6

INT7

R

0h

Task 7 Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 7 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 7 interrupt has been received and is pending execution

5

INT6

R

0h

Task 6 Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 6 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 6 interrupt has been received and is pending execution

4

INT5

R

0h

Task 5 Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 5 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 5 interrupt has been received and is pending execution

804

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 5-34. MIFR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

INT4

R

0h

Task 4 Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 4 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 4 interrupt has been received and is pending execution

2

INT3

R

0h

Task 3 Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 3 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 3 interrupt has been received and is pending execution

1

INT2

R

0h

Task 2 Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 2 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 2 interrupt has been received and is pending execution

0

INT1

R

0h

Task 1 Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 1 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 1 interrupt has been received and is pending execution

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

805

Registers

www.ti.com

5.7.2.11 MIOVF Register (Offset = 21h) [reset = 0h]
MIOVF is shown in Figure 5-12 and described in Table 5-35.
Return to Summary Table.
Each bit in the overflow flag register corresponds to a CLA task. The bit is set when an interrupt overflow
event has occurred for the specific task. An overflow event occurs when the MIFR register bit is already
set when a new interrupt is received from a peripheral source. The MIOVF bits are only affected by
peripheral interrupt events. They do not respond to a task request by the main CPU IACK instruction or by
directly setting MIFR bits. The overflow flag will remain latched and can only be cleared by writing to the
overflow flag clear (MICLROVF) register. Writes to the MIOVF register are ignored.
Figure 5-12. MIOVF Register
15

14

13

12

11

10

9

8

3
INT4
R-0h

2
INT3
R-0h

1
INT2
R-0h

0
INT1
R-0h

RESERVED
R-0h
7
INT8
R-0h

6
INT7
R-0h

5
INT6
R-0h

4
INT5
R-0h

Table 5-35. MIOVF Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

INT8

R

0h

Task 8 Interrupt Overflow Flag
Reset type: SYSRSn
0h (R/W) = A task 8 interrupt overflow has not occurred (default)
1h (R/W) = A task 8 interrupt overflow has occurred

6

INT7

R

0h

Task 7 Interrupt Overflow Flag
Reset type: SYSRSn
0h (R/W) = A task 7 interrupt overflow has not occurred (default)
1h (R/W) = A task 7 interrupt overflow has occurred

5

INT6

R

0h

Task 6 Interrupt Overflow Flag
Reset type: SYSRSn
0h (R/W) = A task 6 interrupt overflow has not occurred (default)
1h (R/W) = A task 6 interrupt overflow has occurred

4

INT5

R

0h

Task 5 Interrupt Overflow Flag
Reset type: SYSRSn
0h (R/W) = A task 5 interrupt overflow has not occurred (default)
1h (R/W) = A task 5 interrupt overflow has occurred

3

INT4

R

0h

Task 4 Interrupt Overflow Flag
Reset type: SYSRSn
0h (R/W) = A task 4 interrupt overflow has not occurred (default)
1h (R/W) = A task 4 interrupt overflow has occurred

2

INT3

R

0h

Task 3 Interrupt Overflow Flag
Reset type: SYSRSn
0h (R/W) = A task 3 interrupt overflow has not occurred (default)
1h (R/W) = A task 3 interrupt overflow has occurred

1

INT2

R

0h

Task 2 Interrupt Overflow Flag
Reset type: SYSRSn
0h (R/W) = A task 2 interrupt overflow has not occurred (default)
1h (R/W) = A task 2 interrupt overflow has occurred

15-8

806

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 5-35. MIOVF Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

INT1

R

0h

Task 1 Interrupt Overflow Flag
Reset type: SYSRSn
0h (R/W) = A task 1 interrupt overflow has not occurred (default)
1h (R/W) = A task 1 interrupt overflow has occurred

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

807

Registers

www.ti.com

5.7.2.12 MIFRC Register (Offset = 22h) [reset = 0h]
MIFRC is shown in Figure 5-13 and described in Table 5-36.
Return to Summary Table.
The interrupt force register can be used by the main CPU to start tasks through software. Writing a 1 to a
MIFRC bit will set the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0. The IACK #16bit operation can also be used to start tasks and has the same effect as the
MIFRC register. To enable IACK to set MIFR bits you must first set the MCTL[IACKE] bit. Using IACK has
the advantage of not having to first set the EALLOW bit. This allows the main CPU to efficiently trigger
CLA tasks through software.
Figure 5-13. MIFRC Register
15

14

13

12

11

10

9

8

3
INT4
R/W-0h

2
INT3
R/W-0h

1
INT2
R/W-0h

0
INT1
R/W-0h

RESERVED
R-0h
7
INT8
R/W-0h

6
INT7
R/W-0h

5
INT6
R/W-0h

4
INT5
R/W-0h

Table 5-36. MIFRC Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

INT8

R/W

0h

Task 8 Interrupt Force
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 8 interrupt

6

INT7

R/W

0h

Task 7 Interrupt Force
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 7 interrupt

5

INT6

R/W

0h

Task 6 Interrupt Force
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 6 interrupt

4

INT5

R/W

0h

Task 5 Interrupt Force
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 5 interrupt

3

INT4

R/W

0h

Task 4 Interrupt Force
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 4 interrupt

2

INT3

R/W

0h

Task 3 Interrupt Force
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 3 interrupt

15-8

808

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 5-36. MIFRC Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

INT2

R/W

0h

Task 2 Interrupt Force
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 2 interrupt

0

INT1

R/W

0h

Task 1 Interrupt Force
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 1 interrupt

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

809

Registers

www.ti.com

5.7.2.13 MICLR Register (Offset = 23h) [reset = 0h]
MICLR is shown in Figure 5-14 and described in Table 5-37.
Return to Summary Table.
Normally bits in the MIFR register are automatically cleared when a task begins. The interrupt flag clear
register can be used to instead manually clear bits in the interrupt flag (MIFR) register. Writing a 1 to a
MICLR bit will clear the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0.
Figure 5-14. MICLR Register
15

14

13

12

11

10

9

8

3
INT4
R/W-0h

2
INT3
R/W-0h

1
INT2
R/W-0h

0
INT1
R/W-0h

RESERVED
R-0h
7
INT8
R/W-0h

6
INT7
R/W-0h

5
INT6
R/W-0h

4
INT5
R/W-0h

Table 5-37. MICLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

INT8

R/W

0h

Task 8 Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt flag

6

INT7

R/W

0h

Task 7 Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt flag

5

INT6

R/W

0h

Task 6 Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt flag

4

INT5

R/W

0h

Task 5 Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt flag

3

INT4

R/W

0h

Task 4 Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt flag

2

INT3

R/W

0h

Task 3 Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt flag

1

INT2

R/W

0h

Task 2 Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt flag

15-8

810

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 5-37. MICLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

INT1

R/W

0h

Task 1 Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt flag

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

811

Registers

www.ti.com

5.7.2.14 MICLROVF Register (Offset = 24h) [reset = 0h]
MICLROVF is shown in Figure 5-15 and described in Table 5-38.
Return to Summary Table.
Overflow flag bits in the MIOVF register are latched until manually cleared using the MICLROVF register.
Writing a 1 to a MICLROVF bit will clear the corresponding bit in the MIOVF register. Writes of 0 are
ignored and reads always return 0.
Figure 5-15. MICLROVF Register
15

14

13

12

11

10

9

8

3
INT4
R/W-0h

2
INT3
R/W-0h

1
INT2
R/W-0h

0
INT1
R/W-0h

RESERVED
R-0h
7
INT8
R/W-0h

6
INT7
R/W-0h

5
INT6
R/W-0h

4
INT5
R/W-0h

Table 5-38. MICLROVF Register Field Descriptions
Bit
15-8

812

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

INT8

R/W

0h

Task 8 Interrupt Overflow Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt overflow flag

6

INT7

R/W

0h

Task 7 Interrupt Overflow Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt overflow flag

5

INT6

R/W

0h

Task 6 Interrupt Overflow Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt overflow flag

4

INT5

R/W

0h

Task 5 Interrupt Overflow Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt overflow flag

3

INT4

R/W

0h

Task 4 Interrupt Overflow Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt overflow flag

2

INT3

R/W

0h

Task 3 Interrupt Overflow Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt overflow flag

1

INT2

R/W

0h

Task 2 Interrupt Overflow Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt overflow flag

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 5-38. MICLROVF Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

INT1

R/W

0h

Task 1 Interrupt Overflow Flag Clear
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt overflow flag

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

813

Registers

www.ti.com

5.7.2.15 MIER Register (Offset = 25h) [reset = 0h]
MIER is shown in Figure 5-16 and described in Table 5-39.
Return to Summary Table.
Setting the bits in the interrupt enable register (MIER) allow an incoming interrupt or main CPU software to
start the corresponding CLA task. Writing a 0 will block the task, but the interrupt request will still be
latched in the flag register (MIFLG). Setting the MIER register bit to 0 while the corresponding task is
executing will have no effect on the task. The task will continue to run until it hits the MSTOP instruction.
When a soft reset is issued, the MIER bits are cleared. There should always be at least a 1 SYSCLKOUT
delay between issuing the soft reset and reconfiguring the MIER bits.
Figure 5-16. MIER Register
15

14

13

12

11

10

9

8

3
INT4
R-0h

2
INT3
R-0h

1
INT2
R-0h

0
INT1
R-0h

RESERVED
R-0h
7
INT8
R-0h

6
INT7
R-0h

5
INT6
R-0h

4
INT5
R-0h

Table 5-39. MIER Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

INT8

R

0h

Task 8 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 8 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 8 interrupt is enabled

6

INT7

R

0h

Task 7 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 7 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 7 interrupt is enabled

5

INT6

R

0h

Task 6 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 6 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 6 interrupt is enabled

4

INT5

R

0h

Task 5 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 5 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 5 interrupt is enabled

3

INT4

R

0h

Task 4 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 4 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 4 interrupt is enabled

814

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 5-39. MIER Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2

INT3

R

0h

Task 3 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 3 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 3 interrupt is enabled

1

INT2

R

0h

Task 2 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 2 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 2 interrupt is enabled

0

INT1

R

0h

Task 1 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 1 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 1 interrupt is enabled

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

815

Registers

www.ti.com

5.7.2.16 MIRUN Register (Offset = 26h) [reset = 0h]
MIRUN is shown in Figure 5-17 and described in Table 5-40.
Return to Summary Table.
The interrupt run status register (MIRUN) indicates which task is currently executing. Only one MIRUN bit
will ever be set to a 1 at any given time. The bit is automatically cleared when the task competes and the
respective interrupt is fed to the peripheral interrupt expansion (PIE) block of the device. This lets the main
CPU know when a task has completed. The main CPU can stop a currently running task by writing to the
MCTL[SOFTRESET] bit. This will clear the MIRUN flag and stop the task. In this case no interrupt will be
generated to the PIE.
Figure 5-17. MIRUN Register
15

14

13

12

11

10

9

8

3
INT4
R-0h

2
INT3
R-0h

1
INT2
R-0h

0
INT1
R-0h

RESERVED
R-0h
7
INT8
R-0h

6
INT7
R-0h

5
INT6
R-0h

4
INT5
R-0h

Table 5-40. MIRUN Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

INT8

R

0h

Task 8 Run Status
Reset type: SYSRSn
0h (R/W) = Task 8 is not executing (default)
1h (R/W) = Task 8 is executing

6

INT7

R

0h

Task 7 Run Status
Reset type: SYSRSn
0h (R/W) = Task 7 is not executing (default)
1h (R/W) = Task 7 is executing

5

INT6

R

0h

Task 6 Run Status
Reset type: SYSRSn
0h (R/W) = Task 6 is not executing (default)
1h (R/W) = Task 6 is executing

4

INT5

R

0h

Task 5 Run Status
Reset type: SYSRSn
0h (R/W) = Task 5 is not executing (default)
1h (R/W) = Task 5 is executing

3

INT4

R

0h

Task 4 Run Status
Reset type: SYSRSn
0h (R/W) = Task 4 is not executing (default)
1h (R/W) = Task 4 is executing

2

INT3

R

0h

Task 3 Run Status
Reset type: SYSRSn
0h (R/W) = Task 3 is not executing (default)
1h (R/W) = Task 3 is executing

1

INT2

R

0h

Task 2 Run Status
Reset type: SYSRSn
0h (R/W) = Task 2 is not executing (default)
1h (R/W) = Task 2 is executing

15-8

816

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 5-40. MIRUN Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

INT1

R

0h

Task 1 Run Status
Reset type: SYSRSn
0h (R/W) = Task 1 is not executing (default)
1h (R/W) = Task 1 is executing

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

817

Registers

www.ti.com

5.7.2.17 _MPC Register (Offset = 28h) [reset = 0h]
_MPC is shown in Figure 5-18 and described in Table 5-41.
Return to Summary Table.
CLA Program Counter
Figure 5-18. _MPC Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

_MPC
R/W-0h

Table 5-41. _MPC Register Field Descriptions

818

Bit

Field

Type

Reset

Description

15-0

_MPC

R/W

0h

Points to the instruction currently in the decode 2 phase of the CLA
pipeline. The address range of the CLA with a 16-bit MPC is 64K 16bit words or 32K CLA instructions.
Reset type: SYSRSn

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.18 _MAR0 Register (Offset = 2Ah) [reset = 0h]
_MAR0 is shown in Figure 5-19 and described in Table 5-42.
Return to Summary Table.
CLA Auxiliary Register 0
Figure 5-19. _MAR0 Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

_MAR0
R/W-0h

Table 5-42. _MAR0 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

_MAR0

R/W

0h

CLA Auxillary Register 0
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

819

Registers

www.ti.com

5.7.2.19 _MAR1 Register (Offset = 2Bh) [reset = 0h]
_MAR1 is shown in Figure 5-20 and described in Table 5-43.
Return to Summary Table.
CLA Auxiliary Register 1
Figure 5-20. _MAR1 Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

_MAR1
R/W-0h

Table 5-43. _MAR1 Register Field Descriptions
Bit
15-0

820

Field

Type

Reset

Description

_MAR1

R/W

0h

CLA Auxillary Register 1
Reset type: SYSRSn

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.20 _MSTF Register (Offset = 2Eh) [reset = 0h]
_MSTF is shown in Figure 5-21 and described in Table 5-44.
Return to Summary Table.
The CLA status register (MSTF) reflects the results of different operations. These are the basic rules for
the flags:
- Zero and negative flags are cleared or set based on:
- floating-point moves to registers
- the result of compare, minimum, maximum, negative and absolute value operations
- the integer result of operations such as MMOV16, MAND32, MOR32, MXOR32, MCMP32,
MASR32, MLSR32
- Overflow and underflow flags are set by floating-point math instructions such as multiply, add, subtract
and 1/x. These flags may also be connected to the peripheral interrupt expansion (PIE) block on your
device. This can be useful for debugging underflow and overflow conditions within an application.
Figure 5-21. _MSTF Register
31

30

29

28

27

26

RESERVED
R-0h
23

22

25

24

_RPC
R/W-0h
21

20

19

18

17

16

12

11
MEALLOW
R/W-0h

10
RESERVED
R-0h

9
RNDF32
R/W-0h

8
RESERVED
R-0h

4

3
ZF
R/W-0h

2
NF
R/W-0h

1
LUF
R/W-0h

0
LVF
R/W-0h

_RPC
R/W-0h
15

14

13
_RPC
R/W-0h

7
RESERVED
R-0h

6
TF
R/W-0h

5
RESERVED
R/W-0h

Table 5-44. _MSTF Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

R

0h

Reserved

27-12

_RPC

R/W

0h

Return program counter
The RPC is used to save and restore the MPC address by the
MCCNDD and MRCNDD operations
Reset type: SYSRSn

11

MEALLOW

R/W

0h

MEALLOW Status
This bit enables and disables CLA write access to EALLOW
protected registers This is independent of the state of the EALLOW
bit in the main CPU status register This status bit can be saved and
restored by the MMOV32 STF, mem32 instruction
Reset type: SYSRSn
0h (R/W) = The CLA cannot write to EALLOW protected registers.
This bit is cleared by the CLA instruction, MEDIS.
1h (R/W) = The CLA is allowed to write to EALLOW protected
registers. This bit is set by the CLA instruction, MEALLOW.

10

RESERVED

R

0h

Reserved

9

RNDF32

R/W

0h

Round 32-bit Floating-Point Mode
Use the MSETFLG and MMOV32 MSTF, mem32 instructions to
change the rounding mode
Reset type: SYSRSn
0h (R/W) = If this bit is zero, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to zero (truncate).
1h (R/W) = If this bit is one, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to the nearest even value.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

821

Registers

www.ti.com

Table 5-44. _MSTF Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8-7

RESERVED

R

0h

Reserved

TF

R/W

0h

Test Flag

6

The MTESTTF instruction can modify this flag based on the
condition tested The MSETFLG and MMOV32 MSTF, mem32
instructions can also be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The condition tested with the MTESTTF instruction is
false.
1h (R/W) = The condition tested with the MTESTTF instruction is
true.
5-4
3

RESERVED

R/W

0h

Reserved

ZF

R/W

0h

Zero Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result
of the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not zero
1h (R/W) = The value is zero

2

NF

R/W

0h

Negative Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result
of the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not negative
1h (R/W) = The value is negative

1

LUF

R/W

0h

Latched Underflow Flag
The following instructions will set this flag to 1 if an underflow occurs:
MMPYF32, MADDF32,
MSUBF32, MMACF32, MEINVF32, MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An underflow condition has not been latched
1h (R/W) = An underflow condition has been latched

822

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 5-44. _MSTF Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

LVF

R/W

0h

Latched Overflow Flag
The following instructions will set this flag to 1 if an overflow occurs:
MMPYF32, MADDF32, MSUBF32, MMACF32, MEINVF32,
MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An overflow condition has not been latched
1h (R/W) = An overflow condition has been latched

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

823

Registers

www.ti.com

5.7.2.21 _MR0 Register (Offset = 30h) [reset = 0h]
_MR0 is shown in Figure 5-22 and described in Table 5-45.
Return to Summary Table.
CLA Floating-Point Result Register 0
Figure 5-22. _MR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
i32
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 5-45. _MR0 Register Field Descriptions
Bit
31-0

824

Field

Type

Reset

Description

i32

R/W

0h

CLA Result Register 0
Reset type: SYSRSn

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.22 _MR1 Register (Offset = 34h) [reset = 0h]
_MR1 is shown in Figure 5-23 and described in Table 5-46.
Return to Summary Table.
CLA Floating-Point Result Register 1
Figure 5-23. _MR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
i32
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 5-46. _MR1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

i32

R/W

0h

CLA Result Register 1
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

825

Registers

www.ti.com

5.7.2.23 _MR2 Register (Offset = 38h) [reset = 0h]
_MR2 is shown in Figure 5-24 and described in Table 5-47.
Return to Summary Table.
CLA Floating-Point Result Register 2
Figure 5-24. _MR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
i32
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 5-47. _MR2 Register Field Descriptions
Bit
31-0

826

Field

Type

Reset

Description

i32

R/W

0h

CLA Result Register 2
Reset type: SYSRSn

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.2.24 _MR3 Register (Offset = 3Ch) [reset = 0h]
_MR3 is shown in Figure 5-25 and described in Table 5-48.
Return to Summary Table.
CLA Floating-Point Result Register 3
Figure 5-25. _MR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
i32
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 5-48. _MR3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

i32

R/W

0h

CLA Result Register 3
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

827

Registers

www.ti.com

5.7.3 CLA_SOFTINT_REGS Registers
Table 5-49 lists the memory-mapped registers for the CLA_SOFTINT_REGS. All register offset addresses
not listed in Table 5-49 should be considered as reserved locations and the register contents should not
be modified.
Table 5-49. CLA_SOFTINT_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

SOFTINTEN

CLA Software Interrupt Enable Register

Go

2h

SOFTINTFRC

CLA Software Interrupt Force Register

Go

Complex bit access types are encoded to fit into small table cells. Table 5-50 shows the codes that are
used for access types in this section.
Table 5-50. CLA_SOFTINT_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

Write

Read Type
R
Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

828

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.3.1

SOFTINTEN Register (Offset = 0h) [reset = 0h]

SOFTINTEN is shown in Figure 5-26 and described in Table 5-51.
Return to Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.
Figure 5-26. SOFTINTEN Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
TASK4
R/W-0h

2
TASK3
R/W-0h

1
TASK2
R/W-0h

0
TASK1
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7
TASK8
R/W-0h

6
TASK7
R/W-0h

5
TASK6
R/W-0h

4
TASK5
R/W-0h

Table 5-51. SOFTINTEN Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

TASK8

R/W

0h

Task 8 Software Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Task8 Software Interrupt is disabled.
1h (R/W) = Task8 Software Interrupt is enabled.

6

TASK7

R/W

0h

Task 7 Software Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Task7 Software Interrupt is disabled.
1h (R/W) = Task7 Software Interrupt is enabled.

5

TASK6

R/W

0h

Task 6 Software Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Task6 Software Interrupt is disabled.
1h (R/W) = Task6 Software Interrupt is enabled.

4

TASK5

R/W

0h

Task 5 Software Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Task5 Software Interrupt is disabled.
1h (R/W) = Task5 Software Interrupt is enabled.

3

TASK4

R/W

0h

Task 4 Software Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Task4 Software Interrupt is disabled.
1h (R/W) = Task4 Software Interrupt is enabled.

2

TASK3

R/W

0h

Task 3 Software Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Task3 Software Interrupt is disabled.
1h (R/W) = Task3 Software Interrupt is enabled.

1

TASK2

R/W

0h

Task 2 Software Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Task2 Software Interrupt is disabled.
1h (R/W) = Task2 Software Interrupt is enabled.

31-8

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

829

Registers

www.ti.com

Table 5-51. SOFTINTEN Register Field Descriptions (continued)
Bit
0

830

Field

Type

Reset

Description

TASK1

R/W

0h

Task 1 Software Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Task1 Software Interrupt is disabled.
1h (R/W) = Task1 Software Interrupt is enabled.

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

5.7.3.2

SOFTINTFRC Register (Offset = 2h) [reset = 0h]

SOFTINTFRC is shown in Figure 5-27 and described in Table 5-52.
Return to Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.This register is only accessible
by the CLA (not the CPU).
Figure 5-27. SOFTINTFRC Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
TASK4
R/W-0h

2
TASK3
R/W-0h

1
TASK2
R/W-0h

0
TASK1
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7
TASK8
R/W-0h

6
TASK7
R/W-0h

5
TASK6
R/W-0h

4
TASK5
R/W-0h

Table 5-52. SOFTINTFRC Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

TASK8

R/W

0h

Task 8 Software Interrupt Force
Reset type: SYSRSn
0h (R/W) = No action performed
1h (R/W) = Forces Task8 Software Interrupt

6

TASK7

R/W

0h

Task 7 Software Interrupt Force
Reset type: SYSRSn
0h (R/W) = No action performed
1h (R/W) = Forces Task7 Software Interrupt

5

TASK6

R/W

0h

Task 6 Software Interrupt Force
Reset type: SYSRSn
0h (R/W) = No action performed
1h (R/W) = Forces Task6 Software Interrupt

4

TASK5

R/W

0h

Task 5 Software Interrupt Force
Reset type: SYSRSn
0h (R/W) = No action performed
1h (R/W) = Forces Task5 Software Interrupt

3

TASK4

R/W

0h

Task 4 Software Interrupt Force
Reset type: SYSRSn
0h (R/W) = No action performed
1h (R/W) = Forces Task4 Software Interrupt

2

TASK3

R/W

0h

Task 3 Software Interrupt Force
Reset type: SYSRSn
0h (R/W) = No action performed
1h (R/W) = Forces Task3 Software Interrupt

1

TASK2

R/W

0h

Task 2 Software Interrupt Force
Reset type: SYSRSn
0h (R/W) = No action performed
1h (R/W) = Forces Task2 Software Interrupt

31-8

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Control Law Accelerator (CLA)

831

Registers

www.ti.com

Table 5-52. SOFTINTFRC Register Field Descriptions (continued)
Bit
0

832

Field

Type

Reset

Description

TASK1

R/W

0h

Task 1 Software Interrupt Force
Reset type: SYSRSn
0h (R/W) = No action performed
1h (R/W) = Forces Task1 Software Interrupt

Control Law Accelerator (CLA)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 6
SPRUHM8G – December 2013 – Revised September 2017

Inter-Processor Communication (IPC)
Topic

...........................................................................................................................

6.1
6.2
6.3
6.4
6.5
6.6
6.7

Inter-Processor Communication .........................................................................
Message RAMs.................................................................................................
IPC Flags and Interrupts ....................................................................................
IPC Command Registers ...................................................................................
Free-Running Counter .......................................................................................
IPC Communication Protocol .............................................................................
Registers .........................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

Page

834
835
835
835
836
837
838

833

Inter-Processor Communication

6.1

www.ti.com

Inter-Processor Communication
The Inter-Processor Communications (IPC) module allows communication between the two CPU
subsystems. This section details the IPC features that each CPU can use to request and share
information. The IPC features are:
• Message RAMs
• IPC flags and interrupts
• IPC command registers
• Flash pump semaphore
• Clock configuration semaphore
• Free-running counter
All IPC features are independent of each other, and most do not require any specific data format. There
are also two registers for boot mode/status communication. Please refer to the boot ROM chapter for
more information on these registers.
Figure 6-1 shows the design structure of the IPC module.
Figure 6-1. IPC Module Architecture
SET31
CLR31
ACK31
FLG31
R=0/W=1

IPCSET[31:0]

R=0/W=1

IPCCLR[31:0]

SET0
CLR0

ACK0

IPCACK[31:0]

R=0/W=1

FLG0
Gen Int Pulse
(on FLG 0->1)
R

IPCFLG[31:0]

R/W

IPCSENDCOM[31:0]

R/W
R/W
R

CPU2.
ePIE

IPCSTS[31:0]

R

C1TOC2IPCCOM[31:0]

IPCRECVCOM[31:0]

R

IPCSENDADDR[31:0]

C1TOC2IPCADDR[31:0]

IPCRECVADDR[31:0]

R

IPCSENDDATA[31:0]

C1TOC2IPCDATAW[31:0]

IPCRECVDATA[31:0]

R

IPCREMOTEREPLY[31:0]

C1TOC2IPCDATAR[31:0]

IPCLOCALREPLY[31:0]

R/W

R/W

IPCBOOTMODE[31:0]

R

R

IPCBOOTSTS[31:0]

R/W

CPU1.EmulationHalt

CPU1

C1TOC2IPCINT1/2/3/4

64-bit Free Run Counter

R

IPCCOUNTERH/L[31:0]

CPU2.EmulationHalt
PLLSYSCLK
R

CPU2

SET31
ACK31
CLR31
FLG31

R=0/W=1

SET0
CLR0

ACK0

IPCACK[31:0]

IPCSET[31:0]

R=0/W=1

IPCCLR[31:0]

R=0/W=1

IPCFLG[31:0]

R

FLG0

CPU1.
ePIE
R

834

Gen Int Pulse
(on FLG 0->1)

C2TOC1IPCINT1/2/3/4
IPCSTS[31:0]

R

IPCRECVCOM[31:0]

C2TOC1IPCCOM[31:0]

IPCSENDCOM[31:0]

R/W

R

IPCRECVADDR[31:0]

C2TOC1IPCADDR[31:0]

IPCSENDADDR[31:0]

R/W

R

IPCRECVDATA[31:0]

C2TOC1IPCDATAW[31:0]

IPCSENDDATA[31:0]

R/W

R/W

IPCLOCALREPLY[31:0]

C2TOC1IPCDATAR[31:0]

IPCREMOTEREPLY[31:0]

R

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Message RAMs

www.ti.com

6.2

Message RAMs
There are two dedicated 2kB blocks of message RAM. Each CPU and its DMA have read/write access to
one RAM and read-only access to the other RAM, as shown in Table 6-1
Table 6-1. IPC Message RAM Read/Write Access
CPU1

CPU2

CPU1 DMA

CPU2 DMA

CPU1 to CPU2 (1K x 16,
address 0x03FC00)

R/W

R

R/W

R

CPU2 to CPU1 (1K x 16,
address 0x03F800)

R

R/W

R

R/W

Reading or writing a message RAM does not trigger any events on the remote CPU.

6.3

IPC Flags and Interrupts
There are 32 IPC event signals from CPU1 to CPU2, and vice-versa. These signals can be used for flagbased event polling. Four of them (IPC0 - IPC3) can be configured to generate IPC interrupts on the
remote CPU. Figure 6-2 shows the IPC flag messaging and interrupt system.
Figure 6-2. Messaging with IPC Flags and Interrupts
CPU1 Memory Map

IPC Registers

CPU1 to CPU2
Set

CPU2 Memory Map
PIE
(IPC0-3)

Q

IPCSET
IPC Registers

Clear
IPCCLR

IPCACK

IPCFLG

IPCSTS

IPCSTS

IPCFLG

IPCACK

IPCCLR

R/W
CPU1

R/W
CPU2

Clear
IPCSET

PIE
(IPC0-3)

Q

Set

CPU2 to CPU1

6.4

IPC Command Registers
The IPC command registers provide a simple and flexible way for the two CPUs to exchange more
complex messages. Each CPU has eight dedicated registers, four for sending messages and four for
receiving messages. The register names were chosen to support a simple command/response protocol,
but can be used for any purpose. Only the read/write permissions are determined by hardware; the data
format is entirely software-defined.
For sending messages, each CPU has three writable registers and one read-only register. Those same
registers are accessible on the remote CPU as three read-only registers and one writable register.
Table 6-2 shows the command registers.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

835

Free-Running Counter

www.ti.com

Table 6-2. IPC Command Registers

6.5

Local Register Name

Local CPU

Remote CPU

IPCSENDCOM

R/W

R

Remote Register Name
IPCRECVCOM

IPCSENDADDR

R/W

R

IPCRECVADDR

IPCSENDDATA

R/W

R

IPCRECVDATA

IPCREMOTEREPLY

R

R/W

IPCLOCALREPLY

Free-Running Counter
A 64-bit free-running counter is present in the device and can be used to timestamp IPC events between
processors. The counter is clocked by PLLSYSCLK and reset by SYSRSn. The counter is implemented as
two 32-bit registers, IPCCOUNTERH and IPCCOUNTERL. When IPCCOUNTERL is read, the value of
IPCCOUNTERH is saved. A subsequent read to IPCCOUNTERH returns this saved value. This design
prevents race conditions due to IPCCOUNTERL overflowing between reads of the two registers.
The free-running counter only stops when both CPUs are in HALT mode. If either core is executing, the
counter runs.

836

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

IPC Communication Protocol

www.ti.com

6.6

IPC Communication Protocol
This section describes the hardware support options for IPC communication between the two CPUs.
These options can be used independently or in combination. All flag definitions and data formats are
entirely user-defined.
• The flag system supports event-based communication via interrupts and register polling.
– CPUx can raise an IPC event by writing to any of the 32 bits of its IPCSET register. This sets the
corresponding bits in CPUx's IPCFLG register and CPUy's IPCSTS register.
– CPUy can signal its response to the event by setting the appropriate bit in its IPCACK register. This
clears the corresponding bits in CPUx's IPCFLG register and CPUy's IPCSTS register.
– If CPUx needs to cancel an event, it can set the appropriate bit in its IPCCLR register. This has the
same effect as CPUy writing to IPCACK.
– Flags 0–3 (set via IPCSET[3:0]) fire interrupts to the remote CPU. The remote CPU must configure
its ePIE module properly in order to receive an IPC interrupt. Flags 4–31 (set via IPCSET[31:4]) do
not produce interrupts. Multiple flags can be set, acknowledged, and cleared simultaneously.
• The command registers support sending several distinct pieces of information. They are named COM,
ADDR, DATA, and REPLY for convenience only and can hold whatever data the application needs.
– CPUx can write data to its IPCSENDCOM, IPCSENDADDR, and IPCSENDDATA registers. CPUy
receives these in its IPCRECVCOM, IPCRECVADDR, and IPCRECVDATA registers.
– CPUy can respond by writing to its IPCLOCALREPLY register. CPUx receives this data in its
IPCREMOTEREPLY register.
– Each CPU can only write to its SEND and LOCALREPLY registers. The RECV and
REMOTEREPLY registers are read-only.
• There is an additional pair of command-like registers offered for boot-time IPC or any other convenient
use — IPCBOOTMODE and IPCBOOTSTS. Both CPUs can read these registers. CPU1 can only write
to IPCBOOTMODE, and CPU2 can only write to IPCBOOTSTS.
• There are two shared memories for passing large amounts of data between the CPUs. Each CPU has
a writable memory for sending data and a read-only memory for receiving data.
• Here is an example of how to use these features together. CPUx needs some data from CPUy's LS
RAM. The data is at CPUy address 0x9400 and is 0x80 16-bit words long. The protocol could be
implemented like this:
– CPUx writes 0x1 to IPCSENDCOM, defined in software to mean "copy data from address". It writes
the address (0x9400) to IPCSENDADDR and the data length (0x80) to IPCSENDDATA.
– CPUx writes to IPCSET[3] and IPCSET[16]. Here, IPC flag 3 is configured to send an interrupt and
IPCSET[16] is defined in software to indicate an incoming command. CPUx begins polling for
IPCFLG[3] to go low.
– CPUy receives the interrupt. In the interrupt handler, it checks IPCSTS, finds that flag 16 is set, and
runs a command processor.
– CPUy reads the command (0x1) from IPCRECVCOM, the address (0x9400) from IPCRECVADDR,
and the data length (0x80) from IPCRECVDATA. CPUy then copies the LS RAM data to an empty
space in its writable shared memory starting at offset 0x210.
– CPUy writes the shared memory address (0x210) to its IPCLOCALREPLY register. It then writes to
IPCACK[16] and IPCACK[3] to clear the flags and indicate completion of the command. CPUy's
work is done.
– CPUx sees IPCFLG[3] go low. It reads IPCREMOTEREPLY to get the shared memory offset of the
copied data (0x210).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

837

Registers

6.7

www.ti.com

Registers

6.7.1 IPC Base Addresses
Table 6-3. IPC Base Addresses
Device Registers

838

Register Name

Start Address

End Address

IpcRegs (CPU1)

IPC_REGS_CPU1

0x0005_0000

0x0005_0023

IpcRegs (CPU2)

IPC_REGS_CPU2

0x0005_0000

0x0005_0023

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2 IPC_REGS_CPU1 Registers
Table 6-4 lists the memory-mapped registers for the IPC_REGS_CPU1. All register offset addresses not
listed in Table 6-4 should be considered as reserved locations and the register contents should not be
modified.
Table 6-4. IPC_REGS_CPU1 Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

IPCACK

IPC incoming flag clear (acknowledge) register

Go

2h

IPCSTS

IPC incoming flag status register

Go

4h

IPCSET

IPC remote flag set register

Go

6h

IPCCLR

IPC remote flag clear register

Go

8h

IPCFLG

IPC remote flag status register

Go

Ch

IPCCOUNTERL

IPC Counter Low Register

Go

Eh

IPCCOUNTERH

IPC Counter High Register

Go

10h

IPCSENDCOM

Local to Remote IPC Command Register

Go

12h

IPCSENDADDR

Local to Remote IPC Address Register

Go

14h

IPCSENDDATA

Local to Remote IPC Data Register

Go

16h

IPCREMOTEREPLY

Remote to Local IPC Reply Data Register

Go

18h

IPCRECVCOM

Remote to Local IPC Command Register

Go

1Ah

IPCRECVADDR

Remote to Local IPC Address Register

Go

1Ch

IPCRECVDATA

Remote to Local IPC Data Register

Go

1Eh

IPCLOCALREPLY

Local to Remote IPC Reply Data Register

Go

20h

IPCBOOTSTS

CPU2 to CPU1 IPC Boot Status Register

Go

22h

IPCBOOTMODE

CPU1 to CPU2 IPC Boot Mode Register

Go

Complex bit access types are encoded to fit into small table cells. Table 6-5 shows the codes that are
used for access types in this section.
Table 6-5. IPC_REGS_CPU1 Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

839

Registers

6.7.2.1

www.ti.com

IPCACK Register (Offset = 0h) [reset = 0h]

IPCACK is shown in Figure 6-20 and described in Table 6-25.
Return to Summary Table.
IPC incoming flag clear (acknowledge) register
Figure 6-3. IPCACK Register
31
IPC31
R=0/W=1-0h

30
IPC30
R=0/W=1-0h

29
IPC29
R=0/W=1-0h

28
IPC28
R=0/W=1-0h

27
IPC27
R=0/W=1-0h

26
IPC26
R=0/W=1-0h

25
IPC25
R=0/W=1-0h

24
IPC24
R=0/W=1-0h

23
IPC23
R=0/W=1-0h

22
IPC22
R=0/W=1-0h

21
IPC21
R=0/W=1-0h

20
IPC20
R=0/W=1-0h

19
IPC19
R=0/W=1-0h

18
IPC18
R=0/W=1-0h

17
IPC17
R=0/W=1-0h

16
IPC16
R=0/W=1-0h

15
IPC15
R=0/W=1-0h

14
IPC14
R=0/W=1-0h

13
IPC13
R=0/W=1-0h

12
IPC12
R=0/W=1-0h

11
IPC11
R=0/W=1-0h

10
IPC10
R=0/W=1-0h

9
IPC9
R=0/W=1-0h

8
IPC8
R=0/W=1-0h

7
IPC7
R=0/W=1-0h

6
IPC6
R=0/W=1-0h

5
IPC5
R=0/W=1-0h

4
IPC4
R=0/W=1-0h

3
IPC3
R=0/W=1-0h

2
IPC2
R=0/W=1-0h

1
IPC1
R=0/W=1-0h

0
IPC0
R=0/W=1-0h

Table 6-6. IPCACK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R=0/W=1

0h

Writing 1 to this bit clears the IPC31 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

30

IPC30

R=0/W=1

0h

Writing 1 to this bit clears the IPC30 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

29

IPC29

R=0/W=1

0h

Writing 1 to this bit clears the IPC29 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

28

IPC28

R=0/W=1

0h

Writing 1 to this bit clears the IPC28 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

27

IPC27

R=0/W=1

0h

Writing 1 to this bit clears the IPC27 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

26

IPC26

R=0/W=1

0h

Writing 1 to this bit clears the IPC26 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

25

IPC25

R=0/W=1

0h

Writing 1 to this bit clears the IPC25 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

840

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-6. IPCACK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

24

IPC24

R=0/W=1

0h

Writing 1 to this bit clears the IPC24 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

23

IPC23

R=0/W=1

0h

Writing 1 to this bit clears the IPC23 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

22

IPC22

R=0/W=1

0h

Writing 1 to this bit clears the IPC22 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

21

IPC21

R=0/W=1

0h

Writing 1 to this bit clears the IPC21 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

20

IPC20

R=0/W=1

0h

Writing 1 to this bit clears the IPC20 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

19

IPC19

R=0/W=1

0h

Writing 1 to this bit clears the IPC19 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

18

IPC18

R=0/W=1

0h

Writing 1 to this bit clears the IPC18 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

17

IPC17

R=0/W=1

0h

Writing 1 to this bit clears the IPC17 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

16

IPC16

R=0/W=1

0h

Writing 1 to this bit clears the IPC16 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

15

IPC15

R=0/W=1

0h

Writing 1 to this bit clears the IPC15 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

14

IPC14

R=0/W=1

0h

Writing 1 to this bit clears the IPC14 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

13

IPC13

R=0/W=1

0h

Writing 1 to this bit clears the IPC13 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

12

IPC12

R=0/W=1

0h

Writing 1 to this bit clears the IPC12 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

841

Registers

www.ti.com

Table 6-6. IPCACK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

IPC11

R=0/W=1

0h

Writing 1 to this bit clears the IPC11 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

10

IPC10

R=0/W=1

0h

Writing 1 to this bit clears the IPC10 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

9

IPC9

R=0/W=1

0h

Writing 1 to this bit clears the IPC9 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

8

IPC8

R=0/W=1

0h

Writing 1 to this bit clears the IPC8 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

7

IPC7

R=0/W=1

0h

Writing 1 to this bit clears the IPC7 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

6

IPC6

R=0/W=1

0h

Writing 1 to this bit clears the IPC6 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

5

IPC5

R=0/W=1

0h

Writing 1 to this bit clears the IPC5 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

4

IPC4

R=0/W=1

0h

Writing 1 to this bit clears the IPC4 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

3

IPC3

R=0/W=1

0h

Writing 1 to this bit clears the IPC3 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

2

IPC2

R=0/W=1

0h

Writing 1 to this bit clears the IPC2 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

1

IPC1

R=0/W=1

0h

Writing 1 to this bit clears the IPC1 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

0

IPC0

R=0/W=1

0h

Writing 1 to this bit clears the IPC0 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

842

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2.2

IPCSTS Register (Offset = 2h) [reset = 0h]

IPCSTS is shown in Figure 6-21 and described in Table 6-26.
Return to Summary Table.
IPC incoming flag status register
Figure 6-4. IPCSTS Register
31
IPC31
R-0h

30
IPC30
R-0h

29
IPC29
R-0h

28
IPC28
R-0h

27
IPC27
R-0h

26
IPC26
R-0h

25
IPC25
R-0h

24
IPC24
R-0h

23
IPC23
R-0h

22
IPC22
R-0h

21
IPC21
R-0h

20
IPC20
R-0h

19
IPC19
R-0h

18
IPC18
R-0h

17
IPC17
R-0h

16
IPC16
R-0h

15
IPC15
R-0h

14
IPC14
R-0h

13
IPC13
R-0h

12
IPC12
R-0h

11
IPC11
R-0h

10
IPC10
R-0h

9
IPC9
R-0h

8
IPC8
R-0h

7
IPC7
R-0h

6
IPC6
R-0h

5
IPC5
R-0h

4
IPC4
R-0h

3
IPC3
R-0h

2
IPC2
R-0h

1
IPC1
R-0h

0
IPC0
R-0h

Table 6-7. IPCSTS Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R

0h

Indicates to the local CPU if the IPC31 event flag was set by the
remote CPU.
0: No IPC31 event was set by the remote CPU
1: An IPC31 event was set by the remote CPU
Reset type: SYSRSn

30

IPC30

R

0h

Indicates to the local CPU if the IPC30 event flag was set by the
remote CPU.
0: No IPC30 event was set by the remote CPU
1: An IPC30 event was set by the remote CPU
Reset type: SYSRSn

29

IPC29

R

0h

Indicates to the local CPU if the IPC29 event flag was set by the
remote CPU.
0: No IPC29 event was set by the remote CPU
1: An IPC29 event was set by the remote CPU
Reset type: SYSRSn

28

IPC28

R

0h

Indicates to the local CPU if the IPC28 event flag was set by the
remote CPU.
0: No IPC28 event was set by the remote CPU
1: An IPC28 event was set by the remote CPU
Reset type: SYSRSn

27

IPC27

R

0h

Indicates to the local CPU if the IPC27 event flag was set by the
remote CPU.
0: No IPC27 event was set by the remote CPU
1: An IPC27 event was set by the remote CPU
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

843

Registers

www.ti.com

Table 6-7. IPCSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

26

IPC26

R

0h

Indicates to the local CPU if the IPC26 event flag was set by the
remote CPU.
0: No IPC26 event was set by the remote CPU
1: An IPC26 event was set by the remote CPU
Reset type: SYSRSn

25

IPC25

R

0h

Indicates to the local CPU if the IPC25 event flag was set by the
remote CPU.
0: No IPC25 event was set by the remote CPU
1: An IPC25 event was set by the remote CPU
Reset type: SYSRSn

24

IPC24

R

0h

Indicates to the local CPU if the IPC24 event flag was set by the
remote CPU.
0: No IPC24 event was set by the remote CPU
1: An IPC24 event was set by the remote CPU
Reset type: SYSRSn

23

IPC23

R

0h

Indicates to the local CPU if the IPC23 event flag was set by the
remote CPU.
0: No IPC23 event was set by the remote CPU
1: An IPC23 event was set by the remote CPU
Reset type: SYSRSn

22

IPC22

R

0h

Indicates to the local CPU if the IPC22 event flag was set by the
remote CPU.
0: No IPC22 event was set by the remote CPU
1: An IPC22 event was set by the remote CPU
Reset type: SYSRSn

21

IPC21

R

0h

Indicates to the local CPU if the IPC21 event flag was set by the
remote CPU.
0: No IPC21 event was set by the remote CPU
1: An IPC21 event was set by the remote CPU
Reset type: SYSRSn

20

IPC20

R

0h

Indicates to the local CPU if the IPC20 event flag was set by the
remote CPU.
0: No IPC20 event was set by the remote CPU
1: An IPC20 event was set by the remote CPU
Reset type: SYSRSn

19

IPC19

R

0h

Indicates to the local CPU if the IPC19 event flag was set by the
remote CPU.
0: No IPC19 event was set by the remote CPU
1: An IPC19 event was set by the remote CPU
Reset type: SYSRSn

18

IPC18

R

0h

Indicates to the local CPU if the IPC18 event flag was set by the
remote CPU.
0: No IPC18 event was set by the remote CPU
1: An IPC18 event was set by the remote CPU
Reset type: SYSRSn

844

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-7. IPCSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

17

IPC17

R

0h

Indicates to the local CPU if the IPC17 event flag was set by the
remote CPU.
0: No IPC17 event was set by the remote CPU
1: An IPC17 event was set by the remote CPU
Reset type: SYSRSn

16

IPC16

R

0h

Indicates to the local CPU if the IPC16 event flag was set by the
remote CPU.
0: No IPC16 event was set by the remote CPU
1: An IPC16 event was set by the remote CPU
Reset type: SYSRSn

15

IPC15

R

0h

Indicates to the local CPU if the IPC15 event flag was set by the
remote CPU.
0: No IPC15 event was set by the remote CPU
1: An IPC15 event was set by the remote CPU
Reset type: SYSRSn

14

IPC14

R

0h

Indicates to the local CPU if the IPC14 event flag was set by the
remote CPU.
0: No IPC14 event was set by the remote CPU
1: An IPC14 event was set by the remote CPU
Reset type: SYSRSn

13

IPC13

R

0h

Indicates to the local CPU if the IPC13 event flag was set by the
remote CPU.
0: No IPC13 event was set by the remote CPU
1: An IPC13 event was set by the remote CPU
Reset type: SYSRSn

12

IPC12

R

0h

Indicates to the local CPU if the IPC12 event flag was set by the
remote CPU.
0: No IPC12 event was set by the remote CPU
1: An IPC12 event was set by the remote CPU
Reset type: SYSRSn

11

IPC11

R

0h

Indicates to the local CPU if the IPC11 event flag was set by the
remote CPU.
0: No IPC11 event was set by the remote CPU
1: An IPC11 event was set by the remote CPU
Reset type: SYSRSn

10

IPC10

R

0h

Indicates to the local CPU if the IPC10 event flag was set by the
remote CPU.
0: No IPC10 event was set by the remote CPU
1: An IPC10 event was set by the remote CPU
Reset type: SYSRSn

9

IPC9

R

0h

Indicates to the local CPU if the IPC9 event flag was set by the
remote CPU.
0: No IPC9 event was set by the remote CPU
1: An IPC9 event was set by the remote CPU
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

845

Registers

www.ti.com

Table 6-7. IPCSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8

IPC8

R

0h

Indicates to the local CPU if the IPC8 event flag was set by the
remote CPU.
0: No IPC8 event was set by the remote CPU
1: An IPC8 event was set by the remote CPU
Reset type: SYSRSn

7

IPC7

R

0h

Indicates to the local CPU if the IPC7 event flag was set by the
remote CPU.
0: No IPC7 event was set by the remote CPU
1: An IPC7 event was set by the remote CPU
Reset type: SYSRSn

6

IPC6

R

0h

Indicates to the local CPU if the IPC6 event flag was set by the
remote CPU.
0: No IPC6 event was set by the remote CPU
1: An IPC6 event was set by the remote CPU
Reset type: SYSRSn

5

IPC5

R

0h

Indicates to the local CPU if the IPC5 event flag was set by the
remote CPU.
0: No IPC5 event was set by the remote CPU
1: An IPC5 event was set by the remote CPU
Reset type: SYSRSn

4

IPC4

R

0h

Indicates to the local CPU if the IPC4 event flag was set by the
remote CPU.
0: No IPC4 event was set by the remote CPU
1: An IPC4 event was set by the remote CPU
Reset type: SYSRSn

3

IPC3

R

0h

Indicates to the local CPU if the IPC3 event flag was set by the
remote CPU.
0: No IPC3 event was set by the remote CPU
1: An IPC3 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

2

IPC2

R

0h

Indicates to the local CPU if the IPC2 event flag was set by the
remote CPU.
0: No IPC2 event was set by the remote CPU
1: An IPC2 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

1

IPC1

R

0h

Indicates to the local CPU if the IPC1 event flag was set by the
remote CPU.
0: No IPC1 event was set by the remote CPU
1: An IPC1 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

846

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-7. IPCSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

IPC0

R

0h

Indicates to the local CPU if the IPC0 event flag was set by the
remote CPU.
0: No IPC0 event was set by the remote CPU
1: An IPC0 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

847

Registers

6.7.2.3

www.ti.com

IPCSET Register (Offset = 4h) [reset = 0h]

IPCSET is shown in Figure 6-22 and described in Table 6-27.
Return to Summary Table.
IPC remote flag set register
Figure 6-5. IPCSET Register
31
IPC31
R=0/W=1-0h

30
IPC30
R=0/W=1-0h

29
IPC29
R=0/W=1-0h

28
IPC28
R=0/W=1-0h

27
IPC27
R=0/W=1-0h

26
IPC26
R=0/W=1-0h

25
IPC25
R=0/W=1-0h

24
IPC24
R=0/W=1-0h

23
IPC23
R=0/W=1-0h

22
IPC22
R=0/W=1-0h

21
IPC21
R=0/W=1-0h

20
IPC20
R=0/W=1-0h

19
IPC19
R=0/W=1-0h

18
IPC18
R=0/W=1-0h

17
IPC17
R=0/W=1-0h

16
IPC16
R=0/W=1-0h

15
IPC15
R=0/W=1-0h

14
IPC14
R=0/W=1-0h

13
IPC13
R=0/W=1-0h

12
IPC12
R=0/W=1-0h

11
IPC11
R=0/W=1-0h

10
IPC10
R=0/W=1-0h

9
IPC9
R=0/W=1-0h

8
IPC8
R=0/W=1-0h

7
IPC7
R=0/W=1-0h

6
IPC6
R=0/W=1-0h

5
IPC5
R=0/W=1-0h

4
IPC4
R=0/W=1-0h

3
IPC3
R=0/W=1-0h

2
IPC2
R=0/W=1-0h

1
IPC1
R=0/W=1-0h

0
IPC0
R=0/W=1-0h

Table 6-8. IPCSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R=0/W=1

0h

Writing 1 to this bit sets the IPC31 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

30

IPC30

R=0/W=1

0h

Writing 1 to this bit sets the IPC30 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

29

IPC29

R=0/W=1

0h

Writing 1 to this bit sets the IPC29 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

28

IPC28

R=0/W=1

0h

Writing 1 to this bit sets the IPC28 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

27

IPC27

R=0/W=1

0h

Writing 1 to this bit sets the IPC27 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

26

IPC26

R=0/W=1

0h

Writing 1 to this bit sets the IPC26 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

25

IPC25

R=0/W=1

0h

Writing 1 to this bit sets the IPC25 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

24

IPC24

R=0/W=1

0h

Writing 1 to this bit sets the IPC24 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

23

IPC23

R=0/W=1

0h

Writing 1 to this bit sets the IPC23 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

848

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-8. IPCSET Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

22

IPC22

R=0/W=1

0h

Writing 1 to this bit sets the IPC22 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

21

IPC21

R=0/W=1

0h

Writing 1 to this bit sets the IPC21 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

20

IPC20

R=0/W=1

0h

Writing 1 to this bit sets the IPC20 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

19

IPC19

R=0/W=1

0h

Writing 1 to this bit sets the IPC19 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

18

IPC18

R=0/W=1

0h

Writing 1 to this bit sets the IPC18 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

17

IPC17

R=0/W=1

0h

Writing 1 to this bit sets the IPC17 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

16

IPC16

R=0/W=1

0h

Writing 1 to this bit sets the IPC16 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

15

IPC15

R=0/W=1

0h

Writing 1 to this bit sets the IPC15 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

14

IPC14

R=0/W=1

0h

Writing 1 to this bit sets the IPC14 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

13

IPC13

R=0/W=1

0h

Writing 1 to this bit sets the IPC13 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

12

IPC12

R=0/W=1

0h

Writing 1 to this bit sets the IPC12 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

11

IPC11

R=0/W=1

0h

Writing 1 to this bit sets the IPC11 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

10

IPC10

R=0/W=1

0h

Writing 1 to this bit sets the IPC10 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

9

IPC9

R=0/W=1

0h

Writing 1 to this bit sets the IPC9 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

8

IPC8

R=0/W=1

0h

Writing 1 to this bit sets the IPC8 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

7

IPC7

R=0/W=1

0h

Writing 1 to this bit sets the IPC7 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

849

Registers

www.ti.com

Table 6-8. IPCSET Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

IPC6

R=0/W=1

0h

Writing 1 to this bit sets the IPC6 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

5

IPC5

R=0/W=1

0h

Writing 1 to this bit sets the IPC5 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

4

IPC4

R=0/W=1

0h

Writing 1 to this bit sets the IPC4 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

3

IPC3

R=0/W=1

0h

Writing 1 to this bit sets the IPC3 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

2

IPC2

R=0/W=1

0h

Writing 1 to this bit sets the IPC2 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

1

IPC1

R=0/W=1

0h

Writing 1 to this bit sets the IPC1 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

0

IPC0

R=0/W=1

0h

Writing 1 to this bit sets the IPC0 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

850

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2.4

IPCCLR Register (Offset = 6h) [reset = 0h]

IPCCLR is shown in Figure 6-23 and described in Table 6-28.
Return to Summary Table.
IPC remote flag clear register
Figure 6-6. IPCCLR Register
31
IPC31
R=0/W=1-0h

30
IPC30
R=0/W=1-0h

29
IPC29
R=0/W=1-0h

28
IPC28
R=0/W=1-0h

27
IPC27
R=0/W=1-0h

26
IPC26
R=0/W=1-0h

25
IPC25
R=0/W=1-0h

24
IPC24
R=0/W=1-0h

23
IPC23
R=0/W=1-0h

22
IPC22
R=0/W=1-0h

21
IPC21
R=0/W=1-0h

20
IPC20
R=0/W=1-0h

19
IPC19
R=0/W=1-0h

18
IPC18
R=0/W=1-0h

17
IPC17
R=0/W=1-0h

16
IPC16
R=0/W=1-0h

15
IPC15
R=0/W=1-0h

14
IPC14
R=0/W=1-0h

13
IPC13
R=0/W=1-0h

12
IPC12
R=0/W=1-0h

11
IPC11
R=0/W=1-0h

10
IPC10
R=0/W=1-0h

9
IPC9
R=0/W=1-0h

8
IPC8
R=0/W=1-0h

7
IPC7
R=0/W=1-0h

6
IPC6
R=0/W=1-0h

5
IPC5
R=0/W=1-0h

4
IPC4
R=0/W=1-0h

3
IPC3
R=0/W=1-0h

2
IPC2
R=0/W=1-0h

1
IPC1
R=0/W=1-0h

0
IPC0
R=0/W=1-0h

Table 6-9. IPCCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R=0/W=1

0h

Writing 1 to this bit clears the IPC31 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

30

IPC30

R=0/W=1

0h

Writing 1 to this bit clears the IPC30 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

29

IPC29

R=0/W=1

0h

Writing 1 to this bit clears the IPC29 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

28

IPC28

R=0/W=1

0h

Writing 1 to this bit clears the IPC28 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

851

Registers

www.ti.com

Table 6-9. IPCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

IPC27

R=0/W=1

0h

Writing 1 to this bit clears the IPC27 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

26

IPC26

R=0/W=1

0h

Writing 1 to this bit clears the IPC26 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

25

IPC25

R=0/W=1

0h

Writing 1 to this bit clears the IPC25 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

24

IPC24

R=0/W=1

0h

Writing 1 to this bit clears the IPC24 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

23

IPC23

R=0/W=1

0h

Writing 1 to this bit clears the IPC23 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

22

IPC22

R=0/W=1

0h

Writing 1 to this bit clears the IPC22 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

21

IPC21

R=0/W=1

0h

Writing 1 to this bit clears the IPC21 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

852

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-9. IPCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

IPC20

R=0/W=1

0h

Writing 1 to this bit clears the IPC20 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

19

IPC19

R=0/W=1

0h

Writing 1 to this bit clears the IPC19 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

18

IPC18

R=0/W=1

0h

Writing 1 to this bit clears the IPC18 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

17

IPC17

R=0/W=1

0h

Writing 1 to this bit clears the IPC17 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

16

IPC16

R=0/W=1

0h

Writing 1 to this bit clears the IPC16 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

15

IPC15

R=0/W=1

0h

Writing 1 to this bit clears the IPC15 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

14

IPC14

R=0/W=1

0h

Writing 1 to this bit clears the IPC14 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

853

Registers

www.ti.com

Table 6-9. IPCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

IPC13

R=0/W=1

0h

Writing 1 to this bit clears the IPC13 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

12

IPC12

R=0/W=1

0h

Writing 1 to this bit clears the IPC12 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

11

IPC11

R=0/W=1

0h

Writing 1 to this bit clears the IPC11 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

10

IPC10

R=0/W=1

0h

Writing 1 to this bit clears the IPC10 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

9

IPC9

R=0/W=1

0h

Writing 1 to this bit clears the IPC9 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

8

IPC8

R=0/W=1

0h

Writing 1 to this bit clears the IPC8 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

7

IPC7

R=0/W=1

0h

Writing 1 to this bit clears the IPC7 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

854

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-9. IPCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

IPC6

R=0/W=1

0h

Writing 1 to this bit clears the IPC6 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

5

IPC5

R=0/W=1

0h

Writing 1 to this bit clears the IPC5 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

4

IPC4

R=0/W=1

0h

Writing 1 to this bit clears the IPC4 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

3

IPC3

R=0/W=1

0h

Writing 1 to this bit clears the IPC3 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

2

IPC2

R=0/W=1

0h

Writing 1 to this bit clears the IPC2 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

1

IPC1

R=0/W=1

0h

Writing 1 to this bit clears the IPC1 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

0

IPC0

R=0/W=1

0h

Writing 1 to this bit clears the IPC0 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

855

Registers

6.7.2.5

www.ti.com

IPCFLG Register (Offset = 8h) [reset = 0h]

IPCFLG is shown in Figure 6-24 and described in Table 6-29.
Return to Summary Table.
IPC remote flag status register
Figure 6-7. IPCFLG Register
31
IPC31
R-0h

30
IPC30
R-0h

29
IPC29
R-0h

28
IPC28
R-0h

27
IPC27
R-0h

26
IPC26
R-0h

25
IPC25
R-0h

24
IPC24
R-0h

23
IPC23
R-0h

22
IPC22
R-0h

21
IPC21
R-0h

20
IPC20
R-0h

19
IPC19
R-0h

18
IPC18
R-0h

17
IPC17
R-0h

16
IPC16
R-0h

15
IPC15
R-0h

14
IPC14
R-0h

13
IPC13
R-0h

12
IPC12
R-0h

11
IPC11
R-0h

10
IPC10
R-0h

9
IPC9
R-0h

8
IPC8
R-0h

7
IPC7
R-0h

6
IPC6
R-0h

5
IPC5
R-0h

4
IPC4
R-0h

3
IPC3
R-0h

2
IPC2
R-0h

1
IPC1
R-0h

0
IPC0
R-0h

Table 6-10. IPCFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R

0h

Indicates to the local CPU whether the remote IPC31 event flag is
set.
0: The remote IPC31 event flag is not set
1: The remote IPC31 event flag is set
Reset type: SYSRSn

30

IPC30

R

0h

Indicates to the local CPU whether the remote IPC30 event flag is
set.
0: The remote IPC30 event flag is not set
1: The remote IPC30 event flag is set
Reset type: SYSRSn

29

IPC29

R

0h

Indicates to the local CPU whether the remote IPC29 event flag is
set.
0: The remote IPC29 event flag is not set
1: The remote IPC29 event flag is set
Reset type: SYSRSn

28

IPC28

R

0h

Indicates to the local CPU whether the remote IPC28 event flag is
set.
0: The remote IPC28 event flag is not set
1: The remote IPC28 event flag is set
Reset type: SYSRSn

27

IPC27

R

0h

Indicates to the local CPU whether the remote IPC27 event flag is
set.
0: The remote IPC27 event flag is not set
1: The remote IPC27 event flag is set
Reset type: SYSRSn

856

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-10. IPCFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

26

IPC26

R

0h

Indicates to the local CPU whether the remote IPC26 event flag is
set.
0: The remote IPC26 event flag is not set
1: The remote IPC26 event flag is set
Reset type: SYSRSn

25

IPC25

R

0h

Indicates to the local CPU whether the remote IPC25 event flag is
set.
0: The remote IPC25 event flag is not set
1: The remote IPC25 event flag is set
Reset type: SYSRSn

24

IPC24

R

0h

Indicates to the local CPU whether the remote IPC24 event flag is
set.
0: The remote IPC24 event flag is not set
1: The remote IPC24 event flag is set
Reset type: SYSRSn

23

IPC23

R

0h

Indicates to the local CPU whether the remote IPC23 event flag is
set.
0: The remote IPC23 event flag is not set
1: The remote IPC23 event flag is set
Reset type: SYSRSn

22

IPC22

R

0h

Indicates to the local CPU whether the remote IPC22 event flag is
set.
0: The remote IPC22 event flag is not set
1: The remote IPC22 event flag is set
Reset type: SYSRSn

21

IPC21

R

0h

Indicates to the local CPU whether the remote IPC21 event flag is
set.
0: The remote IPC21 event flag is not set
1: The remote IPC21 event flag is set
Reset type: SYSRSn

20

IPC20

R

0h

Indicates to the local CPU whether the remote IPC20 event flag is
set.
0: The remote IPC20 event flag is not set
1: The remote IPC20 event flag is set
Reset type: SYSRSn

19

IPC19

R

0h

Indicates to the local CPU whether the remote IPC19 event flag is
set.
0: The remote IPC19 event flag is not set
1: The remote IPC19 event flag is set
Reset type: SYSRSn

18

IPC18

R

0h

Indicates to the local CPU whether the remote IPC18 event flag is
set.
0: The remote IPC18 event flag is not set
1: The remote IPC18 event flag is set
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

857

Registers

www.ti.com

Table 6-10. IPCFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

17

IPC17

R

0h

Indicates to the local CPU whether the remote IPC17 event flag is
set.
0: The remote IPC17 event flag is not set
1: The remote IPC17 event flag is set
Reset type: SYSRSn

16

IPC16

R

0h

Indicates to the local CPU whether the remote IPC16 event flag is
set.
0: The remote IPC16 event flag is not set
1: The remote IPC16 event flag is set
Reset type: SYSRSn

15

IPC15

R

0h

Indicates to the local CPU whether the remote IPC15 event flag is
set.
0: The remote IPC15 event flag is not set
1: The remote IPC15 event flag is set
Reset type: SYSRSn

14

IPC14

R

0h

Indicates to the local CPU whether the remote IPC14 event flag is
set.
0: The remote IPC14 event flag is not set
1: The remote IPC14 event flag is set
Reset type: SYSRSn

13

IPC13

R

0h

Indicates to the local CPU whether the remote IPC13 event flag is
set.
0: The remote IPC13 event flag is not set
1: The remote IPC13 event flag is set
Reset type: SYSRSn

12

IPC12

R

0h

Indicates to the local CPU whether the remote IPC12 event flag is
set.
0: The remote IPC12 event flag is not set
1: The remote IPC12 event flag is set
Reset type: SYSRSn

11

IPC11

R

0h

Indicates to the local CPU whether the remote IPC11 event flag is
set.
0: The remote IPC11 event flag is not set
1: The remote IPC11 event flag is set
Reset type: SYSRSn

10

IPC10

R

0h

Indicates to the local CPU whether the remote IPC10 event flag is
set.
0: The remote IPC10 event flag is not set
1: The remote IPC10 event flag is set
Reset type: SYSRSn

9

IPC9

R

0h

Indicates to the local CPU whether the remote IPC9 event flag is set.
0: The remote IPC9 event flag is not set
1: The remote IPC9 event flag is set
Reset type: SYSRSn

8

IPC8

R

0h

Indicates to the local CPU whether the remote IPC8 event flag is set.
0: The remote IPC8 event flag is not set
1: The remote IPC8 event flag is set
Reset type: SYSRSn

858

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-10. IPCFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7

IPC7

R

0h

Indicates to the local CPU whether the remote IPC7 event flag is set.
0: The remote IPC7 event flag is not set
1: The remote IPC7 event flag is set
Reset type: SYSRSn

6

IPC6

R

0h

Indicates to the local CPU whether the remote IPC6 event flag is set.
0: The remote IPC6 event flag is not set
1: The remote IPC6 event flag is set
Reset type: SYSRSn

5

IPC5

R

0h

Indicates to the local CPU whether the remote IPC5 event flag is set.
0: The remote IPC5 event flag is not set
1: The remote IPC5 event flag is set
Reset type: SYSRSn

4

IPC4

R

0h

Indicates to the local CPU whether the remote IPC4 event flag is set.
0: The remote IPC4 event flag is not set
1: The remote IPC4 event flag is set
Reset type: SYSRSn

3

IPC3

R

0h

Indicates to the local CPU whether the remote IPC3 event flag is set.
0: The remote IPC3 event flag is not set
1: The remote IPC3 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

2

IPC2

R

0h

Indicates to the local CPU whether the remote IPC2 event flag is set.
0: The remote IPC2 event flag is not set
1: The remote IPC2 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

1

IPC1

R

0h

Indicates to the local CPU whether the remote IPC1 event flag is set.
0: The remote IPC1 event flag is not set
1: The remote IPC1 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

0

IPC0

R

0h

Indicates to the local CPU whether the remote IPC0 event flag is set.
0: The remote IPC0 event flag is not set
1: The remote IPC0 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

859

Registers

6.7.2.6

www.ti.com

IPCCOUNTERL Register (Offset = Ch) [reset = 0h]

IPCCOUNTERL is shown in Figure 6-25 and described in Table 6-30.
Return to Summary Table.
IPC Counter Low Register
Figure 6-8. IPCCOUNTERL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COUNT
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-11. IPCCOUNTERL Register Field Descriptions
Bit
31-0

860

Field

Type

Reset

Description

COUNT

R

0h

This is the lower 32-bits of free running 64 bit timestamp counter
clocked by the PLLSYSCLK.
Reset type: CPU1.SYSRSn

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2.7

IPCCOUNTERH Register (Offset = Eh) [reset = 0h]

IPCCOUNTERH is shown in Figure 6-26 and described in Table 6-31.
Return to Summary Table.
IPC Counter High Register
Figure 6-9. IPCCOUNTERH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COUNT
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-12. IPCCOUNTERH Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COUNT

R

0h

This is the upper 32-bits of free running 64 bit timestamp counter
clocked by the PLLSYSCLK.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

861

Registers

6.7.2.8

www.ti.com

IPCSENDCOM Register (Offset = 10h) [reset = 0h]

IPCSENDCOM is shown in Figure 6-31 and described in Table 6-36.
Return to Summary Table.
Local to Remote IPC Command Register
Figure 6-10. IPCSENDCOM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COMMAND
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-13. IPCSENDCOM Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COMMAND

R/W

0h

This is a general purpose register used to send software-defined
commands to the remote CPU. It can only be written by the local
CPU.
Notes
[1] The local CPU's IPCSENDCOM is the same physical register as
the remote CPU's IPCRECVCOM, and is located at the same
address in both CPUs.
Reset type: SYSRSn

862

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2.9

IPCSENDADDR Register (Offset = 12h) [reset = 0h]

IPCSENDADDR is shown in Figure 6-32 and described in Table 6-37.
Return to Summary Table.
Local to Remote IPC Address Register
Figure 6-11. IPCSENDADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDRESS
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-14. IPCSENDADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDRESS

R/W

0h

This is a general purpose register used to send software-defined
addresses to the remote CPU. It can only be written by the local
CPU.
Notes
[1] The local CPU's IPCSENDADDR is the same physical register as
the remote CPU's IPCRECVDATA, and is located at the same
address in both CPUs.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

863

Registers

www.ti.com

6.7.2.10 IPCSENDDATA Register (Offset = 14h) [reset = 0h]
IPCSENDDATA is shown in Figure 6-33 and described in Table 6-38.
Return to Summary Table.
Local to Remote IPC Data Register
Figure 6-12. IPCSENDDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WDATA
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-15. IPCSENDDATA Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

WDATA

R/W

0h

This is a general purpose register used to send software-defined
data to the remote CPU. It can only be written by the local CPU.
Notes
[1] The local CPU's IPCSENDDATA is the same physical register as
the remote CPU's IPCRECVDATA, and is located at the same
address in both CPUs.
Reset type: SYSRSn

864

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2.11 IPCREMOTEREPLY Register (Offset = 16h) [reset = 0h]
IPCREMOTEREPLY is shown in Figure 6-34 and described in Table 6-39.
Return to Summary Table.
Remote to Local IPC Reply Data Register
Figure 6-13. IPCREMOTEREPLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RDATA
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-16. IPCREMOTEREPLY Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RDATA

R

0h

This is a general purpose register used to receive software-defined
data from the remote CPU's response to a command. It can only be
written by the remote CPU.
Notes
[1] The local CPU's IPCREMOTEREPLY is the same physical
register as the remote CPU's IPCLOCALREPLY, and is located at
the same address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

865

Registers

www.ti.com

6.7.2.12 IPCRECVCOM Register (Offset = 18h) [reset = 0h]
IPCRECVCOM is shown in Figure 6-27 and described in Table 6-32.
Return to Summary Table.
Remote to Local IPC Command Register
Figure 6-14. IPCRECVCOM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COMMAND
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-17. IPCRECVCOM Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COMMAND

R

0h

This is a general purpose register used to receive software-defined
commands from the remote CPU. It can only be written by the
remote CPU.
Notes
[1] The local CPU's IPCRECVCOM is the same physical register as
the remote CPU's IPCSENDCOM, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

866

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2.13 IPCRECVADDR Register (Offset = 1Ah) [reset = 0h]
IPCRECVADDR is shown in Figure 6-28 and described in Table 6-33.
Return to Summary Table.
Remote to Local IPC Address Register
Figure 6-15. IPCRECVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDRESS
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-18. IPCRECVADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDRESS

R

0h

This is a general purpose register used to receive software-defined
addresses from the remote CPU. It can only be written by the remote
CPU.
Notes
[1] The local CPU's IPCRECVADDR is the same physical register as
the remote CPU's IPCSENDADDR, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

867

Registers

www.ti.com

6.7.2.14 IPCRECVDATA Register (Offset = 1Ch) [reset = 0h]
IPCRECVDATA is shown in Figure 6-29 and described in Table 6-34.
Return to Summary Table.
Remote to Local IPC Data Register
Figure 6-16. IPCRECVDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WDATA
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-19. IPCRECVDATA Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

WDATA

R

0h

This is a general purpose register used to receive software-defined
data from the remote CPU. It can only be written by the remote CPU.
Notes
[1] The local CPU's IPCRECVDATA is the same physical register as
the remote CPU's IPCSENDDATA, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

868

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2.15 IPCLOCALREPLY Register (Offset = 1Eh) [reset = 0h]
IPCLOCALREPLY is shown in Figure 6-30 and described in Table 6-35.
Return to Summary Table.
Local to Remote IPC Reply Data Register
Figure 6-17. IPCLOCALREPLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RDATA
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-20. IPCLOCALREPLY Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RDATA

R/W

0h

This is a general purpose register used to send software-defined
data to the remote CPU in response to a command. It can only be
written by the local CPU.
Notes
[1] The local CPU's IPCLOCALREPLY is the same physical register
as the remote CPU's IPCREMOTEREPLY, and is located at the
same address in both CPUs.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

869

Registers

www.ti.com

6.7.2.16 IPCBOOTSTS Register (Offset = 20h) [reset = 0h]
IPCBOOTSTS is shown in Figure 6-35 and described in Table 6-40.
Return to Summary Table.
CPU2 to CPU1 IPC Boot Status Register
Figure 6-18. IPCBOOTSTS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOOTSTS
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-21. IPCBOOTSTS Register Field Descriptions
Bit
31-0

870

Field

Type

Reset

Description

BOOTSTS

R/W

0h

This register is used by CPU2 to pass the boot Status to CPU1. The
data format is software-defined. It can only be written by CPU2.
Reset type: CPU2.SYSRSn

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.2.17 IPCBOOTMODE Register (Offset = 22h) [reset = 0h]
IPCBOOTMODE is shown in Figure 6-36 and described in Table 6-41.
Return to Summary Table.
CPU1 to CPU2 IPC Boot Mode Register
Figure 6-19. IPCBOOTMODE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOOTMODE
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-22. IPCBOOTMODE Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

BOOTMODE

R/W

0h

This register is used by CPU1 to pass a boot mode information to
CPU2. The data format is software-defined. It can only be written by
CPU1.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

871

Registers

www.ti.com

6.7.3 IPC_REGS_CPU2 Registers
Table 6-23 lists the memory-mapped registers for the IPC_REGS_CPU2. All register offset addresses not
listed in Table 6-23 should be considered as reserved locations and the register contents should not be
modified.
Table 6-23. IPC_REGS_CPU2 Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

IPCACK

IPC incoming flag clear (acknowledge) register

Go

2h

IPCSTS

IPC incoming flag status register

Go

4h

IPCSET

IPC remote flag set register

Go

6h

IPCCLR

IPC remote flag clear register

Go

8h

IPCFLG

IPC remote flag status register

Go

Ch

IPCCOUNTERL

IPC Counter Low Register

Go

Eh

IPCCOUNTERH

IPC Counter High Register

Go

10h

IPCRECVCOM

Remote to Local IPC Command Register

Go

12h

IPCRECVADDR

Remote to Local IPC Address Register

Go

14h

IPCRECVDATA

Remote to Local IPC Data Register

Go

16h

IPCLOCALREPLY

Local to Remote IPC Reply Data Register

Go

18h

IPCSENDCOM

Local to Remote IPC Command Register

Go

1Ah

IPCSENDADDR

Local to Remote IPC Address Register

Go

1Ch

IPCSENDDATA

Local to Remote IPC Data Register

Go

1Eh

IPCREMOTEREPLY

Remote to Local IPC Reply Data Register

Go

20h

IPCBOOTSTS

CPU2 to CPU1 IPC Boot Status Register

Go

22h

IPCBOOTMODE

CPU1 to CPU2 IPC Boot Mode Register

Go

Complex bit access types are encoded to fit into small table cells. Table 6-24 shows the codes that are
used for access types in this section.
Table 6-24. IPC_REGS_CPU2 Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

872

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.1

IPCACK Register (Offset = 0h) [reset = 0h]

IPCACK is shown in Figure 6-20 and described in Table 6-25.
Return to Summary Table.
IPC incoming flag clear (acknowledge) register
Figure 6-20. IPCACK Register
31
IPC31
R=0/W=1-0h

30
IPC30
R=0/W=1-0h

29
IPC29
R=0/W=1-0h

28
IPC28
R=0/W=1-0h

27
IPC27
R=0/W=1-0h

26
IPC26
R=0/W=1-0h

25
IPC25
R=0/W=1-0h

24
IPC24
R=0/W=1-0h

23
IPC23
R=0/W=1-0h

22
IPC22
R=0/W=1-0h

21
IPC21
R=0/W=1-0h

20
IPC20
R=0/W=1-0h

19
IPC19
R=0/W=1-0h

18
IPC18
R=0/W=1-0h

17
IPC17
R=0/W=1-0h

16
IPC16
R=0/W=1-0h

15
IPC15
R=0/W=1-0h

14
IPC14
R=0/W=1-0h

13
IPC13
R=0/W=1-0h

12
IPC12
R=0/W=1-0h

11
IPC11
R=0/W=1-0h

10
IPC10
R=0/W=1-0h

9
IPC9
R=0/W=1-0h

8
IPC8
R=0/W=1-0h

7
IPC7
R=0/W=1-0h

6
IPC6
R=0/W=1-0h

5
IPC5
R=0/W=1-0h

4
IPC4
R=0/W=1-0h

3
IPC3
R=0/W=1-0h

2
IPC2
R=0/W=1-0h

1
IPC1
R=0/W=1-0h

0
IPC0
R=0/W=1-0h

Table 6-25. IPCACK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R=0/W=1

0h

Writing 1 to this bit clears the IPC31 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

30

IPC30

R=0/W=1

0h

Writing 1 to this bit clears the IPC30 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

29

IPC29

R=0/W=1

0h

Writing 1 to this bit clears the IPC29 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

28

IPC28

R=0/W=1

0h

Writing 1 to this bit clears the IPC28 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

27

IPC27

R=0/W=1

0h

Writing 1 to this bit clears the IPC27 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

26

IPC26

R=0/W=1

0h

Writing 1 to this bit clears the IPC26 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

25

IPC25

R=0/W=1

0h

Writing 1 to this bit clears the IPC25 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

873

Registers

www.ti.com

Table 6-25. IPCACK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

24

IPC24

R=0/W=1

0h

Writing 1 to this bit clears the IPC24 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

23

IPC23

R=0/W=1

0h

Writing 1 to this bit clears the IPC23 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

22

IPC22

R=0/W=1

0h

Writing 1 to this bit clears the IPC22 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

21

IPC21

R=0/W=1

0h

Writing 1 to this bit clears the IPC21 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

20

IPC20

R=0/W=1

0h

Writing 1 to this bit clears the IPC20 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

19

IPC19

R=0/W=1

0h

Writing 1 to this bit clears the IPC19 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

18

IPC18

R=0/W=1

0h

Writing 1 to this bit clears the IPC18 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

17

IPC17

R=0/W=1

0h

Writing 1 to this bit clears the IPC17 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

16

IPC16

R=0/W=1

0h

Writing 1 to this bit clears the IPC16 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

15

IPC15

R=0/W=1

0h

Writing 1 to this bit clears the IPC15 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

14

IPC14

R=0/W=1

0h

Writing 1 to this bit clears the IPC14 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

13

IPC13

R=0/W=1

0h

Writing 1 to this bit clears the IPC13 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

12

IPC12

R=0/W=1

0h

Writing 1 to this bit clears the IPC12 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

874

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-25. IPCACK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

IPC11

R=0/W=1

0h

Writing 1 to this bit clears the IPC11 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

10

IPC10

R=0/W=1

0h

Writing 1 to this bit clears the IPC10 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

9

IPC9

R=0/W=1

0h

Writing 1 to this bit clears the IPC9 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

8

IPC8

R=0/W=1

0h

Writing 1 to this bit clears the IPC8 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

7

IPC7

R=0/W=1

0h

Writing 1 to this bit clears the IPC7 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

6

IPC6

R=0/W=1

0h

Writing 1 to this bit clears the IPC6 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

5

IPC5

R=0/W=1

0h

Writing 1 to this bit clears the IPC5 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

4

IPC4

R=0/W=1

0h

Writing 1 to this bit clears the IPC4 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

3

IPC3

R=0/W=1

0h

Writing 1 to this bit clears the IPC3 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

2

IPC2

R=0/W=1

0h

Writing 1 to this bit clears the IPC2 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

1

IPC1

R=0/W=1

0h

Writing 1 to this bit clears the IPC1 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

0

IPC0

R=0/W=1

0h

Writing 1 to this bit clears the IPC0 event flag which was set by the
remote CPU.
Writing 0 to this bit has no effect.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

875

Registers

6.7.3.2

www.ti.com

IPCSTS Register (Offset = 2h) [reset = 0h]

IPCSTS is shown in Figure 6-21 and described in Table 6-26.
Return to Summary Table.
IPC incoming flag status register
Figure 6-21. IPCSTS Register
31
IPC31
R-0h

30
IPC30
R-0h

29
IPC29
R-0h

28
IPC28
R-0h

27
IPC27
R-0h

26
IPC26
R-0h

25
IPC25
R-0h

24
IPC24
R-0h

23
IPC23
R-0h

22
IPC22
R-0h

21
IPC21
R-0h

20
IPC20
R-0h

19
IPC19
R-0h

18
IPC18
R-0h

17
IPC17
R-0h

16
IPC16
R-0h

15
IPC15
R-0h

14
IPC14
R-0h

13
IPC13
R-0h

12
IPC12
R-0h

11
IPC11
R-0h

10
IPC10
R-0h

9
IPC9
R-0h

8
IPC8
R-0h

7
IPC7
R-0h

6
IPC6
R-0h

5
IPC5
R-0h

4
IPC4
R-0h

3
IPC3
R-0h

2
IPC2
R-0h

1
IPC1
R-0h

0
IPC0
R-0h

Table 6-26. IPCSTS Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R

0h

Indicates to the local CPU if the IPC31 event flag was set by the
remote CPU.
0: No IPC31 event was set by the remote CPU
1: An IPC31 event was set by the remote CPU
Reset type: SYSRSn

30

IPC30

R

0h

Indicates to the local CPU if the IPC30 event flag was set by the
remote CPU.
0: No IPC30 event was set by the remote CPU
1: An IPC30 event was set by the remote CPU
Reset type: SYSRSn

29

IPC29

R

0h

Indicates to the local CPU if the IPC29 event flag was set by the
remote CPU.
0: No IPC29 event was set by the remote CPU
1: An IPC29 event was set by the remote CPU
Reset type: SYSRSn

28

IPC28

R

0h

Indicates to the local CPU if the IPC28 event flag was set by the
remote CPU.
0: No IPC28 event was set by the remote CPU
1: An IPC28 event was set by the remote CPU
Reset type: SYSRSn

27

IPC27

R

0h

Indicates to the local CPU if the IPC27 event flag was set by the
remote CPU.
0: No IPC27 event was set by the remote CPU
1: An IPC27 event was set by the remote CPU
Reset type: SYSRSn

876

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-26. IPCSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

26

IPC26

R

0h

Indicates to the local CPU if the IPC26 event flag was set by the
remote CPU.
0: No IPC26 event was set by the remote CPU
1: An IPC26 event was set by the remote CPU
Reset type: SYSRSn

25

IPC25

R

0h

Indicates to the local CPU if the IPC25 event flag was set by the
remote CPU.
0: No IPC25 event was set by the remote CPU
1: An IPC25 event was set by the remote CPU
Reset type: SYSRSn

24

IPC24

R

0h

Indicates to the local CPU if the IPC24 event flag was set by the
remote CPU.
0: No IPC24 event was set by the remote CPU
1: An IPC24 event was set by the remote CPU
Reset type: SYSRSn

23

IPC23

R

0h

Indicates to the local CPU if the IPC23 event flag was set by the
remote CPU.
0: No IPC23 event was set by the remote CPU
1: An IPC23 event was set by the remote CPU
Reset type: SYSRSn

22

IPC22

R

0h

Indicates to the local CPU if the IPC22 event flag was set by the
remote CPU.
0: No IPC22 event was set by the remote CPU
1: An IPC22 event was set by the remote CPU
Reset type: SYSRSn

21

IPC21

R

0h

Indicates to the local CPU if the IPC21 event flag was set by the
remote CPU.
0: No IPC21 event was set by the remote CPU
1: An IPC21 event was set by the remote CPU
Reset type: SYSRSn

20

IPC20

R

0h

Indicates to the local CPU if the IPC20 event flag was set by the
remote CPU.
0: No IPC20 event was set by the remote CPU
1: An IPC20 event was set by the remote CPU
Reset type: SYSRSn

19

IPC19

R

0h

Indicates to the local CPU if the IPC19 event flag was set by the
remote CPU.
0: No IPC19 event was set by the remote CPU
1: An IPC19 event was set by the remote CPU
Reset type: SYSRSn

18

IPC18

R

0h

Indicates to the local CPU if the IPC18 event flag was set by the
remote CPU.
0: No IPC18 event was set by the remote CPU
1: An IPC18 event was set by the remote CPU
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

877

Registers

www.ti.com

Table 6-26. IPCSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

17

IPC17

R

0h

Indicates to the local CPU if the IPC17 event flag was set by the
remote CPU.
0: No IPC17 event was set by the remote CPU
1: An IPC17 event was set by the remote CPU
Reset type: SYSRSn

16

IPC16

R

0h

Indicates to the local CPU if the IPC16 event flag was set by the
remote CPU.
0: No IPC16 event was set by the remote CPU
1: An IPC16 event was set by the remote CPU
Reset type: SYSRSn

15

IPC15

R

0h

Indicates to the local CPU if the IPC15 event flag was set by the
remote CPU.
0: No IPC15 event was set by the remote CPU
1: An IPC15 event was set by the remote CPU
Reset type: SYSRSn

14

IPC14

R

0h

Indicates to the local CPU if the IPC14 event flag was set by the
remote CPU.
0: No IPC14 event was set by the remote CPU
1: An IPC14 event was set by the remote CPU
Reset type: SYSRSn

13

IPC13

R

0h

Indicates to the local CPU if the IPC13 event flag was set by the
remote CPU.
0: No IPC13 event was set by the remote CPU
1: An IPC13 event was set by the remote CPU
Reset type: SYSRSn

12

IPC12

R

0h

Indicates to the local CPU if the IPC12 event flag was set by the
remote CPU.
0: No IPC12 event was set by the remote CPU
1: An IPC12 event was set by the remote CPU
Reset type: SYSRSn

11

IPC11

R

0h

Indicates to the local CPU if the IPC11 event flag was set by the
remote CPU.
0: No IPC11 event was set by the remote CPU
1: An IPC11 event was set by the remote CPU
Reset type: SYSRSn

10

IPC10

R

0h

Indicates to the local CPU if the IPC10 event flag was set by the
remote CPU.
0: No IPC10 event was set by the remote CPU
1: An IPC10 event was set by the remote CPU
Reset type: SYSRSn

9

IPC9

R

0h

Indicates to the local CPU if the IPC9 event flag was set by the
remote CPU.
0: No IPC9 event was set by the remote CPU
1: An IPC9 event was set by the remote CPU
Reset type: SYSRSn

878

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-26. IPCSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8

IPC8

R

0h

Indicates to the local CPU if the IPC8 event flag was set by the
remote CPU.
0: No IPC8 event was set by the remote CPU
1: An IPC8 event was set by the remote CPU
Reset type: SYSRSn

7

IPC7

R

0h

Indicates to the local CPU if the IPC7 event flag was set by the
remote CPU.
0: No IPC7 event was set by the remote CPU
1: An IPC7 event was set by the remote CPU
Reset type: SYSRSn

6

IPC6

R

0h

Indicates to the local CPU if the IPC6 event flag was set by the
remote CPU.
0: No IPC6 event was set by the remote CPU
1: An IPC6 event was set by the remote CPU
Reset type: SYSRSn

5

IPC5

R

0h

Indicates to the local CPU if the IPC5 event flag was set by the
remote CPU.
0: No IPC5 event was set by the remote CPU
1: An IPC5 event was set by the remote CPU
Reset type: SYSRSn

4

IPC4

R

0h

Indicates to the local CPU if the IPC4 event flag was set by the
remote CPU.
0: No IPC4 event was set by the remote CPU
1: An IPC4 event was set by the remote CPU
Reset type: SYSRSn

3

IPC3

R

0h

Indicates to the local CPU if the IPC3 event flag was set by the
remote CPU.
0: No IPC3 event was set by the remote CPU
1: An IPC3 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

2

IPC2

R

0h

Indicates to the local CPU if the IPC2 event flag was set by the
remote CPU.
0: No IPC2 event was set by the remote CPU
1: An IPC2 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

1

IPC1

R

0h

Indicates to the local CPU if the IPC1 event flag was set by the
remote CPU.
0: No IPC1 event was set by the remote CPU
1: An IPC1 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

879

Registers

www.ti.com

Table 6-26. IPCSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

IPC0

R

0h

Indicates to the local CPU if the IPC0 event flag was set by the
remote CPU.
0: No IPC0 event was set by the remote CPU
1: An IPC0 event was set by the remote CPU
Notes
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

880

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.3

IPCSET Register (Offset = 4h) [reset = 0h]

IPCSET is shown in Figure 6-22 and described in Table 6-27.
Return to Summary Table.
IPC remote flag set register
Figure 6-22. IPCSET Register
31
IPC31
R=0/W=1-0h

30
IPC30
R=0/W=1-0h

29
IPC29
R=0/W=1-0h

28
IPC28
R=0/W=1-0h

27
IPC27
R=0/W=1-0h

26
IPC26
R=0/W=1-0h

25
IPC25
R=0/W=1-0h

24
IPC24
R=0/W=1-0h

23
IPC23
R=0/W=1-0h

22
IPC22
R=0/W=1-0h

21
IPC21
R=0/W=1-0h

20
IPC20
R=0/W=1-0h

19
IPC19
R=0/W=1-0h

18
IPC18
R=0/W=1-0h

17
IPC17
R=0/W=1-0h

16
IPC16
R=0/W=1-0h

15
IPC15
R=0/W=1-0h

14
IPC14
R=0/W=1-0h

13
IPC13
R=0/W=1-0h

12
IPC12
R=0/W=1-0h

11
IPC11
R=0/W=1-0h

10
IPC10
R=0/W=1-0h

9
IPC9
R=0/W=1-0h

8
IPC8
R=0/W=1-0h

7
IPC7
R=0/W=1-0h

6
IPC6
R=0/W=1-0h

5
IPC5
R=0/W=1-0h

4
IPC4
R=0/W=1-0h

3
IPC3
R=0/W=1-0h

2
IPC2
R=0/W=1-0h

1
IPC1
R=0/W=1-0h

0
IPC0
R=0/W=1-0h

Table 6-27. IPCSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R=0/W=1

0h

Writing 1 to this bit sets the IPC31 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

30

IPC30

R=0/W=1

0h

Writing 1 to this bit sets the IPC30 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

29

IPC29

R=0/W=1

0h

Writing 1 to this bit sets the IPC29 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

28

IPC28

R=0/W=1

0h

Writing 1 to this bit sets the IPC28 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

27

IPC27

R=0/W=1

0h

Writing 1 to this bit sets the IPC27 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

26

IPC26

R=0/W=1

0h

Writing 1 to this bit sets the IPC26 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

25

IPC25

R=0/W=1

0h

Writing 1 to this bit sets the IPC25 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

24

IPC24

R=0/W=1

0h

Writing 1 to this bit sets the IPC24 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

23

IPC23

R=0/W=1

0h

Writing 1 to this bit sets the IPC23 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

881

Registers

www.ti.com

Table 6-27. IPCSET Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

22

IPC22

R=0/W=1

0h

Writing 1 to this bit sets the IPC22 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

21

IPC21

R=0/W=1

0h

Writing 1 to this bit sets the IPC21 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

20

IPC20

R=0/W=1

0h

Writing 1 to this bit sets the IPC20 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

19

IPC19

R=0/W=1

0h

Writing 1 to this bit sets the IPC19 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

18

IPC18

R=0/W=1

0h

Writing 1 to this bit sets the IPC18 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

17

IPC17

R=0/W=1

0h

Writing 1 to this bit sets the IPC17 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

16

IPC16

R=0/W=1

0h

Writing 1 to this bit sets the IPC16 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

15

IPC15

R=0/W=1

0h

Writing 1 to this bit sets the IPC15 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

14

IPC14

R=0/W=1

0h

Writing 1 to this bit sets the IPC14 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

13

IPC13

R=0/W=1

0h

Writing 1 to this bit sets the IPC13 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

12

IPC12

R=0/W=1

0h

Writing 1 to this bit sets the IPC12 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

11

IPC11

R=0/W=1

0h

Writing 1 to this bit sets the IPC11 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

10

IPC10

R=0/W=1

0h

Writing 1 to this bit sets the IPC10 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

9

IPC9

R=0/W=1

0h

Writing 1 to this bit sets the IPC9 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

8

IPC8

R=0/W=1

0h

Writing 1 to this bit sets the IPC8 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

7

IPC7

R=0/W=1

0h

Writing 1 to this bit sets the IPC7 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

882

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-27. IPCSET Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

IPC6

R=0/W=1

0h

Writing 1 to this bit sets the IPC6 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

5

IPC5

R=0/W=1

0h

Writing 1 to this bit sets the IPC5 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

4

IPC4

R=0/W=1

0h

Writing 1 to this bit sets the IPC4 event flag for the remote CPU.
Writing 0 has no effect.
Reset type: SYSRSn

3

IPC3

R=0/W=1

0h

Writing 1 to this bit sets the IPC3 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

2

IPC2

R=0/W=1

0h

Writing 1 to this bit sets the IPC2 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

1

IPC1

R=0/W=1

0h

Writing 1 to this bit sets the IPC1 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

0

IPC0

R=0/W=1

0h

Writing 1 to this bit sets the IPC0 event flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

883

Registers

6.7.3.4

www.ti.com

IPCCLR Register (Offset = 6h) [reset = 0h]

IPCCLR is shown in Figure 6-23 and described in Table 6-28.
Return to Summary Table.
IPC remote flag clear register
Figure 6-23. IPCCLR Register
31
IPC31
R=0/W=1-0h

30
IPC30
R=0/W=1-0h

29
IPC29
R=0/W=1-0h

28
IPC28
R=0/W=1-0h

27
IPC27
R=0/W=1-0h

26
IPC26
R=0/W=1-0h

25
IPC25
R=0/W=1-0h

24
IPC24
R=0/W=1-0h

23
IPC23
R=0/W=1-0h

22
IPC22
R=0/W=1-0h

21
IPC21
R=0/W=1-0h

20
IPC20
R=0/W=1-0h

19
IPC19
R=0/W=1-0h

18
IPC18
R=0/W=1-0h

17
IPC17
R=0/W=1-0h

16
IPC16
R=0/W=1-0h

15
IPC15
R=0/W=1-0h

14
IPC14
R=0/W=1-0h

13
IPC13
R=0/W=1-0h

12
IPC12
R=0/W=1-0h

11
IPC11
R=0/W=1-0h

10
IPC10
R=0/W=1-0h

9
IPC9
R=0/W=1-0h

8
IPC8
R=0/W=1-0h

7
IPC7
R=0/W=1-0h

6
IPC6
R=0/W=1-0h

5
IPC5
R=0/W=1-0h

4
IPC4
R=0/W=1-0h

3
IPC3
R=0/W=1-0h

2
IPC2
R=0/W=1-0h

1
IPC1
R=0/W=1-0h

0
IPC0
R=0/W=1-0h

Table 6-28. IPCCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R=0/W=1

0h

Writing 1 to this bit clears the IPC31 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

30

IPC30

R=0/W=1

0h

Writing 1 to this bit clears the IPC30 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

29

IPC29

R=0/W=1

0h

Writing 1 to this bit clears the IPC29 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

28

IPC28

R=0/W=1

0h

Writing 1 to this bit clears the IPC28 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

884

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-28. IPCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

IPC27

R=0/W=1

0h

Writing 1 to this bit clears the IPC27 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

26

IPC26

R=0/W=1

0h

Writing 1 to this bit clears the IPC26 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

25

IPC25

R=0/W=1

0h

Writing 1 to this bit clears the IPC25 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

24

IPC24

R=0/W=1

0h

Writing 1 to this bit clears the IPC24 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

23

IPC23

R=0/W=1

0h

Writing 1 to this bit clears the IPC23 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

22

IPC22

R=0/W=1

0h

Writing 1 to this bit clears the IPC22 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

21

IPC21

R=0/W=1

0h

Writing 1 to this bit clears the IPC21 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

885

Registers

www.ti.com

Table 6-28. IPCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

IPC20

R=0/W=1

0h

Writing 1 to this bit clears the IPC20 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

19

IPC19

R=0/W=1

0h

Writing 1 to this bit clears the IPC19 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

18

IPC18

R=0/W=1

0h

Writing 1 to this bit clears the IPC18 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

17

IPC17

R=0/W=1

0h

Writing 1 to this bit clears the IPC17 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

16

IPC16

R=0/W=1

0h

Writing 1 to this bit clears the IPC16 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

15

IPC15

R=0/W=1

0h

Writing 1 to this bit clears the IPC15 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

14

IPC14

R=0/W=1

0h

Writing 1 to this bit clears the IPC14 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

886

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-28. IPCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

IPC13

R=0/W=1

0h

Writing 1 to this bit clears the IPC13 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

12

IPC12

R=0/W=1

0h

Writing 1 to this bit clears the IPC12 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

11

IPC11

R=0/W=1

0h

Writing 1 to this bit clears the IPC11 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

10

IPC10

R=0/W=1

0h

Writing 1 to this bit clears the IPC10 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

9

IPC9

R=0/W=1

0h

Writing 1 to this bit clears the IPC9 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

8

IPC8

R=0/W=1

0h

Writing 1 to this bit clears the IPC8 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

7

IPC7

R=0/W=1

0h

Writing 1 to this bit clears the IPC7 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

887

Registers

www.ti.com

Table 6-28. IPCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

IPC6

R=0/W=1

0h

Writing 1 to this bit clears the IPC6 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

5

IPC5

R=0/W=1

0h

Writing 1 to this bit clears the IPC5 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

4

IPC4

R=0/W=1

0h

Writing 1 to this bit clears the IPC4 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

3

IPC3

R=0/W=1

0h

Writing 1 to this bit clears the IPC3 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

2

IPC2

R=0/W=1

0h

Writing 1 to this bit clears the IPC2 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

1

IPC1

R=0/W=1

0h

Writing 1 to this bit clears the IPC1 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

0

IPC0

R=0/W=1

0h

Writing 1 to this bit clears the IPC0 flag for the remote CPU.
Writing 0 has no effect.
Notes:
[1] Normally, each CPU will clear (acknowledge) only its own local
flags. This mechanism may be useful if the remote CPU is nonresponsive.
Reset type: SYSRSn

888

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.5

IPCFLG Register (Offset = 8h) [reset = 0h]

IPCFLG is shown in Figure 6-24 and described in Table 6-29.
Return to Summary Table.
IPC remote flag status register
Figure 6-24. IPCFLG Register
31
IPC31
R-0h

30
IPC30
R-0h

29
IPC29
R-0h

28
IPC28
R-0h

27
IPC27
R-0h

26
IPC26
R-0h

25
IPC25
R-0h

24
IPC24
R-0h

23
IPC23
R-0h

22
IPC22
R-0h

21
IPC21
R-0h

20
IPC20
R-0h

19
IPC19
R-0h

18
IPC18
R-0h

17
IPC17
R-0h

16
IPC16
R-0h

15
IPC15
R-0h

14
IPC14
R-0h

13
IPC13
R-0h

12
IPC12
R-0h

11
IPC11
R-0h

10
IPC10
R-0h

9
IPC9
R-0h

8
IPC8
R-0h

7
IPC7
R-0h

6
IPC6
R-0h

5
IPC5
R-0h

4
IPC4
R-0h

3
IPC3
R-0h

2
IPC2
R-0h

1
IPC1
R-0h

0
IPC0
R-0h

Table 6-29. IPCFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

31

IPC31

R

0h

Indicates to the local CPU whether the remote IPC31 event flag is
set.
0: The remote IPC31 event flag is not set
1: The remote IPC31 event flag is set
Reset type: SYSRSn

30

IPC30

R

0h

Indicates to the local CPU whether the remote IPC30 event flag is
set.
0: The remote IPC30 event flag is not set
1: The remote IPC30 event flag is set
Reset type: SYSRSn

29

IPC29

R

0h

Indicates to the local CPU whether the remote IPC29 event flag is
set.
0: The remote IPC29 event flag is not set
1: The remote IPC29 event flag is set
Reset type: SYSRSn

28

IPC28

R

0h

Indicates to the local CPU whether the remote IPC28 event flag is
set.
0: The remote IPC28 event flag is not set
1: The remote IPC28 event flag is set
Reset type: SYSRSn

27

IPC27

R

0h

Indicates to the local CPU whether the remote IPC27 event flag is
set.
0: The remote IPC27 event flag is not set
1: The remote IPC27 event flag is set
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

889

Registers

www.ti.com

Table 6-29. IPCFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

26

IPC26

R

0h

Indicates to the local CPU whether the remote IPC26 event flag is
set.
0: The remote IPC26 event flag is not set
1: The remote IPC26 event flag is set
Reset type: SYSRSn

25

IPC25

R

0h

Indicates to the local CPU whether the remote IPC25 event flag is
set.
0: The remote IPC25 event flag is not set
1: The remote IPC25 event flag is set
Reset type: SYSRSn

24

IPC24

R

0h

Indicates to the local CPU whether the remote IPC24 event flag is
set.
0: The remote IPC24 event flag is not set
1: The remote IPC24 event flag is set
Reset type: SYSRSn

23

IPC23

R

0h

Indicates to the local CPU whether the remote IPC23 event flag is
set.
0: The remote IPC23 event flag is not set
1: The remote IPC23 event flag is set
Reset type: SYSRSn

22

IPC22

R

0h

Indicates to the local CPU whether the remote IPC22 event flag is
set.
0: The remote IPC22 event flag is not set
1: The remote IPC22 event flag is set
Reset type: SYSRSn

21

IPC21

R

0h

Indicates to the local CPU whether the remote IPC21 event flag is
set.
0: The remote IPC21 event flag is not set
1: The remote IPC21 event flag is set
Reset type: SYSRSn

20

IPC20

R

0h

Indicates to the local CPU whether the remote IPC20 event flag is
set.
0: The remote IPC20 event flag is not set
1: The remote IPC20 event flag is set
Reset type: SYSRSn

19

IPC19

R

0h

Indicates to the local CPU whether the remote IPC19 event flag is
set.
0: The remote IPC19 event flag is not set
1: The remote IPC19 event flag is set
Reset type: SYSRSn

18

IPC18

R

0h

Indicates to the local CPU whether the remote IPC18 event flag is
set.
0: The remote IPC18 event flag is not set
1: The remote IPC18 event flag is set
Reset type: SYSRSn

890

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 6-29. IPCFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

17

IPC17

R

0h

Indicates to the local CPU whether the remote IPC17 event flag is
set.
0: The remote IPC17 event flag is not set
1: The remote IPC17 event flag is set
Reset type: SYSRSn

16

IPC16

R

0h

Indicates to the local CPU whether the remote IPC16 event flag is
set.
0: The remote IPC16 event flag is not set
1: The remote IPC16 event flag is set
Reset type: SYSRSn

15

IPC15

R

0h

Indicates to the local CPU whether the remote IPC15 event flag is
set.
0: The remote IPC15 event flag is not set
1: The remote IPC15 event flag is set
Reset type: SYSRSn

14

IPC14

R

0h

Indicates to the local CPU whether the remote IPC14 event flag is
set.
0: The remote IPC14 event flag is not set
1: The remote IPC14 event flag is set
Reset type: SYSRSn

13

IPC13

R

0h

Indicates to the local CPU whether the remote IPC13 event flag is
set.
0: The remote IPC13 event flag is not set
1: The remote IPC13 event flag is set
Reset type: SYSRSn

12

IPC12

R

0h

Indicates to the local CPU whether the remote IPC12 event flag is
set.
0: The remote IPC12 event flag is not set
1: The remote IPC12 event flag is set
Reset type: SYSRSn

11

IPC11

R

0h

Indicates to the local CPU whether the remote IPC11 event flag is
set.
0: The remote IPC11 event flag is not set
1: The remote IPC11 event flag is set
Reset type: SYSRSn

10

IPC10

R

0h

Indicates to the local CPU whether the remote IPC10 event flag is
set.
0: The remote IPC10 event flag is not set
1: The remote IPC10 event flag is set
Reset type: SYSRSn

9

IPC9

R

0h

Indicates to the local CPU whether the remote IPC9 event flag is set.
0: The remote IPC9 event flag is not set
1: The remote IPC9 event flag is set
Reset type: SYSRSn

8

IPC8

R

0h

Indicates to the local CPU whether the remote IPC8 event flag is set.
0: The remote IPC8 event flag is not set
1: The remote IPC8 event flag is set
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

891

Registers

www.ti.com

Table 6-29. IPCFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7

IPC7

R

0h

Indicates to the local CPU whether the remote IPC7 event flag is set.
0: The remote IPC7 event flag is not set
1: The remote IPC7 event flag is set
Reset type: SYSRSn

6

IPC6

R

0h

Indicates to the local CPU whether the remote IPC6 event flag is set.
0: The remote IPC6 event flag is not set
1: The remote IPC6 event flag is set
Reset type: SYSRSn

5

IPC5

R

0h

Indicates to the local CPU whether the remote IPC5 event flag is set.
0: The remote IPC5 event flag is not set
1: The remote IPC5 event flag is set
Reset type: SYSRSn

4

IPC4

R

0h

Indicates to the local CPU whether the remote IPC4 event flag is set.
0: The remote IPC4 event flag is not set
1: The remote IPC4 event flag is set
Reset type: SYSRSn

3

IPC3

R

0h

Indicates to the local CPU whether the remote IPC3 event flag is set.
0: The remote IPC3 event flag is not set
1: The remote IPC3 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

2

IPC2

R

0h

Indicates to the local CPU whether the remote IPC2 event flag is set.
0: The remote IPC2 event flag is not set
1: The remote IPC2 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

1

IPC1

R

0h

Indicates to the local CPU whether the remote IPC1 event flag is set.
0: The remote IPC1 event flag is not set
1: The remote IPC1 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

0

IPC0

R

0h

Indicates to the local CPU whether the remote IPC0 event flag is set.
0: The remote IPC0 event flag is not set
1: The remote IPC0 event flag is set
Notes:
[1] IPC event flags 0-3 will trigger interrupts in the receiving CPU via
the ePIE.
Reset type: SYSRSn

892

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.6

IPCCOUNTERL Register (Offset = Ch) [reset = 0h]

IPCCOUNTERL is shown in Figure 6-25 and described in Table 6-30.
Return to Summary Table.
IPC Counter Low Register
Figure 6-25. IPCCOUNTERL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COUNT
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-30. IPCCOUNTERL Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COUNT

R

0h

This is the lower 32-bits of free running 64 bit timestamp counter
clocked by the PLLSYSCLK.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

893

Registers

6.7.3.7

www.ti.com

IPCCOUNTERH Register (Offset = Eh) [reset = 0h]

IPCCOUNTERH is shown in Figure 6-26 and described in Table 6-31.
Return to Summary Table.
IPC Counter High Register
Figure 6-26. IPCCOUNTERH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COUNT
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-31. IPCCOUNTERH Register Field Descriptions
Bit
31-0

894

Field

Type

Reset

Description

COUNT

R

0h

This is the upper 32-bits of free running 64 bit timestamp counter
clocked by the PLLSYSCLK.
Reset type: CPU1.SYSRSn

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.8

IPCRECVCOM Register (Offset = 10h) [reset = 0h]

IPCRECVCOM is shown in Figure 6-27 and described in Table 6-32.
Return to Summary Table.
Remote to Local IPC Command Register
Figure 6-27. IPCRECVCOM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COMMAND
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-32. IPCRECVCOM Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COMMAND

R

0h

This is a general purpose register used to receive software-defined
commands from the remote CPU. It can only be written by the
remote CPU.
Notes
[1] The local CPU's IPCRECVCOM is the same physical register as
the remote CPU's IPCSENDCOM, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

895

Registers

6.7.3.9

www.ti.com

IPCRECVADDR Register (Offset = 12h) [reset = 0h]

IPCRECVADDR is shown in Figure 6-28 and described in Table 6-33.
Return to Summary Table.
Remote to Local IPC Address Register
Figure 6-28. IPCRECVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDRESS
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-33. IPCRECVADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDRESS

R

0h

This is a general purpose register used to receive software-defined
addresses from the remote CPU. It can only be written by the remote
CPU.
Notes
[1] The local CPU's IPCRECVADDR is the same physical register as
the remote CPU's IPCSENDADDR, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

896

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.10 IPCRECVDATA Register (Offset = 14h) [reset = 0h]
IPCRECVDATA is shown in Figure 6-29 and described in Table 6-34.
Return to Summary Table.
Remote to Local IPC Data Register
Figure 6-29. IPCRECVDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WDATA
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-34. IPCRECVDATA Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

WDATA

R

0h

This is a general purpose register used to receive software-defined
data from the remote CPU. It can only be written by the remote CPU.
Notes
[1] The local CPU's IPCRECVDATA is the same physical register as
the remote CPU's IPCSENDDATA, and is located at the same
address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

897

Registers

www.ti.com

6.7.3.11 IPCLOCALREPLY Register (Offset = 16h) [reset = 0h]
IPCLOCALREPLY is shown in Figure 6-30 and described in Table 6-35.
Return to Summary Table.
Local to Remote IPC Reply Data Register
Figure 6-30. IPCLOCALREPLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RDATA
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-35. IPCLOCALREPLY Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RDATA

R/W

0h

This is a general purpose register used to send software-defined
data to the remote CPU in response to a command. It can only be
written by the local CPU.
Notes
[1] The local CPU's IPCLOCALREPLY is the same physical register
as the remote CPU's IPCREMOTEREPLY, and is located at the
same address in both CPUs.
Reset type: SYSRSn

898

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.12 IPCSENDCOM Register (Offset = 18h) [reset = 0h]
IPCSENDCOM is shown in Figure 6-31 and described in Table 6-36.
Return to Summary Table.
Local to Remote IPC Command Register
Figure 6-31. IPCSENDCOM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COMMAND
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-36. IPCSENDCOM Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COMMAND

R/W

0h

This is a general purpose register used to send software-defined
commands to the remote CPU. It can only be written by the local
CPU.
Notes
[1] The local CPU's IPCSENDCOM is the same physical register as
the remote CPU's IPCRECVCOM, and is located at the same
address in both CPUs.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

899

Registers

www.ti.com

6.7.3.13 IPCSENDADDR Register (Offset = 1Ah) [reset = 0h]
IPCSENDADDR is shown in Figure 6-32 and described in Table 6-37.
Return to Summary Table.
Local to Remote IPC Address Register
Figure 6-32. IPCSENDADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDRESS
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-37. IPCSENDADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDRESS

R/W

0h

This is a general purpose register used to send software-defined
addresses to the remote CPU. It can only be written by the local
CPU.
Notes
[1] The local CPU's IPCSENDADDR is the same physical register as
the remote CPU's IPCRECVDATA, and is located at the same
address in both CPUs.
Reset type: SYSRSn

900

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.14 IPCSENDDATA Register (Offset = 1Ch) [reset = 0h]
IPCSENDDATA is shown in Figure 6-33 and described in Table 6-38.
Return to Summary Table.
Local to Remote IPC Data Register
Figure 6-33. IPCSENDDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WDATA
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-38. IPCSENDDATA Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

WDATA

R/W

0h

This is a general purpose register used to send software-defined
data to the remote CPU. It can only be written by the local CPU.
Notes
[1] The local CPU's IPCSENDDATA is the same physical register as
the remote CPU's IPCRECVDATA, and is located at the same
address in both CPUs.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

901

Registers

www.ti.com

6.7.3.15 IPCREMOTEREPLY Register (Offset = 1Eh) [reset = 0h]
IPCREMOTEREPLY is shown in Figure 6-34 and described in Table 6-39.
Return to Summary Table.
Remote to Local IPC Reply Data Register
Figure 6-34. IPCREMOTEREPLY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RDATA
R-0h

9

8

7

6

5

4

3

2

1

0

Table 6-39. IPCREMOTEREPLY Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RDATA

R

0h

This is a general purpose register used to receive software-defined
data from the remote CPU's response to a command. It can only be
written by the remote CPU.
Notes
[1] The local CPU's IPCREMOTEREPLY is the same physical
register as the remote CPU's IPCLOCALREPLY, and is located at
the same address in both CPUs.
[2] This register is reset by a SYRSn of the remote CPU
Reset type: CPUx.SYSRSn

902

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

6.7.3.16 IPCBOOTSTS Register (Offset = 20h) [reset = 0h]
IPCBOOTSTS is shown in Figure 6-35 and described in Table 6-40.
Return to Summary Table.
CPU2 to CPU1 IPC Boot Status Register
Figure 6-35. IPCBOOTSTS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOOTSTS
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-40. IPCBOOTSTS Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

BOOTSTS

R/W

0h

This register is used by CPU2 to pass the boot Status to CPU1. The
data format is software-defined. It can only be written by CPU2.
Reset type: CPU2.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Inter-Processor Communication (IPC)

Copyright © 2013–2017, Texas Instruments Incorporated

903

Registers

www.ti.com

6.7.3.17 IPCBOOTMODE Register (Offset = 22h) [reset = 0h]
IPCBOOTMODE is shown in Figure 6-36 and described in Table 6-41.
Return to Summary Table.
CPU1 to CPU2 IPC Boot Mode Register
Figure 6-36. IPCBOOTMODE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOOTMODE
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 6-41. IPCBOOTMODE Register Field Descriptions
Bit
31-0

904

Field

Type

Reset

Description

BOOTMODE

R/W

0h

This register is used by CPU1 to pass a boot mode information to
CPU2. The data format is software-defined. It can only be written by
CPU1.
Reset type: CPU1.SYSRSn

Inter-Processor Communication (IPC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 7
SPRUHM8G – December 2013 – Revised September 2017

General-Purpose Input/Output (GPIO)
The GPIO module controls the device's digital I/O MUX, which uses shared pins to maximize application
flexibility. The pins are named by their general-purpose I/O name (for example, GPIO0, GPIO25,
GPIO58). These pins can be individually selected to operate as digital I/O (also called GPIO mode), or
connected to one of several peripheral I/O signals. You can qualify the input signals to remove unwanted
noise.
Topic

...........................................................................................................................

7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9

GPIO Overview .................................................................................................
Configuration Overview .....................................................................................
Digital General-Purpose I/O Control ....................................................................
Input Qualification ............................................................................................
USB Signals .....................................................................................................
SPI Signals ......................................................................................................
GPIO and Peripheral Muxing ..............................................................................
Internal Pullup Configuration Requirements ........................................................
Registers .........................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

Page

906
907
907
909
912
912
914
919
921

905

GPIO Overview

7.1

www.ti.com

GPIO Overview
Up to twelve independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to
the CPU-controlled I/O capability. Each pin output can be controlled by either a peripheral or one of the
four CPU masters (CPU1, CPU1.CLA, CPU2, or CPU2.CLA). There are six I/O ports:
• Port A consists of GPIO0-GPIO31
• Port B consists of GPIO32-GPIO63
• Port C consists of GPIO64-GPIO95
• Port D consists of GPIO96-GPIO127
• Port E consists of GPIO128-GPIO159
• Port F consists of GPIO160-GPIO168
Figure 7-1 shows the GPIO logic for a single pin.
Figure 7-1. GPIO Logic for a Single Pin
CPU2.CLA
GPyDAT (R)

CPU2
GPyDAT (R)

CPU1.CLA
GPyDAT (R)

CPU1
GPyDAT (R)

Low Power
Mode Control

CPU1
GPyPUD

GPyCTRL

CPU1

Pull-Up

GPyINV

Input
XBAR

CPU1
GPyQSEL1-2

SYSCLK

Sync
3-sample
6-sample

0

GPIOx

Async

1
CPU1
GPyGMUX1-2
GPySET
GPyMUX1-2 GPyCLEAR
GPyDIR
GPyTOGGLE
GPyCSEL1-4 GPyDAT (W)

Hibernate
Isolation Latches

Direction

Data

CPU1
GPyODR

00
01
10
11

Enable and
Open Drain
Logic

00:00
00:01
00:10
00:11

Unused
Peripheral A
Peripheral B
Peripheral C

01:00
01:01
01:10
01:11

Unused
Peripheral D
Peripheral E
Peripheral F

10:xx

Peripherals G-I

11:xx

Peripherals J-L

CPU1.CLA
GPySET
GPyCLEAR
GPyTOGGLE
GPyDAT (W)

CPU2
GPySET
GPyCLEAR
GPyTOGGLE
GPyDAT (W)

CPU2.CLA
GPySET
GPyCLEAR
GPyTOGGLE
GPyDAT (W)

00
01
10
11

Data

00:00
00:01
00:10
00:11

Peripheral A
Peripheral B
Peripheral C

Direction

01:00
01:01
01:10
01:11

GPIO (same as 00:00)
Peripheral D
Peripheral E
Peripheral F

10:xx

GPIO and Peripherals G-I

11:xx

GPIO and Peripherals J-L

NOTE: High-speed SPI and AUXCLKIN use a different signal path that does not support inversion or
qualification. For more details on high-speed SPI pins, see Section 7.6.
The USB PHY pin muxing is not shown in this diagram. For more details on USB pins, see
Section 7.5.

906

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Configuration Overview

www.ti.com

There are two key features to note in this diagram. The first is that the input and output paths are entirely
separate, connecting only at the pin. The second is that peripheral muxing takes place far from the pin. As
a result, it is always possible for both CPUs and CLAs to read the physical state of the pin independent of
CPU mastering and peripheral muxing. Likewise, external interrupts can be generated from peripheral
activity. All pin options such as input qualification and open-drain output are valid for all masters and
peripherals. However, the peripheral muxing, CPU muxing, and pin options can only be configured by
CPU1.
A separate configuration is required for the USB signals. See Section 7.5 for details.

7.2

Configuration Overview
I/O pin configuration consists of several steps:
1. Plan the device pin-out
Make a list of all required peripherals for the application. Using the peripheral mux information in the
device data manual, choose which GPIOs to use for the peripheral signals. Decide which of the
remaining GPIOs to use as inputs and outputs for each CPU and CLA. Note that GPIOs 42, 43, 46,
and 47 are the only available USB pins. GPIO41 is hard-wired to be the wake-up signal in hibernate
mode.
Once the peripheral muxing has been chosen, it should be implemented by writing the appropriate
values to the GPyMUX1/2 and GPyGMUX1/2 registers. When changing the GPyGMUX value for a pin,
always set the corresponding GPyMUX bits to zero first to avoid glitching in the muxes. By default, all
pins are general-purpose I/Os, not peripheral signals.
2. (Optional) Enable internal pullup resistors
To enable or disable the pullup resistors, write to the appropriate bits in the GPIO pullup disable
registers (GPyPUD). All pullups are disabled by default. pullups can be used to keep input pins in a
known state when there is no external signal driving them.
3. Select input qualification
If the pin will be used as an input, specify the required input qualification, if any. The input qualification
sampling period is selected in the GPyCTRL registers, while the type of qualification is selected in the
GPyQSEL1 and GPyQSEL2 registers. By default, all qualification is synchronous with a sampling
period equal to PLLSYSCLK. For an explanation of input qualification, see section Section 7.4.
4. Select the direction of any general-purpose I/O pins
For each pin configured as a GPIO, specify the direction of the pin as either input or output using the
GPyDIR registers. By default, all GPIO pins are inputs. Before changing a pin to an output, load the
output latch with the value to be driven by writing that value to the GPySET, GPyCLEAR, or GPyDAT
registers. Once the latch is loaded, write to GPyDIR to change the pin direction. By default, all output
latches are zero.
5. Select low-power mode wake-up sources
GPIOs 0-63 can be used to wake the system up from Standby or Halt mode. To select one or more
GPIOs for wake-up, write to the appropriate bits in the GPIOLPMSEL0 and GPIOLPMSEL1 registers.
These registers are part of the CPU system register space. In Hibernate mode, GPIO 41 is the only
wake-up pin. For more information on low-power modes and GPIO wake-up, see the Low Power
Modes section in the System Control and Interrupts chapter.
6. Select external interrupt sources
Configuring external interrupts is a two-step process. First, the interrupts themselves must be enabled
and their polarity must be configured via the XINTnCR registers. Second, the XINT1-5 GPIO pins must
be set by selecting the sources for Input X-BAR signals 4, 5, 6, 13, and 14, respectively. For more
information on the Input X-BAR architecture, see the ePWM chapter of this manual.

7.3

Digital General-Purpose I/O Control
The values on the pins that are configured as GPIO can be changed by using these registers.
• GPyDAT Registers
Each I/O port has one data register. Each bit in the data register corresponds to one GPIO pin. No
matter how the pin is configured (GPIO or peripheral function), the corresponding bit in the data
register reflects the current state of the pin after qualification. Writing to the GPyDAT register clears or
sets the corresponding output latch and if the pin is enabled as a general purpose output (GPIO

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

907

Digital General-Purpose I/O Control

www.ti.com

output) the pin will also be driven either low or high. If the pin is not configured as a GPIO output then
the value will be latched, but the pin will not be driven. Only if the pin is later configured as a GPIO
output, will the latched value be driven onto the pin.
When using the GPyDAT register to change the level of an output pin, you should be cautious not to
accidentally change the level of another pin. For example, if you mean to change the output latch level
of GPIOA1 by writing to the GPADAT register bit 0 using a read-modify-write instruction, a problem can
occur if another I/O port A signal changes level between the read and the write stage of the instruction.
Following is an analysis of why this happens:
The GPyDAT registers reflect the state of the pin, not the latch. This means the register reflects the
actual pin value. However, there is a lag between when the register is written to when the new pin
value is reflected back in the register. This may pose a problem when this register is used in
subsequent program statements to alter the state of GPIO pins. An example is shown below where two
program statements attempt to drive two different GPIO pins that are currently low to a high state.
If Read-Modify-Write operations are used on the GPyDAT registers, because of the delay between the
output and the input of the first instruction (I1), the second instruction (I2) will read the old value and
write it back.
GpioDataRegs.GPADAT.bit.GPIO1 = 1;
GpioDataRegs.GPADAT.bit.GPIO2 = 1;

•

•

•

908

//I1 performs read-modify-write of GPADAT
//I2 also a read-modify-write of GPADAT.
//GPADAT gets the old value of GPIO1 due to the delay

The second instruction will wait for the first to finish its write due to the write-followed-by-read
protection on this peripheral frame. There will be some lag, however, between the write of (I1) and the
GPyDAT bit reflecting the new value (1) on the pin. During this lag, the second instruction will read the
old value of GPIO1 (0) and write it back along with the new value of GPIO2 (1). Therefore, GPIO1 pin
stays low.
One solution is to put some NOPs between instructions. A better solution is to use the
GPySET/GPyCLEAR/GPyTOGGLE registers instead of the GPyDAT registers. These registers always
read back a 0 and writes of 0 have no effect. Only bits that need to be changed can be specified
without disturbing any other bit(s) that are currently in the process of changing.
GPySET Registers
The set registers are used to drive specified GPIO pins high without disturbing other pins. Each I/O
port has one set register and each bit corresponds to one GPIO pin. The set registers always read
back 0. If the corresponding pin is configured as an output, then writing a 1 to that bit in the set register
will set the output latch high and the corresponding pin will be driven high. If the pin is not configured
as a GPIO output, then the value will be latched but the pin will not be driven. Only if the pin is later
configured as a GPIO output will the latched value will be driven onto the pin. Writing a 0 to any bit in
the set registers has no effect.
GPyCLEAR Registers
The clear registers are used to drive specified GPIO pins low without disturbing other pins. Each I/O
port has one clear register. The clear registers always read back 0. If the corresponding pin is
configured as a general purpose output, then writing a 1 to the corresponding bit in the clear register
will clear the output latch and the pin will be driven low. If the pin is not configured as a GPIO output,
then the value will be latched but the pin will not be driven. Only if the pin is later configured as a GPIO
output will the latched value will be driven onto the pin. Writing a 0 to any bit in the clear registers has
no effect.
GPyTOGGLE Registers
The toggle registers are used to drive specified GPIO pins to the opposite level without disturbing other
pins. Each I/O port has one toggle register. The toggle registers always read back 0. If the
corresponding pin is configured as an output, then writing a 1 to that bit in the toggle register flips the
output latch and pulls the corresponding pin in the opposite direction. That is, if the output pin is driven
low, then writing a 1 to the corresponding bit in the toggle register will pull the pin high. Likewise, if the
output pin is high, then writing a 1 to the corresponding bit in the toggle register will pull the pin low. If
the pin is not configured as a GPIO output, then the value will be latched but the pin will not be driven.
Only if the pin is later configured as a GPIO output will the latched value will be driven onto the pin.
Writing a 0 to any bit in the toggle registers has no effect.

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Input Qualification

www.ti.com

7.4

Input Qualification
The input qualification scheme has been designed to be very flexible. You can select the type of input
qualification for each GPIO pin by configuring the GPyQSEL1 and GPyQSEL2 registers. In the case of a
GPIO input pin, the qualification can be specified as only synchronize to SYSCLKOUT or qualification by a
sampling window. For pins that are configured as peripheral inputs, the input can also be asynchronous in
addition to synchronized to SYSCLKOUT or qualified by a sampling window. The remainder of this section
describes the options available.

7.4.1 No Synchronization (Asynchronous Input)
This mode is used for peripherals where input synchronization is not required or the peripheral itself
performs the synchronization. Examples include communication ports McBSP, SCI, SPI, and I2C. In
addition, it may be desirable to have the ePWM trip zone (TZn) signals function independent of the
presence of SYSCLKOUT.
The asynchronous option is not valid if the pin is used as a general purpose digital input pin (GPIO). If the
pin is configured as a GPIO input and the asynchronous option is selected then the qualification defaults
to synchronization to SYSCLKOUT as described in Section 7.4.2.
NOTE: Using input synchronization when the peripheral itself performs the synchronization may
cause unexpected results. The user should ensure that the GPIO pin is configured for
asynchronous in this case.

7.4.2 Synchronization to SYSCLKOUT Only
This is the default qualification mode of all the pins at reset. In this mode, the input signal is only
synchronized to the system clock (SYSCLKOUT). Because the incoming signal is asynchronous, it can
take up to a SYSCLKOUT period of delay in order for the input to the MCU to be changed. No further
qualification is performed on the signal.

7.4.3 Qualification Using a Sampling Window
In this mode, the signal is first synchronized to the system clock (SYSCLKOUT) and then qualified by a
specified number of cycles before the input is allowed to change. Figure 7-2 and Figure 7-3 show how the
input qualification is performed to eliminate unwanted noise. Two parameters are specified by the user for
this type of qualification: 1) the sampling period, or how often the signal is sampled, and 2) the number of
samples to be taken.
Figure 7-2. Input Qualification Using a Sampling Window
Time between samples
GPxCTRL Reg

GPIOx

SYNC

Qualification

Input Signal
Qualified By 3
or 6 Samples

GPxQSEL1/2
SYSCLKOUT
Number of Samples

Time between samples (sampling period):

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

909

Input Qualification

www.ti.com

To qualify the signal, the input signal is sampled at a regular period. The sampling period is specified by
the user and determines the time duration between samples, or how often the signal will be sampled,
relative to the CPU clock (SYSCLKOUT).
The sampling period is specified by the qualification period (QUALPRDn) bits in the GPxCTRL register.
The sampling period is configurable in groups of 8 input signals. For example, GPIO0 to GPIO7 use
GPACTRL[QUALPRD0] setting and GPIO8 to GPIO15 use GPACTRL[QUALPRD1]. Table 7-1 and
Table 7-2 show the relationship between the sampling period or sampling frequency and the
GPxCTRL[QUALPRDn] setting.
Table 7-1. Sampling Period

If GPxCTRL[QUALPRDn] = 0
If GPxCTRL[QUALPRDn] ≠ 0

Sampling Period
1 × TSYSCLKOUT
2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Table 7-2. Sampling Frequency

If GPxCTRL[QUALPRDn] = 0
If GPxCTRL[QUALPRDn] ≠ 0

Sampling Frequency
fSYSCLKOUT
fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn])
Where fSYSCLKOUT is the frequency of SYSCLKOUT

From these equations, the minimum and maximum time between samples can be calculated for a given
SYSCLKOUT frequency:
Example: Maximum Sampling Frequency:
If GPxCTRL[QUALPRDn] = 0
then the sampling frequency is fSYSCLKOUT
If, for example, fSYSCLKOUT = 60 MHz
then the signal will be sampled at 60 MHz or one sample every 16.67 ns.

Example: Minimum Sampling Frequency:
If GPxCTRL[QUALPRDn] = 0xFF (255)
then the sampling frequency is fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn])
If, for example, fSYSCLKOUT = 60 MHz
then the signal will be sampled at 60 MHz × 1 ÷ (2 × 255) or one sample every 8.5 μs.

Number of samples:
The number of times the signal is sampled is either three samples or six samples as specified in the
qualification selection (GPAQSEL1, GPAQSEL2, GPBQSEL1, and GPBQSEL2) registers. When three or
six consecutive cycles are the same, then the input change will be passed through to the MCU.
Total Sampling Window Width:
The sampling window is the time during which the input signal will be sampled as shown in Figure 7-3. By
using the equation for the sampling period along with the number of samples to be taken, the total width of
the window can be determined.
For the input qualifier to detect a change in the input, the level of the signal must be stable for the duration
of the sampling window width or longer.
The number of sampling periods within the window is always one less than the number of samples taken.
For a three-sample window, the sampling window width is two sampling periods wide where the sampling
period is defined in Table 7-1. Likewise, for a six-sample window, the sampling window width is five
sampling periods wide. Table 7-3 and Table 7-4 show the calculations that can be used to determine the
total sampling window width based on GPxCTRL[QUALPRDn] and the number of samples taken.
910

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Input Qualification

www.ti.com

Table 7-3. Case 1: Three-Sample Sampling Window Width

If GPxCTRL[QUALPRDn] = 0
If GPxCTRL[QUALPRDn] ≠ 0

Total Sampling Window Width
2 × TSYSCLKOUT
2 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Table 7-4. Case 2: Six-Sample Sampling Window Width

If GPxCTRL[QUALPRDn] = 0
If GPxCTRL[QUALPRDn] ≠ 0

Total Sampling Window Width
5 × TSYSCLKOUT
5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

NOTE: The external signal change is asynchronous with respect to both the sampling period and
SYSCLKOUT. Due to the asynchronous nature of the external signal, the input should be
held stable for a time greater than the sampling window width to make sure the logic detects
a change in the signal. The extra time required can be up to an additional sampling period +
TSYSCLKOUT.
The required duration for an input signal to be stable for the qualification logic to detect a
change is described in the device-specific data manual.

Example Qualification Window:
For the example shown in Figure 7-3, the input qualification has been configured as follows:
• GPxQSEL1/2 = 1,0. This indicates a six-sample qualification.
• GPxCTRL[QUALPRDn] = 1. The sampling period is tw(SP) = 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT .
This configuration results in the following:
• The width of the sampling window is: .
tw(IQSW) = 5 × tw(SP) = 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT or 5 × 2 × TSYSCLKOUT
• If, for example, TSYSCLKOUT = 16.67 ns, then the duration of the sampling window is:
tw(IQSW) = 5 × 2 × 16.67 ns =166.7 ns.
• To account for the asynchronous nature of the input relative to the sampling period and SYSCLKOUT,
up to an additional sampling period, tw(SP), + TSYSCLKOUT may be required to detect a change in the
input signal. For this example:
tw(SP) + TSYSCLKOUT = 333.4 ns + 166.67 ns = 500.1 ns
• In Figure 7-3, the glitch (A) is shorter then the qualification window and will be ignored by the input
qualifier.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

911

USB Signals

www.ti.com

Figure 7-3. Input Qualifier Clock Cycles
(A)

GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

1

0

0

0

0

0

0

0

1

0

0

0

1

1

1

1

1

1

1

1

1

Sampling Period determined
by GPxCTRL[QUALPRD](B)

tw(SP)
tw(IQSW)

(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))

Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)

Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value “n”, the qualification sampling period in 2n
SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words,
the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since
external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.

7.5

USB Signals
The USB module on this device has an internal physical layer transceiver (PHY). Its I/O signals are not
normal digital signals, and as a result, they do not connect to the pins through the normal GPIO mux path.
Instead, a special analog mux is used. To connect the USB signals to the device pins, set the GPyAMSEL
bits appropriately as shown in Table 7-5. Do not enable pullups or any other special pin option when using
the USB signals.
Table 7-5. USB I/O Signal Muxing

7.6

Signal

GPIO

AMSEL

USBDM

42

GPBAMSEL[10]

USBDP

43

GPBAMSEL[11]

SPI Signals
The SPI module on this device has a high-speed mode that enables 40 Mbps communication. To achieve
the highest possible speed, a special GPIO configuration is used on a single GPIO mux option for each
SPI. These GPIOs may also be used by the SPI when not in high-speed mode (HS_MODE = 0). Table 76 shows which GPIOs have the special mux option to allow SPI high-speed mode.
Table 7-6. High-Speed SPI-Enabled GPIOs

912

SPI pin

SPIA

SPIB

SPIC

SPISIMO

GPIO58

GPIO63

GPIO69

SPISOMI

GPIO59

GPIO64

GPIO70

SPICLK

GPIO60

GPIO65

GPIO71

SPISTE

GPIO61

GPIO66

GPIO72

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

SPI Signals

www.ti.com

To select these mux options the user should configure GPyGMUX and GPyMUX registers as shown in
Table 7-7.
Table 7-7. GPIO Configuration for High-Speed SPI
GPIO

SPI Signal

GPIO58

SPISIMOA

GPBGMUX2[21:20]=11

GPBMUX2[21:20]=11

GPIO59

SPISOMIA

GPBGMUX2[23:22]=11

GPBMUX2[23:22]=11

GPIO60

SPICLKA

GPBGMUX2[25:24]=11

GPBMUX2[25:24]=11

GPIO61

SPISTEA

GPBGMUX2[27:26]=11

GPBMUX2[27:26]=11

GPIO63

SPISIMOB

GPBGMUX2[31:30]=11

GPBMUX2[31:30]=11

GPIO64

SPISOMIB

GPCGMUX1[1:0]=11

GPCMUX1[1:0]=11

GPIO65

SPICLKB

GPCGMUX1[3:2]=11

GPCMUX1[3:2]=11

GPIO66

SPISTEB

GPCGMUX1[5:4]=11

GPCMUX1[5:4]=11

GPIO69

SPISIMOC

GPCGMUX1[11:10]=11

GPCMUX1[11:10]=11

GPIO70

SPISOMIC

GPCGMUX1[13:12]=11

GPCMUX1[13:12]=11

GPIO71

SPICLKC

GPCGMUX1[15:14]=11

GPCMUX1[15:14]=11

GPIO72

SPISTEC

GPCGMUX1[17:16]=11

GPCMUX1[17:16]=11

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Mux Configuration

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

913

GPIO and Peripheral Muxing

7.7

www.ti.com

GPIO and Peripheral Muxing
Up to twelve different peripheral functions are multiplexed to each pin along with a general-purpose
input/output (GPIO) function. This allows you to choose the peripheral mix and pinout that will work best
for your particular application. Refer to the table below for muxing combinations and definitions.
Table 7-8. GPIO Muxed Pins (1) (2)
GPIO Mux Selection
GPIO Index

0, 4, 8, 12

GPyGMUXn.
GPIOz =

00b, 01b,
10b, 11b

GPyMUXn.
GPIOz =

00b

(2)

2

3

5

00b
01b
EPWM1A (O)

GPIO1

EPWM1B (O)

6

7

01b

10b

GPIO0

11b

01b

10b

15
11b

11b

11b

SDAA (I/OD)
MFSRB (I/O)

SCLA (I/OD)
OUTPUTXBAR1
(O)

SDAB (I/OD)

OUTPUTXBAR2
(O)

SCLB (I/OD)

OUTPUTXBAR3
(O)

CANTXA (O)

GPIO2

EPWM2A (O)

GPIO3

EPWM2B (O)

GPIO4

EPWM3A (O)

GPIO5

EPWM3B (O)

MFSRA (I/O)

OUTPUTXBAR3
(O)

GPIO6

EPWM4A (O)

OUTPUTXBAR4
(O)

EXTSYNCOUT
(O)

GPIO7

EPWM4B (O)

MCLKRA (I/O)

OUTPUTXBAR5
(O)

EQEP3B (I)

CANRXB (I)

GPIO8

EPWM5A (O)

CANTXB (O)

ADCSOCAO (O)

EQEP3S (I/O)

SCITXDA (O)

GPIO9

EPWM5B (O)

SCITXDB (O)

OUTPUTXBAR6
(O)

EQEP3I (I/O)

SCIRXDA (I)

GPIO10

EPWM6A (O)

CANRXB (I)

ADCSOCBO (O)

EQEP1A (I)

SCITXDB (O)

UPP-WAIT (I/O)

GPIO11

EPWM6B (O)

SCIRXDB (I)

OUTPUTXBAR7
(O)

EQEP1B (I)

SCIRXDB (I)

UPP-START (I/O)

GPIO12

EPWM7A (O)

CANTXB (O)

MDXB (O)

EQEP1S (I/O)

SCITXDC (O)

UPP-ENA (I/O)

GPIO13

EPWM7B (O)

CANRXB (I)

MDRB (I)

EQEP1I (I/O)

SCIRXDC (I)

UPP-D7 (I/O)

GPIO14

EPWM8A (O)

SCITXDB (O)

MCLKXB (I/O)

OUTPUTXBAR3
(O)

UPP-D6 (I/O)

GPIO15

EPWM8B (O)

SCIRXDB (I)

MFSXB (I/O)

OUTPUTXBAR4
(O)

UPP-D5 (I/O)

GPIO16

SPISIMOA (I/O)

CANTXB (O)

OUTPUTXBAR7
(O)

EPWM9A (O)

SD1_D1 (I)

UPP-D4 (I/O)

OUTPUTXBAR8
(O)

EPWM9B (O)

SD1_C1 (I)

UPP-D3 (I/O)

OUTPUTXBAR2
(O)

MCLKRB (I/O)

CANRXA (I)
EQEP3A (I)

CANTXB (O)

GPIO17

SPISOMIA (I/O)

CANRXB (I)

GPIO18

SPICLKA (I/O)

SCITXDB (O)

CANRXA (I)

EPWM10A (O)

SD1_D2 (I)

UPP-D2 (I/O)

GPIO19

SPISTEA (I/O)

SCIRXDB (I)

CANTXA (O)

EPWM10B (O)

SD1_C2 (I)

UPP-D1 (I/O)

GPIO20

EQEP1A (I)

MDXA (O)

CANTXB (O)

EPWM11A (O)

SD1_D3 (I)

UPP-D0 (I/O)

GPIO21

EQEP1B (I)

MDRA (I)

CANRXB (I)

EPWM11B (O)

SD1_C3 (I)

UPP-CLK (I/O)

GPIO22

EQEP1S (I/O)

MCLKXA (I/O)

SCITXDB (O)

EPWM12A (O)

SPICLKB (I/O)

SD1_D4 (I)

GPIO23

EQEP1I (I/O)

MFSXA (I/O)

SCIRXDB (I)

EPWM12B (O)

SPISTEB (I/O)

SD1_C4 (I)

GPIO24

OUTPUTXBAR1
(O)

EQEP2A (I)

MDXB (O)

SPISIMOB (I/O)

SD2_D1 (I)

GPIO25

OUTPUTXBAR2
(O)

EQEP2B (I)

MDRB (I)

SPISOMIB (I/O)

SD2_C1 (I)

GPIO26

OUTPUTXBAR3
(O)

EQEP2I (I/O)

MCLKXB (I/O)

OUTPUTXBAR3
(O)

SPICLKB (I/O)

SD2_D2 (I)

GPIO27

OUTPUTXBAR4
(O)

EQEP2S (I/O)

MFSXB (I/O)

OUTPUTXBAR4
(O)

SPISTEB (I/O)

SD2_C2 (I)

GPIO28

SCIRXDA (I)

EM1CS4 (O)

OUTPUTXBAR5
(O)

EQEP3A (I)

SD2_D3 (I)

EQEP3B (I)

SD2_C3 (I)

GPIO29

SCITXDA (O)

EM1SDCKE (O)

OUTPUTXBAR6
(O)

GPIO30

CANRXA (I)

EM1CLK (O)

OUTPUTXBAR7
(O)

EQEP3S (I/O)

SD2_D4 (I)

EM1WE (O)

OUTPUTXBAR8
(O)

EQEP3I (I/O)

SD2_C4 (I)

GPIO31

(1)

1

CANTXA (O)

I = Input, O = Output, OD = Open Drain
GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.

914 General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

GPIO and Peripheral Muxing

www.ti.com

Table 7-8. GPIO Muxed Pins (1) (2) (continued)
GPIO Mux Selection
GPIO Index

0, 4, 8, 12

GPyGMUXn.
GPIOz =

00b, 01b,
10b, 11b

GPyMUXn.
GPIOz =

00b

2

3

5

00b

6

7

01b

01b

10b

SDAA (I/OD)

EM1CS0 (O)

GPIO33

SCLA (I/OD)

EM1RNW (O)

GPIO34

OUTPUTXBAR1
(O)

EM1CS2 (O)

SDAB (I/OD)

GPIO35

SCIRXDA (I)

EM1CS3 (O)

SCLB (I/OD)

GPIO36

SCITXDA (O)

EM1WAIT (I)

CANRXA (I)

GPIO37

OUTPUTXBAR2
(O)

EM1OE (O)

CANTXA (O)

GPIO32

(3)

1

11b

01b

GPIO38

EM1A0 (O)

SCITXDC (O)

GPIO39

EM1A1 (O)

SCIRXDC (I)

GPIO40

EM1A2 (O)

GPIO41

EM1A3 (O)

10b

15
11b

11b

11b

CANTXB (O)
CANRXB (I)
SDAB (I/OD)
SCLB (I/OD)

GPIO42

SDAA (I/OD)

SCITXDA (O)

GPIO43

SCLA (I/OD)

SCIRXDA (I)

GPIO44

EM1A4 (O)

GPIO45

EM1A5 (O)

GPIO46

EM1A6 (O)

SCIRXDD (I)

GPIO47

EM1A7 (O)

SCITXDD (O)

GPIO48

OUTPUTXBAR3
(O)

EM1A8 (O)

SCITXDA (O)

SD1_D1 (I)

GPIO49

OUTPUTXBAR4
(O)

EM1A9 (O)

SCIRXDA (I)

SD1_C1 (I)

GPIO50

EQEP1A (I)

EM1A10 (O)

SPISIMOC (I/O)

SD1_D2 (I)

GPIO51

EQEP1B (I)

EM1A11 (O)

SPISOMIC (I/O)

SD1_C2 (I)

GPIO52

EQEP1S (I/O)

EM1A12 (O)

SPICLKC (I/O)

SD1_D3 (I)

GPIO53

EQEP1I (I/O)

EM1D31 (I/O)

EM2D15 (I/O)

SPISTEC (I/O)

SD1_C3 (I)

GPIO54

SPISIMOA (I/O)

EM1D30 (I/O)

EM2D14 (I/O)

EQEP2A (I)

SCITXDB (O)

SD1_D4 (I)

GPIO55

SPISOMIA (I/O)

EM1D29 (I/O)

EM2D13 (I/O)

EQEP2B (I)

SCIRXDB (I)

SD1_C4 (I)

GPIO56

SPICLKA (I/O)

EM1D28 (I/O)

EM2D12 (I/O)

EQEP2S (I/O)

SCITXDC (O)

SD2_D1 (I)

GPIO57

SPISTEA (I/O)

EM1D27 (I/O)

EM2D11 (I/O)

EQEP2I (I/O)

SCIRXDC (I)

SD2_C1 (I)

SPICLKB (I/O)

SD2_D2 (I)

SPISIMOA (3) (I/O)

GPIO58

MCLKRA (I/O)

EM1D26 (I/O)

EM2D10 (I/O)

OUTPUTXBAR1
(O)

GPIO59

MFSRA (I/O)

EM1D25 (I/O)

EM2D9 (I/O)

OUTPUTXBAR2
(O)

SPISTEB (I/O)

SD2_C2 (I)

SPISOMIA (3) (I/O)

GPIO60

MCLKRB (I/O)

EM1D24 (I/O)

EM2D8 (I/O)

OUTPUTXBAR3
(O)

SPISIMOB (I/O)

SD2_D3 (I)

SPICLKA (3) (I/O)

GPIO61

MFSRB (I/O)

EM1D23 (I/O)

EM2D7 (I/O)

OUTPUTXBAR4
(O)

SPISOMIB (I/O)

SD2_C3 (I)

SPISTEA (3) (I/O)

GPIO62

SCIRXDC (I)

EM1D22 (I/O)

EM2D6 (I/O)

EQEP3A (I)

CANRXA (I)

SD2_D4 (I)

GPIO63

SCITXDC (O)

EM1D21 (I/O)

EM2D5 (I/O)

EQEP3B (I)

CANTXA (O)

SD2_C4 (I)

GPIO64

EM1D20 (I/O)

EM2D4 (I/O)

EQEP3S (I/O)

SCIRXDA (I)

SPISOMIB (3) (I/O)

GPIO65

EM1D19 (I/O)

EM2D3 (I/O)

EQEP3I (I/O)

SCITXDA (O)

SPICLKB (3) (I/O)

GPIO66

EM1D18 (I/O)

EM2D2 (I/O)

SDAB (I/OD)

SPISTEB (3) (I/O)

GPIO67

EM1D17 (I/O)

EM2D1 (I/O)

GPIO68

EM1D16 (I/O)

EM2D0 (I/O)

GPIO69

EM1D15 (I/O)

SCLB (I/OD)

SPISIMOC (3) (I/O)

GPIO70

EM1D14 (I/O)

CANRXA (I)

SCITXDB (O)

SPISOMIC (3) (I/O)

GPIO71

EM1D13 (I/O)

CANTXA (O)

SCIRXDB (I)

SPICLKC (3) (I/O)

GPIO72

EM1D12 (I/O)

CANTXB (O)

SCITXDC (O)

SPISTEC (3) (I/O)

GPIO73

EM1D11 (I/O)

CANRXB (I)

SCIRXDC (I)

GPIO74

EM1D10 (I/O)

GPIO75

EM1D9 (I/O)

XCLKOUT (O)

SPISIMOB (3) (I/O)

High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode
(HS_MODE = 1 in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in
SPICCR).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

General-Purpose Input/Output (GPIO) 915

GPIO and Peripheral Muxing

www.ti.com

Table 7-8. GPIO Muxed Pins (1) (2) (continued)
GPIO Mux Selection
GPIO Index

0, 4, 8, 12

GPyGMUXn.
GPIOz =

00b, 01b,
10b, 11b

GPyMUXn.
GPIOz =

00b

1

2

3

5

00b
01b

10b

6

7

01b
11b

01b

10b

GPIO76

EM1D8 (I/O)

SCITXDD (O)

GPIO77

EM1D7 (I/O)

SCIRXDD (I)

GPIO78

EM1D6 (I/O)

EQEP2A (I)

GPIO79

EM1D5 (I/O)

EQEP2B (I)

GPIO80

EM1D4 (I/O)

EQEP2S (I/O)

GPIO81

EM1D3 (I/O)

EQEP2I (I/O)

GPIO82

EM1D2 (I/O)

GPIO83

EM1D1 (I/O)

GPIO84

15
11b

11b

11b

SCITXDA (O)

MDXB (O)

SCIRXDA (I)

MDRB (I)

MDRA (I)

EM1CAS (O)

SCITXDB (O)

MCLKXB (I/O)

MCLKXA (I/O)

EM1A14 (O)

EM1RAS (O)

SCIRXDB (I)

MFSXB (I/O)

MFSXA (I/O)

EM1A15 (O)

EM1DQM0 (O)

GPIO89

EM1A16 (O)

EM1DQM1 (O)

SCITXDC (O)

GPIO90

EM1A17 (O)

EM1DQM2 (O)

SCIRXDC (I)

GPIO91

EM1A18 (O)

EM1DQM3 (O)

SDAA (I/OD)

GPIO92

EM1A19 (O)

EM1BA1 (O)

SCLA (I/OD)

EM1BA0 (O)

SCITXDD (O)

GPIO85

EM1D0 (I/O)

GPIO86

EM1A13 (O)

GPIO87
GPIO88

GPIO93
GPIO94

MDXA (O)

SCIRXDD (I)

GPIO95
GPIO96

EM2DQM1 (O)

GPIO97

EM2DQM0 (O)

EQEP1A (I)
EQEP1B (I)

GPIO98

EM2A0 (O)

EQEP1S (I/O)

GPIO99

EM2A1 (O)

EQEP1I (I/O)

GPIO100

EM2A2 (O)

EQEP2A (I)

SPISIMOC (I/O)

GPIO101

EM2A3 (O)

EQEP2B (I)

SPISOMIC (I/O)

GPIO102

EM2A4 (O)

EQEP2S (I/O)

SPICLKC (I/O)

GPIO103

EM2A5 (O)

EQEP2I (I/O)

SPISTEC (I/O)
SCITXDD (O)

GPIO104

SDAA (I/OD)

EM2A6 (O)

EQEP3A (I)

GPIO105

SCLA (I/OD)

EM2A7 (O)

EQEP3B (I)

SCIRXDD (I)

EM2A8 (O)

EQEP3S (I/O)

SCITXDC (O)

GPIO107

EM2A9 (O)

EQEP3I (I/O)

SCIRXDC (I)

GPIO108

EM2A10 (O)

GPIO106

GPIO109

EM2A11 (O)

GPIO110

EM2WAIT (I)

GPIO111

EM2BA0 (O)

GPIO112

EM2BA1 (O)

GPIO113

EM2CAS (O)

GPIO114

EM2RAS (O)

GPIO115

EM2CS0 (O)

GPIO116

EM2CS2 (O)

GPIO117

EM2SDCKE (O)

GPIO118

EM2CLK (O)

GPIO119

EM2RNW (O)

GPIO120

EM2WE (O)

USB0PFLT

GPIO121

EM2OE (O)

USB0EPEN

GPIO122

SPISIMOC (I/O)

SD1_D1 (I)

GPIO123

SPISOMIC (I/O)

SD1_C1 (I)

GPIO124

SPICLKC (I/O)

SD1_D2 (I)

GPIO125

SPISTEC (I/O)

SD1_C2 (I)

GPIO126

SD1_D3 (I)

GPIO127

SD1_C3 (I)

916 General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

GPIO and Peripheral Muxing

www.ti.com

Table 7-8. GPIO Muxed Pins (1) (2) (continued)
GPIO Mux Selection
GPIO Index

0, 4, 8, 12

GPyGMUXn.
GPIOz =

00b, 01b,
10b, 11b

GPyMUXn.
GPIOz =

00b

1

2

3

5

6

00b
01b

10b

7

15

01b
11b

01b

10b

11b
11b

11b

GPIO128

SD1_D4 (I)

GPIO129

SD1_C4 (I)

GPIO130

SD2_D1 (I)

GPIO131

SD2_C1 (I)

GPIO132

SD2_D2 (I)

GPIO133/
AUXCLKIN

SD2_C2 (I)

GPIO134

SD2_D3 (I)

GPIO135

SCITXDA (O)

SD2_C3 (I)

GPIO136

SCIRXDA (I)

SD2_D4 (I)

GPIO137

SCITXDB (O)

SD2_C4 (I)

GPIO138

SCIRXDB (I)

GPIO139

SCIRXDC (I)

GPIO140

SCITXDC (O)

GPIO141

SCIRXDD (I)

GPIO142

SCITXDD (O)

GPIO143
GPIO144
GPIO145

EPWM1A (O)

GPIO146

EPWM1B (O)

GPIO147

EPWM2A (O)

GPIO148

EPWM2B (O)

GPIO149

EPWM3A (O)

GPIO150

EPWM3B (O)

GPIO151

EPWM4A (O)

GPIO152

EPWM4B (O)

GPIO153

EPWM5A (O)

GPIO154

EPWM5B (O)

GPIO155

EPWM6A (O)

GPIO156

EPWM6B (O)

GPIO157

EPWM7A (O)

GPIO158

EPWM7B (O)

GPIO159

EPWM8A (O)

GPIO160

EPWM8B (O)

GPIO161

EPWM9A (O)

GPIO162

EPWM9B (O)

GPIO163

EPWM10A (O)

GPIO164

EPWM10B (O)

GPIO165

EPWM11A (O)

GPIO166

EPWM11B (O)

GPIO167

EPWM12A (O)

GPIO168

EPWM12B (O)

For example, the multiplexing for the GPIO 6 pin is controlled by writing toGPAGMUX[13:12] and
GPAMUX[13:12]. By writing to these bits, GPIO 6 can be configured as either ageneral-purpose digital I/O
or one of four different peripheral functions. The options are shown inTable 7-9.
Table 7-9. GPIO and Peripheral Muxing
GPAGMUX1[13:12]

GPAMUX1[13:12]

Pin functionality

00

00

GPIO

00

01

EPWM4A

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

General-Purpose Input/Output (GPIO) 917

GPIO and Peripheral Muxing

www.ti.com

Table 7-9. GPIO and Peripheral Muxing (continued)
GPAGMUX1[13:12]

GPAMUX1[13:12]

Pin functionality

00

10

OUTPUTXBAR4

00

11

EXTSYNCOUT

01

00

GPIO

01

01

EQEP3A

01

10

CANTXB

10

00

GPIO

11

00

GPIO

All others

Reserved

The devices have different multiplexing schemes. If a peripheral is not available on a particular device,
that mux selection is reserved on that device and should not be used.
Note: If you select a reserved GPIO mux configuration that is not mapped to either a peripheral or GPIO
mode, the state of the pin will be undefined and the pin may be driven. Unimplemented configurations are
for future expansion and must not be selected. In the device mux table (see datasheet), these options are
indicated as Reserved or left blank.

918

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Internal Pullup Configuration Requirements

www.ti.com

Some peripherals can be assigned to more than one pin via the mux registers. For example,
OUTPUTXBAR1 can be assigned to GPIOs 2, 24, 34, or 58, depending on individual system
requirements. An example of this is shown in Table 7-10.
Table 7-10. Peripheral Muxing (multiple pins assigned)
GMUX Configuration

MUX Configuration

Choice 1 GPIO2

GPAGMUX1[5:4]=01

GPAMUX1[5:4]=01

or Choice 2 GPIO24

GPAGMUX2[17:16]=00

GPAMUX2[17:16]=01

or Choice 3 GPIO34

GPBGMUX1[5:4]=00

GPBMUX1[5:4]=01

or Choice 4 GPIO58

GPBGMUX2[21:20]=01

GPBMUX2[21:20]=01

If no pin is configured as an input to a peripheral, or if more than one pin is configured to an input for the
same peripheral, then that input will be set to a hard-wired default value.

7.8

Internal Pullup Configuration Requirements
On reset, GPIOs are in input mode and have the internal pullups disabled. An un-driven input can float to
a mid-rail voltage and cause wasted shoot-through current on the input buffer. The user should always put
each GPIO in one of these configurations:
• Input mode and driven on the board by another component to a level above Vih or below Vil
• Input mode with GPIO internal pullup enabled
• Output mode
On devices in the 176PTP or 100PZP packages, the pullups for any internally unbonded GPIO must be
enabled to prevent floating inputs. TI has provided functions in controlSUITE which users can call to
enable the pullup on any unbonded GPIO for the package they are using. This function,
GPIO_EnabledUnbondedIOPullups(), resides in the (Device)_Sysctrl.c file and is called by default from
InitSysCtrl(). The user should take care to avoid disabling these pullups in their application code.
For 176-pin packages, pullup resistors should be enabled on the following GPIOs:
Table 7-11. Pullup Resistors for 176-pin Packages
Unbonded GPIOs on the 176-pin package
95

106

116

126

137

147

157

167

96

107

117

127

138

148

158

168

97

108

118

128

139

149

159

98

109

119

129

140

150

160

100

110

120

130

141

151

161

101

111

121

131

142

152

162

102

112

122

132

143

153

163

103

113

123

134

144

154

164

104

114

124

135

145

155

165

105

115

125

136

146

156

166

For 100-pin packages, pullup resistors should be enabled on the following GPIOs:

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

General-Purpose Input/Output (GPIO) 919

Internal Pullup Configuration Requirements

www.ti.com

Table 7-12. Pullup Resistors for 100-pin Packages
Unbonded GPIOs on the 100-pin package
0

30

48

77

101

116

131

146

161

1

31

49

79

102

117

132

147

162

5

32

50

80

103

118

133

148

163

6

33

51

81

104

119

134

149

164

7

34

52

82

105

120

135

150

165

8

35

53

83

106

121

136

151

166

9

36

54

88

107

122

137

152

167

22

37

55

93

108

123

138

153

168

23

38

56

94

109

124

139

154

24

39

57

95

110

125

140

155

25

40

67

96

111

126

141

156

26

44

68

97

112

127

142

157

27

45

74

98

113

128

143

158

28

46

75

100

114

129

144

159

29

47

76

101

115

130

145

160

920

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9

Registers

7.9.1 GPIO Base Addresses
Table 7-13. GPIO Base Address Table
Start Address

End Address

GpioCtrlRegs (1)

Device Registers

GPIO_CTRL_REGS

0x0000_7C00

0x0000_7D7F

GpioDataRegs

GPIO_DATA_REGS

0x0000_7F00

0x0000_7F2F

(1)

Register Name

Only available on CPU1.

The following table provides both specific and generic germs for registers described in this section and
throughout this document.
Table 7-14. Specific vs Generic Termilogy for Registers
Specific Term

Generic Term Used in the Document

GPAQSEL1, GPAQSEL2, GPBQSEL1, GPBQSEL2,
GPCQSEL1, GPCQSEL2, GPDQSEL1, GPDQSEL2,
GPEQSEL1, GPEQSEL2, GPFQSEL1, GPFQSEL2

GPxQSEL

GPACTRL, GPBCTRL, GPCCTRL, GPDCTRL, GPECTRL,
GPFCTRL

GPxCTRL

GPADIR, GPBDIR, GPCDIR, GPDDIR, GPEDIR, GPFDIR

GPxDIR

GPAPUD, GPBPUD, GPCPUD, GPDPUD, GPEPUD, GPFPUD

GPxPUD

GPAINV, GPBINV, GPCINV, GPDINV, GPEINV, GPFINV

GPxINV

GPAODR, GPBODR, GPCODR, GPDODR, GPEODR,
GPFODR GPxODR GPALOCK, GPBLOCK, GPCLOCK,
GPDLOCK, GPELOCK, GPFLOCK

GPxODR
GPxLOCK

GPACR, GPBCR, GPCCR, GPDCR, GPECR, GPFCR

GPxCR

GPAMUX1, GPAMUX2, GPBMUX1, GPBMUX2, GPCMUX1,
GPCMUX2, GPDMUX1, GPDMUX2, GPEMUX1, GPEMUX2,
GPFMUX1, GPFMUX2

GPxMUX

GPAGMUX1, GPAGMUX2, GPBGMUX1, GPBGMUX2,
GPCGMUX1, GPCGMUX2, GPDGMUX1, GPDGMUX2,
GPEGMUX1, GPEGMUX2, GPFGMUX1, GPFGMUX2

GPxGMUX

GPADAT, GPBDAT, GPCDAT, GPDDAT, GPEDAT, GPFDAT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

GPxDAT

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

921

Registers

www.ti.com

7.9.2 GPIO_CTRL_REGS Registers
Table 7-15 lists the memory-mapped registers for the GPIO_CTRL_REGS. All register offset addresses
not listed in Table 7-15 should be considered as reserved locations and the register contents should not
be modified.
Table 7-15. GPIO_CTRL_REGS Registers
Offset

Acronym

Register Name

Write Protection

0h

GPACTRL

GPIO A Qualification Sampling Period Control
(GPIO0 to 31)

EALLOW

Go

2h

GPAQSEL1

GPIO A Qualifier Select 1 Register (GPIO0 to
15)

EALLOW

Go

4h

GPAQSEL2

GPIO A Qualifier Select 2 Register (GPIO16 to
31)

EALLOW

Go

6h

GPAMUX1

GPIO A Mux 1 Register (GPIO0 to 15)

EALLOW

Go

922

Section

8h

GPAMUX2

GPIO A Mux 2 Register (GPIO16 to 31)

EALLOW

Go

Ah

GPADIR

GPIO A Direction Register (GPIO0 to 31)

EALLOW

Go

Ch

GPAPUD

GPIO A Pull Up Disable Register (GPIO0 to 31)

EALLOW

Go

10h

GPAINV

GPIO A Input Polarity Invert Registers (GPIO0 to EALLOW
31)

Go

12h

GPAODR

GPIO A Open Drain Output Register (GPIO0 to
GPIO31)

EALLOW

Go

20h

GPAGMUX1

GPIO A Peripheral Group Mux (GPIO0 to 15)

EALLOW

Go

22h

GPAGMUX2

GPIO A Peripheral Group Mux (GPIO16 to 31)

EALLOW

Go

28h

GPACSEL1

GPIO A Core Select Register (GPIO0 to 7)

EALLOW

Go

2Ah

GPACSEL2

GPIO A Core Select Register (GPIO8 to 15)

EALLOW

Go

2Ch

GPACSEL3

GPIO A Core Select Register (GPIO16 to 23)

EALLOW

Go

2Eh

GPACSEL4

GPIO A Core Select Register (GPIO24 to 31)

EALLOW

Go

3Ch

GPALOCK

GPIO A Lock Configuration Register (GPIO0 to
31)

EALLOW

Go

3Eh

GPACR

GPIO A Lock Commit Register (GPIO0 to 31)

EALLOW

Go

40h

GPBCTRL

GPIO B Qualification Sampling Period Control
(GPIO32 to 63)

EALLOW

Go

42h

GPBQSEL1

GPIO B Qualifier Select 1 Register (GPIO32 to
47)

EALLOW

Go

44h

GPBQSEL2

GPIO B Qualifier Select 2 Register (GPIO48 to
63)

EALLOW

Go

46h

GPBMUX1

GPIO B Mux 1 Register (GPIO32 to 47)

EALLOW

Go

48h

GPBMUX2

GPIO B Mux 2 Register (GPIO48 to 63)

EALLOW

Go

4Ah

GPBDIR

GPIO B Direction Register (GPIO32 to 63)

EALLOW

Go

4Ch

GPBPUD

GPIO B Pull Up Disable Register (GPIO32 to 63) EALLOW

Go

50h

GPBINV

GPIO B Input Polarity Invert Registers (GPIO32
to 63)

EALLOW

Go

52h

GPBODR

GPIO B Open Drain Output Register (GPIO32 to
GPIO63)

EALLOW

Go

54h

GPBAMSEL

GPIO B Analog Mode Select register (GPIO32 to EALLOW
GPIO63)

Go

60h

GPBGMUX1

GPIO B Peripheral Group Mux (GPIO32 to 47)

EALLOW

Go

62h

GPBGMUX2

GPIO B Peripheral Group Mux (GPIO48 to 63)

EALLOW

Go

68h

GPBCSEL1

GPIO B Core Select Register (GPIO32 to 39)

EALLOW

Go

6Ah

GPBCSEL2

GPIO B Core Select Register (GPIO40 to 47)

EALLOW

Go

6Ch

GPBCSEL3

GPIO B Core Select Register (GPIO48 to 55)

EALLOW

Go

6Eh

GPBCSEL4

GPIO B Core Select Register (GPIO56 to 63)

EALLOW

Go

7Ch

GPBLOCK

GPIO B Lock Configuration Register (GPIO32 to
63)

EALLOW

Go

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-15. GPIO_CTRL_REGS Registers (continued)
Offset

Acronym

Register Name

Write Protection

7Eh

GPBCR

GPIO B Lock Commit Register (GPIO32 to 63)

EALLOW

Section
Go

80h

GPCCTRL

GPIO C Qualification Sampling Period Control
(GPIO64 to 95)

EALLOW

Go

82h

GPCQSEL1

GPIO C Qualifier Select 1 Register (GPIO64 to
79)

EALLOW

Go

84h

GPCQSEL2

GPIO C Qualifier Select 2 Register (GPIO80 to
95)

EALLOW

Go

86h

GPCMUX1

GPIO C Mux 1 Register (GPIO64 to 79)

EALLOW

Go

88h

GPCMUX2

GPIO C Mux 2 Register (GPIO80 to 95)

EALLOW

Go

8Ah

GPCDIR

GPIO C Direction Register (GPIO64 to 95)

EALLOW

Go

8Ch

GPCPUD

GPIO C Pull Up Disable Register (GPIO64 to 95) EALLOW

Go

90h

GPCINV

GPIO C Input Polarity Invert Registers (GPIO64
to 95)

EALLOW

Go

92h

GPCODR

GPIO C Open Drain Output Register (GPIO64 to
GPIO95)

EALLOW

Go

A0h

GPCGMUX1

GPIO C Peripheral Group Mux (GPIO64 to 79)

EALLOW

Go

A2h

GPCGMUX2

GPIO C Peripheral Group Mux (GPIO80 to 95)

EALLOW

Go

A8h

GPCCSEL1

GPIO C Core Select Register (GPIO64 to 71)

EALLOW

Go

AAh

GPCCSEL2

GPIO C Core Select Register (GPIO72 to 79)

EALLOW

Go

ACh

GPCCSEL3

GPIO C Core Select Register (GPIO80 to 87)

EALLOW

Go

AEh

GPCCSEL4

GPIO C Core Select Register (GPIO88 to 95)

EALLOW

Go

BCh

GPCLOCK

GPIO C Lock Configuration Register (GPIO64 to
95)

EALLOW

Go

BEh

GPCCR

GPIO C Lock Commit Register (GPIO64 to 95)

EALLOW

Go

C0h

GPDCTRL

GPIO D Qualification Sampling Period Control
(GPIO96 to 127)

EALLOW

Go

C2h

GPDQSEL1

GPIO D Qualifier Select 1 Register (GPIO96 to
111)

EALLOW

Go

C4h

GPDQSEL2

GPIO D Qualifier Select 2 Register (GPIO112 to
127)

EALLOW

Go

C6h

GPDMUX1

GPIO D Mux 1 Register (GPIO96 to 111)

EALLOW

Go

C8h

GPDMUX2

GPIO D Mux 2 Register (GPIO112 to 127)

EALLOW

Go

CAh

GPDDIR

GPIO D Direction Register (GPIO96 to 127)

EALLOW

Go

CCh

GPDPUD

GPIO D Pull Up Disable Register (GPIO96 to
127)

EALLOW

Go

D0h

GPDINV

GPIO D Input Polarity Invert Registers (GPIO96
to 127)

EALLOW

Go

D2h

GPDODR

GPIO D Open Drain Output Register (GPIO96 to
GPIO127)

EALLOW

Go

E0h

GPDGMUX1

GPIO D Peripheral Group Mux (GPIO96 to 111)

EALLOW

Go

E2h

GPDGMUX2

GPIO D Peripheral Group Mux (GPIO112 to 127) EALLOW

Go

E8h

GPDCSEL1

GPIO D Core Select Register (GPIO96 to 103)

EALLOW

Go

EAh

GPDCSEL2

GPIO D Core Select Register (GPIO104 to 111)

EALLOW

Go

ECh

GPDCSEL3

GPIO D Core Select Register (GPIO112 to 119)

EALLOW

Go

EEh

GPDCSEL4

GPIO D Core Select Register (GPIO120 to 127)

EALLOW

Go

FCh

GPDLOCK

GPIO D Lock Configuration Register (GPIO96 to
127)

EALLOW

Go

FEh

GPDCR

GPIO D Lock Commit Register (GPIO96 to 127)

EALLOW

Go

100h

GPECTRL

GPIO E Qualification Sampling Period Control
(GPIO128 to 159)

EALLOW

Go

102h

GPEQSEL1

GPIO E Qualifier Select 1 Register (GPIO128 to
143)

EALLOW

Go

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

923

Registers

www.ti.com

Table 7-15. GPIO_CTRL_REGS Registers (continued)
Offset

Acronym

Register Name

Write Protection

104h

GPEQSEL2

GPIO E Qualifier Select 2 Register (GPIO144 to
159)

EALLOW

Section
Go

106h

GPEMUX1

GPIO E Mux 1 Register (GPIO128 to 143)

EALLOW

Go

108h

GPEMUX2

GPIO E Mux 2 Register (GPIO144 to 159)

EALLOW

Go

10Ah

GPEDIR

GPIO E Direction Register (GPIO128 to 159)

EALLOW

Go

10Ch

GPEPUD

GPIO E Pull Up Disable Register (GPIO128 to
159)

EALLOW

Go

110h

GPEINV

GPIO E Input Polarity Invert Registers (GPIO128 EALLOW
to 159)

Go

112h

GPEODR

GPIO E Open Drain Output Register (GPIO128
to GPIO159)

EALLOW

Go

120h

GPEGMUX1

GPIO E Peripheral Group Mux (GPIO128 to 143) EALLOW

Go

122h

GPEGMUX2

GPIO E Peripheral Group Mux (GPIO144 to 159) EALLOW

Go

128h

GPECSEL1

GPIO E Core Select Register (GPIO128 to 135)

EALLOW

Go

12Ah

GPECSEL2

GPIO E Core Select Register (GPIO136 to 143)

EALLOW

Go

12Ch

GPECSEL3

GPIO E Core Select Register (GPIO144 to 151)

EALLOW

Go

12Eh

GPECSEL4

GPIO E Core Select Register (GPIO152 to 159)

EALLOW

Go

13Ch

GPELOCK

GPIO E Lock Configuration Register (GPIO128
to 159)

EALLOW

Go

13Eh

GPECR

GPIO E Lock Commit Register (GPIO128 to 159) EALLOW

Go

140h

GPFCTRL

GPIO F Qualification Sampling Period Control
(GPIO160 to 168)

EALLOW

Go

142h

GPFQSEL1

GPIO F Qualifier Select 1 Register (GPIO160 to
168)

EALLOW

Go

146h

GPFMUX1

GPIO F Mux 1 Register (GPIO160 to 168)

EALLOW

Go

14Ah

GPFDIR

GPIO F Direction Register (GPIO160 to 168)

EALLOW

Go

14Ch

GPFPUD

GPIO F Pull Up Disable Register (GPIO160 to
168)

EALLOW

Go

150h

GPFINV

GPIO F Input Polarity Invert Registers (GPIO160 EALLOW
to 168)

Go

152h

GPFODR

GPIO F Open Drain Output Register (GPIO160
to GPIO168)

EALLOW

Go

160h

GPFGMUX1

GPIO F Peripheral Group Mux (GPIO160 to 168) EALLOW

Go

168h

GPFCSEL1

GPIO F Core Select Register (GPIO160 to 167)

EALLOW

Go

16Ah

GPFCSEL2

GPIO F Core Select Register (GPIO168)

EALLOW

Go

17Ch

GPFLOCK

GPIO F Lock Configuration Register (GPIO160
to 168)

EALLOW

Go

17Eh

GPFCR

GPIO F Lock Commit Register (GPIO160 to 168) EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 7-16 shows the codes that are
used for access types in this section.
Table 7-16. GPIO_CTRL_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

W

Write

WOnce

W

Write

Read Type
R
Write Type

Reset or Default Value

924

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-16. GPIO_CTRL_REGS Access Type
Codes (continued)
Access Type

Code

-n

Description
Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

925

Registers

7.9.2.1

www.ti.com

GPACTRL Register (Offset = 0h) [reset = 0h]

GPACTRL is shown in Figure 7-4 and described in Table 7-17.
Return to Summary Table.
GPIO A Qualification Sampling Period Control (GPIO0 to 31)
Figure 7-4. GPACTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUALPRD3
QUALPRD2
QUALPRD1
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5 4 3 2
QUALPRD0
R/W-0h

1

0

Table 7-17. GPACTRL Register Field Descriptions
Bit
31-24

Field

Type

Reset

Description

QUALPRD3

R/W

0h

Qualification sampling period for GPIO24 to GPIO31:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

23-16

QUALPRD2

R/W

0h

Qualification sampling period for GPIO16 to GPIO23:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

15-8

QUALPRD1

R/W

0h

Qualification sampling period for GPIO8 to GPIO15:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

7-0

QUALPRD0

R/W

0h

Qualification sampling period for GPIO0 to GPIO7:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

926

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.2

GPAQSEL1 Register (Offset = 2h) [reset = 0h]

GPAQSEL1 is shown in Figure 7-5 and described in Table 7-18.
Return to Summary Table.
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-5. GPAQSEL1 Register
31
30
GPIO15
R/W-0h

29
28
GPIO14
R/W-0h

27
26
GPIO13
R/W-0h

25
24
GPIO12
R/W-0h

23
22
GPIO11
R/W-0h

21
20
GPIO10
R/W-0h

19
18
GPIO9
R/W-0h

17
16
GPIO8
R/W-0h

15
14
GPIO7
R/W-0h

13
12
GPIO6
R/W-0h

11
10
GPIO5
R/W-0h

9

7

5

3

1

GPIO4
R/W-0h

8

6

GPIO3
R/W-0h

4

GPIO2
R/W-0h

GPIO1
R/W-0h

2

0

GPIO0
R/W-0h

Table 7-18. GPAQSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO15

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO14

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO13

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO12

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO11

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO10

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO9

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO8

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO7

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO6

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO5

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO4

R/W

0h

Input qualification type
Reset type: SYSRSn

7-6

GPIO3

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO2

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

927

Registers

www.ti.com

Table 7-18. GPAQSEL1 Register Field Descriptions (continued)

928

Bit

Field

Type

Reset

Description

3-2

GPIO1

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO0

R/W

0h

Input qualification type
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.3

GPAQSEL2 Register (Offset = 4h) [reset = 0h]

GPAQSEL2 is shown in Figure 7-6 and described in Table 7-19.
Return to Summary Table.
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-6. GPAQSEL2 Register
31
30
GPIO31
R/W-0h

29
28
GPIO30
R/W-0h

27
26
GPIO29
R/W-0h

25
24
GPIO28
R/W-0h

23
22
GPIO27
R/W-0h

21
20
GPIO26
R/W-0h

19
18
GPIO25
R/W-0h

17
16
GPIO24
R/W-0h

15
14
GPIO23
R/W-0h

13
12
GPIO22
R/W-0h

11
10
GPIO21
R/W-0h

9
8
GPIO20
R/W-0h

7
6
GPIO19
R/W-0h

5
4
GPIO18
R/W-0h

3
2
GPIO17
R/W-0h

1
0
GPIO16
R/W-0h

Table 7-19. GPAQSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO31

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO30

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO29

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO28

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO27

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO26

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO25

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO24

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO23

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO22

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO21

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO20

R/W

0h

Input qualification type
Reset type: SYSRSn

7-6

GPIO19

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO18

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

929

Registers

www.ti.com

Table 7-19. GPAQSEL2 Register Field Descriptions (continued)

930

Bit

Field

Type

Reset

Description

3-2

GPIO17

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO16

R/W

0h

Input qualification type
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.4

GPAMUX1 Register (Offset = 6h) [reset = 0h]

GPAMUX1 is shown in Figure 7-7 and described in Table 7-20.
Return to Summary Table.
GPIO A Mux 1 Register (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-7. GPAMUX1 Register
31
30
GPIO15
R/W-0h

29
28
GPIO14
R/W-0h

27
26
GPIO13
R/W-0h

25
24
GPIO12
R/W-0h

23
22
GPIO11
R/W-0h

21
20
GPIO10
R/W-0h

19
18
GPIO9
R/W-0h

17
16
GPIO8
R/W-0h

15
14
GPIO7
R/W-0h

13
12
GPIO6
R/W-0h

11
10
GPIO5
R/W-0h

9

7

5

3

1

GPIO4
R/W-0h

8

6

GPIO3
R/W-0h

4

GPIO2
R/W-0h

GPIO1
R/W-0h

2

0

GPIO0
R/W-0h

Table 7-20. GPAMUX1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO15

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO14

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO13

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO12

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO11

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO10

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO9

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO8

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO7

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO6

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO5

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO4

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO3

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO2

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO1

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

931

Registers

www.ti.com

Table 7-20. GPAMUX1 Register Field Descriptions (continued)

932

Bit

Field

Type

Reset

Description

1-0

GPIO0

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.5

GPAMUX2 Register (Offset = 8h) [reset = 0h]

GPAMUX2 is shown in Figure 7-8 and described in Table 7-21.
Return to Summary Table.
GPIO A Mux 2 Register (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-8. GPAMUX2 Register
31
30
GPIO31
R/W-0h

29
28
GPIO30
R/W-0h

27
26
GPIO29
R/W-0h

25
24
GPIO28
R/W-0h

23
22
GPIO27
R/W-0h

21
20
GPIO26
R/W-0h

19
18
GPIO25
R/W-0h

17
16
GPIO24
R/W-0h

15
14
GPIO23
R/W-0h

13
12
GPIO22
R/W-0h

11
10
GPIO21
R/W-0h

9
8
GPIO20
R/W-0h

7
6
GPIO19
R/W-0h

5
4
GPIO18
R/W-0h

3
2
GPIO17
R/W-0h

1
0
GPIO16
R/W-0h

Table 7-21. GPAMUX2 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO31

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO30

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO29

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO28

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO27

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO26

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO25

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO24

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO23

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO22

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO21

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO20

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO19

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO18

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO17

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

933

Registers

www.ti.com

Table 7-21. GPAMUX2 Register Field Descriptions (continued)

934

Bit

Field

Type

Reset

Description

1-0

GPIO16

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.6

GPADIR Register (Offset = Ah) [reset = 0h]

GPADIR is shown in Figure 7-9 and described in Table 7-22.
Return to Summary Table.
GPIO A Direction Register (GPIO0 to 31)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 7-9. GPADIR Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23

22
GPIO22

21
GPIO21

20
GPIO20

19
GPIO19

18
GPIO18

17
GPIO17

16
GPIO16

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 7-22. GPADIR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

30

GPIO30

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

29

GPIO29

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

28

GPIO28

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

27

GPIO27

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

26

GPIO26

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

25

GPIO25

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

24

GPIO24

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

23

GPIO23

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

22

GPIO22

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

21

GPIO21

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

20

GPIO20

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

935

Registers

www.ti.com

Table 7-22. GPADIR Register Field Descriptions (continued)

936

Bit

Field

Type

Reset

Description

19

GPIO19

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

18

GPIO18

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

17

GPIO17

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

16

GPIO16

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

15

GPIO15

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

14

GPIO14

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

13

GPIO13

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

12

GPIO12

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

11

GPIO11

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

10

GPIO10

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

9

GPIO9

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

8

GPIO8

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

7

GPIO7

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

6

GPIO6

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

5

GPIO5

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

4

GPIO4

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

3

GPIO3

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

2

GPIO2

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

1

GPIO1

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

0

GPIO0

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.7

GPAPUD Register (Offset = Ch) [reset = FFFFFFFFh]

GPAPUD is shown in Figure 7-10 and described in Table 7-23.
Return to Summary Table.
GPIO A Pull Up Disable Register (GPIO0 to 31)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 7-10. GPAPUD Register
31
GPIO31
R/W-1h

30
GPIO30
R/W-1h

29
GPIO29
R/W-1h

28
GPIO28
R/W-1h

27
GPIO27
R/W-1h

26
GPIO26
R/W-1h

25
GPIO25
R/W-1h

24
GPIO24
R/W-1h

23
GPIO23

22
GPIO22

21
GPIO21

20
GPIO20

19
GPIO19

18
GPIO18

17
GPIO17

16
GPIO16

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

15
GPIO15
R/W-1h

14
GPIO14
R/W-1h

13
GPIO13
R/W-1h

12
GPIO12
R/W-1h

11
GPIO11
R/W-1h

10
GPIO10
R/W-1h

9
GPIO9
R/W-1h

8
GPIO8
R/W-1h

7
GPIO7
R/W-1h

6
GPIO6
R/W-1h

5
GPIO5
R/W-1h

4
GPIO4
R/W-1h

3
GPIO3
R/W-1h

2
GPIO2
R/W-1h

1
GPIO1
R/W-1h

0
GPIO0
R/W-1h

Table 7-23. GPAPUD Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

30

GPIO30

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

29

GPIO29

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

28

GPIO28

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

27

GPIO27

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

26

GPIO26

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

25

GPIO25

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

24

GPIO24

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

23

GPIO23

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

22

GPIO22

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

21

GPIO21

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

20

GPIO20

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

937

Registers

www.ti.com

Table 7-23. GPAPUD Register Field Descriptions (continued)

938

Bit

Field

Type

Reset

Description

19

GPIO19

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

18

GPIO18

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

17

GPIO17

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

16

GPIO16

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

15

GPIO15

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

14

GPIO14

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

13

GPIO13

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

12

GPIO12

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

11

GPIO11

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

10

GPIO10

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

9

GPIO9

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

8

GPIO8

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

7

GPIO7

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

6

GPIO6

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

5

GPIO5

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

4

GPIO4

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

3

GPIO3

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

2

GPIO2

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

1

GPIO1

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

0

GPIO0

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.8

GPAINV Register (Offset = 10h) [reset = 0h]

GPAINV is shown in Figure 7-11 and described in Table 7-24.
Return to Summary Table.
GPIO A Input Polarity Invert Registers (GPIO0 to 31)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 7-11. GPAINV Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23

22
GPIO22

21
GPIO21

20
GPIO20

19
GPIO19

18
GPIO18

17
GPIO17

16
GPIO16

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 7-24. GPAINV Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

30

GPIO30

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

29

GPIO29

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

28

GPIO28

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

27

GPIO27

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

26

GPIO26

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

25

GPIO25

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

24

GPIO24

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

23

GPIO23

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

22

GPIO22

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

21

GPIO21

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

20

GPIO20

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

939

Registers

www.ti.com

Table 7-24. GPAINV Register Field Descriptions (continued)

940

Bit

Field

Type

Reset

Description

19

GPIO19

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

18

GPIO18

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

17

GPIO17

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

16

GPIO16

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

15

GPIO15

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

14

GPIO14

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

13

GPIO13

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

12

GPIO12

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

11

GPIO11

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

10

GPIO10

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

9

GPIO9

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

8

GPIO8

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

7

GPIO7

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

6

GPIO6

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

5

GPIO5

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

4

GPIO4

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

3

GPIO3

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

2

GPIO2

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

1

GPIO1

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

0

GPIO0

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.9

GPAODR Register (Offset = 12h) [reset = 0h]

GPAODR is shown in Figure 7-12 and described in Table 7-25.
Return to Summary Table.
GPIO A Open Drain Output Register (GPIO0 to GPIO31)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out
comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 7-12. GPAODR Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23
R/W-0h

22
GPIO22
R/W-0h

21
GPIO21
R/W-0h

20
GPIO20
R/W-0h

19
GPIO19
R/W-0h

18
GPIO18
R/W-0h

17
GPIO17
R/W-0h

16
GPIO16
R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 7-25. GPAODR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

30

GPIO30

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

29

GPIO29

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

28

GPIO28

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

27

GPIO27

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

26

GPIO26

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

25

GPIO25

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

24

GPIO24

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

23

GPIO23

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

22

GPIO22

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

941

Registers

www.ti.com

Table 7-25. GPAODR Register Field Descriptions (continued)

942

Bit

Field

Type

Reset

Description

21

GPIO21

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

20

GPIO20

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

19

GPIO19

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

18

GPIO18

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

17

GPIO17

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

16

GPIO16

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

15

GPIO15

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

14

GPIO14

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

13

GPIO13

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

12

GPIO12

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

11

GPIO11

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

10

GPIO10

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

9

GPIO9

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

8

GPIO8

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

7

GPIO7

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

6

GPIO6

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

5

GPIO5

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

4

GPIO4

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

3

GPIO3

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

2

GPIO2

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

1

GPIO1

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

0

GPIO0

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.10 GPAGMUX1 Register (Offset = 20h) [reset = 0h]
GPAGMUX1 is shown in Figure 7-13 and described in Table 7-26.
Return to Summary Table.
GPIO A Peripheral Group Mux (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-13. GPAGMUX1 Register
31
30
GPIO15
R/W-0h

29
28
GPIO14
R/W-0h

27
26
GPIO13
R/W-0h

25
24
GPIO12
R/W-0h

23
22
GPIO11
R/W-0h

21
20
GPIO10
R/W-0h

19
18
GPIO9
R/W-0h

17
16
GPIO8
R/W-0h

15
14
GPIO7
R/W-0h

13
12
GPIO6
R/W-0h

11
10
GPIO5
R/W-0h

9

7

5

3

1

GPIO4
R/W-0h

8

6

GPIO3
R/W-0h

4

GPIO2
R/W-0h

GPIO1
R/W-0h

2

0

GPIO0
R/W-0h

Table 7-26. GPAGMUX1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO15

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO14

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO13

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO12

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO11

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO10

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO9

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO8

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO7

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO6

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO5

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO4

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO3

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO2

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO1

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO0

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

943

Registers

www.ti.com

7.9.2.11 GPAGMUX2 Register (Offset = 22h) [reset = 0h]
GPAGMUX2 is shown in Figure 7-14 and described in Table 7-27.
Return to Summary Table.
GPIO A Peripheral Group Mux (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-14. GPAGMUX2 Register
31
30
GPIO31
R/W-0h

29
28
GPIO30
R/W-0h

27
26
GPIO29
R/W-0h

25
24
GPIO28
R/W-0h

23
22
GPIO27
R/W-0h

21
20
GPIO26
R/W-0h

19
18
GPIO25
R/W-0h

17
16
GPIO24
R/W-0h

15
14
GPIO23
R/W-0h

13
12
GPIO22
R/W-0h

11
10
GPIO21
R/W-0h

9
8
GPIO20
R/W-0h

7
6
GPIO19
R/W-0h

5
4
GPIO18
R/W-0h

3
2
GPIO17
R/W-0h

1
0
GPIO16
R/W-0h

Table 7-27. GPAGMUX2 Register Field Descriptions
Bit

944

Field

Type

Reset

Description

31-30

GPIO31

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO30

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO29

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO28

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO27

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO26

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO25

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO24

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO23

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO22

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO21

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO20

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO19

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO18

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO17

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO16

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.12 GPACSEL1 Register (Offset = 28h) [reset = 0h]
GPACSEL1 is shown in Figure 7-15 and described in Table 7-28.
Return to Summary Table.
GPIO A Core Select Register (GPIO0 to 7)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-15. GPACSEL1 Register
31

30
29
GPIO7
R/W-0h

28

27

26
25
GPIO6
R/W-0h

24

23

22
21
GPIO5
R/W-0h

20

19

18
17
GPIO4
R/W-0h

16

15

14
13
GPIO3
R/W-0h

12

11

10
9
GPIO2
R/W-0h

8

7

6

4

3

2

0

5

GPIO1
R/W-0h

1

GPIO0
R/W-0h

Table 7-28. GPACSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO7

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO6

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO5

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO4

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO3

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO2

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO1

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO0

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

945

Registers

www.ti.com

7.9.2.13 GPACSEL2 Register (Offset = 2Ah) [reset = 0h]
GPACSEL2 is shown in Figure 7-16 and described in Table 7-29.
Return to Summary Table.
GPIO A Core Select Register (GPIO8 to 15)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-16. GPACSEL2 Register
31

30
29
GPIO15
R/W-0h

28

27

26
25
GPIO14
R/W-0h

24

23

22
21
GPIO13
R/W-0h

20

19

18
17
GPIO12
R/W-0h

16

15

14
13
GPIO11
R/W-0h

12

11

10
9
GPIO10
R/W-0h

8

7

6

4

3

2

0

5

GPIO9
R/W-0h

1

GPIO8
R/W-0h

Table 7-29. GPACSEL2 Register Field Descriptions
Bit

946

Field

Type

Reset

Description

31-28

GPIO15

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO14

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO13

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO12

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO11

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO10

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO9

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO8

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.14 GPACSEL3 Register (Offset = 2Ch) [reset = 0h]
GPACSEL3 is shown in Figure 7-17 and described in Table 7-30.
Return to Summary Table.
GPIO A Core Select Register (GPIO16 to 23)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-17. GPACSEL3 Register
31

30
29
GPIO23
R/W-0h

28

27

26
25
GPIO22
R/W-0h

24

23

22
21
GPIO21
R/W-0h

20

19

18
17
GPIO20
R/W-0h

16

15

14
13
GPIO19
R/W-0h

12

11

10
9
GPIO18
R/W-0h

8

7

6
5
GPIO17
R/W-0h

4

3

2
1
GPIO16
R/W-0h

0

Table 7-30. GPACSEL3 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO23

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO22

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO21

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO20

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO19

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO18

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO17

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO16

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

947

Registers

www.ti.com

7.9.2.15 GPACSEL4 Register (Offset = 2Eh) [reset = 0h]
GPACSEL4 is shown in Figure 7-18 and described in Table 7-31.
Return to Summary Table.
GPIO A Core Select Register (GPIO24 to 31)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-18. GPACSEL4 Register
31

30
29
GPIO31
R/W-0h

28

27

26
25
GPIO30
R/W-0h

24

23

22
21
GPIO29
R/W-0h

20

19

18
17
GPIO28
R/W-0h

16

15

14
13
GPIO27
R/W-0h

12

11

10
9
GPIO26
R/W-0h

8

7

6
5
GPIO25
R/W-0h

4

3

2
1
GPIO24
R/W-0h

0

Table 7-31. GPACSEL4 Register Field Descriptions
Bit

948

Field

Type

Reset

Description

31-28

GPIO31

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO30

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO29

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO28

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO27

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO26

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO25

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO24

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.16 GPALOCK Register (Offset = 3Ch) [reset = 0h]
GPALOCK is shown in Figure 7-19 and described in Table 7-32.
Return to Summary Table.
GPIO A Lock Configuration Register (GPIO0 to 31)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2
and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL,
GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 7-19. GPALOCK Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23
R/W-0h

22
GPIO22
R/W-0h

21
GPIO21
R/W-0h

20
GPIO20
R/W-0h

19
GPIO19
R/W-0h

18
GPIO18
R/W-0h

17
GPIO17
R/W-0h

16
GPIO16
R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 7-32. GPALOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

30

GPIO30

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

29

GPIO29

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

28

GPIO28

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

27

GPIO27

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

26

GPIO26

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

25

GPIO25

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

24

GPIO24

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

23

GPIO23

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

22

GPIO22

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

21

GPIO21

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

949

Registers

www.ti.com

Table 7-32. GPALOCK Register Field Descriptions (continued)

950

Bit

Field

Type

Reset

Description

20

GPIO20

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

19

GPIO19

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

18

GPIO18

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

17

GPIO17

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

16

GPIO16

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

15

GPIO15

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

14

GPIO14

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

13

GPIO13

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

12

GPIO12

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

11

GPIO11

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

10

GPIO10

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

9

GPIO9

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

8

GPIO8

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

7

GPIO7

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

6

GPIO6

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

5

GPIO5

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

4

GPIO4

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

3

GPIO3

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

2

GPIO2

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

1

GPIO1

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

0

GPIO0

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.17 GPACR Register (Offset = 3Eh) [reset = 0h]
GPACR is shown in Figure 7-20 and described in Table 7-33.
Return to Summary Table.
GPIO A Lock Commit Register (GPIO0 to 31)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 7-20. GPACR Register
31
GPIO31
R/WOnce-0h

30
GPIO30
R/WOnce-0h

29
GPIO29
R/WOnce-0h

28
GPIO28
R/WOnce-0h

27
GPIO27
R/WOnce-0h

26
GPIO26
R/WOnce-0h

25
GPIO25
R/WOnce-0h

24
GPIO24
R/WOnce-0h

23
GPIO23
R/WOnce-0h

22
GPIO22
R/WOnce-0h

21
GPIO21
R/WOnce-0h

20
GPIO20
R/WOnce-0h

19
GPIO19
R/WOnce-0h

18
GPIO18
R/WOnce-0h

17
GPIO17
R/WOnce-0h

16
GPIO16
R/WOnce-0h

15
GPIO15
R/WOnce-0h

14
GPIO14
R/WOnce-0h

13
GPIO13
R/WOnce-0h

12
GPIO12
R/WOnce-0h

11
GPIO11
R/WOnce-0h

10
GPIO10
R/WOnce-0h

9
GPIO9
R/WOnce-0h

8
GPIO8
R/WOnce-0h

7
GPIO7
R/WOnce-0h

6
GPIO6
R/WOnce-0h

5
GPIO5
R/WOnce-0h

4
GPIO4
R/WOnce-0h

3
GPIO3
R/WOnce-0h

2
GPIO2
R/WOnce-0h

1
GPIO1
R/WOnce-0h

0
GPIO0
R/WOnce-0h

Table 7-33. GPACR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

30

GPIO30

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

29

GPIO29

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

28

GPIO28

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

27

GPIO27

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

26

GPIO26

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

25

GPIO25

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

24

GPIO24

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

23

GPIO23

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

22

GPIO22

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

21

GPIO21

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

20

GPIO20

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

951

Registers

www.ti.com

Table 7-33. GPACR Register Field Descriptions (continued)

952

Bit

Field

Type

Reset

Description

19

GPIO19

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

18

GPIO18

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

17

GPIO17

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

16

GPIO16

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

15

GPIO15

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

14

GPIO14

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

13

GPIO13

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

12

GPIO12

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

11

GPIO11

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

10

GPIO10

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

9

GPIO9

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

8

GPIO8

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

7

GPIO7

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

6

GPIO6

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

5

GPIO5

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

4

GPIO4

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

3

GPIO3

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

2

GPIO2

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

1

GPIO1

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

0

GPIO0

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.18 GPBCTRL Register (Offset = 40h) [reset = 0h]
GPBCTRL is shown in Figure 7-21 and described in Table 7-34.
Return to Summary Table.
GPIO B Qualification Sampling Period Control (GPIO32 to 63)
Figure 7-21. GPBCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUALPRD3
QUALPRD2
QUALPRD1
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5 4 3 2
QUALPRD0
R/W-0h

1

0

Table 7-34. GPBCTRL Register Field Descriptions
Bit
31-24

Field

Type

Reset

Description

QUALPRD3

R/W

0h

Qualification sampling period for GPIO56 to GPIO63:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

23-16

QUALPRD2

R/W

0h

Qualification sampling period for GPIO48 to GPIO55:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

15-8

QUALPRD1

R/W

0h

Qualification sampling period for GPIO40 to GPIO47:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

7-0

QUALPRD0

R/W

0h

Qualification sampling period for GPIO32 to GPIO39:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

953

Registers

www.ti.com

7.9.2.19 GPBQSEL1 Register (Offset = 42h) [reset = 0h]
GPBQSEL1 is shown in Figure 7-22 and described in Table 7-35.
Return to Summary Table.
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-22. GPBQSEL1 Register
31
30
GPIO47
R/W-0h

29
28
GPIO46
R/W-0h

27
26
GPIO45
R/W-0h

25
24
GPIO44
R/W-0h

23
22
GPIO43
R/W-0h

21
20
GPIO42
R/W-0h

19
18
GPIO41
R/W-0h

17
16
GPIO40
R/W-0h

15
14
GPIO39
R/W-0h

13
12
GPIO38
R/W-0h

11
10
GPIO37
R/W-0h

9
8
GPIO36
R/W-0h

7
6
GPIO35
R/W-0h

5
4
GPIO34
R/W-0h

3
2
GPIO33
R/W-0h

1
0
GPIO32
R/W-0h

Table 7-35. GPBQSEL1 Register Field Descriptions
Bit

954

Field

Type

Reset

Description

31-30

GPIO47

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO46

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO45

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO44

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO43

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO42

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO41

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO40

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO39

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO38

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO37

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO36

R/W

0h

Input qualification type
Reset type: SYSRSn

7-6

GPIO35

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO34

R/W

0h

Input qualification type
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-35. GPBQSEL1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-2

GPIO33

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO32

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

955

Registers

www.ti.com

7.9.2.20 GPBQSEL2 Register (Offset = 44h) [reset = 0h]
GPBQSEL2 is shown in Figure 7-23 and described in Table 7-36.
Return to Summary Table.
GPIO B Qualifier Select 2 Register (GPIO48 to 63)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-23. GPBQSEL2 Register
31
30
GPIO63
R/W-0h

29
28
GPIO62
R/W-0h

27
26
GPIO61
R/W-0h

25
24
GPIO60
R/W-0h

23
22
GPIO59
R/W-0h

21
20
GPIO58
R/W-0h

19
18
GPIO57
R/W-0h

17
16
GPIO56
R/W-0h

15
14
GPIO55
R/W-0h

13
12
GPIO54
R/W-0h

11
10
GPIO53
R/W-0h

9
8
GPIO52
R/W-0h

7
6
GPIO51
R/W-0h

5
4
GPIO50
R/W-0h

3
2
GPIO49
R/W-0h

1
0
GPIO48
R/W-0h

Table 7-36. GPBQSEL2 Register Field Descriptions
Bit

956

Field

Type

Reset

Description

31-30

GPIO63

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO62

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO61

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO60

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO59

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO58

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO57

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO56

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO55

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO54

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO53

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO52

R/W

0h

Input qualification type
Reset type: SYSRSn

7-6

GPIO51

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO50

R/W

0h

Input qualification type
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-36. GPBQSEL2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-2

GPIO49

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO48

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

957

Registers

www.ti.com

7.9.2.21 GPBMUX1 Register (Offset = 46h) [reset = 0h]
GPBMUX1 is shown in Figure 7-24 and described in Table 7-37.
Return to Summary Table.
GPIO B Mux 1 Register (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-24. GPBMUX1 Register
31
30
GPIO47
R/W-0h

29
28
GPIO46
R/W-0h

27
26
GPIO45
R/W-0h

25
24
GPIO44
R/W-0h

23
22
GPIO43
R/W-0h

21
20
GPIO42
R/W-0h

19
18
GPIO41
R/W-0h

17
16
GPIO40
R/W-0h

15
14
GPIO39
R/W-0h

13
12
GPIO38
R/W-0h

11
10
GPIO37
R/W-0h

9
8
GPIO36
R/W-0h

7
6
GPIO35
R/W-0h

5
4
GPIO34
R/W-0h

3
2
GPIO33
R/W-0h

1
0
GPIO32
R/W-0h

Table 7-37. GPBMUX1 Register Field Descriptions
Bit

958

Field

Type

Reset

Description

31-30

GPIO47

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO46

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO45

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO44

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO43

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO42

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO41

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO40

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO39

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO38

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO37

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO36

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO35

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO34

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO33

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-37. GPBMUX1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

GPIO32

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

959

Registers

www.ti.com

7.9.2.22 GPBMUX2 Register (Offset = 48h) [reset = 0h]
GPBMUX2 is shown in Figure 7-25 and described in Table 7-38.
Return to Summary Table.
GPIO B Mux 2 Register (GPIO48 to 63)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-25. GPBMUX2 Register
31
30
GPIO63
R/W-0h

29
28
GPIO62
R/W-0h

27
26
GPIO61
R/W-0h

25
24
GPIO60
R/W-0h

23
22
GPIO59
R/W-0h

21
20
GPIO58
R/W-0h

19
18
GPIO57
R/W-0h

17
16
GPIO56
R/W-0h

15
14
GPIO55
R/W-0h

13
12
GPIO54
R/W-0h

11
10
GPIO53
R/W-0h

9
8
GPIO52
R/W-0h

7
6
GPIO51
R/W-0h

5
4
GPIO50
R/W-0h

3
2
GPIO49
R/W-0h

1
0
GPIO48
R/W-0h

Table 7-38. GPBMUX2 Register Field Descriptions
Bit

960

Field

Type

Reset

Description

31-30

GPIO63

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO62

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO61

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO60

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO59

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO58

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO57

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO56

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO55

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO54

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO53

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO52

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO51

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO50

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO49

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-38. GPBMUX2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

GPIO48

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

961

Registers

www.ti.com

7.9.2.23 GPBDIR Register (Offset = 4Ah) [reset = 0h]
GPBDIR is shown in Figure 7-26 and described in Table 7-39.
Return to Summary Table.
GPIO B Direction Register (GPIO32 to 63)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 7-26. GPBDIR Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55

22
GPIO54

21
GPIO53

20
GPIO52

19
GPIO51

18
GPIO50

17
GPIO49

16
GPIO48

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 7-39. GPBDIR Register Field Descriptions

962

Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

30

GPIO62

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

29

GPIO61

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

28

GPIO60

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

27

GPIO59

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

26

GPIO58

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

25

GPIO57

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

24

GPIO56

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

23

GPIO55

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

22

GPIO54

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

21

GPIO53

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

20

GPIO52

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-39. GPBDIR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

GPIO51

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

18

GPIO50

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

17

GPIO49

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

16

GPIO48

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

15

GPIO47

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

14

GPIO46

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

13

GPIO45

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

12

GPIO44

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

11

GPIO43

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

10

GPIO42

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

9

GPIO41

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

8

GPIO40

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

7

GPIO39

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

6

GPIO38

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

5

GPIO37

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

4

GPIO36

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

3

GPIO35

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

2

GPIO34

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

1

GPIO33

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

0

GPIO32

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

963

Registers

www.ti.com

7.9.2.24 GPBPUD Register (Offset = 4Ch) [reset = FFFFFFFFh]
GPBPUD is shown in Figure 7-27 and described in Table 7-40.
Return to Summary Table.
GPIO B Pull Up Disable Register (GPIO32 to 63)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 7-27. GPBPUD Register
31
GPIO63
R/W-1h

30
GPIO62
R/W-1h

29
GPIO61
R/W-1h

28
GPIO60
R/W-1h

27
GPIO59
R/W-1h

26
GPIO58
R/W-1h

25
GPIO57
R/W-1h

24
GPIO56
R/W-1h

23
GPIO55

22
GPIO54

21
GPIO53

20
GPIO52

19
GPIO51

18
GPIO50

17
GPIO49

16
GPIO48

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

15
GPIO47
R/W-1h

14
GPIO46
R/W-1h

13
GPIO45
R/W-1h

12
GPIO44
R/W-1h

11
GPIO43
R/W-1h

10
GPIO42
R/W-1h

9
GPIO41
R/W-1h

8
GPIO40
R/W-1h

7
GPIO39
R/W-1h

6
GPIO38
R/W-1h

5
GPIO37
R/W-1h

4
GPIO36
R/W-1h

3
GPIO35
R/W-1h

2
GPIO34
R/W-1h

1
GPIO33
R/W-1h

0
GPIO32
R/W-1h

Table 7-40. GPBPUD Register Field Descriptions

964

Bit

Field

Type

Reset

Description

31

GPIO63

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

30

GPIO62

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

29

GPIO61

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

28

GPIO60

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

27

GPIO59

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

26

GPIO58

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

25

GPIO57

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

24

GPIO56

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

23

GPIO55

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

22

GPIO54

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

21

GPIO53

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

20

GPIO52

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-40. GPBPUD Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

GPIO51

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

18

GPIO50

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

17

GPIO49

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

16

GPIO48

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

15

GPIO47

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

14

GPIO46

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

13

GPIO45

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

12

GPIO44

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

11

GPIO43

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

10

GPIO42

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

9

GPIO41

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

8

GPIO40

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

7

GPIO39

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

6

GPIO38

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

5

GPIO37

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

4

GPIO36

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

3

GPIO35

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

2

GPIO34

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

1

GPIO33

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

0

GPIO32

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

965

Registers

www.ti.com

7.9.2.25 GPBINV Register (Offset = 50h) [reset = 0h]
GPBINV is shown in Figure 7-28 and described in Table 7-41.
Return to Summary Table.
GPIO B Input Polarity Invert Registers (GPIO32 to 63)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 7-28. GPBINV Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55

22
GPIO54

21
GPIO53

20
GPIO52

19
GPIO51

18
GPIO50

17
GPIO49

16
GPIO48

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 7-41. GPBINV Register Field Descriptions

966

Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

30

GPIO62

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

29

GPIO61

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

28

GPIO60

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

27

GPIO59

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

26

GPIO58

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

25

GPIO57

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

24

GPIO56

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

23

GPIO55

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

22

GPIO54

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

21

GPIO53

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

20

GPIO52

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-41. GPBINV Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

GPIO51

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

18

GPIO50

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

17

GPIO49

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

16

GPIO48

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

15

GPIO47

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

14

GPIO46

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

13

GPIO45

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

12

GPIO44

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

11

GPIO43

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

10

GPIO42

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

9

GPIO41

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

8

GPIO40

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

7

GPIO39

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

6

GPIO38

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

5

GPIO37

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

4

GPIO36

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

3

GPIO35

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

2

GPIO34

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

1

GPIO33

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

0

GPIO32

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

967

Registers

www.ti.com

7.9.2.26 GPBODR Register (Offset = 52h) [reset = 0h]
GPBODR is shown in Figure 7-29 and described in Table 7-42.
Return to Summary Table.
GPIO B Open Drain Output Register (GPIO32 to GPIO63)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out
comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 7-29. GPBODR Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55
R/W-0h

22
GPIO54
R/W-0h

21
GPIO53
R/W-0h

20
GPIO52
R/W-0h

19
GPIO51
R/W-0h

18
GPIO50
R/W-0h

17
GPIO49
R/W-0h

16
GPIO48
R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 7-42. GPBODR Register Field Descriptions

968

Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

30

GPIO62

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

29

GPIO61

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

28

GPIO60

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

27

GPIO59

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

26

GPIO58

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

25

GPIO57

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

24

GPIO56

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

23

GPIO55

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

22

GPIO54

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-42. GPBODR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

21

GPIO53

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

20

GPIO52

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

19

GPIO51

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

18

GPIO50

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

17

GPIO49

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

16

GPIO48

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

15

GPIO47

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

14

GPIO46

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

13

GPIO45

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

12

GPIO44

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

11

GPIO43

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

10

GPIO42

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

9

GPIO41

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

8

GPIO40

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

7

GPIO39

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

6

GPIO38

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

5

GPIO37

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

4

GPIO36

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

3

GPIO35

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

2

GPIO34

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

1

GPIO33

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

0

GPIO32

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

969

Registers

www.ti.com

7.9.2.27 GPBAMSEL Register (Offset = 54h) [reset = 0h]
GPBAMSEL is shown in Figure 7-30 and described in Table 7-43.
Return to Summary Table.
GPIO B Analog Mode Select register
Selects between digital and analog functionality for GPIO pins.
0: The pin is configured to digital functions according to the other GPIO configuration registers
1: The analog function of the pin is enabled
Figure 7-30. GPBAMSEL Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18
RESERVED
R-0h

17
RESERVED
R-0h

16
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
RESERVED
R-0h

8
RESERVED
R-0h

7
RESERVED
R-0h

6
RESERVED
R-0h

5
RESERVED
R-0h

4
RESERVED
R-0h

3
RESERVED
R-0h

2
RESERVED
R-0h

1
RESERVED
R-0h

0
RESERVED
R-0h

Table 7-43. GPBAMSEL Register Field Descriptions

970

Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

GPIO43

R/W

0h

Selects the USB0DP function
Reset type: SYSRSn

10

GPIO42

R/W

0h

Selects the USB0DM function
Reset type: SYSRSn

9

RESERVED

R

0h

Reserved

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-43. GPBAMSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

971

Registers

www.ti.com

7.9.2.28 GPBGMUX1 Register (Offset = 60h) [reset = 0h]
GPBGMUX1 is shown in Figure 7-31 and described in Table 7-44.
Return to Summary Table.
GPIO B Peripheral Group Mux (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-31. GPBGMUX1 Register
31
30
GPIO47
R/W-0h

29
28
GPIO46
R/W-0h

27
26
GPIO45
R/W-0h

25
24
GPIO44
R/W-0h

23
22
GPIO43
R/W-0h

21
20
GPIO42
R/W-0h

19
18
GPIO41
R/W-0h

17
16
GPIO40
R/W-0h

15
14
GPIO39
R/W-0h

13
12
GPIO38
R/W-0h

11
10
GPIO37
R/W-0h

9
8
GPIO36
R/W-0h

7
6
GPIO35
R/W-0h

5
4
GPIO34
R/W-0h

3
2
GPIO33
R/W-0h

1
0
GPIO32
R/W-0h

Table 7-44. GPBGMUX1 Register Field Descriptions
Bit

972

Field

Type

Reset

Description

31-30

GPIO47

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO46

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO45

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO44

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO43

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO42

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO41

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO40

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO39

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO38

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO37

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO36

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO35

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO34

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO33

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO32

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.29 GPBGMUX2 Register (Offset = 62h) [reset = 0h]
GPBGMUX2 is shown in Figure 7-32 and described in Table 7-45.
Return to Summary Table.
GPIO B Peripheral Group Mux (GPIO48 to 63)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-32. GPBGMUX2 Register
31
30
GPIO63
R/W-0h

29
28
GPIO62
R/W-0h

27
26
GPIO61
R/W-0h

25
24
GPIO60
R/W-0h

23
22
GPIO59
R/W-0h

21
20
GPIO58
R/W-0h

19
18
GPIO57
R/W-0h

17
16
GPIO56
R/W-0h

15
14
GPIO55
R/W-0h

13
12
GPIO54
R/W-0h

11
10
GPIO53
R/W-0h

9
8
GPIO52
R/W-0h

7
6
GPIO51
R/W-0h

5
4
GPIO50
R/W-0h

3
2
GPIO49
R/W-0h

1
0
GPIO48
R/W-0h

Table 7-45. GPBGMUX2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO63

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO62

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO61

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO60

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO59

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO58

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO57

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO56

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO55

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO54

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO53

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO52

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO51

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO50

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO49

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO48

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

973

Registers

www.ti.com

7.9.2.30 GPBCSEL1 Register (Offset = 68h) [reset = 0h]
GPBCSEL1 is shown in Figure 7-33 and described in Table 7-46.
Return to Summary Table.
GPIO B Core Select Register (GPIO32 to 39)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-33. GPBCSEL1 Register
31

30
29
GPIO39
R/W-0h

28

27

26
25
GPIO38
R/W-0h

24

23

22
21
GPIO37
R/W-0h

20

19

18
17
GPIO36
R/W-0h

16

15

14
13
GPIO35
R/W-0h

12

11

10
9
GPIO34
R/W-0h

8

7

6
5
GPIO33
R/W-0h

4

3

2
1
GPIO32
R/W-0h

0

Table 7-46. GPBCSEL1 Register Field Descriptions
Bit

974

Field

Type

Reset

Description

31-28

GPIO39

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO38

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO37

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO36

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO35

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO34

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO33

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO32

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.31 GPBCSEL2 Register (Offset = 6Ah) [reset = 0h]
GPBCSEL2 is shown in Figure 7-34 and described in Table 7-47.
Return to Summary Table.
GPIO B Core Select Register (GPIO40 to 47)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-34. GPBCSEL2 Register
31

30
29
GPIO47
R/W-0h

28

27

26
25
GPIO46
R/W-0h

24

23

22
21
GPIO45
R/W-0h

20

19

18
17
GPIO44
R/W-0h

16

15

14
13
GPIO43
R/W-0h

12

11

10
9
GPIO42
R/W-0h

8

7

6
5
GPIO41
R/W-0h

4

3

2
1
GPIO40
R/W-0h

0

Table 7-47. GPBCSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO47

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO46

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO45

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO44

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO43

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO42

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO41

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO40

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

975

Registers

www.ti.com

7.9.2.32 GPBCSEL3 Register (Offset = 6Ch) [reset = 0h]
GPBCSEL3 is shown in Figure 7-35 and described in Table 7-48.
Return to Summary Table.
GPIO B Core Select Register (GPIO48 to 55)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-35. GPBCSEL3 Register
31

30
29
GPIO55
R/W-0h

28

27

26
25
GPIO54
R/W-0h

24

23

22
21
GPIO53
R/W-0h

20

19

18
17
GPIO52
R/W-0h

16

15

14
13
GPIO51
R/W-0h

12

11

10
9
GPIO50
R/W-0h

8

7

6
5
GPIO49
R/W-0h

4

3

2
1
GPIO48
R/W-0h

0

Table 7-48. GPBCSEL3 Register Field Descriptions
Bit

976

Field

Type

Reset

Description

31-28

GPIO55

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO54

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO53

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO52

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO51

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO50

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO49

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO48

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.33 GPBCSEL4 Register (Offset = 6Eh) [reset = 0h]
GPBCSEL4 is shown in Figure 7-36 and described in Table 7-49.
Return to Summary Table.
GPIO B Core Select Register (GPIO56 to 63)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-36. GPBCSEL4 Register
31

30
29
GPIO63
R/W-0h

28

27

26
25
GPIO62
R/W-0h

24

23

22
21
GPIO61
R/W-0h

20

19

18
17
GPIO60
R/W-0h

16

15

14
13
GPIO59
R/W-0h

12

11

10
9
GPIO58
R/W-0h

8

7

6
5
GPIO57
R/W-0h

4

3

2
1
GPIO56
R/W-0h

0

Table 7-49. GPBCSEL4 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO63

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO62

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO61

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO60

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO59

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO58

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO57

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO56

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

977

Registers

www.ti.com

7.9.2.34 GPBLOCK Register (Offset = 7Ch) [reset = 0h]
GPBLOCK is shown in Figure 7-37 and described in Table 7-50.
Return to Summary Table.
GPIO B Lock Configuration Register (GPIO32 to 63)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2
and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL,
GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 7-37. GPBLOCK Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55
R/W-0h

22
GPIO54
R/W-0h

21
GPIO53
R/W-0h

20
GPIO52
R/W-0h

19
GPIO51
R/W-0h

18
GPIO50
R/W-0h

17
GPIO49
R/W-0h

16
GPIO48
R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 7-50. GPBLOCK Register Field Descriptions

978

Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

30

GPIO62

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

29

GPIO61

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

28

GPIO60

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

27

GPIO59

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

26

GPIO58

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

25

GPIO57

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

24

GPIO56

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

23

GPIO55

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

22

GPIO54

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

21

GPIO53

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-50. GPBLOCK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

GPIO52

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

19

GPIO51

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

18

GPIO50

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

17

GPIO49

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

16

GPIO48

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

15

GPIO47

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

14

GPIO46

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

13

GPIO45

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

12

GPIO44

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

11

GPIO43

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

10

GPIO42

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

9

GPIO41

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

8

GPIO40

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

7

GPIO39

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

6

GPIO38

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

5

GPIO37

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

4

GPIO36

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

3

GPIO35

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

2

GPIO34

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

1

GPIO33

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

0

GPIO32

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

979

Registers

www.ti.com

7.9.2.35 GPBCR Register (Offset = 7Eh) [reset = 0h]
GPBCR is shown in Figure 7-38 and described in Table 7-51.
Return to Summary Table.
GPIO B Lock Commit Register (GPIO32 to 63)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 7-38. GPBCR Register
31
GPIO63
R/WOnce-0h

30
GPIO62
R/WOnce-0h

29
GPIO61
R/WOnce-0h

28
GPIO60
R/WOnce-0h

27
GPIO59
R/WOnce-0h

26
GPIO58
R/WOnce-0h

25
GPIO57
R/WOnce-0h

24
GPIO56
R/WOnce-0h

23
GPIO55
R/WOnce-0h

22
GPIO54
R/WOnce-0h

21
GPIO53
R/WOnce-0h

20
GPIO52
R/WOnce-0h

19
GPIO51
R/WOnce-0h

18
GPIO50
R/WOnce-0h

17
GPIO49
R/WOnce-0h

16
GPIO48
R/WOnce-0h

15
GPIO47
R/WOnce-0h

14
GPIO46
R/WOnce-0h

13
GPIO45
R/WOnce-0h

12
GPIO44
R/WOnce-0h

11
GPIO43
R/WOnce-0h

10
GPIO42
R/WOnce-0h

9
GPIO41
R/WOnce-0h

8
GPIO40
R/WOnce-0h

7
GPIO39
R/WOnce-0h

6
GPIO38
R/WOnce-0h

5
GPIO37
R/WOnce-0h

4
GPIO36
R/WOnce-0h

3
GPIO35
R/WOnce-0h

2
GPIO34
R/WOnce-0h

1
GPIO33
R/WOnce-0h

0
GPIO32
R/WOnce-0h

Table 7-51. GPBCR Register Field Descriptions

980

Bit

Field

Type

Reset

Description

31

GPIO63

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

30

GPIO62

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

29

GPIO61

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

28

GPIO60

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

27

GPIO59

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

26

GPIO58

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

25

GPIO57

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

24

GPIO56

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

23

GPIO55

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

22

GPIO54

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

21

GPIO53

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

20

GPIO52

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-51. GPBCR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

GPIO51

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

18

GPIO50

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

17

GPIO49

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

16

GPIO48

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

15

GPIO47

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

14

GPIO46

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

13

GPIO45

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

12

GPIO44

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

11

GPIO43

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

10

GPIO42

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

9

GPIO41

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

8

GPIO40

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

7

GPIO39

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

6

GPIO38

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

5

GPIO37

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

4

GPIO36

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

3

GPIO35

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

2

GPIO34

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

1

GPIO33

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

0

GPIO32

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

981

Registers

www.ti.com

7.9.2.36 GPCCTRL Register (Offset = 80h) [reset = 0h]
GPCCTRL is shown in Figure 7-39 and described in Table 7-52.
Return to Summary Table.
GPIO C Qualification Sampling Period Control (GPIO64 to 95)
Figure 7-39. GPCCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUALPRD3
QUALPRD2
QUALPRD1
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5 4 3 2
QUALPRD0
R/W-0h

1

0

Table 7-52. GPCCTRL Register Field Descriptions
Bit
31-24

Field

Type

Reset

Description

QUALPRD3

R/W

0h

Qualification sampling period for GPIO88 to GPIO95:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

23-16

QUALPRD2

R/W

0h

Qualification sampling period for GPIO80 to GPIO87:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

15-8

QUALPRD1

R/W

0h

Qualification sampling period for GPIO72 to GPIO79:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

7-0

QUALPRD0

R/W

0h

Qualification sampling period for GPIO64 to GPIO71:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

982

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.37 GPCQSEL1 Register (Offset = 82h) [reset = 0h]
GPCQSEL1 is shown in Figure 7-40 and described in Table 7-53.
Return to Summary Table.
GPIO C Qualifier Select 1 Register (GPIO64 to 79)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-40. GPCQSEL1 Register
31
30
GPIO79
R/W-0h

29
28
GPIO78
R/W-0h

27
26
GPIO77
R/W-0h

25
24
GPIO76
R/W-0h

23
22
GPIO75
R/W-0h

21
20
GPIO74
R/W-0h

19
18
GPIO73
R/W-0h

17
16
GPIO72
R/W-0h

15
14
GPIO71
R/W-0h

13
12
GPIO70
R/W-0h

11
10
GPIO69
R/W-0h

9
8
GPIO68
R/W-0h

7
6
GPIO67
R/W-0h

5
4
GPIO66
R/W-0h

3
2
GPIO65
R/W-0h

1
0
GPIO64
R/W-0h

Table 7-53. GPCQSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO79

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO78

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO77

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO76

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO75

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO74

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO73

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO72

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO71

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO70

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO69

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO68

R/W

0h

Input qualification type
Reset type: SYSRSn

7-6

GPIO67

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO66

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

983

Registers

www.ti.com

Table 7-53. GPCQSEL1 Register Field Descriptions (continued)

984

Bit

Field

Type

Reset

Description

3-2

GPIO65

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO64

R/W

0h

Input qualification type
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.38 GPCQSEL2 Register (Offset = 84h) [reset = 0h]
GPCQSEL2 is shown in Figure 7-41 and described in Table 7-54.
Return to Summary Table.
GPIO C Qualifier Select 2 Register (GPIO80 to 95)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-41. GPCQSEL2 Register
31
30
GPIO95
R/W-0h

29
28
GPIO94
R/W-0h

27
26
GPIO93
R/W-0h

25
24
GPIO92
R/W-0h

23
22
GPIO91
R/W-0h

21
20
GPIO90
R/W-0h

19
18
GPIO89
R/W-0h

17
16
GPIO88
R/W-0h

15
14
GPIO87
R/W-0h

13
12
GPIO86
R/W-0h

11
10
GPIO85
R/W-0h

9
8
GPIO84
R/W-0h

7
6
GPIO83
R/W-0h

5
4
GPIO82
R/W-0h

3
2
GPIO81
R/W-0h

1
0
GPIO80
R/W-0h

Table 7-54. GPCQSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO95

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO94

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO93

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO92

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO91

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO90

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO89

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO88

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO87

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO86

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO85

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO84

R/W

0h

Input qualification type
Reset type: SYSRSn

7-6

GPIO83

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO82

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

985

Registers

www.ti.com

Table 7-54. GPCQSEL2 Register Field Descriptions (continued)

986

Bit

Field

Type

Reset

Description

3-2

GPIO81

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO80

R/W

0h

Input qualification type
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.39 GPCMUX1 Register (Offset = 86h) [reset = 0h]
GPCMUX1 is shown in Figure 7-42 and described in Table 7-55.
Return to Summary Table.
GPIO C Mux 1 Register (GPIO64 to 79)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-42. GPCMUX1 Register
31
30
GPIO79
R/W-0h

29
28
GPIO78
R/W-0h

27
26
GPIO77
R/W-0h

25
24
GPIO76
R/W-0h

23
22
GPIO75
R/W-0h

21
20
GPIO74
R/W-0h

19
18
GPIO73
R/W-0h

17
16
GPIO72
R/W-0h

15
14
GPIO71
R/W-0h

13
12
GPIO70
R/W-0h

11
10
GPIO69
R/W-0h

9
8
GPIO68
R/W-0h

7
6
GPIO67
R/W-0h

5
4
GPIO66
R/W-0h

3
2
GPIO65
R/W-0h

1
0
GPIO64
R/W-0h

Table 7-55. GPCMUX1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO79

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO78

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO77

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO76

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO75

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO74

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO73

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO72

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO71

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO70

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO69

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO68

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO67

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO66

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO65

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

987

Registers

www.ti.com

Table 7-55. GPCMUX1 Register Field Descriptions (continued)

988

Bit

Field

Type

Reset

Description

1-0

GPIO64

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.40 GPCMUX2 Register (Offset = 88h) [reset = 0h]
GPCMUX2 is shown in Figure 7-43 and described in Table 7-56.
Return to Summary Table.
GPIO C Mux 2 Register (GPIO80 to 95)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-43. GPCMUX2 Register
31
30
GPIO95
R/W-0h

29
28
GPIO94
R/W-0h

27
26
GPIO93
R/W-0h

25
24
GPIO92
R/W-0h

23
22
GPIO91
R/W-0h

21
20
GPIO90
R/W-0h

19
18
GPIO89
R/W-0h

17
16
GPIO88
R/W-0h

15
14
GPIO87
R/W-0h

13
12
GPIO86
R/W-0h

11
10
GPIO85
R/W-0h

9
8
GPIO84
R/W-0h

7
6
GPIO83
R/W-0h

5
4
GPIO82
R/W-0h

3
2
GPIO81
R/W-0h

1
0
GPIO80
R/W-0h

Table 7-56. GPCMUX2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO95

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO94

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO93

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO92

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO91

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO90

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO89

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO88

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO87

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO86

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO85

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO84

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO83

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO82

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO81

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

989

Registers

www.ti.com

Table 7-56. GPCMUX2 Register Field Descriptions (continued)

990

Bit

Field

Type

Reset

Description

1-0

GPIO80

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.41 GPCDIR Register (Offset = 8Ah) [reset = 0h]
GPCDIR is shown in Figure 7-44 and described in Table 7-57.
Return to Summary Table.
GPIO C Direction Register (GPIO64 to 95)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 7-44. GPCDIR Register
31
GPIO95
R/W-0h

30
GPIO94
R/W-0h

29
GPIO93
R/W-0h

28
GPIO92
R/W-0h

27
GPIO91
R/W-0h

26
GPIO90
R/W-0h

25
GPIO89
R/W-0h

24
GPIO88
R/W-0h

23
GPIO87

22
GPIO86

21
GPIO85

20
GPIO84

19
GPIO83

18
GPIO82

17
GPIO81

16
GPIO80

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO79
R/W-0h

14
GPIO78
R/W-0h

13
GPIO77
R/W-0h

12
GPIO76
R/W-0h

11
GPIO75
R/W-0h

10
GPIO74
R/W-0h

9
GPIO73
R/W-0h

8
GPIO72
R/W-0h

7
GPIO71
R/W-0h

6
GPIO70
R/W-0h

5
GPIO69
R/W-0h

4
GPIO68
R/W-0h

3
GPIO67
R/W-0h

2
GPIO66
R/W-0h

1
GPIO65
R/W-0h

0
GPIO64
R/W-0h

Table 7-57. GPCDIR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

30

GPIO94

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

29

GPIO93

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

28

GPIO92

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

27

GPIO91

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

26

GPIO90

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

25

GPIO89

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

24

GPIO88

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

23

GPIO87

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

22

GPIO86

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

21

GPIO85

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

20

GPIO84

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

991

Registers

www.ti.com

Table 7-57. GPCDIR Register Field Descriptions (continued)

992

Bit

Field

Type

Reset

Description

19

GPIO83

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

18

GPIO82

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

17

GPIO81

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

16

GPIO80

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

15

GPIO79

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

14

GPIO78

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

13

GPIO77

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

12

GPIO76

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

11

GPIO75

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

10

GPIO74

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

9

GPIO73

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

8

GPIO72

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

7

GPIO71

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

6

GPIO70

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

5

GPIO69

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

4

GPIO68

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

3

GPIO67

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

2

GPIO66

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

1

GPIO65

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

0

GPIO64

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.42 GPCPUD Register (Offset = 8Ch) [reset = FFFFFFFFh]
GPCPUD is shown in Figure 7-45 and described in Table 7-58.
Return to Summary Table.
GPIO C Pull Up Disable Register (GPIO64 to 95)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 7-45. GPCPUD Register
31
GPIO95
R/W-1h

30
GPIO94
R/W-1h

29
GPIO93
R/W-1h

28
GPIO92
R/W-1h

27
GPIO91
R/W-1h

26
GPIO90
R/W-1h

25
GPIO89
R/W-1h

24
GPIO88
R/W-1h

23
GPIO87

22
GPIO86

21
GPIO85

20
GPIO84

19
GPIO83

18
GPIO82

17
GPIO81

16
GPIO80

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

15
GPIO79
R/W-1h

14
GPIO78
R/W-1h

13
GPIO77
R/W-1h

12
GPIO76
R/W-1h

11
GPIO75
R/W-1h

10
GPIO74
R/W-1h

9
GPIO73
R/W-1h

8
GPIO72
R/W-1h

7
GPIO71
R/W-1h

6
GPIO70
R/W-1h

5
GPIO69
R/W-1h

4
GPIO68
R/W-1h

3
GPIO67
R/W-1h

2
GPIO66
R/W-1h

1
GPIO65
R/W-1h

0
GPIO64
R/W-1h

Table 7-58. GPCPUD Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

30

GPIO94

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

29

GPIO93

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

28

GPIO92

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

27

GPIO91

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

26

GPIO90

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

25

GPIO89

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

24

GPIO88

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

23

GPIO87

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

22

GPIO86

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

21

GPIO85

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

20

GPIO84

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

993

Registers

www.ti.com

Table 7-58. GPCPUD Register Field Descriptions (continued)

994

Bit

Field

Type

Reset

Description

19

GPIO83

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

18

GPIO82

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

17

GPIO81

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

16

GPIO80

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

15

GPIO79

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

14

GPIO78

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

13

GPIO77

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

12

GPIO76

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

11

GPIO75

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

10

GPIO74

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

9

GPIO73

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

8

GPIO72

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

7

GPIO71

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

6

GPIO70

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

5

GPIO69

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

4

GPIO68

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

3

GPIO67

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

2

GPIO66

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

1

GPIO65

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

0

GPIO64

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.43 GPCINV Register (Offset = 90h) [reset = 0h]
GPCINV is shown in Figure 7-46 and described in Table 7-59.
Return to Summary Table.
GPIO C Input Polarity Invert Registers (GPIO64 to 95)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 7-46. GPCINV Register
31
GPIO95
R/W-0h

30
GPIO94
R/W-0h

29
GPIO93
R/W-0h

28
GPIO92
R/W-0h

27
GPIO91
R/W-0h

26
GPIO90
R/W-0h

25
GPIO89
R/W-0h

24
GPIO88
R/W-0h

23
GPIO87

22
GPIO86

21
GPIO85

20
GPIO84

19
GPIO83

18
GPIO82

17
GPIO81

16
GPIO80

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO79
R/W-0h

14
GPIO78
R/W-0h

13
GPIO77
R/W-0h

12
GPIO76
R/W-0h

11
GPIO75
R/W-0h

10
GPIO74
R/W-0h

9
GPIO73
R/W-0h

8
GPIO72
R/W-0h

7
GPIO71
R/W-0h

6
GPIO70
R/W-0h

5
GPIO69
R/W-0h

4
GPIO68
R/W-0h

3
GPIO67
R/W-0h

2
GPIO66
R/W-0h

1
GPIO65
R/W-0h

0
GPIO64
R/W-0h

Table 7-59. GPCINV Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

30

GPIO94

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

29

GPIO93

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

28

GPIO92

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

27

GPIO91

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

26

GPIO90

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

25

GPIO89

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

24

GPIO88

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

23

GPIO87

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

22

GPIO86

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

21

GPIO85

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

20

GPIO84

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

995

Registers

www.ti.com

Table 7-59. GPCINV Register Field Descriptions (continued)

996

Bit

Field

Type

Reset

Description

19

GPIO83

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

18

GPIO82

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

17

GPIO81

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

16

GPIO80

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

15

GPIO79

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

14

GPIO78

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

13

GPIO77

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

12

GPIO76

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

11

GPIO75

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

10

GPIO74

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

9

GPIO73

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

8

GPIO72

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

7

GPIO71

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

6

GPIO70

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

5

GPIO69

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

4

GPIO68

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

3

GPIO67

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

2

GPIO66

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

1

GPIO65

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

0

GPIO64

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.44 GPCODR Register (Offset = 92h) [reset = 0h]
GPCODR is shown in Figure 7-47 and described in Table 7-60.
Return to Summary Table.
GPIO C Open Drain Output Register (GPIO64 to GPIO95)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out
comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 7-47. GPCODR Register
31
GPIO95
R/W-0h

30
GPIO94
R/W-0h

29
GPIO93
R/W-0h

28
GPIO92
R/W-0h

27
GPIO91
R/W-0h

26
GPIO90
R/W-0h

25
GPIO89
R/W-0h

24
GPIO88
R/W-0h

23
GPIO87
R/W-0h

22
GPIO86
R/W-0h

21
GPIO85
R/W-0h

20
GPIO84
R/W-0h

19
GPIO83
R/W-0h

18
GPIO82
R/W-0h

17
GPIO81
R/W-0h

16
GPIO80
R/W-0h

15
GPIO79
R/W-0h

14
GPIO78
R/W-0h

13
GPIO77
R/W-0h

12
GPIO76
R/W-0h

11
GPIO75
R/W-0h

10
GPIO74
R/W-0h

9
GPIO73
R/W-0h

8
GPIO72
R/W-0h

7
GPIO71
R/W-0h

6
GPIO70
R/W-0h

5
GPIO69
R/W-0h

4
GPIO68
R/W-0h

3
GPIO67
R/W-0h

2
GPIO66
R/W-0h

1
GPIO65
R/W-0h

0
GPIO64
R/W-0h

Table 7-60. GPCODR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

30

GPIO94

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

29

GPIO93

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

28

GPIO92

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

27

GPIO91

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

26

GPIO90

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

25

GPIO89

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

24

GPIO88

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

23

GPIO87

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

22

GPIO86

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

997

Registers

www.ti.com

Table 7-60. GPCODR Register Field Descriptions (continued)

998

Bit

Field

Type

Reset

Description

21

GPIO85

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

20

GPIO84

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

19

GPIO83

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

18

GPIO82

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

17

GPIO81

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

16

GPIO80

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

15

GPIO79

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

14

GPIO78

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

13

GPIO77

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

12

GPIO76

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

11

GPIO75

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

10

GPIO74

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

9

GPIO73

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

8

GPIO72

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

7

GPIO71

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

6

GPIO70

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

5

GPIO69

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

4

GPIO68

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

3

GPIO67

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

2

GPIO66

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

1

GPIO65

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

0

GPIO64

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.45 GPCGMUX1 Register (Offset = A0h) [reset = 0h]
GPCGMUX1 is shown in Figure 7-48 and described in Table 7-61.
Return to Summary Table.
GPIO C Peripheral Group Mux (GPIO64 to 79)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-48. GPCGMUX1 Register
31
30
GPIO79
R/W-0h

29
28
GPIO78
R/W-0h

27
26
GPIO77
R/W-0h

25
24
GPIO76
R/W-0h

23
22
GPIO75
R/W-0h

21
20
GPIO74
R/W-0h

19
18
GPIO73
R/W-0h

17
16
GPIO72
R/W-0h

15
14
GPIO71
R/W-0h

13
12
GPIO70
R/W-0h

11
10
GPIO69
R/W-0h

9
8
GPIO68
R/W-0h

7
6
GPIO67
R/W-0h

5
4
GPIO66
R/W-0h

3
2
GPIO65
R/W-0h

1
0
GPIO64
R/W-0h

Table 7-61. GPCGMUX1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO79

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO78

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO77

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO76

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO75

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO74

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO73

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO72

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO71

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO70

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO69

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO68

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO67

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO66

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO65

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO64

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

999

Registers

www.ti.com

7.9.2.46 GPCGMUX2 Register (Offset = A2h) [reset = 0h]
GPCGMUX2 is shown in Figure 7-49 and described in Table 7-62.
Return to Summary Table.
GPIO C Peripheral Group Mux (GPIO80 to 95)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-49. GPCGMUX2 Register
31
30
GPIO95
R/W-0h

29
28
GPIO94
R/W-0h

27
26
GPIO93
R/W-0h

25
24
GPIO92
R/W-0h

23
22
GPIO91
R/W-0h

21
20
GPIO90
R/W-0h

19
18
GPIO89
R/W-0h

17
16
GPIO88
R/W-0h

15
14
GPIO87
R/W-0h

13
12
GPIO86
R/W-0h

11
10
GPIO85
R/W-0h

9
8
GPIO84
R/W-0h

7
6
GPIO83
R/W-0h

5
4
GPIO82
R/W-0h

3
2
GPIO81
R/W-0h

1
0
GPIO80
R/W-0h

Table 7-62. GPCGMUX2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO95

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO94

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO93

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO92

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO91

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO90

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO89

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO88

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO87

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO86

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO85

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO84

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO83

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO82

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO81

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO80

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1000

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.47 GPCCSEL1 Register (Offset = A8h) [reset = 0h]
GPCCSEL1 is shown in Figure 7-50 and described in Table 7-63.
Return to Summary Table.
GPIO C Core Select Register (GPIO64 to 71)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-50. GPCCSEL1 Register
31

30
29
GPIO71
R/W-0h

28

27

26
25
GPIO70
R/W-0h

24

23

22
21
GPIO69
R/W-0h

20

19

18
17
GPIO68
R/W-0h

16

15

14
13
GPIO67
R/W-0h

12

11

10
9
GPIO66
R/W-0h

8

7

6
5
GPIO65
R/W-0h

4

3

2
1
GPIO64
R/W-0h

0

Table 7-63. GPCCSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO71

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO70

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO69

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO68

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO67

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO66

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO65

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO64

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1001

Registers

www.ti.com

7.9.2.48 GPCCSEL2 Register (Offset = AAh) [reset = 0h]
GPCCSEL2 is shown in Figure 7-51 and described in Table 7-64.
Return to Summary Table.
GPIO C Core Select Register (GPIO72 to 79)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-51. GPCCSEL2 Register
31

30
29
GPIO79
R/W-0h

28

27

26
25
GPIO78
R/W-0h

24

23

22
21
GPIO77
R/W-0h

20

19

18
17
GPIO76
R/W-0h

16

15

14
13
GPIO75
R/W-0h

12

11

10
9
GPIO74
R/W-0h

8

7

6
5
GPIO73
R/W-0h

4

3

2
1
GPIO72
R/W-0h

0

Table 7-64. GPCCSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO79

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO78

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO77

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO76

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO75

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO74

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO73

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO72

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1002

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.49 GPCCSEL3 Register (Offset = ACh) [reset = 0h]
GPCCSEL3 is shown in Figure 7-52 and described in Table 7-65.
Return to Summary Table.
GPIO C Core Select Register (GPIO80 to 87)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-52. GPCCSEL3 Register
31

30
29
GPIO87
R/W-0h

28

27

26
25
GPIO86
R/W-0h

24

23

22
21
GPIO85
R/W-0h

20

19

18
17
GPIO84
R/W-0h

16

15

14
13
GPIO83
R/W-0h

12

11

10
9
GPIO82
R/W-0h

8

7

6
5
GPIO81
R/W-0h

4

3

2
1
GPIO80
R/W-0h

0

Table 7-65. GPCCSEL3 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO87

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO86

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO85

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO84

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO83

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO82

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO81

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO80

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1003

Registers

www.ti.com

7.9.2.50 GPCCSEL4 Register (Offset = AEh) [reset = 0h]
GPCCSEL4 is shown in Figure 7-53 and described in Table 7-66.
Return to Summary Table.
GPIO C Core Select Register (GPIO88 to 95)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-53. GPCCSEL4 Register
31

30
29
GPIO95
R/W-0h

28

27

26
25
GPIO94
R/W-0h

24

23

22
21
GPIO93
R/W-0h

20

19

18
17
GPIO92
R/W-0h

16

15

14
13
GPIO91
R/W-0h

12

11

10
9
GPIO90
R/W-0h

8

7

6
5
GPIO89
R/W-0h

4

3

2
1
GPIO88
R/W-0h

0

Table 7-66. GPCCSEL4 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO95

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO94

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO93

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO92

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO91

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO90

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO89

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO88

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1004

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.51 GPCLOCK Register (Offset = BCh) [reset = 0h]
GPCLOCK is shown in Figure 7-54 and described in Table 7-67.
Return to Summary Table.
GPIO C Lock Configuration Register (GPIO64 to 95)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2
and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL,
GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 7-54. GPCLOCK Register
31
GPIO95
R/W-0h

30
GPIO94
R/W-0h

29
GPIO93
R/W-0h

28
GPIO92
R/W-0h

27
GPIO91
R/W-0h

26
GPIO90
R/W-0h

25
GPIO89
R/W-0h

24
GPIO88
R/W-0h

23
GPIO87
R/W-0h

22
GPIO86
R/W-0h

21
GPIO85
R/W-0h

20
GPIO84
R/W-0h

19
GPIO83
R/W-0h

18
GPIO82
R/W-0h

17
GPIO81
R/W-0h

16
GPIO80
R/W-0h

15
GPIO79
R/W-0h

14
GPIO78
R/W-0h

13
GPIO77
R/W-0h

12
GPIO76
R/W-0h

11
GPIO75
R/W-0h

10
GPIO74
R/W-0h

9
GPIO73
R/W-0h

8
GPIO72
R/W-0h

7
GPIO71
R/W-0h

6
GPIO70
R/W-0h

5
GPIO69
R/W-0h

4
GPIO68
R/W-0h

3
GPIO67
R/W-0h

2
GPIO66
R/W-0h

1
GPIO65
R/W-0h

0
GPIO64
R/W-0h

Table 7-67. GPCLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

30

GPIO94

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

29

GPIO93

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

28

GPIO92

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

27

GPIO91

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

26

GPIO90

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

25

GPIO89

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

24

GPIO88

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

23

GPIO87

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

22

GPIO86

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

21

GPIO85

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1005

Registers

www.ti.com

Table 7-67. GPCLOCK Register Field Descriptions (continued)

1006

Bit

Field

Type

Reset

Description

20

GPIO84

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

19

GPIO83

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

18

GPIO82

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

17

GPIO81

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

16

GPIO80

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

15

GPIO79

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

14

GPIO78

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

13

GPIO77

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

12

GPIO76

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

11

GPIO75

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

10

GPIO74

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

9

GPIO73

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

8

GPIO72

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

7

GPIO71

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

6

GPIO70

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

5

GPIO69

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

4

GPIO68

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

3

GPIO67

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

2

GPIO66

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

1

GPIO65

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

0

GPIO64

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.52 GPCCR Register (Offset = BEh) [reset = 0h]
GPCCR is shown in Figure 7-55 and described in Table 7-68.
Return to Summary Table.
GPIO C Lock Commit Register (GPIO64 to 95)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 7-55. GPCCR Register
31
GPIO95
R/WOnce-0h

30
GPIO94
R/WOnce-0h

29
GPIO93
R/WOnce-0h

28
GPIO92
R/WOnce-0h

27
GPIO91
R/WOnce-0h

26
GPIO90
R/WOnce-0h

25
GPIO89
R/WOnce-0h

24
GPIO88
R/WOnce-0h

23
GPIO87
R/WOnce-0h

22
GPIO86
R/WOnce-0h

21
GPIO85
R/WOnce-0h

20
GPIO84
R/WOnce-0h

19
GPIO83
R/WOnce-0h

18
GPIO82
R/WOnce-0h

17
GPIO81
R/WOnce-0h

16
GPIO80
R/WOnce-0h

15
GPIO79
R/WOnce-0h

14
GPIO78
R/WOnce-0h

13
GPIO77
R/WOnce-0h

12
GPIO76
R/WOnce-0h

11
GPIO75
R/WOnce-0h

10
GPIO74
R/WOnce-0h

9
GPIO73
R/WOnce-0h

8
GPIO72
R/WOnce-0h

7
GPIO71
R/WOnce-0h

6
GPIO70
R/WOnce-0h

5
GPIO69
R/WOnce-0h

4
GPIO68
R/WOnce-0h

3
GPIO67
R/WOnce-0h

2
GPIO66
R/WOnce-0h

1
GPIO65
R/WOnce-0h

0
GPIO64
R/WOnce-0h

Table 7-68. GPCCR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

30

GPIO94

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

29

GPIO93

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

28

GPIO92

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

27

GPIO91

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

26

GPIO90

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

25

GPIO89

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

24

GPIO88

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

23

GPIO87

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

22

GPIO86

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

21

GPIO85

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

20

GPIO84

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1007

Registers

www.ti.com

Table 7-68. GPCCR Register Field Descriptions (continued)

1008

Bit

Field

Type

Reset

Description

19

GPIO83

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

18

GPIO82

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

17

GPIO81

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

16

GPIO80

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

15

GPIO79

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

14

GPIO78

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

13

GPIO77

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

12

GPIO76

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

11

GPIO75

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

10

GPIO74

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

9

GPIO73

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

8

GPIO72

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

7

GPIO71

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

6

GPIO70

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

5

GPIO69

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

4

GPIO68

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

3

GPIO67

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

2

GPIO66

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

1

GPIO65

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

0

GPIO64

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.53 GPDCTRL Register (Offset = C0h) [reset = 0h]
GPDCTRL is shown in Figure 7-56 and described in Table 7-69.
Return to Summary Table.
GPIO D Qualification Sampling Period Control (GPIO96 to 127)
Figure 7-56. GPDCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUALPRD3
QUALPRD2
QUALPRD1
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5 4 3 2
QUALPRD0
R/W-0h

1

0

Table 7-69. GPDCTRL Register Field Descriptions
Bit
31-24

Field

Type

Reset

Description

QUALPRD3

R/W

0h

Qualification sampling period for GPIO120 to GPIO127:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

23-16

QUALPRD2

R/W

0h

Qualification sampling period for GPIO112 to GPIO119:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

15-8

QUALPRD1

R/W

0h

Qualification sampling period for GPIO104 to GPIO111:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

7-0

QUALPRD0

R/W

0h

Qualification sampling period for GPIO96 to GPIO103:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1009

Registers

www.ti.com

7.9.2.54 GPDQSEL1 Register (Offset = C2h) [reset = 0h]
GPDQSEL1 is shown in Figure 7-57 and described in Table 7-70.
Return to Summary Table.
GPIO D Qualifier Select 1 Register (GPIO96 to 111)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-57. GPDQSEL1 Register
31

30

29

28

GPIO111
R/W-0h
23

22

21

14

7

19

GPIO106
R/W-0h
13

6

5

17

4

10

3

16
GPIO104
R/W-0h

9

GPIO101
R/W-0h

8
GPIO100
R/W-0h

2

GPIO98
R/W-0h

24
GPIO108
R/W-0h

18

11

GPIO102
R/W-0h

GPIO99
R/W-0h

25

GPIO105
R/W-0h
12

GPIO103
R/W-0h

26
GPIO109
R/W-0h

20

GPIO107
R/W-0h
15

27

GPIO110
R/W-0h

GPIO97
R/W-0h

1

0
GPIO96
R/W-0h

Table 7-70. GPDQSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO111

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO110

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO109

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO108

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO107

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO106

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO105

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO104

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO103

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO102

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO101

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO100

R/W

0h

Input qualification type
Reset type: SYSRSn

1010

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-70. GPDQSEL1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

GPIO99

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO98

R/W

0h

Input qualification type
Reset type: SYSRSn

3-2

GPIO97

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO96

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1011

Registers

www.ti.com

7.9.2.55 GPDQSEL2 Register (Offset = C4h) [reset = 0h]
GPDQSEL2 is shown in Figure 7-58 and described in Table 7-71.
Return to Summary Table.
GPIO D Qualifier Select 2 Register (GPIO112 to 127)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-58. GPDQSEL2 Register
31

30

29

28

GPIO127
R/W-0h
23

22

21

14

7

19

GPIO122
R/W-0h
13

6

5

17

4

10

3

16
GPIO120
R/W-0h

9

GPIO117
R/W-0h

GPIO114
R/W-0h

24
GPIO124
R/W-0h

18

11

GPIO118
R/W-0h

GPIO115
R/W-0h

25

GPIO121
R/W-0h
12

GPIO119
R/W-0h

26
GPIO125
R/W-0h

20

GPIO123
R/W-0h
15

27

GPIO126
R/W-0h

8
GPIO116
R/W-0h

2
GPIO113
R/W-0h

1

0
GPIO112
R/W-0h

Table 7-71. GPDQSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO127

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO126

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO125

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO124

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO123

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO122

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO121

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO120

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO119

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO118

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO117

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO116

R/W

0h

Input qualification type
Reset type: SYSRSn

1012

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-71. GPDQSEL2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

GPIO115

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO114

R/W

0h

Input qualification type
Reset type: SYSRSn

3-2

GPIO113

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO112

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1013

Registers

www.ti.com

7.9.2.56 GPDMUX1 Register (Offset = C6h) [reset = 0h]
GPDMUX1 is shown in Figure 7-59 and described in Table 7-72.
Return to Summary Table.
GPIO D Mux 1 Register (GPIO96 to 111)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-59. GPDMUX1 Register
31

30

29

28

GPIO111
R/W-0h
23

22

21

14

7

19

GPIO106
R/W-0h
13

6

5

17

4

10

3

16
GPIO104
R/W-0h

9

GPIO101
R/W-0h

8
GPIO100
R/W-0h

2

GPIO98
R/W-0h

24
GPIO108
R/W-0h

18

11

GPIO102
R/W-0h

GPIO99
R/W-0h

25

GPIO105
R/W-0h
12

GPIO103
R/W-0h

26
GPIO109
R/W-0h

20

GPIO107
R/W-0h
15

27

GPIO110
R/W-0h

GPIO97
R/W-0h

1

0
GPIO96
R/W-0h

Table 7-72. GPDMUX1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO111

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO110

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO109

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO108

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO107

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO106

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO105

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO104

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO103

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO102

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO101

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO100

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1014

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-72. GPDMUX1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

GPIO99

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO98

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO97

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO96

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1015

Registers

www.ti.com

7.9.2.57 GPDMUX2 Register (Offset = C8h) [reset = 0h]
GPDMUX2 is shown in Figure 7-60 and described in Table 7-73.
Return to Summary Table.
GPIO D Mux 2 Register (GPIO112 to 127)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-60. GPDMUX2 Register
31

30

29

28

GPIO127
R/W-0h
23

22

21

14

7

19

GPIO122
R/W-0h
13

6

5

17

4

10

3

16
GPIO120
R/W-0h

9

GPIO117
R/W-0h

GPIO114
R/W-0h

24
GPIO124
R/W-0h

18

11

GPIO118
R/W-0h

GPIO115
R/W-0h

25

GPIO121
R/W-0h
12

GPIO119
R/W-0h

26
GPIO125
R/W-0h

20

GPIO123
R/W-0h
15

27

GPIO126
R/W-0h

8
GPIO116
R/W-0h

2
GPIO113
R/W-0h

1

0
GPIO112
R/W-0h

Table 7-73. GPDMUX2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO127

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO126

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO125

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO124

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO123

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO122

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO121

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO120

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO119

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO118

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO117

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO116

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1016

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-73. GPDMUX2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

GPIO115

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO114

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO113

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO112

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1017

Registers

www.ti.com

7.9.2.58 GPDDIR Register (Offset = CAh) [reset = 0h]
GPDDIR is shown in Figure 7-61 and described in Table 7-74.
Return to Summary Table.
GPIO D Direction Register (GPIO96 to 127)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 7-61. GPDDIR Register
31
GPIO127
R/W-0h

30
GPIO126
R/W-0h

29
GPIO125
R/W-0h

28
GPIO124
R/W-0h

27
GPIO123
R/W-0h

26
GPIO122
R/W-0h

25
GPIO121
R/W-0h

24
GPIO120
R/W-0h

23
GPIO119

22
GPIO118

21
GPIO117

20
GPIO116

19
GPIO115

18
GPIO114

17
GPIO113

16
GPIO112

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO111
R/W-0h

14
GPIO110
R/W-0h

13
GPIO109
R/W-0h

12
GPIO108
R/W-0h

11
GPIO107
R/W-0h

10
GPIO106
R/W-0h

9
GPIO105
R/W-0h

8
GPIO104
R/W-0h

7
GPIO103
R/W-0h

6
GPIO102
R/W-0h

5
GPIO101
R/W-0h

4
GPIO100
R/W-0h

3
GPIO99
R/W-0h

2
GPIO98
R/W-0h

1
GPIO97
R/W-0h

0
GPIO96
R/W-0h

Table 7-74. GPDDIR Register Field Descriptions

1018

Bit

Field

Type

Reset

Description

31

GPIO127

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

30

GPIO126

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

29

GPIO125

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

28

GPIO124

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

27

GPIO123

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

26

GPIO122

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

25

GPIO121

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

24

GPIO120

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

23

GPIO119

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

22

GPIO118

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

21

GPIO117

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

20

GPIO116

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-74. GPDDIR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

GPIO115

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

18

GPIO114

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

17

GPIO113

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

16

GPIO112

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

15

GPIO111

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

14

GPIO110

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

13

GPIO109

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

12

GPIO108

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

11

GPIO107

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

10

GPIO106

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

9

GPIO105

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

8

GPIO104

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

7

GPIO103

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

6

GPIO102

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

5

GPIO101

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

4

GPIO100

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

3

GPIO99

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

2

GPIO98

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

1

GPIO97

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

0

GPIO96

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1019

Registers

www.ti.com

7.9.2.59 GPDPUD Register (Offset = CCh) [reset = FFFFFFFFh]
GPDPUD is shown in Figure 7-62 and described in Table 7-75.
Return to Summary Table.
GPIO D Pull Up Disable Register (GPIO96 to 127)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 7-62. GPDPUD Register
31
GPIO127
R/W-1h

30
GPIO126
R/W-1h

29
GPIO125
R/W-1h

28
GPIO124
R/W-1h

27
GPIO123
R/W-1h

26
GPIO122
R/W-1h

25
GPIO121
R/W-1h

24
GPIO120
R/W-1h

23
GPIO119

22
GPIO118

21
GPIO117

20
GPIO116

19
GPIO115

18
GPIO114

17
GPIO113

16
GPIO112

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

15
GPIO111
R/W-1h

14
GPIO110
R/W-1h

13
GPIO109
R/W-1h

12
GPIO108
R/W-1h

11
GPIO107
R/W-1h

10
GPIO106
R/W-1h

9
GPIO105
R/W-1h

8
GPIO104
R/W-1h

7
GPIO103
R/W-1h

6
GPIO102
R/W-1h

5
GPIO101
R/W-1h

4
GPIO100
R/W-1h

3
GPIO99
R/W-1h

2
GPIO98
R/W-1h

1
GPIO97
R/W-1h

0
GPIO96
R/W-1h

Table 7-75. GPDPUD Register Field Descriptions

1020

Bit

Field

Type

Reset

Description

31

GPIO127

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

30

GPIO126

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

29

GPIO125

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

28

GPIO124

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

27

GPIO123

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

26

GPIO122

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

25

GPIO121

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

24

GPIO120

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

23

GPIO119

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

22

GPIO118

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

21

GPIO117

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

20

GPIO116

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-75. GPDPUD Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

GPIO115

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

18

GPIO114

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

17

GPIO113

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

16

GPIO112

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

15

GPIO111

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

14

GPIO110

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

13

GPIO109

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

12

GPIO108

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

11

GPIO107

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

10

GPIO106

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

9

GPIO105

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

8

GPIO104

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

7

GPIO103

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

6

GPIO102

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

5

GPIO101

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

4

GPIO100

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

3

GPIO99

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

2

GPIO98

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

1

GPIO97

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

0

GPIO96

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1021

Registers

www.ti.com

7.9.2.60 GPDINV Register (Offset = D0h) [reset = 0h]
GPDINV is shown in Figure 7-63 and described in Table 7-76.
Return to Summary Table.
GPIO D Input Polarity Invert Registers (GPIO96 to 127)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 7-63. GPDINV Register
31
GPIO127
R/W-0h

30
GPIO126
R/W-0h

29
GPIO125
R/W-0h

28
GPIO124
R/W-0h

27
GPIO123
R/W-0h

26
GPIO122
R/W-0h

25
GPIO121
R/W-0h

24
GPIO120
R/W-0h

23
GPIO119

22
GPIO118

21
GPIO117

20
GPIO116

19
GPIO115

18
GPIO114

17
GPIO113

16
GPIO112

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO111
R/W-0h

14
GPIO110
R/W-0h

13
GPIO109
R/W-0h

12
GPIO108
R/W-0h

11
GPIO107
R/W-0h

10
GPIO106
R/W-0h

9
GPIO105
R/W-0h

8
GPIO104
R/W-0h

7
GPIO103
R/W-0h

6
GPIO102
R/W-0h

5
GPIO101
R/W-0h

4
GPIO100
R/W-0h

3
GPIO99
R/W-0h

2
GPIO98
R/W-0h

1
GPIO97
R/W-0h

0
GPIO96
R/W-0h

Table 7-76. GPDINV Register Field Descriptions

1022

Bit

Field

Type

Reset

Description

31

GPIO127

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

30

GPIO126

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

29

GPIO125

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

28

GPIO124

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

27

GPIO123

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

26

GPIO122

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

25

GPIO121

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

24

GPIO120

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

23

GPIO119

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

22

GPIO118

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

21

GPIO117

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

20

GPIO116

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-76. GPDINV Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

GPIO115

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

18

GPIO114

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

17

GPIO113

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

16

GPIO112

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

15

GPIO111

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

14

GPIO110

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

13

GPIO109

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

12

GPIO108

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

11

GPIO107

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

10

GPIO106

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

9

GPIO105

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

8

GPIO104

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

7

GPIO103

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

6

GPIO102

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

5

GPIO101

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

4

GPIO100

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

3

GPIO99

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

2

GPIO98

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

1

GPIO97

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

0

GPIO96

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1023

Registers

www.ti.com

7.9.2.61 GPDODR Register (Offset = D2h) [reset = 0h]
GPDODR is shown in Figure 7-64 and described in Table 7-77.
Return to Summary Table.
GPIO D Open Drain Output Register (GPIO96 to GPIO127)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out
comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 7-64. GPDODR Register
31
GPIO127
R/W-0h

30
GPIO126
R/W-0h

29
GPIO125
R/W-0h

28
GPIO124
R/W-0h

27
GPIO123
R/W-0h

26
GPIO122
R/W-0h

25
GPIO121
R/W-0h

24
GPIO120
R/W-0h

23
GPIO119
R/W-0h

22
GPIO118
R/W-0h

21
GPIO117
R/W-0h

20
GPIO116
R/W-0h

19
GPIO115
R/W-0h

18
GPIO114
R/W-0h

17
GPIO113
R/W-0h

16
GPIO112
R/W-0h

15
GPIO111
R/W-0h

14
GPIO110
R/W-0h

13
GPIO109
R/W-0h

12
GPIO108
R/W-0h

11
GPIO107
R/W-0h

10
GPIO106
R/W-0h

9
GPIO105
R/W-0h

8
GPIO104
R/W-0h

7
GPIO103
R/W-0h

6
GPIO102
R/W-0h

5
GPIO101
R/W-0h

4
GPIO100
R/W-0h

3
GPIO99
R/W-0h

2
GPIO98
R/W-0h

1
GPIO97
R/W-0h

0
GPIO96
R/W-0h

Table 7-77. GPDODR Register Field Descriptions

1024

Bit

Field

Type

Reset

Description

31

GPIO127

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

30

GPIO126

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

29

GPIO125

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

28

GPIO124

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

27

GPIO123

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

26

GPIO122

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

25

GPIO121

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

24

GPIO120

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

23

GPIO119

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

22

GPIO118

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-77. GPDODR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

21

GPIO117

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

20

GPIO116

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

19

GPIO115

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

18

GPIO114

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

17

GPIO113

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

16

GPIO112

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

15

GPIO111

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

14

GPIO110

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

13

GPIO109

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

12

GPIO108

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

11

GPIO107

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

10

GPIO106

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

9

GPIO105

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

8

GPIO104

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

7

GPIO103

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

6

GPIO102

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

5

GPIO101

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

4

GPIO100

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

3

GPIO99

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

2

GPIO98

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

1

GPIO97

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

0

GPIO96

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1025

Registers

www.ti.com

7.9.2.62 GPDGMUX1 Register (Offset = E0h) [reset = 0h]
GPDGMUX1 is shown in Figure 7-65 and described in Table 7-78.
Return to Summary Table.
GPIO D Peripheral Group Mux (GPIO96 to 111)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-65. GPDGMUX1 Register
31

30

29

28

GPIO111
R/W-0h
23

22

21

14

7

19

GPIO106
R/W-0h
13

6

5

17

4

10

3

16
GPIO104
R/W-0h

9

GPIO101
R/W-0h

8
GPIO100
R/W-0h

2

GPIO98
R/W-0h

24
GPIO108
R/W-0h

18

11

GPIO102
R/W-0h

GPIO99
R/W-0h

25

GPIO105
R/W-0h
12

GPIO103
R/W-0h

26
GPIO109
R/W-0h

20

GPIO107
R/W-0h
15

27

GPIO110
R/W-0h

GPIO97
R/W-0h

1

0
GPIO96
R/W-0h

Table 7-78. GPDGMUX1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO111

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO110

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO109

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO108

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO107

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO106

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO105

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO104

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO103

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO102

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO101

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO100

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO99

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1026

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-78. GPDGMUX1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-4

GPIO98

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO97

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO96

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1027

Registers

www.ti.com

7.9.2.63 GPDGMUX2 Register (Offset = E2h) [reset = 0h]
GPDGMUX2 is shown in Figure 7-66 and described in Table 7-79.
Return to Summary Table.
GPIO D Peripheral Group Mux (GPIO112 to 127)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-66. GPDGMUX2 Register
31

30

29

28

GPIO127
R/W-0h
23

22

21

14

7

19

GPIO122
R/W-0h
13

6

5

17

4

10

3

16
GPIO120
R/W-0h

9

GPIO117
R/W-0h

GPIO114
R/W-0h

24
GPIO124
R/W-0h

18

11

GPIO118
R/W-0h

GPIO115
R/W-0h

25

GPIO121
R/W-0h
12

GPIO119
R/W-0h

26
GPIO125
R/W-0h

20

GPIO123
R/W-0h
15

27

GPIO126
R/W-0h

8
GPIO116
R/W-0h

2
GPIO113
R/W-0h

1

0
GPIO112
R/W-0h

Table 7-79. GPDGMUX2 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO127

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO126

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO125

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO124

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO123

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO122

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO121

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO120

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO119

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO118

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO117

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO116

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO115

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1028

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-79. GPDGMUX2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-4

GPIO114

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO113

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO112

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1029

Registers

www.ti.com

7.9.2.64 GPDCSEL1 Register (Offset = E8h) [reset = 0h]
GPDCSEL1 is shown in Figure 7-67 and described in Table 7-80.
Return to Summary Table.
GPIO D Core Select Register (GPIO96 to 103)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-67. GPDCSEL1 Register
31

30
29
GPIO103
R/W-0h

28

27

26
25
GPIO102
R/W-0h

24

23

22
21
GPIO101
R/W-0h

20

19

18
17
GPIO100
R/W-0h

16

15

14
13
GPIO99
R/W-0h

12

11

10
9
GPIO98
R/W-0h

8

7

6
5
GPIO97
R/W-0h

4

3

2
1
GPIO96
R/W-0h

0

Table 7-80. GPDCSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO103

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO102

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO101

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO100

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO99

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO98

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO97

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO96

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1030

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.65 GPDCSEL2 Register (Offset = EAh) [reset = 0h]
GPDCSEL2 is shown in Figure 7-68 and described in Table 7-81.
Return to Summary Table.
GPIO D Core Select Register (GPIO104 to 111)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-68. GPDCSEL2 Register
31

30
29
GPIO111
R/W-0h

28

27

26
25
GPIO110
R/W-0h

24

23

22
21
GPIO109
R/W-0h

20

19

18
17
GPIO108
R/W-0h

16

15

14
13
GPIO107
R/W-0h

12

11

10
9
GPIO106
R/W-0h

8

7

6
5
GPIO105
R/W-0h

4

3

2
1
GPIO104
R/W-0h

0

Table 7-81. GPDCSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO111

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO110

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO109

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO108

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO107

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO106

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO105

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO104

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1031

Registers

www.ti.com

7.9.2.66 GPDCSEL3 Register (Offset = ECh) [reset = 0h]
GPDCSEL3 is shown in Figure 7-69 and described in Table 7-82.
Return to Summary Table.
GPIO D Core Select Register (GPIO112 to 119)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-69. GPDCSEL3 Register
31

30
29
GPIO119
R/W-0h

28

27

26
25
GPIO118
R/W-0h

24

23

22
21
GPIO117
R/W-0h

20

19

18
17
GPIO116
R/W-0h

16

15

14
13
GPIO115
R/W-0h

12

11

10
9
GPIO114
R/W-0h

8

7

6
5
GPIO113
R/W-0h

4

3

2
1
GPIO112
R/W-0h

0

Table 7-82. GPDCSEL3 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO119

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO118

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO117

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO116

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO115

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO114

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO113

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO112

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1032

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.67 GPDCSEL4 Register (Offset = EEh) [reset = 0h]
GPDCSEL4 is shown in Figure 7-70 and described in Table 7-83.
Return to Summary Table.
GPIO D Core Select Register (GPIO120 to 127)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-70. GPDCSEL4 Register
31

30
29
GPIO127
R/W-0h

28

27

26
25
GPIO126
R/W-0h

24

23

22
21
GPIO125
R/W-0h

20

19

18
17
GPIO124
R/W-0h

16

15

14
13
GPIO123
R/W-0h

12

11

10
9
GPIO122
R/W-0h

8

7

6
5
GPIO121
R/W-0h

4

3

2
1
GPIO120
R/W-0h

0

Table 7-83. GPDCSEL4 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO127

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO126

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO125

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO124

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO123

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO122

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO121

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO120

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1033

Registers

www.ti.com

7.9.2.68 GPDLOCK Register (Offset = FCh) [reset = 0h]
GPDLOCK is shown in Figure 7-71 and described in Table 7-84.
Return to Summary Table.
GPIO D Lock Configuration Register (GPIO96 to 127)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2
and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL,
GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 7-71. GPDLOCK Register
31
GPIO127
R/W-0h

30
GPIO126
R/W-0h

29
GPIO125
R/W-0h

28
GPIO124
R/W-0h

27
GPIO123
R/W-0h

26
GPIO122
R/W-0h

25
GPIO121
R/W-0h

24
GPIO120
R/W-0h

23
GPIO119
R/W-0h

22
GPIO118
R/W-0h

21
GPIO117
R/W-0h

20
GPIO116
R/W-0h

19
GPIO115
R/W-0h

18
GPIO114
R/W-0h

17
GPIO113
R/W-0h

16
GPIO112
R/W-0h

15
GPIO111
R/W-0h

14
GPIO110
R/W-0h

13
GPIO109
R/W-0h

12
GPIO108
R/W-0h

11
GPIO107
R/W-0h

10
GPIO106
R/W-0h

9
GPIO105
R/W-0h

8
GPIO104
R/W-0h

7
GPIO103
R/W-0h

6
GPIO102
R/W-0h

5
GPIO101
R/W-0h

4
GPIO100
R/W-0h

3
GPIO99
R/W-0h

2
GPIO98
R/W-0h

1
GPIO97
R/W-0h

0
GPIO96
R/W-0h

Table 7-84. GPDLOCK Register Field Descriptions

1034

Bit

Field

Type

Reset

Description

31

GPIO127

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

30

GPIO126

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

29

GPIO125

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

28

GPIO124

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

27

GPIO123

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

26

GPIO122

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

25

GPIO121

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

24

GPIO120

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

23

GPIO119

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

22

GPIO118

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

21

GPIO117

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-84. GPDLOCK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

GPIO116

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

19

GPIO115

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

18

GPIO114

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

17

GPIO113

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

16

GPIO112

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

15

GPIO111

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

14

GPIO110

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

13

GPIO109

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

12

GPIO108

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

11

GPIO107

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

10

GPIO106

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

9

GPIO105

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

8

GPIO104

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

7

GPIO103

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

6

GPIO102

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

5

GPIO101

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

4

GPIO100

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

3

GPIO99

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

2

GPIO98

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

1

GPIO97

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

0

GPIO96

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1035

Registers

www.ti.com

7.9.2.69 GPDCR Register (Offset = FEh) [reset = 0h]
GPDCR is shown in Figure 7-72 and described in Table 7-85.
Return to Summary Table.
GPIO D Lock Commit Register (GPIO96 to 127)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 7-72. GPDCR Register
31
GPIO127
R/WOnce-0h

30
GPIO126
R/WOnce-0h

29
GPIO125
R/WOnce-0h

28
GPIO124
R/WOnce-0h

27
GPIO123
R/WOnce-0h

26
GPIO122
R/WOnce-0h

25
GPIO121
R/WOnce-0h

24
GPIO120
R/WOnce-0h

23
GPIO119
R/WOnce-0h

22
GPIO118
R/WOnce-0h

21
GPIO117
R/WOnce-0h

20
GPIO116
R/WOnce-0h

19
GPIO115
R/WOnce-0h

18
GPIO114
R/WOnce-0h

17
GPIO113
R/WOnce-0h

16
GPIO112
R/WOnce-0h

15
GPIO111
R/WOnce-0h

14
GPIO110
R/WOnce-0h

13
GPIO109
R/WOnce-0h

12
GPIO108
R/WOnce-0h

11
GPIO107
R/WOnce-0h

10
GPIO106
R/WOnce-0h

9
GPIO105
R/WOnce-0h

8
GPIO104
R/WOnce-0h

7
GPIO103
R/WOnce-0h

6
GPIO102
R/WOnce-0h

5
GPIO101
R/WOnce-0h

4
GPIO100
R/WOnce-0h

3
GPIO99
R/WOnce-0h

2
GPIO98
R/WOnce-0h

1
GPIO97
R/WOnce-0h

0
GPIO96
R/WOnce-0h

Table 7-85. GPDCR Register Field Descriptions

1036

Bit

Field

Type

Reset

Description

31

GPIO127

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

30

GPIO126

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

29

GPIO125

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

28

GPIO124

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

27

GPIO123

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

26

GPIO122

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

25

GPIO121

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

24

GPIO120

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

23

GPIO119

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

22

GPIO118

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

21

GPIO117

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

20

GPIO116

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-85. GPDCR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

GPIO115

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

18

GPIO114

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

17

GPIO113

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

16

GPIO112

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

15

GPIO111

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

14

GPIO110

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

13

GPIO109

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

12

GPIO108

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

11

GPIO107

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

10

GPIO106

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

9

GPIO105

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

8

GPIO104

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

7

GPIO103

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

6

GPIO102

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

5

GPIO101

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

4

GPIO100

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

3

GPIO99

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

2

GPIO98

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

1

GPIO97

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

0

GPIO96

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1037

Registers

www.ti.com

7.9.2.70 GPECTRL Register (Offset = 100h) [reset = 0h]
GPECTRL is shown in Figure 7-73 and described in Table 7-86.
Return to Summary Table.
GPIO E Qualification Sampling Period Control (GPIO128 to 159)
Figure 7-73. GPECTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUALPRD3
QUALPRD2
QUALPRD1
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5 4 3 2
QUALPRD0
R/W-0h

1

0

Table 7-86. GPECTRL Register Field Descriptions
Bit
31-24

Field

Type

Reset

Description

QUALPRD3

R/W

0h

Qualification sampling period for GPIO152 to GPIO159:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

23-16

QUALPRD2

R/W

0h

Qualification sampling period for GPIO144 to GPIO151:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

15-8

QUALPRD1

R/W

0h

Qualification sampling period for GPIO136 to GPIO143:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

7-0

QUALPRD0

R/W

0h

Qualification sampling period for GPIO128 to GPIO135:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

1038

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.71 GPEQSEL1 Register (Offset = 102h) [reset = 0h]
GPEQSEL1 is shown in Figure 7-74 and described in Table 7-87.
Return to Summary Table.
GPIO E Qualifier Select 1 Register (GPIO128 to 143)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-74. GPEQSEL1 Register
31

30

29

28

GPIO143
R/W-0h
23

22

21

14

13

7

6

12

5

18

4

16
GPIO136
R/W-0h

11

10

9

GPIO133
R/W-0h

GPIO130
R/W-0h

24

17

GPIO137
R/W-0h

GPIO134
R/W-0h

GPIO131
R/W-0h

25
GPIO140
R/W-0h

19

GPIO138
R/W-0h

GPIO135
R/W-0h

26
GPIO141
R/W-0h

20

GPIO139
R/W-0h
15

27

GPIO142
R/W-0h

8
GPIO132
R/W-0h

3

2
GPIO129
R/W-0h

1

0
GPIO128
R/W-0h

Table 7-87. GPEQSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO143

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO142

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO141

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO140

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO139

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO138

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO137

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO136

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO135

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO134

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO133

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO132

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1039

Registers

www.ti.com

Table 7-87. GPEQSEL1 Register Field Descriptions (continued)

1040

Bit

Field

Type

Reset

Description

7-6

GPIO131

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO130

R/W

0h

Input qualification type
Reset type: SYSRSn

3-2

GPIO129

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO128

R/W

0h

Input qualification type
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.72 GPEQSEL2 Register (Offset = 104h) [reset = 0h]
GPEQSEL2 is shown in Figure 7-75 and described in Table 7-88.
Return to Summary Table.
GPIO E Qualifier Select 2 Register (GPIO144 to 159)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-75. GPEQSEL2 Register
31

30

29

28

GPIO159
R/W-0h
23

22

21

14

13

7

6

12

5

18

4

16
GPIO152
R/W-0h

11

10

9

GPIO149
R/W-0h

GPIO146
R/W-0h

24

17

GPIO153
R/W-0h

GPIO150
R/W-0h

GPIO147
R/W-0h

25
GPIO156
R/W-0h

19

GPIO154
R/W-0h

GPIO151
R/W-0h

26
GPIO157
R/W-0h

20

GPIO155
R/W-0h
15

27

GPIO158
R/W-0h

8
GPIO148
R/W-0h

3

2
GPIO145
R/W-0h

1

0
GPIO144
R/W-0h

Table 7-88. GPEQSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO159

R/W

0h

Input qualification type
Reset type: SYSRSn

29-28

GPIO158

R/W

0h

Input qualification type
Reset type: SYSRSn

27-26

GPIO157

R/W

0h

Input qualification type
Reset type: SYSRSn

25-24

GPIO156

R/W

0h

Input qualification type
Reset type: SYSRSn

23-22

GPIO155

R/W

0h

Input qualification type
Reset type: SYSRSn

21-20

GPIO154

R/W

0h

Input qualification type
Reset type: SYSRSn

19-18

GPIO153

R/W

0h

Input qualification type
Reset type: SYSRSn

17-16

GPIO152

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO151

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO150

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO149

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO148

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1041

Registers

www.ti.com

Table 7-88. GPEQSEL2 Register Field Descriptions (continued)

1042

Bit

Field

Type

Reset

Description

7-6

GPIO147

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO146

R/W

0h

Input qualification type
Reset type: SYSRSn

3-2

GPIO145

R/W

0h

Input qualification type
Reset type: SYSRSn

1-0

GPIO144

R/W

0h

Input qualification type
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.73 GPEMUX1 Register (Offset = 106h) [reset = 0h]
GPEMUX1 is shown in Figure 7-76 and described in Table 7-89.
Return to Summary Table.
GPIO E Mux 1 Register (GPIO128 to 143)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-76. GPEMUX1 Register
31

30

29

28

GPIO143
R/W-0h
23

22

21

14

13

7

6

12

5

18

4

16
GPIO136
R/W-0h

11

10

9

GPIO133
R/W-0h

GPIO130
R/W-0h

24

17

GPIO137
R/W-0h

GPIO134
R/W-0h

GPIO131
R/W-0h

25
GPIO140
R/W-0h

19

GPIO138
R/W-0h

GPIO135
R/W-0h

26
GPIO141
R/W-0h

20

GPIO139
R/W-0h
15

27

GPIO142
R/W-0h

8
GPIO132
R/W-0h

3

2
GPIO129
R/W-0h

1

0
GPIO128
R/W-0h

Table 7-89. GPEMUX1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO143

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO142

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO141

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO140

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO139

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO138

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO137

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO136

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO135

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO134

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO133

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO132

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1043

Registers

www.ti.com

Table 7-89. GPEMUX1 Register Field Descriptions (continued)

1044

Bit

Field

Type

Reset

Description

7-6

GPIO131

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO130

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO129

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO128

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.74 GPEMUX2 Register (Offset = 108h) [reset = 0h]
GPEMUX2 is shown in Figure 7-77 and described in Table 7-90.
Return to Summary Table.
GPIO E Mux 2 Register (GPIO144 to 159)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-77. GPEMUX2 Register
31

30

29

28

GPIO159
R/W-0h
23

22

21

14

13

7

6

12

5

18

4

16
GPIO152
R/W-0h

11

10

9

GPIO149
R/W-0h

GPIO146
R/W-0h

24

17

GPIO153
R/W-0h

GPIO150
R/W-0h

GPIO147
R/W-0h

25
GPIO156
R/W-0h

19

GPIO154
R/W-0h

GPIO151
R/W-0h

26
GPIO157
R/W-0h

20

GPIO155
R/W-0h
15

27

GPIO158
R/W-0h

8
GPIO148
R/W-0h

3

2
GPIO145
R/W-0h

1

0
GPIO144
R/W-0h

Table 7-90. GPEMUX2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

GPIO159

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO158

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO157

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO156

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO155

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO154

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO153

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO152

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO151

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO150

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO149

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO148

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1045

Registers

www.ti.com

Table 7-90. GPEMUX2 Register Field Descriptions (continued)

1046

Bit

Field

Type

Reset

Description

7-6

GPIO147

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO146

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO145

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO144

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.75 GPEDIR Register (Offset = 10Ah) [reset = 0h]
GPEDIR is shown in Figure 7-78 and described in Table 7-91.
Return to Summary Table.
GPIO E Direction Register (GPIO128 to 159)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 7-78. GPEDIR Register
31
GPIO159
R/W-0h

30
GPIO158
R/W-0h

29
GPIO157
R/W-0h

28
GPIO156
R/W-0h

27
GPIO155
R/W-0h

26
GPIO154
R/W-0h

25
GPIO153
R/W-0h

24
GPIO152
R/W-0h

23
GPIO151

22
GPIO150

21
GPIO149

20
GPIO148

19
GPIO147

18
GPIO146

17
GPIO145

16
GPIO144

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO143
R/W-0h

14
GPIO142
R/W-0h

13
GPIO141
R/W-0h

12
GPIO140
R/W-0h

11
GPIO139
R/W-0h

10
GPIO138
R/W-0h

9
GPIO137
R/W-0h

8
GPIO136
R/W-0h

7
GPIO135
R/W-0h

6
GPIO134
R/W-0h

5
GPIO133
R/W-0h

4
GPIO132
R/W-0h

3
GPIO131
R/W-0h

2
GPIO130
R/W-0h

1
GPIO129
R/W-0h

0
GPIO128
R/W-0h

Table 7-91. GPEDIR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

30

GPIO158

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

29

GPIO157

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

28

GPIO156

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

27

GPIO155

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

26

GPIO154

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

25

GPIO153

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

24

GPIO152

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

23

GPIO151

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

22

GPIO150

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

21

GPIO149

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

20

GPIO148

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1047

Registers

www.ti.com

Table 7-91. GPEDIR Register Field Descriptions (continued)

1048

Bit

Field

Type

Reset

Description

19

GPIO147

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

18

GPIO146

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

17

GPIO145

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

16

GPIO144

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

15

GPIO143

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

14

GPIO142

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

13

GPIO141

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

12

GPIO140

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

11

GPIO139

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

10

GPIO138

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

9

GPIO137

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

8

GPIO136

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

7

GPIO135

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

6

GPIO134

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

5

GPIO133

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

4

GPIO132

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

3

GPIO131

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

2

GPIO130

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

1

GPIO129

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

0

GPIO128

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.76 GPEPUD Register (Offset = 10Ch) [reset = FFFFFFFFh]
GPEPUD is shown in Figure 7-79 and described in Table 7-92.
Return to Summary Table.
GPIO E Pull Up Disable Register (GPIO128 to 159)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 7-79. GPEPUD Register
31
GPIO159
R/W-1h

30
GPIO158
R/W-1h

29
GPIO157
R/W-1h

28
GPIO156
R/W-1h

27
GPIO155
R/W-1h

26
GPIO154
R/W-1h

25
GPIO153
R/W-1h

24
GPIO152
R/W-1h

23
GPIO151

22
GPIO150

21
GPIO149

20
GPIO148

19
GPIO147

18
GPIO146

17
GPIO145

16
GPIO144

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

R/W-1h

15
GPIO143
R/W-1h

14
GPIO142
R/W-1h

13
GPIO141
R/W-1h

12
GPIO140
R/W-1h

11
GPIO139
R/W-1h

10
GPIO138
R/W-1h

9
GPIO137
R/W-1h

8
GPIO136
R/W-1h

7
GPIO135
R/W-1h

6
GPIO134
R/W-1h

5
GPIO133
R/W-1h

4
GPIO132
R/W-1h

3
GPIO131
R/W-1h

2
GPIO130
R/W-1h

1
GPIO129
R/W-1h

0
GPIO128
R/W-1h

Table 7-92. GPEPUD Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

30

GPIO158

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

29

GPIO157

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

28

GPIO156

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

27

GPIO155

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

26

GPIO154

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

25

GPIO153

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

24

GPIO152

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

23

GPIO151

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

22

GPIO150

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

21

GPIO149

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

20

GPIO148

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1049

Registers

www.ti.com

Table 7-92. GPEPUD Register Field Descriptions (continued)

1050

Bit

Field

Type

Reset

Description

19

GPIO147

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

18

GPIO146

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

17

GPIO145

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

16

GPIO144

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

15

GPIO143

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

14

GPIO142

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

13

GPIO141

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

12

GPIO140

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

11

GPIO139

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

10

GPIO138

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

9

GPIO137

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

8

GPIO136

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

7

GPIO135

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

6

GPIO134

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

5

GPIO133

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

4

GPIO132

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

3

GPIO131

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

2

GPIO130

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

1

GPIO129

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

0

GPIO128

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.77 GPEINV Register (Offset = 110h) [reset = 0h]
GPEINV is shown in Figure 7-80 and described in Table 7-93.
Return to Summary Table.
GPIO E Input Polarity Invert Registers (GPIO128 to 159)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 7-80. GPEINV Register
31
GPIO159
R/W-0h

30
GPIO158
R/W-0h

29
GPIO157
R/W-0h

28
GPIO156
R/W-0h

27
GPIO155
R/W-0h

26
GPIO154
R/W-0h

25
GPIO153
R/W-0h

24
GPIO152
R/W-0h

23
GPIO151

22
GPIO150

21
GPIO149

20
GPIO148

19
GPIO147

18
GPIO146

17
GPIO145

16
GPIO144

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

15
GPIO143
R/W-0h

14
GPIO142
R/W-0h

13
GPIO141
R/W-0h

12
GPIO140
R/W-0h

11
GPIO139
R/W-0h

10
GPIO138
R/W-0h

9
GPIO137
R/W-0h

8
GPIO136
R/W-0h

7
GPIO135
R/W-0h

6
GPIO134
R/W-0h

5
GPIO133
R/W-0h

4
GPIO132
R/W-0h

3
GPIO131
R/W-0h

2
GPIO130
R/W-0h

1
GPIO129
R/W-0h

0
GPIO128
R/W-0h

Table 7-93. GPEINV Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

30

GPIO158

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

29

GPIO157

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

28

GPIO156

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

27

GPIO155

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

26

GPIO154

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

25

GPIO153

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

24

GPIO152

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

23

GPIO151

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

22

GPIO150

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

21

GPIO149

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

20

GPIO148

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1051

Registers

www.ti.com

Table 7-93. GPEINV Register Field Descriptions (continued)

1052

Bit

Field

Type

Reset

Description

19

GPIO147

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

18

GPIO146

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

17

GPIO145

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

16

GPIO144

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

15

GPIO143

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

14

GPIO142

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

13

GPIO141

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

12

GPIO140

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

11

GPIO139

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

10

GPIO138

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

9

GPIO137

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

8

GPIO136

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

7

GPIO135

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

6

GPIO134

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

5

GPIO133

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

4

GPIO132

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

3

GPIO131

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

2

GPIO130

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

1

GPIO129

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

0

GPIO128

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.78 GPEODR Register (Offset = 112h) [reset = 0h]
GPEODR is shown in Figure 7-81 and described in Table 7-94.
Return to Summary Table.
GPIO E Open Drain Output Register (GPIO128 to GPIO159)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out
comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 7-81. GPEODR Register
31
GPIO159
R/W-0h

30
GPIO158
R/W-0h

29
GPIO157
R/W-0h

28
GPIO156
R/W-0h

27
GPIO155
R/W-0h

26
GPIO154
R/W-0h

25
GPIO153
R/W-0h

24
GPIO152
R/W-0h

23
GPIO151
R/W-0h

22
GPIO150
R/W-0h

21
GPIO149
R/W-0h

20
GPIO148
R/W-0h

19
GPIO147
R/W-0h

18
GPIO146
R/W-0h

17
GPIO145
R/W-0h

16
GPIO144
R/W-0h

15
GPIO143
R/W-0h

14
GPIO142
R/W-0h

13
GPIO141
R/W-0h

12
GPIO140
R/W-0h

11
GPIO139
R/W-0h

10
GPIO138
R/W-0h

9
GPIO137
R/W-0h

8
GPIO136
R/W-0h

7
GPIO135
R/W-0h

6
GPIO134
R/W-0h

5
GPIO133
R/W-0h

4
GPIO132
R/W-0h

3
GPIO131
R/W-0h

2
GPIO130
R/W-0h

1
GPIO129
R/W-0h

0
GPIO128
R/W-0h

Table 7-94. GPEODR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

30

GPIO158

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

29

GPIO157

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

28

GPIO156

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

27

GPIO155

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

26

GPIO154

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

25

GPIO153

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

24

GPIO152

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

23

GPIO151

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

22

GPIO150

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1053

Registers

www.ti.com

Table 7-94. GPEODR Register Field Descriptions (continued)

1054

Bit

Field

Type

Reset

Description

21

GPIO149

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

20

GPIO148

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

19

GPIO147

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

18

GPIO146

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

17

GPIO145

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

16

GPIO144

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

15

GPIO143

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

14

GPIO142

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

13

GPIO141

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

12

GPIO140

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

11

GPIO139

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

10

GPIO138

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

9

GPIO137

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

8

GPIO136

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

7

GPIO135

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

6

GPIO134

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

5

GPIO133

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

4

GPIO132

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

3

GPIO131

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

2

GPIO130

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

1

GPIO129

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

0

GPIO128

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.79 GPEGMUX1 Register (Offset = 120h) [reset = 0h]
GPEGMUX1 is shown in Figure 7-82 and described in Table 7-95.
Return to Summary Table.
GPIO E Peripheral Group Mux (GPIO128 to 143)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-82. GPEGMUX1 Register
31

30

29

28

GPIO143
R/W-0h
23

22

21

14

13

7

6

12

5

18

4

16
GPIO136
R/W-0h

11

10

9

GPIO133
R/W-0h

GPIO130
R/W-0h

24

17

GPIO137
R/W-0h

GPIO134
R/W-0h

GPIO131
R/W-0h

25
GPIO140
R/W-0h

19

GPIO138
R/W-0h

GPIO135
R/W-0h

26
GPIO141
R/W-0h

20

GPIO139
R/W-0h
15

27

GPIO142
R/W-0h

8
GPIO132
R/W-0h

3

2
GPIO129
R/W-0h

1

0
GPIO128
R/W-0h

Table 7-95. GPEGMUX1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO143

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO142

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO141

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO140

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO139

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO138

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO137

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO136

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO135

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO134

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO133

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO132

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO131

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1055

Registers

www.ti.com

Table 7-95. GPEGMUX1 Register Field Descriptions (continued)

1056

Bit

Field

Type

Reset

Description

5-4

GPIO130

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO129

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO128

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.80 GPEGMUX2 Register (Offset = 122h) [reset = 0h]
GPEGMUX2 is shown in Figure 7-83 and described in Table 7-96.
Return to Summary Table.
GPIO E Peripheral Group Mux (GPIO144 to 159)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-83. GPEGMUX2 Register
31

30

29

28

GPIO159
R/W-0h
23

22

21

14

13

7

6

12

5

18

4

16
GPIO152
R/W-0h

11

10

9

GPIO149
R/W-0h

GPIO146
R/W-0h

24

17

GPIO153
R/W-0h

GPIO150
R/W-0h

GPIO147
R/W-0h

25
GPIO156
R/W-0h

19

GPIO154
R/W-0h

GPIO151
R/W-0h

26
GPIO157
R/W-0h

20

GPIO155
R/W-0h
15

27

GPIO158
R/W-0h

8
GPIO148
R/W-0h

3

2
GPIO145
R/W-0h

1

0
GPIO144
R/W-0h

Table 7-96. GPEGMUX2 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

GPIO159

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

29-28

GPIO158

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

27-26

GPIO157

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

25-24

GPIO156

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

23-22

GPIO155

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

21-20

GPIO154

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

19-18

GPIO153

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

17-16

GPIO152

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO151

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO150

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO149

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO148

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO147

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1057

Registers

www.ti.com

Table 7-96. GPEGMUX2 Register Field Descriptions (continued)

1058

Bit

Field

Type

Reset

Description

5-4

GPIO146

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO145

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO144

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.81 GPECSEL1 Register (Offset = 128h) [reset = 0h]
GPECSEL1 is shown in Figure 7-84 and described in Table 7-97.
Return to Summary Table.
GPIO E Core Select Register (GPIO128 to 135)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-84. GPECSEL1 Register
31

30
29
GPIO135
R/W-0h

28

27

26
25
GPIO134
R/W-0h

24

23

22
21
GPIO133
R/W-0h

20

19

18
17
GPIO132
R/W-0h

16

15

14
13
GPIO131
R/W-0h

12

11

10
9
GPIO130
R/W-0h

8

7

6
5
GPIO129
R/W-0h

4

3

2
1
GPIO128
R/W-0h

0

Table 7-97. GPECSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO135

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO134

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO133

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO132

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO131

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO130

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO129

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO128

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1059

Registers

www.ti.com

7.9.2.82 GPECSEL2 Register (Offset = 12Ah) [reset = 0h]
GPECSEL2 is shown in Figure 7-85 and described in Table 7-98.
Return to Summary Table.
GPIO E Core Select Register (GPIO136 to 143)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-85. GPECSEL2 Register
31

30
29
GPIO143
R/W-0h

28

27

26
25
GPIO142
R/W-0h

24

23

22
21
GPIO141
R/W-0h

20

19

18
17
GPIO140
R/W-0h

16

15

14
13
GPIO139
R/W-0h

12

11

10
9
GPIO138
R/W-0h

8

7

6
5
GPIO137
R/W-0h

4

3

2
1
GPIO136
R/W-0h

0

Table 7-98. GPECSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO143

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO142

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO141

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO140

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO139

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO138

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO137

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO136

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1060

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.83 GPECSEL3 Register (Offset = 12Ch) [reset = 0h]
GPECSEL3 is shown in Figure 7-86 and described in Table 7-99.
Return to Summary Table.
GPIO E Core Select Register (GPIO144 to 151)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-86. GPECSEL3 Register
31

30
29
GPIO151
R/W-0h

28

27

26
25
GPIO150
R/W-0h

24

23

22
21
GPIO149
R/W-0h

20

19

18
17
GPIO148
R/W-0h

16

15

14
13
GPIO147
R/W-0h

12

11

10
9
GPIO146
R/W-0h

8

7

6
5
GPIO145
R/W-0h

4

3

2
1
GPIO144
R/W-0h

0

Table 7-99. GPECSEL3 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO151

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO150

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO149

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO148

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO147

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO146

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO145

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO144

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1061

Registers

www.ti.com

7.9.2.84 GPECSEL4 Register (Offset = 12Eh) [reset = 0h]
GPECSEL4 is shown in Figure 7-87 and described in Table 7-100.
Return to Summary Table.
GPIO E Core Select Register (GPIO152 to 159)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-87. GPECSEL4 Register
31

30
29
GPIO159
R/W-0h

28

27

26
25
GPIO158
R/W-0h

24

23

22
21
GPIO157
R/W-0h

20

19

18
17
GPIO156
R/W-0h

16

15

14
13
GPIO155
R/W-0h

12

11

10
9
GPIO154
R/W-0h

8

7

6
5
GPIO153
R/W-0h

4

3

2
1
GPIO152
R/W-0h

0

Table 7-100. GPECSEL4 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO159

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO158

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO157

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO156

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO155

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO154

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO153

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO152

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1062

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.85 GPELOCK Register (Offset = 13Ch) [reset = 0h]
GPELOCK is shown in Figure 7-88 and described in Table 7-101.
Return to Summary Table.
GPIO E Lock Configuration Register (GPIO128 to 159)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2
and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL,
GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 7-88. GPELOCK Register
31
GPIO159
R/W-0h

30
GPIO158
R/W-0h

29
GPIO157
R/W-0h

28
GPIO156
R/W-0h

27
GPIO155
R/W-0h

26
GPIO154
R/W-0h

25
GPIO153
R/W-0h

24
GPIO152
R/W-0h

23
GPIO151
R/W-0h

22
GPIO150
R/W-0h

21
GPIO149
R/W-0h

20
GPIO148
R/W-0h

19
GPIO147
R/W-0h

18
GPIO146
R/W-0h

17
GPIO145
R/W-0h

16
GPIO144
R/W-0h

15
GPIO143
R/W-0h

14
GPIO142
R/W-0h

13
GPIO141
R/W-0h

12
GPIO140
R/W-0h

11
GPIO139
R/W-0h

10
GPIO138
R/W-0h

9
GPIO137
R/W-0h

8
GPIO136
R/W-0h

7
GPIO135
R/W-0h

6
GPIO134
R/W-0h

5
GPIO133
R/W-0h

4
GPIO132
R/W-0h

3
GPIO131
R/W-0h

2
GPIO130
R/W-0h

1
GPIO129
R/W-0h

0
GPIO128
R/W-0h

Table 7-101. GPELOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

30

GPIO158

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

29

GPIO157

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

28

GPIO156

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

27

GPIO155

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

26

GPIO154

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

25

GPIO153

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

24

GPIO152

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

23

GPIO151

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

22

GPIO150

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

21

GPIO149

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1063

Registers

www.ti.com

Table 7-101. GPELOCK Register Field Descriptions (continued)

1064

Bit

Field

Type

Reset

Description

20

GPIO148

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

19

GPIO147

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

18

GPIO146

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

17

GPIO145

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

16

GPIO144

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

15

GPIO143

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

14

GPIO142

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

13

GPIO141

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

12

GPIO140

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

11

GPIO139

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

10

GPIO138

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

9

GPIO137

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

8

GPIO136

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

7

GPIO135

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

6

GPIO134

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

5

GPIO133

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

4

GPIO132

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

3

GPIO131

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

2

GPIO130

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

1

GPIO129

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

0

GPIO128

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.86 GPECR Register (Offset = 13Eh) [reset = 0h]
GPECR is shown in Figure 7-89 and described in Table 7-102.
Return to Summary Table.
GPIO E Lock Commit Register (GPIO128 to 159)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 7-89. GPECR Register
31
GPIO159
R/WOnce-0h

30
GPIO158
R/WOnce-0h

29
GPIO157
R/WOnce-0h

28
GPIO156
R/WOnce-0h

27
GPIO155
R/WOnce-0h

26
GPIO154
R/WOnce-0h

25
GPIO153
R/WOnce-0h

24
GPIO152
R/WOnce-0h

23
GPIO151
R/WOnce-0h

22
GPIO150
R/WOnce-0h

21
GPIO149
R/WOnce-0h

20
GPIO148
R/WOnce-0h

19
GPIO147
R/WOnce-0h

18
GPIO146
R/WOnce-0h

17
GPIO145
R/WOnce-0h

16
GPIO144
R/WOnce-0h

15
GPIO143
R/WOnce-0h

14
GPIO142
R/WOnce-0h

13
GPIO141
R/WOnce-0h

12
GPIO140
R/WOnce-0h

11
GPIO139
R/WOnce-0h

10
GPIO138
R/WOnce-0h

9
GPIO137
R/WOnce-0h

8
GPIO136
R/WOnce-0h

7
GPIO135
R/WOnce-0h

6
GPIO134
R/WOnce-0h

5
GPIO133
R/WOnce-0h

4
GPIO132
R/WOnce-0h

3
GPIO131
R/WOnce-0h

2
GPIO130
R/WOnce-0h

1
GPIO129
R/WOnce-0h

0
GPIO128
R/WOnce-0h

Table 7-102. GPECR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

30

GPIO158

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

29

GPIO157

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

28

GPIO156

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

27

GPIO155

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

26

GPIO154

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

25

GPIO153

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

24

GPIO152

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

23

GPIO151

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

22

GPIO150

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

21

GPIO149

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

20

GPIO148

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1065

Registers

www.ti.com

Table 7-102. GPECR Register Field Descriptions (continued)

1066

Bit

Field

Type

Reset

Description

19

GPIO147

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

18

GPIO146

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

17

GPIO145

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

16

GPIO144

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

15

GPIO143

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

14

GPIO142

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

13

GPIO141

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

12

GPIO140

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

11

GPIO139

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

10

GPIO138

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

9

GPIO137

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

8

GPIO136

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

7

GPIO135

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

6

GPIO134

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

5

GPIO133

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

4

GPIO132

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

3

GPIO131

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

2

GPIO130

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

1

GPIO129

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

0

GPIO128

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.87 GPFCTRL Register (Offset = 140h) [reset = 0h]
GPFCTRL is shown in Figure 7-90 and described in Table 7-103.
Return to Summary Table.
GPIO F Qualification Sampling Period Control (GPIO160 to 168)
Figure 7-90. GPFCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
RESERVED
QUALPRD1
R-0h
R-0h
R/W-0h

9

8

7

6

5 4 3 2
QUALPRD0
R/W-0h

1

0

Table 7-103. GPFCTRL Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R

0h

Reserved

23-16

RESERVED

R

0h

Reserved

15-8

QUALPRD1

R/W

0h

Qualification sampling period for GPIO168:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

7-0

QUALPRD0

R/W

0h

Qualification sampling period for GPIO160 to GPIO167:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1067

Registers

www.ti.com

7.9.2.88 GPFQSEL1 Register (Offset = 142h) [reset = 0h]
GPFQSEL1 is shown in Figure 7-91 and described in Table 7-104.
Return to Summary Table.
GPIO F Qualifier Select 1 Register (GPIO160 to 168)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 7-91. GPFQSEL1 Register
31

30

29

28

RESERVED
R-0h
23

22

21

14

7

19

RESERVED
R-0h
13

6

5

17

4

10

3

16
GPIO168
R/W-0h

9

GPIO165
R/W-0h

GPIO162
R/W-0h

24
RESERVED
R-0h

18

11

GPIO166
R/W-0h

GPIO163
R/W-0h

25

RESERVED
R-0h
12

GPIO167
R/W-0h

26
RESERVED
R-0h

20

RESERVED
R-0h
15

27

RESERVED
R-0h

8
GPIO164
R/W-0h

2
GPIO161
R/W-0h

1

0
GPIO160
R/W-0h

Table 7-104. GPFQSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

RESERVED

R

0h

Reserved

29-28

RESERVED

R

0h

Reserved

27-26

RESERVED

R

0h

Reserved

25-24

RESERVED

R

0h

Reserved

23-22

RESERVED

R

0h

Reserved

21-20

RESERVED

R

0h

Reserved

19-18

RESERVED

R

0h

Reserved

17-16

GPIO168

R/W

0h

Input qualification type
Reset type: SYSRSn

15-14

GPIO167

R/W

0h

Input qualification type
Reset type: SYSRSn

13-12

GPIO166

R/W

0h

Input qualification type
Reset type: SYSRSn

11-10

GPIO165

R/W

0h

Input qualification type
Reset type: SYSRSn

9-8

GPIO164

R/W

0h

Input qualification type
Reset type: SYSRSn

7-6

GPIO163

R/W

0h

Input qualification type
Reset type: SYSRSn

5-4

GPIO162

R/W

0h

Input qualification type
Reset type: SYSRSn

3-2

GPIO161

R/W

0h

Input qualification type
Reset type: SYSRSn

1068

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-104. GPFQSEL1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

GPIO160

R/W

0h

Input qualification type
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1069

Registers

www.ti.com

7.9.2.89 GPFMUX1 Register (Offset = 146h) [reset = 0h]
GPFMUX1 is shown in Figure 7-92 and described in Table 7-105.
Return to Summary Table.
GPIO F Mux 1 Register (GPIO160 to 168)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate
peripheral selects being mapped to the GPIO.
Figure 7-92. GPFMUX1 Register
31

30

29

28

RESERVED
R-0h
23

22

21

14

7

19

RESERVED
R-0h
13

6

5

17

4

10

3

16
GPIO168
R/W-0h

9

GPIO165
R/W-0h

GPIO162
R/W-0h

24
RESERVED
R-0h

18

11

GPIO166
R/W-0h

GPIO163
R/W-0h

25

RESERVED
R-0h
12

GPIO167
R/W-0h

26
RESERVED
R-0h

20

RESERVED
R-0h
15

27

RESERVED
R-0h

8
GPIO164
R/W-0h

2
GPIO161
R/W-0h

1

0
GPIO160
R/W-0h

Table 7-105. GPFMUX1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

R

0h

Reserved

29-28

RESERVED

R

0h

Reserved

27-26

RESERVED

R

0h

Reserved

25-24

RESERVED

R

0h

Reserved

23-22

RESERVED

R

0h

Reserved

21-20

RESERVED

R

0h

Reserved

19-18

RESERVED

R

0h

Reserved

17-16

GPIO168

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO167

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO166

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO165

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO164

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO163

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO162

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO161

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1070

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-105. GPFMUX1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

GPIO160

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1071

Registers

www.ti.com

7.9.2.90 GPFDIR Register (Offset = 14Ah) [reset = 0h]
GPFDIR is shown in Figure 7-93 and described in Table 7-106.
Return to Summary Table.
GPIO F Direction Register (GPIO160 to 168)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 7-93. GPFDIR Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED

22
RESERVED

21
RESERVED

20
RESERVED

19
RESERVED

18
RESERVED

17
RESERVED

16
RESERVED

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-0h

7
GPIO167
R/W-0h

6
GPIO166
R/W-0h

5
GPIO165
R/W-0h

4
GPIO164
R/W-0h

3
GPIO163
R/W-0h

2
GPIO162
R/W-0h

1
GPIO161
R/W-0h

0
GPIO160
R/W-0h

Table 7-106. GPFDIR Register Field Descriptions

1072

Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-106. GPFDIR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8

GPIO168

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

7

GPIO167

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

6

GPIO166

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

5

GPIO165

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

4

GPIO164

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

3

GPIO163

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

2

GPIO162

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

1

GPIO161

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

0

GPIO160

R/W

0h

Defines direction for this pin in GPIO mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1073

Registers

www.ti.com

7.9.2.91 GPFPUD Register (Offset = 14Ch) [reset = FFFFFFFFh]
GPFPUD is shown in Figure 7-94 and described in Table 7-107.
Return to Summary Table.
GPIO F Pull Up Disable Register (GPIO160 to 168)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Figure 7-94. GPFPUD Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED

22
RESERVED

21
RESERVED

20
RESERVED

19
RESERVED

18
RESERVED

17
RESERVED

16
RESERVED

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-1h

7
GPIO167
R/W-1h

6
GPIO166
R/W-1h

5
GPIO165
R/W-1h

4
GPIO164
R/W-1h

3
GPIO163
R/W-1h

2
GPIO162
R/W-1h

1
GPIO161
R/W-1h

0
GPIO160
R/W-1h

Table 7-107. GPFPUD Register Field Descriptions

1074

Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-107. GPFPUD Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8

GPIO168

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

7

GPIO167

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

6

GPIO166

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

5

GPIO165

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

4

GPIO164

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

3

GPIO163

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

2

GPIO162

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

1

GPIO161

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

0

GPIO160

R/W

1h

Pull-Up Disable control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1075

Registers

www.ti.com

7.9.2.92 GPFINV Register (Offset = 150h) [reset = 0h]
GPFINV is shown in Figure 7-95 and described in Table 7-108.
Return to Summary Table.
GPIO F Input Polarity Invert Registers (GPIO160 to 168)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 7-95. GPFINV Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED

22
RESERVED

21
RESERVED

20
RESERVED

19
RESERVED

18
RESERVED

17
RESERVED

16
RESERVED

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-0h

7
GPIO167
R/W-0h

6
GPIO166
R/W-0h

5
GPIO165
R/W-0h

4
GPIO164
R/W-0h

3
GPIO163
R/W-0h

2
GPIO162
R/W-0h

1
GPIO161
R/W-0h

0
GPIO160
R/W-0h

Table 7-108. GPFINV Register Field Descriptions

1076

Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-108. GPFINV Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8

GPIO168

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

7

GPIO167

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

6

GPIO166

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

5

GPIO165

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

4

GPIO164

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

3

GPIO163

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

2

GPIO162

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

1

GPIO161

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

0

GPIO160

R/W

0h

Input inversion control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1077

Registers

www.ti.com

7.9.2.93 GPFODR Register (Offset = 152h) [reset = 0h]
GPFODR is shown in Figure 7-96 and described in Table 7-109.
Return to Summary Table.
GPIO F Open Drain Output Register (GPIO160 to GPIO168)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out
comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 7-96. GPFODR Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18
RESERVED
R-0h

17
RESERVED
R-0h

16
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-0h

7
GPIO167
R/W-0h

6
GPIO166
R/W-0h

5
GPIO165
R/W-0h

4
GPIO164
R/W-0h

3
GPIO163
R/W-0h

2
GPIO162
R/W-0h

1
GPIO161
R/W-0h

0
GPIO160
R/W-0h

Table 7-109. GPFODR Register Field Descriptions

1078

Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 7-109. GPFODR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

9

RESERVED

R

0h

Reserved

8

GPIO168

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

7

GPIO167

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

6

GPIO166

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

5

GPIO165

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

4

GPIO164

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

3

GPIO163

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

2

GPIO162

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

1

GPIO161

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

0

GPIO160

R/W

0h

Outpout Open-Drain control for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1079

Registers

www.ti.com

7.9.2.94 GPFGMUX1 Register (Offset = 160h) [reset = 0h]
GPFGMUX1 is shown in Figure 7-97 and described in Table 7-110.
Return to Summary Table.
GPIO F Peripheral Group Mux (GPIO160 to 168)
Defines pin-muxing selection for GPIO.
Note: For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 7-97. GPFGMUX1 Register
31

30

29

28

RESERVED
R-0h
23

22

21

14

7

19

RESERVED
R-0h
13

6

5

17

4

10

3

16
GPIO168
R/W-0h

9

GPIO165
R/W-0h

GPIO162
R/W-0h

24
RESERVED
R-0h

18

11

GPIO166
R/W-0h

GPIO163
R/W-0h

25

RESERVED
R-0h
12

GPIO167
R/W-0h

26
RESERVED
R-0h

20

RESERVED
R-0h
15

27

RESERVED
R-0h

8
GPIO164
R/W-0h

2
GPIO161
R/W-0h

1

0
GPIO160
R/W-0h

Table 7-110. GPFGMUX1 Register Field Descriptions
Field

Type

Reset

Description

31-30

Bit

RESERVED

R

0h

Reserved

29-28

RESERVED

R

0h

Reserved

27-26

RESERVED

R

0h

Reserved

25-24

RESERVED

R

0h

Reserved

23-22

RESERVED

R

0h

Reserved

21-20

RESERVED

R

0h

Reserved

19-18

RESERVED

R

0h

Reserved

17-16

GPIO168

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

15-14

GPIO167

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

13-12

GPIO166

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

11-10

GPIO165

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

9-8

GPIO164

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

7-6

GPIO163

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

5-4

GPIO162

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

3-2

GPIO161

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1-0

GPIO160

R/W

0h

Defines pin-muxing selection for GPIO
Reset type: SYSRSn

1080

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.95 GPFCSEL1 Register (Offset = 168h) [reset = 0h]
GPFCSEL1 is shown in Figure 7-98 and described in Table 7-111.
Return to Summary Table.
GPIO F Core Select Register (GPIO160 to 167)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-98. GPFCSEL1 Register
31

30
29
GPIO167
R/W-0h

28

27

26
25
GPIO166
R/W-0h

24

23

22
21
GPIO165
R/W-0h

20

19

18
17
GPIO164
R/W-0h

16

15

14
13
GPIO163
R/W-0h

12

11

10
9
GPIO162
R/W-0h

8

7

6
5
GPIO161
R/W-0h

4

3

2
1
GPIO160
R/W-0h

0

Table 7-111. GPFCSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

GPIO167

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

27-24

GPIO166

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

23-20

GPIO165

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

19-16

GPIO164

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

15-12

GPIO163

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

11-8

GPIO162

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

7-4

GPIO161

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

3-0

GPIO160

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1081

Registers

www.ti.com

7.9.2.96 GPFCSEL2 Register (Offset = 16Ah) [reset = 0h]
GPFCSEL2 is shown in Figure 7-99 and described in Table 7-112.
Return to Summary Table.
GPIO F Core Select Register (GPIO168)
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
xx00: CPU1 selected
xx01: CPU1.CLA1 selected
xx10: CPU2 selected
xx11: CPU2.CLA1 selected
Figure 7-99. GPFCSEL2 Register
31

30
29
RESERVED
R-0h

28

27

26
25
RESERVED
R-0h

24

23

22
21
RESERVED
R-0h

20

19

18
17
RESERVED
R-0h

16

15

14
13
RESERVED
R-0h

12

11

10
9
RESERVED
R-0h

8

7

6
5
RESERVED
R-0h

4

3

2
1
GPIO168
R/W-0h

0

Table 7-112. GPFCSEL2 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

R

0h

Reserved

27-24

RESERVED

R

0h

Reserved

23-20

RESERVED

R

0h

Reserved

19-16

RESERVED

R

0h

Reserved

15-12

RESERVED

R

0h

Reserved

11-8

RESERVED

R

0h

Reserved

7-4

RESERVED

R

0h

Reserved

3-0

GPIO168

R/W

0h

Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

1082

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.97 GPFLOCK Register (Offset = 17Ch) [reset = 0h]
GPFLOCK is shown in Figure 7-100 and described in Table 7-113.
Return to Summary Table.
GPIO F Lock Configuration Register (GPIO160 to 168)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2
and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL,
GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 7-100. GPFLOCK Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18
RESERVED
R-0h

17
RESERVED
R-0h

16
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-0h

7
GPIO167
R/W-0h

6
GPIO166
R/W-0h

5
GPIO165
R/W-0h

4
GPIO164
R/W-0h

3
GPIO163
R/W-0h

2
GPIO162
R/W-0h

1
GPIO161
R/W-0h

0
GPIO160
R/W-0h

Table 7-113. GPFLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1083

Registers

www.ti.com

Table 7-113. GPFLOCK Register Field Descriptions (continued)
Bit

1084

Field

Type

Reset

Description

8

GPIO168

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

7

GPIO167

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

6

GPIO166

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

5

GPIO165

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

4

GPIO164

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

3

GPIO163

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

2

GPIO162

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

1

GPIO161

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

0

GPIO160

R/W

0h

Configuration Lock bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.2.98 GPFCR Register (Offset = 17Eh) [reset = 0h]
GPFCR is shown in Figure 7-101 and described in Table 7-114.
Return to Summary Table.
GPIO F Lock Commit Register (GPIO160 to 168)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 7-101. GPFCR Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18
RESERVED
R-0h

17
RESERVED
R-0h

16
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/WOnce-0h

7
GPIO167
R/WOnce-0h

6
GPIO166
R/WOnce-0h

5
GPIO165
R/WOnce-0h

4
GPIO164
R/WOnce-0h

3
GPIO163
R/WOnce-0h

2
GPIO162
R/WOnce-0h

1
GPIO161
R/WOnce-0h

0
GPIO160
R/WOnce-0h

Table 7-114. GPFCR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

GPIO168

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1085

Registers

www.ti.com

Table 7-114. GPFCR Register Field Descriptions (continued)
Bit

1086

Field

Type

Reset

Description

7

GPIO167

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

6

GPIO166

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

5

GPIO165

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

4

GPIO164

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

3

GPIO163

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

2

GPIO162

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

1

GPIO161

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

0

GPIO160

R/WOnce

0h

Configuration lock commit bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3 GPIO_DATA_REGS Registers
Table 7-115 lists the memory-mapped registers for the GPIO_DATA_REGS. All register offset addresses
not listed in Table 7-115 should be considered as reserved locations and the register contents should not
be modified.
Table 7-115. GPIO_DATA_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

GPADAT

GPIO A Data Register (GPIO0 to 31)

Go

2h

GPASET

GPIO A Data Set Register (GPIO0 to 31)

Go

4h

GPACLEAR

GPIO A Data Clear Register (GPIO0 to 31)

Go

6h

GPATOGGLE

GPIO A Data Toggle Register (GPIO0 to 31)

Go

8h

GPBDAT

GPIO B Data Register (GPIO32 to 63)

Go

Ah

GPBSET

GPIO B Data Set Register (GPIO32 to 63)

Go

Ch

GPBCLEAR

GPIO B Data Clear Register (GPIO32 to 63)

Go

Eh

GPBTOGGLE

GPIO B Data Toggle Register (GPIO32 to 63)

Go

10h

GPCDAT

GPIO C Data Register (GPIO64 to 95)

Go

12h

GPCSET

GPIO C Data Set Register (GPIO64 to 95)

Go

14h

GPCCLEAR

GPIO C Data Clear Register (GPIO64 to 95)

Go

16h

GPCTOGGLE

GPIO C Data Toggle Register (GPIO64 to 95)

Go

18h

GPDDAT

GPIO D Data Register (GPIO96 to 127)

Go

1Ah

GPDSET

GPIO D Data Set Register (GPIO96 to 127)

Go

1Ch

GPDCLEAR

GPIO D Data Clear Register (GPIO96 to 127)

Go

1Eh

GPDTOGGLE

GPIO D Data Toggle Register (GPIO96 to 127)

Go

20h

GPEDAT

GPIO E Data Register (GPIO128 to 159)

Go

22h

GPESET

GPIO E Data Set Register (GPIO128 to 159)

Go

24h

GPECLEAR

GPIO E Data Clear Register (GPIO128 to 159)

Go

26h

GPETOGGLE

GPIO E Data Toggle Register (GPIO128 to 159)

Go

28h

GPFDAT

GPIO F Data Register (GPIO160 to 168)

Go

2Ah

GPFSET

GPIO F Data Set Register (GPIO160 to 168)

Go

2Ch

GPFCLEAR

GPIO F Data Clear Register (GPIO160 to 168)

Go

2Eh

GPFTOGGLE

GPIO F Data Toggle Register (GPIO160 to 168)

Go

Complex bit access types are encoded to fit into small table cells. Table 7-116 shows the codes that are
used for access types in this section.
Table 7-116. GPIO_DATA_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

Write

Read Type
R
Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1087

Registers

www.ti.com

Table 7-116. GPIO_DATA_REGS Access Type
Codes (continued)
Access Type

1088

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.1

GPADAT Register (Offset = 0h) [reset = 0h]

GPADAT is shown in Figure 7-102 and described in Table 7-117.
Return to Summary Table.
GPIO A Data Register (GPIO0 to 31)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the
GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads
of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO
Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise
operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to
GPxDAT are necessary, the entire register should be written at one time.
Figure 7-102. GPADAT Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23
R/W-0h

22
GPIO22
R/W-0h

21
GPIO21
R/W-0h

20
GPIO20
R/W-0h

19
GPIO19
R/W-0h

18
GPIO18
R/W-0h

17
GPIO17
R/W-0h

16
GPIO16
R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 7-117. GPADAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

Data Register for this pin
Reset type: SYSRSn

30

GPIO30

R/W

0h

Data Register for this pin
Reset type: SYSRSn

29

GPIO29

R/W

0h

Data Register for this pin
Reset type: SYSRSn

28

GPIO28

R/W

0h

Data Register for this pin
Reset type: SYSRSn

27

GPIO27

R/W

0h

Data Register for this pin
Reset type: SYSRSn

26

GPIO26

R/W

0h

Data Register for this pin
Reset type: SYSRSn

25

GPIO25

R/W

0h

Data Register for this pin
Reset type: SYSRSn

24

GPIO24

R/W

0h

Data Register for this pin
Reset type: SYSRSn

23

GPIO23

R/W

0h

Data Register for this pin
Reset type: SYSRSn

22

GPIO22

R/W

0h

Data Register for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1089

Registers

www.ti.com

Table 7-117. GPADAT Register Field Descriptions (continued)

1090

Bit

Field

Type

Reset

Description

21

GPIO21

R/W

0h

Data Register for this pin
Reset type: SYSRSn

20

GPIO20

R/W

0h

Data Register for this pin
Reset type: SYSRSn

19

GPIO19

R/W

0h

Data Register for this pin
Reset type: SYSRSn

18

GPIO18

R/W

0h

Data Register for this pin
Reset type: SYSRSn

17

GPIO17

R/W

0h

Data Register for this pin
Reset type: SYSRSn

16

GPIO16

R/W

0h

Data Register for this pin
Reset type: SYSRSn

15

GPIO15

R/W

0h

Data Register for this pin
Reset type: SYSRSn

14

GPIO14

R/W

0h

Data Register for this pin
Reset type: SYSRSn

13

GPIO13

R/W

0h

Data Register for this pin
Reset type: SYSRSn

12

GPIO12

R/W

0h

Data Register for this pin
Reset type: SYSRSn

11

GPIO11

R/W

0h

Data Register for this pin
Reset type: SYSRSn

10

GPIO10

R/W

0h

Data Register for this pin
Reset type: SYSRSn

9

GPIO9

R/W

0h

Data Register for this pin
Reset type: SYSRSn

8

GPIO8

R/W

0h

Data Register for this pin
Reset type: SYSRSn

7

GPIO7

R/W

0h

Data Register for this pin
Reset type: SYSRSn

6

GPIO6

R/W

0h

Data Register for this pin
Reset type: SYSRSn

5

GPIO5

R/W

0h

Data Register for this pin
Reset type: SYSRSn

4

GPIO4

R/W

0h

Data Register for this pin
Reset type: SYSRSn

3

GPIO3

R/W

0h

Data Register for this pin
Reset type: SYSRSn

2

GPIO2

R/W

0h

Data Register for this pin
Reset type: SYSRSn

1

GPIO1

R/W

0h

Data Register for this pin
Reset type: SYSRSn

0

GPIO0

R/W

0h

Data Register for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.2

GPASET Register (Offset = 2h) [reset = 0h]

GPASET is shown in Figure 7-103 and described in Table 7-118.
Return to Summary Table.
GPIO A Data Set Register (GPIO0 to 31)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-103. GPASET Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23
R/W-0h

22
GPIO22
R/W-0h

21
GPIO21
R/W-0h

20
GPIO20
R/W-0h

19
GPIO19
R/W-0h

18
GPIO18
R/W-0h

17
GPIO17
R/W-0h

16
GPIO16
R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 7-118. GPASET Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

30

GPIO30

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

29

GPIO29

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

28

GPIO28

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

27

GPIO27

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

26

GPIO26

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

25

GPIO25

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

24

GPIO24

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

23

GPIO23

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

22

GPIO22

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

21

GPIO21

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

20

GPIO20

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1091

Registers

www.ti.com

Table 7-118. GPASET Register Field Descriptions (continued)

1092

Bit

Field

Type

Reset

Description

19

GPIO19

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

18

GPIO18

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

17

GPIO17

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

16

GPIO16

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

15

GPIO15

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

14

GPIO14

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

13

GPIO13

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

12

GPIO12

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

11

GPIO11

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

10

GPIO10

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

9

GPIO9

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

8

GPIO8

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

7

GPIO7

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

6

GPIO6

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

5

GPIO5

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

4

GPIO4

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

3

GPIO3

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

2

GPIO2

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

1

GPIO1

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

0

GPIO0

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.3

GPACLEAR Register (Offset = 4h) [reset = 0h]

GPACLEAR is shown in Figure 7-104 and described in Table 7-119.
Return to Summary Table.
GPIO A Data Clear Register (GPIO0 to 31)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-104. GPACLEAR Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23
R/W-0h

22
GPIO22
R/W-0h

21
GPIO21
R/W-0h

20
GPIO20
R/W-0h

19
GPIO19
R/W-0h

18
GPIO18
R/W-0h

17
GPIO17
R/W-0h

16
GPIO16
R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 7-119. GPACLEAR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

30

GPIO30

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

29

GPIO29

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

28

GPIO28

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

27

GPIO27

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

26

GPIO26

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

25

GPIO25

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

24

GPIO24

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

23

GPIO23

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

22

GPIO22

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

21

GPIO21

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

20

GPIO20

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1093

Registers

www.ti.com

Table 7-119. GPACLEAR Register Field Descriptions (continued)

1094

Bit

Field

Type

Reset

Description

19

GPIO19

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

18

GPIO18

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

17

GPIO17

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

16

GPIO16

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

15

GPIO15

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

14

GPIO14

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

13

GPIO13

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

12

GPIO12

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

11

GPIO11

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

10

GPIO10

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

9

GPIO9

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

8

GPIO8

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

7

GPIO7

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

6

GPIO6

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

5

GPIO5

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

4

GPIO4

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

3

GPIO3

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

2

GPIO2

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

1

GPIO1

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

0

GPIO0

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.4

GPATOGGLE Register (Offset = 6h) [reset = 0h]

GPATOGGLE is shown in Figure 7-105 and described in Table 7-120.
Return to Summary Table.
GPIO A Data Toggle Register (GPIO0 to 31)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-105. GPATOGGLE Register
31
GPIO31
R/W-0h

30
GPIO30
R/W-0h

29
GPIO29
R/W-0h

28
GPIO28
R/W-0h

27
GPIO27
R/W-0h

26
GPIO26
R/W-0h

25
GPIO25
R/W-0h

24
GPIO24
R/W-0h

23
GPIO23
R/W-0h

22
GPIO22
R/W-0h

21
GPIO21
R/W-0h

20
GPIO20
R/W-0h

19
GPIO19
R/W-0h

18
GPIO18
R/W-0h

17
GPIO17
R/W-0h

16
GPIO16
R/W-0h

15
GPIO15
R/W-0h

14
GPIO14
R/W-0h

13
GPIO13
R/W-0h

12
GPIO12
R/W-0h

11
GPIO11
R/W-0h

10
GPIO10
R/W-0h

9
GPIO9
R/W-0h

8
GPIO8
R/W-0h

7
GPIO7
R/W-0h

6
GPIO6
R/W-0h

5
GPIO5
R/W-0h

4
GPIO4
R/W-0h

3
GPIO3
R/W-0h

2
GPIO2
R/W-0h

1
GPIO1
R/W-0h

0
GPIO0
R/W-0h

Table 7-120. GPATOGGLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO31

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

30

GPIO30

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

29

GPIO29

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

28

GPIO28

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

27

GPIO27

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

26

GPIO26

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

25

GPIO25

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

24

GPIO24

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

23

GPIO23

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

22

GPIO22

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

21

GPIO21

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

20

GPIO20

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1095

Registers

www.ti.com

Table 7-120. GPATOGGLE Register Field Descriptions (continued)

1096

Bit

Field

Type

Reset

Description

19

GPIO19

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

18

GPIO18

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

17

GPIO17

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

16

GPIO16

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

15

GPIO15

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

14

GPIO14

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

13

GPIO13

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

12

GPIO12

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

11

GPIO11

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

10

GPIO10

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

9

GPIO9

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

8

GPIO8

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

7

GPIO7

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

6

GPIO6

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

5

GPIO5

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

4

GPIO4

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

3

GPIO3

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

2

GPIO2

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

1

GPIO1

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

0

GPIO0

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.5

GPBDAT Register (Offset = 8h) [reset = 0h]

GPBDAT is shown in Figure 7-106 and described in Table 7-121.
Return to Summary Table.
GPIO B Data Register (GPIO32 to 63)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the
GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads
of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO
Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise
operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to
GPxDAT are necessary, the entire register should be written at one time.
Figure 7-106. GPBDAT Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55
R/W-0h

22
GPIO54
R/W-0h

21
GPIO53
R/W-0h

20
GPIO52
R/W-0h

19
GPIO51
R/W-0h

18
GPIO50
R/W-0h

17
GPIO49
R/W-0h

16
GPIO48
R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 7-121. GPBDAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

Data Register for this pin
Reset type: SYSRSn

30

GPIO62

R/W

0h

Data Register for this pin
Reset type: SYSRSn

29

GPIO61

R/W

0h

Data Register for this pin
Reset type: SYSRSn

28

GPIO60

R/W

0h

Data Register for this pin
Reset type: SYSRSn

27

GPIO59

R/W

0h

Data Register for this pin
Reset type: SYSRSn

26

GPIO58

R/W

0h

Data Register for this pin
Reset type: SYSRSn

25

GPIO57

R/W

0h

Data Register for this pin
Reset type: SYSRSn

24

GPIO56

R/W

0h

Data Register for this pin
Reset type: SYSRSn

23

GPIO55

R/W

0h

Data Register for this pin
Reset type: SYSRSn

22

GPIO54

R/W

0h

Data Register for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1097

Registers

www.ti.com

Table 7-121. GPBDAT Register Field Descriptions (continued)

1098

Bit

Field

Type

Reset

Description

21

GPIO53

R/W

0h

Data Register for this pin
Reset type: SYSRSn

20

GPIO52

R/W

0h

Data Register for this pin
Reset type: SYSRSn

19

GPIO51

R/W

0h

Data Register for this pin
Reset type: SYSRSn

18

GPIO50

R/W

0h

Data Register for this pin
Reset type: SYSRSn

17

GPIO49

R/W

0h

Data Register for this pin
Reset type: SYSRSn

16

GPIO48

R/W

0h

Data Register for this pin
Reset type: SYSRSn

15

GPIO47

R/W

0h

Data Register for this pin
Reset type: SYSRSn

14

GPIO46

R/W

0h

Data Register for this pin
Reset type: SYSRSn

13

GPIO45

R/W

0h

Data Register for this pin
Reset type: SYSRSn

12

GPIO44

R/W

0h

Data Register for this pin
Reset type: SYSRSn

11

GPIO43

R/W

0h

Data Register for this pin
Reset type: SYSRSn

10

GPIO42

R/W

0h

Data Register for this pin
Reset type: SYSRSn

9

GPIO41

R/W

0h

Data Register for this pin
Reset type: SYSRSn

8

GPIO40

R/W

0h

Data Register for this pin
Reset type: SYSRSn

7

GPIO39

R/W

0h

Data Register for this pin
Reset type: SYSRSn

6

GPIO38

R/W

0h

Data Register for this pin
Reset type: SYSRSn

5

GPIO37

R/W

0h

Data Register for this pin
Reset type: SYSRSn

4

GPIO36

R/W

0h

Data Register for this pin
Reset type: SYSRSn

3

GPIO35

R/W

0h

Data Register for this pin
Reset type: SYSRSn

2

GPIO34

R/W

0h

Data Register for this pin
Reset type: SYSRSn

1

GPIO33

R/W

0h

Data Register for this pin
Reset type: SYSRSn

0

GPIO32

R/W

0h

Data Register for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.6

GPBSET Register (Offset = Ah) [reset = 0h]

GPBSET is shown in Figure 7-107 and described in Table 7-122.
Return to Summary Table.
GPIO B Data Set Register (GPIO32 to 63)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-107. GPBSET Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55
R/W-0h

22
GPIO54
R/W-0h

21
GPIO53
R/W-0h

20
GPIO52
R/W-0h

19
GPIO51
R/W-0h

18
GPIO50
R/W-0h

17
GPIO49
R/W-0h

16
GPIO48
R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 7-122. GPBSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

30

GPIO62

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

29

GPIO61

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

28

GPIO60

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

27

GPIO59

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

26

GPIO58

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

25

GPIO57

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

24

GPIO56

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

23

GPIO55

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

22

GPIO54

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

21

GPIO53

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

20

GPIO52

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1099

Registers

www.ti.com

Table 7-122. GPBSET Register Field Descriptions (continued)

1100

Bit

Field

Type

Reset

Description

19

GPIO51

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

18

GPIO50

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

17

GPIO49

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

16

GPIO48

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

15

GPIO47

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

14

GPIO46

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

13

GPIO45

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

12

GPIO44

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

11

GPIO43

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

10

GPIO42

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

9

GPIO41

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

8

GPIO40

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

7

GPIO39

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

6

GPIO38

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

5

GPIO37

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

4

GPIO36

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

3

GPIO35

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

2

GPIO34

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

1

GPIO33

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

0

GPIO32

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.7

GPBCLEAR Register (Offset = Ch) [reset = 0h]

GPBCLEAR is shown in Figure 7-108 and described in Table 7-123.
Return to Summary Table.
GPIO B Data Clear Register (GPIO32 to 63)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-108. GPBCLEAR Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55
R/W-0h

22
GPIO54
R/W-0h

21
GPIO53
R/W-0h

20
GPIO52
R/W-0h

19
GPIO51
R/W-0h

18
GPIO50
R/W-0h

17
GPIO49
R/W-0h

16
GPIO48
R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 7-123. GPBCLEAR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

30

GPIO62

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

29

GPIO61

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

28

GPIO60

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

27

GPIO59

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

26

GPIO58

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

25

GPIO57

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

24

GPIO56

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

23

GPIO55

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

22

GPIO54

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

21

GPIO53

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

20

GPIO52

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1101

Registers

www.ti.com

Table 7-123. GPBCLEAR Register Field Descriptions (continued)

1102

Bit

Field

Type

Reset

Description

19

GPIO51

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

18

GPIO50

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

17

GPIO49

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

16

GPIO48

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

15

GPIO47

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

14

GPIO46

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

13

GPIO45

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

12

GPIO44

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

11

GPIO43

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

10

GPIO42

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

9

GPIO41

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

8

GPIO40

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

7

GPIO39

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

6

GPIO38

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

5

GPIO37

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

4

GPIO36

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

3

GPIO35

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

2

GPIO34

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

1

GPIO33

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

0

GPIO32

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.8

GPBTOGGLE Register (Offset = Eh) [reset = 0h]

GPBTOGGLE is shown in Figure 7-109 and described in Table 7-124.
Return to Summary Table.
GPIO B Data Toggle Register (GPIO32 to 63)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-109. GPBTOGGLE Register
31
GPIO63
R/W-0h

30
GPIO62
R/W-0h

29
GPIO61
R/W-0h

28
GPIO60
R/W-0h

27
GPIO59
R/W-0h

26
GPIO58
R/W-0h

25
GPIO57
R/W-0h

24
GPIO56
R/W-0h

23
GPIO55
R/W-0h

22
GPIO54
R/W-0h

21
GPIO53
R/W-0h

20
GPIO52
R/W-0h

19
GPIO51
R/W-0h

18
GPIO50
R/W-0h

17
GPIO49
R/W-0h

16
GPIO48
R/W-0h

15
GPIO47
R/W-0h

14
GPIO46
R/W-0h

13
GPIO45
R/W-0h

12
GPIO44
R/W-0h

11
GPIO43
R/W-0h

10
GPIO42
R/W-0h

9
GPIO41
R/W-0h

8
GPIO40
R/W-0h

7
GPIO39
R/W-0h

6
GPIO38
R/W-0h

5
GPIO37
R/W-0h

4
GPIO36
R/W-0h

3
GPIO35
R/W-0h

2
GPIO34
R/W-0h

1
GPIO33
R/W-0h

0
GPIO32
R/W-0h

Table 7-124. GPBTOGGLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO63

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

30

GPIO62

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

29

GPIO61

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

28

GPIO60

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

27

GPIO59

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

26

GPIO58

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

25

GPIO57

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

24

GPIO56

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

23

GPIO55

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

22

GPIO54

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

21

GPIO53

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

20

GPIO52

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1103

Registers

www.ti.com

Table 7-124. GPBTOGGLE Register Field Descriptions (continued)

1104

Bit

Field

Type

Reset

Description

19

GPIO51

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

18

GPIO50

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

17

GPIO49

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

16

GPIO48

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

15

GPIO47

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

14

GPIO46

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

13

GPIO45

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

12

GPIO44

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

11

GPIO43

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

10

GPIO42

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

9

GPIO41

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

8

GPIO40

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

7

GPIO39

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

6

GPIO38

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

5

GPIO37

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

4

GPIO36

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

3

GPIO35

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

2

GPIO34

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

1

GPIO33

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

0

GPIO32

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.9

GPCDAT Register (Offset = 10h) [reset = 0h]

GPCDAT is shown in Figure 7-110 and described in Table 7-125.
Return to Summary Table.
GPIO C Data Register (GPIO64 to 95)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the
GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads
of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO
Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise
operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to
GPxDAT are necessary, the entire register should be written at one time.
Figure 7-110. GPCDAT Register
31
GPIO95
R/W-0h

30
GPIO94
R/W-0h

29
GPIO93
R/W-0h

28
GPIO92
R/W-0h

27
GPIO91
R/W-0h

26
GPIO90
R/W-0h

25
GPIO89
R/W-0h

24
GPIO88
R/W-0h

23
GPIO87
R/W-0h

22
GPIO86
R/W-0h

21
GPIO85
R/W-0h

20
GPIO84
R/W-0h

19
GPIO83
R/W-0h

18
GPIO82
R/W-0h

17
GPIO81
R/W-0h

16
GPIO80
R/W-0h

15
GPIO79
R/W-0h

14
GPIO78
R/W-0h

13
GPIO77
R/W-0h

12
GPIO76
R/W-0h

11
GPIO75
R/W-0h

10
GPIO74
R/W-0h

9
GPIO73
R/W-0h

8
GPIO72
R/W-0h

7
GPIO71
R/W-0h

6
GPIO70
R/W-0h

5
GPIO69
R/W-0h

4
GPIO68
R/W-0h

3
GPIO67
R/W-0h

2
GPIO66
R/W-0h

1
GPIO65
R/W-0h

0
GPIO64
R/W-0h

Table 7-125. GPCDAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

0h

Data Register for this pin
Reset type: SYSRSn

30

GPIO94

R/W

0h

Data Register for this pin
Reset type: SYSRSn

29

GPIO93

R/W

0h

Data Register for this pin
Reset type: SYSRSn

28

GPIO92

R/W

0h

Data Register for this pin
Reset type: SYSRSn

27

GPIO91

R/W

0h

Data Register for this pin
Reset type: SYSRSn

26

GPIO90

R/W

0h

Data Register for this pin
Reset type: SYSRSn

25

GPIO89

R/W

0h

Data Register for this pin
Reset type: SYSRSn

24

GPIO88

R/W

0h

Data Register for this pin
Reset type: SYSRSn

23

GPIO87

R/W

0h

Data Register for this pin
Reset type: SYSRSn

22

GPIO86

R/W

0h

Data Register for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1105

Registers

www.ti.com

Table 7-125. GPCDAT Register Field Descriptions (continued)

1106

Bit

Field

Type

Reset

Description

21

GPIO85

R/W

0h

Data Register for this pin
Reset type: SYSRSn

20

GPIO84

R/W

0h

Data Register for this pin
Reset type: SYSRSn

19

GPIO83

R/W

0h

Data Register for this pin
Reset type: SYSRSn

18

GPIO82

R/W

0h

Data Register for this pin
Reset type: SYSRSn

17

GPIO81

R/W

0h

Data Register for this pin
Reset type: SYSRSn

16

GPIO80

R/W

0h

Data Register for this pin
Reset type: SYSRSn

15

GPIO79

R/W

0h

Data Register for this pin
Reset type: SYSRSn

14

GPIO78

R/W

0h

Data Register for this pin
Reset type: SYSRSn

13

GPIO77

R/W

0h

Data Register for this pin
Reset type: SYSRSn

12

GPIO76

R/W

0h

Data Register for this pin
Reset type: SYSRSn

11

GPIO75

R/W

0h

Data Register for this pin
Reset type: SYSRSn

10

GPIO74

R/W

0h

Data Register for this pin
Reset type: SYSRSn

9

GPIO73

R/W

0h

Data Register for this pin
Reset type: SYSRSn

8

GPIO72

R/W

0h

Data Register for this pin
Reset type: SYSRSn

7

GPIO71

R/W

0h

Data Register for this pin
Reset type: SYSRSn

6

GPIO70

R/W

0h

Data Register for this pin
Reset type: SYSRSn

5

GPIO69

R/W

0h

Data Register for this pin
Reset type: SYSRSn

4

GPIO68

R/W

0h

Data Register for this pin
Reset type: SYSRSn

3

GPIO67

R/W

0h

Data Register for this pin
Reset type: SYSRSn

2

GPIO66

R/W

0h

Data Register for this pin
Reset type: SYSRSn

1

GPIO65

R/W

0h

Data Register for this pin
Reset type: SYSRSn

0

GPIO64

R/W

0h

Data Register for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.10 GPCSET Register (Offset = 12h) [reset = 0h]
GPCSET is shown in Figure 7-111 and described in Table 7-126.
Return to Summary Table.
GPIO C Data Set Register (GPIO64 to 95)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-111. GPCSET Register
31
GPIO95
R/W-0h

30
GPIO94
R/W-0h

29
GPIO93
R/W-0h

28
GPIO92
R/W-0h

27
GPIO91
R/W-0h

26
GPIO90
R/W-0h

25
GPIO89
R/W-0h

24
GPIO88
R/W-0h

23
GPIO87
R/W-0h

22
GPIO86
R/W-0h

21
GPIO85
R/W-0h

20
GPIO84
R/W-0h

19
GPIO83
R/W-0h

18
GPIO82
R/W-0h

17
GPIO81
R/W-0h

16
GPIO80
R/W-0h

15
GPIO79
R/W-0h

14
GPIO78
R/W-0h

13
GPIO77
R/W-0h

12
GPIO76
R/W-0h

11
GPIO75
R/W-0h

10
GPIO74
R/W-0h

9
GPIO73
R/W-0h

8
GPIO72
R/W-0h

7
GPIO71
R/W-0h

6
GPIO70
R/W-0h

5
GPIO69
R/W-0h

4
GPIO68
R/W-0h

3
GPIO67
R/W-0h

2
GPIO66
R/W-0h

1
GPIO65
R/W-0h

0
GPIO64
R/W-0h

Table 7-126. GPCSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

30

GPIO94

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

29

GPIO93

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

28

GPIO92

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

27

GPIO91

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

26

GPIO90

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

25

GPIO89

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

24

GPIO88

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

23

GPIO87

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

22

GPIO86

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

21

GPIO85

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

20

GPIO84

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1107

Registers

www.ti.com

Table 7-126. GPCSET Register Field Descriptions (continued)

1108

Bit

Field

Type

Reset

Description

19

GPIO83

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

18

GPIO82

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

17

GPIO81

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

16

GPIO80

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

15

GPIO79

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

14

GPIO78

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

13

GPIO77

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

12

GPIO76

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

11

GPIO75

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

10

GPIO74

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

9

GPIO73

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

8

GPIO72

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

7

GPIO71

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

6

GPIO70

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

5

GPIO69

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

4

GPIO68

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

3

GPIO67

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

2

GPIO66

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

1

GPIO65

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

0

GPIO64

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.11 GPCCLEAR Register (Offset = 14h) [reset = 0h]
GPCCLEAR is shown in Figure 7-112 and described in Table 7-127.
Return to Summary Table.
GPIO C Data Clear Register (GPIO64 to 95)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-112. GPCCLEAR Register
31
GPIO95
R/W-0h

30
GPIO94
R/W-0h

29
GPIO93
R/W-0h

28
GPIO92
R/W-0h

27
GPIO91
R/W-0h

26
GPIO90
R/W-0h

25
GPIO89
R/W-0h

24
GPIO88
R/W-0h

23
GPIO87
R/W-0h

22
GPIO86
R/W-0h

21
GPIO85
R/W-0h

20
GPIO84
R/W-0h

19
GPIO83
R/W-0h

18
GPIO82
R/W-0h

17
GPIO81
R/W-0h

16
GPIO80
R/W-0h

15
GPIO79
R/W-0h

14
GPIO78
R/W-0h

13
GPIO77
R/W-0h

12
GPIO76
R/W-0h

11
GPIO75
R/W-0h

10
GPIO74
R/W-0h

9
GPIO73
R/W-0h

8
GPIO72
R/W-0h

7
GPIO71
R/W-0h

6
GPIO70
R/W-0h

5
GPIO69
R/W-0h

4
GPIO68
R/W-0h

3
GPIO67
R/W-0h

2
GPIO66
R/W-0h

1
GPIO65
R/W-0h

0
GPIO64
R/W-0h

Table 7-127. GPCCLEAR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

30

GPIO94

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

29

GPIO93

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

28

GPIO92

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

27

GPIO91

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

26

GPIO90

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

25

GPIO89

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

24

GPIO88

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

23

GPIO87

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

22

GPIO86

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

21

GPIO85

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

20

GPIO84

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1109

Registers

www.ti.com

Table 7-127. GPCCLEAR Register Field Descriptions (continued)

1110

Bit

Field

Type

Reset

Description

19

GPIO83

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

18

GPIO82

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

17

GPIO81

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

16

GPIO80

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

15

GPIO79

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

14

GPIO78

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

13

GPIO77

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

12

GPIO76

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

11

GPIO75

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

10

GPIO74

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

9

GPIO73

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

8

GPIO72

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

7

GPIO71

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

6

GPIO70

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

5

GPIO69

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

4

GPIO68

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

3

GPIO67

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

2

GPIO66

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

1

GPIO65

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

0

GPIO64

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.12 GPCTOGGLE Register (Offset = 16h) [reset = 0h]
GPCTOGGLE is shown in Figure 7-113 and described in Table 7-128.
Return to Summary Table.
GPIO C Data Toggle Register (GPIO64 to 95)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-113. GPCTOGGLE Register
31
GPIO95
R/W-0h

30
GPIO94
R/W-0h

29
GPIO93
R/W-0h

28
GPIO92
R/W-0h

27
GPIO91
R/W-0h

26
GPIO90
R/W-0h

25
GPIO89
R/W-0h

24
GPIO88
R/W-0h

23
GPIO87
R/W-0h

22
GPIO86
R/W-0h

21
GPIO85
R/W-0h

20
GPIO84
R/W-0h

19
GPIO83
R/W-0h

18
GPIO82
R/W-0h

17
GPIO81
R/W-0h

16
GPIO80
R/W-0h

15
GPIO79
R/W-0h

14
GPIO78
R/W-0h

13
GPIO77
R/W-0h

12
GPIO76
R/W-0h

11
GPIO75
R/W-0h

10
GPIO74
R/W-0h

9
GPIO73
R/W-0h

8
GPIO72
R/W-0h

7
GPIO71
R/W-0h

6
GPIO70
R/W-0h

5
GPIO69
R/W-0h

4
GPIO68
R/W-0h

3
GPIO67
R/W-0h

2
GPIO66
R/W-0h

1
GPIO65
R/W-0h

0
GPIO64
R/W-0h

Table 7-128. GPCTOGGLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO95

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

30

GPIO94

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

29

GPIO93

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

28

GPIO92

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

27

GPIO91

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

26

GPIO90

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

25

GPIO89

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

24

GPIO88

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

23

GPIO87

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

22

GPIO86

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

21

GPIO85

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

20

GPIO84

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1111

Registers

www.ti.com

Table 7-128. GPCTOGGLE Register Field Descriptions (continued)

1112

Bit

Field

Type

Reset

Description

19

GPIO83

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

18

GPIO82

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

17

GPIO81

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

16

GPIO80

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

15

GPIO79

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

14

GPIO78

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

13

GPIO77

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

12

GPIO76

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

11

GPIO75

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

10

GPIO74

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

9

GPIO73

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

8

GPIO72

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

7

GPIO71

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

6

GPIO70

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

5

GPIO69

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

4

GPIO68

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

3

GPIO67

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

2

GPIO66

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

1

GPIO65

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

0

GPIO64

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.13 GPDDAT Register (Offset = 18h) [reset = 0h]
GPDDAT is shown in Figure 7-114 and described in Table 7-129.
Return to Summary Table.
GPIO D Data Register (GPIO96 to 127)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the
GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads
of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO
Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise
operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to
GPxDAT are necessary, the entire register should be written at one time.
Figure 7-114. GPDDAT Register
31
GPIO127
R/W-0h

30
GPIO126
R/W-0h

29
GPIO125
R/W-0h

28
GPIO124
R/W-0h

27
GPIO123
R/W-0h

26
GPIO122
R/W-0h

25
GPIO121
R/W-0h

24
GPIO120
R/W-0h

23
GPIO119
R/W-0h

22
GPIO118
R/W-0h

21
GPIO117
R/W-0h

20
GPIO116
R/W-0h

19
GPIO115
R/W-0h

18
GPIO114
R/W-0h

17
GPIO113
R/W-0h

16
GPIO112
R/W-0h

15
GPIO111
R/W-0h

14
GPIO110
R/W-0h

13
GPIO109
R/W-0h

12
GPIO108
R/W-0h

11
GPIO107
R/W-0h

10
GPIO106
R/W-0h

9
GPIO105
R/W-0h

8
GPIO104
R/W-0h

7
GPIO103
R/W-0h

6
GPIO102
R/W-0h

5
GPIO101
R/W-0h

4
GPIO100
R/W-0h

3
GPIO99
R/W-0h

2
GPIO98
R/W-0h

1
GPIO97
R/W-0h

0
GPIO96
R/W-0h

Table 7-129. GPDDAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO127

R/W

0h

Data Register for this pin
Reset type: SYSRSn

30

GPIO126

R/W

0h

Data Register for this pin
Reset type: SYSRSn

29

GPIO125

R/W

0h

Data Register for this pin
Reset type: SYSRSn

28

GPIO124

R/W

0h

Data Register for this pin
Reset type: SYSRSn

27

GPIO123

R/W

0h

Data Register for this pin
Reset type: SYSRSn

26

GPIO122

R/W

0h

Data Register for this pin
Reset type: SYSRSn

25

GPIO121

R/W

0h

Data Register for this pin
Reset type: SYSRSn

24

GPIO120

R/W

0h

Data Register for this pin
Reset type: SYSRSn

23

GPIO119

R/W

0h

Data Register for this pin
Reset type: SYSRSn

22

GPIO118

R/W

0h

Data Register for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1113

Registers

www.ti.com

Table 7-129. GPDDAT Register Field Descriptions (continued)

1114

Bit

Field

Type

Reset

Description

21

GPIO117

R/W

0h

Data Register for this pin
Reset type: SYSRSn

20

GPIO116

R/W

0h

Data Register for this pin
Reset type: SYSRSn

19

GPIO115

R/W

0h

Data Register for this pin
Reset type: SYSRSn

18

GPIO114

R/W

0h

Data Register for this pin
Reset type: SYSRSn

17

GPIO113

R/W

0h

Data Register for this pin
Reset type: SYSRSn

16

GPIO112

R/W

0h

Data Register for this pin
Reset type: SYSRSn

15

GPIO111

R/W

0h

Data Register for this pin
Reset type: SYSRSn

14

GPIO110

R/W

0h

Data Register for this pin
Reset type: SYSRSn

13

GPIO109

R/W

0h

Data Register for this pin
Reset type: SYSRSn

12

GPIO108

R/W

0h

Data Register for this pin
Reset type: SYSRSn

11

GPIO107

R/W

0h

Data Register for this pin
Reset type: SYSRSn

10

GPIO106

R/W

0h

Data Register for this pin
Reset type: SYSRSn

9

GPIO105

R/W

0h

Data Register for this pin
Reset type: SYSRSn

8

GPIO104

R/W

0h

Data Register for this pin
Reset type: SYSRSn

7

GPIO103

R/W

0h

Data Register for this pin
Reset type: SYSRSn

6

GPIO102

R/W

0h

Data Register for this pin
Reset type: SYSRSn

5

GPIO101

R/W

0h

Data Register for this pin
Reset type: SYSRSn

4

GPIO100

R/W

0h

Data Register for this pin
Reset type: SYSRSn

3

GPIO99

R/W

0h

Data Register for this pin
Reset type: SYSRSn

2

GPIO98

R/W

0h

Data Register for this pin
Reset type: SYSRSn

1

GPIO97

R/W

0h

Data Register for this pin
Reset type: SYSRSn

0

GPIO96

R/W

0h

Data Register for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.14 GPDSET Register (Offset = 1Ah) [reset = 0h]
GPDSET is shown in Figure 7-115 and described in Table 7-130.
Return to Summary Table.
GPIO D Data Set Register (GPIO96 to 127)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-115. GPDSET Register
31
GPIO127
R/W-0h

30
GPIO126
R/W-0h

29
GPIO125
R/W-0h

28
GPIO124
R/W-0h

27
GPIO123
R/W-0h

26
GPIO122
R/W-0h

25
GPIO121
R/W-0h

24
GPIO120
R/W-0h

23
GPIO119
R/W-0h

22
GPIO118
R/W-0h

21
GPIO117
R/W-0h

20
GPIO116
R/W-0h

19
GPIO115
R/W-0h

18
GPIO114
R/W-0h

17
GPIO113
R/W-0h

16
GPIO112
R/W-0h

15
GPIO111
R/W-0h

14
GPIO110
R/W-0h

13
GPIO109
R/W-0h

12
GPIO108
R/W-0h

11
GPIO107
R/W-0h

10
GPIO106
R/W-0h

9
GPIO105
R/W-0h

8
GPIO104
R/W-0h

7
GPIO103
R/W-0h

6
GPIO102
R/W-0h

5
GPIO101
R/W-0h

4
GPIO100
R/W-0h

3
GPIO99
R/W-0h

2
GPIO98
R/W-0h

1
GPIO97
R/W-0h

0
GPIO96
R/W-0h

Table 7-130. GPDSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO127

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

30

GPIO126

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

29

GPIO125

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

28

GPIO124

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

27

GPIO123

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

26

GPIO122

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

25

GPIO121

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

24

GPIO120

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

23

GPIO119

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

22

GPIO118

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

21

GPIO117

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

20

GPIO116

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1115

Registers

www.ti.com

Table 7-130. GPDSET Register Field Descriptions (continued)

1116

Bit

Field

Type

Reset

Description

19

GPIO115

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

18

GPIO114

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

17

GPIO113

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

16

GPIO112

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

15

GPIO111

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

14

GPIO110

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

13

GPIO109

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

12

GPIO108

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

11

GPIO107

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

10

GPIO106

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

9

GPIO105

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

8

GPIO104

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

7

GPIO103

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

6

GPIO102

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

5

GPIO101

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

4

GPIO100

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

3

GPIO99

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

2

GPIO98

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

1

GPIO97

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

0

GPIO96

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.15 GPDCLEAR Register (Offset = 1Ch) [reset = 0h]
GPDCLEAR is shown in Figure 7-116 and described in Table 7-131.
Return to Summary Table.
GPIO D Data Clear Register (GPIO96 to 127)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-116. GPDCLEAR Register
31
GPIO127
R/W-0h

30
GPIO126
R/W-0h

29
GPIO125
R/W-0h

28
GPIO124
R/W-0h

27
GPIO123
R/W-0h

26
GPIO122
R/W-0h

25
GPIO121
R/W-0h

24
GPIO120
R/W-0h

23
GPIO119
R/W-0h

22
GPIO118
R/W-0h

21
GPIO117
R/W-0h

20
GPIO116
R/W-0h

19
GPIO115
R/W-0h

18
GPIO114
R/W-0h

17
GPIO113
R/W-0h

16
GPIO112
R/W-0h

15
GPIO111
R/W-0h

14
GPIO110
R/W-0h

13
GPIO109
R/W-0h

12
GPIO108
R/W-0h

11
GPIO107
R/W-0h

10
GPIO106
R/W-0h

9
GPIO105
R/W-0h

8
GPIO104
R/W-0h

7
GPIO103
R/W-0h

6
GPIO102
R/W-0h

5
GPIO101
R/W-0h

4
GPIO100
R/W-0h

3
GPIO99
R/W-0h

2
GPIO98
R/W-0h

1
GPIO97
R/W-0h

0
GPIO96
R/W-0h

Table 7-131. GPDCLEAR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO127

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

30

GPIO126

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

29

GPIO125

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

28

GPIO124

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

27

GPIO123

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

26

GPIO122

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

25

GPIO121

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

24

GPIO120

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

23

GPIO119

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

22

GPIO118

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

21

GPIO117

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

20

GPIO116

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1117

Registers

www.ti.com

Table 7-131. GPDCLEAR Register Field Descriptions (continued)

1118

Bit

Field

Type

Reset

Description

19

GPIO115

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

18

GPIO114

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

17

GPIO113

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

16

GPIO112

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

15

GPIO111

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

14

GPIO110

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

13

GPIO109

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

12

GPIO108

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

11

GPIO107

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

10

GPIO106

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

9

GPIO105

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

8

GPIO104

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

7

GPIO103

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

6

GPIO102

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

5

GPIO101

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

4

GPIO100

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

3

GPIO99

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

2

GPIO98

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

1

GPIO97

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

0

GPIO96

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.16 GPDTOGGLE Register (Offset = 1Eh) [reset = 0h]
GPDTOGGLE is shown in Figure 7-117 and described in Table 7-132.
Return to Summary Table.
GPIO D Data Toggle Register (GPIO96 to 127)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-117. GPDTOGGLE Register
31
GPIO127
R/W-0h

30
GPIO126
R/W-0h

29
GPIO125
R/W-0h

28
GPIO124
R/W-0h

27
GPIO123
R/W-0h

26
GPIO122
R/W-0h

25
GPIO121
R/W-0h

24
GPIO120
R/W-0h

23
GPIO119
R/W-0h

22
GPIO118
R/W-0h

21
GPIO117
R/W-0h

20
GPIO116
R/W-0h

19
GPIO115
R/W-0h

18
GPIO114
R/W-0h

17
GPIO113
R/W-0h

16
GPIO112
R/W-0h

15
GPIO111
R/W-0h

14
GPIO110
R/W-0h

13
GPIO109
R/W-0h

12
GPIO108
R/W-0h

11
GPIO107
R/W-0h

10
GPIO106
R/W-0h

9
GPIO105
R/W-0h

8
GPIO104
R/W-0h

7
GPIO103
R/W-0h

6
GPIO102
R/W-0h

5
GPIO101
R/W-0h

4
GPIO100
R/W-0h

3
GPIO99
R/W-0h

2
GPIO98
R/W-0h

1
GPIO97
R/W-0h

0
GPIO96
R/W-0h

Table 7-132. GPDTOGGLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO127

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

30

GPIO126

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

29

GPIO125

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

28

GPIO124

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

27

GPIO123

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

26

GPIO122

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

25

GPIO121

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

24

GPIO120

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

23

GPIO119

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

22

GPIO118

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

21

GPIO117

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

20

GPIO116

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1119

Registers

www.ti.com

Table 7-132. GPDTOGGLE Register Field Descriptions (continued)

1120

Bit

Field

Type

Reset

Description

19

GPIO115

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

18

GPIO114

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

17

GPIO113

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

16

GPIO112

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

15

GPIO111

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

14

GPIO110

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

13

GPIO109

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

12

GPIO108

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

11

GPIO107

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

10

GPIO106

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

9

GPIO105

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

8

GPIO104

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

7

GPIO103

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

6

GPIO102

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

5

GPIO101

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

4

GPIO100

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

3

GPIO99

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

2

GPIO98

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

1

GPIO97

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

0

GPIO96

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.17 GPEDAT Register (Offset = 20h) [reset = 0h]
GPEDAT is shown in Figure 7-118 and described in Table 7-133.
Return to Summary Table.
GPIO E Data Register (GPIO128 to 159)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the
GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads
of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO
Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise
operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to
GPxDAT are necessary, the entire register should be written at one time.
Figure 7-118. GPEDAT Register
31
GPIO159
R/W-0h

30
GPIO158
R/W-0h

29
GPIO157
R/W-0h

28
GPIO156
R/W-0h

27
GPIO155
R/W-0h

26
GPIO154
R/W-0h

25
GPIO153
R/W-0h

24
GPIO152
R/W-0h

23
GPIO151
R/W-0h

22
GPIO150
R/W-0h

21
GPIO149
R/W-0h

20
GPIO148
R/W-0h

19
GPIO147
R/W-0h

18
GPIO146
R/W-0h

17
GPIO145
R/W-0h

16
GPIO144
R/W-0h

15
GPIO143
R/W-0h

14
GPIO142
R/W-0h

13
GPIO141
R/W-0h

12
GPIO140
R/W-0h

11
GPIO139
R/W-0h

10
GPIO138
R/W-0h

9
GPIO137
R/W-0h

8
GPIO136
R/W-0h

7
GPIO135
R/W-0h

6
GPIO134
R/W-0h

5
GPIO133
R/W-0h

4
GPIO132
R/W-0h

3
GPIO131
R/W-0h

2
GPIO130
R/W-0h

1
GPIO129
R/W-0h

0
GPIO128
R/W-0h

Table 7-133. GPEDAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

0h

Data Register for this pin
Reset type: SYSRSn

30

GPIO158

R/W

0h

Data Register for this pin
Reset type: SYSRSn

29

GPIO157

R/W

0h

Data Register for this pin
Reset type: SYSRSn

28

GPIO156

R/W

0h

Data Register for this pin
Reset type: SYSRSn

27

GPIO155

R/W

0h

Data Register for this pin
Reset type: SYSRSn

26

GPIO154

R/W

0h

Data Register for this pin
Reset type: SYSRSn

25

GPIO153

R/W

0h

Data Register for this pin
Reset type: SYSRSn

24

GPIO152

R/W

0h

Data Register for this pin
Reset type: SYSRSn

23

GPIO151

R/W

0h

Data Register for this pin
Reset type: SYSRSn

22

GPIO150

R/W

0h

Data Register for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1121

Registers

www.ti.com

Table 7-133. GPEDAT Register Field Descriptions (continued)

1122

Bit

Field

Type

Reset

Description

21

GPIO149

R/W

0h

Data Register for this pin
Reset type: SYSRSn

20

GPIO148

R/W

0h

Data Register for this pin
Reset type: SYSRSn

19

GPIO147

R/W

0h

Data Register for this pin
Reset type: SYSRSn

18

GPIO146

R/W

0h

Data Register for this pin
Reset type: SYSRSn

17

GPIO145

R/W

0h

Data Register for this pin
Reset type: SYSRSn

16

GPIO144

R/W

0h

Data Register for this pin
Reset type: SYSRSn

15

GPIO143

R/W

0h

Data Register for this pin
Reset type: SYSRSn

14

GPIO142

R/W

0h

Data Register for this pin
Reset type: SYSRSn

13

GPIO141

R/W

0h

Data Register for this pin
Reset type: SYSRSn

12

GPIO140

R/W

0h

Data Register for this pin
Reset type: SYSRSn

11

GPIO139

R/W

0h

Data Register for this pin
Reset type: SYSRSn

10

GPIO138

R/W

0h

Data Register for this pin
Reset type: SYSRSn

9

GPIO137

R/W

0h

Data Register for this pin
Reset type: SYSRSn

8

GPIO136

R/W

0h

Data Register for this pin
Reset type: SYSRSn

7

GPIO135

R/W

0h

Data Register for this pin
Reset type: SYSRSn

6

GPIO134

R/W

0h

Data Register for this pin
Reset type: SYSRSn

5

GPIO133

R/W

0h

Data Register for this pin
Reset type: SYSRSn

4

GPIO132

R/W

0h

Data Register for this pin
Reset type: SYSRSn

3

GPIO131

R/W

0h

Data Register for this pin
Reset type: SYSRSn

2

GPIO130

R/W

0h

Data Register for this pin
Reset type: SYSRSn

1

GPIO129

R/W

0h

Data Register for this pin
Reset type: SYSRSn

0

GPIO128

R/W

0h

Data Register for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.18 GPESET Register (Offset = 22h) [reset = 0h]
GPESET is shown in Figure 7-119 and described in Table 7-134.
Return to Summary Table.
GPIO E Data Set Register (GPIO128 to 159)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-119. GPESET Register
31
GPIO159
R/W-0h

30
GPIO158
R/W-0h

29
GPIO157
R/W-0h

28
GPIO156
R/W-0h

27
GPIO155
R/W-0h

26
GPIO154
R/W-0h

25
GPIO153
R/W-0h

24
GPIO152
R/W-0h

23
GPIO151
R/W-0h

22
GPIO150
R/W-0h

21
GPIO149
R/W-0h

20
GPIO148
R/W-0h

19
GPIO147
R/W-0h

18
GPIO146
R/W-0h

17
GPIO145
R/W-0h

16
GPIO144
R/W-0h

15
GPIO143
R/W-0h

14
GPIO142
R/W-0h

13
GPIO141
R/W-0h

12
GPIO140
R/W-0h

11
GPIO139
R/W-0h

10
GPIO138
R/W-0h

9
GPIO137
R/W-0h

8
GPIO136
R/W-0h

7
GPIO135
R/W-0h

6
GPIO134
R/W-0h

5
GPIO133
R/W-0h

4
GPIO132
R/W-0h

3
GPIO131
R/W-0h

2
GPIO130
R/W-0h

1
GPIO129
R/W-0h

0
GPIO128
R/W-0h

Table 7-134. GPESET Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

30

GPIO158

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

29

GPIO157

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

28

GPIO156

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

27

GPIO155

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

26

GPIO154

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

25

GPIO153

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

24

GPIO152

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

23

GPIO151

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

22

GPIO150

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

21

GPIO149

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

20

GPIO148

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1123

Registers

www.ti.com

Table 7-134. GPESET Register Field Descriptions (continued)

1124

Bit

Field

Type

Reset

Description

19

GPIO147

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

18

GPIO146

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

17

GPIO145

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

16

GPIO144

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

15

GPIO143

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

14

GPIO142

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

13

GPIO141

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

12

GPIO140

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

11

GPIO139

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

10

GPIO138

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

9

GPIO137

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

8

GPIO136

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

7

GPIO135

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

6

GPIO134

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

5

GPIO133

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

4

GPIO132

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

3

GPIO131

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

2

GPIO130

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

1

GPIO129

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

0

GPIO128

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.19 GPECLEAR Register (Offset = 24h) [reset = 0h]
GPECLEAR is shown in Figure 7-120 and described in Table 7-135.
Return to Summary Table.
GPIO E Data Clear Register (GPIO128 to 159)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-120. GPECLEAR Register
31
GPIO159
R/W-0h

30
GPIO158
R/W-0h

29
GPIO157
R/W-0h

28
GPIO156
R/W-0h

27
GPIO155
R/W-0h

26
GPIO154
R/W-0h

25
GPIO153
R/W-0h

24
GPIO152
R/W-0h

23
GPIO151
R/W-0h

22
GPIO150
R/W-0h

21
GPIO149
R/W-0h

20
GPIO148
R/W-0h

19
GPIO147
R/W-0h

18
GPIO146
R/W-0h

17
GPIO145
R/W-0h

16
GPIO144
R/W-0h

15
GPIO143
R/W-0h

14
GPIO142
R/W-0h

13
GPIO141
R/W-0h

12
GPIO140
R/W-0h

11
GPIO139
R/W-0h

10
GPIO138
R/W-0h

9
GPIO137
R/W-0h

8
GPIO136
R/W-0h

7
GPIO135
R/W-0h

6
GPIO134
R/W-0h

5
GPIO133
R/W-0h

4
GPIO132
R/W-0h

3
GPIO131
R/W-0h

2
GPIO130
R/W-0h

1
GPIO129
R/W-0h

0
GPIO128
R/W-0h

Table 7-135. GPECLEAR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

30

GPIO158

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

29

GPIO157

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

28

GPIO156

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

27

GPIO155

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

26

GPIO154

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

25

GPIO153

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

24

GPIO152

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

23

GPIO151

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

22

GPIO150

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

21

GPIO149

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

20

GPIO148

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1125

Registers

www.ti.com

Table 7-135. GPECLEAR Register Field Descriptions (continued)

1126

Bit

Field

Type

Reset

Description

19

GPIO147

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

18

GPIO146

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

17

GPIO145

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

16

GPIO144

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

15

GPIO143

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

14

GPIO142

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

13

GPIO141

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

12

GPIO140

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

11

GPIO139

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

10

GPIO138

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

9

GPIO137

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

8

GPIO136

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

7

GPIO135

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

6

GPIO134

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

5

GPIO133

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

4

GPIO132

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

3

GPIO131

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

2

GPIO130

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

1

GPIO129

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

0

GPIO128

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.20 GPETOGGLE Register (Offset = 26h) [reset = 0h]
GPETOGGLE is shown in Figure 7-121 and described in Table 7-136.
Return to Summary Table.
GPIO E Data Toggle Register (GPIO128 to 159)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-121. GPETOGGLE Register
31
GPIO159
R/W-0h

30
GPIO158
R/W-0h

29
GPIO157
R/W-0h

28
GPIO156
R/W-0h

27
GPIO155
R/W-0h

26
GPIO154
R/W-0h

25
GPIO153
R/W-0h

24
GPIO152
R/W-0h

23
GPIO151
R/W-0h

22
GPIO150
R/W-0h

21
GPIO149
R/W-0h

20
GPIO148
R/W-0h

19
GPIO147
R/W-0h

18
GPIO146
R/W-0h

17
GPIO145
R/W-0h

16
GPIO144
R/W-0h

15
GPIO143
R/W-0h

14
GPIO142
R/W-0h

13
GPIO141
R/W-0h

12
GPIO140
R/W-0h

11
GPIO139
R/W-0h

10
GPIO138
R/W-0h

9
GPIO137
R/W-0h

8
GPIO136
R/W-0h

7
GPIO135
R/W-0h

6
GPIO134
R/W-0h

5
GPIO133
R/W-0h

4
GPIO132
R/W-0h

3
GPIO131
R/W-0h

2
GPIO130
R/W-0h

1
GPIO129
R/W-0h

0
GPIO128
R/W-0h

Table 7-136. GPETOGGLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

GPIO159

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

30

GPIO158

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

29

GPIO157

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

28

GPIO156

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

27

GPIO155

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

26

GPIO154

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

25

GPIO153

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

24

GPIO152

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

23

GPIO151

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

22

GPIO150

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

21

GPIO149

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

20

GPIO148

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1127

Registers

www.ti.com

Table 7-136. GPETOGGLE Register Field Descriptions (continued)

1128

Bit

Field

Type

Reset

Description

19

GPIO147

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

18

GPIO146

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

17

GPIO145

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

16

GPIO144

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

15

GPIO143

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

14

GPIO142

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

13

GPIO141

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

12

GPIO140

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

11

GPIO139

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

10

GPIO138

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

9

GPIO137

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

8

GPIO136

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

7

GPIO135

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

6

GPIO134

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

5

GPIO133

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

4

GPIO132

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

3

GPIO131

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

2

GPIO130

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

1

GPIO129

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

0

GPIO128

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.21 GPFDAT Register (Offset = 28h) [reset = 0h]
GPFDAT is shown in Figure 7-122 and described in Table 7-137.
Return to Summary Table.
GPIO F Data Register (GPIO160 to 168)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the
GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads
of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO
Output mode
A system reset will clear all bits and latched values to zero.
NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise
operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to
GPxDAT are necessary, the entire register should be written at one time.
Figure 7-122. GPFDAT Register
31

30

29

28

27

26

25

24

RESERVED
R-0h

RESERVED
R-0h

RESERVED
R-0h

RESERVED
R-0h

RESERVED
R-0h

RESERVED
R-0h

RESERVED
R-0h

RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18
RESERVED
R-0h

17
RESERVED
R-0h

16
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-0h

7
GPIO167
R/W-0h

6
GPIO166
R/W-0h

5
GPIO165
R/W-0h

4
GPIO164
R/W-0h

3
GPIO163
R/W-0h

2
GPIO162
R/W-0h

1
GPIO161
R/W-0h

0
GPIO160
R/W-0h

Table 7-137. GPFDAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1129

Registers

www.ti.com

Table 7-137. GPFDAT Register Field Descriptions (continued)

1130

Bit

Field

Type

Reset

Description

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

GPIO168

R/W

0h

Data Register for this pin
Reset type: SYSRSn

7

GPIO167

R/W

0h

Data Register for this pin
Reset type: SYSRSn

6

GPIO166

R/W

0h

Data Register for this pin
Reset type: SYSRSn

5

GPIO165

R/W

0h

Data Register for this pin
Reset type: SYSRSn

4

GPIO164

R/W

0h

Data Register for this pin
Reset type: SYSRSn

3

GPIO163

R/W

0h

Data Register for this pin
Reset type: SYSRSn

2

GPIO162

R/W

0h

Data Register for this pin
Reset type: SYSRSn

1

GPIO161

R/W

0h

Data Register for this pin
Reset type: SYSRSn

0

GPIO160

R/W

0h

Data Register for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.22 GPFSET Register (Offset = 2Ah) [reset = 0h]
GPFSET is shown in Figure 7-123 and described in Table 7-138.
Return to Summary Table.
GPIO F Data Set Register (GPIO160 to 168)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-123. GPFSET Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18
RESERVED
R-0h

17
RESERVED
R-0h

16
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-0h

7
GPIO167
R/W-0h

6
GPIO166
R/W-0h

5
GPIO165
R/W-0h

4
GPIO164
R/W-0h

3
GPIO163
R/W-0h

2
GPIO162
R/W-0h

1
GPIO161
R/W-0h

0
GPIO160
R/W-0h

Table 7-138. GPFSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

GPIO168

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1131

Registers

www.ti.com

Table 7-138. GPFSET Register Field Descriptions (continued)
Bit

1132

Field

Type

Reset

Description

7

GPIO167

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

6

GPIO166

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

5

GPIO165

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

4

GPIO164

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

3

GPIO163

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

2

GPIO162

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

1

GPIO161

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

0

GPIO160

R/W

0h

Output Set bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.23 GPFCLEAR Register (Offset = 2Ch) [reset = 0h]
GPFCLEAR is shown in Figure 7-124 and described in Table 7-139.
Return to Summary Table.
GPIO F Data Clear Register (GPIO160 to 168)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-124. GPFCLEAR Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18
RESERVED
R-0h

17
RESERVED
R-0h

16
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-0h

7
GPIO167
R/W-0h

6
GPIO166
R/W-0h

5
GPIO165
R/W-0h

4
GPIO164
R/W-0h

3
GPIO163
R/W-0h

2
GPIO162
R/W-0h

1
GPIO161
R/W-0h

0
GPIO160
R/W-0h

Table 7-139. GPFCLEAR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

GPIO168

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1133

Registers

www.ti.com

Table 7-139. GPFCLEAR Register Field Descriptions (continued)
Bit

1134

Field

Type

Reset

Description

7

GPIO167

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

6

GPIO166

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

5

GPIO165

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

4

GPIO164

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

3

GPIO163

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

2

GPIO162

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

1

GPIO161

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

0

GPIO160

R/W

0h

Output Clear bit for this pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

7.9.3.24 GPFTOGGLE Register (Offset = 2Eh) [reset = 0h]
GPFTOGGLE is shown in Figure 7-125 and described in Table 7-140.
Return to Summary Table.
GPIO F Data Toggle Register (GPIO160 to 168)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 7-125. GPFTOGGLE Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18
RESERVED
R-0h

17
RESERVED
R-0h

16
RESERVED
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
GPIO168
R/W-0h

7
GPIO167
R/W-0h

6
GPIO166
R/W-0h

5
GPIO165
R/W-0h

4
GPIO164
R/W-0h

3
GPIO163
R/W-0h

2
GPIO162
R/W-0h

1
GPIO161
R/W-0h

0
GPIO160
R/W-0h

Table 7-140. GPFTOGGLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

GPIO168

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

General-Purpose Input/Output (GPIO)

Copyright © 2013–2017, Texas Instruments Incorporated

1135

Registers

www.ti.com

Table 7-140. GPFTOGGLE Register Field Descriptions (continued)
Bit

1136

Field

Type

Reset

Description

7

GPIO167

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

6

GPIO166

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

5

GPIO165

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

4

GPIO164

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

3

GPIO163

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

2

GPIO162

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

1

GPIO161

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

0

GPIO160

R/W

0h

Output Toggle Register GPIO pin
Reset type: SYSRSn

General-Purpose Input/Output (GPIO)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 8
SPRUHM8G – December 2013 – Revised September 2017

Crossbar (X-BAR)
The crossbars (referred to as X-BAR throughout this document) provide flexibility to connect device inputs,
outputs, and internal resources in a variety of configurations. The device contains a total of three X-BARs:
the Input X-BAR, the Output X-BAR, and the ePWM X-BAR. Each of the X-BARs is named according to
where they take signals. For example, the Input X-BAR brings external signals “in” to the device. The
Output X-BAR takes internal signals “out” of the device to a GPIO. The ePWM X-BAR takes signals and
brings them to the ePWM modules. You can read more about each of these X-BARs in the following
sections.
Topic

8.1
8.2
8.3

...........................................................................................................................

Page

GPIO Input X-BAR ........................................................................................... 1138
ePWM and GPIO Output X-BAR ........................................................................ 1139
X-BAR Registers ............................................................................................. 1145

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1137

GPIO Input X-BAR

8.1

www.ti.com

GPIO Input X-BAR
On this device, the Input X-BAR is used to route signals from a GPIO to many different IP blocks such as
the ADC(s), eCAP(s), ePWM(s), and external interrupts. The Input X-BAR has access to every GPIO and
can route each signal to any (or multiple) of the IP blocks previously mentioned. This flexibility relieves
some of the constraints on peripheral muxing by just requiring any GPIO pin to be available. It is important
to note that the function selected on the GPIO mux does not affect the Input X-BAR. The Input X-BAR
simply connects the signal on the input buffer to the selected destination. Therefore, you can do things
such as route the output of one peripheral to another (that is, measure the output of an ePWM with an
eCAP for a frequency test).
The Input X-BAR is configured via the INPUTxSELECT registers. The available IP destination(s) for each
INPUTx is shown in Figure 8-1. For more information on configuration, see the INPUT_XBAR_REGS
register definitions at the end of this chapter.
Figure 8-1. Input X-BAR

Input X-BAR

INPUT14
INPUT13

GPIOx

Asynchronous
Synchronous
Sync. + Qual.

CPU PIE
CLA

INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12

eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6

INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1

GPIO0

TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3

XINT5
XINT4
XINT3
XINT2
XINT1

TRIP4
TRIP5
ePWM
X-BAR

TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12

ePWM
Modules

TRIP6
ADC

ADCEXTSOC
EXTSYNCIN1
EXTSYNCIN2

ePWM and eCAP
Sync Chain

Output X-BAR

1138Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ePWM and GPIO Output X-BAR

www.ti.com

Table 8-1. Input X-BAR Destinations
Input

8.2

Destinations

INPUT1

ePWM[TZ1,TRIP1], ePWM X-BAR, Output X-BAR

INPUT2

ePWM[TZ2,TRIP2], ePWM X-BAR, Output X-BAR

INPUT3

ePWM[TZ3,TRIP3], ePWM X-BAR, Output X-BAR

INPUT4

XINT1, ePWM X-BAR, Output X-BAR

INPUT5

XINT2, ADCEXTSOC, EXTSYNCIN1, ePWM X-BAR, Output X-BAR

INPUT6

XINT3, ePWM[TRIP6], EXTSYNCIN2, ePWM X-BAR, Output X-BAR

INPUT7

ECAP1

INPUT8

ECAP2

INPUT9

ECAP3

INPUT10

ECAP4

INPUT11

ECAP5

INPUT12

ECAP6

INPUT13

XINT4

INPUT14

XINT5

ePWM and GPIO Output X-BAR

8.2.1 ePWM X-BAR
The ePWM X-BAR brings signals to the ePWM modules. Specifically, the ePWM X-BAR is connected to
the Digital Compare (DC) submodule of each ePWM module for actions such as tripzones and syncing.
Please refer to the ePWM chapter for more information on additional ways the DC submodule can be
used. Figure 8-4 shows the architecture of the ePWM X-BAR. It is worth noting that the architecture of the
ePWM X-BAR is identical to the architecture of the Output X-BAR (with the exception of the output latch).
8.2.1.1

ePWM X-BAR Architecture

The ePWM X-BAR has eight outputs which are routed to each ePWM module. Figure 8-2 represents the
architecture of a single output but it is identical to the architecture of all of the other outputs.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1139

ePWM and GPIO Output X-BAR

www.ti.com

Figure 8-2. ePWM Architecture - Single Output
0.0
0.1
0.2
0.3

0
TRIPxMUXENABLE
(32 bits)
TRIPxMUX0TO15CFG.MUX0

1.0
1.1
1.2
1.3

1

TRIPxMUX0TO15CFG.MUX1

31.0
31.1
31.2
31.3

TRIPOUTINV
(1 bit)

31

TRIPxMUX16TO31CFG.MUX31

First, determine the signal(s) which should be passed to the ePWM by referencing Table 8-3. You may
select up to one signal per mux (32 total muxes) for each TRIPx output. Select the inputs to each mux via
the TRIPxMUX0TO15CFG and TRIPxMUX16TO31CFG registers. In order to pass any signal through to
the ePWM, you must also enable the mux in the TRIPxMUXENABLE register. All muxes which are
enabled will be logically OR’d before being passed on to the respective TRIPx signal on the ePWM. You
may also optionally invert the signal via the TRIPOUTINV register.

1140Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ePWM and GPIO Output X-BAR

www.ti.com

Table 8-2. ePWM X-BAR Mux Configuration Table

(1)

Mux

0

1

2

3

0

CMPSS1.CTRIPH

CMPSS1.CTRIPH_OR_CTRIPL

ADCAEVT1

ECAP1OUT

1

CMPSS1.CTRIPL

INPUTXBAR1

2

CMPSS2.CTRIPH

CMPSS2.CTRIPH_OR_CTRIPL

3

CMPSS2.CTRIPL

INPUTXBAR2

4

CMPSS3.CTRIPH

CMPSS3.CTRIPH_OR_CTRIPL

5

CMPSS3.CTRIPL

INPUTXBAR3

6

CMPSS4.CTRIPH

CMPSS4.CTRIPH_OR_CTRIPL

7

CMPSS4.CTRIPL

INPUTXBAR4

8

CMPSS5.CTRIPH

CMPSS5.CTRIPH_OR_CTRIPL

9

CMPSS5.CTRIPL

INPUTXBAR5

10

CMPSS6.CTRIPH

CMPSS6.CTRIPH_OR_CTRIPL

11

CMPSS6.CTRIPL

INPUTXBAR6

12

CMPSS7.CTRIPH

CMPSS7.CTRIPH_OR_CTRIPL

13

CMPSS7.CTRIPL

ADCSOCAO (1)

14

CMPSS8.CTRIPH

CMPSS8.CTRIPH_OR_CTRIPL

15

CMPSS8.CTRIPL

ADCSOCBO (1)

16

SD1FLT1.COMPH

SD1FLT1.COMPH_OR_COMPL

17

SD1FLT1.COMPL

18

SD1FLT2.COMPH

19

SD1FLT2.COMPL

20

SD1FLT3.COMPH

21

SD1FLT3.COMPL

22

SD1FLT4.COMPH

23

SD1FLT4.COMPL

24

SD2FLT1.COMPH

25

SD2FLT1.COMPL

26

SD2FLT2.COMPH

27

SD2FLT2.COMPL

28

SD2FLT3.COMPH

29

SD2FLT3.COMPL

30

SD2FLT4.COMPH

31

SD2FLT4.COMPL

ADCCEVT1
ADCAEVT2

ECAP2OUT

ADCAEVT3

ECAP3OUT

ADCAEVT4

ECAP4OUT

ADCCEVT2
ADCCEVT3
ADCCEVT4
ADCBEVT1

ECAP5OUT

ADCBEVT2

ECAP6OUT

ADCDEVT1
ADCDEVT2
ADCBEVT3
ADCDEVT3
ADCBEVT4

EXTSYNCOUT
ADCDEVT4

SD1FLT2.COMPH_OR_COMPL
SD1FLT3.COMPH_OR_COMPL
SD1FLT4.COMPH_OR_COMPL
SD2FLT1.COMPH_OR_COMPL
SD2FLT2.COMPH_OR_COMPL
SD2FLT3.COMPH_OR_COMPL
SD2FLT4.COMPH_OR_COMPL

This signal is active high when routed through the X-Bar. It may need to be inverted by the respective TRIPOUTINV bit depending on the
application.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1141

ePWM and GPIO Output X-BAR

www.ti.com

8.2.2 GPIO Output X-BAR
The GPIO Output X-BAR takes signals from inside the device and brings them out to a GPIO. Figure 8-3
shows the architecture of the GPIO Output X-BAR. The signals which are available to bring to the GPIO
are listed in Table 8-3. The X-BAR contains eight outputs and each will contain at least one position on
the GPIO mux, denoted as OUTPUTXBARx. The X-BAR allows the selection of a single signal or a logical
OR of up to 32 signals.
8.2.2.1

GPIO Output X-BAR Architecture

The Output X-BAR has eight outputs which are routed to the GPIO module. Figure 8-3 represents the
architecture of a single output, but it is identical to the architecture of all of the other outputs. It is worth
noting that the architecture of the Output X-BAR (with the exception of the output latch) is identical to the
architecture of the ePWM X-BAR.
Figure 8-3. GPIO Output X-BAR Architecture
0.0
0.1
0.2
0.3

0
OUTPUTxMUXENABLE
(32 bits)
OUTPUTxMUX0TO15CFG.MUX0

1.0
1.1
1.2
1.3

1

OUTPUTx

OUTPUTxMUX0TO15CFG.MUX1

OUTPUTLATCHENABLE
31.0
31.1
31.2
31.3

D
31

Q

OLAT

OUTPUTINV

Q
OUTPUTxMUX16TO31CFG.MUX31

OUTPUTLATCHFRC

OUTPUTLATCHCLR

First, determine the signal(s) which should be passed to the GPIO by referencing Table 8-3. You may
select up to one signal per mux (32 total muxes) for each OUTPUTXBARx output. Select the inputs to
each mux via the OUTPUTxMUX0TO15CFG and OUTPUTxMUX16TO31CFG registers.
In order to pass any signal through to the GPIO, you must also enable the mux in the
OUTPUTxMUXENABLE register. All muxes which are enabled will be logically OR’d before being passed
on to the respective OUTPUTx signal on the GPIO module. You may also optionally invert the signal via
the OUTPUTINV register. The signal will only be seen on the GPIO if the proper OUTPUTx muxing
options are selected via the GpioCtrlRegs.GPxMUX and GpioCtrlRegs.GPxGMUX registers.

1142Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ePWM and GPIO Output X-BAR

www.ti.com

Table 8-3. Output X-Bar Mux Configuration Table

(1)

Mux

0

1

2

3

0

CMPSS1.CTRIPOUTH

CMPSS1.CTRIPOUTH_OR_CTRIPOUTL

ADCAEVT1

ECAP1OUT

1

CMPSS1.CTRIPOUTL

INPUTXBAR1

2

CMPSS2.CTRIPOUTH

CMPSS2.CTRIPOUTH_OR_CTRIPOUTL

3

CMPSS2.CTRIPOUTL

INPUTXBAR2

4

CMPSS3.CTRIPOUTH

CMPSS3.CTRIPOUTH_OR_CTRIPOUTL

5

CMPSS3.CTRIPOUTL

INPUTXBAR3

6

CMPSS4.CTRIPOUTH

CMPSS4.CTRIPOUTH_OR_CTRIPOUTL

7

CMPSS4.CTRIPOUTL

INPUTXBAR4

8

CMPSS5.CTRIPOUTH

CMPSS5.CTRIPOUTH_OR_CTRIPOUTL

9

CMPSS5.CTRIPOUTL

INPUTXBAR5

10

CMPSS6.CTRIPOUTH

CMPSS6.CTRIPOUTH_OR_CTRIPOUTL

11

CMPSS6.CTRIPOUTL

INPUTXBAR6

12

CMPSS7.CTRIPOUTH

CMPSS7.CTRIPOUTH_OR_CTRIPOUTL

13

CMPSS7.CTRIPOUTL

ADCSOCAO (1)

14

CMPSS8.CTRIPOUTH

CMPSS8.CTRIPOUTH_OR_CTRIPOUTL

15

CMPSS8.CTRIPOUTL

ADCSOCBO (1)

16

SD1FLT1.COMPH

SD1FLT1.COMPH_OR_COMPL

17

SD1FLT1.COMPL

18

SD1FLT2.COMPH

19

SD1FLT2.COMPL

20

SD1FLT3.COMPH

21

SD1FLT3.COMPL

22

SD1FLT4.COMPH

23

SD1FLT4.COMPL

24

SD2FLT1.COMPH

25

SD2FLT1.COMPL

26

SD2FLT2.COMPH

27

SD2FLT2.COMPL

28

SD2FLT3.COMPH

29

SD2FLT3.COMPL

30

SD2FLT4.COMPH

31

SD2FLT4.COMPL

ADCCEVT1
ADCAEVT2

ECAP2OUT

ADCAEVT3

ECAP3OUT

ADCAEVT4

ECAP4OUT

ADCCEVT2
ADCCEVT3
ADCCEVT4
ADCBEVT1

ECAP5OUT

ADCBEVT2

ECAP6OUT

ADCDEVT1
ADCDEVT2
ADCBEVT3
ADCDEVT3
ADCBEVT4

EXTSYNCOUT
ADCDEVT4

SD1FLT2.COMPH_OR_COMPL
SD1FLT3.COMPH_OR_COMPL
SD1FLT4.COMPH_OR_COMPL
SD2FLT1.COMPH_OR_COMPL
SD2FLT2.COMPH_OR_COMPL
SD2FLT3.COMPH_OR_COMPL
SD2FLT4.COMPH_OR_COMPL

This signal is active high when routed through the X-Bar. It may need to be inverted by the respective OUTPUTINV bit depending on the
application.

8.2.3

X-BAR Flags
With the exception of the CMPSS signals, the ePWM X-BAR and the Output X-BAR have all of the same
input signals. Due to the inputs being similar, the ePWM X-BAR and Output X-BAR leverage a single set
of input flags to indicate which input signals have been triggered. This allows software to check the input
flags when an event occurs. See Figure 8-4 for more information. There is a bit allocated for each input
signal in one of the XBARFLGx registers. The flag will remain set until cleared through the appropriate
XBARCLRx register.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1143

ePWM and GPIO Output X-BAR

www.ti.com

Figure 8-4. ePWM and Output X-BARs Architectures
CTRIPOUTH
CTRIPOUTL

(Output X-BAR only)

CMPSSx
CTRIPH
CTRIPL

ePWM and eCAP
Sync Chain

EXTSYNCOUT

ADCSOCAO
Select Ckt

ADCSOCAO

ADCSOCBO
Select Ckt

ADCSOCBO

eCAPx

ECAPxOUT

ADCx

Output
X-BAR

EVT1
EVT2
EVT3
EVT4
INPUT1
INPUT2
INPUT3

Input X-Bar

(ePWM X-BAR only)

OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8

GPIO
Mux

TRIP4
TRIP5

ePWM
X-BAR

INPUT4
INPUT5
INPUT6

TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12

All
ePWM
Modules

OTHER DESTINATIONS
(see Input X-BAR)
FLT1.COMPH

X-BAR Flags
(shared)

FLT1.COMPL

SDFMx
FLT4.COMPH
FLT4.COMPL

1144

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3

X-BAR Registers

8.3.1 X-BAR Base Addresses
Table 8-4. X-BAR Base Address Table
Start Address

End Address

InputXbarRegs (1)

Device Registers

INPUT_XBAR_REGS

0x0000_7900

0x0000_791F

XbarRegs (1)

XBAR_REGS

0x0000 7920

0x0000_793F

ePWM_XBAR_REGS

0x0000_7A00

0x0000_7A3F

OUTPUT_XBAR_REGS

0x0000_7A80

0x0000_7ABF

EPwmXbarRegs

(1)

OutputXbarRegs (1)
(1)

Register Name

Only available on CPU1.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1145

X-BAR Registers

www.ti.com

8.3.2 INPUT_XBAR_REGS Registers
Table 8-5 lists the memory-mapped registers for the INPUT_XBAR_REGS. All register offset addresses
not listed in Table 8-5 should be considered as reserved locations and the register contents should not be
modified.
Table 8-5. INPUT_XBAR_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

INPUT1SELECT

INPUT1 Input Select Register (GPIO0 to x)

EALLOW

Go

1h

INPUT2SELECT

INPUT2 Input Select Register (GPIO0 to x)

EALLOW

Go

2h

INPUT3SELECT

INPUT3 Input Select Register (GPIO0 to x)

EALLOW

Go

3h

INPUT4SELECT

INPUT4 Input Select Register (GPIO0 to x)

EALLOW

Go

4h

INPUT5SELECT

INPUT5 Input Select Register (GPIO0 to x)

EALLOW

Go

5h

INPUT6SELECT

INPUT6 Input Select Register (GPIO0 to x)

EALLOW

Go

6h

INPUT7SELECT

INPUT7 Input Select Register (GPIO0 to x)

EALLOW

Go

7h

INPUT8SELECT

INPUT8 Input Select Register (GPIO0 to x)

EALLOW

Go

8h

INPUT9SELECT

INPUT9 Input Select Register (GPIO0 to x)

EALLOW

Go

9h

INPUT10SELECT

INPUT10 Input Select Register (GPIO0 to x)

EALLOW

Go

Ah

INPUT11SELECT

INPUT11 Input Select Register (GPIO0 to x)

EALLOW

Go

Bh

INPUT12SELECT

INPUT12 Input Select Register (GPIO0 to x)

EALLOW

Go

Ch

INPUT13SELECT

INPUT13 Input Select Register (GPIO0 to x)

EALLOW

Go

Dh

INPUT14SELECT

INPUT14 Input Select Register (GPIO0 to x)

EALLOW

Go

1Eh

INPUTSELECTLOCK

Input Select Lock Register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 8-6 shows the codes that are
used for access types in this section.
Table 8-6. INPUT_XBAR_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

1146

Crossbar (X-BAR)

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.2.1

INPUT1SELECT Register (Offset = 0h) [reset = 0h]

INPUT1SELECT is shown in Figure 8-5 and described in Table 8-7.
Return to Summary Table.
INPUT1 Input Select Register (GPIO0 to x)
Figure 8-5. INPUT1SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-7. INPUT1SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT1 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1147

X-BAR Registers

8.3.2.2

www.ti.com

INPUT2SELECT Register (Offset = 1h) [reset = 0h]

INPUT2SELECT is shown in Figure 8-6 and described in Table 8-8.
Return to Summary Table.
INPUT2 Input Select Register (GPIO0 to x)
Figure 8-6. INPUT2SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-8. INPUT2SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT2 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

1148

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.2.3

INPUT3SELECT Register (Offset = 2h) [reset = 0h]

INPUT3SELECT is shown in Figure 8-7 and described in Table 8-9.
Return to Summary Table.
INPUT3 Input Select Register (GPIO0 to x)
Figure 8-7. INPUT3SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-9. INPUT3SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT3 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1149

X-BAR Registers

8.3.2.4

www.ti.com

INPUT4SELECT Register (Offset = 3h) [reset = 0h]

INPUT4SELECT is shown in Figure 8-8 and described in Table 8-10.
Return to Summary Table.
INPUT4 Input Select Register (GPIO0 to x)
Figure 8-8. INPUT4SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-10. INPUT4SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT4 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

1150

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.2.5

INPUT5SELECT Register (Offset = 4h) [reset = 0h]

INPUT5SELECT is shown in Figure 8-9 and described in Table 8-11.
Return to Summary Table.
INPUT5 Input Select Register (GPIO0 to x)
Figure 8-9. INPUT5SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-11. INPUT5SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT5 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1151

X-BAR Registers

8.3.2.6

www.ti.com

INPUT6SELECT Register (Offset = 5h) [reset = 0h]

INPUT6SELECT is shown in Figure 8-10 and described in Table 8-12.
Return to Summary Table.
INPUT6 Input Select Register (GPIO0 to x)
Figure 8-10. INPUT6SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-12. INPUT6SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT6 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

1152

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.2.7

INPUT7SELECT Register (Offset = 6h) [reset = 0h]

INPUT7SELECT is shown in Figure 8-11 and described in Table 8-13.
Return to Summary Table.
INPUT7 Input Select Register (GPIO0 to x)
Figure 8-11. INPUT7SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-13. INPUT7SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT7 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1153

X-BAR Registers

8.3.2.8

www.ti.com

INPUT8SELECT Register (Offset = 7h) [reset = 0h]

INPUT8SELECT is shown in Figure 8-12 and described in Table 8-14.
Return to Summary Table.
INPUT8 Input Select Register (GPIO0 to x)
Figure 8-12. INPUT8SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-14. INPUT8SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT8 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

1154

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.2.9

INPUT9SELECT Register (Offset = 8h) [reset = 0h]

INPUT9SELECT is shown in Figure 8-13 and described in Table 8-15.
Return to Summary Table.
INPUT9 Input Select Register (GPIO0 to x)
Figure 8-13. INPUT9SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-15. INPUT9SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT9 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1155

X-BAR Registers

www.ti.com

8.3.2.10 INPUT10SELECT Register (Offset = 9h) [reset = 0h]
INPUT10SELECT is shown in Figure 8-14 and described in Table 8-16.
Return to Summary Table.
INPUT10 Input Select Register (GPIO0 to x)
Figure 8-14. INPUT10SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-16. INPUT10SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT10 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

1156

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.2.11 INPUT11SELECT Register (Offset = Ah) [reset = 0h]
INPUT11SELECT is shown in Figure 8-15 and described in Table 8-17.
Return to Summary Table.
INPUT11 Input Select Register (GPIO0 to x)
Figure 8-15. INPUT11SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-17. INPUT11SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT11 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1157

X-BAR Registers

www.ti.com

8.3.2.12 INPUT12SELECT Register (Offset = Bh) [reset = 0h]
INPUT12SELECT is shown in Figure 8-16 and described in Table 8-18.
Return to Summary Table.
INPUT12 Input Select Register (GPIO0 to x)
Figure 8-16. INPUT12SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-18. INPUT12SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT12 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

1158

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.2.13 INPUT13SELECT Register (Offset = Ch) [reset = 0h]
INPUT13SELECT is shown in Figure 8-17 and described in Table 8-19.
Return to Summary Table.
INPUT13 Input Select Register (GPIO0 to x)
Figure 8-17. INPUT13SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-19. INPUT13SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT13 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1159

X-BAR Registers

www.ti.com

8.3.2.14 INPUT14SELECT Register (Offset = Dh) [reset = 0h]
INPUT14SELECT is shown in Figure 8-18 and described in Table 8-20.
Return to Summary Table.
INPUT14 Input Select Register (GPIO0 to x)
Figure 8-18. INPUT14SELECT Register
15

14

13

12

11

10

9

8
7
SELECT
R/W-0h

6

5

4

3

2

1

0

Table 8-20. INPUT14SELECT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SELECT

R/W

0h

Select GPIO for INPUT14 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xn : Select GPIOn
Reset type: CPU1.SYSRSn

1160

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.2.15 INPUTSELECTLOCK Register (Offset = 1Eh) [reset = 0h]
INPUTSELECTLOCK is shown in Figure 8-19 and described in Table 8-21.
Return to Summary Table.
Input Select Lock Register
Figure 8-19. INPUTSELECTLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15
INPUT16SELE
CT
R/WSOnce-0h

14
INPUT15SELE
CT
R/WSOnce-0h

13
INPUT14SELE
CT
R/WSOnce-0h

12
INPUT13SELE
CT
R/WSOnce-0h

11
INPUT12SELE
CT
R/WSOnce-0h

10
INPUT11SELE
CT
R/WSOnce-0h

9
INPUT10SELE
CT
R/WSOnce-0h

8
INPUT9SELEC
T
R/WSOnce-0h

7
INPUT8SELEC
T
R/WSOnce-0h

6
INPUT7SELEC
T
R/WSOnce-0h

5
INPUT6SELEC
T
R/WSOnce-0h

4
INPUT5SELEC
T
R/WSOnce-0h

3
INPUT4SELEC
T
R/WSOnce-0h

2
INPUT3SELEC
T
R/WSOnce-0h

1
INPUT2SELEC
T
R/WSOnce-0h

0
INPUT1SELEC
T
R/WSOnce-0h

Table 8-21. INPUTSELECTLOCK Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

INPUT16SELECT

R/WSOnce

0h

Lock bit for INPUT16SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

14

INPUT15SELECT

R/WSOnce

0h

Lock bit for INPUT15SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1161

X-BAR Registers

www.ti.com

Table 8-21. INPUTSELECTLOCK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

INPUT14SELECT

R/WSOnce

0h

Lock bit for INPUT14SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

12

INPUT13SELECT

R/WSOnce

0h

Lock bit for INPUT13SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

11

INPUT12SELECT

R/WSOnce

0h

Lock bit for INPUT12SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

10

INPUT11SELECT

R/WSOnce

0h

Lock bit for INPUT11SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

9

INPUT10SELECT

R/WSOnce

0h

Lock bit for INPUT10SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

1162

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-21. INPUTSELECTLOCK Register Field Descriptions (continued)
Bit
8

Field

Type

Reset

Description

INPUT9SELECT

R/WSOnce

0h

Lock bit for INPUT9SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

7

INPUT8SELECT

R/WSOnce

0h

Lock bit for INPUT8SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

6

INPUT7SELECT

R/WSOnce

0h

Lock bit for INPUT7SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

5

INPUT6SELECT

R/WSOnce

0h

Lock bit for INPUT6SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

4

INPUT5SELECT

R/WSOnce

0h

Lock bit for INPUT5SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1163

X-BAR Registers

www.ti.com

Table 8-21. INPUTSELECTLOCK Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

INPUT4SELECT

R/WSOnce

0h

Lock bit for INPUT4SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

2

INPUT3SELECT

R/WSOnce

0h

Lock bit for INPUT3SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

1

INPUT2SELECT

R/WSOnce

0h

Lock bit for INPUT2SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

0

INPUT1SELECT

R/WSOnce

0h

Lock bit for INPUT1SELECT Register:
0: Respective register is not locked
1: Respective register is locked.
Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
Notes:
[1] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed.
Reset type: CPU1.SYSRSn

1164

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.3 XBAR_REGS Registers
Table 8-22 lists the memory-mapped registers for the XBAR_REGS. All register offset addresses not listed
in Table 8-22 should be considered as reserved locations and the register contents should not be
modified.
Table 8-22. XBAR_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

XBARFLG1

X-Bar Input Flag Register 1

Go

2h

XBARFLG2

X-Bar Input Flag Register 2

Go

4h

XBARFLG3

X-Bar Input Flag Register 3

Go

8h

XBARCLR1

X-Bar Input Flag Clear Register 1

Go

Ah

XBARCLR2

X-Bar Input Flag Clear Register 2

Go

Ch

XBARCLR3

X-Bar Input Flag Clear Register 3

Go

Complex bit access types are encoded to fit into small table cells. Table 8-23 shows the codes that are
used for access types in this section.
Table 8-23. XBAR_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

Write

Read Type

Write Type
W=1

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1165

X-BAR Registers

8.3.3.1

www.ti.com

XBARFLG1 Register (Offset = 0h) [reset = 0h]

XBARFLG1 is shown in Figure 8-20 and described in Table 8-24.
Return to Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources
which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Figure 8-20. XBARFLG1 Register
31
30
29
28
27
26
25
24
CMPSS8_CTRI CMPSS8_CTRI CMPSS7_CTRI CMPSS7_CTRI CMPSS6_CTRI CMPSS6_CTRI CMPSS5_CTRI CMPSS5_CTRI
POUTH
POUTL
POUTH
POUTL
POUTH
POUTL
POUTH
POUTL
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
23
22
21
20
19
18
17
16
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
POUTH
POUTL
POUTH
POUTL
POUTH
POUTL
POUTH
POUTL
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
15
14
13
12
11
10
9
8
CMPSS8_CTRI CMPSS8_CTRI CMPSS7_CTRI CMPSS7_CTRI CMPSS6_CTRI CMPSS6_CTRI CMPSS5_CTRI CMPSS5_CTRI
PH
PL
PH
PL
PH
PL
PH
PL
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
7
6
5
4
3
2
1
0
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
PH
PL
PH
PL
PH
PL
PH
PL
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h

Table 8-24. XBARFLG1 Register Field Descriptions

1166

Bit

Field

Type

Reset

Description

31

CMPSS8_CTRIPOUTH

R

0h

CMPSS8_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn

30

CMPSS8_CTRIPOUTL

R

0h

CMPSS8_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

29

CMPSS7_CTRIPOUTH

R

0h

CMPSS7_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn

28

CMPSS7_CTRIPOUTL

R

0h

CMPSS7_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

27

CMPSS6_CTRIPOUTH

R

0h

CMPSS6_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn

26

CMPSS6_CTRIPOUTL

R

0h

CMPSS6_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

25

CMPSS5_CTRIPOUTH

R

0h

CMPSS5_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn

24

CMPSS5_CTRIPOUTL

R

0h

CMPSS5_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

23

CMPSS4_CTRIPOUTH

R

0h

CMPSS4_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn

22

CMPSS4_CTRIPOUTL

R

0h

CMPSS4_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

21

CMPSS3_CTRIPOUTH

R

0h

CMPSS3_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-24. XBARFLG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

CMPSS3_CTRIPOUTL

R

0h

CMPSS3_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

19

CMPSS2_CTRIPOUTH

R

0h

CMPSS2_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn

18

CMPSS2_CTRIPOUTL

R

0h

CMPSS2_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

17

CMPSS1_CTRIPOUTH

R

0h

CMPSS1_CTRIPOUTH X-BAR Flag
Reset type: CPU1.SYSRSn

16

CMPSS1_CTRIPOUTL

R

0h

CMPSS1_CTRIPOUTL X-BAR Flag
Reset type: CPU1.SYSRSn

15

CMPSS8_CTRIPH

R

0h

CMPSS8_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn

14

CMPSS8_CTRIPL

R

0h

CMPSS8_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

13

CMPSS7_CTRIPH

R

0h

CMPSS7_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn

12

CMPSS7_CTRIPL

R

0h

CMPSS7_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

11

CMPSS6_CTRIPH

R

0h

CMPSS6_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn

10

CMPSS6_CTRIPL

R

0h

CMPSS6_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

9

CMPSS5_CTRIPH

R

0h

CMPSS5_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn

8

CMPSS5_CTRIPL

R

0h

CMPSS5_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

7

CMPSS4_CTRIPH

R

0h

CMPSS4_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn

6

CMPSS4_CTRIPL

R

0h

CMPSS4_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

5

CMPSS3_CTRIPH

R

0h

CMPSS3_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn

4

CMPSS3_CTRIPL

R

0h

CMPSS3_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

3

CMPSS2_CTRIPH

R

0h

CMPSS2_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn

2

CMPSS2_CTRIPL

R

0h

CMPSS2_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

1

CMPSS1_CTRIPH

R

0h

CMPSS1_CTRIPH X-BAR Flag
Reset type: CPU1.SYSRSn

0

CMPSS1_CTRIPL

R

0h

CMPSS1_CTRIPL X-BAR Flag
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1167

X-BAR Registers

8.3.3.2

www.ti.com

XBARFLG2 Register (Offset = 2h) [reset = 0h]

XBARFLG2 is shown in Figure 8-21 and described in Table 8-25.
Return to Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources
which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Figure 8-21. XBARFLG2 Register
31
ADCCEVT1
R-0h

30
ADCBEVT4
R-0h

29
ADCBEVT3
R-0h

28
ADCBEVT2
R-0h

27
ADCBEVT1
R-0h

26
ADCAEVT4
R-0h

25
ADCAEVT3
R-0h

24
ADCAEVT2
R-0h

23
ADCAEVT1
R-0h

22
EXTSYNCOUT
R-0h

21
ECAP6_OUT
R-0h

20
ECAP5_OUT
R-0h

19
ECAP4_OUT
R-0h

18
ECAP3_OUT
R-0h

17
ECAP2_OUT
R-0h

16
ECAP1_OUT
R-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
RESERVED
R-0h

7
ADCSOCBO
R-0h

6
ADCSOCAO
R-0h

5
INPUT6
R-0h

4
INPUT5
R-0h

3
INPUT4
R-0h

2
INPUT3
R-0h

1
INPUT2
R-0h

0
INPUT1
R-0h

Table 8-25. XBARFLG2 Register Field Descriptions

1168

Bit

Field

Type

Reset

Description

31

ADCCEVT1

R

0h

ADCCEVT1 X-BAR Flag
Reset type: CPU1.SYSRSn

30

ADCBEVT4

R

0h

ADCBEVT4 X-BAR Flag
Reset type: CPU1.SYSRSn

29

ADCBEVT3

R

0h

ADCBEVT3 X-BAR Flag
Reset type: CPU1.SYSRSn

28

ADCBEVT2

R

0h

ADCBEVT2 X-BAR Flag
Reset type: CPU1.SYSRSn

27

ADCBEVT1

R

0h

ADCBEVT1 X-BAR Flag
Reset type: CPU1.SYSRSn

26

ADCAEVT4

R

0h

ADCAEVT4 X-BAR Flag
Reset type: CPU1.SYSRSn

25

ADCAEVT3

R

0h

ADCAEVT3 X-BAR Flag
Reset type: CPU1.SYSRSn

24

ADCAEVT2

R

0h

ADCAEVT2 X-BAR Flag
Reset type: CPU1.SYSRSn

23

ADCAEVT1

R

0h

ADCAEVT1 X-BAR Flag
Reset type: CPU1.SYSRSn

22

EXTSYNCOUT

R

0h

EXTSYNCOUT X-BAR Flag
Reset type: CPU1.SYSRSn

21

ECAP6_OUT

R

0h

ECAP6_OUT X-BAR Flag
Reset type: CPU1.SYSRSn

20

ECAP5_OUT

R

0h

ECAP5_OUT X-BAR Flag
Reset type: CPU1.SYSRSn

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-25. XBARFLG2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

19

ECAP4_OUT

R

0h

ECAP4_OUT X-BAR Flag
Reset type: CPU1.SYSRSn

18

ECAP3_OUT

R

0h

ECAP3_OUT X-BAR Flag
Reset type: CPU1.SYSRSn

17

ECAP2_OUT

R

0h

ECAP2_OUT X-BAR Flag
Reset type: CPU1.SYSRSn

16

ECAP1_OUT

R

0h

ECAP1_OUT X-BAR Flag
Reset type: CPU1.SYSRSn

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

RESERVED

R

0h

Reserved

7

ADCSOCBO

R

0h

ADCSOCBO X-BAR Flag
Reset type: CPU1.SYSRSn

6

ADCSOCAO

R

0h

ADCSOCAO X-BAR Flag
Reset type: CPU1.SYSRSn

5

INPUT6

R

0h

INPUT6 X-BAR Flag
Reset type: CPU1.SYSRSn

4

INPUT5

R

0h

INPUT5 X-BAR Flag
Reset type: CPU1.SYSRSn

3

INPUT4

R

0h

INPUT4 X-BAR Flag
Reset type: CPU1.SYSRSn

2

INPUT3

R

0h

INPUT3 X-BAR Flag
Reset type: CPU1.SYSRSn

1

INPUT2

R

0h

INPUT2 X-BAR Flag
Reset type: CPU1.SYSRSn

0

INPUT1

R

0h

INPUT1 X-BAR Flag
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1169

X-BAR Registers

8.3.3.3

www.ti.com

XBARFLG3 Register (Offset = 4h) [reset = 0h]

XBARFLG3 is shown in Figure 8-22 and described in Table 8-26.
Return to Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources
which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Figure 8-22. XBARFLG3 Register
31

30

29

28

27

26

25

24

RESERVED
R=0-0h
23
RESERVED
R=0-0h

22
SD2FLT4_CO
MPH
R-0h

21
SD2FLT4_CO
MPL
R-0h

20
SD2FLT3_CO
MPH
R-0h

19
SD2FLT3_CO
MPL
R-0h

18
SD2FLT2_CO
MPH
R-0h

17
SD2FLT2_CO
MPL
R-0h

16
SD2FLT1_CO
MPH
R-0h

15
SD2FLT1_CO
MPL
R-0h

14
SD1FLT4_CO
MPH
R-0h

13
SD1FLT4_CO
MPL
R-0h

12
SD1FLT3_CO
MPH
R-0h

11
SD1FLT3_CO
MPL
R-0h

10
SD1FLT2_CO
MPH
R-0h

9
SD1FLT2_CO
MPL
R-0h

8
SD1FLT1_CO
MPH
R-0h

7
SD1FLT1_CO
MPL
R-0h

6
ADCDEVT4

5
ADCDEVT3

4
ADCDEVT2

3
ADCDEVT1

2
ADCCEVT4

1
ADCCEVT3

0
ADCCEVT2

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

R-0h

Table 8-26. XBARFLG3 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

22

SD2FLT4_COMPH

R

0h

SD2FLT4_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn

21

SD2FLT4_COMPL

R

0h

SD2FLT4_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

20

SD2FLT3_COMPH

R

0h

SD2FLT3_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn

19

SD2FLT3_COMPL

R

0h

SD2FLT3_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

18

SD2FLT2_COMPH

R

0h

SD2FLT2_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn

17

SD2FLT2_COMPL

R

0h

SD2FLT2_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

16

SD2FLT1_COMPH

R

0h

SD2FLT1_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn

15

SD2FLT1_COMPL

R

0h

SD2FLT1_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

14

SD1FLT4_COMPH

R

0h

SD1FLT4_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn

13

SD1FLT4_COMPL

R

0h

SD1FLT4_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

12

SD1FLT3_COMPH

R

0h

SD1FLT3_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn

31-23

1170

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-26. XBARFLG3 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

SD1FLT3_COMPL

R

0h

SD1FLT3_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

10

SD1FLT2_COMPH

R

0h

SD1FLT2_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn

9

SD1FLT2_COMPL

R

0h

SD1FLT2_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

8

SD1FLT1_COMPH

R

0h

SD1FLT1_COMPH X-BAR Flag
Reset type: CPU1.SYSRSn

7

SD1FLT1_COMPL

R

0h

SD1FLT1_COMPL X-BAR Flag
Reset type: CPU1.SYSRSn

6

ADCDEVT4

R

0h

ADCDEVT4 X-BAR Flag
Reset type: CPU1.SYSRSn

5

ADCDEVT3

R

0h

ADCDEVT3 X-BAR Flag
Reset type: CPU1.SYSRSn

4

ADCDEVT2

R

0h

ADCDEVT2 X-BAR Flag
Reset type: CPU1.SYSRSn

3

ADCDEVT1

R

0h

ADCDEVT1 X-BAR Flag
Reset type: CPU1.SYSRSn

2

ADCCEVT4

R

0h

ADCCEVT4 X-BAR Flag
Reset type: CPU1.SYSRSn

1

ADCCEVT3

R

0h

ADCCEVT3 X-BAR Flag
Reset type: CPU1.SYSRSn

0

ADCCEVT2

R

0h

ADCCEVT2 X-BAR Flag
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1171

X-BAR Registers

8.3.3.4

www.ti.com

XBARCLR1 Register (Offset = 8h) [reset = 0h]

XBARCLR1 is shown in Figure 8-23 and described in Table 8-27.
Return to Summary Table.
This register is used to clear the flag(s) in the XBARFLG1 register.
1: Clears the corresponding bit in the XBARFLG1 register.
0: Writing 0 has no effect
Figure 8-23. XBARCLR1 Register
31
30
29
28
27
26
25
24
CMPSS8_CTRI CMPSS8_CTRI CMPSS7_CTRI CMPSS7_CTRI CMPSS6_CTRI CMPSS6_CTRI CMPSS5_CTRI CMPSS5_CTRI
POUTH
POUTL
POUTH
POUTL
POUTH
POUTL
POUTH
POUTL
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
23
22
21
20
19
18
17
16
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
POUTH
POUTL
POUTH
POUTL
POUTH
POUTL
POUTH
POUTL
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
15
14
13
12
11
10
9
8
CMPSS8_CTRI CMPSS8_CTRI CMPSS7_CTRI CMPSS7_CTRI CMPSS6_CTRI CMPSS6_CTRI CMPSS5_CTRI CMPSS5_CTRI
PH
PL
PH
PL
PH
PL
PH
PL
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
7
6
5
4
3
2
1
0
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
PH
PL
PH
PL
PH
PL
PH
PL
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h
R=0/W=1-0h

Table 8-27. XBARCLR1 Register Field Descriptions

1172

Bit

Field

Type

Reset

Description

31

CMPSS8_CTRIPOUTH

R=0/W=1

0h

CMPSS8_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

30

CMPSS8_CTRIPOUTL

R=0/W=1

0h

CMPSS8_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

29

CMPSS7_CTRIPOUTH

R=0/W=1

0h

CMPSS7_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

28

CMPSS7_CTRIPOUTL

R=0/W=1

0h

CMPSS7_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

27

CMPSS6_CTRIPOUTH

R=0/W=1

0h

CMPSS6_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

26

CMPSS6_CTRIPOUTL

R=0/W=1

0h

CMPSS6_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

25

CMPSS5_CTRIPOUTH

R=0/W=1

0h

CMPSS5_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

24

CMPSS5_CTRIPOUTL

R=0/W=1

0h

CMPSS5_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

23

CMPSS4_CTRIPOUTH

R=0/W=1

0h

CMPSS4_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

22

CMPSS4_CTRIPOUTL

R=0/W=1

0h

CMPSS4_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

21

CMPSS3_CTRIPOUTH

R=0/W=1

0h

CMPSS3_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-27. XBARCLR1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

CMPSS3_CTRIPOUTL

R=0/W=1

0h

CMPSS3_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

19

CMPSS2_CTRIPOUTH

R=0/W=1

0h

CMPSS2_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

18

CMPSS2_CTRIPOUTL

R=0/W=1

0h

CMPSS2_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

17

CMPSS1_CTRIPOUTH

R=0/W=1

0h

CMPSS1_CTRIPOUTH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

16

CMPSS1_CTRIPOUTL

R=0/W=1

0h

CMPSS1_CTRIPOUTL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

15

CMPSS8_CTRIPH

R=0/W=1

0h

CMPSS8_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

14

CMPSS8_CTRIPL

R=0/W=1

0h

CMPSS8_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

13

CMPSS7_CTRIPH

R=0/W=1

0h

CMPSS7_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

12

CMPSS7_CTRIPL

R=0/W=1

0h

CMPSS7_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

11

CMPSS6_CTRIPH

R=0/W=1

0h

CMPSS6_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

10

CMPSS6_CTRIPL

R=0/W=1

0h

CMPSS6_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

9

CMPSS5_CTRIPH

R=0/W=1

0h

CMPSS5_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

8

CMPSS5_CTRIPL

R=0/W=1

0h

CMPSS5_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

7

CMPSS4_CTRIPH

R=0/W=1

0h

CMPSS4_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

6

CMPSS4_CTRIPL

R=0/W=1

0h

CMPSS4_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

5

CMPSS3_CTRIPH

R=0/W=1

0h

CMPSS3_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

4

CMPSS3_CTRIPL

R=0/W=1

0h

CMPSS3_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

3

CMPSS2_CTRIPH

R=0/W=1

0h

CMPSS2_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

2

CMPSS2_CTRIPL

R=0/W=1

0h

CMPSS2_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

1

CMPSS1_CTRIPH

R=0/W=1

0h

CMPSS1_CTRIPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

0

CMPSS1_CTRIPL

R=0/W=1

0h

CMPSS1_CTRIPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1173

X-BAR Registers

8.3.3.5

www.ti.com

XBARCLR2 Register (Offset = Ah) [reset = 0h]

XBARCLR2 is shown in Figure 8-24 and described in Table 8-28.
Return to Summary Table.
This register is used to clear the flag(s) in the XBARFLG2 register.
1: Clears the corresponding bit in the XBARFLG2 register.
0: Writing 0 has no effect
Figure 8-24. XBARCLR2 Register
31
ADCCEVT1
R=0/W=1-0h

30
ADCBEVT4
R=0/W=1-0h

29
ADCBEVT3
R=0/W=1-0h

28
ADCBEVT2
R=0/W=1-0h

27
ADCBEVT1
R=0/W=1-0h

26
ADCAEVT4
R=0/W=1-0h

25
ADCAEVT3
R=0/W=1-0h

24
ADCAEVT2
R=0/W=1-0h

23
ADCAEVT1
R=0/W=1-0h

22
EXTSYNCOUT
R=0/W=1-0h

21
ECAP6_OUT
R=0/W=1-0h

20
ECAP5_OUT
R=0/W=1-0h

19
ECAP4_OUT
R=0/W=1-0h

18
ECAP3_OUT
R=0/W=1-0h

17
ECAP2_OUT
R=0/W=1-0h

16
ECAP1_OUT
R=0/W=1-0h

15
RESERVED
R-0h

14
RESERVED
R-0h

13
RESERVED
R-0h

12
RESERVED
R-0h

11
RESERVED
R-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
RESERVED
R-0h

7
ADCSOCBO
R=0/W=1-0h

6
ADCSOCAO
R=0/W=1-0h

5
INPUT7
R=0/W=1-0h

4
INPUT5
R=0/W=1-0h

3
INPUT4
R=0/W=1-0h

2
INPUT3
R=0/W=1-0h

1
INPUT2
R=0/W=1-0h

0
INPUT1
R=0/W=1-0h

Table 8-28. XBARCLR2 Register Field Descriptions

1174

Bit

Field

Type

Reset

Description

31

ADCCEVT1

R=0/W=1

0h

ADCCEVT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

30

ADCBEVT4

R=0/W=1

0h

ADCBEVT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

29

ADCBEVT3

R=0/W=1

0h

ADCBEVT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

28

ADCBEVT2

R=0/W=1

0h

ADCBEVT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

27

ADCBEVT1

R=0/W=1

0h

ADCBEVT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

26

ADCAEVT4

R=0/W=1

0h

ADCAEVT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

25

ADCAEVT3

R=0/W=1

0h

ADCAEVT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

24

ADCAEVT2

R=0/W=1

0h

ADCAEVT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

23

ADCAEVT1

R=0/W=1

0h

ADCAEVT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

22

EXTSYNCOUT

R=0/W=1

0h

EXTSYNCOUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn

21

ECAP6_OUT

R=0/W=1

0h

ECAP6_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn

20

ECAP5_OUT

R=0/W=1

0h

ECAP5_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn

19

ECAP4_OUT

R=0/W=1

0h

ECAP4_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-28. XBARCLR2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

18

ECAP3_OUT

R=0/W=1

0h

ECAP3_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn

17

ECAP2_OUT

R=0/W=1

0h

ECAP2_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn

16

ECAP1_OUT

R=0/W=1

0h

ECAP1_OUT X-BAR Flag Clear
Reset type: CPU1.SYSRSn

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

RESERVED

R

0h

Reserved

7

ADCSOCBO

R=0/W=1

0h

ADCSOCBO X-BAR Flag Clear
Reset type: CPU1.SYSRSn

6

ADCSOCAO

R=0/W=1

0h

ADCSOCAO X-BAR Flag Clear
Reset type: CPU1.SYSRSn

5

INPUT7

R=0/W=1

0h

INPUT7 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

4

INPUT5

R=0/W=1

0h

INPUT5 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

3

INPUT4

R=0/W=1

0h

INPUT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

2

INPUT3

R=0/W=1

0h

INPUT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

1

INPUT2

R=0/W=1

0h

INPUT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

0

INPUT1

R=0/W=1

0h

INPUT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1175

X-BAR Registers

8.3.3.6

www.ti.com

XBARCLR3 Register (Offset = Ch) [reset = 0h]

XBARCLR3 is shown in Figure 8-25 and described in Table 8-29.
Return to Summary Table.
This register is used to clear the flag(s) in the XBARFLG3 register.
1: Clears the corresponding bit in the XBARFLG3 register.
0: Writing 0 has no effect
Figure 8-25. XBARCLR3 Register
31

30

29

28

27

26

25

24

RESERVED
R=0-0h
23
RESERVED
R=0-0h

22
SD2FLT4_CO
MPH
R=0/W=1-0h

21
SD2FLT4_CO
MPL
R=0/W=1-0h

20
SD2FLT3_CO
MPH
R=0/W=1-0h

19
SD2FLT3_CO
MPL
R=0/W=1-0h

18
SD2FLT2_CO
MPH
R=0/W=1-0h

17
SD2FLT2_CO
MPL
R=0/W=1-0h

16
SD2FLT1_CO
MPH
R=0/W=1-0h

15
SD2FLT1_CO
MPL
R=0/W=1-0h

14
SD1FLT4_CO
MPH
R=0/W=1-0h

13
SD1FLT4_CO
MPL
R=0/W=1-0h

12
SD1FLT3_CO
MPH
R=0/W=1-0h

11
SD1FLT3_CO
MPL
R=0/W=1-0h

10
SD1FLT2_CO
MPH
R=0/W=1-0h

9
SD1FLT2_CO
MPL
R=0/W=1-0h

8
SD1FLT1_CO
MPH
R=0/W=1-0h

7
SD1FLT1_CO
MPL
R=0/W=1-0h

6
ADCDEVT4

5
ADCDEVT3

4
ADCDEVT2

3
ADCDEVT1

2
ADCCEVT4

1
ADCCEVT3

0
ADCCEVT2

R=0/W=1-0h

R=0/W=1-0h

R=0/W=1-0h

R=0/W=1-0h

R=0/W=1-0h

R=0/W=1-0h

R=0/W=1-0h

Table 8-29. XBARCLR3 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

22

SD2FLT4_COMPH

R=0/W=1

0h

SD2FLT4_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

21

SD2FLT4_COMPL

R=0/W=1

0h

SD2FLT4_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

20

SD2FLT3_COMPH

R=0/W=1

0h

SD2FLT3_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

19

SD2FLT3_COMPL

R=0/W=1

0h

SD2FLT3_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

18

SD2FLT2_COMPH

R=0/W=1

0h

SD2FLT2_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

17

SD2FLT2_COMPL

R=0/W=1

0h

SD2FLT2_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

16

SD2FLT1_COMPH

R=0/W=1

0h

SD2FLT1_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

15

SD2FLT1_COMPL

R=0/W=1

0h

SD2FLT1_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

14

SD1FLT4_COMPH

R=0/W=1

0h

SD1FLT4_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

13

SD1FLT4_COMPL

R=0/W=1

0h

SD1FLT4_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

12

SD1FLT3_COMPH

R=0/W=1

0h

SD1FLT3_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

31-23

1176

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-29. XBARCLR3 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

SD1FLT3_COMPL

R=0/W=1

0h

SD1FLT3_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

10

SD1FLT2_COMPH

R=0/W=1

0h

SD1FLT2_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

9

SD1FLT2_COMPL

R=0/W=1

0h

SD1FLT2_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

8

SD1FLT1_COMPH

R=0/W=1

0h

SD1FLT1_COMPH X-BAR Flag Clear
Reset type: CPU1.SYSRSn

7

SD1FLT1_COMPL

R=0/W=1

0h

SD1FLT1_COMPL X-BAR Flag Clear
Reset type: CPU1.SYSRSn

6

ADCDEVT4

R=0/W=1

0h

ADCDEVT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

5

ADCDEVT3

R=0/W=1

0h

ADCDEVT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

4

ADCDEVT2

R=0/W=1

0h

ADCDEVT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

3

ADCDEVT1

R=0/W=1

0h

ADCDEVT1 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

2

ADCCEVT4

R=0/W=1

0h

ADCCEVT4 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

1

ADCCEVT3

R=0/W=1

0h

ADCCEVT3 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

0

ADCCEVT2

R=0/W=1

0h

ADCCEVT2 X-BAR Flag Clear
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1177

X-BAR Registers

www.ti.com

8.3.4 EPWM_XBAR_REGS Registers
Table 14-100 lists the memory-mapped registers for the EPWM_XBAR_REGS. All register offset
addresses not listed in Table 14-100 should be considered as reserved locations and the register contents
should not be modified.
Table 8-30. EPWM_XBAR_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

TRIP4MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP4

EALLOW

Go

2h

TRIP4MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP4

EALLOW

Go

4h

TRIP5MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP5

EALLOW

Go

6h

TRIP5MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP5

EALLOW

Go

8h

TRIP7MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP7

EALLOW

Go

Ah

TRIP7MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP7

EALLOW

Go

Ch

TRIP8MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP8

EALLOW

Go

Eh

TRIP8MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP8

EALLOW

Go

10h

TRIP9MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP9

EALLOW

Go

12h

TRIP9MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP9

EALLOW

Go

14h

TRIP10MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP10

EALLOW

Go

16h

TRIP10MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP10

EALLOW

Go

18h

TRIP11MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP11

EALLOW

Go

1Ah

TRIP11MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP11

EALLOW

Go

1Ch

TRIP12MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP12

EALLOW

Go

1Eh

TRIP12MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP12

EALLOW

Go

20h

TRIP4MUXENABLE

ePWM XBAR Mux Enable for TRIP4

EALLOW

Go

22h

TRIP5MUXENABLE

ePWM XBAR Mux Enable for TRIP5

EALLOW

Go

24h

TRIP7MUXENABLE

ePWM XBAR Mux Enable for TRIP7

EALLOW

Go

26h

TRIP8MUXENABLE

ePWM XBAR Mux Enable for TRIP8

EALLOW

Go

28h

TRIP9MUXENABLE

ePWM XBAR Mux Enable for TRIP9

EALLOW

Go

2Ah

TRIP10MUXENABLE

ePWM XBAR Mux Enable for TRIP10

EALLOW

Go

2Ch

TRIP11MUXENABLE

ePWM XBAR Mux Enable for TRIP11

EALLOW

Go

2Eh

TRIP12MUXENABLE

ePWM XBAR Mux Enable for TRIP12

EALLOW

Go

38h

TRIPOUTINV

ePWM XBAR Output Inversion Register

EALLOW

Go

3Eh

TRIPLOCK

ePWM XBAR Configuration Lock register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 14-101 shows the codes that are
used for access types in this section.
Table 8-31. EPWM_XBAR_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
1178

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-31. EPWM_XBAR_REGS Access Type
Codes (continued)
Access Type

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1179

X-BAR Registers

8.3.4.1

www.ti.com

TRIP4MUX0TO15CFG Register (Offset = 0h) [reset = 0h]

TRIP4MUX0TO15CFG is shown in Figure 14-161 and described in Table 14-102.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP4
Figure 8-26. TRIP4MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-32. TRIP4MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1180

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-32. TRIP4MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1181

X-BAR Registers

www.ti.com

Table 8-32. TRIP4MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1182

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.2

TRIP4MUX16TO31CFG Register (Offset = 2h) [reset = 0h]

TRIP4MUX16TO31CFG is shown in Figure 14-162 and described in Table 14-103.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP4
Figure 8-27. TRIP4MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-33. TRIP4MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1183

X-BAR Registers

www.ti.com

Table 8-33. TRIP4MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1184

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-33. TRIP4MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1185

X-BAR Registers

8.3.4.3

www.ti.com

TRIP5MUX0TO15CFG Register (Offset = 4h) [reset = 0h]

TRIP5MUX0TO15CFG is shown in Figure 14-163 and described in Table 14-104.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP5
Figure 8-28. TRIP5MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-34. TRIP5MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1186

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-34. TRIP5MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1187

X-BAR Registers

www.ti.com

Table 8-34. TRIP5MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1188

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.4

TRIP5MUX16TO31CFG Register (Offset = 6h) [reset = 0h]

TRIP5MUX16TO31CFG is shown in Figure 14-164 and described in Table 14-105.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP5
Figure 8-29. TRIP5MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-35. TRIP5MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1189

X-BAR Registers

www.ti.com

Table 8-35. TRIP5MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1190

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-35. TRIP5MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1191

X-BAR Registers

8.3.4.5

www.ti.com

TRIP7MUX0TO15CFG Register (Offset = 8h) [reset = 0h]

TRIP7MUX0TO15CFG is shown in Figure 14-165 and described in Table 14-106.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP7
Figure 8-30. TRIP7MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-36. TRIP7MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1192

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-36. TRIP7MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1193

X-BAR Registers

www.ti.com

Table 8-36. TRIP7MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1194

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.6

TRIP7MUX16TO31CFG Register (Offset = Ah) [reset = 0h]

TRIP7MUX16TO31CFG is shown in Figure 14-166 and described in Table 14-107.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP7
Figure 8-31. TRIP7MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-37. TRIP7MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1195

X-BAR Registers

www.ti.com

Table 8-37. TRIP7MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1196

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-37. TRIP7MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1197

X-BAR Registers

8.3.4.7

www.ti.com

TRIP8MUX0TO15CFG Register (Offset = Ch) [reset = 0h]

TRIP8MUX0TO15CFG is shown in Figure 14-167 and described in Table 14-108.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP8
Figure 8-32. TRIP8MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-38. TRIP8MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1198

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-38. TRIP8MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1199

X-BAR Registers

www.ti.com

Table 8-38. TRIP8MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1200

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.8

TRIP8MUX16TO31CFG Register (Offset = Eh) [reset = 0h]

TRIP8MUX16TO31CFG is shown in Figure 14-168 and described in Table 14-109.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP8
Figure 8-33. TRIP8MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-39. TRIP8MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1201

X-BAR Registers

www.ti.com

Table 8-39. TRIP8MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1202

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-39. TRIP8MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1203

X-BAR Registers

8.3.4.9

www.ti.com

TRIP9MUX0TO15CFG Register (Offset = 10h) [reset = 0h]

TRIP9MUX0TO15CFG is shown in Figure 14-169 and described in Table 14-110.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP9
Figure 8-34. TRIP9MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-40. TRIP9MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1204

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-40. TRIP9MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1205

X-BAR Registers

www.ti.com

Table 8-40. TRIP9MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1206

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.10 TRIP9MUX16TO31CFG Register (Offset = 12h) [reset = 0h]
TRIP9MUX16TO31CFG is shown in Figure 14-170 and described in Table 14-111.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP9
Figure 8-35. TRIP9MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-41. TRIP9MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1207

X-BAR Registers

www.ti.com

Table 8-41. TRIP9MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1208

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-41. TRIP9MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1209

X-BAR Registers

www.ti.com

8.3.4.11 TRIP10MUX0TO15CFG Register (Offset = 14h) [reset = 0h]
TRIP10MUX0TO15CFG is shown in Figure 14-171 and described in Table 14-112.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP10
Figure 8-36. TRIP10MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-42. TRIP10MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1210

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-42. TRIP10MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1211

X-BAR Registers

www.ti.com

Table 8-42. TRIP10MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1212

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.12 TRIP10MUX16TO31CFG Register (Offset = 16h) [reset = 0h]
TRIP10MUX16TO31CFG is shown in Figure 14-172 and described in Table 14-113.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP10
Figure 8-37. TRIP10MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-43. TRIP10MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1213

X-BAR Registers

www.ti.com

Table 8-43. TRIP10MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1214

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-43. TRIP10MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1215

X-BAR Registers

www.ti.com

8.3.4.13 TRIP11MUX0TO15CFG Register (Offset = 18h) [reset = 0h]
TRIP11MUX0TO15CFG is shown in Figure 14-173 and described in Table 14-114.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP11
Figure 8-38. TRIP11MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-44. TRIP11MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1216

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-44. TRIP11MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1217

X-BAR Registers

www.ti.com

Table 8-44. TRIP11MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1218

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.14 TRIP11MUX16TO31CFG Register (Offset = 1Ah) [reset = 0h]
TRIP11MUX16TO31CFG is shown in Figure 14-174 and described in Table 14-115.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP11
Figure 8-39. TRIP11MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-45. TRIP11MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1219

X-BAR Registers

www.ti.com

Table 8-45. TRIP11MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1220

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-45. TRIP11MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1221

X-BAR Registers

www.ti.com

8.3.4.15 TRIP12MUX0TO15CFG Register (Offset = 1Ch) [reset = 0h]
TRIP12MUX0TO15CFG is shown in Figure 14-175 and described in Table 14-116.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP12
Figure 8-40. TRIP12MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-46. TRIP12MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1222

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-46. TRIP12MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1223

X-BAR Registers

www.ti.com

Table 8-46. TRIP12MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1224

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.16 TRIP12MUX16TO31CFG Register (Offset = 1Eh) [reset = 0h]
TRIP12MUX16TO31CFG is shown in Figure 14-176 and described in Table 14-117.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP12
Figure 8-41. TRIP12MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-47. TRIP12MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1225

X-BAR Registers

www.ti.com

Table 8-47. TRIP12MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1226

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-47. TRIP12MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1227

X-BAR Registers

www.ti.com

8.3.4.17 TRIP4MUXENABLE Register (Offset = 20h) [reset = 0h]
TRIP4MUXENABLE is shown in Figure 14-177 and described in Table 14-118.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP4
Figure 8-42. TRIP4MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-48. TRIP4MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1228

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-48. TRIP4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1229

X-BAR Registers

www.ti.com

Table 8-48. TRIP4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1230

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-48. TRIP4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1231

X-BAR Registers

www.ti.com

Table 8-48. TRIP4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of Mux0 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1232

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.18 TRIP5MUXENABLE Register (Offset = 22h) [reset = 0h]
TRIP5MUXENABLE is shown in Figure 14-178 and described in Table 14-119.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP5
Figure 8-43. TRIP5MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-49. TRIP5MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1233

X-BAR Registers

www.ti.com

Table 8-49. TRIP5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1234

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-49. TRIP5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1235

X-BAR Registers

www.ti.com

Table 8-49. TRIP5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1236

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-49. TRIP5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1237

X-BAR Registers

www.ti.com

8.3.4.19 TRIP7MUXENABLE Register (Offset = 24h) [reset = 0h]
TRIP7MUXENABLE is shown in Figure 14-179 and described in Table 14-120.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP7
Figure 8-44. TRIP7MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-50. TRIP7MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1238

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-50. TRIP7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1239

X-BAR Registers

www.ti.com

Table 8-50. TRIP7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1240

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-50. TRIP7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1241

X-BAR Registers

www.ti.com

Table 8-50. TRIP7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1242

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.20 TRIP8MUXENABLE Register (Offset = 26h) [reset = 0h]
TRIP8MUXENABLE is shown in Figure 14-180 and described in Table 14-121.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP8
Figure 8-45. TRIP8MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-51. TRIP8MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1243

X-BAR Registers

www.ti.com

Table 8-51. TRIP8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1244

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-51. TRIP8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1245

X-BAR Registers

www.ti.com

Table 8-51. TRIP8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1246

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-51. TRIP8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1247

X-BAR Registers

www.ti.com

8.3.4.21 TRIP9MUXENABLE Register (Offset = 28h) [reset = 0h]
TRIP9MUXENABLE is shown in Figure 14-181 and described in Table 14-122.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP9
Figure 8-46. TRIP9MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-52. TRIP9MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1248

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-52. TRIP9MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1249

X-BAR Registers

www.ti.com

Table 8-52. TRIP9MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1250

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-52. TRIP9MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1251

X-BAR Registers

www.ti.com

Table 8-52. TRIP9MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1252

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.22 TRIP10MUXENABLE Register (Offset = 2Ah) [reset = 0h]
TRIP10MUXENABLE is shown in Figure 14-182 and described in Table 14-123.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP10
Figure 8-47. TRIP10MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-53. TRIP10MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1253

X-BAR Registers

www.ti.com

Table 8-53. TRIP10MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1254

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-53. TRIP10MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1255

X-BAR Registers

www.ti.com

Table 8-53. TRIP10MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1256

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-53. TRIP10MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1257

X-BAR Registers

www.ti.com

8.3.4.23 TRIP11MUXENABLE Register (Offset = 2Ch) [reset = 0h]
TRIP11MUXENABLE is shown in Figure 14-183 and described in Table 14-124.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP11
Figure 8-48. TRIP11MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-54. TRIP11MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1258

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-54. TRIP11MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1259

X-BAR Registers

www.ti.com

Table 8-54. TRIP11MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1260

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-54. TRIP11MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1261

X-BAR Registers

www.ti.com

Table 8-54. TRIP11MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1262

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.4.24 TRIP12MUXENABLE Register (Offset = 2Eh) [reset = 0h]
TRIP12MUXENABLE is shown in Figure 14-184 and described in Table 14-125.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP12
Figure 8-49. TRIP12MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-55. TRIP12MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1263

X-BAR Registers

www.ti.com

Table 8-55. TRIP12MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1264

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-55. TRIP12MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1265

X-BAR Registers

www.ti.com

Table 8-55. TRIP12MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1266

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-55. TRIP12MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1267

X-BAR Registers

www.ti.com

8.3.4.25 TRIPOUTINV Register (Offset = 38h) [reset = 0h]
TRIPOUTINV is shown in Figure 14-185 and described in Table 14-126.
Return to Summary Table.
ePWM XBAR Output Inversion Register
Figure 8-50. TRIPOUTINV Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
TRIP8
R/W-0h

2
TRIP7
R/W-0h

1
TRIP5
R/W-0h

0
TRIP4
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
TRIP12
R/W-0h

6
TRIP11
R/W-0h

5
TRIP10
R/W-0h

4
TRIP9
R/W-0h

Table 8-56. TRIPOUTINV Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

TRIP12

R/W

0h

Selects polarity for TRIP12 of EPWM-XBAR

7

0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
6

TRIP11

R/W

0h

Selects polarity for TRIP11 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

TRIP10

R/W

0h

Selects polarity for TRIP10 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

TRIP9

R/W

0h

Selects polarity for TRIP9 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1268

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-56. TRIPOUTINV Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

TRIP8

R/W

0h

Selects polarity for TRIP8 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

TRIP7

R/W

0h

Selects polarity for TRIP7 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

TRIP5

R/W

0h

Selects polarity for TRIP5 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

TRIP4

R/W

0h

Selects polarity for TRIP4 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1269

X-BAR Registers

www.ti.com

8.3.4.26 TRIPLOCK Register (Offset = 3Eh) [reset = 0h]
TRIPLOCK is shown in Figure 14-186 and described in Table 14-127.
Return to Summary Table.
ePWM XBAR Configuration Lock register
Figure 8-51. TRIPLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
LOCK
R/WSOnce-0h

KEY
R=0/W=1-0h
23

22

21

20
KEY
R=0/W=1-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 8-57. TRIPLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

KEY

R=0/W=1

0h

Bit-0 of this register can be set only if KEY= 0x5a5a
Reset type: CPU1.SYSRSn

15-1

RESERVED

R=0

0h

Reserved

LOCK

R/WSOnce

0h

Locks the configuration for EPWM-XBAR. Once the configuration is
locked, writes to the below registers for EPWM-XBAR is blocked.

0

Registers Affected by the LOCK mechanism:
EPWM-XBAROUTyMUX0TO15CFG
EPWM-XBAROUTyMUX16TO31CFG
EPWM-XBAROUTyMUXENABLE
EPWM-XBAROUTLATEN
EPWM-XBAROUTINV
0: Writes to the above registers are allowed
1: Writes to the above registers are blocked
Note:
[1] LOCK mechanism only apples to writes. Reads are never
blocked.
Reset type: CPU1.SYSRSn

1270

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5 OUTPUT_XBAR_REGS Registers
Table 8-58 lists the memory-mapped registers for the OUTPUT_XBAR_REGS. All register offset
addresses not listed in Table 8-58 should be considered as reserved locations and the register contents
should not be modified.
Table 8-58. OUTPUT_XBAR_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

OUTPUT1MUX0TO15CFG

Output X-BAR Mux Configuration for Output 1

EALLOW

Go

2h

OUTPUT1MUX16TO31CFG

Output X-BAR Mux Configuration for Output 1

EALLOW

Go

4h

OUTPUT2MUX0TO15CFG

Output X-BAR Mux Configuration for Output 2

EALLOW

Go

6h

OUTPUT2MUX16TO31CFG

Output X-BAR Mux Configuration for Output 2

EALLOW

Go

8h

OUTPUT3MUX0TO15CFG

Output X-BAR Mux Configuration for Output 3

EALLOW

Go

Ah

OUTPUT3MUX16TO31CFG

Output X-BAR Mux Configuration for Output 3

EALLOW

Go

Ch

OUTPUT4MUX0TO15CFG

Output X-BAR Mux Configuration for Output 4

EALLOW

Go

Eh

OUTPUT4MUX16TO31CFG

Output X-BAR Mux Configuration for Output 4

EALLOW

Go

10h

OUTPUT5MUX0TO15CFG

Output X-BAR Mux Configuration for Output 5

EALLOW

Go

12h

OUTPUT5MUX16TO31CFG

Output X-BAR Mux Configuration for Output 5

EALLOW

Go

14h

OUTPUT6MUX0TO15CFG

Output X-BAR Mux Configuration for Output 6

EALLOW

Go

16h

OUTPUT6MUX16TO31CFG

Output X-BAR Mux Configuration for Output 6

EALLOW

Go

18h

OUTPUT7MUX0TO15CFG

Output X-BAR Mux Configuration for Output 7

EALLOW

Go

1Ah

OUTPUT7MUX16TO31CFG

Output X-BAR Mux Configuration for Output 7

EALLOW

Go

1Ch

OUTPUT8MUX0TO15CFG

Output X-BAR Mux Configuration for Output 8

EALLOW

Go

1Eh

OUTPUT8MUX16TO31CFG

Output X-BAR Mux Configuration for Output 8

EALLOW

Go

20h

OUTPUT1MUXENABLE

Output X-BAR Mux Enable for Output 1

EALLOW

Go

22h

OUTPUT2MUXENABLE

Output X-BAR Mux Enable for Output 2

EALLOW

Go

24h

OUTPUT3MUXENABLE

Output X-BAR Mux Enable for Output 3

EALLOW

Go

26h

OUTPUT4MUXENABLE

Output X-BAR Mux Enable for Output 4

EALLOW

Go

28h

OUTPUT5MUXENABLE

Output X-BAR Mux Enable for Output 5

EALLOW

Go

2Ah

OUTPUT6MUXENABLE

Output X-BAR Mux Enable for Output 6

EALLOW

Go

2Ch

OUTPUT7MUXENABLE

Output X-BAR Mux Enable for Output 7

EALLOW

Go

2Eh

OUTPUT8MUXENABLE

Output X-BAR Mux Enable for Output 8

EALLOW

Go

30h

OUTPUTLATCH

Output X-BAR Output Latch

Go

32h

OUTPUTLATCHCLR

Output X-BAR Output Latch Clear

Go

34h

OUTPUTLATCHFRC

Output X-BAR Output Latch Clear

Go

36h

OUTPUTLATCHENABLE

Output X-BAR Output Latch Enable

EALLOW

Go

38h

OUTPUTINV

Output X-BAR Output Inversion

EALLOW

Go

3Eh

OUTPUTLOCK

Output X-BAR Configuration Lock register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 8-59 shows the codes that are
used for access types in this section.
Table 8-59. OUTPUT_XBAR_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1271

X-BAR Registers

www.ti.com

Table 8-59. OUTPUT_XBAR_REGS Access Type
Codes (continued)
Access Type

Code

Description

WSOnce

SOnce
W

Set once
Write

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

1272

Crossbar (X-BAR)

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.1

OUTPUT1MUX0TO15CFG Register (Offset = 0h) [reset = 0h]

OUTPUT1MUX0TO15CFG is shown in Figure 8-52 and described in Table 8-60.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 1
Figure 8-52. OUTPUT1MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
2

MUX1
R/W-0h

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-60. OUTPUT1MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for OUTPUT1 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for OUTPUT1 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for OUTPUT1 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for OUTPUT1 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1273

X-BAR Registers

www.ti.com

Table 8-60. OUTPUT1MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for OUTPUT1 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for OUTPUT1 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for OUTPUT1 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for OUTPUT1 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for OUTPUT1 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for OUTPUT1 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1274

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-60. OUTPUT1MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for OUTPUT1 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for OUTPUT1 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for OUTPUT1 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for OUTPUT1 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for OUTPUT1 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for OUTPUT1 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1275

X-BAR Registers

8.3.5.2

www.ti.com

OUTPUT1MUX16TO31CFG Register (Offset = 2h) [reset = 0h]

OUTPUT1MUX16TO31CFG is shown in Figure 8-53 and described in Table 8-61.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 1
Figure 8-53. OUTPUT1MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-61. OUTPUT1MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for OUTPUT1 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for OUTPUT1 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for OUTPUT1 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for OUTPUT1 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1276

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-61. OUTPUT1MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for OUTPUT1 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for OUTPUT1 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for OUTPUT1 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for OUTPUT1 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for OUTPUT1 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for OUTPUT1 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1277

X-BAR Registers

www.ti.com

Table 8-61. OUTPUT1MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for OUTPUT1 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for OUTPUT1 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for OUTPUT1 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for OUTPUT1 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for OUTPUT1 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for OUTPUT1 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1278

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.3

OUTPUT2MUX0TO15CFG Register (Offset = 4h) [reset = 0h]

OUTPUT2MUX0TO15CFG is shown in Figure 8-54 and described in Table 8-62.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 2
Figure 8-54. OUTPUT2MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
2

MUX1
R/W-0h

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-62. OUTPUT2MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for OUTPUT2 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for OUTPUT2 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for OUTPUT2 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for OUTPUT2 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1279

X-BAR Registers

www.ti.com

Table 8-62. OUTPUT2MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for OUTPUT2 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for OUTPUT2 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for OUTPUT2 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for OUTPUT2 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for OUTPUT2 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for OUTPUT2 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1280

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-62. OUTPUT2MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for OUTPUT2 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for OUTPUT2 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for OUTPUT2 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for OUTPUT2 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for OUTPUT2 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for OUTPUT2 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1281

X-BAR Registers

8.3.5.4

www.ti.com

OUTPUT2MUX16TO31CFG Register (Offset = 6h) [reset = 0h]

OUTPUT2MUX16TO31CFG is shown in Figure 8-55 and described in Table 8-63.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 2
Figure 8-55. OUTPUT2MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-63. OUTPUT2MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for OUTPUT2 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for OUTPUT2 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for OUTPUT2 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for OUTPUT2 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1282

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-63. OUTPUT2MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for OUTPUT2 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for OUTPUT2 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for OUTPUT2 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for OUTPUT2 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for OUTPUT2 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for OUTPUT2 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1283

X-BAR Registers

www.ti.com

Table 8-63. OUTPUT2MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for OUTPUT2 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for OUTPUT2 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for OUTPUT2 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for OUTPUT2 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for OUTPUT2 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for OUTPUT2 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1284

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.5

OUTPUT3MUX0TO15CFG Register (Offset = 8h) [reset = 0h]

OUTPUT3MUX0TO15CFG is shown in Figure 8-56 and described in Table 8-64.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 3
Figure 8-56. OUTPUT3MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
2

MUX1
R/W-0h

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-64. OUTPUT3MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for OUTPUT3 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for OUTPUT3 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for OUTPUT3 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for OUTPUT3 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1285

X-BAR Registers

www.ti.com

Table 8-64. OUTPUT3MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for OUTPUT3 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for OUTPUT3 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for OUTPUT3 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for OUTPUT3 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for OUTPUT3 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for OUTPUT3 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1286

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-64. OUTPUT3MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for OUTPUT3 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for OUTPUT3 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for OUTPUT3 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for OUTPUT3 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for OUTPUT3 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for OUTPUT3 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1287

X-BAR Registers

8.3.5.6

www.ti.com

OUTPUT3MUX16TO31CFG Register (Offset = Ah) [reset = 0h]

OUTPUT3MUX16TO31CFG is shown in Figure 8-57 and described in Table 8-65.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 3
Figure 8-57. OUTPUT3MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-65. OUTPUT3MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for OUTPUT3 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for OUTPUT3 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for OUTPUT3 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for OUTPUT3 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1288

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-65. OUTPUT3MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for OUTPUT3 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for OUTPUT3 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for OUTPUT3 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for OUTPUT3 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for OUTPUT3 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for OUTPUT3 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1289

X-BAR Registers

www.ti.com

Table 8-65. OUTPUT3MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for OUTPUT3 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for OUTPUT3 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for OUTPUT3 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for OUTPUT3 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for OUTPUT3 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for OUTPUT3 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1290

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.7

OUTPUT4MUX0TO15CFG Register (Offset = Ch) [reset = 0h]

OUTPUT4MUX0TO15CFG is shown in Figure 8-58 and described in Table 8-66.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 4
Figure 8-58. OUTPUT4MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
2

MUX1
R/W-0h

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-66. OUTPUT4MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for OUTPUT4 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for OUTPUT4 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for OUTPUT4 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for OUTPUT4 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1291

X-BAR Registers

www.ti.com

Table 8-66. OUTPUT4MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for OUTPUT4 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for OUTPUT4 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for OUTPUT4 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for OUTPUT4 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for OUTPUT4 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for OUTPUT4 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1292

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-66. OUTPUT4MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for OUTPUT4 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for OUTPUT4 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for OUTPUT4 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for OUTPUT4 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for OUTPUT4 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for OUTPUT4 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1293

X-BAR Registers

8.3.5.8

www.ti.com

OUTPUT4MUX16TO31CFG Register (Offset = Eh) [reset = 0h]

OUTPUT4MUX16TO31CFG is shown in Figure 8-59 and described in Table 8-67.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 4
Figure 8-59. OUTPUT4MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-67. OUTPUT4MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for OUTPUT4 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for OUTPUT4 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for OUTPUT4 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for OUTPUT4 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1294

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-67. OUTPUT4MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for OUTPUT4 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for OUTPUT4 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for OUTPUT4 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for OUTPUT4 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for OUTPUT4 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for OUTPUT4 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1295

X-BAR Registers

www.ti.com

Table 8-67. OUTPUT4MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for OUTPUT4 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for OUTPUT4 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for OUTPUT4 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for OUTPUT4 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for OUTPUT4 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for OUTPUT4 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1296

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.9

OUTPUT5MUX0TO15CFG Register (Offset = 10h) [reset = 0h]

OUTPUT5MUX0TO15CFG is shown in Figure 8-60 and described in Table 8-68.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 5
Figure 8-60. OUTPUT5MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
2

MUX1
R/W-0h

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-68. OUTPUT5MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for OUTPUT5 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for OUTPUT5 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for OUTPUT5 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for OUTPUT5 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1297

X-BAR Registers

www.ti.com

Table 8-68. OUTPUT5MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for OUTPUT5 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for OUTPUT5 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for OUTPUT5 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for OUTPUT5 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for OUTPUT5 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for OUTPUT5 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1298

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-68. OUTPUT5MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for OUTPUT5 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for OUTPUT5 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for OUTPUT5 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for OUTPUT5 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for OUTPUT5 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for OUTPUT5 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1299

X-BAR Registers

www.ti.com

8.3.5.10 OUTPUT5MUX16TO31CFG Register (Offset = 12h) [reset = 0h]
OUTPUT5MUX16TO31CFG is shown in Figure 8-61 and described in Table 8-69.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 5
Figure 8-61. OUTPUT5MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-69. OUTPUT5MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for OUTPUT5 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for OUTPUT5 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for OUTPUT5 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for OUTPUT5 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1300

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-69. OUTPUT5MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for OUTPUT5 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for OUTPUT5 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for OUTPUT5 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for OUTPUT5 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for OUTPUT5 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for OUTPUT5 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1301

X-BAR Registers

www.ti.com

Table 8-69. OUTPUT5MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for OUTPUT5 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for OUTPUT5 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for OUTPUT5 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for OUTPUT5 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for OUTPUT5 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for OUTPUT5 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1302

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.11 OUTPUT6MUX0TO15CFG Register (Offset = 14h) [reset = 0h]
OUTPUT6MUX0TO15CFG is shown in Figure 8-62 and described in Table 8-70.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 6
Figure 8-62. OUTPUT6MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
2

MUX1
R/W-0h

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-70. OUTPUT6MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for OUTPUT6 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for OUTPUT6 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for OUTPUT6 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for OUTPUT6 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1303

X-BAR Registers

www.ti.com

Table 8-70. OUTPUT6MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for OUTPUT6 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for OUTPUT6 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for OUTPUT6 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for OUTPUT6 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for OUTPUT6 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for OUTPUT6 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1304

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-70. OUTPUT6MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for OUTPUT6 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for OUTPUT6 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for OUTPUT6 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for OUTPUT6 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for OUTPUT6 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for OUTPUT6 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1305

X-BAR Registers

www.ti.com

8.3.5.12 OUTPUT6MUX16TO31CFG Register (Offset = 16h) [reset = 0h]
OUTPUT6MUX16TO31CFG is shown in Figure 8-63 and described in Table 8-71.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 6
Figure 8-63. OUTPUT6MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-71. OUTPUT6MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for OUTPUT6 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for OUTPUT6 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for OUTPUT6 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for OUTPUT6 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1306

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-71. OUTPUT6MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for OUTPUT6 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for OUTPUT6 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for OUTPUT6 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for OUTPUT6 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for OUTPUT6 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for OUTPUT6 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1307

X-BAR Registers

www.ti.com

Table 8-71. OUTPUT6MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for OUTPUT6 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for OUTPUT6 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for OUTPUT6 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for OUTPUT6 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for OUTPUT6 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for OUTPUT6 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1308

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.13 OUTPUT7MUX0TO15CFG Register (Offset = 18h) [reset = 0h]
OUTPUT7MUX0TO15CFG is shown in Figure 8-64 and described in Table 8-72.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 7
Figure 8-64. OUTPUT7MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
2

MUX1
R/W-0h

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-72. OUTPUT7MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for OUTPUT7 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for OUTPUT7 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for OUTPUT7 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for OUTPUT7 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1309

X-BAR Registers

www.ti.com

Table 8-72. OUTPUT7MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for OUTPUT7 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for OUTPUT7 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for OUTPUT7 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for OUTPUT7 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for OUTPUT7 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for OUTPUT7 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1310

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-72. OUTPUT7MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for OUTPUT7 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for OUTPUT7 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for OUTPUT7 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for OUTPUT7 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for OUTPUT7 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for OUTPUT7 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1311

X-BAR Registers

www.ti.com

8.3.5.14 OUTPUT7MUX16TO31CFG Register (Offset = 1Ah) [reset = 0h]
OUTPUT7MUX16TO31CFG is shown in Figure 8-65 and described in Table 8-73.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 7
Figure 8-65. OUTPUT7MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-73. OUTPUT7MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for OUTPUT7 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for OUTPUT7 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for OUTPUT7 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for OUTPUT7 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1312

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-73. OUTPUT7MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for OUTPUT7 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for OUTPUT7 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for OUTPUT7 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for OUTPUT7 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for OUTPUT7 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for OUTPUT7 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1313

X-BAR Registers

www.ti.com

Table 8-73. OUTPUT7MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for OUTPUT7 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for OUTPUT7 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for OUTPUT7 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for OUTPUT7 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for OUTPUT7 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for OUTPUT7 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1314

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.15 OUTPUT8MUX0TO15CFG Register (Offset = 1Ch) [reset = 0h]
OUTPUT8MUX0TO15CFG is shown in Figure 8-66 and described in Table 8-74.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 8
Figure 8-66. OUTPUT8MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
2

MUX1
R/W-0h

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 8-74. OUTPUT8MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for OUTPUT8 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for OUTPUT8 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for OUTPUT8 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for OUTPUT8 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1315

X-BAR Registers

www.ti.com

Table 8-74. OUTPUT8MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for OUTPUT8 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for OUTPUT8 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for OUTPUT8 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for OUTPUT8 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for OUTPUT8 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for OUTPUT8 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1316

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-74. OUTPUT8MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for OUTPUT8 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for OUTPUT8 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for OUTPUT8 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for OUTPUT8 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for OUTPUT8 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for OUTPUT8 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1317

X-BAR Registers

www.ti.com

8.3.5.16 OUTPUT8MUX16TO31CFG Register (Offset = 1Eh) [reset = 0h]
OUTPUT8MUX16TO31CFG is shown in Figure 8-67 and described in Table 8-75.
Return to Summary Table.
Output X-BAR Mux Configuration for Output 8
Figure 8-67. OUTPUT8MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

2

MUX17
R/W-0h

0

MUX16
R/W-0h

Table 8-75. OUTPUT8MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for OUTPUT8 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for OUTPUT8 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for OUTPUT8 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for OUTPUT8 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1318

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-75. OUTPUT8MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for OUTPUT8 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for OUTPUT8 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for OUTPUT8 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for OUTPUT8 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for OUTPUT8 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for OUTPUT8 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1319

X-BAR Registers

www.ti.com

Table 8-75. OUTPUT8MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for OUTPUT8 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for OUTPUT8 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for OUTPUT8 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for OUTPUT8 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for OUTPUT8 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for OUTPUT8 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1320

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.17 OUTPUT1MUXENABLE Register (Offset = 20h) [reset = 0h]
OUTPUT1MUXENABLE is shown in Figure 8-68 and described in Table 8-76.
Return to Summary Table.
Output X-BAR Mux Enable for Output 1
Figure 8-68. OUTPUT1MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-76. OUTPUT1MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux31 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux31 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux30 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux30 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux29 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux29 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux28 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux28 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1321

X-BAR Registers

www.ti.com

Table 8-76. OUTPUT1MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux27 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux27 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux26 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux26 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux25 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux25 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux24 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux24 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux23 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux23 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux22 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux22 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux21 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux21 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1322

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-76. OUTPUT1MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux20 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux20 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux19 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux19 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux18 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux18 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux17 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux17 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux16 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux16 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux15 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux15 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux14 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux14 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1323

X-BAR Registers

www.ti.com

Table 8-76. OUTPUT1MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux13 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux13 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux12 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux12 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux11 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux11 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux10 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux10 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux9 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux9 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux8 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux8 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux7 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux7 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1324

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-76. OUTPUT1MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux6 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux6 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux5 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux5 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux4 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux4 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux3 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux3 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux2 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux2 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux1 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux1 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive OUTPUT1 of OUTPUT-XBAR
0: Respective output of Mux0 is disabled to drive the OUTPUT1 of
OUTPUT-XBAR
1: Respective output of Mux0 is enabled to drive the OUTPUT1 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1325

X-BAR Registers

www.ti.com

8.3.5.18 OUTPUT2MUXENABLE Register (Offset = 22h) [reset = 0h]
OUTPUT2MUXENABLE is shown in Figure 8-69 and described in Table 8-77.
Return to Summary Table.
Output X-BAR Mux Enable for Output 2
Figure 8-69. OUTPUT2MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-77. OUTPUT2MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux31 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux31 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux30 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux30 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux29 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux29 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux28 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux28 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1326

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-77. OUTPUT2MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux27 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux27 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux26 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux26 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux25 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux25 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux24 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux24 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux23 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux23 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux22 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux22 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux21 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux21 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1327

X-BAR Registers

www.ti.com

Table 8-77. OUTPUT2MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux20 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux20 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux19 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux19 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux18 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux18 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux17 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux17 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux16 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux16 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux15 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux15 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux14 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux14 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1328

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-77. OUTPUT2MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux13 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux13 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux12 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux12 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux11 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux11 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux10 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux10 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux9 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux9 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux8 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux8 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux7 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux7 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1329

X-BAR Registers

www.ti.com

Table 8-77. OUTPUT2MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux6 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux6 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux5 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux5 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux4 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux4 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux3 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux3 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux2 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux2 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux1 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux1 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive OUTPUT2 of OUTPUT-XBAR
0: Respective output of Mux0 is disabled to drive the OUTPUT2 of
OUTPUT-XBAR
1: Respective output of Mux0 is enabled to drive the OUTPUT2 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1330

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.19 OUTPUT3MUXENABLE Register (Offset = 24h) [reset = 0h]
OUTPUT3MUXENABLE is shown in Figure 8-70 and described in Table 8-78.
Return to Summary Table.
Output X-BAR Mux Enable for Output 3
Figure 8-70. OUTPUT3MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-78. OUTPUT3MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux31 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux31 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux30 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux30 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux29 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux29 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux28 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux28 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1331

X-BAR Registers

www.ti.com

Table 8-78. OUTPUT3MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux27 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux27 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux26 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux26 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux25 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux25 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux24 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux24 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux23 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux23 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux22 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux22 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux21 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux21 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1332

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-78. OUTPUT3MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux20 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux20 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux19 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux19 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux18 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux18 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux17 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux17 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux16 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux16 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux15 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux15 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux14 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux14 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1333

X-BAR Registers

www.ti.com

Table 8-78. OUTPUT3MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux13 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux13 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux12 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux12 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux11 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux11 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux10 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux10 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux9 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux9 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux8 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux8 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux7 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux7 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1334

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-78. OUTPUT3MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux6 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux6 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux5 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux5 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux4 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux4 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux3 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux3 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux2 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux2 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux1 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux1 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive OUTPUT3 of OUTPUT-XBAR
0: Respective output of Mux0 is disabled to drive the OUTPUT3 of
OUTPUT-XBAR
1: Respective output of Mux0 is enabled to drive the OUTPUT3 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1335

X-BAR Registers

www.ti.com

8.3.5.20 OUTPUT4MUXENABLE Register (Offset = 26h) [reset = 0h]
OUTPUT4MUXENABLE is shown in Figure 8-71 and described in Table 8-79.
Return to Summary Table.
Output X-BAR Mux Enable for Output 4
Figure 8-71. OUTPUT4MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-79. OUTPUT4MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux31 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux31 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux30 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux30 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux29 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux29 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux28 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux28 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1336

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-79. OUTPUT4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux27 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux27 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux26 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux26 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux25 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux25 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux24 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux24 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux23 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux23 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux22 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux22 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux21 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux21 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1337

X-BAR Registers

www.ti.com

Table 8-79. OUTPUT4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux20 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux20 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux19 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux19 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux18 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux18 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux17 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux17 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux16 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux16 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux15 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux15 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux14 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux14 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1338

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-79. OUTPUT4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux13 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux13 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux12 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux12 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux11 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux11 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux10 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux10 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux9 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux9 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux8 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux8 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux7 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux7 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1339

X-BAR Registers

www.ti.com

Table 8-79. OUTPUT4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux6 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux6 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux5 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux5 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux4 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux4 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux3 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux3 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux2 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux2 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux1 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux1 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive OUTPUT4 of OUTPUT-XBAR
0: Respective output of Mux0 is disabled to drive the OUTPUT4 of
OUTPUT-XBAR
1: Respective output of Mux0 is enabled to drive the OUTPUT4 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1340

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.21 OUTPUT5MUXENABLE Register (Offset = 28h) [reset = 0h]
OUTPUT5MUXENABLE is shown in Figure 8-72 and described in Table 8-80.
Return to Summary Table.
Output X-BAR Mux Enable for Output 5
Figure 8-72. OUTPUT5MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-80. OUTPUT5MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux31 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux31 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux30 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux30 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux29 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux29 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux28 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux28 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1341

X-BAR Registers

www.ti.com

Table 8-80. OUTPUT5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux27 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux27 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux26 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux26 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux25 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux25 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux24 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux24 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux23 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux23 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux22 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux22 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux21 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux21 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1342

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-80. OUTPUT5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux20 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux20 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux19 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux19 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux18 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux18 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux17 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux17 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux16 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux16 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux15 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux15 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux14 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux14 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1343

X-BAR Registers

www.ti.com

Table 8-80. OUTPUT5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux13 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux13 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux12 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux12 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux11 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux11 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux10 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux10 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux9 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux9 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux8 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux8 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux7 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux7 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1344

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-80. OUTPUT5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux6 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux6 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux5 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux5 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux4 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux4 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux3 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux3 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux2 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux2 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux1 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux1 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive OUTPUT5 of OUTPUT-XBAR
0: Respective output of Mux0 is disabled to drive the OUTPUT5 of
OUTPUT-XBAR
1: Respective output of Mux0 is enabled to drive the OUTPUT5 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1345

X-BAR Registers

www.ti.com

8.3.5.22 OUTPUT6MUXENABLE Register (Offset = 2Ah) [reset = 0h]
OUTPUT6MUXENABLE is shown in Figure 8-73 and described in Table 8-81.
Return to Summary Table.
Output X-BAR Mux Enable for Output 6
Figure 8-73. OUTPUT6MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-81. OUTPUT6MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux31 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux31 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux30 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux30 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux29 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux29 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux28 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux28 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1346

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-81. OUTPUT6MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux27 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux27 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux26 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux26 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux25 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux25 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux24 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux24 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux23 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux23 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux22 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux22 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux21 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux21 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1347

X-BAR Registers

www.ti.com

Table 8-81. OUTPUT6MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux20 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux20 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux19 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux19 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux18 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux18 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux17 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux17 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux16 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux16 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux15 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux15 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux14 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux14 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1348

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-81. OUTPUT6MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux13 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux13 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux12 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux12 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux11 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux11 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux10 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux10 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux9 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux9 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux8 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux8 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux7 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux7 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1349

X-BAR Registers

www.ti.com

Table 8-81. OUTPUT6MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux6 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux6 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux5 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux5 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux4 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux4 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux3 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux3 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux2 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux2 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux1 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux1 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive OUTPUT6 of OUTPUT-XBAR
0: Respective output of Mux0 is disabled to drive the OUTPUT6 of
OUTPUT-XBAR
1: Respective output of Mux0 is enabled to drive the OUTPUT6 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1350

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.23 OUTPUT7MUXENABLE Register (Offset = 2Ch) [reset = 0h]
OUTPUT7MUXENABLE is shown in Figure 8-74 and described in Table 8-82.
Return to Summary Table.
Output X-BAR Mux Enable for Output 7
Figure 8-74. OUTPUT7MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-82. OUTPUT7MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux31 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux31 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux30 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux30 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux29 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux29 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux28 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux28 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1351

X-BAR Registers

www.ti.com

Table 8-82. OUTPUT7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux27 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux27 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux26 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux26 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux25 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux25 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux24 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux24 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux23 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux23 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux22 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux22 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux21 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux21 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1352

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-82. OUTPUT7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux20 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux20 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux19 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux19 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux18 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux18 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux17 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux17 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux16 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux16 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux15 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux15 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux14 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux14 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1353

X-BAR Registers

www.ti.com

Table 8-82. OUTPUT7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux13 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux13 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux12 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux12 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux11 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux11 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux10 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux10 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux9 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux9 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux8 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux8 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux7 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux7 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1354

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-82. OUTPUT7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux6 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux6 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux5 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux5 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux4 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux4 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux3 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux3 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux2 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux2 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux1 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux1 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive OUTPUT7 of OUTPUT-XBAR
0: Respective output of Mux0 is disabled to drive the OUTPUT7 of
OUTPUT-XBAR
1: Respective output of Mux0 is enabled to drive the OUTPUT7 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1355

X-BAR Registers

www.ti.com

8.3.5.24 OUTPUT8MUXENABLE Register (Offset = 2Eh) [reset = 0h]
OUTPUT8MUXENABLE is shown in Figure 8-75 and described in Table 8-83.
Return to Summary Table.
Output X-BAR Mux Enable for Output 8
Figure 8-75. OUTPUT8MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 8-83. OUTPUT8MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux31 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux31 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux30 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux30 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux29 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux29 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux28 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux28 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1356

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-83. OUTPUT8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux27 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux27 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux26 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux26 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux25 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux25 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux24 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux24 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux23 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux23 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux22 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux22 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux21 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux21 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1357

X-BAR Registers

www.ti.com

Table 8-83. OUTPUT8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux20 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux20 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux19 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux19 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux18 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux18 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux17 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux17 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux16 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux16 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux15 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux15 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux14 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux14 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1358

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

Table 8-83. OUTPUT8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux13 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux13 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux12 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux12 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux11 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux11 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux10 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux10 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux9 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux9 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux8 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux8 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux7 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux7 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1359

X-BAR Registers

www.ti.com

Table 8-83. OUTPUT8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux6 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux6 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux5 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux5 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux4 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux4 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux3 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux3 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux2 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux2 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux1 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux1 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive OUTPUT8 of OUTPUT-XBAR
0: Respective output of Mux0 is disabled to drive the OUTPUT8 of
OUTPUT-XBAR
1: Respective output of Mux0 is enabled to drive the OUTPUT8 of
OUTPUT-XBAR
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1360

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.25 OUTPUTLATCH Register (Offset = 30h) [reset = 0h]
OUTPUTLATCH is shown in Figure 8-76 and described in Table 8-84.
Return to Summary Table.
Output X-BAR Output Latch
Figure 8-76. OUTPUTLATCH Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
OUTPUT4
R-0h

2
OUTPUT3
R-0h

1
OUTPUT2
R-0h

0
OUTPUT1
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
OUTPUT8
R-0h

6
OUTPUT7
R-0h

5
OUTPUT6
R-0h

4
OUTPUT5
R-0h

Table 8-84. OUTPUTLATCH Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

OUTPUT8

R

0h

Records the OUTPUT8 of OUTPUT-XBAR.

7

0: Respective output has not been triggered
1: Respective output is triggered
Refer to the Output X-BAR section of this chapter for more details.
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
6

OUTPUT7

R

0h

Records the OUTPUT7 of OUTPUT-XBAR.
0: Respective output has not been triggered
1: Respective output is triggered
Refer to the Output X-BAR section of this chapter for more details.
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

5

OUTPUT6

R

0h

Records the OUTPUT6 of OUTPUT-XBAR.
0: Respective output has not been triggered
1: Respective output is triggered
Refer to the Output X-BAR section of this chapter for more details.
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1361

X-BAR Registers

www.ti.com

Table 8-84. OUTPUTLATCH Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

OUTPUT5

R

0h

Records the OUTPUT5 of OUTPUT-XBAR.
0: Respective output has not been triggered
1: Respective output is triggered
Refer to the Output X-BAR section of this chapter for more details.
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

3

OUTPUT4

R

0h

Records the OUTPUT4 of OUTPUT-XBAR.
0: Respective output has not been triggered
1: Respective output is triggered
Refer to the Output X-BAR section of this chapter for more details.
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

2

OUTPUT3

R

0h

Records the OUTPUT3 of OUTPUT-XBAR.
0: Respective output has not been triggered
1: Respective output is triggered
Refer to the Output X-BAR section of this chapter for more details.
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

1

OUTPUT2

R

0h

Records the OUTPUT2 of OUTPUT-XBAR.
0: Respective output has not been triggered
1: Respective output is triggered
Refer to the Output X-BAR section of this chapter for more details.
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

0

OUTPUT1

R

0h

Records the OUTPUT1 of OUTPUT-XBAR.
0: Respective output has not been triggered
1: Respective output is triggered
Refer to the Output X-BAR section of this chapter for more details.
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

1362

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.26 OUTPUTLATCHCLR Register (Offset = 32h) [reset = 0h]
OUTPUTLATCHCLR is shown in Figure 8-77 and described in Table 8-85.
Return to Summary Table.
Output X-BAR Output Latch Clear
Figure 8-77. OUTPUTLATCHCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
OUTPUT4
R=0/W=1-0h

2
OUTPUT3
R=0/W=1-0h

1
OUTPUT2
R=0/W=1-0h

0
OUTPUT1
R=0/W=1-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
OUTPUT8
R=0/W=1-0h

6
OUTPUT7
R=0/W=1-0h

5
OUTPUT6
R=0/W=1-0h

4
OUTPUT5
R=0/W=1-0h

Table 8-85. OUTPUTLATCHCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

OUTPUT8

R=0/W=1

0h

Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR

7

Writing 1 clears the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
6

OUTPUT7

R=0/W=1

0h

Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR
Writing 1 clears the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

OUTPUT6

R=0/W=1

0h

Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR
Writing 1 clears the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

OUTPUT5

R=0/W=1

0h

Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR
Writing 1 clears the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1363

X-BAR Registers

www.ti.com

Table 8-85. OUTPUTLATCHCLR Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

OUTPUT4

R=0/W=1

0h

Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR
Writing 1 clears the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

OUTPUT3

R=0/W=1

0h

Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR
Writing 1 clears the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

OUTPUT2

R=0/W=1

0h

Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR
Writing 1 clears the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

OUTPUT1

R=0/W=1

0h

Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR
Writing 1 clears the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1364

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.27 OUTPUTLATCHFRC Register (Offset = 34h) [reset = 0h]
OUTPUTLATCHFRC is shown in Figure 8-78 and described in Table 8-86.
Return to Summary Table.
Output X-BAR Output Latch Clear
Figure 8-78. OUTPUTLATCHFRC Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
OUTPUT4
R=0/W=1-0h

2
OUTPUT3
R=0/W=1-0h

1
OUTPUT2
R=0/W=1-0h

0
OUTPUT1
R=0/W=1-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
OUTPUT8
R=0/W=1-0h

6
OUTPUT7
R=0/W=1-0h

5
OUTPUT6
R=0/W=1-0h

4
OUTPUT5
R=0/W=1-0h

Table 8-86. OUTPUTLATCHFRC Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

OUTPUT8

R=0/W=1

0h

Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR

7

Writing 1 sets the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
6

OUTPUT7

R=0/W=1

0h

Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR
Writing 1 sets the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

OUTPUT6

R=0/W=1

0h

Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR
Writing 1 sets the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

OUTPUT5

R=0/W=1

0h

Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR
Writing 1 sets the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1365

X-BAR Registers

www.ti.com

Table 8-86. OUTPUTLATCHFRC Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

OUTPUT4

R=0/W=1

0h

Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR
Writing 1 sets the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

OUTPUT3

R=0/W=1

0h

Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR
Writing 1 sets the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

OUTPUT2

R=0/W=1

0h

Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR
Writing 1 sets the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

OUTPUT1

R=0/W=1

0h

Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR
Writing 1 sets the corresponding output latch bit in the
OUTPUTLATCH register
Write of 0 has no effect
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1366

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.28 OUTPUTLATCHENABLE Register (Offset = 36h) [reset = 0h]
OUTPUTLATCHENABLE is shown in Figure 8-79 and described in Table 8-87.
Return to Summary Table.
Output X-BAR Output Latch Enable
Figure 8-79. OUTPUTLATCHENABLE Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
OUTPUT4
R/W-0h

2
OUTPUT3
R/W-0h

1
OUTPUT2
R/W-0h

0
OUTPUT1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
OUTPUT8
R/W-0h

6
OUTPUT7
R/W-0h

5
OUTPUT6
R/W-0h

4
OUTPUT5
R/W-0h

Table 8-87. OUTPUTLATCHENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

OUTPUT8

R/W

0h

Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR

7

0: Output Latch is not selected to driven the respective output
1: Output Latch is selected to drive the respective output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
6

OUTPUT7

R/W

0h

Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR
0: Output Latch is not selected to driven the respective output
1: Output Latch is selected to drive the respective output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

OUTPUT6

R/W

0h

Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR
0: Output Latch is not selected to driven the respective output
1: Output Latch is selected to drive the respective output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

OUTPUT5

R/W

0h

Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR
0: Output Latch is not selected to driven the respective output
1: Output Latch is selected to drive the respective output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1367

X-BAR Registers

www.ti.com

Table 8-87. OUTPUTLATCHENABLE Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

OUTPUT4

R/W

0h

Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR
0: Output Latch is not selected to driven the respective output
1: Output Latch is selected to drive the respective output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

OUTPUT3

R/W

0h

Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR
0: Output Latch is not selected to driven the respective output
1: Output Latch is selected to drive the respective output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

OUTPUT2

R/W

0h

Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR
0: Output Latch is not selected to driven the respective output
1: Output Latch is selected to drive the respective output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

OUTPUT1

R/W

0h

Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR
0: Output Latch is not selected to driven the respective output
1: Output Latch is selected to drive the respective output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1368

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.29 OUTPUTINV Register (Offset = 38h) [reset = 0h]
OUTPUTINV is shown in Figure 8-80 and described in Table 8-88.
Return to Summary Table.
Output X-BAR Output Inversion
Figure 8-80. OUTPUTINV Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
OUTPUT4
R/W-0h

2
OUTPUT3
R/W-0h

1
OUTPUT2
R/W-0h

0
OUTPUT1
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
OUTPUT8
R/W-0h

6
OUTPUT7
R/W-0h

5
OUTPUT6
R/W-0h

4
OUTPUT5
R/W-0h

Table 8-88. OUTPUTINV Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

OUTPUT8

R/W

0h

Selects polarity for OUTPUT8 of OUTPUT-XBAR

7

0: drives active high output
1: drives active-low output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
6

OUTPUT7

R/W

0h

Selects polarity for OUTPUT7 of OUTPUT-XBAR
0: drives active high output
1: drives active-low output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

OUTPUT6

R/W

0h

Selects polarity for OUTPUT6 of OUTPUT-XBAR
0: drives active high output
1: drives active-low output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

OUTPUT5

R/W

0h

Selects polarity for OUTPUT5 of OUTPUT-XBAR
0: drives active high output
1: drives active-low output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1369

X-BAR Registers

www.ti.com

Table 8-88. OUTPUTINV Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

OUTPUT4

R/W

0h

Selects polarity for OUTPUT4 of OUTPUT-XBAR
0: drives active high output
1: drives active-low output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

OUTPUT3

R/W

0h

Selects polarity for OUTPUT3 of OUTPUT-XBAR
0: drives active high output
1: drives active-low output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

OUTPUT2

R/W

0h

Selects polarity for OUTPUT2 of OUTPUT-XBAR
0: drives active high output
1: drives active-low output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

OUTPUT1

R/W

0h

Selects polarity for OUTPUT1 of OUTPUT-XBAR
0: drives active high output
1: drives active-low output
Refer to the Output X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1370

Crossbar (X-BAR)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

X-BAR Registers

www.ti.com

8.3.5.30 OUTPUTLOCK Register (Offset = 3Eh) [reset = 0h]
OUTPUTLOCK is shown in Figure 8-81 and described in Table 8-89.
Return to Summary Table.
Output X-BAR Configuration Lock register
Figure 8-81. OUTPUTLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
LOCK
R/WSOnce-0h

KEY
R=0/W=1-0h
23

22

21

20
KEY
R=0/W=1-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 8-89. OUTPUTLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

KEY

R=0/W=1

0h

Bit-0 of this register can be set only if KEY= 0x5a5a
Reset type: CPU1.SYSRSn

15-1

RESERVED

R=0

0h

Reserved

LOCK

R/WSOnce

0h

Locks the configuration for OUTPUT-XBAR. Once the configuration
is locked, writes to the below registers for OUTPUT-XBAR is
blocked.

0

Registers Affected by the LOCK mechanism:
OUTPUT-XBAROUTyMUX0TO15CFG
OUTPUT-XBAROUTyMUX16TO31CFG
OUTPUT-XBAROUTyMUXENABLE
OUTPUT-XBAROUTLATENABLE
OUTPUT-XBAROUTINV
0: Writes to the above registers are allowed
1: Writes to the above registers are blocked
Note:
[1] LOCK mechanism only apples to writes. Reads are never
blocked.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Crossbar (X-BAR)

1371

Chapter 9
SPRUHM8G – December 2013 – Revised September 2017

Analog Subsystem
This analog subsystem module is described in this chapter.
Topic

9.1
9.2

1372

...........................................................................................................................

Page

Analog Subsystem .......................................................................................... 1373
Registers ....................................................................................................... 1377

Analog Subsystem

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

www.ti.com

9.1

Analog Subsystem
The analog modules on this device include the Analog-to-Digital Converter (ADC), Temperature Sensor,
Buffered Digital-to-Analog Converter (DAC), and Comparator Subsystem (CMPSS).

9.1.1 Features
The analog subsystem has the following features:
• Flexible voltage references
– The ADCs are referenced to VREFHIx and VREFLOx pins
• VREFHIx pin voltage must be driven in externally
• The buffered DACs are referenced to VREFHIx and VREFLOx
– Alternately, these DACs can be referenced to the VDAC pin and VSSA
• The comparator DACs are referenced to VDDA and VSSA
– Alternately, these DACs can be referenced to the VDAC pin and VSSA
• Flexible pin usage
– Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
• Internal connection to VREFLO on all ADCs for offset self-calibration

9.1.2 Block Diagram
The subsystem block diagrams show the connections between the different integrated analog modules
and to the device pins. These pins fall into two categories: analog module inputs/outputs and reference
pins.
The reference pins, VREFHIA to VRFHID and VREFLOA to VREFLOD, can be used to externally supply
the reference to the ADC. VREFHIA can also be used to supply the reference voltage to DAC A and DAC
B and VREFHIB can be used to supply the reference to DAC C.
The analog module input/outputs are all ADC inputs by default. The pins which connect to CMPSS inputs
can be used for the CMPSS without further action and without preventing use as an ADC input
simultaneously. DAC outputs must be enabled; this will prevent the channel from simultaneously being
used as an ADC input (but the ADC can be used to sample the DAC output voltage if desired).
The VDAC reference pin can be used to set an alternate range for DAC A, DAC B, and DAC C and for the
DACs inside the CMPSS modules (the CMPSS DACs are referenced to VDDA and VSSA by default).
Using this pin as a reference will prevent the channel from being used as an ADC input (but the ADC can
be used to sample the VDAC voltage if desired). The choice of reference is configurable per-module for
each CMPSS or buffered DAC and the selection is made via the module’s configuration registers.
The block diagram for the analog subsystem is presented in the following graphics.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

1373

Analog Subsystem

www.ti.com

Figure 9-1. Analog Subsystem Block Diagram (337-Ball ZWT)

VREFLOA
VREFLOA

TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

REFHI

VREFHIA

VDAC

DACREFSEL

ADC-A
16-bits
or
12-bits
(selectable)

VDDA or VDAC

Digital
Filter

CTRIP1H
CTRIPOUT1H

Digital
Filter

CTRIP1L
CTRIPOUT1L

DAC12
DAC12
VSSA

VDAC

DACREFSEL

VREFLOA

Comparator Subsystem 1

CMPIN1N

VREFHIA

REFLO

CMPIN1P

12-bit
Buffered
DAC

DACOUTB

DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5

DACOUTA

VREFHIA

12-bit
Buffered
DAC

CMPIN2P

Comparator Subsystem 2
VDDA or VDAC

Digital
Filter

CTRIP2H
CTRIPOUT2H

Digital
Filter

CTRIP2L
CTRIPOUT2L

DAC12
DAC12

CMPIN2N

VREFHIB
VSSA

VREFLOB
VREFLOB

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

REFHI

CMPIN3P
VREFHIB

VDAC

DACREFSEL

ADC-B
16-bits
or
12-bits
(selectable)

12-bit
Buffered
DAC

DACOUTC

VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
ADCINB4
ADCINB5

Comparator Subsystem 3
VDDA or VDAC

DAC12

CMPIN4P

Digital
Filter

CTRIP3L
CTRIPOUT3L

Comparator Subsystem 4
VDDA or VDAC

Digital
Filter

CTRIP4H
CTRIPOUT4H

Digital
Filter

CTRIP4L
CTRIPOUT4L

DAC12

REFLO

DAC12

VREFLOB

CTRIP3H
CTRIPOUT3H

DAC12

CMPIN3N

VSSA

Digital
Filter

CMPIN4N

VREFHIC

CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4
CMPIN5N/ADCINC5
VREFLOC
VREFLOC

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

REFHI

CMPIN5P

Comparator Subsystem 5
VDDA or VDAC

Digital
Filter

CTRIP5H
CTRIPOUT5H

Digital
Filter

CTRIP5L
CTRIPOUT5L

DAC12

ADC-C
16-bits
or
12-bits
(selectable)

DAC12

CMPIN5N

CMPIN6P

Comparator Subsystem 6
VDDA or VDAC

CTRIP6H
CTRIPOUT6H

Digital
Filter

CTRIP6L
CTRIPOUT6L

DAC12

REFLO

DAC12

VREFLOC

Digital
Filter

CMPIN6N

VREFHID
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
ADCIND4
ADCIND5
VREFLOD
VREFLOD

VREFLOD

1374

Analog Subsystem

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

REFHI

CMPIN7P

Comparator Subsystem 7
VDDA or VDAC

Digital
Filter

CTRIP7H
CTRIPOUT7H

Digital
Filter

CTRIP7L
CTRIPOUT7L

DAC12

ADC-D
16-bits
or
12-bits
(selectable)

DAC12

CMPIN7N

CMPIN8P

Comparator Subsystem 8
VDDA or VDAC

Digital
Filter

CTRIP8H
CTRIPOUT8H

Digital
Filter

CTRIP8L
CTRIPOUT8L

DAC12

REFLO

DAC12

CMPIN8N

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

www.ti.com

Figure 9-2. Analog Subsystem Block Diagram (176-Pin PTP)

TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15

REFHI

VREFHIA

VDAC

DACREFSEL

ADC-A
16-bits
or
12-bits
(selectable)

VREFLOB
VREFLOB

Digital
Filter

CTRIP1H
CTRIPOUT1H

DAC12

Digital
Filter

CTRIP1L
CTRIPOUT1L

VSSA

VDAC

12-bit
Buffered
DAC

VREFHIB
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3

VDDA or VDAC
DAC12

DACREFSEL

VREFLOA

Comparator Subsystem 1

CMPIN1N

VREFHIA

REFLO

CMPIN1P

12-bit
Buffered
DAC

DACOUTB

VREFLOA
VREFLOA

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

CMPIN2P

Comparator Subsystem 2
VDDA or VDAC

Digital
Filter

CTRIP2H
CTRIPOUT2H

Digital
Filter

CTRIP2L
CTRIPOUT2L

DAC12
DAC12

CMPIN2N
VSSA

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

REFHI

CMPIN3P
VREFHIB

DACOUTC

DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5

DACOUTA

VREFHIA

VDAC

DACREFSEL

ADC-B
16-bits
or
12-bits
(selectable)

Comparator Subsystem 3
VDDA or VDAC

CMPIN3N
VSSA

CMPIN4P

Digital
Filter

CTRIP3L
CTRIPOUT3L

Comparator Subsystem 4
VDDA or VDAC

Digital
Filter

CTRIP4H
CTRIPOUT4H

Digital
Filter

CTRIP4L
CTRIPOUT4L

DAC12

REFLO

DAC12

VREFLOB

CTRIP3H
CTRIPOUT3H

DAC12
DAC12

12-bit
Buffered
DAC

Digital
Filter

CMPIN4N

VREFHIC

CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4

VREFLOC
VREFLOC

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

REFHI

CMPIN5P

Comparator Subsystem 5
VDDA or VDAC

Digital
Filter

CTRIP5H
CTRIPOUT5H

Digital
Filter

CTRIP5L
CTRIPOUT5L

DAC12

ADC-C

DAC12

16-bits
or
12-bits
(selectable)
CMPIN6P

Comparator Subsystem 6
VDDA or VDAC

CTRIP6H
CTRIPOUT6H

Digital
Filter

CTRIP6L
CTRIPOUT6L

DAC12

REFLO

DAC12

VREFLOC

Digital
Filter

CMPIN6N

VREFHID
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
ADCIND4

VREFLOD
VREFLOD

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

REFHI

CMPIN7P

Comparator Subsystem 7
VDDA or VDAC

Digital
Filter

CTRIP7H
CTRIPOUT7H

Digital
Filter

CTRIP7L
CTRIPOUT7L

DAC12

ADC-D
16-bits
or
12-bits
(selectable)

DAC12

CMPIN7N

CMPIN8P

Comparator Subsystem 8
VDDA or VDAC

CTRIP8H
CTRIPOUT8H

Digital
Filter

CTRIP8L
CTRIPOUT8L

DAC12

REFLO

DAC12

VREFLOD

Digital
Filter

CMPIN8N

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

1375

Analog Subsystem

www.ti.com

Figure 9-3. Analog Subsystem Block Diagram (100-Pin PZP)

TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15

REFHI

VREFHIA

VDAC

DACREFSEL

ADC-A
16-bits
or
12-bits
(selectable)

VREFLOA

VREFLOB
VREFLOB

VREFLOB

VDDA or VDAC

DAC12

CMPIN1N

Digital
Filter

CTRIP1H
CTRIPOUT1H

Digital
Filter

CTRIP1L
CTRIPOUT1L

VSSA

VREFHIA

VDAC

CMPIN2P

Comparator Subsystem 2
VDDA or VDAC

Digital
Filter

CTRIP2H
CTRIPOUT2H

Digital
Filter

CTRIP2L
CTRIPOUT2L

DAC12

12-bit
Buffered
DAC

VREFHIB
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
ADCINB4
ADCINB5

Comparator Subsystem 1

DAC12

DACREFSEL

REFLO

CMPIN1P

12-bit
Buffered
DAC

DACOUTB

VREFLOA
VREFLOA

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

DAC12

CMPIN2N
VSSA

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

REFHI
VREFHIB

VDAC

DACREFSEL

ADC-B
16-bits
or
12-bits
(selectable)

12-bit
Buffered
DAC

DACOUTC

DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5

DACOUTA

VREFHIA

CMPIN3P

Comparator Subsystem 3
VDDA or VDAC

Digital
Filter

CTRIP3H
CTRIPOUT3H

Digital
Filter

CTRIP3L
CTRIPOUT3L

DAC12
DAC12

CMPIN3N
VSSA

CMPIN4P

Comparator Subsystem 4
VDDA or VDAC

Digital
Filter

CTRIP4H
CTRIPOUT4H

Digital
Filter

CTRIP4L
CTRIPOUT4L

DAC12

REFLO

DAC12

CMPIN4N

NOTES:
• Not all analog pins are available on all devices. Consult the datasheet for your specific device to
determine which pins are available.
• Consult the datasheet for your device to determine the allowable voltage range for VREFHI and
VREFLO
• An external capacitor is required on the VREFHI pins. Consult the datasheet for the specific value
required.
• For buffered DAC modules, VSSA will be the low reference whether VREFHIx or VDAC is selected as
the high reference.
• For CMPSS modules, VSSA will be the low reference whether VDAC or VDDA is selected as the high
reference.

9.1.3 Lock Registers
Setting the TSNSCTL bit in the LOCK register will disable any further changes in the TSNSCTL register.

1376

Analog Subsystem

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

9.2

Registers

9.2.1 Analog Subsystem Base Addresses
Table 9-1. Analog Subsystem Base Address Table
Device Registers

Register Name

Start Address

End Address

AnalogSubsysRegs

ANALOG_SUBSYS_REGS

0x0005_D180

0x0005_D1FF

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

1377

Registers

www.ti.com

9.2.2 ANALOG_SUBSYS_REGS Registers
Table 9-2 lists the memory-mapped registers for the ANALOG_SUBSYS_REGS. All register offset
addresses not listed in Table 9-2 should be considered as reserved locations and the register contents
should not be modified.
Table 9-2. ANALOG_SUBSYS_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

20h

INTOSC1TRIM

Internal Oscillator 1 Trim Register

EALLOW

Go

22h

INTOSC2TRIM

Internal Oscillator 2 Trim Register

EALLOW

Go

26h

TSNSCTL

Temperature Sensor Control Register

EALLOW

Go

2Eh

LOCK

Lock Register

EALLOW

Go

36h

ANAREFTRIMA

Analog Reference Trim A Register

EALLOW

Go

38h

ANAREFTRIMB

Analog Reference Trim B Register

EALLOW

Go

3Ah

ANAREFTRIMC

Analog Reference Trim C Register

EALLOW

Go

3Ch

ANAREFTRIMD

Analog Reference Trim D Register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 9-3 shows the codes that are
used for access types in this section.
Table 9-3. ANALOG_SUBSYS_REGS Access Type
Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

WOnce

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

1378

Analog Subsystem

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

9.2.2.1

INTOSC1TRIM Register (Offset = 20h) [reset = 0h]

INTOSC1TRIM is shown in Figure 9-4 and described in Table 9-4.
Return to Summary Table.
Internal Oscillator 1 Trim Register
Figure 9-4. INTOSC1TRIM Register
31

30

29

15

14
13
RESERVED
R-0h

28
27
RESERVED
R-0h

26

25

24

23

12

10

9

8

7

11

22

21

6
5
VALFINETRIM
R/W-0h

20
19
RESERVED
R-0h
4

3

18

17

16

2

1

0

Table 9-4. INTOSC1TRIM Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R

0h

Reserved

23-16

RESERVED

R

0h

Reserved

15-12

RESERVED

R

0h

Reserved

11-0

VALFINETRIM

R/W

0h

Oscillator Value Fine Trim Bits.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

1379

Registers

9.2.2.2

www.ti.com

INTOSC2TRIM Register (Offset = 22h) [reset = 0h]

INTOSC2TRIM is shown in Figure 9-5 and described in Table 9-5.
Return to Summary Table.
Internal Oscillator 2 Trim Register
Figure 9-5. INTOSC2TRIM Register
31

30

29

15

14
13
RESERVED
R-0h

28
27
RESERVED
R-0h

26

25

24

23

12

10

9

8

7

11

22

21

6
5
VALFINETRIM
R/W-0h

20
19
RESERVED
R-0h
4

3

18

17

16

2

1

0

Table 9-5. INTOSC2TRIM Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R

0h

Reserved

23-16

RESERVED

R

0h

Reserved

15-12

RESERVED

R

0h

Reserved

11-0

VALFINETRIM

R/W

0h

Oscillator Value Fine Trim Bits.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: XRSn

1380

Analog Subsystem

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

9.2.2.3

TSNSCTL Register (Offset = 26h) [reset = 0h]

TSNSCTL is shown in Figure 9-6 and described in Table 9-6.
Return to Summary Table.
Temperature Sensor Control Register
Figure 9-6. TSNSCTL Register
15

14

13

12

11

10

9

8

3

2

1

0
ENABLE
R/W-0h

RESERVED
R-0h
7

6

5

4
RESERVED
R-0h

Table 9-6. TSNSCTL Register Field Descriptions
Bit
15-1
0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

ENABLE

R/W

0h

Temperature Sensor Enable. This bit enables the temperature
sensor output to the ADC.
0 Disabled
1 Enabled
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

1381

Registers

9.2.2.4

www.ti.com

LOCK Register (Offset = 2Eh) [reset = 0h]

LOCK is shown in Figure 9-7 and described in Table 9-7.
Return to Summary Table.
Lock Register
Figure 9-7. LOCK Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
RESERVED
R-0h

27
RESERVED
R-0h

26
RESERVED
R-0h

25
RESERVED
R-0h

24
RESERVED
R-0h

23
RESERVED
R-0h

22
RESERVED
R-0h

21
RESERVED
R-0h

20
RESERVED
R-0h

19
RESERVED
R-0h

18

17
RESERVED
R-0h

16

15

14

13

12

11

10

9

8

3
TSNSCTL
R/WOnce-0h

2
RESERVED
R-0h

1
RESERVED
R-0h

0
RESERVED
R-0h

RESERVED
R-0h
7
RESERVED
R-0h

6
RESERVED
R-0h

5
RESERVED
R-0h

4
RESERVED
R-0h

Table 9-7. LOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

RESERVED

R

0h

Reserved

27

RESERVED

R

0h

Reserved

26

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23

RESERVED

R

0h

Reserved

22

RESERVED

R

0h

Reserved

21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18-7

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

TSNSCTL

R/WOnce

0h

Temperature Sensor Control Register Lock. Setting this bit will
disable any future write to the respective register. This bit can only
be cleared by a reset.
Reset type: CPU1.SYSRSn

2

RESERVED

R

0h

Reserved

1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

1382

Analog Subsystem

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

9.2.2.5

ANAREFTRIMA Register (Offset = 36h) [reset = 0h]

ANAREFTRIMA is shown in Figure 9-8 and described in Table 9-8.
Return to Summary Table.
Analog Reference Trim A Register
Figure 9-8. ANAREFTRIMA Register
31

30

29

15

14

13
IREFTRIM
R/W-0h

28
27
RESERVED
R-0h

26

25

12

10

9

11

24

23

22

21

8
7
BGSLOPETRIM
R/W-0h

6

5

20
19
RESERVED
R-0h
4

18

3
2
BGVALTRIM
R/W-0h

17

16

1

0

Table 9-8. ANAREFTRIMA Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R

0h

Reserved

23-16

RESERVED

R

0h

Reserved

15-11

IREFTRIM

R/W

0h

Reference Current Trim. This bit field defines the reference current
trim value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

10-6

BGSLOPETRIM

R/W

0h

Bandgap Slope Trim. This bit field defines the bandgap slope trim
value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

5-0

BGVALTRIM

R/W

0h

Bandgap Value Trim. This bit field defines the bandgap voltage
offset trim value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

1383

Registers

9.2.2.6

www.ti.com

ANAREFTRIMB Register (Offset = 38h) [reset = 0h]

ANAREFTRIMB is shown in Figure 9-9 and described in Table 9-9.
Return to Summary Table.
Analog Reference Trim B Register
Figure 9-9. ANAREFTRIMB Register
31

30

29

15

14

13
IREFTRIM
R/W-0h

28
27
RESERVED
R-0h

26

25

12

10

9

11

24

23

22

21

8
7
BGSLOPETRIM
R/W-0h

6

5

20
19
RESERVED
R-0h
4

18

3
2
BGVALTRIM
R/W-0h

17

16

1

0

Table 9-9. ANAREFTRIMB Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R

0h

Reserved

23-16

RESERVED

R

0h

Reserved

15-11

IREFTRIM

R/W

0h

Reference Current Trim. This bit field defines the reference current
trim value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

10-6

BGSLOPETRIM

R/W

0h

Bandgap Slope Trim. This bit field defines the bandgap slope trim
value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

5-0

BGVALTRIM

R/W

0h

Bandgap Value Trim. This bit field defines the bandgap voltage
offset trim value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

1384

Analog Subsystem

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

9.2.2.7

ANAREFTRIMC Register (Offset = 3Ah) [reset = 0h]

ANAREFTRIMC is shown in Figure 9-10 and described in Table 9-10.
Return to Summary Table.
Analog Reference Trim C Register
Figure 9-10. ANAREFTRIMC Register
31

30

29

15

14

13
IREFTRIM
R/W-0h

28
27
RESERVED
R-0h

26

25

12

10

9

11

24

23

22

21

8
7
BGSLOPETRIM
R/W-0h

6

5

20
19
RESERVED
R-0h
4

18

3
2
BGVALTRIM
R/W-0h

17

16

1

0

Table 9-10. ANAREFTRIMC Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R

0h

Reserved

23-16

RESERVED

R

0h

Reserved

15-11

IREFTRIM

R/W

0h

Reference Current Trim. This bit field defines the reference current
trim value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

10-6

BGSLOPETRIM

R/W

0h

Bandgap Slope Trim. This bit field defines the bandgap slope trim
value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

5-0

BGVALTRIM

R/W

0h

Bandgap Value Trim. This bit field defines the bandgap voltage
offset trim value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog Subsystem

1385

Registers

9.2.2.8

www.ti.com

ANAREFTRIMD Register (Offset = 3Ch) [reset = 0h]

ANAREFTRIMD is shown in Figure 9-11 and described in Table 9-11.
Return to Summary Table.
Analog Reference Trim D Register
Figure 9-11. ANAREFTRIMD Register
31

30

29

15

14

13
IREFTRIM
R/W-0h

28
27
RESERVED
R-0h

26

25

12

10

9

11

24

23

22

21

8
7
BGSLOPETRIM
R/W-0h

6

5

20
19
RESERVED
R-0h
4

18

3
2
BGVALTRIM
R/W-0h

17

16

1

0

Table 9-11. ANAREFTRIMD Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R

0h

Reserved

23-16

RESERVED

R

0h

Reserved

15-11

IREFTRIM

R/W

0h

Reference Current Trim. This bit field defines the reference current
trim value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

10-6

BGSLOPETRIM

R/W

0h

Bandgap Slope Trim. This bit field defines the bandgap slope trim
value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

5-0

BGVALTRIM

R/W

0h

Bandgap Value Trim. This bit field defines the bandgap voltage
offset trim value.
0x0 - Untrimmed
all other values - Trimmed
Reset type: XRSn

1386

Analog Subsystem

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 10
SPRUHM8G – December 2013 – Revised September 2017

Analog-to-Digital Converter (ADC)
The analog-to-digital converter module described in this chapter is a Type 4 ADC. See the TMS320C28xx,
28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with modules of the same type,
to determine the differences between the types, and for a list of device-specific differences within a type.
Topic

10.1
10.2
10.3
10.4

...........................................................................................................................
Analog-to-Digital Converter (ADC) ....................................................................
ADC Timings ..................................................................................................
Additional Information .....................................................................................
Registers .......................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Page

1388
1408
1413
1421

Analog-to-Digital Converter (ADC)

1387

Analog-to-Digital Converter (ADC)

10.1

www.ti.com

Analog-to-Digital Converter (ADC)
The ADC module described here is a successive approximation (SAR) style ADC with selectable
resolution of either 16 bits or 12 bits. This chapter refers to the analog circuits of the converter as the
“core,” and includes the channel select MUX, the sample-and-hold (S/H) circuit, the successive
approximation circuits, voltage reference circuits, and other analog support circuits. The digital circuits of
the converter are referred to as the “wrapper” and includes logic for programmable conversions, result
registers, interfaces to analog circuits, interfaces to the peripheral buses, post-processing circuits, and
interfaces to other on-chip modules.

10.1.1 Features
Each ADC module consists of a single sample-and-hold (s/h) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of
multiple ADCs. The ADC wrapper is start-of-conversion (SOC) based (see Section 10.1.4).
Each ADC has the following features:
• Selectable resolution of 12 bits or 16 bits
• Ratiometric external reference set by VREFHI\VREFLO
• Differential signal conversions (16-bit mode only)
• Single-ended signal conversions (12-bit mode only)
• Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
• 16 configurable SOCs
• 16 individually addressable result registers
• Multiple trigger sources
– S/W - software immediate start
– All ePWMs - ADCSOC A or B
– GPIO XINT2
– CPU Timers 0/1/2 (from each C28x core present)
– ADCINT1/2
• Four flexible PIE interrupts
• Burst mode
• Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture

NOTE: Not every channel may be pinned out from all ADCs. Check the datasheet for your device to
determine which channels are available.

10.1.2 ADC Block Diagram
The block diagram for the ADC core and ADC wrapper are presented in Figure 10-1.

1388

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

Figure 10-1. ADC Module Block Diagram
Analog to Digital Core

Analog to Digital Wrapper Logic

SIGNALMODE
RESOLUTION

RESOLUTION

CHSEL

ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15

[15:0]
ADCSOC

0
1

SOC
Arbitration
& Control

SOCx (0-15)

[15:0]

ACQPS

[15:0]

CHSEL

xV1IN+

7

u

DOUT1

8
xV
2 IN-

9

EOCx[15:0]

6

10
11
12
13
14

S/H Circuit

...

5

...

4

SOCxSTART[15:0]

2
3

ADCCOUNTER

TRIGGER[15:0]

SOC Delay
Timestamp

Converter
RESULT

ADCRESULT
0–15 Regs

15

TRIGSEL
Triggers

Input Circuit

SIGNALMODE

+

-

S

ADCPPBxOFFCAL

saturate
ADCPPBxOFFREF
-

+

S
VREFHI
CONFIG

VREFLO
Reference Voltage Levels

Trigger
Timestamp

ADCPPBxRESULT

Event
Logic

ADCEVT
ADCEVTINT

Post Processing Block (1-4)

Interrupt Block (1-4)

ADCINT1-4

10.1.3 ADC Configurability
Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per
ADC module. Table 10-1 summarizes the basic ADC options and their level of configurability. The
subsequent sections discuss these configurations.
Table 10-1. ADC Options and Configuration Levels
Options

Configurability

Clock

Per module (1)

Resolution

Per module (1)

Signal mode

Per module

Reference voltage source

Not configurable (external reference only)

Trigger source

Per SOC (1)

Converted channel

Per SOC

Acquisition window duration

Per SOC (1)

EOC location

Per module

Burst Mode

Per module (1)

(1)

Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. See Section 10.3.1 for guidance on when the ADCs are operating synchronously or
asynchronously.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1389

Analog-to-Digital Converter (ADC)

www.ti.com

10.1.3.1 Clock Configuration
The base ADC clock is provided directly by the system clock (SYSCLK). This clock is used to generate
the ADC acquisition window. The register ADCCTL2 has a PRESCALE field which determines the
ADCCLK. The ADCCLK is used to clock the converter.
In 16-bit mode, the core requires approximately 29.5 ADCLCK cycles to process a voltage into a
conversion result, while in 12-bit mode, this process requires approximately 10.5 ADCCLK cycles. The
choice of resolution will also determine the necessary duration of the acquisition window, see
Section 10.3.2.

NOTE: To determine an appropriate value for ADCCTL2.PRESCALE, consult the datasheet of your
device to determine the maximum SYSCLK and ADCCLK frequency.

10.1.3.2 Resolution
The resolution of the ADC determines how finely the analog range is quantized into digital values. This
ADC supports a configurable resolution of 16 bits or 12 bits. The resolution should be configured by using
the AdcSetMode function provided in ControlSUITE in F2837xD_Adc.c. This function ensures that the
correct trim is loaded into the ADC trim registers. This function must be called at least once after a device
reset. The resolution should not be configured by writing to the ADCCTL2 register directly. The resolution
can be changed at any time when the ADC is idle (no active or pending SOCs). No wait time is necessary
after changing the resolution before conversions can be initiated. If SOCs are active or pending when the
resolution is changed, those SOCs may produce incorrect conversion results.

10.1.3.3 Voltage Reference
Each ADC has a VREFHI input and a VREFLO input, which is used as a ratiometric reference.
See Section 10.3.4 for information on how to supply the reference voltage.
NOTES:
• On devices with no external VREFLO signals, VREFLO has been internally connected to the device
analog ground, VSSA.
• Consult the datasheet for your device to determine the allowable voltage range for VREFHI and
VREFLO.
• The external reference mode requires an external capacitor on the VREFHI pin. Consult the device
datasheet for the specific value required.
10.1.3.4 Signal Mode
The ADC supports two signal modes: single-ended and differential. In single-ended mode, the input
voltage to the converter is sampled through a single pin (ADCINx), referenced to VREFLO. In differential
signaling mode, the input voltage to the converter is sampled through a pair of input pins, one of which is
the positive input (ADCINxP) and the other is the negative input (ADCINxN). The actual input voltage is
the difference between the two (ADCINxP – ADCINxN). .
The signal mode should be configured by using the AdcSetMode function provided in ControlSUITE in
F2837xD_Adc.c. This function ensures that the correct trim is loaded into the ADC trim registers. This
function must be called at least once after a device reset. The signal mode should not be configured by
writing to the ADCCTL2 register directly.
NOTES:
• In 16-bit differential signaling mode, VREFLO must be connected to VSSA.
• In differential signal mode, the common mode voltage is
VCM = (ADCINxP + ADCINxN)/2
The datasheet for a particular device will place some requirements on how close this voltage needs to
be to
(VREFHI + VREFLO)/2
1390

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

•

Note: The above condition is not met by connecting the negative input to VSSA or VREFLO.
Differential signaling mode is advantageous because noise encountered on both inputs will be largely
cancelled. The effect can be maximized by routing the positive and negative traces for the same
differential input as close together as possible and keeping them symmetrical with respect to the signal
reference.

10.1.3.5 Expected Conversion Results
Based on a given analog input voltage, the ideal expected digital conversion is given by the tables below.
Fractional values are truncated.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1391

Analog-to-Digital Converter (ADC)

www.ti.com

Table 10-2. Analog to 12-bit Digital Formulas
Analog Input
Single-Ended

Differential

Digital Result

when ADCINy ≤ VREFLO

ADCRESULTx = 0

when VREFLO < ADCINy < VREFHI

æ ADCINy - VREFLO ö
ç
÷
ADCRESULTx = 4096è VREFHI - VREFLO ø

when ADCINy ≥ VREFHI

ADCRESULTx = 4095

Invalid Mode

Invalid Mode

Table 10-3. Analog to 16-bit Digital Formulas
Analog Input

Digital Result

Single-Ended

Invalid Mode

Invalid Mode

Differential

when ADCINyP - ADCINyN ≤ -VREFHI

ADCRESULTx = 0

when -VREFHI < ADCINyP - ADCINyN ≤ VREFHI

æ ADCINyP - ADCINyN + VREFHI ö
ç
÷
2 VREFHI
ø
ADCRESULTx = 65536 è

when ADCINyP - ADCINyN ≥ VREFHI

ADCRESULTx = 65535

10.1.3.6 Interpreting Conversion Results
Based on a given ADC conversion result, the ideal corresponding analog input is given by the below
tables. This corresponds to the center of the possible range of analog voltages that could have produced
this conversion result.
Table 10-4. 12-Bit Digital-to-Analog Formulas
Digital Value
Single-Ended

Differential

Analog Equivalent

when ADCRESULTy = 0

ADCINx ≤ VREFLO

when 0 < ADCRESULTy < 4095

æ ADCRESULTy ö
ç
÷ + VREFLO
4096
ø
ADCINx = (VREFHI - VREFLO) è

when ADCRESULTy = 4095

ADCINx ≥ VREFHI

Invalid Mode

Invalid Mode

Table 10-5. 16-Bit Digital-to-Analog Formulas
Digital Value

Analog Equivalent

Single-Ended

Invalid Mode

Invalid Mode

Differential

when ADCRESULTy = 0

ADCINxP - ADCINxN ≤ -VREFHI

when 0 < ADCRESULTy < 65535

æ 2 ADCRESULTy
ö
- 1÷
ç
65536
ø
ADCINxP - ADCINxN = VREFHI è

when ADCRESULTy = 65535

ADCINxP - ADCINxN ≥ VREFHI

1392

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

10.1.4 SOC Principle of Operation
The ADC triggering and conversion sequencing is accomplished through configurable start-of-conversions
(SOCs). Each SOC is a configuration set defining the single conversion of a single channel. In that set
there are three configurations: the trigger source that starts the conversion, the channel to convert, and
the acquisition (sample) window duration. Upon receiving the trigger configured for a SOC, the wrapper
will ensure that the specified channel is captured using the specified acquisition window duration.
Multiple SOCs can be configured for the same trigger, channel, and/or acquisition window as desired.
Configuring multiple SOCs to use the same trigger will allow the trigger to generate a sequence of
conversions. Configuring multiple SOCs to use the same trigger and channel will allow for oversampling.
Figure 10-2. SOC Block Diagram
SOC
Arbitration
and Control

SOC15
SOC2
SOC1
SOC0

ACQPS

ADCSOC15CTL.ACQPS

CHSEL

ADCSOC15CTL.CHSEL

ADCSOC0CTL.TRIGSEL
ADCSOC2CTL.ACQPS
ADCSOC1CTL.ACQPS
ADCSOC0CTL.ACQPS

ADCSOC0CTL.ACQPS

ADCSOC2CTL.CHSEL
ADCSOC1CTL.CHSEL
ADCSOC0CTL.CHSEL

0
1
2

ADCSOC0CTL.CHSEL

ADCSOCFLG1.SOC15

SOC

31

SOCOVF

ADCSOCFLG1.SOC2
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC0

Set

ADCTRIG1
ADCTRIG2

ADCTRIG31
ADCSOCFRC1.SOC0

Latch

0

Clear

1

ADCINT1

2

ADCINT2

3

undefined

SOC15START

SOC2START
SOC1START

ADCINTSOCSEL1.SOC0

SOC0START

REQSTAMP

10.1.4.1 SOC Configuration
Each SOC has its own configuration register, ADCSOCxCTL. Within this register, SOCx can be configured
for trigger source, channel to convert, and acquisition (sample) window duration.
10.1.4.2 Trigger Operation
Each SOC can be configured to start on one of many input triggers. The primary trigger select for SOCx is
in the ADCSOCxCTL.TRIGSEL register, which can select between:
• Disabled (software only)
• CPU Timers 0/1/2 (from each C28x core present)
• GPIO: Input X-Bar INPUT5
• ePWM1 to ePWM12, ADCSOCA or ADCSOCB

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1393

Analog-to-Digital Converter (ADC)

www.ti.com

In addition, each SOC can also be triggered when the ADCINT1 flag or ADCINT2 flag is set. This is
achieved by configuring the ADCINTSOCSEL1 register (for SOC0 to SOC7) or the ADCINTSOCSEL2
register (for SOC8 to SOC15). This is useful for creating continuous conversions.
10.1.4.3 ADC Acquisition (Sample and Hold) Window
External signal sources vary in their ability to drive an analog signal quickly and effectively. In order to
achieve rated resolution, the signal source needs to charge the sampling capacitor in the ADC core to
within 0.5LSBs of the signal voltage. The acquisition window is the amount of time the sampling capacitor
is allowed to charge and is configurable for SOCx by the ADCSOCxCTL.ACQPS register.
ACQPS is a 9-bit register that can be set to a value between 0 and 511, resulting in an acquisition window
duration of:
Acquisition window = (ACQPS + 1)∙(System Clock (SYSCLK) cycle time)
• The acquisition window duration is based on the System Clock (SYSCLK), not the ADC clock
(ADCCLK).
• The selected acquisition window duration must be at least as long as one ADCCLK cycle.
• The datasheet will specify a minimum acquisition window duration (in nanoseconds). The user is
responsible for selecting an acquisition window duration that meets this requirement.
10.1.4.4 ADC Input Models
For single-ended operation, the ADC input characteristics for values in the single-ended input model (see
Figure 10-3) can be found in the device data manual.
Figure 10-3. Single-Ended Input Model
ADC
Rs

ADCINx
Switch

AC

Ron

Cp

Ch

VREFLO

For differential operation, the ADC input characteristics for values in the differential input model (see
Figure 10-4 ) can be found in the device data manual.
Figure 10-4. Differential Input Model

ADC

ADCINxP

Rs

Cp

Switch

Ron
Ch

VSSA

AC

Cp

ADCINxN

Switch

Ron

Rs

These input models should be used along with actual signal source impedance to determine the
acquisition window duration. See Section 10.3.2 for more information.

1394

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

10.1.4.5 Channel Selection
Each SOC can be configured to convert any of the ADC channels. This behavior is selected for SOCx by
the ADCSOCxCTL.CHSEL register. Depending on the signal mode, the selection is different. For singleended signal mode, the value in CHSEL selects a single pin as the input. For differential signal mode, the
value in CHSEL selects an even-odd pin pair to be the positive and negative inputs. This is summarized in
Table 10-6.
Table 10-6. Channel Selection of Input Pins
Input Mode

CHSEL

Input

Single-Ended

0

ADCIN0

1

ADCIN1

2

ADCIN2

3

ADCIN3

4

ADCIN4

5

ADCIN5

6

ADCIN6

7

ADCIN7

8

ADCIN8

9

ADCIN9

10

ADCIN10

11

ADCIN11

12

ADCIN12

13

ADCIN13

14

ADCIN14

15
Differential

ADCIN15

CHSEL

Positive Input

Negative Input

0 or 1

ADCIN0

ADCIN1

2 or 3

ADCIN2

ADCIN3

4 or 5

ADCIN4

ADCIN5

6 or 7

ADCIN6

ADCIN7

8 or 9

ADCIN8

ADCIN9

10 or 11

ADCIN10

ADCIN11

12 or 13

ADCIN12

ADCIN13

14 or 15

ADCIN14

ADCIN15

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1395

Analog-to-Digital Converter (ADC)

www.ti.com

10.1.5 SOC Configuration Examples
The following sections provide some specific examples of how to configure the SOCs to produce some
conversions.
10.1.5.1 Single Conversion from ePWM Trigger
To configure ADCA to perform a single conversion on channel ADCIN1 when the ePWM timer reaches its
period match, a few things are necessary. First, ePWM3 must be configured to generate an SOCA or
SOCB signal (in this statement, SOC refers to a signal in the ePWM module). See the Enhanced Pulse
Width Modulator Module (ePWM) chapter on how to do this. Assume that SOCB was chosen.
SOC5 is chosen arbitrarily. Any of the 16 SOCs could be used.
Assuming a 100ns sample window is desired with a SYSCLK frequency of 200MHz, then the acquisition
window duration should be 100ns/5ns = 20 SYSCLK cycles. The ACQPS field should therefore be set to
20 – 1 = 19.
AdcaRegs.ADCSOC5CTL.bit.CHSEL = 1;
AdcaRegs.ADCSOC5CTL.bit.ACQPS = 19;
AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = 10;

//SOC5 will convert ADCINA1
//SOC5 will use sample duration of 20 SYSCLK cycles
//SOC5 will begin conversion on ePWM3 SOCB

As configured, when ePWM3 matches its period and generates the SOCB signal, the ADC will begin
sampling channel ADCINA1 (SOC5) immediately if the ADC is idle. If the ADC is busy, ADCINA1 will
begin sampling when SOC5 gains priority (see Section 10.1.6).The ADC control logic will sample
ADCINA1 with the specified acquisition window width of 100 ns. Immediately after the acquisition is
complete, the ADC will begin converting the sampled voltage to a digital value. When the ADC conversion
is complete, the results will be available in the ADCRESULT5 register (see Section 10.2 for exact sample,
conversion, and result latch timings).
10.1.5.2 Oversampled Conversion from ePWM Trigger
To configure the ADC to oversample ADCINA1 4 times, we use the same configurations as the previous
example, but apply them to SOC5, SOC6, SOC7, and SOC8.
AdcaRegs.ADCSOC5CTL.bit.CHSEL =
AdcaRegs.ADCSOC5CTL.bit.ACQPS =
AdcaRegs.ADCSOC5CTL.bit.TRIGSEL
AdcaRegs.ADCSOC6CTL.bit.CHSEL =
AdcaRegs.ADCSOC6CTL.bit.ACQPS =
AdcaRegs.ADCSOC6CTL.bit.TRIGSEL
AdcaRegs.ADCSOC7CTL.bit.CHSEL =
AdcaRegs.ADCSOC7CTL.bit.ACQPS =
AdcaRegs.ADCSOC7CTL.bit.TRIGSEL
AdcaRegs.ADCSOC8CTL.bit.CHSEL =
AdcaRegs.ADCSOC8CTL.bit.ACQPS =
AdcaRegs.ADCSOC8CTL.bit.TRIGSEL

1;
19;
= 10;
1;
19;
= 10;
1;
19;
= 10;
1;
19;
= 10;

//SOC5
//SOC5
//SOC5
//SOC6
//SOC6
//SOC6
//SOC7
//SOC7
//SOC7
//SOC8
//SOC8
//SOC8

will
will
will
will
will
will
will
will
will
will
will
will

convert ADCINA1
use sample duration
begin conversion on
convert ADCINA1
use sample duration
begin conversion on
convert ADCINA1
use sample duration
begin conversion on
convert ADCINA1
use sample duration
begin conversion on

of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB

As configured, when ePWM3 matches its period and generates the SOCB signal, the ADC will begin
sampling channel ADCINA1 (SOC5) immediately if the ADC is idle. If the ADC is busy, ADCINA1 will
begin sampling when SOC5 gains priority (see ADC Conversion Priority). Once the conversion is complete
for SOC5, SOC6 will begin converting ADCINA1 and the results for SOC5 will be placed in the
ADCRESULT5 register. All four conversions will eventually be completed sequentially, with the results in
ADCRESULT5, ADCRESULT6, ADCRESULT7, and ADCRESULT8 for SOC5, SOC6, SOC7, and SOC8,
respectively.
NOTE: It is possible, but unlikely, that the ADC could begin converting SOC6, SOC7, or SOC8
before SOC5 depending on the position of the round-robin pointer when the ePWM trigger is
received. See ADC Conversion Priority to understand how the next SOC to be converted is
chosen.

1396

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

10.1.5.3 Multiple Conversions from CPU Timer Trigger
This example will show how to sample multiple signals with different acquisition window requirements.
CPU1 Timer 2 will be used to generate the trigger. To see how to configure the CPU timer, see the
System Control and Interrupts chapter.
A good first step when designing a sampling scheme with many signals is to list out the signals and their
required acquisition window. From this, calculate the necessary number of SYSCLK cycles for each
signal, then the ACQPS register setting. This is shown in Table 10-7, where a SYCLK of 200MHz is
assumed ( 5ns cycle time).
Table 10-7. Example Requirements for Multiple Signal Sampling
Signal Name

Acquisition Window
Requirement (ns)

Acquisition Window SYSCLK
Cycles

ACQPS Register Value

Signal 1

>120ns

120ns/5ns = 24

24 – 1 = 23

Signal 2

>444ns

444ns/5ns = 89 (round up)

89 – 1 = 88

Signal 3

>110ns

110ns/5ns = 22

22 – 1 = 21

Signal 4

>291ns

291ns/5ns = 59 (round up)

59 – 1 = 58

Next decide which ADC pins to connect to each signal. This will be highly dependent on application board
layout. Once the pins are selected, determining the value of CHSEL is straightforward (see Table 10-8).
Table 10-8. Example Connections for Multiple Signal Sampling
Signal Name

ADC PIN

CHSEL Register Value

Signal 1

ADCINA5

5

Signal 2

ADCINA0

0

Signal 3

ADCINA3

3

Signal 4

ADCINA2

2

With the information tabulated, it is easy to generate the SOC configurations:
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcaRegs.ADCSOC1CTL.bit.CHSEL =
AdcaRegs.ADCSOC1CTL.bit.ACQPS =
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL
AdcaRegs.ADCSOC2CTL.bit.CHSEL =
AdcaRegs.ADCSOC2CTL.bit.ACQPS =
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL
AdcaRegs.ADCSOC3CTL.bit.CHSEL =
AdcaRegs.ADCSOC3CTL.bit.ACQPS =
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL

5;
23;
= 3;
0;
88;
= 3;
3;
21;
= 3;
2;
58;
= 3;

//SOC0
//SOC0
//SOC0
//SOC1
//SOC1
//SOC1
//SOC2
//SOC2
//SOC2
//SOC3
//SOC3
//SOC3

will
will
will
will
will
will
will
will
will
will
will
will

convert ADCINA5
use sample duration
begin conversion on
convert ADCINA0
use sample duration
begin conversion on
convert ADCINA3
use sample duration
begin conversion on
convert ADCINA2
use sample duration
begin conversion on

of 24 SYSCLK cycles
CPU1 Timer 2
of 89 SYSCLK cycles
CPU1 Timer 2
of 22 SYSCLK cycles
CPU1 Timer 2
of 59 SYSCLK cycles
CPU1 Timer 2

As configured, when CPU1 Timer 2 generates an event, SOC0, SOC1, SOC2, and SOC3 will eventually
be sampled and converted, in that order. The conversion results for ACINA5 (Signal 1) will be in
ADCRESULT0. Similarly, The results for ADCINA0 (Signal 2), ADCINA3 (Signal 3), and ADCINA2 (Signal
4) will be in ADCRESULT1, ADCRESULT2, and ADCRESULT3, respectively.
NOTE: It is possible, but unlikely, that the ADC could begin converting SOC1, SOC2, or SOC3
before SOC0 depending on the position of the round-robin pointer when the CPU Timer
trigger is received. See ADC Conversion Priority to understand how the next SOC to be
converted is chosen.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1397

Analog-to-Digital Converter (ADC)

www.ti.com

10.1.5.4 Software Triggering of SOCs
At any point, whether or not the SOCs have been configured to accept a specific trigger, a software trigger
can set the SOCs to be converted. This is accomplished by writing bits in the ADCSOCFRC1 register.
Software triggering of the previous example without waiting for the CPU1 Timer 2 to generate the trigger
could be accomplished by the statement:
AdcaRegs.ADCSOCFRC1.all = 0x000F;

//set SOC flags for SOC0 to SOC3

10.1.6 ADC Conversion Priority
When multiple SOC flags are set at the same time, one of two forms of priority determines the order in
which they are converted. The default priority method is round robin. In this scheme, no SOC has an
inherent higher priority than another. Priority depends on the round robin pointer (RRPOINTER). The
RRPOINTER reflected in the ADCSOCPRIORITYCTL register points to the last SOC converted. The
highest priority SOC is given to the next value greater than the RRPOINTER value, wrapping around back
to SOC0 after SOC15. At reset the value is 16 since 0 indicates a conversion has already occurred. When
RRPOINTER equals 16 the highest priority is given to SOC0. The RRPOINTER is reset by a device reset,
when the ADCCTL1.RESET bit is set, or when the SOCPRICTL register is written.
An example of the round robin priority method is given in Figure 10-5 .

1398

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

Figure 10-5. Round Robin Priority Example
A After reset, SOC0 is highest priority SOC ;
SOC7 receives trigger ;
SOC7 configured channel is converted
immediately .

A
SOC
15

SOC
3

SOC
12

RRPOINTER
(default = 16)

SOC
5
SOC
10
SOC
9

SOC
1

SOC
14

SOC
15
SOC
2

SOC
13
RRPOINTER
(value = 7)

SOC
4

SOC
10

D
SOC
15

SOC
10

SOC
1

SOC
6

SOC
15

RRPOINTER
(value = 12)

SOC
4
SOC
5

SOC
11
SOC
10

SOC
8

SOC
0

SOC
7

SOC
1

SOC
14
SOC
3

SOC
6
SOC
8

SOC
5

SOC
9

SOC
13

SOC
4

SOC
11

SOC
2

SOC
9

RRPOINTER
(value = 7)

E

SOC
0

SOC
14

SOC
12

SOC
3

SOC
7

SOC
8

SOC
1
SOC
2

SOC
12

SOC
6
SOC
9

SOC
0

SOC
7

SOC
13

SOC
5

SOC
11

SOC
8

SOC
14
SOC
3

SOC
12

SOC
6

C

SOC
0

SOC
4

SOC
11

E RRPOINTER changes to point to SOC 2;
SOC3 is now highest priority SOC .

SOC
15

SOC
2

SOC
13

D RRPOINTER changes to point to SOC 12;
SOC2 configured channel is now converted .

B

SOC
1

SOC
14

B RRPOINTER changes to point to SOC 7;
SOC8 is now highest priority SOC .
C SOC2 & SOC12 triggers rcvd . simultaneously ;
SOC12 is first on round robin wheel ;
SOC12 configured channel is converted while
SOC2 stays pending .

SOC
0

SOC
7

SOC
2

SOC
13

SOC
3

SOC
12

RRPOINTER
(value = 2)

SOC
4
SOC
5

SOC
11
SOC
10

SOC
6
SOC
9

SOC
8

SOC
7

The SOCPRIORITY field in the ADCSOCPRIORITYCTL register can be used to assign high priority from
a single to all of the SOCs. When configured as high priority, an SOC will interrupt the round robin wheel
after any current conversion completes and insert itself in as the next conversion. After its conversion
completes, the round robin wheel will continue where it was interrupted. If two high priority SOC’s are
triggered at the same time, the SOC with the lower number will take precedence.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1399

Analog-to-Digital Converter (ADC)

www.ti.com

High priority mode is assigned first to SOC0, then in increasing numerical order. The value written in the
SOCPRIORITY field defines the first SOC that is not high priority. In other words, if a value of 4 is written
into SOCPRIORITY, then SOC0, SOC1, SOC2, and SOC3 are defined as high priority, with SOC0 the
highest.
An example using high priority SOC’s is given in Figure 10-6 .
Figure 10-6. High Priority Example

A

Example when SOCPRIORITY = 4
A

B

C

D

E

After reset, SOC4 is 1 st on round robin wheel ;
SOC7 receives trigger ;
SOC7 configured channel is converted immediately .

High Priority
SOC
0

RRPOINTER changes to point to SOC 7;
SOC8 is now 1 st on round robin wheel .

SOC
1

SOC2 & SOC12 triggers rcvd . simultaneously ;
SOC2 interrupts round robin wheel and SOC 2 configured
channel is converted while SOC 12 stays pending .

SOC
2
SOC
3

High Priority
SOC
0
SOC
1
SOC
2
SOC
3

SOC
4

SOC
13

RRPOINTER
(default = 16)

SOC
8

SOC
13

RRPOINTER
(value = 7)

SOC
1
SOC
2
SOC
3

SOC
1
SOC
2

SOC
8

SOC
10

D

SOC
4

SOC
15

High Priority

SOC
0

SOC
7

SOC
12

SOC
12

SOC
8

Analog-to-Digital Converter (ADC)

SOC
0
SOC
1
SOC
2
SOC
3

SOC
5

RRPOINTER
(value = 7)

SOC
7

SOC
12

SOC
8

SOC
15

High Priority

SOC
7

RRPOINTER
(value = 7)

SOC
10

SOC
13

E
SOC
5

SOC
4

SOC
9

SOC
6

SOC
11

SOC
6

SOC
11

SOC
3

SOC
10

SOC
14

SOC
9

SOC
14

SOC
13

SOC
15

High Priority
SOC
6

SOC
11

SOC
0

C

SOC
14

SOC
7

SOC
12
SOC
11

SOC
5

SOC
5
SOC
6

RRPOINTER changes to point to SOC 12;
SOC13 is now 1st on round robin wheel .

SOC
15

SOC
4

SOC
14

RRPOINTER stays pointing to 7;
SOC12 configured channel is now converted .

B

1400

SOC
15

SOC
10

SOC
4

SOC
9

SOC
5

SOC
14

SOC
6

SOC
13

RRPOINTER
(value = 12)

SOC
7

SOC
12

SOC
9

SOC
8
SOC
11

SOC
10

SOC
9

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

10.1.7 Burst Mode
Burst mode allows a single trigger to walk through the round-robin SOCs one or more at a time. Setting
the bit BURSTEN in the ADCBURSTCTL register configures the ADC wrapper for burst mode. This
causes the TRIGSEL field to be ignored, but only for SOCs that are configured for round-robin operation
(not high priority). Instead of the TRIGSEL field, all round-robin SOCs are triggered based on the
BURSTTRIG field in the ADCBURSTCTL register. Upon reception of the burst trigger, the ADC wrapper
will not set all round-robin SOCs to be converted, but only (ADCBURSTCTL.BURSTSIZE + 1) SOCs. The
first SOC to be set will be that with the highest priority based on the round-robin pointer, and subsequent
SOCs will be set until BURSTSIZE SOCs have been set.
NOTE: When configuring the ADC for burst mode, the user is responsible for ensuring that each
burst of conversions is allowed to complete before the next burst trigger is received.

10.1.7.1 Burst Mode Example
Burst mode can be used to sample a different set of signals on every other trigger. In the following
example, ADCIN7 and ADCIN5 are converted on the first trigger from CPU1 Timer 2 and every other
trigger thereafter. ADCIN2 and ACIN3 are converted on the second trigger from CPU1 Timer 2 and every
other trigger thereafter. All signals are converted with 20 SYSCLK cycle wide acquisition windows, but
different durations could be configured for each SOC as desired.
AdcaRegs.BURSTCTL.BURSTEN = 1;
AdcaRegs.BURSTCTL.BURSTTRIG = 3;
AdcaRegs.BURSTCTL.BURSTSIZE = 1;

//Enable ADC burst mode
//CPU1 Timer 2 will trigger burst of conversions
//conversion bursts are 1 + 1 = 2 conversions long

AdcaRegs.SOCPRICTL.bit.SOCPRIORITY = 12;

//SOC0 to SOC11 are high priority

AdcaRegs.ADCSOC12CTL.bit.CHSEL
AdcaRegs.ADCSOC12CTL.bit.ACQPS
AdcaRegs.ADCSOC13CTL.bit.CHSEL
AdcaRegs.ADCSOC13CTL.bit.ACQPS
AdcaRegs.ADCSOC14CTL.bit.CHSEL
AdcaRegs.ADCSOC14CTL.bit.ACQPS
AdcaRegs.ADCSOC15CTL.bit.CHSEL
AdcaRegs.ADCSOC15CTL.bit.ACQPS

//SOC12
//SOC12
//SOC13
//SOC13
//SOC14
//SOC14
//SOC15
//SOC15

=
=
=
=
=
=
=
=

7;
19;
5;
19;
2;
19;
3;
19;

will
will
will
will
will
will
will
will

convert ADCINA7
use sample duration
convert ADCINA5
use sample duration
convert ADCINA2
use sample duration
convert ADCINA3
use sample duration

of 20 SYSCLK cycles
of 20 SYSCLK cycles
of 20 SYSCLK cycles
of 20 SYSCLK cycles

When the first CPU1 Timer 2 trigger is received, SOC12 and SOC13 will be converted immediately if the
ADC is idle. If the ADC is busy, SOC12 and SOC13 will be converted once their SOCs gain priority. The
results for SOC12 and SOC13 will be in ADCRESULT12 and ADCRESULT13, respectively. After SOC13
completes, the round robin pointer will give highest priority to SOC14. Because of this, when the next
CPU1 Timer 2 trigger is received, SOC14 and SOC15 will be set as pending and eventually be converted.
The results for SOC14 and SOC15 will be in ADCRESULT14 and ADCRESULT15, respectively.
Subsequent triggers will continue to toggle between converting SOC12 and SOC13, and converting
SOC14 and SOC15.
While the above example toggles between two sets of conversions, three or more different sets of
conversions could be achieved using a similar approach.
10.1.7.2 Burst Mode Priority Example
An example of priority resolution using burst mode and high-priority SOCs is presented in Figure 10-7.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1401

Analog-to-Digital Converter (ADC)

www.ti.com

Figure 10-7. Burst Priority Example
A

Example when SOCPRIORITY = 4, BURSTEN = 1, and
BURSTSIZE = 1

A

B

RRPOINTER changes to point to SOC5;
SOC6 is now 1st on round robin wheel.

SOC
1

C

BURSTTRIG & SOC1 triggers rcvd. simultaneously;
SOC1, SOC6, and SOC7 are set;
SOC1 interrupts round robin wheel and SOC1 configured
channel is converted while SOC6 and SOC7 stay pending.

SOC
2

D

RRPOINTER stays pointing to 5;
SOC6/SOC7 configured channels are now converted.

E

RRPOINTER changes to point to SOC7;
SOC8 is now 1st on round robin wheel, waiting for BURSTTRIG.

SOC
15

High
Priority
SOC
0
SOC
1
SOC
2
SOC
3

SOC
1
SOC
2
SOC
3

SOC
5

RRPOINTER
(value = 5)

SOC
1
SOC
2

SOC
8

SOC
15

SOC
5

RRPOINTER
(value = 5)

SOC
8

Analog-to-Digital Converter (ADC)

SOC
0
SOC
1
SOC
2
SOC
3

SOC
10

SOC
4

SOC
9

SOC
5

SOC
14

SOC
6

RRPOINTER
(value = 5)

SOC
13

SOC
7

SOC
12

SOC
8

SOC
15

High
Priority

SOC
7

SOC
12

SOC
10

SOC
15

E

SOC
4

SOC
7

SOC
8

SOC
11

SOC
6

SOC
11

RRPOINTER
(default = 16)

SOC
12

SOC
9

SOC
10

SOC
14

SOC
13

SOC
3

SOC
5
SOC
6

SOC
13

High
Priority
SOC
0

SOC
4

SOC
14

SOC
11

SOC
7

SOC
12

D

SOC
0

SOC
3

SOC
6

SOC
13

High
Priority

SOC
0

C

SOC
4

SOC
14

SOC
11

1402

High
Priority

After reset, SOC4 is 1st on round robin wheel;
BURSTTRIG trigger is received;
SOC4 & SOC5 are set and configured channels converted
immediately.

B

SOC
15

SOC
10

SOC
4

SOC
9

SOC
5

SOC
14

SOC
6

RRPOINTER
(value = 7)

SOC
13

SOC
7

SOC
12

SOC
9

SOC
8
SOC
11

SOC
10

SOC
9

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

10.1.8 EOC and Interrupt Operation
Each SOC has a corresponding end-of-conversion (EOC) signal. This EOC signal can be used to trigger
an ADC interrupt. The ADC can be configured to generate the EOC pulse at either the end of the
acquisition window or at the end of the voltage conversion. This is configured using the bit INTPULSEPOS
in the ADCCTL1 register. See Section 10.2, for exact EOC pulse location.
Each ADC module has 4 configurable ADC interrupts. These interrupts can be triggered by any of the 16
EOC signals. The flag bit for each ADCINT can be read directly or the interrupt can be passed on to the
PIE.
Figure 10-8 shows a block diagram of the ADC interrupt structure.
Figure 10-8. ADC EOC Interrupts
INT4
INT3
INT2
INT1

INTSEL1N2.INT1SEL
ADCINT4 to PIE
INTSEL1N2.INT1E
EOC

0
1
2

EOC15:EOC0

15

INTSEL1N2.INT1CONT

ADCINT2 to PIE

1
0

ADCINT3 to PIE

Set
Latch

1
ADCINT1 to PIE
0

Clear
INTOVF

ADCINTFLGCLR.ADCINT1

ADC Sample
Generation
Logic

ADCINTFLG.ADCINT1

10.1.9 Post-Processing Blocks
Each ADC module contains four post-processing blocks (PPB). These blocks can be associated with any
of the 16 RESULT registers using the ADCPPBxCONFIG.CONFIG bit field. Each PPB can simultaneously
remove an offset associated with the ADCIN channel, subtract out a reference value, flag a zero-crossing
point, and flag a high or low compare limit. Furthermore, the zero-crossing and compare flags can trip a
PWM and/or generate an interrupt. A PPB is also capable of recording the delay between when the SOC
associated with the PPB is triggered and when it actually begins to be sampled. Figure 10-9 presents the
structure of each PPB. Subsequent sections explain the use of each submodule.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1403

Analog-to-Digital Converter (ADC)

www.ti.com

Figure 10-9. ADC PPB Block Diagram
ADC Post Processing Block

ADCEVTSEL.PPBxTRIPLO
ADCEVTSEL.PPBxTRIPHI
Delay Capture
ADCEVTSEL.PPBxZERO

SOC Control Signals
ADCEVTSTAT.PPBxTRIPLO

SOC
Start
Detect

SOC
Trigger
Detect

EVENTx

ADCEVTSTAT.PPBxTRIPHI
Latch

Latch
-

REQSTAMPx

DLYSTAMPx

ADCEVTSTAT.PPBxZERO

+
FREECOUNT
Zero Crossing Detection Logic

ADCPPBxOFFCAL
ADC Output

Detects when
ADCPPBxRESULT
changes sign

Offset Correction
with Saturation

INTx

-

+

Pulse

Threshold Compare
Saturate

ADCRESULTy
ADCPPBxTRIPHI

+

Pulse

-

Error/Bipolar Calculation
ADCPPBxOFFREF

-

+

Twos
Comp
Inv

+
ADCPPBxRESULT
ADCPPBxTRIPLO

-

Pulse

Enable
ADCPPBxCONFIG.TWOSCOMPEN

ADCEVTINTSEL.PPBxZERO
ADCEVTINTSEL.PPBxTRIPHI

ADCEVTINTSEL.PPBxTRIPLO

10.1.9.1 PPB Offset Correction
In many applications, external sensors and signal sources produce an offset. A global trimming of the
ADC offset is not enough to compensate for these offsets, which vary from channel to channel. The postprocessing block can remove these offsets with zero overhead, saving numerous cycles in tight control
loops.
Offset correction is accomplished by first pointing the ADCPPBxCONFIG.CONFIG to the desired SOC,
then writing an offset correction value to the ADCPPBxOFFCAL.OFFCAL register. The post-processing
block will automatically add or subtract the value in the OFFCAL register from the raw conversion result
and store it in the ADCRESULT register. This addition/subtraction will saturate at 0 on the low end and
either 4095 or 65535 on the high end for 12-bit or 16-bit mode, respectively.
NOTES:
• Writing a 0 to the OFFCAL register effectively disables the offset correction feature, passing the raw
result unchanged to the ADCRESULT register.
• It is possible to point multiple PPBs to the same SOC. In this case, the OFFCAL value that will actually
be applied will be that of the PPB with the highest number.
• In particular, care needs to be taken when using the PPB on SOC0, as all the PPB point to this SOC
by default. This may cause unintentional overwriting of offset correction of a lower numbered PPB by a
higher numbered PPB.
10.1.9.2 PPB Error Calculation
In many applications, an error from a setpoint or expected value must be computed from the digital output
of an ADC conversion. In other cases, a bipolar signal is necessary or convenient for control calculations.
The PPB can perform these function automatically, reducing the sample to output latency and reducing
software overhead.

1404

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

Error calculation is accomplished by first pointing the ADCPPBxCONFIG.CONFIG to the desired SOC,
then writing a value to the ADCPPBxOFFCAL.OFFREF register. The post-processing block will
automatically subtract the value in the OFFREF register from the ADCRESULT value and store it in the
ADCPPBxRESULT register. This subtraction will produce a sign-extended 32-bit result. It is also possible
to selectively invert the calculated value before storing in the ADCPPBxRESULT register by setting the
TWOSCOMPEN bit in the ADCPPBxCONFIG register.
NOTES:
• In 12-bit mode, do not write a value larger than 12 bits to the OFFREF register.
• Since the PPBxRESULT register is unique for each PPB, it is possible to point multiple PPBs to the
same SOC and get different results for each PPB.
• Writing a 0 to the OFFREF register effectively disables the error calculation feature, passing the
ADCRESULT value unchanged to the ADCPPBxRESULT register.
10.1.9.3 PPB Limit Detection and Zero-Crossing Detection
Many applications perform a limit check against the ADC conversion results. The PPB can automatically
perform a check against a high and low limit or whenever ADCPPBxRESULT changes sign. Based on
these comparisons, it can generate a trip to the PWM and/or an interrupt automatically, lowering the
sample to ePWM latency and reducing software overhead. This functionality also enables safety
conscious applications to trip the ePWM based on an out-of-range ADC conversion without any CPU
intervention.
To enable this functionality, first point the ADCPPBxCONFIG.CONFIG to the desired SOC, then write a
value to one or both of the registers ADCPPBxTRIPHI.LIMITHI and ADCPPBxTRIPLO.LIMITLO
(zerocrossing detection does not require further configuration). Whenever these limits are exceeded, the
PPBxTRIPHI bit or PPBxTRIPLO bit will be set in the ADCEVTSTAT register. Note that the PPBxZERO
bit in the ADCEVTSTAT register is gated by EOC and not by the sign change in the ADCPPBxRESULT
register. The ADCEVTCLR register has corresponding bits to clear these event flags. The ADCEVTSEL
register has corresponding bits which allow the events to propagate through to the PWM. The
ADCINTSEL register has corresponding bits which allow the events to propagate through to the PIE.
One PIE interrupt is shared between all the PPBs for a given ADC module as shown in Figure 10-10.
Figure 10-10. ADC PPB Interrupt Event
Post Processing Block1
EVENTx

ADCEVT1

INTx

Post Processing Block2
EVENTx

ADCEVT2

INTx
ADCEVTINT
Post Processing Block3
EVENTx

ADCEVT3

INTx

Post Processing Block4
EVENTx

ADCEVT4

INTx

NOTES:
• Zero-crossing and limit compare reference the ADCPPBxRESULT register. This will include any
correction applied by the OFFCAL and OFFREF registers. TRIPHI and TRIPLO do NOT perform a
signed comparison. It is recommended to leave OFFREF as 0 when using limit compare functionality.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1405

Analog-to-Digital Converter (ADC)

•

•

www.ti.com

If different actions need to be taken for different PPB events from the same ADC module, then the
ADCEVTINT ISR will have to read the PPB event flags in the ADCEVTSTAT register to determine
which event caused the interrupt.
If different ePWM trips need to be generated separately for high compare, low compare, and/or zerocrossing, this can be achieved by pointing multiple PPBs to the same SOC.

10.1.9.4 PPB Sample Delay Capture
When multiple control loops are running asynchronously on the same ADC, there is a chance that an ADC
request from two or more loops will collide, causing one of the samples to be delayed. This shows up as a
measurement error in the system. By knowing when this delay occurs and the amount of delay that has
occurred software can employ extrapolation techniques to reduce the error.
To this effect, each PPB has the field DLYSTAMP in the ADCPPBxSTAMP register. This field will contain
the number of SYSCLK cycles between when the associate SOC was triggered and when it began
converting.
This is achieved by having a global 12-bit free running counter based off of SYSCLK, which is in the field
FREECOUNT in the ADCCOUNTER register. When the trigger for the associated SOC arrives, the value
of this counter is loaded into the bit field ADCPPBxTRIPLO.REQSTAMP. When the actual sample window
for that SOC begins, the value in REQSTAMP is subtracted from the current FREECOUNT value and
stored in DLYSTAMP.
NOTE: If more than 4096 SYSCLK cycles elapse between the SOC trigger and the actual start of
the SOC acquisition, the FREECOUNT register may overflow more than once, leading to
incorrect DLYSTAMP value. Be cautious when using very slow conversions to prevent this
from happening.

NOTE: The sample delay capture will not function if the associated SOC is triggered via software. It
will, however, correctly record the delay if the software triggering of a different SOC causes
the SOC associated with the PPB to be delayed

10.1.10 Opens/Shorts Detection Circuit (OSDETECT)
The opens/shorts detection circuit (OSDETECT) can be used to detect pin faults in the system. The circuit
connects to the ADC input after the channel select multiplexer but before the S+H circuit as shown in
Figure 10-11.
Figure 10-11. Opens/Shorts Detection Circuit
CHSEL

Opens/Shorts Detection Circuit
VDDA

ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN014
ADCIN15

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

S2

Analog-to-Digital Converter (ADC)

S1

5 kW
To S+H
7 kW

S3

VDDA

1406

VSSA

S4

VSSA

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

www.ti.com

The circuit can be operated by writing a value to the DETECTCFG field in the ADCOSDETECT register.
This will cause the circuit to source a voltage onto the input during the S+H phase of any conversion. The
voltage and drive strength of the OSDETECT circuit for different DETECTCFG settings is given in
Table 10-9.
Table 10-9. DETECTCFG Settings
ADCOSDETECT.DETEC
TCFG

Source Voltage

S4

S3

S2

S1

Drive Impedance

0

Off

Open

Open

Open

Open

Open

1

Zero Scale

Closed

Open

Open

Closed

5K || 7K

2

Full Scale

Open

Closed

Closed

Open

5K || 7K

3

5/12 VDDA

Open

Closed

Open

Closed

5K || 7K

4

7/12 VDDA

Closed

Open

Closed

Open

5K || 7K

5

Zero Scale

Open

Open

Open

Closed

5K

6

Full Scale

Open

Open

Closed

Open

5K

7

Zero Scale

Closed

Open

Open

Open

7K

10.1.10.1 Detecting an Open Input Pin
By cycling through the various OSDETECT settings, the input signal will be pulled towards the sourced
voltages. An input with good drive strength (pin not open) will be minimally affected. However, if the pin is
open, the sampled voltages will be close to the source voltages specified in Section 10.1.11.
10.1.10.2 Detecting a Shorted Input Pin
By cycling through the various OSDETECT settings, the input signal will be pulled towards the sourced
voltages. An input with finite drive strength (pin not shorted) will be pulled toward each sourced voltage.
However, if the pin is shorted, the signal will remain at the same voltage.

10.1.11 Power-Up Sequence
Upon device power-up or system level reset, the ADC will be powered down and disabled. When
powering up the ADC, use the following sequence:
1. Set the bit to enable the desired ADC clock in the PCLKCR13 register.
2. Set the desired ADC clock divider in the PRESCALE field of ADCCTL2.
3. Power up the ADC by setting the ADCPWDNZ bit in ADCCTL1.
4. Allow a delay before sampling. See the data manual for the necessary time.
If multiple ADCs are powered up simultaneously, steps 1 and step 3 can each be done for all ADCs in one
write instruction. Also, only one delay is necessary as long as it occurs after all the ADCs have begun
powering up.

10.1.12 ADC Calibration
During the fabrication and test process, Texas Instruments calibrates the gain, offset, and linearity of the
ADCs and the offset of the buffered DACs. These trim settings are embedded into TI reserved OTP
memory as part of C-callable functions.
• The Device_cal() function copies the trim values for ADC gain and DAC offset from OTP memory to
their respective trim registers.
• The CalAdcXINL() functions copy the trim values for linearity from OTP memory to the respective trim
registers.
• A different offset trim is required for each possible combination of resolution and signalmode. The
GetAdcOffsetTrimOTP(Uint16) function takes an input value corresponding to the ADC, resolution, and
signal mode and returns the corresponding offset trim value from OTP memory, which the user then
moves into the ADC offset trim register.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1407

ADC Timings

www.ti.com

Until the appropriate factory trim is loaded, the ADC (and other modules) will not be guaranteed to operate
within datasheet specifications. Similarly, if trim values other than the factory settings are placed into the
trim registers, the ADC (and other modules) will not be guaranteed to operate within datasheet
specifications.
The boot ROM will call the calibration functions, so trim values should be initially populated without user
intervention. However, if the trims are cleared due to a module reset or modified for some other reason,
then the user can call the calibration functions (defined in the headerfiles).
10.1.12.1 ADC Zero Offset Calibration
Zero offset error is defined as the difference from 0 that occurs when converting a voltage at VREFLO
(single-ended operation) or the difference from (maximum code/2) when converting ADCINxP = ADCINxN
(differential mode). The zero offset error can be positive or negative. To correct this error, an adjustment
of equal magnitude and opposite polarity is written into the ADCOFFTRIM register. The value contained in
this register will be applied before the results are available in the ADC result registers. This operation is
fully contained within the ADC core, so the timing of the results will not be affected and the full dynamic
range of the ADC will be maintained for any trim value.
Using the GetAdcOffsetTrimOTP(Uint16) function, the ADCOFFTRIM register can be loaded with the
factory calibrated offset error correction. The user can modify the ADCOFFTRIM register to compensate
for additional offset error induced by the application environment if desired, but this is not typically
necessary to achieve datasheet specified performance.
NOTE: Regardless of the converter resolution, the size of each ADCOFFTRIM step is (VREFHIVREFLO)/65536.

Use the following procedure to re-calibrate the ADC offset in 12-bit, single-ended mode:
1. Set ADCOFFTRIM to +112 steps (0x70). This adds an artificial offset to account for negative offset that
may reside in the ADC core.
2. Perform some multiple of 16 conversions on VREFLO (internal connection), accumulating the results
(for example, 32*16 conversions = 512 conversions).
3. Divide the accumulated result by the multiple of 16 (for example, for 512 conversions, divide by 32).
4. Set ADCOFFTRIM to 112 – result from step 3.
Use the following procedure to re-calibrate the ADC offset in 16-bit, differential mode:
1. Set ADCOFFTRIM to no adjustment (0x00).
2. Short ADCINxP and ADCINyN together (external connection) and accumulate some multiple of 16
conversions (e.g. 32*16 conversions = 512 conversions).
3. Divide the accumulated result by the number of conversions (for example, for 512 conversions, divide
by 512).
4. Set ADCOFFTRIM to 0 – result from step 3).

10.2 ADC Timings
The process of converting an analog voltage to a digital value is broken down into an S+H phase and a
conversion phase. The ADC sample and hold circuits (S+H) are clocked by SYSCLK while the ADC
conversion process is clocked by ADCCLK. ADCCLK is generated by dividing down SYSCLK based on
the PRESCALE field in the ADCCTL2 register.
The S+H duration is the value of the ACQPS field of the SOC being converted, plus one, times the
SYSCLK period. The user must ensure that this duration exceeds both 1 ADCCLK period and the
minimum S+H duration specified in the datasheet. The conversion time is approximately 10.5 ADCCLK
cycles in 12-bit mode and 29.5 ADCCLK cycles in 16-bit mode. The exact conversion time is always a
whole number of SYSCLK cycles. See the timing diagrams and tables in Section 10.2.1 for exact timings.

10.2.1 ADC Timing Diagrams
The following diagrams show the ADC conversion timings for two SOCs given the following assumptions:
1408

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ADC Timings

www.ti.com

•
•
•
•

SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE
module).

The following parameters are identified in the timing diagrams:
• The parameter tSH is the duration of the S+H window. At the end of this window, the value on the S+H
capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS +
1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH will not necessarily be
the same for different SOCs.
• The parameter tLAT is the time from the end of the S+H window until the ADC conversion results latch
in the ADCRESULTx register. If the ADCRESULTx register is read before this time, the previous
conversion results will be returned.
• The parameter tEOC is the time from the end of the S+H window until the next ADC conversion S+H
window can begin. In 16-bit mode, this will coincide with the latching of the conversion results, while in
12-bit mode, the subsequent sample can start before the conversion results are latched.
• The parameter tINT is the time from the end of the S+H window until an ADCINT flag is set (if
configured). If the INTPULSEPOS bit in the ADCCTL1 register is set, this will coincide with the
conversion results being latched into the result register. If the bit is cleared, this will coincide with the
end of the S+H window.
Figure 10-12. ADC Timings for 12-bit Mode in Early Interrupt Mode
Sample n

Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1

ADC S+H

SOC0

SOC1

SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0

(old data)

ADCRESULT1

(old data)

Sample n

Sample n+1

ADCINTFLG.ADCINTx
tSH

tLAT
tEOC
tINT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1409

ADC Timings

www.ti.com

Figure 10-13. ADC Timings for 12-bit Mode in Late Interrupt Mode
Sample n

Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1

ADC S+H

SOC0

SOC1

SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0

(old data)

ADCRESULT1

(old data)

Sample n

Sample n+1

ADCINTFLG.ADCINTx
tSH

tLAT
tEOC
tINT

1410

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

ADC Timings

www.ti.com

Figure 10-14. ADC Timings for 16-bit Mode in Early Interrupt Mode
Sample n

Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1

ADC S+H

SOC0

SOC1

SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0

(old data)

ADCRESULT1

(old data)

Sample n

Sample n+1

ADCINTFLG.ADCINTx
tSH

tLAT
tEOC
tINT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1411

ADC Timings

www.ti.com

Figure 10-15. ADC Timings for 16-bit Mode in Late Interrupt Mode (SYSCLK Cycles)
Sample n

Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1

ADC S+H

SOC0

SOC1

SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0

(old data)

ADCRESULT1

(old data)

Sample n

Sample n+1

ADCINTFLG.ADCINTx
tSH

tLAT
tEOC
tINT

Table 10-10. ADC Timings in 12-bit Mode (SYSCLK Cycles)

1412

ADCCTL2.
PRESCALE

Prescale Ratio

tEOC

tLAT

tINT
(Early)

tINT
(Late)

0

1

11

12

0

12

2

2

21

22

0

22

3

2.5

26

27

0

27

4

3

31

33

0

33

5

3.5

36

38

0

38

6

4

41

43

0

43

7

4.5

46

48

0

48

8

5

51

54

0

54

9

5.5

56

59

0

59

10

6

61

64

0

64

11

6.5

66

69

0

69

12

7

71

75

0

75

13

7.5

76

80

0

80

14

8

81

85

0

85

15

8.5

86

90

0

90

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Additional Information

www.ti.com

Table 10-11. ADC Timings in 16-bit Mode
ADCCTL2.
PRESCALE

Prescale Ratio

tEOC

tLAT

tINT
(Early)

tINT
(Late)

0

1

31

31

0

31

2

2

60

60

0

60

3

2.5

75

75

0

75

4

3

90

90

0

90

5

3.5

104

104

0

104

6

4

119

119

0

119

7

4.5

134

134

0

134

8

5

149

149

0

149

9

5.5

163

163

0

163

10

6

178

178

0

178

11

6.5

193

193

0

193

12

7

208

208

0

208

13

7.5

222

222

0

222

14

8

237

237

0

237

15

8.5

252

252

0

252

10.3 Additional Information
The following sections contain additional practical information.

10.3.1 Ensuring Synchronous Operation
For best performance, all ADCs on the device should be operated synchronously. The device datasheet
specifies the performance in both synchronous and asynchronous mode for those parameters which differ
between the modes of operation.
To ensure synchronous operation, all ADCs on the device should operate in lockstep. This is
accomplished by writing configurations to all ADCs that cause the sampling and conversion phases of all
ADCs to be exactly aligned. The easiest way to accomplish this is to write identical values to the SOC
configurations for each ADC for trigger select and ACQPS (S+H duration).
10.3.1.1 Basic Synchronous Operation
The below example configures two SOCs each on ADCA and ADCB with identical trigger select and
ACQPS values. This will result in synchronous operation between ADCA and ADCB. For devices with
more than two ADCs, the same principles can be used to synchronize all the ADCs.
Example 1: Basic Synchronous Operation
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL

4; //SOC0 will convert ADCINA4
19; //SOC0 will use sample duration of 20 SYSCLK cycles
= 10; //SOC0 will begin conversion on ePWM3 SOCB
0; //SOC0 will convert ADCINB0
19; //SOC0 will use sample duration of 20 SYSCLK cycles
= 10; //SOC0 will begin conversion on ePWM3 SOCB

AdcaRegs.ADCSOC1CTL.bit.CHSEL =
AdcaRegs.ADCSOC1CTL.bit.ACQPS =
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL
AdcbRegs.ADCSOC1CTL.bit.CHSEL =
AdcbRegs.ADCSOC1CTL.bit.ACQPS =
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL

4; //SOC1 will convert ADCINA4
30; //SOC1 will use sample duration of 31 SYSCLK cycles
= 10; //SOC1 will begin conversion on ePWM3 SOCB
1; //SOC1 will convert ADCINB1
30; //SOC1 will use sample duration of 31 SYSCLK cycles
= 10; //SOC1 will begin conversion on ePWM3 SOCB

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1413

Additional Information

www.ti.com

Figure 10-16. Example: Basic Synchronous Operation
ePWM3B
Trigger

ADC A

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

ADC B

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

Several things should be noted from Example 1. First, while the ACQPS values must be the same for
SOCs with the same number, different ACQPS values can be used for SOCs with different numbers.
Because of this, synchronous operation does not require a single global S+H time, but instead only
channels sampled simultaneously require identical S+H durations. Another important point from this
example is that any channel select value can be used for any SOC. Finally, this example assumes roundrobin operation. If high priority SOCs are to be used, the priority must be configured the same on all
ADCs.
10.3.1.2 Synchronous Operation with Multiple Trigger Sources
As long as each set of SOCs has identical trigger select and ACQPS settings, multiple trigger sources can
be used while still achieving synchronous operation.
The below example demonstrates synchronous operation between ADCA and ADCB while using 3 SOCs
and 2 trigger sources. Figure 10-17 demonstrates that any combination of relative trigger timings still
results in synchronous operation.
Example: Synchronous Operation with Multiple Trigger Sources

1414

AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL

4; //SOC0 will convert ADCINA4
19; //SOC0 will use sample duration of 20 SYSCLK cycles
= 10; //SOC0 will begin conversion on ePWM3 SOCB
0; //SOC0 will convert ADCINB0
19; //SOC0 will use sample duration of 20 SYSCLK cycles
= 10; //SOC0 will begin conversion on ePWM3 SOCB

AdcaRegs.ADCSOC1CTL.bit.CHSEL =
AdcaRegs.ADCSOC1CTL.bit.ACQPS =
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL
AdcbRegs.ADCSOC1CTL.bit.CHSEL =
AdcbRegs.ADCSOC1CTL.bit.ACQPS =
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL

4; //SOC1 will convert ADCINA4
30; //SOC1 will use sample duration of 31 SYSCLK cycles
= 10; //SOC1 will begin conversion on ePWM3 SOCB
1; //SOC1 will convert ADCINB1
30; //SOC1 will use sample duration of 31 SYSCLK cycles
= 10; //SOC1 will begin conversion on ePWM3 SOCB

AdcaRegs.ADCSOC2CTL.bit.CHSEL =
AdcaRegs.ADCSOC2CTL.bit.ACQPS =
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL
AdcbRegs.ADCSOC2CTL.bit.CHSEL =
AdcbRegs.ADCSOC2CTL.bit.ACQPS =
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL

0; //SOC2 will convert ADCINA0
19; //SOC2 will use sample duration of 31
= 2; //SOC2 will begin conversion on CPU1
2; //SOC2 will convert ADCINB2
19; //SOC2 will use sample duration of 31
= 2; //SOC2 will begin conversion on CPU1

Analog-to-Digital Converter (ADC)

SYSCLK cycles
Timer1
SYSCLK cycles
Timer1

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Additional Information

www.ti.com

Figure 10-17. Example: Synchronous Operation with Multiple Trigger Sources
ePWM3B
Trigger

CPU1 Timer 1
Trigger

ADC A

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

SOC2 - S+H

SOC2 - Conversion

ADC B

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

SOC2 - S+H

SOC2 - Conversion

ePWM3B
Trigger

CPU1 Timer 1
Trigger

ADC A

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

SOC2 - S+H

SOC2 - Conversion

ADC B

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

SOC2 - S+H

SOC2 - Conversion

CPU1 Timer 1
Trigger

ePWM3B
Trigger

ADC A

SOC2 - S+H

SOC2 - Conversion

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

ADC B

SOC2 - S+H

SOC2 - Conversion

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

Note that any trigger source that can be selected in the TRIGSEL field can be used except for software
triggering. There is no way to issue the software triggers for all ADCs simultaneously, so it will likely result
in asynchronous operation. ADCINT1 or ADCINT2 can also be used as a trigger as long as the
ADCINTSOCSEL1 and ADCINTSOCSEL2 registers are configured identically for all ADCs and software
triggering is not used to start the chain of conversions.
10.3.1.3 Synchronous Operation with Uneven SOC Numbers
If only one trigger source is used, one ADC can use more SOCs than the other ADCs while still operating
synchronously.
Example: Synchronous Operation With Uneven SOC Numbers
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL

4; //SOC0 will convert ADCINA4
19; //SOC0 will use sample duration of 20 SYSCLK cycles
= 10; //SOC0 will begin conversion on ePWM3 SOCB
0; //SOC0 will convert ADCINB0
19; //SOC0 will use sample duration of 20 SYSCLK cycles
= 10; //SOC0 will begin conversion on ePWM3 SOCB

AdcaRegs.ADCSOC1CTL.bit.CHSEL =
AdcaRegs.ADCSOC1CTL.bit.ACQPS =
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL
AdcbRegs.ADCSOC1CTL.bit.CHSEL =
AdcbRegs.ADCSOC1CTL.bit.ACQPS =
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL

4; //SOC1 will convert ADCINA4
30; //SOC1 will use sample duration of 31 SYSCLK cycles
= 10; //SOC1 will begin conversion on ePWM3 SOCB
1; //SOC1 will convert ADCINB1
30; //SOC1 will use sample duration of 31 SYSCLK cycles
= 10; //SOC1 will begin conversion on ePWM3 SOCB

AdcaRegs.ADCSOC2CTL.bit.CHSEL = 0; //SOC2 will convert ADCINA0
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 19; //SOC2 will use sample duration of 31 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 10; //SOC2 will begin conversion on ePWM3 SOCB

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1415

Additional Information

www.ti.com

Figure 10-18. Example: Synchronous Operation with Uneven SOC Numbers
ePWM3B
Trigger

ADC A

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

ADC B

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

SOC2 - S+H

SOC2 - Conversion

Note that if the trigger comes again before all SOCs have completed their conversions, ADCB will begin
converting immediately on SOC0 while ADCA will not start converting SOC0 again until SOC2 is
complete. This will result in asynchronous operation, so care must be taken to not overflow the trigger.
Figure 10-19. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow
ePWM3B
Trigger

ADC A

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

ADC B

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

SOC2 - S+H
SOC0 - S+H

SOC2 - Conversion
SOC0 - Conversion

SOC0 - S+H
SOC1 - S+H

...
SOC1 - Conversion

10.3.1.4 Synchronous Operation with Different Resolutions
Configuring different ADCs to use different resolutions will result in asynchronous operation. This will
occur because the conversion time for 12-bit mode and 16-bit mode are different. Synchronous operation
requires both the start and end of the conversion phase to be aligned, so even using the same S+H
window duration will not result in synchronous operation.
Example: Asynchronous Operation with Different Resolutions
//ADCA = 12-bit mode
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
//ADCB = 16-bit mode
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL

4; //SOC0 will convert ADCINA4
50; //SOC0 will use sample duration of 51 SYSCLK cycles
= 10; //SOC0 will begin conversion on ePWM3 SOCB
0; //SOC0 will convert ADCINB0/B1
50; //SOC0 will use sample duration of 51 SYSCLK cycles
= 10; //SOC0 will begin conversion on ePWM3 SOCB

Figure 10-20. Example: Asynchronous Operation with Different Resolutions
ePWM3B
Trigger
(12-bits)

ADC A

SOC0 - S+H

ADC B

SOC0 - S+H

SOC0 - Conversion
(16-bits)
SOC0 - Conversion

In order to achieve synchronous operation while using both 12-bit and 16-bit resolution, conversions must
be done in parallel at one resolution. Once conversions are complete at one resolution, the CPU must
switch the resolution on all ADCs and then cause another trigger (this trigger should not be a software
SOC force, as all ADCs can’t be started simultaneously via this method).

1416

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Additional Information

www.ti.com

Figure 10-21. Example: Synchronous Operation with Different Resolutions
Trigger 1

Trigger 2
(12-bit)

(16-bit)

ADC A

SOC0 - S+H

SOC0 - Conversion
(12-bit)

SOC1 - S+H

SOC1 - Conversion
(16-bit)

ADC B

SOC0 - S+H

SOC0 - Conversion

SOC1 - S+H

SOC1 - Conversion

(CPU changes
resolution on all ADCs)

10.3.1.5 Non-overlapping Conversions
If conversion timings can be guaranteed to not overlap by the user, then it is not necessary to configure all
SOCs identically on all ADCs to achieve performance equivalent to synchronous operation. For example,
if the two ADC triggers in a system come from two ePWM sources which are always 180 degrees out-ofphase, then SOC0 could be used for both ADCA and ADCB with different trigger sources and different
ACQPS values.
Example: Operation with Non-overlapping Conversions
//ePWM3 SOCA and SOCB are 180 degrees out of phase
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 4; //SOC0 will convert ADCINA4
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will use sample duration of 20 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert ADCINB0
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will use sample duration of 20 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 9; //SOC0 will begin conversion on ePWM3 SOCA

Figure 10-22. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions
ePWM3B
Trigger

ADC A
ADC B

SOC0 - S+H

ePWM3A
Trigger

ePWM3B
Trigger

SOC0 - Conversion

SOC0 - S+H
SOC0 - S+H

ePWM3A
Trigger

SOC0 - Conversion

SOC0 - Conversion

SOC0 - S+H

SOC0 - Conversion

10.3.2 Choosing an Acquisition Window Duration
For correct operation, the input signal to the ADC must be allowed adequate time to charge the sample
and hold capacitor, Ch. Typically, the S+H duration is chosen such that the sampling capacitor will be
charged to within ½ LSB or ¼ LSB of the final value, depending on tolerable settling error. A rough
approximation of the required sampling time can be determined using a first-order RC model with R = Rs
+ Ron and C = Ch. The RC time constant is then (Rs + Ron)∙(Ch). The required number of time constants
is:

æ settling accuracy (LSBs ) ö
t = -In ç
÷
2N
è
ø
For example, assuming desired accuracy is ¼ LSB, resolution is 12-bits, Rs = 250Ω, Ron = 300Ω, and Ch
= 14.5pF.
æ settling accuracy (LSBs ) ö
t = -In ç
÷T
2N
è
ø
æ 0.25 ö
t = -In ç
÷ (550kW 14.5 pf ) = 77 ns
è 212 ø

The sample and hold window duration for this ADC is
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1417

Additional Information

www.ti.com

1
TS+H = (ACQPS + 1)
SYSCLK
If SYSCLK = 200 MHz, then 1/SYSCLK = 5ns, and 1+ACQPS should therefore be chosen to be 16, giving
ACQPS = 15.
While this gives a rough estimate of the required acquisition window, a better method would be to setup a
circuit with the ADC input model, a model of the source impedance/capacitance, and any board parasitics
in SPICE (or similar software) and simulate to verify that the sampling capacitor settles to the desired
accuracy.
NOTE: The device datasheet will specify a minimum ADC S+H window duration. Do not use an
ACQPS value that gives a duration less than this specification.

10.3.3 Achieving Simultaneous Sampling
While the Type 4 ADC does not have dual S+H circuits, it is easy to achieve simultaneous sampling. This
is accomplished by setting the SOC triggers on two or more ADC modules to use the same trigger source.
The example below demonstrates x4 simultaneous sampling based on an ePWM3 event. ADCINA3,
ADCINB5, ADCINC5, and ADCIND2 are sampled. An acquisition window of 20 SYSCLK cycles is used,
but different durations are possible.
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL
AdccRegs.ADCSOC0CTL.bit.CHSEL =
AdccRegs.ADCSOC0CTL.bit.ACQPS =
AdccRegs.ADCSOC0CTL.bit.TRIGSEL
AdcdRegs.ADCSOC0CTL.bit.CHSEL =
AdcdRegs.ADCSOC0CTL.bit.ACQPS =
AdcdRegs.ADCSOC0CTL.bit.TRIGSEL
\

3;
19;
= 10;
5;
19;
= 10;
5;
19;
= 10;
2;
19;
= 10;

//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0

will
will
will
will
will
will
will
will
will
will
will
will

convert ADCINA3
use sample duration
begin conversion on
convert ADCINB5
use sample duration
begin conversion on
convert ADCINC5
use sample duration
begin conversion on
convert ADCIND2
use sample duration
begin conversion on

of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB

When the ePWM3 trigger is received, all four ADCs will begin converting in parallel immediately. All
results will be in the ADCRESULT0 register for each ADC. Note that this assumes that all ADCs are idle
when the trigger is received. If one or more ADCs is busy, the samples will not happen at exactly the
same time.

10.3.4 Designing an External Reference Circuit
Figure 10-23 shows the basic organization of the external voltage reference generation circuitry. A single
reference voltage generation should be shared by all ADC modules. This will minimize reference voltage
mismatch between ADC modules. The reference voltage should then be buffered by a precision op-amp
with good bandwidth and low output impedance before being driven into the reference pin. A capacitor
between the high and low reference pins should be placed on the PCB as close to the pins as practical to
help absorb high frequency currents. A series resistor (typically <1Ω ) in series with this capacitor may be
necessary to ensure op-amp
It is also possible to share two reference pins between one op-amp driver. This organization is shown in
Figure 10-24. This will give slightly reduced performance compared to the case where each reference pin
has a dedicated op-amp buffer, but it should still be possible to achieve all ADC specifications in the data
manual..

1418

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Additional Information

www.ti.com

Figure 10-23. ADC Reference System

Reference Generation

Type 4 ADC

Non-Inverting
Buffers

Voltage
Reference
REF3230
REF3225
REF3030
REF3025
REF5030
REF5025
(or similar)

VREFHIA
RA
OPA320
OPA350
(or similar)

CA
VREFLOA

VREFHIC
RC
OPA320
OPA350
(or similar)

CC
VREFLOC

VREFHIB
RB
OPA320
OPA350
(or similar)

CB
VREFLOB

VREFHID
RD
OPA320
OPA350
(or similar)

CD

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

VREFLOD

Analog-to-Digital Converter (ADC)

1419

Additional Information

www.ti.com

Figure 10-24. ADC Shared Reference System

Reference Generation

Type 4 ADC

Non-Inverting
Buffers

Voltage
Reference

VREFHIA
RA

REF3230
REF3225
REF3030
REF3025
REF5030
REF5025
(or similar)

OPA320
OPA350
(or similar)

CA
VREFLOA

VREFHIC
RC
CC
VREFLOC

VREFHIB
RB
OPA320
OPA350
(or similar)

CB
VREFLOB

VREFHID
RD
CD
VREFLOD

10.3.5 Internal Temperature Sensor
The internal temperature sensor measures the junction temperature of the device. The output of the
sensor can be sampled with the ADC through an internal connection. This can be enabled on channel
ADCIN13 on ADCA by setting the ENABLE bit in the TSNSCTL register.
To convert the temperature sensor reading into a temperature, pass the temperature sensor reading to the
GetTemperatureC() function in F2837xD_TempSensorConv.c
. Note that this function assumes that the temperature reading was taken with VREFHI = 2.5V. If a
different reference voltage is used, the sample should be scaled appropriately before passing it to the
function by using the below formula.
adjusted sensor reading = raw sensor reading * (VREFHI / 2.5V)
NOTE: To sample the temperature sensor, the ADC must be in single-ended 12-bit mode.
If the temperature sensor is sampled in 16-bit mode, the ADC will switch to 12-bit m ode to
perform the conversion. This could cause incorrect ADC results.

1420

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4 Registers
10.4.1 ADC Base Addresses
Table 10-12. ADC Base Address Table
Device Registers

Register Name

Start Address

End Address

AdcaResultRegs

ADC_RESULT_REGS

0x0000_0B00

0x0000_0B1F

AdcbResultRegs

ADC_RESULT_REGS

0x0000_0B20

0x0000_0B3F

AdccResultRegs

ADC_RESULT_REGS

0x0000_0B40

0x0000_0B5F

AdcdResultRegs

ADC_RESULT_REGS

0x0000_0B60

0x0000_0B7F

AdcaRegs

ADC_REGS

0x0000_7400

0x0000_747F

AdcbRegs

ADC_REGS

0x0000_7480

0x0000_74FF

AdccRegs

ADC_REGS

0x0000_7500

0x0000_757F

AdcdRegs

ADC_REGS

0x0000_7580

0x0000_75FF

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1421

Registers

www.ti.com

10.4.2 ADC_REGS Registers
Table 10-13 lists the memory-mapped registers for the ADC_REGS. All register offset addresses not listed
in Table 10-13 should be considered as reserved locations and the register contents should not be
modified.
Table 10-13. ADC_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

ADCCTL1

ADC Control 1 Register

EALLOW

Go

1h

ADCCTL2

ADC Control 2 Register

EALLOW

Go

2h

ADCBURSTCTL

ADC Burst Control Register

EALLOW

Go

3h

ADCINTFLG

ADC Interrupt Flag Register

Go

4h

ADCINTFLGCLR

ADC Interrupt Flag Clear Register

Go

5h

ADCINTOVF

ADC Interrupt Overflow Register

Go

6h

ADCINTOVFCLR

ADC Interrupt Overflow Clear Register

Go

7h

ADCINTSEL1N2

ADC Interrupt 1 and 2 Selection Register

EALLOW

Go

8h

ADCINTSEL3N4

ADC Interrupt 3 and 4 Selection Register

EALLOW

Go

9h

ADCSOCPRICTL

ADC SOC Priority Control Register

EALLOW

Go

Ah

ADCINTSOCSEL1

ADC Interrupt SOC Selection 1 Register

EALLOW

Go

Bh

ADCINTSOCSEL2

ADC Interrupt SOC Selection 2 Register

EALLOW

Go

Ch

ADCSOCFLG1

ADC SOC Flag 1 Register

Go

Dh

ADCSOCFRC1

ADC SOC Force 1 Register

Go

Eh

ADCSOCOVF1

ADC SOC Overflow 1 Register

Go

Fh

ADCSOCOVFCLR1

ADC SOC Overflow Clear 1 Register

10h

ADCSOC0CTL

ADC SOC0 Control Register

EALLOW

Go

12h

ADCSOC1CTL

ADC SOC1 Control Register

EALLOW

Go

14h

ADCSOC2CTL

ADC SOC2 Control Register

EALLOW

Go

16h

ADCSOC3CTL

ADC SOC3 Control Register

EALLOW

Go

Go

18h

ADCSOC4CTL

ADC SOC4 Control Register

EALLOW

Go

1Ah

ADCSOC5CTL

ADC SOC5 Control Register

EALLOW

Go

1Ch

ADCSOC6CTL

ADC SOC6 Control Register

EALLOW

Go

1Eh

ADCSOC7CTL

ADC SOC7 Control Register

EALLOW

Go

20h

ADCSOC8CTL

ADC SOC8 Control Register

EALLOW

Go

22h

ADCSOC9CTL

ADC SOC9 Control Register

EALLOW

Go

24h

ADCSOC10CTL

ADC SOC10 Control Register

EALLOW

Go

26h

ADCSOC11CTL

ADC SOC11 Control Register

EALLOW

Go

28h

ADCSOC12CTL

ADC SOC12 Control Register

EALLOW

Go

2Ah

ADCSOC13CTL

ADC SOC13 Control Register

EALLOW

Go

2Ch

ADCSOC14CTL

ADC SOC14 Control Register

EALLOW

Go

2Eh

ADCSOC15CTL

ADC SOC15 Control Register

EALLOW

Go

30h

ADCEVTSTAT

ADC Event Status Register

32h

ADCEVTCLR

ADC Event Clear Register

34h

ADCEVTSEL

ADC Event Selection Register

EALLOW

Go

36h

ADCEVTINTSEL

ADC Event Interrupt Selection Register

EALLOW

Go

39h

ADCCOUNTER

ADC Counter Register

3Ah

ADCREV

ADC Revision Register

3Bh

ADCOFFTRIM

ADC Offset Trim Register

EALLOW

Go

40h

ADCPPB1CONFIG

ADC PPB1 Config Register

EALLOW

Go

41h

ADCPPB1STAMP

ADC PPB1 Sample Delay Time Stamp Register

42h

ADCPPB1OFFCAL

ADC PPB1 Offset Calibration Register

43h

ADCPPB1OFFREF

ADC PPB1 Offset Reference Register

1422

Analog-to-Digital Converter (ADC)

Go
Go

Go
Go

Go
EALLOW

Go
Go

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-13. ADC_REGS Registers (continued)
Offset

Acronym

Register Name

Write Protection

44h

ADCPPB1TRIPHI

ADC PPB1 Trip High Register

EALLOW

Section
Go

46h

ADCPPB1TRIPLO

ADC PPB1 Trip Low/Trigger Time Stamp
Register

EALLOW

Go

48h

ADCPPB2CONFIG

ADC PPB2 Config Register

EALLOW

Go

49h

ADCPPB2STAMP

ADC PPB2 Sample Delay Time Stamp Register

4Ah

ADCPPB2OFFCAL

ADC PPB2 Offset Calibration Register

4Bh

ADCPPB2OFFREF

ADC PPB2 Offset Reference Register

4Ch

ADCPPB2TRIPHI

ADC PPB2 Trip High Register

EALLOW

Go

4Eh

ADCPPB2TRIPLO

ADC PPB2 Trip Low/Trigger Time Stamp
Register

EALLOW

Go

50h

ADCPPB3CONFIG

ADC PPB3 Config Register

EALLOW

Go

51h

ADCPPB3STAMP

ADC PPB3 Sample Delay Time Stamp Register

52h

ADCPPB3OFFCAL

ADC PPB3 Offset Calibration Register

53h

ADCPPB3OFFREF

ADC PPB3 Offset Reference Register

54h

ADCPPB3TRIPHI

ADC PPB3 Trip High Register

EALLOW

Go

56h

ADCPPB3TRIPLO

ADC PPB3 Trip Low/Trigger Time Stamp
Register

EALLOW

Go

58h

ADCPPB4CONFIG

ADC PPB4 Config Register

EALLOW

Go

Go
EALLOW

Go
Go

Go
EALLOW

Go
Go

59h

ADCPPB4STAMP

ADC PPB4 Sample Delay Time Stamp Register

5Ah

ADCPPB4OFFCAL

ADC PPB4 Offset Calibration Register

Go

5Bh

ADCPPB4OFFREF

ADC PPB4 Offset Reference Register

5Ch

ADCPPB4TRIPHI

ADC PPB4 Trip High Register

EALLOW

Go

5Eh

ADCPPB4TRIPLO

ADC PPB4 Trip Low/Trigger Time Stamp
Register

EALLOW

Go

70h

ADCINLTRIM1

ADC Linearity Trim 1 Register

EALLOW

Go

72h

ADCINLTRIM2

ADC Linearity Trim 2 Register

EALLOW

Go

74h

ADCINLTRIM3

ADC Linearity Trim 3 Register

EALLOW

Go

76h

ADCINLTRIM4

ADC Linearity Trim 4 Register

EALLOW

Go

78h

ADCINLTRIM5

ADC Linearity Trim 5 Register

EALLOW

Go

7Ah

ADCINLTRIM6

ADC Linearity Trim 6 Register

EALLOW

Go

EALLOW

Go
Go

Complex bit access types are encoded to fit into small table cells. Table 10-14 shows the codes that are
used for access types in this section.
Table 10-14. ADC_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1423

Registers

www.ti.com

Table 10-14. ADC_REGS Access Type
Codes (continued)
Access Type

1424

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.1 ADCCTL1 Register (Offset = 0h) [reset = 0h]
ADCCTL1 is shown in Figure 10-25 and described in Table 10-15.
Return to Summary Table.
ADC Control 1 Register
Figure 10-25. ADCCTL1 Register
15

14
RESERVED
R-0h

7
ADCPWDNZ
R/W-0h

6

13
ADCBSY
R-0h

12
RESERVED
R-0h

11

5

4

3

10

9

8

ADCBSYCHN
R-0h

RESERVED
R-0h

2
INTPULSEPOS
R/W-0h

1

0
RESERVED
R-0h

Table 10-15. ADCCTL1 Register Field Descriptions
Bit
15-14
13

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

ADCBSY

R

0h

ADC Busy. Set when ADC SOC is generated, cleared by hardware
four ADC clocks after negative edge of S/H pulse. Used by the ADC
state machine to determine if ADC is available to sample.
0 ADC is available to sample next channel
1 ADC is busy and cannot sample another channel
Reset type: SYSRSn

12
11-8

RESERVED

R

0h

Reserved

ADCBSYCHN

R

0h

ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is
generated.
When ADCBSY=0: holds the value of the last converted SOC
When ADCBSY=1: reflects the SOC currently being processed
0h SOC0 is currently processing or was last SOC converted
1h SOC1 is currently processing or was last SOC converted
2h SOC2 is currently processing or was last SOC converted
3h SOC3 is currently processing or was last SOC converted
4h SOC4 is currently processing or was last SOC converted
5h SOC5 is currently processing or was last SOC converted
6h SOC6 is currently processing or was last SOC converted
7h SOC7 is currently processing or was last SOC converted
8h SOC8 is currently processing or was last SOC converted
9h SOC9 is currently processing or was last SOC converted
Ah SOC10 is currently processing or was last SOC converted
Bh SOC11 is currently processing or was last SOC converted
Ch SOC12 is currently processing or was last SOC converted
Dh SOC13 is currently processing or was last SOC converted
Eh SOC14 is currently processing or was last SOC converted
Fh SOC15 is currently processing or was last SOC converted
Reset type: SYSRSn

7

ADCPWDNZ

R/W

0h

ADC Power Down (active low). This bit controls the power up and
power down of all the analog circuitry inside the analog core.
0 All analog circuitry inside the core is powered down
1 All analog circuitry inside the core is powered up
Reset type: SYSRSn

6-3

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1425

Registers

www.ti.com

Table 10-15. ADCCTL1 Register Field Descriptions (continued)
Bit
2

Field

Type

Reset

Description

INTPULSEPOS

R/W

0h

ADC Interrupt Pulse Position.
0 Interrrupt pulse generation occurs at the end of the acquistion
window
1 Interrupt pulse generation occurs at the end of the conversion, 1
cycle prior to the ADC result latching into its result register
Reset type: SYSRSn

1-0

1426

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.2 ADCCTL2 Register (Offset = 1h) [reset = 0h]
ADCCTL2 is shown in Figure 10-26 and described in Table 10-16.
Return to Summary Table.
ADC Control 2 Register
Figure 10-26. ADCCTL2 Register
15

14
RESERVED
R-0h

13

7
SIGNALMODE
R/W-0h

6
RESOLUTION
R/W-0h

5

12

11

10
RESERVED
R-0h

9

8

4

3

2

1

0

RESERVED
R-0h

PRESCALE
R/W-0h

Table 10-16. ADCCTL2 Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R

0h

Reserved

12-8

RESERVED

R

0h

Reserved

SIGNALMODE

R/W

0h

SOC Signaling Mode. Selects the input mode of the converter. Use
the AdcSetMode function to change the signal mode.

7

0 Single-ended
1 Differential
Reset type: SYSRSn
6

RESOLUTION

R/W

0h

SOC Conversion Resolution. Selects the resolution of the converter.
Use the AdcSetMode function to change the resolution.
0 12-bit resolution
1 16-bit resolution
Reset type: SYSRSn

5-4

RESERVED

R

0h

Reserved

3-0

PRESCALE

R/W

0h

ADC Clock Prescaler.
0000 ADCCLK = Input Clock / 1.0
0001 Invalid
0010 ADCCLK = Input Clock / 2.0
0011 ADCCLK = Input Clock / 2.5
0100 ADCCLK = Input Clock / 3.0
0101 ADCCLK = Input Clock / 3.5
0110 ADCCLK = Input Clock / 4.0
0111 ADCCLK = Input Clock / 4.5
1000 ADCCLK = Input Clock / 5.0
1001 ADCCLK = Input Clock / 5.5
1010 ADCCLK = Input Clock / 6.0
1011 ADCCLK = Input Clock / 6.5
1100 ADCCLK = Input Clock / 7.0
1101 ADCCLK = Input Clock / 7.5
1110 ADCCLK = Input Clock / 8.0
1111 ADCCLK = Input Clock / 8.5
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1427

Registers

www.ti.com

10.4.2.3 ADCBURSTCTL Register (Offset = 2h) [reset = 0h]
ADCBURSTCTL is shown in Figure 10-27 and described in Table 10-17.
Return to Summary Table.
ADC Burst Control Register
Figure 10-27. ADCBURSTCTL Register
15
BURSTEN
R/W-0h

14

7

6

13
RESERVED
R-0h

12

5

4

11

10

9

8

1

0

BURSTSIZE
R/W-0h

RESERVED
R-0h

3
2
BURSTTRIGSEL
R/W-0h

Table 10-17. ADCBURSTCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

BURSTEN

R/W

0h

SOC Burst Mode Enable. This bit enables the SOC Burst Mode of
operation.
0 Burst mode is disabled.
1 Burst mode is enabled.
Reset type: SYSRSn

14-12

RESERVED

R

0h

Reserved

11-8

BURSTSIZE

R/W

0h

SOC Burst Size Select. This bit field determines how many SOCs
are converted when a burst conversion sequence is started. The first
SOC converted is defined by the round robin pointer, which is
advanced as each SOC is converted.
0h 1 SOC converted
1h 2 SOCs converted
2h 3 SOCs converted
3h 4 SOCs converted
4h 5 SOCs converted
5h 6 SOCs converted
6h 7 SOCs converted
7h 8 SOCs converted
8h 9 SOCs converted
9h 10 SOCs converted
Ah 11 SOCs converted
Bh 12 SOCs converted
Ch 13 SOCs converted
Dh 14 SOCs converted
Eh 15 SOCs converted
Fh 16 SOCs converted
Reset type: SYSRSn

7-6

1428

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-17. ADCBURSTCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

BURSTTRIGSEL

R/W

0h

SOC Burst Trigger Source Select. Configures which trigger will start
a burst conversion sequence.
00h BURSTTRIG0 - Software only
01h BURSTTRIG1 - CPU1 Timer 0, TINT0n
02h BURSTTRIG2 - CPU1 Timer 1, TINT1n
03h BURSTTRIG3 - CPU1 Timer 2, TINT2n
04h BURSTTRIG4 - GPIO, Input X-Bar INPUT5
05h BURSTTRIG5 - ePWM1, ADCSOCA
06h BURSTTRIG6 - ePWM1, ADCSOCB
07h BURSTTRIG7 - ePWM2, ADCSOCA
08h BURSTTRIG8 - ePWM2, ADCSOCB
09h BURSTTRIG9 - ePWM3, ADCSOCA
0Ah BURSTTRIG10 - ePWM3, ADCSOCB
0Bh BURSTTRIG11 - ePWM4, ADCSOCA
0Ch BURSTTRIG12 - ePWM4, ADCSOCB
0Dh BURSTTRIG13 - ePWM5, ADCSOCA
0Eh BURSTTRIG14 - ePWM5, ADCSOCB
0Fh BURSTTRIG15 - ePWM6, ADCSOCA
10h BURSTTRIG16 - ePWM6, ADCSOCB
11h BURSTTRIG17 - ePWM7, ADCSOCA
12h BURSTTRIG18 - ePWM7, ADCSOCB
13h BURSTTRIG19 - ePWM8, ADCSOCA
14h BURSTTRIG20 - ePWM8, ADCSOCB
15h BURSTTRIG21 - ePWM9, ADCSOCA
16h BURSTTRIG22 - ePWM9, ADCSOCB
17h BURSTTRIG23 - ePWM10, ADCSOCA
18h BURSTTRIG24 - ePWM10, ADCSOCB
19h BURSTTRIG25 - ePWM11, ADCSOCA
1Ah BURSTTRIG26 - ePWM11, ADCSOCB
1Bh BURSTTRIG27 - ePWM12, ADCSOCA
1Ch BURSTTRIG28 - ePWM12, ADCSOCB
1Dh BURSTTRIG29 - CPU2 Timer 0, TINT0n
1Eh BURSTTRIG30 - CPU2 Timer 1, TINT1n
1Fh BURSTTRIG31 - CPU2 Timer 2, TINT2n
20h - 3Fh - Reserved
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1429

Registers

www.ti.com

10.4.2.4 ADCINTFLG Register (Offset = 3h) [reset = 0h]
ADCINTFLG is shown in Figure 10-28 and described in Table 10-18.
Return to Summary Table.
ADC Interrupt Flag Register
Figure 10-28. ADCINTFLG Register
15

14

13

12

11

10

9

8

3
ADCINT4
R-0h

2
ADCINT3
R-0h

1
ADCINT2
R-0h

0
ADCINT1
R-0h

RESERVED
R-0h
7

6

5

4

RESERVED
R-0h

Table 10-18. ADCINTFLG Register Field Descriptions
Bit
15-4
3

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

ADCINT4

R

0h

ADC Interrupt 4 Flag. Reading these flags indicates if the associated
ADCINT pulse was generated since the last clear.
0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated
If the ADC interrupt is placed in continuous mode (INTSELxNy
register) then further interrupt pulses are generated whenever a
selected EOC event occurs even if the flag bit is set. If the
continuous mode is not enabled, then no further interrupt pulses are
generated until the user clears this flag bit using the ADCINFLGCLR
register. Rather, an ADC interrupt overflow event occurs in the
ADCINTOVF register.
Reset type: SYSRSn

2

ADCINT3

R

0h

ADC Interrupt 3 Flag. Reading these flags indicates if the associated
ADCINT pulse was generated since the last clear.
0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated
If the ADC interrupt is placed in continuous mode (INTSELxNy
register) then further interrupt pulses are generated whenever a
selected EOC event occurs even if the flag bit is set. If the
continuous mode is not enabled, then no further interrupt pulses are
generated until the user clears this flag bit using the ADCINFLGCLR
register. Rather, an ADC interrupt overflow event occurs in the
ADCINTOVF register.
Reset type: SYSRSn

1

ADCINT2

R

0h

ADC Interrupt 2 Flag. Reading these flags indicates if the associated
ADCINT pulse was generated since the last clear.
0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated
If the ADC interrupt is placed in continuous mode (INTSELxNy
register) then further interrupt pulses are generated whenever a
selected EOC event occurs even if the flag bit is set. If the
continuous mode is not enabled, then no further interrupt pulses are
generated until the user clears this flag bit using the ADCINFLGCLR
register. Rather, an ADC interrupt overflow event occurs in the
ADCINTOVF register.
Reset type: SYSRSn

1430

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-18. ADCINTFLG Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

ADCINT1

R

0h

ADC Interrupt 1 Flag. Reading these flags indicates if the associated
ADCINT pulse was generated since the last clear.
0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated
If the ADC interrupt is placed in continuous mode (INTSELxNy
register) then further interrupt pulses are generated whenever a
selected EOC event occurs even if the flag bit is set. If the
continuous mode is not enabled, then no further interrupt pulses are
generated until the user clears this flag bit using the ADCINFLGCLR
register. Rather, an ADC interrupt overflow event occurs in the
ADCINTOVF register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1431

Registers

www.ti.com

10.4.2.5 ADCINTFLGCLR Register (Offset = 4h) [reset = 0h]
ADCINTFLGCLR is shown in Figure 10-29 and described in Table 10-19.
Return to Summary Table.
ADC Interrupt Flag Clear Register
Figure 10-29. ADCINTFLGCLR Register
15

14

13

12

11

10

9

8

3
ADCINT4
R=0/W=1-0h

2
ADCINT3
R=0/W=1-0h

1
ADCINT2
R=0/W=1-0h

0
ADCINT1
R=0/W=1-0h

RESERVED
R-0h
7

6

5

4

RESERVED
R-0h

Table 10-19. ADCINTFLGCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

3

ADCINT4

R=0/W=1

0h

ADC Interrupt 4 Flag Clear. Reads return 0.
0 No action
1 Clears respective flag bit in the ADCINTFLG register. If software
sets the clear bit on the same cycle that hardware is trying to set the
flag bit, then hardware has priority but the overflow bit will not be
affected (retains current state)
Boundary condition: If hardware is trying to set the bit flag while
software tries to clear the bit in the same cycle, the following will take
place:
1. SW has prioirity and will clear the flag
2. HW set will be discarded
no signal will propagate to the PIE from the latch
3. Overflow flag/condition will be generated
Reset type: SYSRSn

2

ADCINT3

R=0/W=1

0h

ADC Interrupt 3 Flag Clear. Reads return 0.
0 No action
1 Clears respective flag bit in the ADCINTFLG register. If software
sets the clear bit on the same cycle that hardware is trying to set the
flag bit, then hardware has priority but the overflow bit will not be
affected (retains current state)
Boundary condition: If hardware is trying to set the bit flag while
software tries to clear the bit in the same cycle, the following will take
place:
1. SW has prioirity and will clear the flag
2. HW set will be discarded
no signal will propagate to the PIE from the latch
3. Overflow flag/condition will be generated
Reset type: SYSRSn

1

ADCINT2

R=0/W=1

0h

ADC Interrupt 2 Flag Clear. Reads return 0.
0 No action
1 Clears respective flag bit in the ADCINTFLG register. If software
sets the clear bit on the same cycle that hardware is trying to set the
flag bit, then hardware has priority but the overflow bit will not be
affected (retains current state)
Boundary condition: If hardware is trying to set the bit flag while
software tries to clear the bit in the same cycle, the following will take
place:
1. SW has prioirity and will clear the flag
2. HW set will be discarded
no signal will propagate to the PIE from the latch
3. Overflow flag/condition will be generated
Reset type: SYSRSn

15-4

1432

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-19. ADCINTFLGCLR Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

ADCINT1

R=0/W=1

0h

ADC Interrupt 1 Flag Clear. Reads return 0.
0 No action
1 Clears respective flag bit in the ADCINTFLG register. If software
sets the clear bit on the same cycle that hardware is trying to set the
flag bit, then hardware has priority but the overflow bit will not be
affected (retains current state)
Boundary condition: If hardware is trying to set the bit flag while
software tries to clear the bit in the same cycle, the following will take
place:
1. SW has prioirity and will clear the flag
2. HW set will be discarded
no signal will propagate to the PIE from the latch
3. Overflow flag/condition will be generated
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1433

Registers

www.ti.com

10.4.2.6 ADCINTOVF Register (Offset = 5h) [reset = 0h]
ADCINTOVF is shown in Figure 10-30 and described in Table 10-20.
Return to Summary Table.
ADC Interrupt Overflow Register
Figure 10-30. ADCINTOVF Register
15

14

13

12

11

10

9

8

3
ADCINT4
R-0h

2
ADCINT3
R-0h

1
ADCINT2
R-0h

0
ADCINT1
R-0h

RESERVED
R-0h
7

6

5

4

RESERVED
R-0h

Table 10-20. ADCINTOVF Register Field Descriptions
Bit
15-4
3

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

ADCINT4

R

0h

ADC Interrupt 4 Overflow Flags
Indicates if an overflow occurred when generating ADCINT pulses. If
the respective ADCINTFLG bit is set and a selected additional EOC
trigger is generated, then an overflow condition occurs.
0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.
The overflow bit does not care about the continuous mode bit state.
An overflow condition is generated irrespective of this mode
selection.
Reset type: SYSRSn

2

ADCINT3

R

0h

ADC Interrupt 3 Overflow Flags
Indicates if an overflow occurred when generating ADCINT pulses. If
the respective ADCINTFLG bit is set and a selected additional EOC
trigger is generated, then an overflow condition occurs.
0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.
The overflow bit does not care about the continuous mode bit state.
An overflow condition is generated irrespective of this mode
selection.
Reset type: SYSRSn

1

ADCINT2

R

0h

ADC Interrupt 2 Overflow Flags
Indicates if an overflow occurred when generating ADCINT pulses. If
the respective ADCINTFLG bit is set and a selected additional EOC
trigger is generated, then an overflow condition occurs.
0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.
The overflow bit does not care about the continuous mode bit state.
An overflow condition is generated irrespective of this mode
selection.
Reset type: SYSRSn

1434

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-20. ADCINTOVF Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

ADCINT1

R

0h

ADC Interrupt 1 Overflow Flags
Indicates if an overflow occurred when generating ADCINT pulses. If
the respective ADCINTFLG bit is set and a selected additional EOC
trigger is generated, then an overflow condition occurs.
0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.
The overflow bit does not care about the continuous mode bit state.
An overflow condition is generated irrespective of this mode
selection.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1435

Registers

www.ti.com

10.4.2.7 ADCINTOVFCLR Register (Offset = 6h) [reset = 0h]
ADCINTOVFCLR is shown in Figure 10-31 and described in Table 10-21.
Return to Summary Table.
ADC Interrupt Overflow Clear Register
Figure 10-31. ADCINTOVFCLR Register
15

14

13

12

11

10

9

8

3
ADCINT4
R=0/W=1-0h

2
ADCINT3
R=0/W=1-0h

1
ADCINT2
R=0/W=1-0h

0
ADCINT1
R=0/W=1-0h

RESERVED
R-0h
7

6

5

4

RESERVED
R-0h

Table 10-21. ADCINTOVFCLR Register Field Descriptions
Bit
15-4
3

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

ADCINT4

R=0/W=1

0h

ADC Interrupt 4 Overflow Clear Bits
0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If
software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCINTOVF register, then
hardware has priority and the ADCINTOVF bit will be set.
Reset type: SYSRSn

2

ADCINT3

R=0/W=1

0h

ADC Interrupt 3 Overflow Clear Bits
0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If
software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCINTOVF register, then
hardware has priority and the ADCINTOVF bit will be set.
Reset type: SYSRSn

1

ADCINT2

R=0/W=1

0h

ADC Interrupt 2 Overflow Clear Bits
0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If
software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCINTOVF register, then
hardware has priority and the ADCINTOVF bit will be set.
Reset type: SYSRSn

0

ADCINT1

R=0/W=1

0h

ADC Interrupt 1 Overflow Clear Bits
0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If
software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCINTOVF register, then
hardware has priority and the ADCINTOVF bit will be set.
Reset type: SYSRSn

1436

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.8 ADCINTSEL1N2 Register (Offset = 7h) [reset = 0h]
ADCINTSEL1N2 is shown in Figure 10-32 and described in Table 10-22.
Return to Summary Table.
ADC Interrupt 1 and 2 Selection Register
Figure 10-32. ADCINTSEL1N2 Register
15
RESERVED
R-0h

14
INT2CONT
R/W-0h

13
INT2E
R/W-0h

12
RESERVED
R-0h

11

7
RESERVED
R-0h

6
INT1CONT
R/W-0h

5
INT1E
R/W-0h

4
RESERVED
R-0h

3

10

9

8

1

0

INT2SEL
R/W-0h
2
INT1SEL
R/W-0h

Table 10-22. ADCINTSEL1N2 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

INT2CONT

R/W

0h

ADCINT2 Continuous Mode Enable
0 No further ADCINT2 pulses are generated until ADCINT2 flag (in
ADCINTFLG register) is cleared by user.
1 ADCINT2 pulses are generated whenever an EOC pulse is
generated irrespective of whether the flag bit is cleared or not.
Reset type: SYSRSn

13

INT2E

R/W

0h

ADCINT2 Interrupt Enable
0 ADCINT2 is disabled
1 ADCINT2 is enabled
Reset type: SYSRSn

12
11-8

RESERVED

R

0h

Reserved

INT2SEL

R/W

0h

ADCINT2 EOC Source Select
0h EOC0 is trigger for ADCINT2
1h EOC1 is trigger for ADCINT2
2h EOC2 is trigger for ADCINT2
3h EOC3 is trigger for ADCINT2
4h EOC4 is trigger for ADCINT2
5h EOC5 is trigger for ADCINT2
6h EOC6 is trigger for ADCINT2
7h EOC7 is trigger for ADCINT2
8h EOC8 is trigger for ADCINT2
9h EOC9 is trigger for ADCINT2
Ah EOC10 is trigger for ADCINT2
Bh EOC11 is trigger for ADCINT2
Ch EOC12 is trigger for ADCINT2
Dh EOC13 is trigger for ADCINT2
Eh EOC14 is trigger for ADCINT2
Fh EOC15 is trigger for ADCINT2
Reset type: SYSRSn

7

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1437

Registers

www.ti.com

Table 10-22. ADCINTSEL1N2 Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

INT1CONT

R/W

0h

ADCINT1 Continuous Mode Enable
0 No further ADCINT1 pulses are generated until ADCINT1 flag (in
ADCINTFLG register) is cleared by user.
1 ADCINT1 pulses are generated whenever an EOC pulse is
generated irrespective of whether the flag bit is cleared or not.
Reset type: SYSRSn

5

INT1E

R/W

0h

ADCINT1 Interrupt Enable
0 ADCINT1 is disabled
1 ADCINT1 is enabled
Reset type: SYSRSn

4
3-0

RESERVED

R

0h

Reserved

INT1SEL

R/W

0h

ADCINT1 EOC Source Select
0h EOC0 is trigger for ADCINT1
1h EOC1 is trigger for ADCINT1
2h EOC2 is trigger for ADCINT1
3h EOC3 is trigger for ADCINT1
4h EOC4 is trigger for ADCINT1
5h EOC5 is trigger for ADCINT1
6h EOC6 is trigger for ADCINT1
7h EOC7 is trigger for ADCINT1
8h EOC8 is trigger for ADCINT1
9h EOC9 is trigger for ADCINT1
Ah EOC10 is trigger for ADCINT1
Bh EOC11 is trigger for ADCINT1
Ch EOC12 is trigger for ADCINT1
Dh EOC13 is trigger for ADCINT1
Eh EOC14 is trigger for ADCINT1
Fh EOC15 is trigger for ADCINT1
Reset type: SYSRSn

1438

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.9 ADCINTSEL3N4 Register (Offset = 8h) [reset = 0h]
ADCINTSEL3N4 is shown in Figure 10-33 and described in Table 10-23.
Return to Summary Table.
ADC Interrupt 3 and 4 Selection Register
Figure 10-33. ADCINTSEL3N4 Register
15
RESERVED
R-0h

14
INT4CONT
R/W-0h

13
INT4E
R/W-0h

12
RESERVED
R-0h

11

7
RESERVED
R-0h

6
INT3CONT
R/W-0h

5
INT3E
R/W-0h

4
RESERVED
R-0h

3

10

9

8

1

0

INT4SEL
R/W-0h
2
INT3SEL
R/W-0h

Table 10-23. ADCINTSEL3N4 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

INT4CONT

R/W

0h

ADCINT4 Continuous Mode Enable
0 No further ADCINT4 pulses are generated until ADCINT4 flag (in
ADCINTFLG register) is cleared by user.
1 ADCINT4 pulses are generated whenever an EOC pulse is
generated irrespective of whether the flag bit is cleared or not.
Reset type: SYSRSn

13

INT4E

R/W

0h

ADCINT4 Interrupt Enable
0 ADCINT4 is disabled
1 ADCINT4 is enabled
Reset type: SYSRSn

12
11-8

RESERVED

R

0h

Reserved

INT4SEL

R/W

0h

ADCINT4 EOC Source Select
0h EOC0 is trigger for ADCINT4
1h EOC1 is trigger for ADCINT4
2h EOC2 is trigger for ADCINT4
3h EOC3 is trigger for ADCINT4
4h EOC4 is trigger for ADCINT4
5h EOC5 is trigger for ADCINT4
6h EOC6 is trigger for ADCINT4
7h EOC7 is trigger for ADCINT4
8h EOC8 is trigger for ADCINT4
9h EOC9 is trigger for ADCINT4
Ah EOC10 is trigger for ADCINT4
Bh EOC11 is trigger for ADCINT4
Ch EOC12 is trigger for ADCINT4
Dh EOC13 is trigger for ADCINT4
Eh EOC14 is trigger for ADCINT4
Fh EOC15 is trigger for ADCINT4
Reset type: SYSRSn

7

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1439

Registers

www.ti.com

Table 10-23. ADCINTSEL3N4 Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

INT3CONT

R/W

0h

ADCINT3 Continuous Mode Enable
0 No further ADCINT3 pulses are generated until ADCINT3 flag (in
ADCINTFLG register) is cleared by user.
1 ADCINT3 pulses are generated whenever an EOC pulse is
generated irrespective of whether the flag bit is cleared or not.
Reset type: SYSRSn

5

INT3E

R/W

0h

ADCINT3 Interrupt Enable
0 ADCINT3 is disabled
1 ADCINT3 is enabled
Reset type: SYSRSn

4
3-0

RESERVED

R

0h

Reserved

INT3SEL

R/W

0h

ADCINT3 EOC Source Select
0h EOC0 is trigger for ADCINT3
1h EOC1 is trigger for ADCINT3
2h EOC2 is trigger for ADCINT3
3h EOC3 is trigger for ADCINT3
4h EOC4 is trigger for ADCINT3
5h EOC5 is trigger for ADCINT3
6h EOC6 is trigger for ADCINT3
7h EOC7 is trigger for ADCINT3
8h EOC8 is trigger for ADCINT3
9h EOC9 is trigger for ADCINT3
Ah EOC10 is trigger for ADCINT3
Bh EOC11 is trigger for ADCINT3
Ch EOC12 is trigger for ADCINT3
Dh EOC13 is trigger for ADCINT3
Eh EOC14 is trigger for ADCINT3
Fh EOC15 is trigger for ADCINT3
Reset type: SYSRSn

1440

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.10 ADCSOCPRICTL Register (Offset = 9h) [reset = 200h]
ADCSOCPRICTL is shown in Figure 10-34 and described in Table 10-24.
Return to Summary Table.
ADC SOC Priority Control Register
Figure 10-34. ADCSOCPRICTL Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6
RRPOINTER
R-10h

5

8
RRPOINTER
R-10h

4

3

2
SOCPRIORITY
R/W-0h

1

0

Table 10-24. ADCSOCPRICTL Register Field Descriptions
Bit
15-10

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1441

Registers

www.ti.com

Table 10-24. ADCSOCPRICTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

9-5

RRPOINTER

R

10h

Round Robin Pointer. Holds the value of the last converted round
robin SOCx to be used by the round robin scheme to determine
order of conversions.
00h SOC0 was last round robin SOC to convert, SOC1 is highest
round robin priority.
01h SOC1 was last round robin SOC to convert, SOC2 is highest
round robin priority.
02h SOC2 was last round robin SOC to convert, SOC3 is highest
round robin priority.
03h SOC3 was last round robin SOC to convert, SOC4 is highest
round robin priority.
04h SOC4 was last round robin SOC to convert, SOC5 is highest
round robin priority.
05h SOC5 was last round robin SOC to convert, SOC6 is highest
round robin priority.
06h SOC6 was last round robin SOC to convert, SOC7 is highest
round robin priority.
07h SOC7 was last round robin SOC to convert, SOC8 is highest
round robin priority.
08h SOC8 was last round robin SOC to convert, SOC9 is highest
round robin priority.
09h SOC9 was last round robin SOC to convert, SOC10 is highest
round robin priority.
0Ah SOC10 was last round robin SOC to convert, SOC11 is highest
round robin priority.
0Bh SOC11 was last round robin SOC to convert, SOC12 is highest
round robin priority.
0Ch SOC12 was last round robin SOC to convert, SOC13 is highest
round robin priority.
0Dh SOC13 was last round robin SOC to convert, SOC14 is highest
round robin priority.
0Eh SOC14 was last round robin SOC to convert, SOC15 is highest
round robin priority.
0Fh SOC15 was last round robin SOC to convert, SOC0 is highest
round robin priority.
10h Reset value to indicate no SOC has been converted. SOC0 is
hghest round robin priority. Set to this value when the device is
reset, when the ADCCTL1.RESET bit is set, or when the
ADCSOCPRICTL register is written. In the latter case, if a
conversion is currently in progress, it will complete and then the new
priority will take effect.
Others Invalid value.
Reset type: SYSRSn

1442

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-24. ADCSOCPRICTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-0

SOCPRIORITY

R/W

0h

SOC Priority
Determines the cutoff point for priority mode and round robin
arbitration for SOCx
00h SOC priority is handled in round robin mode for all channels.
01h SOC0 is high priority, rest of channels are in round robin mode.
02h SOC0-SOC1 are high priority, SOC2-SOC15 are in round robin
mode.
03h SOC0-SOC2 are high priority, SOC3-SOC15 are in round robin
mode.
04h SOC0-SOC3 are high priority, SOC4-SOC15 are in round robin
mode.
05h SOC0-SOC4 are high priority, SOC5-SOC15 are in round robin
mode.
06h SOC0-SOC5 are high priority, SOC6-SOC15 are in round robin
mode.
07h SOC0-SOC6 are high priority, SOC7-SOC15 are in round robin
mode.
08h SOC0-SOC7 are high priority, SOC8-SOC15 are in round robin
mode.
09h SOC0-SOC8 are high priority, SOC9-SOC15 are in round robin
mode.
0Ah SOC0-SOC9 are high priority, SOC10-SOC15 are in round
robin mode.
0Bh SOC0-SOC10 are high priority, SOC11-SOC15 are in round
robin mode.
0Ch SOC0-SOC11 are high priority, SOC12-SOC15 are in round
robin mode.
0Dh SOC0-SOC12 are high priority, SOC13-SOC15 are in round
robin mode.
0Eh SOC0-SOC13 are high priority, SOC14-SOC15 are in round
robin mode.
0Fh SOC0-SOC14 are high priority, SOC15 is in round robin mode.
10h All SOCs are in high priority mode, arbitrated by SOC number.
Others Invalid selection.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1443

Registers

www.ti.com

10.4.2.11 ADCINTSOCSEL1 Register (Offset = Ah) [reset = 0h]
ADCINTSOCSEL1 is shown in Figure 10-35 and described in Table 10-25.
Return to Summary Table.
ADC Interrupt SOC Selection 1 Register
Figure 10-35. ADCINTSOCSEL1 Register
15

14

13

12

SOC7
R/W-0h
7

11

10

SOC6
R/W-0h
6

5

4

SOC3
R/W-0h

9

SOC5
R/W-0h
3

2

SOC2
R/W-0h

8
SOC4
R/W-0h

SOC1
R/W-0h

1

0
SOC0
R/W-0h

Table 10-25. ADCINTSOCSEL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15-14

SOC7

R/W

0h

SOC7 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC7. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC7. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC7.
10 ADCINT2 will trigger SOC7.
11 Invalid selection.
Reset type: SYSRSn

13-12

SOC6

R/W

0h

SOC6 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC6. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC6. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC6.
10 ADCINT2 will trigger SOC6.
11 Invalid selection.
Reset type: SYSRSn

11-10

SOC5

R/W

0h

SOC5 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC5. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC5. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC5.
10 ADCINT2 will trigger SOC5.
11 Invalid selection.
Reset type: SYSRSn

9-8

SOC4

R/W

0h

SOC4 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC4. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC4. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC4.
10 ADCINT2 will trigger SOC4.
11 Invalid selection.
Reset type: SYSRSn

1444

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-25. ADCINTSOCSEL1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

SOC3

R/W

0h

SOC3 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC3. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC3. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC3.
10 ADCINT2 will trigger SOC3.
11 Invalid selection.
Reset type: SYSRSn

5-4

SOC2

R/W

0h

SOC2 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC2. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC2. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC2.
10 ADCINT2 will trigger SOC2.
11 Invalid selection.
Reset type: SYSRSn

3-2

SOC1

R/W

0h

SOC1 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC1. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC1. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC1.
10 ADCINT2 will trigger SOC1.
11 Invalid selection.
Reset type: SYSRSn

1-0

SOC0

R/W

0h

SOC0 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC0. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC0. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC0.
10 ADCINT2 will trigger SOC0.
11 Invalid selection.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1445

Registers

www.ti.com

10.4.2.12 ADCINTSOCSEL2 Register (Offset = Bh) [reset = 0h]
ADCINTSOCSEL2 is shown in Figure 10-36 and described in Table 10-26.
Return to Summary Table.
ADC Interrupt SOC Selection 2 Register
Figure 10-36. ADCINTSOCSEL2 Register
15

14

13

12

SOC15
R/W-0h
7

11

10

SOC14
R/W-0h
6

5

4

SOC11
R/W-0h

9

SOC13
R/W-0h
3

2

SOC10
R/W-0h

8
SOC12
R/W-0h

SOC9
R/W-0h

1

0
SOC8
R/W-0h

Table 10-26. ADCINTSOCSEL2 Register Field Descriptions
Bit
15-14

Field

Type

Reset

Description

SOC15

R/W

0h

SOC15 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC15. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC15. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC15.
10 ADCINT2 will trigger SOC15.
11 Invalid selection.
Reset type: SYSRSn

13-12

SOC14

R/W

0h

SOC14 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC14. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC14. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC14.
10 ADCINT2 will trigger SOC14.
11 Invalid selection.
Reset type: SYSRSn

11-10

SOC13

R/W

0h

SOC13 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC13. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC13. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC13.
10 ADCINT2 will trigger SOC13.
11 Invalid selection.
Reset type: SYSRSn

9-8

SOC12

R/W

0h

SOC12 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC12. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC12. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC12.
10 ADCINT2 will trigger SOC12.
11 Invalid selection.
Reset type: SYSRSn

1446

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-26. ADCINTSOCSEL2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

SOC11

R/W

0h

SOC11 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC11. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC11. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC11.
10 ADCINT2 will trigger SOC11.
11 Invalid selection.
Reset type: SYSRSn

5-4

SOC10

R/W

0h

SOC10 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC10. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC10. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC10.
10 ADCINT2 will trigger SOC10.
11 Invalid selection.
Reset type: SYSRSn

3-2

SOC9

R/W

0h

SOC9 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC9. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC9. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC9.
10 ADCINT2 will trigger SOC9.
11 Invalid selection.
Reset type: SYSRSn

1-0

SOC8

R/W

0h

SOC8 ADC Interrupt Trigger Select. Selects which, if any, ADCINT
triggers SOC8. The trigger selected in this field is in addition to the
TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC8. TRIGSEL field alone determines
SOC0 trigger.
01 ADCINT1 will trigger SOC8.
10 ADCINT2 will trigger SOC8.
11 Invalid selection.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1447

Registers

www.ti.com

10.4.2.13 ADCSOCFLG1 Register (Offset = Ch) [reset = 0h]
ADCSOCFLG1 is shown in Figure 10-37 and described in Table 10-27.
Return to Summary Table.
ADC SOC Flag 1 Register
Figure 10-37. ADCSOCFLG1 Register
15
SOC15
R-0h

14
SOC14
R-0h

13
SOC13
R-0h

12
SOC12
R-0h

11
SOC11
R-0h

10
SOC10
R-0h

9
SOC9
R-0h

8
SOC8
R-0h

7
SOC7
R-0h

6
SOC6
R-0h

5
SOC5
R-0h

4
SOC4
R-0h

3
SOC3
R-0h

2
SOC2
R-0h

1
SOC1
R-0h

0
SOC0
R-0h

Table 10-27. ADCSOCFLG1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SOC15

R

0h

SOC15 Start of Conversion Flag. Indicates the state of SOC15
conversions.
0 No sample pending for SOC15.
1 Trigger has been received and sample is pending for SOC15.
This bit will be automatically cleared when the SOC15 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

14

SOC14

R

0h

SOC14 Start of Conversion Flag. Indicates the state of SOC14
conversions.
0 No sample pending for SOC14.
1 Trigger has been received and sample is pending for SOC14.
This bit will be automatically cleared when the SOC14 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

13

SOC13

R

0h

SOC13 Start of Conversion Flag. Indicates the state of SOC13
conversions.
0 No sample pending for SOC13.
1 Trigger has been received and sample is pending for SOC13.
This bit will be automatically cleared when the SOC13 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

1448

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-27. ADCSOCFLG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

12

SOC12

R

0h

SOC12 Start of Conversion Flag. Indicates the state of SOC12
conversions.
0 No sample pending for SOC12.
1 Trigger has been received and sample is pending for SOC12.
This bit will be automatically cleared when the SOC12 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

11

SOC11

R

0h

SOC11 Start of Conversion Flag. Indicates the state of SOC11
conversions.
0 No sample pending for SOC11.
1 Trigger has been received and sample is pending for SOC11.
This bit will be automatically cleared when the SOC11 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

10

SOC10

R

0h

SOC10 Start of Conversion Flag. Indicates the state of SOC10
conversions.
0 No sample pending for SOC10.
1 Trigger has been received and sample is pending for SOC10.
This bit will be automatically cleared when the SOC10 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

9

SOC9

R

0h

SOC9 Start of Conversion Flag. Indicates the state of SOC9
conversions.
0 No sample pending for SOC9.
1 Trigger has been received and sample is pending for SOC9.
This bit will be automatically cleared when the SOC9 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1449

Registers

www.ti.com

Table 10-27. ADCSOCFLG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

8

SOC8

R

0h

SOC8 Start of Conversion Flag. Indicates the state of SOC8
conversions.
0 No sample pending for SOC8.
1 Trigger has been received and sample is pending for SOC8.
This bit will be automatically cleared when the SOC8 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

7

SOC7

R

0h

SOC7 Start of Conversion Flag. Indicates the state of SOC7
conversions.
0 No sample pending for SOC7.
1 Trigger has been received and sample is pending for SOC7.
This bit will be automatically cleared when the SOC7 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

6

SOC6

R

0h

SOC6 Start of Conversion Flag. Indicates the state of SOC6
conversions.
0 No sample pending for SOC6.
1 Trigger has been received and sample is pending for SOC6.
This bit will be automatically cleared when the SOC6 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

5

SOC5

R

0h

SOC5 Start of Conversion Flag. Indicates the state of SOC5
conversions.
0 No sample pending for SOC5.
1 Trigger has been received and sample is pending for SOC5.
This bit will be automatically cleared when the SOC5 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

1450

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-27. ADCSOCFLG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4

SOC4

R

0h

SOC4 Start of Conversion Flag. Indicates the state of SOC4
conversions.
0 No sample pending for SOC4.
1 Trigger has been received and sample is pending for SOC4.
This bit will be automatically cleared when the SOC4 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

3

SOC3

R

0h

SOC3 Start of Conversion Flag. Indicates the state of SOC3
conversions.
0 No sample pending for SOC3.
1 Trigger has been received and sample is pending for SOC3.
This bit will be automatically cleared when the SOC3 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

2

SOC2

R

0h

SOC2 Start of Conversion Flag. Indicates the state of SOC2
conversions.
0 No sample pending for SOC2.
1 Trigger has been received and sample is pending for SOC2.
This bit will be automatically cleared when the SOC2 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

1

SOC1

R

0h

SOC1 Start of Conversion Flag. Indicates the state of SOC1
conversions.
0 No sample pending for SOC1.
1 Trigger has been received and sample is pending for SOC1.
This bit will be automatically cleared when the SOC1 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1451

Registers

www.ti.com

Table 10-27. ADCSOCFLG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

SOC0

R

0h

SOC0 Start of Conversion Flag. Indicates the state of SOC0
conversions.
0 No sample pending for SOC0.
1 Trigger has been received and sample is pending for SOC0.
This bit will be automatically cleared when the SOC0 conversion is
started. If contention exists where this bit receives both a request to
set and a request to clear on the same cycle, regardless of the
source of either, this bit will be set and the request to clear will be
ignored. In this case the overflow bit in the ADCSOCOVF1 register
will not be affected regardless of whether this bit was previously set
or not.
Reset type: SYSRSn

1452

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.14 ADCSOCFRC1 Register (Offset = Dh) [reset = 0h]
ADCSOCFRC1 is shown in Figure 10-38 and described in Table 10-28.
Return to Summary Table.
ADC SOC Force 1 Register
Figure 10-38. ADCSOCFRC1 Register
15
SOC15
R=0/W=1-0h

14
SOC14
R=0/W=1-0h

13
SOC13
R=0/W=1-0h

12
SOC12
R=0/W=1-0h

11
SOC11
R=0/W=1-0h

10
SOC10
R=0/W=1-0h

9
SOC9
R=0/W=1-0h

8
SOC8
R=0/W=1-0h

7
SOC7
R=0/W=1-0h

6
SOC6
R=0/W=1-0h

5
SOC5
R=0/W=1-0h

4
SOC4
R=0/W=1-0h

3
SOC3
R=0/W=1-0h

2
SOC2
R=0/W=1-0h

1
SOC1
R=0/W=1-0h

0
SOC0
R=0/W=1-0h

Table 10-28. ADCSOCFRC1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SOC15

R=0/W=1

0h

SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC15 flag in the ADCSOCFLG1 register. This can be used to
initiate a software initiated conversion. Writes of 0 are ignored. This
bit will always read as a 0.
0 No action.
1 Force SOC15 flag bit to 1. This will cause a conversion to start
once priority is given to SOC15.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC15 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

14

SOC14

R=0/W=1

0h

SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC14 flag in the ADCSOCFLG1 register. This can be used to
initiate a software initiated conversion. Writes of 0 are ignored. This
bit will always read as a 0.
0 No action.
1 Force SOC14 flag bit to 1. This will cause a conversion to start
once priority is given to SOC14.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC14 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1453

Registers

www.ti.com

Table 10-28. ADCSOCFRC1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

SOC13

R=0/W=1

0h

SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC13 flag in the ADCSOCFLG1 register. This can be used to
initiate a software initiated conversion. Writes of 0 are ignored. This
bit will always read as a 0.
0 No action.
1 Force SOC13 flag bit to 1. This will cause a conversion to start
once priority is given to SOC13.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC13 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

12

SOC12

R=0/W=1

0h

SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC12 flag in the ADCSOCFLG1 register. This can be used to
initiate a software initiated conversion. Writes of 0 are ignored. This
bit will always read as a 0.
0 No action.
1 Force SOC12 flag bit to 1. This will cause a conversion to start
once priority is given to SOC12.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC12 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

11

SOC11

R=0/W=1

0h

SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC11 flag in the ADCSOCFLG1 register. This can be used to
initiate a software initiated conversion. Writes of 0 are ignored. This
bit will always read as a 0.
0 No action.
1 Force SOC11 flag bit to 1. This will cause a conversion to start
once priority is given to SOC11.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC11 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

10

SOC10

R=0/W=1

0h

SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC10 flag in the ADCSOCFLG1 register. This can be used to
initiate a software initiated conversion. Writes of 0 are ignored. This
bit will always read as a 0.
0 No action.
1 Force SOC10 flag bit to 1. This will cause a conversion to start
once priority is given to SOC10.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC10 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

1454

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-28. ADCSOCFRC1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

9

SOC9

R=0/W=1

0h

SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC9 flag bit to 1. This will cause a conversion to start once
priority is given to SOC9.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC9 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

8

SOC8

R=0/W=1

0h

SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC8 flag bit to 1. This will cause a conversion to start once
priority is given to SOC8.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC8 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

7

SOC7

R=0/W=1

0h

SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC7 flag bit to 1. This will cause a conversion to start once
priority is given to SOC7.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC7 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

6

SOC6

R=0/W=1

0h

SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC6 flag bit to 1. This will cause a conversion to start once
priority is given to SOC6.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC6 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1455

Registers

www.ti.com

Table 10-28. ADCSOCFRC1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5

SOC5

R=0/W=1

0h

SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC5 flag bit to 1. This will cause a conversion to start once
priority is given to SOC5.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC5 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

4

SOC4

R=0/W=1

0h

SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC4 flag bit to 1. This will cause a conversion to start once
priority is given to SOC4.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC4 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

3

SOC3

R=0/W=1

0h

SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC3 flag bit to 1. This will cause a conversion to start once
priority is given to SOC3.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC3 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

2

SOC2

R=0/W=1

0h

SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC2 flag bit to 1. This will cause a conversion to start once
priority is given to SOC2.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC2 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

1456

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-28. ADCSOCFRC1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

SOC1

R=0/W=1

0h

SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC1 flag bit to 1. This will cause a conversion to start once
priority is given to SOC1.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC1 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

0

SOC0

R=0/W=1

0h

SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the
SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate
a software initiated conversion. Writes of 0 are ignored. This bit will
always read as a 0.
0 No action.
1 Force SOC0 flag bit to 1. This will cause a conversion to start once
priority is given to SOC0.
If software tries to set this bit on the same clock cycle that hardware
tries to clear the SOC0 bit in the ADCSOCFLG1 register, then
software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be
affected regardless of whether the ADCSOCFLG1 bit was previously
set or not.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1457

Registers

www.ti.com

10.4.2.15 ADCSOCOVF1 Register (Offset = Eh) [reset = 0h]
ADCSOCOVF1 is shown in Figure 10-39 and described in Table 10-29.
Return to Summary Table.
ADC SOC Overflow 1 Register
Figure 10-39. ADCSOCOVF1 Register
15
SOC15
R-0h

14
SOC14
R-0h

13
SOC13
R-0h

12
SOC12
R-0h

11
SOC11
R-0h

10
SOC10
R-0h

9
SOC9
R-0h

8
SOC8
R-0h

7
SOC7
R-0h

6
SOC6
R-0h

5
SOC5
R-0h

4
SOC4
R-0h

3
SOC3
R-0h

2
SOC2
R-0h

1
SOC1
R-0h

0
SOC0
R-0h

Table 10-29. ADCSOCOVF1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SOC15

R

0h

SOC15 Start of Conversion Overflow Flag. Indicates an SOC15
event was generated in hardware while an existing SOC15 event
was already pending.
0 No SOC15 event overflow.
1 SOC15 event overflow.
An overflow condition does not stop SOC15 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

14

SOC14

R

0h

SOC14 Start of Conversion Overflow Flag. Indicates an SOC14
event was generated in hardware while an existing SOC14 event
was already pending.
0 No SOC14 event overflow.
1 SOC14 event overflow.
An overflow condition does not stop SOC14 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

13

SOC13

R

0h

SOC13 Start of Conversion Overflow Flag. Indicates an SOC13
event was generated in hardware while an existing SOC13 event
was already pending.
0 No SOC13 event overflow.
1 SOC13 event overflow.
An overflow condition does not stop SOC13 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

1458

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-29. ADCSOCOVF1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

12

SOC12

R

0h

SOC12 Start of Conversion Overflow Flag. Indicates an SOC12
event was generated in hardware while an existing SOC12 event
was already pending.
0 No SOC12 event overflow.
1 SOC12 event overflow.
An overflow condition does not stop SOC12 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

11

SOC11

R

0h

SOC11 Start of Conversion Overflow Flag. Indicates an SOC11
event was generated in hardware while an existing SOC11 event
was already pending.
0 No SOC11 event overflow.
1 SOC11 event overflow.
An overflow condition does not stop SOC11 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

10

SOC10

R

0h

SOC10 Start of Conversion Overflow Flag. Indicates an SOC10
event was generated in hardware while an existing SOC10 event
was already pending.
0 No SOC10 event overflow.
1 SOC10 event overflow.
An overflow condition does not stop SOC10 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

9

SOC9

R

0h

SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event
was generated in hardware while an existing SOC9 event was
already pending.
0 No SOC9 event overflow.
1 SOC9 event overflow.
An overflow condition does not stop SOC9 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

8

SOC8

R

0h

SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event
was generated in hardware while an existing SOC8 event was
already pending.
0 No SOC8 event overflow.
1 SOC8 event overflow.
An overflow condition does not stop SOC8 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1459

Registers

www.ti.com

Table 10-29. ADCSOCOVF1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7

SOC7

R

0h

SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event
was generated in hardware while an existing SOC7 event was
already pending.
0 No SOC7 event overflow.
1 SOC7 event overflow.
An overflow condition does not stop SOC7 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

6

SOC6

R

0h

SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event
was generated in hardware while an existing SOC6 event was
already pending.
0 No SOC6 event overflow.
1 SOC6 event overflow.
An overflow condition does not stop SOC6 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

5

SOC5

R

0h

SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event
was generated in hardware while an existing SOC5 event was
already pending.
0 No SOC5 event overflow.
1 SOC5 event overflow.
An overflow condition does not stop SOC5 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

4

SOC4

R

0h

SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event
was generated in hardware while an existing SOC4 event was
already pending.
0 No SOC4 event overflow.
1 SOC4 event overflow.
An overflow condition does not stop SOC4 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

3

SOC3

R

0h

SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event
was generated in hardware while an existing SOC3 event was
already pending.
0 No SOC3 event overflow.
1 SOC3 event overflow.
An overflow condition does not stop SOC3 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

1460

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-29. ADCSOCOVF1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2

SOC2

R

0h

SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event
was generated in hardware while an existing SOC2 event was
already pending.
0 No SOC2 event overflow.
1 SOC2 event overflow.
An overflow condition does not stop SOC2 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

1

SOC1

R

0h

SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event
was generated in hardware while an existing SOC1 event was
already pending.
0 No SOC1 event overflow.
1 SOC1 event overflow.
An overflow condition does not stop SOC1 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

0

SOC0

R

0h

SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event
was generated in hardware while an existing SOC0 event was
already pending.
0 No SOC0 event overflow.
1 SOC0 event overflow.
An overflow condition does not stop SOC0 events from being
processed. It simply is an indication that a hardware trigger was
missed. A write to the ADCSOCFRC1 register does not affect this
bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1461

Registers

www.ti.com

10.4.2.16 ADCSOCOVFCLR1 Register (Offset = Fh) [reset = 0h]
ADCSOCOVFCLR1 is shown in Figure 10-40 and described in Table 10-30.
Return to Summary Table.
ADC SOC Overflow Clear 1 Register
Figure 10-40. ADCSOCOVFCLR1 Register
15
SOC15
R=0/W=1-0h

14
SOC14
R=0/W=1-0h

13
SOC13
R=0/W=1-0h

12
SOC12
R=0/W=1-0h

11
SOC11
R=0/W=1-0h

10
SOC10
R=0/W=1-0h

9
SOC9
R=0/W=1-0h

8
SOC8
R=0/W=1-0h

7
SOC7
R=0/W=1-0h

6
SOC6
R=0/W=1-0h

5
SOC5
R=0/W=1-0h

4
SOC4
R=0/W=1-0h

3
SOC3
R=0/W=1-0h

2
SOC2
R=0/W=1-0h

1
SOC1
R=0/W=1-0h

0
SOC0
R=0/W=1-0h

Table 10-30. ADCSOCOVFCLR1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SOC15

R=0/W=1

0h

SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC15 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

14

SOC14

R=0/W=1

0h

SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC14 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

13

SOC13

R=0/W=1

0h

SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC13 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

12

SOC12

R=0/W=1

0h

SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC12 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

1462

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-30. ADCSOCOVFCLR1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

SOC11

R=0/W=1

0h

SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC11 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

10

SOC10

R=0/W=1

0h

SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC10 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

9

SOC9

R=0/W=1

0h

SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC9 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

8

SOC8

R=0/W=1

0h

SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC8 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

7

SOC7

R=0/W=1

0h

SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC7 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1463

Registers

www.ti.com

Table 10-30. ADCSOCOVFCLR1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

SOC6

R=0/W=1

0h

SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC6 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

5

SOC5

R=0/W=1

0h

SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC5 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

4

SOC4

R=0/W=1

0h

SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC4 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

3

SOC3

R=0/W=1

0h

SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC3 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

2

SOC2

R=0/W=1

0h

SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC2 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

1464

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-30. ADCSOCOVFCLR1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

SOC1

R=0/W=1

0h

SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC1 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

0

SOC0

R=0/W=1

0h

SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear
the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0
are ignored. Reads will always return a 0.
0 No action.
1 Clear SOC0 overflow flag.
If software tries to set this bit on the same clock cycle that hardware
tries to set the overflow bit in the ADCSOCOVF1 register, then
hardware has priority and the ADCSOCOVF1 bit will be set..
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1465

Registers

www.ti.com

10.4.2.17 ADCSOC0CTL Register (Offset = 10h) [reset = 0h]
ADCSOC0CTL is shown in Figure 10-41 and described in Table 10-31.
Return to Summary Table.
ADC SOC0 Control Register
Figure 10-41. ADCSOC0CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-31. ADCSOC0CTL Register Field Descriptions
Bit
31-25

1466

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-31. ADCSOC0CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC0 Trigger Source Select. Along with the SOC0 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC0 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1467

Registers

www.ti.com

Table 10-31. ADCSOC0CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC0 Channel Select. Selects the channel to be converted when
SOC0 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC0 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

1468

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.18 ADCSOC1CTL Register (Offset = 12h) [reset = 0h]
ADCSOC1CTL is shown in Figure 10-42 and described in Table 10-32.
Return to Summary Table.
ADC SOC1 Control Register
Figure 10-42. ADCSOC1CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-32. ADCSOC1CTL Register Field Descriptions
Bit
31-25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1469

Registers

www.ti.com

Table 10-32. ADCSOC1CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC1 Trigger Source Select. Along with the SOC1 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC1 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

1470

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-32. ADCSOC1CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC1 Channel Select. Selects the channel to be converted when
SOC1 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC1 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1471

Registers

www.ti.com

10.4.2.19 ADCSOC2CTL Register (Offset = 14h) [reset = 0h]
ADCSOC2CTL is shown in Figure 10-43 and described in Table 10-33.
Return to Summary Table.
ADC SOC2 Control Register
Figure 10-43. ADCSOC2CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-33. ADCSOC2CTL Register Field Descriptions
Bit
31-25

1472

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-33. ADCSOC2CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC2 Trigger Source Select. Along with the SOC2 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC2 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1473

Registers

www.ti.com

Table 10-33. ADCSOC2CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC2 Channel Select. Selects the channel to be converted when
SOC2 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC2 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

1474

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.20 ADCSOC3CTL Register (Offset = 16h) [reset = 0h]
ADCSOC3CTL is shown in Figure 10-44 and described in Table 10-34.
Return to Summary Table.
ADC SOC3 Control Register
Figure 10-44. ADCSOC3CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-34. ADCSOC3CTL Register Field Descriptions
Bit
31-25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1475

Registers

www.ti.com

Table 10-34. ADCSOC3CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC3 Trigger Source Select. Along with the SOC3 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC3 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

1476

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-34. ADCSOC3CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC3 Channel Select. Selects the channel to be converted when
SOC3 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC3 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1477

Registers

www.ti.com

10.4.2.21 ADCSOC4CTL Register (Offset = 18h) [reset = 0h]
ADCSOC4CTL is shown in Figure 10-45 and described in Table 10-35.
Return to Summary Table.
ADC SOC4 Control Register
Figure 10-45. ADCSOC4CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-35. ADCSOC4CTL Register Field Descriptions
Bit
31-25

1478

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-35. ADCSOC4CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC4 Trigger Source Select. Along with the SOC4 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC4 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1479

Registers

www.ti.com

Table 10-35. ADCSOC4CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC4 Channel Select. Selects the channel to be converted when
SOC4 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC4 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

1480

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.22 ADCSOC5CTL Register (Offset = 1Ah) [reset = 0h]
ADCSOC5CTL is shown in Figure 10-46 and described in Table 10-36.
Return to Summary Table.
ADC SOC5 Control Register
Figure 10-46. ADCSOC5CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-36. ADCSOC5CTL Register Field Descriptions
Bit
31-25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1481

Registers

www.ti.com

Table 10-36. ADCSOC5CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC5 Trigger Source Select. Along with the SOC5 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC5 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

1482

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-36. ADCSOC5CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC5 Channel Select. Selects the channel to be converted when
SOC5 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC5 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1483

Registers

www.ti.com

10.4.2.23 ADCSOC6CTL Register (Offset = 1Ch) [reset = 0h]
ADCSOC6CTL is shown in Figure 10-47 and described in Table 10-37.
Return to Summary Table.
ADC SOC6 Control Register
Figure 10-47. ADCSOC6CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-37. ADCSOC6CTL Register Field Descriptions
Bit
31-25

1484

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-37. ADCSOC6CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC6 Trigger Source Select. Along with the SOC6 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC6 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1485

Registers

www.ti.com

Table 10-37. ADCSOC6CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC6 Channel Select. Selects the channel to be converted when
SOC6 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC6 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

1486

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.24 ADCSOC7CTL Register (Offset = 1Eh) [reset = 0h]
ADCSOC7CTL is shown in Figure 10-48 and described in Table 10-38.
Return to Summary Table.
ADC SOC7 Control Register
Figure 10-48. ADCSOC7CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-38. ADCSOC7CTL Register Field Descriptions
Bit
31-25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1487

Registers

www.ti.com

Table 10-38. ADCSOC7CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC7 Trigger Source Select. Along with the SOC7 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC7 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

1488

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-38. ADCSOC7CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC7 Channel Select. Selects the channel to be converted when
SOC7 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC7 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1489

Registers

www.ti.com

10.4.2.25 ADCSOC8CTL Register (Offset = 20h) [reset = 0h]
ADCSOC8CTL is shown in Figure 10-49 and described in Table 10-39.
Return to Summary Table.
ADC SOC8 Control Register
Figure 10-49. ADCSOC8CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-39. ADCSOC8CTL Register Field Descriptions
Bit
31-25

1490

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-39. ADCSOC8CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC8 Trigger Source Select. Along with the SOC8 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC8 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1491

Registers

www.ti.com

Table 10-39. ADCSOC8CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC8 Channel Select. Selects the channel to be converted when
SOC8 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC8 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

1492

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.26 ADCSOC9CTL Register (Offset = 22h) [reset = 0h]
ADCSOC9CTL is shown in Figure 10-50 and described in Table 10-40.
Return to Summary Table.
ADC SOC9 Control Register
Figure 10-50. ADCSOC9CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-40. ADCSOC9CTL Register Field Descriptions
Bit
31-25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1493

Registers

www.ti.com

Table 10-40. ADCSOC9CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC9 Trigger Source Select. Along with the SOC9 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC9 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

1494

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-40. ADCSOC9CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC9 Channel Select. Selects the channel to be converted when
SOC9 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC9 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1495

Registers

www.ti.com

10.4.2.27 ADCSOC10CTL Register (Offset = 24h) [reset = 0h]
ADCSOC10CTL is shown in Figure 10-51 and described in Table 10-41.
Return to Summary Table.
ADC SOC10 Control Register
Figure 10-51. ADCSOC10CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-41. ADCSOC10CTL Register Field Descriptions
Bit
31-25

1496

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-41. ADCSOC10CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC10 Trigger Source Select. Along with the SOC10 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC10 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1497

Registers

www.ti.com

Table 10-41. ADCSOC10CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC10 Channel Select. Selects the channel to be converted when
SOC10 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC10 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

1498

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.28 ADCSOC11CTL Register (Offset = 26h) [reset = 0h]
ADCSOC11CTL is shown in Figure 10-52 and described in Table 10-42.
Return to Summary Table.
ADC SOC11 Control Register
Figure 10-52. ADCSOC11CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-42. ADCSOC11CTL Register Field Descriptions
Bit
31-25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1499

Registers

www.ti.com

Table 10-42. ADCSOC11CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC11 Trigger Source Select. Along with the SOC11 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC11 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

1500

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-42. ADCSOC11CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC11 Channel Select. Selects the channel to be converted when
SOC11 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC11 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1501

Registers

www.ti.com

10.4.2.29 ADCSOC12CTL Register (Offset = 28h) [reset = 0h]
ADCSOC12CTL is shown in Figure 10-53 and described in Table 10-43.
Return to Summary Table.
ADC SOC12 Control Register
Figure 10-53. ADCSOC12CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-43. ADCSOC12CTL Register Field Descriptions
Bit
31-25

1502

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-43. ADCSOC12CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC12 Trigger Source Select. Along with the SOC12 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC12 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1503

Registers

www.ti.com

Table 10-43. ADCSOC12CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC12 Channel Select. Selects the channel to be converted when
SOC12 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC12 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

1504

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.30 ADCSOC13CTL Register (Offset = 2Ah) [reset = 0h]
ADCSOC13CTL is shown in Figure 10-54 and described in Table 10-44.
Return to Summary Table.
ADC SOC13 Control Register
Figure 10-54. ADCSOC13CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-44. ADCSOC13CTL Register Field Descriptions
Bit
31-25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1505

Registers

www.ti.com

Table 10-44. ADCSOC13CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC13 Trigger Source Select. Along with the SOC13 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC13 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

1506

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-44. ADCSOC13CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC13 Channel Select. Selects the channel to be converted when
SOC13 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC13 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1507

Registers

www.ti.com

10.4.2.31 ADCSOC14CTL Register (Offset = 2Ch) [reset = 0h]
ADCSOC14CTL is shown in Figure 10-55 and described in Table 10-45.
Return to Summary Table.
ADC SOC14 Control Register
Figure 10-55. ADCSOC14CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-45. ADCSOC14CTL Register Field Descriptions
Bit
31-25

1508

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-45. ADCSOC14CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC14 Trigger Source Select. Along with the SOC14 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC14 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1509

Registers

www.ti.com

Table 10-45. ADCSOC14CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC14 Channel Select. Selects the channel to be converted when
SOC14 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC14 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

1510

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.32 ADCSOC15CTL Register (Offset = 2Eh) [reset = 0h]
ADCSOC15CTL is shown in Figure 10-56 and described in Table 10-46.
Return to Summary Table.
ADC SOC15 Control Register
Figure 10-56. ADCSOC15CTL Register
31

30

23

22

29

28
RESERVED
R-0h

27

26

25

24
TRIGSEL
R/W-0h

21

20

19
RESERVED
R-0h

18

17
CHSEL
R/W-0h

16

13

12

11

10

9

8
ACQPS
R/W-0h

3

2

1

0

TRIGSEL
R/W-0h
15
CHSEL
R/W-0h

14

7

6

RESERVED
R-0h
5

4
ACQPS
R/W-0h

Table 10-46. ADCSOC15CTL Register Field Descriptions
Bit
31-25

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1511

Registers

www.ti.com

Table 10-46. ADCSOC15CTL Register Field Descriptions (continued)
Bit
24-20

Field

Type

Reset

Description

TRIGSEL

R/W

0h

SOC15 Trigger Source Select. Along with the SOC15 field in the
ADCINTSOCSEL1 register, this bit field configures which trigger will
set the SOC15 flag in the ADCSOCFLG1 register to initiate a
conversion to start once priority is given to it.
00h ADCTRIG0 - Software only
01h ADCTRIG1 - CPU1 Timer 0, TINT0n
02h ADCTRIG2 - CPU1 Timer 1, TINT1n
03h ADCTRIG3 - CPU1 Timer 2, TINT2n
04h ADCTRIG4 - GPIO, ADCEXTSOC
05h ADCTRIG5 - ePWM1, ADCSOCA
06h ADCTRIG6 - ePWM1, ADCSOCB
07h ADCTRIG7 - ePWM2, ADCSOCA
08h ADCTRIG8 - ePWM2, ADCSOCB
09h ADCTRIG9 - ePWM3, ADCSOCA
0Ah ADCTRIG10 - ePWM3, ADCSOCB
0Bh ADCTRIG11 - ePWM4, ADCSOCA
0Ch ADCTRIG12 - ePWM4, ADCSOCB
0Dh ADCTRIG13 - ePWM5, ADCSOCA
0Eh ADCTRIG14 - ePWM5, ADCSOCB
0Fh ADCTRIG15 - ePWM6, ADCSOCA
10h ADCTRIG16 - ePWM6, ADCSOCB
11h ADCTRIG17 - ePWM7, ADCSOCA
12h ADCTRIG18 - ePWM7, ADCSOCB
13h ADCTRIG19 - ePWM8, ADCSOCA
14h ADCTRIG20 - ePWM8, ADCSOCB
15h ADCTRIG21 - ePWM9, ADCSOCA
16h ADCTRIG22 - ePWM9, ADCSOCB
17h ADCTRIG23 - ePWM10, ADCSOCA
18h ADCTRIG24 - ePWM10, ADCSOCB
19h ADCTRIG25 - ePWM11, ADCSOCA
1Ah ADCTRIG26 - ePWM11, ADCSOCB
1Bh ADCTRIG27 - ePWM12, ADCSOCA
1Ch ADCTRIG28 - ePWM12, ADCSOCB
1Dh ADCTRIG29 - CPU2 Timer 0, TINT0n
1Eh ADCTRIG30 - CPU2 Timer 1, TINT1n
1Fh ADCTRIG31 - CPU2 Timer 2, TINT2n
Reset type: SYSRSn

19

1512

RESERVED

Analog-to-Digital Converter (ADC)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-46. ADCSOC15CTL Register Field Descriptions (continued)
Bit
18-15

Field

Type

Reset

Description

CHSEL

R/W

0h

SOC15 Channel Select. Selects the channel to be converted when
SOC15 is received by the ADC.
Single-ended Signaling Mode (SIGNALMODE = 0):
0h ADCIN0
1h ADCIN1
2h ADCIN2
3h ADCIN3
4h ADCIN4
5h ADCIN5
6h ADCIN6
7h ADCIN7
8h ADCIN8
9h ADCIN9
Ah ADCIN10
Bh ADCIN11
Ch ADCIN12
Dh ADCIN13
Eh ADCIN14
Fh ADCIN15
Differential Signaling Mode (SIGNALMODE = 1):
0h ADCIN0 (non-inverting) and ADCIN1 (inverting)
1h ADCIN0 (non-inverting) and ADCIN1 (inverting)
2h ADCIN2 (non-inverting) and ADCIN3 (inverting)
3h ADCIN2 (non-inverting) and ADCIN3 (inverting)
4h ADCIN4 (non-inverting) and ADCIN5 (inverting)
5h ADCIN4 (non-inverting) and ADCIN5 (inverting)
6h ADCIN6 (non-inverting) and ADCIN7 (inverting)
7h ADCIN6 (non-inverting) and ADCIN7 (inverting)
8h ADCIN8 (non-inverting) and ADCIN9 (inverting)
9h ADCIN8 (non-inverting) and ADCIN9 (inverting)
Ah ADCIN10 (non-inverting) and ADCIN11 (inverting)
Bh ADCIN10 (non-inverting) and ADCIN11 (inverting)
Ch ADCIN12 (non-inverting) and ADCIN13 (inverting)
Dh ADCIN12 (non-inverting) and ADCIN13 (inverting)
Eh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Fh ADCIN14 (non-inverting) and ADCIN15 (inverting)
Reset type: SYSRSn

14-9

RESERVED

R

0h

Reserved

8-0

ACQPS

R/W

0h

SOC15 Acquisition Prescale. Controls the sample and hold window
for this SOC. The configured acquisition time must be at least as
long as one ADCCLK cycle for correct ADC operation. The device
datasheet will also specify a minimum sample and hold window
duration.
000h Sample window is 1 system clock cycle wide
001h Sample window is 2 system clock cycles wide
002h Sample window is 3 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1513

Registers

www.ti.com

10.4.2.33 ADCEVTSTAT Register (Offset = 30h) [reset = 0h]
ADCEVTSTAT is shown in Figure 10-57 and described in Table 10-47.
Return to Summary Table.
ADC Event Status Register
Figure 10-57. ADCEVTSTAT Register
15
RESERVED
R-0h

14
PPB4ZERO
R-0h

13
PPB4TRIPLO
R-0h

12
PPB4TRIPHI
R-0h

11
RESERVED
R-0h

10
PPB3ZERO
R-0h

9
PPB3TRIPLO
R-0h

8
PPB3TRIPHI
R-0h

7
RESERVED
R-0h

6
PPB2ZERO
R-0h

5
PPB2TRIPLO
R-0h

4
PPB2TRIPHI
R-0h

3
RESERVED
R-0h

2
PPB1ZERO
R-0h

1
PPB1TRIPLO
R-0h

0
PPB1TRIPHI
R-0h

Table 10-47. ADCEVTSTAT Register Field Descriptions

1514

Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

PPB4ZERO

R

0h

Post Processing Block 4 Zero Crossing Flag. When set indicates the
ADCPPB4RESULT register has changed sign. This bit is gated by
EOC signal.
Reset type: SYSRSn

13

PPB4TRIPLO

R

0h

Post Processing Block 4 Trip Low Flag. When set indicates a digital
compare trip low event has occurred.
Reset type: SYSRSn

12

PPB4TRIPHI

R

0h

Post Processing Block 4 Trip High Flag. When set indicates a digital
compare trip high event has occurred.
Reset type: SYSRSn

11

RESERVED

R

0h

Reserved

10

PPB3ZERO

R

0h

Post Processing Block 3 Zero Crossing Flag. When set indicates the
ADCPPB3RESULT register has changed sign. This bit is gated by
EOC signal.
Reset type: SYSRSn

9

PPB3TRIPLO

R

0h

Post Processing Block 3 Trip Low Flag. When set indicates a digital
compare trip low event has occurred.
Reset type: SYSRSn

8

PPB3TRIPHI

R

0h

Post Processing Block 3 Trip High Flag. When set indicates a digital
compare trip high event has occurred.
Reset type: SYSRSn

7

RESERVED

R

0h

Reserved

6

PPB2ZERO

R

0h

Post Processing Block 2 Zero Crossing Flag. When set indicates the
ADCPPB2RESULT register has changed sign. This bit is gated by
EOC signal.
Reset type: SYSRSn

5

PPB2TRIPLO

R

0h

Post Processing Block 2 Trip Low Flag. When set indicates a digital
compare trip low event has occurred.
Reset type: SYSRSn

4

PPB2TRIPHI

R

0h

Post Processing Block 2 Trip High Flag. When set indicates a digital
compare trip high event has occurred.
Reset type: SYSRSn

3

RESERVED

R

0h

Reserved

2

PPB1ZERO

R

0h

Post Processing Block 1 Zero Crossing Flag. When set indicates the
ADCPPB1RESULT register has changed sign. This bit is gated by
EOC signal.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-47. ADCEVTSTAT Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

PPB1TRIPLO

R

0h

Post Processing Block 1 Trip Low Flag. When set indicates a digital
compare trip low event has occurred.
Reset type: SYSRSn

0

PPB1TRIPHI

R

0h

Post Processing Block 1 Trip High Flag. When set indicates a digital
compare trip high event has occurred.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1515

Registers

www.ti.com

10.4.2.34 ADCEVTCLR Register (Offset = 32h) [reset = 0h]
ADCEVTCLR is shown in Figure 10-58 and described in Table 10-48.
Return to Summary Table.
ADC Event Clear Register
Figure 10-58. ADCEVTCLR Register
15
RESERVED
R-0h

14
PPB4ZERO
R/W-0h

13
PPB4TRIPLO
R/W-0h

12
PPB4TRIPHI
R/W-0h

11
RESERVED
R-0h

10
PPB3ZERO
R/W-0h

9
PPB3TRIPLO
R/W-0h

8
PPB3TRIPHI
R/W-0h

7
RESERVED
R-0h

6
PPB2ZERO
R/W-0h

5
PPB2TRIPLO
R/W-0h

4
PPB2TRIPHI
R/W-0h

3
RESERVED
R-0h

2
PPB1ZERO
R/W-0h

1
PPB1TRIPLO
R/W-0h

0
PPB1TRIPHI
R/W-0h

Table 10-48. ADCEVTCLR Register Field Descriptions

1516

Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

PPB4ZERO

R/W

0h

Post Processing Block 4 Zero Crossing Clear. Clears the
corresponding zero crossing flag in the ADCEVTSTAT register.
Reset type: SYSRSn

13

PPB4TRIPLO

R/W

0h

Post Processing Block 4 Trip Low Clear. Clears the corresponding
trip low flag in the ADCEVTSTAT register.
Reset type: SYSRSn

12

PPB4TRIPHI

R/W

0h

Post Processing Block 4 Trip High Clear. Clears the corresponding
trip high flag in the ADCEVTSTAT register.
Reset type: SYSRSn

11

RESERVED

R

0h

Reserved

10

PPB3ZERO

R/W

0h

Post Processing Block 3 Zero Crossing Clear. Clears the
corresponding zero crossing flag in the ADCEVTSTAT register.
Reset type: SYSRSn

9

PPB3TRIPLO

R/W

0h

Post Processing Block 3 Trip Low Clear. Clears the corresponding
trip low flag in the ADCEVTSTAT register.
Reset type: SYSRSn

8

PPB3TRIPHI

R/W

0h

Post Processing Block 3 Trip High Clear. Clears the corresponding
trip high flag in the ADCEVTSTAT register.
Reset type: SYSRSn

7

RESERVED

R

0h

Reserved

6

PPB2ZERO

R/W

0h

Post Processing Block 2 Zero Crossing Clear. Clears the
corresponding zero crossing flag in the ADCEVTSTAT register.
Reset type: SYSRSn

5

PPB2TRIPLO

R/W

0h

Post Processing Block 2 Trip Low Clear. Clears the corresponding
trip low flag in the ADCEVTSTAT register.
Reset type: SYSRSn

4

PPB2TRIPHI

R/W

0h

Post Processing Block 2 Trip High Clear. Clears the corresponding
trip high flag in the ADCEVTSTAT register.
Reset type: SYSRSn

3

RESERVED

R

0h

Reserved

2

PPB1ZERO

R/W

0h

Post Processing Block 1 Zero Crossing Clear. Clears the
corresponding zero crossing flag in the ADCEVTSTAT register.
Reset type: SYSRSn

1

PPB1TRIPLO

R/W

0h

Post Processing Block 1 Trip Low Clear. Clears the corresponding
trip low flag in the ADCEVTSTAT register.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-48. ADCEVTCLR Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

PPB1TRIPHI

R/W

0h

Post Processing Block 1 Trip High Clear. Clears the corresponding
trip high flag in the ADCEVTSTAT register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1517

Registers

www.ti.com

10.4.2.35 ADCEVTSEL Register (Offset = 34h) [reset = 0h]
ADCEVTSEL is shown in Figure 10-59 and described in Table 10-49.
Return to Summary Table.
ADC Event Selection Register
Figure 10-59. ADCEVTSEL Register
15
RESERVED
R-0h

14
PPB4ZERO
R/W-0h

13
PPB4TRIPLO
R/W-0h

12
PPB4TRIPHI
R/W-0h

11
RESERVED
R-0h

10
PPB3ZERO
R/W-0h

9
PPB3TRIPLO
R/W-0h

8
PPB3TRIPHI
R/W-0h

7
RESERVED
R-0h

6
PPB2ZERO
R/W-0h

5
PPB2TRIPLO
R/W-0h

4
PPB2TRIPHI
R/W-0h

3
RESERVED
R-0h

2
PPB1ZERO
R/W-0h

1
PPB1TRIPLO
R/W-0h

0
PPB1TRIPHI
R/W-0h

Table 10-49. ADCEVTSEL Register Field Descriptions

1518

Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

PPB4ZERO

R/W

0h

Post Processing Block 4 Zero Crossing Event Enable. Setting this bit
allows the corresponding rising zero crossing flag to activate the
event signal to the PWM blocks. The flag must be cleared before it
can produce additional events to the PWM blocks.
Reset type: SYSRSn

13

PPB4TRIPLO

R/W

0h

Post Processing Block 4 Trip Low Event Enable. Setting this bit
allows the corresponding rising trip low flag to activate the event
signal to the PWM blocks. The flag must be cleared before it can
produce additional events to the PWM blocks.
Reset type: SYSRSn

12

PPB4TRIPHI

R/W

0h

Post Processing Block 4 Trip High Event Enable. Setting this bit
allows the corresponding rising trip high flag to activate the event
signal to the PWM blocks. The flag must be cleared before it can
produce additional events to the PWM blocks.
Reset type: SYSRSn

11

RESERVED

R

0h

Reserved

10

PPB3ZERO

R/W

0h

Post Processing Block 3 Zero Crossing Event Enable. Setting this bit
allows the corresponding rising zero crossing flag to activate the
event signal to the PWM blocks. The flag must be cleared before it
can produce additional events to the PWM blocks.
Reset type: SYSRSn

9

PPB3TRIPLO

R/W

0h

Post Processing Block 3 Trip Low Event Enable. Setting this bit
allows the corresponding rising trip low flag to activate the event
signal to the PWM blocks. The flag must be cleared before it can
produce additional events to the PWM blocks.
Reset type: SYSRSn

8

PPB3TRIPHI

R/W

0h

Post Processing Block 3 Trip High Event Enable. Setting this bit
allows the corresponding rising trip high flag to activate the event
signal to the PWM blocks. The flag must be cleared before it can
produce additional events to the PWM blocks.
Reset type: SYSRSn

7

RESERVED

R

0h

Reserved

6

PPB2ZERO

R/W

0h

Post Processing Block 2 Zero Crossing Event Enable. Setting this bit
allows the corresponding rising zero crossing flag to activate the
event signal to the PWM blocks. The flag must be cleared before it
can produce additional events to the PWM blocks.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-49. ADCEVTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5

PPB2TRIPLO

R/W

0h

Post Processing Block 2 Trip Low Event Enable. Setting this bit
allows the corresponding rising trip low flag to activate the event
signal to the PWM blocks. The flag must be cleared before it can
produce additional events to the PWM blocks.
Reset type: SYSRSn

4

PPB2TRIPHI

R/W

0h

Post Processing Block 2 Trip High Event Enable. Setting this bit
allows the corresponding rising trip high flag to activate the event
signal to the PWM blocks. The flag must be cleared before it can
produce additional events to the PWM blocks.
Reset type: SYSRSn

3

RESERVED

R

0h

Reserved

2

PPB1ZERO

R/W

0h

Post Processing Block 1 Zero Crossing Event Enable. Setting this bit
allows the corresponding rising zero crossing flag to activate the
event signal to the PWM blocks. The flag must be cleared before it
can produce additional events to the PWM blocks.
Reset type: SYSRSn

1

PPB1TRIPLO

R/W

0h

Post Processing Block 1 Trip Low Event Enable. Setting this bit
allows the corresponding rising trip low flag to activate the event
signal to the PWM blocks. The flag must be cleared before it can
produce additional events to the PWM blocks.
Reset type: SYSRSn

0

PPB1TRIPHI

R/W

0h

Post Processing Block 1 Trip High Event Enable. Setting this bit
allows the corresponding rising trip high flag to activate the event
signal to the PWM blocks. The flag must be cleared before it can
produce additional events to the PWM blocks.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1519

Registers

www.ti.com

10.4.2.36 ADCEVTINTSEL Register (Offset = 36h) [reset = 0h]
ADCEVTINTSEL is shown in Figure 10-60 and described in Table 10-50.
Return to Summary Table.
ADC Event Interrupt Selection Register
Figure 10-60. ADCEVTINTSEL Register
15
RESERVED
R-0h

14
PPB4ZERO
R/W-0h

13
PPB4TRIPLO
R/W-0h

12
PPB4TRIPHI
R/W-0h

11
RESERVED
R-0h

10
PPB3ZERO
R/W-0h

9
PPB3TRIPLO
R/W-0h

8
PPB3TRIPHI
R/W-0h

7
RESERVED
R-0h

6
PPB2ZERO
R/W-0h

5
PPB2TRIPLO
R/W-0h

4
PPB2TRIPHI
R/W-0h

3
RESERVED
R-0h

2
PPB1ZERO
R/W-0h

1
PPB1TRIPLO
R/W-0h

0
PPB1TRIPHI
R/W-0h

Table 10-50. ADCEVTINTSEL Register Field Descriptions

1520

Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

PPB4ZERO

R/W

0h

Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this
bit allows the corresponding rising zero crossing flag to activate the
event interrupt signal to the PIE. The flag must be cleared before it
can produce additional interrupts to the PIE.
Reset type: SYSRSn

13

PPB4TRIPLO

R/W

0h

Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit
allows the corresponding rising trip low flag to activate the event
interrupt signal to the PIE. The flag must be cleared before it can
produce additional interrupts to the PIE.
Reset type: SYSRSn

12

PPB4TRIPHI

R/W

0h

Post Processing Block 4 Trip High Interrupt Enable. Setting this bit
allows the corresponding rising trip high flag to activate the event
interrupt signal to the PIE. The flag must be cleared before it can
produce additional interrupts to the PIE.
Reset type: SYSRSn

11

RESERVED

R

0h

Reserved

10

PPB3ZERO

R/W

0h

Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this
bit allows the corresponding rising zero crossing flag to activate the
event interrupt signal to the PIE. The flag must be cleared before it
can produce additional interrupts to the PIE.
Reset type: SYSRSn

9

PPB3TRIPLO

R/W

0h

Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit
allows the corresponding rising trip low flag to activate the event
interrupt signal to the PIE. The flag must be cleared before it can
produce additional interrupts to the PIE.
Reset type: SYSRSn

8

PPB3TRIPHI

R/W

0h

Post Processing Block 3 Trip High Interrupt Enable. Setting this bit
allows the corresponding rising trip high flag to activate the event
interrupt signal to the PIE. The flag must be cleared before it can
produce additional interrupts to the PIE.
Reset type: SYSRSn

7

RESERVED

R

0h

Reserved

6

PPB2ZERO

R/W

0h

Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this
bit allows the corresponding rising zero crossing flag to activate the
event interrupt signal to the PIE. The flag must be cleared before it
can produce additional interrupts to the PIE.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-50. ADCEVTINTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5

PPB2TRIPLO

R/W

0h

Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit
allows the corresponding rising trip low flag to activate the event
interrupt signal to the PIE. The flag must be cleared before it can
produce additional interrupts to the PIE.
Reset type: SYSRSn

4

PPB2TRIPHI

R/W

0h

Post Processing Block 2 Trip High Interrupt Enable. Setting this bit
allows the corresponding rising trip high flag to activate the event
interrupt signal to the PIE. The flag must be cleared before it can
produce additional interrupts to the PIE.
Reset type: SYSRSn

3

RESERVED

R

0h

Reserved

2

PPB1ZERO

R/W

0h

Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this
bit allows the corresponding rising zero crossing flag to activate the
event interrupt signal to the PIE. The flag must be cleared before it
can produce additional interrupts to the PIE.
Reset type: SYSRSn

1

PPB1TRIPLO

R/W

0h

Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit
allows the corresponding rising trip low flag to activate the event
interrupt signal to the PIE. The flag must be cleared before it can
produce additional interrupts to the PIE.
Reset type: SYSRSn

0

PPB1TRIPHI

R/W

0h

Post Processing Block 1 Trip High Interrupt Enable. Setting this bit
allows the corresponding rising trip high flag to activate the event
interrupt signal to the PIE. The flag must be cleared before it can
produce additional interrupts to the PIE.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1521

Registers

www.ti.com

10.4.2.37 ADCCOUNTER Register (Offset = 39h) [reset = 0h]
ADCCOUNTER is shown in Figure 10-61 and described in Table 10-51.
Return to Summary Table.
ADC Counter Register
Figure 10-61. ADCCOUNTER Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

FREECOUNT
R-0h
5

4

3

2

FREECOUNT
R-0h

Table 10-51. ADCCOUNTER Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

FREECOUNT

R

0h

ADC Free Running Counter Value. This bit field reflects the status of
the free running ADC counter.
Reset type: SYSRSn

1522

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.38 ADCREV Register (Offset = 3Ah) [reset = 4h]
ADCREV is shown in Figure 10-62 and described in Table 10-52.
Return to Summary Table.
ADC Revision Register
Figure 10-62. ADCREV Register
15

14

13

12

11

10

9

8

3

2

1

0

REV
R-0h
7

6

5

4
TYPE
R-4h

Table 10-52. ADCREV Register Field Descriptions
Bit

Field

Type

Reset

Description

15-8

REV

R

0h

ADC Revision. To allow documentation of differences between
revisions. First version is labeled as 00h.
Reset type: SYSRSn

7-0

TYPE

R

4h

ADC Type. Always set to 4 for this ADC.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1523

Registers

www.ti.com

10.4.2.39 ADCOFFTRIM Register (Offset = 3Bh) [reset = 0h]
ADCOFFTRIM is shown in Figure 10-63 and described in Table 10-53.
Return to Summary Table.
ADC Offset Trim Register
Figure 10-63. ADCOFFTRIM Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
OFFTRIM
R/W-0h

Table 10-53. ADCOFFTRIM Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

OFFTRIM

R/W

0h

ADC Offset Trim. Adjusts the conversion results of the converter up
or down to account for offset error in the ADC. A different offset trim
is required for each combination of resolution and signal mode.
Using the AdcSetMode function to set the resolution and signal
mode will ensure that the correct offset trim is loaded.
Range is +127 steps to -128 steps (2's compliment format).
Regardless of the converter resolution, the size of each trim step is
(VREFHI-VREFLO)/65536.
Reset type: SYSRSn

1524

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.40 ADCPPB1CONFIG Register (Offset = 40h) [reset = 0h]
ADCPPB1CONFIG is shown in Figure 10-64 and described in Table 10-54.
Return to Summary Table.
ADC PPB1 Config Register
Figure 10-64. ADCPPB1CONFIG Register
15

14

13

12

11

10

3

2

9

8

1

0

RESERVED
R-0h
7
RESERVED

6

5
CBCEN

R-0h

R/W-0h

4
TWOSCOMPE
N
R/W-0h

CONFIG
R/W-0h

Table 10-54. ADCPPB1CONFIG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

5

CBCEN

R/W

0h

ADC Post Processing Block Cycle By Cycle Enable. When set, this
bit enables the post conversion hardware processing circuit to
automatically clear the ADCEVTSTAT on a conversion if the event
condition is no longer present.
Reset type: SYSRSn

4

TWOSCOMPEN

R/W

0h

ADC Post Processing Block 1 Two's Complement Enable. When set
this bit enables the post conversion hardware processing circuit that
performs a two's complement on the output of the offset/reference
subtraction unit before storing the result in the ADCPPB1RESULT
register.

15-6

0 ADCPPB1RESULT = ADCRESULTx - ADCPPB1OFFREF
1 ADCPPB1RESULT = ADCPPB1OFFREF - ADCRESULTx
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1525

Registers

www.ti.com

Table 10-54. ADCPPB1CONFIG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

CONFIG

R/W

0h

ADC Post Processing Block 1 Configuration. This bit field defines
which SOC/EOC/RESULT is assocatied with this post processing
block.
0000 SOC0/EOC0/RESULT0 is associated with post processing
block 1
0001 SOC1/EOC1/RESULT1 is associated with post processing
block 1
0010 SOC2/EOC2/RESULT2 is associated with post processing
block 1
0011 SOC3/EOC3/RESULT3 is associated with post processing
block 1
0100 SOC4/EOC4/RESULT4 is associated with post processing
block 1
0101 SOC5/EOC5/RESULT5 is associated with post processing
block 1
0110 SOC6/EOC6/RESULT6 is associated with post processing
block 1
0111 SOC7/EOC7/RESULT7 is associated with post processing
block 1
1000 SOC8/EOC8/RESULT8 is associated with post processing
block 1
1001 SOC9/EOC9/RESULT9 is associated with post processing
block 1
1010 SOC10/EOC10/RESULT10 is associated with post processing
block 1
1011 SOC11/EOC11/RESULT11 is associated with post processing
block 1
1100 SOC12/EOC12/RESULT12 is associated with post processing
block 1
1101 SOC13/EOC13/RESULT13 is associated with post processing
block 1
1110 SOC14/EOC14/RESULT14 is associated with post processing
block 1
1111 SOC15/EOC15/RESULT15 is associated with post processing
block 1
Reset type: SYSRSn

1526

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.41 ADCPPB1STAMP Register (Offset = 41h) [reset = 0h]
ADCPPB1STAMP is shown in Figure 10-65 and described in Table 10-55.
Return to Summary Table.
ADC PPB1 Sample Delay Time Stamp Register
Figure 10-65. ADCPPB1STAMP Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DLYSTAMP
R-0h
5

4

3

2

DLYSTAMP
R-0h

Table 10-55. ADCPPB1STAMP Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DLYSTAMP

R

0h

ADC Post Processing Block 1 Delay Time Stamp. When an SOC
starts sampling the value contained in REQSTAMP is subtracted
from the value in ADCCOUNTER.FREECOUNT and loaded into this
bit field, thereby giving the number of system clock cycles delay
between the SOC trigger and the actual start of the sample.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1527

Registers

www.ti.com

10.4.2.42 ADCPPB1OFFCAL Register (Offset = 42h) [reset = 0h]
ADCPPB1OFFCAL is shown in Figure 10-66 and described in Table 10-56.
Return to Summary Table.
ADC PPB1 Offset Calibration Register
Figure 10-66. ADCPPB1OFFCAL Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6

5

8
OFFCAL
R/W-0h

4

3

2

1

0

OFFCAL
R/W-0h

Table 10-56. ADCPPB1OFFCAL Register Field Descriptions
Bit
15-10
9-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

OFFCAL

R/W

0h

ADC Post Processing Block 1 Offset Correction. This bit field can be
used to digitally remove any system level offset inherent in the
ADCIN circuit. This 10-bit signed value is subtracted from the ADC
output before being stored in the ADCRESULT register.
000h No change. The ADC output is stored directly into
ADCRESULT.
001h ADC output - 1 is stored into ADCRESULT.
002h ADC output - 2 is stored into ADCRESULT.
...
200h ADC output + 512 is stored into ADCRESULT.
...
3FFh ADC output + 1 is stored into ADCRESULT.
NOTE: In 16-bit mode, the subtraction will saturate at 0000h and
FFFFh before being stored into the ADCRESULT register. In 12-bit
mode, the subtraction will saturate at 0000h and 0FFFh before being
stored into the ADCRESULT register.
Reset type: SYSRSn

1528

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.43 ADCPPB1OFFREF Register (Offset = 43h) [reset = 0h]
ADCPPB1OFFREF is shown in Figure 10-67 and described in Table 10-57.
Return to Summary Table.
ADC PPB1 Offset Reference Register
Figure 10-67. ADCPPB1OFFREF Register
15

14

13

12

11

10

9

8
7
OFFREF
R/W-0h

6

5

4

3

2

1

0

Table 10-57. ADCPPB1OFFREF Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

OFFREF

R/W

0h

ADC Post Processing Block 1 Offset Correction. This bit field can be
used to either calculate the feedback error or convert a unipolar
signal to bipolar by subtracting a reference value. This 16-bit
unsigned value is subtracted from the ADCRESULT register before
being passed through an optional two's complement function and
stored in the ADCPPB1RESULT register. This subtraction is not
saturated.
0000h No change. The ADCRESULT value is passed on.
0001h ADCRESULT - 1 is passed on.
0002h ADCRESULT - 2 is passed on.
...
8000h ADCRESULT - 32,768 is passed on.
...
FFFFh ADCRESULT - 65,535 is passed on.
NOTE: In 12-bit mode the size of this register does not change from
16-bits. It is the user's responsibility to ensure that only a 12-bit
value is written to this register when in 12-bit mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1529

Registers

www.ti.com

10.4.2.44 ADCPPB1TRIPHI Register (Offset = 44h) [reset = 0h]
ADCPPB1TRIPHI is shown in Figure 10-68 and described in Table 10-58.
Return to Summary Table.
ADC PPB1 Trip High Register
Figure 10-68. ADCPPB1TRIPHI Register
31

30

29

28

27

26

25

24

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

19

18

17

16
HSIGN
R/W-0h

15

14

13

12

11

10

9

8

3

2

1

0

LIMITHI
R/W-0h
7

6

5

4
LIMITHI
R/W-0h

Table 10-58. ADCPPB1TRIPHI Register Field Descriptions
Bit
31-17

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

16

HSIGN

R/W

0h

High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit
field when in 16-bit ADC mode.
Reset type: SYSRSn

15-0

LIMITHI

R/W

0h

ADC Post Processing Block 1 Trip High Limit. This value sets the
digital comparator trip high limit. In 16-bit mode all 17 bits will be
compared against the 17 bits of the PPBRESULT bit field of the
ADCPPB1RESULT register. In 12-bit mode bits 12:0 will be
compared against bits 12:0 of the PPBRESULT bit field of the
ADCPPB1RESULT register.
Reset type: SYSRSn

1530

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.45 ADCPPB1TRIPLO Register (Offset = 46h) [reset = 0h]
ADCPPB1TRIPLO is shown in Figure 10-69 and described in Table 10-59.
Return to Summary Table.
ADC PPB1 Trip Low/Trigger Time Stamp Register
Figure 10-69. ADCPPB1TRIPLO Register
31

30

29

28

27

26

25

24

19

18
RESERVED
R-0h

17

16
LSIGN
R/W-0h

11

10

9

8

3

2

1

0

REQSTAMP
R-0h
23

22

21

20

13

12

REQSTAMP
R-0h
15

14

LIMITLO
R/W-0h
7

6

5

4
LIMITLO
R/W-0h

Table 10-59. ADCPPB1TRIPLO Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

REQSTAMP

R

0h

ADC Post Processing Block 1 Request Time Stamp. When a trigger
sets the associated SOC flag in the ADCSOCFLG1 register the
value of ADCCOUNTER.FREECOUNT is loaded into this bit field.
Reset type: SYSRSn

19-17

RESERVED

R

0h

Reserved

LSIGN

R/W

0h

Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit
field when in 16-bit ADC mode.
Reset type: SYSRSn

LIMITLO

R/W

0h

ADC Post Processing Block 1 Trip Low Limit. This value sets the
digital comparator trip low limit. In 16-bit mode all 17 bits will be
compared against the 17 bits of the PPBRESULT bit field of the
ADCPPB1RESULT register. In 12-bit mode bits 12:0 will be
compared against bits 12:0 of the PPBRSULT bit field of the
ADCPPB1RESULT register.
Reset type: SYSRSn

16

15-0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1531

Registers

www.ti.com

10.4.2.46 ADCPPB2CONFIG Register (Offset = 48h) [reset = 0h]
ADCPPB2CONFIG is shown in Figure 10-70 and described in Table 10-60.
Return to Summary Table.
ADC PPB2 Config Register
Figure 10-70. ADCPPB2CONFIG Register
15

14

13

12

11

10

3

2

9

8

1

0

RESERVED
R-0h
7
RESERVED

6

5
CBCEN

R-0h

R/W-0h

4
TWOSCOMPE
N
R/W-0h

CONFIG
R/W-0h

Table 10-60. ADCPPB2CONFIG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

5

CBCEN

R/W

0h

ADC Post Processing Block Cycle By Cycle Enable. When set, this
bit enables the post conversion hardware processing circuit to
automatically clear the ADCEVTSTAT on a conversion if the event
condition is no longer present.
Reset type: SYSRSn

4

TWOSCOMPEN

R/W

0h

ADC Post Processing Block 2 Two's Complement Enable. When set
this bit enables the post conversion hardware processing circuit that
performs a two's complement on the output of the offset/reference
subtraction unit before storing the result in the ADCPPB2RESULT
register.

15-6

0 ADCPPB2RESULT = ADCRESULTx - ADCPPB2OFFREF
1 ADCPPB2RESULT = ADCPPB2OFFREF - ADCRESULTx
Reset type: SYSRSn

1532

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-60. ADCPPB2CONFIG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

CONFIG

R/W

0h

ADC Post Processing Block 2 Configuration. This bit field defines
which SOC/EOC/RESULT is assocatied with this post processing
block.
0000 SOC0/EOC0/RESULT0 is associated with post processing
block 2
0001 SOC1/EOC1/RESULT1 is associated with post processing
block 2
0010 SOC2/EOC2/RESULT2 is associated with post processing
block 2
0011 SOC3/EOC3/RESULT3 is associated with post processing
block 2
0100 SOC4/EOC4/RESULT4 is associated with post processing
block 2
0101 SOC5/EOC5/RESULT5 is associated with post processing
block 2
0110 SOC6/EOC6/RESULT6 is associated with post processing
block 2
0111 SOC7/EOC7/RESULT7 is associated with post processing
block 2
1000 SOC8/EOC8/RESULT8 is associated with post processing
block 2
1001 SOC9/EOC9/RESULT9 is associated with post processing
block 2
1010 SOC10/EOC10/RESULT10 is associated with post processing
block 2
1011 SOC11/EOC11/RESULT11 is associated with post processing
block 2
1100 SOC12/EOC12/RESULT12 is associated with post processing
block 2
1101 SOC13/EOC13/RESULT13 is associated with post processing
block 2
1110 SOC14/EOC14/RESULT14 is associated with post processing
block 2
1111 SOC15/EOC15/RESULT15 is associated with post processing
block 2
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1533

Registers

www.ti.com

10.4.2.47 ADCPPB2STAMP Register (Offset = 49h) [reset = 0h]
ADCPPB2STAMP is shown in Figure 10-71 and described in Table 10-61.
Return to Summary Table.
ADC PPB2 Sample Delay Time Stamp Register
Figure 10-71. ADCPPB2STAMP Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DLYSTAMP
R-0h
5

4

3

2

DLYSTAMP
R-0h

Table 10-61. ADCPPB2STAMP Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DLYSTAMP

R

0h

ADC Post Processing Block 2 Delay Time Stamp. When an SOC
starts sampling the value contained in REQSTAMP is subtracted
from the value in ADCCOUNTER.FREECOUNT and loaded into this
bit field, thereby giving the number of system clock cycles delay
between the SOC trigger and the actual start of the sample.
Reset type: SYSRSn

1534

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.48 ADCPPB2OFFCAL Register (Offset = 4Ah) [reset = 0h]
ADCPPB2OFFCAL is shown in Figure 10-72 and described in Table 10-62.
Return to Summary Table.
ADC PPB2 Offset Calibration Register
Figure 10-72. ADCPPB2OFFCAL Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6

5

8
OFFCAL
R/W-0h

4

3

2

1

0

OFFCAL
R/W-0h

Table 10-62. ADCPPB2OFFCAL Register Field Descriptions
Bit
15-10
9-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

OFFCAL

R/W

0h

ADC Post Processing Block 2 Offset Correction. This bit field can be
used to digitally remove any system level offset inherent in the
ADCIN circuit. This 10-bit signed value is subtracted from the ADC
output before being stored in the ADCRESULT register.
000h No change. The ADC output is stored directly into
ADCRESULT.
001h ADC output - 1 is stored into ADCRESULT.
002h ADC output - 2 is stored into ADCRESULT.
...
200h ADC output + 512 is stored into ADCRESULT.
...
3FFh ADC output + 1 is stored into ADCRESULT.
NOTE: In 16-bit mode, the subtraction will saturate at 0000h and
FFFFh before being stored into the ADCRESULT register. In 12-bit
mode, the subtraction will saturate at 0000h and 0FFFh before being
stored into the ADCRESULT register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1535

Registers

www.ti.com

10.4.2.49 ADCPPB2OFFREF Register (Offset = 4Bh) [reset = 0h]
ADCPPB2OFFREF is shown in Figure 10-73 and described in Table 10-63.
Return to Summary Table.
ADC PPB2 Offset Reference Register
Figure 10-73. ADCPPB2OFFREF Register
15

14

13

12

11

10

9

8
7
OFFREF
R/W-0h

6

5

4

3

2

1

0

Table 10-63. ADCPPB2OFFREF Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

OFFREF

R/W

0h

ADC Post Processing Block 2 Offset Correction. This bit field can be
used to either calculate the feedback error or convert a unipolar
signal to bipolar by subtracting a reference value. This 16-bit
unsigned value is subtracted from the ADCRESULT register before
being passed through an optional two's complement function and
stored in the ADCPPB2RESULT register. This subtraction is not
saturated.
0000h No change. The ADCRESULT value is passed on.
0001h ADCRESULT - 1 is passed on.
0002h ADCRESULT - 2 is passed on.
...
8000h ADCRESULT - 32,768 is passed on.
...
FFFFh ADCRESULT - 65,535 is passed on.
NOTE: In 12-bit mode the size of this register does not change from
16-bits. It is the user's responsibility to ensure that only a 12-bit
value is written to this register when in 12-bit mode.
Reset type: SYSRSn

1536

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.50 ADCPPB2TRIPHI Register (Offset = 4Ch) [reset = 0h]
ADCPPB2TRIPHI is shown in Figure 10-74 and described in Table 10-64.
Return to Summary Table.
ADC PPB2 Trip High Register
Figure 10-74. ADCPPB2TRIPHI Register
31

30

29

28

27

26

25

24

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

19

18

17

16
HSIGN
R/W-0h

15

14

13

12

11

10

9

8

3

2

1

0

LIMITHI
R/W-0h
7

6

5

4
LIMITHI
R/W-0h

Table 10-64. ADCPPB2TRIPHI Register Field Descriptions
Bit
31-17

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

16

HSIGN

R/W

0h

High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit
field when in 16-bit ADC mode.
Reset type: SYSRSn

15-0

LIMITHI

R/W

0h

ADC Post Processing Block 2 Trip High Limit. This value sets the
digital comparator trip high limit. In 16-bit mode all 17 bits will be
compared against the 17 bits of the PPBRESULT bit field of the
ADCPPB2RESULT register. In 12-bit mode bits 12:0 will be
compared against bits 12:0 of the PPBRESULT bit field of the
ADCPPB2RESULT register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1537

Registers

www.ti.com

10.4.2.51 ADCPPB2TRIPLO Register (Offset = 4Eh) [reset = 0h]
ADCPPB2TRIPLO is shown in Figure 10-75 and described in Table 10-65.
Return to Summary Table.
ADC PPB2 Trip Low/Trigger Time Stamp Register
Figure 10-75. ADCPPB2TRIPLO Register
31

30

29

28

27

26

25

24

19

18
RESERVED
R-0h

17

16
LSIGN
R/W-0h

11

10

9

8

3

2

1

0

REQSTAMP
R-0h
23

22

21

20

13

12

REQSTAMP
R-0h
15

14

LIMITLO
R/W-0h
7

6

5

4
LIMITLO
R/W-0h

Table 10-65. ADCPPB2TRIPLO Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

REQSTAMP

R

0h

ADC Post Processing Block 2 Request Time Stamp. When a trigger
sets the associated SOC flag in the ADCSOCFLG1 register the
value of ADCCOUNTER.FREECOUNT is loaded into this bit field.
Reset type: SYSRSn

19-17

RESERVED

R

0h

Reserved

LSIGN

R/W

0h

Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit
field when in 16-bit ADC mode.
Reset type: SYSRSn

LIMITLO

R/W

0h

ADC Post Processing Block 2 Trip Low Limit. This value sets the
digital comparator trip low limit. In 16-bit mode all 17 bits will be
compared against the 17 bits of the PPBRESULT bit field of the
ADCPPB2RESULT register. In 12-bit mode bits 12:0 will be
compared against bits 12:0 of the PPBRSULT bit field of the
ADCPPB2RESULT register.
Reset type: SYSRSn

16

15-0

1538

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.52 ADCPPB3CONFIG Register (Offset = 50h) [reset = 0h]
ADCPPB3CONFIG is shown in Figure 10-76 and described in Table 10-66.
Return to Summary Table.
ADC PPB3 Config Register
Figure 10-76. ADCPPB3CONFIG Register
15

14

13

12

11

10

3

2

9

8

1

0

RESERVED
R-0h
7
RESERVED

6

5
CBCEN

R-0h

R/W-0h

4
TWOSCOMPE
N
R/W-0h

CONFIG
R/W-0h

Table 10-66. ADCPPB3CONFIG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

5

CBCEN

R/W

0h

ADC Post Processing Block Cycle By Cycle Enable. When set, this
bit enables the post conversion hardware processing circuit to
automatically clear the ADCEVTSTAT on a conversion if the event
condition is no longer present.
Reset type: SYSRSn

4

TWOSCOMPEN

R/W

0h

ADC Post Processing Block 3 Two's Complement Enable. When set
this bit enables the post conversion hardware processing circuit that
performs a two's complement on the output of the offset/reference
subtraction unit before storing the result in the ADCPPB3RESULT
register.

15-6

0 ADCPPB3RESULT = ADCRESULTx - ADCPPB3OFFREF
1 ADCPPB3RESULT = ADCPPB3OFFREF - ADCRESULTx
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1539

Registers

www.ti.com

Table 10-66. ADCPPB3CONFIG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

CONFIG

R/W

0h

ADC Post Processing Block 3 Configuration. This bit field defines
which SOC/EOC/RESULT is assocatied with this post processing
block.
0000 SOC0/EOC0/RESULT0 is associated with post processing
block 3
0001 SOC1/EOC1/RESULT1 is associated with post processing
block 3
0010 SOC2/EOC2/RESULT2 is associated with post processing
block 3
0011 SOC3/EOC3/RESULT3 is associated with post processing
block 3
0100 SOC4/EOC4/RESULT4 is associated with post processing
block 3
0101 SOC5/EOC5/RESULT5 is associated with post processing
block 3
0110 SOC6/EOC6/RESULT6 is associated with post processing
block 3
0111 SOC7/EOC7/RESULT7 is associated with post processing
block 3
1000 SOC8/EOC8/RESULT8 is associated with post processing
block 3
1001 SOC9/EOC9/RESULT9 is associated with post processing
block 3
1010 SOC10/EOC10/RESULT10 is associated with post processing
block 3
1011 SOC11/EOC11/RESULT11 is associated with post processing
block 3
1100 SOC12/EOC12/RESULT12 is associated with post processing
block 3
1101 SOC13/EOC13/RESULT13 is associated with post processing
block 3
1110 SOC14/EOC14/RESULT14 is associated with post processing
block 3
1111 SOC15/EOC15/RESULT15 is associated with post processing
block 3
Reset type: SYSRSn

1540

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.53 ADCPPB3STAMP Register (Offset = 51h) [reset = 0h]
ADCPPB3STAMP is shown in Figure 10-77 and described in Table 10-67.
Return to Summary Table.
ADC PPB3 Sample Delay Time Stamp Register
Figure 10-77. ADCPPB3STAMP Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DLYSTAMP
R-0h
5

4

3

2

DLYSTAMP
R-0h

Table 10-67. ADCPPB3STAMP Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DLYSTAMP

R

0h

ADC Post Processing Block 3 Delay Time Stamp. When an SOC
starts sampling the value contained in REQSTAMP is subtracted
from the value in ADCCOUNTER.FREECOUNT and loaded into this
bit field, thereby giving the number of system clock cycles delay
between the SOC trigger and the actual start of the sample.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1541

Registers

www.ti.com

10.4.2.54 ADCPPB3OFFCAL Register (Offset = 52h) [reset = 0h]
ADCPPB3OFFCAL is shown in Figure 10-78 and described in Table 10-68.
Return to Summary Table.
ADC PPB3 Offset Calibration Register
Figure 10-78. ADCPPB3OFFCAL Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6

5

8
OFFCAL
R/W-0h

4

3

2

1

0

OFFCAL
R/W-0h

Table 10-68. ADCPPB3OFFCAL Register Field Descriptions
Bit
15-10
9-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

OFFCAL

R/W

0h

ADC Post Processing Block 3 Offset Correction. This bit field can be
used to digitally remove any system level offset inherent in the
ADCIN circuit. This 10-bit signed value is subtracted from the ADC
output before being stored in the ADCRESULT register.
000h No change. The ADC output is stored directly into
ADCRESULT.
001h ADC output - 1 is stored into ADCRESULT.
002h ADC output - 2 is stored into ADCRESULT.
...
200h ADC output + 512 is stored into ADCRESULT.
...
3FFh ADC output + 1 is stored into ADCRESULT.
NOTE: In 16-bit mode, the subtraction will saturate at 0000h and
FFFFh before being stored into the ADCRESULT register. In 12-bit
mode, the subtraction will saturate at 0000h and 0FFFh before being
stored into the ADCRESULT register.
Reset type: SYSRSn

1542

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.55 ADCPPB3OFFREF Register (Offset = 53h) [reset = 0h]
ADCPPB3OFFREF is shown in Figure 10-79 and described in Table 10-69.
Return to Summary Table.
ADC PPB3 Offset Reference Register
Figure 10-79. ADCPPB3OFFREF Register
15

14

13

12

11

10

9

8
7
OFFREF
R/W-0h

6

5

4

3

2

1

0

Table 10-69. ADCPPB3OFFREF Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

OFFREF

R/W

0h

ADC Post Processing Block 3 Offset Correction. This bit field can be
used to either calculate the feedback error or convert a unipolar
signal to bipolar by subtracting a reference value. This 16-bit
unsigned value is subtracted from the ADCRESULT register before
being passed through an optional two's complement function and
stored in the ADCPPB3RESULT register. This subtraction is not
saturated.
0000h No change. The ADCRESULT value is passed on.
0001h ADCRESULT - 1 is passed on.
0002h ADCRESULT - 2 is passed on.
...
8000h ADCRESULT - 32,768 is passed on.
...
FFFFh ADCRESULT - 65,535 is passed on.
NOTE: In 12-bit mode the size of this register does not change from
16-bits. It is the user's responsibility to ensure that only a 12-bit
value is written to this register when in 12-bit mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1543

Registers

www.ti.com

10.4.2.56 ADCPPB3TRIPHI Register (Offset = 54h) [reset = 0h]
ADCPPB3TRIPHI is shown in Figure 10-80 and described in Table 10-70.
Return to Summary Table.
ADC PPB3 Trip High Register
Figure 10-80. ADCPPB3TRIPHI Register
31

30

29

28

27

26

25

24

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

19

18

17

16
HSIGN
R/W-0h

15

14

13

12

11

10

9

8

3

2

1

0

LIMITHI
R/W-0h
7

6

5

4
LIMITHI
R/W-0h

Table 10-70. ADCPPB3TRIPHI Register Field Descriptions
Bit
31-17

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

16

HSIGN

R/W

0h

High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit
field when in 16-bit ADC mode.
Reset type: SYSRSn

15-0

LIMITHI

R/W

0h

ADC Post Processing Block 3 Trip High Limit. This value sets the
digital comparator trip high limit. In 16-bit mode all 17 bits will be
compared against the 17 bits of the PPBRESULT bit field of the
ADCPPB3RESULT register. In 12-bit mode bits 12:0 will be
compared against bits 12:0 of the PPBRESULT bit field of the
ADCPPB3RESULT register.
Reset type: SYSRSn

1544

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.57 ADCPPB3TRIPLO Register (Offset = 56h) [reset = 0h]
ADCPPB3TRIPLO is shown in Figure 10-81 and described in Table 10-71.
Return to Summary Table.
ADC PPB3 Trip Low/Trigger Time Stamp Register
Figure 10-81. ADCPPB3TRIPLO Register
31

30

29

28

27

26

25

24

19

18
RESERVED
R-0h

17

16
LSIGN
R/W-0h

11

10

9

8

3

2

1

0

REQSTAMP
R-0h
23

22

21

20

13

12

REQSTAMP
R-0h
15

14

LIMITLO
R/W-0h
7

6

5

4
LIMITLO
R/W-0h

Table 10-71. ADCPPB3TRIPLO Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

REQSTAMP

R

0h

ADC Post Processing Block 3 Request Time Stamp. When a trigger
sets the associated SOC flag in the ADCSOCFLG1 register the
value of ADCCOUNTER.FREECOUNT is loaded into this bit field.
Reset type: SYSRSn

19-17

RESERVED

R

0h

Reserved

LSIGN

R/W

0h

Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit
field when in 16-bit ADC mode.
Reset type: SYSRSn

LIMITLO

R/W

0h

ADC Post Processing Block 3 Trip Low Limit. This value sets the
digital comparator trip low limit. In 16-bit mode all 17 bits will be
compared against the 17 bits of the PPBRESULT bit field of the
ADCPPB3RESULT register. In 12-bit mode bits 12:0 will be
compared against bits 12:0 of the PPBRSULT bit field of the
ADCPPB3RESULT register.
Reset type: SYSRSn

16

15-0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1545

Registers

www.ti.com

10.4.2.58 ADCPPB4CONFIG Register (Offset = 58h) [reset = 0h]
ADCPPB4CONFIG is shown in Figure 10-82 and described in Table 10-72.
Return to Summary Table.
ADC PPB4 Config Register
Figure 10-82. ADCPPB4CONFIG Register
15

14

13

12

11

10

3

2

9

8

1

0

RESERVED
R-0h
7
RESERVED

6

5
CBCEN

R-0h

R/W-0h

4
TWOSCOMPE
N
R/W-0h

CONFIG
R/W-0h

Table 10-72. ADCPPB4CONFIG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

5

CBCEN

R/W

0h

ADC Post Processing Block Cycle By Cycle Enable. When set, this
bit enables the post conversion hardware processing circuit to
automatically clear the ADCEVTSTAT on a conversion if the event
condition is no longer present.
Reset type: SYSRSn

4

TWOSCOMPEN

R/W

0h

ADC Post Processing Block 4 Two's Complement Enable. When set
this bit enables the post conversion hardware processing circuit that
performs a two's complement on the output of the offset/reference
subtraction unit before storing the result in the ADCPPB4RESULT
register.

15-6

0 ADCPPB4RESULT = ADCRESULTx - ADCPPB4OFFREF
1 ADCPPB4RESULT = ADCPPB4OFFREF - ADCRESULTx
Reset type: SYSRSn

1546

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 10-72. ADCPPB4CONFIG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

CONFIG

R/W

0h

ADC Post Processing Block 4 Configuration. This bit field defines
which SOC/EOC/RESULT is assocatied with this post processing
block.
0000 SOC0/EOC0/RESULT0 is associated with post processing
block 4
0001 SOC1/EOC1/RESULT1 is associated with post processing
block 4
0010 SOC2/EOC2/RESULT2 is associated with post processing
block 4
0011 SOC3/EOC3/RESULT3 is associated with post processing
block 4
0100 SOC4/EOC4/RESULT4 is associated with post processing
block 4
0101 SOC5/EOC5/RESULT5 is associated with post processing
block 4
0110 SOC6/EOC6/RESULT6 is associated with post processing
block 4
0111 SOC7/EOC7/RESULT7 is associated with post processing
block 4
1000 SOC8/EOC8/RESULT8 is associated with post processing
block 4
1001 SOC9/EOC9/RESULT9 is associated with post processing
block 4
1010 SOC10/EOC10/RESULT10 is associated with post processing
block 4
1011 SOC11/EOC11/RESULT11 is associated with post processing
block 4
1100 SOC12/EOC12/RESULT12 is associated with post processing
block 4
1101 SOC13/EOC13/RESULT13 is associated with post processing
block 4
1110 SOC14/EOC14/RESULT14 is associated with post processing
block 4
1111 SOC15/EOC15/RESULT15 is associated with post processing
block 4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1547

Registers

www.ti.com

10.4.2.59 ADCPPB4STAMP Register (Offset = 59h) [reset = 0h]
ADCPPB4STAMP is shown in Figure 10-83 and described in Table 10-73.
Return to Summary Table.
ADC PPB4 Sample Delay Time Stamp Register
Figure 10-83. ADCPPB4STAMP Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DLYSTAMP
R-0h
5

4

3

2

DLYSTAMP
R-0h

Table 10-73. ADCPPB4STAMP Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DLYSTAMP

R

0h

ADC Post Processing Block 4 Delay Time Stamp. When an SOC
starts sampling the value contained in REQSTAMP is subtracted
from the value in ADCCOUNTER.FREECOUNT and loaded into this
bit field, thereby giving the number of system clock cycles delay
between the SOC trigger and the actual start of the sample.
Reset type: SYSRSn

1548

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.60 ADCPPB4OFFCAL Register (Offset = 5Ah) [reset = 0h]
ADCPPB4OFFCAL is shown in Figure 10-84 and described in Table 10-74.
Return to Summary Table.
ADC PPB4 Offset Calibration Register
Figure 10-84. ADCPPB4OFFCAL Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6

5

8
OFFCAL
R/W-0h

4

3

2

1

0

OFFCAL
R/W-0h

Table 10-74. ADCPPB4OFFCAL Register Field Descriptions
Bit
15-10
9-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

OFFCAL

R/W

0h

ADC Post Processing Block 4 Offset Correction. This bit field can be
used to digitally remove any system level offset inherent in the
ADCIN circuit. This 10-bit signed value is subtracted from the ADC
output before being stored in the ADCRESULT register.
000h No change. The ADC output is stored directly into
ADCRESULT.
001h ADC output - 1 is stored into ADCRESULT.
002h ADC output - 2 is stored into ADCRESULT.
...
200h ADC output + 512 is stored into ADCRESULT.
...
3FFh ADC output + 1 is stored into ADCRESULT.
NOTE: In 16-bit mode, the subtraction will saturate at 0000h and
FFFFh before being stored into the ADCRESULT register. In 12-bit
mode, the subtraction will saturate at 0000h and 0FFFh before being
stored into the ADCRESULT register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1549

Registers

www.ti.com

10.4.2.61 ADCPPB4OFFREF Register (Offset = 5Bh) [reset = 0h]
ADCPPB4OFFREF is shown in Figure 10-85 and described in Table 10-75.
Return to Summary Table.
ADC PPB4 Offset Reference Register
Figure 10-85. ADCPPB4OFFREF Register
15

14

13

12

11

10

9

8
7
OFFREF
R/W-0h

6

5

4

3

2

1

0

Table 10-75. ADCPPB4OFFREF Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

OFFREF

R/W

0h

ADC Post Processing Block 4 Offset Correction. This bit field can be
used to either calculate the feedback error or convert a unipolar
signal to bipolar by subtracting a reference value. This 16-bit
unsigned value is subtracted from the ADCRESULT register before
being passed through an optional two's complement function and
stored in the ADCPPB4RESULT register. This subtraction is not
saturated.
0000h No change. The ADCRESULT value is passed on.
0001h ADCRESULT - 1 is passed on.
0002h ADCRESULT - 2 is passed on.
...
8000h ADCRESULT - 32,768 is passed on.
...
FFFFh ADCRESULT - 65,535 is passed on.
NOTE: In 12-bit mode the size of this register does not change from
16-bits. It is the user's responsibility to ensure that only a 12-bit
value is written to this register when in 12-bit mode.
Reset type: SYSRSn

1550

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.62 ADCPPB4TRIPHI Register (Offset = 5Ch) [reset = 0h]
ADCPPB4TRIPHI is shown in Figure 10-86 and described in Table 10-76.
Return to Summary Table.
ADC PPB4 Trip High Register
Figure 10-86. ADCPPB4TRIPHI Register
31

30

29

28

27

26

25

24

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

19

18

17

16
HSIGN
R/W-0h

15

14

13

12

11

10

9

8

3

2

1

0

LIMITHI
R/W-0h
7

6

5

4
LIMITHI
R/W-0h

Table 10-76. ADCPPB4TRIPHI Register Field Descriptions
Bit
31-17

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

16

HSIGN

R/W

0h

High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit
field when in 16-bit ADC mode.
Reset type: SYSRSn

15-0

LIMITHI

R/W

0h

ADC Post Processing Block 4 Trip High Limit. This value sets the
digital comparator trip high limit. In 16-bit mode all 17 bits will be
compared against the 17 bits of the PPBRESULT bit field of the
ADCPPB4RESULT register. In 12-bit mode bits 12:0 will be
compared against bits 12:0 of the PPBRESULT bit field of the
ADCPPB4RESULT register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1551

Registers

www.ti.com

10.4.2.63 ADCPPB4TRIPLO Register (Offset = 5Eh) [reset = 0h]
ADCPPB4TRIPLO is shown in Figure 10-87 and described in Table 10-77.
Return to Summary Table.
ADC PPB4 Trip Low/Trigger Time Stamp Register
Figure 10-87. ADCPPB4TRIPLO Register
31

30

29

28

27

26

25

24

19

18
RESERVED
R-0h

17

16
LSIGN
R/W-0h

11

10

9

8

3

2

1

0

REQSTAMP
R-0h
23

22

21

20

13

12

REQSTAMP
R-0h
15

14

LIMITLO
R/W-0h
7

6

5

4
LIMITLO
R/W-0h

Table 10-77. ADCPPB4TRIPLO Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

REQSTAMP

R

0h

ADC Post Processing Block 4 Request Time Stamp. When a trigger
sets the associated SOC flag in the ADCSOCFLG1 register the
value of ADCCOUNTER.FREECOUNT is loaded into this bit field.
Reset type: SYSRSn

19-17

RESERVED

R

0h

Reserved

LSIGN

R/W

0h

Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit
field when in 16-bit ADC mode.
Reset type: SYSRSn

LIMITLO

R/W

0h

ADC Post Processing Block 4 Trip Low Limit. This value sets the
digital comparator trip low limit. In 16-bit mode all 17 bits will be
compared against the 17 bits of the PPBRESULT bit field of the
ADCPPB4RESULT register. In 12-bit mode bits 12:0 will be
compared against bits 12:0 of the PPBRSULT bit field of the
ADCPPB4RESULT register.
Reset type: SYSRSn

16

15-0

1552

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.64 ADCINLTRIM1 Register (Offset = 70h) [reset = 0h]
ADCINLTRIM1 is shown in Figure 10-88 and described in Table 10-78.
Return to Summary Table.
ADC Linearity Trim 1 Register
Figure 10-88. ADCINLTRIM1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INLTRIM31TO0
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 10-78. ADCINLTRIM1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

INLTRIM31TO0

R/W

0h

ADC Linearity Trim Bits 31-0.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1553

Registers

www.ti.com

10.4.2.65 ADCINLTRIM2 Register (Offset = 72h) [reset = 0h]
ADCINLTRIM2 is shown in Figure 10-89 and described in Table 10-79.
Return to Summary Table.
ADC Linearity Trim 2 Register
Figure 10-89. ADCINLTRIM2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INLTRIM63TO32
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 10-79. ADCINLTRIM2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

INLTRIM63TO32

R/W

0h

ADC Linearity Trim Bits 63-32.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: SYSRSn

1554

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.66 ADCINLTRIM3 Register (Offset = 74h) [reset = 0h]
ADCINLTRIM3 is shown in Figure 10-90 and described in Table 10-80.
Return to Summary Table.
ADC Linearity Trim 3 Register
Figure 10-90. ADCINLTRIM3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INLTRIM95TO64
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 10-80. ADCINLTRIM3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

INLTRIM95TO64

R/W

0h

ADC Linearity Trim Bits 95-64.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1555

Registers

www.ti.com

10.4.2.67 ADCINLTRIM4 Register (Offset = 76h) [reset = 0h]
ADCINLTRIM4 is shown in Figure 10-91 and described in Table 10-81.
Return to Summary Table.
ADC Linearity Trim 4 Register
Figure 10-91. ADCINLTRIM4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INLTRIM127TO96
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 10-81. ADCINLTRIM4 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

INLTRIM127TO96

R/W

0h

ADC Linearity Trim Bits 127-96.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: SYSRSn

1556

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.2.68 ADCINLTRIM5 Register (Offset = 78h) [reset = 0h]
ADCINLTRIM5 is shown in Figure 10-92 and described in Table 10-82.
Return to Summary Table.
ADC Linearity Trim 5 Register
Figure 10-92. ADCINLTRIM5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INLTRIM159TO128
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 10-82. ADCINLTRIM5 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

INLTRIM159TO128

R/W

0h

ADC Linearity Trim Bits 159-128.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1557

Registers

www.ti.com

10.4.2.69 ADCINLTRIM6 Register (Offset = 7Ah) [reset = 0h]
ADCINLTRIM6 is shown in Figure 10-93 and described in Table 10-83.
Return to Summary Table.
ADC Linearity Trim 6 Register
Figure 10-93. ADCINLTRIM6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INLTRIM191TO160
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 10-83. ADCINLTRIM6 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

INLTRIM191TO160

R/W

0h

ADC Linearity Trim Bits 191-160.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: SYSRSn

1558

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1559

Registers

www.ti.com

10.4.3 ADC_RESULT_REGS Registers
Table 10-84 lists the memory-mapped registers for the ADC_RESULT_REGS. All register offset
addresses not listed in Table 10-84 should be considered as reserved locations and the register contents
should not be modified.
Table 10-84. ADC_RESULT_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

ADCRESULT0

ADC Result 0 Register

Go

1h

ADCRESULT1

ADC Result 1 Register

Go

2h

ADCRESULT2

ADC Result 2 Register

Go

3h

ADCRESULT3

ADC Result 3 Register

Go

4h

ADCRESULT4

ADC Result 4 Register

Go

5h

ADCRESULT5

ADC Result 5 Register

Go

6h

ADCRESULT6

ADC Result 6 Register

Go

7h

ADCRESULT7

ADC Result 7 Register

Go

8h

ADCRESULT8

ADC Result 8 Register

Go

9h

ADCRESULT9

ADC Result 9 Register

Go

Ah

ADCRESULT10

ADC Result 10 Register

Go

Bh

ADCRESULT11

ADC Result 11 Register

Go

Ch

ADCRESULT12

ADC Result 12 Register

Go

Dh

ADCRESULT13

ADC Result 13 Register

Go

Eh

ADCRESULT14

ADC Result 14 Register

Go

Fh

ADCRESULT15

ADC Result 15 Register

Go

10h

ADCPPB1RESULT

ADC Post Processing Block 1 Result Register

Go

12h

ADCPPB2RESULT

ADC Post Processing Block 2 Result Register

Go

14h

ADCPPB3RESULT

ADC Post Processing Block 3 Result Register

Go

16h

ADCPPB4RESULT

ADC Post Processing Block 4 Result Register

Go

Complex bit access types are encoded to fit into small table cells. Table 10-85 shows the codes that are
used for access types in this section.
Table 10-85. ADC_RESULT_REGS Access Type Codes
Access Type

Code

Description

R

Read

Read Type
R

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

1560

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.1 ADCRESULT0 Register (Offset = 0h) [reset = 0h]
ADCRESULT0 is shown in Figure 10-94 and described in Table 10-86.
Return to Summary Table.
ADC Result 0 Register
Figure 10-94. ADCRESULT0 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-86. ADCRESULT0 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 0. 16-bit ADC result. After the ADC completes a
conversion of SOC0, the digital result is placed in this bit field.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1561

Registers

www.ti.com

10.4.3.2 ADCRESULT1 Register (Offset = 1h) [reset = 0h]
ADCRESULT1 is shown in Figure 10-95 and described in Table 10-87.
Return to Summary Table.
ADC Result 1 Register
Figure 10-95. ADCRESULT1 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-87. ADCRESULT1 Register Field Descriptions
Bit
15-0

1562

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 1. 16-bit ADC result. After the ADC completes a
conversion of SOC1, the digital result is placed in this bit field.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.3 ADCRESULT2 Register (Offset = 2h) [reset = 0h]
ADCRESULT2 is shown in Figure 10-96 and described in Table 10-88.
Return to Summary Table.
ADC Result 2 Register
Figure 10-96. ADCRESULT2 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-88. ADCRESULT2 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 2. 16-bit ADC result. After the ADC completes a
conversion of SOC2, the digital result is placed in this bit field.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1563

Registers

www.ti.com

10.4.3.4 ADCRESULT3 Register (Offset = 3h) [reset = 0h]
ADCRESULT3 is shown in Figure 10-97 and described in Table 10-89.
Return to Summary Table.
ADC Result 3 Register
Figure 10-97. ADCRESULT3 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-89. ADCRESULT3 Register Field Descriptions
Bit
15-0

1564

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 3. 16-bit ADC result. After the ADC completes a
conversion of SOC3, the digital result is placed in this bit field.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.5 ADCRESULT4 Register (Offset = 4h) [reset = 0h]
ADCRESULT4 is shown in Figure 10-98 and described in Table 10-90.
Return to Summary Table.
ADC Result 4 Register
Figure 10-98. ADCRESULT4 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-90. ADCRESULT4 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 4. 16-bit ADC result. After the ADC completes a
conversion of SOC4, the digital result is placed in this bit field.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1565

Registers

www.ti.com

10.4.3.6 ADCRESULT5 Register (Offset = 5h) [reset = 0h]
ADCRESULT5 is shown in Figure 10-99 and described in Table 10-91.
Return to Summary Table.
ADC Result 5 Register
Figure 10-99. ADCRESULT5 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-91. ADCRESULT5 Register Field Descriptions
Bit
15-0

1566

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 5. 16-bit ADC result. After the ADC completes a
conversion of SOC5, the digital result is placed in this bit field.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.7 ADCRESULT6 Register (Offset = 6h) [reset = 0h]
ADCRESULT6 is shown in Figure 10-100 and described in Table 10-92.
Return to Summary Table.
ADC Result 6 Register
Figure 10-100. ADCRESULT6 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-92. ADCRESULT6 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 6. 16-bit ADC result. After the ADC completes a
conversion of SOC6, the digital result is placed in this bit field.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1567

Registers

www.ti.com

10.4.3.8 ADCRESULT7 Register (Offset = 7h) [reset = 0h]
ADCRESULT7 is shown in Figure 10-101 and described in Table 10-93.
Return to Summary Table.
ADC Result 7 Register
Figure 10-101. ADCRESULT7 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-93. ADCRESULT7 Register Field Descriptions
Bit
15-0

1568

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 7. 16-bit ADC result. After the ADC completes a
conversion of SOC7, the digital result is placed in this bit field.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.9 ADCRESULT8 Register (Offset = 8h) [reset = 0h]
ADCRESULT8 is shown in Figure 10-102 and described in Table 10-94.
Return to Summary Table.
ADC Result 8 Register
Figure 10-102. ADCRESULT8 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-94. ADCRESULT8 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 8. 16-bit ADC result. After the ADC completes a
conversion of SOC8, the digital result is placed in this bit field.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1569

Registers

www.ti.com

10.4.3.10 ADCRESULT9 Register (Offset = 9h) [reset = 0h]
ADCRESULT9 is shown in Figure 10-103 and described in Table 10-95.
Return to Summary Table.
ADC Result 9 Register
Figure 10-103. ADCRESULT9 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-95. ADCRESULT9 Register Field Descriptions
Bit
15-0

1570

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 9. 16-bit ADC result. After the ADC completes a
conversion of SOC9, the digital result is placed in this bit field.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.11 ADCRESULT10 Register (Offset = Ah) [reset = 0h]
ADCRESULT10 is shown in Figure 10-104 and described in Table 10-96.
Return to Summary Table.
ADC Result 10 Register
Figure 10-104. ADCRESULT10 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-96. ADCRESULT10 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 10. 16-bit ADC result. After the ADC completes a
conversion of SOC10, the digital result is placed in this bit field.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1571

Registers

www.ti.com

10.4.3.12 ADCRESULT11 Register (Offset = Bh) [reset = 0h]
ADCRESULT11 is shown in Figure 10-105 and described in Table 10-97.
Return to Summary Table.
ADC Result 11 Register
Figure 10-105. ADCRESULT11 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-97. ADCRESULT11 Register Field Descriptions
Bit
15-0

1572

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 11. 16-bit ADC result. After the ADC completes a
conversion of SOC11, the digital result is placed in this bit field.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.13 ADCRESULT12 Register (Offset = Ch) [reset = 0h]
ADCRESULT12 is shown in Figure 10-106 and described in Table 10-98.
Return to Summary Table.
ADC Result 12 Register
Figure 10-106. ADCRESULT12 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-98. ADCRESULT12 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 12. 16-bit ADC result. After the ADC completes a
conversion of SOC12, the digital result is placed in this bit field.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1573

Registers

www.ti.com

10.4.3.14 ADCRESULT13 Register (Offset = Dh) [reset = 0h]
ADCRESULT13 is shown in Figure 10-107 and described in Table 10-99.
Return to Summary Table.
ADC Result 13 Register
Figure 10-107. ADCRESULT13 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-99. ADCRESULT13 Register Field Descriptions
Bit
15-0

1574

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 13. 16-bit ADC result. After the ADC completes a
conversion of SOC13, the digital result is placed in this bit field.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.15 ADCRESULT14 Register (Offset = Eh) [reset = 0h]
ADCRESULT14 is shown in Figure 10-108 and described in Table 10-100.
Return to Summary Table.
ADC Result 14 Register
Figure 10-108. ADCRESULT14 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-100. ADCRESULT14 Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 14. 16-bit ADC result. After the ADC completes a
conversion of SOC14, the digital result is placed in this bit field.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1575

Registers

www.ti.com

10.4.3.16 ADCRESULT15 Register (Offset = Fh) [reset = 0h]
ADCRESULT15 is shown in Figure 10-109 and described in Table 10-101.
Return to Summary Table.
ADC Result 15 Register
Figure 10-109. ADCRESULT15 Register
15

14

13

12

11

10

9

8
7
RESULT
R-0h

6

5

4

3

2

1

0

Table 10-101. ADCRESULT15 Register Field Descriptions
Bit
15-0

1576

Field

Type

Reset

Description

RESULT

R

0h

ADC Result 15. 16-bit ADC result. After the ADC completes a
conversion of SOC15, the digital result is placed in this bit field.
Reset type: SYSRSn

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.17 ADCPPB1RESULT Register (Offset = 10h) [reset = 0h]
ADCPPB1RESULT is shown in Figure 10-110 and described in Table 10-102.
Return to Summary Table.
ADC Post Processing Block 1 Result Register
Figure 10-110. ADCPPB1RESULT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SIGN
R-0h

9 8 7 6
PPBRESULT
R-0h

5

4

3

2

1

0

Table 10-102. ADCPPB1RESULT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

SIGN

R

0h

Sign Extended Bits. These bits reflect the same value as bit 16.
NOTE: If the conversion associated with this Post Processing Block
is a 12-bit conversion, the SIGN bits extend down to bit 12, and all
reflect the same value as bit 12.
Reset type: SYSRSn

15-0

PPBRESULT

R

0h

ADC Post Processing Block Result 1. The result of the
offset/reference subtraction post conversion processing is stored in
this register.
NOTE: If the conversion associated with this Post Processing Block
is a 12-bit conversion, the PPBRESULT bits are limited to bits 11:0.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1577

Registers

www.ti.com

10.4.3.18 ADCPPB2RESULT Register (Offset = 12h) [reset = 0h]
ADCPPB2RESULT is shown in Figure 10-111 and described in Table 10-103.
Return to Summary Table.
ADC Post Processing Block 2 Result Register
Figure 10-111. ADCPPB2RESULT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SIGN
R-0h

9 8 7 6
PPBRESULT
R-0h

5

4

3

2

1

0

Table 10-103. ADCPPB2RESULT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

SIGN

R

0h

Sign Extended Bits. These bits reflect the same value as bit 16.
NOTE: If the conversion associated with this Post Processing Block
is a 12-bit conversion, the SIGN bits extend down to bit 12, and all
reflect the same value as bit 12.
Reset type: SYSRSn

15-0

PPBRESULT

R

0h

ADC Post Processing Block Result 2. The result of the
offset/reference subtraction post conversion processing is stored in
this register.
NOTE: If the conversion associated with this Post Processing Block
is a 12-bit conversion, the PPBRESULT bits are limited to bits 11:0.
Reset type: SYSRSn

1578

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

10.4.3.19 ADCPPB3RESULT Register (Offset = 14h) [reset = 0h]
ADCPPB3RESULT is shown in Figure 10-112 and described in Table 10-104.
Return to Summary Table.
ADC Post Processing Block 3 Result Register
Figure 10-112. ADCPPB3RESULT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SIGN
R-0h

9 8 7 6
PPBRESULT
R-0h

5

4

3

2

1

0

Table 10-104. ADCPPB3RESULT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

SIGN

R

0h

Sign Extended Bits. These bits reflect the same value as bit 16.
NOTE: If the conversion associated with this Post Processing Block
is a 12-bit conversion, the SIGN bits extend down to bit 12, and all
reflect the same value as bit 12.
Reset type: SYSRSn

15-0

PPBRESULT

R

0h

ADC Post Processing Block Result 3. The result of the
offset/reference subtraction post conversion processing is stored in
this register.
NOTE: If the conversion associated with this Post Processing Block
is a 12-bit conversion, the PPBRESULT bits are limited to bits 11:0.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Analog-to-Digital Converter (ADC)

1579

Registers

www.ti.com

10.4.3.20 ADCPPB4RESULT Register (Offset = 16h) [reset = 0h]
ADCPPB4RESULT is shown in Figure 10-113 and described in Table 10-105.
Return to Summary Table.
ADC Post Processing Block 4 Result Register
Figure 10-113. ADCPPB4RESULT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SIGN
R-0h

9 8 7 6
PPBRESULT
R-0h

5

4

3

2

1

0

Table 10-105. ADCPPB4RESULT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

SIGN

R

0h

Sign Extended Bits. These bits reflect the same value as bit 16.
NOTE: If the conversion associated with this Post Processing Block
is a 12-bit conversion, the SIGN bits extend down to bit 12, and all
reflect the same value as bit 12.
Reset type: SYSRSn

15-0

PPBRESULT

R

0h

ADC Post Processing Block Result 4. The result of the
offset/reference subtraction post conversion processing is stored in
this register.
NOTE: If the conversion associated with this Post Processing Block
is a 12-bit conversion, the PPBRESULT bits are limited to bits 11:0.
Reset type: SYSRSn

1580

Analog-to-Digital Converter (ADC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 11
SPRUHM8G – December 2013 – Revised September 2017

Buffered Digital to Analog Converter (DAC)
The buffered digital to analog converter (DAC) is an analog module that can output a programmable,
arbitrary reference voltage.
Topic

11.1
11.2
11.3
11.4

...........................................................................................................................
Buffered Digital to Analog Converter (DAC) Overview .........................................
Using the DAC ................................................................................................
Lock Registers ...............................................................................................
Registers .......................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

1582
1582
1583
1583

Buffered Digital to Analog Converter (DAC)

Copyright © 2013–2017, Texas Instruments Incorporated

Page

1581

Buffered Digital to Analog Converter (DAC) Overview

www.ti.com

11.1 Buffered Digital to Analog Converter (DAC) Overview
The buffered DAC module consists of an internal reference DAC and an analog output buffer that is
capable of driving an external load. An integrated pull-down resistor on the DAC output helps to provide a
known pin voltage when the output buffer is disabled. This pull-down resistor cannot be disabled and
remains as a passive component on the pin, even for other shared pinmux functions. Software writes to
the DAC value register can take effect immediately or can be synchronized with PWMSYNC events.

11.1.1 Features
Each buffered DAC has the following features:
• 12-bit programmable internal DAC
• Selectable reference voltage
• Pull-down resistor on output
• Ability to synchronize with PWMSYNC

11.1.2 Block Diagram
The block diagram for the buffered DAC is shown in Figure 11-1.
Figure 11-1. DAC Module Block Diagram
DACCTL[DACREFSEL]

VDAC 0
VREFHI 1

SYSCLK
DACVALS

>

VDDA

DACCTL[LOADMODE]

D Q

0

12-bit
DAC

DACVALA
1

D Q
PWMSYNC1 0
PWMSYNC2 1
PWMSYNC3 2
...
…
PWMSYNCn n-1

Buffer
RPD

>

VSSA
VSSA

DACCTL[SYNCSEL]

11.2 Using the DAC
The reference voltage for the internal DAC is selectable between the VDAC and VREFHI.
Two sets of DACVAL registers are present in the buffered DAC module: DACVALA and DACVALS.
DACVALA is a read-only register that actively controls the DAC value. DACVALS is a writable shadow
register that loads into DACVALA either immediately or synchronized with the next PWMSYNC event.
The ideal output of the internal DAC can be calculated as follows:
VDAC =

DACVALA * DACREF
4096

The Buffered DAC output buffer may exhibit non-linear behavior near the supply rails (VDDA/VSSA). See
the device datasheet to determine the valid operating range of the Buffered DAC.
1582

Buffered Digital to Analog Converter (DAC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Lock Registers

www.ti.com

11.3 Lock Registers
A DACLOCK register is provided to prevent spurious writes from modifying the DACCTL, DACVALS, and
DACOUTEN registers. Once a register is protected through DACLOCK, write access will be locked out
until the device is reset.

11.4 Registers
11.4.1 DAC Base Addresses
Table 11-1. DAC Base Address Table
Start Address

End Address

DacaRegs

Device Registers

DAC_REGS

Register Name

0x0000_5C00

0x0000_5C0F

DacbRegs

DAC_REGS

0x0000_5C10

0x0000_5C1F

DaccRegs

DAC_REGS

0x0000_5C20

0x0000_5C2F

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Buffered Digital to Analog Converter (DAC)

Copyright © 2013–2017, Texas Instruments Incorporated

1583

Registers

www.ti.com

11.4.2 DAC_REGS Registers
Table 11-2 lists the memory-mapped registers for the DAC_REGS. All register offset addresses not listed
in Table 11-2 should be considered as reserved locations and the register contents should not be
modified.
Table 11-2. DAC_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

DACREV

DAC Revision Register

1h

DACCTL

DAC Control Register

2h

DACVALA

DAC Value Register - Active

3h

DACVALS

DAC Value Register - Shadow

4h

DACOUTEN

DAC Output Enable Register

EALLOW

Go

5h

DACLOCK

DAC Lock Register

EALLOW

Go

6h

DACTRIM

DAC Trim Register

EALLOW

Go

Go
EALLOW

Go
Go
Go

Complex bit access types are encoded to fit into small table cells. Table 11-3 shows the codes that are
used for access types in this section.
Table 11-3. DAC_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type
R
Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

1584

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

Buffered Digital to Analog Converter (DAC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

11.4.2.1 DACREV Register (Offset = 0h) [reset = 0h]
DACREV is shown in Figure 11-2 and described in Table 11-4.
Return to Summary Table.
DAC Revision Register
Figure 11-2. DACREV Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
REV
R-0h

Table 11-4. DACREV Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

REV

R

0h

DAC Revision
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Buffered Digital to Analog Converter (DAC)

Copyright © 2013–2017, Texas Instruments Incorporated

1585

Registers

www.ti.com

11.4.2.2 DACCTL Register (Offset = 1h) [reset = 0h]
DACCTL is shown in Figure 11-3 and described in Table 11-5.
Return to Summary Table.
DAC Control Register
Figure 11-3. DACCTL Register
15

14

13

12

11

10

9

8

3
RESERVED
R-0h

2
LOADMODE
R/W-0h

1
RESERVED
R-0h

0
DACREFSEL
R/W-0h

RESERVED
R-0h
7

6

5

4

SYNCSEL
R/W-0h

Table 11-5. DACCTL Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-4

SYNCSEL

R/W

0h

DAC PWMSYNC select. Determines which PWMSYNC signal will
update the DACVALA register.
Where n represents the maximum number of PWMSYNC signals
available on the device:
0 PWMSYNC1
1 PWMSYNC2
2 PWMSYNC3
...
n-1 PWMSYNCn
Reset type: SYSRSn

3

RESERVED

R

0h

Reserved

2

LOADMODE

R/W

0h

DACVALA load mode. Determines when the DACVALA register is
updated with the value from DACVALS.
0 Load on next SYSCLK
1 Load on next PWMSYNC specified by SYNCSEL
Reset type: SYSRSn

1

RESERVED

R

0h

Reserved

0

DACREFSEL

R/W

0h

DAC reference select. Selects which voltage references are used by
the DAC.
0 VDAC/VSSA are the reference voltages
1 ADC VREFHI/VREFLO are the reference voltages
Reset type: SYSRSn

1586

Buffered Digital to Analog Converter (DAC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

11.4.2.3 DACVALA Register (Offset = 2h) [reset = 0h]
DACVALA is shown in Figure 11-4 and described in Table 11-6.
Return to Summary Table.
DAC Value Register - Active
Figure 11-4. DACVALA Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DACVALA
R-0h
5

4

3

2

DACVALA
R-0h

Table 11-6. DACVALA Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DACVALA

R

0h

Active output code currently driven by the DAC
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Buffered Digital to Analog Converter (DAC)

Copyright © 2013–2017, Texas Instruments Incorporated

1587

Registers

www.ti.com

11.4.2.4 DACVALS Register (Offset = 3h) [reset = 0h]
DACVALS is shown in Figure 11-5 and described in Table 11-7.
Return to Summary Table.
DAC Value Register - Shadow
Figure 11-5. DACVALS Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DACVALS
R/W-0h
5

4

3

2

DACVALS
R/W-0h

Table 11-7. DACVALS Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DACVALS

R/W

0h

Shadow output code to be loaded into DACVALA
Reset type: SYSRSn

1588

Buffered Digital to Analog Converter (DAC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

11.4.2.5 DACOUTEN Register (Offset = 4h) [reset = 0h]
DACOUTEN is shown in Figure 11-6 and described in Table 11-8.
Return to Summary Table.
DAC Output Enable Register
Figure 11-6. DACOUTEN Register
15

14

13

12

11

10

9

8

3

2

1

0
DACOUTEN
R/W-0h

RESERVED
R-0h
7

6

5

4
RESERVED
R-0h

Table 11-8. DACOUTEN Register Field Descriptions
Field

Type

Reset

Description

15-1

Bit

RESERVED

R

0h

Reserved

0

DACOUTEN

R/W

0h

DAC output enable
0 DAC output is disabled
1 DAC output is enabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Buffered Digital to Analog Converter (DAC)

Copyright © 2013–2017, Texas Instruments Incorporated

1589

Registers

www.ti.com

11.4.2.6 DACLOCK Register (Offset = 5h) [reset = 0h]
DACLOCK is shown in Figure 11-7 and described in Table 11-9.
Return to Summary Table.
DAC Lock Register
Figure 11-7. DACLOCK Register
15

14

13

12

11

10

9

8

3

2
DACOUTEN
R/WSOnce-0h

1
DACVAL
R/WSOnce-0h

0
DACCTL
R/WSOnce-0h

RESERVED
R-0h
7

6

5
RESERVED
R-0h

4

Table 11-9. DACLOCK Register Field Descriptions
Field

Type

Reset

Description

15-3

Bit

RESERVED

R

0h

Reserved

2

DACOUTEN

R/WSOnce

0h

Lock write-access to the DACOUTEN register.
0 DACOUTEN register is not locked. Write 0 to this bit has no effect.
1 DACOUTEN register is locked. Only a system reset can clear this
bit.
Reset type: SYSRSn

1

DACVAL

R/WSOnce

0h

Lock write-access to the DACVALS register.
0 DACVALS register is not locked. Write 0 to this bit has no effect.
1 DACVALS register is locked. Only a system reset can clear this bit.
Reset type: SYSRSn

0

DACCTL

R/WSOnce

0h

Lock write-access to the DACCTL register.
0 DACCTL register is not locked. Write 0 to this bit has no effect.
1 DACCTL register is locked. Only a system reset can clear this bit.
Reset type: SYSRSn

1590

Buffered Digital to Analog Converter (DAC)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

11.4.2.7 DACTRIM Register (Offset = 6h) [reset = 0h]
DACTRIM is shown in Figure 11-8 and described in Table 11-10.
Return to Summary Table.
DAC Trim Register
Figure 11-8. DACTRIM Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

RESERVED
R-0h
5

4

3

2

OFFSET_TRIM
R/W-0h

Table 11-10. DACTRIM Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-8

RESERVED

R

0h

Reserved

7-0

OFFSET_TRIM

R/W

0h

DAC Offset Trim.
This register should not be modified unless specifically indicated by
TI Errata or other documentation. Modifying the contents of this
register could cause this module to operate outside of datasheet
specifications.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Buffered Digital to Analog Converter (DAC)

Copyright © 2013–2017, Texas Instruments Incorporated

1591

Chapter 12
SPRUHM8G – December 2013 – Revised September 2017

Comparator Subsystem (CMPSS)
The Comparator Subsystem (CMPSS) consists of analog comparators and supporting circuits that are
useful for power applications such as peak current mode control, switched-mode power, power factor
correction, and voltage trip monitoring.
Topic

12.1
12.2
12.3
12.4
12.5
12.6

1592

...........................................................................................................................
CMPSS Overview ............................................................................................
Comparator ....................................................................................................
Internal DAC ...................................................................................................
Ramp Generator .............................................................................................
Digital Filter....................................................................................................
Registers .......................................................................................................

Comparator Subsystem (CMPSS)

Page

1593
1594
1594
1595
1596
1598

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CMPSS Overview

www.ti.com

12.1

CMPSS Overview
The comparator subsystem is built around a number of modules, each comprising a pair of analog
comparators. Comparators are denoted "H" or "L" within each module. Each comparator generates a
digital output which indicates whether the voltage on the positive input is greater than the voltage on the
negative input. The positive input of the comparator is always driven from an external pin, but the negative
input can be driven by either an external pin or by an internal programmable 12-bit DAC. Each comparator
output passes through a programmable digital filter that can remove spurious trip signals. A ramp
generator circuit is optionally available to control the internal DAC value for one comparator in the
subsystem.

12.1.1 Features
CMPSS Features
• Each CMPSS module includes:
– Two analog comparators
– Two programmable 12-bit DACs
– One ramp generator
– Two digital filters
• Ability to synchronize with PWMSYNC
• Option for negative input of comparator to be driven by an external signal or by an internal DAC
• Option to choose between VDDA or VDAC to be the DAC reference voltage

12.1.2 Block Diagram
The block diagram for the CMPSS is shown in Figure 12-1.
• CTRIPx(x= "H" or "L") signals are connected to the ePWM X-BAR for ePWM trip response. See the
ePWM chapter for more details on the ePWM X-BAR mux configuration.
• CTRIPxOUT signals are connected to the Output X-BAR for external signaling. See the GPIO chapter
for more details on the Output X-BAR mux configuration.
Figure 12-1. CMPSS Module Block Diagram
COMPCTL[CTRIPHSEL]

COMPSTS[COMPHSTS]

SYSCLK >

CMPINxP

D Q

0

D Q

1

0

DACHVALA

12-bit
DACH

SYSCLK

+

>

DACHVALS

COMPDACCTL[SWLOADSEL]

COMPH
0

0
1

COMPCTL[COMPHINV]

Ramp Generator

0

To EPWM X-BAR

S
COMPCTL[CTRIPOUTHSEL]

R Q

0

OR

1
COMPCTL[COMPHSOURCE]

1

COMPDACCTL[DACSOURCE]

COMPSTS[COMPHLATCH]

COMPCTL[ASYNCHEN]
COMPSTSCLR[HSYNCCLREN]

PWMSYNC1 0
PWMSYNC2 1
PWMSYNC3 2
...
…
PWMSYNCn n-1

CTRIPH

2 CTRIPOUTH
3 To OUTPUT X-BAR

Digital
Filter

D Q

_

CMPINxN 1

>

ASYNCH
0
SYNCH
1
COMPSTS[COMPHSTS]

0
PWMSYNC

OR
COMPSTSCLR[HLATCHCLR]

0
1

COMPSTSCLR[LSYNCCLREN]
COMPCTL[ASYNCLEN]

COMPSTSCLR[LLATCHCLR]

OR

COMPDACCTL[RAMPSOURCE]
0

CMPINxP

SYSCLK >
DACLVALS

D Q

0

D Q

1

DACLVALA

12-bit
DACL

+
0

D Q

_

1

>

CMPINxN 1

>

COMPCTL[COMPLINV]

COMPDACCTL[SWLOADSEL]

OR

1

COMPL
0

COMPSTS[COMPLLATCH]

0

SYSCLK

COMPCTL[COMPLSOURCE]

R Q
Digital
Filter

COMPCTL[CTRIPLSEL]

S
3 CTRIPL
COMPSTS[COMPLSTS]
2 To EPWM X-BAR
SYNCL 1
CTRIPOUTL
ASYNCL
0 To OUTPUT X-BAR
COMPCTL[CTRIPOUTLSEL]

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1593

Comparator

www.ti.com

12.2 Comparator
The comparator generates a digital output which indicates whether the voltage on the positive input is
greater than the voltage on the negative input.
Figure 12-2. Comparator Digital Output
A

+
Comparator

B

Output

_

Voltages

Output

Voltage A > Voltage B

1

Voltage A < Voltage B

0

12.3 Internal DAC
Each 12-bit internal DAC can be configured to drive the reference voltage into the negative input of its
respective comparator. The DAC output is internal only and cannot be observed externally.
Two sets of DACxVAL registers are present for each DAC: DACxVALA and DACxVALS. DACxVALA is a
read-only register that actively controls the DAC value. DACxVALS is a writable shadow register that
loads into DACxVALA either immediately or synchronized with the next PWMSYNC event. The high DAC
(DACH) can optionally source its DACHVALA value from the Ramp Generator instead of DACHVALS.
The operating range of the DACs is bounded by its high and low reference voltages. The high voltage
reference is VDDA by default, but it can be configured to be VDAC if desired.
Figure 12-3. DAC Reference Select

VDDA 0
VDAC 1

DACHVALA

12-bit To COMPH
DACH

DACLVALA

12-bit To COMPL
DACL

VSSA
The ideal output voltage of the DACs can be calculated as follows:
Figure 12-4. Output Voltage Calculation
VDACx =

1594

Comparator Subsystem (CMPSS)

DACxVALA * DACREF
4096

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Ramp Generator

www.ti.com

12.4 Ramp Generator
When selected, the ramp generator produces a falling-ramp reference for DACH. In this mode, the DAC
uses the most significant 12 bits of the RAMPSTS countdown register as its input.
The RAMPSTS register is loaded from RAMPMAXREFS when the selected PWMSYNC signal is received.
After the PWMSYNC event, the value of RAMPDECVALA is subtracted from RAMPSTS on every
SYSCLK cycle thereafter.
The RAMPDLYA register serves as a delay counter to hold off the RAMPSTS subtraction. When a
PWMSYNC signal is received, the value of RAMPDLYA is decremented by one for every SYSCLK cycle
until the register reaches zero. RAMPSTS subtraction will only begin when RAMPDLYA is zero.
When the ramp generator is first enabled by setting DACSOURCE = 1, the value of RAMPSTS is loaded
from RAMPMAXREFS, and the register remains static until the first PWMSYNC signal is received.
If the COMPHSTS bit is set by the comparator while the ramp generator is active, the RAMPSTS register
will reset to the value of RAMPMAXREFA and remain static until the next PWMSYNC signal is received. If
the value of RAMPSTS reaches zero, the RAMPSTS register will remain static at zero until the next
PWMSYNC is received. The ramp generator is illustrated in Figure 12-5.
Figure 12-5. Ramp Generator
SYSCLK
COMPSTS[COMPHSTS]
COMPCTL[COMPHINV]

AND

PWMSYNC

CLOCK

RAMP_RESET

ENABLE

1

>
RAMP_RESET
COMPDACCTL[RAMPLOADSEL]

AND

RAMPDLYS

D Q

RAMPDLYA

SYSCLK
CLOCK

COMPDACCTL[DACSOURCE]
PWMSYNC

>

OR

RAMPDECVALS

D Q

0

RAMPDECVALA

PWMSYNC
ENABLE

X
0
RAMP_RESET

RAMPMAXREFS

D Q

>

>
RAMPMAXREFA

PWMSYNC

0

D Q

1

1
0

RAMPSTS (16b)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

START
STOP

COMPDACCTL[RAMPLOADSEL]

To DACHVALA
D Q
COMPDACCTL[DACSOURCE]

OR

>

PWMSYNC

OR

RAMP_RESET
COMPDACCTL[DACSOURCE]

The ramp generator behavior is further illustrated in Figure 12-6.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1595

Digital Filter

www.ti.com

Figure 12-6. Ramp Generator Behavior

PWMSYNC

0xFFFF
RAMPMAXREFA

RAMPMAXREFA

RAMPSTS

RAMPMAXREFA

CMPINxP

RAMPMAXREFA

0x0000

COMPHSTS
12.5 Digital Filter
The digital filter works on a window of FIFO samples (SAMPWIN + 1) taken from the input. The filter
output resolves to the majority value of the sample window, where majority is defined by the threshold
(THRESH) value. If the majority threshold is not satisfied, the filter output remains unchanged.
For proper operation, the value of THRESH must be greater than SAMPWIN / 2.
A prescale function (CLKPRESCALE) determines the filter sampling rate, where the filter FIFO captures
one sample every CLKPRESCALE system clocks. Old data from the FIFO is discarded.
A conceptual model of the digital filter is shown in Figure 12-7.
Figure 12-7. Digital Filter Behavior

Digital Filter
Filter Input

Data Latch

32-bit FIFO
0 1 2 3 4 5 6 7 8 9 …... 28 29 30 31

Filter Output
[Data Discard]

SAMPWIN = 9

CLKPRESCALE

SYSCLK

Equivalent C code of the filter implementation is shown below:
if (FILTER_OUTPUT == 0) {
if (Num_1s_in_SAMPWIN >= THRESH) {
FILTER_OUTPUT = 1;
1596

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Digital Filter

www.ti.com
}
}
else {
if (Num_0s_in_SAMPWIN >= THRESH) {
FILTER_OUTPUT = 0;
}
}

To ensure proper operation of the digital filter, the following initialization sequence is recommended:
1. Configure and enable the comparator for operation
2. Configure the digital filter parameters for operation
• Set SAMPWIN for the number of samples to monitor in FIFO window
• Set THRESH for the threshold required for majority qualification
• Set CLKPRESCALE for the digital filter clock prescale value
3. Initialize the sample values in the digital FIFO window by setting FILINIT
4. Clear COMPSTS latch via COMPSTSCLR if the latched path is desired
5. Configure the CTRIP and CTRIPOUT signal paths
6. If desired, configure the ePWM and GPIO modules to accept the filtered signals

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1597

Registers

www.ti.com

12.6 Registers
12.6.1 CMPSS Base Addresses
Table 12-1. CMPSS Base Address Table
Device Registers

1598

Register Name

Start Address

End Address

Cmpss1Regs

CMPSS_REGS

0x0000_5C80

0x0000_5C9F

Cmpss2Regs

CMPSS_REGS

0x0000_5CA0

0x0000_5CBF

Cmpss3Regs

CMPSS_REGS

0x0000_5CC0

0x0000_5CDF

Cmpss4Regs

CMPSS_REGS

0x0000_5CE0

0x0000_5CFF

Cmpss5Regs

CMPSS_REGS

0x0000_5D00

0x0000_5D1F

Cmpss6Regs

CMPSS_REGS

0x0000_5D20

0x0000_5D3F

Cmpss7Regs

CMPSS_REGS

0x0000_5D40

0x0000_5D5F

Cmpss8Regs

CMPSS_REGS

0x0000_5D60

0x0000_5D7F

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2 CMPSS_REGS Registers
Table 12-2 lists the memory-mapped registers for the CMPSS_REGS. All register offset addresses not
listed in Table 12-2 should be considered as reserved locations and the register contents should not be
modified.
Table 12-2. CMPSS_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

COMPCTL

CMPSS Comparator Control Register

EALLOW

Go

1h

COMPHYSCTL

CMPSS Comparator Hysteresis Control Register

EALLOW

Go

2h

COMPSTS

CMPSS Comparator Status Register

3h

COMPSTSCLR

CMPSS Comparator Status Clear Register

EALLOW

Go

4h

COMPDACCTL

CMPSS DAC Control Register

EALLOW

Go

6h

DACHVALS

CMPSS High DAC Value Shadow Register

Go

7h

DACHVALA

CMPSS High DAC Value Active Register

Go

Go

8h

RAMPMAXREFA

CMPSS Ramp Max Reference Active Register

Go

Ah

RAMPMAXREFS

CMPSS Ramp Max Reference Shadow Register

Go

Ch

RAMPDECVALA

CMPSS Ramp Decrement Value Active Register

Go

Eh

RAMPDECVALS

CMPSS Ramp Decrement Value Shadow
Register

Go

10h

RAMPSTS

CMPSS Ramp Status Register

Go

12h

DACLVALS

CMPSS Low DAC Value Shadow Register

Go

13h

DACLVALA

CMPSS Low DAC Value Active Register

Go

14h

RAMPDLYA

CMPSS Ramp Delay Active Register

Go

15h

RAMPDLYS

CMPSS Ramp Delay Shadow Register

Go

16h

CTRIPLFILCTL

CTRIPL Filter Control Register

EALLOW

Go

17h

CTRIPLFILCLKCTL

CTRIPL Filter Clock Control Register

EALLOW

Go

18h

CTRIPHFILCTL

CTRIPH Filter Control Register

EALLOW

Go

19h

CTRIPHFILCLKCTL

CTRIPH Filter Clock Control Register

EALLOW

Go

1Ah

COMPLOCK

CMPSS Lock Register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 12-3 shows the codes that are
used for access types in this section.
Table 12-3. CMPSS_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1599

Registers

www.ti.com

Table 12-3. CMPSS_REGS Access Type
Codes (continued)
Access Type

1600

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.1 COMPCTL Register (Offset = 0h) [reset = 0h]
COMPCTL is shown in Figure 12-8 and described in Table 12-4.
Return to Summary Table.
CMPSS Comparator Control Register
Figure 12-8. COMPCTL Register
15
COMPDACE

14
ASYNCLEN

13
12
CTRIPOUTLSEL

R/W-0h

R/W-0h

R/W-0h

7
RESERVED

6
ASYNCHEN

5
4
CTRIPOUTHSEL

R-0h

R/W-0h

R/W-0h

11
CTRIPLSEL

10

9
COMPLINV

R/W-0h

R/W-0h

3
CTRIPHSEL

2

1
COMPHINV

R/W-0h

R/W-0h

8
COMPLSOUR
CE
R/W-0h
0
COMPHSOUR
CE
R/W-0h

Table 12-4. COMPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

COMPDACE

R/W

0h

Comparator/DAC enable.
0 Comparator/DAC disabled
1 Comparator/DAC enabled
Reset type: SYSRSn

14

ASYNCLEN

R/W

0h

Low comparator asynchronous path enable. Allows asynchronous
comparator output to feed into OR gate with latched digital filter
signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3.
0 Asynchronous comparator output does not feed into OR gate with
latched digital filter output
1 Asynchronous comparator output feeds into OR gate with latched
digital filter output
Reset type: SYSRSn

13-12

CTRIPOUTLSEL

R/W

0h

Low comparator CTRIPOUTL source select.
0 Asynchronous comparator output drives CTRIPOUTL
1 Synchronous comparator output drives CTRIPOUTL
2 Output of digital filter drives CTRIPOUTL
3 Latched output of digital filter drives CTRIPOUTL
Reset type: SYSRSn

11-10

CTRIPLSEL

R/W

0h

Low comparator CTRIPL source select.
0 Asynchronous comparator output drives CTRIPL
1 Synchronous comparator output drives CTRIPL
2 Output of digital filter drives CTRIPL
3 Latched output of digital filter drives CTRIPL
Reset type: SYSRSn

9

COMPLINV

R/W

0h

Low comparator output invert.
0 Output of comparator is not inverted
1 Output of comparator is inverted
Reset type: SYSRSn

8

COMPLSOURCE

R/W

0h

Low comparator input source.
0 Inverting input of comparator driven by internal DAC
1 Inverting input of comparator driven through external pin
Reset type: SYSRSn

7

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1601

Registers

www.ti.com

Table 12-4. COMPCTL Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

ASYNCHEN

R/W

0h

High comparator asynchronous path enable. Allows asynchronous
comparator output to feed into OR gate with latched digital filter
signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3.
0 Asynchronous comparator output does not feed into OR gate with
latched digital filter output
1 Asynchronous comparator output feeds into OR gate with latched
digital filter output
Reset type: SYSRSn

5-4

CTRIPOUTHSEL

R/W

0h

High comparator CTRIPOUTH source select.
0 Asynchronous comparator output drives CTRIPOUTH
1 Synchronous comparator output drives CTRIPOUTH
2 Output of digital filter drives CTRIPOUTH
3 Latched output of digital filter drives CTRIPOUTH
Reset type: SYSRSn

3-2

CTRIPHSEL

R/W

0h

High comparator CTRIPH source select.
0 Asynchronous comparator output drives CTRIPH
1 Synchronous comparator output drives CTRIPH
2 Output of digital filter drives CTRIPH
3 Latched output of digital filter drives CTRIPH
Reset type: SYSRSn

1

COMPHINV

R/W

0h

High comparator output invert.
0 Output of comparator is not inverted
1 Output of comparator is inverted
Reset type: SYSRSn

0

COMPHSOURCE

R/W

0h

High comparator input source.
0 Inverting input of comparator driven by internal DAC
1 Inverting input of comparator driven through external pin
Reset type: SYSRSn

1602

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.2 COMPHYSCTL Register (Offset = 1h) [reset = 0h]
COMPHYSCTL is shown in Figure 12-9 and described in Table 12-5.
Return to Summary Table.
CMPSS Comparator Hysteresis Control Register
Figure 12-9. COMPHYSCTL Register
15

14

13

12

11

10

9

8

3

2

1
COMPHYS
R/W-0h

0

RESERVED
R-0h
7

6

5
RESERVED
R-0h

4

Table 12-5. COMPHYSCTL Register Field Descriptions
Field

Type

Reset

Description

15-3

Bit

RESERVED

R

0h

Reserved

2-0

COMPHYS

R/W

0h

Comparator hysteresis. Sets the amount of hysteresis on the
comparator inputs.
0 None
1 Set to typical hysteresis
2 Set to 2x of typical hysteresis
3 Set to 3x of typical hysteresis
4 Set to 4x of typical hysteresis
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1603

Registers

www.ti.com

12.6.2.3 COMPSTS Register (Offset = 2h) [reset = 0h]
COMPSTS is shown in Figure 12-10 and described in Table 12-6.
Return to Summary Table.
CMPSS Comparator Status Register
Figure 12-10. COMPSTS Register
15

14

13

12

11

10

9
COMPLLATCH
R-0h

8
COMPLSTS
R-0h

4

3

2

1
COMPHLATCH
R-0h

0
COMPHSTS
R-0h

RESERVED
R-0h
7

6

5
RESERVED
R-0h

Table 12-6. COMPSTS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

9

COMPLLATCH

R

0h

Latched value of low comparator digital filter output
Reset type: SYSRSn

8

COMPLSTS

R

0h

Low comparator digital filter output
Reset type: SYSRSn

7-2

RESERVED

R

0h

Reserved

1

COMPHLATCH

R

0h

Latched value of high comparator digital filter output
Reset type: SYSRSn

0

COMPHSTS

R

0h

High comparator digital filter output
Reset type: SYSRSn

15-10

1604

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.4 COMPSTSCLR Register (Offset = 3h) [reset = 0h]
COMPSTSCLR is shown in Figure 12-11 and described in Table 12-7.
Return to Summary Table.
CMPSS Comparator Status Clear Register
Figure 12-11. COMPSTSCLR Register
15

14

13
RESERVED
R-0h

12

11

10
LSYNCCLREN
R/W-0h

9
LLATCHCLR
R=0/W=1-0h

8
RESERVED
R-0h

7

6

5
RESERVED
R-0h

4

3

2
HSYNCCLREN
R/W-0h

1
HLATCHCLR
R=0/W=1-0h

0
RESERVED
R-0h

Table 12-7. COMPSTSCLR Register Field Descriptions
Bit
15-11
10

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

LSYNCCLREN

R/W

0h

Low comparator latch PWMSYNC clear. Enable PWMSYNC reset of
low comparator digital filter output latch COMPSTS[COMPLLATCH].
0 PWMSYNC will not reset latch
1 PWMSYNC will reset latch
Reset type: SYSRSn

9

LLATCHCLR

R=0/W=1

0h

Low comparator latch software clear. Perform software reset of low
comparator digital filter output latch COMPSTS[COMPLLATCH].
Reads always return 0.
0 No effect
1 Generate a single pulse of latch reset signal for
COMPSTS[COMPLLATCH]
Reset type: SYSRSn

8-3
2

RESERVED

R

0h

Reserved

HSYNCCLREN

R/W

0h

High comparator latch PWMSYNC clear. Enable PWMSYNC reset of
high comparator digital filter output latch
COMPSTS[COMPHLATCH].
0 PWMSYNC will not reset latch
1 PWMSYNC will reset latch
Reset type: SYSRSn

1

HLATCHCLR

R=0/W=1

0h

High comparator latch software clear. Perform software reset of high
comparator digital filter output latch COMPSTS[COMPHLATCH].
Reads always return 0.
0 No effect
1 Generate a single pulse of latch reset signal for
COMPSTS[COMPHLATCH]
Reset type: SYSRSn

0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1605

Registers

www.ti.com

12.6.2.5 COMPDACCTL Register (Offset = 4h) [reset = 0h]
COMPDACCTL is shown in Figure 12-12 and described in Table 12-8.
Return to Summary Table.
CMPSS DAC Control Register
Figure 12-12. COMPDACCTL Register
15

14

13

12

11

10

9

8

2

1

RAMPSOURCE

0
DACSOURCE

R/W-0h

R/W-0h

FREESOFT
R/W-0h
7
SWLOADSEL
R/W-0h

6
RAMPLOADSE
L
R/W-0h

RESERVED
R-0h
5
SELREF

4

3

R/W-0h

Table 12-8. COMPDACCTL Register Field Descriptions
Bit
15-14

Field

Type

Reset

Description

FREESOFT

R/W

0h

Free-run or software-run emulation behavior. Behavior of the ramp
generator during emulation suspend.
00b Ramp generator stops immediately during emulation suspend
01b Ramp generator completes current ramp and stops at next
PWMSYNC during emulation suspend
1Xb Ramp generator runs freely
Reset type: SYSRSn

13-8
7

RESERVED

R

0h

Reserved

SWLOADSEL

R/W

0h

Software load select. Determines whether DACxVALA is updated
from DACxVALS on SYSCLK or PWMSYNC.
0 DACxVALA is updated from DACxVALS on SYSCLK
1 DACxVALA is updated from DACxVALS on PWMSYNC
Reset type: SYSRSn

6

RAMPLOADSEL

R/W

0h

Ramp load select. Determines whether RAMPSTS is updated from
RAMPMAXREFA or RAMPMAXREFS when
COMPSTS[COMPHSTS] is triggered.
0 RAMPSTS is loaded from RAMPMAXREFA
1 RAMPSTS is loaded from RAMPMAXREFS
Reset type: SYSRSn

5

SELREF

R/W

0h

DAC reference select. Determines which voltage supply is used as
the reference for the internal comparator DACs.
0 VDDA is the voltage reference for the DAC
1 VDAC is the voltage reference for the DAC
Reset type: SYSRSn

4-1

RAMPSOURCE

R/W

0h

Ramp generator source select. Determines which PWMSYNC signal
is used within the CMPSS module.
Where n represents the maximum number of PWMSYNC signals
available on the device:
0 PWMSYNC1
1 PWMSYNC2
2 PWMSYNC3
...
n-1 PWMSYNCn
Reset type: SYSRSn

1606

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 12-8. COMPDACCTL Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

DACSOURCE

R/W

0h

DAC source select. Determines whether DACHVALA is updated
from DACHVALS or from the ramp generator.
0 DACHVALA is updated from DACHVALS
1 DACHVALA is updated from the ramp generator
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1607

Registers

www.ti.com

12.6.2.6 DACHVALS Register (Offset = 6h) [reset = 0h]
DACHVALS is shown in Figure 12-13 and described in Table 12-9.
Return to Summary Table.
CMPSS High DAC Value Shadow Register
Figure 12-13. DACHVALS Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DACVAL
R/W-0h
5

4

3

2

DACVAL
R/W-0h

Table 12-9. DACHVALS Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DACVAL

R/W

0h

High DAC shadow value. When COMPDACCTL[DACSOURCE]=0,
the value of DACHVALS is loaded into DACHVALA on the trigger
signal selected by COMPDACCTL[SWLOADSEL].
Reset type: SYSRSn

1608

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.7 DACHVALA Register (Offset = 7h) [reset = 0h]
DACHVALA is shown in Figure 12-14 and described in Table 12-10.
Return to Summary Table.
CMPSS High DAC Value Active Register
Figure 12-14. DACHVALA Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DACVAL
R-0h
5

4

3

2

DACVAL
R-0h

Table 12-10. DACHVALA Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DACVAL

R

0h

High DAC active value. Value that is actively driven by the high
DAC.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1609

Registers

www.ti.com

12.6.2.8 RAMPMAXREFA Register (Offset = 8h) [reset = 0h]
RAMPMAXREFA is shown in Figure 12-15 and described in Table 12-11.
Return to Summary Table.
CMPSS Ramp Max Reference Active Register
Figure 12-15. RAMPMAXREFA Register
15

14

13

12

11

10

9

8
7
RAMPMAXREF
R-0h

6

5

4

3

2

1

0

Table 12-11. RAMPMAXREFA Register Field Descriptions
Bit
15-0

1610

Field

Type

Reset

Description

RAMPMAXREF

R

0h

Ramp maximum reference active value. Latched value to be loaded
into ramp generator RAMPSTS.
Reset type: SYSRSn

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.9 RAMPMAXREFS Register (Offset = Ah) [reset = 0h]
RAMPMAXREFS is shown in Figure 12-16 and described in Table 12-12.
Return to Summary Table.
CMPSS Ramp Max Reference Shadow Register
Figure 12-16. RAMPMAXREFS Register
15

14

13

12

11

10

9

8
7
RAMPMAXREF
R/W-0h

6

5

4

3

2

1

0

Table 12-12. RAMPMAXREFS Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RAMPMAXREF

R/W

0h

Ramp maximum reference shadow. Unlatched value to be loaded
into ramp generator RAMPSTS.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1611

Registers

www.ti.com

12.6.2.10 RAMPDECVALA Register (Offset = Ch) [reset = 0h]
RAMPDECVALA is shown in Figure 12-17 and described in Table 12-13.
Return to Summary Table.
CMPSS Ramp Decrement Value Active Register
Figure 12-17. RAMPDECVALA Register
15

14

13

12

11

10

9

8
7
RAMPDECVAL
R-0h

6

5

4

3

2

1

0

Table 12-13. RAMPDECVALA Register Field Descriptions
Bit
15-0

1612

Field

Type

Reset

Description

RAMPDECVAL

R

0h

Ramp decrement value active. Latched value that will be subtracted
from RAMPSTS.
Reset type: SYSRSn

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.11 RAMPDECVALS Register (Offset = Eh) [reset = 0h]
RAMPDECVALS is shown in Figure 12-18 and described in Table 12-14.
Return to Summary Table.
CMPSS Ramp Decrement Value Shadow Register
Figure 12-18. RAMPDECVALS Register
15

14

13

12

11

10

9

8
7
RAMPDECVAL
R/W-0h

6

5

4

3

2

1

0

Table 12-14. RAMPDECVALS Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

RAMPDECVAL

R/W

0h

Ramp decrement value shadow. Unlatched value to be loaded into
RAMPDECVALA.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1613

Registers

www.ti.com

12.6.2.12 RAMPSTS Register (Offset = 10h) [reset = 0h]
RAMPSTS is shown in Figure 12-19 and described in Table 12-15.
Return to Summary Table.
CMPSS Ramp Status Register
Figure 12-19. RAMPSTS Register
15

14

13

12

11

10

9

8
7
RAMPVALUE
R-0h

6

5

4

3

2

1

0

Table 12-15. RAMPSTS Register Field Descriptions
Bit
15-0

1614

Field

Type

Reset

Description

RAMPVALUE

R

0h

Ramp value. Present value of ramp generator.
Reset type: SYSRSn

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.13 DACLVALS Register (Offset = 12h) [reset = 0h]
DACLVALS is shown in Figure 12-20 and described in Table 12-16.
Return to Summary Table.
CMPSS Low DAC Value Shadow Register
Figure 12-20. DACLVALS Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DACVAL
R/W-0h
5

4

3

2

DACVAL
R/W-0h

Table 12-16. DACLVALS Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DACVAL

R/W

0h

Low DAC shadow value. value to be loaded into DACLVALA on the
trigger signal selected by COMPDACCTL[SWLOADSEL].
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1615

Registers

www.ti.com

12.6.2.14 DACLVALA Register (Offset = 13h) [reset = 0h]
DACLVALA is shown in Figure 12-21 and described in Table 12-17.
Return to Summary Table.
CMPSS Low DAC Value Active Register
Figure 12-21. DACLVALA Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

DACVAL
R-0h
5

4

3

2

DACVAL
R-0h

Table 12-17. DACLVALA Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-0

DACVAL

R

0h

Low DAC active value. Value that is actively driven by the low DAC.
Reset type: SYSRSn

1616

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.15 RAMPDLYA Register (Offset = 14h) [reset = 0h]
RAMPDLYA is shown in Figure 12-22 and described in Table 12-18.
Return to Summary Table.
CMPSS Ramp Delay Active Register
Figure 12-22. RAMPDLYA Register
15

14
RESERVED
R-0h

13

12

7

6

5

4

11

10
DELAY
R-0h

9

8

3

2

1

0

DELAY
R-0h

Table 12-18. RAMPDLYA Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R

0h

Reserved

12-0

DELAY

R

0h

Ramp delay active value. Latched value of the number of cycles to
delay the start of the ramp generator decrementer after a
PWMSYNC is received.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1617

Registers

www.ti.com

12.6.2.16 RAMPDLYS Register (Offset = 15h) [reset = 0h]
RAMPDLYS is shown in Figure 12-23 and described in Table 12-19.
Return to Summary Table.
CMPSS Ramp Delay Shadow Register
Figure 12-23. RAMPDLYS Register
15

14
RESERVED
R-0h

13

12

7

6

5

4

11

10
DELAY
R/W-0h

9

8

3

2

1

0

DELAY
R/W-0h

Table 12-19. RAMPDLYS Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R

0h

Reserved

12-0

DELAY

R/W

0h

Ramp delay shadow value. Unlatched value to be loaded into
RAMPDLYA.
Reset type: SYSRSn

1618

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.17 CTRIPLFILCTL Register (Offset = 16h) [reset = 0h]
CTRIPLFILCTL is shown in Figure 12-24 and described in Table 12-20.
Return to Summary Table.
CTRIPL Filter Control Register
Figure 12-24. CTRIPLFILCTL Register
15
FILINIT
R=0/W=1-0h

14
RESERVED
R-0h

13

12

11
THRESH
R/W-0h

10

7

6

5

4

3

2

SAMPWIN
R/W-0h

9

8
SAMPWIN
R/W-0h

1

0

RESERVED
R-0h

Table 12-20. CTRIPLFILCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

FILINIT

R=0/W=1

0h

Low filter initialization.
0 No effect
1 Initialize all samples to the filter input value
Reset type: SYSRSn

14

RESERVED

R

0h

Reserved

13-9

THRESH

R/W

0h

Low filter majority voting threshold. At least THRESH samples of the
opposite state must appear within the sample window in order for the
output to change state.
Reset type: SYSRSn

8-4

SAMPWIN

R/W

0h

Low filter sample window size. Number of samples to monitor is
SAMPWIN+1.
Reset type: SYSRSn

3-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1619

Registers

www.ti.com

12.6.2.18 CTRIPLFILCLKCTL Register (Offset = 17h) [reset = 0h]
CTRIPLFILCLKCTL is shown in Figure 12-25 and described in Table 12-21.
Return to Summary Table.
CTRIPL Filter Clock Control Register
Figure 12-25. CTRIPLFILCLKCTL Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6

5

8
CLKPRESCALE
R/W-0h

4

3

2

1

0

CLKPRESCALE
R/W-0h

Table 12-21. CTRIPLFILCLKCTL Register Field Descriptions
Bit
15-10
9-0

1620

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

CLKPRESCALE

R/W

0h

Low filter sample clock prescale. Number of system clocks between
samples.
Reset type: SYSRSn

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.19 CTRIPHFILCTL Register (Offset = 18h) [reset = 0h]
CTRIPHFILCTL is shown in Figure 12-26 and described in Table 12-22.
Return to Summary Table.
CTRIPH Filter Control Register
Figure 12-26. CTRIPHFILCTL Register
15
FILINIT
R=0/W=1-0h

14
RESERVED
R-0h

13

12

11
THRESH
R/W-0h

10

7

6

5

4

3

2

SAMPWIN
R/W-0h

9

8
SAMPWIN
R/W-0h

1

0

RESERVED
R-0h

Table 12-22. CTRIPHFILCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

FILINIT

R=0/W=1

0h

High filter initialization.
0 No effect
1 Initialize all samples to the filter input value
Reset type: SYSRSn

14

RESERVED

R

0h

Reserved

13-9

THRESH

R/W

0h

High filter majority voting threshold. At least THRESH samples of the
opposite state must appear within the sample window in order for the
output to change state.
Reset type: SYSRSn

8-4

SAMPWIN

R/W

0h

High filter sample window size. Number of samples to monitor is
SAMPWIN+1.
Reset type: SYSRSn

3-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1621

Registers

www.ti.com

12.6.2.20 CTRIPHFILCLKCTL Register (Offset = 19h) [reset = 0h]
CTRIPHFILCLKCTL is shown in Figure 12-27 and described in Table 12-23.
Return to Summary Table.
CTRIPH Filter Clock Control Register
Figure 12-27. CTRIPHFILCLKCTL Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6

5

8
CLKPRESCALE
R/W-0h

4

3

2

1

0

CLKPRESCALE
R/W-0h

Table 12-23. CTRIPHFILCLKCTL Register Field Descriptions
Bit
15-10
9-0

1622

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

CLKPRESCALE

R/W

0h

High filter sample clock prescale. Number of system clocks between
samples.
Reset type: SYSRSn

Comparator Subsystem (CMPSS)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

12.6.2.21 COMPLOCK Register (Offset = 1Ah) [reset = 0h]
COMPLOCK is shown in Figure 12-28 and described in Table 12-24.
Return to Summary Table.
CMPSS Lock Register
Figure 12-28. COMPLOCK Register
15

14

13

12

11

10

9

8

3
CTRIP
R/WSOnce-0h

2
DACCTL
R/WSOnce-0h

1
COMPHYSCTL
R/WSOnce-0h

0
COMPCTL
R/WSOnce-0h

RESERVED
R-0h
7

6
RESERVED
R-0h

5

4
RESERVED
R-0h

Table 12-24. COMPLOCK Register Field Descriptions
Field

Type

Reset

Description

15-5

Bit

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

CTRIP

R/WSOnce

0h

Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL
registers.
0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked.
Write 0 to this bit has no effect.
1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only
a system reset can clear this bit.
Reset type: SYSRSn

2

DACCTL

R/WSOnce

0h

Lock write-access to the DACCTL register.
0 DACCTL register is not locked. Write 0 to this bit has no effect.
1 DACCTL register is locked. Only a system reset can clear this bit.
Reset type: SYSRSn

1

COMPHYSCTL

R/WSOnce

0h

Lock write-access to the COMPHYSCTL register.
0 COMPHYSCTL register is not locked. Write 0 to this bit has no
effect.
1 COMPHYSCTL register is locked. Only a system reset can clear
this bit.
Reset type: SYSRSn

0

COMPCTL

R/WSOnce

0h

Lock write-access to the COMPCTL register.
0 COMPCTL register is not locked. Write 0 to this bit has no effect.
1 COMPCTL register is locked. Only a system reset can clear this
bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Subsystem (CMPSS)

1623

Chapter 13
SPRUHM8G – December 2013 – Revised September 2017

Sigma Delta Filter Module (SDFM)
This chapter describes the sigma delta filter module (SDFM). SDFM is a four-channel digital filter
designed specifically for current measurement and resolver position decoding in motor control
applications. Each channel can receive an independent delta-sigma (ΔΣ) modulator bit stream. The bit
streams are processed by four individually-programmable digital decimation filters. The filter set includes a
fast comparator for immediate digital threshold comparisons for over-current and under-current monitoring.
Topic

13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8

1624

...........................................................................................................................
SDFM Module Overview ...................................................................................
Configuring Device Pins ..................................................................................
Input Control Unit ...........................................................................................
Comparator Unit .............................................................................................
Data Filter Unit ...............................................................................................
Interrupt Unit ..................................................................................................
Register Descriptions ......................................................................................
Registers .......................................................................................................

Sigma Delta Filter Module (SDFM)

Page

1625
1627
1628
1629
1630
1634
1636
1637

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

SDFM Module Overview

www.ti.com

13.1 SDFM Module Overview
Figure 13-1 shows the SDFM CPU interfaces:
Figure 13-1. Sigma Delta Filter Module (SDFM) CPU Interface
CPUSEL4.SD1
CPU1.SYSCLK
CPU1.SYSRSn

Arbiter

CPU1.PCLKCR6.SD1/SD2
C
P
U
1

CPU1.CLA1

SYSCLK

CPU1.DMA

SYSRSn

CPU1.SECMSEL

M
U
X

CPU2.SYSCLK

R
e
g
i
s
t
e
r
s

SDINT1
SDFM
SDINT2

CPU1/2.ePIE

CPU2.SYSRSn

Arbiter

CPU2.PCLKCR6.SD1/SD2
C
P
U
2

CPU2.CLA1

SD-D1 to 8

CPU2.DMA

SD-C1 to 8
GPIO MUX

CPU2.SECMSEL
CPUSEL4.SD2

13.1.1 SDFM Features
The SDFM features include:
• 8 external pins per SDFM module
– 4 sigma delta data input pins per SDFM module (SD-Dx, where x = 1 to 4)
– 4 sigma delta clock input pins per SDFM module (SD-Cx, where x = 1 to 4)
• 4 different configurable modulator clock modes:
– Mode 0: Modulator clock rate equals modulator data rate
– Mode 1: Modulator clock rate running at half the modulator data rate
– Mode 2: Modulator data is Manchester encoded. Modulator clock not required.
– Mode 3: Modulator clock rate is double that of modulator data rate
• 4 independent configurable comparator units per SDFM module:
– 4 different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Ability to detect over and under value conditions
– OSR value for comparator programmable from 1 to 32
• 4 independent configurable sinc filter units per SDFM module:
– 4 different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– OSR value for filter unit programmable from 1 to 256
– Ability to enable / disable individual filter module
– Ability to synchronize all the 4 independent filters of a SDFM module using Master Filter Enable
(MFE) bit (or) using PWM signals.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1625

SDFM Module Overview

•
•

www.ti.com

Data filter output can be represented in either 16 bits (or) 32 bits
PWMs can be used to generate a modulator clock for sigma delta modulators

13.1.2 Block Diagram
Figure 13-2 shows the SDFM module block diagram. The SDFM port operation is configured and
controlled by the registers listed in Table 13-1.
Figure 13-2. Sigma Delta Filter Module (SDFM) Block Diagram
SDFM- Sigma Delta Filter Module
G4
Streams

Filter Channel 1
R

Comparator filter

SD1_D1
Input
Ctrl

SD1_C1

Data filter

SD1INT

IEL
IEH

Interrupt
Unit

SD2INT
PIE

R

FILRES

PWM11.CMPC
Filter Channel 2

SD1_D2
SD1_C2

FILRES

SD1_D3

Filter Channel 3

Register
Map

Data bus

SD1_C3
FILRES

PWM11.CMPD
SD1_D4
SD1_C4

Filter Channel 4
SD1FLT1.IEH
SD1FLT1.IEL
SD1FLT2.IEH
SD1FLT2.IEL

FILRES

GPIO
MUX
SDFM- Sigma Delta Filter Module
G4
Streams

Output
XBar

Filter Channel 1
R

Comparator filter

SD2_D1
SD2_C1

SD1FLT3.IEH
SD1FLT3.IEL
SD1FLT4.IEH
SD1FLT4.IEL

Input
Ctrl

Data filter
Data filter

IEL
IEH

SD2FLT1.IEH
SD2FLT1.IEL
SD2FLT2.IEH
SD2FLT2.IEL

Interrupt
Unit

R

FILRES

SD2FLT3.IEH
SD2FLT3.IEL
SD2FLT4.IEH
SD2FLT4.IEL

PWM12.CMPC
SD2_D2
SD2_C2

Filter Channel 2
FILRES

SD2_D3
SD2_C3

Filter Channel 3
PWM12.CMPD

Register
Map

Data bus

FILRES

SD2_D4
SD2_C4

Filter Channel 4
FILRES

Each SDFM module has four independent filter modules. These filter modules are identical and can be
configured independently. Each individual filter module has the following units:
• Input Control unit
• Data filter unit
• Comparator unit
Figure 13-3 shows the block diagram of one filter module. When the SDDFPARMx.SDSYNCEN bit is set,
the filter reset signal ( SDSYNC) from the PWM module can be used to synchronize filters. It should be
noted that the SDSYNC input is ONLY connected to the main Data Filter Unit and NOT the comparator,
and that the reset function is limited to resetting the OSR counter. The SDSYNC input does not reset the
data registers in the Filter Unit. Figure 13-4 shows how the PWM signals are connected to sigma delta
module. In this device, PWM11 can be used to reset SDFM1 module and PWM12 can be used to reset
SDFM2 module.

1626

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Configuring Device Pins

www.ti.com

Figure 13-3. Block Diagram of One Filter Module
CLK_out

SDSYNCEN (SDDFPARMx)

SDSYNC

Comparator Unit
HTL

To Interrupt
Unit

IEHx
SINCx

IELx
LTL

CLK_out

Input Control
Unit

Data Filter Unit

SD-Dx

SINCx
Data
Register

Decoding
SD-Cx

SDSYNC

Figure 13-4. Typical PWM Interface to Sigma Delta Filter Module
SDFM

PWM

SDSYNC
PWMn.CMPC

Filter 1
Filter 2

SDSYNC
PWMn.CMPD

Filter 3
Filter 4

Note: When using PWM11 (or) PWM12 for SDFM filter synchronization, users MUST ensure that ONLY
ONE CMPC (or) CMPD event will be generated per PWM timer period. Using PWM in up-count (or) downcount mode would automatically ensure that you get ONLY one PWMC (or) PWMD event. But, if the user
wishes to use up-down count mode, then they need to make sure that only one CMPC (or) CMPD event
per PWM cycle is generated otherwise filter synchronizer will corrupt SDFM timing by providing two pulses
per PWM cycle.

13.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1627

Input Control Unit

www.ti.com

13.3 Input Control Unit
The input control unit receives sigma delta modulated data and a sigma delta modulated clock. The
modulated data received is captured and passed onto the data filter unit and comparator unit. This unit
can be configured to receive the modulated data in four different modes. Table 13-1 shows how
SDCTLPARMx.MOD bits can be configured in these four different modes.
Table 13-1. Modulator Clock Modes
MODULATOR MODE [MOD]
Mode0

(2)

1628

DESCRIPTION
The modulator clock is running with the modulator data rate. The modulator data is
strobed at every rising edge of the modulator clock.

Mode1 (1)

The modulator clock is running with half of the modulator data rate. The modulator data
is strobed at every edge of the modulator clock.

Mode2 (1)

The modulator clock is off and the modulator data is Manchester-encoded. (2)

Mode3
(1)

(1)

(1)

The modulator clock is running with double of the modulator data rate. The modulator
data is strobed at every other positive modulator clock edge.

Irrespective of which SDFM mode is selected, care MUST be taken to guarantee that differential input voltage applied to the
sigma delta modulator stays within linear full scale range specified in the sigma delta modulator data sheet
Because of the inherent architecture of the Manchester decoder, input data rate of mode2 supported dependents on SYSCLK
frequency. Please refer to the SDFM Electrical Data and Timing in device data sheet.

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Comparator Unit

www.ti.com

Figure 13-5. Operation Diagrams

MCLK

MDAT

MCLK

MDAT

When MOD=2, data and modulated clock signals are encoded into modulated data as shown in Figure 135. In this mode, the clock input SDCLKx.pin should be left floating. The input control unit performs
continuous automatic calibration to achieve optimum decoding performance.

13.4 Comparator Unit
An independent comparator unit allows the user to monitor input conditions with a fast settling time without
sacrificing input measurement resolution. The comparator filter is a configurable sinc filter which supports
the following filter types:- Sinc1, Sinc2, Sinc3 and Sincfast filter. Comparator filter OSR (COSR) value can
be configured from 1 to 32. With Sinc3 as filter type and OSR = 32, a maximum 15-bit output width of
32,768 can be achieved. The output of the filter is compared with two programmed threshold levels to

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1629

Data Filter Unit

www.ti.com

detect over- and under-value conditions. But output of the comparator filter cannot be read out of the filter.
The comparator unit can be configured by high- and low-level Threshold registers (SDCMPHx and
SDCMPLx) for each individual filter module. When an over- or under-value condition occurs, appropriate
bits in SDIFLG (Interrupt Flag) register are set and then this register can be polled to see which condition
caused interrupt signal.
The comparator filter unit and the data filter unit differ in the way they handle input data. The comparator
filter unit translates a low input signal to a '0' and a high input signal to a '1', whereas the data filter unit
uses '–1' and '1'. The resulting calculations give only positive values for the output of the comparator filter.
The data representation is straight binary . Table 13-2 and Figure 13-6 show the different full-scale values
that the comparator filter can store using different oversampling ratios.
Table 13-2. Peak Data Values for Different OSR/Filter Combinations
OSR

Sinc1

Sinc2

Sinc3

Sincfast

x

0 to x

0 to x2

0 to x3

0 to 2x2

4

0 to 4

0 to 16

0 to 64

0 to 32
0 to 128

8

0 to 8

0 to 64

0 to 512

16

0 to 16

0 to 256

0 to 4096

0 to 512

32

0 to 32

0 to 1024

0 to 32,768

0 to 2048

Figure 13-6. Comparator Filter Resolution
100000
Sinc

3

10000

Resolution

Sincfast
1000
Sinc

2

100
Sinc

10

1
0

2

4

6

1

8 10 12 14 16 18 20 22 24 26 28 30 32
Oversampling Ratio

In order to achieve the maximum value, the delta-sigma modulator is operated at absolute maximum
positive or negative full-scale, which is outside of the recommended full-scale range of 80% of most deltasigma modulators.

13.5 Data Filter Unit
The data filter is a configurable sinc filter which supports the following filter types: Sinc1, Sinc2, Sinc3 and
Sincfast filter. The data filter OSR (DOSR) value can be configured from 1 to 256. Figure 13-7 illustrates
the frequency response of each type of filter when DOSR = 32 and modulator rate = 10 MHz.

1630

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Data Filter Unit

www.ti.com

Figure 13-7. Frequency Response of Various Sinc Filters

The user can achieve a higher resolution by increasing the data filter oversampling ratio (DOSR) but this
would reduce the data rate of the data filter. Table 13-3 shows the peak data for different filter type or
DOSR combinations and Figure 13-8 shows the relationship between the DOSR and filter resolution. The
highest resolution for any given DOSR can be achieved by using the Sinc3 filter and the highest possible
resolution can be achieved with DOSR = 256 and Sinc3 filter.
Table 13-3. Peak Data Values for Different DOSR/Filter Combinations
DOSR

Sinc1

Sinc2
2

Sinc3
3

Sincfast
2

x

x

x

x

2x

4

–4 to 4

–16 to 16

–64 to 64

–32 to 32

8

–8 to 8

–64 to 64

–512 to 512

–128 to 128

16

–16 to 16

–256 to 256

–4096 to 4096

–512 to 512

32

–32 to 32

–1024 to 1024

–32,768 to 32,768

–2048 to 2048

64

–64 to 64

–4096 to 4096

–262,144 to 262,144

–8192 to 8192

128

–128 to 128

–16,384 to 16,384

–2,097,152 to 2,097,152 –32,768 to 32,768

256

–256 to 256

–65,536 to 65,536

–16,777,216 to
16,777,215

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

–131,072 to 131,072

Sigma Delta Filter Module (SDFM)

1631

Data Filter Unit

www.ti.com

Figure 13-8. Data Filter Resolution
100000000
Sinc

3

10000000
Sincfast

Resolution

1000000
100000
Sinc

10000

2

1000
Sinc

100

1

10
1
1

21 41

61 81 101 121 141 161 181 201 221 241 261
Oversampling Ratio

The data filter uses 25 bits to represent signed integer in two's complement format. The maximum
possible resolution gives a 25-bit word (-16,777,216 to +16,777,215). Note that this value is only reached
if the delta-sigma modulator is operated at absolute maximum positive or negative full-scale, which is
beyond the recommended full-scale range of 80% of most delta-sigma modulators. This value also does
not represent the resolution of the signal. The signal resolution is determined by the modulator, and
increasing the filter bit width will not offer any improved noise performance beyond the modulator
capabilities.

NOTE: Because of the inherent architecture of the Sinc filter (Sinc1, Sinc2, SincFast, and Sinc3),
the first few samples, depending upon the filter type, will be incorrect. Table 13-4 tabulates
the number of incorrect samples after the filter is enabled and configured. This is an
expected behavior.

Table 13-4. Number of Incorrect Samples Tabulated
Filter type

Number of incorrect samples after the filter is enabled and configured

Sinc1

No incorrect sample

Sinc2

The first sample of the Sinc2 filter is incorrect

SincFast
Sinc3

The first two samples of the SincFast filter are incorrect
The first two samples of the Sinc3 filter are incorrect

SDFM Comparator interrupts (IELx and IEHx) should be enabled only after providing sufficient settling
time to make sure the comparator filter does not trip on these incorrect samples. Therefore, SDFM
comparator interrupts (IELx and IEHx) should be enabled only after a sufficient delay is provided after the
comparator filter is configured. This sufficient delay is calculated by adding the latency of the comparator
filter and five SD-Cx clock cycles.
In case of the SDFM data filter, each time the filter is enabled or reconfigured, or the filter is reset by the
PWM sync pulse, or the filter is reset by SDDFPARMx.FEN, depending upon the filter type, there will be
some incorrect samples as mentioned in Table 13-4.

13.5.1 32-bit or 16-bit Data Filter Output Representation
The data filter output can be represented in either 32-bit (or) 16 bit format.
32-bit data filter representation:
• When SDDPARMx.DR = 1, data filter output is represented in 32-bit format. Writes to shift control bits
do not have any bearing on the output of the data filter in this configuration.
16-bit data filter representation:
1632

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Data Filter Unit

www.ti.com

•
•

By default, data filter output is represented in 16-bit format
When SDDPARMx.DR = 0, data filter output is represented in 16-bit format. But it is the responsibility
of the user to configure the corresponding shift control bits in the SDDPARMx register to control which
16-bit part of the 32-bit word is sent to the register map.
For example, for the data filter configuration below:
– Filter type = Sinc3
The data filter with a 25-bit signed output value can be in the range of –16,777,216 to 16,777,215. But,
16-bit signed output can support values only from –32,768 to 32,767. Therefore, it is required to
configure shift control bits (SDDPARMx.SH) to 9 to represent the data filter output correctly in 16-bit
format. Table 13-5 shows the configuration settings of shift control bits for different OSR and filter
types.
Table 13-5. Shift Control Bit Configuration Settings
OSR

SINC1

SINC2

SINCFAST

SINC3

1 to 31

0

0

0

0

32 to 40

0

0

0

1

41 to 50

0

0

0

2

51 to 63

0

0

0

3

64 to 80

0

0

0

4

81 to 101

0

0

0

5

102 to 127

0

0

0

6

128 to 161

0

0

1

7

162 to 181

0

0

1

8

182 to 203

0

1

2

8

204 to 255

0

1

2

9

256

0

2

3

9

WARNING
Configuring shift control bits incorrectly will result in getting
wrong 16-bit data filter output.

13.5.2 Data Rate and Latency of the Sinc Filter
The data rate of the sinc filter (filter throughput) represented in samples/sec can be calculated by the
formula shown here:
Data rate of Sinc filter =

Modulator data rate
OSR

The latency of the sinc filter represented in secs is defined as the amount of time taken by a sinc filter type
to deliver the correct filtered output upon initiation. For a given filter type, latency can be calculated as
shown in this equation:
Latency of Sinc filter =

Order of Sinc filter
Data rate of Sinc filter

Example configuration:
Sinc filter type
Modulator data rate
OSR

= sinc3
= 10 MHz
= 256

Data rate of Sinc Filter

= 10 MHz / 256 = 39.1 K samples / sec

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1633

Interrupt Unit

www.ti.com

Sinc filter latency

= 76.8 µs

Sinc filter type
Modulator data rate
OSR

= sinc2
= 10 MHz
= 256

Data rate of Sinc Filter
Sinc filter latency

= 10 MHz / 256 = 39.1 K samples / sec
=51.2 µs

13.6 Interrupt Unit
Figure 13-9 shows the structure of the interrupt unit. Each SDFM module can generate a CPU interrupt.
An SDFM interrupt can be triggered by any of these 16 interrupt sources:
• Four comparator low (IELx)
This interrupt source can be enabled when the master interrupt (SDCTL.MIE = 1) and the appropriate
individual filter interrupts are enabled (SDCPARMx.IEL = 1). The Comparator compares the
comparator filter output results continuously with the LLT threshold value. If the comparator filter output
<=LLT, the SDIFLG.IELx bit is set, triggering an under-value condition. This SDIFLG.IELx flag can be
reset if the corresponding bit in the SDIFLGCLR register is set and the interrupt source is no longer
active.
For example, since the comparator output changes only after every OSR SD-Cx clock cycle, writing to
the SDIFLGCLR.IELx bit will clear the flag for only one SYSCLK cycle. On the next cycle, since the
interrupt source is still active, the Comparator compares the comparator filter output with the lower
threshold and sets the SDIFLG.IELx bit again. To avoid this situation, the comparator lower threshold
setting should be changed to LLT = 0x0 before writing to the SDIFLGCLR.IELx bit.
• Four comparator high (IEHx)
This interrupt source can be enabled when the master interrupt (SDCTL.MIE = 1) and the appropriate
individual filter interrupt are enabled (SDCPARMx.IEH = 1). The Comparator compares the comparator
filter output results continuously with the HLT threshold value. If the comparator filter output >= HLT,
the SDIFLG.IEHx bit is set, triggering an over-value condition. This SDIFLG.IEHx flag can be reset if
the corresponding bit in SDIFLGCLR register is set and the interrupt source is no longer active.
For example, since the comparator output changes only after every OSR SD-Cx clock cycle, writing to
the SDIFLGCLR.IEHx bit will clear the flag for only one SYSCLK cycle. On the next cycle, since the
interrupt source is still active, the Comparator compares the comparator filter output with the higher
threshold and sets the SDIFLG.IEHx bit again. To avoid this situation, the comparator higher threshold
setting should be changed to HLT = 0x7FFF before writing to the SDIFLGCLR.IEHx bit.
• Four modulator failure (MFx)
This interrupt source can be enabled when the master interrupt (SDCTL.MIE = 1) and the appropriate
individual filter interrupt are enabled (SDCPARMx. MFIE = 1). When the modulator clock (SD-Cx) fails
or goes missing, the appropriate MFx flag bit is set in the Interrupt Flag Register (SDIFLG). This flag
will be reset if the Interrupt Register is cleared (by setting the corresponding bit in the SDIFLGCLR
register) and the interrupt source is no longer active. If the modulator clock is failing (when the
modulator clock is slower than 1/128th of the system clock SYSCLK), the appropriate MFx flag bit is
set if the appropriate modulator flag interrupt enable bit (MFIEx) and the master interrupt enable (MIE)
is set.
• Four filter data acknowledge (AFx)
This interrupt source can be enabled when the master interrupt (SDCTL.MIE = 1) and the appropriate
individual filter interrupts are enabled (SDDFPARMx. AE = 1). When the data filter generates new data,
the appropriate AFx flag bit is set in the Interrupt Flag Register (SDIFLG). This flag will be reset if the
Interrupt Register is cleared (by setting the corresponding bit in the SDIFLGCLR register) and the
interrupt source is no longer active. The acknowledge flags cannot be set if the data filter is disabled.
Each acknowledge flag can be disabled if the Acknowledge Enable control bit (AE) in the appropriate
Data Filter Parameter Register SDDFPARMx is set to low.
For some reason, if the user wishes to disable the data acknowledge event (AFx) and use a timer to
1634

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Interrupt Unit

www.ti.com

generate an interrupt at the data filter rate to read filter data results, there is a possibility of reading a
metastable filter data. In such cases, there are two possible options:
– Option 1: Make sure timer interrupts at a rate shown below
• Timer interrupt time interval = Latency of data filter + 5 SD clock cycles
– Option 2: If the user disables PIE interrupts from SDFM, or if the Master Interrupt Enable (MIE) bit
is disabled, a timer can be used to generate an interrupt at the data filter rate and filter data should
be read after the data acknowledge event (AFx) is set
Figure 13-9. SDFM Interrupt Unit
SDCMPHx.HLTx

+

SDCTL .MIE

COMPHx
S

-

SDCPARMx.IEH

R
Data

IEHx flag bit

Q

SDIFLGCLR.IEHx

+
SDCMPLx.LLTx

SDCTL .MIE

COMPLx

-

S
R

IELx flag bit

Q
SDCPARMx.IEL

SDIFLGCLR.IELx

SDCTL .MIE

Modulator failure

S

IEHx flag bit
MFx flag bit

Q

IELx flag bit
SDCPARMx.MFIE

R

SDINTy
MFx flag bit

SDIFLGCLR.MFx

AFx flag bit
SDCTL .MIE
New filter data

S
R

AFx flag bit

Q
SDSFPARM x.AE

Where,
x = 1 to 4
y = 1 (or) 2

SDIFLGCLR.AFx

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1635

Register Descriptions

www.ti.com

13.7 Register Descriptions
The register descriptions are shown in the following table and subsections.
Table 13-6. General Registers
Name

SDFM1 address

SDFM2 address

Size (x16)

Description

SDIFLG

0x5E00

0x5E80

2

Interrupt Flag Register

EALLOW?

SDIFLGCLR

0x5E02

0x5E82

2

Interrupt Flag Clear Register

SDCTL

0x5E04

0x5E84

1

SD Control Register

YES

SDMFILEN

0x5E06

0x5E86

1

SD Master Filter Enable

YES

Reserved

0x5E07

0x5E87

1

Reserved

Table 13-7. Filter 1 Registers
Name

SDFM1 address

SDFM2 address

Size (x16)

Description

EALLOW?

SDCTLPARM1

0x5E10

0x5E90

1

Control Parameter Register
for Ch1

YES

SDDFPARM1

0x5E11

0x5E91

1

Data Filter Parameter
Register for Ch1

YES

SDDPARM1

0x5E12

0x5E92

1

Integer Parameter Register
for Ch1

YES

SDCMPH1

0x5E13

0x5E93

1

High-level Threshold
Register for Ch1

YES

SDCMPL1

0x5E14

0x5E94

1

Low-level Threshold Register
for Ch1

YES

SDCPARM1

0x5E15

0x5E95

1

Comparator Parameter
Register for Ch1

YES

SDDATA1

0x5E16

0x5E96

2

Filter Data Register (16- or
32-bit) for Ch1

Table 13-8. Filter 2 Registers
Name

SDFM1 address

SDFM2 address

Size (x16)

Description

EALLOW?

SDCTLPARM2

0x5E20

0x5EA0

1

Control Parameter Register
for Ch2

YES

SDDFPARM2

0x5E21

0x5EA1

1

Data Filter Parameter
Register for Ch2

YES

SDDPARM2

0x5E22

0x5EA2

1

Integer Parameter Register
for Ch2

YES

SDCMPH2

0x5E23

0x5EA3

1

High-level Threshold
Register for Ch2

YES

SDCMPL2

0x5E24

0x5EA4

1

Low-level Threshold Register
for Ch2

YES

SDCPARM2

0x5E25

0x5EA5

1

Comparator Parameter
Register for Ch2

YES

SDDATA2

0x5E26

0x5EA6

2

Filter Data Register (16- or
32-bit) for Ch2

Table 13-9. Filter 3 Registers
Name

SDFM1 address

SDFM2 address

Size (x16)

Description

EALLOW?

SDCTLPARM3

0x5E30

0x5EB0

1

Control Parameter Register
for Ch3

YES

SDDFPARM3

0x5E31

0x5EB1

1

Data Filter Parameter
Register for Ch3

YES

SDDPARM3

0x5E32

0x5EB2

1

Integer Parameter Register
for Ch3

YES

1636Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 13-9. Filter 3 Registers (continued)
Name

SDFM1 address

SDFM2 address

Size (x16)

Description

EALLOW?

SDCMPH3

0x5E33

0x5EB3

1

High-level Threshold
Register for Ch3

YES

SDCMPL3

0x5E34

0x5EB4

1

Low-level Threshold Register
for Ch3

YES

SDCPARM3

0x5E35

0x5EB5

1

Comparator Parameter
Register for Ch3

YES

SDDATA3

0x5E36

0x5EB6

2

Filter Data Register (16- or
32-bit) for Ch3

Table 13-10. Filter 4 Registers
Name

SDFM1 address

SDFM2 address

Size (x16)

Description

EALLOW?

SDCTLPARM4

0x5E40

0x5EC0

1

Control Parameter Register
for Ch4

YES

SDDFPARM4

0x5E41

0x5EC1

1

Data Filter Parameter
Register for Ch4

YES

SDDPARM4

0x5E42

0x5EC2

1

Integer Parameter Register
for Ch4

YES

SDCMPH4

0x5E43

0x5EC3

1

High-level Threshold
Register for Ch4

YES

SDCMPL4

0x5E44

0x5EC4

1

Low-level Threshold Register
for Ch4

YES

SDCPARM4

0x5E45

0x5EC5

1

Comparator Parameter
Register for Ch4

YES

SDDATA4

0x5E46

0x5EC6

2

Filter Data Register (16- or
32-bit) for Ch4

13.8 Registers
13.8.1 SDFM Base Addresses
Table 13-11. SDFM Base Address Table
Start Address

End Address

Sdfm1Regs

Device Registers

SDFM_REGS

Register Name

0x0000_5E00

0x0000_5E7F

Sdfm2Regs

SDFM_REGS

0x0000_5E80

0x0000_5EFF

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1637

Registers

www.ti.com

13.8.2 SDFM_REGS Registers
Table 13-12 lists the memory-mapped registers for the SDFM_REGS. All register offset addresses not
listed in Table 13-12 should be considered as reserved locations and the register contents should not be
modified.
Table 13-12. SDFM_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

SDIFLG

Interrupt Flag Register

2h

SDIFLGCLR

Interrupt Flag Clear Register

4h

SDCTL

SD Control Register

EALLOW

Go

Go
Go

6h

SDMFILEN

SD Master Filter Enable

EALLOW

Go

10h

SDCTLPARM1

Control Parameter Register for Ch1

EALLOW

Go

11h

SDDFPARM1

Data Filter Parameter Register for Ch1

EALLOW

Go

12h

SDDPARM1

Integer Parameter Register for Ch1

EALLOW

Go

13h

SDCMPH1

High-level Threshold Register for Ch1

EALLOW

Go

14h

SDCMPL1

Low-level Threshold Register for Ch1

EALLOW

Go

15h

SDCPARM1

Comparator Parameter Register for Ch1

EALLOW

Go

16h

SDDATA1

Filter Data Register (16 or 32bit) for Ch1

20h

SDCTLPARM2

Control Parameter Register for Ch2

EALLOW

Go

21h

SDDFPARM2

Data Filter Parameter Register for Ch2

EALLOW

Go

22h

SDDPARM2

Integer Parameter Register for Ch2

EALLOW

Go

23h

SDCMPH2

High-level Threshold Register for Ch2

EALLOW

Go

24h

SDCMPL2

Low-level Threshold Register for Ch2

EALLOW

Go

25h

SDCPARM2

Comparator Parameter Register for Ch2

EALLOW

Go

26h

SDDATA2

Filter Data Register (16 or 32bit) for Ch2

30h

SDCTLPARM3

Control Parameter Register for Ch3

EALLOW

Go

31h

SDDFPARM3

Data Filter Parameter Register for Ch3

EALLOW

Go

32h

SDDPARM3

Integer Parameter Register for Ch3

EALLOW

Go

33h

SDCMPH3

High-level Threshold Register for Ch3

EALLOW

Go

34h

SDCMPL3

Low-level Threshold Register for Ch3

EALLOW

Go

35h

SDCPARM3

Comparator Parameter Register for Ch3

EALLOW

Go

36h

SDDATA3

Filter Data Register (16 or 32bit) for Ch3

40h

SDCTLPARM4

Control Parameter Register for Ch4

EALLOW

Go

41h

SDDFPARM4

Data Filter Parameter Register for Ch4

EALLOW

Go

42h

SDDPARM4

Integer Parameter Register for Ch4

EALLOW

Go

43h

SDCMPH4

High-level Threshold Register for Ch4

EALLOW

Go

44h

SDCMPL4

Low-level Threshold Register for Ch4

EALLOW

Go

45h

SDCPARM4

Comparator Parameter Register for Ch4

EALLOW

Go

46h

SDDATA4

Filter Data Register (16 or 32bit) for Ch4

Go

Go

Go

Go

Complex bit access types are encoded to fit into small table cells. Table 13-13 shows the codes that are
used for access types in this section.
Table 13-13. SDFM_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

Write

Read Type

Write Type
W

1638

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 13-13. SDFM_REGS Access Type
Codes (continued)
Access Type

Code

Description

W=1

W

Write

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1639

Registers

www.ti.com

13.8.2.1 SDIFLG Register (Offset = 0h) [reset = 0h]
SDIFLG is shown in Figure 13-10 and described in Table 13-14.
Return to Summary Table.
Interrupt Flag Register
Figure 13-10. SDIFLG Register
31
MIF
R-0h

30

29

28

23

22

21

20

27
RESERVED
R-0h

26

25

24

19

18

17

16

RESERVED
R-0h
15
AF4
R-0h

14
AF3
R-0h

13
AF2
R-0h

12
AF1
R-0h

11
MF4
R-0h

10
MF3
R-0h

9
MF2
R-0h

8
MF1
R-0h

7
IFL4
R-0h

6
IFH4
R-0h

5
IFL3
R-0h

4
IFH3
R-0h

3
IFL2
R-0h

2
IFH2
R-0h

1
IFL1
R-0h

0
IFH1
R-0h

Table 13-14. SDIFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MIF

R

0h

Set whenever any interrupt (ACK1-4, MF1-4,IFL1-4,IFH1-4) is active
Reset type: SYSRSn

RESERVED

R

0h

Reserved

AF4

R

0h

0: No new data available from Filter 4

30-16
15

1: New data available from Filter 4
Reset type: SYSRSn
14

AF3

R

0h

0: No new data available from Filter 3
1: New data available from Filter 3
Reset type: SYSRSn

13

AF2

R

0h

0: No new data available from Filter 2
1: New data available from Filter 2
Reset type: SYSRSn

12

AF1

R

0h

0: No new data available from Filter 1
1: New data available from Filter 1
Reset type: SYSRSn

11

MF4

R

0h

0: Modulator is operating normally for Filter 4
1: Modulator failure for Filter 4
Reset type: SYSRSn

10

MF3

R

0h

0: Modulator is operating normally for Filter 3
1: Modulator failure for Filter 3
Reset type: SYSRSn

9

MF2

R

0h

0: Modulator is operating normally for Filter 2
1: Modulator failure for Filter 2
Reset type: SYSRSn

8

MF1

R

0h

0: Modulator is operating normally for Filter 1
1: Modulator failure for Filter 1
Reset type: SYSRSn

1640

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 13-14. SDIFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7

IFL4

R

0h

0: Comparator Filter 4 output is above the low limit threshold
1: Comparator Filter 4 output is equal to or below the low level
threshold, if enabled
Reset type: SYSRSn

6

IFH4

R

0h

0: Comparator Filter 4 output is below the high limit threshold
1: Comparator Filter 4 output is equal to or above the high level
threshold, if enabled
Reset type: SYSRSn

5

IFL3

R

0h

0: Comparator Filter 3 output is above the low limit threshold
1: Comparator Filter 3 output is equal to or below the low level
threshold, if enabled
Reset type: SYSRSn

4

IFH3

R

0h

0: Comparator Filter 3 output is below the high limit threshold
1: Comparator Filter 3 output is equal to or above the high level
threshold, if enabled
Reset type: SYSRSn

3

IFL2

R

0h

0: Comparator Filter 2 output is above the low limit threshold
1: Comparator Filter 2 output is equal to or below the low level
threshold, if enabled
Reset type: SYSRSn

2

IFH2

R

0h

0: Comparator Filter 2 output is below the high limit threshold
1: Comparator Filter 2 output is equal to or above the high level
threshold, if enabled
Reset type: SYSRSn

1

IFL1

R

0h

0: Comparator Filter 1 output is above the low limit threshold
1: Comparator Filter 1 output is equal to or below the low level
threshold, if enabled
Reset type: SYSRSn

0

IFH1

R

0h

0: Comparator Filter 1 output is below the high limit threshold
1: Comparator Filter 1 output is equal to or above the high level
threshold, if enabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1641

Registers

www.ti.com

13.8.2.2 SDIFLGCLR Register (Offset = 2h) [reset = 0h]
SDIFLGCLR is shown in Figure 13-11 and described in Table 13-15.
Return to Summary Table.
Interrupt Flag Clear Register
Figure 13-11. SDIFLGCLR Register
31
MIF
R=0/W=1-0h

30

29

28

23

22

21

20

27
RESERVED
R-0h

26

25

24

19

18

17

16

RESERVED
R-0h
15
AF4
R=0/W=1-0h

14
AF3
R=0/W=1-0h

13
AF2
R=0/W=1-0h

12
AF1
R=0/W=1-0h

11
MF4
R=0/W=1-0h

10
MF3
R=0/W=1-0h

9
MF2
R=0/W=1-0h

8
MF1
R=0/W=1-0h

7
IFL4
R=0/W=1-0h

6
IFH4
R=0/W=1-0h

5
IFL3
R=0/W=1-0h

4
IFH3
R=0/W=1-0h

3
IFL2
R=0/W=1-0h

2
IFH2
R=0/W=1-0h

1
IFL1
R=0/W=1-0h

0
IFH1
R=0/W=1-0h

Table 13-15. SDIFLGCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MIF

R=0/W=1

0h

Flag-clear bit for SDFM Master Interrupt flag. Write 1 to clear MIF.
Writes of "0" are ignored.
Note: If the MIF flag is cleared and other Interrupts are still pending,
MIF will again be set to 1 on the following SysClk cycle, and the INT
output will be reasserted (pulsed low)
Reset type: SYSRSn

30-16
15

RESERVED

R

0h

Reserved

AF4

R=0/W=1

0h

SD Module Interrupt Flag Clear Bits:
Writing a "1" will clear the respective flag bit in the SDINTFLG
register. Writes of "0" are ignored.
Note: If user writes a "1" to clear a bit on the same cycle that the
hardware is trying to set the bit to "1", then hardware has priority and
the bit will not be cleared.
Flag-clear bit for Acknowledge flag for Filter 4
Reset type: SYSRSn

1642

14

AF3

R=0/W=1

0h

Flag-clear bit for Acknowledge flag for Filter 3
Reset type: SYSRSn

13

AF2

R=0/W=1

0h

Flag-clear bit for Acknowledge flag for Filter 2
Reset type: SYSRSn

12

AF1

R=0/W=1

0h

Flag-clear bit for Acknowledge flag for Filter 1
Reset type: SYSRSn

11

MF4

R=0/W=1

0h

Flag-clear bit for Modulator Failure for Filter 4
Reset type: SYSRSn

10

MF3

R=0/W=1

0h

Flag-clear bit for Modulator Failure for Filter 3
Reset type: SYSRSn

9

MF2

R=0/W=1

0h

Flag-clear bit for Modulator Failure for Filter 2
Reset type: SYSRSn

8

MF1

R=0/W=1

0h

Flag-clear bit for Modulator Failure for Filter 1
Reset type: SYSRSn

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 13-15. SDIFLGCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7

IFL4

R=0/W=1

0h

Flag-clear bit for Low-Level Interrupt flag Filter 4
Reset type: SYSRSn

6

IFH4

R=0/W=1

0h

Flag-clear bit for High-level Interrupt flag Filter 4
Reset type: SYSRSn

5

IFL3

R=0/W=1

0h

Flag-clear bit for Low-Level Interrupt flag Filter 3
Reset type: SYSRSn

4

IFH3

R=0/W=1

0h

Flag-clear bit for High-level Interrupt flag Filter 3
Reset type: SYSRSn

3

IFL2

R=0/W=1

0h

Flag-clear bit for Low-Level Interrupt flag Filter 2
Reset type: SYSRSn

2

IFH2

R=0/W=1

0h

Flag-clear bit for High-level Interrupt flag Filter 2
Reset type: SYSRSn

1

IFL1

R=0/W=1

0h

Flag-clear bit for Low-Level Interrupt flag Filter 1
Reset type: SYSRSn

0

IFH1

R=0/W=1

0h

Flag-clear bit for High-level Interrupt flag Filter 1
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1643

Registers

www.ti.com

13.8.2.3 SDCTL Register (Offset = 4h) [reset = 0h]
SDCTL is shown in Figure 13-12 and described in Table 13-16.
Return to Summary Table.
SD Control Register
Figure 13-12. SDCTL Register
15
RESERVED
R-0h

14
RESERVED
R-0h

13
MIE
R/W-0h

12

7

6

5

4

11

10
RESERVED
R-0h

9

8

3

2

1

0

RESERVED
R-0h

Table 13-16. SDCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13

MIE

R/W

0h

Master interrupt enable.
0: Interrupt pin and interrupt flags are blocked (interrupt pin INT
always inactive).
1: Interrupt pin and interrupt flags are not blocked and can be set
and reset (if individually
enabled).
Reset type: SYSRSn

12-0

1644

RESERVED

Sigma Delta Filter Module (SDFM)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.4 SDMFILEN Register (Offset = 6h) [reset = 0h]
SDMFILEN is shown in Figure 13-13 and described in Table 13-17.
Return to Summary Table.
SD Master Filter Enable
Figure 13-13. SDMFILEN Register
15

14
RESERVED
R-0h

13

12
RESERVED
R-0h

11
MFE
R/W-0h

10
RESERVED
R-0h

9
RESERVED
R-0h

8
RESERVED
R-0h

7
RESERVED
R-0h

6

5
RESERVED
R-0h

4

3

2

1

0

RESERVED
R-0h

Table 13-17. SDMFILEN Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R

0h

Reserved

12

RESERVED

R

0h

Reserved

11

MFE

R/W

0h

Master Filter Enable. Functionally AND'ed with bit FEN in the Data
Filter Parameter Register
0: Data filter units of all filter modules are disabled.
1: Data filter units can be enabled if bit FEN is '1'.
Reset type: SYSRSn

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8-7

RESERVED

R

0h

Reserved

6-4

RESERVED

R

0h

Reserved

3-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1645

Registers

www.ti.com

13.8.2.5 SDCTLPARM1 Register (Offset = 10h) [reset = 0h]
SDCTLPARM1 is shown in Figure 13-14 and described in Table 13-18.
Return to Summary Table.
Control Parameter Register for Ch1
Figure 13-14. SDCTLPARM1 Register
15

14

13

12

11

10

9

3
RESERVED
R-0h

2
RESERVED
R-0h

1

8

RESERVED
R-0h
7

6
RESERVED
R-0h

5

4
RESERVED
R-0h

0
MOD
R/W-0h

Table 13-18. SDCTLPARM1 Register Field Descriptions
Field

Type

Reset

Description

15-5

Bit

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

MOD

R/W

0h

Delta-Sigma Modulator mode

1-0

00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
Reset type: SYSRSn

1646

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.6 SDDFPARM1 Register (Offset = 11h) [reset = 0h]
SDDFPARM1 is shown in Figure 13-15 and described in Table 13-19.
Return to Summary Table.
Data Filter Parameter Register for Ch1
Figure 13-15. SDDFPARM1 Register
15

14
RESERVED
R-0h

13

6

5

7

12
SDSYNCEN
R/W-0h

11

4

3

10

9
AE
R/W-0h

8
FEN
R/W-0h

2

1

0

SST
R/W-0h

DOSR
R/W-0h

Table 13-19. SDDFPARM1 Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R

0h

Reserved

12

SDSYNCEN

R/W

0h

Data Filter Reset enable for External Reset typ from PWM Compare
output.
0: Data filter cannot be reset by external PWM compare output
1: Data filter can be reset by external PWM compare output
Reset type: SYSRSn

11-10

SST

R/W

0h

Data filter structure.
00: Data filter runs with a Sincfast structure
01: Data filter runs with a Sinc1 structure
10: Data filter runs with a Sinc2 structure
11: Data filter runs with a Sinc3 structure
Reset type: SYSRSn

9

AE

R/W

0h

Acknowledge enable.
0: Acknowledge flag is disabled for the particular filter
1: Acknowledge flag is enabled for the particular filter
Reset type: SYSRSn

8

FEN

R/W

0h

Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the Data filter
Reset type: SYSRSn

7-0

DOSR

R/W

0h

Oversampling ratio. The actual rate is DOSR + 1.
These bits set the oversampling ratio of the filter.
0x0FF represents an oversampling ratio of 256.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1647

Registers

www.ti.com

13.8.2.7 SDDPARM1 Register (Offset = 12h) [reset = 0h]
SDDPARM1 is shown in Figure 13-16 and described in Table 13-20.
Return to Summary Table.
Integer Parameter Register for Ch1
Figure 13-16. SDDPARM1 Register
15

14

13
SH
R/W-0h

12

11

10
DR
R/W-0h

9
RESERVED
R/W-0h

8
RESERVED
R/W-0h

7
RESERVED
R-0h

6

5

4

3
RESERVED
R/W-0h

2

1

0

Table 13-20. SDDPARM1 Register Field Descriptions
Bit
15-11

Field

Type

Reset

Description

SH

R/W

0h

Shift Control
These bits indicate by how many bits the 16-bit window is shifted up
when 16-bit data representation is chosen.
Reset type: SYSRSn

10

DR

R/W

0h

Data representation
0: Data stored in 16b 2's complement
1: Data stored in 32b 2's complement
Reset type: SYSRSn

1648

9

RESERVED

R/W

0h

Reserved

8

RESERVED

R/W

0h

Reserved

7

RESERVED

R

0h

Reserved

6-0

RESERVED

R/W

0h

Reserved

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.8 SDCMPH1 Register (Offset = 13h) [reset = 0h]
SDCMPH1 is shown in Figure 13-17 and described in Table 13-21.
Return to Summary Table.
High-level Threshold Register for Ch1
Figure 13-17. SDCMPH1 Register
15
RESERVED
R-0h

14

13

12

7

6

5

4

11
HLT
R/W-0h

10

9

8

3

2

1

0

HLT
R/W-0h

Table 13-21. SDCMPH1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

HLT

R/W

0h

Unsigned high-level threshold for the comparator filter output.
Reset type: SYSRSn

14-0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1649

Registers

www.ti.com

13.8.2.9 SDCMPL1 Register (Offset = 14h) [reset = 0h]
SDCMPL1 is shown in Figure 13-18 and described in Table 13-22.
Return to Summary Table.
Low-level Threshold Register for Ch1
Figure 13-18. SDCMPL1 Register
15
RESERVED
R-0h

14

13

12

7

6

5

4

11
LLT
R/W-0h

10

9

8

3

2

1

0

LLT
R/W-0h

Table 13-22. SDCMPL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

LLT

R/W

0h

Unsigned low-level threshold for the comparator filter output.
Reset type: SYSRSn

14-0

1650

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.10 SDCPARM1 Register (Offset = 15h) [reset = 0h]
SDCPARM1 is shown in Figure 13-19 and described in Table 13-23.
Return to Summary Table.
Comparator Parameter Register for Ch1
Figure 13-19. SDCPARM1 Register
15

14

13

12

11

10

9
MFIE
R/W-0h

8
CS1_CS0
R/W-0h

4

3

2
COSR
R/W-0h

1

0

RESERVED
R-0h
7
CS1_CS0
R/W-0h

6
IEL
R/W-0h

5
IEH
R/W-0h

Table 13-23. SDCPARM1 Register Field Descriptions
Bit
15-10
9

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

MFIE

R/W

0h

0: The modulator failure flag as well as the output INT is disabled for
this particular flag
1: The modulator failure flag is enabled
Reset type: SYSRSn

8-7

CS1_CS0

R/W

0h

Comparator filter structure.
00: Comparator filter runs with a sincfast structure
01: Comparator filter runs with a Sinc1 structure
10: Comparator filter runs with a Sinc2 structure
11: Comparator filter runs with a Sinc3 structure
Reset type: SYSRSn

6

IEL

R/W

0h

Low-level interrupt enable.
0: The low-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The low-level interrupt flag is enabled
Reset type: SYSRSn

5

IEH

R/W

0h

High-level interrupt enable.
0: The high-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The high-level interrupt flag is enabled
Reset type: SYSRSn

4-0

COSR

R/W

0h

Oversampling ratio. The actual rate is COSR + 1.
These bits set the oversampling ratio of the filter.
0x1F represents an oversampling ratio of 31.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1651

Registers

www.ti.com

13.8.2.11 SDDATA1 Register (Offset = 16h) [reset = 0h]
SDDATA1 is shown in Figure 13-20 and described in Table 13-24.
Return to Summary Table.
Filter Data Register (16 or 32bit) for Ch1
Figure 13-20. SDDATA1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA32HI
R-0h

9

8 7 6
DATA16
R-0h

5

4

3

2

1

0

Table 13-24. SDDATA1 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

DATA32HI

R

0h

Hi-order 16-bit in 32-bit mode
Reset type: SYSRSn

15-0

DATA16

R

0h

Hi-order 16-bit in 32 mode, 16-bit data in 16-bit mode
Reset type: SYSRSn

1652

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.12 SDCTLPARM2 Register (Offset = 20h) [reset = 0h]
SDCTLPARM2 is shown in Figure 13-21 and described in Table 13-25.
Return to Summary Table.
Control Parameter Register for Ch2
Figure 13-21. SDCTLPARM2 Register
15

14

13

12

11

10

9

3
RESERVED
R-0h

2
RESERVED
R-0h

1

8

RESERVED
R-0h
7

6
RESERVED
R-0h

5

4
RESERVED
R-0h

0
MOD
R/W-0h

Table 13-25. SDCTLPARM2 Register Field Descriptions
Field

Type

Reset

Description

15-5

Bit

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

MOD

R/W

0h

Delta-Sigma Modulator mode

1-0

00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1653

Registers

www.ti.com

13.8.2.13 SDDFPARM2 Register (Offset = 21h) [reset = 0h]
SDDFPARM2 is shown in Figure 13-22 and described in Table 13-26.
Return to Summary Table.
Data Filter Parameter Register for Ch2
Figure 13-22. SDDFPARM2 Register
15

14
RESERVED
R-0h

13

6

5

7

12
SDSYNCEN
R/W-0h

11

4

3

10

9
AE
R/W-0h

8
FEN
R/W-0h

2

1

0

SST
R/W-0h

DOSR
R/W-0h

Table 13-26. SDDFPARM2 Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R

0h

Reserved

12

SDSYNCEN

R/W

0h

Data Filter Reset enable for External Reset typ from PWM Compare
output.
0: Data filter cannot be reset by external PWM compare output
1: Data filter can be reset by external PWM compare output
Reset type: SYSRSn

11-10

SST

R/W

0h

Data filter structure.
00: Data filter runs with a Sincfast structure
01: Data filter runs with a Sinc1 structure
10: Data filter runs with a Sinc2 structure
11: Data filter runs with a Sinc3 structure
Reset type: SYSRSn

9

AE

R/W

0h

Acknowledge enable.
0: Acknowledge flag is disabled for the particular filter
1: Acknowledge flag is enabled for the particular filter
Reset type: SYSRSn

8

FEN

R/W

0h

Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the Data filter
Reset type: SYSRSn

7-0

DOSR

R/W

0h

Oversampling ratio. The actual rate is DOSR + 1.
These bits set the oversampling ratio of the filter.
0x0FF represents an oversampling ratio of 256.
Reset type: SYSRSn

1654

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.14 SDDPARM2 Register (Offset = 22h) [reset = 0h]
SDDPARM2 is shown in Figure 13-23 and described in Table 13-27.
Return to Summary Table.
Integer Parameter Register for Ch2
Figure 13-23. SDDPARM2 Register
15

14

13
SH
R/W-0h

12

11

10
DR
R/W-0h

9
RESERVED
R/W-0h

8
RESERVED
R/W-0h

7
RESERVED
R-0h

6

5

4

3
RESERVED
R/W-0h

2

1

0

Table 13-27. SDDPARM2 Register Field Descriptions
Bit
15-11

Field

Type

Reset

Description

SH

R/W

0h

Shift Control
These bits indicate by how many bits the 16-bit window is shifted up
when 16-bit data representation is chosen.
Reset type: SYSRSn

10

DR

R/W

0h

Data representation
0: Data stored in 16b 2's complement
1: Data stored in 32b 2's complement
Reset type: SYSRSn

9

RESERVED

R/W

0h

Reserved

8

RESERVED

R/W

0h

Reserved

7

RESERVED

R

0h

Reserved

6-0

RESERVED

R/W

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1655

Registers

www.ti.com

13.8.2.15 SDCMPH2 Register (Offset = 23h) [reset = 0h]
SDCMPH2 is shown in Figure 13-24 and described in Table 13-28.
Return to Summary Table.
High-level Threshold Register for Ch2
Figure 13-24. SDCMPH2 Register
15
RESERVED
R-0h

14

13

12

7

6

5

4

11
HLT
R/W-0h

10

9

8

3

2

1

0

HLT
R/W-0h

Table 13-28. SDCMPH2 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

HLT

R/W

0h

Unsigned high-level threshold for the comparator filter output.
Reset type: SYSRSn

14-0

1656

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.16 SDCMPL2 Register (Offset = 24h) [reset = 0h]
SDCMPL2 is shown in Figure 13-25 and described in Table 13-29.
Return to Summary Table.
Low-level Threshold Register for Ch2
Figure 13-25. SDCMPL2 Register
15
RESERVED
R-0h

14

13

12

7

6

5

4

11
LLT
R/W-0h

10

9

8

3

2

1

0

LLT
R/W-0h

Table 13-29. SDCMPL2 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

LLT

R/W

0h

Unsigned low-level threshold for the comparator filter output.
Reset type: SYSRSn

14-0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1657

Registers

www.ti.com

13.8.2.17 SDCPARM2 Register (Offset = 25h) [reset = 0h]
SDCPARM2 is shown in Figure 13-26 and described in Table 13-30.
Return to Summary Table.
Comparator Parameter Register for Ch2
Figure 13-26. SDCPARM2 Register
15

14

13

12

11

10

9
MFIE
R/W-0h

8
CS1_CS0
R/W-0h

4

3

2
COSR
R/W-0h

1

0

RESERVED
R-0h
7
CS1_CS0
R/W-0h

6
IEL
R/W-0h

5
IEH
R/W-0h

Table 13-30. SDCPARM2 Register Field Descriptions
Bit
15-10
9

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

MFIE

R/W

0h

0: The modulator failure flag as well as the output INT is disabled for
this particular flag
1: The modulator failure flag is enabled
Reset type: SYSRSn

8-7

CS1_CS0

R/W

0h

Comparator filter structure.
00: Comparator filter runs with a sincfast structure
01: Comparator filter runs with a Sinc1 structure
10: Comparator filter runs with a Sinc2 structure
11: Comparator filter runs with a Sinc3 structure
Reset type: SYSRSn

6

IEL

R/W

0h

Low-level interrupt enable.
0: The low-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The low-level interrupt flag is enabled
Reset type: SYSRSn

5

IEH

R/W

0h

High-level interrupt enable.
0: The high-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The high-level interrupt flag is enabled
Reset type: SYSRSn

4-0

COSR

R/W

0h

Oversampling ratio. The actual rate is COSR + 1.
These bits set the oversampling ratio of the filter.
0x1F represents an oversampling ratio of 31.
Reset type: SYSRSn

1658

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.18 SDDATA2 Register (Offset = 26h) [reset = 0h]
SDDATA2 is shown in Figure 13-27 and described in Table 13-31.
Return to Summary Table.
Filter Data Register (16 or 32bit) for Ch2
Figure 13-27. SDDATA2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA32HI
R-0h

9

8 7 6
DATA16
R-0h

5

4

3

2

1

0

Table 13-31. SDDATA2 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

DATA32HI

R

0h

Hi-order 16b in 32b mode
Reset type: SYSRSn

15-0

DATA16

R

0h

16-bit Data in 16b mode, Lo-order 16b in 32b mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1659

Registers

www.ti.com

13.8.2.19 SDCTLPARM3 Register (Offset = 30h) [reset = 0h]
SDCTLPARM3 is shown in Figure 13-28 and described in Table 13-32.
Return to Summary Table.
Control Parameter Register for Ch3
Figure 13-28. SDCTLPARM3 Register
15

14

13

12

11

10

9

3
RESERVED
R-0h

2
RESERVED
R-0h

1

8

RESERVED
R-0h
7

6
RESERVED
R-0h

5

4
RESERVED
R-0h

0
MOD
R/W-0h

Table 13-32. SDCTLPARM3 Register Field Descriptions
Field

Type

Reset

Description

15-5

Bit

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

MOD

R/W

0h

Delta-Sigma Modulator mode

1-0

00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
Reset type: SYSRSn

1660

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.20 SDDFPARM3 Register (Offset = 31h) [reset = 0h]
SDDFPARM3 is shown in Figure 13-29 and described in Table 13-33.
Return to Summary Table.
Data Filter Parameter Register for Ch3
Figure 13-29. SDDFPARM3 Register
15

14
RESERVED
R-0h

13

6

5

7

12
SDSYNCEN
R/W-0h

11

4

3

10

9
AE
R/W-0h

8
FEN
R/W-0h

2

1

0

SST
R/W-0h

DOSR
R/W-0h

Table 13-33. SDDFPARM3 Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R

0h

Reserved

12

SDSYNCEN

R/W

0h

Data Filter Reset enable for External Reset typ from PWM Compare
output.
0: Data filter cannot be reset by external PWM compare output
1: Data filter can be reset by external PWM compare output
Reset type: SYSRSn

11-10

SST

R/W

0h

Data filter structure.
00: Data filter runs with a Sincfast structure
01: Data filter runs with a Sinc1 structure
10: Data filter runs with a Sinc2 structure
11: Data filter runs with a Sinc3 structure
Reset type: SYSRSn

9

AE

R/W

0h

Acknowledge enable.
0: Acknowledge flag is disabled for the particular filter
1: Acknowledge flag is enabled for the particular filter
Reset type: SYSRSn

8

FEN

R/W

0h

Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the data filter
Reset type: SYSRSn

7-0

DOSR

R/W

0h

Oversampling ratio. The actual rate is DOSR + 1.
These bits set the oversampling ratio of the filter.
0x0FF represents an oversampling ratio of 256.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1661

Registers

www.ti.com

13.8.2.21 SDDPARM3 Register (Offset = 32h) [reset = 0h]
SDDPARM3 is shown in Figure 13-30 and described in Table 13-34.
Return to Summary Table.
Integer Parameter Register for Ch3
Figure 13-30. SDDPARM3 Register
15

14

13
SH
R/W-0h

12

11

10
DR
R/W-0h

9
RESERVED
R/W-0h

8
RESERVED
R/W-0h

7
RESERVED
R-0h

6

5

4

3
RESERVED
R/W-0h

2

1

0

Table 13-34. SDDPARM3 Register Field Descriptions
Bit
15-11

Field

Type

Reset

Description

SH

R/W

0h

Shift Control
These bits indicate by how many bits the 16-bit window is shifted up
when 16-bit data representation is chosen.
Reset type: SYSRSn

10

DR

R/W

0h

Data representation
0: Data stored in 16b 2's complement
1: Data stored in 32b 2's complement
Reset type: SYSRSn

1662

9

RESERVED

R/W

0h

Reserved

8

RESERVED

R/W

0h

Reserved

7

RESERVED

R

0h

Reserved

6-0

RESERVED

R/W

0h

Reserved

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.22 SDCMPH3 Register (Offset = 33h) [reset = 0h]
SDCMPH3 is shown in Figure 13-31 and described in Table 13-35.
Return to Summary Table.
High-level Threshold Register for Ch3
Figure 13-31. SDCMPH3 Register
15
RESERVED
R-0h

14

13

12

7

6

5

4

11
HLT
R/W-0h

10

9

8

3

2

1

0

HLT
R/W-0h

Table 13-35. SDCMPH3 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

HLT

R/W

0h

Unsigned high-level threshold for the comparator filter output.
Reset type: SYSRSn

14-0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1663

Registers

www.ti.com

13.8.2.23 SDCMPL3 Register (Offset = 34h) [reset = 0h]
SDCMPL3 is shown in Figure 13-32 and described in Table 13-36.
Return to Summary Table.
Low-level Threshold Register for Ch3
Figure 13-32. SDCMPL3 Register
15
RESERVED
R-0h

14

13

12

7

6

5

4

11
LLT
R/W-0h

10

9

8

3

2

1

0

LLT
R/W-0h

Table 13-36. SDCMPL3 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

LLT

R/W

0h

Unsigned low-level threshold for the comparator filter output.
Reset type: SYSRSn

14-0

1664

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.24 SDCPARM3 Register (Offset = 35h) [reset = 0h]
SDCPARM3 is shown in Figure 13-33 and described in Table 13-37.
Return to Summary Table.
Comparator Parameter Register for Ch3
Figure 13-33. SDCPARM3 Register
15

14

13

12

11

10

9
MFIE
R/W-0h

8
CS1_CS0
R/W-0h

4

3

2
COSR
R/W-0h

1

0

RESERVED
R-0h
7
CS1_CS0
R/W-0h

6
IEL
R/W-0h

5
IEH
R/W-0h

Table 13-37. SDCPARM3 Register Field Descriptions
Bit
15-10
9

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

MFIE

R/W

0h

0: The modulator failure flag as well as the output INT is disabled for
this particular flag
1: The modulator failure flag is enabled
Reset type: SYSRSn

8-7

CS1_CS0

R/W

0h

Comparator filter structure.
00: Comparator filter runs with a sincfast structure
01: Comparator filter runs with a Sinc1 structure
10: Comparator filter runs with a Sinc2 structure
11: Comparator filter runs with a Sinc3 structure
Reset type: SYSRSn

6

IEL

R/W

0h

Low-level interrupt enable.
0: The low-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The low-level interrupt flag is enabled
Reset type: SYSRSn

5

IEH

R/W

0h

High-level interrupt enable.
0: The high-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The high-level interrupt flag is enabled
Reset type: SYSRSn

4-0

COSR

R/W

0h

Oversampling ratio. The actual rate is COSR + 1.
These bits set the oversampling ratio of the filter.
0x1F represents an oversampling ratio of 31.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1665

Registers

www.ti.com

13.8.2.25 SDDATA3 Register (Offset = 36h) [reset = 0h]
SDDATA3 is shown in Figure 13-34 and described in Table 13-38.
Return to Summary Table.
Filter Data Register (16 or 32bit) for Ch3
Figure 13-34. SDDATA3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA32HI
R-0h

9

8 7 6
DATA16
R-0h

5

4

3

2

1

0

Table 13-38. SDDATA3 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

DATA32HI

R

0h

Hi-order 16b in 32b mode
Reset type: SYSRSn

15-0

DATA16

R

0h

16-bit Data in 16b mode, Lo-order 16b in 32b mode
Reset type: SYSRSn

1666

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.26 SDCTLPARM4 Register (Offset = 40h) [reset = 0h]
SDCTLPARM4 is shown in Figure 13-35 and described in Table 13-39.
Return to Summary Table.
Control Parameter Register for Ch4
Figure 13-35. SDCTLPARM4 Register
15

14

13

12

11

10

9

3
RESERVED
R-0h

2
RESERVED
R-0h

1

8

RESERVED
R-0h
7

6
RESERVED
R-0h

5

4
RESERVED
R-0h

0
MOD
R/W-0h

Table 13-39. SDCTLPARM4 Register Field Descriptions
Field

Type

Reset

Description

15-5

Bit

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

MOD

R/W

0h

Delta-Sigma Modulator mode

1-0

00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1667

Registers

www.ti.com

13.8.2.27 SDDFPARM4 Register (Offset = 41h) [reset = 0h]
SDDFPARM4 is shown in Figure 13-36 and described in Table 13-40.
Return to Summary Table.
Data Filter Parameter Register for Ch4
Figure 13-36. SDDFPARM4 Register
15

14
RESERVED
R-0h

13

6

5

7

12
SDSYNCEN
R/W-0h

11

4

3

10

9
AE
R/W-0h

8
FEN
R/W-0h

2

1

0

SST
R/W-0h

DOSR
R/W-0h

Table 13-40. SDDFPARM4 Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R

0h

Reserved

12

SDSYNCEN

R/W

0h

Data Filter Reset enable for External Reset typ from PWM Compare
output.
0: Data filter cannot be reset by external PWM compare output
1: Data filter can be reset by external PWM compare output
Reset type: SYSRSn

11-10

SST

R/W

0h

Data filter structure.
00: Data filter runs with a Sincfast structure
01: Data filter runs with a Sinc1 structure
10: Data filter runs with a Sinc2 structure
11: Data filter runs with a Sinc3 structure
Reset type: SYSRSn

9

AE

R/W

0h

Acknowledge enable.
0: Acknowledge flag is disabled for the particular filter
1: Acknowledge flag is enabled for the particular filter
Reset type: SYSRSn

8

FEN

R/W

0h

Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the sinc filter
Reset type: SYSRSn

7-0

DOSR

R/W

0h

Oversampling ratio. The actual rate is DOSR + 1.
These bits set the oversampling ratio of the filter.
0x0FF represents an oversampling ratio of 256.
Reset type: SYSRSn

1668

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.28 SDDPARM4 Register (Offset = 42h) [reset = 0h]
SDDPARM4 is shown in Figure 13-37 and described in Table 13-41.
Return to Summary Table.
Integer Parameter Register for Ch4
Figure 13-37. SDDPARM4 Register
15

14

13
SH
R/W-0h

12

11

10
DR
R/W-0h

9
RESERVED
R/W-0h

8
RESERVED
R/W-0h

7
RESERVED
R-0h

6

5

4

3
RESERVED
R/W-0h

2

1

0

Table 13-41. SDDPARM4 Register Field Descriptions
Bit
15-11

Field

Type

Reset

Description

SH

R/W

0h

Shift Control
These bits indicate by how many bits the 16-bit window is shifted up
when 16-bit data representation is chosen.
Reset type: SYSRSn

10

DR

R/W

0h

Data representation
0: Data stored in 16b 2's complement
1: Data stored in 32b 2's complement
Reset type: SYSRSn

9

RESERVED

R/W

0h

Reserved

8

RESERVED

R/W

0h

Reserved

7

RESERVED

R

0h

Reserved

6-0

RESERVED

R/W

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1669

Registers

www.ti.com

13.8.2.29 SDCMPH4 Register (Offset = 43h) [reset = 0h]
SDCMPH4 is shown in Figure 13-38 and described in Table 13-42.
Return to Summary Table.
High-level Threshold Register for Ch4
Figure 13-38. SDCMPH4 Register
15
RESERVED
R-0h

14

13

12

7

6

5

4

11
HLT
R/W-0h

10

9

8

3

2

1

0

HLT
R/W-0h

Table 13-42. SDCMPH4 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

HLT

R/W

0h

Unsigned high-level threshold for the comparator filter output.
Reset type: SYSRSn

14-0

1670

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.30 SDCMPL4 Register (Offset = 44h) [reset = 0h]
SDCMPL4 is shown in Figure 13-39 and described in Table 13-43.
Return to Summary Table.
Low-level Threshold Register for Ch4
Figure 13-39. SDCMPL4 Register
15
RESERVED
R-0h

14

13

12

7

6

5

4

11
LLT
R/W-0h

10

9

8

3

2

1

0

LLT
R/W-0h

Table 13-43. SDCMPL4 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

LLT

R/W

0h

Unsigned low-level threshold for the comparator filter output.
Reset type: SYSRSn

14-0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1671

Registers

www.ti.com

13.8.2.31 SDCPARM4 Register (Offset = 45h) [reset = 0h]
SDCPARM4 is shown in Figure 13-40 and described in Table 13-44.
Return to Summary Table.
Comparator Parameter Register for Ch4
Figure 13-40. SDCPARM4 Register
15

14

13

12

11

10

9
MFIE
R/W-0h

8
CS1_CS0
R/W-0h

4

3

2
COSR
R/W-0h

1

0

RESERVED
R-0h
7
CS1_CS0
R/W-0h

6
IEL
R/W-0h

5
IEH
R/W-0h

Table 13-44. SDCPARM4 Register Field Descriptions
Bit
15-10
9

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

MFIE

R/W

0h

0: The modulator failure flag as well as the output INT is disabled for
this particular flag
1: The modulator failure flag is enabled
Reset type: SYSRSn

8-7

CS1_CS0

R/W

0h

Comparator filter structure.
00: Comparator filter runs with a sincfast structure
01: Comparator filter runs with a Sinc1 structure
10: Comparator filter runs with a Sinc2 structure
11: Comparator filter runs with a Sinc3 structure
Reset type: SYSRSn

6

IEL

R/W

0h

Low-level interrupt enable.
0: The low-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The low-level interrupt flag is enabled
Reset type: SYSRSn

5

IEH

R/W

0h

High-level interrupt enable.
0: The high-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The high-level interrupt flag is enabled
Reset type: SYSRSn

4-0

COSR

R/W

0h

Oversampling ratio. The actual rate is COSR + 1.
These bits set the oversampling ratio of the filter.
0x1F represents an oversampling ratio of 31.
Reset type: SYSRSn

1672

Sigma Delta Filter Module (SDFM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

13.8.2.32 SDDATA4 Register (Offset = 46h) [reset = 0h]
SDDATA4 is shown in Figure 13-41 and described in Table 13-45.
Return to Summary Table.
Filter Data Register (16 or 32bit) for Ch4
Figure 13-41. SDDATA4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA32HI
R-0h

9

8 7 6
DATA16
R-0h

5

4

3

2

1

0

Table 13-45. SDDATA4 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

DATA32HI

R

0h

Hi-order 16b in 32b mode
Reset type: SYSRSn

15-0

DATA16

R

0h

16-bit Data in 16b mode, Lo-order 16b in 32b mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Sigma Delta Filter Module (SDFM)

1673

Chapter 14
SPRUHM8G – December 2013 – Revised September 2017

Enhanced Pulse Width Modulator (ePWM)
The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power
electronic systems found in both commercial and industrial equipment. These systems include digital
motor control, switch mode power supply control, uninterruptible power supplies (UPS), and other forms of
power conversion. The ePWM peripheral performs a digital to analog (DAC) function, where the duty cycle
is equivalent to a DAC analog value; it is sometimes referred to as a power DAC.
This chapter is applicable for ePWM type 4. See the TMS320x28xx, 28xxx DSP Peripheral Reference
Guide (SPRU566) for a list of all devices with an ePWM module of the same type, to determine the
differences between the types, and for a list of device-specific differences within a type.
Topic

...........................................................................................................................

14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
14.14

1674

Introduction ...................................................................................................
Configuring Device Pins ..................................................................................
Overview........................................................................................................
Time-Base (TB) Submodule ..............................................................................
Counter-Compare (CC) Submodule ...................................................................
Action-Qualifier (AQ) Submodule ......................................................................
Dead-Band Generator (DB) Submodule .............................................................
PWM Chopper (PC) Submodule .......................................................................
Trip-Zone (TZ) Submodule ...............................................................................
Event-Trigger (ET) Submodule ........................................................................
Digital Compare (DC) Submodule ....................................................................
EPWM X-BAR ................................................................................................
Applications to Power Topologies ...................................................................
Registers ......................................................................................................

Enhanced Pulse Width Modulator (ePWM)

Page

1675
1682
1682
1684
1695
1701
1714
1721
1725
1730
1736
1744
1745
1763

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

14.1 Introduction
This chapter includes an overview of the module and information about each of its submodules:
• Time-Base Submodule
• Counter Compare Submodule
• Action Qualifier Submodule
• Dead-Band Generator Submodule
• PWM Chopper (PC) Submodule
• Trip Zone Submodule
• Event Trigger Submodule
• Digital Compare Submodule
The ePWM Type 4 is functionally compatible to Type 2 (a Type 3 does not exist). Type 4 has the following
enhancements in addition to the Type 2 features:
• Register Address Map
Additional registers are required for new features on ePWM Type 4. The ePWM register address
space has been remapped for better alignment and easy usage.
• Delayed Trip Functionality
Changes have been added to achieve deadband insertion capabilities to support, for example, delayed
trip functionality needed for peak current mode control type application scenarios. This has been
accomplished by allowing comparator events to go into the Action Qualifier as a trigger event (Events
T1 and T2). If comparator T1/T2 events are used to edit the PWM, changes to the PWM waveform will
not take place immediately. Instead, they will synchronize to the next TBCLK.
• Dead-Band Generator Submodule Enhancements
Shadowing of DBCTL register to allow dynamic configuration changes.
• One Shot and Global Load of Registers
The ePWM Type 4 allows one-shot and global load capability from shadow to active registers to avoid
partial loads in, for example, multi-phase applications. It also allows programmable pre-scale of
shadow to active load events.
• Trip Zone Submodule Enhancements
Independent flags have been added to reflect the trip status for each of the TZ sources. Changes have
been made to the trip zone submodule to support certain power converter switching techniques like
valley switching.
• Digital Compare Submodule Enhancements
Blanking window filter register width has been increased from 8 to 16 bits. DCCAP functionality has
been enhanced to provide more programmability.
• PWM SYNC Related Enhancements
The ePWM Type 4 allows PWM SYNCOUT generation based on CMPC and CMPD events. These
events can also be used for PWMSYNC pulse selection.
The ePWM Type 2 is fully compatible to Type 1. Type 2 has the following enhancements in addition to the
Type 1 features:
• High Resolution Dead-Band Capability
High resolution capability is added to dead-band RED and FED in half-cycle clocking mode.
• Dead-Band Generator Submodule Enhancements
The ePWM Type 2 has features to enable both RED and FED on either PWM outputs. Provides
increased dead band with 14-bit counters and dead-band / dead-band high-resolution registers are
shadowed
• High Resolution Extension Available on ePWMxB Outputs
Provides the ability to enable high-resolution period and duty cycle control on ePWMxB outputs. This is
discussed in more detail in the HRPWM chapter in this manual.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1675

Introduction

•

•

•

•

•

www.ti.com

Counter Compare Submodule Enhancements
The ePWM Type 2 allows Interrupts and SOC events to be generated by additional counter compares
CMPC and CMPD.
Event Trigger Submdule Enhancements
Prescaling logic to issue interrupt requests and ADC start of conversion expanded up to every 15
events. It allows Software initialization of event counters on SYNC event.
Digital Compare Submodule Enhancements
Digital Compare Trip Select logic [DCTRIPSEL] has up to 12 external trip sources selected by the
Input X-BAR logic in addition to an ability to OR all of them (up to 14 [external and internal sources]) to
create the respective DCxEVTs.
Simultaneous Writes to TBPRD and CMPx Registers
This feature allows writes to TBPRD, CMPA:CMPAHR, CMPB:CMPBHR, CMPC and CMPD of any
ePWM module to be tied to any other ePWM module, and also allows all ePWM modules to be tied to
a particular ePWM module if desired.
Shadow to Active Load on SYNC of TBPRD and CMP Registers
This feature supports simultaneous writes of TBPRD and CMPA/B/C/D registers.

The ePWM Type 1 is functionally compatible to Type 0. Type 1 has the following enhancements in
addition to the Type 0 features:
• Increased Dead-Band Resolution
Dead-band clocking has been enhanced to allow half-cycle clocking to double resolution.
• Enhanced Interrupt and SOC Generation
Interrupts and ADC start-of-conversion can now be generated on both the TBCTR == zero and TBCTR
== period events. This feature enables dual edge PWM control. Additionally, the ADC start-ofconversion can be generated from an event defined in the digital compare submodule.
• High Resolution Period Capability
Provides the ability to enable high-resolution period. This is discussed in more detail in the devicespecific HRPWM Reference Guide.
• Digital Compare Submodule
The digital compare submodule enhances the event triggering and trip zone submodules by providing
filtering, blanking and improved trip functionality to digital compare signals. Such features are essential
for peak current mode control and for support of analog comparators.
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The ePWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the ePWM is built up from smaller single channel submodules with separate
resources that can operate together as required to form a system. This modular approach results in an
orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to
understand its operation quickly.
In this document, the letter x within a signal or submodule name is used to indicate a generic ePWM
instance on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from
the ePWMx instance. Thus, EPWM1A and EPWM1B belong to ePWM1 and likewise EPWM4A and
EPWM4B belong to ePWM4.

1676

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

14.1.1 Submodule Overview
The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA
and EPWMxB. Multiple ePWM submodules are instanced within a device as shown in Figure 14-1. Each
ePWM instance is identical with one exception. Some instances include a hardware extension that allows
more precise control of the PWM outputs. This extension is the high-resolution pulse width modulator
(HRPWM) and is described in the device-specific High-Resolution Pulse Width Modulator (HRPWM)
chapter. See the device-specific data manual to determine which ePWM instances include this feature.
Each ePWM submodule is indicated by a numerical value starting with 1. For example ePWM1 is the first
instance and ePWM3 is the third instance in the system and ePWMx indicates any instance.
The ePWM submodules are chained together via a clock synchronization scheme that allows them to
operate as a single system when required. Additionally, this synchronization scheme can be extended to
the capture peripheral modules (eCAP). The number of submodules is device-dependent and based on
target application needs. Modules can also operate standalone.
Each ePWM submodule supports the following features:
• Dedicated 16-bit time-base counter with period and frequency control
• Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:
– Two independent PWM outputs with single-edge operation
– Two independent PWM outputs with dual-edge symmetric operation
– One independent PWM output with dual-edge asymmetric operation
• Asynchronous override control of PWM signals through software.
• Programmable phase-control support for lag or lead operation relative to other ePWM modules.
• Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
• Dead-band generation with independent rising and falling edge delay control.
• Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions.
• A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs.
• All events can trigger both CPU interrupts and ADC start of conversion (SOC)
• Programmable event prescaling minimizes CPU overhead on interrupts.
• PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
Each ePWM submodule is connected to the input/output signals shown in Figure 14-1. The signals are
described in detail in subsequent sections.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1677

Introduction

www.ti.com

Figure 14-1. Multiple ePWM Modules
To PWMs

INPUTXBAR5

SYNC SCHEME

INPUTXBAR6
ECCDBLERR
PIEERR

EPWM1TZINT
EPWM1
Module

EPWM1INT

TZ1 to TZ3

EPWM2TZINT
PIE

EPWM2INT

TZ4

EPWMxTZINT

TZ5

EPWMxINT

TZ6

From PWMs

EQEPxERR
CLOCKFAIL
EMUSTOP
EPWM1ENCLK
TBCLKSYNC

TZ1 to TZ3

EPWM XBAR

INPUTXBAR1
INPUTXBAR2
INPUTXBAR3

ECCDBLERR
PIEERR

EPWM2
Module
TZ4
TZ5
TZ6

EQEPxERR

ePWM1A/ePWM1B
H
R
P
W
M

CLOCKFAIL
EMUSTOP
EPWM2ENCLK
TBCLKSYNC

ePWMxA/ePWMxB
G
P
I
O

Peripheral Bus

SOCA1
SOCB1
SOCA2
ADC

ePWM2A/ePWM2B

SOCB2

M
U
X

EQEP1ERR

TZ1 to TZ3

SOCAx

EPWMx
Module

SOCBx

EQEPnERR
TZ4
TZ5
TZ6

EQEPxERR
CLOCKFAIL
EMUSTOP
EPWMxENCLK

PIE

TBCLKSYNC

28x RAM/Flash
ECC

ECCDBLERR
PIEERR

System Control

PIEERR
ECCDBLERR

C28x CPU

Copyright © 2017, Texas Instruments Incorporated

The order in which the ePWM submodules are connected may differ from what is shown in Figure 14-1.
See Figure 16-8 for the synchronization scheme for a particular device. Each ePWM submodule consists
of eight submodules and is connected within a system via the signals shown in Figure 14-2.

1678

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

Figure 14-2. Submodules and Signal Connections for an ePWM Module
EPWMxSYNCI
ECCDBLERR

ePWM module
GPIO
MUX

EPWMxSYNCO

EMUSTOP

COMPxOUT

CLOCKFAIL
EQEPxERR
Time-base (TB) module

EPWMxTZINT
PIE

EPWMxINT
PIEERR

Counter-compare (CC) module

ePWMxA

Action-qualifier (AQ) module

ePWMxB

GPIO
MUX

EPWMxSOCA
ADC

Dead-band (DB) module

EPWMxSOCB

PWM-chopper (PC) module

Peripheral bus

Event-trigger (ET) module

INPUTXBAR

Trip-zone (TZ) module

TZ1 to TZ3

Digital Compare (DC) module

TRIPIN1
TRIPIN2
TRIPIN3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12

Figure 14-3 shows more internal details of a single ePWM submodule. The main signals used by the
ePWM submodules are:
• PWM output signals (EPWMxA and EPWMxB).
The PWM output signals are made available external to the device through the GPIO peripheral
described in the System Control and Interrupts chapter for your device.
• Trip-zone signals (TZ1 to TZ6).
These input signals alert the ePWM submodule of fault conditions external to the ePWM submodule.
Each submodule on a device can be configured to either use or ignore any of the trip-zone signals.
The TZ1 to TZ3 trip-zone signals can be configured as asynchronous inputs through the GPIO
peripheral using the Input X-BAR logic, refer to Figure 14-49. TZ4 is connected to an inverted EQEPx
error signal (EQEPxERR), which can be generated from any one of the EQEP submodule (for those
devices with an EQEP module). TZ5 is connected to the system clock fail logic, and TZ6 is connected
to the EMUSTOP output from the CPU. This allows you to configure a trip action when the clock fails
or the CPU halts.
• Time-base synchronization input (EPWMxSYNCI) and output (EPWMxSYNCO) signals.
The synchronization signals daisy chain the ePWM submodules together. Each submodule can be
configured via INPUTXBAR6 to either use or ignore its synchronization input. The clock
synchronization input and output signal are brought out to pins only for ePWM1 (ePWM module #1).
The ePWM submodules are separated into groups of three for syncing purposes. An external sync
signal (EXTSYNCIN1 or EXTSYNCIN2) may be used to issue a sync signal to the first ePWM
submodule in each chain. These same submodules can also send their EPWMxSYNCOUT signal to a
GPIO. For more information, see Section 14.4.3.3.
• ADC start-of-conversion signals (EPWMxSOCA and EPWMxSOCB).
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1679

Introduction

•

•

1680

www.ti.com

Each ePWM module has two ADC start of conversion signals. Any ePWM submodule can trigger a
start of conversion. Whichever event triggers the start of conversion is configured in the event-trigger
subsubmodule of the ePWM.
Comparator output signals (COMPxOUT).
Output signals from the comparator submodule can be fed through the Input X-BAR to one or all of the
12 trip inputs [TRIPIN1 - TRIPIN12] and in conjunction with the trip zone signals can generate digital
compare events.
Peripheral Bus
The peripheral bus is 32-bits wide and allows both 16-bit and 32-bit writes to the ePWM register file.

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

Figure 14-3. ePWM Submodules and Critical Internal Signal Interconnects
TBCTL2[SYNCOSELX]
Time-Base (TB)
Disable
CTR=CMPC
CTR=CMPD
Rsvd

TBPRD Shadow (24)
TBPRDHR (8)

TBPRD Active (24)

8
CTR=PRD

00
01
10
11

CTR=ZERO
CTR=CMPB

TBCTL[SWFSYNC]

Sync
Out
Select

EPWMxSYNCO

EPWMxSYNCI

TBCTL[PHSEN]

TBCTL[SYNCOSEL]

Counter
Up/Down
(16 Bit)

(A)

DCAEVT1.sync
DCBEVT1.sync(A)
CTR=ZERO

TBCTR
Active (16)

CTR_Dir

CTR=PRD

TBPHSHR (8)
16

8

TBPHS Active (24)

EPWMxINT

CTR=ZERO
CTR=PRD or ZERO

Phase
Control

CTR=CMPA
CTR=CMPB
CTR=CMPC
CTR=CMPD

Counter Compare (CC)
CTR=CMPA

Event
Trigger
and
Interrupt
(ET)

EPWMxSOCA
EPWMxSOCB

ADCSOCOUTSEL

CTR_Dir

Action
Qualifier
(AQ)

DCAEVT1.soc
DCBEVT1.soc

CMPAHR (8)

Select and pulse stretch
for external ADC

(A)
(A)

EPWMSOCAO
EPWMSOCBO

16
CMPA Active (24)
CMPA Shadow (24)

ePWMxA

EPWMA
Dead
Band
(DB)

CMPBHR (8)
16

HiRes PWM (HRPWM)

CMPAHR (8)

CTR=CMPB

On-chip
ADC

PWM
Chopper
(PC)

Trip
Zone
(TZ)
ePWMxB

EPWMB
CMPB Active (24)
CMPB Shadow (24)

CMPBHR (8)
EPWMxTZINT

TBCNT(16)
CTR=CMPC
CMPC[15-0]

16

CMPC Active (16)

TZ1 to TZ3
EMUSTOP

CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter

CLOCKFAIL
EQEPxERR
DCAEVT1.force

CMPC Shadow (16)

DCAEVT2.force
DCBEVT1.force
DCBEVT2.force

TBCNT(16)

(A)
(A)
(A)
(A)

CTR=CMPD
CMPD[15-0]

16

CMPD Active (16)
CMPD Shadow (16)

A

These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1681

Configuring Device Pins

www.ti.com

14.2 Configuring Device Pins
To connect the device input pins to the module, the Input X-BAR must be used. Some examples of when
an external signal may be needed are TZx, TRIPx, and EXTSYNCIN. Any GPIO on the device can be
configured as an input. The GPIO input qualification should be set to asynchronous mode by setting the
appropriate GPxQSEL register bits to 11b. The internal pullups can be configured in the GPyPUD register.
Since the GPIO mode is used, the GPyINV register can invert the signals. Additionally, some TRIPx
(TRIP4-12 excluding TRIP6) signals must be routed through the EPWM X-Bar in addition to the Input XBar.
The GPIO mux registers must be configured for this peripheral. To avoid glitches on the pins, the
GPyGMUX bits must be configured first (while keeping the corresponding GPyMUX bits at the default of
zero), followed by writing the GPyMUX register to the desired value.
See the GPIO chapter for more details on GPIO mux, GPIO settings, and XBAR configuration.

14.3 Overview
Table 14-1 lists the eight key submodules together with a list of their main configuration parameters. For
example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the
counter-compare submodule in Section 14.5 for relevant details.
Table 14-1. Submodule Configuration Parameters
Submodule
Time Base (TB)

Configuration Parameter or Option
• Scale the time-base clock (TBCLK) relative to the EPWM clock (EPWMCLK).
• Configure the PWM time-base counter (TBCTR) frequency or period.
• Set the mode for the time-base counter:

•
•
•
•
•
•

–

count-up mode: used for asymmetric PWM

–

count-down mode: used for asymmetric PWM

– count-up-and-down mode: used for symmetric PWM
Configure the time-base phase relative to another ePWM module.
Synchronize the time-base counter between modules through hardware or software.
Configure the direction (up or down) of the time-base counter after a synchronization event.
Simultaneous writes to the TBPRD registers on all PWM's corresponding to the configuration on
EPWMXLINK.
Configure how the time-base counter will behave when the device is halted by an emulator.
Specify the source for the synchronization output of the ePWM module:
–

Synchronization input signal

–

Time-base counter equal to zero

–

Time-base counter equal to counter-compare B (CMPB)

– No output synchronization signal generated.
• Configure one shot and global load of registers in this module.
Counter Compare (CC)

•
•
•
•

Action Qualifier (AQ)

• Specify the type of action taken when a time-base counter-compare, trip-zone submodule, or
comparator event occurs:

Specify the PWM duty cycle for output EPWMxA and/or output EPWMxB
Specify the time at which switching events occur on the EPWMxA or EPWMxB output
Specify the programmable delay for interrupt and SOC generation with additional comparators
Simultaneous writes to the CMPA, CMPB, CMPC, CMPD registers on all PWM's corresponding
to the configuration on EPWMXLINK.
• Configure one shot and global load of registers in this module.

–

No action taken

–

Output EPWMxA and/or EPWMxB switched high

–

Output EPWMxA and/or EPWMxB switched low

– Output EPWMxA and/or EPWMxB toggled
• Force the PWM output state through software control
• Configure and control the PWM dead band through software
• Configure one shot and global load of registers in this module.

1682Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Overview

www.ti.com

Table 14-1. Submodule Configuration Parameters (continued)
Submodule

Configuration Parameter or Option

Dead Band (DB)

•
•
•
•

PWM Chopper (PC)

•
•
•
•

Trip Zone (TZ)

• Configure the ePWM module to react to one, all, or none of the trip-zone signals or digital
compare events.
• Specify the trip action taken when a fault occurs:

Control of traditional complementary dead-band relationship between upper and lower switches
Specify the output rising-edge-delay value
Specify the output falling-edge delay value
Bypass the dead-band module entirely. In this case the PWM waveform is passed through
without modification.
• Option to enable half-cycle clocking for double resolution.
• Allow ePWMxB phase shifting with respect to the ePWMxA output.
• Configure one shot and global load of registers in this module.
Create a chopping (carrier) frequency.
Pulse width of the first pulse in the chopped pulse train.
Duty cycle of the second and subsequent pulses.
Bypass the PWM chopper module entirely. In this case the PWM waveform is passed through
without modification.

–

Force EPWMxA and/or EPWMxB high

–

Force EPWMxA and/or EPWMxB low

–

Force EPWMxA and/or EPWMxB to a high-impedance state

– Configure EPWMxA and/or EPWMxB to ignore any trip condition.
• Configure how often the ePWM will react to each trip-zone signal:
–
•
•
•
•

One-shot

– Cycle-by-cycle
Enable the trip-zone to initiate an interrupt.
Bypass the trip-zone module entirely.
Programmable option for cycle-by-cycle trip clear
If desired, independently configure trip actions taken when time-base counter is counting down.

Event Trigger (ET)

• Enable the ePWM events that will trigger an interrupt.
• Enable ePWM events that will trigger an ADC start-of-conversion event.
• Specify the rate at which events cause triggers (every occurrence or every 2nd or up to 15th
occurrence)
• Poll, set, or clear event flags

Digital Compare (DC)

• Enables comparator (COMP) module outputs and trip zone signals which are configured using
the Input X-BAR to create events and filtered events
• Specify event-filtering options to capture TBCTR counter, generate blanking window, or insert
delay in PWM output or time-base counter based on captured value.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1683

Time-Base (TB) Submodule

www.ti.com

14.4 Time-Base (TB) Submodule
Each ePWM module has its own time-base submodule that determines all of the event timing for the
ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work
together as a single system. Figure 14-4 illustrates the time-base submodule's place within the ePWM.
Figure 14-4. Time-Base Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals

Time-Base
(TB)

Action
Qualifier
(AQ)

CTR = 0

Digital Compare
Signals

PIE

EPWMxSOCA
ADC
EPWMxSOCB

CTR_Dir
T1
T2

ePWMxA
ePWMxB

CTR = CMPA
Counter
Compare
(CC)

Counter Compare
Signals

EPWMxINT
Event
Trigger
and
Interrupt
(ET)

ePWMxA
ePWMxB
Dead
Band
(DB)

PWMchopper
(PC)

CTR = CMPB
CTR = CMPC

Trip
Zone
(TZ)

CTR = PRD

CTR = CMPD

GPIO
MUX

TZ1 to TZ3

Input X-BAR

EMUSTOP

CPU

CLOCKFAIL

SYSCTRL

CTR = 0
EQEPxERR

EPWMxTZINT
PIE

GPIO
MUX

EQEPx
TZ1 to TZ3

Digital Compare
Signals

Digital
Compare
(DC)

ECCDBLERR
PIEERR
CMPSSx

28x RAM/
Flash ECC

EPWM X-BAR

14.4.1 Purpose of the Time-Base Submodule
You can configure the time-base submodule for the following:
• Specify the ePWM time-base counter (TBCTR) frequency or period to control how often events occur.
• Manage time-base synchronization with other ePWM modules.
• Maintain a phase relationship with other ePWM modules.
• Set the time-base counter to count-up, count-down, or count-up-and-down mode.
• Generate the following events:
– CTR = PRD: Time-base counter equal to the specified period (TBCTR = TBPRD) .
– CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00).
• Configure the rate of the time-base clock; a prescaled version of the EPWM clock (EPWMCLK). This
allows the time-base counter to increment/decrement at a slower rate.
Note: The Type 4 EPWM clocking varies from previous EPWM types. Prior to the Type 4 EPWM, the
time-base submodule was clocked directly by the system clock (SYSCLKOUT). On this version of the
ePWM, there is a divider (EPWMCLKDIV) of the system clock which defaults to EPWMCLK =
SYSCLKOUT / 2.

1684

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Time-Base (TB) Submodule

www.ti.com

14.4.2 Controlling and Monitoring the Time-Base Submodule
The block diagram in Figure 14-5 shows the critical signals and registers of the time-base submodule.
Table 14-2 provides descriptions of the key signals associated with the time-base submodule.
Figure 14-5. Time-Base Submodule Signals and Registers
TBPRD
Period Shadow

TBCTL[PRDLD]

TBPRD
Period Active

TBCTL(SWFSYNC)
DCAEVT1.sync

16

DCBEVT1.sync
CTR = PRD

TBCTR[15:0]

(A)
(A)

EPWMxSYNCI

16
CTR=ZERO

CTR = Zero
Zero
CTR_dir
CTR_max
TBCLK

Dir

Reset
Counter
UP/DOWN Mode

CTR=CMPB

TBCTL[CTRMODE]

Sync
Out
Select

Load

Max

EPWMxSYNCO

TBCTL[SYNCOSEL]

clk
TBCTL2[SYNCOSELX]

TBCTL[PHSEN]

TBCTR
Counter Active Reg

TBCTL[SWFSYNC]

Disable

EPWMxSYNCI

CTR=CMPC
CTR=CMPD
Rsvd

16
TBPHS
Phase Active Reg

SYSCLK

Clock
Prescale

EPWMCLK

EPWMCLK
Prescale

ClkCfgRegs.PERCLKDIVSEL[EPWMCLKDIV]

00
01
10
11

TBCLK

TBCTL[HSPCLKDIV]

TBCTL[CLKDIV]
A. These signals are generated by the digital compare (DC) submodule.

Table 14-2. Key Time-Base Signals
Signal

Description

EPWMxSYNCI

Time-base synchronization input.
Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the
synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM
module in each synchronization chain, this signal may come from a device pin via INPUT5 or INPUT6 of the
Input X-BAR or from a previous ePWM module. For subsequent ePWM modules in each chain, this signal is
passed from another ePWM peripheral. For example, EPWM2SYNCI is generated by the ePWM1 peripheral,
EPWM3SYNCI is generated by ePWM2 and so forth. For information on the synchronization order of a
particular device, see Section 14.4.3.3.

EPWMxSYNCO

Time-base synchronization output.
This output pulse is used to synchronize the counter of an ePWM module later in the synchronization chain.
The ePWM module generates this signal from one of three event sources:
1.
2.
3.

CTR = PRD

EPWMxSYNCI (Synchronization input pulse)
CTR = Zero: The time-base counter equal to zero (TBCTR = 0x00).
CTR = CMPB: The time-base counter equal to the counter-compare B (TBCTR = CMPB) register.

Time-base counter equal to the specified period.
This signal is generated whenever the counter value is equal to the active period register value. That is when
TBCTR = TBPRD.

CTR = Zero

Time-base counter equal to zero
This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x00.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM) 1685

Copyright © 2013–2017, Texas Instruments Incorporated

Time-Base (TB) Submodule

www.ti.com

Table 14-2. Key Time-Base Signals (continued)
Signal

Description

CTR = CMPB

Time-base counter equal to active counter-compare B register (TBCTR = CMPB).
This event is generated by the counter-compare submodule and used by the synchronization out logic

CTR_dir

Time-base counter direction.
Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is
increasing and low when it is decreasing.

CTR_max

Time-base counter equal max value. (TBCTR = 0xFFFF)
Generated event when the TBCTR value reaches its maximum value. This signal is only used only as a status
bit

TBCLK

Time-base clock.
This is a prescaled version of the EPWM clock (EPWMCLK) and is used by all submodules within the ePWM.
This clock determines the rate at which time-base counter increments or decrements.

14.4.3 Calculating PWM Period and Frequency
The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the
time-base counter. Figure 14-6 shows the period (Tpwm) and frequency (Fpwm) relationships for the upcount, down-count, and up-down-count time-base counter modes when the period is set to 4 (TBPRD =
4). The time increment for each step is defined by the time-base clock (TBCLK) which is a prescaled
version of the EPWM clock (EPWMCLK).
The time-base counter has three modes of operation selected by the time-base control register (TBCTL):
• Up-Down-Count Mode:
In up-down-count mode, the time-base counter starts from zero and increments until the period
(TBPRD) value is reached. When the period value is reached, the time-base counter then decrements
until it reaches zero. At this point the counter repeats the pattern and begins to increment.
• Up-Count Mode:
In this mode, the time-base counter starts from zero and increments until it reaches the value in the
period register (TBPRD). When the period value is reached, the time-base counter resets to zero and
begins to increment once again.
• Down-Count Mode:
In down-count mode, the time-base counter starts from the period (TBPRD) value and decrements until
it reaches zero. When it reaches zero, the time-base counter is reset to the period value and it begins
to decrement once again.

1686

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Time-Base (TB) Submodule

www.ti.com

Figure 14-6. Time-Base Frequency and Period
TPWM
4

PRD
4

4

3

3

2

3

2

1

2

1

0

Z 1
0

0

For Up Count and Down Count
TPWM
4

4
3

TPWM = (TBPRD + 1) x TTBCLK
FPWM = 1/ (TPWM)

PRD
4
3

2

3
2

1

2
1

0

1 Z
0

0

TPWM

TPWM

4
3

3

3
2

2
1

14.4.3.1

3
2

2
1

0
CTR_dir

1

1
0

0
Up

For Up and Down Count
TPWM = 2 x TBPRD x TTBCLK
FPWM = 1 / (TPWM)

4

Down

Up

Down

Time-Base Period Shadow Register

The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to
be synchronized with the hardware. The following definitions are used to describe all shadow registers in
the ePWM module:
• Active Register
The active register controls the hardware and is responsible for actions that the hardware causes or
invokes.
• Shadow Register
The shadow register buffers or provides a temporary holding location for the active register. It has no
direct effect on any control hardware. At a strategic point in time the shadow register's content is
transferred to the active register. This prevents corruption or spurious operation due to the register
being asynchronously modified by software.
The memory address of the shadow period register is the same as the active register. Which register is
written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD
shadow register as follows:
• Time-Base Period Shadow Mode:
The TBPRD shadow register is enabled when TBCTL[PRDLD] = 0. Reads from and writes to the
TBPRD memory address go to the shadow register. The shadow register contents are transferred to
the active register (TBPRD (Active) ← TBPRD (shadow)) when the time-base counter equals zero
(TBCTR = 0x00) and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. The
PRDLDSYNC bit is valid only if TBCTL[PRDLD] = 0. By default the TBPRD shadow register is
enabled. The sources for the SYNC input is explained in Section 14.4.3.3.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1687

Time-Base (TB) Submodule

•

www.ti.com

The global load control mechanism can also be used with the time-base period register by configuring
the appropriate bits in the global load configuration register (GLDCFG). When global load mode is
selected the transfer of contents from shadow register to active register, for all registers that have this
mode enabled, occurs at the same event as defined by the configuration bits in Global Shadow to
Active Load Control Register (GLDCTL). Global load control mechanism is explained in Section 14.4.7.
Time-Base Period Immediate Load Mode:
If immediate load mode is selected (TBCTL[PRDLD] = 1), then a read from or a write to the TBPRD
memory address goes directly to the active register.

14.4.3.2 Time-Base Clock Synchronization
The TBCLKSYNC bit in the peripheral clock enable registers allows all users to globally synchronize all
enabled ePWM modules to the time-base clock (TBCLK). When set, all enabled ePWM module clocks are
started with the first rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescalers for
each ePWM module must be set identically.
The proper procedure for enabling ePWM clocks is as follows:
1. Enable ePWM module clocks in the PCLKCRx register
2. Set TBCLKSYNC= 0
3. Configure ePWM modules
4. Set TBCLKSYNC=1
14.4.3.3

Time-Base Counter Synchronization

The ePWM type 4 introduces a new synchronization scheme that allows for increased flexibility of
synchronization of the ePWM modules. Each ePWM module has a synchronization input (SYNCI) and a
synchronization output (SYNCO). In Figure 16-8, EXTSYNC1 is sourced from INPUTXBAR5 and
EXTSYNC2 is sourced from INPUTXBAR6, which can be configured to select any GPIO as the
synchronization input. When configuring the sync chain propagation path using the SYNCSEL registers,
make sure that the longest path does not exceed four ePWM/eCAP modules.

1688

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Time-Base (TB) Submodule

www.ti.com

Figure 14-7. Time-Base Counter Synchronization Scheme
EXTSYNCIN1

EXTSYNCIN2

EPWM1

EPWM1SYNCOUT

EPWM2

EPWM4

EPWM3

EXTSYNCOUT

EPWM4SYNCOUT

Pulse-Stretched
(8 PLLSYSCLK
Cycles)

EPWM5

SYNCSEL.EPWM4SYNCIN

EPWM6

EPWM7

EPWM7SYNCOUT

EPWM8
SYNCSEL.EPWM7SYNCIN

EPWM9

EPWM10

EPWM10SYNCOUT

EPWM11
SYNCSEL.EPWM10SYNCIN

EPWM12

ECAP1
ECAP1SYNCOUT
SYNCSEL.SYNCOUT

SYNCSEL.ECAP1SYNCIN

ECAP2

ECAP3

SYNCSEL.ECAP4SYNCIN

ECAP4

ECAP5

ECAP6

NOTE: See the data manual for the number of ePWM and eCAP modules available on your specific
device.
Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN]
bit is set, then the time-base counter (TBCTR) of the ePWM module will be automatically loaded with the
phase register (TBPHS) contents when one of the following conditions occur:
• EPWMxSYNCI: Synchronization Input Pulse:
The value of the phase register is loaded into the counter register when an input synchronization pulse
is detected (TBPHS → TBCTR). This operation occurs on the next valid time-base clock (TBCLK)
edge.
The delay from internal master module to slave modules is given by:
– if ( TBCLK = EPWMCLK): 2 x EPWMCLK
– if ( TBCLK != EPWMCLK):1 TBCLK
• Software Forced Synchronization Pulse:
Writing a 1 to the TBCTL[SWFSYNC] control bit invokes a software forced synchronization. This pulse
is ORed with the synchronization input signal, and therefore has the same effect as a pulse on
EPWMxSYNCI.
• Digital Compare Event Synchronization Pulse:
DCAEVT1 and DCBEVT1 digital compare events can be configured to generate synchronization
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1689

Time-Base (TB) Submodule

www.ti.com

pulses which have the same affect as EPWMxSYNCI.
This feature enables the ePWM module to be automatically synchronized to the time base of another
ePWM module. Lead or lag phase control can be added to the waveforms generated by different ePWM
modules to synchronize them. In up-down-count mode, the TBCTL[PSHDIR] bit configures the direction of
the time-base counter immediately after a synchronization event. The new direction is independent of the
direction prior to the synchronization event. The PHSDIR bit is ignored in count-up or count-down modes.
See Figure 14-8 through Figure 14-11 for examples.
Clearing the TBCTL[PHSEN] bit configures the ePWM to ignore the synchronization input pulse. The
synchronization pulse can still be allowed to flow-through to the EPWMxSYNCO and be used to
synchronize other ePWM modules. In this way, you can set up a master time-base (for example, ePWM1)
and downstream modules (ePWM2 - ePWMx) may elect to run in synchronization with the master. See
Section 14.13 for more details on synchronization strategies.

14.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM
modules on a device. This bit is part of the device's clock enable registers and is described in the System
Control and Interrupts section of this manual. When TBCLKSYNC = 0, the time-base clock of all ePWM
modules is stopped (default). When TBCLKSYNC = 1, all ePWM time-base clocks are started with the
rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL
register of each ePWM module must be set identically. The proper procedure for enabling the ePWM
clocks is as follows:
1. Enable the individual ePWM module clocks. This is described in the System Control and Interrupts
chapter.
2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
3. Configure the prescaler values and desired ePWM modes.
4. Set TBCLKSYNC = 1.

14.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
For variable frequency applications, there is a need for simultaneous writes of TBPRD and CMPx registers
between ePWM modules. This prevents situations where a CTR = 0 or CTR = PRD pulse forces a
shadow to active load of these registers before all registers are updated between ePWM modules
(resulting in some registers being loaded from new shadow values while others are loaded from old
shadow values). To support this, an ePWM register linking scheme for TBPRD:TBPRDHR,
CMPA:CMPAHR, CMPB:CMPBHR, CMPC, and CMPD registers between PWM modules has been
added.
For a particular ePWM module # A , user code writes “B+1”, to the linked register bit-field in EPWMXLINK.
“B” is the ePWM module # being linked to (that is, writes to the ePWM module “B” TBPRD:TBPRDHR,
CMPA:CMPAHR, CMPB:CMPBHR, or CMPC will simultaneously be written to corresponding register in
ePWM module “A”). For instance if ePWM3 EPWMXLINK register is configured so that CMPA:CMPAHR
are linked to ePWM1, then a write to CMPA:CMPAHR in ePWM 1 will simultaneously write the same
value to CMPA:CMPAHR in ePWM3. If ePWM4 also has its CMPA:CMPAHR registers linked to ePWM1,
then a write to ePWM 1 will write the same value to the CMPA:CMPAHR registers in both ePWM3 and
ePWM4.
The register description for EPWMXLINK clearly explains the linked register bit-field values for
corresponding ePWM.
NOTE:

The ePWM register linking scheme works with the TBPRD:TBPRDHR [Mirrored instance],
CMPA:CMPAHR [Mirrored instance], CMPB:CMPBHR [Mirrored instance], CMPC, and
CMPD registers present in the upper page offset. Only the instance of these registers in
offsets 0x62-0x6B are linked between ePWM modules
A typical example snippet will use the following registers linked between modules
EPwmxRegs.TBPRDHRM2, EPwmxRegs.CMPAM2, EPwmxRegs.CMPBM,
EPwmxRegs.CMPC, EPwmxRegs.CMPD

1690

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Time-Base (TB) Submodule

www.ti.com

14.4.6 Time-Base Counter Modes and Timing Waveforms
The time-base counter operates in one of four modes:
• Up-count mode which is asymmetrical
• Down-count mode which is asymmetrical
• Up-down-count which is symmetrical
• Frozen where the time-base counter is held constant at the current value
To illustrate the operation of the first three modes, the following timing diagrams show when events are
generated and how the time-base responds to an EPWMxSYNCI signal.
Figure 14-8. Time-Base Up-Count Mode Waveforms
TBCTR[15:0]
0xFFFF
TBPRD
(value)

TBPHS
(value)
0000

EPWMxSYNCI

CTR_dir

CTR = zero

CTR = PRD

CNT_max

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1691

Time-Base (TB) Submodule

www.ti.com

Figure 14-9. Time-Base Down-Count Mode Waveforms
TBCTR[15:0]
0xFFFF

TBPRD
(value)
TBPHS
(value)
0x000
EPWMxSYNCI

CTR_dir

CTR = zero

CTR = PRD

CNT_max

Figure 14-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event
TBCTR[15:0]
0xFFFF
TBPRD
(value)
TBPHS
(value)
0x0000
EPWMxSYNCI
UP

UP

UP

UP

CTR_dir
DOWN

DOWN

DOWN

CTR = zero

CTR = PRD

CNT_max

1692

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Time-Base (TB) Submodule

www.ti.com

Figure 14-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event
TBCTR[15:0]
0xFFFF
TBPRD (value)
TBPHS (value)

0x0000
EPWMxSYNCI
UP

UP

UP

CTR_dir
DOWN

DOWN

DOWN

CTR = zero

CTR = PRD

CNT_max

14.4.7 Global Load
Figure 14-12 illustrates the signals and registers associated with the global load feature.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1693

Time-Base (TB) Submodule

www.ti.com

Figure 14-12. Global Load: Signals and Registers
Write 1 to
GLDCTL2[OSHTLD]
CNT_ZRO
PRD_EQ
CNT_ZRO or PRD_EQ
DCAEVT1.sync(A)
SYNCEVT

SYNCEVT
CNT_ZRO
SYNCEVT
PRD_EQ
SYNCEVT
CNT_ZRO or PRD_EQ
GLDCTL2[GFRCLD]

0011

CLR
One
Shot
Latch
Load
Strobe

Set

Q

1

0100

0110

0

0

0101

…

DCBEVT1.sync(A)
EPWMxSYNCI
TBCTL[SWFSYNC]

0000
0001
0010

1
GLDCTL[GLDCNT]

1111
clear CNT
3-bit
Counter
inc CNT

Load
Strobe

Global
Load
Strobe

1

0

Load
Strobe

GLDCTL[OSHTMODE]
Local
Load
Strobe

GLDCTL[GLDMODE]

0

GLDCTL[GLDPRD]
event1
event2
event3
event14

LOADMODE

When this feature is enabled, the transfer of contents from the shadow register to the active register, for
all registers that have this mode enabled, occurs at the same event as defined by the configuration bits in
Global Shadow to Active Load Control Register (GLDCTL[GLDMODE]). When GLDCTL[GLD] = ’1’,
shadow to active load event selection bits for individual shadowed registers are ignored and global load
mode takes effect for the corresponding registers enabled by GLDCFG[REGx].
When GLDCTL[GLD] = ’1’ and GLDCFG[REGx] = ‘0’ global load mode does not affect the corresponding
register (REGx). Shadow to active load event selection bits for individual shadowed registers decide how
the transfer of contents from shadow register to active register takes place.
14.4.7.1 Global Load Pulse Pre-Scalar
This feature provides the capability to choose shadow to active transfers to happen once in ‘N’
occurrences of selected global load pulse (GLDCTL[GLDMODE]). This pre-scale functionality is not
available for registers that cannot or are not configured to use the global load mechanism (that is,
GLDCTL[GLD] = ’0’ or GLDCFG[REGx] = ‘0’).
14.4.7.2 One-Shot Load Mode
This feature allows users to cause the shadow register to active register transfers to occur once. When
GLDCTL2[OSHTLD] = ‘1’ the shadow to active register transfer, for registers that are configured to use the
global load mechanism, takes place on the event selected by GLDCTL[GLDMODE].
Software force loading of contents from shadow register to active register is possible by using
GLDCTL2[GFRCLD]. The GLDCTL2 register can also be linked across multiple PWM modules by using
EPWMXLINK[GLDCTL2LINK]. This, along with the one-shot load mode feature discussed above, provides
a method to correctly update multiple PWM registers in one or more PWM modules at certain PWM
events or, if desired, in the same clock cycle. This is very useful in variable frequency applications and/or
multi-phase interleaved applications.

1694

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Counter-Compare (CC) Submodule

www.ti.com

14.5 Counter-Compare (CC) Submodule
Figure 14-13 illustrates the counter-compare submodule within the ePWM.
Figure 14-13. Counter-Compare Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals

Time-Base
(TB)

Action
Qualifier
(AQ)

CTR = 0

Digital Compare
Signals

PIE

EPWMxSOCA
ADC
EPWMxSOCB

CTR_Dir
T1
T2

ePWMxA
ePWMxB

CTR = CMPA
Counter
Compare
(CC)

Counter Compare
Signals

EPWMxINT
Event
Trigger
and
Interrupt
(ET)

ePWMxA
ePWMxB
Dead
Band
(DB)

PWMchopper
(PC)

CTR = CMPB
CTR = CMPC

Trip
Zone
(TZ)

CTR = PRD

CTR = CMPD

CTR = 0
EPWMxTZINT

GPIO
MUX

TZ1 to TZ3

Input X-BAR

EMUSTOP

CPU

CLOCKFAIL

SYSCTRL

EQEPxERR

PIE

GPIO
MUX

EQEPx
TZ1 to TZ3

Digital Compare
Signals

Digital
Compare
(DC)

ECCDBLERR
PIEERR
COMPxOUT

28x RAM/
Flash ECC

Input X-BAR

14.5.1 Purpose of the Counter-Compare Submodule
The counter-compare submodule takes as input the time-base counter value. This value is continuously
compared to the counter-compare A (CMPA) counter-compare B (CMPB) counter-compare C (CMPC) and
counter-compare D (CMPD )registers. When the time-base counter is equal to one of the compare
registers, the counter-compare unit generates an appropriate event.
The counter-compare:
• Generates events based on programmable time stamps using the CMPA, CMPB, CMPC and CMPD
registers
– CTR = CMPA: Time-base counter equals counter-compare A register (TBCTR = CMPA).
– CTR = CMPB: Time-base counter equals counter-compare B register (TBCTR = CMPB)
– CTR = CMPC: Time-base counter equals counter-compare C register (TBCTR = CMPC).
– CTR = CMPD: Time-base counter equals counter-compare D register (TBCTR = CMPD)
• Controls the PWM duty cycle if the action-qualifier submodule is configured appropriately using
counter-compare A (CMPA) & counter-compare B (CMPB)
• Shadows new compare values to prevent corruption or glitches during the active PWM cycle

14.5.2 Controlling and Monitoring the Counter-Compare Submodule
The counter-compare submodule operation is shown in Figure 14-14.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1695

Counter-Compare (CC) Submodule

www.ti.com

Figure 14-14. Detailed View of the Counter-Compare Submodule
TBCTR[15:0]

Time
Base
(TB)
Module

16
CTR = CMPA

CMPA[15:0]

16

CMPCTL
[LOADASYNC]
Shadow load

(A)

DCAEVT1.sync
(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]

0

CMPCTL
[SHDWAFULL]

CMPA
Compare A Active Reg.
CMPA
Compare A Shadow Reg.

CMPCTL
[LOADAMODE]

Counter
Compare A

Action
Qualifier
(AQ)
Module

CMPCTL
[SHDWAMODE]

16
TBCTR[15:0]

CTR = PRD

CTR = CMPB
CMPB[15:0]

CTR = Zero

16

CMPCTL
[LOADBSYNC]
Shadow load

(A)

DCAEVT1.sync
(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]

0

CMPCTL
[SHDWBFULL]

CMPB
Compare B Active Reg.
CMPB
Compare B Shadow Reg.

CMPCTL
[LOADBMODE]

Counter
Compare B

CMPCTL
[SHDWBMODE]

16
TBCTR[15:0]

CTR = PRD

CTR = CMPC
CMPC[15:0]

CTR = Zero

16

Counter
Compare C

CMPCTL2
[LOADCSYNC]
Shadow load

(A)

DCAEVT1.sync
(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]

0

SOCA
CMPCTL2
[SHDWCMODE]

CMPC
Compare C Active Reg.
CMPC
Compare C Shadow Reg.

CMPCTL2
[LOADCMODE]

Event
Trigger
and
Interrupt
(ET)

SOCB

EPWMxINT

16
TBCTR[15:0]

CTR = PRD

CTR = CMPD
CMPD[15:0]

CTR = Zero

16

Counter
Compare D

CMPCTL2
[LOADDSYNC]
Shadow load

(A)

DCAEVT1.sync
(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]

0

CMPD
Compare D Active Reg.

CMPCTL2
[SHDWDMODE]

CMPD
Compare D Shadow Reg.

CMPCTL2
[LOADDMODE]
CTR = PRD

CTR = Zero

A

These events are generated by the type 4 ePWM digital compare (DC) submodule based on the levels of the TRIPIN
inputs(for example, CMPSSx and TZ signals).

14.5.3 Operational Highlights for the Counter-Compare Submodule
The counter-compare submodule is responsible for generating two independent compare events based on
two compare registers, which is fed to action-qualifier submodule and event trigger submodule :
1. CTR = CMPA: Time-base counter equal to counter-compare A register (TBCTR = CMPA).
2. CTR = CMPB: Time-base counter equal to counter-compare B register (TBCTR = CMPB).

1696

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Counter-Compare (CC) Submodule

www.ti.com

For up-count or down-count mode, each event occurs only once per cycle. For up-down count mode each
event occurs twice per cycle if the compare value is between 0x00-TBPRD and once per cycle if the
compare value is equal to 0x00 or equal to TBPRD. These events are fed into the action-qualifier
submodule where they are qualified by the counter direction and converted into actions if enabled. Refer
to Section 14.6.1 for more details.
The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing
provides a way to keep updates to the registers synchronized with the hardware. When shadowing is
used, updates to the active registers only occur at strategic points. This prevents corruption or spurious
operation due to the register being asynchronously modified by software. The memory address of the
active register and the shadow register is identical. Which register is written to or read from is determined
by the CMPCTL[SHDWAMODE] and CMPCTL[SHDWBMODE] bits. These bits enable and disable the
CMPC shadow register and CMPB shadow register respectively. The behavior of the two load modes is
described below:
Shadow Mode:
The shadow mode for the CMPA is enabled by clearing the CMPCTL[SHDWAMODE] bit and the shadow
register for CMPB is enabled by clearing the CMPCTL[SHDWBMODE] bit. Shadow mode is enabled by
default for both CMPA and CMPB.
If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events as specified by the CMPCTL[LOADAMODE]
CMPCTL[LOADBMODE] CMPCTL[LOADASYNC] & CMPCTL[LOADBSYNC] register bits:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
• SYNC event caused by DCAEVT1 or DCBEVT1 or EPWMxSYNCI or TBCTL[SWFSYNC]
• Both SYNC event or a selection made by LOADAMODE/LOADBMODE
Only the active register contents are used by the counter-compare submodule to generate events to be
sent to the action-qualifier.
Immediate Mode:
If immediate load mode is selected (that is, CMPCTL[SHDWAMODE] = 1 or CMPCTL[SHDWBMODE] =
1), then a read from or a write to the register will go directly to the active register.
Additional Comparators
The counter-compare submodule on ePWMs type 2 and later are responsible for generating two additional
independent compare events based on two compare registers, which is fed to Event Trigger submodule :
1. CTR = CMPC: Time-base counter equal to counter-compare C register (TBCTR = CMPC).
2. CTR = CMPD: Time-base counter equal to counter-compare D register (TBCTR = CMPD).
The counter-compare registers CMPC and CMPD each have an associated shadow register. By default
this register is shadowed. The memory address of the active register and the shadow register is identical.
The value in the active CMPC and CMPD register is compared to the time-base counter (TBCTR). When
the values are equal, the counter compare module generates a “time-base counter equal to counter
compare C or counter compare D ” event respectively. Shadowing of this register is enabled and disabled
by the CMPCTL2[SHDWCMODE] and CMPCTL2[SHDWDMODE] bit. These bits enable and disable the
CMPA shadow register and CMPB shadow register respectively. The behavior of the two load modes is
described below:
Shadow Mode:
The shadow mode for the CMPC is enabled by clearing the CMPCTL2[SHDWCMODE] bit and the
shadow register for CMPD is enabled by clearing the CMPCTL2[SHDWDMODE] bit. Shadow mode is
enabled by default for both CMPC and CMPD.
If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events as specified by the CMPCTL2[LOADCMODE]
CMPCTL2[LOADDMODE] CMPCTL2[LOADCSYNC] & CMPCTL2[LOADDSYNC] register bits:
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1697

Counter-Compare (CC) Submodule

•
•
•
•
•

www.ti.com

CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
Both CTR = PRD and CTR = Zero
SYNC event caused by DCAEVT1 or DCBEVT1 or EPWMxSYNCI or TBCTL[SWFSYNC]
Both SYNC event or a selection made by LOADCMODE/LOADDMODE

Only the active register contents are used by the counter-compare submodule to generate events to be
sent to the action-qualifier.
Immediate Load Mode:
If the immediate load mode is selected (that is, CMPCTL2[SHDWCMODE] = 1 or
CMPCTL2[SHDWDMODE] = 1), then a read from or a write to the register will go directly to the active
register.
Global Load Support
The global load control mechanism can also be used for all counter-compare registers by configuring the
appropriate bits in the global load configuration register (GLDCFG). When the global load mode is
selected the transfer of contents from shadow register to active register, for all registers that have this
mode enabled, occurs at the same event as defined by the configuration bits in the Global Shadow to
Active Load Control Register (GLDCTL). The global load control mechanism is explained in
Section 14.4.7.

14.5.4 Count Mode Timing Waveforms
The counter-compare module can generate compare events in all three count modes:
• Up-count mode: used to generate an asymmetrical PWM waveform.
• Down-count mode: used to generate an asymmetrical PWM waveform.
• Up-down-count mode: used to generate a symmetrical PWM waveform.
To best illustrate the operation of the first three modes, the timing diagrams in Figure 14-15 through
Figure 14-18 show when events are generated and how the EPWMxSYNCI signal interacts.

1698

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Counter-Compare (CC) Submodule

www.ti.com

Figure 14-15. Counter-Compare Event Waveforms in Up-Count Mode
TBCTR[15:0]
0xFFFF
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0x0000
EPWMxSYNCI
CTR = CMPA
CTR = CMPB
NOTE: An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCTR count
sequence. This can lead to a compare event being skipped. This skipping is considered normal operation and
must be taken into account.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1699

Counter-Compare (CC) Submodule

www.ti.com

Figure 14-16. Counter-Compare Events in Down-Count Mode
TBCTR[15:0]
0xFFFF
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0x0000
EPWMxSYNCI
CTR = CMPA
CTR = CMPB

1700

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Action-Qualifier (AQ) Submodule

www.ti.com

Figure 14-17. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event
TBCTR[15:0]
0xFFFF
TBPRD (value)
CMPA (value)
CMPB (value)
TBPHS (value)
0x0000

EPWMxSYNCI
CTR = CMPB

CTR = CMPA

Figure 14-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On
Synchronization Event
TBCTR[15:0]
0xFFFF
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0x0000

EPWMxSYNCI
CTR = CMPB
CTR = CMPA

14.6 Action-Qualifier (AQ) Submodule
Figure 14-19 shows the action-qualifier (AQ) submodule in the ePWM system.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1701

Action-Qualifier (AQ) Submodule

www.ti.com

Figure 14-19. Action-Qualifier Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals

Time-Base
(TB)

Action
Qualifier
(AQ)

CTR = 0

Digital Compare
Signals

PIE

EPWMxSOCA
ADC
EPWMxSOCB

CTR_Dir
T1
T2

ePWMxA
ePWMxB

CTR = CMPA
Counter
Compare
(CC)

Counter Compare
Signals

EPWMxINT
Event
Trigger
and
Interrupt
(ET)

ePWMxA
ePWMxB
Dead
Band
(DB)

PWMchopper
(PC)

CTR = CMPB
CTR = CMPC

Trip
Zone
(TZ)

CTR = PRD

CTR = CMPD

GPIO
MUX

TZ1 to TZ3

Input X-BAR

EMUSTOP

CPU

CLOCKFAIL

CTR = 0

SYSCTRL

EQEPxERR

EPWMxTZINT
PIE

GPIO
MUX

EQEPx
TZ1 to TZ3

Digital Compare
Signals

Digital
Compare
(DC)

ECCDBLERR
PIEERR

28x RAM/
Flash ECC

EPWM X-BAR

The action-qualifier submodule has the most important role in waveform construction and PWM
generation. It decides which events are converted into various action types, thereby producing the
required switched waveforms at the EPWMxA and EPWMxB outputs.

14.6.1 Purpose of the Action-Qualifier Submodule
The action-qualifier submodule is responsible for the following:
• Qualifying and generating actions (set, clear, toggle) based on the following events:
– CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
– CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
– CTR = CMPA: Time-base counter equal to the counter-compare A register (TBCTR = CMPA)
– CTR = CMPB: Time-base counter equal to the counter-compare B register (TBCTR = CMPB)
• T1, T2 events: Trigger events based on comparator, trip or syncin events
• Managing priority when these events occur concurrently
• Providing independent control of events when the time-base counter is increasing and when it is
decreasing

14.6.2 Action-Qualifier Submodule Control and Status Register Definitions
The action-qualifier submodule operation is shown in Figure 14-20 rolled and monitored via the registers
in Section 14.14.

1702

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Action-Qualifier (AQ) Submodule

www.ti.com

Figure 14-20. Action-Qualifier Submodule Inputs and Outputs
Action-qualifier (AQ) Module
AQCTLR[15:0]
Action-qualifier control register
TBCLK

ePWMA

AQCTLA[15:0]
Action-qualifier control A

CTR = PRD
AQCTLB[15:0]
Action-qualifier control B

CTR = Zero
CTR = CMPA

AQSFRC[15:0]
Action-qualifier S/W force
ePWMB

CTR = CMPB
AQCSFRC[3:0] (shadow)
continuous S/W force

CTR_dir
T1

AQCSFRC[3:0] (active)
continuous S/W force

T2

For convenience, the possible input events are summarized again in Table 14-3.
Table 14-3. Action-Qualifier Submodule Possible Input Events
Signal

Description

Registers Compared

CTR = PRD

Time-base counter equal to the period value

TBCTR = TBPRD

CTR = Zero

Time-base counter equal to zero

TBCTR = 0x00

CTR = CMPA

Time-base counter equal to the counter-compare A

TBCTR = CMPA

CTR = CMPB

Time-base counter equal to the counter-compare B

TBCTR = CMPB

T1 event

Based on comparator, trip or syncin events

None

T2 event

Based on comparator, trip or syncin events

None

Software forced event

Asynchronous event initiated by software

The software forced action is a useful asynchronous event. This control is handled by the AQSFRC and
AQCSFRC registers.
The action-qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a
particular event occurs. The event inputs to the action-qualifier submodule are further qualified by the
counter direction (up or down). This allows for independent action on outputs on both the count-up and
count-down phases.
The possible actions imposed on outputs EPWMxA and EPWMxB are:
• Set High:
Set output EPWMxA or EPWMxB to a high level.
• Clear Low:
Set output EPWMxA or EPWMxB to a low level.
• Toggle:
If EPWMxA or EPWMxB is currently pulled high, then pull the output low. If EPWMxA or EPWMxB is
currently pulled low, then pull the output high.
• Do Nothing:
Keep outputs EPWMxA and EPWMxB at same level as currently set. Although the "Do Nothing" option
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1703

Action-Qualifier (AQ) Submodule

www.ti.com

prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this event can still
trigger interrupts and ADC start of conversion. See the Event-trigger submodule description in
Section 14.10 for details.
Actions are specified independently for either output (EPWMxA or EPWMxB). Any or all events can be
configured to generate actions on a given output. For example, both CTR = CMPA and CTR = CMPB can
operate on output EPWMxA. All qualifier actions are configured via the control registers found at the end
of this section.
For clarity, the drawings in this document use a set of symbolic actions. These symbols are summarized in
Figure 14-21. Each symbol represents an action as a marker in time. Some actions are fixed in time (zero
and period) while the CMPA and CMPB actions are moveable and their time positions are programmed
via the counter-compare A and B registers, respectively. To turn off or disable an action, use the "Do
Nothing option"; it is the default at reset.
Figure 14-21. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs

S/W
force
SW

TB Counter equals
Zero
Z

Trigger Events Actions

Comp
A

Comp Period
B

T1

T2

CA

CB

P

T1

T2

SW

Z

CA

CB

P

T1

T2

SW

Z

CA

CB

P

T1

T2

SW

Z

CA

CB

P

T1

T2

Do Nothing

Clear Lo

Set Hi

Toggle

The Action Qualifier Trigger Event Source Selection register (AQTSRCSEL) is used to select the source
for T1 and T2 events. T1/T2 selection and configuration of a trip/digital-compare event in Action Qualifier
submodule is independent of the configuration of that event in the Trip-Zone submodule. A particular trip
event may or may not be configured to cause trip action in the Trip Zone submodule, but the same event
can be used by the Action Qualifier to generate T1/T2 for controlling PWM generation.

1704

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Action-Qualifier (AQ) Submodule

www.ti.com

14.6.3 Action-Qualifier Event Priority
It is possible for the ePWM action qualifier to receive more than one event at the same time. In this case
events are assigned a priority by the hardware. The general rule is events occurring later in time have a
higher priority and software forced events always have the highest priority. The event priority levels for updown-count mode are shown in Table 14-4. A priority level of 1 is the highest priority and level 10 is the
lowest. The priority changes slightly depending on the direction of TBCTR.
Table 14-4. Action-Qualifier Event Priority for Up-Down-Count Mode
Priority Level

Event If TBCTR is Incrementing
TBCTR = Zero up to TBCTR = TBPRD

Event If TBCTR is Decrementing
TBCTR = TBPRD down to TBCTR = 1

1 (Highest)

Software forced event

Software forced event

2

T1 on up-count (T1U)

T1 on down-count (T1D)

3

T2 on up-count (T2U)

T2 on down-count (T2D)

4

Counter equals CMPB on up-count (CBU)

Counter equals CMPB on down-count (CBD)

5

Counter equals CMPA on up-count (CAU)

Counter equals CMPA on down-count (CAD)

6

Counter equals zero

Counter equals period (TBPRD)

7

T1 on down-count (T1D)

T1 on up-count (T1U)

8

T2 on down-count (T2D)

T2 on up-count (T2U)

9

Counter equals CMPB on down-count (CBD)

Counter equals CMPB on up-count (CBU)

10 (Lowest)

Counter equals CMPA on down-count (CAD)

Counter equals CMPA on up-count (CBU)

Table 14-5 shows the action-qualifier priority for up-count mode. In this case, the counter direction is
always defined as up and thus down-count events will never be taken.
Table 14-5. Action-Qualifier Event Priority for Up-Count Mode
Priority Level
1 (Highest)

Event
Software forced event

2

Counter equal to period (TBPRD)

3

T1 on up-count (T1U)

4

T2 on up-count (T2U)

5

Counter equal to CMPB on up-count (CBU)

6

Counter equal to CMPA on up-count (CAU)

7 (Lowest)

Counter equal to Zero

Table 14-6 shows the action-qualifier priority for down-count mode. In this case, the counter direction is
always defined as down and thus up-count events will never be taken.
Table 14-6. Action-Qualifier Event Priority for Down-Count Mode
Priority Level

Event

1 (Highest)

Software forced event

2

Counter equal to Zero

3

T1 on down-count (T1D)

4

T2 on down-count (T2D)

5

Counter equal to CMPB on down-count (CBD)

6

Counter equal to CMPA on down-count (CAD)

7(Lowest)

Counter equal to period (TBPRD)

It is possible to set the compare value greater than the period. In this case the action will take place as
shown in Table 14-7.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1705

Action-Qualifier (AQ) Submodule

www.ti.com

Table 14-7. Behavior if CMPA/CMPB is Greater than the Period
Counter Mode

Compare on Up-Count Event
CAD/CBD

Compare on Down-Count Event
CAD/CBD

Up-Count Mode

If CMPA/CMPB ≤ TBPRD period, then the event
occurs on a compare match (TBCTR=CMPA or
CMPB).

Never occurs.

If CMPA/CMPB > TBPRD, then the event will not
occur.
Down-Count Mode Never occurs.

If CMPA/CMPB < TBPRD, the event will occur on a
compare match (TBCTR=CMPA or CMPB).
If CMPA/CMPB ≥ TBPRD, the event will occur on a
period match (TBCTR=TBPRD).

Up-Down-Count
Mode

If CMPA/CMPB < TBPRD and the counter is
incrementing, the event occurs on a compare match
(TBCTR=CMPA or CMPB).

If CMPA/CMPB < TBPRD and the counter is
decrementing, the event occurs on a compare match
(TBCTR=CMPA or CMPB).

If CMPA/CMPB is ≥ TBPRD, the event will occur on a
period match (TBCTR = TBPRD).

If CMPA/CMPB ≥ TBPRD, the event occurs on a
period match (TBCTR=TBPRD).

14.6.4 AQCTLA and AQCTLB Shadow Mode Operations
To enable Action Qualifier mode changes which must occur at the end of a period even when the phase
changes, shadowing of the AQCTLA and AQCTLB registers has been added on ePWMs type 2 and later.
Additionally, shadow to active load on SYNC of these registers is supported as well. Shadowing of this
register is enabled and disabled by the AQCTLR[SHDWAQAMODE] and AQCTLR[SHDWAQBMODE]
bits. These bits enable and disable the AQCTLA shadow register and AQCTLB shadow register,
respectively. The behavior of the two load modes is described below:
Shadow Mode:
The shadow mode for the AQCTLA is enabled by setting the AQCTLR[SHDWAQAMODE] bit, and the
shadow register for AQCTLB is enabled by setting the AQCTLR[SHDWAQBMODE] bit. Shadow mode is
disabled by default for both AQCTLA and AQCTLB
If the shadow register is enabled, then the content of the shadow register is transferred to the active
register on one of the following events as specified by the AQCTLR[LDAQAMODE]
AQCTLR[LDAQBMODE] AQCTLR[LDAQASYNC] & AQCTLR[LDAQBSYNC] register bits:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
• SYNC event caused by DCAEVT1 or DCBEVT1 or EPWMxSYNCI or TBCTL[SWFSYNC]
• Both SYNC event or a selection made by LDAQAMODE/LDAQBMODE
Global Load Support
Global load control mechanism can also be used for AQCTLA:AQCTLA2, AQCTLB:AQCTLB2 and
AQCSFRC registers by configuring the appropriate bits in the global load configuration register
(GLDCFG). When global load mode is selected, the transfer of contents from shadow register to active
register for all registers that have this mode enabled, occurs at the same event as defined by the
configuration bits in the Global Shadow to Active Load Control Register (GLDCTL). The global load control
mechanism is explained in Section 14.4.7.
Immediate Load Mode:
If immediate load mode is selected (that is, AQCTLR[SHDWAQAMODE] = 0 or
AQCTLR[SHDWAQBMODE] = 0), then a read from or a write to the register will go directly to the active
register. See Figure 14-22 and Figure 14-23.

1706

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Action-Qualifier (AQ) Submodule

www.ti.com

NOTE: Shadow to Active Load of Action Qualifier Output A/B Control Register [AQCTLA &
AQCTLB] on CMPA = 0 or CMPB = 0 boundary
If the Counter-Compare A Register (CMPA) or Counter-Compare B Register (CMPB) is set
to a value of 0 and the action qualifier action on AQCTLA and AQCTLB is configured to
occur in the same instant as a shadow to active load (that is, CMPA=0 and AQCTLA shadow
to active load on TBCTR=0 using AQCTLR register LDAQAMODE and LDAQAMODE bits),
then both events enter contention and it is recommended to use a Non-Zero CounterCompare when using Shadow to Active Load of Action Qualifier Output A/B Control Register
on TBCTR = 0 boundary.

Figure 14-22. AQCTLR[SHDWAQAMODE]
AQCTLR
[LDAQASYNC]
0

(A)

DCAEVT1.sync(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]

11

16
Load
Strobe

10
01

AQCTLA(16)
Active Reg

00

AQCTLR
[LDAQAMODE]

AQCTLA(16)
Shadow Reg
AQCTLR[SHDWAQAMODE]

CTR = PRD

01
10
00

CTR = Zero

Figure 14-23. AQCTLR[SHDWAQBMODE]
AQCTLR
[LDAQBSYNC]
0

(A)

DCAEVT1.sync(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]

16

11
10

Load
Strobe
AQCTLB(16)
Active Reg

01

AQCTLR
[LDAQBMODE]

00

AQCTLB(16)
Shadow Reg

AQCTLR[SHDWAQBMODE]
CTR = PRD

01
10

CTR = Zero

00

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1707

Action-Qualifier (AQ) Submodule

www.ti.com

14.6.5 Waveforms for Common Configurations
NOTE:

The waveforms in this document show the behavior of the ePWMs for a static compare
register value. In a running system, the active compare registers (CMPA and CMPB) are
typically updated from their respective shadow registers once every period. The user
specifies when the update will take place; either when the time-base counter reaches zero or
when the time-base counter reaches period. There are some cases when the action based
on the new value can be delayed by one period or the action based on the old value can
take effect for an extra period. Some PWM configurations avoid this situation. These include,
but are not limited to, the following:

Use up-down-count mode to generate a symmetric PWM:
• If you load CMPA/CMPB on zero, then use CMPA/CMPB values greater
than or equal to 1.
• If you load CMPA/CMPB on period, then use CMPA/CMPB values less than
or equal to TBPRD-1.
This means there will always be a pulse of at least one TBCLK cycle in a
PWM period which, when very short, tend to be ignored by the system.
Use up-down-count mode to generate an asymmetric PWM:
• To achieve 50%-0% asymmetric PWM use the following configuration: Load
CMPA/CMPB on period and use the period action to clear the PWM and a
compare-up action to set the PWM. Modulate the compare value from 0 to
TBPRD to achieve 50%-0% PWM duty.
When using up-count mode to generate an asymmetric PWM:
• To achieve 0-100% asymmetric PWM use the following configuration: Load
CMPA/CMPB on TBPRD. Use the Zero action to set the PWM and a
compare-up action to clear the PWM. Modulate the compare value from 0 to
TBPRD+1 to achieve 0-100% PWM duty.
See the Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100%
Duty Cycle Control Application Report (literature number SPRAAI1)
Figure 14-24 shows how a symmetric PWM waveform can be generated using the up-down-count mode
of the TBCTR. In this mode, 0%-100% DC modulation is achieved by using equal compare matches on
the up count and down count portions of the waveform. In the example shown, CMPA is used to make the
comparison. When the counter is incrementing the CMPA match will pull the PWM output high. Likewise,
when the counter is decrementing the compare match will pull the PWM signal low. When CMPA = 0, the
PWM signal is low for the entire period giving the 0% duty waveform. When CMPA = TBPRD, the PWM
signal is high achieving 100% duty.
When using this configuration in practice, if you load CMPA/CMPB on zero, then use CMPA/CMPB values
greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or
equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period
which, when very short, tend to be ignored by the system.

1708

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Action-Qualifier (AQ) Submodule

www.ti.com

Figure 14-24. Up-Down-Count Mode Symmetrical Waveform
4

4
Mode: Up-Down Count
TBPRD = 4
CAU = SET, CAD = CLEAR
0% - 100% Duty

3

TBCTR

1

1

1

1

2

2

2

2

3

3

3

0

0

0

TBCTR Direction
UP

DOWN

DOWN

UP

Case 1:
CMPA = 4, 0% Duty

EPWMxA/EPWMxB

Case 2:
CMPA = 3, 25% Duty

EPWMxA/EPWMxB

Case 3:
CMPA = 2, 50% Duty

EPWMxA/EPWMxB

Case 3:
CMPA = 1, 75% Duty

EPWMxA/EPWMxB

Case 4:
CMPA = 0, 100% Duty

EPWMxA/EPWMxB

The PWM waveforms in Figure 14-25 through Figure 14-30 show some common action-qualifier
configurations. Some conventions used in the figures and examples are as follows:
• TBPRD, CMPA, and CMPB refer to the value written in their respective registers. The active register,
not the shadow register, is used by the hardware.
• CMPx, refers to either CMPA or CMPB.
• EPWMxA and EPWMxB refer to the output signals from ePWMx
• Up-Down means Count-up-and-down mode, Up means up-count mode and Dwn means down-count
mode
• Sym = Symmetric, Asym = Asymmetric

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1709

Action-Qualifier (AQ) Submodule

www.ti.com

Figure 14-25. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High
TBCTR
TBPRD
value

Z

P

CB

CA

Z

P

CB

CA

Z

P

Z

P

CB

CA

Z

P

CB

CA

Z

P

EPWMxA

EPWMxB

A

1710

PWM period = (TBPRD + 1 ) × TTBCLK

B

Duty modulation for EPWMxA is set by CMPA, and is active high (that is, high time duty proportional to CMPA).

C

Duty modulation for EPWMxB is set by CMPB and is active high (that is, high time duty proportional to CMPB).

D

The "Do Nothing" actions ( X ) are shown for completeness, but will not be shown on subsequent diagrams.

E

Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period.
TBCTR wraps from period to 0000.

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Action-Qualifier (AQ) Submodule

www.ti.com

Figure 14-26. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low
TBCTR
TBPRD
value

P

CA

P

CA

P

EPWMxA

P

CB

CB

P

P

EPWMxB

A

PWM period = (TBPRD + 1 ) × TTBCLK

B

Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA).

C

Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).

D

Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period.
TBCTR wraps from period to 0000.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1711

Action-Qualifier (AQ) Submodule

www.ti.com

Figure 14-27. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on
EPWMxA
TBCTR
TBPRD
value

CB

CA

CA

CB

EPWMxA

Z
T

Z
T

Z
T

EPWMxB
A

PWM frequency = 1/( (TBPRD + 1 ) × TTBCLK )

B

Pulse can be placed anywhere within the PWM cycle (0000 - TBPRD)

C

High time duty proportional to (CMPB - CMPA)

Figure 14-28. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on
EPWMxA and EPWMxB — Active Low
TBCTR
TBPRD
value

CA

CA

CA

CA

EPWMxA

CB

CB

CB

CB

EPWMxB

A

1712

PWM period = 2 x TBPRD × TTBCLK

B

Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA).

C

Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).

D

Outputs EPWMxA and EPWMxB can drive independent power switches.

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Action-Qualifier (AQ) Submodule

www.ti.com

Figure 14-29. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on
EPWMxA and EPWMxB — Complementary
TBCTR
TBPRD
value

CA

CA

CA

CA

EPWMxA

CB

CB

CB

CB

EPWMxB

A

PWM period = 2 × TBPRD × TTBCLK

B

Duty modulation for EPWMxA is set by CMPA, and is active low, that is, low time duty proportional to CMPA.

C

Duty modulation for EPWMxB is set by CMPB and is active high, that is, high time duty proportional to CMPB.

D

Outputs EPWMx can drive upper/lower (complementary) power switches.

E

Dead-band = CMPB - CMPA (fully programmable edge placement by software). Note the dead-band module is also
available if the more classical edge delay method is required.

Figure 14-30. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on
EPWMxA—Active Low
TBCTR

CA

CA

CB

CB

EPWMxA

Z

P

Z

P

EPWMxB
A

PWM period = 2 × TBPRD × TBCLK

B

Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse placement
techniques.

C

Duty modulation for EPWMxA is set by CMPA and CMPB.

D

Low time duty for EPWMxA is proportional to (CMPA + CMPB).

E

To change this example to active high, CMPA and CMPB actions need to be inverted (that is, Clear on CMPA, Set on
CMPB).

F

Duty modulation for EPWMxB is fixed at 50% (utilizes spare action resources for EPWMxB).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1713

Dead-Band Generator (DB) Submodule

www.ti.com

Figure 14-31. Up-Down-Count, PWM Waveform Generation Utilizing T1 and T2 Events
TBCTR

T1U

T1D

T1U

T1D

EPWMxA

T2U

T2D

T2U

T2D

EPWMxB

A

PWM period = 2 × TBPRD × TTBCLK

B

Independent T1 event actions when counter is counting up and when it is counting down are used to generate
EPWMxA output.

C

Independent T2 event actions when counter is counting up and when it is counting down are used to generate
EPWMxB output.

D

TZ1 is selected as the source for T1.

E

TZ2 is selected as the source for T2.

14.7 Dead-Band Generator (DB) Submodule
Figure 14-32 illustrates the dead-band submodule within the ePWM module.
Figure 14-32. Dead_Band Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals

Time-Base
(TB)

Action
Qualifier
(AQ)

CTR = 0

Digital Compare
Signals

PIE

EPWMxSOCA
ADC
EPWMxSOCB

CTR_Dir
T1
T2

ePWMxA
ePWMxB

CTR = CMPA
Counter
Compare
(CC)

Counter Compare
Signals

EPWMxINT
Event
Trigger
and
Interrupt
(ET)

ePWMxA
ePWMxB
Dead
Band
(DB)

PWMchopper
(PC)

CTR = CMPB
CTR = CMPC

Trip
Zone
(TZ)

CTR = PRD

CTR = CMPD

GPIO
MUX

TZ1 to TZ3

Input X-BAR

EMUSTOP

CPU

CLOCKFAIL

CTR = 0

SYSCTRL

EQEPxERR

EPWMxTZINT
PIE

GPIO
MUX

EQEPx
TZ1 to TZ3

Digital Compare
Signals

Digital
Compare
(DC)

ECCDBLERR
PIEERR

28x RAM/
Flash ECC

EPWM X-BAR

1714

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Dead-Band Generator (DB) Submodule

www.ti.com

14.7.1 Purpose of the Dead-Band Submodule
The action-qualifier (AQ) module section discussed how it is possible to generate the required dead band
by having full control over edge placement using both the CMPA and CMPB resources of the ePWM
module. However, if the more classical edge delay-based dead band with polarity control is required, then
the dead-band submodule described here should be used.
The key functions of the dead-band module are:
• Generating appropriate signal pairs (EPWMxA and EPWMxB) with dead-band relationship from a
single EPWMxA input
• Programming signal pairs for:
– Active high (AH)
– Active low (AL)
– Active high complementary (AHC)
– Active low complementary (ALC)
• Adding programmable delay to rising edges (RED)
• Adding programmable delay to falling edges (FED)
• Can be totally bypassed from the signal path (note dotted lines in diagram)

14.7.2 Dead-band Submodule Additional Operating Modes
On type 1 ePWM RED could appear on one channel output and FED could appear on the other channel
output.
The following list shows the distinct difference between type 1 and type 4 modules with respect to deadband operating modes:
• By adding S6, S7, and S8 in Figure 14-33, RED and FED can appear on both the A-channel and Bchannel outputs. Additionally, both RED and FED together can be applied to either the A-channel or Bchannel outputs to allow B-channel phase shifting with respect to the A-channel.
Note: Phase shifting B-channel with respect to the A-channel using the dead-band submodule
additional operating modes has limitations with respect to the choice of RED and FED delay with
respect to the operating duty cycle of the ePWMxA and ePWMxB outputs.
• The dead-band counters have also been increased to 14 bits
• Dead-band and dead-band High-resolution registers are now shadowed.
• High-resolution dead-band RED and FED have been enabled using the DBREDHR and DBFEDHR
registers
NOTE: The PWM chopper will not be enabled when high-resolution dead band is enabled.

NOTE: High-resolution dead-band RED and FED requires Half-Cycle clocking mode
(DBCTL[HALFCYCLE] = 1).
Cannot have both RED and FED together applied to both ePWMxA and ePWMxB. RED and
FED together can be applied only to either OutA OR OutB.

NOTE: Phase shifting B-channel with respect to the A-channel: When PWMxB is derived from
PWMxA using the DEDB_MODE bit and by delaying rising edge and falling edge by the
phase shift amount. When the duty cycle value on PWMxA is less than this phase shift
amount, PWMxA’s falling edge has precedence over the delayed rising edge for PWMxB. It
is recommended to make sure the duty cycle value of the current waveform fed to the deadband module is greater than the required phase shift amount.

Shadow Mode:

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1715

Dead-Band Generator (DB) Submodule

www.ti.com

The shadow mode for the DBRED is enabled by setting the DBCTL[SHDWDBREDMODE] bit and the
shadow register for DBFED is enabled by setting the DBCTL [SHDWDBFEDMODE] bit. Shadow mode is
disabled by default for both DBRED and DBFED
If the shadow register is enabled, then the content of the shadow register is transferred to the active
register on one of the following events as specified by the DBCTL [LOADREDMODE] & DBCTL
[LOADFEDMODE] register bits:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
The DBCTL register can be shadowed. The shadow mode for DBCTL is enabled by setting the
DBCTL2[SHDWDBCTLMODE] bit. If the shadow register is enabled then the content of the shadow
register is transferred to the active register on one of the following events as specified by the
DBCTL2[LOADDBCTLMODE] register bit:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD)
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
Global Load Support
Global load control mechanism can also be used for DBRED:DBREDHR, DBFED:DBFEDHR and DBCTL
registers by configuring the appropriate bits in the global load configuration register (GLDCFG). When
global load mode is selected the transfer of contents from shadow register to active register, for all
registers that have this mode enabled, occurs at the same event as defined by the configuration bits in the
Global Shadow to Active Load Control Register (GLDCTL). The global load control mechanism is
explained in Section 14.4.7.
NOTE: When DBRED/DBFED active is loaded with a new shadow value while DB counters are
counting, the new DBRED / DBFED value only affects the NEXT PWMx edge and not the
current edge.

14.7.3 Operational Highlights for the Dead-Band Submodule
The configuration options for the dead-band submodule are shown in Figure 14-33.

1716

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Dead-Band Generator (DB) Submodule

www.ti.com

Figure 14-33. Configuration Options for the Dead-Band Submodule
ePWMxA
DBCTL
[LOADREDMODE]

Rising Edge
Delay
DBRED
Shadow

0

1

DBRED
Active Out
In
(14-bit counter)

S4

0

0

A path

0

RED
1

1

S2

S6
OutA

S1
1

0
S8

1

Falling Edge
Delay
1

0
S5
1

0

S8

DBFED
Active Out
In
(14-bit counter)
DBFED
Shadow

0 S7
0 S3

FED

1

OutB

1 S0
0

1
B path

DBCTL
[LOADFEDMODE]

DBCTL[HALFCYCLE]
ePWMxB
DBCTL[OUT_MODE]
DBCTL[IN_MODE]

DBCTL[DEDB_MODE]

DBCTL[POLSEL]

DBCTL[OUTSWAP]

Although all combinations are supported, not all are typical usage modes. Table 14-8 documents some
classical dead-band configurations. These modes assume that the DBCTL[IN_MODE] is configured such
that EPWMxA In is the source for both falling-edge and rising-edge delay. Enhanced, or non-traditional
modes can be achieved by changing the input signal source. The modes shown in Table 14-8 fall into the
following categories:
• Mode 1: Bypass both falling-edge delay (FED) and rising-edge delay (RED)
Allows you to fully disable the dead-band submodule from the PWM signal path.
• Mode 2-5: Classical Dead-Band Polarity Settings:
These represent typical polarity configurations that should address all the active high/low modes
required by available industry power switch gate drivers. The waveforms for these typical cases are
shown in Figure 14-34. Note that to generate equivalent waveforms to Figure 14-34, configure the
action-qualifier submodule to generate the signal as shown for EPWMxA.
• Mode 6: Bypass rising-edge-delay and Mode 7: Bypass falling-edge-delay
Finally the last two entries in Table 14-8 show combinations where either the falling-edge-delay (FED)
or rising-edge-delay (RED) blocks are bypassed.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM) 1717

Copyright © 2013–2017, Texas Instruments Incorporated

Dead-Band Generator (DB) Submodule

www.ti.com

Table 14-8. Classical Dead-Band Operating Modes
Mode

DBCTL[POLSEL]

Mode Description

S1

S0

EPWMxA and EPWMxB Passed Through (No Delay)

X

X

0

0

2

Active High Complementary (AHC)

1

0

1

1

3

Active Low Complementary (ALC)

0

1

1

1

4

Active High (AH)

0

0

1

1

5

Active Low (AL)

1

1

1

1

0 or 1

0 or 1

0

1

0 or 1

0 or 1

1

0

6

EPWMxB Out = EPWMxA In with Falling Edge Delay
EPWMxA Out = EPWMxA In with Rising Edge Delay

7

EPWMxB Out = EPWMxB In with No Delay

S2

DBCTL[OUT_MODE]

1

EPWMxA Out = EPWMxA In (No Delay)

S3

Table 14-9. Additional Dead-Band Operating Modes
DBCTL[DEDBMODE]
Mode Description

DBCTL[OUTSWAP]

S8

S6

S7

EPWMxA and EPWMxB signals are as defined by OUT-MODE bits.

0

0

0

EPWMxA = A-path as defined by OUT-MODE bits.

0

0

1

0

1

0

0

1

1

0

X

X

1

X

X

EPWMxB = A-path as defined by OUT-MODE bits (rising edge delay or delaybypassed A-signal path)
EPWMxA = B-path as defined by OUT-MODE bits (falling edge delay or delaybypassed B-signal path)
EPWMxB = B-path as defined by OUT-MODE bits
EPWMxA = B-path as defined by OUT-MODE bits (falling edge delay or delaybypassed B-signal path)
EPWMxB = A-path as defined by OUT-MODE bits (rising edge delay or delaybypassed A-signal path)
Rising edge delay applied to EPWMxA / EPWMxB as selected by S4 switch (INMODE bits) on A signal path only.
Falling edge delay applied to EPWMxA / EPWMxB as selected by S5 switch (INMODE bits) on B signal path only.
Rising edge delay and falling edge delay applied to source selected by S4 switch
(IN-MODE bits) and output to B signal path only. (1)
(1)

1718

When this bit is set to 1, user should always either set OUT_MODE bits such that Apath = InA or OUTSWAP bits such that
EPWMxA=Bpath. Otherwise, EPWMxA will be invalid.

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Dead-Band Generator (DB) Submodule

www.ti.com

Figure 14-34 shows waveforms for typical cases where 0% < duty < 100%.
Figure 14-34. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
Period
Original
(outA)
RED
Rising Edge
Delayed (RED)
FED
Falling Edge
Delayed (FED)

Active High
Complementary
(AHC)

Active Low
Complementary
(ALC)

Active High
(AH)

Active Low
(AL)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1719

Dead-Band Generator (DB) Submodule

www.ti.com

The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED)
delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit
registers and their value represents the number of time-base clock (TBCLK) periods by which a signal
edge is delayed. For example, the formula to calculate falling-edge-delay and rising-edge-delay is:
FED = DBFED × TTBCLK
RED = DBRED × TTBCLK
Where TTBCLK is the period of TBCLK, the prescaled version of EPWMCLK.
For convenience, delay values for various TBCLK options are shown in Table 14-10. The ePWM input
clock frequency that these delay values have been computed by is 100 MHz.
Table 14-10. Dead-Band Delay Values in μS as a Function of DBFED and DBRED
Dead-Band Value

Dead-Band Delay in μS

DBFED, DBRED

TBCLK = EPWMCLK/1

TBCLK = EPWMCLK /2

TBCLK = EPWMCLK/4

1

0.01

0.02

0.04

5

0.05

0.1

0.2

10

0.1

0.2

0.4

100

1

2

4

200

2

4

8

400

4

8

16

500

5

10

20

600

6

12

24

700

7

14

28

800

8

16

32

900

9

18

36

1000

10

20

40

When half-cycle clocking is enabled, the formula to calculate the falling-edge-delay and rising-edge-delay
becomes:
FED = DBFED × TTBCLK/2
RED = DBRED × TTBCLK/2

1720

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

PWM Chopper (PC) Submodule

www.ti.com

14.8 PWM Chopper (PC) Submodule
Figure 14-35 illustrates the PWM chopper (PC) submodule within the ePWM module.
Figure 14-35. PWM Chopper Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals

Time-Base
(TB)

Action
Qualifier
(AQ)

CTR = 0

Digital Compare
Signals

PIE

EPWMxSOCA
ADC
EPWMxSOCB

CTR_Dir

ePWMxA
ePWMxB
CTR = CMPA
Counter
Compare
(CC)

Counter Compare
Signals

EPWMxINT
Event
Trigger
and
Interrupt
(ET)

ePWMxA
ePWMxB
Dead
Band
(DB)

PWMchopper
(PC)

CTR = CMPB
CTR = CMPC

Trip
Zone
(TZ)

CTR = PRD

CTR = CMPD

CTR = 0
EPWMxTZINT

GPIO
MUX

TZ1 to TZ3

Input X-BAR

EMUSTOP

CPU

CLOCKFAIL

SYSCTRL

EQEPxERR

PIE

GPIO
MUX

EQEPx
TZ1 to TZ3

Digital Compare
Signals

Digital
Compare
(DC)

ECCDBLERR
PIEERR

28x RAM/
Flash ECC

ePWM X-BAR

The PWM chopper submodule allows a high-frequency carrier signal to modulate the PWM waveform
generated by the action-qualifier and dead-band submodules. This capability is important if you need
pulse transformer-based gate drivers to control the power switching elements.

14.8.1 Purpose of the PWM Chopper Submodule
The key functions of the PWM chopper submodule are:
• Programmable chopping (carrier) frequency
• Programmable pulse width of first pulse
• Programmable duty cycle of second and subsequent pulses
• Can be fully bypassed if not required

14.8.2 Operational Highlights for the PWM Chopper Submodule
Figure 14-36 shows the operational details of the PWM chopper submodule. The carrier clock is derived
from EPWMCLK. Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in the
PCCTL register. The one-shot block is a feature that provides a high energy first pulse to ensure hard and
fast power switch turn on, while the subsequent pulses sustain pulses, ensuring the power switch remains
on. The one-shot width is programmed via the OSHTWTH bits. The PWM chopper submodule can be fully
disabled (bypassed) via the CHPEN bit.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1721

PWM Chopper (PC) Submodule

www.ti.com

Figure 14-36. PWM Chopper Submodule Operational Details
Bypass
0
EPWMxA
EPWMxA

Start
One
shot

OSHT

PWMA_ch

1

Clk
Pulse-width
EPWMCLK

/8

PCCTL
[OSHTWTH]
PCCTL
[OSHTWTH]
Pulse-width

Divider and
duty control

PCCTL
[CHPEN]

PSCLK

PCCTL[CHPFREQ]
PCCTL[CHPDUTY]

Clk
One
shot
EPWMxB

PWMB_ch
1

OSHT

EPWMxB

Start
Bypass

0

14.8.3 Waveforms
Figure 14-37 shows simplified waveforms of the chopping action only; one-shot and duty-cycle control are
not shown. Details of the one-shot and duty-cycle control are discussed in the following sections.
Figure 14-37. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only
EPWMxA

EPWMxB

PSCLK

EPWMxA

EPWMxB

1722

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

PWM Chopper (PC) Submodule

www.ti.com

14.8.3.1

One-Shot Pulse

The width of the first pulse can be programmed to any of 16 possible pulse width values. The width or
period of the first pulse is given by:
T1stpulse = TEPWMCLK × 8 × OSHTWTH
Where TEPWMCLK is the period of the system clock (EPWMCLK) and OSHTWTH is the four control bits
(value from 1 to 16)
Figure 14-38 shows the first and subsequent sustaining pulses and Table 14-11 gives the possible pulse
width values for a EPWMCLK = 80 MHz.
Figure 14-38. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining
Pulses
Start OSHT pulse
EPWMxA in

PSCLK
Prog. pulse width
(OSHTWTH)
OSHT

EPWMxA out

Sustaining pulses

Table 14-11. Possible Pulse Width Values for
EPWMCLK = 80 MHz
OSHTWTHz
(hex)

Pulse Width
(nS)

0

100

1

200

2

300

3

400

4

500

5

600

6

700

7

800

8

900

9

1000

A

1100

B

1200

C

1300

D

1400

E

1500

F

1600

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1723

PWM Chopper (PC) Submodule

14.8.3.2

www.ti.com

Duty Cycle Control

Pulse transformer-based gate drive designs need to comprehend the magnetic properties or
characteristics of the transformer and associated circuitry. Saturation is one such consideration. To assist
the gate drive designer, the duty cycles of the second and subsequent pulses have been made
programmable. These sustaining pulses ensure the correct drive strength and polarity is maintained on the
power switch gate during the on period, and hence a programmable duty cycle allows a design to be
tuned or optimized via software control.
Figure 14-39 shows the duty cycle control that is possible by programming the CHPDUTY bits. One of
seven possible duty ratios can be selected ranging from 12.5% to 87.5%.
Figure 14-39. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of
Sustaining Pulses
PSCLK
PSCLK
period

75%
50%
25%
62.5% 37.5%
87.5%
12.5%

PSCLK Period

Duty
1/8

Duty
2/8

Duty
3/8

Duty
4/8

Duty
5/8

Duty
6/8

Duty
7/8

1724

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Trip-Zone (TZ) Submodule

www.ti.com

14.9 Trip-Zone (TZ) Submodule
Figure 14-40 shows how the trip-zone (TZ) submodule fits within the ePWM module.
Figure 14-40. Trip-Zone Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals

Time-Base
(TB)

Action
Qualifier
(AQ)

CTR = 0

Digital Compare
Signals

PIE

EPWMxSOCA
ADC
EPWMxSOCB

CTR_Dir
T1
T2

ePWMxA
ePWMxB

CTR = CMPA
Counter
Compare
(CC)

Counter Compare
Signals

EPWMxINT
Event
Trigger
and
Interrupt
(ET)

ePWMxA
ePWMxB
Dead
Band
(DB)

PWMchopper
(PC)

CTR = CMPB
CTR = CMPC

Trip
Zone
(TZ)

CTR = PRD

CTR = CMPD

CTR = 0
EPWMxTZINT

GPIO
MUX

TZ1 to TZ3

Input X-BAR

EMUSTOP

CPU

CLOCKFAIL

SYSCTRL

EQEPxERR

PIE

GPIO
MUX

EQEPx
TZ1 to TZ3

Digital Compare
Signals

Digital
Compare
(DC)

ECCDBLERR
PIEERR

28x RAM/
Flash ECC
ePWM X-BAR

Each ePWM module is connected to six TZn signals (TZ1 to TZ6). TZ1 to TZ3 are sourced from the GPIO
mux. TZ4 is sourced from an inverted EQEPxERR signal on those devices with an EQEP module. TZ5 is
connected to the system clock fail logic, and TZ6 is sourced from the EMUSTOP output from the CPU.
These signals indicate external fault or trip conditions, and the ePWM outputs can be programmed to
respond accordingly when faults occur.

14.9.1 Purpose of the Trip-Zone Submodule
The key functions of the trip-zone submodule are:
• Trip inputs TZ1 to TZ6 can be flexibly mapped to any ePWM module.
• Upon a fault condition, outputs EPWMxA and EPWMxB can be forced to one of the following:
– High
– Low
– High-impedance
– No action taken
• Support for one-shot trip (OSHT) for major short circuits or over-current conditions.
• Support for cycle-by-cycle tripping (CBC) for current limiting operation.
• Support for digital compare tripping (DC) based on state of on-chip analog comparator module outputs
and/or TZ1 to TZ3 signals.
• Each trip-zone input and digital compare (DC) submodule DCAEVT1/2 or DCBEVT1/2 force event can
be allocated to either one-shot or cycle-by-cycle operation.
• Interrupt generation is possible on any trip-zone input.
• Software-forced tripping is also supported.
• The trip-zone submodule can be fully bypassed if it is not required.

14.9.2 Operational Highlights for the Trip-Zone Submodule
The following sections describe the operational highlights and configuration options for the trip-zone
submodule.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1725

Trip-Zone (TZ) Submodule

www.ti.com

The trip-zone signals TZ1 to TZ6 (also collectively referred to as TZn) are active low input signals. When
one of these signals goes low, or when a DCAEVT1/2 or DCBEVT1/2 force happens based on the
TZDCSEL register event selection, it indicates that a trip event has occurred. Each ePWM module can be
individually configured to ignore or use each of the trip-zone signals or DC events. Which trip-zone signals
or DC events are used by a particular ePWM module is determined by the TZSEL register for that specific
ePWM module. The trip-zone signals may or may not be synchronized to the EPWM clock (EPWMCLK)
and digitally filtered within the GPIO MUX block. A minimum of 3*TBCLK low pulse width on TZn inputs is
sufficient to trigger a fault condition on the ePWM module. If the pulse width is less than this, the trip
condition may not be latched by CBC or OST latches. The asynchronous trip makes sure that if clocks are
missing for any reason, the outputs can still be tripped by a valid event present on TZn inputs . The
GPIOs or peripherals must be appropriately configured. For more information, see the device-specific
version of the System Control and Interrupts chapter.
Each TZn input can be individually configured to provide either a cycle-by-cycle or one-shot trip event for
an ePWM module. DCAEVT1 and DCBEVT1 events can be configured to directly trip an ePWM module or
provide a one-shot trip event to the module. Likewise, DCAEVT2 and DCBEVT2 events can also be
configured to directly trip an ePWM module or provide a cycle-by-cycle trip event to the module. This
configuration is determined by the TZSEL[DCAEVT1/2], TZSEL[DCBEVT1/2], TZSEL[CBCn], and
TZSEL[OSHTn] control bits (where n corresponds to the trip input) respectively.
•

•

•

1726

Cycle-by-Cycle (CBC):
When a cycle-by-cycle trip event occurs, the action specified in the TZCTL[TZA] and TZCTL[TZB] bits
is carried out immediately on the EPWMxA and/or EPWMxB outputs. Table 14-12 lists some of the
possible actions. Independent actions can be specified based on the occurrence of the event while the
counter is counting up and/or while it is counting down by appropriately configuring bits in the TZCTL2
register. Actions specified in the TZCTL2 register take effect only when the ETZE bit in TZCTL2 is set.
Additionally, when a cycle-by-cycle trip event occurs, the cycle-by-cycle trip event flag (TZFLG[CBC])
is set and a EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE
peripheral. A corresponding flag for the event that caused the CBC event is also set in register
TZCBCFLG.
If the CBC interrupt is enabled via the TZEINT register, and DCAEVT2 or DCBEVT2 are selected as
CBC trip sources via the TZSEL register, it is not necessary to also enable the DCAEVT2 or DCBEVT2
interrupts in the TZEINT register, as the DC events trigger interrupts through the CBC mechanism.
The specified condition on the inputs is automatically cleared based on the selection made with
TZCLR[CBCPULSE] if the trip event is no longer present. Therefore, in this mode, the trip event is
cleared or reset every PWM cycle. The TZFLG[CBC] and TZCBCFLG flag bits will remain set until they
are manually cleared by writing to the TZCLR[CBC] and TZCBCCLR flag bits. If the cycle-by-cycle trip
event is still present when the TZFLG[CBC] and/or TZCBCFLG register bits are cleared, then these
bits will again be immediately set..
One-Shot (OSHT):
When a one-shot trip event occurs, the action specified in the TZCTL[TZA] and TZCTL[TZB] bits is
carried out immediately on the EPWMxA and/or EPWMxB output. Table 14-12 lists some of the
possible actions. Independent actions can be specified based on the occurrence of the event while the
counter is counting up and/or while it is counting down by appropriately configuring bits in TZCTL2
register. Actions specified in TZCTL2 register take effect only when ETZE bit in TZCTL2 is set.
Additionally, when a one-shot trip event occurs, the one-shot trip event flag (TZFLG[OST]) is set and a
EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE peripheral. A
corresponding flag for the event that caused the OST event is also set in register TZOSTFLG. The
one-shot trip condition must be cleared manually by writing to the TZCLR[OST] bit. If desired,
TZOSTFLG register bit should be cleared by manually writing to the corresponding bit in the
TZOSTCLR register.
If the one-shot interrupt is enabled via the TZEINT register, and DCAEVT1 or DCBEVT1 are selected
as OSHT trip sources via the TZSEL register, it is not necessary to also enable the DCAEVT1 or
DCBEVT1 interrupts in the TZEINT register, as the DC events trigger interrupts through the OSHT
mechanism.
Digital Compare Events (DCAEVT1/2 and DCBEVT1/2):
A digital compare DCAEVT1/2 or DCBEVT1/2 event is generated based on a combination of the
DCAH/DCAL and DCBH/DCBL signals as selected by the TZDCSEL register. The signals which

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Trip-Zone (TZ) Submodule

www.ti.com

source the DCAH/DCAL and DCBH/DCBL signals are selected via the DCTRIPSEL register and can
be either trip zone input pins or analog comparator CMPSSx signals. For more information on the
digital compare submodule signals, see Section 14.11.
When a digital compare event occurs, the action specified in the TZCTL[DCAEVT1/2] and
TZCTL[DCBEVT1/2] bits is carried out immediately on the EPWMxA and/or EPWMxB output.
Table 14-12 lists the possible actions. Independent actions can be specified based on the occurrence
of the event while the counter is counting up and/or while it is counting down by appropriately
configuring bits in TZCTLDCA and TZCTLDCB register. Actions specified in TZCTLDCA and
TZCTLDCB registers take effect only when ETZE bit in TZCTL2 is set.
In addition, the relevant DC trip event flag (TZFLG[DCAEVT1/2] / TZFLG[DCBEVT1/2]) is set and a
EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE peripheral.
The specified condition on the pins is automatically cleared when the DC trip event is no longer
present. The TZFLG[DCAEVT1/2] or TZFLG[DCBEVT1/2] flag bit will remain set until it is manually
cleared by writing to the TZCLR[DCAEVT1/2] or TZCLR[DCBEVT1/2] bit. If the DC trip event is still
present when the TZFLG[DCAEVT1/2] or TZFLG[DCBEVT1/2] flag is cleared, then it will again be
immediately set.
The action taken when a trip event occurs can be configured individually for each of the ePWM output
pins by way of the TZCTL, TZCTL2, TZCTLDCA,, and TZCTLDCB register bit fields. Some of the possible
actions, shown in Table 14-12, can be taken on a trip event.
Table 14-12. Possible Actions On a Trip Event
TZCTL Register bitfield Settings

EPWMxA
and/or
EPWMxB

Comment

0,0

High-Impedance

Tripped

0,1

Force to High State

Tripped

1,0

Force to Low State

Tripped

1,1

No Change

Do Nothing.
No change is made to the output.

Example 14‑1. Trip-Zone Configurations
Scenario A:
A one-shot trip event on TZ1 pulls both EPWM1A, EPWM1B low and also forces EPWM2A and EPWM2B
high.
• Configure the ePWM1 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM1
– TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event.
– TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
• Configure the ePWM2 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM2
– TZCTL[TZA] = 1: EPWM2A will be forced high on a trip event.
– TZCTL[TZB] = 1: EPWM2B will be forced high on a trip event.
Scenario B:
A cycle-by-cycle event on TZ5 pulls both EPWM1A, EPWM1B low.
A one-shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state.
• Configure the ePWM1 registers as follows:
– TZSEL[CBC5] = 1: enables TZ5 as a one-shot event source for ePWM1
– TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event.
– TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
• Configure the ePWM2 registers as follows:
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1727

Trip-Zone (TZ) Submodule

www.ti.com

Example 14‑1. Trip-Zone Configurations (continued)
–
–
–
–

TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM2
TZSEL[OSHT6] = 1: enables TZ6 as a one-shot event source for ePWM2
TZCTL[TZA] = 0: EPWM2A will be put into a high-impedance state on a trip event.
TZCTL[TZB] = 3: EPWM2B will ignore the trip event.

14.9.3 Generating Trip Event Interrupts
Figure 14-41 and Figure 14-42 illustrate the trip-zone submodule control and interrupt logic, respectively.
DCAEVT1/2 and DCBEVT1/2 signals are described in further detail in Section 14.11.

1728

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Trip-Zone (TZ) Submodule

www.ti.com

Figure 14-41. Trip-Zone Submodule Mode Control Logic
TZCTLDCA[DCAEVT1U, DCAEVT1D, DCAEVT2U, DCAEVT2D]
TZCTL[TZA, DCAEVT1, DCAEVT2]
TZCTL2[TZAU, TZAD, ETZE]
EPWMxA (from PC submodule)
DCAEVT1.force
DCAEVT2.force
TRIPx
TZx

DCAEVT1.force
Digital
DCAEVT2.force
Compare
DCBEVT1.force
Submodule
DCBEVT2.force

EPWMxB (from PC submodule)
DCBEVT1.force
DCBEVT2.force

EPWMB
Trip
Logic

EPWMxB

01
10

CTR = Zero

EPWMxA

TZCTLDCB[DCBEVT1U, DCBEVT1D,
DCBEVT2U, DCBEVT2D]
TZCTL[TZB, DCBEVT1, DCBEVT2]
TZCTL2[TZBU, TZBD, ETZE]

TZCLR[CBCPULSE]

CTR = PRD

EPWMA
Trip
Logic

Clear
Clear

00

CBC Latch
TZFRC[CBC]

Trip

Set

TZ1
TZ2
TZ3
TZ4
TZ5
TZ6
DCAEVT2.force
DCBEVT2.force

Sync

Set

TZCLR[CBC]

Async
Trip

TZFLG[CBC]
Clear

Cycle-by-Cycle (CBC)
Trip Events

TZSEL[CBC1 to CBC6, DCAEVT2, DCBEVT2]

TZCLR[OST]

Clear
OSHT Latch

TZFRC[OSHT]

Trip

Set

TZ1
TZ2
TZ3
TZ4
TZ5
TZ6
DCAEVT1.force
DCBEVT1.force

Sync

Clear

Set

Async
Trip

TZFLG[OST]

One-Shot (OSHT)
Trip Events

TZSEL[OSHT1 to OSHT6, DCAEVT1, DCBEVT1]

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1729

Event-Trigger (ET) Submodule

www.ti.com

Figure 14-42. Trip-Zone Submodule Interrupt Logic
TZFLG[CBC]

TZEINT[CBC]
TZFLG[INT]

TZCLR[INT]

Clear
Latch
Set

Clear
Latch
Set

TZCLR[CBC]

Clear
Latch
Set

TZCLR[OST]

CBC Force
Output Event

TZFLG[OST]

TZEINT[OST]

OST Force
Output Event

TZFLG[DCAEVT1]

Generate
Interrupt
Pulse
EPWMxTZINT (PIE)
When
Input = 1

TZEINT[DCAEVT1]

Clear
Latch
Set

TZCLR[DCAEVT1]
DCAEVT1.inter

TZFLG[DCAEVT2]

TZEINT[DCAEVT2]

Clear
Latch
Set

TZCLR[DCAEVT2]
DCAEVT2.inter

TZFLG[DCBEVT1]

TZEINT[DCBEVT1]

Clear
Latch
Set

TZCLR[DCBEVT1]
DCBEVT1.inter

TZFLG[DCBEVT2]

TZEINT[DCBEVT2]

Clear
Latch
Set

TZCLR[DCBEVT2]
DCBEVT2.inter

14.10 Event-Trigger (ET) Submodule
The key functions of the event-trigger submodule are:
• Receives event inputs generated by the time-base, counter-compare, and digital-compare submodules
• Uses the time-base direction information for up/down event qualification
• Uses prescaling logic to issue interrupt requests and ADC start of conversion at:
– Every event
– Every second event
– Up to every fifteenth event
• Provides full visibility of event generation via event counters and flags
• Allows software forcing of Interrupts and ADC start of conversion
The event-trigger submodule manages the events generated by the time-base submodule, the countercompare submodule, and the digital-compare submodule to generate an interrupt to the CPU and/or a
start of conversion pulse to the ADC when a selected event occurs. Figure 14-43 illustrates where the
event-trigger submodule fits within the ePWM system.

1730

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Event-Trigger (ET) Submodule

www.ti.com

Figure 14-43. Event-Trigger Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals

Time-Base
(TB)

Action
Qualifier
(AQ)

CTR = 0

Digital Compare
Signals

PIE

EPWMxSOCA
ADC
EPWMxSOCB

CTR_Dir
T1
T2

ePWMxA
ePWMxB

CTR = CMPA
Counter
Compare
(CC)

Counter Compare
Signals

EPWMxINT
Event
Trigger
and
Interrupt
(ET)

ePWMxA
ePWMxB
Dead
Band
(DB)

PWMchopper
(PC)

CTR = CMPB
CTR = CMPC

Trip
Zone
(TZ)

CTR = PRD

CTR = CMPD

CTR = 0
EPWMxTZINT

GPIO
MUX

TZ1 to TZ3

Input X-BAR

EMUSTOP

CPU

CLOCKFAIL

SYSCTRL

EQEPxERR

PIE

GPIO
MUX

EQEPx
TZ1 to TZ3

Digital Compare
Signals

Digital
Compare
(DC)

ECCDBLERR
PIEERR

28x RAM/
Flash ECC

EPWM X-BAR

14.10.1 Operational Overview of the ePWM Type 4 Event-Trigger Submodule
The event-trigger submodule monitors various event conditions (shown as inputs on the left side of
Figure 14-44) and can be configured to prescale these events before issuing an Interrupt request or an
ADC start of conversion. The event-trigger prescaling logic can issue Interrupt requests and ADC start of
conversion at:
• Every event
• Every second event
• Up to Every fifteenth event

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1731

Event-Trigger (ET) Submodule

www.ti.com

Figure 14-44. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
clear

CTR=Zero
Event Trigger
Module Logic

CTR=PRD

/n

EPWMxINTn

PIE

ETSEL reg

CTR=Zero or PRD

count

CTRU=CMPA
ETPS reg
CTR=CMPA

CTRD=CMPA
Direction
qualifier

CTR=CMPB

CTRU=CMPB

clear

ETFLG reg
/n

CTRD=CMPB

ETCLR reg

EPWMxSOCA

count

CTRU=CMPC
CTR=CMPC

CTRD=CMPC
CTRU=CMPD

CTR=CMPD

ETFRC reg
ETINTPS reg

CTRD=CMPD
ETSOCPS reg

ADC

clear

/n

EPWMxSOCB

count

CTR_dir
DCAEVT1.soc
From Digital Compare
(DC) Submodule

ETNTINITCTL reg
DCBEVT1.soc
ETCNTINIT reg
EPWMxSYNCI

•
•
•
•
•
•
•
•
•

ETSEL - This selects which of the possible events will trigger an interrupt or start an ADC conversion.
ETPS - This programs the event prescaling options mentioned above.
ETFLG - These are flag bits indicating status of the selected and prescaled events.
ETCLR - These bits allow you to clear the flag bits in the ETFLG register via software.
ETFRC - These bits allow software forcing of an event. Useful for debugging or software intervention.
ETINTPS - This programs the interrupt event prescaling options, supporting count and period up to 15
events.
ETSOCPS - This programs the SOC event prescaling options, supporting count and period up to 15
events.
ETCNTINITCTL - These bits enable ETCNTINIT initialization via SYNC event OR via software force.
ETCNTINIT - These bits allow you to initialize INT/SOCA/SOCB counters on SYNC events (or software
force) with user programmed value.

A more detailed look at how the various register bits interact with the Interrupt and ADC start of
conversion logic are shown in Figure 14-45, Figure 14-46, and Figure 14-47.
Figure 14-45 shows the event-trigger's interrupt generation logic. The interrupt-period (ETPS[INTPRD])
bits specify the number of events required to cause an interrupt pulse to be generated. The choices
available are:
• Do not generate an interrupt.
• Generate an interrupt on every event
• Generate an interrupt on every second event
• Generate an interrupt on every third event
On ePWM type 4, in order to enable event generation capability up to 15 events the following changes
have been made. The selection made on ETPS[INTPSSEL] bit determines whether ETINTPS register,
INTCNT2 and INTPRD2 bit fields determine frequency of events (interrupt once every 0-15 events).
Which event can cause an interrupt is configured by the interrupt selection (ETSEL[INTSEL]) and
(ETSEL[INTSELCMP]) bits. The event can be one of the following:
1732

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Event-Trigger (ET) Submodule

www.ti.com

•
•
•
•
•
•
•
•
•
•
•

Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base

counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal

to
to
to
to
to
to
to
to
to
to
to

zero (TBCTR = 0x00).
period (TBCTR = TBPRD).
zero or period (TBCTR = 0x00 || TBCTR = TBPRD).
the compare A register (CMPA) when the timer is incrementing.
the compare A register (CMPA) when the timer is decrementing.
the compare B register (CMPB) when the timer is incrementing.
the compare B register (CMPB) when the timer is decrementing.
the compare C register (CMPC) when the timer is incrementing.
the compare C register (CMPC) when the timer is decrementing.
the compare D register (CMPD) when the timer is incrementing.
the compare D register (CMPD) when the timer is decrementing.

The number of events that have occurred can be read from the interrupt event counter ETPS[INTCNT] or
ETINTPS[INTCNT2] register bits based off of the selection made using ETPS[INTPSSEL]. That is, when
the specified event occurs the ETPS[INTCNT] or ETINTPS[INTCNT2] bits are incremented until they
reach the value specified by ETPS[INTPRD] or ETINTPS[INTPRD2] determined again by the selection
made in ETPS[INTPSSEL]. When ETPS[INTCNT] = ETPS[INTPRD] the counter stops counting and its
output is set. The counter is only cleared when an interrupt is sent to the PIE.
When ETPS[INTCNT] reaches ETPS[INTPRD] the following behavior will occur [The below behavior is
also applicable to ETINTPS[INTCNT2] & ETINTPS[INTPRD2] :
• If interrupts are enabled, ETSEL[INTEN] = 1 and the interrupt flag is clear, ETFLG[INT] = 0, then an
interrupt pulse is generated and the interrupt flag is set, ETFLG[INT] = 1, and the event counter is
cleared ETPS[INTCNT] = 0. The counter will begin counting events again.
• If interrupts are disabled, ETSEL[INTEN] = 0, or the interrupt flag is set, ETFLG[INT] = 1, the counter
stops counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
• If interrupts are enabled, but the interrupt flag is already set, then the counter will hold its output high
until the ENTFLG[INT] flag is cleared. This allows for one interrupt to be pending while one is serviced.
Writing a 1 to the ETFRC[INT] bit will increment the event counter INTCNT. The counter will behave as
described above when INTCNT = INTPRD. When INTPRD = 0, the counter is disabled and hence no
events will be detected and the ETFRC[INT] bit is also ignored. The same applies to ETINTPS[INTCNT2]
& ETINTPS[INTPRD2]
The above definition means that you can generate an interrupt on every event, on every second event, or
on every third event if using the INTCNT and INTPRD. You can generate an interrupt on every event up to
15 events if using the INTCNT2 and INTPRD2.
The INTCNT2 value can be initialized with the value from ETCNTINIT[INTINIT] based on the selection
made in ETCNTINITCTL[INTINITEN]. When ETCNTINITCTL[INTINITEN] is set, then it enables
initialization of INTCNT2 counter with contents of ETCNTINIT[INTINIT] on a SYNC event or software force
determined by ETCNTINITCTL[INTINITFRC] .

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1733

Event-Trigger (ET) Submodule

www.ti.com

Figure 14-45. Event-Trigger Interrupt Generator
ETFLG[INT]
ETINTPS[INTCNT2]

ETPS[INTCNT]
ETCLR[INT]

Clear
Latch
Set

1

0

ETPS[INTPSSEL]

ETSEL[INTSEL]

EPWMxINT

Generate
Interrupt
Pulse
When
Input = 1

1

0
Clear CNT
4-bit
Counter

0
ETSEL[INT]

ETCNTINIT[INTINIT]

4

ETFRC[INT]

Inc CNT

4

ETCNTINITCTL[INTINITFRC]

000
001
010
011

0
CTR = Zero
CTR = PRD

100

0
1

CTRU = CMPA
CTRU = CMPC

101

0
1

CTRD = CMPA
CTRD = CMPC

101

0
1

CTRU = CMPB
CTRU = CMPD

111

0
1

CTRD = CMPB
CTRD = CMPD

EPWMxSYNCI
0

ETCNTINITCTL[INTINITEN]

1

ETPS[INTPSSEL]

ETPS[INTPRD] ETINTPS[INTPRD2]

ETSEL[INTSELCMP]

Figure 14-46 shows the operation of the event-trigger's start-of-conversion-A (SOCA) pulse generator. The
enhancements include SOCASELCMP and SOCBSELCMP bit fields defined in the ETSEL register enable
CMPC and CMPD events respectively to cause a start of conversion. The ETPS[SOCPSSEL] bit field
determines whether SOCACNT2 and SOCAPRD2 take control or not. The ETPS[SOCACNT] counter and
ETPS[SOCAPRD] period values behave similarly to the interrupt generator except that the pulses are
continuously generated. That is, the pulse flag ETFLG[SOCA] is latched when a pulse is generated, but it
does not stop further pulse generation. The enable/disable bit ETSEL[SOCAEN] stops pulse generation,
but input events can still be counted until the period value is reached as with the interrupt generation logic.
The event that will trigger an SOCA and SOCB pulse can be configured separately in the
ETSEL[SOCASEL] and ETSEL[SOCBSEL] bits. The possible events are the same events that can be
specified for the interrupt generation logic with the addition of the DCAEVT1.soc and DCBEVT1.soc event
signals from the digital compare (DC) submodule. The SOCACNT2 initialization scheme is very similar to
the interrupt generator with respective enable, value initialize and SYNC or software force options.

1734

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Event-Trigger (ET) Submodule

www.ti.com

Figure 14-46. Event-Trigger SOCA Pulse Generator
ETFLG[SOCA]
ETPS[SOCACNT] ETSOCPS[SOCACNT2]
ETCLR[SOCA]

Clear
Latch
Set

1

0

ETPS[SOCPSSEL]

ETSEL[SOCASEL]

EPWMxSOCA

Generate
SOC
Pulse
When
Input = 1

ClrCNT
4-bit
Counter
ETSEL[SOCA]

ETCNTINIT[SOCAINIT]

4

ETFRC[SOCA]

Inc CNT

4

ETCNTINITCTL[SOCAINITFRC]

000
001
010
011

DCAEVT1.soc
CTR = Zero
CTR = PRD

100

0
1

CTRU = CMPA
CTRU = CMPC

101

0
1

CTRD = CMPA
CTRD = CMPC

110

0
1

CTRU = CMPB
CTRU = CMPD

111

0
1

CTRD = CMPB
CTRD = CMPD

EPWMxSYNCI
0

ETCNTINITCTL[SOCAINITEN]

1

ETPS[SOCPSSEL]

ETPS[SOCAPRD] ETINTPS[SOCAPRD2]

A

ETSEL[SOCASELCMP]

The DCAEVT1.soc signals are signals generated by the Digital compare (DC) submodule in Section 14.11.

Figure 14-47 shows the operation of the event-trigger's start-of-conversion-B (SOCB) pulse generator. The
event-trigger's SOCB pulse generator operates the same way as the SOCA.
Figure 14-47. Event-Trigger SOCB Pulse Generator
ETFLG[SOCB]
ETPS[SOCBCNT] ETSOCPS[SOCBCNT2]
ETCLR[SOCB]

Clear
Latch
Set

1

0

ETPS[SOCPSSEL]

ETSEL[SOCBSEL]

EPWMxSOCB

Generate
SOC
Pulse
When
Input = 1

ClrCNT
4-bit
Counter
ETSEL[SOCB]

ETCNTINIT[SOCBINIT]

4

ETFRC[SOCB]

Inc CNT

4

ETCNTINITCTL[SOCBINITFRC]

000
001
010
011

DCBEVT1.soc
CTR = Zero
CTR = PRD

100

0
1

CTRU = CMPA
CTRU = CMPC

101

0
1

CTRD = CMPA
CTRD = CMPC

110

0
1

CTRU = CMPB
CTRU = CMPD

111

0
1

CTRD = CMPB
CTRD = CMPD

EPWMxSYNCI
0

ETCNTINITCTL[SOCBINITEN]

1

ETPS[SOCPSSEL]

ETPS[SOCBPRD] ETINTPS[SOCBPRD2]

A

ETSEL[SOCBSELCMP]

The DCBEVT1.soc signals are signals generated by the Digital compare (DC) submodule in Section 14.11.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1735

Digital Compare (DC) Submodule

www.ti.com

14.11 Digital Compare (DC) Submodule
Figure 14-48 illustrates where the digital compare (DC) submodule signals interface to other submodules
in the ePWM system.
Figure 14-48. Digital-Compare Submodule High-Level Block Diagram
Digital Compare Submodule

Input X-BAR

TRIPIN3 and TZ3
TRIPIN6
TRIPIN4
TRIPIN5
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12

EPWM X-BAR

DCAH
DCAL

DCAEVT1.sync
DCBEVT1.sync

DCAEVT1
Event A
Qual

DCAEVT2

Blanking
Window
Counter
Capture
DCBH
DCBL

DCBEVT1
Event B
Qual

DCBEVT2

Time-Base
submodule

DCAEVT1.force
DCAEVT2.force

Event
Filtering

DCTRIPSEL

GPIO
MUX

TRIPIN1 and TZ1
TRIPIN2 and TZ2

DCEVTFILT

Event
Triggering

DCBEVT1.force
DCBEVT2.force
DCAEVT1.inter
DCAEVT2.inter

Trip-Zone
submodule

DCBEVT1.inter
DCBEVT2.inter
DCAEVT1.soc
DCBEVT1.soc

TRIPIN14 [ECCDBLERR]
TRIPIN15 [PIEERR]

Event-Trigger
submodule

TRIPIN1 and TZ1
TRIPIN2 and TZ2
TRIPIN3 and TZ3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12

Trip Combination Input

TRIPIN14 [ECCDBLERR]
TRIPIN15 [PIEERR]

[DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL]

The eCAP input signals are sourced from the Input X-BAR signals as shown in Figure 14-49.

1736

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Digital Compare (DC) Submodule

www.ti.com

Figure 14-49. ePWM Trip Input Connectivity
INPUT14
INPUT13

Input X-Bar

INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6

GPIOx

Async/
Sync/
Sync+Filter

PIE(s),
CLA(s)

XINT5
XINT4

INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12

GPIO0

eCAP6
eCAP5

PIE(s),
CLA(s)

XINT1

eCAP4

XINT2

eCAP3

XINT3

eCAP2
eCAP1

ADC

EXTSYNCIN1

Wrapper(s)

TZ1
TZ2
TZ3
TRIP1
TRIP2
TRIP3
TRIP6

ePWM
X-Bar

CPU1.PIEVECTERROR
CPU2.PIEVECTERROR
CPU1.EMUSTOP
CPU2.EMUSTOP

ePWM and eCAP
Sync Chain

EXTSYNCIN2

ECCERR
EQEPERR
CLKFAIL

TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12

EPWMINT
TZINT

PIE(s),
CLA(s)
EPWMx.EPWMCLK
EPWMENCLK
TBCLKSYNC

ADCSOCAO Select Ckt
ADCSOCBO Select Ckt

All
ePWM
Modules

TRIP14
TRIP15
TZ4
TZ5
TZ6

SOCA

ADC
Wrapper(s)

SOCB

PWM11.CMPC
PWM11.CMPD

EPWMn.EMUSTOP

Filter-Reset

SD1
FLT1
FLT1
FLT1
FLT1

Filter-Reset
Filter-Reset

FLT1
FLT1
FLT1
FLT1

PWM12.CMPC
PWM12.CMPD Filter-Reset
CPUSEL0.EPWMx

SD2

Copyright © 2017, Texas Instruments Incorporated

On this device, any of the GPIO pins can be flexibly mapped to be the trip-zone input and/or trip inputs to
the trip-zone submodule and digital compare submodule. The Input X-BAR Input Select (INPUTxSELECT)
register defines which GPIO pins gets assigned to be the trip-zone inputs / trip inputs.
The digital compare (DC) submodule compares signals external to the ePWM module (for instance,
CMPSSx signals from the analog comparators) to directly generate PWM events/actions which then feed
to the event-trigger, trip-zone, and time-base submodules. Additionally, blanking window functionality is
supported to filter noise or unwanted pulses from the DC event signals.
NOTE:

The user is responsible for driving correct state on the selected pin before enabling clock
and configuring the trip input for the respective ePWM peripheral to avoid spurious latch of
TRIP signal.

14.11.1 Purpose of the Digital Compare Submodule
The key functions of the digital compare submodule are:
• Analog comparator (COMP) module outputs fed though the Input X-BAR logic externally using the
GPIO peripheral, internal PIE, ECC error signals, TZ1, TZ2, and TZ3 inputs generate Digital Compare
A High/Low (DCAH, DCAL) and Digital Compare B High/Low (DCBH, DCBL) signals.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1737

Digital Compare (DC) Submodule

•

•

www.ti.com

DCAH/L and DCBH/L signals trigger events which can then either be filtered or fed directly to the tripzone, event-trigger, and time-base submodules to:
– generate a trip zone interrupt
– generate an ADC start of conversion
– force an event
– generate a synchronization event for synchronizing the ePWM module TBCTR.
Event filtering (blanking window logic) can optionally blank the input signal to remove noise.

14.11.2 Enhanced Trip Action
In order to allow multiple comparators at a time to affect DCA/BEVTx events and trip actions, there is a
OR logic to bring together ALL trip inputs (up to 15) from sources external to the ePWM module and feed
into DCAH, DCAL, DCBH, and DCBL as “combinational input” using the DCTRIPSEL register. This is
configured by writing appropriate value [Trip Combination input ] to the
DCAHCOMPSEL,DCALCOMPSEL, DCBHCOMPSEL, DCBLCOMPSEL bit fields in the DCTRIPSEL
register.
The user has an discrete choice for which trip input to put through the combinational logic for Digital
Compare A High/Low (DCAH, DCAL) and Digital Compare B High/Low (DCBH, DCBL) signals generation.
This is achieved using the selection from DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL and
DCBLTRIPSEL register. The appropriate bit when set indicates that Trip input is chosen for “combinational
input” by the DCTRIPSEL register.
Apart from these options user can also make the external trip inputs which feed into the OR gate
individually selectable and not go through the “combinational input” by using the DCTRIPSEL register.

14.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
When using the CMPSS to trip the ePWM on a cycle-by-cycle basis, steps should be taken to prevent an
asserted comparator trip state in one PWM cycle from extending into the following cycle. The CMPSS can
be used to signal a trip condition to the downstream ePWM modules. For applications like peak current
mode control, only one trip event per PWM cycle is expected. Under certain conditions, it is possible for a
sustained or late trip event (arriving near the end of a PWM cycle) to carry over into the next PWM cycle if
precautions are not taken. If either the CMPSS Digital Filter or the ePWM Digital Compare (DC)
submodule is configured to qualify the comparator trip signal, “N” number of clock cycles of qualification
will be introduced before the EPWM trip logic can respond to logic changes of the trip signal. Once an
ePWM trip condition is qualified, the trip condition will remain active for N clock cycles after the
comparator trip signal has de-asserted. If a qualified comparator trip signal remains asserted within N
clock cycles prior to the end of a PWM cycle, the trip condition will not be cleared until after the following
PWM cycle has started. Thus, the new PWM cycle will detect a trip condition as soon as it begins.
To avoid this undesired trip condition, the user application should take steps to ensure that the qualified
trip signal seen by the ePWM trip logic is deasserted prior to the end of each PWM cycle. This can be
accomplished through various methods:
• Design the system such that a comparator trip will not be asserted within N clock cycles prior to the
end of the PWM cycle.
• Activate blanking of the comparator trip signal via the EPWM event filter at least two clock cycles prior
to the PWMSYNC signal and continue blanking for at least N clock cycles into the next PWM cycle.
• If the CMPSS COMPxLATCH path is used, clear the COMPxLATCH at least N clock cycles prior to the
end of the PWM cycle. The latch can be cleared by software (via COMPSTSCLR) or by generating an
early PWMSYNC signal. The ePWM modules on this device include the ability to generate PWMSYNC
upon a CMPC or CMPD match (via HRPCTL) for arbitrary PWMSYNC placement within the PWM
cycle.

14.11.4 Operation Highlights of the Digital Compare Submodule
The following sections describe the operational highlights and configuration options for the digital compare
submodule.

1738

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Digital Compare (DC) Submodule

www.ti.com

14.11.4.1 Digital Compare Events
As illustrated in Section 14.11.4.2 earlier in this section, trip zone inputs (TZ1, TZ2, and TZ3) and
CMPSSx signals from the analog comparator (COMP) module can be selected via the DCTRIPSEL bits to
generate the Digital Compare A High and Low (DCAH/L) and Digital Compare B High and Low (DCBH/L)
signals. Then, the configuration of the TZDCSEL register qualifies the actions on the selected DCAH/L
and DCBH/L signals, which generate the DCAEVT1/2 and DCBEVT1/2 events (Event Qualification A and
B).
NOTE: The TZn signals, when used as a DCEVT tripping functions, are treated as a normal input
signal and can be defined to be active high or active low inputs. ePWM outputs are
asynchronously tripped when either the TZn, DCAEVTx.force, or DCBEVTx.force signals are
active. For the condition to remain latched, a minimum of 3*TBCLK sync pulse width is
required. If pulse width is < 3*TBCLK sync pulse width, the trip condition may or may not get
latched by CBC or OST latches.

The DCAEVT1/2 and DCBEVT1/2 events can then be filtered to provide a filtered version of the event
signals (DCEVTFILT) or the filtering can be bypassed. Filtering is discussed further in Section 14.11.4.2.
Either the DCAEVT1/2 and DCBEVT1/2 event signals or the filtered DCEVTFILT event signals can
generate a force to the trip zone module, a TZ interrupt, an ADC SOC, or a PWM sync signal.
• force signal:
DCAEVT1/2.force signals force trip zone conditions which either directly influence the output on the
EPWMxA pin (via TZCTL, TZCTLDCA, TZCTLDCB register configurations) or, if the DCAEVT1/2
signals are selected as one-shot or cycle-by-cycle trip sources (via the TZSEL register), the
DCAEVT1/2.force signals can effect the trip action via the TZCTL or TZCTL2 register configurations.
The DCBEVT1/2.force signals behaves similarly, but affect the EPWMxB output pin instead of the
EPWMxA output pin.
The priority of conflicting actions on the TZCTL, TZCTL2, TZCTLDCA and TZCTLDCB registers is as
follows (highest priority overrides lower priority):
Output EPWMxA:
– TZA (highest) -> DCAEVT1 -> DCAEVT2 (lowest)
– TZAU (highest) -> DCAEVT1U -> DCAEVT2U (lowest)
– TZAD (highest) -> DCAEVT1D -> DCAEVT2D (lowest)
Output EPWMxB:
– TZB (highest) -> DCBEVT1 -> DCBEVT2 (lowest)
– TZBU (highest) -> DCBEVT1U -> DCBEVT2U (lowest)
– TZBD (highest) -> DCBEVT1D -> DCBEVT2D (lowest)
• interrupt signal:
DCAEVT1/2.interrupt signals generate trip zone interrupts to the PIE. To enable the interrupt, the user
must set the DCAEVT1, DCAEVT2, DCBEVT1, or DCBEVT2 bits in the TZEINT register. Once one of
these events occurs, an EPWMxTZINT interrupt is triggered, and the corresponding bit in the TZCLR
register must be set in order to clear the interrupt.
• soc signal:
The DCAEVT1.soc signal interfaces with the event-trigger submodule and can be selected as an event
which generates an ADC start-of-conversion-A (SOCA) pulse via the ETSEL[SOCASEL] bit. Likewise,
the DCBEVT1.soc signal can be selected as an event which generates an ADC start-of-conversion-B
(SOCB) pulse via the ETSEL[SOCBSEL] bit.
• sync signal:
The DCAEVT1.sync and DCBEVT1.sync events are ORed with the EPWMxSYNCI input signal and the
TBCTL[SWFSYNC] signal to generate a synchronization pulse to the time-base counter.
The diagrams below show how the DCAEVT1, DCAEVT2 or DCEVTFLT signals are processed to
generate the digital compare A event force, interrupt, soc and sync signals.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1739

Digital Compare (DC) Submodule

www.ti.com

Figure 14-50. DCAEVT1 Event Triggering
DCACTL[EVT1SRCSEL]
DCACTL[EVT1FRCSYNCSEL]
DCEVTFILT

1

DCAEVT1

0

Async
Sync

1
DCAEVT1.force
0

TBCLK

TZEINT[DCAEVT1]
Set
Latch
Clear

DCAEVT1.inter
TZFLG[DCAEVT1]

TZCLR[DCAEVT1]

DCAEVT1.soc
DCACTL[EVT1SOCE]

TZFRC[DCAEVT1]

DCAEVT1.sync
DCACTL[EVT1SYNCE]

Figure 14-51. DCAEVT2 Event Triggering
DCACTL[EVT2SRCSEL]
DCACTL[EVT2FRCSYNCSEL]
DCEVTFILT

1

Async

DCAEVT2

0

Sync

1
DCAEVT2.force

0

TBCLK

TZEINT[DCAEVT2]
Set
Latch
Clear

TZFRC[DCAEVT2]

TZCLR[DCAEVT2]

1740

Enhanced Pulse Width Modulator (ePWM)

DCAEVT2.inter
TZFLG[DCAEVT2]

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Digital Compare (DC) Submodule

www.ti.com

Figure 14-52 and Figure 14-53 show how the DCBEVT1, DCBEVT2 or DCEVTFLT signals are processed
to generate the digital compare B event force, interrupt, soc and sync signals.
Figure 14-52. DCBEVT1 Event Triggering
DCBCTL[EVT1SRCSEL]

DCEVTFILT

1

DCBEVT1

0

DCBCTL[EVT1FRCSYNCSEL]

async
Sync

1
DCBEVT1.force

0

TBCLK
TZEINT[DCBEVT1]
set
Latch
clear
TZCLR[DCBEVT1]

DCBEVT1.inter
TZFLG[DCBEVT1]

DCBEVT1.soc
DCBCTL[EVT1SOCE]

DCBEVT1.sync
TZFRC[DCBEVT1]
DCBCTL[EVT1SYNCE]

Figure 14-53. DCBEVT2 Event Triggering
DCBCTL[EVT2SRCSEL]

DCEVTFILT

1

DCBEVT2

0

DCBCTL[EVT2FRCSYNCSEL]

1

async
Sync

DCBEVT2.force

0

TBCLK
TZEINT[DCBEVT2]
set
Latch
clear
TZCLR[DCBEVT2]

DCBEVT2.inter
TZFLG[DCBEVT2]

TZFRC[DCBEVT2]

14.11.4.2 Event Filtering
The DCAEVT1/2 and DCBEVT1/2 events can be filtered via event filtering logic to remove noise by
optionally blanking events for a certain period of time. This is useful for cases where the analog
comparator outputs may be selected to trigger DCAEVT1/2 and DCBEVT1/2 events, and the blanking
logic is used to filter out potential noise on the signal prior to tripping the PWM outputs or generating an
interrupt or ADC start-of-conversion. The event filtering can also capture the TBCTR value of the trip
event. Figure 14-54 shows the details of the event filtering logic.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1741

Digital Compare (DC) Submodule

www.ti.com

Figure 14-54. Event Filtering
DCCAP[15:0] Reg
Blank
Control
Logic

CTR=PRD
CTR=Zero
TBCLK

DCFCTL[BLANKE, PULSESEL]
DCFOFFSET[OFFSET]
TBCTR(16)

DCFWINDOW[WINDOW]

CTR = PRD
CTR = 0
TBCLK

BLANKWDW
DCFCTL[INVERT]

Capture
Control
Logic

DCCAPCTL[CAPE, SHDWMODE]
DCFCTL[PULSESEL]
Sync
1

0
TBCLK

DCAEVT1

00

DCAEVT2

01

DCBEVT1

10

DCBEVT2

11

async

DCEVTFILT

DCFCTL[SRCSEL]

If the blanking logic is enabled, one of the digital compare events – DCAEVT1, DCAEVT2, DCBEVT1,
DCBEVT2 – is selected for filtering. The blanking window, which filters out all event occurrences on the
signal while it is active, will be aligned to either a CTR = PRD pulse or a CTR = 0 pulse or both CTR =
PRD and CTR = 0 (configured by the DCFCTL[PULSESEL] bits). An offset value in TBCLK counts is
programmed into the DCFOFFSET register, which determines at what point after the CTR = PRD or CTR
= 0 pulse the blanking window starts. The duration of the blanking window, in number of TBCLK counts
after the offset counter expires, is written to the DCFWINDOW register by the application. During the
blanking window, all events are ignored. Before and after the blanking window ends, events can generate
soc, sync, interrupt, and force signals as before.
The diagram below illustrates several timing conditions for the offset and blanking window within an
ePWM period. Notice that if the blanking window crosses the CTR = 0 or CTR = PRD boundary, the next
window still starts at the same offset value after the CTR = 0 or CTR = PRD pulse.
Figure 14-55. Blanking Window Timing Diagram
Period
TBCLK

CTR = PRD
or CTR = 0

Offset(n)
BLANKWDW

Offset(n+1)
Window(n)

Window(n+1)

Offset(n)
BLANKWDW

Offset(n+1)
Window(n)

Offset(n)

1742

Enhanced Pulse Width Modulator (ePWM)

Window(n+1)

Offset(n+1)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Digital Compare (DC) Submodule

www.ti.com

14.11.4.3 Valley Switching
Event filtering depicts the valley switching function along with the event filtering logic described in
Section 14.11.4.2. This function can be used to achieve programmable valley switching without any
additional external circuitry. This module provides an on-chip hardware mechanism that can:
• Capture the oscillation period
• Accurately delay the PWM switching instant
• Allow a programmable number of edges before the delay takes effect
• Provide multiple choices of triggers and events
• Allow easy adaptability for optimum performance under changing system/operating conditions
The DCxEVTy signal needs further processing to support valley switching. Here is a brief description of
how valley switching function is enabled:
1. Select one of the DCxEVTy events as input to the valley switching block (DCFCTL[SRCSEL]) with an
option to add the blanking window (Blank Control Logic). This is where the comparator output (or
external input) above is selected as an input to the valley switching block.
2. Configure the edge filter to capture ‘n’ rising, falling or both edges through the edge selection logic
(DCFCTL[EDGEMODE, EDGECOUNT]).
3. Select the correct event to reset and restart the edge filter (VCAPCTL[TRIGSEL]). Edge capturing
event is triggered or armed by this selected edge.
4. Enable valley capture logic (VCAPCTL[VCAPE]).
5. Select the start edge that will indicate the start of capture for oscillation period measurement
(VCNTCFG[STARTEDGE]). This is where the 16-bit counter starts counting.
6. Select the stop edge (VCNTCFG[STOPEDGE]) that will indicate the edge at which the 16-bit counter
stops counting. The captured counter value (CNTVAL) provides oscillation period information.
• The STOPEDGE value must always be greater than STARTEDGE value.
7. Configure and apply the captured delay (CNTVAL) to the edge filtered DCxEVTy signal. The CNTVAL
value may be applied as is or applied in conjunction with a software programmed value (useful for
offset adjustment) (SWVDELVAL) or only a fraction of the delay may be applied with or without
SWVDELVAL. This is useful to correctly apply a delay corresponding to the valley point.
(VCAPCTL[VDELAYDIV])
8. Configure VCAPCTL[EDGEFILTDLYSEL] to apply hardware delay based on the captured value above.
Once the counter is stopped, counter value is copied into CNTVAL register and counter is reset to zero.
No further captures are done until the logic is triggered again by occurrence of event selected by
VCAPCTL[TRIGSEL]. In this implementation, the software trigger is used as the source for
VCAPCTL[TRIGSEL]. Upon occurrence of the trigger event, irrespective of the current status of the
counter, the counter is reset and starts counting from zero upon occurrence of the STARTEDGE.
Similarly, upon occurrence of the trigger event, the edge filter is reset and starts counting from zero upon
occurrence of the STARTEDGE.
Output from the valley switching block (DCEVTFILT) is then used to synchronize the PWM time-base. The
process is shown in Figure 14-56.
NOTE: A specific application example showcasing the usage of valley switching hardware and
software is available on the controlSuite.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1743

EPWM X-BAR

www.ti.com

Figure 14-56. Valley Switching
DCCAP[15:0] Reg

TBCNT(16)
PRD_eq
CNT_zero
TBCLK

Blank
Control
Logic

DCFCTL[BLANKE, PULSESEL]
DCFOFFSET[OFFSET]

PRD_eq
CNT_zero
TBCLK

DCFWINDOW[WINDOW]

Capture
Control
Logic

DCCAPCTL[CAPE, SHDWMODE]
BLANKWDW

DCFCTL[PULSESEL]

DCFCTL[INVERT]

0

DCAEVT1

00

DCAEVT2

01

DCBEVT1

10

DCBEVT2

11

1

Sync

0

TBCLK

1

0

async

DCEVTFILT

EDGE FILTER
Reset
Edge
Selection
Logic

1

0

Edge Fiter

1

Delay

DFCTL[EDGEFILTSEL]

DCFCTL[SRCSEL]
VCAPCTL[EDGEFILTDLYSEL]

1

DCFCTL[EDGEMODE,
EDGECOUNT]
HWVDELVAL

VCAPCTL[TRIGSEL]
Software

VCAPCTL[VCAPE]

000

CNT_zero

001

PRD_eq

010

PRD_eq or
CNT_zero
DCAEVT1
DCAEVT2
DCBEVT1
DCBEVT2

SWVDELVAL

011
100

Edge Capture Trigger

101

Hardware
calculated
Delay

0

Edge
Capture
Logic

Edge Procesisng/
Delay generation

Start

CNTVAL

Stop

16 bit Counter

VCAPCTL[VDELAYDIV]

Reset

110
111

TBCLK

14.12 EPWM X-BAR
Figure 14-57 shows the connections to the EPWM X-Bar. This module enables selection of various trigger
sources into any of the eight dedicated ETWPM trips inputs, namely the TRIP4, TRIP5, TRIP7, TRIP8,
TRIP9, TRIP10, TRIP11 and TRIP12. See the Crossbar (X-BAR) chapter for details on the X-BAR
architecture and configuration.

1744

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

Figure 14-57. EPWM X-BAR
CTRIPOUTH
CTRIPOUTL

(Output X-BAR only)

CMPSSx
CTRIPH
CTRIPL

ePWM and eCAP
Sync Chain

EXTSYNCOUT

ADCSOCAO
Select Ckt

ADCSOCAO

ADCSOCBO
Select Ckt

ADCSOCBO

eCAPx

ECAPxOUT

ADCx

Output
X-BAR

EVT1
EVT2
EVT3
EVT4
INPUT1
INPUT2
INPUT3

Input X-Bar

(ePWM X-BAR only)

OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8

GPIO
Mux

TRIP4
TRIP5

ePWM
X-BAR

INPUT4
INPUT5
INPUT6

TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12

All
ePWM
Modules

OTHER DESTINATIONS
(see Input X-BAR)
FLT1.COMPH

X-BAR Flags
(shared)

FLT1.COMPL

SDFMx
FLT4.COMPH
FLT4.COMPL

14.13 Applications to Power Topologies
An ePWM module has all the local resources necessary to operate completely as a standalone module or
to operate in synchronization with other identical ePWM modules.

14.13.1 Overview of Multiple Modules
Previously in this chapter, all discussions have described the operation of a single module. To facilitate the
understanding of multiple modules working together in a system, the ePWM module described in
reference is represented by the more simplified block diagram shown in Figure 14-58. This simplified
ePWM block shows only the key resources needed to explain how a multiswitch power topology is
controlled with multiple ePWM modules working together.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1745

Applications to Power Topologies

www.ti.com

Figure 14-58. Simplified ePWM Module

SyncIn
Phase reg

EN

Φ=0°

EPWMxA
EPWMxB

CTR = 0
CTR=CMPB
X
SyncOut

14.13.2 Key Configuration Capabilities
The key configuration choices available to each module are as follows:
• Options for SyncIn
– Load own counter with phase register on an incoming sync strobe—enable (EN) switch closed
– Do nothing or ignore incoming sync strobe—enable switch open
– Sync flow-through - SyncOut connected to SyncIn
– Master mode, provides a sync at PWM boundaries—SyncOut connected to CTR = PRD
– Master mode, provides a sync at any programmable point in time—SyncOut connected to CTR =
CMPB
– Module is in standalone mode and provides No sync to other modules—SyncOut connected to X
(disabled)
• Options for SyncOut
– Sync flow-through - SyncOut connected to SyncIn
– Master mode, provides a sync at PWM boundaries—SyncOut connected to CTR = PRD
– Master mode, provides a sync at any programmable point in time—SyncOut connected to CTR =
CMPB
– Module is in standalone mode and provides No sync to other modules—SyncOut connected to X
(disabled)
For each choice of SyncOut, a module may also choose to load its own counter with a new phase value
on a SyncIn strobe input or choose to ignore it (that is, via the enable switch). Although various
combinations are possible, the two most common—master module and slave module modes—are shown
in Figure 14-59.

1746

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

Figure 14-59. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
Ext SyncIn
(optional)
Master

Slave
Phase reg

SyncIn
Phase reg EN
Φ=0°

EN
Φ=0°

EPWM1A
EPWM1B

CTR=0
CTR=CMPB
X
1

SyncIn
EPWM2A

2

SyncOut

EPWM2B

CTR=0
CTR=CMPB
X
SyncOut

14.13.3 Controlling Multiple Buck Converters With Independent Frequencies
One of the simplest power converter topologies is the buck. A single ePWM module configured as a
master can control two buck stages with the same PWM frequency. If independent frequency control is
required for each buck converter, then one ePWM module must be allocated for each converter stage.
Figure 14-60 shows four buck stages, each running at independent frequencies. In this case, all four
ePWM modules are configured as Masters and no synchronization is used. Figure 14-61 shows the
waveforms generated by the setup shown in Figure 14-60; note that only three waveforms are shown,
although there are four stages.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1747

Applications to Power Topologies

www.ti.com

Figure 14-60. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4
Ext SyncIn
(optional)

Master1
Phase reg
Φ=X

SyncIn
En

Vin1
EPWM1B

CTR=zero
CTR=CMPB
X
1

Buck #1
EPWM1A

SyncOut

Master2
Phase reg
Φ=X

SyncIn

Vin2

Vout2

En
EPWM2A

2

Buck #2

EPWM2B

CTR=zero
CTR=CMPB
X

EPWM2A
SyncOut

Master3
Phase reg
Φ=X

SyncIn

Vin3

En

Vout3

EPWM3A

3

Buck #3

EPWM3B

CTR=zero
CTR=CMPB
X

EPWM3A
SyncOut

Master4
Phase reg
Φ=X

Vin4

SyncIn

Vout4

En
EPWM4A
Buck #4
EPWM4B

CTR=zero
CTR=CMPB
X
3

Vout1

EPWM1A

EPWM4A

SyncOut

NOTE: φ = X indicates value in phase register is a "don't care"

1748

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

Figure 14-61. Buck Waveforms for Figure 14-60 (Note: Only three bucks shown here)
P
I

P
I

P
I

P

700

950

CA

CB
A

1200

P

CA

P

EPWM1A

Pulse center

P

700

1150

CA

CB
A

1400

P

CA

EPWM2A

650
500

CA

P

800

CA

P

CA

P

CB
A
EPWM3A
P
I

Indicates this event triggers an interrupt

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

CB
A

Indicates this event triggers an ADC start
of conversion

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1749

Applications to Power Topologies

www.ti.com

14.13.4 Controlling Multiple Buck Converters With Same Frequencies
If synchronization is a requirement, ePWM module 2 can be configured as a slave and can operate at
integer multiple (N) frequencies of module 1. The sync signal from master to slave ensures these modules
remain locked. Figure 14-62 shows such a configuration; Figure 14-63 shows the waveforms generated by
the configuration.
Figure 14-62. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1)
Vin1
Buck #1

Ext SyncIn
(optional)
Master
Phase reg
Φ=0°

Vout1

EPWM1A

SyncIn
En
EPWM1A

Vin2

Vout2

EPWM1B

CTR=zero
CTR=CMPB

Buck #2
EPWM1B

X
SyncOut

Vin3
Buck #3

Slave
Phase reg
Φ=X

Vout3

EPWM2A

SyncIn
En
EPWM2A
EPWM2B

CTR=zero
CTR=CMPB
X

Vin4

Vout4
Buck #4

SyncOut

EPWM2B

NOTE: φ = X indicates value in phase register is a "don't care"

1750

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

Figure 14-63. Buck Waveforms for Figure 14-62 (Note: FPWM2 = FPWM1))
600

Z
I

400

Z
I

Z
I

400

200

200

CA

P
(A)
A

CA

CA

P
(A)
A

CA

EPWM1A
CB

CB

CB

CB

EPWM1B

500

500

300

300

CA

CA

CA

CA

EPWM2A
CB

CB

CB

CB

EPWM2B

A

Starts ADC conversion.

14.13.5 Controlling Multiple Half H-Bridge (HHB) Converters
Topologies that require control of multiple switching elements can also be addressed with these same
ePWM modules. It is possible to control a Half-H bridge stage with a single ePWM module. This control
can be extended to multiple stages. Figure 14-64 shows control of two synchronized Half-H bridge stages
where stage 2 can operate at integer multiple (N) frequencies of stage 1. Figure 14-65 shows the
waveforms generated by the configuration shown in Figure 14-64.
Module 2 (slave) is configured for Sync flow-through; if required, this configuration allows for a third Half-H
bridge to be controlled by PWM module 3 and also, most importantly, to remain in synchronization with
master module 1.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1751

Applications to Power Topologies

www.ti.com

Figure 14-64. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1)
VDC_bus

Ext SyncIn
(optional)
Master
Phase reg
En
Φ=0°

SyncIn

EPWM1A
EPWM1A
EPWM1B

CTR=zero
CTR=CMPB
X

EPWM1B

SyncOut
Slave
Phase reg
En
Φ=0°

Vout1

SyncIn
VDC_bus

Vout2

EPWM2A
EPWM2B

CTR=zero
CTR=CMPB
X

EPWM2A
SyncOut

EPWM2B

1752

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

Figure 14-65. Half-H Bridge Waveforms for Figure 14-64 (Note: Here FPWM2 = FPWM1 )
Z
I

Z
I

600
400

400

200

200

Z

CB
A

Z
I

Z

CA

CB
A

CA

EPWM1A
CA

CB
A

Z

CA

CB
A

Z

CA

CB
A

Z

EPWM1B
Pulse Center
500

500

250

Z

CB
A

250

CA

Z

CB
A

CA

EPWM2A

CA

CB
A

Z

EPWM2B
Pulse Center

14.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
The idea of multiple modules controlling a single power stage can be extended to the 3-phase Inverter
case. In such a case, six switching elements can be controlled using three PWM modules, one for each
leg of the inverter. Each leg must switch at the same frequency and all legs must be synchronized. A
master + two slaves configuration can easily address this requirement.
As in the cases shown in the previous sections, we have a choice of running each inverter at a different
frequency (module 1 and module 4 are masters or both inverters can be synchronized by using one
master (module 1) and five slaves. In this case, the frequency of modules 4, 5, and 6 (all equal) can be
integer multiples of the frequency for modules 1, 2, 3 (also all equal).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1753

Applications to Power Topologies

www.ti.com

Figure 14-66. 3-Phase Inverter Waveforms (Only One Inverter Shown)
Z
I

Z
I

800
500

500

CA

CA

P
A

EPWM1A

CA

CA

P
A
RED

RED

EPWM1B

FED

FED

Φ2=0

600

600

CA

CA

CA

CA

EPWM2A
RED

EPWM2B
FED

700

Φ3=0

CA

EPWM3A

CA

CA

CA

RED

EPWM3B

1754

700

FED

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

14.13.7 Practical Applications Using Phase Control Between PWM Modules
So far, none of the examples have made use of the phase register (TBPHS). It has either been set to zero
or its value has been a don't care. However, by programming appropriate values into TBPHS, multiple
PWM modules can address another class of power topologies that rely on phase relationship between
legs (or stages) for correct operation. As described in the TB module section, a PWM module can be
configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCTR register. To
illustrate this concept, Figure 14-67 shows a master and slave module with a phase relationship of 120°
(that is, the slave leads the master).
Figure 14-67. Configuring Two PWM Modules for Phase Control
Ext SyncIn
(optional)
Master
Phase reg

SyncIn
En

Φ=0°

EPWM1A
EPWM1B

CTR=zero
CTR=CMPB
X
1

SyncOut

Slave
Phase reg

SyncIn
En

Φ=120°

EPWM2A
EPWM2B

CTR=zero
CTR=CMPB
X
2

SyncOut

Figure 14-68 shows the associated timing waveforms for this configuration. Here, TBPRD = 600 for both
master and slave. For the slave, TBPHS = 200 (that is, 200/600 X 360° = 120°). Whenever the master
generates a SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCTR
register so the slave time-base is always leading the master's time-base by 120°.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1755

Applications to Power Topologies

www.ti.com

Figure 14-68. Timing Waveforms Associated With Phase Control Between Two Modules
FFFFh

TBCTR[0-15]
Master Module
600

600

TBPRD

0000
CTR = PRD
(SycnOut)
FFFFh

time
TBCTR[0-15]
Φ2

Phase = 120°

Slave Module
TBPRD

600

600
200

200

TBPHS
0000
SyncIn

time

14.13.8 Controlling a 3-Phase Interleaved DC/DC Converter
A popular power topology that makes use of phase-offset between modules is shown in Figure 14-69. This
system uses three PWM modules, with module 1 configured as the master. To work, the phase
relationship between adjacent modules must be F = 120°. This is achieved by setting the slave TBPHS
registers 2 and 3 with values of 1/3 and 2/3 of the period value, respectively. For example, if the period
register is loaded with a value of 600 counts, then TBPHS (slave 2) = 200 and TBPHS (slave 3) = 400.
Both slave modules are synchronized to the master 1 module.
This concept can be extended to four or more phases, by setting the TBPHS values appropriately. The
following formula gives the TBPHS values for N phases:
TBPHS(N,M) = (TBPRD/N) x (M-1)
Where:
N = number of phases
M = PWM module number
For example, for the 3-phase case (N=3), TBPRD = 600,
TBPHS(3,2) = (600/3) x (2-1) = 200 (that is, Phase value for Slave module 2)
TBPHS(3,3) = 400 (that is, Phase value for Slave module 3)
Figure 14-70 shows the waveforms for the configuration in Figure 14-69.

1756

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

Figure 14-69. Control of a 3-Phase Interleaved DC/DC Converter
Ext SyncIn
(optional)
Master
Phase reg
Φ=0°

SyncIn

VIN

En
EPWM1A
EPWM1B

CTR=zero
CTR=CMPB
X
1

EPWM1A

EPWM2A

EPWM3A

EPWM1B

EPWM2B

EPWM3B

SyncOut

Slave
Phase reg
Φ=120°

SyncIn

VOUT

En
EPWM2A
EPWM2B

CTR=zero
CTR=CMPB
X
2

SyncOut

Slave
Phase reg

SyncIn
En

Φ=240°

EPWM3A
EPWM3B

CTR=zero
CTR=CMPB
X
3

SyncOut

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1757

Applications to Power Topologies

www.ti.com

Figure 14-70. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 14-69
Z
I

285
CA

EPWM1A

285
P
A

CA

CA

RED

P
A

FED

Z
I

CA

CA

RED

EPWM1B
300

Z
I

Z
I

450

P
A

CA

RED

FED

FED

F2=120°

TBPHS
(=300)

EPWM2A

EPWM2B
300

F2=120°

TBPHS
(=300)

EPWM3A

EPWM3B

1758

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

14.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
The example given in Figure 14-71 assumes a static or constant phase relationship between legs
(modules). In such a case, control is achieved by modulating the duty cycle. It is also possible to
dynamically change the phase value on a cycle-by-cycle basis. This feature lends itself to controlling a
class of power topologies known as phase-shifted full bridge, or zero voltage switched full bridge. Here the
controlled parameter is not duty cycle (this is kept constant at approximately 50 percent); instead it is the
phase relationship between legs. Such a system can be implemented by allocating the resources of two
PWM modules to control a single power stage, which in turn requires control of four switching elements.
Figure 14-72 shows a master/slave module combination synchronized together to control a full H-bridge.
In this case, both master and slave modules are required to switch at the same PWM frequency. The
phase is controlled by using the slave's phase register (TBPHS). The master's phase register is not used
and therefore can be initialized to zero.
Figure 14-71. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1)
Ext SyncIn
(optional)
Master
Phase reg
Φ=0°

SyncIn
En
EPWM1A

CTR=zero
CTR=CMPB
X

Slave
Phase reg
Φ=Var°

Vout

VDC_bus

EPWM1B

SyncOut

EPWM1A

EPWM2A

EPWM1B

EPWM2B

SyncIn
En

CTR=zero
CTR=CMPB
X

EPWM2A
EPWM2B

SyncOut

Var = Variable

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1759

Applications to Power Topologies

www.ti.com

Figure 14-72. ZVS Full-H Bridge Waveforms
Period
TBCLK

CTR = PRD
or CTR = 0

Offset(n)
BLANKWDW

Offset(n+1)
Window(n)

Window(n+1)

Offset(n)

Offset(n+1)

BLANKWDW

Window(n)

Offset(n)

Window(n+1)

Offset(n+1)

14.13.10 Controlling a Peak Current Mode Controlled Buck Module
Peak current control techniques offer a number of benefits like automatic over current limiting, fast
correction for input voltage variations and reducing magnetic saturation. Figure 14-73 shows the use of
ePWM1A along with the on-chip analog comparator for buck converter topology. The output current is
sensed through a current sense resistor and fed to the positive terminal of the on-chip comparator. The
internal programmable 10-bit DAC can be used to provide a reference peak current at the negative
terminal of the comparator. Alternatively, an external reference could be connected at this input. The
comparator output is an input to the Digital compare sub-module. The ePWM module is configured in such
a way so as to trip the ePWM1A output as soon as the sensed current reaches the peak reference value.
A cycle-by-cycle trip mechanism is used. Figure 14-74 shows the waveforms generated by the
configuration.
Figure 14-73. Peak Current Mode Control of a Buck Converter
Vin
Phase Reg

"#$#%

En

Vout

SyncIn

!

EPWM1A

EPWM1A

CNT=Zero
CNT=CMPB

EPWM1B

X
SyncOut
COMP1+/
ADCA2

Isense

Difference
Amplifier

1760

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Applications to Power Topologies

www.ti.com

Figure 14-74. Peak Current Mode Control Waveforms for Figure 14-73

0
R=

3
to

00

CT
TB

ePWM1
Time base

TBPRD
= 300

Increased
Load

DAC OUT/
COMP1-

Isense

DCAEVT2.force

ePWM1A

14.13.11 Controlling H-Bridge LLC Resonant Converter
Various topologies of resonant converters are well-known in the field of power electronics for many years.
In addition to these, H-bridge LLC resonant converter topology has recently gained popularity in many
consumer electronics applications where high efficiency and power density are required. In this example
single channel configuration of ePWM1 is detailed, yet the configuration can easily be extended to multi
channel. Here the controlled parameter is not duty cycle (this is kept constant at approximately 50
percent); instead it is frequency. Although the deadband is not controlled and kept constant as 300ns (that
is, 30 @100MHz TBCLK), it is up to user to update it in real time to enhance the efficiency by adjusting
enough time delay for soft switching.
Figure 14-75. Control of Two Resonant Converter Stages
Ext Sync In
(optional)

Master
Phase Reg

En

SyncIn
EPWM1A

!"#" X

Integrated
Magnetcis

V OUT

LLC Resonant
Transformer

EPWM1A

CNT=Zero
CNT=CMPB

1

V DC_bus

X

EPWM1B
SyncOut

EPWM1B

Cr

NOTE: Θ = X indicates value in phase register is a"don't care"

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1761

Applications to Power Topologies

www.ti.com

Figure 14-76. H-Bridge LLC Resonant Converter PWM Waveforms
P

P

P

I

I

I

period
period/2
period/4

P

CB

CA

P

CB

A

CA

P

A

EPWMxA

RED

ZVS
transition

EPWMxB

FED

ZVS
transition

P

I

1762

Indicates this event triggers an interrupt

Enhanced Pulse Width Modulator (ePWM)

CB

A

Indicates this event triggers an ADC
start of conversion

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14 Registers
14.14.1 EPWM Base Addresses
Table 14-13. EPWM Base Address Table
Device Register

Register Name

Start Address

End Address

EPwm1Regs

EPWM_REGS

0x0000_4000

0x0000_40FF

EPwm2Regs

EPWM_REGS

0x0000_4100

0x0000_41FF

EPwm3Regs

EPWM_REGS

0x0000_4200

0x0000_42FF

EPwm4Regs

EPWM_REGS

0x0000_4300

0x0000_43FF

EPwm5Regs

EPWM_REGS

0x0000_4400

0x0000_44FF

EPwm6Regs

EPWM_REGS

0x0000_4500

0x0000_45FF

EPwm7Regs

EPWM_REGS

0x0000_4600

0x0000_46FF

EPwm8Regs

EPWM_REGS

0x0000_4700

0x0000_47FF

EPwm9Regs

EPWM_REGS

0x0000_4800

0x0000_48FF

EPwm10Regs

EPWM_REGS

0x0000_4900

0x0000_49FF

EPwm11Regs

EPWM_REGS

0x0000_4A00

0x0000_4AFF

EPwm12Regs

EPWM_REGS

0x0000_4B00

0x0000_4BFF

EPwmXbarRegs (1)

EPWM_XBAR_REGS

0x0000_7A00

0x0000_7A3F

SYNC_SOC_REGS

0x0000_7940

0x0000_794F

SyncSocRegs
(1)

(1)

Only available on CPU1.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1763

Registers

www.ti.com

14.14.2 EPWM_REGS Registers
Table 14-14 lists the memory-mapped registers for the EPWM_REGS. All register offset addresses not
listed in Table 14-14 should be considered as reserved locations and the register contents should not be
modified.
Table 14-14. EPWM_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

TBCTL

Time Base Control Register

Go

1h

TBCTL2

Time Base Control Register 2

Go

3h

EPWMSYNCINSEL

EPWMxSYNCIN Source Select Register

Go

4h

TBCTR

Time Base Counter Register

Go

5h

TBSTS

Time Base Status Register

Go

6h

EPWMSYNCOUTEN

EPWMxSYNCOUT Source Enable Register

Go

8h

CMPCTL

Counter Compare Control Register

Go

9h

CMPCTL2

Counter Compare Control Register 2

Go

Ch

DBCTL

Dead-Band Generator Control Register

Go

Dh

DBCTL2

Dead-Band Generator Control Register 2

Go

10h

AQCTL

Action Qualifier Control Register

Go

11h

AQTSRCSEL

Action Qualifier Trigger Event Source Select
Register

Go

14h

PCCTL

PWM Chopper Control Register

Go

18h

VCAPCTL

Valley Capture Control Register

Go

19h

VCNTCFG

Valley Counter Config Register

20h

HRCNFG

HRPWM Configuration Register

EALLOW

Go

21h

HRPWR

HRPWM Power Register

EALLOW

Go

26h

HRMSTEP

HRPWM MEP Step Register

EALLOW

Go

27h

HRCNFG2

HRPWM Configuration 2 Register

EALLOW

Go

2Dh

HRPCTL

High Resolution Period Control Register

EALLOW

Go

2Eh

TRREM

Translator High Resolution Remainder Register

EALLOW

Go

34h

GLDCTL

Global PWM Load Control Register

EALLOW

Go

35h

GLDCFG

Global PWM Load Config Register

EALLOW

Go

Go

38h

EPWMXLINK

EPWMx Link Register

Go

3Eh

EPWMREV

EPWM Revision Register

Go

40h

AQCTLA

Action Qualifier Control Register For Output A

Go

41h

AQCTLA2

Additional Action Qualifier Control Register For
Output A

Go

42h

AQCTLB

Action Qualifier Control Register For Output B

Go

43h

AQCTLB2

Additional Action Qualifier Control Register For
Output B

Go

47h

AQSFRC

Action Qualifier Software Force Register

Go

49h

AQCSFRC

Action Qualifier Continuous S/W Force Register

Go

50h

DBREDHR

Dead-Band Generator Rising Edge Delay High
Resolution Mirror Register

Go

51h

DBRED

Dead-Band Generator Rising Edge Delay High
Resolution Mirror Register

Go

52h

DBFEDHR

Dead-Band Generator Falling Edge Delay High
Resolution Register

Go

53h

DBFED

Dead-Band Generator Falling Edge Delay Count
Register

Go

60h

TBPHS

Time Base Phase High

Go

62h

TBPRDHR

Time Base Period High Resolution Register

Go

63h

TBPRD

Time Base Period Register

Go

1764

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-14. EPWM_REGS Registers (continued)
Offset

Acronym

Register Name

6Ah

CMPA

Counter Compare A Register

Write Protection

Section
Go

6Ch

CMPB

Compare B Register

Go

6Fh

CMPC

Counter Compare C Register

Go

71h

CMPD

Counter Compare D Register

74h

GLDCTL2

Global PWM Load Control Register 2

77h

SWVDELVAL

Software Valley Mode Delay Register

80h

TZSEL

Trip Zone Select Register

EALLOW

Go

82h

TZDCSEL

Trip Zone Digital Comparator Select Register

EALLOW

Go

84h

TZCTL

Trip Zone Control Register

EALLOW

Go

85h

TZCTL2

Additional Trip Zone Control Register

EALLOW

Go

86h

TZCTLDCA

Trip Zone Control Register Digital Compare A

EALLOW

Go

Go
EALLOW

Go
Go

87h

TZCTLDCB

Trip Zone Control Register Digital Compare B

EALLOW

Go

8Dh

TZEINT

Trip Zone Enable Interrupt Register

EALLOW

Go

93h

TZFLG

Trip Zone Flag Register

Go

94h

TZCBCFLG

Trip Zone CBC Flag Register

Go

95h

TZOSTFLG

Trip Zone OST Flag Register

97h

TZCLR

Trip Zone Clear Register

EALLOW

Go

98h

TZCBCCLR

Trip Zone CBC Clear Register

EALLOW

Go

Go

99h

TZOSTCLR

Trip Zone OST Clear Register

EALLOW

Go

9Bh

TZFRC

Trip Zone Force Register

EALLOW

Go

A4h

ETSEL

Event Trigger Selection Register

Go

A6h

ETPS

Event Trigger Pre-Scale Register

Go

A8h

ETFLG

Event Trigger Flag Register

Go

AAh

ETCLR

Event Trigger Clear Register

Go

ACh

ETFRC

Event Trigger Force Register

Go

AEh

ETINTPS

Event-Trigger Interrupt Pre-Scale Register

Go

B0h

ETSOCPS

Event-Trigger SOC Pre-Scale Register

Go

B2h

ETCNTINITCTL

Event-Trigger Counter Initialization Control
Register

Go

B4h

ETCNTINIT

Event-Trigger Counter Initialization Register

C0h

DCTRIPSEL

Digital Compare Trip Select Register

EALLOW

Go
Go

C3h

DCACTL

Digital Compare A Control Register

EALLOW

Go

C4h

DCBCTL

Digital Compare B Control Register

EALLOW

Go

C7h

DCFCTL

Digital Compare Filter Control Register

EALLOW

Go

C8h

DCCAPCTL

Digital Compare Capture Control Register

EALLOW

Go

C9h

DCFOFFSET

Digital Compare Filter Offset Register

Go

CAh

DCFOFFSETCNT

Digital Compare Filter Offset Counter Register

Go

CBh

DCFWINDOW

Digital Compare Filter Window Register

Go

CCh

DCFWINDOWCNT

Digital Compare Filter Window Counter Register

Go

CFh

DCCAP

Digital Compare Counter Capture Register

D2h

DCAHTRIPSEL

Digital Compare AH Trip Select

EALLOW

Go

D3h

DCALTRIPSEL

Digital Compare AL Trip Select

EALLOW

Go

D4h

DCBHTRIPSEL

Digital Compare BH Trip Select

EALLOW

Go

D5h

DCBLTRIPSEL

Digital Compare BL Trip Select

EALLOW

Go

FAh

EPWMLOCK

EPWM Lock Register

Go

FDh

HWVDELVAL

Hardware Valley Mode Delay Register

Go

FEh

VCNTVAL

Hardware Valley Counter Register

Go

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Go

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1765

Registers

www.ti.com

Complex bit access types are encoded to fit into small table cells. Table 14-15 shows the codes that are
used for access types in this section.
Table 14-15. EPWM_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W1C

1C
W

1 to clear
Write

W=1

W

Write

WOnce

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

1766

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.1 TBCTL Register (Offset = 0h) [reset = 83h]
TBCTL is shown in Figure 14-77 and described in Table 14-16.
Return to Summary Table.
Time Base Control Register
Figure 14-77. TBCTL Register
15

14
FREE_SOFT
R/W-0h

7
HSPCLKDIV
R/W-1h

6
SWFSYNC
R=0/W=1-0h

13
PHSDIR
R/W-0h

12

5

4
SYNCOSEL
R/W-0h

11
CLKDIV
R/W-0h

10

3
PRDLD
R/W-0h

2
PHSEN
R/W-0h

9

8
HSPCLKDIV
R/W-1h

1

0
CTRMODE
R/W-3h

Table 14-16. TBCTL Register Field Descriptions
Bit
15-14

Field

Type

Reset

Description

FREE_SOFT

R/W

0h

Emulation Mode Bits. These bits select the behavior of the ePWM
time-base counter during emulation events
00: Stop after the next time-base counter increment or decrement
01: Stop when counter completes a whole cycle:
- Up-count mode: stop when the time-base counter = period (TBCTR
= TBPRD)
- Down-count mode: stop when the time-base counter = 0x00
(TBCTR = 0x00)
- Up-down-count mode: stop when the time-base counter = 0x00
(TBCTR = 0x00)
1x: Free run
Reset type: SYSRSn

13

PHSDIR

R/W

0h

Phase Direction Bit
This bit is only used when the time-base counter is configured in the
up-down-count mode. The
PHSDIR bit indicates the direction the time-base counter (TBCTR)
will count after a synchronization
event occurs and a new phase value is loaded from the phase
(TBPHS) register. This is
irrespective of the direction of the counter before the synchronization
event..
In the up-count and down-count modes this bit is ignored.
0: Count down after the synchronization event.
1: Count up after the synchronization event.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1767

Registers

www.ti.com

Table 14-16. TBCTL Register Field Descriptions (continued)
Bit
12-10

Field

Type

Reset

Description

CLKDIV

R/W

0h

Time Base Clock Pre-Scale Bits
These bits select the time base clock pre-scale value (TBCLK =
EPWMCLK/(HSPCLKDIV * CLKDIV):
000: /1 (default on reset)
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128
Reset type: SYSRSn

9-7

HSPCLKDIV

R/W

1h

High Speed Time Base Clock Pre-Scale Bits
These bits determine part of the time-base clock prescale value.
TBCLK = EPWMCLK / (HSPCLKDIV x CLKDIV). This divisor
emulates the HSPCLK in the TMS320x281x system as used on the
Event Manager (EV) peripheral.
000: /1
001: /2 (default on reset)
010: /4
011: /6
100: /8
101: /10
110: /12
111: /14
Reset type: SYSRSn

6

SWFSYNC

R=0/W=1

0h

Software Forced Sync Pulse
0: Writing a 0 has no effect and reads always return a 0.
1: Writing a 1 forces a one-time synchronization pulse to be
generated.
SWFSYNC affects EPWMxSYNCO only when SYNCOSEL = 00.
Reset type: SYSRSn

5-4

SYNCOSEL

R/W

0h

Sync Output Select
00: EPWMxSYNCI / SWFSYNC
01: CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)
10: CTR = CMPB : Time-base counter equal to counter-compare B
(TBCTR = CMPB)
11: EPWMXSYNCO is defined by TBCTL2[SYNCOSELX]
Reset type: SYSRSn

3

PRDLD

R/W

0h

Active Period Reg Load from Shadow Select
0: The period register (TBPRD) is loaded from its shadow register
when the time-base counter, TBCTR, is equal to zero and/or a sync
event as determined by the TBCTL2[PRDLDSYNC] bit.
A write/read to the TBPRD register accesses the shadow register.
1: Immediate Mode (Shadow register bypassed): A write or read to
the TBPRD register accesses the active register.
Reset type: SYSRSn

1768

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-16. TBCTL Register Field Descriptions (continued)
Bit
2

Field

Type

Reset

Description

PHSEN

R/W

0h

Counter Reg Load from Phase Reg Enable
0: Do not load the time-base counter (TBCTR) from the time-base
phase register (TBPHS).
1: Allow Counter to be loaded from the Phase register (TBPHS) and
shadow to active load events when an EPWMxSYNCI input signal
occurs or a software-forced sync signal, see bit 6.
Reset type: SYSRSn

1-0

CTRMODE

R/W

3h

Counter Mode
The time-base counter mode is normally configured once and not
changed during normal operation. If you change the mode of the
counter, the change will take effect at the next TBCLK edge and the
current counter value shall increment or decrement from the value
before the mode change. These bits set the time-base counter mode
of operation as follows:
00: Up-count mode
01: Down-count mode
10: Up-down count mode
11: Freeze counter operation (default on reset)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1769

Registers

www.ti.com

14.14.2.2 TBCTL2 Register (Offset = 1h) [reset = 0h]
TBCTL2 is shown in Figure 14-78 and described in Table 14-17.
Return to Summary Table.
Time Base Control Register 2
Figure 14-78. TBCTL2 Register
15

14

13

PRDLDSYNC
R/W-0h
7
OSHTSYNC
R=0/W=1-0h

6
OSHTSYNCM
ODE
R/W-0h

12

11

10

SYNCOSELX
R/W-0h
5
RESERVED

9

8

1

0

RESERVED
R=0-0h
4

3

2
RESERVED

R-0h

R=0-0h

Table 14-17. TBCTL2 Register Field Descriptions
Bit
15-14

Field

Type

Reset

Description

PRDLDSYNC

R/W

0h

Shadow to Active Period Register Load on SYNC event
00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0
(same as legacy).
01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0
and when SYNC occurs.
10: Shadow to Active Load of TBPRD occurs only when a SYNC is
received.
11: Reserved
Note: This bit selection is valid only if TBCTL[PRDLD]=0.
Reset type: SYSRSn

13-12

SYNCOSELX

R/W

0h

Extended selection bits for SYNCOUT
00: Disabled EPWMxSYNCO sync signal
01: EPWMxSYNCO = CMPC
10: EPWMxSYNCO = CMPD
11: Reserved
Reset type: SYSRSn

11-8

RESERVED

R=0

0h

Reserved

7

OSHTSYNC

R=0/W=1

0h

Oneshot sync bit
0: Writing a '0' has no effect.
1: Allow one sync pulse to propogate.
Reset type: SYSRSn

6

OSHTSYNCMODE

R/W

0h

Oneshot sync enable bit
0: Oneshot sync mode disabled
1: Oneshot sync mode enabled
Reset type: SYSRSn

1770

5

RESERVED

R

0h

Reserved

4-0

RESERVED

R=0

0h

Reserved

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.3 EPWMSYNCINSEL Register (Offset = 3h) [reset = 1h]
EPWMSYNCINSEL is shown in Figure 14-79 and described in Table 14-18.
Return to Summary Table.
EPWMxSYNCIN Source Select Register
Figure 14-79. EPWMSYNCINSEL Register
15

14

13

12

11

10

9

8

3

2
SEL
R/W-1h

1

0

RESERVED
R-0h
7

6
RESERVED
R-0h

5

4

Table 14-18. EPWMSYNCINSEL Register Field Descriptions
Field

Type

Reset

Description

15-5

Bit

RESERVED

R

0h

Reserved

4-0

SEL

R/W

1h

These bits determine the source of the EPWMxSYNCI signal.
+I722
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1771

Registers

www.ti.com

14.14.2.4 TBCTR Register (Offset = 4h) [reset = 0h]
TBCTR is shown in Figure 14-80 and described in Table 14-19.
Return to Summary Table.
Time Base Counter Register
Figure 14-80. TBCTR Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TBCTR
R/W-0h

Table 14-19. TBCTR Register Field Descriptions
Bit
15-0

1772

Field

Type

Reset

Description

TBCTR

R/W

0h

Time Base Counter Register
Reset type: SYSRSn

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.5 TBSTS Register (Offset = 5h) [reset = 1h]
TBSTS is shown in Figure 14-81 and described in Table 14-20.
Return to Summary Table.
Time Base Status Register
Figure 14-81. TBSTS Register
15

14

13

12

11

10

9

8

3

2
CTRMAX
R/W1C-0h

1
SYNCI
R/W1C-0h

0
CTRDIR
R-1h

RESERVED
R=0-0h
7

6

5
RESERVED
R=0-0h

4

Table 14-20. TBSTS Register Field Descriptions
Bit
15-3
2

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

CTRMAX

R/W1C

0h

Time-Base Counter Max Latched Status Bit
0: Reading a 0 indicates the time-base counter never reached its
maximum value. Writing a 0 will have no effect.
1: Reading a 1 on this bit indicates that the time-base counter
reached the max value 0xFFFF. Writing a 1 to this bit will clear the
latched event.
Reset type: SYSRSn

1

SYNCI

R/W1C

0h

Input Synchronization Latched Status Bit
0: Writing a 0 will have no effect. Reading a 0 indicates no external
synchronization event has occurred.
1: Reading a 1 on this bit indicates that an external synchronization
event has occurred (EPWMxSYNCI). Writing a 1 to this bit will clear
the latched event.
Reset type: SYSRSn

0

CTRDIR

R

1h

Time Base Counter Direction Status Bit
0: Time-Base Counter is currently counting down.
1: Time-Base Counter is currently counting up.
Note: This bit is only valid when the counter is not frozen.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1773

Registers

www.ti.com

14.14.2.6 EPWMSYNCOUTEN Register (Offset = 6h) [reset = 1h]
EPWMSYNCOUTEN is shown in Figure 14-82 and described in Table 14-21.
Return to Summary Table.
EPWMxSYNCOUT Source Enable Register
Figure 14-82. EPWMSYNCOUTEN Register
15

14

13

12

11

10

9

8

3
CMPCEN
R/W-0h

2
CMPBEN
R/W-0h

1
ZEROEN
R/W-0h

0
SWEN
R/W-1h

RESERVED
R-0h
7
RESERVED
R-0h

6
DCBEVT1EN
R/W-0h

5
DCAEVT1EN
R/W-0h

4
CMPDEN
R/W-0h

Table 14-21. EPWMSYNCOUTEN Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7

RESERVED

R

0h

Reserved

6

DCBEVT1EN

R/W

0h

This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO
signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period
upon a DCBEVT1.sync event
Reset type: SYSRSn

5

DCAEVT1EN

R/W

0h

This bit enables the DCAEVT1.sync event to set the
EPWMxSYNCOUT signal.
0 Disabled
1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period
upon a DCAEVT1.sync event
Reset type: SYSRSn

4

CMPDEN

R/W

0h

This bit enables the TBCTR = CMPD event to set the
EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period
upon a time-base counter equal to counter compare D event
(TBCTR = CMPD)
Reset type: SYSRSn

3

CMPCEN

R/W

0h

This bit enables the TBCTR = CMPC event to set the
EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period
upon a time-base counter equal to counter compare C event
(TBCTR = CMPC)
Reset type: SYSRSn

2

CMPBEN

R/W

0h

This bit enables the TBCTR = CMPB event to set the
EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period
upon a time-base counter equal to counter compare B event
(TBCTR = CMPB)
Reset type: SYSRSn

1774

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-21. EPWMSYNCOUTEN Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

ZEROEN

R/W

0h

This bit enables the TBCTR = 0x0000 event to set the
EPWMxSYNCOUT signal.
0 Disabled
1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period
upon the value of TBCTR changing to 0x0000
Reset type: SYSRSn

0

SWEN

R/W

1h

This bit enables the TBCTL.SWFSYNC bit to set the
EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period
when the TBCTL.SWFSYNC bit is set
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1775

Registers

www.ti.com

14.14.2.7 CMPCTL Register (Offset = 8h) [reset = 0h]
CMPCTL is shown in Figure 14-83 and described in Table 14-22.
Return to Summary Table.
Counter Compare Control Register
Figure 14-83. CMPCTL Register
15

14

13

RESERVED
R=0-0h
7
RESERVED
R=0-0h

6
SHDWBMODE
R/W-0h

12

11

LOADBSYNC
R/W-0h
5
RESERVED
R=0-0h

4
SHDWAMODE
R/W-0h

10

9
SHDWBFULL
R-0h

8
SHDWAFULL
R-0h

2

1

0

LOADASYNC
R/W-0h
3
LOADBMODE
R/W-0h

LOADAMODE
R/W-0h

Table 14-22. CMPCTL Register Field Descriptions
Field

Type

Reset

Description

15-14

Bit

RESERVED

R=0

0h

Reserved

13-12

LOADBSYNC

R/W

0h

Shadow to Active CMPB Register Load on SYNC event
00: Shadow to Active Load of CMPB:CMPBHR occurs according to
LOADBMODE (bits 1,0) (same as legacy)
01: Shadow to Active Load of CMPB:CMPBHR occurs both
according to LOADBMODE bits and when SYNC occurs
10: Shadow to Active Load of CMPB:CMPBHR occurs only when a
SYNC is received
11: Reserved
Note: This bit is valid only if CMPCTL[SHDWBMODE] = 0.
Reset type: SYSRSn

11-10

LOADASYNC

R/W

0h

Shadow to Active CMPA Register Load on SYNC event
00: Shadow to Active Load of CMPA:CMPAHR occurs according to
LOADAMODE (bits 1,0) (same as legacy)
01: Shadow to Active Load of CMPA:CMPAHR occurs both
according to LOADAMODE bits and when SYNC occurs
10: Shadow to Active Load of CMPA:CMPAHR occurs only when a
SYNC is received
11: Reserved
Note: This bit is valid only if CMPCTL[SHDWAMODE] = 0.
Reset type: SYSRSn

9

SHDWBFULL

R

0h

Counter-compare B (CMPB) Shadow Register Full Status Flag
This bit self clears once a loadstrobe occurs.
0: CMPB shadow FIFO not full yet
1: Indicates the CMPB shadow FIFO is full
a CPU write will overwrite current shadow value
Reset type: SYSRSn

8

SHDWAFULL

R

0h

Counter-compare A (CMPA) Shadow Register Full Status Flag
The flag bit is set when a 32-bit write to CMPA:CMPAHR register or
a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR
register will not affect the flag. This bit self clears once a load-strobe
occurs.
0: CMPA shadow FIFO not full yet
1: Indicates the CMPA shadow FIFO is full, a CPU write will
overwrite the current shadow value
Reset type: SYSRSn

1776

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-22. CMPCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7

RESERVED

R=0

0h

Reserved

6

SHDWBMODE

R/W

0h

Counter-compare B (CMPB) Register Operating Mode
0: Shadow mode. Operates as a double buffer. All writes via the
CPU access the shadow register
1: Immediate mode. Only the active compare B register is used. All
writes and reads directly access the active register for immediate
compare action
Reset type: SYSRSn

5

RESERVED

R=0

0h

Reserved

4

SHDWAMODE

R/W

0h

Counter-compare A (CMPA) Register Operating Mode
0: Shadow mode. Operates as a double buffer. All writes via the
CPU access the shadow register
1: Immediate mode. Only the active compare register is used. All
writes and reads directly access the active register for immediate
compare action
Reset type: SYSRSn

3-2

LOADBMODE

R/W

0h

Active Counter-Compare B (CMPB) Load From Shadow Select
Mode
This bit has no effect in immediate mode (CMPCTL[SHDWBMODE]
= 1).
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)
Reset type: SYSRSn

1-0

LOADAMODE

R/W

0h

Active Counter-Compare A (CMPA) Load From Shadow Select
Mode
This bit has no effect in immediate mode (CMPCTL[SHDWAMODE]
= 1).
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1777

Registers

www.ti.com

14.14.2.8 CMPCTL2 Register (Offset = 9h) [reset = 0h]
CMPCTL2 is shown in Figure 14-84 and described in Table 14-23.
Return to Summary Table.
Counter Compare Control Register 2
Figure 14-84. CMPCTL2 Register
15

14
RESERVED
R=0-0h

7
RESERVED
R=0-0h

6
SHDWDMODE
R/W-0h

13

12

11

10

LOADDSYNC
R/W-0h
5
RESERVED
R=0-0h

4
SHDWCMODE
R/W-0h

9

LOADCSYNC
R/W-0h
3

8
RESERVED
R=0-0h

2
LOADDMODE
R/W-0h

1

0
LOADCMODE
R/W-0h

Table 14-23. CMPCTL2 Register Field Descriptions
Field

Type

Reset

Description

15-14

Bit

RESERVED

R=0

0h

Reserved

13-12

LOADDSYNC

R/W

0h

Shadow to Active CMPD Register Load on SYNC event
00: Shadow to Active Load of CMPD occurs according to
LOADDMODE
01: Shadow to Active Load of CMPD occurs both according to
LOADDMODE bits and when SYNC occurs
10: Shadow to Active Load of CMPD occurs only when a SYNC is
received
11: Reserved
Note: This bit is valid only if CMPCTL2[SHDWDMODE] = 0.
Reset type: SYSRSn

11-10

LOADCSYNC

R/W

0h

Shadow to Active CMPC Register Load on SYNC event
00: Shadow to Active Load of CMPC occurs according to
LOADCMODE
01: Shadow to Active Load of CMPC occurs both according to
LOADCMODE bits and when SYNC occurs
10: Shadow to Active Load of CMPC occurs only when a SYNC is
received
11: Reserved
Note: This bit is valid only if CMPCTL2[SHDWCMODE] = 0.
Reset type: SYSRSn

9-7
6

RESERVED

R=0

0h

Reserved

SHDWDMODE

R/W

0h

Counter-Compare D Register Operating Mode
0: Shadow mode - operates as a double buffer. All writes via the
CPU access Shadow register.
1: Immediate mode - only the Active compare register is used. All
writes/reads via the CPU directly access the Active register for
immediate Compare action.
Reset type: SYSRSn

5

1778

RESERVED

R=0

Enhanced Pulse Width Modulator (ePWM)

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-23. CMPCTL2 Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

SHDWCMODE

R/W

0h

Counter-Compare C Register Operating Mode
0: Shadow mode - operates as a double buffer. All writes via the
CPU access Shadow register.
1: Immediate mode - only the Active compare register is used. All
writes/reads via the CPU directly access the Active register for
immediate Compare action.
Reset type: SYSRSn

3-2

LOADDMODE

R/W

0h

Active Counter-Compare D (CMPD) Load from Shadow Select Mode
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)
Note: Has no effect in Immediate mode.
Reset type: SYSRSn

1-0

LOADCMODE

R/W

0h

Active Counter-Compare C (CMPC) Load from Shadow Select Mode
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)
Note: Has no effect in Immediate mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1779

Registers

www.ti.com

14.14.2.9 DBCTL Register (Offset = Ch) [reset = 0h]
DBCTL is shown in Figure 14-85 and described in Table 14-24.
Return to Summary Table.
Dead-Band Generator Control Register
Figure 14-85. DBCTL Register
15
HALFCYCLE

14
DEDB_MODE

R/W-0h

R/W-0h

7
6
LOADREDMODE
R/W-0h

13

12
OUTSWAP
R/W-0h

5

4

11
SHDWDBFED
MODE
R/W-0h

10
SHDWDBRED
MODE
R/W-0h

3

2

IN_MODE
R/W-0h

POLSEL
R/W-0h

9
8
LOADFEDMODE
R/W-0h
1

0
OUT_MODE
R/W-0h

Table 14-24. DBCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

HALFCYCLE

R/W

0h

Half Cycle Clocking Enable Bit
0: Full cycle clocking enabled. The dead-band counters are clocked
at the TBCLK rate.
1: Half cycle clocking enabled. The dead-band counters are clocked
at TBCLK*2.
Reset type: SYSRSn

14

DEDB_MODE

R/W

0h

Dead Band Dual-Edge B Mode Control (S8 switch)
0: Rising edge delay applied to InA/InB as selected by S4 switch (INMODE bits) on A signal path only. Falling edge delay applied to
InA/InB as selected by S5 switch (INMODE bits) on B signal path
only.
1: Rising edge delay and falling edge delay applied to source
selected by S4 switch (INMODE bits) and output to B signal path
only. Note: When this bit is set to 1, user should always either set
OUT_MODE bits such that Apath = InA OR OUTSWAP bits such
that OutA=Bpath
otherwise, OutA will be invalid.
Reset type: SYSRSn

13-12

OUTSWAP

R/W

0h

Dead Band Output Swap Control
Bit 13 controls the S7 switch and bit 12 controls the S6 switch.
00: OutA and OutB signals are as defined by OUT-MODE bits.
01: OutA = A-path as defined by OUT-MODE bits.
OutB = A-path as defined by OUT-MODE bits (rising edge delay or
delay-bypassed A signal path).
10: OutA = B-path as defined by OUT-MODE bits (falling edge delay
or delay-bypassed B signal path).
OutB = B-path as defined by OUT-MODE bits.
11: OutA = B-path as defined by OUT-MODE bits (falling edge delay
or delay-bypassed B signal path).
OutB = A-path as defined by OUT-MODE bits (rising edge delay or
delay-bypassed A signal path).
Reset type: SYSRSn

1780

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-24. DBCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

SHDWDBFEDMODE

R/W

0h

FED Dead-Band Load Mode
0: Immediate mode. Only the active DBFED register is used. All
writes/reads via the CPU directly access the active register for
immediate "FED dead-band action."
1: Shadow mode. Operates as a double buffer. All writes via the
CPU access Shadow register. Default at Reset is Immediate mode
(for compatibility with legacy).
Reset type: SYSRSn

10

SHDWDBREDMODE

R/W

0h

RED Dead-Band Load Mode
0: Immediate mode. Only the active DBRED register is used. All
writes/reads via the CPU directly access the active register for
immediate "RED dead-band action."
1: Shadow mode. Operates as a double buffer. All writes via the
CPU access Shadow register. Default at Reset is Immediate mode
(for compatibility with legacy).
Reset type: SYSRSn

9-8

LOADFEDMODE

R/W

0h

Active DBFED Load from Shadow Select Mode
00: Load on Counter = 0 (CNT_eq)
01: Load on Counter = Period (PRD_eq)
10: Load on either Counter = 0, or Counter = Period
11: Freeze (no loads possible)
Note: has no effect in Immediate mode.
Reset type: SYSRSn

7-6

LOADREDMODE

R/W

0h

Active DBRED Load from Shadow Select Mode
00: Load on Counter = 0 (CNT_eq)
01: Load on Counter = Period (PRD_eq)
10: Load on either Counter = 0, or Counter = Period
11: Freeze (no loads possible)
Note: has no effect in Immediate mode.
Reset type: SYSRSn

5-4

IN_MODE

R/W

0h

Dead-Band Input Mode Control
Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown.
This allows you to select the input source to the falling-edge and
rising-edge delay. To produce classical dead-band waveforms the
default is EPWMxA In is the source for both falling and rising-edge
delays.
00: EPWMxA In (from the action-qualifier) is the source for both
falling-edge and rising-edge delay.
01: EPWMxB In (from the action-qualifier) is the source for risingedge delayed signal.
EPWMxA In (from the action-qualifier) is the source for falling-edge
delayed signal.
10: EPWMxA In (from the action-qualifier) is the source for risingedge delayed signal.
EPWMxB In (from the action-qualifier) is the source for falling-edge
delayed signal.
11: EPWMxB In (from the action-qualifier) is the source for both
rising-edge delay and falling-edge delayed signal.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1781

Registers

www.ti.com

Table 14-24. DBCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-2

POLSEL

R/W

0h

Polarity Select Control
Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This
allows you to selectively invert one of the delayed signals before it is
sent out of the dead-band submodule. The following descriptions
correspond to classical upper/lower switch control as found in one
leg of a digital motor control inverter. These assume that
DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0x0. Other
enhanced modes are also possible, but not regarded as typical
usage modes.
00: Active high (AH) mode. Neither EPWMxA nor EPWMxB is
inverted (default).
01: Active low complementary (ALC) mode. EPWMxA is inverted.
10: Active high complementary (AHC). EPWMxB is inverted.
11: Active low (AL) mode. Both EPWMxA and EPWMxB are
inverted.
Reset type: SYSRSn

1-0

OUT_MODE

R/W

0h

Dead-Band Output Mode Control
Bit 1 controls the S1 switch and bit 0 controls the S0 switch.
00: DBM is fully disabled or by-passed. In this mode the POLSEL
and IN-MODE bits have no effect.
01: Apath = InA (delay is by-passed for A signal path)
Bpath = FED (Falling Edge Delay in B signal path)
10: Apath = RED (Rising Edge Delay in A signal path)
Bpath = InB (delay is by-passed for B signal path)
11: DBM is fully enabled (i.e. both RED and FED active)
Reset type: SYSRSn

1782

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.10 DBCTL2 Register (Offset = Dh) [reset = 0h]
DBCTL2 is shown in Figure 14-86 and described in Table 14-25.
Return to Summary Table.
Dead-Band Generator Control Register 2
Figure 14-86. DBCTL2 Register
15

14

13

12

11

10

3

2
SHDWDBCTL
MODE
R/W-0h

9

8

RESERVED
R=0-0h
7

6

5
RESERVED

4

R=0-0h

1
0
LOADDBCTLMODE
R/W-0h

Table 14-25. DBCTL2 Register Field Descriptions
Bit
15-3
2

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

SHDWDBCTLMODE

R/W

0h

DBCTL Load Mode
0: Immediate mode - only the Active DBCTL register is used. All
writes/reads via the CPU directly access the Active register.
1: Shadow mode - All writes and reads via the CPU access the
Shadow register.
Reset type: SYSRSn

1-0

LOADDBCTLMODE

R/W

0h

Active DBCTL Load from Shadow Select Mode
00: Load on Counter = 0 (CNT_eq)
01: Load on Counter = Period (PRD_eq)
10: Load on either Counter = 0, or Counter = Period
11: Freeze (no loads possible)
Note: has no effect in Immediate mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1783

Registers

www.ti.com

14.14.2.11 AQCTL Register (Offset = 10h) [reset = 0h]
AQCTL is shown in Figure 14-87 and described in Table 14-26.
Return to Summary Table.
Action Qualifier Control Register
Figure 14-87. AQCTL Register
15

14

13

12

11

RESERVED
R=0-0h
7
RESERVED
R=0-0h

6
SHDWAQBMO
DE
R/W-0h

10

9

LDAQBSYNC
R/W-0h

5
RESERVED
R=0-0h

4
SHDWAQAMO
DE
R/W-0h

3

8
LDAQASYNC
R/W-0h

2

1

0

LDAQBMODE

LDAQAMODE

R/W-0h

R/W-0h

Table 14-26. AQCTL Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R=0

0h

Reserved

11-10

LDAQBSYNC

R/W

0h

Shadow to Active AQCTLB Register Load on SYNC event
00: Shadow to Active Load of AQCTLB occurs according to
LDAQBMODE
01: Shadow to Active Load of AQCTLB occurs both according to
LDAQBMODE bits and when SYNC occurs.
10: Shadow to Active Load of AQCTLB occurs only when a SYNC is
received.
11: Reserved
Note: This bit is valid only if AQCTLR[SHDWAQBMODE] = 1.
Reset type: SYSRSn

9-8

LDAQASYNC

R/W

0h

Shadow to Active AQCTLA Register Load on SYNC event
00: Shadow to Active Load of AQCTLA occurs according to
LDAQAMODE
01: Shadow to Active Load of AQCTLA occurs both according to
LDAQAMODE bits and when SYNC occurs.
10: Shadow to Active Load of AQCTLA occurs only when a SYNC is
received.
11: Reserved
Note: This bit is valid only if AQCTLR[SHDWAQAMODE] = 1.
Reset type: SYSRSn

7

RESERVED

R=0

0h

Reserved

6

SHDWAQBMODE

R/W

0h

Action Qualifier B Register operating mode
1: Shadow mode - operates as a double buffer. All writes via the
CPU access Shadow register.
0: Immediate mode - only the Active action qualifier register is used.
All writes/reads via the CPU directly access the Active register.
Reset type: SYSRSn

5

RESERVED

R=0

0h

Reserved

4

SHDWAQAMODE

R/W

0h

Action Qualifier A Register operating mode
1: Shadow mode - operates as a double buffer. All writes via the
CPU access Shadow register.
0: Immediate mode - only the Active action qualifier register is used.
All writes/reads via the CPU directly access the Active register.
Reset type: SYSRSn

1784

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-26. AQCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-2

LDAQBMODE

R/W

0h

Active Action Qualifier B Load from Shadow Select Mode
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)
Note: has no effect in Immediate mode.
Reset type: SYSRSn

1-0

LDAQAMODE

R/W

0h

Active Action Qualifier A Load from Shadow Select Mode
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)
Note: has no effect in Immediate mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1785

Registers

www.ti.com

14.14.2.12 AQTSRCSEL Register (Offset = 11h) [reset = 0h]
AQTSRCSEL is shown in Figure 14-88 and described in Table 14-27.
Return to Summary Table.
Action Qualifier Trigger Event Source Select Register
Figure 14-88. AQTSRCSEL Register
15

14

13

12

11

10

3

2

9

8

1

0

RESERVED
R=0-0h
7

6

5

4

T2SEL
R/W-0h

T1SEL
R/W-0h

Table 14-27. AQTSRCSEL Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7-4

T2SEL

R/W

0h

T2 Event Source Select Bits
0000: DCAEVT1
0001: DCAEVT2
0010: DCBEVT1
0011: DCBEVT2
0100: TZ1
0101: TZ2
0110: TZ3
0111: EPWMxSYNCI
1xxx: Reserved
Reset type: SYSRSn

3-0

T1SEL

R/W

0h

T1 Event Source Select Bits
0000: DCAEVT1
0001: DCAEVT2
0010: DCBEVT1
0011: DCBEVT2
0100: TZ1
0101: TZ2
0110: TZ3
0111: EPWMxSYNCI
1xxx: Reserved
Reset type: SYSRSn

1786

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.13 PCCTL Register (Offset = 14h) [reset = 0h]
PCCTL is shown in Figure 14-89 and described in Table 14-28.
Return to Summary Table.
PWM Chopper Control Register
Figure 14-89. PCCTL Register
15

14

13
RESERVED
R=0-0h

12

11

7

6
CHPFREQ
R/W-0h

5

4

3

10

9
CHPDUTY
R/W-0h

8

2

1

0
CHPEN
R/W-0h

OSHTWTH
R/W-0h

Table 14-28. PCCTL Register Field Descriptions
Field

Type

Reset

Description

15-11

Bit

RESERVED

R=0

0h

Reserved

10-8

CHPDUTY

R/W

0h

Chopping Clock Duty Cycle
000: Duty = 1/8 (12.5%)
001: Duty = 2/8 (25.0%)
010: Duty = 3/8 (37.5%)
011: Duty = 4/8 (50.0%)
100: Duty = 5/8 (62.5%)
101: Duty = 6/8 (75.0%)
110: Duty = 7/8 (87.5%)
111: Reserved
Reset type: SYSRSn

7-5

CHPFREQ

R/W

0h

Chopping Clock Frequency
000: Divide by 1 (no prescale, = 12.5 MHz at 100 MHz TBCLK)
001: Divide by 2 (6.25 MHz at 100 MHz TBCLK)
010: Divide by 3 (4.16 MHz at 100 MHz TBCLK)
011: Divide by 4 (3.12 MHz at 100 MHz TBCLK)
100: Divide by 5 (2.50 MHz at 100 MHz TBCLK)
101: Divide by 6 (2.08 MHz at 100 MHz TBCLK)
110: Divide by 7 (1.78 MHz at 100 MHz TBCLK)
111: Divide by 8 (1.56 MHz at 100 MHz TBCLK)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1787

Registers

www.ti.com

Table 14-28. PCCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-1

OSHTWTH

R/W

0h

One-Shot Pulse Width
0000: 1 x EPWMCLK / 8 wide ( = 80 ns at 100 MHz EPWMCLK)
0001: 2 x EPWMCLK / 8 wide ( = 160 ns at 100 MHz EPWMCLK)
0010: 3 x EPWMCLK / 8 wide ( = 240 ns at 100 MHz EPWMCLK)
0011: 4 x EPWMCLK / 8 wide ( = 320 ns at 100 MHz EPWMCLK)
0100: 5 x EPWMCLK / 8 wide ( = 400 ns at 100 MHz EPWMCLK)
0101: 6 x EPWMCLK / 8 wide ( = 480 ns at 100 MHz EPWMCLK)
0110: 7 x EPWMCLK / 8 wide ( = 560 ns at 100 MHz EPWMCLK)
0111: 8 x EPWMCLK / 8 wide ( = 640 ns at 100 MHz EPWMCLK)
1000: 9 x EPWMCLK / 8 wide ( = 720 ns at 100 MHz EPWMCLK)
1001: 10 x EPWMCLK / 8 wide ( = 800 ns at 100 MHz EPWMCLK)
1010: 11 x EPWMCLK / 8 wide ( = 880 ns at 100 MHz EPWMCLK)
1011: 12 x EPWMCLK / 8 wide ( = 960 ns at 100 MHz EPWMCLK)
1100: 13 x EPWMCLK / 8 wide ( = 1040 ns at 100 MHz EPWMCLK)
1101: 14 x EPWMCLK / 8 wide ( = 1120 ns at 100 MHz EPWMCLK)
1110: 15 x EPWMCLK / 8 wide ( = 1200 ns at 100 MHz EPWMCLK)
1111: 16 x EPWMCLK / 8 wide ( = 1280 ns at 100 MHz EPWMCLK)
Reset type: SYSRSn

0

CHPEN

R/W

0h

PWM-Chopping Enable
0: Disable (bypass) PWM chopping function
1: Enable chopping function
Reset type: SYSRSn

1788

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.14 VCAPCTL Register (Offset = 18h) [reset = 0h]
VCAPCTL is shown in Figure 14-90 and described in Table 14-29.
Return to Summary Table.
Valley Capture Control Register
Figure 14-90. VCAPCTL Register
15

14

13
RESERVED

12

11

R=0-0h
7
VDELAYDIV
R/W-0h

6

5

4

RESERVED
R=0-0h

10
EDGEFILTDLY
SEL
R/W-0h

9

2

1
VCAPSTART
R=0/W=1-0h

3
TRIGSEL
R/W-0h

8
VDELAYDIV
R/W-0h
0
VCAPE
R/W-0h

Table 14-29. VCAPCTL Register Field Descriptions
Bit
15-11
10

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

EDGEFILTDLYSEL

R/W

0h

Valley Switching Mode Delay Selection
0: No delay applied to the edge filter output
1: HWDELAYVAL delay applied to the edge filter output
Reset type: SYSRSn

9-7

VDELAYDIV

R/W

0h

Valley Delay Mode Divide Enable
000: HWVDELVAL = SWVDELVAL
001: HWVDELVAL = VCNTVAL+SWVDELVAL
010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL
011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL
100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL
Note: Delay value between the consecutive edge captures can
optionally be divided by using these bits.
Reset type: SYSRSn

6-5

RESERVED

R=0

0h

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Reserved

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1789

Registers

www.ti.com

Table 14-29. VCAPCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-2

TRIGSEL

R/W

0h

Status of Numbered of Captured Events
000: Capture sequence is triggered by software via writes to
VCAPCTL[VCAPSTART].
001: Capture sequence is triggered by CNT_zero event.
010: Capture sequence is triggered by PRD_eq event.
011: Capture sequence is triggered by CNT_zero or PRD_eq event.
100: Capture sequence is triggered by DCAEVT1 event.
101: Capture sequence is triggered by DCAEVT2 event.
110: Capture sequence is triggered by DCBEVT1 event.
111: Capture sequence is triggered by DCBEVT2 event.
Note: Valley capture sequence triggered by the selected event in this
register field. Once the chosen event occurs the capture sequence is
armed. Event captures occur based of the event chosen in
DCFCTL[SRCSEL] register.
Note: Same event may not be chosen in both DCFCTL[SRCSEL]
and VCAPCTL[TRIGSEL] registers.
Note: Once the chosen event in VCAPCTL[TRIGSEL] occurs,
irrespective of the current capture status, capture sequence is
retriggered.
Reset type: SYSRSn

1

VCAPSTART

R=0/W=1

0h

Valley Capture Start
0: Writing a 0 has no effect
1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0
Note: This bit is used to start valley capture sequence through
software. VCAPCTL[TRIGSEL] has to be chosen for software trigger
for this bit to have any effect. Writing of 1 will result in one capture
sequence trigger.
Reset type: SYSRSn

0

VCAPE

R/W

0h

Valley Capture Enable/Disable
0: Disabled
1: Enabled
Reset type: SYSRSn

1790

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.15 VCNTCFG Register (Offset = 19h) [reset = 0h]
VCNTCFG is shown in Figure 14-91 and described in Table 14-30.
Return to Summary Table.
Valley Counter Config Register
Figure 14-91. VCNTCFG Register
15
STOPEDGEST
S
R-0h

14

7
STARTEDGES
TS
R-0h

6

13
RESERVED

12

11

10

9

8

1

0

STOPEDGE

R=0-0h

R/W-0h

5
RESERVED

4

3

2
STARTEDGE

R=0-0h

R/W-0h

Table 14-30. VCNTCFG Register Field Descriptions
Bit

Field

Type

Reset

Description

15

STOPEDGESTS

R

0h

Stop Edge Status Bit
0: Stop edge has not occurred
1: Stop edge occurred
Note: This bit is set only after the trigger sequence is armed (upon
occurrence of trigger pulse selected through VCAPCTL[TRIGSEL])
and STOPEDGE occurs.
Note:This bit is reset by the occurrence of the trigger pulse selected
through VCAPCTL[TRIGSEL]
Reset type: SYSRSn

14-12

RESERVED

R=0

0h

Reserved

11-8

STOPEDGE

R/W

0h

Counter Stop Edge Selection
Once the counter operation is armed, upon occurrence of trigger
pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter
would stop counting upon the occurrence of chosen number of
events thorough this bit field. Stop counting on occurrence of:
0000: Do not stop
0001
1st edge
0010: 2nd edge
0011: 3rd edge
...
1,1,1,1: 15th edge
Reset type: SYSRSn

7

STARTEDGESTS

R

0h

Start Edge Status Bit
0: Start edge has not occurred
1: Start edge occurred
Note: This bit is set only after the trigger sequence is armed (upon
occurrence of trigger pulse selected through VCAPCTL[TRIGSEL])
and STARTEDGE occurs.
Note:This bit is reset by the occurrence of the trigger pulse selected
through VCAPCTL[TRIGSEL]
Reset type: SYSRSn

6-4

RESERVED

R=0

0h

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Reserved

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1791

Registers

www.ti.com

Table 14-30. VCNTCFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

STARTEDGE

R/W

0h

Counter Start Edge Selection
Once the counter operation is armed, upon occurrence of trigger
pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter
would start counting upon the occurrence of chosen number of
events thorough this bit field. Start counting on occurrence of
0000: Do not start
0001: 1st edge
0010: 2nd edge
0011: 3rd edge
...
1111: 15th edge
Reset type: SYSRSn

1792

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.16 HRCNFG Register (Offset = 20h) [reset = 0h]
HRCNFG is shown in Figure 14-92 and described in Table 14-31.
Return to Summary Table.
HRPWM Configuration Register
This register is only accessible on EPWM modules with HRPWM capabilities.
Figure 14-92. HRCNFG Register
15

14
RESERVED
R-0h

7
SWAPAB
R/W-0h

6
AUTOCONV
R/W-0h

13
RESERVED
R=0-0h

12

5
SELOUTB
R/W-0h

4

11
HRLOADB
R/W-0h
3
HRLOAD
R/W-0h

10
CTLMODEB
R/W-0h

9

2
CTLMODE
R/W-0h

1

8
EDGMODEB
R/W-0h
0
EDGMODE
R/W-0h

Table 14-31. HRCNFG Register Field Descriptions
Field

Type

Reset

Description

15-14

Bit

RESERVED

R

0h

Reserved

13

RESERVED

R=0

0h

Reserved

HRLOADB

R/W

0h

Shadow Mode Bit

12-11

Selects the time event that loads the CMPBHR shadow value into
the active register.
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Reserved
Reset type: SYSRSn
10

CTLMODEB

R/W

0h

Control Mode Bits
Selects the register (CMP/TBPRD or TBPHS) that controls the MEP:
0: CMPBHR(8) or TBPRDHR(8) Register controls the edge position
(i.e., this is duty or period control mode). (Default on Reset)
1: TBPHSHR(8) Register controls the edge position (i.e., this is
phase control mode).
Reset type: SYSRSn

9-8

EDGMODEB

R/W

0h

Edge Mode Bits
Selects the edge of the PWM that is controlled by the micro-edge
position (MEP) logic:
00: HRPWM capability is disabled (default on reset)
01: MEP control of rising edge (CMPBHR)
10: MEP control of falling edge (CMPBHR)
11: MEP control of both edges (TBPHSHR or TBPRDHR)
Reset type: SYSRSn

7

SWAPAB

R/W

0h

Swap ePWM A & B Output Signals
This bit enables the swapping of the A & B signal outputs. The
selection is as follows:
0: ePWMxA and ePWMxB outputs are unchanged.
1: ePWMxA signal appears on ePWMxB output and ePWMxB signal
appears on ePWMxA output.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1793

Registers

www.ti.com

Table 14-31. HRCNFG Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

AUTOCONV

R/W

0h

Auto Convert Delay Line Value
Selects whether the fractional duty cycle/period/phase in the
CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by
the MEP scale factor in the HRMSTEP register or manually scaled
by calculations in application software. The SFO library function
automatically updates the HRMSTEP register with the appropriate
MEP scale factor.
0: Automatic HRMSTEP scaling is disabled.
1: Automatic HRMSTEP scaling is enabled.
If application software is manually scaling the fractional duty cycle, or
phase (i.e. software sets CMPAHR = (fraction(PWMduty *
PWMperiod) * MEP Scale Factor)<<8 + 0x080 for duty cycle), then
this mode must be disabled.
Reset type: SYSRSn

5

SELOUTB

R/W

0h

EPWMxB Output Select Bit
This bit selects which signal is output on the ePWMxB channel
output.
0: ePWMxB output is normal.
1: ePWMxB output is inverted version of ePWMxA signal.
Reset type: SYSRSn

4-3

HRLOAD

R/W

0h

Shadow Mode Bit
Selects the time event that loads the CMPAHR shadow value into
the active register.
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Reserved
Reset type: SYSRSn

2

CTLMODE

R/W

0h

Control Mode Bits
Selects the register (CMP/TBPRD or TBPHS) that controls the MEP:
0: CMPAHR(8) or TBPRDHR(8) Register controls the edge position
(i.e., this is duty or period control mode). (Default on Reset)
1: TBPHSHR(8) Register controls the edge position (i.e., this is
phase control mode).
Reset type: SYSRSn

1-0

EDGMODE

R/W

0h

Edge Mode Bits
Selects the edge of the PWM that is controlled by the micro-edge
position (MEP) logic:
00: HRPWM capability is disabled (default on reset)
01: MEP control of rising edge (CMPAHR)
10: MEP control of falling edge (CMPAHR)
11: MEP control of both edges (TBPHSHR or TBPRDHR)
Reset type: SYSRSn

1794

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.17 HRPWR Register (Offset = 21h) [reset = 0h]
HRPWR is shown in Figure 14-93 and described in Table 14-32.
Return to Summary Table.
HRPWM Power Register
This register is only accessible on EPWM modules with HRPWM capabilities.
Figure 14-93. HRPWR Register
15
CALPWRON
R/W-0h

14

7

6
RESERVED
R-0h

13

5
RESERVED
R-0h

12
RESERVED
R=0-0h

11

4
RESERVED
R-0h

3
RESERVED
R-0h

10

9

8
RESERVED
R-0h

2
RESERVED
R-0h

1

0
RESERVED
R-0h

Table 14-32. HRPWR Register Field Descriptions
Bit

Field

Type

Reset

Description

15

CALPWRON

R/W

0h

MEP Calibration Power Bits
0: Disables MEP calibration logic in the HRPWM and reduces power
consumption.
1: Enables MEP calibration logic
Reset type: SYSRSn

14-10

RESERVED

R=0

0h

Reserved

9-6

RESERVED

R

0h

Reserved

5

RESERVED

R

0h

Reserved

4

RESERVED

R

0h

Reserved

3

RESERVED

R

0h

Reserved

2

RESERVED

R

0h

Reserved

1-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1795

Registers

www.ti.com

14.14.2.18 HRMSTEP Register (Offset = 26h) [reset = 0h]
HRMSTEP is shown in Figure 14-94 and described in Table 14-33.
Return to Summary Table.
HRPWM MEP Step Register
This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are
allowed for this register. Debugger access in 32 bit mode may display incorrect values.
Figure 14-94. HRMSTEP Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R=0-0h
7

6

5

4
HRMSTEP
R/W-0h

Table 14-33. HRMSTEP Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7-0

HRMSTEP

R/W

0h

High Resolution MEP Step
When auto-conversion is enabled (HRCNFG[AUTOCONV] = 1), This
8-bit field contains the MEP_ScaleFactor (number of MEP steps per
coarse steps) used by the hardware to automatically convert the
value in the CMPAHR, CMPBHR, DBFEDHR, DBREDHR ,
TBPHSHR, or TBPRDHR register to a scaled micro-edge delay on
the high-resolution ePWM output. The value in this register is written
by the SFO calibration software at the end of each calibration run.
Reset type: SYSRSn

1796

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.19 HRCNFG2 Register (Offset = 27h) [reset = 0h]
HRCNFG2 is shown in Figure 14-95 and described in Table 14-34.
Return to Summary Table.
HRPWM Configuration 2 Register
This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are
allowed for this register. Debugger access in 32 bit mode may display incorrect values.
Figure 14-95. HRCNFG2 Register
15
RESERVED
R-0h

14
RESERVED
R-0h

7

6
RESERVED
R=0-0h

13

12

11

10

9

3
2
CTLMODEDBRED
R/W-0h

1

8

RESERVED
R=0-0h
5
4
CTLMODEDBFED
R/W-0h

0
EDGMODEDB
R/W-0h

Table 14-34. HRCNFG2 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

RESERVED

R

0h

Reserved

13-6

RESERVED

R=0

0h

Reserved

5-4

CTLMODEDBFED

R/W

0h

Shadow Mode Bit - selection should match
DBCTL[LOADFEDMODE]
Selects the time event that loads the DBFEDHR shadow value into
the active register.
00 Load on CTR = Zero: Time-base counter equal to zero (TBCTR =
0x0000)
01 Load on CTR = PRD: Time-base counter equal to period (TBCTR
= TBPRD)
10 Load on either CTR = Zero or CTR = PRD
11 Reserved
Reset type: SYSRSn

3-2

CTLMODEDBRED

R/W

0h

Shadow Mode Bit - selection should match
DBCTL[LOADREDMODE]
Selects the time event that loads the DBREDHR shadow value into
the active register.
00 Load on CTR = Zero: Time-base counter equal to zero (TBCTR =
0x0000)
01 Load on CTR = PRD: Time-base counter equal to period (TBCTR
= TBPRD)
10 Load on either CTR = Zero or CTR = PRD
11 Reserved
Reset type: SYSRSn

1-0

EDGMODEDB

R/W

0h

Edge Mode Bits
Selects the edge of the PWM that is controlled by the micro-edge
position (MEP) logic:
00 HRPWM capability is disabled (default on reset)
01 MEP control of rising edge (DBREDHR)
10 MEP control of falling edge (DBFEDHR)
11 MEP control of both edges (rising edge of DBREDHR or falling
edge of DBFEDHR )
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1797

Registers

www.ti.com

14.14.2.20 HRPCTL Register (Offset = 2Dh) [reset = 0h]
HRPCTL is shown in Figure 14-96 and described in Table 14-35.
Return to Summary Table.
High Resolution Period Control Register
This register is only accessible on EPWM modules with HRPWM capabilities.
Figure 14-96. HRPCTL Register
15

14

13

12

11

10

9

8

RESERVED
R=0-0h
7
RESERVED

6

R=0-0h

5
PWMSYNCSELX

4

R/W-0h

3
RESERVED
R-0h

2
1
TBPHSHRLOA PWMSYNCSEL
DE
R/W-0h
R/W-0h

0
HRPE
R/W-0h

Table 14-35. HRPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15-7

RESERVED

R=0

0h

Reserved

6-4

PWMSYNCSELX

R/W

0h

PWMSYNCX Source Select Bit
000: PWMSYNC is defined by PWMSYNCSEL - > default condition
(compatible with previous EPWM versions)
001: Reserved
010: Reserved
011: Reserved
100: PWMSYNC = CMPC_eq, Count direction Up
101: PWMSYNC = CMPC_eq, Count direction Down
110: PWMSYNC = CMPD_eq, Count direction Up
111: PWMSYNC = CMPD_eq, Count direction Down
Reset type: SYSRSn

3

RESERVED

R

0h

Reserved

2

TBPHSHRLOADE

R/W

0h

TBPHSHR Load Enable
This bit allows you to synchronize ePWM modules with a highresolution phase on a SYNCIN, TBCTL[SWFSYNC] or digital
compare event. This allows for multiple ePWM modules operating at
the same frequency to be phase aligned with high-resolution.
0: Disables synchronization of high-resolution phase on a SYNCIN,
TBCTL[SWFSYNC] or digital compare event:
1: Synchronize the high-resolution phase on a SYNCIN,
TBCTL[SWFSYNC] or digital comparator synchronization event. The
phase is synchronized using the contents of the high-resolution
phase TBPHSHR register. The TBCTL[PHSEN] bit which enables
the loading of the TBCTR register with TBPHS register value on a
SYNCIN or TBCTL[SWFSYNC] event works independently.
However, users need to enable this bit also if they want to control
phase in conjunction with the high-resolution period feature.
This bit and the TBCTL[PHSEN] bit must be set to 1 when highresolution period is enabled for up-down count mode even if
TBPHSHR = 0x0000. This bit does not need to be set when only
high-resolution duty is enabled.
Reset type: SYSRSn

1798

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-35. HRPCTL Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

PWMSYNCSEL

R/W

0h

PWMSYNC Source Select Bit: This bit selects the source for the
PWMSYNC signal. The PWMSYNC signal is used by external
modules (such as COMP+DAC) for syncing timing to the selected
EPWM mdoule:
0 PWMSYNC = PRD_eq signal pulse
1 PWMSYNC = CNT_zero signal pulse
Reset type: SYSRSn

0

HRPE

R/W

0h

High Resolution Period Enable Bit
0: High resolution period feature disabled. In this mode the ePWM
behaves as a Type 0 ePWM.
1: High resolution period enabled. In this mode the HRPWM module
can control high-resolution of both the duty and frequency. When
high-resolution period is enabled, TBCTL[CTRMODE] = 0,1 (downcount mode) is not supported.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1799

Registers

www.ti.com

14.14.2.21 TRREM Register (Offset = 2Eh) [reset = 0h]
TRREM is shown in Figure 14-97 and described in Table 14-36.
Return to Summary Table.
Translator High Resolution Remainder Register
This register is only accessible on EPWM modules with HRPWM capabilities.
Figure 14-97. TRREM Register
15

14

13
RESERVED
R=0-0h

12

7

6

5

4

11

10

9
TRREM
R/W-0h

8

3

2

1

0

TRREM
R/W-0h

Table 14-36. TRREM Register Field Descriptions
Field

Type

Reset

Description

15-11

Bit

RESERVED

R=0

0h

Reserved

10-0

TRREM

R/W

0h

Translator Remainder Bits: This 11-bit value keeps track of the
remainder portion of the translator algorithm calculations.
Reset type: SYSRSn

1800

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.22 GLDCTL Register (Offset = 34h) [reset = 0h]
GLDCTL is shown in Figure 14-98 and described in Table 14-37.
Return to Summary Table.
Global PWM Load Control Register
Figure 14-98. GLDCTL Register
15

7
GLDPRD
R/W-0h

14
RESERVED
R=0-0h

13

12

6
RESERVED
R=0-0h

5
OSHTMODE
R/W-0h

4

11
GLDCNT
R-0h

10

3

2

9

8
GLDPRD
R/W-0h

1

GLDMODE
R/W-0h

0
GLD
R/W-0h

Table 14-37. GLDCTL Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

RESERVED

R=0

0h

Reserved

12-10

GLDCNT

R

0h

Global Reload Strobe Counter Register
These bits indicate how many selected events have occurred:
000: No events
001: 1 event
010: 2 events
011: 3 events
100: 4 events
101: 5 events
110: 6 events
111: 7 events
Reset type: SYSRSn

9-7

GLDPRD

R/W

0h

Global Reload Strobe Period Select Register
These bits select how many selected events need to occur before a
load strobe is generated
000: Disable counter
001: Generate strobe on GLDCNT = 001 (1st event)
010: Generate strobe on GLDCNT = 010 (2nd event)
011: Generate strobe on GLDCNT = 011 (3rd event)
100: Generate strobe on GLDCNT = 011 (4th event)
101: Generate strobe on GLDCNT = 001 (5th event)
110: Generate strobe on GLDCNT = 010 (6th event)
111: Generate strobe on GLDCNT = 011 (7th event)
Reset type: SYSRSn

6

RESERVED

R=0

0h

Reserved

5

OSHTMODE

R/W

0h

One Shot Load Mode Control Bit
0: One shot load mode is disabled and shadow to active loading
happens continuously on all the chosen load strobes.
1: One shot mode is active. All load strobes are blocked until
GLDCTL2[OSHTLD] is written with 1.
Note: One Shot mode can only be used with global shadow to active
load mode enabled (GLDCTL[GLD]=1)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1801

Registers

www.ti.com

Table 14-37. GLDCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-1

GLDMODE

R/W

0h

Global Load Pulse selection for Shadow to Active Mode Reloads
0000: Load on Counter = 0 (CNT_ZRO)
0001: Load on Counter = Period (PRD_EQ)
0010: Load on either Counter = 0, or Counter = Period
0011: Load on SYNCEVT - this is logical OR of DCAEVT1.sync,
DCBEVT1.sync, EPWMxSYNCI and TBCTL[SWFSYNC]
0100: Load on SYNCEVT or CNT_ZRO
0101: Load on SYNCEVT or PRD_EQ
0110: Load on SYNCEVT or CNT_ZRO or PRD_EQ
1000: Reserved
...
1110: Reserved
1111: Load on GLDCTL[GLDFRCLD] write
Reset type: SYSRSn

0

GLD

R/W

0h

Global Shadow to Active Load Event Control
0: Shadow to active reload for all shadowed registers happens as
per the individual reload control bits specified (Compatible with
previous EPWM versions).
1: When set, all the shadow to active reload events are defined by
GLDMODE bits in GLDCTL register. All the shadow registers use
same reload pulse from shadow to active reloading. Individual
LOADMODE bits are ignored.
Reset type: SYSRSn

1802

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.23 GLDCFG Register (Offset = 35h) [reset = 0h]
GLDCFG is shown in Figure 14-99 and described in Table 14-38.
Return to Summary Table.
Global PWM Load Config Register
Figure 14-99. GLDCFG Register
15

14

13
RESERVED

12

11

R=0-0h
7
DBCTL
R/W-0h

6
DBFED_DBFE
DHR
R/W-0h

10
AQCSFRC

9
AQCTLB_AQC
TLB2
R/W-0h

8
AQCTLA_AQC
TLA2
R/W-0h

2
1
CMPB_CMPBH CMPA_CMPAH
R
R
R/W-0h
R/W-0h

0
TBPRD_TBPR
DHR
R/W-0h

R/W-0h

5
DBRED_DBRE
DHR
R/W-0h

4
CMPD

3
CMPC

R/W-0h

R/W-0h

Table 14-38. GLDCFG Register Field Descriptions
Bit
15-11
10

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

AQCSFRC

R/W

0h

Global load event configuration for AQCSFRC
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

9

AQCTLB_AQCTLB2

R/W

0h

Global load event configuration for AQCTLB_AQCTLB2
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

8

AQCTLA_AQCTLA2

R/W

0h

Global load event configuration for AQCTLA_AQCTLA2
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

7

DBCTL

R/W

0h

Global load event configuration for DBCTL
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

6

DBFED_DBFEDHR

R/W

0h

Global load event configuration for DBFED_DBFEDHR
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1803

Registers

www.ti.com

Table 14-38. GLDCFG Register Field Descriptions (continued)
Bit
5

Field

Type

Reset

Description

DBRED_DBREDHR

R/W

0h

Global load event configuration for DBRED_DBREDHR
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

4

CMPD

R/W

0h

Global load event configuration for CMPD
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

3

CMPC

R/W

0h

Global load event configuration for CMPC
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

2

CMPB_CMPBHR

R/W

0h

Global load event configuration for CMPB_CMPBHR
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

1

CMPA_CMPAHR

R/W

0h

Global load event configuration for CMPA_CMPAHR
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

0

TBPRD_TBPRDHR

R/W

0h

Global load event configuration for TBPRD_TBPRDHR
0: Registers use local reload configuration even if GLDCTL(GLD)=1
(reload is compatible with previous EPWMs)
1: Registers use global reload configuration if this bit is set and
GLDCTL(GLD)=1
Reset type: SYSRSn

1804

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.24 EPWMXLINK Register (Offset = 38h) [reset = X]
EPWMXLINK is shown in Figure 14-100 and described in Table 14-39.
Return to Summary Table.
EPWMx Link Register
This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary
for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of
modules.
Figure 14-100. EPWMXLINK Register
31

30
29
GLDCTL2LINK
R/W-X

28

27

26

25

15

14
13
CMPCLINK
R/W-X

12

11

10
9
CMPBLINK
R/W-X

24
23
RESERVED
R=0-0h
8

7

22

21

20

19

18
17
CMPDLINK
R/W-X

16

6
5
CMPALINK
R/W-X

4

3

2
1
TBPRDLINK
R/W-X

0

Table 14-39. EPWMXLINK Register Field Descriptions
Bit
31-28

Field

Type

Reset

Description

GLDCTL2LINK

R/W

X

GLDCTL2 Link Bits
Writes to the GLDCTL2 registers in the ePWM module selected by
the following bit selections results in a simultaneous write to the
current ePWM module's GLDCTL2 registers.
0000: ePWM1
0001: ePWM2
0010: ePWM3
0011: ePWM4
0100: ePWM5
0101: ePWM6
0110: ePWM7
0111: ePWM8
1000: ePWM9
1001: ePWM10
1010: ePWM11
1011: ePWM12
1100: Reserved
...
1111: Reserved
Reset type: SYSRSn

27-20

RESERVED

R=0

0h

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Reserved

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1805

Registers

www.ti.com

Table 14-39. EPWMXLINK Register Field Descriptions (continued)
Bit
19-16

Field

Type

Reset

Description

CMPDLINK

R/W

X

CMPD Link Bits
Writes to the CMPD registers in the ePWM module selected by the
following bit selections results in a simultaneous write to the current
ePWM module's CMPD registers.
0000: ePWM1
0001: ePWM2
0010: ePWM3
0011: ePWM4
0100: ePWM5
0101: ePWM6
0110: ePWM7
0111: ePWM8
1000: ePWM9
1001: ePWM10
1010: ePWM11
1011: ePWM12
1100: Reserved
...
1111: Reserved
Reset type: SYSRSn

15-12

CMPCLINK

R/W

X

CMPC Link Bits
Writes to the CMPC registers in the ePWM module selected by the
following bit selections results in a simultaneous write to the current
ePWM module's CMPC registers.
0000: ePWM1
0001: ePWM2
0010: ePWM3
0011: ePWM4
0100: ePWM5
0101: ePWM6
0110: ePWM7
0111: ePWM8
1000: ePWM9
1001: ePWM10
1010: ePWM11
1011: ePWM12
1100: Reserved
...
1111: Reserved
Reset type: SYSRSn

1806

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-39. EPWMXLINK Register Field Descriptions (continued)
Bit
11-8

Field

Type

Reset

Description

CMPBLINK

R/W

X

CMPB_CMPBHR Link Bits
Writes to the CMPB_CMPBHR registers in the ePWM module
selected by the following bit selections results in a simultaneous
write to the current ePWM module's CMPB_CMPBHR registers.
0000: ePWM1
0001: ePWM2
0010: ePWM3
0011: ePWM4
0100: ePWM5
0101: ePWM6
0110: ePWM7
0111: ePWM8
1000: ePWM9
1001: ePWM10
1010: ePWM11
1011: ePWM12
1100: Reserved
...
1111: Reserved
Reset type: SYSRSn

7-4

CMPALINK

R/W

X

CMPA_CMPAHR Link Bits
Writes to the CMPA_CMPAHR registers in the ePWM module
selected by the following bit selections results in a simultaneous
write to the current ePWM module's CMPA_CMPAHR registers.
0000: ePWM1
0001: ePWM2
0010: ePWM3
0011: ePWM4
0100: ePWM5
0101: ePWM6
0110: ePWM7
0111: ePWM8
1000: ePWM9
1001: ePWM10
1010: ePWM11
1011: ePWM12
1100: Reserved
...
1111: Reserved
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1807

Registers

www.ti.com

Table 14-39. EPWMXLINK Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

TBPRDLINK

R/W

X

TBPRD_TBPRDHR Link Bits
Writes to the TBPRD:TBPRDHR registers in the ePWM module
selected by the following bit selections results in a simultaneous
write to the current ePWM module's TBPRD_TBPRDHR registers.
0000: ePWM1
0001: ePWM2
0010: ePWM3
0011: ePWM4
0100: ePWM5
0101: ePWM6
0110: ePWM7
0111: ePWM8
1000: ePWM9
1001: ePWM10
1010: ePWM11
1011: ePWM12
1100: Reserved
...
1111: Reserved
Reset type: SYSRSn

1808

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.25 EPWMREV Register (Offset = 3Eh) [reset = X]
EPWMREV is shown in Figure 14-101 and described in Table 14-40.
Return to Summary Table.
EPWM Revision Register
Figure 14-101. EPWMREV Register
15

14

13

12

11

10

9

8

3

2

1

0

TYPE
R-4h
7

6

5

4
REV
R-X

Table 14-40. EPWMREV Register Field Descriptions
Bit

Field

Type

Reset

Description

15-8

TYPE

R

4h

EPWM Type Bits: These bits specify the EPWM type. These bits are
changed if the functionality of the EPWM is changed or any feature
is added or removed:
Reset type: SYSRSn

7-0

REV

R

X

EPWM Silicon Revision Bits: These bits specify the EPWM revision.
These bits are changed if any bug fixes are performed:
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1809

Registers

www.ti.com

14.14.2.26 AQCTLA Register (Offset = 40h) [reset = 0h]
AQCTLA is shown in Figure 14-102 and described in Table 14-41.
Return to Summary Table.
Action Qualifier Control Register For Output A
Figure 14-102. AQCTLA Register
15

14

13

12

11

10

RESERVED
R=0-0h
7

6

9

CBD
R/W-0h
5

4

CAD
R/W-0h

3

2

CAU
R/W-0h

8
CBU
R/W-0h

1

PRD
R/W-0h

0
ZRO
R/W-0h

Table 14-41. AQCTLA Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R=0

0h

Reserved

11-10

CBD

R/W

0h

Action When TBCTR = CMPB on Down Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

9-8

CBU

R/W

0h

Action When TBCTR = CMPB on Up Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

7-6

CAD

R/W

0h

Action When TBCTR = CMPA on Down Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

1810

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-41. AQCTLA Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-4

CAU

R/W

0h

Action When TBCTR = CMPA on Up Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

3-2

PRD

R/W

0h

Action When TBCTR = TBPRD
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

1-0

ZRO

R/W

0h

Action When TBCTR = 0
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1811

Registers

www.ti.com

14.14.2.27 AQCTLA2 Register (Offset = 41h) [reset = 0h]
AQCTLA2 is shown in Figure 14-103 and described in Table 14-42.
Return to Summary Table.
Additional Action Qualifier Control Register For Output A
Figure 14-103. AQCTLA2 Register
15

14

13

12

11

10

9

2

1

8

RESERVED
R=0-0h
7

6

5

4

T2D
R/W-0h

3

T2U
R/W-0h

T1D
R/W-0h

0
T1U
R/W-0h

Table 14-42. AQCTLA2 Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7-6

T2D

R/W

0h

Action when event occurs on T2 in DOWN-Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

5-4

T2U

R/W

0h

Action when event occurs on T2 in UP-Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

3-2

T1D

R/W

0h

Action when event occurs on T1 in DOWN-Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

1812

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-42. AQCTLA2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

T1U

R/W

0h

Action when event occurs on T1 in UP-Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1813

Registers

www.ti.com

14.14.2.28 AQCTLB Register (Offset = 42h) [reset = 0h]
AQCTLB is shown in Figure 14-104 and described in Table 14-43.
Return to Summary Table.
Action Qualifier Control Register For Output B
Figure 14-104. AQCTLB Register
15

14

13

12

11

10

RESERVED
R=0-0h
7

6

9

CBD
R/W-0h
5

4

CAD
R/W-0h

3

2

CAU
R/W-0h

8
CBU
R/W-0h

1

PRD
R/W-0h

0
ZRO
R/W-0h

Table 14-43. AQCTLB Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R=0

0h

Reserved

11-10

CBD

R/W

0h

Action When TBCTR = CMPB on Down Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

9-8

CBU

R/W

0h

Action When TBCTR = CMPB on Up Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

7-6

CAD

R/W

0h

Action When TBCTR = CMPA on Down Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

1814

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-43. AQCTLB Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-4

CAU

R/W

0h

Action When TBCTR = CMPA on Up Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

3-2

PRD

R/W

0h

Action When TBCTR = TBPRD
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

1-0

ZRO

R/W

0h

Action When TBCTR = 0
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1815

Registers

www.ti.com

14.14.2.29 AQCTLB2 Register (Offset = 43h) [reset = 0h]
AQCTLB2 is shown in Figure 14-105 and described in Table 14-44.
Return to Summary Table.
Additional Action Qualifier Control Register For Output B
Figure 14-105. AQCTLB2 Register
15

14

13

12

11

10

9

2

1

8

RESERVED
R=0-0h
7

6

5

4

T2D
R/W-0h

3

T2U
R/W-0h

T1D
R/W-0h

0
T1U
R/W-0h

Table 14-44. AQCTLB2 Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7-6

T2D

R/W

0h

Action when event occurs on T2 in DOWN-Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

5-4

T2U

R/W

0h

Action when event occurs on T2 in UP-Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

3-2

T1D

R/W

0h

Action when event occurs on T1 in DOWN-Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

1816

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-44. AQCTLB2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

T1U

R/W

0h

Action when event occurs on T1 in UP-Count
Note: By definition, in count up-down mode when the counter equals
0 the direction is defined as 1 or counting up.
00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high,
and a high signal will be forced low.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1817

Registers

www.ti.com

14.14.2.30 AQSFRC Register (Offset = 47h) [reset = 0h]
AQSFRC is shown in Figure 14-106 and described in Table 14-45.
Return to Summary Table.
Action Qualifier Software Force Register
Figure 14-106. AQSFRC Register
15

14

13

12

11

10

9

3

2
OTSFA
R=0/W=1-0h

1

8

RESERVED
R=0-0h
7

6
RLDCSF
R/W-0h

5
OTSFB
R=0/W=1-0h

4
ACTSFB
R/W-0h

0
ACTSFA
R/W-0h

Table 14-45. AQSFRC Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7-6

RLDCSF

R/W

0h

AQCSFRC Active Register Reload From Shadow Options
00: Load on event counter equals zero
01: Load on event counter equals period
10: Load on event counter equals zero or counter equals period
11: Load immediately (the active register is directly accessed by the
CPU and is not loaded from the shadow register).
Reset type: SYSRSn

5

OTSFB

R=0/W=1

0h

One-Time Software Forced Event on Output B
0: Writing a 0 (zero) has no effect. Always reads back a 0. This bit is
auto cleared once a write to this register is complete (i.e., a forced
event is initiated.). This is a one-shot forced event. It can be
overridden by another subsequent event on output B.
1: Initiates a single software forced event
Reset type: SYSRSn

4-3

ACTSFB

R/W

0h

Action When One-Time Software Force B is Invoked
00: Does nothing (action disabled)
01: Clear (low)
10: Set (high)
11: Toggle (Low -> High, High -> Low)
Note: This action is not qualified by counter direction (CNT_dir)
Reset type: SYSRSn

2

OTSFA

R=0/W=1

0h

One-Time Software Forced Event on Output A
0: Writing a 0 (zero) has no effect. Always reads back a 0. This bit is
auto cleared once a write to this register is complete ( i.e., a forced
event is initiated). This is a one-shot forced event. It can be
overridden by another subsequent event on output A.
1: Initiates a single software forced event
Reset type: SYSRSn

1818

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-45. AQSFRC Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

ACTSFA

R/W

0h

Action When One-Time Software Force A Is Invoked
00: Does nothing (action disabled)
01: Clear (low)
10: Set (high)
11: Toggle (Low -> High, High -> Low)
Note: This action is not qualified by counter direction (CNT_dir)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1819

Registers

www.ti.com

14.14.2.31 AQCSFRC Register (Offset = 49h) [reset = 0h]
AQCSFRC is shown in Figure 14-107 and described in Table 14-46.
Return to Summary Table.
Action Qualifier Continuous S/W Force Register
Figure 14-107. AQCSFRC Register
15

14

13

12

11

10

9

2

1

8

RESERVED
R=0-0h
7

6

5

4

3

RESERVED
R=0-0h

CSFB
R/W-0h

0
CSFA
R/W-0h

Table 14-46. AQCSFRC Register Field Descriptions
Field

Type

Reset

Description

15-4

Bit

RESERVED

R=0

0h

Reserved

3-2

CSFB

R/W

0h

Continuous Software Force on Output B
In immediate mode, a continuous force takes effect on the next
TBCLK edge. In shadow mode, a continuous force takes effect on
the next TBCLK edge after a shadow load into the active register. To
configure shadow mode, use AQSFRC[RLDCSF].
00: Software forcing is disabled and has no effect
01: Forces a continuous low on output B
10: Forces a continuous high on output B
11: Software forcing is disabled and has no effect
Reset type: SYSRSn

1-0

CSFA

R/W

0h

Continuous Software Force on Output A
In immediate mode, a continuous force takes effect on the next
TBCLK edge. In shadow mode, a continuous force takes effect on
the next TBCLK edge after a shadow load into the active register.
00: Software forcing is disabled and has no effect
01: Forces a continuous low on output A
10: Forces a continuous high on output A
11: Software forcing is disabled and has no effect
Reset type: SYSRSn

1820

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.32 DBREDHR Register (Offset = 50h) [reset = 0h]
DBREDHR is shown in Figure 14-108 and described in Table 14-47.
Return to Summary Table.
Dead-Band Generator Rising Edge Delay High Resolution Mirror Register
Figure 14-108. DBREDHR Register
15

14

13

12
DBREDHR
R/W-0h

11

10

9

8
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

3

2

1

0
RESERVED
R-0h

Table 14-47. DBREDHR Register Field Descriptions
Field

Type

Reset

Description

15-9

Bit

DBREDHR

R/W

0h

Dead Band Rising Edge Delay High Resolution Bits
Reset type: SYSRSn

8

RESERVED

R

0h

Reserved

7-1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1821

Registers

www.ti.com

14.14.2.33 DBRED Register (Offset = 51h) [reset = 0h]
DBRED is shown in Figure 14-109 and described in Table 14-48.
Return to Summary Table.
Dead-Band Generator Rising Edge Delay High Resolution Mirror Register
Figure 14-109. DBRED Register
15

14

13

12

11

RESERVED
R-0h
7

10

9

8

2

1

0

DBRED
R/W-0h
6

5

4

3
DBRED
R/W-0h

Table 14-48. DBRED Register Field Descriptions
Field

Type

Reset

Description

15-14

Bit

RESERVED

R

0h

Reserved

13-0

DBRED

R/W

0h

Rising edge delay value
Reset type: SYSRSn

1822

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.34 DBFEDHR Register (Offset = 52h) [reset = 0h]
DBFEDHR is shown in Figure 14-110 and described in Table 14-49.
Return to Summary Table.
Dead-Band Generator Falling Edge Delay High Resolution Register
Figure 14-110. DBFEDHR Register
15

14

13

12
DBFEDHR
R/W-0h

11

10

9

8
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

3

2

1

0
RESERVED
R-0h

Table 14-49. DBFEDHR Register Field Descriptions
Bit

Field

Type

Reset

Description

DBFEDHR

R/W

0h

Dead Band Falling Edge Delay High Resolution Bits
Reset type: SYSRSn

8

RESERVED

R

0h

Reserved

7-1

RESERVED

R

0h

Reserved

0

RESERVED

R

0h

Reserved

15-9

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1823

Registers

www.ti.com

14.14.2.35 DBFED Register (Offset = 53h) [reset = 0h]
DBFED is shown in Figure 14-111 and described in Table 14-50.
Return to Summary Table.
Dead-Band Generator Falling Edge Delay Count Register
Figure 14-111. DBFED Register
15

14

13

12

11

RESERVED
R-0h
7

10

9

8

2

1

0

DBFED
R/W-0h
6

5

4

3
DBFED
R/W-0h

Table 14-50. DBFED Register Field Descriptions
Field

Type

Reset

Description

15-14

Bit

RESERVED

R

0h

Reserved

13-0

DBFED

R/W

0h

Falling Edge Delay Count
14-bit counter
Reset type: SYSRSn

1824

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.36 TBPHS Register (Offset = 60h) [reset = 0h]
TBPHS is shown in Figure 14-112 and described in Table 14-51.
Return to Summary Table.
Time Base Phase High
Figure 14-112. TBPHS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TBPHS
R/W-0h

9

8 7 6
TBPHSHR
R/W-0h

5

4

3

2

1

0

Table 14-51. TBPHS Register Field Descriptions
Bit
31-16

Field

Type

Reset

Description

TBPHS

R/W

0h

Phase Offset Register
These bits set time-base counter phase of the selected ePWM
relative to the time-base that is supplying the synchronization input
signal.
- If TBCTL[PHSEN] = 0, then the synchronization event is ignored
and the time-base counter is not loaded with the phase.
- If TBCTL[PHSEN] = 1, then the time-base counter (TBCTR) will be
loaded with the phase (TBPHS) when a synchronization event
occurs. The synchronization event can be initiated by the input
synchronization signal (EPWMxSYNCI) or by a software forced
synchronization.
Reset type: SYSRSn

15-0

TBPHSHR

R/W

0h

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Phase Offset (High Resolution) Register
Reset type: SYSRSn

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1825

Registers

www.ti.com

14.14.2.37 TBPRDHR Register (Offset = 62h) [reset = 0h]
TBPRDHR is shown in Figure 14-113 and described in Table 14-52.
Return to Summary Table.
Time Base Period High Resolution Register
Figure 14-113. TBPRDHR Register
15

14

13

12

11

10

9

8
7
TBPRDHR
R/W-0h

6

5

4

3

2

1

0

Table 14-52. TBPRDHR Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

TBPRDHR

R/W

0h

Period High Resolution Bits
These 8-bits contain the high-resolution portion of the period value.
The TBPRDHR register is not affected by the TBCTL[PRDLD] bit.
Reads from this register always reflect the shadow register. Likewise
writes are also to the shadow register. The TBPRDHR register is
only used when the high resolution period feature is enabled. This
register is only available with ePWM modules which support highresolution period control.
Reset type: SYSRSn

1826

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.38 TBPRD Register (Offset = 63h) [reset = 0h]
TBPRD is shown in Figure 14-114 and described in Table 14-53.
Return to Summary Table.
Time Base Period Register
Figure 14-114. TBPRD Register
15

14

13

12

11

10

9

8
7
TBPRD
R/W-0h

6

5

4

3

2

1

0

Table 14-53. TBPRD Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

TBPRD

R/W

0h

Time Base Period Register
These bits determine the period of the time-base counter. This sets
the PWM frequency. Shadowing of this register is enabled and
disabled by the TBCTL[PRDLD] bit. By default this register is
shadowed.
- If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or
read will automatically go to the shadow register. In this case, the
active register will be loaded from the shadow register when the
time-base counter equals zero.
- If TBCTL[PRDLD] = 1, then the shadow is disabled and any write
or read will go directly to the active register, that is the register
actively controlling the hardware.
- The active and shadow registers share the same memory map
address.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1827

Registers

www.ti.com

14.14.2.39 CMPA Register (Offset = 6Ah) [reset = 0h]
CMPA is shown in Figure 14-115 and described in Table 14-54.
Return to Summary Table.
Counter Compare A Register
Figure 14-115. CMPA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CMPA
R/W-0h

9

8 7 6
CMPAHR
R/W-0h

5

4

3

2

1

0

Table 14-54. CMPA Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

CMPA

R/W

0h

Compare A Register
The value in the active CMPA register is continuously compared to
the time-base counter (TBCTR). When the values are equal, the
counter-compare module generates a "time-base counter equal to
counter compare A" event. This event is sent to the action-qualifier
where it is qualified and converted it into one or more actions. These
actions can be applied to either the EPWMxA or the EPWMxB
output depending on the configuration of the AQCTLA and AQCTLB
registers. The actions that can be defined in the AQCTLA and
AQCTLB registers include:
- Do nothing
the event is ignored.
- Clear: Pull the EPWMxA and/or EPWMxB signal low
- Set: Pull the EPWMxA and/or EPWMxB signal high
- Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the
CMPCTL[SHDWAMODE] bit. By default this register is shadowed.
- If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and
any write or read will automatically go to the shadow register. In this
case, the CMPCTL[LOADAMODE] bit field determines which event
will load the active register from the shadow register.
- Before a write, the CMPCTL[SHDWAFULL] bit can be read to
determine if the shadow register is currently full.
- If CMPCTL[SHDWAMODE] = 1, then the shadow register is
disabled and any write or read will go directly to the active register,
that is the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same
memory map address.
Reset type: SYSRSn

15-0

CMPAHR

R/W

0h

Compare A HRPWM Extension Register
These 8-bits contain the high-resolution portion (least significant 8bits) of the counter-compare A value. CMPA:CMPAHR can be
accessed in a single 32-bit read/write. Shadowing is enabled and
disabled by the CMPCTL[SHDWAMODE] bit as described for the
CMPA register.
Reset type: SYSRSn

1828

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.40 CMPB Register (Offset = 6Ch) [reset = 0h]
CMPB is shown in Figure 14-116 and described in Table 14-55.
Return to Summary Table.
Compare B Register
Figure 14-116. CMPB Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CMPB
R/W-0h

9

8 7 6
CMPBHR
R/W-0h

5

4

3

2

1

0

Table 14-55. CMPB Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

CMPB

R/W

0h

Compare B Register
The value in the active CMPB register is continuously compared to
the time-base counter (TBCTR). When the values are equal, the
counter-compare module generates a "time-base counter equal to
counter compare B" event. This event is sent to the action-qualifier
where it is qualified and converted it into one or more actions. These
actions can be applied to either the EPWMxA or the EPWMxB
output depending on the configuration of the AQCTLA and AQCTLB
registers. The actions that can be defined in the AQCTLA and
AQCTLB registers include:
- Do nothing
the event is ignored.
- Clear: Pull the EPWMxA and/or EPWMxB signal low
- Set: Pull the EPWMxA and/or EPWMxB signal high
- Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the
CMPCTL[SHDWBMODE] bit. By default this register is shadowed.
- If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and
any write or read will automatically go to the shadow register. In this
case, the CMPCTL[LOADBMODE] bit field determines which event
will load the active register from the shadow register.
- Before a write, the CMPCTL[SHDWBFULL] bit can be read to
determine if the shadow register is currently full.
- If CMPCTL[SHDWBMODE] = 1, then the shadow register is
disabled and any write or read will go directly to the active register,
that is the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same
memory map address.
Reset type: SYSRSn

15-0

CMPBHR

R/W

0h

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Compare B High Resolution Bits
Reset type: SYSRSn

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1829

Registers

www.ti.com

14.14.2.41 CMPC Register (Offset = 6Fh) [reset = 0h]
CMPC is shown in Figure 14-117 and described in Table 14-56.
Return to Summary Table.
Counter Compare C Register
LINK feature access should always be 16-bit
Figure 14-117. CMPC Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CMPC
R/W-0h

Table 14-56. CMPC Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

CMPC

R/W

0h

Compare C Register
The value in the active CMPC register is continuously compared to
the time-base counter (TBCTR). When the values are equal, the
counter-compare module generates a "time-base counter equal to
counter compare C" event.
Shadowing of this register is enabled and disabled by the
CMPCTL2[SHDWCMODE] bit. By default this register is shadowed.
- If CMPCTL2[SHDWCMODE] = 0, then the shadow is enabled and
any write or read will automatically go to the shadow register. In this
case, the CMPCTL2[LOADCMODE] bit field determines which event
will load the active register from the shadow register:
- If CMPCTL2[SHDWCMODE] = 1, then the shadow register is
disabled and any write or read will go directly to the active register
that is, the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same
memory map address.
Reset type: SYSRSn

1830

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.42 CMPD Register (Offset = 71h) [reset = 0h]
CMPD is shown in Figure 14-118 and described in Table 14-57.
Return to Summary Table.
Counter Compare D Register
LINK feature access should always be 16-bit
Figure 14-118. CMPD Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CMPD
R/W-0h

Table 14-57. CMPD Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

CMPD

R/W

0h

Compare D Register
The value in the active CMPD register is continuously compared to
the time-base counter (TBCTR). When the values are equal, the
counter-compare module generates a "time-base counter equal to
counter compare D" event.
Shadowing of this register is enabled and disabled by the
CMPCTL2[SHDWDMODE] bit. By default this register is shadowed.
- If CMPCTL2[SHDWDMODE] = 0, then the shadow is enabled and
any write or read will automatically go to the shadow register. In this
case, the CMPCTL2[LOADDMODE] bit field determines which event
will load the active register from the shadow register:
- If CMPCTL2[SHDWDMODE] = 1, then the shadow register is
disabled and any write or read will go directly to the active register
that is, the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same
memory map address.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1831

Registers

www.ti.com

14.14.2.43 GLDCTL2 Register (Offset = 74h) [reset = 0h]
GLDCTL2 is shown in Figure 14-119 and described in Table 14-58.
Return to Summary Table.
Global PWM Load Control Register 2
Figure 14-119. GLDCTL2 Register
15

14

13

12

11

10

9

8

3

2

1
GFRCLD
R=0/W=1-0h

0
OSHTLD
R=0/W=1-0h

RESERVED
R=0-0h
7

6

5

4
RESERVED
R=0-0h

Table 14-58. GLDCTL2 Register Field Descriptions
Bit
15-2
1

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

GFRCLD

R=0/W=1

0h

Force Load Event in One Shot Mode
0: Writing of 0 will be ignored. Always reads back a 0.
1: Force one load event at the input of the event pre-scale counter
as shown in the diagram below. This bit is intended to be used for
testing and/or software force loading of the events in global load
mode.
Reset type: SYSRSn

0

OSHTLD

R=0/W=1

0h

Enable Reload Event in One Shot Mode
0: Writing of 0 will be ignored. Always reads back a 0.
1: Turns the one shot latch condition ON. Upon occurrence of a
chosen load strobe, one shadow to active reload occurs and the
latch will be cleared. Hence writing 1 to this bit would allow one load
strobe event to pass through and block further strobe events.
Reset type: SYSRSn

1832

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.44 SWVDELVAL Register (Offset = 77h) [reset = 0h]
SWVDELVAL is shown in Figure 14-120 and described in Table 14-59.
Return to Summary Table.
Software Valley Mode Delay Register
Figure 14-120. SWVDELVAL Register
15

14

13

12

11

10

9

8
7
SWVDELVAL
R-0h

6

5

4

3

2

1

0

Table 14-59. SWVDELVAL Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SWVDELVAL

R

0h

Software Valley Delay Value Register
This register can be optionally used define offset value for the
hardware calculated delay HWDELAYVAL as defined in
VCAPCTL[VDELAYDIV] bits.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1833

Registers

www.ti.com

14.14.2.45 TZSEL Register (Offset = 80h) [reset = 0h]
TZSEL is shown in Figure 14-121 and described in Table 14-60.
Return to Summary Table.
Trip Zone Select Register
Figure 14-121. TZSEL Register
15
DCBEVT1
R/W-0h

14
DCAEVT1
R/W-0h

13
OSHT6
R/W-0h

12
OSHT5
R/W-0h

11
OSHT4
R/W-0h

10
OSHT3
R/W-0h

9
OSHT2
R/W-0h

8
OSHT1
R/W-0h

7
DCBEVT2
R/W-0h

6
DCAEVT2
R/W-0h

5
CBC6
R/W-0h

4
CBC5
R/W-0h

3
CBC4
R/W-0h

2
CBC3
R/W-0h

1
CBC2
R/W-0h

0
CBC1
R/W-0h

Table 14-60. TZSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

DCBEVT1

R/W

0h

Digital Compare Output B Event 1 Select
0: Disable DCBEVT1 as one-shot-trip source for this ePWM module.
1: Enable DCBEVT1 as one-shot-trip source for this ePWM module.
Reset type: SYSRSn

14

DCAEVT1

R/W

0h

Digital Compare Output A Event 1 Select
0: Disable DCAEVT1 as one-shot-trip source for this ePWM module.
1: Enable DCAEVT1 as one-shot-trip source for this ePWM module.
Reset type: SYSRSn

13

OSHT6

R/W

0h

Trip-zone 6 (TZ6) Select
0: Disable TZ6 as a one-shot trip source for this ePWM module
1: Enable TZ6 as a one-shot trip source for this ePWM module
Reset type: SYSRSn

12

OSHT5

R/W

0h

Trip-zone 5 (TZ5) Select
0: Disable TZ5 as a one-shot trip source for this ePWM module
1: Enable TZ5 as a one-shot trip source for this ePWM module
Reset type: SYSRSn

11

OSHT4

R/W

0h

Trip-zone 4 (TZ4) Select
0: Disable TZ4 as a one-shot trip source for this ePWM module
1: Enable TZ4 as a one-shot trip source for this ePWM module
Reset type: SYSRSn

10

OSHT3

R/W

0h

Trip-zone 3 (TZ3) Select
0: Disable TZ3 as a one-shot trip source for this ePWM module
1: Enable TZ3 as a one-shot trip source for this ePWM module
Reset type: SYSRSn

9

OSHT2

R/W

0h

Trip-zone 2 (TZ2) Select
0: Disable TZ2 as a one-shot trip source for this ePWM module
1: Enable TZ2 as a one-shot trip source for this ePWM module
Reset type: SYSRSn

8

OSHT1

R/W

0h

Trip-zone 1 (TZ1) Select
0: Disable TZ1 as a one-shot trip source for this ePWM module
1: Enable TZ1 as a one-shot trip source for this ePWM module
Reset type: SYSRSn

1834

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-60. TZSEL Register Field Descriptions (continued)
Bit
7

Field

Type

Reset

Description

DCBEVT2

R/W

0h

Digital Compare Output B Event 2 Select
0: Disable DCBEVT2 as a CBC trip source for this ePWM module
1: Enable DCBEVT2 as a CBC trip source for this ePWM module
Reset type: SYSRSn

6

DCAEVT2

R/W

0h

Digital Compare Output A Event 2 Select
0: Disable DCAEVT2 as a CBC trip source for this ePWM module
1: Enable DCAEVT2 as a CBC trip source for this ePWM module
Reset type: SYSRSn

5

CBC6

R/W

0h

Trip-zone 6 (TZ6) Select
0: Disable TZ6 as a CBC trip source for this ePWM module
1: Enable TZ6 as a CBC trip source for this ePWM module
Reset type: SYSRSn

4

CBC5

R/W

0h

Trip-zone 5 (TZ5) Select
0: Disable TZ5 as a CBC trip source for this ePWM module
1: Enable TZ5 as a CBC trip source for this ePWM module
Reset type: SYSRSn

3

CBC4

R/W

0h

Trip-zone 4 (TZ4) Select
0: Disable TZ4 as a CBC trip source for this ePWM module
1: Enable TZ4 as a CBC trip source for this ePWM module
Reset type: SYSRSn

2

CBC3

R/W

0h

Trip-zone 3 (TZ3) Select
0: Disable TZ3 as a CBC trip source for this ePWM module
1: Enable TZ3 as a CBC trip source for this ePWM module
Reset type: SYSRSn

1

CBC2

R/W

0h

Trip-zone 2 (TZ2) Select
0: Disable TZ2 as a CBC trip source for this ePWM module
1: Enable TZ2 as a CBC trip source for this ePWM module
Reset type: SYSRSn

0

CBC1

R/W

0h

Trip-zone 1 (TZ1) Select
0: Disable TZ1 as a CBC trip source for this ePWM module
1: Enable TZ1 as a CBC trip source for this ePWM module
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1835

Registers

www.ti.com

14.14.2.46 TZDCSEL Register (Offset = 82h) [reset = 0h]
TZDCSEL is shown in Figure 14-122 and described in Table 14-61.
Return to Summary Table.
Trip Zone Digital Comparator Select Register
Figure 14-122. TZDCSEL Register
15

14

13

12

11

10
DCBEVT2
R/W-0h

9

8
DCBEVT1
R/W-0h

5

4
DCAEVT2
R/W-0h

3

2

1
DCAEVT1
R/W-0h

0

RESERVED
R=0-0h
7

6
DCBEVT1
R/W-0h

Table 14-61. TZDCSEL Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R=0

0h

Reserved

11-9

DCBEVT2

R/W

0h

Digital Compare Output B Event 2 Selection
000: Event disabled
001: DCBH = low, DCBL = don't care
010: DCBH = high, DCBL = don't care
011: DCBL = low, DCBH = don't care
100: DCBL = high, DCBH = don't care
101: DCBL = high, DCBH = low
110: Reserved
111: Reserved
Reset type: SYSRSn

8-6

DCBEVT1

R/W

0h

Digital Compare Output B Event 1 Selection
000: Event disabled
001: DCBH = low, DCBL = don't care
010: DCBH = high, DCBL = don't care
011: DCBL = low, DCBH = don't care
100: DCBL = high, DCBH = don't care
101: DCBL = high, DCBH = low
110: Reserved
111: Reserved
Reset type: SYSRSn

5-3

DCAEVT2

R/W

0h

Digital Compare Output A Event 2 Selection
000: Event disabled
001: DCAH = low, DCAL = don't care
010: DCAH = high, DCAL = don't care
011: DCAL = low, DCAH = don't care
100: DCAL = high, DCAH = don't care
101: DCAL = high, DCAH = low
110: Reserved
111: Reserved
Reset type: SYSRSn

1836

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-61. TZDCSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2-0

DCAEVT1

R/W

0h

Digital Compare Output A Event 1 Selection
000: Event disabled
001: DCAH = low, DCAL = don't care
010: DCAH = high, DCAL = don't care
011: DCAL = low, DCAH = don't care
100: DCAL = high, DCAH = don't care
101: DCAL = high, DCAH = low
110: Reserved
111: Reserved
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1837

Registers

www.ti.com

14.14.2.47 TZCTL Register (Offset = 84h) [reset = 0h]
TZCTL is shown in Figure 14-123 and described in Table 14-62.
Return to Summary Table.
Trip Zone Control Register
Figure 14-123. TZCTL Register
15

14

13

12

11

RESERVED
R=0-0h
7

6

10

9

DCBEVT2
R/W-0h
5

4

DCAEVT2
R/W-0h

3

2

DCAEVT1
R/W-0h

8
DCBEVT1
R/W-0h

1

TZB
R/W-0h

0
TZA
R/W-0h

Table 14-62. TZCTL Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R=0

0h

Reserved

11-10

DCBEVT2

R/W

0h

Digital Compare Output B Event 2 Action On EPWMxB
00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state.
10: Force EPWMxB to a low state.
11: Do Nothing, trip action is disabled
Reset type: SYSRSn

9-8

DCBEVT1

R/W

0h

Digital Compare Output B Event 1 Action On EPWMxB
00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state.
10: Force EPWMxB to a low state.
11: Do Nothing, trip action is disabled
Reset type: SYSRSn

7-6

DCAEVT2

R/W

0h

Digital Compare Output A Event 2 Action On EPWMxA
00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state.
10: Force EPWMxA to a low state.
11: Do Nothing, trip action is disabled
Reset type: SYSRSn

5-4

DCAEVT1

R/W

0h

Digital Compare Output A Event 1 Action On EPWMxA
00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state.
10: Force EPWMxA to a low state.
11: Do Nothing, trip action is disabled
Reset type: SYSRSn

3-2

TZB

R/W

0h

TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2Trip Action On EPWMxB
When a trip event occurs the following action is taken on output
EPWMxB. Which trip-zone pins can cause an event is defined in the
TZSEL register.
00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state
10: Force EPWMxB to a low state
11: Do nothing, no action is taken on EPWMxB.
Reset type: SYSRSn

1838

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-62. TZCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

TZA

R/W

0h

TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA
When a trip event occurs the following action is taken on output
EPWMxA. Which trip-zone pins can cause an event is defined in the
TZSEL register.
00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state
10: Force EPWMxA to a low state
11: Do nothing, no action is taken on EPWMxA.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1839

Registers

www.ti.com

14.14.2.48 TZCTL2 Register (Offset = 85h) [reset = 0h]
TZCTL2 is shown in Figure 14-124 and described in Table 14-63.
Return to Summary Table.
Additional Trip Zone Control Register
Figure 14-124. TZCTL2 Register
15
ETZE
R/W-0h
7

14

13
RESERVED
R=0-0h

12

11

10
TZBD
R/W-0h

9

8
TZBU
R/W-0h

6

5

4
TZAD
R/W-0h

3

2

1
TZAU
R/W-0h

0

TZBU
R/W-0h

Table 14-63. TZCTL2 Register Field Descriptions
Bit

Field

Type

Reset

Description

15

ETZE

R/W

0h

TZCTL2 Enable
0: Use trip action from TZCTL (legacy EPWM compatibility)
1: Use trip action defined in TZCTL2, TZCTLDCA and TZCTLDCB.
Settings in TZCTL are ignored
Reset type: SYSRSn

14-12

RESERVED

R=0

0h

Reserved

11-9

TZBD

R/W

0h

TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxB
while Count direction is DOWN
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

8-6

TZBU

R/W

0h

TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxB
while Count direction is UP
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

1840

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-63. TZCTL2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-3

TZAD

R/W

0h

TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA
while Count direction is DOWN
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

2-0

TZAU

R/W

0h

TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA
while Count direction is UP
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1841

Registers

www.ti.com

14.14.2.49 TZCTLDCA Register (Offset = 86h) [reset = 0h]
TZCTLDCA is shown in Figure 14-125 and described in Table 14-64.
Return to Summary Table.
Trip Zone Control Register Digital Compare A
Figure 14-125. TZCTLDCA Register
15

14

13

12

11

10
DCAEVT2D
R/W-0h

9

8
DCAEVT2U
R/W-0h

5

4
DCAEVT1D
R/W-0h

3

2

1
DCAEVT1U
R/W-0h

0

RESERVED
R=0-0h
7

6
DCAEVT2U
R/W-0h

Table 14-64. TZCTLDCA Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R=0

0h

Reserved

11-9

DCAEVT2D

R/W

0h

Digital Compare Output A Event 2 Action On EPWMxA while Count
direction is DOWN
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

8-6

DCAEVT2U

R/W

0h

Digital Compare Output A Event 2 Action On EPWMxA while Count
direction is UP
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

5-3

DCAEVT1D

R/W

0h

Digital Compare Output A Event 1 Action On EPWMxA while Count
direction is DOWN
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

1842

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-64. TZCTLDCA Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2-0

DCAEVT1U

R/W

0h

Digital Compare Output A Event 1 Action On EPWMxA while Count
direction is UP
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1843

Registers

www.ti.com

14.14.2.50 TZCTLDCB Register (Offset = 87h) [reset = 0h]
TZCTLDCB is shown in Figure 14-126 and described in Table 14-65.
Return to Summary Table.
Trip Zone Control Register Digital Compare B
Figure 14-126. TZCTLDCB Register
15

14

13

12

11

10
DCBEVT2D
R/W-0h

9

8
DCBEVT2U
R/W-0h

5

4
DCBEVT1D
R/W-0h

3

2

1
DCBEVT1U
R/W-0h

0

RESERVED
R=0-0h
7

6
DCBEVT2U
R/W-0h

Table 14-65. TZCTLDCB Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R=0

0h

Reserved

11-9

DCBEVT2D

R/W

0h

Digital Compare Output A Event 2 Action On EPWMxB while Count
direction is DOWN
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

8-6

DCBEVT2U

R/W

0h

Digital Compare Output A Event 2 Action On EPWMxB while Count
direction is UP
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

5-3

DCBEVT1D

R/W

0h

Digital Compare Output A Event 1 Action On EPWMxB while Count
direction is DOWN
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

1844

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-65. TZCTLDCB Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2-0

DCBEVT1U

R/W

0h

Digital Compare Output A Event 1 Action On EPWMxB while Count
direction is UP
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1845

Registers

www.ti.com

14.14.2.51 TZEINT Register (Offset = 8Dh) [reset = 0h]
TZEINT is shown in Figure 14-127 and described in Table 14-66.
Return to Summary Table.
Trip Zone Enable Interrupt Register
Figure 14-127. TZEINT Register
15

14

13

12

11

10

9

8

3
DCAEVT1
R/W-0h

2
OST
R/W-0h

1
CBC
R/W-0h

0
RESERVED
R=0-0h

RESERVED
R=0-0h
7
RESERVED
R=0-0h

6
DCBEVT2
R/W-0h

5
DCBEVT1
R/W-0h

4
DCAEVT2
R/W-0h

Table 14-66. TZEINT Register Field Descriptions
Bit
15-7
6

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

DCBEVT2

R/W

0h

Digital Compare Output B Event 2 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn

5

DCBEVT1

R/W

0h

Digital Compare Output B Event 1 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn

4

DCAEVT2

R/W

0h

Digital Compare Output A Event 2 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn

3

DCAEVT1

R/W

0h

Digital Compare Output A Event 1 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn

2

OST

R/W

0h

Trip-zone One-Shot Interrupt Enable
0: Disable one-shot interrupt generation
1: Enable Interrupt generation
a one-shot trip event will cause a EPWMx_TZINT PIE interrupt.
Reset type: SYSRSn

1

CBC

R/W

0h

Trip-zone Cycle-by-Cycle Interrupt Enable
0: Disable cycle-by-cycle interrupt generation.
1: Enable interrupt generation
a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE
interrupt.
Reset type: SYSRSn

0

1846

RESERVED

R=0

Enhanced Pulse Width Modulator (ePWM)

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.52 TZFLG Register (Offset = 93h) [reset = 0h]
TZFLG is shown in Figure 14-128 and described in Table 14-67.
Return to Summary Table.
Trip Zone Flag Register
Figure 14-128. TZFLG Register
15

14

13

12

11

10

9

8

3
DCAEVT1
R-0h

2
OST
R-0h

1
CBC
R-0h

0
INT
R-0h

RESERVED
R=0-0h
7
RESERVED
R=0-0h

6
DCBEVT2
R-0h

5
DCBEVT1
R-0h

4
DCAEVT2
R-0h

Table 14-67. TZFLG Register Field Descriptions
Bit
15-7
6

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

DCBEVT2

R

0h

Latched Status Flag for Digital Compare Output B Event 2
0: Indicates no trip event has occurred on DCBEVT2
1: Indicates a trip event has occurred for the event defined for
DCBEVT2
Reset type: SYSRSn

5

DCBEVT1

R

0h

Latched Status Flag for Digital Compare Output B Event 1
0: Indicates no trip event has occurred on DCBEVT1
1: Indicates a trip event has occurred for the event defined for
DCBEVT1
Reset type: SYSRSn

4

DCAEVT2

R

0h

Latched Status Flag for Digital Compare Output A Event 2
0: Indicates no trip event has occurred on DCAEVT2
1: Indicates a trip event has occurred for the event defined for
DCAEVT2
Reset type: SYSRSn

3

DCAEVT1

R

0h

Latched Status Flag for Digital Compare Output A Event 1
0: Indicates no trip event has occurred on DCAEVT1
1: Indicates a trip event has occurred for the event defined for
DCAEVT1
Reset type: SYSRSn

2

OST

R

0h

Latched Status Flag for A One-Shot Trip Event
0: No one-shot trip event has occurred.
1: Indicates a trip event has occurred on a pin selected as a oneshot trip source.
This bit is cleared by writing the appropriate value to the TZCLR
register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1847

Registers

www.ti.com

Table 14-67. TZFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

CBC

R

0h

Latched Status Flag for Cycle-By-Cycle Trip Event
0: No cycle-by-cycle trip event has occurred.
1: Indicates a trip event has occurred on a signal selected as a
cycle-by-cycle trip source. The
TZFLG[CBC] bit will remain set until it is manually cleared by the
user. If the cycle-by-cycle trip event is still present when the CBC bit
is cleared, then CBC will be immediately set again. The specified
condition on the signal is automatically cleared when the ePWM
time-base counter reaches zero (TBCTR = 0x00) if the trip condition
is no longer present. The condition on the signal is only cleared
when the TBCTR = 0x00 no matter where in the cycle the CBC flag
is cleared.
This bit is cleared by writing the appropriate value to the TZCLR
register.
Reset type: SYSRSn

0

INT

R

0h

Latched Trip Interrupt Status Flag
0: Indicates no interrupt has been generated.
1: Indicates an EPWMx_TZINT PIE interrupt was generated because
of a trip condition.
No further EPWMx_TZINT PIE interrupts will be generated until this
flag is cleared. If the interrupt flag is cleared when either CBC or
OST is set, then another interrupt pulse will be generated. Clearing
all flag bits will prevent further interrupts. This bit is cleared by writing
the appropriate value to the TZCLR register.
Reset type: SYSRSn

1848

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.53 TZCBCFLG Register (Offset = 94h) [reset = 0h]
TZCBCFLG is shown in Figure 14-129 and described in Table 14-68.
Return to Summary Table.
Trip Zone CBC Flag Register
Figure 14-129. TZCBCFLG Register
15

14

13

12

11

10

9

8

3
CBC4
R-0h

2
CBC3
R-0h

1
CBC2
R-0h

0
CBC1
R-0h

RESERVED
R=0-0h
7
DCBEVT2
R-0h

6
DCAEVT2
R-0h

5
CBC6
R-0h

4
CBC5
R-0h

Table 14-68. TZCBCFLG Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

DCBEVT2

R

0h

Latched Status Flag for Digital Compare B Output Event 2 Trip Latch
0: Reading a 0 indicates that no trip has occurred on DCBEVT2.
1: Reading a 1 indicates a trip has occured on the DCBEVT2
selected event.
Reset type: SYSRSn

6

DCAEVT2

R

0h

Latched Status Flag for Digital Compare A Output Event 2 Trip Latch
0: Reading a 0 indicates that no trip has occurred on DCAEVT2.
1: Reading a 1 indicates a trip has occured on the DCAEVT2
selected event.
Reset type: SYSRSn

5

CBC6

R

0h

Latched Status Flag for CBC6 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC6.
1: Reading a 1 indicates a trip has occured on the CBC6 selected
event.
Reset type: SYSRSn

4

CBC5

R

0h

Latched Status Flag for CBC5 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC5.
1: Reading a 1 indicates a trip has occured on the CBC5 selected
event.
Reset type: SYSRSn

3

CBC4

R

0h

Latched Status Flag for CBC4 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC4.
1: Reading a 1 indicates a trip has occured on the CBC4 selected
event.
Reset type: SYSRSn

2

CBC3

R

0h

Latched Status Flag for CBC3 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC3.
1: Reading a 1 indicates a trip has occured on the CBC3 selected
event.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1849

Registers

www.ti.com

Table 14-68. TZCBCFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

CBC2

R

0h

Latched Status Flag for CBC2 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC2.
1: Reading a 1 indicates a trip has occured on the CBC2 selected
event.
Reset type: SYSRSn

0

CBC1

R

0h

Latched Status Flag for CBC1 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC1.
1: Reading a 1 indicates a trip has occured on the CBC1 selected
event.
Reset type: SYSRSn

1850

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.54 TZOSTFLG Register (Offset = 95h) [reset = 0h]
TZOSTFLG is shown in Figure 14-130 and described in Table 14-69.
Return to Summary Table.
Trip Zone OST Flag Register
Figure 14-130. TZOSTFLG Register
15

14

13

12

11

10

9

8

3
OST4
R-0h

2
OST3
R-0h

1
OST2
R-0h

0
OST1
R-0h

RESERVED
R=0-0h
7
DCBEVT1
R-0h

6
DCAEVT1
R-0h

5
OST6
R-0h

4
OST5
R-0h

Table 14-69. TZOSTFLG Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

DCBEVT1

R

0h

Latched Status Flag for Digital Compare B Output Event 1 Trip Latch
0: Reading a 0 indicates that no trip has occurred on DCBEVT1.
1: Reading a 1 indicates a trip has occured on the DCBEVT1
selected event.
Reset type: SYSRSn

6

DCAEVT1

R

0h

Latched Status Flag for Digital Compare A Output Event 1 Trip Latch
0: Reading a 0 indicates that no trip has occurred on DCAEVT1.
1: Reading a 1 indicates a trip has occured on the DCAEVT1
selected event.
Reset type: SYSRSn

5

OST6

R

0h

Latched Status Flag for OST6 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST6.
1: Reading a 1 indicates a trip has occured on the OST6 selected
event.
Reset type: SYSRSn

4

OST5

R

0h

Latched Status Flag for OST5 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST5.
1: Reading a 1 indicates a trip has occured on the OST5 selected
event.
Reset type: SYSRSn

3

OST4

R

0h

Latched Status Flag for OST4 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST4.
1: Reading a 1 indicates a trip has occured on the OST4 selected
event.
Reset type: SYSRSn

2

OST3

R

0h

Latched Status Flag for OST3 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST3.
1: Reading a 1 indicates a trip has occured on the OST3 selected
event.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1851

Registers

www.ti.com

Table 14-69. TZOSTFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

OST2

R

0h

Latched Status Flag for OST2 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST2.
1: Reading a 1 indicates a trip has occured on the OST2 selected
event.
Reset type: SYSRSn

0

OST1

R

0h

Latched Status Flag for OST1 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST1.
1: Reading a 1 indicates a trip has occured on the OST1 selected
event.
Reset type: SYSRSn

1852

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.55 TZCLR Register (Offset = 97h) [reset = 0h]
TZCLR is shown in Figure 14-131 and described in Table 14-70.
Return to Summary Table.
Trip Zone Clear Register
Figure 14-131. TZCLR Register
15

14

13

12

11

CBCPULSE
R/W-0h
7
RESERVED
R=0-0h

6
DCBEVT2
R=0/W=1-0h

10

9

8

2
OST
R=0/W=1-0h

1
CBC
R=0/W=1-0h

0
INT
R=0/W=1-0h

RESERVED
R=0-0h
5
DCBEVT1
R=0/W=1-0h

4
DCAEVT2
R=0/W=1-0h

3
DCAEVT1
R=0/W=1-0h

Table 14-70. TZCLR Register Field Descriptions
Bit
15-14

Field

Type

Reset

Description

CBCPULSE

R/W

0h

Clear Pulse for Cycle-By-Cycle (CBC) Trip Latch
This bit field determines which pulse clears the CBC trip latch.
00: CTR = zero pulse clears CBC trip latch. (Same as legacy
designs.)
01: CTR = PRD pulse clears CBC trip latch.
10: CTR = zero or CTR = PRD pulse clears CBC trip latch.
11: CBC trip latch is not cleared
Reset type: SYSRSn

13-7
6

RESERVED

R=0

0h

Reserved

DCBEVT2

R=0/W=1

0h

Clear Flag for Digital Compare Output B Event 2
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCBEVT2 event trip condition.
Reset type: SYSRSn

5

DCBEVT1

R=0/W=1

0h

Clear Flag for Digital Compare Output B Event 1
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCBEVT1 event trip condition.
Reset type: SYSRSn

4

DCAEVT2

R=0/W=1

0h

Clear Flag for Digital Compare Output A Event 2
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCAEVT2 event trip condition.
Reset type: SYSRSn

3

DCAEVT1

R=0/W=1

0h

Clear Flag for Digital Compare Output A Event 1
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCAEVT1 event trip condition.
Reset type: SYSRSn

2

OST

R=0/W=1

0h

Clear Flag for One-Shot Trip (OST) Latch
0: Has no effect. Always reads back a 0.
1: Clears this Trip (set) condition.
Reset type: SYSRSn

1

CBC

R=0/W=1

0h

Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
0: Has no effect. Always reads back a 0.
1: Clears this Trip (set) condition.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1853

Registers

www.ti.com

Table 14-70. TZCLR Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

INT

R=0/W=1

0h

Global Interrupt Clear Flag
0: Has no effect. Always reads back a 0.
1: Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMx_TZINT PIE interrupts will be generated
until the flag is cleared. If the TZFLG[INT] bit is cleared and any of
the other flag bits are set, then another interrupt pulse will be
generated. Clearing all flag bits will prevent further interrupts.
Reset type: SYSRSn

1854

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.56 TZCBCCLR Register (Offset = 98h) [reset = 0h]
TZCBCCLR is shown in Figure 14-132 and described in Table 14-71.
Return to Summary Table.
Trip Zone CBC Clear Register
Figure 14-132. TZCBCCLR Register
15

14

13

12

11

10

9

8

3
CBC4
R=0/W=1-0h

2
CBC3
R=0/W=1-0h

1
CBC2
R=0/W=1-0h

0
CBC1
R=0/W=1-0h

RESERVED
R=0-0h
7
DCBEVT2
R=0/W=1-0h

6
DCAEVT2
R=0/W=1-0h

5
CBC6
R=0/W=1-0h

4
CBC5
R=0/W=1-0h

Table 14-71. TZCBCCLR Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

DCBEVT2

R=0/W=1

0h

Clear Flag for Digital Compare Output B Event 2 selected for CBC
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit.
Reset type: SYSRSn

6

DCAEVT2

R=0/W=1

0h

Clear Flag for Digital Compare Output A Event 2 selected for CBC
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit.
Reset type: SYSRSn

5

CBC6

R=0/W=1

0h

Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC6] bit.
Reset type: SYSRSn

4

CBC5

R=0/W=1

0h

Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC5] bit.
Reset type: SYSRSn

3

CBC4

R=0/W=1

0h

Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC4] bit.
Reset type: SYSRSn

2

CBC3

R=0/W=1

0h

Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC3] bit.
Reset type: SYSRSn

1

CBC2

R=0/W=1

0h

Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC2] bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1855

Registers

www.ti.com

Table 14-71. TZCBCCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

CBC1

R=0/W=1

0h

Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC1] bit.
Reset type: SYSRSn

1856

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.57 TZOSTCLR Register (Offset = 99h) [reset = 0h]
TZOSTCLR is shown in Figure 14-133 and described in Table 14-72.
Return to Summary Table.
Trip Zone OST Clear Register
Figure 14-133. TZOSTCLR Register
15

14

13

12

11

10

9

8

3
OST4
R=0/W=1-0h

2
OST3
R=0/W=1-0h

1
OST2
R=0/W=1-0h

0
OST1
R=0/W=1-0h

RESERVED
R=0-0h
7
DCBEVT1
R=0/W=1-0h

6
DCAEVT1
R=0/W=1-0h

5
OST6
R=0/W=1-0h

4
OST5
R=0/W=1-0h

Table 14-72. TZOSTCLR Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

DCBEVT1

R=0/W=1

0h

Clear Flag for Digital Compare Output B Event 1 selected for OST
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit.
Reset type: SYSRSn

6

DCAEVT1

R=0/W=1

0h

Clear Flag for Digital Compare Output A Event 1 selected for OST
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit.
Reset type: SYSRSn

5

OST6

R=0/W=1

0h

Clear Flag for Oneshot (OST6) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST6] bit.
Reset type: SYSRSn

4

OST5

R=0/W=1

0h

Clear Flag for Oneshot (OST5) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST5] bit.
Reset type: SYSRSn

3

OST4

R=0/W=1

0h

Clear Flag for Oneshot (OST4) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST4] bit.
Reset type: SYSRSn

2

OST3

R=0/W=1

0h

Clear Flag for Oneshot (OST3) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST3] bit.
Reset type: SYSRSn

1

OST2

R=0/W=1

0h

Clear Flag for Oneshot (OST2) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST2] bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1857

Registers

www.ti.com

Table 14-72. TZOSTCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

OST1

R=0/W=1

0h

Clear Flag for Oneshot (OST1) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST1] bit.
Reset type: SYSRSn

1858

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.58 TZFRC Register (Offset = 9Bh) [reset = 0h]
TZFRC is shown in Figure 14-134 and described in Table 14-73.
Return to Summary Table.
Trip Zone Force Register
Figure 14-134. TZFRC Register
15

14

13

12

11

10

9

8

3
DCAEVT1
R=0/W=1-0h

2
OST
R=0/W=1-0h

1
CBC
R=0/W=1-0h

0
RESERVED
R=0-0h

RESERVED
R=0-0h
7
RESERVED
R=0-0h

6
DCBEVT2
R=0/W=1-0h

5
DCBEVT1
R=0/W=1-0h

4
DCAEVT2
R=0/W=1-0h

Table 14-73. TZFRC Register Field Descriptions
Bit
15-7
6

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

DCBEVT2

R=0/W=1

0h

Force Flag for Digital Compare Output B Event 2
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCBEVT2 event trip condition and sets the
TZFLG[DCBEVT2] bit.
Reset type: SYSRSn

5

DCBEVT1

R=0/W=1

0h

Force Flag for Digital Compare Output B Event 1
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCBEVT1 event trip condition and sets the
TZFLG[DCBEVT1] bit.
Reset type: SYSRSn

4

DCAEVT2

R=0/W=1

0h

Force Flag for Digital Compare Output A Event 2
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCAEVT2 event trip condition and sets the
TZFLG[DCAEVT2] bit.
Reset type: SYSRSn

3

DCAEVT1

R=0/W=1

0h

Force Flag for Digital Compare Output A Event 1
0: Writing 0 has no effect. This bit always reads back 0
1: Writing 1 forces the DCAEVT1 event trip condition and sets the
TZFLG[DCAEVT1] bit.
Reset type: SYSRSn

2

OST

R=0/W=1

0h

Force a One-Shot Trip Event via Software
0: Writing of 0 is ignored. Always reads back a 0.
1: Forces a one-shot trip event and sets the TZFLG[OST] bit.
Reset type: SYSRSn

1

CBC

R=0/W=1

0h

Force a Cycle-by-Cycle Trip Event via Software
0: Writing of 0 is ignored. Always reads back a 0.
1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.
Reset type: SYSRSn

0

RESERVED

R=0

0h

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Reserved

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1859

Registers

www.ti.com

14.14.2.59 ETSEL Register (Offset = A4h) [reset = 0h]
ETSEL is shown in Figure 14-135 and described in Table 14-74.
Return to Summary Table.
Event Trigger Selection Register
Figure 14-135. ETSEL Register
15
SOCBEN
R/W-0h

14

7
RESERVED
R=0-0h

6
INTSELCMP
R/W-0h

13
SOCBSEL
R/W-0h

12

5
4
SOCBSELCMP SOCASELCMP
R/W-0h
R/W-0h

11
SOCAEN
R/W-0h

10

9
SOCASEL
R/W-0h

8

3
INTEN
R/W-0h

2

1
INTSEL
R/W-0h

0

Table 14-74. ETSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SOCBEN

R/W

0h

Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse
0: Disable EPWMxSOCB.
1: Enable EPWMxSOCB pulse.
Reset type: SYSRSn

14-12

SOCBSEL

R/W

0h

EPWMxSOCB Selection Options
These bits determine when a EPWMxSOCB pulse will be generated.
000: Enable DCBEVT1.soc event
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR =
TBPRD)
011: Enable event time-base counter equal to zero or period
(TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in updown count mode.
100: Enable event time-base counter equal to CMPA when the timer
is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer
is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer
is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer
is decrementing or CMPD when the timer is decrementing (*) Event
selected is determined by SOCBSELCMP bit.
Reset type: SYSRSn

11

SOCAEN

R/W

0h

Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse
0: Disable EPWMxSOCA.
1: Enable EPWMxSOCA pulse.
Reset type: SYSRSn

1860

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-74. ETSEL Register Field Descriptions (continued)
Bit
10-8

Field

Type

Reset

Description

SOCASEL

R/W

0h

EPWMxSOCA Selection Options
These bits determine when a EPWMxSOCA pulse will be generated.
000: Enable DCAEVT1.soc event
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR =
TBPRD)
011: Enable event time-base counter equal to zero or period
(TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in updown count mode.
100: Enable event time-base counter equal to CMPA when the timer
is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer
is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer
is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer
is decrementing or CMPD when the timer is decrementing (*) Event
selected is determined by SOCASELCMP bit.
Reset type: SYSRSn

7

RESERVED

R=0

0h

Reserved

6

INTSELCMP

R/W

0h

EPWMxINT Compare Register Selection Options
0: Enable event time-base counter equal to CMPA when the timer is
incrementing / Enable event time-base counter equal to CMPA when
the timer is decrementing / Enable event: time-base counter equal to
CMPB when the timer is incrementing / Enable event: time-base
counter equal to CMPB when the timer is decrementing to INTSEL
selection mux.
1: Enable event time-base counter equal to CMPC when the timer is
incrementing / Enable event time-base counter equal to CMPC when
the timer is decrementing / Enable event: time-base counter equal to
CMPD when the timer is incrementing / Enable event: time-base
counter equal to CMPD when the timer is decrementing to INTSEL
selection mux.
Reset type: SYSRSn

5

SOCBSELCMP

R/W

0h

EPWMxSOCB Compare Register Selection Options
0: Enable event time-base counter equal to CMPA when the timer is
incrementing / Enable event time-base counter equal to CMPA when
the timer is decrementing / Enable event: time-base counter equal to
CMPB when the timer is incrementing / Enable event: time-base
counter equal to CMPB when the timer is decrementing to
SOCBSEL selection mux.
1: Enable event time-base counter equal to CMPC when the timer is
incrementing / Enable event time-base counter equal to CMPC when
the timer is decrementing / Enable event: time-base counter equal to
CMPD when the timer is incrementing / Enable event: time-base
counter equal to CMPD when the timer is decrementing to
SOCBSEL selection mux.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1861

Registers

www.ti.com

Table 14-74. ETSEL Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

SOCASELCMP

R/W

0h

EPWMxSOCA Compare Register Selection Options
0: Enable event time-base counter equal to CMPA when the timer is
incrementing / Enable event time-base counter equal to CMPA when
the timer is decrementing / Enable event: time-base counter equal to
CMPB when the timer is incrementing / Enable event: time-base
counter equal to CMPB when the timer is decrementing to
SOCASEL selection mux.
1: Enable event time-base counter equal to CMPC when the timer is
incrementing / Enable event time-base counter equal to CMPC when
the timer is decrementing / Enable event: time-base counter equal to
CMPD when the timer is incrementing / Enable event: time-base
counter equal to CMPD when the timer is decrementing to
SOCASEL selection mux.
Reset type: SYSRSn

3

INTEN

R/W

0h

Enable ePWM Interrupt (EPWMx_INT) Generation
0: Disable EPWMx_INT generation
1: Enable EPWMx_INT generation
Reset type: SYSRSn

2-0

INTSEL

R/W

0h

ePWM Interrupt (EPWMx_INT) Selection Options
000: Reserved
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR =
TBPRD)
011: Enable event time-base counter equal to zero or period
(TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in updown count mode.
100: Enable event time-base counter equal to CMPA when the timer
is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer
is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer
is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer
is decrementing or CMPD when the timer is decrementing (*) Event
selected is determined by INTSELCMP bit.
Reset type: SYSRSn

1862

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.60 ETPS Register (Offset = A6h) [reset = 0h]
ETPS is shown in Figure 14-136 and described in Table 14-75.
Return to Summary Table.
Event Trigger Pre-Scale Register
Figure 14-136. ETPS Register
15

14

13

SOCBCNT
R-0h
7

12

11

SOCBPRD
R/W-0h
6

RESERVED
R=0-0h

5
SOCPSSEL
R/W-0h

4
INTPSSEL
R/W-0h

10

9

SOCACNT
R-0h
3

8
SOCAPRD
R/W-0h

2
INTCNT
R-0h

1

0
INTPRD
R/W-0h

Table 14-75. ETPS Register Field Descriptions
Bit
15-14

Field

Type

Reset

Description

SOCBCNT

R

0h

ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter
Register
These bits indicate how many selected ETSEL[SOCBSEL] events
have occurred:
00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.
Reset type: SYSRSn

13-12

SOCBPRD

R/W

0h

ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period
Select
These bits determine how many selected ETSEL[SOCBSEL] events
need to occur before an EPWMxSOCB pulse is generated. To be
generated, the pulse must be enabled (ETSEL[SOCBEN] = 1). The
SOCB pulse will be generated even if the status flag is set from a
previous start of conversion (ETFLG[SOCB] = 1). Once the SOCB
pulse is generated, the ETPS[SOCBCNT] bits will automatically be
cleared.
00: Disable the SOCB event counter. No EPWMxSOCB pulse will be
generated
01: Generate the EPWMxSOCB pulse on the first event:
ETPS[SOCBCNT] = 0,1
10: Generate the EPWMxSOCB pulse on the second event:
ETPS[SOCBCNT] = 1,0
11: Generate the EPWMxSOCB pulse on the third event:
ETPS[SOCBCNT] = 1,1
Reset type: SYSRSn

11-10

SOCACNT

R

0h

ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter
Register
These bits indicate how many selected ETSEL[SOCASEL] events
have occurred:
00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1863

Registers

www.ti.com

Table 14-75. ETPS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

9-8

SOCAPRD

R/W

0h

ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period
Select
These bits determine how many selected ETSEL[SOCASEL] events
need to occur before an EPWMxSOCA pulse is generated. To be
generated, the pulse must be enabled (ETSEL[SOCAEN] = 1). The
SOCA pulse will be generated even if the status flag is set from a
previous start of conversion (ETFLG[SOCA] = 1). Once the SOCA
pulse is generated, the ETPS[SOCACNT] bits will automatically be
cleared.
00: Disable the SOCA event counter. No EPWMxSOCA pulse will be
generated
01: Generate the EPWMxSOCA pulse on the first event:
ETPS[SOCACNT] = 0,1
10: Generate the EPWMxSOCA pulse on the second event:
ETPS[SOCACNT] = 1,0
11: Generate the EPWMxSOCA pulse on the third event:
ETPS[SOCACNT] = 1,1
Reset type: SYSRSn

7-6

RESERVED

R=0

0h

Reserved

5

SOCPSSEL

R/W

0h

EPWMxSOC A/B Pre-Scale Selection Bits
0: Selects ETPS [SOCACNT/SOCBCNT] and
[SOCAPRD/SOCBPRD] registers to determine frequency of events
(interrupt once every 0-3 events).
1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and
[SOCAPRD2/SOCBPRD2] registers to determine frequency of
events (interrupt once every 0-15 events).
Reset type: SYSRSn

4

INTPSSEL

R/W

0h

EPWMxINTn Pre-Scale Selection Bits
0: Selects ETPS [INTCNT, and INTPRD] registers to determine
frequency of events (interrupt once every 0-3 events).
1: Selects ETINTPS [ INTCNT2, and INTPRD2 ] registers to
determine frequency of events (interrupt once every 0-15 events).
Reset type: SYSRSn

3-2

INTCNT

R

0h

ePWM Interrupt Event (EPWMx_INT) Counter Register
These bits indicate how many selected ETSEL[INTSEL] events have
occurred. These bits are automatically cleared when an interrupt
pulse is generated. If interrupts are disabled, ETSEL[INT] = 0 or the
interrupt flag is set, ETFLG[INT] = 1, the counter will stop counting
events when it reaches the period value ETPS[INTCNT] =
ETPS[INTPRD].
00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.
Reset type: SYSRSn

1864

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-75. ETPS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

INTPRD

R/W

0h

ePWM Interrupt (EPWMx_INT) Period Select
These bits determine how many selected ETSEL[INTSEL] events
need to occur before an interrupt is generated. To be generated, the
interrupt must be enabled (ETSEL[INT] = 1). If the interrupt status
flag is set from a previous interrupt (ETFLG[INT] = 1) then no
interrupt will be generated until the flag is cleared via the
ETCLR[INT] bit. This allows for one interrupt to be pending while
another is still being serviced. Once the interrupt is generated, the
ETPS[INTCNT] bits will automatically be cleared.
Writing a INTPRD value that is the same as the current counter
value will trigger an interrupt if it is enabled and the status flag is
clear.
Writing a INTPRD value that is less than the current counter value
will result in an undefined state. If a counter event occurs at the
same instant as a new zero or non-zero INTPRD value is written, the
counter is incremented.
00: Disable the interrupt event counter. No interrupt will be
generated and ETFRC[INT] is ignored.
01: Generate an interrupt on the first event INTCNT = 01 (first event)
10: Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
11: Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1865

Registers

www.ti.com

14.14.2.61 ETFLG Register (Offset = A8h) [reset = 0h]
ETFLG is shown in Figure 14-137 and described in Table 14-76.
Return to Summary Table.
Event Trigger Flag Register
Figure 14-137. ETFLG Register
15

14

13

12

11

10

9

8

3
SOCB
R-0h

2
SOCA
R-0h

1
RESERVED
R=0-0h

0
INT
R-0h

RESERVED
R=0-0h
7

6

5

4

RESERVED
R=0-0h

Table 14-76. ETFLG Register Field Descriptions
Bit
15-4
3

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

SOCB

R

0h

Latched ePWM ADC Start-of-Conversion A (EPWMxSOCB) Status
Flag
Unlike the ETFLG[INT] flag, the EPWMxSOCB output will continue
to pulse even if the flag bit is set.
0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on
EPWMxSOCB. The EPWMxSOCB output will continue to be
generated even if the flag bit is set.
Reset type: SYSRSn

2

SOCA

R

0h

Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status
Flag
Unlike the ETFLG[INT] flag, the EPWMxSOCA output will continue
to pulse even if the flag bit is set.
0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on
EPWMxSOCA. The EPWMxSOCA output will continue to be
generated even if the flag bit is set.
Reset type: SYSRSn

1

RESERVED

R=0

0h

Reserved

0

INT

R

0h

Latched ePWM Interrupt (EPWMx_INT) Status Flag
0: Indicates no event occurred
1: Indicates that an ePWMx interrupt (EPWMx_INT) was generated.
No further interrupts will be generated until the flag bit is cleared. Up
to one interrupt can be pending while the ETFLG[INT] bit is still set.
If an interrupt is pending, it will not be generated until after the
ETFLG[INT] bit is cleared.
Reset type: SYSRSn

1866

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.62 ETCLR Register (Offset = AAh) [reset = 0h]
ETCLR is shown in Figure 14-138 and described in Table 14-77.
Return to Summary Table.
Event Trigger Clear Register
Figure 14-138. ETCLR Register
15

14

13

12

11

10

9

8

3
SOCB
R=0/W=1-0h

2
SOCA
R=0/W=1-0h

1
RESERVED
R=0-0h

0
INT
R=0/W=1-0h

RESERVED
R=0-0h
7

6

5

4

RESERVED
R=0-0h

Table 14-77. ETCLR Register Field Descriptions
Bit
15-4
3

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

SOCB

R=0/W=1

0h

ePWM ADC Start-of-Conversion A (EPWMxSOCB) Flag Clear Bit
0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[SOCB] flag bit
Reset type: SYSRSn

2

SOCA

R=0/W=1

0h

ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit
0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[SOCA] flag bit
Reset type: SYSRSn

1

RESERVED

R=0

0h

Reserved

0

INT

R=0/W=1

0h

ePWM Interrupt (EPWMx_INT) Flag Clear Bit
0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[INT] flag bit and enable further interrupts
pulses to be generated
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1867

Registers

www.ti.com

14.14.2.63 ETFRC Register (Offset = ACh) [reset = 0h]
ETFRC is shown in Figure 14-139 and described in Table 14-78.
Return to Summary Table.
Event Trigger Force Register
Figure 14-139. ETFRC Register
15

14

13

12

11

10

9

8

3
SOCB
R=0/W=1-0h

2
SOCA
R=0/W=1-0h

1
RESERVED
R=0-0h

0
INT
R=0/W=1-0h

RESERVED
R=0-0h
7

6

5

4

RESERVED
R=0-0h

Table 14-78. ETFRC Register Field Descriptions
Bit
15-4
3

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

SOCB

R=0/W=1

0h

SOCB Force Bit
The SOCB pulse will only be generated if the event is enabled in the
ETSEL register. The ETFLG[SOCB] flag bit will be set regardless.
0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates a pulse on EPWMxSOCB and set the SOCBFLG bit.
This bit is used for test purposes.
Reset type: SYSRSn

2

SOCA

R=0/W=1

0h

SOCA Force Bit
The SOCA pulse will only be generated if the event is enabled in the
ETSEL register. The ETFLG[SOCA] flag bit will be set regardless.
0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates a pulse on EPWMxSOCA and set the SOCAFLG bit.
This bit is used for test purposes.
Reset type: SYSRSn

1

RESERVED

R=0

0h

Reserved

0

INT

R=0/W=1

0h

INT Force Bit
The interrupt will only be generated if the event is enabled in the
ETSEL register. The INT flag bit will be set regardless.
0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates an interrupt on EPWMxINT and set the INT flag bit.
This bit is used for test purposes.
Reset type: SYSRSn

1868

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.64 ETINTPS Register (Offset = AEh) [reset = 0h]
ETINTPS is shown in Figure 14-140 and described in Table 14-79.
Return to Summary Table.
Event-Trigger Interrupt Pre-Scale Register
Figure 14-140. ETINTPS Register
15

14

13

12

11

10

3

2

9

8

1

0

RESERVED
R=0-0h
7

6

5

4

INTCNT2
R-0h

INTPRD2
R/W-0h

Table 14-79. ETINTPS Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R=0

0h

Reserved

7-4

INTCNT2

R

0h

EPWMxINT Counter 2
When ETPS[INTPSSEL]=1, these bits indicate how many selected
events have occurred:
0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events
Reset type: SYSRSn

3-0

INTPRD2

R/W

0h

EPWMxINT Period 2 Select
When ETPS[INTPSSEL] = 1, these bits select how many selected
events need to occur before an interrupt is generated:
0000: Disable counter
0001: Generate interrupt on INTCNT = 1 (first event)
0010: Generate interrupt on INTCNT = 2 (second event)
0011: Generate interrupt on INTCNT = 3 (third event)
0100: Generate interrupt on INTCNT = 4 (fourth event)
...
1111: Generate interrupt on INTCNT = 15 (fifteenth event)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1869

Registers

www.ti.com

14.14.2.65 ETSOCPS Register (Offset = B0h) [reset = 0h]
ETSOCPS is shown in Figure 14-141 and described in Table 14-80.
Return to Summary Table.
Event-Trigger SOC Pre-Scale Register
Figure 14-141. ETSOCPS Register
15

14

13

12

11

10

SOCBCNT2
R-0h
7

6

9

8

1

0

SOCBPRD2
R/W-0h
5

4

3

2

SOCACNT2
R-0h

SOCAPRD2
R/W-0h

Table 14-80. ETSOCPS Register Field Descriptions
Bit
15-12

Field

Type

Reset

Description

SOCBCNT2

R

0h

EPWMxSOCB Counter 2
When ETPS[SOCPSSEL] = 1, these bits indicate how many selected
events have occurred:
0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events
Reset type: SYSRSn

11-8

SOCBPRD2

R/W

0h

EPWMxSOCB Period 2 Select
When ETPS[SOCPSSEL] = 1, these bits select how many selected
event need to occur before an SOCB pulse is generated:
0000: Disable counter
0001: Generate interrupt on SOCBCNT2 = 1 (first event)
0010: Generate interrupt on SOCBCNT2 = 2 (second event)
0011: Generate interrupt on SOCBCNT2 = 3 (third event)
0100: Generate interrupt on SOCBCNT2 = 4 (fourth event)
...
1111: Generate interrupt on SOCBCNT2 = 15 (fifteenth event)
Reset type: SYSRSn

7-4

SOCACNT2

R

0h

EPWMxSOCA Counter 2
When ETPS[SOCPSSEL] = 1, these bits indicate how many selected
events have occurred:
0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events
Reset type: SYSRSn

1870

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-80. ETSOCPS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

SOCAPRD2

R/W

0h

EPWMxSOCA Period 2 Select
When ETPS[SOCPSSEL] = 1, these bits select how many selected
event need to occur before an SOCA pulse is generated:
0000: Disable counter
0001: Generate interrupt on SOCACNT2 = 1 (first event)
0010: Generate interrupt on SOCACNT2 = 2 (second event)
0011: Generate interrupt on SOCACNT2 = 3 (third event)
0100: Generate interrupt on SOCACNT2 = 4 (fourth event)
...
1111: Generate interrupt on SOCACNT2 = 15 (fifteenth event)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1871

Registers

www.ti.com

14.14.2.66 ETCNTINITCTL Register (Offset = B2h) [reset = 0h]
ETCNTINITCTL is shown in Figure 14-142 and described in Table 14-81.
Return to Summary Table.
Event-Trigger Counter Initialization Control Register
Figure 14-142. ETCNTINITCTL Register
15
SOCBINITEN
R/W-0h

14
SOCAINITEN
R/W-0h

13
INTINITEN
R/W-0h

12
SOCBINITFRC
R/W-0h

11
SOCAINITFRC
R/W-0h

10
INTINITFRC
R/W-0h

9

7

6

5

4

3

2

1

8
RESERVED
R=0-0h
0

RESERVED
R=0-0h

Table 14-81. ETCNTINITCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SOCBINITEN

R/W

0h

EPWMxSOCB Counter 2 Initialization Enable
0: Has no effect.
1: Enable initialization of EPWMxSOCB counter with contents of
ETCNTINIT[SOCBINIT] on a SYNC event or software force.
Reset type: SYSRSn

14

SOCAINITEN

R/W

0h

EPWMxSOCA Counter 2 Initialization Enable
0: Has no effect.
1: Enable initialization of EPWMxSOCA counter with contents of
ETCNTINIT[SOCAINIT] on a SYNC event or software force.
Reset type: SYSRSn

13

INTINITEN

R/W

0h

EPWMxINT Counter 2 Initialization Enable
0: Has no effect.
1: Enable initialization of EPWMxINT counter 2 with contents of
ETCNTINIT[INTINIT] on a SYNC event or software force.
Reset type: SYSRSn

12

SOCBINITFRC

R/W

0h

EPWMxSOCB Counter 2 Initialization Force
0: Has no effect.
1: This bit forces the ET EPWMxSOCB counter to be initialized with
the contents of ETCNTINIT[SOCBINIT].
Reset type: SYSRSn

11

SOCAINITFRC

R/W

0h

EPWMxSOCA Counter 2 Initialization Force
0: Has no effect.
1: This bit forces the ET EPWMxSOCA counter to be initialized with
the contents of ETCNTINIT[SOCAINIT].
Reset type: SYSRSn

10

INTINITFRC

R/W

0h

EPWMxINT Counter 2 Initialization Force
0: Has no effect.
1: This bit forces the ET EPWMxINT counter to be initialized with the
contents of ETCNTINIT[INTINIT].
Reset type: SYSRSn

9-0

1872

RESERVED

R=0

Enhanced Pulse Width Modulator (ePWM)

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.67 ETCNTINIT Register (Offset = B4h) [reset = 0h]
ETCNTINIT is shown in Figure 14-143 and described in Table 14-82.
Return to Summary Table.
Event-Trigger Counter Initialization Register
Figure 14-143. ETCNTINIT Register
15

14

13

12

11

10

RESERVED
R-0h
7

6

9

8

1

0

SOCBINIT
R/W-0h
5

4

3

2

SOCAINIT
R/W-0h

INTINIT
R/W-0h

Table 14-82. ETCNTINIT Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-8

SOCBINIT

R/W

0h

EPWMxSOCB Counter 2 Initialization Bits
The ET EPWMxSOCB counter is initialized with the contents of this
register on an ePWM SYNC event or a software force.
Reset type: SYSRSn

7-4

SOCAINIT

R/W

0h

EPWMxSOCA Counter 2 Initialization Bits
The ET EPWMxSOCA counter is initialized with the contents of this
register on an ePWM SYNC event or a software force.
Reset type: SYSRSn

3-0

INTINIT

R/W

0h

EPWMxINT Counter 2 Initialization Bits
The ET EPWMxINT counter is initialized with the contents of this
register on an ePWM SYNC event or a software force.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1873

Registers

www.ti.com

14.14.2.68 DCTRIPSEL Register (Offset = C0h) [reset = 0h]
DCTRIPSEL is shown in Figure 14-144 and described in Table 14-83.
Return to Summary Table.
Digital Compare Trip Select Register
Figure 14-144. DCTRIPSEL Register
15

14
13
DCBLCOMPSEL
R/W-0h

12

11

10
9
DCBHCOMPSEL
R/W-0h

8

7

6
5
DCALCOMPSEL
R/W-0h

4

3

2
1
DCAHCOMPSEL
R/W-0h

0

Table 14-83. DCTRIPSEL Register Field Descriptions
Bit
15-12

Field

Type

Reset

Description

DCBLCOMPSEL

R/W

0h

Digital Compare B Low Input Select Bits
0000: TRIPIN1 and (TZ1 input)
0001: TRIPIN2 and (TZ2 input)
0010: TRIPIN3 and (TZ3 input)
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by
DCBLTRIPSEL register ORed together)
Reset type: SYSRSn

11-8

DCBHCOMPSEL

R/W

0h

Digital Compare B High Input Select Bits
0000: TRIPIN1 and (TZ1 input)
0001: TRIPIN2 and (TZ2 input)
0010: TRIPIN3 and (TZ3 input)
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by
DCBHTRIPSEL register ORed together)
Reset type: SYSRSn

1874

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-83. DCTRIPSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-4

DCALCOMPSEL

R/W

0h

Digital Compare A Low Input Select Bits
0000: TRIPIN1 and (TZ1 input)
0001: TRIPIN2 and (TZ2 input)
0010: TRIPIN3 and (TZ3 input)
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by
DCALTRIPSEL register ORed together)
Reset type: SYSRSn

3-0

DCAHCOMPSEL

R/W

0h

Digital Compare A High Input Select Bits
0000: TRIPIN1 and (TZ1 input)
0001: TRIPIN2 and (TZ2 input)
0010: TRIPIN3 and (TZ3 input)
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by
DCAHTRIPSEL register ORed together)
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1875

Registers

www.ti.com

14.14.2.69 DCACTL Register (Offset = C3h) [reset = 0h]
DCACTL is shown in Figure 14-145 and described in Table 14-84.
Return to Summary Table.
Digital Compare A Control Register
Figure 14-145. DCACTL Register
15
EVT2LAT

14
13
EVT2LATCLRSEL

12
EVT2LATSEL

11

10

R-0h

R/W-0h

R/W-0h

7
EVT1LAT

6
5
EVT1LATCLRSEL

4
EVT1LATSEL

3
EVT1SYNCE

2
EVT1SOCE

R-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

RESERVED
R=0-0h

9
EVT2FRCSYN
CSEL
R/W-0h

8
EVT2SRCSEL

1
EVT1FRCSYN
CSEL
R/W-0h

0
EVT1SRCSEL

R/W-0h

R/W-0h

Table 14-84. DCACTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

EVT2LAT

R

0h

Indicates the status of DCAEVT2LAT siganal.
Reset type: SYSRSn

EVT2LATCLRSEL

R/W

0h

DCAEVT2 Latched clear source select:

14-13

00 CNT_ZERO event clears DCAEVT2 latch.
01 PRD_EQ event clears DCAEVT2 latch.
10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch.
11 Reserved.
Reset type: SYSRSn
12

EVT2LATSEL

R/W

0h

DCAEVT2 Latched signal select:
0 Does not select the DCAEVT2 latched signal (Refer figure
"Modifications to DCAEVT1.force/DCAEVT2.force generation.") as
source of DCAEVT2.force.
1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force.
Reset type: SYSRSn

11-10
9

RESERVED

R=0

0h

Reserved

EVT2FRCSYNCSEL

R/W

0h

DCAEVT2 Force Synchronization Signal Select
0: Source Is Synchronous Signal
1: Source Is Asynchronous Signal
Reset type: SYSRSn

8

EVT2SRCSEL

R/W

0h

DCAEVT2 Source Signal Select
0: Source Is DCAEVT2 Signal
1: Source Is DCEVTFILT Signal
Reset type: SYSRSn

7
6-5

EVT1LAT

R

0h

Indicates the status of DCAEVT1LAT signal.
Reset type: SYSRSn

EVT1LATCLRSEL

R/W

0h

DCAEVT1 Latched clear source select:
00 CNT_ZERO event clears DCAEVT1 latch.
01 PRD_EQ event clears DCAEVT1 latch.
10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch.
11 Reserved.
Reset type: SYSRSn

1876

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-84. DCACTL Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

EVT1LATSEL

R/W

0h

DCAEVT1 Latched signal select:
0 Does not select the DCAEVT1 latched signal (Refer figure
"Modifications to DCAEVT1.force/DCAEVT2.force generation.") as
source of DCAEVT1.force.
1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force.
Reset type: SYSRSn

3

EVT1SYNCE

R/W

0h

DCAEVT1 SYNC, Enable/Disable
0: SYNC Generation Disabled
1: SYNC Generation Enabled
Reset type: SYSRSn

2

EVT1SOCE

R/W

0h

DCAEVT1 SOC, Enable/Disable
0: SOC Generation Disabled
1: SOC Generation Enabled
Reset type: SYSRSn

1

EVT1FRCSYNCSEL

R/W

0h

DCAEVT1 Force Synchronization Signal Select
0: Source is passed through asynchronously
1: Source is synchronized with EPWMCLK
Reset type: SYSRSn

0

EVT1SRCSEL

R/W

0h

DCAEVT1 Source Signal Select
0: Source Is DCAEVT1 Signal
1: Source Is DCEVTFILT Signal
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1877

Registers

www.ti.com

14.14.2.70 DCBCTL Register (Offset = C4h) [reset = 0h]
DCBCTL is shown in Figure 14-146 and described in Table 14-85.
Return to Summary Table.
Digital Compare B Control Register
Figure 14-146. DCBCTL Register
15
EVT2LAT

14
13
EVT2LATCLRSEL

12
EVT2LATSEL

11

10

R-0h

R/W-0h

R/W-0h

7
EVT1LAT

6
5
EVT1LATCLRSEL

4
EVT1LATSEL

3
EVT1SYNCE

2
EVT1SOCE

R-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

RESERVED
R=0-0h

9
EVT2FRCSYN
CSEL
R/W-0h

8
EVT2SRCSEL

1
EVT1FRCSYN
CSEL
R/W-0h

0
EVT1SRCSEL

R/W-0h

R/W-0h

Table 14-85. DCBCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

EVT2LAT

R

0h

Indicates the status of DCBEVT2LAT siganal.
Reset type: SYSRSn

EVT2LATCLRSEL

R/W

0h

DCBEVT2 Latched clear source select:

14-13

00 CNT_ZERO event clears DCBEVT2 latch.
01 PRD_EQ event clears DCBEVT2 latch.
10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch.
11 Reserved.
Reset type: SYSRSn
12

EVT2LATSEL

R/W

0h

DCBEVT2 Latched signal select:
0 Does not select the DCBEVT2 latched signal (Refer figure
"Modifications to DCBEVT1.force/DCBEVT2.force generation.") as
source of DCBEVT2.force.
1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force.
Reset type: SYSRSn

11-10
9

RESERVED

R=0

0h

Reserved

EVT2FRCSYNCSEL

R/W

0h

DCBEVT2 Force Synchronization Signal Select
0: Source Is Synchronous Signal
1: Source Is Asynchronous Signal
Reset type: SYSRSn

8

EVT2SRCSEL

R/W

0h

DCBEVT2 Source Signal Select
0: Source Is DCBEVT2 Signal
1: Source Is DCEVTFILT Signal
Reset type: SYSRSn

7
6-5

EVT1LAT

R

0h

Indicates the status of DCBEVT1LAT signal.
Reset type: SYSRSn

EVT1LATCLRSEL

R/W

0h

DCBEVT1 Latched clear source select:
00 CNT_ZERO event clears DCBEVT1 latch.
01 PRD_EQ event clears DCBEVT1 latch.
10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch.
11 Reserved.
Reset type: SYSRSn

1878

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-85. DCBCTL Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

EVT1LATSEL

R/W

0h

DCBEVT1 Latched signal select:
0 Does not select the DCBEVT1 latched signal (Refer figure
"Modifications to DCBEVT1.force/DCBEVT2.force generation.") as
source of DCBEVT1.force.
1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force.
Reset type: SYSRSn

3

EVT1SYNCE

R/W

0h

DCBEVT1 SYNC, Enable/Disable
0: SYNC Generation Disabled
1: SYNC Generation Enabled
Reset type: SYSRSn

2

EVT1SOCE

R/W

0h

DCBEVT1 SOC, Enable/Disable
0: SOC Generation Disabled
1: SOC Generation Enabled
Reset type: SYSRSn

1

EVT1FRCSYNCSEL

R/W

0h

DCBEVT1 Force Synchronization Signal Select
0: Source Is Synchronous Signal
1: Source Is Asynchronous Signal
Reset type: SYSRSn

0

EVT1SRCSEL

R/W

0h

DCBEVT1 Source Signal Select
0: Source Is DCBEVT1 Signal
1: Source Is DCEVTFILT Signal
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1879

Registers

www.ti.com

14.14.2.71 DCFCTL Register (Offset = C7h) [reset = 0h]
DCFCTL is shown in Figure 14-147 and described in Table 14-86.
Return to Summary Table.
Digital Compare Filter Control Register
Figure 14-147. DCFCTL Register
15

7
RESERVED
R=0-0h

14
EDGESTATUS
R-0h

13

6
EDGEFILTSEL
R/W-0h

5

12

4
PULSESEL
R/W-0h

11
EDGECOUNT
R/W-0h

10

3
BLANKINV
R/W-0h

2
BLANKE
R/W-0h

9

8
EDGEMODE
R/W-0h

1

0
SRCSEL
R/W-0h

Table 14-86. DCFCTL Register Field Descriptions
Field

Type

Reset

Description

15-13

Bit

EDGESTATUS

R

0h

Edge Status:
Reset type: SYSRSn

12-10

EDGECOUNT

R/W

0h

Edge Count: These bits select how many edges to count before
generating a TBCLK wide pulse on the DCEVTFILT signal:
Reset type: SYSRSn

9-8

EDGEMODE

R/W

0h

Edge Mode Select:
Reset type: SYSRSn

7

RESERVED

R=0

0h

Reserved

6

EDGEFILTSEL

R/W

0h

Edge Filter Select:
Reset type: SYSRSn

PULSESEL

R/W

0h

Pulse Select For Blanking & Capture Alignment

5-4

00: Time-base counter equal to period (TBCTR = TBPRD)
01: Time-base counter equal to zero (TBCTR = 0x00)
10: Time-base counter equal to zero (TBCTR = 0x00) or period
(TBCTR = TBPRD)
11: Reserved
Reset type: SYSRSn
3

BLANKINV

R/W

0h

Blanking Window Inversion
0: Blanking window not inverted
1: Blanking window inverted
Reset type: SYSRSn

2

BLANKE

R/W

0h

Blanking Window Enable/Disable
0: Blanking window is disabled
1: Blanking window is enabled
Reset type: SYSRSn

1-0

SRCSEL

R/W

0h

Filter Block Signal Source Select
00: Source Is DCAEVT1 Signal
01: Source Is DCAEVT2 Signal
10: Source Is DCBEVT1 Signal
11: Source Is DCBEVT2 Signal
Reset type: SYSRSn

1880

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.72 DCCAPCTL Register (Offset = C8h) [reset = 0h]
DCCAPCTL is shown in Figure 14-148 and described in Table 14-87.
Return to Summary Table.
Digital Compare Capture Control Register
Figure 14-148. DCCAPCTL Register
15
CAPMODE
R/W-0h

14
CAPCLR
R=0/W=1-0h

13
CAPSTS
R-0h

12

11

10
RESERVED
R=0-0h

9

8

7

6

5

4

3

2

1
SHDWMODE
R/W-0h

0
CAPE
R/W-0h

RESERVED
R=0-0h

Table 14-87. DCCAPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

CAPMODE

R/W

0h

Counter Capture Mode
0: When a DCEVTFILT occurs and the counter capture is enabled,
then the current TBCNT value is captured in the active register.
When the respective trip event occurs, further trip (capture) events
are ignored until the next PRD_eq or CNT_zero event (as selected
by the PULSESEL bit in the DCFCTL register) re-triggers the capture
mechanism.
If active mode is enabled, via SHDWMODE bit in DCCAPCTL
register, CPU reads of this register will return the active register
value.
If shadow mode is enabled, via SHDWMODE bit in DCCAPCTL
register, the active register is copied to the shadow register on the
PRD_eq or CNT_zero event (whichever is selected by PULSESEL
bit in DCFCTL register). CPU reads of this register will return the
shadow register value.
1: When a DCEVTFILT occurs and the counter capture is enabled,
then the current TBCNT value is captured in the active register.
When the respective trip event occurs - it will set the CAPSTS flag
and further trip (capture) events are ignored until this bit is cleared.
CAPSTS can be cleared by writing to CAPCLR bit in DCCAPCTL
register and it re-triggers the capture mechanism.
If active mode is enabled, via SHDWMODE bit in DCCAPCTL
register, CPU reads of this register will return the active register
value.
If shadow mode is enabled, via SHDWMODE bit in DCCAPCTL
register, the active register is copied to the shadow register on the
PRD_eq or CNT_zero event (whichever is selected by PULSESEL
bit in DCFCTL register). CPU reads of this register will return the
shadow register value.
Reset type: SYSRSn

14

CAPCLR

R=0/W=1

0h

DC Capture Latched Status Clear Flag
0: Writing a 0 has no effect.
1: Writing a 1 will clear this CAPSTS (set) condition.
Reset type: SYSRSn

13

CAPSTS

R

0h

Latched Status Flag for Capture Event
0: No DC capture event occurred.
1: A DC capture event has occurred.
Reset type: SYSRSn

12-2

RESERVED

R=0

0h

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Reserved

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1881

Registers

www.ti.com

Table 14-87. DCCAPCTL Register Field Descriptions (continued)
Bit
1

Field

Type

Reset

Description

SHDWMODE

R/W

0h

TBCTR Counter Capture Shadow Select Mode
0: Enable shadow mode. The DCCAP active register is copied to
shadow register on a TBCTR = TBPRD or TBCTR = zero event as
defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP
register will return the shadow register contents.
1: Active Mode. In this mode the shadow register is disabled. CPU
reads from the DCCAP register will always return the active register
contents.
Reset type: SYSRSn

0

CAPE

R/W

0h

TBCTR Counter Capture Enable/Disable
0: Disable the time-base counter capture.
1: Enable the time-base counter capture.
Reset type: SYSRSn

1882

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.73 DCFOFFSET Register (Offset = C9h) [reset = 0h]
DCFOFFSET is shown in Figure 14-149 and described in Table 14-88.
Return to Summary Table.
Digital Compare Filter Offset Register
Figure 14-149. DCFOFFSET Register
15

14

13

12

11

10

9

8
7
DCFOFFSET
R/W-0h

6

5

4

3

2

1

0

Table 14-88. DCFOFFSET Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

DCFOFFSET

R/W

0h

Blanking Window Offset
These 16-bits specify the number of TBCLK cycles from the blanking
window reference to the point when the blanking window is applied.
The blanking window reference is either period or zero as defined by
the DCFCTL[PULSESEL] bit. This offset register is shadowed and
the active register is loaded at the reference point defined by
DCFCTL[PULSESEL]. The offset counter is also initialized and
begins to count down when the active register is loaded. When the
counter expires, the blanking window is applied. If the blanking
window is currently active, then the blanking window counter is
restarted.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1883

Registers

www.ti.com

14.14.2.74 DCFOFFSETCNT Register (Offset = CAh) [reset = 0h]
DCFOFFSETCNT is shown in Figure 14-150 and described in Table 14-89.
Return to Summary Table.
Digital Compare Filter Offset Counter Register
Figure 14-150. DCFOFFSETCNT Register
15

14

13

12

11

10

9

8
7
DCFOFFSETCNT
R-0h

6

5

4

3

2

1

0

Table 14-89. DCFOFFSETCNT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

DCFOFFSETCNT

R

0h

Blanking Offset Counter
These 16-bits are read only and indicate the current value of the
offset counter. The counter counts down to zero and then stops until
it is re-loaded on the next period or zero event as defined by the
DCFCTL[PULSESEL] bit. The offset counter is not affected by the
free/soft emulation bits. That is, it will always continue to count down
if the device is halted by a emulation stop.
Reset type: SYSRSn

1884

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.75 DCFWINDOW Register (Offset = CBh) [reset = 0h]
DCFWINDOW is shown in Figure 14-151 and described in Table 14-90.
Return to Summary Table.
Digital Compare Filter Window Register
Figure 14-151. DCFWINDOW Register
15

14

13

12

11

10

9

8
7
DCFWINDOW
R/W-0h

6

5

4

3

2

1

0

Table 14-90. DCFWINDOW Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

DCFWINDOW

R/W

0h

Blanking Window Width
00h: No blanking window is generated.
01-FFh: Specifies the width of the blanking window in TBCLK cycles.
The blanking window begins when the offset counter expires. When
this occurs, the window counter is loaded and begins to count down.
If the blanking window is currently active and the offset counter
expires, the blanking window counter is not restarted and the
blanking window is cut short prematurely. Care should be taken to
avoid this situation. The blanking window can cross a PWM period
boundary.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1885

Registers

www.ti.com

14.14.2.76 DCFWINDOWCNT Register (Offset = CCh) [reset = 0h]
DCFWINDOWCNT is shown in Figure 14-152 and described in Table 14-91.
Return to Summary Table.
Digital Compare Filter Window Counter Register
Figure 14-152. DCFWINDOWCNT Register
15

14

13

12

11

10

9

8
7
DCFWINDOWCNT
R-0h

6

5

4

3

2

1

0

Table 14-91. DCFWINDOWCNT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

DCFWINDOWCNT

R

0h

Blanking Window Counter
These 16 bits are read only and indicate the current value of the
window counter. The counter counts down to zero and then stops
until it is re-loaded when the offset counter reaches zero again.
Reset type: SYSRSn

1886

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.77 DCCAP Register (Offset = CFh) [reset = 0h]
DCCAP is shown in Figure 14-153 and described in Table 14-92.
Return to Summary Table.
Digital Compare Counter Capture Register
Figure 14-153. DCCAP Register
15

14

13

12

11

10

9

8
7
DCCAP
R-0h

6

5

4

3

2

1

0

Table 14-92. DCCAP Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

DCCAP

R

0h

Digital Compare Time-Base Counter Capture
To enable time-base counter capture, set the DCCAPCLT[CAPE] bit
to 1. If enabled, reflects the value of the time-base counter (TBCTR)
on the low to high edge transition of a filtered (DCEVTFLT) event.
Further capture events are ignored until the next period or zero as
selected by the DCFCTL[PULSESEL] bit. Shadowing of DCCAP is
enabled and disabled by the DCCAPCTL[SHDWMODE] bit. By
default this register is shadowed.
- If DCCAPCTL[SHDWMODE] = 0, then the shadow is enabled. In
this mode, the active register is copied to the shadow register on the
TBCTR = TBPRD or TBCTR = zero as defined by the
DCFCTL[PULSESEL] bit. CPU reads of this register will return the
shadow register value.
- If DCCAPCTL[SHDWMODE] = 1, then the shadow register is
disabled. In this mode, CPU reads will return the active register
value. The active and shadow registers share the same memory
map address.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1887

Registers

www.ti.com

14.14.2.78 DCAHTRIPSEL Register (Offset = D2h) [reset = 0h]
DCAHTRIPSEL is shown in Figure 14-154 and described in Table 14-93.
Return to Summary Table.
Digital Compare AH Trip Select
Figure 14-154. DCAHTRIPSEL Register
15
RESERVED
R-0h

14
TRIPINPUT15
R/W-0h

13
TRIPINPUT14
R/W-0h

12
RESERVED
R-0h

11
TRIPINPUT12
R/W-0h

10
TRIPINPUT11
R/W-0h

9
TRIPINPUT10
R/W-0h

8
TRIPINPUT9
R/W-0h

7
TRIPINPUT8
R/W-0h

6
TRIPINPUT7
R/W-0h

5
TRIPINPUT6
R/W-0h

4
TRIPINPUT5
R/W-0h

3
TRIPINPUT4
R/W-0h

2
TRIPINPUT3
R/W-0h

1
TRIPINPUT2
R/W-0h

0
TRIPINPUT1
R/W-0h

Table 14-93. DCAHTRIPSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

TRIPINPUT15

R/W

0h

TRIP Input 15
0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

13

TRIPINPUT14

R/W

0h

TRIP Input 14
0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

12

RESERVED

R

0h

Reserved

11

TRIPINPUT12

R/W

0h

TRIP Input 12
0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

10

TRIPINPUT11

R/W

0h

TRIP Input 11
0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

9

TRIPINPUT10

R/W

0h

TRIP Input 10
0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

8

TRIPINPUT9

R/W

0h

TRIP Input 9
0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

7

TRIPINPUT8

R/W

0h

TRIP Input 8
0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

1888

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-93. DCAHTRIPSEL Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

TRIPINPUT7

R/W

0h

TRIP Input 7
0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

5

TRIPINPUT6

R/W

0h

TRIP Input 6
0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

4

TRIPINPUT5

R/W

0h

TRIP Input 5
0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

3

TRIPINPUT4

R/W

0h

TRIP Input 4
0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

2

TRIPINPUT3

R/W

0h

TRIP Input 3
0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

1

TRIPINPUT2

R/W

0h

TRIP Input 2
0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

0

TRIPINPUT1

R/W

0h

TRIP Input 1
0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1889

Registers

www.ti.com

14.14.2.79 DCALTRIPSEL Register (Offset = D3h) [reset = 0h]
DCALTRIPSEL is shown in Figure 14-155 and described in Table 14-94.
Return to Summary Table.
Digital Compare AL Trip Select
Figure 14-155. DCALTRIPSEL Register
15
RESERVED
R-0h

14
TRIPINPUT15
R/W-0h

13
TRIPINPUT14
R/W-0h

12
RESERVED
R-0h

11
TRIPINPUT12
R/W-0h

10
TRIPINPUT11
R/W-0h

9
TRIPINPUT10
R/W-0h

8
TRIPINPUT9
R/W-0h

7
TRIPINPUT8
R/W-0h

6
TRIPINPUT7
R/W-0h

5
TRIPINPUT6
R/W-0h

4
TRIPINPUT5
R/W-0h

3
TRIPINPUT4
R/W-0h

2
TRIPINPUT3
R/W-0h

1
TRIPINPUT2
R/W-0h

0
TRIPINPUT1
R/W-0h

Table 14-94. DCALTRIPSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

TRIPINPUT15

R/W

0h

TRIP Input 15
0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

13

TRIPINPUT14

R/W

0h

TRIP Input 14
0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

12

RESERVED

R

0h

Reserved

11

TRIPINPUT12

R/W

0h

TRIP Input 12
0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

10

TRIPINPUT11

R/W

0h

TRIP Input 11
0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

9

TRIPINPUT10

R/W

0h

TRIP Input 10
0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

8

TRIPINPUT9

R/W

0h

TRIP Input 9
0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

7

TRIPINPUT8

R/W

0h

TRIP Input 8
0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

1890

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-94. DCALTRIPSEL Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

TRIPINPUT7

R/W

0h

TRIP Input 7
0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

5

TRIPINPUT6

R/W

0h

TRIP Input 6
0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

4

TRIPINPUT5

R/W

0h

TRIP Input 5
0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

3

TRIPINPUT4

R/W

0h

TRIP Input 4
0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

2

TRIPINPUT3

R/W

0h

TRIP Input 3
0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

1

TRIPINPUT2

R/W

0h

TRIP Input 2
0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

0

TRIPINPUT1

R/W

0h

TRIP Input 1
0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1891

Registers

www.ti.com

14.14.2.80 DCBHTRIPSEL Register (Offset = D4h) [reset = 0h]
DCBHTRIPSEL is shown in Figure 14-156 and described in Table 14-95.
Return to Summary Table.
Digital Compare BH Trip Select
Figure 14-156. DCBHTRIPSEL Register
15
RESERVED
R-0h

14
TRIPINPUT15
R/W-0h

13
TRIPINPUT14
R/W-0h

12
RESERVED
R-0h

11
TRIPINPUT12
R/W-0h

10
TRIPINPUT11
R/W-0h

9
TRIPINPUT10
R/W-0h

8
TRIPINPUT9
R/W-0h

7
TRIPINPUT8
R/W-0h

6
TRIPINPUT7
R/W-0h

5
TRIPINPUT6
R/W-0h

4
TRIPINPUT5
R/W-0h

3
TRIPINPUT4
R/W-0h

2
TRIPINPUT3
R/W-0h

1
TRIPINPUT2
R/W-0h

0
TRIPINPUT1
R/W-0h

Table 14-95. DCBHTRIPSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

TRIPINPUT15

R/W

0h

TRIP Input 15
0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

13

TRIPINPUT14

R/W

0h

TRIP Input 14
0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

12

RESERVED

R

0h

Reserved

11

TRIPINPUT12

R/W

0h

TRIP Input 12
0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

10

TRIPINPUT11

R/W

0h

TRIP Input 11
0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

9

TRIPINPUT10

R/W

0h

TRIP Input 10
0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

8

TRIPINPUT9

R/W

0h

TRIP Input 9
0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

7

TRIPINPUT8

R/W

0h

TRIP Input 8
0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

1892

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-95. DCBHTRIPSEL Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

TRIPINPUT7

R/W

0h

TRIP Input 7
0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

5

TRIPINPUT6

R/W

0h

TRIP Input 6
0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

4

TRIPINPUT5

R/W

0h

TRIP Input 5
0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

3

TRIPINPUT4

R/W

0h

TRIP Input 4
0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

2

TRIPINPUT3

R/W

0h

TRIP Input 3
0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

1

TRIPINPUT2

R/W

0h

TRIP Input 2
0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

0

TRIPINPUT1

R/W

0h

TRIP Input 1
0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1893

Registers

www.ti.com

14.14.2.81 DCBLTRIPSEL Register (Offset = D5h) [reset = 0h]
DCBLTRIPSEL is shown in Figure 14-157 and described in Table 14-96.
Return to Summary Table.
Digital Compare BL Trip Select
Figure 14-157. DCBLTRIPSEL Register
15
RESERVED
R-0h

14
TRIPINPUT15
R/W-0h

13
TRIPINPUT14
R/W-0h

12
RESERVED
R-0h

11
TRIPINPUT12
R/W-0h

10
TRIPINPUT11
R/W-0h

9
TRIPINPUT10
R/W-0h

8
TRIPINPUT9
R/W-0h

7
TRIPINPUT8
R/W-0h

6
TRIPINPUT7
R/W-0h

5
TRIPINPUT6
R/W-0h

4
TRIPINPUT5
R/W-0h

3
TRIPINPUT4
R/W-0h

2
TRIPINPUT3
R/W-0h

1
TRIPINPUT2
R/W-0h

0
TRIPINPUT1
R/W-0h

Table 14-96. DCBLTRIPSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

TRIPINPUT15

R/W

0h

TRIP Input 15
0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

13

TRIPINPUT14

R/W

0h

TRIP Input 14
0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

12

RESERVED

R

0h

Reserved

11

TRIPINPUT12

R/W

0h

TRIP Input 12
0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

10

TRIPINPUT11

R/W

0h

TRIP Input 11
0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

9

TRIPINPUT10

R/W

0h

TRIP Input 10
0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

8

TRIPINPUT9

R/W

0h

TRIP Input 9
0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

7

TRIPINPUT8

R/W

0h

TRIP Input 8
0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

1894

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-96. DCBLTRIPSEL Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

TRIPINPUT7

R/W

0h

TRIP Input 7
0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

5

TRIPINPUT6

R/W

0h

TRIP Input 6
0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

4

TRIPINPUT5

R/W

0h

TRIP Input 5
0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

3

TRIPINPUT4

R/W

0h

TRIP Input 4
0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

2

TRIPINPUT3

R/W

0h

TRIP Input 3
0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

1

TRIPINPUT2

R/W

0h

TRIP Input 2
0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

0

TRIPINPUT1

R/W

0h

TRIP Input 1
0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1895

Registers

www.ti.com

14.14.2.82 EPWMLOCK Register (Offset = FAh) [reset = 0h]
EPWMLOCK is shown in Figure 14-158 and described in Table 14-97.
Return to Summary Table.
EPWM Lock Register
Figure 14-158. EPWMLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
TZCLRLOCK
R/WOnce-0h

2
TZCFGLOCK
R/WOnce-0h

1
GLLOCK
R/WOnce-0h

0
HRLOCK
R/WOnce-0h

KEY
R=0/W-0h
23

22

21

20
KEY
R=0/W-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED
R-0h

5

4
DCLOCK
R/WOnce-0h

Table 14-97. EPWMLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

KEY

R=0/W

0h

Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: SYSRSn

15-5
4

RESERVED

R

0h

Reserved

DCLOCK

R/WOnce

0h

0:Digital Compare registers from 0xC0 to 0xD5 offsets are protected
by EALLOW.
1: Digital Compare registers from 0xC0 and 0xD5 offsets are locked
and not writable.
Reset type: SYSRSn

3

TZCLRLOCK

R/WOnce

0h

0:Digital Compare registers from 0x97 to 0x9B offsets are protected
by EALLOW.
1: Digital Compare registers from 0x97 and 0x9B offsets are locked
and not writable.
Reset type: SYSRSn

2

TZCFGLOCK

R/WOnce

0h

0:TripZone registers from 0x80 to 0x8D offsets are protected by
EALLOW.
1: TripZone registers from 0x80 and 0x8D offsets are locked and not
writable.
Reset type: SYSRSn

1

GLLOCK

R/WOnce

0h

0:TripZone registers from 0x34 to 0x35 offsets are protected by
EALLOW.
1: TripZone registers from 0x34 to 0x35 offsets are locked and not
writable
Reset type: SYSRSn

1896

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-97. EPWMLOCK Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

HRLOCK

R/WOnce

0h

0: HRPWM registers from 0x20 to 0x2D offsets are protected by
EALLOW
1: HRPWM registers from 0x20 and 0x2D offsets are locked and not
writable.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1897

Registers

www.ti.com

14.14.2.83 HWVDELVAL Register (Offset = FDh) [reset = 0h]
HWVDELVAL is shown in Figure 14-159 and described in Table 14-98.
Return to Summary Table.
Hardware Valley Mode Delay Register
Figure 14-159. HWVDELVAL Register
15

14

13

12

11

10

9

8
7
HWVDELVAL
R-0h

6

5

4

3

2

1

0

Table 14-98. HWVDELVAL Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

HWVDELVAL

R

0h

Hardware Valley Delay Value Register
This read only register reflects the hardware delay value calculated
by the equations defined in VCAPCTL[VDELAYDIV]. This reflects
the latest value from the hardware calculations and can change
every time valley capture sequence is triggered and VCAP1 and
VCAP2 values are updated.
Reset type: SYSRSn

1898

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.2.84 VCNTVAL Register (Offset = FEh) [reset = 0h]
VCNTVAL is shown in Figure 14-160 and described in Table 14-99.
Return to Summary Table.
Hardware Valley Counter Register
Figure 14-160. VCNTVAL Register
15

14

13

12

11

10

9

8
7
VCNTVAL
R-0h

6

5

4

3

2

1

0

Table 14-99. VCNTVAL Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

VCNTVAL

R

0h

Valley Time Base Counter Register
This registers reflects the captured VCNT value upon occurrence of
STOPEDGE selected in VCNTCFG register.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1899

Registers

www.ti.com

14.14.3 EPWM_XBAR_REGS Registers
Table 14-100 lists the memory-mapped registers for the EPWM_XBAR_REGS. All register offset
addresses not listed in Table 14-100 should be considered as reserved locations and the register contents
should not be modified.
Table 14-100. EPWM_XBAR_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

TRIP4MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP4

EALLOW

Go

2h

TRIP4MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP4

EALLOW

Go

4h

TRIP5MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP5

EALLOW

Go

6h

TRIP5MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP5

EALLOW

Go

8h

TRIP7MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP7

EALLOW

Go

Ah

TRIP7MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP7

EALLOW

Go

Ch

TRIP8MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP8

EALLOW

Go

Eh

TRIP8MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP8

EALLOW

Go

10h

TRIP9MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP9

EALLOW

Go

12h

TRIP9MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP9

EALLOW

Go

14h

TRIP10MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP10

EALLOW

Go

16h

TRIP10MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP10

EALLOW

Go

18h

TRIP11MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP11

EALLOW

Go

1Ah

TRIP11MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP11

EALLOW

Go

1Ch

TRIP12MUX0TO15CFG

ePWM XBAR Mux Configuration for TRIP12

EALLOW

Go

1Eh

TRIP12MUX16TO31CFG

ePWM XBAR Mux Configuration for TRIP12

EALLOW

Go

20h

TRIP4MUXENABLE

ePWM XBAR Mux Enable for TRIP4

EALLOW

Go

22h

TRIP5MUXENABLE

ePWM XBAR Mux Enable for TRIP5

EALLOW

Go

24h

TRIP7MUXENABLE

ePWM XBAR Mux Enable for TRIP7

EALLOW

Go

26h

TRIP8MUXENABLE

ePWM XBAR Mux Enable for TRIP8

EALLOW

Go

28h

TRIP9MUXENABLE

ePWM XBAR Mux Enable for TRIP9

EALLOW

Go

2Ah

TRIP10MUXENABLE

ePWM XBAR Mux Enable for TRIP10

EALLOW

Go

2Ch

TRIP11MUXENABLE

ePWM XBAR Mux Enable for TRIP11

EALLOW

Go

2Eh

TRIP12MUXENABLE

ePWM XBAR Mux Enable for TRIP12

EALLOW

Go

38h

TRIPOUTINV

ePWM XBAR Output Inversion Register

EALLOW

Go

3Eh

TRIPLOCK

ePWM XBAR Configuration Lock register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 14-101 shows the codes that are
used for access types in this section.
Table 14-101. EPWM_XBAR_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
1900

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-101. EPWM_XBAR_REGS Access Type
Codes (continued)
Access Type

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1901

Registers

www.ti.com

14.14.3.1 TRIP4MUX0TO15CFG Register (Offset = 0h) [reset = 0h]
TRIP4MUX0TO15CFG is shown in Figure 14-161 and described in Table 14-102.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP4
Figure 14-161. TRIP4MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 14-102. TRIP4MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1902

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-102. TRIP4MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1903

Registers

www.ti.com

Table 14-102. TRIP4MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1904

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.2 TRIP4MUX16TO31CFG Register (Offset = 2h) [reset = 0h]
TRIP4MUX16TO31CFG is shown in Figure 14-162 and described in Table 14-103.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP4
Figure 14-162. TRIP4MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

MUX17
R/W-0h

2

0

MUX16
R/W-0h

Table 14-103. TRIP4MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1905

Registers

www.ti.com

Table 14-103. TRIP4MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1906

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-103. TRIP4MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP4 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1907

Registers

www.ti.com

14.14.3.3 TRIP5MUX0TO15CFG Register (Offset = 4h) [reset = 0h]
TRIP5MUX0TO15CFG is shown in Figure 14-163 and described in Table 14-104.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP5
Figure 14-163. TRIP5MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 14-104. TRIP5MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1908

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-104. TRIP5MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1909

Registers

www.ti.com

Table 14-104. TRIP5MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1910

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.4 TRIP5MUX16TO31CFG Register (Offset = 6h) [reset = 0h]
TRIP5MUX16TO31CFG is shown in Figure 14-164 and described in Table 14-105.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP5
Figure 14-164. TRIP5MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

MUX17
R/W-0h

2

0

MUX16
R/W-0h

Table 14-105. TRIP5MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1911

Registers

www.ti.com

Table 14-105. TRIP5MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1912

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-105. TRIP5MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP5 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1913

Registers

www.ti.com

14.14.3.5 TRIP7MUX0TO15CFG Register (Offset = 8h) [reset = 0h]
TRIP7MUX0TO15CFG is shown in Figure 14-165 and described in Table 14-106.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP7
Figure 14-165. TRIP7MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 14-106. TRIP7MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1914

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-106. TRIP7MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1915

Registers

www.ti.com

Table 14-106. TRIP7MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1916

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.6 TRIP7MUX16TO31CFG Register (Offset = Ah) [reset = 0h]
TRIP7MUX16TO31CFG is shown in Figure 14-166 and described in Table 14-107.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP7
Figure 14-166. TRIP7MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

MUX17
R/W-0h

2

0

MUX16
R/W-0h

Table 14-107. TRIP7MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1917

Registers

www.ti.com

Table 14-107. TRIP7MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1918

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-107. TRIP7MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP7 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1919

Registers

www.ti.com

14.14.3.7 TRIP8MUX0TO15CFG Register (Offset = Ch) [reset = 0h]
TRIP8MUX0TO15CFG is shown in Figure 14-167 and described in Table 14-108.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP8
Figure 14-167. TRIP8MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 14-108. TRIP8MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1920

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-108. TRIP8MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1921

Registers

www.ti.com

Table 14-108. TRIP8MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1922

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.8 TRIP8MUX16TO31CFG Register (Offset = Eh) [reset = 0h]
TRIP8MUX16TO31CFG is shown in Figure 14-168 and described in Table 14-109.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP8
Figure 14-168. TRIP8MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

MUX17
R/W-0h

2

0

MUX16
R/W-0h

Table 14-109. TRIP8MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1923

Registers

www.ti.com

Table 14-109. TRIP8MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1924

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-109. TRIP8MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP8 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1925

Registers

www.ti.com

14.14.3.9 TRIP9MUX0TO15CFG Register (Offset = 10h) [reset = 0h]
TRIP9MUX0TO15CFG is shown in Figure 14-169 and described in Table 14-110.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP9
Figure 14-169. TRIP9MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 14-110. TRIP9MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1926

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-110. TRIP9MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1927

Registers

www.ti.com

Table 14-110. TRIP9MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1928

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.10 TRIP9MUX16TO31CFG Register (Offset = 12h) [reset = 0h]
TRIP9MUX16TO31CFG is shown in Figure 14-170 and described in Table 14-111.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP9
Figure 14-170. TRIP9MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

MUX17
R/W-0h

2

0

MUX16
R/W-0h

Table 14-111. TRIP9MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1929

Registers

www.ti.com

Table 14-111. TRIP9MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1930

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-111. TRIP9MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP9 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1931

Registers

www.ti.com

14.14.3.11 TRIP10MUX0TO15CFG Register (Offset = 14h) [reset = 0h]
TRIP10MUX0TO15CFG is shown in Figure 14-171 and described in Table 14-112.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP10
Figure 14-171. TRIP10MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 14-112. TRIP10MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1932

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-112. TRIP10MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1933

Registers

www.ti.com

Table 14-112. TRIP10MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1934

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.12 TRIP10MUX16TO31CFG Register (Offset = 16h) [reset = 0h]
TRIP10MUX16TO31CFG is shown in Figure 14-172 and described in Table 14-113.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP10
Figure 14-172. TRIP10MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

MUX17
R/W-0h

2

0

MUX16
R/W-0h

Table 14-113. TRIP10MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1935

Registers

www.ti.com

Table 14-113. TRIP10MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1936

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-113. TRIP10MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP10 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1937

Registers

www.ti.com

14.14.3.13 TRIP11MUX0TO15CFG Register (Offset = 18h) [reset = 0h]
TRIP11MUX0TO15CFG is shown in Figure 14-173 and described in Table 14-114.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP11
Figure 14-173. TRIP11MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 14-114. TRIP11MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1938

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-114. TRIP11MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1939

Registers

www.ti.com

Table 14-114. TRIP11MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1940

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.14 TRIP11MUX16TO31CFG Register (Offset = 1Ah) [reset = 0h]
TRIP11MUX16TO31CFG is shown in Figure 14-174 and described in Table 14-115.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP11
Figure 14-174. TRIP11MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

MUX17
R/W-0h

2

0

MUX16
R/W-0h

Table 14-115. TRIP11MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1941

Registers

www.ti.com

Table 14-115. TRIP11MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1942

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-115. TRIP11MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP11 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1943

Registers

www.ti.com

14.14.3.15 TRIP12MUX0TO15CFG Register (Offset = 1Ch) [reset = 0h]
TRIP12MUX0TO15CFG is shown in Figure 14-175 and described in Table 14-116.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP12
Figure 14-175. TRIP12MUX0TO15CFG Register
31
30
MUX15
R/W-0h

29
28
MUX14
R/W-0h

27
26
MUX13
R/W-0h

25
24
MUX12
R/W-0h

23
22
MUX11
R/W-0h

21
20
MUX10
R/W-0h

19

15

13

11

9

7

5

3

14
MUX7
R/W-0h

12
MUX6
R/W-0h

10
MUX5
R/W-0h

MUX4
R/W-0h

8

6

MUX3
R/W-0h

4

MUX2
R/W-0h

18
MUX9
R/W-0h
MUX1
R/W-0h

2

17

16
MUX8
R/W-0h

1

0

MUX0
R/W-0h

Table 14-116. TRIP12MUX0TO15CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX15

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux15:
00 : Select .0 input for Mux15
01 : Select .1 input for Mux15
10 : Select .2 input for Mux15
11 : Select .3 input for Mux15
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX14

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux14:
00 : Select .0 input for Mux14
01 : Select .1 input for Mux14
10 : Select .2 input for Mux14
11 : Select .3 input for Mux14
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX13

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux13:
00 : Select .0 input for Mux13
01 : Select .1 input for Mux13
10 : Select .2 input for Mux13
11 : Select .3 input for Mux13
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX12

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux12:
00 : Select .0 input for Mux12
01 : Select .1 input for Mux12
10 : Select .2 input for Mux12
11 : Select .3 input for Mux12
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1944

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-116. TRIP12MUX0TO15CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX11

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux11:
00 : Select .0 input for Mux11
01 : Select .1 input for Mux11
10 : Select .2 input for Mux11
11 : Select .3 input for Mux11
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX10

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux10:
00 : Select .0 input for Mux10
01 : Select .1 input for Mux10
10 : Select .2 input for Mux10
11 : Select .3 input for Mux10
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX9

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux9:
00 : Select .0 input for Mux9
01 : Select .1 input for Mux9
10 : Select .2 input for Mux9
11 : Select .3 input for Mux9
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX8

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux8:
00 : Select .0 input for Mux8
01 : Select .1 input for Mux8
10 : Select .2 input for Mux8
11 : Select .3 input for Mux8
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX7

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux7:
00 : Select .0 input for Mux7
01 : Select .1 input for Mux7
10 : Select .2 input for Mux7
11 : Select .3 input for Mux7
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX6

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux6:
00 : Select .0 input for Mux6
01 : Select .1 input for Mux6
10 : Select .2 input for Mux6
11 : Select .3 input for Mux6
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1945

Registers

www.ti.com

Table 14-116. TRIP12MUX0TO15CFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11-10

MUX5

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux5:
00 : Select .0 input for Mux5
01 : Select .1 input for Mux5
10 : Select .2 input for Mux5
11 : Select .3 input for Mux5
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX4

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux4:
00 : Select .0 input for Mux4
01 : Select .1 input for Mux4
10 : Select .2 input for Mux4
11 : Select .3 input for Mux4
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX3

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux3:
00 : Select .0 input for Mux3
01 : Select .1 input for Mux3
10 : Select .2 input for Mux3
11 : Select .3 input for Mux3
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX2

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux2:
00 : Select .0 input for Mux2
01 : Select .1 input for Mux2
10 : Select .2 input for Mux2
11 : Select .3 input for Mux2
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX1

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux1:
00 : Select .0 input for Mux1
01 : Select .1 input for Mux1
10 : Select .2 input for Mux1
11 : Select .3 input for Mux1
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX0

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux0:
00 : Select .0 input for Mux0
01 : Select .1 input for Mux0
10 : Select .2 input for Mux0
11 : Select .3 input for Mux0
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1946

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.16 TRIP12MUX16TO31CFG Register (Offset = 1Eh) [reset = 0h]
TRIP12MUX16TO31CFG is shown in Figure 14-176 and described in Table 14-117.
Return to Summary Table.
ePWM XBAR Mux Configuration for TRIP12
Figure 14-176. TRIP12MUX16TO31CFG Register
31
30
MUX31
R/W-0h

29
28
MUX30
R/W-0h

27
26
MUX29
R/W-0h

25
24
MUX28
R/W-0h

23
22
MUX27
R/W-0h

21
20
MUX26
R/W-0h

19
18
MUX25
R/W-0h

17
16
MUX24
R/W-0h

15
14
MUX23
R/W-0h

13
12
MUX22
R/W-0h

11
10
MUX21
R/W-0h

9

7

5

3

1

MUX20
R/W-0h

8

6

MUX19
R/W-0h

4

MUX18
R/W-0h

MUX17
R/W-0h

2

0

MUX16
R/W-0h

Table 14-117. TRIP12MUX16TO31CFG Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

MUX31

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux31:
00 : Select .0 input for Mux31
01 : Select .1 input for Mux31
10 : Select .2 input for Mux31
11 : Select .3 input for Mux31
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29-28

MUX30

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux30:
00 : Select .0 input for Mux30
01 : Select .1 input for Mux30
10 : Select .2 input for Mux30
11 : Select .3 input for Mux30
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

27-26

MUX29

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux29:
00 : Select .0 input for Mux29
01 : Select .1 input for Mux29
10 : Select .2 input for Mux29
11 : Select .3 input for Mux29
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25-24

MUX28

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux28:
00 : Select .0 input for Mux28
01 : Select .1 input for Mux28
10 : Select .2 input for Mux28
11 : Select .3 input for Mux28
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1947

Registers

www.ti.com

Table 14-117. TRIP12MUX16TO31CFG Register Field Descriptions (continued)
Bit
23-22

Field

Type

Reset

Description

MUX27

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux27:
00 : Select .0 input for Mux27
01 : Select .1 input for Mux27
10 : Select .2 input for Mux27
11 : Select .3 input for Mux27
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21-20

MUX26

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux26:
00 : Select .0 input for Mux26
01 : Select .1 input for Mux26
10 : Select .2 input for Mux26
11 : Select .3 input for Mux26
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19-18

MUX25

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux25:
00 : Select .0 input for Mux25
01 : Select .1 input for Mux25
10 : Select .2 input for Mux25
11 : Select .3 input for Mux25
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17-16

MUX24

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux24:
00 : Select .0 input for Mux24
01 : Select .1 input for Mux24
10 : Select .2 input for Mux24
11 : Select .3 input for Mux24
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15-14

MUX23

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux23:
00 : Select .0 input for Mux23
01 : Select .1 input for Mux23
10 : Select .2 input for Mux23
11 : Select .3 input for Mux23
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

13-12

MUX22

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux22:
00 : Select .0 input for Mux22
01 : Select .1 input for Mux22
10 : Select .2 input for Mux22
11 : Select .3 input for Mux22
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1948

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-117. TRIP12MUX16TO31CFG Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

MUX21

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux21:
00 : Select .0 input for Mux21
01 : Select .1 input for Mux21
10 : Select .2 input for Mux21
11 : Select .3 input for Mux21
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9-8

MUX20

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux20:
00 : Select .0 input for Mux20
01 : Select .1 input for Mux20
10 : Select .2 input for Mux20
11 : Select .3 input for Mux20
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7-6

MUX19

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux19:
00 : Select .0 input for Mux19
01 : Select .1 input for Mux19
10 : Select .2 input for Mux19
11 : Select .3 input for Mux19
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5-4

MUX18

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux18:
00 : Select .0 input for Mux18
01 : Select .1 input for Mux18
10 : Select .2 input for Mux18
11 : Select .3 input for Mux18
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3-2

MUX17

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux17:
00 : Select .0 input for Mux17
01 : Select .1 input for Mux17
10 : Select .2 input for Mux17
11 : Select .3 input for Mux17
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1-0

MUX16

R/W

0h

Select Bits for EPWM-XBAR TRIP12 Mux16:
00 : Select .0 input for Mux16
01 : Select .1 input for Mux16
10 : Select .2 input for Mux16
11 : Select .3 input for Mux16
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1949

Registers

www.ti.com

14.14.3.17 TRIP4MUXENABLE Register (Offset = 20h) [reset = 0h]
TRIP4MUXENABLE is shown in Figure 14-177 and described in Table 14-118.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP4
Figure 14-177. TRIP4MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 14-118. TRIP4MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1950

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-118. TRIP4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1951

Registers

www.ti.com

Table 14-118. TRIP4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1952

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-118. TRIP4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1953

Registers

www.ti.com

Table 14-118. TRIP4MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of Mux0 to drive TRIP4 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP4 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP4 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1954

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.18 TRIP5MUXENABLE Register (Offset = 22h) [reset = 0h]
TRIP5MUXENABLE is shown in Figure 14-178 and described in Table 14-119.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP5
Figure 14-178. TRIP5MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 14-119. TRIP5MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1955

Registers

www.ti.com

Table 14-119. TRIP5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1956

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-119. TRIP5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1957

Registers

www.ti.com

Table 14-119. TRIP5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1958

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-119. TRIP5MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP5 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP5 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP5 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1959

Registers

www.ti.com

14.14.3.19 TRIP7MUXENABLE Register (Offset = 24h) [reset = 0h]
TRIP7MUXENABLE is shown in Figure 14-179 and described in Table 14-120.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP7
Figure 14-179. TRIP7MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 14-120. TRIP7MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1960

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-120. TRIP7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1961

Registers

www.ti.com

Table 14-120. TRIP7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1962

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-120. TRIP7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1963

Registers

www.ti.com

Table 14-120. TRIP7MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP7 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP7 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP7 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1964

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.20 TRIP8MUXENABLE Register (Offset = 26h) [reset = 0h]
TRIP8MUXENABLE is shown in Figure 14-180 and described in Table 14-121.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP8
Figure 14-180. TRIP8MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 14-121. TRIP8MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1965

Registers

www.ti.com

Table 14-121. TRIP8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1966

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-121. TRIP8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1967

Registers

www.ti.com

Table 14-121. TRIP8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1968

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-121. TRIP8MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP8 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP8 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP8 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1969

Registers

www.ti.com

14.14.3.21 TRIP9MUXENABLE Register (Offset = 28h) [reset = 0h]
TRIP9MUXENABLE is shown in Figure 14-181 and described in Table 14-122.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP9
Figure 14-181. TRIP9MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 14-122. TRIP9MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1970

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-122. TRIP9MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1971

Registers

www.ti.com

Table 14-122. TRIP9MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1972

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-122. TRIP9MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1973

Registers

www.ti.com

Table 14-122. TRIP9MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP9 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP9 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP9 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1974

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.22 TRIP10MUXENABLE Register (Offset = 2Ah) [reset = 0h]
TRIP10MUXENABLE is shown in Figure 14-182 and described in Table 14-123.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP10
Figure 14-182. TRIP10MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 14-123. TRIP10MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1975

Registers

www.ti.com

Table 14-123. TRIP10MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1976

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-123. TRIP10MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1977

Registers

www.ti.com

Table 14-123. TRIP10MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1978

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-123. TRIP10MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP10 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP10 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP10 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1979

Registers

www.ti.com

14.14.3.23 TRIP11MUXENABLE Register (Offset = 2Ch) [reset = 0h]
TRIP11MUXENABLE is shown in Figure 14-183 and described in Table 14-124.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP11
Figure 14-183. TRIP11MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 14-124. TRIP11MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1980

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-124. TRIP11MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1981

Registers

www.ti.com

Table 14-124. TRIP11MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1982

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-124. TRIP11MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1983

Registers

www.ti.com

Table 14-124. TRIP11MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP11 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP11 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP11 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1984

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.3.24 TRIP12MUXENABLE Register (Offset = 2Eh) [reset = 0h]
TRIP12MUXENABLE is shown in Figure 14-184 and described in Table 14-125.
Return to Summary Table.
ePWM XBAR Mux Enable for TRIP12
Figure 14-184. TRIP12MUXENABLE Register
31
MUX31
R/W-0h

30
MUX30
R/W-0h

29
MUX29
R/W-0h

28
MUX28
R/W-0h

27
MUX27
R/W-0h

26
MUX26
R/W-0h

25
MUX25
R/W-0h

24
MUX24
R/W-0h

23
MUX23
R/W-0h

22
MUX22
R/W-0h

21
MUX21
R/W-0h

20
MUX20
R/W-0h

19
MUX19
R/W-0h

18
MUX18
R/W-0h

17
MUX17
R/W-0h

16
MUX16
R/W-0h

15
MUX15
R/W-0h

14
MUX14
R/W-0h

13
MUX13
R/W-0h

12
MUX12
R/W-0h

11
MUX11
R/W-0h

10
MUX10
R/W-0h

9
MUX9
R/W-0h

8
MUX8
R/W-0h

7
MUX7
R/W-0h

6
MUX6
R/W-0h

5
MUX5
R/W-0h

4
MUX4
R/W-0h

3
MUX3
R/W-0h

2
MUX2
R/W-0h

1
MUX1
R/W-0h

0
MUX0
R/W-0h

Table 14-125. TRIP12MUXENABLE Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MUX31

R/W

0h

Selects the output of Mux31 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux31 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux31 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

30

MUX30

R/W

0h

Selects the output of Mux30 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux30 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux30 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

29

MUX29

R/W

0h

Selects the output of Mux29 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux29 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux29 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

28

MUX28

R/W

0h

Selects the output of Mux28 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux28 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux28 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1985

Registers

www.ti.com

Table 14-125. TRIP12MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

27

MUX27

R/W

0h

Selects the output of Mux27 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux27 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux27 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

26

MUX26

R/W

0h

Selects the output of Mux26 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux26 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux26 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

25

MUX25

R/W

0h

Selects the output of Mux25 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux25 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux25 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

24

MUX24

R/W

0h

Selects the output of Mux24 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux24 is enabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux24 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

23

MUX23

R/W

0h

Selects the output of Mux23 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux23 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux23 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

22

MUX22

R/W

0h

Selects the output of Mux22 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux22 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux22 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

21

MUX21

R/W

0h

Selects the output of Mux21 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux21 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux21 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1986

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-125. TRIP12MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

20

MUX20

R/W

0h

Selects the output of Mux20 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux20 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux20 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

19

MUX19

R/W

0h

Selects the output of Mux19 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux19 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux19 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

18

MUX18

R/W

0h

Selects the output of Mux18 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux18 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux18 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

17

MUX17

R/W

0h

Selects the output of Mux17 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux17 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux17 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

16

MUX16

R/W

0h

Selects the output of Mux16 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux16 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux16 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

15

MUX15

R/W

0h

Selects the output of Mux15 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux15 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux15 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

14

MUX14

R/W

0h

Selects the output of Mux14 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux14 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux14 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1987

Registers

www.ti.com

Table 14-125. TRIP12MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

13

MUX13

R/W

0h

Selects the output of Mux13 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux13 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux13 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

12

MUX12

R/W

0h

Selects the output of Mux12 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux12 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux12 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

11

MUX11

R/W

0h

Selects the output of Mux11 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux11 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux11 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

10

MUX10

R/W

0h

Selects the output of Mux10 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux10 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux10 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

9

MUX9

R/W

0h

Selects the output of Mux9 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux9 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux9 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

8

MUX8

R/W

0h

Selects the output of Mux8 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux8 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux8 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

7

MUX7

R/W

0h

Selects the output of Mux7 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux7 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux7 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1988

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-125. TRIP12MUXENABLE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

MUX6

R/W

0h

Selects the output of Mux6 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux6 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux6 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

MUX5

R/W

0h

Selects the output of Mux5 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux5 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux5 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

MUX4

R/W

0h

Selects the output of Mux4 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux4 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux4 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

3

MUX3

R/W

0h

Selects the output of Mux3 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux3 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux3 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

MUX2

R/W

0h

Selects the output of Mux2 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux2 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux2 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

MUX1

R/W

0h

Selects the output of Mux1 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux1 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux1 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

MUX0

R/W

0h

Selects the output of mux0 to drive TRIP12 of EPWM-XBAR
0: Respective output of Mux0 is disabled to drive the TRIP12 of
EPWM-XBAR
1: Respective output of Mux0 is enabled to drive the TRIP12 of
EPWM-XBAR
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1989

Registers

www.ti.com

14.14.3.25 TRIPOUTINV Register (Offset = 38h) [reset = 0h]
TRIPOUTINV is shown in Figure 14-185 and described in Table 14-126.
Return to Summary Table.
ePWM XBAR Output Inversion Register
Figure 14-185. TRIPOUTINV Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
TRIP8
R/W-0h

2
TRIP7
R/W-0h

1
TRIP5
R/W-0h

0
TRIP4
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
TRIP12
R/W-0h

6
TRIP11
R/W-0h

5
TRIP10
R/W-0h

4
TRIP9
R/W-0h

Table 14-126. TRIPOUTINV Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R=0

0h

Reserved

15-8

RESERVED

R=0

0h

Reserved

TRIP12

R/W

0h

Selects polarity for TRIP12 of EPWM-XBAR

7

0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn
6

TRIP11

R/W

0h

Selects polarity for TRIP11 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

5

TRIP10

R/W

0h

Selects polarity for TRIP10 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

4

TRIP9

R/W

0h

Selects polarity for TRIP9 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1990

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-126. TRIPOUTINV Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

TRIP8

R/W

0h

Selects polarity for TRIP8 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

2

TRIP7

R/W

0h

Selects polarity for TRIP7 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

1

TRIP5

R/W

0h

Selects polarity for TRIP5 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

0

TRIP4

R/W

0h

Selects polarity for TRIP4 of EPWM-XBAR
0: drives active high output
1: drives active-low output
Refer to the EPWM X-BAR section of this chapter for more details.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1991

Registers

www.ti.com

14.14.3.26 TRIPLOCK Register (Offset = 3Eh) [reset = 0h]
TRIPLOCK is shown in Figure 14-186 and described in Table 14-127.
Return to Summary Table.
ePWM XBAR Configuration Lock register
Figure 14-186. TRIPLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
LOCK
R/WSOnce-0h

KEY
R=0/W=1-0h
23

22

21

20
KEY
R=0/W=1-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 14-127. TRIPLOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

KEY

R=0/W=1

0h

Bit-0 of this register can be set only if KEY= 0x5a5a
Reset type: CPU1.SYSRSn

15-1

RESERVED

R=0

0h

Reserved

LOCK

R/WSOnce

0h

Locks the configuration for EPWM-XBAR. Once the configuration is
locked, writes to the below registers for EPWM-XBAR is blocked.

0

Registers Affected by the LOCK mechanism:
EPWM-XBAROUTyMUX0TO15CFG
EPWM-XBAROUTyMUX16TO31CFG
EPWM-XBAROUTyMUXENABLE
EPWM-XBAROUTLATEN
EPWM-XBAROUTINV
0: Writes to the above registers are allowed
1: Writes to the above registers are blocked
Note:
[1] LOCK mechanism only apples to writes. Reads are never
blocked.
Reset type: CPU1.SYSRSn

1992

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.4 SYNC_SOC_REGS Registers
Table 14-128 lists the memory-mapped registers for the SYNC_SOC_REGS. All register offset addresses
not listed in Table 14-128 should be considered as reserved locations and the register contents should not
be modified.
Table 14-128. SYNC_SOC_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

SYNCSELECT

Sync Input and Output Select Register

EALLOW

Go

2h

ADCSOCOUTSELECT

External ADC (Off Chip) SOC Select Register

EALLOW

Go

4h

SYNCSOCLOCK

SYNCSEL and EXTADCSOC Select Lock
register

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 14-129 shows the codes that are
used for access types in this section.
Table 14-129. SYNC_SOC_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1993

Registers

www.ti.com

14.14.4.1 SYNCSELECT Register (Offset = 0h) [reset = 0h]
SYNCSELECT is shown in Figure 14-187 and described in Table 14-130.
Return to Summary Table.
Sync Input and Output Select Register
Figure 14-187. SYNCSELECT Register
31

23

30
RESERVED
R=0-0h

29

22

21

28

27

26

25
RESERVED
R=0-0h

24

19

18

17

16

12

11

10
ECAP1SYNCIN

9

8
EPWM10SYNC
IN
R/W-0h

4
EPWM7SYNCIN
R/W-0h

3

1
EPWM4SYNCIN
R/W-0h

0

SYNCOUT
R/W-0h
20
RESERVED
R=0-0h

15
RESERVED

14

R=0-0h

13
ECAP4SYNCIN
R/W-0h

7
6
EPWM10SYNCIN
R/W-0h

5

R/W-0h
2

Table 14-130. SYNCSELECT Register Field Descriptions
Field

Type

Reset

Description

31-29

Bit

RESERVED

R=0

0h

Reserved

28-27

SYNCOUT

R/W

0h

Select Syncout Source:
00: EPWM1SYNCOUT selected
01: EPWM4SYNCOUT selected
10: EPPW7SYNCOUT selected
11: EPWM10SYNCOUT selected
Reset type: CPU1.SYSRSn

26-16

RESERVED

R=0

0h

Reserved

15

RESERVED

R=0

0h

Reserved

ECAP4SYNCIN

R/W

0h

Selects Sync Input Source for ECAP4:

14-12

000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPPW7SYNCOUT selected
011: EPWM10SYNCOUT selected
100: ECAP1SYNCOUT selected
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn

1994

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-130. SYNCSELECT Register Field Descriptions (continued)
Bit
11-9

Field

Type

Reset

Description

ECAP1SYNCIN

R/W

0h

Selects Sync Input Source for ECAP1:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPPW7SYNCOUT selected
011: EPWM10SYNCOUT selected
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn

8-6

EPWM10SYNCIN

R/W

0h

Selects Sync Input Source for EPWM10:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPPW7SYNCOUT selected
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn

5-3

EPWM7SYNCIN

R/W

0h

Selects Sync Input Source for EPWM7:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPPW7SYNCOUT selected (Reserved)
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1995

Registers

www.ti.com

Table 14-130. SYNCSELECT Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2-0

EPWM4SYNCIN

R/W

0h

Selects Sync Input Source for EPWM4:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected (Reserved)
010: EPPW7SYNCOUT selected (Reserved)
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn

1996

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

14.14.4.2 ADCSOCOUTSELECT Register (Offset = 2h) [reset = 0h]
ADCSOCOUTSELECT is shown in Figure 14-188 and described in Table 14-131.
Return to Summary Table.
The ADCSOCAO and ADCSOCBO signals will be active low for 32 SYSCLK cycles. They can be used to
trigger a conversion on an external ADC.
Figure 14-188. ADCSOCOUTSELECT Register
31

30

29

28

RESERVED
R=0-0h
23
PWM8SOCBE
N
R/W-0h

22
PWM7SOCBE
N
R/W-0h

21
PWM6SOCBE
N
R/W-0h

20
PWM5SOCBE
N
R/W-0h

15

14

13

12

5
PWM6SOCAE
N
R/W-0h

4
PWM5SOCAE
N
R/W-0h

RESERVED
R=0-0h
7
PWM8SOCAE
N
R/W-0h

6
PWM7SOCAE
N
R/W-0h

27
26
25
PWM12SOCBE PWM11SOCBE PWM10SOCBE
N
N
N
R/W-0h
R/W-0h
R/W-0h

24
PWM9SOCBE
N
R/W-0h

19
PWM4SOCBE
N
R/W-0h

17
PWM2SOCBE
N
R/W-0h

16
PWM1SOCBE
N
R/W-0h

11
10
9
PWM12SOCAE PWM11SOCAE PWM10SOCAE
N
N
N
R/W-0h
R/W-0h
R/W-0h

8
PWM9SOCAE
N
R/W-0h

3
PWM4SOCAE
N
R/W-0h

0
PWM1SOCAE
N
R/W-0h

18
PWM3SOCBE
N
R/W-0h

2
PWM3SOCAE
N
R/W-0h

1
PWM2SOCAE
N
R/W-0h

Table 14-131. ADCSOCOUTSELECT Register Field Descriptions
Bit
31-28
27

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

PWM12SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

26

PWM11SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

25

PWM10SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

24

PWM9SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

23

PWM8SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1997

Registers

www.ti.com

Table 14-131. ADCSOCOUTSELECT Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

22

PWM7SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

21

PWM6SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

20

PWM5SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

19

PWM4SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

18

PWM3SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

17

PWM2SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

16

PWM1SOCBEN

R/W

0h

ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

15-12
11

RESERVED

R=0

0h

Reserved

PWM12SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

10

PWM11SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

9

PWM10SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

8

PWM9SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

1998

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 14-131. ADCSOCOUTSELECT Register Field Descriptions (continued)
Bit
7

Field

Type

Reset

Description

PWM8SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

6

PWM7SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

5

PWM6SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

4

PWM5SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

3

PWM4SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

2

PWM3SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

1

PWM2SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

0

PWM1SOCAEN

R/W

0h

ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Enhanced Pulse Width Modulator (ePWM)

Copyright © 2013–2017, Texas Instruments Incorporated

1999

Registers

www.ti.com

14.14.4.3 SYNCSOCLOCK Register (Offset = 4h) [reset = 0h]
SYNCSOCLOCK is shown in Figure 14-189 and described in Table 14-132.
Return to Summary Table.
SYNCSEL and EXTADCSOC Select Lock register
Figure 14-189. SYNCSOCLOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
ADCSOCOUTS
ELECT
R/WSOnce-0h

0
SYNCSELECT

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

R/WSOnce-0h

Table 14-132. SYNCSOCLOCK Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-2

RESERVED

R=0

0h

Reserved

ADCSOCOUTSELECT

R/WSOnce

0h

ADCSOCOUTSELECT Register Lock bit:

1

0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
0

SYNCSELECT

R/WSOnce

0h

SYNCSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn

2000

Enhanced Pulse Width Modulator (ePWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 15
SPRUHM8G – December 2013 – Revised September 2017

High-Resolution Pulse Width Modulator (HRPWM)
This document is used in conjunction with the device-specific Enhanced Pulse Width Modulator (ePWM)
Module Reference Guide. The HRPWM module described in this reference guide is a Type 2 HRPWM.
See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with an
HRPWM module of the same type, to determine the differences between types, and for a list of devicespecific differences within a type.
Topic

15.1
15.2
15.3

...........................................................................................................................

Page

Introduction ................................................................................................... 2002
Operational Description of HRPWM................................................................... 2004
Appendix A: SFO Library Software - SFO_TI_Build_V7.lib ................................... 2025

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2001

Introduction

www.ti.com

15.1 Introduction
This module extends the time resolution capabilities of the conventionally derived digital pulse width
modulator (PWM). HRPWM is typically used when PWM resolution falls below ~ 9-10 bits. The key
features of HRPWM are:
• Extended time resolution capability
• Used in both duty cycle and phase-shift control methods
• Finer time granularity control or edge positioning using extensions to the Compare A, Compare B and
Phase registers
• Implemented using the A & B signal path of PWM, that is, on the EPWMxA and EPWMxB output.
• Dead band high-resolution control for falling and rising edge delay in half cycle clocking operation
• Self-check diagnostics software mode to check if the micro edge positioner (MEP) logic is running
optimally
• Enables high resolution output swapping on the EPWMxA and EPWMxB output
• Enables high-resolution output on EPWMxB signal output via inversion of EPWMxA signal output
• Enables high-resolution period, duty and phase control on the EPWMxA and EPWMxB output on
devices with an ePWM module. See the device-specific data manual to determine if your device has
an ePWM module for high-resolution period support.
The ePWM peripheral is used to perform a function mathematically equivalent to a digital-to-analog
converter (DAC). As shown in Figure 15-1, the effective resolution for conventionally generated PWM is a
function of PWM frequency (or period) and system clock frequency.
Figure 15-1. Resolution Calculations for Conventionally Generated PWM
TPWM

PWM resolution (%) = FPWM/FEPWMCLK x 100%
PWM resolution (bits) = Log2 (TPWM/TEPWMCLK)

PWM
t
TEPWMCLK

If the required PWM operating frequency does not offer sufficient resolution in PWM mode, you may want
to consider HRPWM. As an example of improved performance offered by HRPWM, Table 15-1 shows
resolution in bits for various PWM frequencies. These values assume a MEP step size of 180 ps. See the
device-specific data sheet for typical and maximum performance specifications for the MEP.

2002High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

Table 15-1. Resolution for PWM and HRPWM
PWM Freq

Regular Resolution (PWM)

High Resolution (HRPWM)

100 MHz EPWMCLK
(kHz)

Bits

%

Bits

%

20

12.3

0.02

18.1

0.000

50

11

0.05

16.8

0.001

100

10

0.1

15.8

0.002

150

9.4

0.15

15.2

0.003

200

9

0.2

14.8

0.004

250

8.6

0.25

14.4

0.005

500

7.6

0.5

13.4

0.009

1000

6.6

1

12.4

0.018

1500

6.1

1.5

11.9

0.027

2000

5.6

2

11.4

0.036

Although each application may differ, typical low frequency PWM operation (below 250 kHz) may not
require HRPWM. HRPWM capability is most useful for high frequency PWM requirements of power
conversion topologies such as:
• Single-phase buck, boost, and flyback
• Multi-phase buck, boost, and flyback
• Phase-shifted full bridge
• Direct modulation of D-Class power amplifiers

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2003

Operational Description of HRPWM

www.ti.com

15.2 Operational Description of HRPWM
The HRPWM is based on micro edge positioner (MEP) technology. MEP logic is capable of positioning an
edge very finely by sub-dividing one coarse system clock of a conventional PWM generator. The time step
accuracy is on the order of 150 ps. See the device-specific data sheet for the typical MEP step size on a
particular device. The HRPWM also has a self-check software diagnostics mode to check if the MEP logic
is running optimally, under all operating conditions. Details on software diagnostics and functions are in
Section 15.2.6.
Figure 15-2 shows the relationship between one coarse system clock and edge position in terms of MEP
steps, which are controlled via an 8-bit field in the Compare A extension register (CMPAHR). The same
operating logic applies to CMPBHR as well.
Figure 15-2. Operating Logic Using MEP

(1 EPWMCLK cycle)

+ 0.5 (rounding)

(upper 8 bits)
(0x0080 in Q8 format)

To generate an HRPWM waveform, configure the ePWM registers as you would to generate a
conventional PWM of a given frequency and polarity. The HRPWM works together with the ePWM
registers to extend edge resolution. Although many programming combinations are possible, only a few
are needed and practical. These methods are described in Section 15.2.7.
Registers discussed but not found in this document can be seen in the device-specific Enhanced Pulse
Width Modulator (ePWM) Module Reference Guide.

15.2.1 Controlling the HRPWM Capabilities
The MEP of the HRPWM is controlled by six extension registers. These HRPWM registers are
concatenated with the 16-bit TBPHS, TBPRD, CMPA, CMPBM, DBREDM & DBFEDM registers used to
control PWM operation.
• TBPHSHR - Time Base Phase High Resolution Register
• CMPAHR - Counter Compare A High Resolution Register
• TBPRDHR - Time Base Period High Resolution Register. (available on some devices)
• CMPBHR - Compare B High Resolution Register
• DBREDHR - Deadband Generator Rising Edge Delay High Resolution Register
• DBFEDHR - Deadband Generator Falling Edge Delay High Resolution Register

2004

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

Figure 15-3. HRPWM Extension Registers and Memory Configuration
31
TBPHSHR (8)

Reserved (8)

16 15
TBPHS (16)

8 7

0
Reserved(8)

TBPHSHR (8)

TBPHS (16)
Single 32-bit write
31

A

CMPAHR (8)

Reserved (8)

16 15
A

CMPA (16)

8 7
A

0
Reserved(8)

CMPAHR (8)

CMPAA (16)
Single 32-bit write

A

TBPRDHR (8)

31
Reserved (8)

16 15
TBPRD(16)

8 7
TBPRDHR (8)

0
Reserved(8)

TBPRDA (16)
Single 32-bit write

A

CMPBHR (8)

31
Reserved (8)

16 15
CMPB (16)

8 7
CMPBHR (8)

0
Reserved(8)

CMPBA (16)
Single 32-bit write

A

DBFEDHR (7)

31
Reserved (9)

9 8

16 15
DBFED(16)

DBFEDHR (7)

0
Reserved(8)

DBFEDA (16)
Single 32-bit write

A

DBREDHR (7)

31
Reserved (9)

16 15
DBRED(16)

9 8

DBREDHR(7)

0
Reserved(8)

DBREDA (16)
Single 32-bit write

A

Dependant upon your device, these registers may be mirrored and can be written to at two different memory
locations. Check the device-specific Technical Reference Manual's ePWM chapter for more details on how to read
and write to these locations.

NOTE: HRPWM capabilities on Deadband Rising Edge Delay and Falling Edge Delay is applicable
only during Dead Band half cycle clocking Operation. The number of MEP steps is half in
size [ bits 15:9 ]than duty and phase high resolution registers for the same reason

HRPWM capabilities are controlled using the Channel A & B PWM signal path. HRPWM support on the
Dead band signal path is available by properly configuring the HRCNFG2 register. Figure 15-4 shows how
the HRPWM interfaces with the 8-bit extension registers.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2005

Operational Description of HRPWM

www.ti.com

Figure 15-4. HRPWM System Interface
Time-Base (TB)
CTR=ZERO
TBPRD Shadow (24)

Sync
In/Out
Select
Mux

CTR=CMPB
TBPRDHR (8)

TBPRD Active (24)

Disabled

EPWMxSYNCO

8
CTR=PRD
TBCTL[SYNCOSEL]

TBCTL[PHSEN]
Counter
Up/Down
(16 Bit)

TBCTL[SWFSYNC]
(Software Forced
Sync)

CTR=ZERO
TBCTR
Active (16)

CTR=PRD

CTR_Dir

CTR=ZERO

TBPHSHR (8)
16

CTR=CMPA

Phase
Control

CTR=CMPB
CTR=CMPC
CTR=CMPD

Event
Trigger
and
Interrupt
(ET)

CTR_Dir

Counter Compare (CC)
CTR=CMPA

EPWMxINT

CTR=PRD or ZERO

8

TBPHS Active (24)

EPWMxSYNCI
DCAEVT1.sync
DCBEVT1.sync

Action
Qualifier
(AQ)

DCAEVT1.soc
DCBEVT1.soc

EPWMxSOCA
EPWMxSOCB
EPWMxSOCA
ADC
EPWMxSOCB

(A)
(A)

CMPAHR (8)
16
CMPA Active (24)
CMPA Shadow (24)

EPWMA

ePWMxA
Dead
Band
(DB)

CTR=CMPB
CMPBHR (8)
16

HiRes PWM (HRPWM)

CMPAHR (8)

PWM
Chopper
(PC)

Trip
Zone
(TZ)
ePWMxB

EPWMB
CMPB Active (24)
CMPB Shadow (24)

CMPBHR (8)
EPWMxTZINT
TZ1 to TZ3

TBCNT(16)
CTR=CMPC
CMPC[15-0]

16

CMPC Active (16)

EMUSTOP

CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter

CLOCKFAIL
(B)
EQEPxERR
DCAEVT1.force
DCAEVT2.force
DCBEVT1.force

CMPC Shadow (16)

DCBEVT2.force

(A)
(A)
(A)
(A)

TBCNT(16)
CTR=CMPD
CMPD[15-0]

16

CMPD Active (16)
CMPD Shadow (16)

A

2006

These events are generated by the ePWM digital compare (DC) submodule.

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

Figure 15-5. HRPWM Block Diagram
1

TBPHSHR(8)

2

CMPAHR(8)

HRPWM
Micro-edge Positioner
(MEP) Calibration Module

2

CMPBHR(8)

1

TBPRDHR(8)
Action
Qualifier
(AQ)

DBREDHR(7)

3

DBFEDHR(7)

3

HRMSTEP

HRCNFG/HRCNFG2

HRPWR

High- Resolution PWM (HRPWM)

EPWMxAO

EPWMA
Dead
band
(DB)

PWM
chopper
(PC)

EPWMB

Trip
zone
(TZ)
EPWMxBO

(1)

From ePWM Time-base (TB) submodule

(2)

From ePWM counter-compare (CC) submodule

(3)

From ePWM Deadband (DB) submodule

15.2.2 Configuring the HRPWM
Once the ePWM has been configured to provide conventional PWM of a given frequency and polarity, the
HRPWM is configured by programming the HRCNFG register in that particular ePWM module's register
space. This register provides the following configuration options:
Edge Mode — The MEP can be programmed to provide precise position control on the rising edge (RE),
falling edge (FE) or both edges (BE) at the same time. FE and RE are used for power topologies
requiring duty cycle control(CMPA or CMPB high-resolution control), while BE is used for topologies
requiring phase shifting, for example, phase shifted full bridge (TBPHS or TBPRD high-resolution
control).
Control Mode — The MEP is programmed to be controlled either from the CMPAHR / CMPBHR register
in case of duty cycle control or the TBPHSHR register (phase control). RE or FE control mode
should be used with CMPAHR or CMPBHR register. BE control mode should be used with
TBPHSHR register. When the MEP is controlled from the TBPRDHR register (period control) the
duty cycle and phase can also be controlled via their respective high-resolution registers.
Shadow Mode — This mode provides the same shadowing (double buffering) option as in regular PWM
mode. This option is valid only when operating from the CMPAHR, CMPBHR and TBPRDHR
registers and should be chosen to be the same as the regular load option for the CMPA, CMPB
register. If TBPHSHR is used, then this option has no effect.
High-Resolution B Signal Control — The B signal path of an ePWM channel can generate a highresolution output by outputting an inverted version of the high-resolution ePWMxA signal on the
ePWMxB pin. A Type 2 HRPWM module can also enable high-resolution features on the B signal
path indepedently of the A signal path as well.
Swap ePWMxA and ePWMxB Outputs — This mode enables the swapping of the high resolution A & B
outputs . The mode selection allows either A & B Outputs Unchanged or A Output Comes Out On B
and B Output Comes Out On A

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2007

Operational Description of HRPWM

www.ti.com

Auto-conversion Mode — This mode is used in conjunction with the scale factor optimization (SFO)
software only. For a type 2 HRPWM module, below is a description of the Auto-conversion Mode
taking CMPAHR as an example. If auto-conversion is enabled, CMPAHR =
fraction(PWMduty*PWMperiod)<<8. The scale factor optimization software will calculate the MEP
scale factor in background code and automatically update the HRMSTEP register with the
calculated number of MEP steps per coarse step. The MEP Calibration Module will then use the
values in the HRMSTEP and CMPAHR register to automatically calculate the appropriate number
of MEP steps represented by the fractional duty cycle and move the high-resolution ePWM signal
edge accordingly. If auto-conversion is disabled, the CMPAHR register behaves like a type 0
HRPWM module and CMPAHR = (fraction(PWMduty * PWMperiod) * MEP Scale Factor +
0.5)<<8). All calculations will need to be performed by user code in this mode, and the HRMSTEP
register is ignored. Auto-conversion for high-resolution period has the same behavior as autoconversion for high-resolution duty cycle. Auto-conversion must always be enabled for highresolution period mode.
NOTE: Auto-conversion Mode performs the calculation for CMPBHR , DBREDHR and DBFEDHR as
well. The scale factor optimization software will calculate the MEP scale factor in background
code and automatically update the HRMSTEP register with the calculated number of MEP
steps per coarse step. The MEP Calibration Module will then use the values in the
HRMSTEP and CMPBHR or DBREDHR / DBFEDHR register to automatically calculate the
appropriate number of MEP steps represented by the fractional components and move the
high-resolution ePWM signal edge accordingly. If auto-conversion is disabled, CMPBHR
behaves same as CMPAHR. CMPBHR = (fraction(PWMduty * PWMperiod) * MEP Scale
Factor + 0.5)<<8).

NOTE: HRPWM functionality is only available on CPU1.

15.2.3 Configuring Hi-Res in Deadband Rising Edge and Falling Edge Delay
Once the ePWM has been configured to provide conventional PWM of a given frequency, polarity and
deadband enabled in half cycle clocking mode, the high resolution operation on dead band RED and FED
lines are enabled by programming the HRCNFG2 register in that particular ePWM module's register
space. This register provides the following configuration options:
Edge Mode — The MEP can be programmed to provide precise position control on the dead band rising
edge (RED), dead band falling edge (FED) or both edges (rising edge of DBRED signal and falling
edge of DBFED signal ) at the same time.
Control Mode — Selects the time event that loads the shadow value in active register for DBRED and
DBFED in high resolution mode. The user needs to select the pulse to match the selection in the
ePWM DBCTL[LOADREDMODE] & DBCTL[LOADFEDMODE] bits .

15.2.4 Principle of Operation
The MEP logic is capable of placing an edge in one of 255 (8 bits) discrete time steps (see device-specific
data sheet for typical MEP step size). The MEP works with the TBM and CCM registers to be certain that
time steps are optimally applied and that edge placement accuracy is maintained over a wide range of
PWM frequencies, system clock frequencies and other operating conditions.
The HRPWM module requires that TBCLK = EPWMCLK. TBCLK cannot be further divided now from
EPWMCLK.
Table 15-2 shows the typical range of operating frequencies supported by the HRPWM.

2008High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

Table 15-2. Relationship Between MEP Steps, PWM Frequency and Resolution

(1)
(2)
(3)
(4)
(5)

System
(MHz)

MEP Steps Per
EPWMCLK (1) (2) (3)

PWM MIN
(Hz) (4)

PWM MAX
(MHz)

Res. @ MAX
(Bits) (5)

60.0

93

916

3.00

10.9

70.0

79

1068

3.50

10.6

80.0

69

1221

4.00

10.4

90.0

62

1373

4.50

10.3

100.0

56

1526

5.00

10.1

TBCLK = EPWMCLK.
Table data based on a MEP time resolution of 180 ps (this is an example value. See the device-specific data sheet for MEP limits)
MEP steps applied = TEPWMCLK/180 ps in this example.
PWM minimum frequency is based on a maximum period value,(TBPRD = 65535). PWM mode is asymmetrical up-count.
Resolution in bits is given for the maximum PWM frequency stated.

15.2.4.1 Edge Positioning
NOTE: The below example is presented using [CMPA:CMPAHR] register combination. The theory of
operation and equations is same if the user intends to use [CMPBM:CMPBHRM] for duty
cycle control.

In a typical power control loop, a digital controller issues a duty command, usually expressed in a per unit
or percentage terms. Assume that for a particular operating point, the demanded duty cycle is 0.405 or
40.5% on time and the required converter PWM frequency is 1.25 MHz. In conventional PWM generation
with a system clock of 100 MHz, the duty cycle choices are in the vicinity of 40.5%. As shown in
Figure 15-6, a compare value of 32 counts (duty = 40%) is the closest to 40.5% that can be attained. This
is equivalent to an edge position of 320 ns instead of the desired 324 ns. This data is shown in Table 153.
By utilizing the MEP, you can achieve an edge position much closer to the desired point of 324 ns.
Table 15-3 shows that in addition to the CMPA value, 22 steps of the MEP (CMPAHR register) will
position the edge at 323.96 ns, resulting in almost zero error. In this example, it is assumed that the MEP
has a step resolution of 180 ps.
Figure 15-6. Required PWM Waveform for a Requested Duty = 40.5%
Tpwm = 800 ns
324 ns
Demanded
duty (40.5%)
10 ns steps
0

30 31 32 33 34

79

EPWM1A

37.5%

40.0%

38.8%

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

42.5%

41.3%

High-Resolution Pulse Width Modulator (HRPWM) 2009

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

Table 15-3. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)
CMPA (count) (1)

(2) (3)

DUTY
%

High
Time
(ns)

CMPA
(count)

CMPAHR
(count)

Duty
(%)

High
Time
(ns)

28

35.0

280

32

18

40.405

323.24

29

36.3

290

32

19

40.428

323.42

30

37.5

300

32

20

40.450

323.60

31

38.8

310

32

21

40.473

323.78

32

40.0

320

32

22

40.495

323.96

33

41.3

330

32

23

40.518

324.14

34

42.5

340

32

24

40.540

324.32

32

25

40.563

324.50

32

26

40.585

324.68

32

27

40.608

324.86

Required
32.40
(1)
(2)
(3)

40.5

324

TBCLK = 100 MHz, 10 ns
For a PWM Period register value of 80 counts, PWM Period = 80 x 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz
Assumed MEP step size for the above example = 180 ps
See the device-specific data manual for typical and maximum MEP values.

15.2.4.2 Scaling Considerations
The mechanics of how to position an edge precisely in time has been demonstrated using the resources
of the standard CMPA and MEP (CMPAHR) registers. In a practical application, however, it is necessary
to seamlessly provide the CPU a mapping function from a per-unit (fractional) duty cycle to a final integer
(non-fractional) representation that is written to the [CMPA:CMPAHR] register combination.
To do this, first examine the scaling or mapping steps involved. It is common in control software to
express duty cycle in a per-unit or percentage basis. This has the advantage of performing all needed
math calculations without concern for the final absolute duty cycle, expressed in clock counts or high time
in ns. Furthermore, it makes the code more transportable across multiple converter types running different
PWM frequencies.
To implement the mapping scheme, a two-step scaling procedure is required.

2010

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

Assumptions for this example:
TBCLK
PWM frequency
Required PWM duty cycle, PWMDuty
PWM period in terms of coarse steps,
PWMPeriod (800 ns/10 ns)
Number of MEP steps per coarse step at
180 ps (10 n/180 ps ), MEP_ScaleFactor
Value to keep CMPAHR within the range of
1-255 and fractional rounding constant
(default value)

=
=
=
=

10 ns (100 MHz)
1.25 MHz (1/800 ns)
0.405 (40.5%)
80

= 55

= 0.5 (0080h in Q8 format)

Step 1: Percentage Integer Duty value conversion for CMPA register
CMPA register value

=
=
=
=

CMPA register value

int(PWMDuty*PWMPeriod); int means integer part
int(0.405 * 80 )
int(32.4)
32 (20h)

Step 2: Fractional value conversion for CMPAHR register
CMPAHR

= (frac(PWMDuty*PWMPeriod)*MEP_ScaleFactor
+0.5) << 8); frac means fractional part
= (frac(32.4) * 55 + 0.5) << 8; Shifting is to move the
value to the high byte of CMPAHR.
= (0.4 * 55 + 0.5) << 8
= (22 + 0.5) << 8
= 22.5 * 256; Shifting left by 8 is the same as multiplying
by 256.
= 5760 (1680h)
= 1680h CMPAHR value = 1600h (lower 8 bits will be
ignored by hardware).

CMPAHR

NOTE: If the AUTOCONV bit (HRCNFG.6) is set and the MEP_ScaleFactor is in the HRMSTEP
register, then CMPAHR / CMPBHR register value = frac (PWMDuty*PWMperiod<<8). The
rest of the conversion calculations are performed automatically in hardware, and the correct
MEP-scaled signal edge appears on the ePWM channel output. If AUTOCONV is not set, the
above calculations must be performed by software.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2011

Operational Description of HRPWM

www.ti.com

NOTE: The MEP scale factor (MEP_ScaleFactor) varies with the system clock and DSP operating
conditions. TI provides an MEP scale factor optimizing (SFO) software C function, which
uses the built in diagnostics in each HRPWM and returns the best scale factor for a given
operating point.
The scale factor varies slowly over a limited range so the optimizing C function can be run
very slowly in a background loop.
The CMPA, CMPB, CMPAHR and CMPBHR registers are configured in memory so that the
32-bit data capability of the 28x CPU can write this as a single concatenated value, that is,
[CMPA:CMPAHR] , [CMPB:CMPBHR], and so on.
The mapping scheme has been implemented in both C and assembly, as shown in
Section 15.2.7. The actual implementation takes advantage of the 32-bit CPU architecture of
the 28xx, and is somewhat different from the steps shown in Section 15.2.4.2.
For time-critical control loops where every cycle counts, the assembly version is
recommended. This is a cycle optimized function (11 EPWMCLK cycles ) that takes a Q15
duty value as input and writes a single [CMPA:CMPAHR] value.

15.2.4.3 Duty Cycle Range Limitation
In high resolution mode, the MEP is not active for 100% of the PWM period. It becomes operational:
• Three EPWMCLK cycles after the period starts when high-resolution period (TBPRDHR) control is not
enabled.
• When high resolution period (TBPRDHR) control is enabled via the HRPCTL register:
– In up-count mode: three EPWMCLK cycles after the period starts until three EPWMCLK cycles
before the period ends.
– In up-down count mode: when counting up, three cycles after CTR = 0 until three cycles before
CTR = PRD, and when counting down, three cycles after CTR = PRD until three cycles before CTR
= 0.
• When using DBREDHR or DBFEDHR, DBRED and/or DBFED (the register corresponding to the edge
with hi-resolution displacement) must be greater than or equal to 3.
Duty cycle range limitations are illustrated in Figure 15-7 to Figure 15-10. This limitation imposes a duty
cycle limit on the MEP. For example, precision edge control is not available all the way down to 0% duty
cycle. When high-resolution period control is disabled, regular PWM duty control is fully operational down
to 0% duty cycle despite the unavailability of HRPWM features in the first three cycles. In most
applications this should not be an issue as the controller regulation point is usually not designed to be
close to 0% duty cycle. To better understand the useable duty cycle range, see Table 15-4. When highresolution period control is enabled (HRPCTL[HRPE]=1), the duty cycle must not fall within the restricted
range. Otherwise, there may be undefined behavior on the ePWMxA output.
Figure 15-7. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)
TPWM

0

EPWMCLK
TBCLK

3

=

TBPRD

EPWM1A

2012

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

Table 15-4. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles
PWM Frequency
(kHz)

(1)
(2)

(1)

3 Cycles
Minimum Duty

3 Cycles
Maximum Duty (2)

200

0.6%

99.4%

400

1.2%

98.8%

600

1.8%

98.2%

800

2.4%

97.6%

1000

3%

97%

1200

3.6%

96.4%

1400

4.2%

95.8%

1600

4.8%

95.2%

1800

5.4%

94.6%

2000

6%

94%

EPWMCLK = TBCLK = 100 MHz
This limitation applies only if high-resolution period (TBPRDHR) control is enabled.

If the application demands HRPWM operation below the minimum duty cycle limitation, then the HRPWM
can be configured to operate in count-down mode with the rising edge position (REP) controlled by the
MEP when high-resolution period is disabled (HRPCTL[HRPE] = 0). This is illustrated in Figure 15-8. In
this configuration, the minimum duty cycle limitation is no longer an issue. However, there will be a
maximum duty limitation with same percent numbers as given in Table 15-4.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2013

Operational Description of HRPWM

www.ti.com

Figure 15-8. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)
Tpwm

EPWMCLK

0

3

TBPRD

EPWM1A

Figure 15-9. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)
Tpwm

0

EPWMCLK=
TBCLK

TBPRD - 3

3

TBPRD

EPWM1A

2014

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

Figure 15-10. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)
Tpwm

TBPRD

0

3

TBPRD-3

TBPRD-3

3

0

NOTE: If the application has enabled high-resolution period control (HRPCTL[HRPE]=1), the duty
cycle must not fall within the restricted range. Otherwise, there will be undefined behavior on
the ePWM output.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2015

Operational Description of HRPWM

www.ti.com

15.2.4.4 High Resolution Period
High resolution period control using the MEP logic is supported on devices with a Type 1 ePWM module
or greater.
NOTE: When high-resolution period control is enabled, on ePWMxA only, and not ePWMxB output
and vice versa, the non hi-res output will have +/- 1 TBCLK cycle jitter in up-count mode and
+/- 2 TBCLK cycle jitter in up-down count mode.

The scaling procedure described for duty cycle in Section 15.2.4.2 applies for high-resolution period as
well:
Assumptions for this example:
TBCLK
Required PWM frequency

= 10 ns (100 MHz)

= 175 kHz (period of 571.428)
Number of MEP steps per coarse step at 180 ps
= 55 (10 ns / 180 ps)
(MEP_ScaleFactor)
Value to keep TBPRDHR within range of 1-255 and = 0.5 (0080h in Q8 format)
fractional rounding constant (default value)
Problem:
In up-count mode:
If TBPRD = 571, then PWM frequency = 174.82 kHz (period = (571+1)* TTBCLK).
If TBPRD = 570, then PWM frequency = 175.13 kHz (period = (570+1)* TTBCLK).
In up-down count mode:
If TBPRD = 286, then PWM frequency = 174.82 kHz (period = (286*2)* TTBCLK).
If TBPRD = 285, then PWM frequency = 175.44 kHz (period = (285*2)* TTBCLK).
Solution:
With 55 MEP steps per coarse step at 180 ps each:
Step 1: Percentage Integer Period value conversion for TBPRD register
Integer period value

= 571 * TTBCLK
= int (571.428) * TTBCLK
= int (PWMperiod) * TTBCLK

In up-count mode:
TBPRD

=
=
=
=

In up-down count mode:
TBPRD

570 (TBPRD = period value - 1)
023Ah
285 (TBPRD = period value / 2)
011Dh

Step 2: Fractional value conversion for TBPRDHR register
TBPRDHR register value
If auto-conversion enabled and HRMSTEP =
MEP_ScaleFactor value (55):
TBPRDHR register value

2016

High-Resolution Pulse Width Modulator (HRPWM)

= (frac(PWMperiod) * MEP_ScaleFactor + 0.5)
=frac (PWMperiod) << 8 (Shifting is to move the
value to the high byte of TBPRDHR)
=frac (571.428) << 8
=0.428 × 256
=6D00h
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

The autoconversion will then automatically perform
the calculation such that TBPRDHR MEP delay is
scaled by hardware to:

=((TBPRDHR(15:0) >> 8) × HRMSTEP + 80h) << 8

= (006Dh × 55 + 80h) >> 8
=(17EBh) >> 8
=0017h MEP Steps

Period MEP delay

15.2.4.4.1 High-Resolution Period Configuration
To use High Resolution Period, the ePWMx module must be initialized in the exact order presented.
The steps below use CMPA with shadow registers and the corresponding HRCNFG bits for hi-resolution
operation on EPWMxA. For hi-resolution operation on EPWMxB, make the appropriate substitutions with
the B channel fields.
1. Enable ePWMx clock
2. Enable HRPWM clock
3. Disable TBCLKSYNC
4. Configure ePWMx registers - AQ, TBPRD, CC, and so on.
• ePWMx may only be configured for up-count or up-down count modes. High-resolution period is
not compatible with down-count mode.
• TBPRD and CC registers must be configured for shadow loads.
• CMPCTL[LOADAMODE]
– In up-count mode: CMPCTL[LOADAMODE] = 1 (load on CTR = PRD)
– In up-down count mode: CMPCTL[LOADAMODE] = 2 (load on CTR=0 or CTR=PRD)
5. Configure the HRCNFG register such that:
• HRCNFG[HRLOAD] = 2 (load on either CTR = 0 or CTR = PRD)
• HRCNFG[AUTOCONV] = 1 (Enable auto-conversion)
• HRCNFG[EDGMODE] = 3 (MEP control on both edges)
6. For TBPHS:TBPHSHR synchronization with high-resolution period, set both
HRPCTL[TBPSHRLOADE] = 1 and TBCTL[PHSEN] = 1. In up-down count mode these bits must be
set to 1 regardless of the contents of TBPHSHR.
7. Enable high-resolution period control (HRPCTL[HRPE] = 1)
8. Enable TBCLKSYNC
9. TBCTL[SWFSYNC] = 1
10. HRMSTEP must contain an accurate MEP scale factor (# of MEP steps per EPWMCLK coarse step)
because auto-conversion is enabled. The MEP scale factor can be acquired via the SFO() function
described in Section 15.3.
11. To control high-resolution period, write to the TBPRDHR(M) registers.
NOTE: When high-resolution period mode is enabled, an EPWMxSYNC pulse will introduce +/- 1 - 2
cycle jitter to the PWM (+/- 1 cycle in up-count mode and +/- 2 cycle in up-down count
mode). For this reason, TBCTL[SYNCOSEL] should not be set to 1 (CTR = 0 is
EPWMxSYNCO source) or 2 (CTR = CMPB is EPWMxSYNCO source). Otherwise, the jitter
will occur on every PWM cycle with the synchronization pulse.
When TBCTL[SYNCOSEL] = 0 (EPWMxSYNCI is EPWMxSYNCO source), a software
synchronization pulse should be issued only once during high-resolution period initialization.
If a software sync pulse is applied while the PWM is running, the jitter will appear on the
PWM output at the time of the sync pulse.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2017

Operational Description of HRPWM

www.ti.com

15.2.5 Deadband High Resolution Operation
Assumptions for this example:
System clock
Deadband Enabled in half cycle mode, TBCLK =
EPWMCLK
Required PWM frequency

= 10 ns (100 MHz) &

Required PWM duty cycle

0.5 (50%)
5% over duty
(0.05 * 375 ns ) = 18.75 ns

Required Dead band Rising Edge Delay
Required Dead band Rising Edge Delay in ns

1.33MHz (1 / 750 ns)

NOTE: Just like the duty cycle restrictions when using HRPWM, the DBRED and DBFED values
must be greater than 3 to use hi-res deadband.

Deadband Delay Values as a Function of DBFED and DBRED:
When half-cycle clocking is enabled, the formula to calculate the falling-edge-delay and rising-edge-delay
becomes:
FED = DBFED * TBCLK / 2
RED = DBRED * TBCLK / 2
DBRED and DBFED Calculated Values:
Required Dead band Rising Edge Delay in ns = 18.75 ns
DBRED = RED / (TBCLK / 2)
DBRED = 18.75 ns / 5 ns
DBRED Required = 3.75 ns
With 55 MEP steps per coarse step at 180 ps each:
Step 1: Integer Dead band value conversion for DBREDM register
Integer DBRED value

= int (RED / (TBCLK / 2))
= int (3.75)
=3

DBRED

Step 2: Fractional value conversion for Dead band high resolution register DBREDHR
DBREDHR register value

= (frac(DBRED Required) * MEP_ScaleFactor +
0.5) << 8 (Shifting is to move the value to the high
byte of DBREDHR)
=(frac (3.75) * 55 + 0.5) << 8
= ( 0.75 * 55 + 0.5 ) << 8
=(41.75) * 256 Shifting left by 8 is the same as
multiplying by 256.
=29C0h MEP Steps
Hardware will ignore lower 9 bits in the above
calculated DBREDHR value

DBREDHR value

2018

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

NOTE: If the AUTOCONV bit (HRCNFG.6) is set and the MEP_ScaleFactor is in the HRMSTEP
register, then DBREDHR:DBRED = frac((required DB value) < <8). The rest of the
conversion calculations are performed automatically in hardware, and the correct MEPscaled signal edge appears on the ePWM channel output. If AUTOCONV is not set, the
above calculations must be performed by software.

15.2.6 Scale Factor Optimizing Software (SFO)
The micro edge positioner (MEP) logic is capable of placing an edge in one of 255 discrete time steps. As
previously mentioned, the size of these steps is on the order of 150 ps (see device-specific data sheet for
typical MEP step size on your device). The MEP step size varies based on worst-case process
parameters, operating temperature, and voltage. MEP step size increases with decreasing voltage and
increasing temperature and decreases with increasing voltage and decreasing temperature. Applications
that use the HRPWM feature should use the TI-supplied MEP scale factor optimization (SFO) software
function. The SFO function helps to dynamically determine the number of MEP steps per EPWMCLK
period while the HRPWM is in operation.
To utilize the MEP capabilities effectively, the correct value for the MEP scaling factor needs to be known
by the software. To accomplish this, the HRPWM module has built in self-check and diagnostic
capabilities that can be used to determine the optimum MEP scale factor value for any operating
condition. TI provides a C-callable library containing one SFO function that utilizes this hardware and
determines the optimum MEP scale factor. As such, MEP control and diagnostics registers are reserved
for TI use.
A detailed description of the SFO library - SFO_TI_Build_V7.lib software can be found in Section 15.3.

15.2.7 HRPWM Examples Using Optimized Assembly Code.
The best way to understand how to use the HRPWM capabilities is through two real examples:
1. Simple buck converter using asymmetrical PWM (count-up) with active high polarity.
2. DAC function using simple R+C reconstruction filter.
The following examples all have initialization and configuration code written in C. To make these easier to
understand, the #defines shown below are used. Note, #defines introduced in the device-specific Pulse
Width Modulator (ePWM) Module Reference Guide are also used.
Example 15-1 This example assumes MEP step size of 150 ps and does not use the SFO library.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2019

Operational Description of HRPWM

www.ti.com

Example 15-1. #Defines for HRPWM Header Files
// HRPWM (High Resolution PWM) //
================================
// HRCNFG
#define HR_Disable 0x0
#define HR_REP 0x1
// Rising Edge position
#define HR_FEP 0x2
// Falling Edge position
#define HR_BEP 0x3
// Both Edge position #define HR_CMP 0x0 // CMPAHR controlled
#define HR_PHS 0x1
// TBPHSHR controlled #define HR_CTR_ZERO 0x0 // CTR = Zero event
#define HR_CTR_PRD 0x1
// CTR = Period event
#define HR_CTR_ZERO_PRD 0x2 // CTR = ZERO or Period event
#define HR_NORM_B 0x0
// Normal ePWMxB output
#define HR_INVERT_B 0x1
// ePWMxB is inverted ePWMxA output

15.2.7.1 Implementing a Simple Buck Converter
In
•
•
•

this example, the PWM requirements are:
PWM frequency = 1 MHz (that is, TBPRD = 100 )
PWM mode = asymmetrical, up-count
Resolution = 12.7 bits (with a MEP step size of 150 ps)

Figure 15-11 and Figure 15-12 show the required PWM waveform. As explained previously, configuration
for the ePWM1 module is almost identical to the normal case except that the appropriate MEP options
need to be enabled/selected.
Figure 15-11. Simple Buck Controlled Converter Using a Single PWM
Vin1

Vout1
Buck

EPWM1A

Figure 15-12. PWM Waveform Generated for Simple Buck Controlled Converter
Tpwrr

Z

CA

Z

CA

Z

EPWM1A

2020

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

The example code shown consists of two main parts:
• Initialization code (executed once)
• Run time code (typically executed within an ISR)
Example 15-2 shows the Initialization code. The first part is configured for conventional PWM. The second
part sets up the HRPWM resources.
This example assumes MEP step size of 150 ps and does not use the SFO library.
Example 15-2. HRPWM Buck Converter Initialization Code
void HrBuckDrvCnf(void)
{
// Config for conventional PWM first
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;
//
EPwm1Regs.TBPRD = 100;
//
hrbuck_period = 200;
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
//
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Note: ChB is initialized here only for comparison
EPwm1Regs.CMPCTL.bit.LOADAMODE
EPwm1Regs.CMPCTL.bit.SHDWAMODE
EPwm1Regs.CMPCTL.bit.LOADBMODE
EPwm1Regs.CMPCTL.bit.SHDWBMODE
EPwm1Regs.AQCTLA.bit.ZRO =
EPwm1Regs.AQCTLA.bit.CAU =
EPwm1Regs.AQCTLB.bit.ZRO =
EPwm1Regs.AQCTLB.bit.CBU =
// Now configure the HRPWM
EALLOW;

=
=
=
=

CC_CTR_ZERO;
CC_SHADOW;
CC_CTR_ZERO;
CC_SHADOW;

AQ_SET;
AQ_CLEAR;
AQ_SET;
AQ_CLEAR;
resources

EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP;
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
EDIS;
MEP_ScaleFactor = 66*256;

set Immediate load
Period set for 1000 kHz PWM
Used for Q15 to Q0 scaling
EPWM1 is the Master

purposes, it is not required

// optional
// optional

// optional
// optional
//
//
//
//
//
//

Note these registers are protected
and act only on ChA
clear all bits first
Control Falling Edge Position
CMPAHR controls the MEP
Shadow load on CTR=Zero

// Start with typical Scale Factor
// value for 100 MHz
// Note: Use SFO functions to update
MEP_ScaleFactor dynamically

}

Example 15-3 shows an assembly example of run-time code for the HRPWM buck converter.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2021

Operational Description of HRPWM

www.ti.com

Example 15-3. HRPWM Buck Converter Run-Time Code
EPWM1_BASE .set 0x6800
CMPAHR1 .set EPWM1_BASE+0x8
;===============================================
HRBUCK_DRV; (can execute within an ISR or loop)
;===============================================
MOVW DP, #_HRBUCK_In
MOVL XAR2,@_HRBUCK_In
; Pointer to Input Q15 Duty (XAR2)
MOVL XAR3,#CMPAHR1
; Pointer to HRPWM CMPA reg (XAR3)
; Output for EPWM1A (HRPWM)
MOV T,*XAR2 ; T <= Duty
MPYU ACC,T,@_hrbuck_period ; Q15 to Q0 scaling based on Period
MOV T,@_MEP_ScaleFactor
; MEP scale factor (from optimizer s/w)
MPYU P,T,@AL
; P <= T * AL, Optimizer scaling
MOVH @AL,P
; AL <= P, move result back to ACC
ADD ACC, #0x080
; MEP range and rounding adjustment
MOVL *XAR3,ACC
; CMPA:CMPAHR(31:8) <= ACC
; Output for EPWM1B (Regular Res) Optional - for comparison purpose only
MOV *+XAR3[2],AH
; Store ACCH to regular CMPB

15.2.7.2 Implementing a DAC function Using an R+C Reconstruction Filter
In
•
•
•

this example, the PWM requirements are:
PWM frequency = 400 kHz (that is, TBPRD = 250)
PWM mode = Asymmetrical, Up-count
Resolution = 14 bits ( MEP step size = 150 ps)

Figure 15-13 and Figure 15-14 show the DAC function and the required PWM waveform. As explained
previously, configuration for the ePWM1 module is almost identical to the normal case except that the
appropriate MEP options need to be enabled/selected.
Figure 15-13. Simple Reconstruction Filter for a PWM-based DAC
EPWM1A

VOUT1
LPF

Figure 15-14. PWM Waveform Generated for the PWM DAC Function
TPWM = 2.5 µs

CA

Z

Z

CA

Z

EPWM1A

The example code shown consists of two main parts:
• Initialization code (executed once)
• Run time code (typically executed within an ISR)
2022

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Operational Description of HRPWM

www.ti.com

This example assumes a typical MEP_SP and does not use the SFO library.
Example 15-4 shows the Initialization code. The first part is configured for conventional PWM. The second
part sets up the HRPWM resources.
Example 15-4. PWM DAC Function Initialization Code
void HrPwmDacDrvCnf(void)
{
// Config for conventional PWM first
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;
// Set Immediate load
EPwm1Regs.TBPRD = 250;
// Period set for 400 kHz PWM
hrDAC_period = 250;
// Used for Q15 to Q0 scaling
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
// EPWM1 is the Master
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Note: ChB is initialized here only for comparison purposes, it is not required
EPwm1Regs.CMPCTL.bit.LOADAMODE
EPwm1Regs.CMPCTL.bit.SHDWAMODE
EPwm1Regs.CMPCTL.bit.LOADBMODE
EPwm1Regs.CMPCTL.bit.SHDWBMODE
EPwm1Regs.AQCTLA.bit.ZRO =
EPwm1Regs.AQCTLA.bit.CAU =
EPwm1Regs.AQCTLB.bit.ZRO =
EPwm1Regs.AQCTLB.bit.CBU =
// Now configure the HRPWM
EALLOW;

=
=
=
=

CC_CTR_ZERO;
CC_SHADOW;
CC_CTR_ZERO;
CC_SHADOW;

AQ_SET;
AQ_CLEAR;
AQ_SET;
AQ_CLEAR;
resources

// optional
// optional

// optional
// optional

// Note these registers are protected
// and act only on ChA.
EPwm1Regs.HRCNFG.all = 0x0; // Clear all bits first
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP;
// Control falling edge position
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
// CMPAHR controls the MEP.
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
// Shadow load on CTR=Zero.
EDIS;
MEP_ScaleFactor = 66*256;
// Start with typical Scale Factor
// value for 100 MHz.
// Use SFO functions to update MEP_ScaleFactor
// dynamically.
}

Example 15-5 shows an assembly example of run-time code that can execute in a high-speed ISR loop.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2023

Operational Description of HRPWM

www.ti.com

Example 15-5. PWM DAC Function Run-Time Code
EPWM1_BASE .set 0x6800
CMPAHR1 .set EPWM1_BASE+0x8
;=================================================
HRPWM_DAC_DRV; (can execute within an ISR or loop)
;=================================================
MOVW DP, #_HRDAC_In
MOVL XAR2,@_HRDAC_In
; Pointer to input Q15 duty (XAR2)
MOVL XAR3,#CMPAHR1
; Pointer to HRPWM CMPA reg (XAR3)
; Output for EPWM1A (HRPWM
MOV T,*XAR2
; T <= duty
MPY ACC,T,@_hrDAC_period
; Q15 to Q0 scaling based on period
ADD ACC,@_HrDAC_period<<15 ; Offset for bipolar operation
MOV T,@_MEP_ScaleFactor
; MEP scale factor (from optimizer s/w)
MPYU P,T,@AL
; P <= T * AL, optimizer scaling
MOVH @AL,P
; AL <= P, move result back to ACC
ADD ACC, #0x080
; MEP range and rounding adjustment
MOVL *XAR3,ACC
; CMPA:CMPAHR(31:8) <= ACC
; Output for EPWM1B (Regular Res) Optional - for comparison purpose only
MOV *+XAR3[2],AH
; Store ACCH to regular CMPB

2024

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Appendix A: SFO Library Software - SFO_TI_Build_V7.lib

www.ti.com

15.3 Appendix A: SFO Library Software - SFO_TI_Build_V7.lib
The following table lists several features of the SFO_TI_Build_V7.lib library.
Table 15-5. SFO Library Features
SFO_TI_Build_V7.lib

Unit

Completion-checking?

Yes

Function return value

Typical cycles required for SFO() to update
MEP_ScaleFactor if called repetitively without
interrupts

130,000

EPWMCLK cycles

A functional description of the SFO library routine, SFO(), is found below.

15.3.1 Scale Factor Optimizer Function - int SFO()
This routine drives the micro-edge positioner (MEP) calibration module to run SFO diagnostics and
determine the appropriate MEP scale factor (number of MEP steps per coarse EPWMCLK step) for a
device at any given time.
If EPWMCLK = TBCLK = 100 MHz and assuming the MEP step size is 150 ps, the typical scale factor
value at 100 MHz = 66 MEP steps per TBCLK unit (10 ns)
The function returns a MEP scale factor value:
MEP_ScaleFactor = Number of MEP steps per EPWMCLK.
Constraints when using this function:
• SFO() can be used with a minimum EPWMCLK = TBCLK = 50 MHz. MEP diagnostics logic uses
EPWMCLK and not TBCLK, so the EPWMCLK restriction is an important constraint. Below 50 MHz,
with device process variation, the MEP step size may decrease under cold temperature and high core
voltage conditions to such a point, that 255 MEP steps will not span an entire EPWMCLK cycle.
• At any time, SFO() can be called to run SFO diagnostics on the MEP calibration module
Usage:
• SFO() can be called at any time in the background while the ePWM channels are running in HRPWM
mode. The scale factor result obtained can be applied to all ePWM channels running in HRPWM mode
because the function makes use of the diagnostics logic in the MEP calibration module (which runs
independently of ePWM channels).
• This routine returns a 1 when calibration is finished and a new scale factor has been calculated, or a 0
if calibration is still running. The routine returns a 2 if there is an error, and the MEP_ScaleFactor is
greater than the maximum 255 fine steps per coarse EPWMCLK cycle. In this case, the HRMSTEP
register will maintain the last MEP scale factor value less than 256 for auto conversion.
• All ePWM modules operating in HRPWM incur only a 3-EPWMCLK cycle minimum duty cycle limitation
when high-resolution period control is not used. If high-resolution period control is enabled, there is an
additional duty cycle limitation 3-EPWMCLK cycles before the end of the PWM period (see
Section 15.2.4.3).
• The SFO() function also updates the HRMSTEP register with the scale factor result. If the
HRCNFG[AUTOCONV] bit is set, the application software is responsible only for setting CMPAHR =
fraction(PWMduty*PWMperiod) << 8 or CMPBHR = fraction(PWMduty*PWMperiod) << 8 or TBPRDHR
= fraction (PWMperiod) while running SFO() in the background. The MEP Calibration Module will then
use the values in the HRMSTEP and CMPAHR/CMPBHR/TBPRDHR register to automatically
calculate the appropriate number of MEP steps represented by the fractional duty cycle or period and
move the high-resolution ePWM signal edge accordingly.
• If the HRCNFG[AUTOCONV] bit is clear, the HRMSTEP register is ignored. The application software
will need to perform the necessary calculations manually so that:
– CMPAHR = (fraction(PWMduty * PWMperiod) * MEP Scale Factor) << 8 + 0x080.
– Similar behavior applies for TBPHSHR, CMPBHR, DBREDHR, DBFEDHR. Auto-conversion must
be enabled when using TBPRDHR.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2025

Appendix A: SFO Library Software - SFO_TI_Build_V7.lib

www.ti.com

The routine can be run as a background task in a slow loop requiring negligible CPU cycles. The repetition
rate at which an SFO function needs to be executed depends on the application's operating environment.
As with all digital CMOS devices, temperature and supply voltage variations have an effect on MEP
operation. However, in most applications these parameters vary slowly and therefore it is often sufficient
to execute the SFO function once every 5 to 10 seconds. If more rapid variations are expected, then
execution may have to be performed more frequently to match the application. Note, there is no high limit
restriction on the SFO function repetition rate, hence it can execute as quickly as the background loop is
capable.
While using the HRPWM feature, HRPWM logic will not be active for the first three EPWMCLK cycles of
the PWM period (and the last three EPWMCLK cycles of the PWM period if TBPRDHR is used). While
running the application in this configuration, if high-resolution period control is disabled
(HRPCTL[HRPE=0]) and the CMPA/CMPB register value is less than three cycles, then its
CMPAHR/CMPBHR register must be cleared to zero. If high-resolution period control is enabled
(HRPCTL[HRPE=1]), the CMPA register value must not fall below three or above TBPRD-3.This would
avoid any unexpected transitions on the PWM signal.

15.3.2 Software Usage
The software library function SFO(), calculates the MEP scale factor for the HRPWM-supported ePWM
modules. The scale factor is an integer value in the range 1-255, and represents the number of micro step
edge positions available for a system clock period. The scale factor value is returned in an integer variable
called MEP_ScaleFactor. For example, see Table 15-6.
Table 15-6. Factor Values
Software Function call

Functional Description

Updated Variables

SFO()

Returns MEP scale factor in the HRMSTEP register

MEP_ScaleFactor & HRMSTEP register.

To use the HRPWM feature of the ePWMs, it is recommended that the SFO function be used as
described here.
Step 1. Add "Include" Files
The SFO_V7.h file needs to be included as follows. This include file is mandatory while using the SFO
library function. For the SFO() to operate, the appropriate (Device)_Device.h and
(Device)_Epwm_defines.h must be included in the project. These include files are optional if customized
header files are used in the end applications.
Example 15-6. A Sample of How to Add "Include" Files
#include "F28x7x_Device.h"
// F28x7x Headerfile
#include "F28x7x_EPwm_defines.h" // init defines
#include "SFO_V7.h"
// SFO lib functions (needed for HRPWM)

Step 2. Element Declaration
Declare an integer variable for the scale factor value as shown below.

2026

High-Resolution Pulse Width Modulator (HRPWM)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Appendix A: SFO Library Software - SFO_TI_Build_V7.lib

www.ti.com

Example 15-7. Declaring an Element
int MEP_ScaleFactor = 0;
//scale factor value
volatile struct EPWM_REGS *ePWM[] = {0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs,
&EPwm4Regs};

Step 3. MEP_ScaleFactor Initialization
The SFO() function does not require a starting scale factor value in MEP_ScaleFactor. Prior to using the
MEP_ScaleFactor variable in application code, SFO() should be called to drive the MEP calibration
module to calculate an MEP_ScaleFactor value.
As part of the one-time initialization code prior to using MEP_ScaleFactor, include the following:
Example 15-8. Initializing With a Scale Factor Value
MEP_ScaleFactor initialized using function SFO ()
while (SFO() == 0) {} // MEP_ScaleFactor calculated by MEP Cal Module

Step 4. Application Code
While the application is running, fluctuations in both device temperature and supply voltage may be
expected. To be sure that optimal Scale Factors are used for each ePWM module, the SFO function
should be re-run periodically as part of a slower back-ground loop. Some examples of this are shown
here.
NOTE: See the HRPWM_SFO example in the device-specific C/C++ header files and peripheral
examples available from the TI website.

Example 15-9. SFO Function Calls
main ()
{
int status;
// User code
// ePWM1, 2, 3, 4 are running in HRPWM mode
// The status variable returns 1 once a new MEP_ScaleFactor has been
// calculated by the MEP Calibration Module running SFO
// diagnostics.
status = SFO();
if(status==2) {ESTOP0;}

// The function returns a 2 if MEP_ScaleFactor is greater
// than the maximum 255 allowed (error condition)

}

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

High-Resolution Pulse Width Modulator (HRPWM)

Copyright © 2013–2017, Texas Instruments Incorporated

2027

Chapter 16
SPRUHM8G – December 2013 – Revised September 2017

Enhanced Capture (eCAP)
This chapter describes the enhanced capture (eCAP), which is used in systems where accurate timing of
external events is important.
The eCAP module described in this reference guide is a Type 0 eCAP. See the TMS320C28xx, 28xxx
DSP Peripheral Reference Guide (SPRU566) for a list of all devices with a eCAP module of the same
type, to determine the differences between the types, and for a list of device-specific differences within a
type.
Topic

16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8

2028

...........................................................................................................................
Introduction ...................................................................................................
Description ....................................................................................................
Configuring Device Pins for the eCAP ...............................................................
Capture and APWM Operating Mode .................................................................
Capture Mode Description ...............................................................................
Application of the ECAP Module ......................................................................
Application of the APWM Mode ........................................................................
Registers .......................................................................................................

Enhanced Capture (eCAP)

Page

2029
2029
2029
2030
2031
2039
2048
2050

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

16.1 Introduction
Features for eCAP include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module described in this guide includes the following features:
• 4-event time-stamp registers (each 32 bits)
• Edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt on any of the four events
• Single shot capture of up to four event time-stamps
• Continuous mode capture of time-stamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All above resources dedicated to a single input pin
• When not used in capture mode, the ECAP module can be configured as a single channel PWM output

16.2 Description
The eCAP module represents one complete capture channel that can be instantiated multiple times
depending on the target device. In the context of this guide, one eCAP channel has the following
independent key resources:
• Dedicated input capture pin
• 32-bit time base (counter)
• 4 x 32-bit time-stamp capture registers (CAP1-CAP4)
• 4-stage sequencer (Modulo4 counter) that is synchronized to external events, ECAP pin rising/falling
edges.
• Independent edge polarity (rising/falling edge) selection for all 4 events
• Input capture signal prescaling (from 2-62)
• One-shot compare register (2 bits) to freeze captures after 1 to 4 time-stamp events
• Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4) scheme
• Interrupt capabilities on any of the 4 capture events

16.3 Configuring Device Pins for the eCAP
To connect the device input pins to the module, the Input X-BAR must be used. Any GPIO on the device
can be configured as an input. The GPIO input qualification can be set to synchronous or asynchronous
mode. Using synchronized inputs can help with noise immunity; however, when synchronized inputs are
used this will affect the eCAP's accuracy ±2 cycles. The internal pull-ups can be configured in the
GPyPUD register. Since the GPIO mode is used the GPyINV register can invert the signals.
The Output X-BAR must be used to connect output signals to the OUTPUTXBARx output locations. The
GPIO mux then be configured to connect the OUTPUTXBARx lines to any of several IO pins with the
GPIO Mux. To avoid glitches on the pins, the GPyGMUX bits must be configured first (while keeping the
corresponding GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the
desired value.
See the GPIO Chapter for more details on GPIO mux, GPIO settings, and XBAR configuration.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2029

Capture and APWM Operating Mode

www.ti.com

16.4 Capture and APWM Operating Mode
You can use the eCAP module resources to implement a single-channel PWM generator (with 32-bit
capabilities) when it is not being used for input captures. The counter operates in count-up mode,
providing a time-base for asymmetrical pulse width modulation (PWM) waveforms. The CAP1 and CAP2
registers become the active period and compare registers, respectively, while CAP3 and CAP4 registers
become the period and capture shadow registers, respectively. Figure 16-1 is a high-level view of both the
capture and auxiliary pulse-width modulator (APWM) modes of operation.
Figure 16-1. Capture and APWM Modes of Operation

SyncIn

Counter (”timer”)

Capture
mode

32

Note:
Same pin
depends on
operating
mode

CAP1 reg
CAP2 reg
CAP3 reg

Sequencing
Edge detection
Edge polarity
Prescale

ECAPx
pin

CAP4 reg
ECAPxINT

Interrupt I/F

Or

SyncIn

Counter (”timer”)

APWM
mode

32

Syncout

Period reg
(active) (”CAP1”)
Compare reg
(active) (”CAP2”)
Period reg
(shadow) (”CAP3”)

PWM
Compare logic

APWMx
pin

Compare reg
(shadow) (”CAP4”)
ECAPxINT

Interrupt I/F

A

A single pin is shared between CAP and APWM functions. In capture mode, it is an input; in APWM mode, it is an
output.

B

In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the corresponding
shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow registers CAP3/CAP4 invokes
the shadow mode.

Figure 16-2 further descries the output of the eCAP in APWM mode based on the CMP and PRD values.

2030

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Capture Mode Description

www.ti.com

Figure 16-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode
32
PRD [0-31]

CTR = PRD
Digital
Comparator

32

POLSEL

CTR [0-31]
set

ECAPxOUT
Q

CTR = CMP
clear

32
CMP [0-31]

Digital
Comparator
CTR [0-31]
set

FFFFFFFF
Period
Register
PRD [0-31]
clear

Compare
Register
CMP [0-31]

set

clear

0000000C

ECAPOUT

Off−time

On
time

Period

16.5 Capture Mode Description
Figure 16-3 shows the various components that implement the capture function.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2031

Capture Mode Description

www.ti.com

Figure 16-3. Capture Function Diagram
ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]

SYNC

CTRPHS
(phase register−32 bit)
SYNCIn

APWM mode
CTR_OVF

OVF
TSCTR
(counter−32 bit)

SYNCOut

RST

CTR [0−31]

Delta−mode

PRD [0−31]

PWM
compare
logic

CMP [0−31]
32
CTR=PRD

CTR [0−31]

CTR=CMP
32
PRD [0−31]
ECCTL1 [ CAPLDEN, CTRRSTx]

LD1

CAP1
(APRD active)
APRD
shadow

32
CMP [0−31]

CAP2
(ACMP active)

LD

32

32

Polarity
select

LD

32

32

32

MODE SELECT

ECAPx
32

LD2

Polarity
select
Event
qualifier

ACMP
shadow

CAP3
(APRD shadow)

LD

CAP4
(ACMP shadow)

LD

Event
Prescale

Polarity
select

LD3

LD4

ECCTL1[EVTPS]

Polarity
select

4
Capture events

Edge Polarity Select
ECCTL1[CAPxPOL]
4

CEVT[1:4]

to PIE

Interrupt
Trigger
and
Flag
control

CTR_OVF

Continuous /
Oneshot
Capture Control

CTR=PRD
CTR=CMP
ECCTL2 [ RE−ARM, CONT/ONESHT, STOP_WRAP]

Registers: ECEINT, ECFLG, ECCLR, ECFRC

16.5.1 Event Prescaler
•

2032

An input capture signal (pulse train) can be prescaled by N = 2-62 (in multiples of 2) or can bypass the
prescaler.
This is useful when very high frequency signals are used as inputs. Figure 16-4 shows a functional
diagram and Figure 16-5 shows the operation of the prescale function.

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Capture Mode Description

www.ti.com

Figure 16-4. Event Prescale Control
Event prescaler
0
PSout
1

By−pass

ECAPx pin
(from GPIO)

/n
5
ECCTL1[EVTPS]
prescaler [5 bits]
(counter)

A

When a prescale value of 1 is chosen ( ECCTL1[13:9] = 0,0,0,0,0 ) the input capture signal by-passes the prescale
logic completely.

Figure 16-5. Prescale Function Waveforms
ECAPx

PSout
div 2

PSout
div 4
PSout
div 6
PSout
div 8
PSout
div 10

16.5.2 Edge Polarity Select and Qualifier
•
•
•

Four independent edge polarity (rising edge/falling edge) selection MUXes are used, one for each
capture event.
Each edge (up to 4) is event qualified by the Modulo4 sequencer.
The edge event is gated to its respective CAPx register by the Mod4 counter. The CAPx register is
loaded on the falling edge.

16.5.3 Continuous/One-Shot Control
•
•
•

The Mod4 (2 bit) counter is incremented via edge qualified events (CEVT1-CEVT4).
The Mod4 counter continues counting (0->1->2->3->0) and wraps around unless stopped.
A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4
counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2033

Capture Mode Description

www.ti.com

The continuous/one-shot block controls the start/stop and reset (zero) functions of the Mod4 counter via a
mono-shot type of action that can be triggered by the stop-value comparator and re-armed via software
control.
Once armed, the eCAP module waits for 1-4 (defined by stop-value) capture events before freezing both
the Mod4 counter and contents of CAP1-4 registers (time-stamps).
Re-arming prepares the eCAP module for another capture sequence. Also re-arming clears (to zero) the
Mod4 counter and permits loading of CAP1-4 registers again, providing the CAPLDEN bit is set.
In continuous mode, the Mod4 counter continues to run (0->1->2->3->0, the one-shot action is ignored,
and capture values continue to be written to CAP1-4 in a circular buffer sequence.
Figure 16-6. Details of the Continuous/One-shot Block
0 1 2 3
2:4 MUX

2

CEVT1
CEVT2
CEVT3
CEVT4

CLK
Modulo 4
counter Stop
RST

Mod_eq

One−shot
control logic

Stop value (2b)

ECCTL2[STOP_WRAP]

ECCTL2[RE−ARM]
ECCTL2[CONT/ONESHT]

16.5.4 32-Bit Counter and Phase Control
This counter provides the time-base for event captures, and is clocked via the system clock.
A phase register is provided to achieve synchronization with other counters, via a hardware and software
forced sync. This is useful in APWM mode when a phase offset between modules is needed.
On any of the four event loads, an option to reset the 32-bit counter is given. This is useful for time
difference capture. The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4
signals.

2034

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Capture Mode Description

www.ti.com

Figure 16-7. Details of the Counter and Synchronization Block
SYNC
ECCTL2[SWSYNC]

ECCTL2[SYNCOSEL]
SYNCI
CTR=PRD
Disable
Disable

ECCTL2[SYNCI_EN]

SYNCO
Sync out
select

CTRPHS

LD_CTRPHS

RST

Delta−mode

TSCTR
(counter 32b)
SYSCLK

CLK

OVF

CTR−OVF

CTR[31−0]

16.5.5 CAP1-CAP4 Registers
These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (capture a timestamp) when their respective LD inputs are strobed.
Loading of the capture registers can be inhibited via control bit CAPLDEN. During one-shot operation, this
bit is cleared (loading is inhibited) automatically when a stop condition occurs, StopValue = Mod4.
CAP1 and CAP2 registers become the active period and compare registers, respectively, in APWM mode.
CAP3 and CAP4 registers become the respective shadow registers (APRD and ACMP) for CAP1 and
CAP2 during APWM operation.

16.5.6 Using SWSYNC with the ECAP Module
The SWSYNC of the ECAP module is logical OR’d with the SYNC signal as shown in Figure 16-7. The
SYNC signal is defined by the selection in the SYNCSEL[ECAPxSYNCIN] bit for ECAP1 and ECAP4 as
shown in Figure 16-8.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2035

Capture Mode Description

www.ti.com

Figure 16-8. Time-Base Counter Synchronization Scheme 4
EXTSYNCIN1

EXTSYNCIN2

EPWM1

EPWM1SYNCOUT

EPWM2

EPWM4

EPWM3

EXTSYNCOUT

EPWM4SYNCOUT

Pulse-Stretched
(8 PLLSYSCLK
Cycles)

EPWM5

SYNCSEL.EPWM4SYNCIN

EPWM6

EPWM7

EPWM7SYNCOUT

EPWM8
SYNCSEL.EPWM7SYNCIN

EPWM9

EPWM10

EPWM10SYNCOUT

EPWM11
SYNCSEL.EPWM10SYNCIN

EPWM12

ECAP1
ECAP1SYNCOUT
SYNCSEL.SYNCOUT

SYNCSEL.ECAP1SYNCIN

ECAP2

ECAP3

SYNCSEL.ECAP4SYNCIN

ECAP4

ECAP5

ECAP6

Other ECAP modules receive the SYNC signal from the previous ECAP module. To use SWYNC with
ECAP1 and ECAP4, the following workaround can be implemented:
• Select an unused GPIO in InputXbarRegs.INPUT5SELECT.
• Configure this GPIO in output mode and Write ‘0’ to GPIO DAT register. By default this is programmed
to GPIO0 so any activity on this pin will cause problems with the SWSYNC
• Program SYNCSEL[ECAPxSYNCIN] = 0x101. This will take ECAPx.EXTSYNCIN to an inactive state.
To use SWSYNC with other ECAP modules, take measures to ensure that the previous ECAP chain is not
generating a SYNCOUT signal which will interfere with the software synchronization.

16.5.7 Interrupt Control
An Interrupt can be generated on capture events (CEVT1-CEVT4, CTROVF) or APWM events (CTR =
PRD, CTR = CMP).
A counter overflow event (FFFFFFFF->00000000) is also provided as an interrupt source (CTROVF).
The capture events are edge and sequencer qualified (ordered in time) by the polarity select and Mod4
gating, respectively.
One of these events can be selected as the interrupt source (from the eCAPx module) going to the PIE.

2036

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Capture Mode Description

www.ti.com

Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF, CTR=PRD, CTR=CMP) can be
generated. The interrupt enable register (ECEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (ECFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT). An interrupt pulse is generated to the PIE only if any of the interrupt
events are enabled, the flag bit is 1, and the INT flag bit is 0. The interrupt service routine must clear the
global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR) before any other
interrupt pulses are generated. You can force an interrupt event via the interrupt force register (ECFRC).
This is useful for test purposes.
Note: The CEVT1, CEVT2, CEVT3, CEVT4 flags are only active in capture mode (ECCTL2[CAP/APWM
== 0]). The CTR=PRD, CTR=CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM == 1]).
CNTOVF flag is valid in both modes.
Figure 16-9. Interrupts in eCAP Module
ECFLG
Clear

ECCLR
ECFRC

Latch
ECEINT

Set

CEVT1

ECFLG
Clear

ECCLR
ECFRC

Latch
ECFLG
ECEINT

ECCLR

Set
ECFLG

Clear

Clear

Latch

ECEINT

ECAPxINT

ECCLR
ECFRC

Latch

Set

Generate
interrupt
pulse when
input=1

CEVT2

1

Set

CEVT3

ECFLG

0

Clear
0

ECCLR
ECFRC

Latch
ECEINT

Set

CEVT4

ECFLG
Clear

ECCLR
ECFRC

Latch

CTROVF

Set

ECEINT
ECFLG

Clear

ECCLR
ECFRC

Latch
ECEINT

PRDEQ

Set
ECFLG
Clear
Latch

ECEINT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Set

ECCLR
ECFRC
CMPEQ

Enhanced Capture (eCAP)

2037

Capture Mode Description

www.ti.com

16.5.8 Shadow Load and Lockout Control
In capture mode, this logic inhibits (locks out) any shadow loading of CAP1 or CAP2 from APRD and
ACMP registers, respectively.
In APWM mode, shadow loading is active and two choices are permitted:
• Immediate - APRD or ACMP are transferred to CAP1 or CAP2 immediately upon writing a new value.
• On period equal, CTR[31:0] = PRD[31:0]

16.5.9 APWM Mode Operation
Main operating highlights of the APWM section:
• The time-stamp counter bus is made available for comparison via 2 digital (32-bit) comparators.
• When CAP1/2 registers are not used in capture mode, their contents can be used as Period and
Compare values in APWM mode.
• Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4). The shadow register
contents are transferred over to CAP1/2 registers either immediately upon a write, or on a CTR = PRD
trigger.
• In APWM mode, writing to CAP1/CAP2 active registers will also write the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 will invoke the shadow mode.
• During initialization, you must write to the active registers for both period and compare. This
automatically copies the initial values into the shadow values. For subsequent compare updates,
during run-time, you only need to use the shadow registers.
Figure 16-10. PWM Waveform Details Of APWM Mode Operation
TSCTR
FFFFFFFF
APRD

1000h

500h
ACMP

300h

0000000C
APWMx
(o/p pin)

On
time

Off−time

Period

The behavior of APWM active high mode (APWMPOL == 0) is as follows:
CMP = 0x00000000, output low for duration of period (0% duty)
CMP = 0x00000001, output high 1 cycle
CMP = 0x00000002, output high 2 cycles
CMP = PERIOD, output high except for 1 cycle (<100% duty)
CMP = PERIOD+1, output high for complete period (100% duty)
CMP > PERIOD+1, output high for complete period

The behavior of APWM active low mode (APWMPOL == 1) is as follows:
2038

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Application of the ECAP Module

www.ti.com
CMP = 0x00000000, output high for duration of period (0% duty)
CMP = 0x00000001, output low 1 cycle
CMP = 0x00000002, output low 2 cycles
CMP = PERIOD, output low except for 1 cycle (<100% duty)
CMP = PERIOD+1, output low for complete period (100% duty)
CMP > PERIOD+1, output low for complete period

Figure 16-11. Time-Base Frequency and Period Calculation
TPWM

3

3

3

2

TPWM

2

2

1
0

4

4

4

1

1
0

0

FPWM

CAP1 1 u T TSCTR
1
TPWM

16.6 Application of the ECAP Module
The following sections will provide Applications examples and code snippets to show how to configure and
operate the eCAP module. For clarity and ease of use, the examples use the eCAP “C” header files.
Below are useful #defines which will help in the understanding of the examples.

// ECCTL1 (ECAP Control Reg 1)
//==========================
// CAPxPOL bits
// CTRRSTx bits
// PRESCALE bits

#define EC_RISING 0x0
#define EC_ABS_MODE 0x0
#define EC_BYPASS 0x0

#define
#define
#define
#define
#define

EC_FALLING 0x1
EC_DELTA_MODE 0x1
EC_DIV1 0x0 #define EC_DIV2 0x1
EC_DIV4 0x2 #define EC_DIV6 0x3
EC_DIV8 0x4 #define EC_DIV10 0x5

// ECCTL2 ( ECAP Control Reg 2)
//==========================
// CONT/ONESHOT bit #define EC_CONTINUOUS 0x0 #define
// STOPVALUE bit
#define EC_EVENT1 0x0
#define
#define
// RE-ARM bit #define EC_ARM 0x1
// TSCTRSTOP bit
#define EC_FREEZE 0x0
#define
// SYNCO_SEL bit
#define EC_SYNCIN 0x0
#define
#define
// CAP/APWM mode bit #define EC_CAP_MODE 0x0
#define
// APWMPOL bit
#define EC_ACTV_HI 0x0
#define
// Generic
#define EC_DISABLE 0x0
#define

EC_ONESHOT 0x1
EC_EVENT2 0x1 #define EC_EVENT3 0x2
EC_EVENT4 0x3
EC_RUN 0x1
EC_CTR_PRD 0x1
EC_SYNCO_DIS 0x2
EC_APWM_MODE 0x1
EC_ACTV_LO 0x1
EC_ENABLE 0x1 #define EC_FORCE 0x1

16.6.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger
Figure 16-12 shows an example of continuous capture operation (Mod4 counter wraps around). In this
figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this
gives period (and frequency) information.
On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the
next state. When the TSCTR reaches FFFFFFFF (maximum value), it wraps around to 00000000 (not
shown in Figure 16-12), if this occurs, the CTROVF (counter overflow) flag is set, and an interrupt (if
enabled) occurs, CTROVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. Captured
Time-stamps are valid at the point indicated by the diagram (after the 4th event), hence event CEVT4 can
conveniently be used to trigger an interrupt and the CPU can read data from the CAPx registers.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2039

Application of the ECAP Module

www.ti.com

Figure 16-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect
CEVT1

CEVT2

CEVT3

CEVT4

CEVT1

CAPx pin
t5

t4

FFFFFFFF

t3
t2
t1

CTR[0−31]
00000000
MOD4
CTR
CAP1

0

1

2

XX

3

0

1

t5

t1

CAP2

XX

t2

XX

CAP3

t3

XX

CAP4

t4
t

Polarity selection
Capture registers [1−4]

2040

Enhanced Capture (eCAP)

All capture values valid
(can be read) at this time

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Application of the ECAP Module

www.ti.com

16.6.1.1 Code snippet for CAP mode Absolute Time, Rising Edge Trigger
// Code snippet for CAP mode Absolute Time, Rising edge trigger
// Initialization Time
//=======================
// ECAP module 1 config
ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST3 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1;
ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_CONTINUOUS;
ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE;
ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN;
// Allow TSCTR to run
// Run Time (CEVT4 triggered ISR call)
//==========================================
TSt1 = ECap1Regs.CAP1;
// Fetch Time-Stamp captured at
// Fetch Time-Stamp captured at
// Fetch Time-Stamp captured at
// Fetch Time-Stamp captured at
// Calculate 1st period Period2
// Calculate 2nd period Period3
// Calculate 3rd period

t1 TSt2 = ECap1Regs.CAP2;
t2 TSt3 = ECap1Regs.CAP3;
t3 TSt4 = ECap1Regs.CAP4;
t4 Period1 = TSt2-TSt1;
= TSt3-TSt2;
= TSt4-TSt3;

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2041

Application of the ECAP Module

www.ti.com

16.6.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger
In Figure 16-13 the eCAP operating mode is almost the same as in the previous section except capture
events are qualified as either rising or falling edge, this now gives both period and duty cycle information,
i.e: Period1 = t3 – t1, Period2 = t5 – t3, …etc. Duty Cycle1 (on-time %) = (t2 – t1) / Period1 x 100%, and so
on. Duty Cycle1 (off-time %) = (t3 – t2) / Period1 x 100%, and so on.
Figure 16-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect
CEVT2

CEVT4

CEVT1

CEVT2

CEVT3

CEVT1

CEVT4
CEVT1
CEVT3

CAPx pin
FFFFFFFF
t6

t5
CTR[0−31]

t3

t9

t8

t7

t4

t2
t1
00000000
MOD4
CTR
CAP1

CAP2

0

1

2

XX

3

0

1

t1

XX

0

t6

t3

XX

CAP4

3

t5

t2

XX

CAP3

2

t7

t4

t8
tt

Polarity selection
Capture registers [1−4]

2042

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Application of the ECAP Module

www.ti.com

16.6.2.1 Code Snippet for CAP mode Absolute Time, Rising and Falling Edge Triggers
// Code snippet for CAP mode Absolute Time, Rising and Falling
// edge triggers // Initialization Time
//=======================
// ECAP module 1 config
ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_FALLING;
ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_FALLING;
ECap1Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST3 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1;
ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_CONTINUOUS;
ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE;
ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN;
// Allow TSCTR to run
// Run Time (CEVT4 triggered ISR call)
//==========================================
TSt1 = ECap1Regs.CAP1;
// Fetch Time-Stamp captured at t1 TSt2 = ECap1Regs.CAP2;
// Fetch Time-Stamp captured at t2 TSt3 = ECap1Regs.CAP3;
// Fetch Time-Stamp captured at t3 TSt4 = ECap1Regs.CAP4;
// Fetch Time-Stamp captured at t4 Period1 = TSt3-TSt1;
// Calculate 1st period DutyOnTime1 = TSt2-TSt1;
// Calculate On time DutyOffTime1 = TSt3-TSt2;
// Calculate Off time

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2043

Application of the ECAP Module

www.ti.com

16.6.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger
This example Figure 16-14 shows how the eCAP module can be used to collect Delta timing data from
pulse train waveforms. Here Continuous Capture mode (TSCTR counts-up without resetting, and Mod4
counter wraps around) is used. In Delta-time mode, TSCTR is Reset back to Zero on every valid event.
Here Capture events are qualified as Rising edge only. On an event, TSCTR contents (Time-Stamp) is
captured first, and then TSCTR is reset to Zero. The Mod4 counter then increments to the next state. If
TSCTR reaches FFFFFFFF (Max value), before the next event, it wraps around to 00000000 and
continues, a CNTOVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. The advantage
of Delta-time Mode is that the CAPx contents directly give timing data without the need for CPU
calculations, that is, Period1 = T1, Period2 = T2,…and so on. As shown in the diagram, the CEVT1 event is
a good trigger point to read the timing data, T1, T2, T3, T4 are all valid here.
Figure 16-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect
CEVT1

CEVT3

CEVT2

CEVT4

CEVT1

CAPx pin
T1

FFFFFFFF

T3

T2

T4

CTR[0−31]

00000000
MOD4
CTR

CAP1

0

1

2

XX

3

0

1

CTR value at CEVT1

t4

XX

CAP2

t1

XX

CAP3

t2

XX

CAP4

t3
t

Polarity selection
Capture registers [1−4]

2044

Enhanced Capture (eCAP)

All capture values valid
(can be read) at this time

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Application of the ECAP Module

www.ti.com

16.6.3.1 Code snippet for CAP mode Delta Time, Rising Edge Trigger
// Code snippet for CAP mode Delta Time, Rising edge trigger
// Initialization Time
//=======================
// ECAP module 1 config
ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CTRRST1 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST3 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1;
ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_CONTINUOUS;
ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE;
ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN;
// Allow TSCTR to run
// Run Time (CEVT1 triggered ISR call)
//==========================================
//
//
//
//
//

Note:
Fetch
Fetch
Fetch
Fetch

here Time-stamp directly represents
Time-Stamp captured at T1 Period1 =
Time-Stamp captured at T2 Period2 =
Time-Stamp captured at T3 Period3 =
Time-Stamp captured at T4

the Period value. Period4 = ECap1Regs.CAP1;
ECap1Regs.CAP2;
ECap1Regs.CAP3;
ECap1Regs.CAP4;

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2045

Application of the ECAP Module

www.ti.com

16.6.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger
In Figure 16-15 the eCAP operating mode is almost the same as in the previous section except Capture
events are qualified as either Rising or Falling edge. This now gives both Period and Duty cycle
information, that is, Period1 = T1+T2, Period2 = T3+T4, …and so on, Duty Cycle1 (on-time %) = T1 /
Period1 x 100%, and so on, Duty Cycle1 (off-time %) = T2 / Period1 x 100%, and so on.
Figure 16-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect
CEVT4

CEVT2

CEVT2

CEVT3

CEVT1

CEVT4
CEVT5
CEVT3

CEVT1

CAPx pin
T1

FFFFFFFF

T3

T5

T8

T2

T6
T4

T7

CTR[0−31]

00000000
MOD4
CTR
CAP1

CAP2

0

1

XX

2

3

0

1

2

CAP3

CAP4

t5

t1

XX

t2

XX

0

t4

CTR value at CEVT1

XX

3

t6

t3

t7
t

Polarity selection
Capture registers [1−4]

During initialization, you must write to the active registers for both period and compare. This will then
automatically copy the init values into the shadow values. For subsequent compare updates, during runtime, only the shadow registers must be used.

2046

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Application of the ECAP Module

www.ti.com

16.6.4.1 Code snippet for CAP mode Delta Time, Rising and Falling Edge Triggers
// Code snippet for CAP mode Delta Time, Rising and Falling
// edge triggers
// Initialization Time
//=======================
// ECAP module 1 config
ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_FALLING;
ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_FALLING;
ECap1Regs.ECCTL1.bit.CTRRST1 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST3 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1;
ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_CONTINUOUS;
ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE;
ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN;
// Allow TSCTR to run
// Run Time (CEVT1 triggered ISR call)
//==========================================
//
Note: here Time-stamp directly represents the Duty cycle values. DutyOnTime1 = ECap1Regs.CAP2;
// Fetch Time-Stamp captured
// Fetch Time-Stamp captured
// Fetch Time-Stamp captured
// Fetch TimeStamp captured at T1 Period1

at T2 DutyOffTime1 = ECap1Regs.CAP3;
at T3 DutyOnTime2 = ECap1Regs.CAP4;
at T4 DutyOffTime2 = ECap1Regs.CAP1;
= DutyOnTime1 + DutyOffTime1; Period2 = DutyOnTime2 + DutyOffTime2;

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2047

Application of the APWM Mode

www.ti.com

16.7 Application of the APWM Mode
In this example, the eCAP module is configured to operate as a PWM generator. Here a very simple
single channel PWM waveform is generated from output pin APWMx. The PWM polarity is active high,
which means that the compare value (CAP2 reg is now a compare register) represents the on-time (high
level) of the period. Alternatively, if the APWMPOL bit is configured for active low, then the compare value
represents the off-time. Note here values are in hexadecimal (“h”) notation.

16.7.1 Example 1 - Simple PWM Generation (Independent Channel/s)
Figure 16-16. PWM Waveform Details of APWM Mode Operation
TSCTR
FFFFFFFF
APRD

1000h

500h
ACMP

300h

0000000C
APWMx
(o/p pin)

On
time

Off−time

Period

Example 16-1. Code Snippet for APWM Mode
// Code snippet for APWM mode Example 1
// Initialization Time
//=======================
// ECAP module 1 config ECap1Regs.CAP1 = 0x1000;
// Set period value ECap1Regs.CTRPHS = 0x0;
// make phase zero ECap1Regs.ECCTL2.bit.CAP_APWM = EC_APWM_MODE;
ECap1Regs.ECCTL2.bit.APWMPOL = EC_ACTV_HI;
// Active high ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE;
// Synch not used ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
// Synch not used ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN;
// Allow TSCTR to run
// Run Time (Instant 1, for example, ISR call)
//======================
ECap1Regs.CAP2 = 0x300;
2048

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Application of the APWM Mode

www.ti.com

Example 16-1. Code Snippet for APWM Mode (continued)
// Set Duty cycle, that

is,

compare value

// Run Time (Instant 2, for example, another ISR call)
//======================\
ECap1Regs.CAP2 = 0x500;
// Set Duty cycle, that is, compare value

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2049

Registers

www.ti.com

16.8 Registers
16.8.1 eCAP Base Addresses
Table 16-1. eCAP Base Address Table

2050

Device Register

Register Name

Start Address

End Address

ECap1Regs

ECAP_REGS

0x0000_5000

0x0000_501F

ECap2Regs

ECAP_REGS

0x0000_5020

0x0000_503F

ECap3Regs

ECAP_REGS

0x0000_5040

0x0000_505F

ECap4Regs

ECAP_REGS

0x0000_5060

0x0000_507F

ECap5Regs

ECAP_REGS

0x0000_5080

0x0000_509F

ECap6Regs

ECAP_REGS

0x0000_50A0

0x0000_50BF

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

16.8.2 ECAP_REGS Registers
Table 16-2 lists the memory-mapped registers for the ECAP_REGS. All register offset addresses not listed
in Table 16-2 should be considered as reserved locations and the register contents should not be
modified.
Table 16-2. ECAP_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

TSCTR

Time-Stamp Counter

Go

2h

CTRPHS

Counter Phase Offset Value Register

Go

4h

CAP1

Capture 1 Register

Go

6h

CAP2

Capture 2 Register

Go

8h

CAP3

Capture 3 Register

Go

Ah

CAP4

Capture 4 Register

14h

ECCTL1

Capture Control Register 1

EALLOW

Go

15h

ECCTL2

Capture Control Register 2

EALLOW

Go

16h

ECEINT

Capture Interrupt Enable Register

EALLOW

Go

17h

ECFLG

Capture Interrupt Flag Register

Go

18h

ECCLR

Capture Interrupt Clear Register

Go

19h

ECFRC

Capture Interrupt Force Register

Go

Go

Complex bit access types are encoded to fit into small table cells. Table 16-3 shows the codes that are
used for access types in this section.
Table 16-3. ECAP_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2051

Registers

www.ti.com

16.8.2.1 TSCTR Register (Offset = 0h) [reset = 0h]
TSCTR is shown in Figure 16-17 and described in Table 16-4.
Return to Summary Table.
Time-Stamp Counter
Figure 16-17. TSCTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TSCTR
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 16-4. TSCTR Register Field Descriptions
Bit
31-0

2052

Field

Type

Reset

Description

TSCTR

R/W

0h

Active 32-bit counter register that is used as the capture time-base
Reset type: SYSRSn

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

16.8.2.2 CTRPHS Register (Offset = 2h) [reset = 0h]
CTRPHS is shown in Figure 16-18 and described in Table 16-5.
Return to Summary Table.
Counter Phase Offset Value Register
Figure 16-18. CTRPHS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CTRPHS
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 16-5. CTRPHS Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CTRPHS

R/W

0h

Counter phase value register that can be programmed for phase
lag/lead. This register shadows
TSCTR and is loaded into TSCTR upon either a SYNCI event or
S/W force via a control bit. Used
to achieve phase control synchronization with respect to other eCAP
and EPWM time-bases.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2053

Registers

www.ti.com

16.8.2.3 CAP1 Register (Offset = 4h) [reset = 0h]
CAP1 is shown in Figure 16-19 and described in Table 16-6.
Return to Summary Table.
Capture 1 Register
Figure 16-19. CAP1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CAP1
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 16-6. CAP1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

CAP1

R/W

0h

This register can be loaded (written) by:
- Time-Stamp ( counter value) during a capture event
- Software - may be useful for test purposes
- APRD shadow register (CAP3) when used in APWM mode
Reset type: SYSRSn

2054

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

16.8.2.4 CAP2 Register (Offset = 6h) [reset = 0h]
CAP2 is shown in Figure 16-20 and described in Table 16-7.
Return to Summary Table.
Capture 2 Register
Figure 16-20. CAP2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CAP2
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 16-7. CAP2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

CAP2

R/W

0h

This register can be loaded (written) by:
- Time-Stamp ( counter value) during a capture event
- Software - may be useful for test purposes
- APRD shadow register (CAP4) when used in APWM mode
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2055

Registers

www.ti.com

16.8.2.5 CAP3 Register (Offset = 8h) [reset = 0h]
CAP3 is shown in Figure 16-21 and described in Table 16-8.
Return to Summary Table.
Capture 3 Register
Figure 16-21. CAP3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CAP3
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 16-8. CAP3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

CAP3

R/W

0h

In CMP mode, this is a time-stamp capture register. In APWM mode,
this is the period shadow
(APRD) register. You update the PWM period value through this
register. In this mode, CAP3
(APRD) shadows CAP1.
Reset type: SYSRSn

2056

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

16.8.2.6 CAP4 Register (Offset = Ah) [reset = 0h]
CAP4 is shown in Figure 16-22 and described in Table 16-9.
Return to Summary Table.
Capture 4 Register
Figure 16-22. CAP4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CAP4
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 16-9. CAP4 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

CAP4

R/W

0h

In CMP mode, this is a time-stamp capture register. In APWM mode,
this is the compare shadow
(ACMP) register. You update the PWM compare value via this
register. In this mode, CAP4
(ACMP) shadows CAP2.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2057

Registers

www.ti.com

16.8.2.7 ECCTL1 Register (Offset = 14h) [reset = 0h]
ECCTL1 is shown in Figure 16-23 and described in Table 16-10.
Return to Summary Table.
Capture Control Register 1
Figure 16-23. ECCTL1 Register
15

14

13

12

11
PRESCALE
R/W-0h

10

9

8
CAPLDEN
R/W-0h

6
CAP4POL
R/W-0h

5
CTRRST3
R/W-0h

4
CAP3POL
R/W-0h

3
CTRRST2
R/W-0h

2
CAP2POL
R/W-0h

1
CTRRST1
R/W-0h

0
CAP1POL
R/W-0h

FREE_SOFT
R/W-0h
7
CTRRST4
R/W-0h

Table 16-10. ECCTL1 Register Field Descriptions
Field

Type

Reset

Description

15-14

Bit

FREE_SOFT

R/W

0h

Emulation Control
Reset type: SYSRSn
0h (R/W) = TSCTR counter stops immediately on emulation suspend
1h (R/W) = TSCTR counter runs until = 0
2h (R/W) = TSCTR counter is unaffected by emulation suspend (Run
Free)
3h (R/W) = TSCTR counter is unaffected by emulation suspend (Run
Free)

13-9

PRESCALE

R/W

0h

Event Filter prescale select
Reset type: SYSRSn
0h (R/W) = Divide by 1 (i.e,. no prescale, by-pass the prescaler)
1h (R/W) = Divide by 2
2h (R/W) = Divide by 4
3h (R/W) = Divide by 6
4h (R/W) = Divide by 8
5h (R/W) = Divide by 10
1Eh (R/W) = Divide by 60
1Fh (R/W) = Divide by 62

8

CAPLDEN

R/W

0h

Enable Loading of CAP1-4 registers on a capture event. Note that
this bit does not disable CEVTn events from being generated.
Reset type: SYSRSn
0h (R/W) = Disable CAP1-4 register loads at capture event time.
1h (R/W) = Enable CAP1-4 register loads at capture event time.

7

CTRRST4

R/W

0h

Counter Reset on Capture Event 4
Reset type: SYSRSn
0h (R/W) = Do not reset counter on Capture Event 4 (absolute time
stamp operation)
1h (R/W) = Reset counter after Capture Event 4 time-stamp has
been captured

6

CAP4POL

R/W

0h

(used in difference mode operation)

2058

Enhanced Capture (eCAP)

Capture Event 4 Polarity select
Reset type: SYSRSn
0h (R/W) = Capture Event 4 triggered on a rising edge (RE)
1h (R/W) = Capture Event 4 triggered on a falling edge (FE)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 16-10. ECCTL1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5

CTRRST3

R/W

0h

Counter Reset on Capture Event 3
Reset type: SYSRSn
0h (R/W) = Do not reset counter on Capture Event 3 (absolute time
stamp)
1h (R/W) = Reset counter after Event 3 time-stamp has been
captured

4

CAP3POL

R/W

0h

Capture Event 3 Polarity select
Reset type: SYSRSn
0h (R/W) = Capture Event 3 triggered on a rising edge (RE)
1h (R/W) = Capture Event 3 triggered on a falling edge (FE)

3

CTRRST2

R/W

0h

Counter Reset on Capture Event 2
Reset type: SYSRSn
0h (R/W) = Do not reset counter on Capture Event 2 (absolute time
stamp)
1h (R/W) = Reset counter after Event 2 time-stamp has been
captured

2

CAP2POL

R/W

0h

Capture Event 2 Polarity select
Reset type: SYSRSn
0h (R/W) = Capture Event 2 triggered on a rising edge (RE)
1h (R/W) = Capture Event 2 triggered on a falling edge (FE)

1

CTRRST1

R/W

0h

Counter Reset on Capture Event 1
Reset type: SYSRSn
0h (R/W) = Do not reset counter on Capture Event 1 (absolute time
stamp)
1h (R/W) = Reset counter after Event 1 time-stamp has been
captured (used in difference mode operation)

0

CAP1POL

R/W

0h

Capture Event 1 Polarity select
Reset type: SYSRSn
0h (R/W) = Capture Event 1 triggered on a rising edge (RE)
1h (R/W) = Capture Event 1 triggered on a falling edge (FE)

(used in difference mode operation)

(used in difference mode operation)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2059

Registers

www.ti.com

16.8.2.8 ECCTL2 Register (Offset = 15h) [reset = 6h]
ECCTL2 is shown in Figure 16-24 and described in Table 16-11.
Return to Summary Table.
Capture Control Register 2
Figure 16-24. ECCTL2 Register
15

14

13
RESERVED
R-0h

12

11

10
APWMPOL
R/W-0h

9
CAP_APWM
R/W-0h

8
SWSYNC
R/W-0h

6

5
SYNCI_EN

4
TSCTRSTOP

3
REARM

2

1

SYNCO_SEL
R/W-0h

R/W-0h

R/W-0h

R/W-0h

0
CONT_ONESH
T
R/W-0h

7

STOP_WRAP
R/W-3h

Table 16-11. ECCTL2 Register Field Descriptions
Field

Type

Reset

Description

15-11

Bit

RESERVED

R

0h

Reserved

10

APWMPOL

R/W

0h

APWM output polarity select.
Reset type: SYSRSn
0h (R/W) = Output is active high (Compare value defines high time)
1h (R/W) = Output is active low (Compare value defines low time)

9

CAP_APWM

R/W

0h

CAP/APWM operating mode select
Reset type: SYSRSn
0h (R/W) = ECAP module operates in capture mode. This mode
forces the following
configuration:
- Inhibits TSCTR resets via CTR = PRD event
- Inhibits shadow loads on CAP1 and 2 registers
- Permits user to enable CAP1-4 register load
- CAPx/APWMx pin operates as a capture input
1h (R/W) = ECAP module operates in APWM mode. This mode
forces the following
configuration:
- Resets TSCTR on CTR = PRD event (period boundary
- Permits shadow loading on CAP1 and 2 registers
- Disables loading of time-stamps into CAP1-4 registers
- CAPx/APWMx pin operates as a APWM output

8

SWSYNC

R/W

0h

Software-forced Counter (TSCTR) Synchronizing.
Reset type: SYSRSn
0h (R/W) = Writing a zero has no effect. Reading always returns a
zero
1h (R/W) = Writing a one forces a TSCTR shadow load of current
ECAP module and any
ECAP modules down-stream providing the SYNCO_SEL bits are
0,0. After writing
a 1, this bit returns to a zero.
Note: Selection CTR = PRD is meaningful only in APWM mode
however, you can
choose it in CAP mode if you find doing so useful.

2060

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 16-11. ECCTL2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-6

SYNCO_SEL

R/W

0h

Sync-Out Select
Reset type: SYSRSn
0h (R/W) = Select sync-in event to be the sync-out signal pass
through
1h (R/W) = Select CTR = PRD event to be the sync-out signal
2h (R/W) = Disable sync out signal
3h (R/W) = Disable sync out signal

5

SYNCI_EN

R/W

0h

Counter (TSCTR) Sync-In select mode
Reset type: SYSRSn
0h (R/W) = Disable sync-in option
1h (R/W) = Enable counter (TSCTR) to be loaded from CTRPHS
register upon either a SYNCI signal or a S/W force event.

4

TSCTRSTOP

R/W

0h

Time Stamp (TSCTR) Counter Stop (freeze) Control
Reset type: SYSRSn
0h (R/W) = TSCTR stopped
1h (R/W) = TSCTR free-running

3

REARM

R/W

0h

Re-Arming Control. Note: The re-arm function is valid in one shot or
continuous mode.
Reset type: SYSRSn
0h (R/W) = Has no effect (reading always returns a 0)
1h (R/W) = Arms the one-shot sequence as follows:
1) Resets the Mod4 counter to zero
2) Unfreezes the Mod4 counter
3) Enables capture register loads

2-1

STOP_WRAP

R/W

3h

Stop value for one-shot mode. This is the number (between 1-4) of
captures allowed to occur before the CAP(1-4) registers are frozen,
that is, capture sequence is stopped.
Wrap value for continuous mode. This is the number (between 1-4)
of the capture
register in which the circular buffer wraps around and starts again.
Notes: STOP_WRAP is compared to Mod4 counter and, when
equal, 2 actions
occur:
- Mod4 counter is stopped (frozen)
- Capture register loads are inhibited
In one-shot mode, further interrupt events are blocked until rearmed.
Reset type: SYSRSn
0h (R/W) = Stop after Capture Event 1 in one-shot mode
Wrap after Capture Event 1 in continuous mode.
1h (R/W) = Stop after Capture Event 2 in one-shot mode
Wrap after Capture Event 2 in continuous mode.
2h (R/W) = Stop after Capture Event 3 in one-shot mode
Wrap after Capture Event 3 in continuous mode.
3h (R/W) = Stop after Capture Event 4 in one-shot mode
Wrap after Capture Event 4 in continuous mode.

0

CONT_ONESHT

R/W

0h

Continuous or one-shot mode control (applicable only in capture
mode)
Reset type: SYSRSn
0h (R/W) = Operate in continuous mode
1h (R/W) = Operate in one-Shot mode

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2061

Registers

www.ti.com

16.8.2.9 ECEINT Register (Offset = 16h) [reset = 0h]
ECEINT is shown in Figure 16-25 and described in Table 16-12.
Return to Summary Table.
The interrupt enable bits (CEVT1, ...) block any of the selected events from generating an interrupt.
Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the
ECFRC/ECCLR registers.
The proper procedure for configuring peripheral modes and interrupts is as follows:
- Disable global interrupts
- Stop eCAP counter
- Disable eCAP interrupts
- Configure peripheral registers
- Clear spurious eCAP interrupt flags
- Enable eCAP interrupts
- Start eCAP counter
- Enable global interrupts
Figure 16-25. ECEINT Register
15

14

13

12

11

10

9

8

3
CEVT3
R/W-0h

2
CEVT2
R/W-0h

1
CEVT1
R/W-0h

0
RESERVED
R/W-0h

RESERVED
R/W-0h
7
CTR_EQ_CMP
R/W-0h

6
CTR_EQ_PRD
R/W-0h

5
CTROVF
R/W-0h

4
CEVT4
R/W-0h

Table 16-12. ECEINT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

0h

Reserved

7

CTR_EQ_CMP

R/W

0h

Counter Equal Compare Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Compare Equal as an Interrupt source
1h (R/W) = Enable Compare Equal as an Interrupt source

6

CTR_EQ_PRD

R/W

0h

Counter Equal Period Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Period Equal as an Interrupt source
1h (R/W) = Enable Period Equal as an Interrupt source

5

CTROVF

R/W

0h

Counter Overflow Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disabled counter Overflow as an Interrupt source
1h (R/W) = Enable counter Overflow as an Interrupt source

4

CEVT4

R/W

0h

Capture Event 4 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 4 as an Interrupt source
1h (R/W) = Capture Event 4 Interrupt Enable

3

CEVT3

R/W

0h

Capture Event 3 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 3 as an Interrupt source
1h (R/W) = Enable Capture Event 3 as an Interrupt source

2

CEVT2

R/W

0h

Capture Event 2 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 2 as an Interrupt source
1h (R/W) = Enable Capture Event 2 as an Interrupt source

15-8

2062

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 16-12. ECEINT Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

CEVT1

R/W

0h

Capture Event 1 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 1 as an Interrupt source
1h (R/W) = Enable Capture Event 1 as an Interrupt source

0

RESERVED

R/W

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2063

Registers

www.ti.com

16.8.2.10 ECFLG Register (Offset = 17h) [reset = 0h]
ECFLG is shown in Figure 16-26 and described in Table 16-13.
Return to Summary Table.
Capture Interrupt Flag Register
Figure 16-26. ECFLG Register
15

14

13

12

11

10

9

8

3
CEVT3
R-0h

2
CEVT2
R-0h

1
CEVT1
R-0h

0
INT
R-0h

RESERVED
R-0h
7
CTR_CMP
R-0h

6
CTR_PRD
R-0h

5
CTROVF
R-0h

4
CEVT4
R-0h

Table 16-13. ECFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

CTR_CMP

R

0h

Compare Equal Compare Status Flag. This flag is active only in
APWM mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) reached the compare
register value (ACMP)

6

CTR_PRD

R

0h

Counter Equal Period Status Flag. This flag is only active in APWM
mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) reached the period
register value (APRD) and was reset.

5

CTROVF

R

0h

Counter Overflow Status Flag. This flag is active in CAP and APWM
mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) has made the transition
from FFFFFFFF " 00000000

4

CEVT4

R

0h

Capture Event 4 Status Flag This flag is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = ndicates the fourth event occurred at ECAPx pin

3

CEVT3

R

0h

Capture Event 3 Status Flag. This flag is active only in CAP mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the third event occurred at ECAPx pin.

2

CEVT2

R

0h

Capture Event 2 Status Flag. This flag is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the second event occurred at ECAPx pin.

1

CEVT1

R

0h

Capture Event 1 Status Flag. This flag is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the first event occurred at ECAPx pin.

15-8

2064

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 16-13. ECFLG Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

INT

R

0h

Global Interrupt Status Flag
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates that an interrupt was generated.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2065

Registers

www.ti.com

16.8.2.11 ECCLR Register (Offset = 18h) [reset = 0h]
ECCLR is shown in Figure 16-27 and described in Table 16-14.
Return to Summary Table.
Capture Interrupt Clear Register
Figure 16-27. ECCLR Register
15

14

13

12

11

10

9

8

3
CEVT3
R=0/W=1-0h

2
CEVT2
R=0/W=1-0h

1
CEVT1
R=0/W=1-0h

0
INT
R/W-0h

RESERVED
R-0h
7
CTR_CMP
R=0/W=1-0h

6
CTR_PRD
R=0/W=1-0h

5
CTROVF
R=0/W=1-0h

4
CEVT4
R=0/W=1-0h

Table 16-14. ECCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

CTR_CMP

R=0/W=1

0h

Counter Equal Compare Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTR=CMP flag condition

6

CTR_PRD

R=0/W=1

0h

Counter Equal Period Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTR=PRD flag condition

5

CTROVF

R=0/W=1

0h

Counter Overflow Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTROVF flag condition

4

CEVT4

R=0/W=1

0h

Capture Event 4 Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT4 flag condition.

3

CEVT3

R=0/W=1

0h

Capture Event 3 Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT3 flag condition.

2

CEVT2

R=0/W=1

0h

Capture Event 2 Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT2 flag condition.

1

CEVT1

R=0/W=1

0h

Capture Event 1 Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT1 flag condition.

0

INT

R/W

0h

ECAP Global Interrupt Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the INT flag and enable further
interrupts to be generated if any of the event flags are set to 1

15-8

2066

Enhanced Capture (eCAP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

16.8.2.12 ECFRC Register (Offset = 19h) [reset = 0h]
ECFRC is shown in Figure 16-28 and described in Table 16-15.
Return to Summary Table.
Capture Interrupt Force Register
Figure 16-28. ECFRC Register
15

14

13

12

11

10

9

8

3
CEVT3
R/W-0h

2
CEVT2
R/W-0h

1
CEVT1
R/W-0h

0
RESERVED
R-0h

RESERVED
R-0h
7
CTR_CMP
R/W-0h

6
CTR_PRD
R/W-0h

5
CTROVF
R/W-0h

4
CEVT4
R/W-0h

Table 16-15. ECFRC Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

CTR_CMP

R/W

0h

Force Counter Equal Compare Interrupt. This event is only active in
APWM mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CTR=CMP flag bit.

6

CTR_PRD

R/W

0h

Force Counter Equal Period Interrupt. This event is only active in
APWM mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CTR=PRD flag bit.

5

CTROVF

R/W

0h

Force Counter Overflow.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 to this bit sets the CTROVF flag bit.

4

CEVT4

R/W

0h

Force Capture Event 4. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT4 flag bit

3

CEVT3

R/W

0h

Force Capture Event 3. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT3 flag bit

2

CEVT2

R/W

0h

Force Capture Event 2. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT2 flag bit.

1

CEVT1

R/W

0h

Force Capture Event 1. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Sets the CEVT1 flag bit.

0

RESERVED

R

0h

Reserved

15-8

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced Capture (eCAP)

2067

Chapter 17
SPRUHM8G – December 2013 – Revised September 2017

Enhanced QEP (eQEP)
The enhanced QEP (eQEP) module described here is a Type 0 eQEP. See the TMS320x28xx, 28xxx
DSP Peripheral Reference Guide (SPRU566) for a list of all devices with a module of the same type to
determine the differences between types and for a list of device-specific differences within a type.
The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotary
incremental encoder to get position, direction, and speed information from a rotating machine for use in a
high-performance motion and position-control system.
Topic

...........................................................................................................................

17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
17.10

2068

Introduction ...................................................................................................
Configuring Device Pins ..................................................................................
Description ....................................................................................................
Quadrature Decoder Unit (QDU)........................................................................
Position Counter and Control Unit (PCCU) .........................................................
eQEP Edge Capture Unit ..................................................................................
eQEP Watchdog..............................................................................................
Unit Timer Base ..............................................................................................
eQEP Interrupt Structure .................................................................................
Registers ......................................................................................................

Enhanced QEP (eQEP)

Page

2069
2071
2071
2074
2077
2083
2087
2087
2088
2089

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

17.1 Introduction
A single track of slots patterns the periphery of an incremental encoder disk, as shown in Figure 17-1.
These slots create an alternating pattern of dark and light lines. The disk count is defined as the number
of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added to
generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate an
absolute position. Encoder manufacturers identify the index pulse using different terms such as index,
marker, home position, and zero reference
Figure 17-1. Optical Encoder Disk
QEPA

QEPB

QEPI

To derive direction information, the lines on the disk are read out by two different photo-elements that
"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is
realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk
lines. As the disk rotates, the two photo-elements generate signals that are shifted 90° out of phase from
each other. These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction
for most encoders is defined as the QEPA channel going positive before the QEPB channel and vise
versa as shown in Figure 17-2.
Figure 17-2. QEP Encoder Output Signal for Forward/Reverse Movement
T0

Clockwise shaft rotation/forward movement
0

1

2

3

4

5

6

7

N−6 N−5 N−4 N−3 N−2 N−1

0

QEPA
QEPB
QEPI

T0

Anti-clockwise shaft rotation/reverse movement
0

N−1 N−2 N−3 N−4 N−5 N−6 N−7

6

5

4

3

2

1

0

N−1 N−2

QEPA
QEPB
QEPI

Legend: N = lines per revolution

The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at
a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from
the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line
encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can
determine the velocity of the motor.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2069

Introduction

www.ti.com

Quadrature encoders from different manufacturers come with two forms of index pulse (gated index pulse
or ungated index pulse) as shown in Figure 17-3. A nonstandard form of index pulse is ungated. In the
ungated configuration, the index edges are not necessarily coincident with A and B signals. The gated
index pulse is aligned to any of the four quadrature edges and width of the index pulse and can be equal
to a quarter, half, or full period of the quadrature signal.
Figure 17-3. Index Pulse Example
T0
QEPA

QEPB

0.25T0 ±0.1T0
QEPI
(gated to
A and B)
0.5T0 ±0.1T0
QEPI
(gated to A)
T0 ±0.5T0
QEPI
(ungated)

Some typical applications of shaft encoders include robotics and even computer input in the form of a
mouse. Inside your mouse you can see where the mouse ball spins a pair of axles (a left/right, and an
up/down axle). These axles are connected to optical shaft encoders that effectively tell the computer how
fast and in what direction the mouse is moving.
General Issues: Estimating velocity from a digital position sensor is a cost-effective strategy in motor
control. Two different first order approximations for velocity may be written as:
x(k) * x(k * 1)
v(k) [
+ DX
T
T
X
X
v(k) [
+
t(k) * t(k * 1)
DT

(1)
(2)

where
v(k): Velocity at time instant k
x(k): Position at time instant k
x(k-1): Position at time instant k-1
T: Fixed unit time or inverse of velocity calculation rate
ΔX: Incremental position movement in unit time
t(k): Time instant "k"
t(k-1): Time instant "k-1"
X: Fixed unit position
ΔT: Incremental time elapsed for unit position movement.
Equation 1 is the conventional approach to velocity estimation and it requires a time base to provide unit
time event for velocity calculation. Unit time is basically the inverse of the velocity calculation rate.

2070

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Configuring Device Pins

www.ti.com

The encoder count (position) is read once during each unit time event. The quantity [x(k) - x(k-1)] is
formed by subtracting the previous reading from the current reading. Then the velocity estimate is
computed by multiplying by the known constant 1/T (where T is the constant time between unit time
events and is known in advance).
Estimation based on Equation 1 has an inherent accuracy limit directly related to the resolution of the
position sensor and the unit time period T. For example, consider a 500-line per revolution quadrature
encoder with a velocity calculation rate of 400 Hz. When used for position the quadrature encoder gives a
four-fold increase in resolution, in this case, 2000 counts per revolution. The minimum rotation that can be
detected is therefore 0.0005 revolutions, which gives a velocity resolution of 12 rpm when sampled at 400
Hz. While this resolution may be satisfactory at moderate or high speeds, e.g. 1% error at 1200 rpm, it
would clearly prove inadequate at low speeds. In fact, at speeds below 12 rpm, the speed estimate would
erroneously be zero much of the time.
At low speed, Equation 2 provides a more accurate approach. It requires a position sensor that outputs a
fixed interval pulse train, such as the aforementioned quadrature encoder. The width of each pulse is
defined by motor speed for a given sensor resolution. Equation 2 can be used to calculate motor speed by
measuring the elapsed time between successive quadrature pulse edges. However, this method suffers
from the opposite limitation, as does Equation 1. A combination of relatively large motor speeds and high
sensor resolution makes the time interval ΔT small, and thus more greatly influenced by the timer
resolution. This can introduce considerable error into high-speed estimates.
For systems with a large speed range (that is, speed estimation is needed at both low and high speeds),
one approach is to use Equation 2 at low speed and have the DSP software switch over to Equation 1
when the motor speed rises above some specified threshold.

17.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
For proper operation of the eQEP module, input GPIO pins must be configured via the GPxQSELn
registers for synchronous input mode (with or without qualification). The asynchronous mode should not
be used for eQEP input pins. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.

17.3 Description
This section provides the eQEP inputs, memory map, and functional description.

17.3.1 EQEP Inputs
The eQEP inputs include two pins for quadrature-clock mode or direction-count mode, an index (or 0
marker), and a strobe input. The eQEP module requires that the QEPA, QEPB, and QEPI inputs are
synchronized to SYSCLK prior to entering the module. The application code should enable the
synchronous GPIO input feature on any eQEP-enabled GPIO pins (see the System Control and
Interruptschapter for more details).
• QEPA/XCLK and QEPB/XDIR
These two pins can be used in quadrature-clock mode or direction-count mode.
– Quadrature-clock Mode
The eQEP encoders provide two square wave signals (A and B) 90 electrical degrees out of phase
whose phase relationship is used to determine the direction of rotation of the input shaft and
number of eQEP pulses from the index position to derive the relative position information. For
forward or clockwise rotation, QEPA signal leads QEPB signal and vice versa. The quadrature
decoder uses these two inputs to generate quadrature-clock and direction signals.
– Direction-count Mode
In direction-count mode, direction and clock signals are provided directly from the external source.
Some position encoders have this type of output instead of quadrature output. The QEPA pin
provides the clock input and the QEPB pin provides the direction input.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2071

Description

•

•

www.ti.com

QEPI: Index or Zero Marker
The eQEP encoder uses an index signal to assign an absolute start position from which position
information is incrementally encoded using quadrature pulses. This pin is connected to the index
output of the eQEP encoder to optionally reset the position counter for each revolution. This signal can
be used to initialize or latch the position counter on the occurrence of a desired event on the index pin.
QEPS: Strobe Input
This general-purpose strobe signal can initialize or latch the position counter on the occurrence of a
desired event on the strobe pin. This signal is typically connected to a sensor or limit switch to notify
that the motor has reached a defined position.

17.3.2 Functional Description
The eQEP peripheral contains the following major functional units (as shown in Figure 17-4):
• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)
• Position counter and control unit for position measurement (PCCU)
• Quadrature edge-capture unit for low-speed measurement (QCAP)
• Unit time base for speed/frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
Figure 17-4. Functional Block Diagram of the eQEP Peripheral
System
control registers

To CPU

EQEPxENCLK
Data bus

SYSCLKOUT

QCPRD
QCTMR

QCAPCTL
16

16

16
Quadrature
capture unit
(QCAP)

QCTMRLAT
QCPRDLAT

QWDTMR
QWDPRD

QUTMR
QUPRD

Registers
used by
multiple units

32

QEPCTL
QEPSTS
QFLG

UTIME

16
UTOUT

QWDOG

QDECCTL
16

WDTOUT
PIE

QCLK
QDIR
QI
QS
PHE

EQEPxINT
32

Position counter/
control unit
(PCCU)

QPOSLAT
QPOSSLAT
QPOSILAT

Quadrature
decoder
(QDU)

PCSOUT

32
QPOSCNT
QPOSINIT
QPOSMAX

32
QPOSCMP

EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE

EQEPxA/XCLK
EQEPxB/XDIR
GPIO
MUX

EQEPxI
EQEPxS

16
QEINT
QFRC
QCLR
QPOSCTL

Enhanced QEP (eQEP) peripheral

2072

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Description

www.ti.com

17.3.3 eQEP Memory Map
Table 17-1 lists the registers with their memory locations, sizes, and reset values.
Table 17-1. EQEP Memory Map
Offset

Size(x16)/
#shadow

Reset

Register Description

QPOSCNT

0x00

2/0

0x00000000

eQEP Position Counter

QPOSINIT

0x02

2/0

0x00000000

eQEP Initialization Position Count

QPOSMAX

0x04

2/0

0x00000000

eQEP Maximum Position Count

QPOSCMP

0x06

2/1

0x00000000

eQEP Position-compare

QPOSILAT

0x08

2/0

0x00000000

eQEP Index Position Latch

QPOSSLAT

0x0A

2/0

0x00000000

eQEP Strobe Position Latch

QPOSLAT

0x0C

2/0

0x00000000

eQEP Position Latch

QUTMR

0x0E

2/0

0x00000000

QEP Unit Timer

QUPRD

0x10

2/0

0x00000000

eQEP Unit Period Register

QWDTMR

0x12

1/0

0x0000

eQEP Watchdog Timer

QWDPRD

0x13

1/0

0x0000

eQEP Watchdog Period Register

QDECCTL

0x14

1/0

0x0000

eQEP Decoder Control Register

QEPCTL

0x15

1/0

0x0000

eQEP Control Register

QCAPCTL

0x16

1/0

0x0000

eQEP Capture Control Register

QPOSCTL

0x17

1/0

0x00000

eQEP Position-compare Control Register

QEINT

0x18

1/0

0x0000

eQEP Interrupt Enable Register

QFLG

0x19

1/0

0x0000

eQEP Interrupt Flag Register

QCLR

0x1A

1/0

0x0000

eQEP Interrupt Clear Register

QFRC

0x1B

1/0

0x0000

eQEP Interrupt Force Register

QEPSTS

0x1C

1/0

0x0000

eQEP Status Register

QCTMR

0x1D

1/0

0x0000

eQEP Capture Timer

QCPRD

0x1E

1/0

0x0000

eQEP Capture Period Register

QCTMRLAT

0x1F

1/0

0x0000

eQEP Capture Timer Latch

QCPRDLAT

0x20

1/0

0x0000

eQEP Capture Period Latch

reserved

0x21
to
0x3F

31/0

Name

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2073

Quadrature Decoder Unit (QDU)

www.ti.com

17.4 Quadrature Decoder Unit (QDU)
Figure 17-5 shows a functional block diagram of the QDU.
Figure 17-5. Functional Block Diagram of Decoder Unit
QFLG:PHE

QEPSTS:QDF

QDECCTL:SWAP

QDECCTL:QAP

PHE

00
01

QCLK

10
11

iCLK
xCLK
xCLK
xCLK

QA

QDIR

10
11

EQEPxAIN

0
1

1
Quadrature
decoder

EQEPB
QB

00
01

0

EQEPA

EQEPxBIN

0

0
1

iDIR
xDIR

1
QDECCTL:QBP

1
0
x1
x2

x1, x2

2

QDECCTL:XCR

QDECCTL:QSRC

QDECCTL:QIP
EQEPxIIN

0
0

QI

1
1
QDECCTL:IGATE

EQEPxSIN

0

QS

1
QDECCTL:QSP

QDECCTL:SPSEL

EQEPxIOUT

0

PCSOUT

EQEPxSOUT
1
QDECCTL:SPSEL
EQEPxIOE

0
QDECCTL:SOEN

EQEPxSOE

1

17.4.1 Position Counter Input Modes
Clock and direction input to position counter is selected using QDECCTL[QSRC] bits, based on interface
input requirement as follows:
• Quadrature-count mode
• Direction-count mode
• UP-count mode
• DOWN-count mode
2074

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Quadrature Decoder Unit (QDU)

www.ti.com

17.4.1.1 Quadrature Count Mode
The quadrature decoder generates the direction and clock to the position counter in quadrature count
mode.
Direction Decoding— The direction decoding logic of the eQEP circuit determines which one of the
sequences (QEPA, QEPB) is the leading sequence and accordingly updates the direction
information in QEPSTS[QDF] bit. Table 17-2 and Figure 17-6 show the direction decoding logic in
truth table and state machine form. Both edges of the QEPA and QEPB signals are sensed to
generate count pulses for the position counter. Therefore, the frequency of the clock generated by
the eQEP logic is four times that of each input sequence. Figure 17-7 shows the direction decoding
and clock generation from the eQEP input signals.
Table 17-2. Quadrature Decoder Truth Table
.
Previous Edge

Present Edge

QDIR

QPOSCNT

QA↑

QB↑

UP

Increment

QB↓

DOWN

Decrement

QA↓

TOGGLE

QB↓

UP

Increment

QB↑

DOWN

Decrement

QA↑

TOGGLE

QA↑

DOWN

Increment

QA↓

UP

Decrement

QB↓

TOGGLE

QA↓

DOWN

Increment

QA↑

UP

Decrement

QB↑

TOGGLE

QA↓

QB↑

QB↓

Increment or Decrement

Increment or Decrement

Increment or Decrement

Increment or Decrement

Figure 17-6. Quadrature Decoder State Machine

(A,B)=

(00)

Increment
counter

(11)
(10)

Increment
counter
10

(01)
Decrement
counter

QEPA

Decrement
counter

00
QEPB

11

Decrement
counter

Decrement
counter
01

eQEP signals
Increment
counter

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Increment
counter

Enhanced QEP (eQEP)

2075

Quadrature Decoder Unit (QDU)

www.ti.com

Figure 17-7. Quadrature-clock and Direction Decoding
QA

QB

QCLK

QDIR

QPOSCNT

+1 +1 +1 +1 +1 +1

+1

−1 −1 −1 −1 −1 −1 −1 −1 −1 −1

−1

+1 +1 +1

−1 −1 −1 −1 −1 −1

−1

+1 +1 +1 +1 +1 +1 +1 +1 +1 +1

+1

−1 −1 −1

QA

QB

QCLK

QDIR

QPOSCNT

Phase Error Flag— In normal operating conditions, quadrature inputs QEPA and QEPB will be 90
degrees out of phase. The phase error flag (PHE) is set in the QFLG register when edge transition
is detected simultaneously on the QEPA and QEPB signals to optionally generate interrupts. State
transitions marked by dashed lines in Figure 17-6 are invalid transitions that generate a phase
error.
Count Multiplication— The eQEP position counter provides 4x times the resolution of an input clock by
generating a quadrature-clock (QCLK) on the rising/falling edges of both eQEP input clocks (QEPA
and QEPB) as shown in Figure 17-7 .
Reverse Count— In normal quadrature count operation, QEPA input is fed to the QA input of the
quadrature decoder and the QEPB input is fed to the QB input of the quadrature decoder. Reverse
counting is enabled by setting the SWAP bit in the QDECCTL register. This will swap the input to
the quadrature decoder thereby reversing the counting direction.
17.4.1.2 Direction-count Mode
Some position encoders provide direction and clock outputs, instead of quadrature outputs. In such cases,
direction-count mode can be used. QEPA input will provide the clock for position counter and the QEPB
input will have the direction information. The position counter is incremented on every rising edge of a
QEPA input when the direction input is high and decremented when the direction input is low.

2076

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Quadrature Decoder Unit (QDU)

www.ti.com

17.4.1.3 Up-Count Mode
The counter direction signal is hard-wired for up count and the position counter is used to measure the
frequency of the QEPA input. Clearing the QDECCTL[XCR] bit enables clock generation to the position
counter on both edges of the QEPA input, thereby increasing the measurement resolution by 2x factor. In
up-count mode, it is recommended that the application not configure QEPB as a GPIO mux option, or
ensure that a signal edge is not generated on the QEPB input.
17.4.1.4 Down-Count Mode
The counter direction signal is hardwired for a down count and the position counter is used to measure the
frequency of the QEPA input. Setting of the QDECCTL[XCR] bit enables clock generation to the position
counter on both edges of a QEPA input, thereby increasing the measurement resolution by 2x factor. In
down-count mode, it is recommended that the application not configure QEPB as a GPIO mux option, or
ensure that a signal edge is not generated on the QEPB input.

17.4.2 eQEP Input Polarity Selection
Each eQEP input can be inverted using QDECCTL[8:5] control bits. As an example, setting of
QDECCTL[QIP] bit will invert the index input.

17.4.3 Position-Compare Sync Output
The enhanced eQEP peripheral includes a position-compare unit that is used to generate the positioncompare sync signal on compare match between the position counter register (QPOSCNT) and the
position-compare register (QPOSCMP). This sync signal can be output using an index pin or strobe pin of
the EQEP peripheral.
Setting the QDECCTL[SOEN] bit enables the position-compare sync output and the QDECCTL[SPSEL] bit
selects either an eQEP index pin or an eQEP strobe pin.

17.5 Position Counter and Control Unit (PCCU)
The position counter and control unit provides two configuration registers (QEPCTL and QPOSCTL) for
setting up position counter operational modes, position counter initialization/latch modes and positioncompare logic for sync signal generation.

17.5.1 Position Counter Operating Modes
Position counter data may be captured in different manners. In some systems, the position counter is
accumulated continuously for multiple revolutions and the position counter value provides the position
information with respect to the known reference. An example of this is the quadrature encoder mounted on
the motor controlling the print head in the printer. Here the position counter is reset by moving the print
head to the home position and then position counter provides absolute position information with respect to
home position.
In other systems, the position counter is reset on every revolution using index pulse and position counter
provides rotor angle with respect to index pulse position.
Position counter can be configured to operate in following four modes
• Position Counter Reset on Index Event
• Position Counter Reset on Maximum Position
• Position Counter Reset on the first Index Event
• Position Counter Reset on Unit Time Out Event (Frequency Measurement)
In all the above operating modes, position counter is reset to 0 on overflow and to QPOSMAX register
value on underflow. Overflow occurs when the position counter counts up after QPOSMAX value.
Underflow occurs when position counter counts down after "0". Interrupt flag is set to indicate
overflow/underflow in QFLG register.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2077

Position Counter and Control Unit (PCCU)

www.ti.com

17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
If the index event occurs during the forward movement, then position counter is reset to 0 on the next
eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to
the value in the QPOSMAX register on the next eQEP clock.
First index marker is defined as the quadrature edge following the first index edge. The eQEP peripheral
records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event
marker (QEPSTS[FIDF]) in QEPSTS registers, it also remembers the quadrature edge on the first index
marker so that same relative quadrature transition is used for index event reset operation.
For example, if the first reset operation occurs on the falling edge of QEPB during the forward direction,
then all the subsequent reset must be aligned with the falling edge of QEPB for the forward rotation and
on the rising edge of QEPB for the reverse rotation as shown in Figure 17-8.
The position-counter value is latched to the QPOSILAT register and direction information is recorded in
the QEPSTS[QDLF] bit on every index event marker. The position-counter error flag (QEPSTS[PCEF])
and error interrupt flag (QFLG[PCE]) are set if the latched value is not equal to 0 or QPOSMAX. The
position-counter error flag (QEPSTS[PCEF]) is updated on every index event marker and an interrupt flag
(QFLG[PCE]) will be set on error that can be cleared only through software.
The index event latch configuration QEPCTL[IEL] must be configured to '00' or '11' when prcm=0 and the
position counter error flag/interrupt flag are generated only in index event reset mode.
Figure 17-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F)
QA

QB

QI

QCLK

QEPSTS:QDF
F8D

Index interrupt/
index event
marker
QPOSILAT

F9F

F8F
0

QPOSCNT F8C

1

2

...

24

25

F9D

F9B

F99

F97

24 23 22 21 20

F8E

F9E

F8F

F9C

F9A

F98

0

QEPSTS:QDLF

17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
If the position counter is equal to QPOSMAX, then the position counter is reset to 0 on the next eQEP
clock for forward movement and position counter overflow flag is set. If the position counter is equal to
ZERO, then the position counter is reset to QPOSMAX on the next QEP clock for reverse movement and
position counter underflow flag is set. Figure 17-9shows the position counter reset operation in this mode.
The first index marker fields (QEPSTS[FIDF] and QEPSTS[FIMF]) are not applicable in this mode.

2078

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Position Counter and Control Unit (PCCU)

www.ti.com

Figure 17-9. Position Counter Underflow/Overflow (QPOSMAX = 4)
QA

QB

QCLK

QDIR

QPOSCNT

1

2

3

4

0

1

2

1

0

4

3

2

1

0

4

3

2

1

2

3

4

1

0

4

3

2

1

0

1

2

3

4

0

1

2

3

4

0

1

0

4

3

0

OV/UF

QA

QB

QCLK

QDIR

QPOSCNT

OV/UF

17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
If the index event occurs during forward movement, then the position counter is reset to 0 on the next
eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to
the value in the QPOSMAX register on the next eQEP clock. Note that this is done only on the first
occurrence and subsequently the position counter value is not reset on an index event; rather, it is reset
based on maximum position as described in Section Section 17.5.1.2.
The first index marker fields (QEPSTS[FIDF] and QEPSTS[FIMF]) are not applicable in this mode.
17.5.1.4 Position Counter Reset on Unit Time out Event (QEPCTL[PCRM] = 11)
In this mode, the QPOSCNT value is latched to the QPOSLAT register and then the QPOSCNT is reset
(to 0 or QPOSMAX, depending on the direction mode selected by QDECCTL[QSRC] bits on a unit time
event). This is useful for frequency measurement.

17.5.2 Position Counter Latch
The eQEP index and strobe input can be configured to latch the position counter (QPOSCNT) into
QPOSILAT and QPOSSLAT, respectively, on occurrence of a definite event on these pins.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2079

Position Counter and Control Unit (PCCU)

www.ti.com

17.5.2.1 Index Event Latch
In some applications, it may not be desirable to reset the position counter on every index event and
instead it may be required to operate the position counter in full 32-bit mode (QEPCTL[PCRM] = 01 and
QEPCTL[PCRM] = 10 modes).
In such cases, the eQEP position counter can be configured to latch on the following events and direction
information is recorded in the QEPSTS[QDLF] bit on every index event marker.
• Latch on Rising edge (QEPCTL[IEL]=01)
• Latch on Falling edge (QEPCTL[IEL]=10)
• Latch on Index Event Marker (QEPCTL[IEL]=11)
This is particularly useful as an error checking mechanism to check if the position counter accumulated
the correct number of counts between index events. As an example, the 1000-line encoder must count
4000 times when moving in the same direction between the index events.
The index event latch interrupt flag (QFLG[IEL]) is set when the position counter is latched to the
QPOSILAT register.
Latch on Rising Edge (QEPCTL[IEL]=01)— The position counter value (QPOSCNT) is latched to the
QPOSILAT register on every rising edge of an index input.
Latch on Falling Edge (QEPCTL[IEL] = 10)— The position counter value (QPOSCNT) is latched to the
QPOSILAT register on every falling edge of index input.
Latch on Index Event Marker/Software Index Marker (QEPCTL[IEL] = 11— The first index marker is
defined as the quadrature edge following the first index edge. The eQEP peripheral records the
occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event marker
(QEPSTS[FIDF]) in the QEPSTS registers. It also remembers the quadrature edge on the first
index marker so that same relative quadrature transition is used for latching the position counter
(QEPCTL[IEL]=11).
Figure 17-10 shows the position counter latch using an index event marker.
Figure 17-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)
QA

QB

QI

QCLK

QEPSTS:QDF
F9D

F9F

FA1

FA3

FA4

QPOSCNT F9C

FA2

FA0

F9E

F9C

F9A

F98

FA5
F9E

FA0

FA2

FA4

F97
FA3

FA1

F9F

F9D

F9B

F99

Index interrupt/
index event
marker
QPOSILAT

F9F

0

QEPSTS:QDLF

2080

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Position Counter and Control Unit (PCCU)

www.ti.com

17.5.2.2 Strobe Event Latch
The position-counter value is latched to the QPOSSLAT register on the rising edge of the strobe input by
clearing the QEPCTL[SEL] bit.
If the QEPCTL[SEL] bit is set, then the position counter value is latched to the QPOSSLAT register on the
rising edge of the strobe input for forward direction and on the falling edge of the strobe input for reverse
direction as shown in Figure 17-11.
The strobe event latch interrupt flag (QFLG[SEL) is set when the position counter is latched to the
QPOSSLAT register.
Figure 17-11. Strobe Event Latch (QEPCTL[SEL] = 1)
QA

QB

QS

QCLK

QEPST:QDF
F9D

F9F

FA1

FA3

FA4

QPOSCNT F9C

FA2

FA0

F9E

F9C

F9A

F98

FA5
F9E

FA0

FA2

QIPOSSLAT

FA4

F97
FA3

FA1

F9F

F9F

F9D

F9B

F99

F9F

17.5.3 Position Counter Initialization
The position counter can be initialized using following events:
• Index event
• Strobe event
• Software initialization
Index Event Initialization (IEI)— The QEPI index input can be used to trigger the initialization of the
position counter at the rising or falling edge of the index input. If the QEPCTL[IEI] bits are 10, then
the position counter (QPOSCNT) is initialized with a value in the QPOSINIT register on the rising
edge of index input. Conversely, if the QEPCTL[IEI] bits are 11, initialization will be on the falling
edge of the index input.
Strobe Event Initialization (SEI)— If the QEPCTL[SEI] bits are 10, then the position counter is initialized
with a value in the QPOSINIT register on the rising edge of strobe input.
If QEPCTL[SEL] bits are 11, then the position counter is initialized with a value in the QPOSINIT
register on the rising edge of strobe input for forward direction and on the falling edge of strobe
input for reverse direction.
Software Initialization (SWI)— The position counter can be initialized in software by writing a 1 to the
QEPCTL[SWI] bit. This bit is not automatically cleared. While the bit is still set, if a 1 is written to it
again, the position counter will be re-initialized.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2081

Position Counter and Control Unit (PCCU)

www.ti.com

17.5.4 eQEP Position-compare Unit
The eQEP peripheral includes a position-compare unit that is used to generate a sync output and/or
interrupt on a position-compare match. Figure 17-12 shows a diagram. The position-compare
(QPOSCMP) register is shadowed and shadow mode can be enabled or disabled using the
QPOSCTL[PSSHDW] bit. If the shadow mode is not enabled, the CPU writes directly to the active position
compare register.
Figure 17-12. eQEP Position-compare Unit
QPOSCTL:PCSHDW
QPOSCTL:PCLOAD

QPOSCMP

QFLG:PCR
QFLG:PCM

QPOSCTL:PCSPW

QPOSCTL:PCPOL

8

32
PCEVENT

Pulse
stretcher

0

32

PCSOUT

1

QPOSCNT

In shadow mode, you can configure the position-compare unit (QPOSCTL[PCLOAD]) to load the shadow
register value into the active register on the following events and to generate the position-compare ready
(QFLG[PCR]) interrupt after loading.
• Load on compare match
• Load on position-counter zero event
The position-compare match (QFLG[PCM]) is set when the position-counter value (QPOSCNT) matches
with the active position-compare register (QPOSCMP) and the position-compare sync output of the
programmable pulse width is generated on compare match to trigger an external device.
For example, if QPOSCMP = 2, the position-compare unit generates a position-compare event on 1 to 2
transitions of the eQEP position counter for forward counting direction and on 3 to 2 transitions of the
eQEP position counter for reverse counting direction (see Figure 17-13).
See the register section for the layout of the eQEP Position-Compare Control Register (QPOSCTL) and
description of the QPOSCTL bit fields.

2082

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

eQEP Edge Capture Unit

www.ti.com

Figure 17-13. eQEP Position-compare Event Generation Points
4
3
2

eQEP counter

4
3

3
2

1

1

0

3

2

2

1

POSCMP=2

1

0

0

PCEVNT

PCSOUT (active HIGH)
PCSPW
PCSOUT (active LOW)

The pulse stretcher logic in the position-compare unit generates a programmable position-compare sync
pulse output on the position-compare match. In the event of a new position-compare match while a
previous position-compare pulse is still active, then the pulse stretcher generates a pulse of specified
duration from the new position-compare event as shown in Figure 17-14.
Figure 17-14. eQEP Position-compare Sync Output Pulse Stretcher
DIR

QPOSCMP

QPOSCNT

PCEVNT

PCSPW

PCSPW
PCSPW

PCSOUT (active HIGH)

17.6 eQEP Edge Capture Unit
The eQEP peripheral includes an integrated edge capture unit to measure the elapsed time between the
unit position events as shown in Figure 17-15. This feature is typically used for low speed measurement
using the following equation:
X
v(k) +
+ X
t(k) * t(k * 1)
DT
(3)
where,
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2083

eQEP Edge Capture Unit

•
•
•

www.ti.com

X - Unit position is defined by integer multiple of quadrature edges (see Figure 17-16)
ΔT - Elapsed time between unit position events
v(k) - Velocity at time instant "k"

The eQEP capture timer (QCTMR) runs from prescaled SYSCLKOUT and the prescaler is programmed
by the QCAPCTL[CCPS] bits. The capture timer (QCTMR) value is latched into the capture period register
(QCPRD) on every unit position event and then the capture timer is reset, a flag is set in
QEPSTS:UPEVNT to indicate that new value is latched into the QCPRD register. Software can check this
status flag before reading the period register for low speed measurement and clear the flag by writing 1.
Time measurement (ΔT) between unit position events will be correct if the following conditions are met:
• No more than 65,535 counts have occurred between unit position events.
• No direction change between unit position events.
The capture unit sets the eQEP overflow error flag (QEPSTS[COEF]) in the event of capture timer
overflow between unit position events. If a direction change occurs between the unit position events, then
an error flag is set in the status register (QEPSTS[CDEF]).
Capture Timer (QCTMR) and Capture period register (QCPRD) can be configured to latch on following
events.
• CPU read of QPOSCNT register
• Unit time-out event
If the QEPCTL[QCLM] bit is cleared, then the capture timer and capture period values are latched into the
QCTMRLAT and QCPRDLAT registers, respectively, when the CPU reads the position counter
(QPOSCNT).
If the QEPCTL[QCLM] bit is set, then the position counter, capture timer, and capture period values are
latched into the QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out.
Figure 17-17 shows the capture unit operation along with the position counter.

2084

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

eQEP Edge Capture Unit

www.ti.com

Figure 17-15. eQEP Edge Capture Unit

16
0xFFFF

QEPSTS:COEF
16
QCTMR
QCPRD

QCAPCTL:CCPS

16

3
3-bit binary
divider
x1, 1/2, 1/4...,
1/128

SYSCLKOUT

CAPCLK

16
Capture timer
control unit
(CTCU)

QCAPCTL:CEN

QCAPCTL:UPPS

QCTMRLAT
QCPRDLAT

QEPSTS:UPEVNT
UPEVNT

QEPSTS:CDEF

4

4-bit binary
divider
x1, 1/2, 1/4...,
1/2048

Rising/falling
edge detect

QCLK

QDIR

UTIME
QEPCTL:UTE
SYSCLKOUT

QFLG:UTO

QUTMR
UTOUT

QUPRD

NOTE:

The QCAPCTL[UPPS] prescaler should not be modified dynamically (such as switching the
unit event prescaler from QCLK/4 to QCLK/8). Doing so may result in undefined behavior.
The QCAPCTL[CPPS] prescaler can be modified dynamically (such as switching CAPCLK
prescaling mode from SYSCLK/4 to SYSCLK/8) only after the capture unit is disabled.

Figure 17-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
P

QA

QB

QCLK

UPEVNT
X=N x P
A

N - Number of quadrature periods selected using QCAPCTL[UPPS] bits

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2085

eQEP Edge Capture Unit

www.ti.com

Figure 17-17. eQEP Edge Capture Unit - Timing Details
QEPA

QEPB

QCLK

QPOSCNT

x(k)

∆X
x(k−1)

UPEVNT
t(k)

∆T
QCTMR
t(k−1)
T
UTOUT

Velocity Calculation Equations:
x(k) * x(k * 1)
v(k) +
+ DX or
T
T

(4)

where
v(k): Velocity at time instant k
x(k): Position at time instant k
x(k-1): Position at time instant k-1
T: Fixed unit time or inverse of velocity calculation rate
ΔX: Incremental position movement in unit time
X: Fixed unit position
ΔT: Incremental time elapsed for unit position movement
t(k): Time instant "k"
t(k-1): Time instant "k-1"
Unit time (T) and unit period(X) are configured using the QUPRD and QCAPCTL[UPPS] registers.
Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT
registers.

2086

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

eQEP Watchdog

www.ti.com
Parameter
T
ΔX
X
ΔT

Relevant Register to Configure or Read the Information
Unit Period Register (QUPRD)
Incremental Position = QPOSLAT(k) - QPOSLAT(K-1)
Fixed unit position defined by sensor resolution and ZCAPCTL[UPPS] bits
Capture Period Latch (QCPRDLAT)

17.7 eQEP Watchdog
The eQEP peripheral contains a 16-bit watchdog timer that monitors the quadrature-clock to indicate
proper operation of the motion-control system. The eQEP watchdog timer is clocked from
SYSCLKOUT/64 and the quadrate clock event (pulse) resets the watchdog timer. If no quadrature-clock
event is detected until a period match (QWDPRD = QWDTMR), then the watchdog timer will time out and
the watchdog interrupt flag will be set (QFLG[WTO]). The time-out value is programmable through the
watchdog period register (QWDPRD).
Figure 17-18. eQEP Watchdog Timer
QWDOG
QEPCTL:WDE
SYSCLKOUT

/64

SYSCLKOUT

QWDTMR
16

QCLK

RESET

WDTOUT
16
QWDPRD

QFLG:WTO

17.8 Unit Timer Base
The eQEP peripheral includes a 32-bit timer (QUTMR) that is clocked by SYSCLKOUT to generate
periodic interrupts for velocity calculations. The unit time out interrupt is set (QFLG[UTO]) when the unit
timer (QUTMR) matches the unit period register (QUPRD). The unit timer gets reset whenever timer value
equals to configured period value.
The eQEP peripheral can be configured to latch the position counter, capture timer, and capture period
values on a unit time out event so that latched values are used for velocity calculation as described in
Section 17.6.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2087

eQEP Interrupt Structure

www.ti.com

Figure 17-19. eQEP Unit Time Base
UTIME
QEPCTL:UTE
SYSCLKOUT

QUTMR
32
UTOUT
32
QUPRD

QFLG:UTO

17.9 eQEP Interrupt Structure
Figure 17-20 shows how the interrupt mechanism works in the EQEP module.
Figure 17-20. EQEP Interrupt Generation
Set

Clr
Latch

QEINT:PCE

QCLR:INT

Clr
QFLG:INT

QCLR:PCE

Latch
Set
EQEPxINT

Pulse
generator
when
input=1

0

0

QFRC:PCE
PCE

QFLG:PCE
1
QEINT:UTO
clr

QCLR:UTO

Latch
set

QFRC:UTO
UTO

QFLG:UTO

Eleven interrupt events (PCE, PHE, QDC, WTO, PCU, PCO, PCR, PCM, SEL, IEL and UTO) can be
generated. The interrupt control register (QEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (QFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT).
An Interrupt pulse is generated to PIE when:
a. Interrupt is enabled for eQEP event inside QEINT register
b. Interrupt flag for eQEP event inside QFLG register is set, and
c. Global interrupt status flag bit QFLG[INT] had been cleared for previously generated interrupt event.
The interrupt service routine will need to clear the global interrupt flag bit and the serviced event, via
the interrupt clear register (QCLR), before any other interrupt pulses are generated.If either flags inside
the QFLG register are not cleared, further interrupt event will not generate interrupt to PIE. You can
force an interrupt event by way of the interrupt force register (QFRC), which is useful for test purposes

2088

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10 Registers
17.10.1 eQEP Base Addresses
Table 17-3. eQEP Base Address Table
Device Registers

Register Name

Start Address

End Address

EQep1Regs

EQEP_REGS

0x0000_5100

0x0000_513F

EQep2Regs

EQEP_REGS

0x0000_5140

0x0000_517F

EQep3Regs

EQEP_REGS

0x0000_5180

0x0000_51BF

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2089

Registers

www.ti.com

17.10.2 EQEP_REGS Registers
Table 17-4 lists the memory-mapped registers for the EQEP_REGS. All register offset addresses not
listed in Table 17-4 should be considered as reserved locations and the register contents should not be
modified.
Table 17-4. EQEP_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

QPOSCNT

Position Counter

Go

2h

QPOSINIT

Position Counter Init

Go

4h

QPOSMAX

Maximum Position Count

Go

6h

QPOSCMP

Position Compare

Go

8h

QPOSILAT

Index Position Latch

Go

Ah

QPOSSLAT

Strobe Position Latch

Go

Ch

QPOSLAT

Position Latch

Go

Eh

QUTMR

QEP Unit Timer

Go

10h

QUPRD

QEP Unit Period

Go

12h

QWDTMR

QEP Watchdog Timer

Go

13h

QWDPRD

QEP Watchdog Period

Go

14h

QDECCTL

Quadrature Decoder Control

Go

15h

QEPCTL

QEP Control

Go

16h

QCAPCTL

Qaudrature Capture Control

Go

17h

QPOSCTL

Position Compare Control

Go

18h

QEINT

QEP Interrupt Control

Go

19h

QFLG

QEP Interrupt Flag

Go

1Ah

QCLR

QEP Interrupt Clear

Go

1Bh

QFRC

QEP Interrupt Force

Go

1Ch

QEPSTS

QEP Status

Go

1Dh

QCTMR

QEP Capture Timer

Go

1Eh

QCPRD

QEP Capture Period

Go

1Fh

QCTMRLAT

QEP Capture Latch

Go

20h

QCPRDLAT

QEP Capture Period Latch

Go

Complex bit access types are encoded to fit into small table cells. Table 17-5 shows the codes that are
used for access types in this section.
Table 17-5. EQEP_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

2090

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 17-5. EQEP_REGS Access Type
Codes (continued)
Access Type

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2091

Registers

www.ti.com

17.10.2.1 QPOSCNT Register (Offset = 0h) [reset = 0h]
QPOSCNT is shown in Figure 17-21 and described in Table 17-6.
Return to Summary Table.
Position Counter
Figure 17-21. QPOSCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSCNT
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 17-6. QPOSCNT Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QPOSCNT

R/W

0h

Position Counter
This 32-bit position counter register counts up/down on every eQEP
pulse based on direction input. This counter acts as a position
integrator whose count value is proportional to position from a give
reference point. This Register acts as a Read ONLY register while
counter is counting up/down.
Reset type: SYSRSn

2092

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.2 QPOSINIT Register (Offset = 2h) [reset = 0h]
QPOSINIT is shown in Figure 17-22 and described in Table 17-7.
Return to Summary Table.
Position Counter Init
Figure 17-22. QPOSINIT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSINIT
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 17-7. QPOSINIT Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QPOSINIT

R/W

0h

Position Counter Init
This register contains the position value that is used to initialize the
position counter based on
external strobe or index event. The position counter can be initialized
through software. Writes to this register should always be full 32-bit
writes.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2093

Registers

www.ti.com

17.10.2.3 QPOSMAX Register (Offset = 4h) [reset = 0h]
QPOSMAX is shown in Figure 17-23 and described in Table 17-8.
Return to Summary Table.
Maximum Position Count
Figure 17-23. QPOSMAX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSMAX
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 17-8. QPOSMAX Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QPOSMAX

R/W

0h

Maximum Position Count
This register contains the maximum position counter value. Writes to
this register should
always be full 32-bit writes.
Reset type: SYSRSn

2094

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.4 QPOSCMP Register (Offset = 6h) [reset = 0h]
QPOSCMP is shown in Figure 17-24 and described in Table 17-9.
Return to Summary Table.
Position Compare
Figure 17-24. QPOSCMP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSCMP
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 17-9. QPOSCMP Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QPOSCMP

R/W

0h

Position Compare
The position-compare value in this register is compared with the
position counter (QPOSCNT) to generate sync output and/or
interrupt on compare match.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2095

Registers

www.ti.com

17.10.2.5 QPOSILAT Register (Offset = 8h) [reset = 0h]
QPOSILAT is shown in Figure 17-25 and described in Table 17-10.
Return to Summary Table.
Index Position Latch
Figure 17-25. QPOSILAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSILAT
R-0h

9

8

7

6

5

4

3

2

1

0

Table 17-10. QPOSILAT Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QPOSILAT

R

0h

Index Position Latch
The position-counter value is latched into this register on an index
event as defined by the
QEPCTL[IEL] bits.
Reset type: SYSRSn

2096

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.6 QPOSSLAT Register (Offset = Ah) [reset = 0h]
QPOSSLAT is shown in Figure 17-26 and described in Table 17-11.
Return to Summary Table.
Strobe Position Latch
Figure 17-26. QPOSSLAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSSLAT
R-0h

9

8

7

6

5

4

3

2

1

0

Table 17-11. QPOSSLAT Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QPOSSLAT

R

0h

Strobe Position Latch
The position-counter value is latched into this register on strobe
event as defined by the
QEPCTL[SEL] bits.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2097

Registers

www.ti.com

17.10.2.7 QPOSLAT Register (Offset = Ch) [reset = 0h]
QPOSLAT is shown in Figure 17-27 and described in Table 17-12.
Return to Summary Table.
Position Latch
Figure 17-27. QPOSLAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSLAT
R-0h

9

8

7

6

5

4

3

2

1

0

Table 17-12. QPOSLAT Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QPOSLAT

R

0h

Position Latch
The position-counter value is latched into this register on unit time
out event.
Reset type: SYSRSn

2098

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.8 QUTMR Register (Offset = Eh) [reset = 0h]
QUTMR is shown in Figure 17-28 and described in Table 17-13.
Return to Summary Table.
QEP Unit Timer
Figure 17-28. QUTMR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUTMR
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 17-13. QUTMR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QUTMR

R/W

0h

QEP Unit Timer
This register acts as time base for unit time event generation. When
this timer value matches
with unit time period value, unit time event is generated.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2099

Registers

www.ti.com

17.10.2.9 QUPRD Register (Offset = 10h) [reset = 0h]
QUPRD is shown in Figure 17-29 and described in Table 17-14.
Return to Summary Table.
QEP Unit Period
Figure 17-29. QUPRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUPRD
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 17-14. QUPRD Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

QUPRD

R/W

0h

QEP Unit Period
This register contains the period count for unit timer to generate
periodic unit time events to latch
the eQEP position information at periodic interval and optionally to
generate interrupt. Writes to
this register should always be full 32-bit writes.
Reset type: SYSRSn

2100

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.10 QWDTMR Register (Offset = 12h) [reset = 0h]
QWDTMR is shown in Figure 17-30 and described in Table 17-15.
Return to Summary Table.
QEP Watchdog Timer
Figure 17-30. QWDTMR Register
15

14

13

12

11

10

9

8
7
QWDTMR
R/W-0h

6

5

4

3

2

1

0

Table 17-15. QWDTMR Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

QWDTMR

R/W

0h

QEP Watchdog Timer
This register acts as time base for watch dog to detect motor stalls.
When this timer value
matches with watch dog period value, watch dog timeout interrupt is
generated. This register is
reset upon edge transition in quadrature-clock indicating the motion.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2101

Registers

www.ti.com

17.10.2.11 QWDPRD Register (Offset = 13h) [reset = 0h]
QWDPRD is shown in Figure 17-31 and described in Table 17-16.
Return to Summary Table.
QEP Watchdog Period
Figure 17-31. QWDPRD Register
15

14

13

12

11

10

9

8
7
QWDPRD
R/W-0h

6

5

4

3

2

1

0

Table 17-16. QWDPRD Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

QWDPRD

R/W

0h

QEP Watchdog Period
This register contains the time-out count for the eQEP peripheral
watch dog timer.
When the watchdog timer value matches the watchdog period value,
a watchdog
timeout interrupt is generated.
Reset type: SYSRSn

2102

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.12 QDECCTL Register (Offset = 14h) [reset = 0h]
QDECCTL is shown in Figure 17-32 and described in Table 17-17.
Return to Summary Table.
Quadrature Decoder Control
Figure 17-32. QDECCTL Register
15

14

13
SOEN
R/W-0h

12
SPSEL
R/W-0h

11
XCR
R/W-0h

10
SWAP
R/W-0h

9
IGATE
R/W-0h

8
QAP
R/W-0h

6
QIP
R/W-0h

5
QSP
R/W-0h

4

3

2
RESERVED
R-0h

1

0

QSRC
R/W-0h
7
QBP
R/W-0h

Table 17-17. QDECCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15-14

QSRC

R/W

0h

Position-counter source selection
Reset type: SYSRSn
0h (R/W) = Quadrature count mode (QCLK = iCLK, QDIR = iDIR)
1h (R/W) = Direction-count mode (QCLK = xCLK, QDIR = xDIR)
2h (R/W) = UP count mode for frequency measurement (QCLK =
xCLK, QDIR = 1)
3h (R/W) = DOWN count mode for frequency measurement (QCLK =
xCLK, QDIR = 0)

13

SOEN

R/W

0h

Sync output-enable
Reset type: SYSRSn
0h (R/W) = Disable position-compare sync output
1h (R/W) = Enable position-compare sync output

12

SPSEL

R/W

0h

Sync output pin selection
Reset type: SYSRSn
0h (R/W) = Index pin is used for sync output
1h (R/W) = Strobe pin is used for sync output

11

XCR

R/W

0h

External Clock Rate
Reset type: SYSRSn
0h (R/W) = 2x resolution: Count the rising/falling edge
1h (R/W) = 1x resolution: Count the rising edge only

10

SWAP

R/W

0h

CLK/DIR Signal Source for Position Counter
Reset type: SYSRSn
0h (R/W) = Quadrature-clock inputs are not swapped
1h (R/W) = Quadrature-clock inputs are swapped

9

IGATE

R/W

0h

Index pulse gating option
Reset type: SYSRSn
0h (R/W) = Disable gating of Index pulse
1h (R/W) = Gate the index pin with strobe

8

QAP

R/W

0h

QEPA input polarity
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Negates QEPA input

7

QBP

R/W

0h

QEPB input polarity
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Negates QEPB input

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2103

Registers

www.ti.com

Table 17-17. QDECCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

QIP

R/W

0h

QEPI input polarity
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Negates QEPI input

5

QSP

R/W

0h

QEPS input polarity
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Negates QEPS input

RESERVED

R

0h

Reserved

4-0

2104

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.13 QEPCTL Register (Offset = 15h) [reset = 0h]
QEPCTL is shown in Figure 17-33 and described in Table 17-18.
Return to Summary Table.
QEP Control
Figure 17-33. QEPCTL Register
15

14

13

12

FREE_SOFT
R/W-0h
7
SWI
R/W-0h

6
SEL
R/W-0h

11

PCRM
R/W-0h

10

9

SEI
R/W-0h

5

4
IEL
R/W-0h

3
QPEN
R/W-0h

8
IEI
R/W-0h

2
QCLM
R/W-0h

1
UTE
R/W-0h

0
WDE
R/W-0h

Table 17-18. QEPCTL Register Field Descriptions
Bit
15-14

Field

Type

Reset

Description

FREE_SOFT

R/W

0h

Emulation mode
Reset type: SYSRSn
0h (R/W) = QPOSCNT behavior
Position counter stops immediately on emulation suspend
QWDTMR behavior
Watchdog counter stops immediately
QUTMR behavior
Unit timer stops immediately
QCTMR behavior
Capture Timer stops immediately
1h (R/W) = QPOSCNT behavior
Position counter continues to count until the rollover
QWDTMR behavior
Watchdog counter counts until WD period match roll over
QUTMR behavior
Unit timer counts until period rollover
QCTMR behavior
Capture Timer counts until next unit period event
2h (R/W) = QPOSCNT behavior
Position counter is unaffected by emulation suspend
QWDTMR behavior
Watchdog counter is unaffected by emulation suspend
QUTMR behavior
Unit timer is unaffected by emulation suspend
QCTMR behavior
Capture Timer is unaffected by emulation suspend
3h (R/W) = Same as FREE_SOFT_2

13-12

PCRM

R/W

0h

Postion counter reset
Reset type: SYSRSn
0h (R/W) = Position counter reset
1h (R/W) = Position counter reset
2h (R/W) = Position counter reset
3h (R/W) = Position counter reset

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

on
on
on
on

an index event
the maximum position
the first index event
a unit time event

Enhanced QEP (eQEP)

2105

Registers

www.ti.com

Table 17-18. QEPCTL Register Field Descriptions (continued)
Bit
11-10

Field

Type

Reset

Description

SEI

R/W

0h

Strobe event init
Reset type: SYSRSn
0h (R/W) = Does nothing (action disabled)
1h (R/W) = Does nothing (action disabled)
2h (R/W) = Initializes the position counter on rising edge of the
QEPS signal
3h (R/W) = Clockwise Direction:
Initializes the position counter on the rising edge of QEPS strobe
Counter Clockwise Direction:
Initializes the position counter on the falling edge of QEPS strobe

9-8

IEI

R/W

0h

Index event init of position count
Reset type: SYSRSn
0h (R/W) = Do nothing (action disabled)
1h (R/W) = Do nothing (action disabled)
2h (R/W) = Initializes the position counter on the rising edge of the
QEPI signal (QPOSCNT = QPOSINIT)
3h (R/W) = Initializes the position counter on the falling edge of
QEPI signal (QPOSCNT = QPOSINIT)

7

SWI

R/W

0h

Software init position counter
Reset type: SYSRSn
0h (R/W) = Do nothing (action disabled)
1h (R/W) = Initialize position counter (QPOSCNT=QPOSINIT). This
bit is not cleared automatically

6

SEL

R/W

0h

Strobe event latch of position counter
Reset type: SYSRSn
0h (R/W) = The position counter is latched on the rising edge of
QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling
edge can be done by inverting the strobe input using the
QSP bit in the QDECCTL register
1h (R/W) = Clockwise Direction:
Position counter is latched on rising edge of QEPS strobe
Counter Clockwise Direction:
Position counter is latched on falling edge of QEPS strobe

5-4

IEL

R/W

0h

Index event latch of position counter (software index marker)
Reset type: SYSRSn
0h (R/W) = Reserved
1h (R/W) = Latches position counter on rising edge of the index
signal
2h (R/W) = Latches position counter on falling edge of the index
signal
3h (R/W) = Software index marker. Latches the position counter and
quadrature direction flag on index
event marker. The position counter is latched to the QPOSILAT
register and the direction flag
is latched in the QEPSTS[QDLF] bit. This mode is useful for
software index marking.

3

QPEN

R/W

0h

Quadrature position counter enable/software reset
Reset type: SYSRSn
0h (R/W) = Reset the eQEP peripheral internal operating flags/readonly registers. Control/configuration
registers are not disturbed by a software reset.
1h (R/W) = eQEP position counter is enabled

2106

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 17-18. QEPCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2

QCLM

R/W

0h

QEP capture latch mode
Reset type: SYSRSn
0h (R/W) = Latch on position counter read by CPU. Capture timer
and capture period values are latched into QCTMRLAT and
QCPRDLAT registers when CPU reads the QPOSCNT register.
1h (R/W) = Latch on unit time out. Position counter, capture timer
and capture period values are latched into QPOSLAT, QCTMRLAT
and QCPRDLAT registers on unit time out.

1

UTE

R/W

0h

QEP unit timer enable
Reset type: SYSRSn
0h (R/W) = Disable eQEP unit timer
1h (R/W) = Enable unit timer

0

WDE

R/W

0h

QEP watchdog enable
Reset type: SYSRSn
0h (R/W) = Disable the eQEP watchdog timer
1h (R/W) = Enable the eQEP watchdog timer

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2107

Registers

www.ti.com

17.10.2.14 QCAPCTL Register (Offset = 16h) [reset = 0h]
QCAPCTL is shown in Figure 17-34 and described in Table 17-19.
Return to Summary Table.
Qaudrature Capture Control
Figure 17-34. QCAPCTL Register
15
CEN
R/W-0h

14

13

12

11
RESERVED
R-0h

10

7
RESERVED
R-0h

6

5
CCPS
R/W-0h

4

3

2

9

8

1

0

UPPS
R/W-0h

Table 17-19. QCAPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

CEN

R/W

0h

Enable eQEP capture
Reset type: SYSRSn
0h (R/W) = eQEP capture unit is disabled
1h (R/W) = eQEP capture unit is enabled

14-7

RESERVED

R

0h

Reserved

6-4

CCPS

R/W

0h

eQEP capture timer clock prescaler
Reset type: SYSRSn
0h (R/W) = CAPCLK = SYSCLKOUT/1
1h (R/W) = CAPCLK = SYSCLKOUT/2
2h (R/W) = CAPCLK = SYSCLKOUT/4
3h (R/W) = CAPCLK = SYSCLKOUT/8
4h (R/W) = CAPCLK = SYSCLKOUT/16
5h (R/W) = CAPCLK = SYSCLKOUT/32
6h (R/W) = CAPCLK = SYSCLKOUT/64
7h (R/W) = CAPCLK = SYSCLKOUT/128

3-0

UPPS

R/W

0h

Unit position event prescaler
Reset type: SYSRSn
0h (R/W) = UPEVNT = QCLK/1
1h (R/W) = UPEVNT = QCLK/2
2h (R/W) = UPEVNT = QCLK/4
3h (R/W) = UPEVNT = QCLK/8
4h (R/W) = UPEVNT = QCLK/16
5h (R/W) = UPEVNT = QCLK/32
6h (R/W) = UPEVNT = QCLK/64
7h (R/W) = UPEVNT = QCLK/128
8h (R/W) = UPEVNT = QCLK/256
9h (R/W) = UPEVNT = QCLK/512
Ah (R/W) = UPEVNT = QCLK/1024
Bh (R/W) = UPEVNT = QCLK/2048
Ch (R/W) = Reserved
Dh (R/W) = Reserved
Eh (R/W) = Reserved
Fh (R/W) = Reserved

2108

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.15 QPOSCTL Register (Offset = 17h) [reset = 0h]
QPOSCTL is shown in Figure 17-35 and described in Table 17-20.
Return to Summary Table.
Position Compare Control
Figure 17-35. QPOSCTL Register
15
PCSHDW
R/W-0h

14
PCLOAD
R/W-0h

13
PCPOL
R/W-0h

12
PCE
R/W-0h

7

6

5

4

11

10

9

8

1

0

PCSPW
R/W-0h
3

2

PCSPW
R/W-0h

Table 17-20. QPOSCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

15

PCSHDW

R/W

0h

Position compare of shadow enable
Reset type: SYSRSn
0h (R/W) = Shadow disabled, load Immediate
1h (R/W) = Shadow enabled

14

PCLOAD

R/W

0h

Position compare of shadow load
Reset type: SYSRSn
0h (R/W) = Load on QPOSCNT = 0
1h (R/W) = Load when QPOSCNT = QPOSCMP

13

PCPOL

R/W

0h

Polarity of sync output
Reset type: SYSRSn
0h (R/W) = Active HIGH pulse output
1h (R/W) = Active LOW pulse output

12

PCE

R/W

0h

Position compare enable/disable
Reset type: SYSRSn
0h (R/W) = Disable position compare unit
1h (R/W) = Enable position compare unit

PCSPW

R/W

0h

Select-position-compare sync output pulse width
Reset type: SYSRSn
0h (R/W) = 1 * 4 * SYSCLKOUT cycles
1h (R/W) = 2 * 4 * SYSCLKOUT cycles
FFFh (R/W) = 4096 * 4 * SYSCLKOUT cycles

11-0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2109

Registers

www.ti.com

17.10.2.16 QEINT Register (Offset = 18h) [reset = 0h]
QEINT is shown in Figure 17-36 and described in Table 17-21.
Return to Summary Table.
QEP Interrupt Control
Figure 17-36. QEINT Register
15

14

13

12

11
UTO
R/W-0h

10
IEL
R/W-0h

9
SEL
R/W-0h

8
PCM
R/W-0h

5
PCU
R/W-0h

4
WTO
R/W-0h

3
QDC
R/W-0h

2
QPE
R/W-0h

1
PCE
R/W-0h

0
RESERVED
R-0h

RESERVED
R-0h
7
PCR
R/W-0h

6
PCO
R/W-0h

Table 17-21. QEINT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

11

UTO

R/W

0h

Unit time out interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

10

IEL

R/W

0h

Index event latch interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

9

SEL

R/W

0h

Strobe event latch interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

8

PCM

R/W

0h

Position-compare match interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

7

PCR

R/W

0h

Position-compare ready interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

6

PCO

R/W

0h

Position counter overflow interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

5

PCU

R/W

0h

Position counter underflow interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

4

WTO

R/W

0h

Watchdog time out interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

15-12

2110

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 17-21. QEINT Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

QDC

R/W

0h

Quadrature direction change interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

2

QPE

R/W

0h

Quadrature phase error interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

1

PCE

R/W

0h

Position counter error interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled

0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2111

Registers

www.ti.com

17.10.2.17 QFLG Register (Offset = 19h) [reset = 0h]
QFLG is shown in Figure 17-37 and described in Table 17-22.
Return to Summary Table.
QEP Interrupt Flag
Figure 17-37. QFLG Register
15

14

13

12

11
UTO
R-0h

10
IEL
R-0h

9
SEL
R-0h

8
PCM
R-0h

5
PCU
R-0h

4
WTO
R-0h

3
QDC
R-0h

2
PHE
R-0h

1
PCE
R-0h

0
INT
R-0h

RESERVED
R-0h
7
PCR
R-0h

6
PCO
R-0h

Table 17-22. QFLG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

11

UTO

R

0h

Unit time out interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

10

IEL

R

0h

Index event latch interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

9

SEL

R

0h

Strobe event latch interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

8

PCM

R

0h

eQEP compare match event interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

7

PCR

R

0h

Position-compare ready interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

6

PCO

R

0h

Position counter overflow interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

5

PCU

R

0h

Position counter underflow interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

4

WTO

R

0h

Watchdog timeout interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

15-12

2112

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 17-22. QFLG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

QDC

R

0h

Quadrature direction change interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

2

PHE

R

0h

Quadrature phase error interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

1

PCE

R

0h

Position counter error interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

0

INT

R

0h

Global interrupt status flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2113

Registers

www.ti.com

17.10.2.18 QCLR Register (Offset = 1Ah) [reset = 0h]
QCLR is shown in Figure 17-38 and described in Table 17-23.
Return to Summary Table.
QEP Interrupt Clear
Figure 17-38. QCLR Register
15

14

13

12

11
UTO
R=0/W=1-0h

10
IEL
R=0/W=1-0h

9
SEL
R=0/W=1-0h

8
PCM
R=0/W=1-0h

5
PCU
R=0/W=1-0h

4
WTO
R=0/W=1-0h

3
QDC
R=0/W=1-0h

2
PHE
R=0/W=1-0h

1
PCE
R=0/W=1-0h

0
INT
R=0/W=1-0h

RESERVED
R-0h
7
PCR
R=0/W=1-0h

6
PCO
R=0/W=1-0h

Table 17-23. QCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

11

UTO

R=0/W=1

0h

Clear unit time out interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

10

IEL

R=0/W=1

0h

Clear index event latch interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

9

SEL

R=0/W=1

0h

Clear strobe event latch interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

8

PCM

R=0/W=1

0h

Clear eQEP compare match event interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

7

PCR

R=0/W=1

0h

Clear position-compare ready interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

6

PCO

R=0/W=1

0h

Clear position counter overflow interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

5

PCU

R=0/W=1

0h

Clear position counter underflow interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

4

WTO

R=0/W=1

0h

Clear watchdog timeout interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

15-12

2114

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 17-23. QCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

QDC

R=0/W=1

0h

Clear quadrature direction change interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

2

PHE

R=0/W=1

0h

Clear quadrature phase error interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

1

PCE

R=0/W=1

0h

Clear position counter error interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

0

INT

R=0/W=1

0h

Global interrupt clear flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2115

Registers

www.ti.com

17.10.2.19 QFRC Register (Offset = 1Bh) [reset = 0h]
QFRC is shown in Figure 17-39 and described in Table 17-24.
Return to Summary Table.
QEP Interrupt Force
Figure 17-39. QFRC Register
15

14

13

12

11
UTO
R/W-0h

10
IEL
R/W-0h

9
SEL
R/W-0h

8
PCM
R/W-0h

5
PCU
R/W-0h

4
WTO
R/W-0h

3
QDC
R/W-0h

2
PHE
R/W-0h

1
PCE
R/W-0h

0
RESERVED
R-0h

RESERVED
R-0h
7
PCR
R/W-0h

6
PCO
R/W-0h

Table 17-24. QFRC Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

11

UTO

R/W

0h

Force unit time out interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

10

IEL

R/W

0h

Force index event latch interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

9

SEL

R/W

0h

Force strobe event latch interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

8

PCM

R/W

0h

Force position-compare match interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

7

PCR

R/W

0h

Force position-compare ready interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

6

PCO

R/W

0h

Force position counter overflow interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

5

PCU

R/W

0h

Force position counter underflow interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

4

WTO

R/W

0h

Force watchdog time out interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

15-12

2116

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 17-24. QFRC Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

QDC

R/W

0h

Force quadrature direction change interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

2

PHE

R/W

0h

Force quadrature phase error interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

1

PCE

R/W

0h

Force position counter error interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt

0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2117

Registers

www.ti.com

17.10.2.20 QEPSTS Register (Offset = 1Ch) [reset = 0h]
QEPSTS is shown in Figure 17-40 and described in Table 17-25.
Return to Summary Table.
QEP Status
Figure 17-40. QEPSTS Register
15

14

13

12

11

10

9

8

3
COEF
R/W-0h

2
CDEF
R/W-0h

1
FIMF
R/W-0h

0
PCEF
R-0h

RESERVED
R-0h
7
UPEVNT
R/W-0h

6
FIDF
R-0h

5
QDF
R-0h

4
QDLF
R-0h

Table 17-25. QEPSTS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

7

UPEVNT

R/W

0h

Unit position event flag
Reset type: SYSRSn
0h (R/W) = No unit position event detected
1h (R/W) = Unit position event detected. Write 1 to clear

6

FIDF

R

0h

Direction on the first index marker

15-8

Status of the direction is latched on the first index event marker.
Reset type: SYSRSn
0h (R/W) = Counter-clockwise rotation (or reverse movement) on the
first index event
1h (R/W) = Clockwise rotation (or forward movement) on the first
index event
5

QDF

R

0h

Quadrature direction flag
Reset type: SYSRSn
0h (R/W) = Counter-clockwise rotation (or reverse movement)
1h (R/W) = Clockwise rotation (or forward movement)

4

QDLF

R

0h

eQEP direction latch flag
Reset type: SYSRSn
0h (R/W) = Counter-clockwise rotation (or reverse movement) on
index event marker
1h (R/W) = Clockwise rotation (or forward movement) on index event
marker

3

COEF

R/W

0h

Capture overflow error flag
Reset type: SYSRSn
0h (R/W) = Overflow has not occurred.
1h (R/W) = Overflow occurred in eQEP Capture timer (QEPCTMR).

2

CDEF

R/W

0h

Capture direction error flag
Reset type: SYSRSn
0h (R/W) = Capture direction error has not occurred.
1h (R/W) = Direction change occurred between the capture position
event.

1

FIMF

R/W

0h

First index marker flag
Note: Once this flag has been set, if the flag is cleared the flag will
not be set again until the module is reset by a peripheral or system
reset.
Reset type: SYSRSn
0h (R/W) = First index pulse has not occurred.
1h (R/W) = Set by first occurrence of index pulse.

2118

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 17-25. QEPSTS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

PCEF

R

0h

Position counter error flag.
This bit is not sticky and it is updated for every index event.
Reset type: SYSRSn
0h (R/W) = No error occurred during the last index transition
1h (R/W) = Position counter error

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2119

Registers

www.ti.com

17.10.2.21 QCTMR Register (Offset = 1Dh) [reset = 0h]
QCTMR is shown in Figure 17-41 and described in Table 17-26.
Return to Summary Table.
QEP Capture Timer
Figure 17-41. QCTMR Register
15

14

13

12

11

10

9

8
7
QCTMR
R/W-0h

6

5

4

3

2

1

0

Table 17-26. QCTMR Register Field Descriptions
Bit
15-0

2120

Field

Type

Reset

Description

QCTMR

R/W

0h

This register provides time base for edge capture unit.
Reset type: SYSRSn

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.22 QCPRD Register (Offset = 1Eh) [reset = 0h]
QCPRD is shown in Figure 17-42 and described in Table 17-27.
Return to Summary Table.
QEP Capture Period
Figure 17-42. QCPRD Register
15

14

13

12

11

10

9

8
7
QCPRD
R/W-0h

6

5

4

3

2

1

0

Table 17-27. QCPRD Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

QCPRD

R/W

0h

This register holds the period count value between the last
successive eQEP position events
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2121

Registers

www.ti.com

17.10.2.23 QCTMRLAT Register (Offset = 1Fh) [reset = 0h]
QCTMRLAT is shown in Figure 17-43 and described in Table 17-28.
Return to Summary Table.
QEP Capture Latch
Figure 17-43. QCTMRLAT Register
15

14

13

12

11

10

9

8
7
QCTMRLAT
R-0h

6

5

4

3

2

1

0

Table 17-28. QCTMRLAT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

QCTMRLAT

R

0h

The eQEP capture timer value can be latched into this register on
two events viz., unit timeout
event, reading the eQEP position counter.
Reset type: SYSRSn

2122

Enhanced QEP (eQEP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

17.10.2.24 QCPRDLAT Register (Offset = 20h) [reset = 0h]
QCPRDLAT is shown in Figure 17-44 and described in Table 17-29.
Return to Summary Table.
QEP Capture Period Latch
Figure 17-44. QCPRDLAT Register
15

14

13

12

11

10

9

8
7
QCPRDLAT
R-0h

6

5

4

3

2

1

0

Table 17-29. QCPRDLAT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

QCPRDLAT

R

0h

eQEP capture period value can be latched into this register on two
events viz., unit timeout
event, reading the eQEP position counter.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced QEP (eQEP)

2123

Chapter 18
SPRUHM8G – December 2013 – Revised September 2017

Serial Peripheral Interface (SPI)
This chapter describes the serial peripheral interface (SPI) which is a high-speed synchronous serial input
and output (I/O) port that allows a serial bit stream of programmed length (one to 16 bits) to be shifted into
and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications
between the DSP controller and external peripherals or another controller. Typical applications include
external I/O or peripheral expansion via devices such as shift registers, display drivers, and analog-todigital converters (ADCs). Multi-device communications are supported by the master or slave operation of
the SPI. The port supports a 16-level, receive and transmit FIFO for reducing CPU servicing overhead.
Topic

18.1
18.2
18.3
18.4
18.5

2124

...........................................................................................................................
SPI Module Overview ......................................................................................
System-Level Integration .................................................................................
SPI Operation .................................................................................................
Programming Procedure ..................................................................................
Registers .......................................................................................................

Serial Peripheral Interface (SPI)

Page

2125
2126
2130
2139
2144

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

SPI Module Overview

www.ti.com

18.1 SPI Module Overview
18.1.1 Features
The SPI module features include:
• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.

•
•

•
•

•
•
•
•
•
•
•
•

Two operational modes: Master and Slave
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited
by the maximum speed of the I/O buffers used on the SPI pins. See the device-specific data manual
for more details.
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt- driven or polled
algorithm
16-level transmit/receive FIFO
DMA support
High-speed mode
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7−0), and the upper byte
(15−8) is read as zeros. Writing to the upper byte has no effect.

18.1.2 CPU Interface
Figure 18-1 shows the SPI CPU interfaces.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2125

System-Level Integration

www.ti.com

Figure 18-1. SPI CPU Interface
PCLKCR8
Low Speed
Prescaler

Bit
Clock

SYSCLK

CPU

Peripheral Bus

LSPCLK

SYSRS

SPISIMO

GPIO
MUX

SPISOMI

SPI

SPICLK

SPIINT
SPITXINT

PIE

SPIRXDMA
SPITXDMA

DMA

SPISTE

18.2 System-Level Integration
This section describes the various functionality that is applicable to the device integration. These features
require configuration of other modules in the device that are not within the scope of this chapter.

18.2.1 SPI Module Signals
Table 18-1 classifies and provides a summary of the SPI module signals.
Table 18-1. SPI Module Signal Summary
Signal Name

Description

External Signals
SPICLK

SPI clock

SPISIMO

SPI slave in, master out

SPISOMI

SPI slave out, master in

SPISTE

SPI slave transmit enable

Control
SPI Clock Rate

LSPCLK

Interrupt Signals
SPIINT/SPIRXINT

Transmit interrupt/ Receive Interrupt in non FIFO mode (referred to as SPIINT)
Receive interrupt in FIFO mode

SPITXINT

Transmit interrupt in FIFO mode

DMA Triggers

2126

SPITXDMA

Transmit request to DMA

SPIRXDMA

Receive request to DMA

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System-Level Integration

www.ti.com

Special Considerations
The SPISTE signal provides the ability to gate any spurious clock and data pulses when the SPI is in
slave mode. An active SPISTE will not allow the slave to receive data. This prevents the SPI slave from
losing synchronization with the master. It is this reason that TI does not recommend that the SPISTE
always be tied to the active state.
If the SPI slave does ever lose synchronization with the master, toggling SPISWRESET will reset internal
bit counter as well as the various status flags in the module. By resetting the bit counter, the SPI will
interpret the next clock transition as the first bit of a new transmission. The register bits fields which are
reset by SPISWRESET can be found in Section 18.5
Configuring a GPIO to emulate SPISTE
In many systems, a SPI master may be connected to multiple SPI slaves using multiple instances of
SPISTE. Though this SPI module does not natively support multiple SPISTE signals, it is possible to
emulate this behavior in software using GPIOs. In this configuration, the SPI must be configured as the
master. Rather than using the GPIO Mux to select SPISTE, the application would configure pins to be
GPIO outputs, one GPIO per SPI slave. Before transmitting any data, the application would drive the
desired GPIO to the active state. Immediately after the transmission has been completed, the GPIO chip
select would be driven to the inactive state. This process can be repeated for many slaves which share
the SPICLK, SPISIMO, and SPISOMI lines.

18.2.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.
GPIOs Required for High-Speed Mode
The high-speed mode of the SPI is only available on specific GPIO mux options. To enable the highspeed enhancements, set SPICCR.HS_MODE to 1.
When not operating in high-speed mode, SPICCR.HS_MODE should be set to 0. The high-speed capable
GPIOs may still be used as standard SPI pins if HS_MODE is not enabled. They are explained in
Table 18-2. Regardless of the configuration of the HS_MODE, GPIO input qualification will be bypassed if
the high-speed capable GPIOs are used
Table 18-2. High-Speed SPI Capable GPIOs
SPI pin

SPIA

SPIB

SPIC

SPISIMO

GPIO58

GPIO63

GPIO69

SPISOMI

GPIO59

GPIO64

GPIO70

SPICLK

GPIO60

GPIO65

GPIO71

SPISTE

GPIO61

GPIO66

GPIO72

18.2.3 SPI Interrupts
This section includes information on the available interrupts present in the SPI module.
The SPI module contains two interrupt lines: SPIINT/SPIRXINT and SPITXINT. When the SPI is operating
without FIFO mode, all available interrupts are routed together to generate the single SPIINT interrupt.
When FIFO mode is used, both SPIRXINT and SPITXINT can be generated.
SPIINT/SPIRXINT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2127

System-Level Integration

www.ti.com

When the SPI is operating in non-FIFO mode, the interrupt generated is called SPIINT. If FIFO
enhancements are enabled, the interrupt is called SPIRXINT. These interrupts share the same interrupt
vector in the Peripheral Interrupt Expansion (PIE) block.
In non-FIFO mode, two conditions can trigger an interrupt: a transmission is complete (INT_FLAG), or
there is overrun in the receiver (OVERRUN_FLAG). Both of these conditions share the same interrupt
vector: SPIINT.
The transmission complete flag (INT_FLAG) indicates that the SPI has completed sending or receiving the
last bit and is ready to be serviced. At the same time this bit is set, the received character is placed in the
receiver buffer (SPIRXBUF). The INT_FLAG will generate an interrupt on the SPIINT vector if the
SPIINTENA bit is set.
The receiver overrun flag (OVERRUN_FLAG) indicates that a transmit or receive operation has completed
before the previous character has been read from the buffer. The OVERRUN_FLAG will generate an
interrupt on the SPIINT vector if the OVERRUNINTENA bit is set and OVERRUN_FLAG was previously
cleared.
In FIFO mode, the SPI can interrupt the CPU upon a match condition between the current receive FIFO
status (RXFFST) and the receive FIFO interrupt level (RXFFIL). If RXFFST is greater than or equal to
RXFFIL, the receive FIFO interrupt flag (RXFFINT) will be set. SPIRXINT will be triggered in the PIE block
if RXFFINT is set and the receive FIFO interrupt is enabled (RXFFIENA = 1).
SPITXINT
The SPITXINT interrupt is not available when the SPI is operating in non-FIFO mode.
In FIFO mode, the SPITXINT behavior is similar to the SPIRXINT. SPITXINT is generated upon a match
condition between the current transmit FIFO status (TXFFST) and the transmit FIFO interrupt level
(TXFFIL). If TXFFST is less than or equal to TXFFIL, the transmit FIFO interrupt flag (TXFFINT) will be
set. SPITXINT will be triggered in the PIE block if TXFFINT is set and the transmit FIFO interrupt is
enabled in the SPI module (TXFFIENA = 1).
Figure 18-2 and Table 18-3 show how these control bits influence the SPI interrupt generation.

2128

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

System-Level Integration

www.ti.com

Figure 18-2. SPI Interrupt Flags and Enable Logic Generation
RXFFOVF

16
RX FIFO_15
…
RX FIFO_1
RX FIFO_0

>?

RXFFIENA

RXFFST

=?

RXFFIL

1

SPIRXINT
0
OVRNINTENA

SPISOMI
SPISIMO

SPIRXBUF
SPIDAT
SPITXBUF

OVERRUN_FLAG
SPIFFENA

INT_FLAG

SPIINTENA

TX FIFO_0
TX FIFO_1
...
TX FIFO_15

TXFFST

 3, and CLKPOLARITY =
1
2 cycles

3 cycles

2 cycles

LSPCLK

SPICLK

18.3.7 SPI FIFO Description
The following steps explain the FIFO features and help with programming the SPI FIFOs:
1. Reset. At reset the SPI powers up in standard SPI mode and the FIFO function is disabled. The FIFO
registers SPIFFTX, SPIFFRX and SPIFFCT remain inactive.
2. Standard SPI. The standard 28x SPI mode will work with SPIINT/SPIRXINT as the interrupt source.
3. Mode change. FIFO mode is enabled by setting the SPIFFENA bit to 1 in the SPIFFTX register.
SPIRST can reset the FIFO mode at any stage of its operation.
4. Active registers. All the SPI registers and SPI FIFO registers SPIFFTX, SPIFFRX, and SPIFFCT will
be active.
5. Interrupts. FIFO mode has two interrupts one for the transmit FIFO, SPITXINT and one for the receive
FIFO, SPIRXINT. SPIRXINT is the common interrupt for SPI FIFO receive, receive error and receive
FIFO overflow conditions. The single SPIINT for both transmit and receive sections of the standard SPI
will be disabled and this interrupt will service as SPI receive FIFO interrupt. For more information, refer
to Section 18.2.3
2136

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

SPI Operation

www.ti.com

6. Buffers. Transmit and receive buffers are each supplemented with a 16 word FIFO. The one-word
transmit buffer (SPITXBUF) of the standard SPI functions as a transition buffer between the transmit
FIFO and shift register. The one-word transmit buffer will be loaded from transmit FIFO only after the
last bit of the shift register is shifted out.
7. Delayed transfer. The rate at which transmit words in the FIFO are transferred to transmit shift
register is programmable. The SPIFFCT register bits (7−0) FFTXDLY7−FFTXDLY0 define the delay
between the word transfer. The delay is defined in number SPI serial clock cycles. The 8-bit register
could define a minimum delay of 0 SPICLK cycles and a maximum of 255 SPICLK cycles. With zero
delay, the SPI module can transmit data in continuous mode with the FIFO words shifting out back to
back. With the 255 clock delay, the SPI module can transmit data in a maximum delayed mode with
the FIFO words shifting out with a delay of 255 SPICLK cycles between each words. The
programmable delay facilitates glueless interface to various slow SPI peripherals, such as EEPROMs,
ADC, DAC, and so on.
8. FIFO status bits. Both transmit and receive FIFOs have status bits TXFFST or RXFFST that define
the number of words available in the FIFOs at any time. The transmit FIFO reset bit (TXFIFO) and
receive reset bit (RXFIFO) will reset the FIFO pointers to zero when these bits are set to 1. The FIFOs
will resume operation from start once these bits are cleared to zero.
9. Programmable interrupt levels. Both transmit and receive FIFOs can generate CPU interrupts and
DMA triggers. The transmit interrupt (SPITXINT) is generated whenever the transmit FIFO status bits
(TXFFST) match (less than or equal to) the interrupt trigger level bits (TXFFIL). The receive interrtupt
(SPIRXINT) is generated whenever the receive FIFO status bits (RXFFST) match (greater than or
equal to) the interrupt trigger level RXFFIL. This provides a programmable interrupt trigger for transmit
and receive sections of the SPI. The default value for these trigger level bits will be 0x11111 for
receive FIFO and 0x00000 for transmit FIFO, respectively.

18.3.8 SPI DMA Transfers
18.3.8.1 Transmitting Data Using SPI with DMA
When using the DMA with the TX FIFO, the DMA Burst Size (DMA_BURST_SIZE) should be no greater
than 16 – TXFFIL in order to prevent the DMA from writing to an already full FIFO. This will lead to data
loss and is not recommended.
For complete data transmission, please follow these steps:
1. Calculate the total number or words to be transmitted. [NUM_WORDS]
2. Decide the transmit FIFO level. [TXFFIL]
3. Calculate the number of DMA transfers. [DMA_TRANSFER_SIZE]
4. Calculate the size of the DMA Burst. [DMA_BURST_SIZE]
5. Configure DMA using calculated values.
6. Configure SPI with FIFO using the calculated values.
To transfer 128 words to SPI using the DMA:
NUM_WORDS: 128
TXFFIL: 8
DMA_TRANSFER_SIZE: (NUM_WORDS /TXFFIL) – 1 = (128/8) – 1 = 15 (16 transfers)
DMA_BURST_SIZE: (16 – TXFFIL) – 1 = (16 – 8) – 1 = 7 (8 words per burst)
18.3.8.2 Receiving Data Using SPI with DMA
When using the DMA with the RX FIFO, the DMA Burst Size (BURST_SIZE) should be no greater than
RXFFIL in order to prevent the DMA from reading from an empty FIFO. To ensure that the DMA correctly
receives all data from the RX FIFO, the DMA Burst Size should equal RXFFIL and also be an integer
divisor of the total number of SPI transmissions.
For complete data reception, please follow these steps:
1. Calculate the number of words to be received. [NUM_WORDS]
2. Calculate the necessary FIFO level [RXFFIL]
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2137

SPI Operation

3.
4.
5.
6.

www.ti.com

Calculate the total number of DMA transfers. [DMA_TRANSFER_SIZE]
Calculate the size of the DMA Burst. [DMA_BURST_SIZE]
Configure DMA using the calculated values.
Configure SPI with FIFO using the calculated values.

To receive 200 words from SPI using the DMA:
NUM_WORDS = 200
RXFFIL: 4
DMA_TRANSFER_SIZE: (NUM_WORDS /RXFFIL) – 1 = (200/4) – 1 = 49 (50 transfers)
DMA_BURST_SIZE = RXFFIL-1 = 3 (4 words per burst)

18.3.9 SPI High-Speed Mode
The SPI module is capable of reaching full-duplex communication speeds up to LSPCLK/4 (where
LSPCLK equals SYSCLK). For the maximum rated speed, refer the device Data Manual.
In order to achieve the maximum full-duplex speeds, two restrictions are placed on the design:
• High-speed capability is available on a single pin mux option
• Single master to single slave configuration is supported to limit the loading on the pins.
When configuring the GPIOs to support High-Speed mode, refer to GPIOs Required for High-Speed Mode
for more information.

18.3.10 SPI 3-Wire Mode Description
SPI 3-wire mode allows for SPI communication over three pins instead of the normal four pins.
In master mode, if the TRIWIRE bit is set, enabling 3-wire SPI mode, SPISIMOx becomes the bidirectional SPIMOMIx (SPI master out, master in) pin, and SPISOMIx is no longer used by the SPI. In
slave mode, if the TRIWIRE bit is set, SPISOMIx becomes the bi-directional SPISISOx (SPI slave in, slave
out) pin, and SPISIMOx is no longer used by the SPI.
Table 18-5 indicates the pin function differences between 3-wire and 4-wire SPI mode for a master and
slave SPI.
Table 18-5. 4-wire vs. 3-wire SPI Pin Functions
4-wire SPI

3-wire SPI (Master)

3-wire SPI(Slave)

SPICLKx

SPICLKx

SPICLKx

SPISTEx

SPISTEx

SPISTEx

SPISIMOx

SPIMOMIx

Free

SPISOMIx

Free

SPISISOx

Because in 3-wire mode, the receive and transmit paths within the SPI are connected, any data
transmitted by the SPI module is also received by itself. The application software must take care to
perform a dummy read to clear the SPI data register of the additional received data.
The TALK bit plays an important role in 3-wire SPI mode. The bit must be set to transmit data and cleared
prior to reading data. In master mode, in order to initiate a read, the application software must write
dummy data to the SPI data register (SPIDAT or SPIRXBUF) while the TALK bit is cleared (no data is
transmitted out the SPIMOMI pin) before reading from the data register.
Figure 18-9 and Figure 18-10 illustrate 3-wire master and slave mode.

2138

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Programming Procedure

www.ti.com

Figure 18-9. SPI 3-wire Master Mode
GPIO MUX

SPI Module
Data RX

Free pin

SPIDAT

Data TX
SPIMOMIx

Talk
SPICTL.1

Figure 18-10. SPI 3-wire Slave Mode
GPIO MUX

SPI Module
Data RX

SPISISOx

SPIDAT

Data TX
Free pin
Talk
SPICTL.1

Table 18-6 indicates how data is received or transmitted in the various SPI modes while the TALK bit is
set or cleared.
Table 18-6. 3-Wire SPI Pin Configuration
Pin Mode

SPIPRI[TRIWIRE]

SPICTL[TALK]

SPISIMO

SPISOMI

4-wire

0

X

TX

RX

3-pin mode

1

0

RX

Disconnect from SPI

1

TX/RX

Master Mode

Slave Mode
4-wire

0

X

RX

TX

3-pin mode

1

0

Disconnect from SPI

RX

1

TX/RX

18.4 Programming Procedure
This section describes the procedure for configuring the SPI for the various modes of operation.

18.4.1 Initialization Upon Reset
A system reset forces the SPI peripheral into the following default configuration:
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2139

Programming Procedure

•
•
•
•
•
•

www.ti.com

Unit is configured as a slave module (MASTER_SLAVE = 0)
Transmit capability is disabled (TALK = 0)
Data is latched at the input on the falling edge of the SPICLK signal
Character length is assumed to be one bit
SPI interrupts are disabled
Data in SPIDAT is reset to 0000h

18.4.2 Configuring the SPI
This section describes the procedure in which to configure the SPI module for operation. To prevent
unwanted and unforeseen events from occurring during or as a result of initialization changes, clear the
SPISWRESET bit before making initialization changes, and then set this bit after initialization is complete.
While the SPI is held in reset (SPISWRESET = 0), configuration may be changed in any order. The
following list shows the the SPI configuration procedure in a logical order. However, the SPI registers can
be written with single 16-bit writes, so the order is not required with the exception of SPISWRESET.
To change the SPI configuration:
Step 1. Clear the SPI Software Reset bit (SPISWRESET) to 0 to force the SPI to the reset state.
Step 2. Configure the SPI as desired:
• Select either master or slave mode (MASTER_SLAVE).
• Choose SPICLK polarity and phase (CLKPOLARITY and CLK_PHASE).
• Set the desired baud rate (SPIBRR).
• Enable high speed mode if desired (HS_MODE).
• Set the SPI character length (SPICHAR).
• Clear the SPI Flags (OVERRUN_FLAG, INT_FLAG).
• Enable SPISTE inversion (STEINV).
• Enable 3-wire mode (TRIWIRE).
• If using FIFO enhancements:
– Enable the FIFO enhancements (SPIFFENA).
– Clear the FIFO Flags (TXFFINTCLR, RXFFOVFCLR, and RXFFINTCLR).
– Release transmit and receive FIFO resets (TXFIFO and RXFIFORESET).
– Release SPI FIFO channels from reset (SPIRST).
Step 3. If interrupts are used:
• In non-FIFO mode, enable the receiver overrun and/or SPI interrupts (OVERRUNINTENA
and SPIINTENA).
• In FIFO mode, set the transmit and receive interrupt levels (TXFFIL and RXFFIL) then
enable the interrupts (TXFFIENA and RXFFIENA).
Step 4. Set SPISWRESET to 1 to release the SPI from the reset state.
NOTE: Do not change the SPI configuration when communication is in progress.

18.4.3 Configuring the SPI for High-Speed Mode
In order to achieve the maximum rated speeds, the following settings must be made. This example
assumes that the device is operating at 200 MHz.
Set LSPCLK equal to SYSCLK:
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 0;

Select the appropriate Pin Mux options in GPIO_CTRL_REGS.
During the SPI configuration procedure:
2140

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Programming Procedure

www.ti.com

Set HS_MODE to 1.
SpiaRegs.SPICCR.bit.HS_MODE = 0x1;

Set SPIBRR to 3. SPICLK = LSPCLK/(SPIBRR+1) = 50 MHz
SpiaRegs.SPIBRR = 0x3;

There are no other differences in the configuration from normal SPI operation. Sending and receiving
data, interrupts, and DMA operation will operate without change.

18.4.4 Data Transfer Example
The timing diagram shown in Figure 18-11 illustrates an SPI data transfer between two devices using a
character length of five bits with the SPICLK being symmetrical.
The timing diagram with SPICLK asymmetrical (Figure 18-8) shares similar characterizations with
Figure 18-11 except that the data transfer is one LSPCLK cycle longer per bit during the low pulse
(CLKPOLARITY = 0) or during the high pulse (CLKPOLARITY = 1) of the SPICLK.
Figure 18-11 is applicable for 8-bit SPI only and is not for 28x devices that are capable of working with 16bit data. The figure is shown for illustrative purposes only.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2141

Programming Procedure

www.ti.com

Figure 18-11. Five Bits per Character
Master SPI
Int flag
Slave SPI
Int flag
A B C

D E F G

H

I

J

K

SPISOMI
from slave
7

6

5

4

3

7

6

5

4

3

7

6

5

4

3

7

6

5

4

3

SPISIMO
from master
SPICLK signal options:
CLOCK POLARITY = 0
CLOCK PHASE = 0

CLOCK POLARITY = 0
CLOCK PHASE = 1
CLOCK POLARITY = 1
CLOCK PHASE = 0
CLOCK POLARITY = 1
CLOCK PHASE = 1

SPISTE
A

Slave writes 0D0h to SPIDAT and waits for the master to shift out the data.

B

Master sets the slave SPISTE signal low (active).

C

Master writes 058h to SPIDAT, which starts the transmission procedure.

D

First byte is finished and sets the interrupt flags.

E

Slave reads 0Bh from its SPIRXBUF (right-justified).

F

Slave writes 04Ch to SPIDAT and waits for the master to shift out the data.

G

Master writes 06Ch to SPIDAT, which starts the transmission procedure.

H

Master reads 01Ah from the SPIRXBUF (right−justified).

I

Second byte is finished and sets the interrupt flags.

J

Master reads 89h and the slave reads 8Dh from their respective SPIRXBUF. After the user’s software masks off the
unused bits, the master receives 09h and the slave receives 0Dh.

K

Master clears the slave SPISTE signal high (inactive).

18.4.5 SPI STEINV Bit in Digital Audio Transfers
On those devices with two SPI modules, enabling the STEINV bit on one of the SPI modules allows the
pair of SPIs to receive both left and right-channel digital audio data in slave mode. The SPI module that
receives a normal active-low SPISTE signal stores right-channel data, and the SPI module that receives
an inverted active-high SPISTE signal stores left-channel data from the master. To receive digital audio
data from a digital audio interface receiver, the SPI modules can be connected as shown in Figure 18-12.
NOTE: This configuration is only applicable to slave mode (MASTER_SLAVE = 0). When the SPI is
configured as master (MASTER_SLAVE = 1), the STEINV bit will have no effect on the
SPISTE pin.

2142

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Programming Procedure

www.ti.com

Figure 18-12. SPI Digital Audio Receiver Configuration Using 2 SPIs
SPICLKA

SPICLKB

SPISIMOA

SPISIMOB

SPISOMIA

SPISOMIB

SPI-A

SPI-B

SPISTEA

DATA OUT

L/R CLK

AUDIOBIT
CLK

SPISTEB

DIGITAL
AUDIO
RECEiVER

Standard 28x SPI timing requirements limit the number of digital audio interface formats supported using
the 2-SPI configuration with the STEINV bit. See your device-specific data sheet electricals for SPI timing
requirements. With the SPI clock phase configured such that the CLKPOLARITY bit is 0 and the
CLK_PHASE bit is 1 (data latched on rising edge of clock), standard right-justified digital audio interface
data format is supported as shown in Figure 18-13.
Figure 18-13. Standard Right-Justified Digital Audio Data Format
1/fs

SPI-B Receive (SPISTE invert)
L/R CLK

SPI-A Receive (normal SPISTE)
R-channel

L-channel

SPISTEA/B
SPICLKA/B

AUDIO BIT CLK
DATA OUT

0

n n-1

2

1

0

n n-1

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

2

1

0

SPISIMOA/B

Serial Peripheral Interface (SPI)

2143

Registers

www.ti.com

18.5 Registers
18.5.1 SPI Base Addresses
The base addresses for SPI are shown in Table 18-7.
Table 18-7. SPI Base Address Table
Device Registers

2144

Start Address

End Address

SpiaRegs

SPI_REGS

0x0000_6100

0x0000_610F

SpibRegs

SPI_REGS

0x0000_6110

0x0000_611F

SpicRegs

SPI_REGS

0x0000_6120

0x0000_612F

Serial Peripheral Interface (SPI)

Register Name

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

18.5.2 SPI_REGS Registers
Table 18-8 lists the memory-mapped registers for the SPI_REGS. All register offset addresses not listed in
Table 18-8 should be considered as reserved locations and the register contents should not be modified.
Table 18-8. SPI_REGS Registers
Offset

Acronym

Register Name

0h

SPICCR

SPI Configuration Control Register

Write Protection

Section
Go

1h

SPICTL

SPI Operation Control Register

Go

2h

SPISTS

SPI Status Register

Go

4h

SPIBRR

SPI Baud Rate Register

Go

6h

SPIRXEMU

SPI Emulation Buffer Register

Go

7h

SPIRXBUF

SPI Serial Input Buffer Register

Go

8h

SPITXBUF

SPI Serial Output Buffer Register

Go

9h

SPIDAT

SPI Serial Data Register

Go

Ah

SPIFFTX

SPI FIFO Transmit Register

Go

Bh

SPIFFRX

SPI FIFO Receive Register

Go

Ch

SPIFFCT

SPI FIFO Control Register

Go

Fh

SPIPRI

SPI Priority Control Register

Go

Complex bit access types are encoded to fit into small table cells. Table 18-9 shows the codes that are
used for access types in this section.
Table 18-9. SPI_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

RC

C
R

to Clear
Read

W

W

Write

W1C

1C
W

1 to clear
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2145

Registers

www.ti.com

18.5.2.1 SPICCR Register (Offset = 0h) [reset = 0h]
SPICCR is shown in Figure 18-14 and described in Table 18-10.
Return to Summary Table.
SPI Configuration Control Register
Figure 18-14. SPICCR Register
15

14

13

12

11

10

3

2

9

8

1

0

RESERVED
R-0h
7
SPISWRESET
R/W-0h

6
CLKPOLARITY
R/W-0h

5
HS_MODE
R/W-0h

4
SPILBK
R/W-0h

SPICHAR
R/W-0h

Table 18-10. SPICCR Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SPISWRESET

R/W

0h

SPI Software Reset
When changing configuration, you should clear this bit before the
changes and set this bit before resuming operation.
Reset type: SYSRSn
0h (R/W) = Initializes the SPI operating flags to the reset condition.
Specifically, the RECEIVER OVERRUN Flag bit (SPISTS.7), the SPI
INT FLAG bit (SPISTS.6), and the TXBUF FULL Flag bit (SPISTS.5)
are cleared. SPISTE will become inactive. SPICLK will be
immediately driven to 0 regardless of the clock polarity. The SPI
configuration remains unchanged.
1h (R/W) = SPI is ready to transmit or receive the next character.
When the SPI SW RESET bit is a 0, a character written to the
transmitter will not be shifted out when this bit is set. A new
character must be written to the serial data register. SPICLK will be
returned to its inactive state one SPICLK cycle after this bit is set.

6

CLKPOLARITY

R/W

0h

Shift Clock Polarity
This bit controls the polarity of the SPICLK signal. CLOCK
POLARITY and POLARITY CLOCK PHASE (SPICTL.3) control four
clocking schemes on the SPICLK pin.
Reset type: SYSRSn
0h (R/W) = Data is output on rising edge and input on falling edge.
When no SPI data is sent, SPICLK is at low level. The data input
and output edges depend on the value of the CLOCK PHASE bit
(SPICTL.3) as follows:
- CLOCK PHASE = 0: Data is output on the rising edge of the
SPICLK signal. Input data is latched on the falling edge of the
SPICLK signal.
- CLOCK PHASE = 1: Data is output one half-cycle before the first
rising edge of the SPICLK signal and on subsequent falling edges of
the SPICLK signal. Input data is latched on the rising edge of the
SPICLK signal.
1h (R/W) = Data is output on falling edge and input on rising edge.
When no SPI data is sent, SPICLK is at high level. The data input
and output edges depend on the value of the CLOCK PHASE bit
(SPICTL.3) as follows:
- CLOCK PHASE = 0: Data is output on the falling edge of the
SPICLK signal. Input data is latched on the rising edge of the
SPICLK signal.
- CLOCK PHASE = 1: Data is output one half-cycle before the first
falling edge of the SPICLK signal and on subsequent rising edges of
the SPICLK signal. Input data is latched on the falling edge of the
SPICLK signal.

2146

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 18-10. SPICCR Register Field Descriptions (continued)
Bit
5

Field

Type

Reset

Description

HS_MODE

R/W

0h

High Speed Mode Enable Bits
This bit determines if the High Speed mode is enabled. The correct
GPIOs should be selected in the GPxGMUX/GPxMUX registers.
Reset type: SYSRSn
0h (R/W) = SPI High Speed mode disabled. This is the default value
after reset.
1h (R/W) = SPI High Speed mode enabled,

4

SPILBK

R/W

0h

SPI Loopback Mode Select
Loopback mode allows module validation during device testing. This
mode is valid only in master mode of the SPI.
Reset type: SYSRSn
0h (R/W) = SPI loopback mode disabled. This is the default value
after reset.
1h (R/W) = SPI loopback mode enabled, SIMO/SOMI lines are
connected internally. Used for module self-tests.

3-0

SPICHAR

R/W

0h

Character Length Control Bits
These four bits determine the number of bits to be shifted in or SPI
CHAR0 out as a single character during one shift sequence.
SPICHAR = Word length - 1
Reset type: SYSRSn
0h (R/W) = 1-bit word
1h (R/W) = 2-bit word
7h (R/W) = 8-bit word
Fh (R/W) = 16-bit word

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2147

Registers

www.ti.com

18.5.2.2 SPICTL Register (Offset = 1h) [reset = 0h]
SPICTL is shown in Figure 18-15 and described in Table 18-11.
Return to Summary Table.
SPI Operation Control Register
Figure 18-15. SPICTL Register
15

14

13

12

11

10

9

8

3
CLK_PHASE

2
MASTER_SLA
VE
R/W-0h

1
TALK

0
SPIINTENA

R/W-0h

R/W-0h

RESERVED
R-0h
7

6
RESERVED

5

4
OVERRUNINT
ENA
R/W-0h

R-0h

R/W-0h

Table 18-11. SPICTL Register Field Descriptions
Bit
15-5
4

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

OVERRUNINTENA

R/W

0h

Overrun Interrupt Enable
Overrun Interrupt Enable. Setting this bit causes an interrupt to be
generated when the RECEIVER OVERRUN Flag bit (SPISTS.7) is
set by hardware. Interrupts generated by the RECEIVER OVERRUN
Flag bit and the SPI INT FLAG bit (SPISTS.6) share the same
interrupt vector.
Reset type: SYSRSn
0h (R/W) = Disable RECEIVER OVERRUN interrupts.
1h (R/W) = Enable RECEIVER_OVERRUN interrupts.

3

CLK_PHASE

R/W

0h

SPI Clock Phase Select
This bit controls the phase of the SPICLK signal. CLOCK PHASE
and CLOCK POLARITY (SPICCR.6) make four different clocking
schemes possible (see clocking figures in SPI chapter). When
operating with CLOCK PHASE high, the SPI (master or slave)
makes the first bit of data available after SPIDAT is written and
before the first edge of the SPICLK signal, regardless of which SPI
mode is being used.
Reset type: SYSRSn
0h (R/W) = Normal SPI clocking scheme, depending on the CLOCK
POLARITY bit (SPICCR.6).
1h (R/W) = SPICLK signal delayed by one half-cycle. Polarity
determined by the CLOCK POLARITY bit.

2

MASTER_SLAVE

R/W

0h

SPI Network Mode Control
This bit determines whether the SPI is a network master or slave.
SLAVE During reset initialization, the SPI is automatically configured
as a network slave.
Reset type: SYSRSn
0h (R/W) = SPI is configured as a slave.
1h (R/W) = SPI is configured as a master.

2148

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 18-11. SPICTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

TALK

R/W

0h

Transmit Enable
The TALK bit can disable data transmission (master or slave) by
placing the serial data output in the high-impedance state. If this bit
is disabled during a transmission, the transmit shift register
continues to operate until the previous character is shifted out. When
the TALK bit is disabled, the SPI is still able to receive characters
and update the status flags. TALK is cleared (disabled) by a system
reset.
Reset type: SYSRSn
0h (R/W) = Disables transmission:
- Slave mode operation: If not previously configured as a generalpurpose I/O pin, the SPISOMI pin will be put in the high-impedance
state.
- Master mode operation: If not previously configured as a generalpurpose I/O pin, the SPISIMO pin will be put in the high-impedance
state.
1h (R/W) = Enables transmission For the 4-pin option, ensure to
enable the receiver's SPISTEn input pin.

0

SPIINTENA

R/W

0h

SPI Interrupt Enable
This bit controls the SPI's ability to generate a transmit/receive
interrupt. The SPI INT FLAG bit (SPISTS.6) is unaffected by this bit.
Reset type: SYSRSn
0h (R/W) = Disables the interrupt.
1h (R/W) = Enables the interrupt.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2149

Registers

www.ti.com

18.5.2.3 SPISTS Register (Offset = 2h) [reset = 0h]
SPISTS is shown in Figure 18-16 and described in Table 18-12.
Return to Summary Table.
SPI Status Register
Figure 18-16. SPISTS Register
15

14

13

12

11

10

9

8

3

2
RESERVED

1

0

RESERVED
R-0h
7
OVERRUN_FL
AG
W1C-0h

6
INT_FLAG
RC-0h

5
BUFFULL_FLA
G
R-0h

4

R-0h

Table 18-12. SPISTS Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

OVERRUN_FLAG

W1C

0h

SPI Receiver Overrun Flag
This bit is a read/clear-only flag. The SPI hardware sets this bit when
a receive or transmit operation completes before the previous
character has been read from the buffer. The bit is cleared in one of
three ways:
- Writing a 1 to this bit
- Writing a 0 to SPI SW RESET (SPICCR.7)
- Resetting the system
If the OVERRUN INT ENA bit (SPICTL.4) is set, the SPI requests
only one interrupt upon the first occurrence of setting the RECEIVER
OVERRUN Flag bit. Subsequent overruns will not request additional
interrupts if this flag bit is already set. This means that in order to
allow new overrun interrupt requests the user must clear this flag bit
by writing a 1 to SPISTS.7 each time an overrun condition occurs. In
other words, if the RECEIVER OVERRUN Flag bit is left set (not
cleared) by the interrupt service routine, another overrun interrupt
will not be immediately re-entered when the interrupt service routine
is exited.
Reset type: SYSRSn
0h (R/W) = A receive overrun condition has not occurred.
1h (R/W) = The last received character has been overwritten and
therefore lost (when the SPIRXBUF was overwritten by the SPI
module before the previous character was read by the user
application).
Writing a '1' will clear this bit. The RECEIVER OVERRUN Flag bit
should be cleared during the interrupt service routine because the
RECEIVER OVERRUN Flag bit and SPI INT FLAG bit (SPISTS.6)
share the same interrupt vector. This will alleviate any possible doubt
as to the source of the interrupt when the next byte is received.

2150

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 18-12. SPISTS Register Field Descriptions (continued)
Bit
6

Field

Type

Reset

Description

INT_FLAG

RC

0h

SPI Interrupt Flag
SPI INT FLAG is a read-only flag. Hardware sets this bit to indicate
that the SPI has completed sending or receiving the last bit and is
ready to be serviced. This flag causes an interrupt to be requested if
the SPI INT ENA bit (SPICTL.0) is set. The received character is
placed in the receiver buffer at the same time this bit is set. This bit
is cleared in one of three ways:
- Reading SPIRXBUF
- Writing a 0 to SPI SW RESET (SPICCR.7)
- Resetting the system
Note: This bit should not be used if FIFO mode is enabled. The
internal process of copying the received word from SPIRXBUF to the
Receive FIFO will clear this bit. Use the FIFO status, or FIFO
interrupt bits for similar functionality.
Reset type: SYSRSn
0h (R/W) = No full words have been received or transmitted.
1h (R/W) = Indicates that the SPI has completed sending or
receiving the last bit and is ready to be serviced.

5

BUFFULL_FLAG

R

0h

SPI Transmit Buffer Full Flag
This read-only bit gets set to 1 when a character is written to the SPI
Transmit buffer SPITXBUF. It is cleared when the character is
automatically loaded into SPIDAT when the shifting out of a previous
character is complete.
Reset type: SYSRSn
0h (R/W) = Transmit buffer is not full.
1h (R/W) = Transmit buffer is full.

4-0

RESERVED

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2151

Registers

www.ti.com

18.5.2.4 SPIBRR Register (Offset = 4h) [reset = 0h]
SPIBRR is shown in Figure 18-17 and described in Table 18-13.
Return to Summary Table.
SPI Baud Rate Register
Figure 18-17. SPIBRR Register
15

14

13

12

11

10

9

8

3
SPI_BIT_RATE
R/W-0h

2

1

0

RESERVED
R-0h
7
RESERVED
R-0h

6

5

4

Table 18-13. SPIBRR Register Field Descriptions
Field

Type

Reset

Description

15-7

Bit

RESERVED

R

0h

Reserved

6-0

SPI_BIT_RATE

R/W

0h

SPI Baud Rate Control
These bits determine the bit transfer rate if the SPI is the network
SPI BIT RATE 0 master. There are 125 data-transfer rates (each a
function of the CPU clock, LSPCLK) that can be selected. One data
bit is shifted per SPICLK cycle. (SPICLK is the baud rate clock
output on the SPICLK pin.)
If the SPI is a network slave, the module receives a clock on the
SPICLK pin from the network master. Therefore, these bits have no
effect on the SPICLK signal. The frequency of the input clock from
the master should not exceed the slave SPI's LSPCLK signal divided
by 4.
In master mode, the SPI clock is generated by the SPI and is output
on the SPICLK pin. The SPI baud rates are determined by the
following formula:
For SPIBRR = 3 to 127: SPI Baud Rate = LSPCLK / (SPIBRR + 1)
For SPIBRR = 0, 1, or 2: SPI Baud Rate = LSPCLK / 4
where: LSPCLK = Function of CPU clock frequency X low-speed
peripheral clock of the device SPIBRR = Contents of the SPIBRR in
the master SPI device.
Reset type: SYSRSn
3h (R/W) = SPI Baud Rate = LSPCLK/4
4h (R/W) = SPI Baud Rate = LSPCLK/5
7Eh (R/W) = SPI Baud Rate = LSPCLK/127
7Fh (R/W) = SPI Baud Rate = LSPCLK/128

2152

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

18.5.2.5 SPIRXEMU Register (Offset = 6h) [reset = 0h]
SPIRXEMU is shown in Figure 18-18 and described in Table 18-14.
Return to Summary Table.
SPI Emulation Buffer Register
Figure 18-18. SPIRXEMU Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ERXBn
R-0h

Table 18-14. SPIRXEMU Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

ERXBn

R

0h

Emulation Buffer Received Data
SPIRXEMU functions almost identically to SPIRXBUF, except that
reading SPIRXEMU does not clear the SPI INT FLAG bit
(SPISTS.6). Once the SPIDAT has received the complete character,
the character is transferred to SPIRXEMU and SPIRXBUF, where it
can be read. At the same time, SPI INT FLAG is set.
This mirror register was created to support emulation. Reading
SPIRXBUF clears the SPI INT FLAG bit (SPISTS.6). In the normal
operation of the emulator, the control registers are read to
continually update the contents of these registers on the display
screen. SPIRXEMU was created so that the emulator can read this
register and properly update the contents on the display screen.
Reading SPIRXEMU does not clear the SPI INT FLAG bit, but
reading SPIRXBUF clears this flag. In other words, SPIRXEMU
enables the emulator to emulate the true operation of the SPI more
accurately.
It is recommended that you view SPIRXEMU in the normal emulator
run mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2153

Registers

www.ti.com

18.5.2.6 SPIRXBUF Register (Offset = 7h) [reset = 0h]
SPIRXBUF is shown in Figure 18-19 and described in Table 18-15.
Return to Summary Table.
SPI Serial Input Buffer Register
Figure 18-19. SPIRXBUF Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RXBn
R-0h

Table 18-15. SPIRXBUF Register Field Descriptions
Bit

Field

Type

Reset

Description

15-0

RXBn

R

0h

Received Data
Once SPIDAT has received the complete character, the character is
transferred to SPIRXBUF, where it can be read. At the same time,
the SPI INT FLAG bit (SPISTS.6) is set. Since data is shifted into the
SPI's most significant bit first, it is stored right-justified in this
register.
Reset type: SYSRSn

2154

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

18.5.2.7 SPITXBUF Register (Offset = 8h) [reset = 0h]
SPITXBUF is shown in Figure 18-20 and described in Table 18-16.
Return to Summary Table.
SPI Serial Output Buffer Register
Figure 18-20. SPITXBUF Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TXBn
R/W-0h

Table 18-16. SPITXBUF Register Field Descriptions
Bit

Field

Type

Reset

Description

15-0

TXBn

R/W

0h

Transmit Data Buffer
This is where the next character to be transmitted is stored. When
the transmission of the current character has completed, if the TX
BUF FULL Flag bit is set, the contents of this register is
automatically transferred to SPIDAT, and the TX BUF FULL Flag is
cleared. Writes to SPITXBUF must be left-justified.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2155

Registers

www.ti.com

18.5.2.8 SPIDAT Register (Offset = 9h) [reset = 0h]
SPIDAT is shown in Figure 18-21 and described in Table 18-17.
Return to Summary Table.
SPI Serial Data Register
Figure 18-21. SPIDAT Register
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SDATn
R/W-0h

Table 18-17. SPIDAT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

SDATn

R/W

0h

Serial Data Shift Register
- It provides data to be output on the serial output pin if the TALK bit
(SPICTL.1) is set.
- When the SPI is operating as a master, a data transfer is initiated.
When initiating a transfer, see the CLOCK POLARITY bit
(SPICCR.6) described in Section 10.2.1.1 and the CLOCK PHASE
bit (SPICTL.3) described in Section 10.2.1.2, for the requirements.
In master mode, writing dummy data to SPIDAT initiates a receiver
sequence. Since the data is not hardware-justified for characters
shorter than sixteen bits, transmit data must be written in left-justified
form, and received data read in right-justified form.
Reset type: SYSRSn

2156

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

18.5.2.9 SPIFFTX Register (Offset = Ah) [reset = A000h]
SPIFFTX is shown in Figure 18-22 and described in Table 18-18.
Return to Summary Table.
SPI FIFO Transmit Register
Figure 18-22. SPIFFTX Register
15
SPIRST
R/W-1h

14
SPIFFENA
R/W-0h

13
TXFIFO
R/W-1h

12

11

10
TXFFST
R-0h

9

8

7
TXFFINT
R-0h

6
TXFFINTCLR
W-0h

5
TXFFIENA
R/W-0h

4

3

2
TXFFIL
R/W-0h

1

0

Table 18-18. SPIFFTX Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SPIRST

R/W

1h

SPI Reset
Reset type: SYSRSn
0h (R/W) = Write 0 to reset the SPI transmit and receive channels.
The SPI FIFO register configuration bits will be left as is.
1h (R/W) = SPI FIFO can resume transmit or receive. No effect to
the SPI registers bits.

14

SPIFFENA

R/W

0h

SPI FIFO Enhancements Enable
Reset type: SYSRSn
0h (R/W) = SPI FIFO enhancements are disabled.
1h (R/W) = SPI FIFO enhancements are enabled.

13

TXFIFO

R/W

1h

TX FIFO Reset
Reset type: SYSRSn
0h (R/W) = Write 0 to reset the FIFO pointer to zero, and hold in
reset.
1h (R/W) = Release transmit FIFO from reset.

12-8

TXFFST

R

0h

Transmit FIFO Status
Reset type: SYSRSn
0h (R/W) = Transmit FIFO is empty.
1h (R/W) = Transmit FIFO has 1 word.
2h (R/W) = Transmit FIFO has 2 words.
10h (R/W) = Transmit FIFO has 16 words, which is the maximum.
1Fh (R/W) = Reserved.

7

TXFFINT

R

0h

TX FIFO Interrupt Flag
Reset type: SYSRSn
0h (R/W) = TXFIFO interrupt has not occurred, This is a read-only
bit.
1h (R/W) = TXFIFO interrupt has occurred, This is a read-only bit.

6

TXFFINTCLR

W

0h

TXFIFO Interrupt Clear
Reset type: SYSRSn
0h (R/W) = Write 0 has no effect on TXFIFINT flag bit, Bit reads
back a zero.
1h (R/W) = Write 1 to clear SPIFFTX[TXFFINT] flag.

5

TXFFIENA

R/W

0h

TX FIFO Interrupt Enable
Reset type: SYSRSn
0h (R/W) = TX FIFO interrupt based on TXFFIL match (less than or
equal to) will be disabled.
1h (R/W) = TX FIFO interrupt based on TXFFIL match (less than or
equal to) will be enabled.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2157

Registers

www.ti.com

Table 18-18. SPIFFTX Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-0

TXFFIL

R/W

0h

Transmit FIFO Interrupt Level Bits
Transmit FIFO will generate interrupt when the FIFO status bits
(TXFFST4-0) and FIFO level bits (TXFFIL4-0 ) match (less than or
equal to).
Reset type: SYSRSn
0h (R/W) = A TX FIFO interrupt request is generated when there are
no words remaining in the TX buffer.
1h (R/W) = A TX FIFO interrupt request is generated when there is 1
word or no words remaining in the TX buffer.
2h (R/W) = A TX FIFO interrupt request is generated when there is 2
words or fewer remaining in the TX buffer.
10h (R/W) = A TX FIFO interrupt request is generated when there
are 16 words or fewer remaining in the TX buffer.
1Fh (R/W) = Reserved.

2158

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

18.5.2.10 SPIFFRX Register (Offset = Bh) [reset = 201Fh]
SPIFFRX is shown in Figure 18-23 and described in Table 18-19.
Return to Summary Table.
SPI FIFO Receive Register
Figure 18-23. SPIFFRX Register
15
RXFFOVF
R-0h

14
RXFFOVFCLR
W-0h

13
RXFIFORESET
R/W-1h

12

11

10
RXFFST
R-0h

9

8

7
RXFFINT
R-0h

6
RXFFINTCLR
W-0h

5
RXFFIENA
R/W-0h

4

3

2
RXFFIL
R/W-1Fh

1

0

Table 18-19. SPIFFRX Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RXFFOVF

R

0h

Receive FIFO Overflow Flag
Reset type: SYSRSn
0h (R/W) = Receive FIFO has not overflowed. This is a read-only bit.
1h (R/W) = Receive FIFO has overflowed, read-only bit. More than
16 words have been received in to the FIFO, and the first received
word is lost.

14

RXFFOVFCLR

W

0h

Receive FIFO Overflow Clear
Reset type: SYSRSn
0h (R/W) = Write 0 does not affect RXFFOVF flag bit, Bit reads back
a zero.
1h (R/W) = Write 1 to clear SPIFFRX[RXFFOVF].

13

RXFIFORESET

R/W

1h

Receive FIFO Reset
Reset type: SYSRSn
0h (R/W) = Write 0 to reset the FIFO pointer to zero, and hold in
reset.
1h (R/W) = Re-enable receive FIFO operation.

12-8

RXFFST

R

0h

Receive FIFO Status
Reset type: SYSRSn
0h (R/W) = Receive FIFO is empty.
1h (R/W) = Receive FIFO has 1 word.
2h (R/W) = Receive FIFO has 2 words.
10h (R/W) = Receive FIFO has 16 words, which is the maximum.
1Fh (R/W) = Reserved.

7

RXFFINT

R

0h

Receive FIFO Interrupt Flag
Reset type: SYSRSn
0h (R/W) = RXFIFO interrupt has not occurred. This is a read-only
bit.
1h (R/W) = RXFIFO interrupt has occurred. This is a read-only bit.

6

RXFFINTCLR

W

0h

Receive FIFO Interrupt Clear
Reset type: SYSRSn
0h (R/W) = Write 0 has no effect on RXFIFINT flag bit, Bit reads
back a zero.
1h (R/W) = Write 1 to clear SPIFFRX[RXFFINT] flag

5

RXFFIENA

R/W

0h

RX FIFO Interrupt Enable
Reset type: SYSRSn
0h (R/W) = RX FIFO interrupt based on RXFFIL match (greater than
or equal to) will be disabled.
1h (R/W) = RX FIFO interrupt based on RXFFIL match (greater than
or equal to) will be enabled.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2159

Registers

www.ti.com

Table 18-19. SPIFFRX Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-0

RXFFIL

R/W

1Fh

Receive FIFO Interrupt Level Bits
11111 Receive FIFO generates an interrupt when the FIFO status
bits (RXFFST4-0) are greater than or equal to the FIFO level bits
(RXFFIL4-0). The default value of these bits after reset is 11111.
This avoids frequent interrupts after reset, as the receive FIFO will
be empty most of the time.
Reset type: SYSRSn
0h (R/W) = A RX FIFO interrupt request is generated when there is 0
or more words in the RX buffer.
1h (R/W) = A RX FIFO interrupt request is generated when there are
1 or more words in the RX buffer.
2h (R/W) = A RX FIFO interrupt request is generated when there are
2 or more words in the RX buffer.
10h (R/W) = A RX FIFO interrupt request is generated when there
are 16 words in the RX buffer.
1Fh (R/W) = Reserved.

2160

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

18.5.2.11 SPIFFCT Register (Offset = Ch) [reset = 0h]
SPIFFCT is shown in Figure 18-24 and described in Table 18-20.
Return to Summary Table.
SPI FIFO Control Register
Figure 18-24. SPIFFCT Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
TXDLY
R/W-0h

Table 18-20. SPIFFCT Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

TXDLY

R/W

0h

FIFO Transmit Delay Bits
These bits define the delay between every transfer from FIFO
transmit buffer to transmit shift register. The delay is defined in
number SPI serial clock cycles. The 8-bit register could define a
minimum delay of 0 serial clock cycles and a maximum of 255 serial
clock cycles. In FIFO mode, the buffer (TXBUF) between the shift
register and the FIFO should be filled only after the shift register has
completed shifting of the last bit. This is required to pass on the
delay between transfers to the data stream. In the FIFO mode
TXBUF should not be treated as one additional level of buffer.
Reset type: SYSRSn
0h (R/W) = The next word in the TX FIFO buffer is transferred to
SPITXBUF immediately upon completion of transmission of the
previous word.
1h (R/W) = The next word in the TX FIFO buffer is transferred to
SPITXBUF1 serial clock cycle after completion of transmission of the
previous word.
2h (R/W) = The next word in the TX FIFO buffer is transferred to
SPITXBUF 2 serial clock cycles after completion of transmission of
the previous word.
FFh (R/W) = The next word in the TX FIFO buffer is transferred to
SPITXBUF 255 serial clock cycles after completion of transmission
of the previous word.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2161

Registers

www.ti.com

18.5.2.12 SPIPRI Register (Offset = Fh) [reset = 0h]
SPIPRI is shown in Figure 18-25 and described in Table 18-21.
Return to Summary Table.
SPI Priority Control Register
Figure 18-25. SPIPRI Register
15

14

13

12

11

10

9

8

2

1
STEINV
R/W-0h

0
TRIWIRE
R/W-0h

RESERVED
R-0h
7
RESERVED
R-0h

6
RESERVED
R-0h

5
SOFT
R/W-0h

4
FREE
R/W-0h

3
RESERVED
R-0h

Table 18-21. SPIPRI Register Field Descriptions
Field

Type

Reset

Description

15-7

Bit

RESERVED

R

0h

Reserved

6

RESERVED

R

0h

Reserved

5

SOFT

R/W

0h

Emulation Soft Run
This bit only has an effect when the FREE bit is 0.
Reset type: SYSRSn
0h (R/W) = Transmission stops after midway in the bit stream while
TSUSPEND is asserted. Once TSUSPEND is deasserted without a
system reset, the remainder of the bits pending in the DATBUF are
shifted. Example: If SPIDAT has shifted 3 out of 8 bits, the
communication freezes right there. However, if TSUSPEND is later
deasserted without resetting the SPI, SPI starts transmitting from
where it had stopped (fourth bit in this case) and will transmit 8 bits
from that point. The SCI module operates differently.
1h (R/W) = If the emulation suspend occurs before the start of a
transmission, (that is, before the first SPICLK pulse) then the
transmission will not occur. If the emulation suspend occurs after the
start of a transmission, then the data will be shifted out to
completion. When the start of transmission occurs is dependent on
the baud rate used.
Standard SPI mode: Stop after transmitting the words in the shift
register and buffer. That is, after TXBUF and SPIDAT are empty.
In FIFO mode: Stop after transmitting the words in the shift register
and buffer. That is, after TX FIFO and SPIDAT are empty.

4

3-2
1

FREE

R/W

0h

Emulation Free Run
Reset type: SYSRSn
0h (R/W) = Emulation mode is selected by the SOFT bit
1h (R/W) = Free run, continue SPI operation regardless of suspend
or when the suspend occurred.

RESERVED

R

0h

Reserved

STEINV

R/W

0h

SPISTEn Inversion Bit
On devices with 2 SPI modules, inverting the SPISTE signal on one
of the modules allows the device to receive left and right- channel
digital audio data.
This bit is only applicable to slave mode. Writing to this bit while
configured as master (MASTER_SLAVE = 1) has no effect
Reset type: SYSRSn
0h (R/W) = SPISTEn is active low (normal)
1h (R/W) = SPISTE is active high (inverted)

2162

Serial Peripheral Interface (SPI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 18-21. SPIPRI Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

TRIWIRE

R/W

0h

SPI 3-wire Mode Enable
Reset type: SYSRSn
0h (R/W) = Normal 4-wire SPI mode.
1h (R/W) = 3-wire SPI mode enabled. The unused pin becomes a
GPIO pin. In master mode, the SPISIMO pin becomes the SPIMOMI
(master receive and transmit) pin and SPISOMI is free for non-SPI
use. In slave mode, the SPISOMI pin becomes the SPISISO (slave
receive and transmit) pin and SPISIMO is free for non-SPI use.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Serial Peripheral Interface (SPI)

2163

Chapter 19
SPRUHM8G – December 2013 – Revised September 2017

Serial Communications Interface (SCI)
This chapter describes the features and operation of the serial communication interface (SCI) module. SCI
is a two−wire asynchronous serial port, commonly known as a UART. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard non-returnto-zero (NRZ) format. The SCI receiver and transmitter each have a 16-level deep FIFO for reducing
servicing overhead, and each has its own separate enable and interrupt bits. Both can be operated
independently for half-duplex communication, or simultaneously for full-duplex communication.
To specify data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to different speeds through a 16-bit baud-select register.
Topic

...........................................................................................................................

19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
19.12
19.13
19.14

2164

Enhanced SCI Module Overview .......................................................................
Architecture ...................................................................................................
SCI Module Signal Summary ............................................................................
Configuring Device Pins ..................................................................................
Multiprocessor and Asynchronous Communication Modes .................................
SCI Programmable Data Format........................................................................
SCI Multiprocessor Communication ..................................................................
Idle-Line Multiprocessor Mode .........................................................................
Address-Bit Multiprocessor Mode .....................................................................
SCI Communication Format ............................................................................
SCI Port Interrupts .........................................................................................
SCI Baud Rate Calculations ............................................................................
SCI Enhanced Features ..................................................................................
Registers ......................................................................................................

Serial Communications Interface (SCI)

Page

2165
2166
2167
2167
2167
2168
2168
2169
2171
2172
2174
2174
2175
2178

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Enhanced SCI Module Overview

www.ti.com

19.1 Enhanced SCI Module Overview
The SCI interfaces are shown in Figure 19-1.
Figure 19-1. SCI CPU Interface
PCLKCR7

Bit
Clock

GPIO
MUX

SCITXD

Low Speed
Prescaler

SYSCLK

CPU

Peripheral Bus

LSPCLK

SYSRS

SCI

SCIRXD

RXINT
TXINT

PIE

Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Both pins can be used as GPIO if not used for SCI.
• Baud rate programmable to 64K different rates
• Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt- driven or polled algorithms
with status flags.
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ (non-return-to-zero) format
• 13 SCI module control registers located in the control register frame beginning at address 7050h
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as
zeros. Writing to the upper byte has no effect.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2165

Architecture

www.ti.com

Enhanced features:
• Auto-baud-detect hardware logic
• 16-level transmit/receive FIFO
Figure 19-2 shows the SCI module block diagram. The SCI port operation is configured and controlled by
the registers listed in Section 19.14 of this chapter.
Figure 19-2. Serial Communications Interface (SCI) Module Block Diagram

SCICTL1.1
SCITXD

Frame Format and Mode
TXSHF
Register

Parity
Even/Odd
Enable

TX EMPTY
SCICTL2.6

8

SCICCR.6 SCICCR.5

TXRDY
Transmitter−Data
Buffer Register

TXWAKE

8
TX FIFO _0

SCICTL1.3
1

TX INT ENA

SCICTL2.7
SCICTL2.0
TXINT

TX FIFO Interrupt

TX Interrupt
Logic

TX FIFO _1
−−−−−
TX FIFO _15

To CPU
SCI TX Interrupt select logic

SCITXBUF.7−0

WUT

SCITXD

TXENA

TX FIFO registers
SCIFFENA

Auto baud detect logic

SCIFFTX.14
SCIHBAUD. 15 − 8
SCIRXD

RXSHF

Baud Rate
MSbyte
Register

SCIRXD

Register
RXWAKE
SCIRXST.1

LSPCLK
SCILBAUD. 7 − 0

RXENA
8

Baud Rate
LSbyte
Register

SCICTL1.0

Receive Data
Buffer register
SCIRXBUF.7−0
8
RX FIFO _15
−−−−−
RX FIFO_1

SCICTL2.1
RXRDY
SCIRXST.6
BRKDT
SCIRXST.5

RX FIFO _0
SCIRXBUF.7−0

RX/BK INT ENA

RX FIFO Interrupt

RX Interrupt
Logic

RXINT
To CPU

RX FIFO registers
RXFFOVF
SCIRXST.7

SCIRXST.4 − 2
SCIFFRX.15

RX Error

FE OE PE
RX Error
RX ERR INT ENA
SCICTL1.6

SCI RX Interrupt select logic

19.2 Architecture
The major elements used in full-duplex operation are shown in Figure 19-2 and include:
• A transmitter (TX) and its major registers (upper half of Figure 19-2)
2166

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

SCI Module Signal Summary

www.ti.com

•

•
•

– SCITXBUF — transmitter data buffer register. Contains data (loaded by the CPU) to be transmitted
– TXSHF register — transmitter shift register. Accepts data from register SCITXBUF and shifts data
onto the SCITXD pin, one bit at a time
A receiver (RX) and its major registers (lower half of Figure 19-2)
– RXSHF register — receiver shift register. Shifts data in from SCIRXD pin, one bit at a time
– SCIRXBUF — receiver data buffer register. Contains data to be read by the CPU. Data from a
remote processor is loaded into register RXSHF and then into registers SCIRXBUF and
SCIRXEMU
A programmable baud generator
Data-memory-mapped control and status registers

The SCI receiver and transmitter can operate either independently or simultaneously.

19.3 SCI Module Signal Summary
Table 19-1. SCI Module Signal Summary
Signal Name

Description
External signals

SCIRXD

SCI Asynchronous Serial Port receive data

SCITXD

SCI Asynchronous Serial Port transmit data
Control

Baud clock

LSPCLK Prescaled clock
Interrupt signals

TXINT

Transmit interrupt

RXINT

Receive Interrupt

19.4 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.

19.5 Multiprocessor and Asynchronous Communication Modes
The SCI has two multiprocessor protocols, the idle-line multiprocessor mode (see Section 19.8) and the
address-bit multiprocessor mode (see Section 19.9). These protocols allow efficient data transfer between
multiple processors.
The SCI offers the universal asynchronous receiver/transmitter (UART) communications mode for
interfacing with many popular peripherals. The asynchronous mode (see Section 19.10) requires two lines
to interface with many standard devices such as terminals and printers that use RS-232-C formats. Data
transmission characteristics include:
• One start bit
• One to eight data bits
• An even/odd parity bit or no parity bit
• One or two stop bits

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2167

SCI Programmable Data Format

www.ti.com

19.6 SCI Programmable Data Format
SCI data, both receive and transmit, is in NRZ (non-return-to-zero) format. The NRZ data format, shown in
Figure 19-3, consists of:
• One start bit
• One to eight data bits
• An even/odd parity bit (optional)
• One or two stop bits
• An extra bit to distinguish addresses from data (address-bit mode only)
The basic unit of data is called a character and is one to eight bits in length. Each character of data is
formatted with a start bit, one or two stop bits, and optional parity and address bits. A character of data
with its formatting information is called a frame and is shown in Figure 19-3.
Figure 19-3. Typical SCI Data Frame Formats
Start

LSB

2

3

4

5

6

7

MSB Parity Stop

Idle-line mode
(Normal nonmultiprocessor communications)
Address bit
Start

LSB

2

3

4

5

6

7

MSB Addr/ Parity Stop
data

Address-bit mode

To program the data format, use the SCICCR register. The bits used to program the data format are
shown in Table 19-2.
Table 19-2. Programming the Data Format Using SCICCR
Bit(s)
2-0
5

Bit Name

Designation

Functions

SCI CHAR2-0

SCICCR.2:0

Select the character (data) length (one to eight bits).

PARITY

SCICCR.5

Enables the parity function if set to 1, or disables the parity function

ENABLE
6

EVEN/ODD

if cleared to 0.
SCICCR.6

PARITY
7

STOP BITS

If parity is enabled, selects odd parity if cleared to 0 or even parity if
set to 1.

SCICCR.7

Determines the number of stop bits transmitted—one stop bit if cleared to 0 or two
stop bits if set to 1.

19.7 SCI Multiprocessor Communication
The multiprocessor communication format allows one processor to efficiently send blocks of data to other
processors on the same serial link. On one serial line, there should be only one transfer at a time. In other
words, there can be only one talker on a serial line at a time.
Address Byte
The first byte of a block of information that the talker sends contains an address byte that is read by all
listeners. Only listeners with the correct address can be interrupted by the data bytes that follow the
address byte. The listeners with an incorrect address remain uninterrupted until the next address byte.
Sleep Bit
All processors on the serial link set the SCI SLEEP bit (bit 2 of SCICTL1) to 1 so that they are interrupted
only when the address byte is detected. When a processor reads a block address that corresponds to the
CPU device address as set by your application software, your program must clear the SLEEP bit to enable
the SCI to generate an interrupt on receipt of each data byte.

2168

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

SCI Multiprocessor Communication

www.ti.com

Although the receiver still operates when the SLEEP bit is 1, it does not set RXRDY, RXINT, or any of the
receiver error status bits to 1 unless the address byte is detected and the address bit in the received
frame is a 1 (applicable to address-bit mode). The SCI does not alter the SLEEP bit; your software must
alter the SLEEP bit.

19.7.1 Recognizing the Address Byte
A processor recognizes an address byte differently, depending on the multiprocessor mode used. For
example:
• The idle-line mode (Section 19.8) leaves a quiet space before the address byte. This mode does not
have an extra address/data bit and is more efficient than the address-bit mode for handling blocks that
contain more than ten bytes of data. The idle-line mode should be used for typical non-multiprocessor
SCI communication.
• The address-bit mode (Section 19.9) adds an extra bit (that is, an address bit) into every byte to
distinguish addresses from data. This mode is more efficient in handling many small blocks of data
because, unlike the idle mode, it does not have to wait between blocks of data. However, at a high
transmit speed, the program is not fast enough to avoid a 10-bit idle in the transmission stream.

19.7.2 Controlling the SCI TX and RX Features
The multiprocessor mode is software selectable via the ADDR/IDLE MODE bit (SCICCR, bit 3). Both
modes use the TXWAKE flag bit (SCICTL1, bit 3), RXWAKE flag bit (SCIRXST, bit1), and the SLEEP flag
bit (SCICTL1, bit 2) to control the SCI transmitter and receiver features of these modes.

19.7.3 Receipt Sequence
In both multiprocessor modes, the receive sequence is as follows:
1. At the receipt of an address block, the SCI port wakes up and requests an interrupt (bit number 1
RX/BK INT ENA-of SCICTL2 must be enabled to request an interrupt). It reads the first frame of the
block, which contains the destination address.
2. A software routine is entered through the interrupt and checks the incoming address. This address
byte is checked against its device address byte stored in memory.
3. If the check shows that the block is addressed to the device CPU, the CPU clears the SLEEP bit and
reads the rest of the block. If not, the software routine exits with the SLEEP bit still set, and does not
receive interrupts until the next block start.

19.8 Idle-Line Multiprocessor Mode
In the idle-line multiprocessor protocol (ADDR/IDLE MODE bit=0), blocks are separated by having a
longer idle time between the blocks than between frames in the blocks. An idle time of ten or more highlevel bits after a frame indicates the start of a new block. The time of a single bit is calculated directly from
the baud value (bits per second). The idle-line multiprocessor communication format is shown in
Figure 19-4 (ADDR/IDLE MODE bit is bit 3 of SCICCR).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2169

Idle-Line Multiprocessor Mode

www.ti.com

ÇÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇ

ÇÇÇÇÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ

ÇÇÇÇ
ÇÇ
ÇÇ
ÇÇÇÇ
ÇÇÇÇ

Figure 19-4. Idle-Line Multiprocessor Communication Format

Data format
(Pins SCIRXD, SCITXD)

Several blocks of frames

Idle periods of 10 bits or more
separate the blocks

Address

First frame within block
Is address; it follows idle
period of 10 bits or more

Start

Data format expanded

Start

Start

One block of frames
Data

Frame within Idle period
block
less than 10
bits

Last Data

Idle period
of 10 bits
or more

19.8.1 Idle-Line Mode Steps
The steps followed by the idle-line mode:
Step 1. SCI wakes up after receipt of the block-start signal.
Step 2. The processor recognizes the next SCI interrupt.
Step 3. The interrupt service routine compares the received address (sent by a remote transmitter) to
its own.
Step 4. If the CPU is being addressed, the service routine clears the SLEEP bit and receives the rest
of the data block.
Step 5. If the CPU is not being addressed, the SLEEP bit remains set. This lets the CPU continue to
execute its main program without being interrupted by the SCI port until the next detection of
a block start.

19.8.2 Block Start Signal
There are two ways to send a block-start signal:
1. Method 1: Deliberately leave an idle time of ten bits or more by delaying the time between the
transmission of the last frame of data in the previous block and the transmission of the address frame
of the new block.
2. Method 2: The SCI port first sets the TXWAKE bit (SCICTL1, bit 3) to 1 before writing to the
SCITXBUF register. This sends an idle time of exactly 11 bits. In this method, the serial
communications line is not idle any longer than necessary. (A don't care byte has to be written to
SCITXBUF after setting TXWAKE, and before sending the address, so as to transmit the idle time.)

19.8.3 Wake-UP Temporary (WUT) Flag
Associated with the TXWAKE bit is the wake-up temporary (WUT) flag. WUT is an internal flag, doublebuffered with TXWAKE. When TXSHF is loaded from SCITXBUF, WUT is loaded from TXWAKE, and the
TXWAKE bit is cleared to 0. This arrangement is shown in Figure 19-5.
Figure 19-5. Double-Buffered WUT and TXSHF
TXWAKE

Transmit buffer (SCITXBUF)

1

8

WUT

TXSHF

Sending a Block Start Signal
2170

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Idle-Line Multiprocessor Mode

www.ti.com

To send out a block-start signal of exactly one frame time during a sequence of block transmissions:
1. Write a 1 to the TXWAKE bit.
2. Write a data word (content not important: a don’t care) to the SCITXBUF register (transmit data buffer)
to send a block-start signal. (The first data word written is suppressed while the block-start signal is
sent out and ignored after that.) When the TXSHF (transmit shift register) is free again, SCITXBUF
contents are shifted to TXSHF, the TXWAKE value is shifted to WUT, and then TXWAKE is cleared.
Because TXWAKE was set to a 1, the start, data, and parity bits are replaced by an idle period of 11
bits transmitted following the last stop bit of the previous frame.
3. Write a new address value to SCITXBUF
A don’t-care data word must first be written to register SCITXBUF so that the TXWAKE bit value can
be shifted to WUT. After the don’t-care data word is shifted to the TXSHF register, the SCITXBUF (and
TXWAKE if necessary) can be written to again because TXSHF and WUT are both double-buffered.

19.8.4 Receiver Operation
The receiver operates regardless of the SLEEP bit. However, the receiver neither sets RXRDY nor the
error status bits, nor does it request a receive interrupt until an address frame is detected.

19.9 Address-Bit Multiprocessor Mode
In the address-bit protocol (ADDR/IDLE MODE bit=1), frames have an extra bit called an address bit that
immediately follows the last data bit. The address bit is set to 1 in the first frame of the block and to 0 in all
other frames. The idle period timing is irrelevant (see Figure 19-6).

19.9.1 Sending an Address
The TXWAKE bit value is placed in the address bit. During transmission, when the SCITXBUF register
and TXWAKE are loaded into the TXSHF register and WUT respectively, TXWAKE is reset to 0 and WUT
becomes the value of the address bit of the current frame. Thus, to send an address:
1. Set the TXWAKE bit to 1 and write the appropriate address value to the SCITXBUF register.
When this address value is transferred to the TXSHF register and shifted out, its address bit is sent as
a 1. This flags the other processors on the serial link to read the address.
2. Write to SCITXBUF and TXWAKE after TXSHF and WUT are loaded. (Can be written to immediately
since both TXSHF and WUT are both double-buffered.
3. Leave the TXWAKE bit set to 0 to transmit non-address frames in the block.
NOTE: As a general rule, the address-bit format is typically used for data frames of 11 bytes or less.
This format adds one bit value (1 for an address frame, 0 for a data frame) to all data bytes
transmitted. The idle-line format is typically used for data frames of 12 bytes or more.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2171

SCI Communication Format

www.ti.com

ÉÉ
ÉÉ
ÉÉ
ÉÉ

ÉÉ
ÉÉ
ÉÉ
ÉÉ

ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ

Figure 19-6. Address-Bit Multiprocessor Communication Format

Data format
(Pins SCIRXD, SCITXD)

Blocks of frames

Idle periods of no significance

Addr

1

First frame within
block is address
(Address bit is 1)

Start

Data format expanded

Start

Start

One block
0

Data

Frame within block
(Address bit is 0)

Addr

1

Next frame is address
for next block
(Address bit is 1)
Idle time is of
no significance

Address bit
Start LSB

1

MSB

Parity Stop

Address-bit mode frame example

19.10 SCI Communication Format
The SCI asynchronous communication format uses either single line (one way) or two line (two way)
communications. In this mode, the frame consists of a start bit, one to eight data bits, an optional
even/odd parity bit, and one or two stop bits (shown in Figure 19-7). There are eight SCICLK periods per
data bit.
The receiver begins operation on receipt of a valid start bit. A valid start bit is identified by four
consecutive internal SCICLK periods of zero bits as shown in Figure 19-7. If any bit is not zero, then the
processor starts over and begins looking for another start bit.
For the bits following the start bit, the processor determines the bit value by making three samples in the
middle of the bits. These samples occur on the fourth, fifth, and sixth SCICLK periods, and bit-value
determination is on a majority (two out of three) basis. Figure 19-7 illustrates the asynchronous
communication format for this with a start bit showing where a majority vote is taken.
Since the receiver synchronizes itself to frames, the external transmitting and receiving devices do not
have to use a synchronized serial clock. The clock can be generated locally.
Figure 19-7. SCI Asynchronous Communications Format
Majority
vote
SC ICLK
(internal)

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

SCIRXD
Start bit

8 SCICLK periods per data bit

2172

Serial Communications Interface (SCI)

LSB of data

8 SCICLK periods per data bit

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

SCI Communication Format

www.ti.com

19.10.1 Receiver Signals in Communication Modes
Figure 19-8 illustrates an example of receiver signal timing that assumes the following conditions:
• Address-bit wake-up mode (address bit does not appear in idle-line mode)
• Six bits per character
Figure 19-8. SCI RX Signals in Communication Modes
RXENA
1

6

RXRDY
3
2

Start

SCIRXD pin

4
5

0

1

2

3

4

5

Ad

Pa

Stop

0

Start

1

2

Frame

(1)

Data arrives on the SCIRXD pin, start bit detected.

(2)

Bit RXENA is brought low to disable the receiver. Data continues to be assembled in RXSHF but is not
transferred to the receiver buffer register.

Notes:
1. Flag bit RXENA (SCICTL1, bit 0) goes high to enable the receiver.
2. Data arrives on the SCIRXD pin, start bit detected.
3. Data is shifted from RXSHF to the receiver buffer register (SCIRXBUF); an interrupt is requested. Flag
bit RXRDY (SCIRXST, bit 6) goes high to signal that a new character has been received.
4. The program reads SCIRXBUF; flag RXRDY is automatically cleared.
5. The next byte of data arrives on the SCIRXD pin; the start bit is detected, then cleared.
6. Bit RXENA is brought low to disable the receiver. Data continues to be assembled in RXSHF but is not
transferred to the receiver buffer register.

19.10.2 Transmitter Signals in Communication Modes
Figure 19-9 illustrates an example of transmitter signal timing that assumes the following conditions:
• Address-bit wake-up mode (address bit does not appear in idle-line mode)
• Three bits per character
Figure 19-9. SCI TX Signals in Communications Mode
TXENA
1

6

TXRDY
2 3

4
5

TX EMPTY
First Character
SCITXD pin

Start

0

1

2

Ad

Second Character
Pa Stop

Start

0

1

Frame

2

Ad

7

Pa Stop

Frame

Notes:
1. Bit TXENA (SCICTL1, bit 1) goes high, enabling the transmitter to send data.
2. SCITXBUF is written to; thus, (1) the transmitter is no longer empty, and (2) TXRDY goes low.
3. The SCI transfers data to the shift register (TXSHF). The transmitter is ready for a second character
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2173

SCI Port Interrupts

4.
5.
6.
7.

www.ti.com

(TXRDY goes high), and it requests an interrupt (to enable an interrupt, bit TX INT ENA — SCICTL2,
bit 0 — must be set).
The program writes a second character to SCITXBUF after TXRDY goes high (item 3). (TXRDY goes
low again after the second character is written to SCITXBUF.)
Transmission of the first character is complete. Transfer of the second character to shift register
TXSHF begins.
Bit TXENA goes low to disable the transmitter; the SCI finishes transmitting the current character.
Transmission of the second character is complete; transmitter is empty and ready for new character.

19.11 SCI Port Interrupts
The SCI receiver and transmitter can be interrupt controlled. The SCICTL2 register has one flag bit
(TXRDY) that indicates active interrupt conditions, and the SCIRXST register has two interrupt flag bits
(RXRDY and BRKDT), plus the RX ERROR interrupt flag which is a logical OR of the FE, OE, BRKDT,
and PE conditions. The transmitter and receiver have separate interrupt-enable bits. When not enabled,
the interrupts are not asserted; however, the condition flags remain active, reflecting transmission and
receipt status.
The SCI has independent peripheral interrupt vectors for the receiver and transmitter. Peripheral interrupt
requests can be either high priority or low priority. This is indicated by the priority bits which are output
from the peripheral to the PIE controller. When both RX and TX interrupt requests are made at the same
priority level, the receiver always has higher priority than the transmitter, reducing the possibility of
receiver overrun.
The operation of peripheral interrupts is described in the peripheral interrupt expansion controller section
of the External Peripheral Interface (ePIE) chapter.
• If the RX/BK INT ENA bit (SCICTL2, bit 1) is set, the receiver peripheral interrupt request is asserted
when one of the following events occurs:
– The SCI receives a complete frame and transfers the data in the RXSHF register to the SCIRXBUF
register. This action sets the RXRDY flag (SCIRXST, bit 6) and initiates an interrupt.
– A break detect condition occurs (the SCIRXD is low for ten bit periods following a missing stop bit).
This action sets the BRKDT flag bit (SCIRXST, bit 5) and initiates an interrupt.
• If the TX INT ENA bit (SCICTL2.0) is set, the transmitter peripheral interrupt request is asserted
whenever the data in the SCITXBUF register is transferred to the TXSHF register, indicating that the
CPU can write to SCITXBUF; this action sets the TXRDY flag bit (SCICTL2, bit 7) and initiates an
interrupt.
NOTE: Interrupt generation due to the RXRDY and BRKDT bits is controlled by the RX/BK INT ENA
bit (SCICTL2, bit 1). Interrupt generation due to the RX ERROR bit is controlled by the RX
ERR INT ENA bit (SCICTL1, bit 6).

19.12 SCI Baud Rate Calculations
The internally generated serial clock is determined by the low-speed peripheral clock LSPCLK) and the
baud-select registers. The SCI uses the 16-bit value of the baud-select registers to select one of the 64K
different serial clock rates possible for a given LSPCLK.
See the SCIHBAUD register for the formula to use when calculating the SCI asynchronous baud rate.
Table 19-3 shows the baud-select values for common SCI bit rates.
Table 19-3. Asynchronous Baud Register Values for Common SCI Bit Rates
LSPCLK (MHz)

Ideal Baud

BRR

Actual Baud

% Error

50

2400

2603 (A2Bh)

2400.15

0.01

50

4800

1301(515h)

4800.31

0.01

50

9600

650 (28Ah)

9600.61

0.01

50

19200

325 (145h)

19171.78

-0.15

2174Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

SCI Enhanced Features

www.ti.com

Table 19-3. Asynchronous Baud Register Values for Common SCI Bit Rates (continued)
LSPCLK (MHz)

Ideal Baud

BRR

Actual Baud

% Error

50

38400

162 (A2h)

38343.56

-0.15

LSPCLK/16 is the maximum baud rate. For example, if LSPCLK is 120MHz, then the maximum baud rate
is 7.5Mbps.

19.13 SCI Enhanced Features
The 28x SCI features autobaud detection and transmit/receive FIFO. The following section explains the
FIFO operation.

19.13.1 SCI FIFO Description
The following steps explain the FIFO features and help with programming the SCI with FIFOs.
1. Reset. At reset the SCI powers up in standard SCI mode and the FIFO function is disabled. The FIFO
registers SCIFFTX, SCIFFRX, and SCIFFCT remain inactive.
2. Standard SCI. The SCI uses the TXINT/RXINT interrupts as the interrupt source for the module.
3. FIFO enable. FIFO mode is enabled by setting the SCIFFEN bit in the SCIFFTX register. SCIRST can
reset the FIFO mode at any stage of its operation.
4. Active registers. All the SCI registers and SCI FIFO registers (SCIFFTX, SCIFFRX, and SCIFFCT) are
active.
5. Interrupts. FIFO mode has two interrupts; one for transmit FIFO, TXINT and one for receive FIFO,
RXINT. RXINT is the common interrupt for SCI FIFO receive, receive error, and receive FIFO overflow
conditions. The TXINT of the standard SCI will be disabled and this interrupt will service as SCI
transmit FIFO interrupt.
6. Buffers. Transmit and receive buffers are supplemented with two 16-level FIFOs. The transmit FIFO
registers are 8 bits wide and receive FIFO registers are 10 bits wide. The one-word transmit buffer of
the standard SCI functions as a transition buffer between the transmit FIFO and shift register. The oneword transmit buffer is loaded from the transmit FIFO only after the last bit of the shift register is shifted
out. With the FIFO enabled, TXSHF is directly loaded after an optional delay value (SCIFFCT), TXBUF
is not used. When FIFO mode is enabled for SCI, characters written to SCITXBUF are queued in to
SCI-TXFIFO and the characters received in SCI-RXFIFO can be read using SCIRXBUF.
7. Delayed transfer. The rate at which words in the FIFO are transferred to the transmit shift register is
programmable. The SCIFFCT register bits (7−0) FFTXDLY7−FFTXDLY0 define the delay between the
word transfer. The delay is defined in the number SCI baud clock cycles. The 8 bit register can define
a minimum delay of 0 baud clock cycles and a maximum of 256-baud clock cycles. With zero delay,
the SCI module can transmit data in continuous mode with the FIFO words shifting out back to back.
With the 256 clock delay the SCI module can transmit data in a maximum delayed mode with the FIFO
words shifting out with a delay of 256 baud clocks between each words. The programmable delay
facilitates communication with slow SCI/UARTs with little CPU intervention.
8. FIFO status bits. Both the transmit and receive FIFOs have status bits TXFFST or RXFFST (bits 12−8)
that define the number of words available in the FIFOs at any time. The transmit FIFO reset bit
TXFIFO and receive reset bit RXFIFO reset the FIFO pointers to zero when these bits are cleared to 0.
The FIFOs resumes operation from start once these bits are set to one.
9. Programmable interrupt levels. Both transmit and receive FIFO can generate CPU interrupts. The
interrupt trigger is generated whenever the transmit FIFO status bits TXFFST (bits 12−8) match (less
than or equal to) the interrupt trigger level bits TXFFIL (bits 4−0 ). This provides a programmable
interrupt trigger for transmit and receive sections of the SCI. Default value for these trigger level bits
will be 0x11111 for receive FIFO and 0x00000 for transmit FIFO, respectively.
Figure 19-10 and Table 19-4 explain the operation/configuration of SCI interrupts in nonFIFO/FFO mode.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2175

SCI Enhanced Features

www.ti.com

Figure 19-10. SCI FIFO Interrupt Flags and Enable Logic
16x8 bit FIFO
RX FIFO 15
RXFFIENA
RXFFOVF flag
RXFFIL
1 SCIFFENA

RX FIFO 0
RXERRINTENA
RX BUF

RXERR flag

RXSHF

RXRDY/BRKDT

RXINT
0

RX
RX/BKINTENA
TXSHF
TX

TXRDY flag
TX BUF

TXINTENA

0 SCIFFENA
TXINT

TX FIFO 0

1
TXFFIENA
TXFFIL

TX FIFO 15

Auto-baud
detect logic

ABD bit
CDC bit

Table 19-4. SCI Interrupt Flags
FIFO Options (1)

SCI Interrupt Source

SCI without FIFO

Receive error

SCI with FIFO

Auto-baud
(1)
(2)

Interrupt Flags
RXERR

(2)

Interrupt Enables

FIFO Enable
SCIFFENA

Interrupt Line

RXERRINTENA

0

RXINT

Receive break

BRKDT

RX/BKINTENA

0

RXINT

Data receive

RXRDY

RX/BKINTENA

0

RXINT

Transmit empty

TXRDY

TXINTENA

0

TXINT

Receive error and
receive break

RXERR

RXERRINTENA

1

RXINT

FIFO receive

RXFFIL

RXFFIENA

1

RXINT

Transmit empty

TXFFIL

TXFFIENA

1

TXINT

ABD

Don’t care

x

TXINT

Auto-baud detected

FIFO mode TXSHF is directly loaded after delay value, TXBUF is not used.
RXERR can be set by BRKDT, FE, OE, PE flags. In FIFO mode, BRKDT interrupt is only through RXERR flag

19.13.2 SCI Auto-Baud
Most SCI modules do not have an auto-baud detect logic built-in hardware. These SCI modules are
integrated with embedded controllers whose clock rates are dependent on PLL reset values. Often
embedded controller clocks change after final design. In the enhanced feature set this module supports an
autobaud-detect logic in hardware. The following section explains the enabling sequence for autobauddetect feature.

2176

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

SCI Enhanced Features

www.ti.com

19.13.3 Autobaud-Detect Sequence
Bits ABD and CDC in SCIFFCT control the autobaud logic. The SCIRST bit should be enabled to make
autobaud logic work.
If ABD is set while CDC is 1, which indicates auto-baud alignment, SCI transmit FIFO interrupt will occur
(TXINT). After the interrupt service CDC bit has to be cleared by software. If CDC remains set even after
interrupt service, there should be no repeat interrupts.
1. Enable autobaud-detect mode for the SCI by setting the CDC bit (bit 13) in SCIFFCT and clearing the
ABD bit (Bit 15) by writing a 1 to ABDCLR bit (bit 14).
2. Initialize the baud register to be 1 or less than a baud rate limit of 500 Kbps.
3. Allow SCI to receive either character "A" or "a" from a host at the desired baud rate. If the first
character is either "A" or "a", the autobaud- detect hardware will detect the incoming baud rate and set
the ABD bit.
4. The auto-detect hardware will update the baud rate register with the equivalent baud value hex. The
logic will also generate an interrupt to the CPU.
5. Respond to the interrupt clear ADB bit by writing a 1 to ABD CLR (bit 14) of SCIFFCT register and
disable further autobaud locking by clearing CDC bit by writing a 0.
6. Read the receive buffer for character "A" or "a" to empty the buffer and buffer status.
7. If ABD is set while CDC is 1, which indicates autobaud alignment, the SCI transmit FIFO interrupt will
occur (TXINT). After the interrupt service CDC bit must be cleared by software.
NOTE: At higher baud rates, the slew rate of the incoming data bits can be affected by transceiver
and connector performance. While normal serial communications may work well, this slew
rate may limit reliable autobaud detection at higher baud rates (typically beyond 100k baud)
and cause the auto-baudlock feature to fail.
To avoid this, the following is recommended:

•
•

Achieve a baud-lock between the host and 28x SCI boot loader using a lower
baud rate.
The host may then handshake with the loaded 28x application to set the SCI
baud rate register to the desired higher baud rate.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2177

Registers

www.ti.com

19.14 Registers
19.14.1 SCI Base Addresses
Table 19-5. SCI Base Address Table
Device Registers

2178

Register Name

Start Address

End Address

SciaRegs

SCI_REGS

0x0000_7200

0x0000_720F

ScibRegs

SCI_REGS

0x0000_7210

0x0000_721F

ScicRegs

SCI_REGS

0x0000_7220

0x0000_722F

ScidRegs

SCI_REGS

0x0000_7230

0x0000_723F

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

19.14.2 SCI_REGS Registers
Table 19-6 lists the memory-mapped registers for the SCI_REGS. All register offset addresses not listed
in Table 19-6 should be considered as reserved locations and the register contents should not be
modified.
Table 19-6. SCI_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

SCICCR

Communications control register

Go

1h

SCICTL1

Control register 1

Go

2h

SCIHBAUD

Baud rate (high) register

Go

3h

SCILBAUD

Baud rate (low) register

Go

4h

SCICTL2

Control register 2

Go

5h

SCIRXST

Recieve status register

Go

6h

SCIRXEMU

Recieve emulation buffer register

Go

7h

SCIRXBUF

Recieve data buffer

Go

9h

SCITXBUF

Transmit data buffer

Go

Ah

SCIFFTX

FIFO transmit register

Go

Bh

SCIFFRX

FIFO recieve register

Go

Ch

SCIFFCT

FIFO control register

Go

Fh

SCIPRI

SCI Priority control

Go

Complex bit access types are encoded to fit into small table cells. Table 19-7 shows the codes that are
used for access types in this section.
Table 19-7. SCI_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2179

Registers

www.ti.com

19.14.2.1 SCICCR Register (Offset = 0h) [reset = 0h]
SCICCR is shown in Figure 19-11 and described in Table 19-8.
Return to Summary Table.
Communications control register
Figure 19-11. SCICCR Register
15

14

13

12

11

10

9

8

3
ADDRIDLE_M
ODE
R/W-0h

2

1
SCICHAR

0

RESERVED
R-0h
7
STOPBITS

6
PARITY

5
PARITYENA

4
LOOPBKENA

R/W-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

Table 19-8. SCICCR Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7

STOPBITS

R/W

0h

SCI number of stop bits.
This bit specifies the number of stop bits transmitted. The receiver
checks for only one stop bit.
Reset type: SYSRSn
0h (R/W) = One stop bit
1h (R/W) = Two stop bits

6

PARITY

R/W

0h

SCI parity odd/even selection.
If the PARITY ENABLE bit (SCICCR, bit 5) is set, PARITY (bit 6)
designates odd or even parity (odd or even number of bits with the
value of 1 in both transmitted and received characters).
Reset type: SYSRSn
0h (R/W) = Odd parity
1h (R/W) = Even parity

5

PARITYENA

R/W

0h

SCI parity enable.
This bit enables or disables the parity function. If the SCI is in the
addressbit multiprocessor mode (set using bit 3 of this register), the
address bit is included in the parity calculation (if parity is enabled).
For characters of less than eight bits, the remaining unused bits
should be masked out of the parity calculation.
Reset type: SYSRSn
0h (R/W) = Parity disabled
no parity bit is generated during transmission or is expected during
reception
1h (R/W) = Parity is enabled

4

LOOPBKENA

R/W

0h

Loop Back test mode enable.
This bit enables the Loop Back test mode where the Tx pin is
internally connected to the Rx pin.
Reset type: SYSRSn
0h (R/W) = Loop Back test mode disabled
1h (R/W) = Loop Back test mode enabled

2180

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 19-8. SCICCR Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

ADDRIDLE_MODE

R/W

0h

SCI multiprocessor mode control bit.
This bit selects one of the multiprocessor protocols.Multiprocessor
communication is different from the other communication modes
because it uses SLEEP and TXWAKE functions (bits SCICTL1, bit 2
and SCICTL1, bit 3, respectively). The idle-line mode is usually used
for normal communications because the address-bit mode
adds an extra bit to the frame. The idle-line mode does not add this
extra bit and is compatible with RS-232 type communications.
Reset type: SYSRSn
0h (R/W) = Idle-line mode protocol selected
1h (R/W) = Address-bit mode protocol selected

2-0

SCICHAR

R/W

0h

Character-length control bits 2-0.
These bits select the SCI character length from one to eight bits.
Characters of less than eight bits are right-justified in SCIRXBUF
and SCIRXEMU and are padded with leading zeros in SCIRXBUF.
SCITXBUF doesn't need to be padded with leading zeros.
Reset type: SYSRSn
0h (R/W) = SCICHAR_LEGNTH_1
1h (R/W) = SCICHAR_LEGNTH_2
2h (R/W) = SCICHAR_LEGNTH_3
3h (R/W) = SCICHAR_LEGNTH_4
4h (R/W) = SCICHAR_LEGNTH_5
5h (R/W) = SCICHAR_LEGNTH_6
6h (R/W) = SCICHAR_LEGNTH_7
7h (R/W) = SCICHAR_LEGNTH_8

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2181

Registers

www.ti.com

19.14.2.2 SCICTL1 Register (Offset = 1h) [reset = 0h]
SCICTL1 is shown in Figure 19-12 and described in Table 19-9.
Return to Summary Table.
Control register 1
Figure 19-12. SCICTL1 Register
15

14

13

12

11

10

9

8

RESERVED
R-0h
7
RESERVED
R-0h

6
RXERRINTEN
A
R/W-0h

5
SWRESET

4
RESERVED

3
TXWAKE

2
SLEEP

1
TXENA

0
RXENA

R/W-0h

R-0h

R/W-0h

R/W-0h

R/W-0h

R/W-0h

Table 19-9. SCICTL1 Register Field Descriptions
Bit
15-7
6

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

RXERRINTENA

R/W

0h

SCI receive error interrupt enable.
Setting this bit enables an interrupt if the RX ERROR bit (SCIRXST,
bit 7) becomes set because of errors occurring.
Reset type: SYSRSn
0h (R/W) = Receive error interrupt disabled
1h (R/W) = Receive error interrupt enabled

5

SWRESET

R/W

0h

SCI software reset (active low).
Writing a 0 to this bit initializes the SCI state machines and operating
flags (registers SCICTL2 and SCIRXST) to the reset condition. The
SW RESET bit does not affect any of the configuration bits.
All affected logic is held in the specified reset state until a 1 is written
to SW RESET (the bit values following a reset are shown beneath
each register diagram in this section). Thus, after a system reset, reenable the SCI by writing a 1 to this bit. Clear this bit after a receiver
break detect (BRKDT flag, bit SCIRXST, bit 5).
SW RESET affects the operating flags of the SCI, but it neither
affects the configuration bits nor restores the reset values. Once SW
RESET is asserted, the flags are frozen until the bit is deasserted.
The affected flags are as follows:
Value After SW SCI Flag Register Bit
RESET
1 TXRDY SCICTL2, bit 7
1 TX EMPTY SCICTL2, bit 6
0 RXWAKE SCIRXST, bit 1
0 PE SCIRXST, bit 2
0 OE SCIRXST, bit 3
0 FE SCIRXST, bit 4
0 BRKDT SCIRXST, bit 5
0 RXRDY SCIRXST, bit 6
0 RX ERROR SCIRXST, bit 7
Reset type: SYSRSn
0h (R/W) = Writing a 0 to this bit initializes the SCI state machines
and operating flags (registers SCICTL2 and SCIRXST) to the reset
condition.
1h (R/W) = After a system reset, re-enable the SCI by writing a 1 to
this bit.

4
2182

RESERVED

R

0h

Serial Communications Interface (SCI)

Reserved
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 19-9. SCICTL1 Register Field Descriptions (continued)
Bit
3

Field

Type

Reset

Description

TXWAKE

R/W

0h

SCI transmitter wake-up method select.
The TXWAKE bit controls selection of the data-transmit feature,
depending on which transmit mode (idle-line or address-bit) is
specified at the ADDR/IDLE MODE bit (SCICCR, bit 3)
Reset type: SYSRSn
0h (R/W) = Transmit feature is not selected. In idle-line mode: write a
1 to TXWAKE, then write data to register SCITXBUF to generate an
idle period of 11 data bits In address-bit mode: write a 1 to
TXWAKE, then write data to SCITXBUF to set the address bit for
that frame to 1
1h (R/W) = Transmit feature selected is dependent on the mode,
idle-line or address-bit: TXWAKE is not cleared by the SW RESET
bit (SCICTL1, bit 5)
it is cleared by a system reset or the transfer of TXWAKE to the
WUT flag.

2

SLEEP

R/W

0h

SCI sleep.
The TXWAKE bit controls selection of the data-transmit feature,
depending on which transmit mode (idle-line or address-bit) is
specified at the ADDR/IDLE MODE bit (SCICCR, bit 3). In a
multiprocessor configuration, this bit controls the receiver sleep
function. Clearing this bit brings the SCI out of the sleep mode.
The receiver still operates when the SLEEP bit is set
however, operation does not update the receiver buffer ready bit
(SCIRXST, bit 6, RXRDY) or the error status bits (SCIRXST, bit 5-2:
BRKDT, FE, OE, and PE) unless the address byte is detected.
SLEEP is not cleared when the address byte is detected.
Reset type: SYSRSn
0h (R/W) = Sleep mode disabled
1h (R/W) = Sleep mode enabled

1

TXENA

R/W

0h

SCI transmitter enable.
Data is transmitted through the SCITXD pin only when TXENA is
set. If reset, transmission is halted but only after all data previously
written to SCITXBUF has been sent. Data written into SCITXBUF
when TXENA is disabled will not be transmitted even if the TXENA is
enabled later.
Reset type: SYSRSn
0h (R/W) = Transmitter disabled
1h (R/W) = Transmitter enabled

0

RXENA

R/W

0h

SCI receiver enable.
Data is received on the SCIRXD pin and is sent to the receiver shift
register and then the receiver buffers. This bit enables or disables
the receiver (transfer to the buffers).
Clearing RXENA stops received characters from being transferred to
the two receiver buffers and also stops the generation of receiver
interrupts. However, the receiver shift register can continue to
assemble characters. Thus, if RXENA is set during the reception of a
character, the complete character will be transferred into the receiver
buffer registers, SCIRXEMU and SCIRXBUF.
Reset type: SYSRSn
0h (R/W) = Prevent received characters from transfer into the
SCIRXEMU and SCIRXBUF receiver buffers
1h (R/W) = Send received characters to SCIRXEMU and SCIRXBUF

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2183

Registers

www.ti.com

19.14.2.3 SCIHBAUD Register (Offset = 2h) [reset = 0h]
SCIHBAUD is shown in Figure 19-13 and described in Table 19-10.
Return to Summary Table.
Baud rate (high) register
Figure 19-13. SCIHBAUD Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
BAUD
R/W-0h

Table 19-10. SCIHBAUD Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

BAUD

R/W

0h

SCI 16-bit baud selection Registers SCIHBAUD (MSbyte).
The internally-generated serial clock is determined by the low speed
peripheral clock (LSPCLK) signal and the two baud-select registers.
The SCI uses the 16-bit value of these registers to select one of 64K
serial clock rates for the communication modes.
The SCI baud rate is calculated using the following equation:
SCI Asynchronous Baud = LSPCLK / ((BRR + 1) *8)
Alternatively,
BRR = LSPCLK / (SCI Asynchronous Baud * 8) - 1
Note that the above formulas are applicable only when 0 < BRR <
65536. If BRR = 0, then
SCI Asynchronous Baud = LSPCLK / 16
Where: BRR = the 16-bit value (in decimal) in the baud-select
registers
Reset type: SYSRSn

2184

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

19.14.2.4 SCILBAUD Register (Offset = 3h) [reset = 0h]
SCILBAUD is shown in Figure 19-14 and described in Table 19-11.
Return to Summary Table.
Baud rate (low) register
Figure 19-14. SCILBAUD Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
BAUD
R/W-0h

Table 19-11. SCILBAUD Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

BAUD

R/W

0h

See SCIHBAUD Detailed Description
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2185

Registers

www.ti.com

19.14.2.5 SCICTL2 Register (Offset = 4h) [reset = C0h]
SCICTL2 is shown in Figure 19-15 and described in Table 19-12.
Return to Summary Table.
Control register 2
Figure 19-15. SCICTL2 Register
15

14

13

12

11

10

9

8

3

2

1
RXBKINTENA
R/W-0h

0
TXINTENA
R/W-0h

RESERVED
R-0h
7
TXRDY
R-1h

6
TXEMPTY
R-1h

5

4
RESERVED
R-0h

Table 19-12. SCICTL2 Register Field Descriptions
Bit
15-8
7

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

TXRDY

R

1h

Transmitter buffer register ready flag.
When set, this bit indicates that the transmit data buffer register,
SCITXBUF, is ready to receive another character. Writing data to the
SCITXBUF automatically clears this bit. When set, this flag asserts a
transmitter interrupt request if the interrupt-enable bit, TX INT ENA
(SCICTL2.0), is also set. TXRDY is set to 1 by enabling the SW
RESET bit (SCICTL1.5) or by a system reset.
Reset type: SYSRSn
0h (R/W) = SCITXBUF is full
1h (R/W) = SCITXBUF is ready to receive the next character

6

TXEMPTY

R

1h

Transmitter empty flag.
This flag's value indicates the contents of the transmitter's buffer
register (SCITXBUF) and shift register (TXSHF). An active SW
RESET (SCICTL1.5), or a system reset, sets this bit. This bit does
not cause an interrupt request.
Reset type: SYSRSn
0h (R/W) = Transmitter buffer or shift register or both are loaded with
data
1h (R/W) = Transmitter buffer and shift registers are both empty

5-2
1

RESERVED

R

0h

Reserved

RXBKINTENA

R/W

0h

Receiver-buffer/break interrupt enable.
This bit controls the interrupt request caused by either the RXRDY
flag or the BRKDT flag (bits SCIRXST.6 and .5) being set. However,
RX/BK INT ENA does not prevent the setting of these flags.
Reset type: SYSRSn
0h (R/W) = Disable RXRDY/BRKDT interrupt
1h (R/W) = Enable RXRDY/BRKDT interrupt

2186

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 19-12. SCICTL2 Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

TXINTENA

R/W

0h

SCITXBUF-register interrupt enable.
This bit controls the interrupt request caused by the setting of
TXRDY flag bit (SCICTL2.7). However, it does not prevent the
TXRDY flag from being set (which indicates SCITXBUF is ready to
receive another character).
0 Disable TXRDY interrupt
1 Enable TXRDY interrupt.
In non-FIFO mode, a dummy (or a valid) data has to be written to
SCITXBUF for the first transmit interrupt to occur. This is the case
when you enable the transmit interrupt for the first time and also
when you re-enable (disable and then enable) the transmit interrupt.
If TXINTENA is enabled after writing the data to SCITXBUF, it will
not generate an interrupt.
Reset type: SYSRSn
0h (R/W) = Disable TXRDY interrupt
1h (R/W) = Enable TXRDY interrupt

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2187

Registers

www.ti.com

19.14.2.6 SCIRXST Register (Offset = 5h) [reset = 0h]
SCIRXST is shown in Figure 19-16 and described in Table 19-13.
Return to Summary Table.
Recieve status register
Figure 19-16. SCIRXST Register
15

14

13

12

11

10

9

8

3
OE
R-0h

2
PE
R-0h

1
RXWAKE
R-0h

0
RESERVED
R-0h

RESERVED
R-0h
7
RXERROR
R-0h

6
RXRDY
R-0h

5
BRKDT
R-0h

4
FE
R-0h

Table 19-13. SCIRXST Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7

RXERROR

R

0h

SCI receiver error flag.
The RX ERROR flag indicates that one of the error flags in the
receiver status register is set. RX ERROR is a logical OR of the
break detect, framing error, overrun, and parity error enable flags
(bits 5-2: BRKDT, FE, OE, and PE).
A 1 on this bit will cause an interrupt if the RX ERR INT ENA bit
(SCICTL1.6) is set. This bit can be used for fast error-condition
checking during the interrupt service routine. This error flag cannot
be cleared directly
it is cleared by an active SW RESET or by a system reset.
Reset type: SYSRSn
0h (R/W) = No error flags set
1h (R/W) = Error flag(s) set

6

RXRDY

R

0h

SCI receiver-ready flag.
When a new character is ready to be read from the SCIRXBUF
register, the receiver sets this bit, and a receiver interrupt is
generated if the RX/BK INT ENA bit (SCICTL2.1) is a 1. RXRDY is
cleared by a reading of the SCIRXBUF register, by an active SW
RESET, or by a system reset.
Reset type: SYSRSn
0h (R/W) = No new character in SCIRXBUF
1h (R/W) = Character ready to be read from SCIRXBUF

5

BRKDT

R

0h

SCI break-detect flag.
The SCI sets this bit when a break condition occurs. A break
conditionoccurs when the SCI receiver data line (SCIRXD) remains
continuously low for at least ten bits,
beginning after a missing first stop bit. The occurrence of a break
causes a receiver interrupt to be generated if the RX/BK INT ENA bit
is a 1, but it does not cause the receiver buffer to be loaded. A
BRKDT interrupt can occur even if the receiver SLEEP bit is set to 1.
BRKDT is cleared by an active SW RESET or by a system reset. It
is not cleared by receipt of a character after the break is detected. In
order to receive more characters, the SCI must be reset by toggling
the SW RESET bit or by a system reset.
Reset type: SYSRSn
0h (R/W) = No break condition
1h (R/W) = Break condition occurred

2188

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 19-13. SCIRXST Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

FE

R

0h

SCI framing-error flag.
The SCI sets this bit when an expected stop bit is not found. Only
the first stop bit is checked. The missing stop bit indicates that
synchronization with the start bit has been lost and that the character
is incorrectly framed. The FE bit is reset by a clearing of the SW
RESET bit or by a system reset.
Reset type: SYSRSn
0h (R/W) = No framing error detected
1h (R/W) = Framing error detected

3

OE

R

0h

SCI overrun-error flag.
The SCI sets this bit when a character is transferred into registers
SCIRXEMU and SCIRXBUF before the previous character is fully
read by the CPU or DMAC. The previous character is overwritten
and lost. The OE flag bit is reset by an active SW RESET or by a
system reset.
Reset type: SYSRSn
0h (R/W) = No overrun error detected
1h (R/W) = Overrun error detected

2

PE

R

0h

SCI parity-error flag.
This flag bit is set when a character is received with a mismatch
between the number of 1s and its parity bit. The address bit is
included in the calculation. If parity generation and detection is not
enabled, the PE flag is disabled and read as 0. The PE bit is reset
by an active SW RESET or a system reset.
Reset type: SYSRSn
0h (R/W) = No parity error or parity is disabled
1h (R/W) = Parity error is detected

1

RXWAKE

R

0h

Receiver wake-up-detect flag
Reset type: SYSRSn
0h (R/W) = No detection of a receiver wake-up condition
1h (R/W) = A value of 1 in this bit indicates detection of a receiver
wake-up condition. In the address-bit multiprocessor mode
(SCICCR.3 = 1), RXWAKE reflects the value of the address bit for
the character contained in SCIRXBUF. In the idle-line multiprocessor
mode, RXWAKE is set if the SCIRXD data line is detected as idle.
RXWAKE is a read-only flag, cleared by one of the following:
- The transfer of the first byte after the address byte to SCIRXBUF
(only in non-FIFO mode)
- The reading of SCIRXBUF
- An active SW RESET
- A system reset

0

RESERVED

R

0h

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Reserved

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2189

Registers

www.ti.com

19.14.2.7 SCIRXEMU Register (Offset = 6h) [reset = 0h]
SCIRXEMU is shown in Figure 19-17 and described in Table 19-14.
Return to Summary Table.
Recieve emulation buffer register
Figure 19-17. SCIRXEMU Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
ERXDT
R-0h

Table 19-14. SCIRXEMU Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

ERXDT

R

0h

Receive emulation buffer data
Reset type: SYSRSn

2190

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

19.14.2.8 SCIRXBUF Register (Offset = 7h) [reset = 0h]
SCIRXBUF is shown in Figure 19-18 and described in Table 19-15.
Return to Summary Table.
Recieve data buffer
Figure 19-18. SCIRXBUF Register
15
SCIFFFE
R-0h

14
SCIFFPE
R-0h

13

7

6

5

12

11

10

9

8

2

1

0

RESERVED
R-0h
4

3
SAR
R-0h

Table 19-15. SCIRXBUF Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SCIFFFE

R

0h

SCIFFFE. SCI FIFO Framing error flag bit (applicable only if the
FIFO is enabled)
Reset type: SYSRSn
0h (R/W) = No frame error occurred while receiving the character, in
bits 7-0. This bit is associated with the character on the top of the
FIFO.
1h (R/W) = A frame error occurred while receiving the character in
bits 7-0. This bit is associated with the character on the top of the
FIFO.

14

SCIFFPE

R

0h

SCIFFPE. SCI FIFO parity error flag bit (applicable only if the FIFO
is enabled)
Reset type: SYSRSn
0h (R/W) = No parity error occurred while receiving the character, in
bits 7-0. This bit is associated with the character on the top of the
FIFO.
1h (R/W) = A parity error occurred while receiving the character in
bits 7-0. This bit is associated with the character on the top of the
FIFO.

13-8

RESERVED

R

0h

Reserved

7-0

SAR

R

0h

Receive Character bits
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2191

Registers

www.ti.com

19.14.2.9 SCITXBUF Register (Offset = 9h) [reset = 0h]
SCITXBUF is shown in Figure 19-19 and described in Table 19-16.
Return to Summary Table.
Transmit data buffer
Figure 19-19. SCITXBUF Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
TXDT
R/W-0h

Table 19-16. SCITXBUF Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

TXDT

R/W

0h

Transmit data buffer
Reset type: SYSRSn

2192

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

19.14.2.10 SCIFFTX Register (Offset = Ah) [reset = A000h]
SCIFFTX is shown in Figure 19-20 and described in Table 19-17.
Return to Summary Table.
FIFO transmit register
Figure 19-20. SCIFFTX Register
15
SCIRST
R/W-1h

14
SCIFFENA
R/W-0h

13
TXFIFORESET
R/W-1h

12

11

10
TXFFST
R-0h

9

8

7
TXFFINT
R-0h

6
TXFFINTCLR
R=0/W=1-0h

5
TXFFIENA
R/W-0h

4

3

2
TXFFIL
R/W-0h

1

0

Table 19-17. SCIFFTX Register Field Descriptions
Bit

Field

Type

Reset

Description

15

SCIRST

R/W

1h

SCI Reset
0 Write 0 to reset the SCI transmit and receive channels. SCI FIFO
register configuration bits will be left as is.
1 SCI FIFO can resume transmit or receive. SCIRST should be 1
even for Autobaud logic to work.
Reset type: SYSRSn

14

SCIFFENA

R/W

0h

SCI FIFO enable
Reset type: SYSRSn
0h (R/W) = SCI FIFO enhancements are disabled
1h (R/W) = SCI FIFO enhancements are enabled

13

TXFIFORESET

R/W

1h

Transmit FIFO reset
Reset type: SYSRSn
0h (R/W) = Reset the FIFO pointer to zero and hold in reset
1h (R/W) = Re-enable transmit FIFO operation

12-8

TXFFST

R

0h

FIFO status
Reset type: SYSRSn
0h (R/W) = Transmit FIFO is empty
1h (R/W) = Transmit FIFO has 1 words
2h (R/W) = Transmit FIFO has 2 words
3h (R/W) = Transmit FIFO has 3 words
4h (R/W) = Transmit FIFO has 4 words
5h (R/W) = Transmit FIFO has 5 words
6h (R/W) = Transmit FIFO has 6 words
7h (R/W) = Transmit FIFO has 7 words
8h (R/W) = Transmit FIFO has 8 words
9h (R/W) = Transmit FIFO has 9 words
Ah (R/W) = Transmit FIFO has 10 words
Bh (R/W) = Transmit FIFO has 11 words
Ch (R/W) = Transmit FIFO has 12 words
Dh (R/W) = Transmit FIFO has 13 words
Eh (R/W) = Transmit FIFO has 14 words
Fh (R/W) = Transmit FIFO has 15 words
10h (R/W) = Transmit FIFO has 16 words

7

TXFFINT

R

0h

Transmit FIFO interrupt
Reset type: SYSRSn
0h (R/W) = TXFIFO interrupt has not occurred, read-only bit
1h (R/W) = TXFIFO interrupt has occurred, read-only bit

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2193

Registers

www.ti.com

Table 19-17. SCIFFTX Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

TXFFINTCLR

R=0/W=1

0h

Transmit FIFO clear
Reset type: SYSRSn
0h (R/W) = Write 0 has no effect on TXFIFINT flag bit, Bit reads
back a zero
1h (R/W) = Write 1 to clear TXFFINT flag in bit 7

5

TXFFIENA

R/W

0h

Transmit FIFO interrrupt enable
Reset type: SYSRSn
0h (R/W) = TX FIFO interrupt based on TXFFIL match (less than or
equal to) is disabled
1h (R/W) = TX FIFO interrupt based on TXFFIL match (less than or
equal to) is enabled.

TXFFIL

R/W

0h

TXFFIL4-0 Transmit FIFO interrupt level bits.

4-0

The transmit FIFO generates an interrupt whenever the FIFO status
bits (TXFFST4-0) are less than or equal to the FIFO level bits
(TXFFIL4-0). The maximum value that can be assigned to these bits
to generate an interrupt cannot be more than the depth of the TX
FIFO. The default value of these bits after reset is 00000b. Users
should set TXFFIL to best fit their application needs by weighing
between the CPU overhead to service the ISR and the best possible
usage of SCI bus bandwidth.
Reset type: SYSRSn

2194

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

19.14.2.11 SCIFFRX Register (Offset = Bh) [reset = 201Fh]
SCIFFRX is shown in Figure 19-21 and described in Table 19-18.
Return to Summary Table.
FIFO recieve register
Figure 19-21. SCIFFRX Register
15
RXFFOVF
R-0h

14
13
RXFFOVRCLR RXFIFORESET
R=0/W=1-0h
R/W-1h

12

11

10
RXFFST
R-0h

9

8

7
RXFFINT
R-0h

6
RXFFINTCLR
W-0h

4

3

2
RXFFIL
R/W-1Fh

1

0

5
RXFFIENA
R/W-0h

Table 19-18. SCIFFRX Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RXFFOVF

R

0h

Receive FIFO overflow.
This will function as flag, but cannot generate interrupt by itself. This
condition will occur while receive interrupt is active. Receive
interrupts should service this flag condition.
Reset type: SYSRSn
0h (R/W) = Receive FIFO has not overflowed, read-only bit
1h (R/W) = Receive FIFO has overflowed, read-only bit. More than
16 words have been received in to the FIFO, and the first received
word is lost

14

RXFFOVRCLR

R=0/W=1

0h

RXFFOVF clear
Reset type: SYSRSn
0h (R/W) = Write 0 has no effect on RXFFOVF flag bit, Bit reads
back a zero
1h (R/W) = Write 1 to clear RXFFOVF flag in bit 15

13

RXFIFORESET

R/W

1h

Receive FIFO reset
Reset type: SYSRSn
0h (R/W) = Write 0 to reset the FIFO pointer to zero, and hold in
reset.
1h (R/W) = Re-enable receive FIFO operation

RXFFST

R

0h

FIFO status
Reset type: SYSRSn
0h (R/W) = Receive FIFO is empty
1h (R/W) = Receive FIFO has 1 words
2h (R/W) = Receive FIFO has 2 words
3h (R/W) = Receive FIFO has 3 words
4h (R/W) = Receive FIFO has 4 words
5h (R/W) = Receive FIFO has 5 words
6h (R/W) = Receive FIFO has 6 words
7h (R/W) = Receive FIFO has 7 words
8h (R/W) = Receive FIFO has 8 words
9h (R/W) = Receive FIFO has 9 words
Ah (R/W) = Receive FIFO has 10 words
Bh (R/W) = Receive FIFO has 11 words
Ch (R/W) = Receive FIFO has 12 words
Dh (R/W) = Receive FIFO has 13 words
Eh (R/W) = Receive FIFO has 14 words
Fh (R/W) = Receive FIFO has 15 words
10h (R/W) = Receive FIFO has 16 words

12-8

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2195

Registers

www.ti.com

Table 19-18. SCIFFRX Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7

RXFFINT

R

0h

Receive FIFO interrupt
Reset type: SYSRSn
0h (R/W) = RXFIFO interrupt has not occurred, read-only bit
1h (R/W) = RXFIFO interrupt has occurred, read-only bit

6

RXFFINTCLR

W

0h

Receive FIFO interrupt clear
Reset type: SYSRSn
0h (R/W) = Write 0 has no effect on RXFIFINT flag bit. Bit reads
back a zero.
1h (R/W) = Write 1 to clear RXFFINT flag in bit 7

5

RXFFIENA

R/W

0h

Receive FIFO interrupt enable
Reset type: SYSRSn
0h (R/W) = RX FIFO interrupt based on RXFFIL match (greater than
or equal to) will be disabled
1h (R/W) = RX FIFO interrupt based on RXFFIL match (greater than
or equal to) will be enabled

RXFFIL

R/W

1Fh

Receive FIFO interrupt level bits

4-0

The receive FIFO generates an interrupt whenever the FIFO status
bits (RXFFST4-0) are greater than or equal to the FIFO level bits
(RXFFIL4-0). The maximum value that can be assigned to these bits
to generate an interrupt cannot be more than the depth of the RX
FIFO. The default value of these bits after reset is 11111b. Users
should set RXFFIL to best fit their application needs by weighing
between the CPU overhead to service the ISR and the best possible
usage of received SCI data.
Reset type: SYSRSn

2196

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

19.14.2.12 SCIFFCT Register (Offset = Ch) [reset = 0h]
SCIFFCT is shown in Figure 19-22 and described in Table 19-19.
Return to Summary Table.
FIFO control register
Figure 19-22. SCIFFCT Register
15
ABD
R-0h

14
ABDCLR
W-0h

13
CDC
R/W-0h

12

7

6

5

4

11

10
RESERVED
R-0h

9

8

3

2

1

0

FFTXDLY
R/W-0h

Table 19-19. SCIFFCT Register Field Descriptions
Bit

Field

Type

Reset

Description

15

ABD

R

0h

Auto-baud detect (ABD) bit
Reset type: SYSRSn
0h (R/W) = Auto-baud detection is not complete. "A","a" character
has not been received successfully.
1h (R/W) = Auto-baud hardware has detected "A" or "a" character on
the SCI receive register. Auto-detect is

14

ABDCLR

W

0h

ABD-clear bit
Reset type: SYSRSn
0h (R/W) = Write 0 has no effect on ABD flag bit. Bit reads back a
zero.
1h (R/W) = Write 1 to clear ABD flag in bit 15.

13

CDC

R/W

0h

CDC calibrate A-detect bit
Reset type: SYSRSn
0h (R/W) = Disables auto-baud alignment
1h (R/W) = Enables auto-baud alignment

12-8

RESERVED

R

0h

Reserved

7-0

FFTXDLY

R/W

0h

FIFO transfer delay. These bits define the delay between every
transfer from FIFO transmit bufferto transmit shift register. The delay
is defined in the number of SCI serial baud clock cycles. The 8 bit
register could define a minimum delay of 0 baud clock cycles and a
maximum of 256 baud clock cycles

complete.

In FIFO mode, the buffer (TXBUF) between the shift register and the
FIFO should be filled only after the shift register has completed
shifting of the last bit. This is required to pass on the delay between
transfers to the data stream. In FIFO mode, TXBUF should not be
treated as one additional level of buffer. The delayed transmit feature
will help to create an auto-flow scheme without RTS/CTS controls as
in standard UARTS.
When SCI is configured for one stop-bit, delay introduced by
FFTXDLY between one frame and the next frame is equal to number
of baud clock cycles that FFTXDLY is set to.
When SCI is configured for two stop-bits, delay introduced by
FFTXDLY between one frame and the next frame is equal to number
of baud clock cycles that FFTXDLY is set to minus 1.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Serial Communications Interface (SCI)

Copyright © 2013–2017, Texas Instruments Incorporated

2197

Registers

www.ti.com

19.14.2.13 SCIPRI Register (Offset = Fh) [reset = 0h]
SCIPRI is shown in Figure 19-23 and described in Table 19-20.
Return to Summary Table.
SCI Priority control
Figure 19-23. SCIPRI Register
15

14

13

12

11

10

9

8

3

2

1
RESERVED
R-0h

0

RESERVED
R-0h
7

6
RESERVED
R-0h

5

4
FREESOFT
R/W-0h

Table 19-20. SCIPRI Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-5

RESERVED

R

0h

Reserved

4-3

FREESOFT

R/W

0h

These bits determine what occurs when an emulation suspend event
occurs (for example, when the debugger hits a breakpoint). The
peripheral can continue whatever it is doing (free-run mode), or if in
stop mode, it can either stop immediately or stop when the current
operation (the current receive/transmit sequence) is complete.
Reset type: SYSRSn
0h (R/W) = Immediate stop on suspend
1h (R/W) = Complete current receive/transmit sequence before
stopping
2h (R/W) = Free run
3h (R/W) = Free run

2-0

RESERVED

R

0h

Reserved

2198

Serial Communications Interface (SCI)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 20
SPRUHM8G – December 2013 – Revised September 2017

Inter-Integrated Circuit Module (I2C)
This chapter describes the features and operation of the inter-integrated circuit (I2C) module. The I2C
module provides an interface between one of these devices and devices compliant with Philips
Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.
External components attached to this 2-wire serial bus can transmit/receive 1 to 8-bit data to/from the
device through the I2C module. This guide assumes the reader is familiar with the I2C-bus specification.
NOTE: A unit of data transmitted or received by the I2C module can have fewer than 8 bits;
however, for convenience, a unit of data is called a data byte throughout this document. The
number of bits in a data byte is selectable via the BC bits of the mode register, I2CMDR.

Topic

20.1
20.2
20.3
20.4
20.5
20.6

...........................................................................................................................
Introduction to the I2C Module .........................................................................
Configuring Device Pins ..................................................................................
I2C Module Operational Details.........................................................................
Interrupt Requests Generated by the I2C Module ................................................
Resetting or Disabling the I2C Module...............................................................
Registers .......................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Page

2200
2204
2204
2211
2213
2214

Inter-Integrated Circuit Module (I2C)

2199

Introduction to the I2C Module

www.ti.com

20.1 Introduction to the I2C Module
The I2C module supports any slave or master I2C-compatible device. Figure 20-1 shows an example of
multiple I2C modules connected for a two-way transfer from one device to other devices.
Figure 20-1. Multiple I2C Modules Connected
VDD

Pullup
resistors

28x

I2C

I2C

controller

Serial data (SDA)
Serial clock (SCL)

I2C
EPROM

28x
I2C

20.1.1 Features
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
• One 16-byte receive FIFO and one 16-byte transmit FIFO
• One interrupt that can always be used by the CPU. This interrupt can be generated as a result of one
of the following conditions: transmit-data ready, receive-data ready, register-access ready, noacknowledgment received, arbitration lost, stop condition detected, addressed as slave.
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode

20.1.2 Features Not Supported
The I2C module does not support:
• High-speed mode (Hs-mode)
• CBUS-compatibility mode

2200

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Introduction to the I2C Module

www.ti.com

20.1.3 Functional Overview
Each device connected to an I2C-bus is recognized by a unique address. Each device can operate as
either a transmitter or a receiver, depending on the function of the device. A device connected to the I2Cbus can also be considered as the master or the slave when performing data transfers. A master device is
the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer.
During this transfer, any device addressed by this master is considered a slave. The I2C module supports
the multi-master mode, in which one or more devices capable of controlling an I2C-bus can be connected
to the same I2C-bus.
For data communication, the I2C module has a serial data pin (SDA) and a serial clock pin (SCL), as
shown in the Registers section. These two pins carry information between the 28x device and other
devices connected to the I2C-bus. The SDA and SCL pins both are bidirectional. They each must be
connected to a positive supply voltage using a pull-up resistor. When the bus is free, both pins are high.
The driver of these two pins has an open-drain configuration to perform the required wired-AND function.
There are two major transfer techniques: .
• Standard Mode: Send exactly n data values, where n is a value you program in an I2C module
register. See the Register section for more information.
• Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new
START condition. See Registers for RM bit information.
The I2C module consists of the following primary blocks:
• A serial interface: one data pin (SDA) and one clock pin (SCL)
• Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the
SDA pin and the CPU
• Control and status registers
• A peripheral bus interface to enable the CPU to access the I2C module registers and FIFOs.
• A clock synchronizer to synchronize the I2C input clock (from the device clock generator) and the clock
on the SCL pin, and to synchronize data transfers with masters of different clock speeds
• A prescaler to divide down the input clock that is driven to the I2C module
• A noise filter on each of the two pins, SDA and SCL
• An arbitrator to handle arbitration between the I2C module (when it is a master) and another master
• Interrupt generation logic, so that an interrupt can be sent to the CPU
• FIFO interrupt generation logic, so that FIFO access can be synchronized to data reception and data
transmission in the I2C module
Figure 20-2 shows the four registers used for transmission and reception in non-FIFO mode. The CPU
writes data for transmission to I2CDXR and reads received data from I2CDRR. When the I2C module is
configured as a transmitter, data written to I2CDXR is copied to I2CXSR and shifted out on the SDA pin
one bit a time. When the I2C module is configured as a receiver, received data is shifted into I2CRSR and
then copied to I2CDRR.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2201

Introduction to the I2C Module

www.ti.com

Figure 20-2. I2C Module Conceptual Block Diagram
I2C module
I2CXSR

I2CDXR

TX FIFO

FIFO Interrupt
to CPU/PIE

SDA
RX FIFO

Peripheral bus
I2CRSR

SCL

I2CDRR

Clock
synchronizer

Control/status
registers

CPU

Prescaler

Noise filters

Interrupt to
CPU/PIE

I2C INT
Arbitrator

20.1.4 Clock Generation
As shown in Figure 20-3, the device clock generator receives a signal from an external clock source and
produces an I2C input clock with a programmed frequency. The I2C input clock is equivalent to the CPU
clock and is then divided twice more inside the I2C module to produce the module clock and the master
clock.
Figure 20-3. Clocking Diagram for the I2C Module
28x device
I2C module

Device input clock

PLLCR
divider

2

I C input clock
(SYSCLKOUT)

IPSC

ICCL,
ICCH

÷

÷

Master clock
on SCL pin

To I2C-bus

Module clock
for I2C module operation

2202

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Introduction to the I2C Module

www.ti.com

The module clock determines the frequency at which the I2C module operates. A programmable prescaler
in the I2C module divides down the I2C input clock to produce the module clock. To specify the dividedown value, initialize the IPSC field of the prescaler register, I2CPSC. The resulting frequency is:

module clock frequency +

I2C input clock frequency
( IPSC ) 1 )

NOTE: To meet all of the I2C protocol timing specifications, the module clock must be configured
between 7 - 12 MHz.

The prescaler must be initialized only while the I2C module is in the reset state (IRS = 0 in I2CMDR). The
prescaled frequency takes effect only when IRS is changed to 1. Changing the IPSC value while IRS = 1
has no effect.
The master clock appears on the SCL pin when the I2C module is configured to be a master on the I2Cbus. This clock controls the timing of communication between the I2C module and a slave. As shown in
Figure 20-3, a second clock divider in the I2C module divides down the module clock to produce the
master clock. The clock divider uses the ICCL value of I2CCLKL to divide down the low portion of the
module clock signal and uses the ICCH value of I2CCLKH to divide down the high portion of the module
clock signal. See Section 20.1.5 for the master clock frequency equation.

20.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
As explained in Section 20.1.4, when the I2C module is a master, the module clock is divided down for
use as the master clock on the SCL pin. As shown in Figure 20-4, the shape of the master clock depends
on two divide-down values:
• ICCL in I2CCLKL. For each master clock cycle, ICCL determines the amount of time the signal is low.
• ICCH in I2CCKLH. For each master clock cycle, ICCH determines the amount of time the signal is
high.
Figure 20-4. The Roles of the Clock Divide-Down Values (ICCL and ICCH)
High-time duration:
Tmod × (ICCH + d)

High-time duration:
Tmod × (ICCH + d)

SCL

Low-time duration:
Tmod × (ICCL + d)

Low-time duration:
Tmod × (ICCL + d)

20.1.5.1 Formula for the Master Clock Period
The period of the master clock (Tmst) is a multiple of the period of the module clock (Tmod):
T mst + T mod
T mst +

[( ICCL ) d ) ) ( ICCH ) d )]

( IPSC ) 1 ) [ ( ICCL ) d ) ) ( ICCH ) d ) ]
I2C input clock frequency

where d depends on the divide-down value IPSC, as shown in Table 20-1. IPSC is described in the
I2CPSC register.
Table 20-1. Dependency of Delay d on the Divide-Down
Value IPSC
IPSC

d

0

7

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2203

Configuring Device Pins

www.ti.com

Table 20-1. Dependency of Delay d on the Divide-Down
Value IPSC (continued)
IPSC

d

1

6

Greater than 1

5

20.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.

20.3 I2C Module Operational Details
This section provides an overview of the I2C-bus protocol and how it is implemented.

20.3.1 Input and Output Voltage Levels
One clock pulse is generated by the master device for each data bit transferred. Due to a variety of
different technology devices that can be connected to the I2C-bus, the levels of logic 0 (low) and logic 1
(high) are not fixed and depend on the associated level of VDD. For details, see the data manual for your
particular device.

20.3.2 Data Validity
The data on SDA must be stable during the high period of the clock (see Figure 20-5). The high or low
state of the data line, SDA, should change only when the clock signal on SCL is low.
Figure 20-5. Bit Transfer on the I2C-Bus
Data line
stable data
SDA

SCL

Change of data
allowed

20.3.3 Operating Modes
The I2C module has four basic operating modes to support data transfers as a master and as a slave.
See Table 20-2 for the names and descriptions of the modes.
If the I2C module is a master, it begins as a master-transmitter and typically transmits an address for a
particular slave. When giving data to the slave, the I2C module must remain a master-transmitter. To
receive data from a slave, the I2C module must be changed to the master-receiver mode.
If the I2C module is a slave, it begins as a slave-receiver and typically sends acknowledgment when it
recognizes its slave address from a master. If the master will be sending data to the I2C module, the
module must remain a slave-receiver. If the master has requested data from the I2C module, the module
must be changed to the slave-transmitter mode.
2204

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

I2C Module Operational Details

www.ti.com

Table 20-2. Operating Modes of the I2C Module
Operating Mode

Description

Slave-receiver modes

The I2C module is a slave and receives data from a master.
All slaves begin in this mode. In this mode, serial data bits received on SDA are shifted in with
the clock pulses that are generated by the master. As a slave, the I2C module does not
generate the clock signal, but it can hold SCL low while the intervention of the device is
required (RSFULL = 1 in I2CSTR) after a byte has been received. See section Section 20.3.7
for more details.

Slave-transmitter mode

The I2C module is a slave and transmits data to a master.
This mode can be entered only from the slave-receiver mode; the I2C module must first receive
a command from the master. When you are using any of the 7-bit/10-bit addressing formats,
the I2C module enters its slave-transmitter mode if the slave address byte is the same as its
own address (in I2COAR) and the master has transmitted R/W = 1. As a slave-transmitter, the
I2C module then shifts the serial data out on SDA with the clock pulses that are generated by
the master. While a slave, the I2C module does not generate the clock signal, but it can hold
SCL low while the intervention of the device is required (XSMT = 0 in I2CSTR) after a byte has
been transmitted. See section Section 20.3.7 for more details.

Master-receiver mode

The I2C module is a master and receives data from a slave.
This mode can be entered only from the master-transmitter mode; the I2C module must first
transmit a command to the slave. When you are using any of the 7-bit/10-bit addressing
formats, the I2C module enters its master-receiver mode after transmitting the slave address
byte and R/W = 1. Serial data bits on SDA are shifted into the I2C module with the clock pulses
generated by the I2C module on SCL. The clock pulses are inhibited and SCL is held low when
the intervention of the device is required (RSFULL = 1 in I2CSTR) after a byte has been
received.

Master-transmitter modes

The IC module is a master and transmits control information and data to a slave.
All masters begin in this mode. In this mode, data assembled in any of the 7-bit/10-bit
addressing formats is shifted out on SDA. The bit shifting is synchronized with the clock pulses
generated by the I2C module on SCL. The clock pulses are inhibited and SCL is held low when
the intervention of the device is required (XSMT = 0 in I2CSTR) after a byte has been
transmitted.

Table 20-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of
I2CMDR

(1)

Bus Activity (1)

Description

0

None

No activity

0

1

P

STOP condition

0

1

0

S-A-D..(n)..D.

START condition, slave address, n data bytes (n = value in
I2CCNT)

0

1

1

S-A-D..(n)..D-P

START condition, slave address, n data bytes, STOP condition (n =
value in I2CCNT)

1

0

0

None

No activity

1

0

1

P

STOP condition

1

1

0

S-A-D-D-D.

Repeat mode transfer: START condition, slave address, continuous
data transfers until STOP condition or next START condition

1

1

1

None

Reserved bit combination (No activity)

RM

STT

STP

0

0

0

S = START condition; A = Address; D = Data byte; P = STOP condition;

20.3.4 I2C Module START and STOP Conditions
START and STOP conditions can be generated by the I2C module when the module is configured to be a
master on the I2C-bus. As shown in Figure 20-6:
• The START condition is defined as a high-to-low transition on the SDA line while SCL is high. A
master drives this condition to indicate the start of a data transfer.
• The STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. A master
drives this condition to indicate the end of a data transfer.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2205

I2C Module Operational Details

www.ti.com

Figure 20-6. I2C Module START and STOP Conditions

SDA

SCL

START
condition (S)

STOP
condition (P)

After a START condition and before a subsequent STOP condition, the I2C-bus is considered busy, and
the bus busy (BB) bit of I2CSTR is 1. Between a STOP condition and the next START condition, the bus
is considered free, and BB is 0.
For the I2C module to start a data transfer with a START condition, the master mode bit (MST) and the
START condition bit (STT) in I2CMDR must both be 1. For the I2C module to end a data transfer with a
STOP condition, the STOP condition bit (STP) must be set to 1. When the BB bit is set to 1 and the STT
bit is set to 1, a repeated START condition is generated. For a description of I2CMDR and its bits
(including MST, STT, and STP), see Registers.

20.3.5 Serial Data Formats
Figure 20-7 shows an example of a data transfer on the I2C-bus. The I2C module supports 1 to 8-bit data
values. In Figure 20-7, 8-bit data is transferred. Each bit put on the SDA line equates to 1 pulse on the
SCL line, and the values are always transferred with the most significant bit (MSB) first. The number of
data values that can be transmitted or received is unrestricted. The serial data format used in Figure 20-7
is the 7-bit addressing format. The I2C module supports the formats shown in Figure 20-8 through
Figure 20-10 and described in the paragraphs that follow the figures.
NOTE: In Figure 20-7 through Figure 20-10, n = the number of data bits (from 1 to 8) specified by
the bit count (BC) field of I2CMDR.

Figure 20-7. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)
Acknowledgement
bit from slave

(No-)Acknowledgement
bit from receiver

SDA
MSB
SCL
1
2
7
START
Slave address
condition (S)

8
9
R/W ACK

1

2

8

9
ACK

Data

STOP
condition (P)

Figure 20-8. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR)
1

S

7

xxxxxxx

1

1

R/W

ACK

n

Data

1

ACK

n

Data

1

1

ACK P

7 bits of slave address

2206

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

I2C Module Operational Details

www.ti.com

Figure 20-9. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR)
1

7

1

1

8

1

S

11110xx

R/W

ACK

xxxxxxxx

ACK

x x = 2 MSBs

n

Data

1

1

ACK P

8 LSBs of slave address

Figure 20-10. I2C Module Free Data Format (FDF = 1 in I2CMDR)
1

n

1

n

1

S

Data

ACK

Data

ACK

n

Data

1

1

ACK P

20.3.5.1 7-Bit Addressing Format
In the 7-bit addressing format (see Figure 20-8), the first byte after a START condition (S) consists of a 7bit slave address followed by a R/W bit. R/W determines the direction of the data:
• R/W = 0: The master writes (transmits) data to the addressed slave.
• R/W = 1: The master reads (receives) data from the slave.
An extra clock cycle dedicated for acknowledgment (ACK) is inserted after each byte. If the ACK bit is
inserted by the slave after the first byte from the master, it is followed by n bits of data from the transmitter
(master or slave, depending on the R/W bit). n is a number from 1 to 8 determined by the bit count (BC)
field of I2CMDR. After the data bits have been transferred, the receiver inserts an ACK bit.
To select the 7-bit addressing format, write 0 to the expanded address enable (XA) bit of I2CMDR, and
make sure the free data format mode is off (FDF = 0 in I2CMDR).
20.3.5.2 10-Bit Addressing Format
The 10-bit addressing format (see Figure 20-9) is similar to the 7-bit addressing format, but the master
sends the slave address in two separate byte transfers. The first byte consists of 11110b, the two MSBs of
the 10-bit slave address, and R/W = 0 (write). The second byte is the remaining 8 bits of the 10-bit slave
address. The slave must send acknowledgment after each of the two byte transfers. Once the master has
written the second byte to the slave, the master can either write data or use a repeated START condition
to change the data direction. For more details about using 10-bit addressing, see the Philips
Semiconductors I2C-bus specification.
To select the 10-bit addressing format, write 1 to the XA bit of I2CMDR and make sure the free data
format mode is off (FDF = 0 in I2CMDR).
20.3.5.3 Free Data Format
In this format (see Figure 20-10), the first byte after a START condition (S) is a data byte. An ACK bit is
inserted after each data byte, which can be from 1 to 8 bits, depending on the BC field of I2CMDR. No
address or data-direction bit is sent. Therefore, the transmitter and the receiver must both support the free
data format, and the direction of the data must be constant throughout the transfer.
To select the free data format, write 1 to the free data format (FDF) bit of I2CMDR. The free data format is
not supported in the digital loopback mode (DLB = 1 in I2CMDR).
Table 20-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR
MST

FDF

I2C Module State

Function of TRX

0

0

In slave mode but not free data
format mode

TRX is a don’t care. Depending on the command from the master, the I2C
module responds as a receiver or a transmitter.

0

1

In slave mode and free data
format mode

The free data format mode requires that the I2C module remains the
transmitter or the receiver throughout the transfer. TRX identifies the role
of the I2C module:
TRX = 1: The I2C module is a transmitter.
TRX = 0: The I2C module is a receiver.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C) 2207

I2C Module Operational Details

www.ti.com

Table 20-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of
I2CMDR (continued)
MST

FDF

I2C Module State

Function of TRX

1

0

In master mode but not free data
format mode

TRX = 1: The I2C module is a transmitter.
TRX = 0: The I2C module is a receiver.

1

1

In master mode and free data
format mode

TRX = 0: The I2C module is a receiver.
TRX = 1: The I2C module is a transmitter.

20.3.5.4 Using a Repeated START Condition
At the end of each data byte, the master can drive another START condition. Using this capability, a
master can communicate with multiple slave addresses without having to give up control of the bus by
driving a STOP condition. The length of a data byte can be from 1 to 8 bits and is selected with the BC
field of I2CMDR. The repeated START condition can be used with the 7-bit addressing, 10-bit addressing,
and free data formats. Figure 20-11 shows a repeated START condition in the 7-bit addressing format.
Figure 20-11. Repeated START Condition (in This Case, 7-Bit Addressing Format)
1

S

1

7

1

Slave address R/W ACK
1

n

1

1

7

Data

ACK

S

Slave address

Any
number

1

1

R/W ACK

1

n

1

1

Data

ACK

P

Any number

NOTE: In Figure 20-11, n = the number of data bits (from 1 to 8) specified by the bit count (BC) field
of I2CMDR.

20.3.6 NACK Bit Generation
When the I2C module is a receiver (master or slave), it can acknowledge or ignore bits sent by the
transmitter. To ignore any new bits, the I2C module must send a no-acknowledge (NACK) bit during the
acknowledge cycle on the bus. Table 20-5 summarizes the various ways you can tell the I2C module to
send a NACK bit.
Table 20-5. Ways to Generate a NACK Bit
I2C Module Condition

2208

NACK Bit Generation Options

Slave-receiver modes

• Allow an overrun condition (RSFULL = 1 in I2CSTR)
• Reset the module (IRS = 0 in I2CMDR)
• Set the NACKMOD bit of I2CMDR before the rising edge of the last data bit you
intend to receive

Master-receiver mode AND
Repeat mode (RM = 1 in I2CMDR)

• Generate a STOP condition (STP = 1 in I2CMDR)
• Reset the module (IRS = 0 in I2CMDR)
• Set the NACKMOD bit of I2CMDR before the rising edge of the last data bit you
intend to receive

Master-receiver mode AND
Nonrepeat mode
(RM = 0 in I2CMDR)

• If STP = 1 in I2CMDR, allow the internal data counter to count down to 0 and thus
force a STOP condition
• If STP = 0, make STP = 1 to generate a STOP condition
• Reset the module (IRS = 0 in I2CMDR). = 1 to generate a STOP condition
• Set the NACKMOD bit of I2CMDR before the rising edge of the last data bit you
intend to receive

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

I2C Module Operational Details

www.ti.com

20.3.7 Clock Synchronization
Under normal conditions, only one master device generates the clock signal, SCL. During the arbitration
procedure, however, there are two or more masters and the clock must be synchronized so that the data
output can be compared. Figure 20-12 illustrates the clock synchronization. The wired-AND property of
SCL means that a device that first generates a low period on SCL overrules the other devices. At this
high-to-low transition, the clock generators of the other devices are forced to start their own low period.
The SCL is held low by the device with the longest low period. The other devices that finish their low
periods must wait for SCL to be released, before starting their high periods. A synchronized signal on SCL
is obtained, where the slowest device determines the length of the low period and the fastest device
determines the length of the high period.
If a device pulls down the clock line for a longer time, the result is that all clock generators must enter the
wait state. In this way, a slave slows down a fast master and the slow device creates enough time to store
a received byte or to prepare a byte to be transmitted.
Figure 20-12. Synchronization of Two I2C Clock Generators During Arbitration
Wait
state

Start HIGH
period

SCL from
device #1

SCL from
device #2

Bus line
SCL

20.3.8 Arbitration
If two or more master-transmitters attempt to start a transmission on the same bus at approximately the
same time, an arbitration procedure is invoked. The arbitration procedure uses the data presented on the
serial data bus (SDA) by the competing transmitters. Figure 20-13 illustrates the arbitration procedure
between two devices. The first master-transmitter that releases the SDA line high is overruled by another
master-transmitter that drives the SDA low. The arbitration procedure gives priority to the device that
transmits the serial data stream with the lowest binary value. Should two or more devices send identical
first bytes, arbitration continues on the subsequent bytes.
If the I2C module is the losing master, it switches to the slave-receiver mode, sets the arbitration lost (AL)
flag, and generates the arbitration-lost interrupt request.
If during a serial transfer the arbitration procedure is still in progress when a repeated START condition or
a STOP condition is transmitted to SDA, the master-transmitters involved must send the repeated START
condition or the STOP condition at the same position in the format frame. Arbitration is not allowed
between:
• A repeated START condition and a data bit
• A STOP condition and a data bit
• A repeated START condition and a STOP condition

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2209

I2C Module Operational Details

www.ti.com

Figure 20-13. Arbitration Procedure Between Two Master-Transmitters
Bus line
SCL
Device #1 loses arbitration
and switches off
Data from
device #1

1

0

Data from
device #2

1

0

0

1

0

1

Bus line
SDA

1

0

0

1

0

1

Device #2 drives SDA

20.3.9 Digital Loopback Mode
The I2C module support a self-test mode called digital loopback, which is enabled by setting the DLB bit in
the I2CMDR register. In this mode, data transmitted out of the I2CDXR register is received in the I2CDRR
register. The data follows an internal path, and takes n cycles to reach I2CDRR, where:
n = 8 * (I2C input clock frequency) / (Module clock frequency)
The transmit clock and the receive clock are the same. The address seen on the external SDA pin is the
address in the I2COAR register. Figure 20-14 shows the signal routing in digital loopback mode.
Figure 20-14. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit
I2C module
DLB

To internal I2C logic

0

SCL_IN

1
From internal I2C logic

SCL
0

SCL_OUT

DLB
To internal

I2C

logic
0

To CPU

I2CDRR

SDA

I2CRSR
1

DLB
From CPU

I2CSAR

0

From CPU

I2COAR

1

From CPU

I2CDXR

0

I2CXSR

Address/data

NOTE: The free data format (I2CMDR.FDF = 1) is not supported in digital loopback mode.

2210

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Interrupt Requests Generated by the I2C Module

www.ti.com

20.4 Interrupt Requests Generated by the I2C Module
The I2C module can generate seven types of basic interrupt requests, which are described in
Section 20.4.1. Two of these can tell the CPU when to write transmit data and when to read receive data.
If you want the FIFOs to handle transmit and receive data, you can also use the FIFO interrupts described
in Section 20.4.2. The basic I2C interrupts are combined to form PIE Group 8, Interrupt 1
(I2CINT1A_ISR), and the FIFO interrupts are combined to form PIE Group 8, Interrupt 2 (I2CINT2A_ISR).

20.4.1 Basic I2C Interrupt Requests
The I2C module generates the interrupt requests described in Table 20-6. As shown in Figure 20-15, all
requests are multiplexed through an arbiter to a single I2C interrupt request to the CPU. Each interrupt
request has a flag bit in the status register (I2CSTR) and an enable bit in the interrupt enable register
(I2CIER). When one of the specified events occurs, its flag bit is set. If the corresponding enable bit is 0,
the interrupt request is blocked. If the enable bit is 1, the request is forwarded to the CPU as an I2C
interrupt.
The I2C interrupt is one of the maskable interrupts of the CPU. As with any maskable interrupt request, if
it is properly enabled in the CPU, the CPU executes the corresponding interrupt service routine
(I2CINT1A_ISR). The I2CINT1A_ISR for the I2C interrupt can determine the interrupt source by reading
the interrupt source register, I2CISRC. Then the I2CINT1A_ISR can branch to the appropriate subroutine.
After the CPU reads I2CISRC, the following events occur:
1. The flag for the source interrupt is cleared in I2CSTR. Exception: The ARDY, RRDY, and XRDY bits in
I2CSTR are not cleared when I2CISRC is read. To clear one of these bits, write a 1 to it.
2. The arbiter determines which of the remaining interrupt requests has the highest priority, writes the
code for that interrupt to I2CISRC, and forwards the interrupt request to the CPU.
Table 20-6. Descriptions of the Basic I2C Interrupt Requests
I2C Interrupt Request

Interrupt Source

XRDYINT

Transmit ready condition: The data transmit register (I2CDXR) is ready to accept new data because the
previous data has been copied from I2CDXR to the transmit shift register (I2CXSR).
As an alternative to using XRDYINT, the CPU can poll the XRDY bit of the status register, I2CSTR.
XRDYINT should not be used when in FIFO mode. Use the FIFO interrupts instead.

RRDYINT

Receive ready condition: The data receive register (I2CDRR) is ready to be read because data has been
copied from the receive shift register (I2CRSR) to I2CDRR.
As an alternative to using RRDYINT, the CPU can poll the RRDY bit of I2CSTR. RRDYINT should not
be used when in FIFO mode. Use the FIFO interrupts instead.

ARDYINT

Register-access ready condition: The I2C module registers are ready to be accessed because the
previously programmed address, data, and command values have been used.
The specific events that generate ARDYINT are the same events that set the ARDY bit of I2CSTR.
As an alternative to using ARDYINT, the CPU can poll the ARDY bit.

NACKINT

No-acknowledgment condition: The I2C module is configured as a master-transmitter and did not
received acknowledgment from the slave-receiver.
As an alternative to using NACKINT, the CPU can poll the NACK bit of I2CSTR.

ALINT

Arbitration-lost condition: The I2C module has lost an arbitration contest with another master-transmitter.
As an alternative to using ALINT, the CPU can poll the AL bit of I2CSTR.

SCDINT

Stop condition detected: A STOP condition was detected on the I2C bus.
As an alternative to using SCDINT, the CPU can poll the SCD bit of the status register, I2CSTR.

AASINT

Addressed as slave condition: The I2C has been addressed as a slave device by another master on the
I2C bus.
As an alternative to using AASINT, the CPU can poll the AAS bit of the status register, I2CSTR.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2211

Interrupt Requests Generated by the I2C Module

www.ti.com

Figure 20-15. Enable Paths of the I2C Interrupt Requests
Flag bits

I2C interrupt requests

Enable bits

I2CSTR(XRDY)

XRDYINT
I2CIER(XRDY)

I2CSTR(RRDY)

RRDYINT
I2CIER(RRDY)

I2CSTR(ARDY)

ARDYINT
I2CIER(ARDY)

I2CSTR(NACK)

Arbiter

NACKINT

I2C interrupt
request to CPU

I2CIER(NACK)
I2CSTR(AL)

ALINT
I2CIER(AL)

I2CSTR(SCD)

SCDINT
I2CIER(SCD)

I2CSTR(AAS)

AASINT
I2CIER(AAS)

20.4.2 I2C FIFO Interrupts
In addition to the seven basic I2C interrupts, the transmit and receive FIFOs each contain the ability to
generate an interrupt (I2CINT2A). The transmit FIFO can be configured to generate an interrupt after
transmitting a defined number of bytes, up to 16 . The receive FIFO can be configured to generate an
interrupt after receiving a defined number of bytes, up to 16. These two interrupt sources are ORed
together into a single maskable CPU interrupt. The interrupt service routine can then read the FIFO
interrupt status flags to determine from which source the interrupt came. See the I2C transmit FIFO
register (I2CFFTX) and the I2C receive FIFO register (I2CFFRX) descriptions.

2212

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Resetting or Disabling the I2C Module

www.ti.com

20.5 Resetting or Disabling the I2C Module
You can reset or disable the I2C module in two ways:
• Write 0 to the I2C reset bit (IRS) in the I2C mode register (I2CMDR). All status bits (in I2CSTR) are
forced to their default values, and the I2C module remains disabled until IRS is changed to 1. The SDA
and SCL pins are in the high-impedance state.
• Initiate a device reset by driving the XRS pin low. The entire device is reset and is held in the reset
state until you drive the pin high. When the XRS pin is released, all I2C module registers are reset to
their default values. The IRS bit is forced to 0, which resets the I2C module. The I2C module stays in
the reset state until you write 1 to IRS.
The IRS must be 0 while you configure or reconfigure the I2C module. Forcing IRS to 0 can be used to
save power and to clear error conditions.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2213

Registers

www.ti.com

20.6 Registers
20.6.1 I2C Base Addresses
Table 20-7. I2C Base Address Table
Device Registers

2214

Register Names

Start Address

End Address

I2caRegs

I2C_REGS

0x0000_7300

0x0000_733F

I2cbRegs

I2C_REGS

0x0000_7340

0x0000_737F

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

20.6.2 I2C_REGS Registers
Table 20-8 lists the memory-mapped registers for the I2C_REGS. All register offset addresses not listed in
Table 20-8 should be considered as reserved locations and the register contents should not be modified.
Table 20-8. I2C_REGS Registers
Offset

Acronym

Register Name

0h

I2COAR

I2C Own address

Write Protection

Section
Go

1h

I2CIER

I2C Interrupt Enable

Go

2h

I2CSTR

I2C Status

Go

3h

I2CCLKL

I2C Clock low-time divider

Go

4h

I2CCLKH

I2C Clock high-time divider

Go

5h

I2CCNT

I2C Data count

Go

6h

I2CDRR

I2C Data receive

Go

7h

I2CSAR

I2C Slave address

Go

8h

I2CDXR

I2C Data Transmit

Go

9h

I2CMDR

I2C Mode

Go

Ah

I2CISRC

I2C Interrupt Source

Go

Bh

I2CEMDR

I2C Extended Mode

Go

Ch

I2CPSC

I2C Prescaler

Go

20h

I2CFFTX

I2C FIFO Transmit

Go

21h

I2CFFRX

I2C FIFO Receive

Go

Complex bit access types are encoded to fit into small table cells. Table 20-9 shows the codes that are
used for access types in this section.
Table 20-9. I2C_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

Write

Read Type
R
Write Type
W

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2215

Registers

www.ti.com

20.6.2.1 I2COAR Register (Offset = 0h) [reset = 0h]
I2COAR is shown in Figure 20-16 and described in Table 20-10.
Return to Summary Table.
I2C Own address
Figure 20-16. I2COAR Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6

5

8
OAR
R/W-0h

4

3

2

1

0

OAR
R/W-0h

Table 20-10. I2COAR Register Field Descriptions
Bit
15-10
9-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

OAR

R/W

0h

In 7-bit addressing mode (XA = 0 in I2CMDR):
00h-7Fh Bits 6-0 provide the 7-bit slave address of the I2C module.
Write 0s to bits 9-7.
In 10-bit addressing mode (XA = 1 in I2CMDR):
000h-3FFh Bits 9-0 provide the 10-bit slave address of the I2C
module.
Reset type: SYSRSn

2216

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

20.6.2.2 I2CIER Register (Offset = 1h) [reset = 0h]
I2CIER is shown in Figure 20-17 and described in Table 20-11.
Return to Summary Table.
I2C Interrupt Enable
Figure 20-17. I2CIER Register
15

14

13

12

11

10

9

8

3
RRDY
R/W-0h

2
ARDY
R/W-0h

1
NACK
R/W-0h

0
ARBL
R/W-0h

RESERVED
R-0h
7
RESERVED
R-0h

6
AAS
R/W-0h

5
SCD
R/W-0h

4
XRDY
R/W-0h

Table 20-11. I2CIER Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

6

AAS

R/W

0h

Addressed as slave interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled

5

SCD

R/W

0h

Stop condition detected interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled

4

XRDY

R/W

0h

Transmit-data-ready interrupt enable bit.

15-7

This bit should not be set when using FIFO mode.
Reset type: SYSRSn
0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled
3

RRDY

R/W

0h

Receive-data-ready interrupt enable bit.
This bit should not be set when using FIFO mode.
Reset type: SYSRSn
0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled

2

ARDY

R/W

0h

Register-access-ready interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled

1

NACK

R/W

0h

No-acknowledgment interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled

0

ARBL

R/W

0h

Arbitration-lost interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt request disabled
1h (R/W) = Interrupt request enabled

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2217

Registers

www.ti.com

20.6.2.3 I2CSTR Register (Offset = 2h) [reset = 0h]
I2CSTR is shown in Figure 20-18 and described in Table 20-12.
Return to Summary Table.
I2C Status
Figure 20-18. I2CSTR Register
15
RESERVED
R-0h

14
SDIR
R/W-0h

13
NACKSNT
R/W-0h

12
BB
R/W-0h

11
RSFULL
R/W-0h

10
XSMT
R/W-0h

9
AAS
R/W-0h

8
AD0
R/W-0h

7

6

5
SCD
R/W-0h

4
XRDY
R/W-0h

3
RRDY
R/W-0h

2
ARDY
R/W-0h

1
NACK
R/W-0h

0
ARBL
R/W-0h

RESERVED
R/W-0h

Table 20-12. I2CSTR Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

SDIR

R/W

0h

Slave direction bit
Reset type: SYSRSn
0h (R/W) = I2C is not addressed as a slave transmitter. SDIR is
cleared by one of the following events:
- It is manually cleared. To clear this bit, write a 1 to it.
- Digital loopback mode is enabled.
- A START or STOP condition occurs on the I2C bus.
1h (R/W) = I2C is addressed as a slave transmitter.

13

NACKSNT

R/W

0h

NACK sent bit.
This bit is used when the I2C module is in the receiver mode. One
instance in which NACKSNT is affected is when the NACK mode is
used (see the description for NACKMOD in
Reset type: SYSRSn
0h (R/W) = NACK not sent. NACKSNT bit is cleared by any one of
the following events:
- It is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset (either when 0 is written to the IRS bit of
I2CMDR or when the whole device is reset).
1h (R/W) = NACK sent: A no-acknowledge bit was sent during the
acknowledge cycle on the I2C-bus.

12

BB

R/W

0h

Bus busy bit.
BB indicates whether the I2C-bus is busy or is free for another data
transfer. See the paragraph following the table for more information
Reset type: SYSRSn
0h (R/W) = Bus free. BB is cleared by any one of the following
events:
- The I2C module receives or transmits a STOP bit (bus free).
- The I2C module is reset.
1h (R/W) = Bus busy: The I2C module has received or transmitted a
START bit on the bus.

2218

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 20-12. I2CSTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

RSFULL

R/W

0h

Receive shift register full bit.
RSFULL indicates an overrun condition during reception. Overrun
occurs when new data is received into the shift register (I2CRSR)
and the old data has not been read from the receive register
(I2CDRR). As new bits arrive from the SDA pin, they overwrite the
bits in I2CRSR. The new data will not be copied to ICDRR until the
previous data is read.
Reset type: SYSRSn
0h (R/W) = No overrun detected. RSFULL is cleared by any one of
the following events:
- I2CDRR is read is read by the CPU. Emulator reads of the I2CDRR
do not affect this bit.
- The I2C module is reset.
1h (R/W) = Overrun detected

10

XSMT

R/W

0h

Transmit shift register empty bit.
XSMT = 0 indicates that the transmitter has experienced
underflow. Underflow occurs when the transmit shift register
(I2CXSR) is empty but the data
transmit register (I2CDXR) has not been loaded since the last
I2CDXR-to-I2CXSR transfer. The
next I2CDXR-to-I2CXSR transfer will not occur until new data is in
I2CDXR. If new data is not
transferred in time, the previous data may be re-transmitted on the
SDA pin.
Reset type: SYSRSn
0h (R/W) = Underflow detected (empty)
1h (R/W) = No underflow detected (not empty). XSMT is set by one
of the following events:
- Data is written to I2CDXR.
- The I2C module is reset

9

AAS

R/W

0h

Addressed-as-slave bit
Reset type: SYSRSn
0h (R/W) = In the 7-bit addressing mode, the AAS bit is cleared
when receiving a NACK, a STOP condition, or a repeated START
condition. In the 10-bit addressing mode, the AAS bit is cleared
when receiving a NACK, a STOP condition, or by a slave address
different from the I2C peripheral's own slave address.
1h (R/W) = The I2C module has recognized its own slave address or
an address of all zeros (general call).

8

AD0

R/W

0h

Address 0 bits
Reset type: SYSRSn
0h (R/W) = AD0 has been cleared by a START or STOP condition.
1h (R/W) = An address of all zeros (general call) is detected.

RESERVED

R/W

0h

Reserved

7-6

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2219

Registers

www.ti.com

Table 20-12. I2CSTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5

SCD

R/W

0h

Stop condition detected bit.
SCD is set when the I2C sends or receives a STOP condition. The
I2C module delays clearing of the I2CMDR[STP] bit until the SCD bit
is set.
Reset type: SYSRSn
0h (R/W) = STOP condition not detected since SCD was last
cleared. SCD is cleared by any one of the following events:
- I2CISRC is read by the CPU when it contains the value 110b (stop
condition detected). Emulator reads of the I2CISRC do not affect this
bit.
- SCD is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset.
1h (R/W) = A STOP condition has been detected on the I2C bus.

4

XRDY

R/W

0h

Transmit-data-ready interrupt flag bit.
When not in FIFO mode, XRDY indicates that the data
transmit register (I2CDXR) is ready to accept new data because the
previous data has been copied from I2CDXR to the transmit shift
register (I2CXSR). The CPU can poll XRDY or use the XRDY
interrupt request When in FIFO mode, use TXFFINT instead.
Reset type: SYSRSn
0h (R/W) = I2CDXR not ready. XRDY is cleared when data is written
to I2CDXR.
1h (R/W) = I2CDXR ready: Data has been copied from I2CDXR to
I2CXSR.
XRDY is also forced to 1 when the I2C module is reset.

3

RRDY

R/W

0h

Receive-data-ready interrupt flag bit.
When not in FIFO mode, RRDY indicates that the data receive
register (I2CDRR) is ready to be read because data has been copied
from the receive shift register
(I2CRSR) to I2CDRR. The CPU can poll RRDY or use the RRDY
interrupt request When in FIFO mode, use RXFFINT instead.
Reset type: SYSRSn
0h (R/W) = I2CDRR not ready. RRDY is cleared by any one of the
following events:
- I2CDRR is read by the CPU. Emulator reads of the I2CDRR do not
affect this bit.
- RRDY is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset.
1h (R/W) = I2CDRR ready: Data has been copied from I2CRSR to
I2CDRR.

2220

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 20-12. I2CSTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2

ARDY

R/W

0h

Register-access-ready interrupt flag bit (only applicable when the I2C
module is in the master
mode).
ARDY indicates that the I2C module registers are ready to be
accessed because the previously programmed address, data, and
command values have been used. The CPU can poll ARDY or use
the ARDY interrupt request
Reset type: SYSRSn
0h (R/W) = The registers are not ready to be accessed. ARDY is
cleared by any one of the following events:
- The I2C module starts using the current register contents.
- ARDY is manually cleared. To clear this bit, write a 1 to it.
- The I2C module is reset.
1h (R/W) = The registers are ready to be accessed.
In the nonrepeat mode (RM = 0 in I2CMDR): If STP = 0 in I2CMDR,
the ARDY bit is set when the internal data counter counts down to 0.
If STP = 1, ARDY is not affected (instead, the I2C module generates
a STOP condition when the counter reaches 0).
In the repeat mode (RM = 1): ARDY is set at the end of each byte
transmitted from I2CDXR.

1

NACK

R/W

0h

No-acknowledgment interrupt flag bit.
NACK applies when the I2C module is a transmitter (master or
slave). NACK indicates whether the I2C module has detected an
acknowledge bit (ACK) or a noacknowledge bit (NACK) from the
receiver. The CPU can poll NACK or use the NACK interrupt request
Reset type: SYSRSn
0h (R/W) = ACK received/NACK not received. This bit is cleared by
any one of the following events:
- An acknowledge bit (ACK) has been sent by the receiver.
- NACK is manually cleared. To clear this bit, write a 1 to it.
- The CPU reads the interrupt source register (I2CISRC) and the
register contains the code for a NACK interrupt. Emulator reads of
the I2CISRC do not affect this bit.
- The I2C module is reset.
1h (R/W) = NACK bit received. The hardware detects that a noacknowledge (NACK) bit has been received.
Note: While the I2C module performs a general call transfer, NACK
is 1, even if one or more slaves send acknowledgment.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2221

Registers

www.ti.com

Table 20-12. I2CSTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

0

ARBL

R/W

0h

Arbitration-lost interrupt flag bit (only applicable when the I2C
module is a master-transmitter).
AL primarily indicates when the I2C module has lost an arbitration
contest with another mastertransmitter. The CPU can poll AL or use
the AL interrupt request
Reset type: SYSRSn
0h (R/W) = Arbitration not lost. AL is cleared by any one of the
following events:
- AL is manually cleared. To clear this bit, write a 1 to it.
- The CPU reads the interrupt source register (I2CISRC) and the
register contains the code for an
AL interrupt. Emulator reads of the I2CISRC do not affect this bit.
- The I2C module is reset.
1h (R/W) = Arbitration lost. AL is set by any one of the following
events:
- The I2C module senses that it has lost an arbitration with two or
more competing transmitters that started a transmission almost
simultaneously.
- The I2C module attempts to start a transfer while the BB (bus busy)
bit is set to 1.
When AL becomes 1, the MST and STP bits of I2CMDR are cleared,
and the I2C module becomes a slave-receiver.

2222

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

20.6.2.4 I2CCLKL Register (Offset = 3h) [reset = 0h]
I2CCLKL is shown in Figure 20-19 and described in Table 20-13.
Return to Summary Table.
I2C Clock low-time divider
Figure 20-19. I2CCLKL Register
15

14

13

12

11

10

9

8
7
I2CCLKL
R/W-0h

6

5

4

3

2

1

0

Table 20-13. I2CCLKL Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

I2CCLKL

R/W

0h

Clock low-time divide-down value.
To produce the low time duration of the master clock, the period of
the module clock is multiplied by (ICCL + d). d is an adjustment
factor based on the prescaler. See the Clock Divider Registers
section of the Introduction for details.
Note: These bits must be set to a non-zero value for proper I2C
clock generation.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2223

Registers

www.ti.com

20.6.2.5 I2CCLKH Register (Offset = 4h) [reset = 0h]
I2CCLKH is shown in Figure 20-20 and described in Table 20-14.
Return to Summary Table.
I2C Clock high-time divider
Figure 20-20. I2CCLKH Register
15

14

13

12

11

10

9

8
7
I2CCLKH
R/W-0h

6

5

4

3

2

1

0

Table 20-14. I2CCLKH Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

I2CCLKH

R/W

0h

Clock high-time divide-down value.
To produce the high time duration of the master clock, the period of
the module clock is multiplied by (ICCL + d). d is an adjustment
factor based on the prescaler. See the Clock Divider Registers
section of the Introduction for details.
Note: These bits must be set to a non-zero value for proper I2C
clock generation.
Reset type: SYSRSn

2224

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

20.6.2.6 I2CCNT Register (Offset = 5h) [reset = 0h]
I2CCNT is shown in Figure 20-21 and described in Table 20-15.
Return to Summary Table.
I2C Data count
Figure 20-21. I2CCNT Register
15

14

13

12

11

10

9

8
7
I2CCNT
R/W-0h

6

5

4

3

2

1

0

Table 20-15. I2CCNT Register Field Descriptions
Bit
15-0

Field

Type

Reset

Description

I2CCNT

R/W

0h

Data count value. ICDC indicates the number of data bytes to
transfer or receive.
The value in I2CCNT is a don't care when the RM bit in I2CMDR is
set to 1.
The start value loaded to the internal data counter is 65536.
The start value loaded to internal data counter is 1-65535.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2225

Registers

www.ti.com

20.6.2.7 I2CDRR Register (Offset = 6h) [reset = 0h]
I2CDRR is shown in Figure 20-22 and described in Table 20-16.
Return to Summary Table.
I2C Data receive
Figure 20-22. I2CDRR Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
DATA
R-0h

Table 20-16. I2CDRR Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

DATA

R

0h

Receive data
Reset type: SYSRSn

2226

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

20.6.2.8 I2CSAR Register (Offset = 7h) [reset = 3FFh]
I2CSAR is shown in Figure 20-23 and described in Table 20-17.
Return to Summary Table.
I2C Slave address
Figure 20-23. I2CSAR Register
15

14

13

12

11

10

9

RESERVED
R-0h
7

6

5

8
SAR
R/W-3FFh

4

3

2

1

0

SAR
R/W-3FFh

Table 20-17. I2CSAR Register Field Descriptions
Bit
15-10
9-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

SAR

R/W

3FFh

In 7-bit addressing mode (XA = 0 in I2CMDR):
00h-7Fh Bits 6-0 provide the 7-bit slave address that the I2C module
transmits when it is in the master-transmitter
mode. Write 0s to bits 9-7.
In 10-bit addressing mode (XA = 1 in I2CMDR):
000h-3FFh Bits 9-0 provide the 10-bit slave address that the I2C
module transmits when it is in the master transmitter mode.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2227

Registers

www.ti.com

20.6.2.9 I2CDXR Register (Offset = 8h) [reset = 0h]
I2CDXR is shown in Figure 20-24 and described in Table 20-18.
Return to Summary Table.
I2C Data Transmit
Figure 20-24. I2CDXR Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
DATA
R/W-0h

Table 20-18. I2CDXR Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

DATA

R/W

0h

Transmit data
Reset type: SYSRSn

2228

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

20.6.2.10 I2CMDR Register (Offset = 9h) [reset = 0h]
I2CMDR is shown in Figure 20-25 and described in Table 20-19.
Return to Summary Table.
I2C Mode
Figure 20-25. I2CMDR Register
15
NACKMOD
R/W-0h

14
FREE
R/W-0h

13
STT
R/W-0h

12
RESERVED
R-0h

11
STP
R/W-0h

10
MST
R/W-0h

9
TRX
R/W-0h

8
XA
R/W-0h

7
RM
R/W-0h

6
DLB
R/W-0h

5
IRS
R/W-0h

4
STB
R/W-0h

3
FDF
R/W-0h

2

1
BC
R/W-0h

0

Table 20-19. I2CMDR Register Field Descriptions
Bit

Field

Type

Reset

Description

15

NACKMOD

R/W

0h

NACK mode bit.
This bit is only applicable when the I2C module is acting as a
receiver.
Reset type: SYSRSn
0h (R/W) = In the slave-receiver mode: The I2C module sends an
acknowledge (ACK) bit to the transmitter during each acknowledge
cycle on the bus. The I2C module only sends a no-acknowledge
(NACK) bit if you set the NACKMOD bit.
In the master-receiver mode: The I2C module sends an ACK bit
during each acknowledge cycle until the internal data counter counts
down to 0. At that point, the I2C module sends a NACK bit to the
transmitter. To have a NACK bit sent earlier, you must set the
NACKMOD bit
1h (R/W) = In either slave-receiver or master-receiver mode: The
I2C module sends a NACK bit to the transmitter during the next
acknowledge cycle on the bus. Once the NACK bit has been sent,
NACKMOD is cleared.
Important: To send a NACK bit in the next acknowledge cycle, you
must set NACKMOD before the rising edge of the last data bit.

14

FREE

R/W

0h

This bit controls the action taken by the I2C module when a
debugger breakpoint is encountered.
Reset type: SYSRSn
0h (R/W) = When I2C module is master:
If SCL is low when the breakpoint occurs, the I2C module stops
immediately and keeps driving SCL low, whether the I2C module is
the transmitter or the receiver. If SCL is high, the I2C module waits
until SCL becomes low and then stops.
When I2C module is slave:
A breakpoint forces the I2C module to stop when the current
transmission/reception is complete.
1h (R/W) = The I2C module runs free
that is, it continues to operate when a breakpoint occurs.

13

STT

R/W

0h

START condition bit (only applicable when the I2C module is a
master). The RM, STT, and STP bits determine when the I2C
module starts and stops data transmissions (see Table 9-6). Note
that the STT and STP bits can be used to terminate the repeat
mode, and that this bit is not writable when IRS = 0.
Reset type: SYSRSn
0h (R/W) = In the master mode, STT is automatically cleared after
the START condition has been generated.
1h (R/W) = In the master mode, setting STT to 1 causes the I2C
module to generate a START condition on the I2C-bus

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2229

Registers

www.ti.com

Table 20-19. I2CMDR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

12

RESERVED

R

0h

Reserved

11

STP

R/W

0h

STOP condition bit (only applicable when the I2C module is a
master).
In the master mode, the RM,STT, and STP bits determine when the
I2C module starts and stops data transmissions.
Note that the STT and STP bits can be used to terminate the repeat
mode, and that this bit is not writable when IRS=0. When in nonrepeat mode, at least one byte must be transferred before a stop
condition can be generated. The I2C module delays clearing of this
bit until after the I2CSTR[SCD] bit is set. To avoid disrupting the I2C
state machine, the user must wait until this bit is clear before
initiating a new message.
Reset type: SYSRSn
0h (R/W) = STP is automatically cleared after the STOP condition
has been generated
1h (R/W) = STP has been set by the device to generate a STOP
condition when the internal data counter of the I2C module counts
down to 0.

10

MST

R/W

0h

Master mode bit.
MST determines whether the I2C module is in the slave mode or the
master mode. MST is automatically changed from 1 to 0 when the
I2C master generates a STOP condition
Reset type: SYSRSn
0h (R/W) = Slave mode. The I2C module is a slave and receives the
serial clock from the master.
1h (R/W) = Master mode. The I2C module is a master and generates
the serial clock on the SCL pin.

9

TRX

R/W

0h

Transmitter mode bit.
When relevant, TRX selects whether the I2C module is in the
transmitter mode or the receiver mode.
Reset type: SYSRSn
0h (R/W) = Receiver mode. The I2C module is a receiver and
receives data on the SDA pin.
1h (R/W) = Transmitter mode. The I2C module is a transmitter and
transmits data on the SDA pin.

8

XA

R/W

0h

Expanded address enable bit.
Reset type: SYSRSn
0h (R/W) = 7-bit addressing mode (normal address mode). The I2C
module transmits 7-bit slave addresses (from bits 6-0 of I2CSAR),
and its own slave address has 7 bits (bits 6-0 of I2COAR).
1h (R/W) = 10-bit addressing mode (expanded address mode). The
I2C module transmits 10-bit slave addresses (from bits 9-0 of
I2CSAR), and its own slave address has 10 bits (bits 9-0 of
I2COAR).

7

RM

R/W

0h

Repeat mode bit (only applicable when the I2C module is a mastertransmitter).
The RM, STT, and STP bits determine when the I2C module starts
and stops data transmissions
Reset type: SYSRSn
0h (R/W) = Nonrepeat mode. The value in the data count register
(I2CCNT) determines how many bytes are
received/transmitted by the I2C module.
1h (R/W) = Repeat mode. A data byte is transmitted each time the
I2CDXR register is written to (or until the transmit FIFO is empty
when in FIFO mode) until the STP bit is manually set. The value of
I2CCNT is ignored. The ARDY bit/interrupt can be used to determine
when the I2CDXR (or FIFO) is ready for more data, or when the data
has all been sent and the CPU is allowed to write to the STP bit.

2230

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 20-19. I2CMDR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6

DLB

R/W

0h

Digital loopback mode bit.
Reset type: SYSRSn
0h (R/W) = Digital loopback mode is disabled.
1h (R/W) = Digital loopback mode is enabled. For proper operation
in this mode, the MST bit must be 1.
In the digital loopback mode, data transmitted out of I2CDXR is
received in I2CDRR after n device cycles by an internal path, where:
n = ((I2C input clock frequency/module clock frequency) x 8)
The transmit clock is also the receive clock. The address transmitted
on the SDA pin is the address in I2COAR.
Note: The free data format (FDF = 1) is not supported in the digital
loopback mode.

5

IRS

R/W

0h

I2C module reset bit.
Reset type: SYSRSn
0h (R/W) = The I2C module is in reset/disabled. When this bit is
cleared to 0, all status bits (in I2CSTR) are set to their default
values.
1h (R/W) = The I2C module is enabled. This has the effect of
releasing the I2C bus if the I2C peripheral is holding it.

4

STB

R/W

0h

START byte mode bit. This bit is only applicable when the I2C
module is a master. As described in version 2.1 of the Philips
Semiconductors I2C-bus specification, the START byte can be used
to help a slave that needs extra time to detect a START condition.
When the I2C module is a slave, it ignores a START byte from a
master, regardless of the value of the STB bit.
Reset type: SYSRSn
0h (R/W) = The I2C module is not in the START byte mode.
1h (R/W) = The I2C module is in the START byte mode. When you
set the START condition bit (STT), the I2C module begins the
transfer with more than just a START condition. Specifically, it
generates:
1. A START condition
2. A START byte (0000 0001b)
3. A dummy acknowledge clock pulse
4. A repeated START condition
Then, as normal, the I2C module sends the slave address that is in
I2CSAR.

3

FDF

R/W

0h

Free data format mode bit.
Reset type: SYSRSn
0h (R/W) = Free data format mode is disabled. Transfers use the 7/10-bit addressing format selected by the XA bit.
1h (R/W) = Free data format mode is enabled. Transfers have the
free data (no address) format described in Section 9.2.5.
The free data format is not supported in the digital loopback mode
(DLB=1).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2231

Registers

www.ti.com

Table 20-19. I2CMDR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

2-0

BC

R/W

0h

Bit count bits.
BC defines the number of bits (1 to 8) in the next data byte that is to
be received or transmitted by the I2C module. The number of bits
selected with BC must match the data size of the other device.
Notice that when BC = 000b, a data byte has 8 bits. BC does not
affect address bytes, which always have 8 bits.
Note: If the bit count is less than 8, receive data is right-justified in
I2CDRR(7-0), and the other bits of I2CDRR(7-0) are undefined. Also,
transmit data written to I2CDXR must be right-justified
Reset type: SYSRSn
0h (R/W) = 8 bits per data byte
1h (R/W) = 1 bit per data byte
2h (R/W) = 2 bits per data byte
3h (R/W) = 3 bits per data byte
4h (R/W) = 4 bits per data byte
5h (R/W) = 5 bits per data byte
6h (R/W) = 6 bits per data byte
7h (R/W) = 7 bits per data byte

2232

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

20.6.2.11 I2CISRC Register (Offset = Ah) [reset = 0h]
I2CISRC is shown in Figure 20-26 and described in Table 20-20.
Return to Summary Table.
I2C Interrupt Source
Figure 20-26. I2CISRC Register
15

14

13

12

11

10
9
WRITE_ZEROS
R/W-0h

8

5
RESERVED
R-0h

4

3

2

0

RESERVED
R-0h
7

6

1
INTCODE
R-0h

Table 20-20. I2CISRC Register Field Descriptions
Field

Type

Reset

Description

15-12

Bit

RESERVED

R

0h

Reserved

11-8

WRITE_ZEROS

R/W

0h

TI internal testing bits
These reserved bit locations should always be written as zeros.
Reset type: SYSRSn

7-3

RESERVED

R

0h

Reserved

2-0

INTCODE

R

0h

Interrupt code bits.
The binary code in INTCODE indicates the event that generated an
I2C interrupt.
A CPU read will clear this field. If another lower priority interrupt is
pending and enabled, the value corresponding to that interrupt will
then be loaded. Otherwise, the value will stay cleared.
In the case of an arbitration lost, a no-acknowledgment condition
detected, or a stop condition detected, a CPU read will also clear the
associated interrupt flag bit in the I2CSTR register.
Emulator reads will not affect the state of this field or of the status
bits in the I2CSTR register.
Reset type: SYSRSn
0h (R/W) = None
1h (R/W) = Arbitration lost
2h (R/W) = No-acknowledgment condition detected
3h (R/W) = Registers ready to be accessed
4h (R/W) = Receive data ready
5h (R/W) = Transmit data ready
6h (R/W) = Stop condition detected
7h (R/W) = Addressed as slave

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2233

Registers

www.ti.com

20.6.2.12 I2CEMDR Register (Offset = Bh) [reset = 0h]
I2CEMDR is shown in Figure 20-27 and described in Table 20-21.
Return to Summary Table.
I2C Extended Mode
Figure 20-27. I2CEMDR Register
15

14

13

12

11

10

9

8

3

2

1

0
BC
R/W-0h

RESERVED
R-0h
7

6

5

4
RESERVED
R-0h

Table 20-21. I2CEMDR Register Field Descriptions
Bit
15-1
0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

BC

R/W

0h

Backwards compatibility mode.
This bit affects the timing of the transmit status bits (XRDY and
XSMT) in the I2CSTR register when in slave transmitter mode.
Reset type: SYSRSn
0h (R/W) = See Figure 9-17 for details.
1h (R/W) = See Figure 9-17 for details.

2234

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

20.6.2.13 I2CPSC Register (Offset = Ch) [reset = 0h]
I2CPSC is shown in Figure 20-28 and described in Table 20-22.
Return to Summary Table.
I2C Prescaler
Figure 20-28. I2CPSC Register
15

14

13

12

11

10

9

8

3

2

1

0

RESERVED
R-0h
7

6

5

4
IPSC
R/W-0h

Table 20-22. I2CPSC Register Field Descriptions
Field

Type

Reset

Description

15-8

Bit

RESERVED

R

0h

Reserved

7-0

IPSC

R/W

0h

I2C prescaler divide-down value.
IPSC determines how much the CPU clock is divided to create the
module clock of the I2C module:
module clock frequency = I2C input clock frequency/(IPSC + 1)
Note: IPSC must be initialized while the I2C module is in reset (IRS
= 0 in I2CMDR).
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2235

Registers

www.ti.com

20.6.2.14 I2CFFTX Register (Offset = 20h) [reset = 0h]
I2CFFTX is shown in Figure 20-29 and described in Table 20-23.
Return to Summary Table.
I2C FIFO Transmit
Figure 20-29. I2CFFTX Register
15
RESERVED
R-0h

14
I2CFFEN
R/W-0h

13
TXFFRST
R/W-0h

12

11

10
TXFFST
R-0h

9

8

7
TXFFINT
R-0h

6
TXFFINTCLR
R/W-0h

5
TXFFIENA
R/W-0h

4

3

2
TXFFIL
R/W-0h

1

0

Table 20-23. I2CFFTX Register Field Descriptions
Bit

Field

Type

Reset

Description

15

RESERVED

R

0h

Reserved

14

I2CFFEN

R/W

0h

I2C FIFO mode enable bit.
This bit must be enabled for either the transmit or the receive FIFO
to operate correctly.
Reset type: SYSRSn
0h (R/W) = Disable the I2C FIFO mode.
1h (R/W) = Enable the I2C FIFO mode.

13

12-8

TXFFRST

R/W

0h

Transmit FIFO Reset
Reset type: SYSRSn
0h (R/W) = Reset the transmit FIFO pointer to 0000 and hold the
transmit FIFO in the reset state.
1h (R/W) = Enable the transmit FIFO operation.

TXFFST

R

0h

Contains the status of the transmit FIFO:
xxxxx Transmit FIFO contains xxxxx bytes.
00000 Transmit FIFO is empty.
Note: Since these bits are reset to zero, the transmit FIFO interrupt
flag will be set when the transmit FIFO operation is enabled and the
I2C is taken out of reset. This will generate a transmit FIFO interrupt
if enabled. To avoid any detrimental effects from this, write a one to
the TXFFINTCLR once the transmit FIFO operation is enabled and
the I2C is taken out of reset.
Reset type: SYSRSn

7

TXFFINT

R

0h

Transmit FIFO interrupt flag.
This bit cleared by a CPU write of a 1 to the TXFFINTCLR bit. If the
TXFFIENA bit is set, this bit will generate an interrupt when it is set.
Reset type: SYSRSn
0h (R/W) = Transmit FIFO interrupt condition has not occurred.
1h (R/W) = Transmit FIFO interrupt condition has occurred.

2236

6

TXFFINTCLR

R/W

0h

Transmit FIFO Interrupt Flag Clear
Reset type: SYSRSn
0h (R/W) = Writes of zeros have no effect. Reads return a 0.
1h (R/W) = Writing a 1 to this bit clears the TXFFINT flag.

5

TXFFIENA

R/W

0h

Transmit FIFO Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disabled. TXFFINT flag does not generate an interrupt
when set.
1h (R/W) = Enabled. TXFFINT flag does generate an interrupt when
set.

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 20-23. I2CFFTX Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-0

TXFFIL

R/W

0h

Transmit FIFO interrupt level.
These bits set the status level that will set the transmit interrupt flag.
When the TXFFST4-0 bits reach a value equal to or less than these
bits, the TXFFINT flag will be set. This will generate an interrupt if
the TXFFIENA bit is set. Because the I2C on these devices has a
16-level transmit FIFO, these bits cannot be configured for an
interrupt of more than 16 FIFO levels.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

2237

Registers

www.ti.com

20.6.2.15 I2CFFRX Register (Offset = 21h) [reset = 0h]
I2CFFRX is shown in Figure 20-30 and described in Table 20-24.
Return to Summary Table.
I2C FIFO Receive
Figure 20-30. I2CFFRX Register
15

14

13
RXFFRST
R/W-0h

12

11

10
RXFFST
R-0h

9

8

6
RXFFINTCLR
R/W-0h

5
RXFFIENA
R/W-0h

4

3

2
RXFFIL
R/W-0h

1

0

RESERVED
R-0h
7
RXFFINT
R-0h

Table 20-24. I2CFFRX Register Field Descriptions
Bit
15-14
13

12-8

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

RXFFRST

R/W

0h

I2C receive FIFO reset bit
Reset type: SYSRSn
0h (R/W) = Reset the receive FIFO pointer to 0000 and hold the
receive FIFO in the reset state.
1h (R/W) = Enable the receive FIFO operation.

RXFFST

R

0h

Contains the status of the receive FIFO:
xxxxx Receive FIFO contains xxxxx bytes
00000 Receive FIFO is empty.
Reset type: SYSRSn

7

RXFFINT

R

0h

Receive FIFO interrupt flag.
This bit cleared by a CPU write of a 1 to the RXFFINTCLR bit. If the
RXFFIENA bit is set, this bit will generate an interrupt when it is set
Reset type: SYSRSn
0h (R/W) = Receive FIFO interrupt condition has not occurred.
1h (R/W) = Receive FIFO interrupt condition has occurred.

6

RXFFINTCLR

R/W

0h

Receive FIFO interrupt flag clear bit.
Reset type: SYSRSn
0h (R/W) = Writes of zeros have no effect. Reads return a zero.
1h (R/W) = Writing a 1 to this bit clears the RXFFINT flag.

5

RXFFIENA

R/W

0h

Receive FIFO interrupt enable bit.
Reset type: SYSRSn
0h (R/W) = Disabled. RXFFINT flag does not generate an interrupt
when set.
1h (R/W) = Enabled. RXFFINT flag does generate an interrupt when
set.

RXFFIL

R/W

0h

Receive FIFO interrupt level.

4-0

These bits set the status level that will set the receive interrupt flag.
When the RXFFST4-0 bits reach a value equal to or greater than
these bits, the RXFFINT flag is set. This will generate an interrupt if
the RXFFIENA bit is set.
Note: Since these bits are reset to zero, the receive FIFO interrupt
flag will be set if the receive FIFO operation is enabled and the I2C
is taken out of reset. This will generate a receive FIFO interrupt if
enabled. To avoid this, modify these bits on the same instruction as
or prior to setting the RXFFRST bit. Because the I2C on these
devices has a 16-level receive FIFO, these bits cannot be configured
for an interrupt of more than 16 FIFO levels.
Reset type: SYSRSn
2238

Inter-Integrated Circuit Module (I2C)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 21
SPRUHM8G – December 2013 – Revised September 2017

Multichannel Buffered Serial Port (McBSP)
This document describes the multichannel buffered serial port (McBSP) of this device.
Topic

...........................................................................................................................

21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
21.12
21.13
21.14

Overview........................................................................................................
Configuring Device Pins ..................................................................................
McBSP Operation............................................................................................
McBSP Sample Rate Generator ........................................................................
McBSP Exception/Error Conditions ...................................................................
Multichannel Selection Modes ..........................................................................
SPI Operation Using the Clock Stop Mode .........................................................
Receiver Configuration ....................................................................................
Transmitter Configuration ................................................................................
Emulation and Reset Considerations ...............................................................
Data Packing Examples ..................................................................................
Interrupt Generation.......................................................................................
McBSP Modes ...............................................................................................
McBSP Registers ..........................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

2240
2242
2242
2252
2259
2267
2274
2281
2300
2316
2319
2321
2323
2325

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

Page

2239

Overview

www.ti.com

21.1 Overview
This device provides up to two high-speed multichannel buffered serial ports (McBSPs) that allow direct
interface to codecs and other devices in a system. The McBSP consists of a data-flow path and a control
path connected to external devices by six pins as shown in Figure 21-1.
Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for
transmission and via the data receive (DR) pin for reception. Control information in the form of clocking
and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive
clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization).
The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible
via the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the
data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX via the transmit shift
registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers
(RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is
then copied to the DRRs, which can be read by the CPU or the DMA controller. This allows simultaneous
movement of internal and external data communications.
DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is 8
bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant
bits.
The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and
FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads;
instead of the CLKR and FSR pins.

21.1.1 Features of the McBSPs
The McBSPs feature:
• Full-duplex communication
• Double-buffered transmission and triple-buffered reception, allowing a continuous data stream
• Independent clocking and framing for reception and transmission
• The capability to send interrupts to the CPU and to send DMA events to the DMA controller
• 128 channels for transmission and reception
• Multichannel selection modes that enable or disable block transfers in each of the channels
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected A/D and D/A devices
• Support for external generation of clock signals and frame-synchronization signals
• A programmable sample rate generator for internal generation and control of clock signals and framesynchronization signals
• Programmable polarity for frame-synchronization pulses and clock signals
• Direct interface to:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame capability is provided)
– I2S compliant devices
– SPI devices
• A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
NOTE: A value of the chosen data size is referred to as a serial word or word throughout the
McBSP documentation. Elsewhere, word is used to describe a 16-bit value.

•
•
•
2240

μ-law and A-law companding
The option of transmitting/receiving 8-bit data with the LSB first
Status bits for flagging exception/error conditions

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Overview

www.ti.com

•

ABIS mode is not supported.

21.1.2 McBSP Pins/Signals
Table 21-1 describes the McBSP interface pins and some internal signals.
Table 21-1. McBSP Interface Pins/Signals
McBSP-A Pin McBSP-B Pin

Type

Description

MCLKRA

MCLKRB

I/O

Supplying or reflecting the receive clock; supplying the input clock of the sample rate
generator

MCLKXA

MCLKXB

I/O

Supplying or reflecting the transmit clock; supplying the input clock of the sample rate
generator

MDRA

MDRB

I

Serial data receive pin

MDXA

MDXB

O

Serial data transmit pin

MFSRA

MFSRB

I/O

Supplying or reflecting the receive frame-sync signal; controlling sample rate generator
synchronization for the case when GSYNC = 1 (see Section 21.4.3)

MFSXA

MFSXB

I/O

Supplying or reflecting the transmit frame-sync signal

CPU Interrupt Signals
MRINT

Receive interrupt to CPU

MXINT

Transmit interrupt to CPU

DMA Events
REVT

Receive synchronization event to DMA

XEVT

Transmit synchronization event to DMA

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2241

Configuring Device Pins

21.1.2.1

www.ti.com

McBSP Generic Block Diagram

The McBSP consists of a data-flow path and a control path connected to external devices by six pins as
shown in Figure 21-1. The figure and the text in this section use generic pin names.
Figure 21-1. Conceptual Block Diagram of the McBSP
TX
Interrupt

MXINT
To CPU

Peripheral Write Bus

CPU

TX Interrupt Logic

16

McBSP Transmit
Interrupt Select Logic

16

DXR2 Transmit Buffer

LSPCLK

DXR1 Transmit Buffer
MFSXx

16

16

MCLKXx

DMA Bus

Bridge

CPU

Peripheral Bus

Compand Logic
XSR2

XSR1

MDXx

RSR2

RSR1

MDRx

16

MCLKRx

16

Expand Logic
MFSRx

RBR2 Register
16

16

DRR2 Receive Buffer

DRR1 Receive Buffer

McBSP Receive
Interrupt Select Logic

MRINT

RX Interrupt Logic

RBR1 Register

16
RX
Interrupt

16

Peripheral Read Bus

CPU

To CPU

A

Not available in all devices. See the device-specific data sheet

21.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.

21.3 McBSP Operation
This section addresses the following topics:
• Data transfer process
• Companding (compressing and expanding) data
• Clocking and framing data
2242

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Operation

www.ti.com

•
•
•
•

Frame phases
McBSP reception
McBSP transmission
Interrupts and DMA events generated by McBSPs

21.3.1 Data Transfer Process of McBSPs
Figure 21-2 shows a diagram of the McBSP data transfer paths. The McBSP receive operation is triplebuffered, and transmit operation is double-buffered. The use of registers varies, depending on whether the
defined length of each serial word is 16 bits.

ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ

ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ

Figure 21-2. McBSP Data Transfer Paths

DR
DX

RSR[1,2]

RBR[1,2]

XSR[1,2]

Compand
Expand
Compress

DRR[1,2]

To CPU/DMA controller

DXR[1,2]

From CPU/DMA controller

21.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits

If the word length is 16 bits or smaller, only one 16-bit register is needed at each stage of the data transfer
paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted).
Receive data arrives on the DR pin and is shifted into receive shift register 1 (RSR1). Once a full word is
received, the content of RSR1 is copied to receive buffer register 1 (RBR1) if RBR1 is not full with
previous data. RBR1 is then copied to data receive register 1 (DRR1), unless the previous content of
DRR1 has not been read by the CPU or the DMA controller. If the companding feature of the McBSP is
implemented, the required word length is 8 bits and receive data is expanded into the appropriate format
before being passed from RBR1 to DRR1. For more details about reception, see Section 21.3.5.
Transmit data is written by the CPU or the DMA controller to data transmit register 1 (DXR1). If there is no
previous data in transmit shift register (XSR1), the value in DXR1 is copied to XSR1; otherwise, DXR1 is
copied to XSR1 when the last bit of the previous data is shifted out on the DX pin. If selected, the
companding module compresses 16-bit data into the appropriate 8-bit format before passing it to XSR1.
After transmit frame synchronization, the transmitter begins shifting bits from XSR1 to the DX pin. For
more details about transmission, see Section 21.3.6.
21.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
If the word length is larger than 16 bits, two 16-bit registers are needed at each stage of the data transfer
paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are needed to hold the most significant bits.
Receive data arrives on the DR pin and is shifted first into RSR2 and then into RSR1. Once the full word
is received, the contents of RSR2 and RSR1 are copied to RBR2 and RBR1, respectively, if RBR1 is not
full. Then the contents of RBR2 and RBR1 are copied to DRR2 and DRR1, respectively, unless the
previous content of DRR1 has not been read by the CPU or the DMA controller. The CPU or the DMA
controller must read data from DRR2 first and then from DRR1. When DRR1 is read, the next RBR-toDRR copy occurs. For more details about reception, see Section 21.3.5.
For transmission, the CPU or the DMA controller must write data to DXR2 first and then to DXR1. When
new data arrives in DXR1, if there is no previous data in XSR1, the contents of DXR2 and DXR1 are
copied to XSR2 and XSR1, respectively; otherwise, the contents of the DXRs are copied to the XSRs
when the last bit of the previous data is shifted out on the DX pin. After transmit frame synchronization,
the transmitter begins shifting bits from the XSRs to the DX pin. For more details about transmission, see
Section 21.3.6.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2243

McBSP Operation

www.ti.com

21.3.2 Companding (Compressing and Expanding) Data
Companding (COMpressing and exPANDing) hardware allows compression and expansion of data in
either μ-law or A-law format. The companding standard employed in the United States and Japan is μ-law.
The European companding standard is referred to as A-law. The specifications for μ-law and A-law log
PCM are part of the CCITT G.711 recommendation.
A-law and μ-law allow 13 bits and 14 bits of dynamic range, respectively. Any values outside this range
are set to the most positive or most negative value. Thus, for companding to work best, the data
transferred to and from the McBSP via the CPU or DMA controller must be at least 16 bits wide.
The μ-law and A-law formats both encode data into 8-bit code words. Companded data is always 8 bits
wide; the appropriate word length bits (RWDLEN1, RWDLEN2, XWDLEN1, XWDLEN2) must therefore be
set to 0, indicating an 8-bit wide serial data stream. If companding is enabled and either of the frame
phases does not have an 8-bit word length, companding continues as if the word length is 8 bits.
Figure 21-3 illustrates the companding processes. When companding is chosen for the transmitter,
compression occurs during the process of copying data from DXR1 to XSR1. The transmit data is
encoded according to the specified companding law (A-law or μ-law). When companding is chosen for the
receiver, expansion occurs during the process of copying data from RBR1 to DRR1. The receive data is
decoded to twos-complement format.
Figure 21-3. Companding Processes
DR

RSR1

DX

RBR1

XSR1

8

16
Expand

8

Compress

16

DRR1

To CPU or DMA controller

DXR1

From CPU or DMA controller

21.3.2.1 Companding Formats
For reception, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1. The
receive sign-extension and justification mode specified in RJUST is ignored when companding is used.
For transmission using μ-law compression, the 14 data bits must be left-justified in DXR1 and that the
remaining two low-order bits are filled with 0s as shown in Figure 21-4.
Figure 21-4. μ-Law Transmit Data Companding Format
15-2
µ-law format in DXR1

1-0

Value

00

For transmission using A-law compression, the 13 data bits must be left-justified in DXR1, with the
remaining three low-order bits filled with 0s as shown in Figure 21-5.
Figure 21-5. A-Law Transmit Data Companding Format

A-law format in DXR1

15-3

2-0

Value

000

21.3.2.2 Capability to Compand Internal Data
If the McBSP is otherwise unused (the serial port transmit and receive sections are reset), the
companding hardware can compand internal data. This can be used to:
• Convert linear to the appropriate μ-law or A-law format
• Convert μ-law or A-law to the linear format
• Observe the quantization effects in companding by transmitting linear data and compressing and reexpanding this data. This is useful only if both XCOMPAND and RCOMPAND enable the same
companding format.
2244

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Operation

www.ti.com

Figure 21-6 shows two methods by which the McBSP can compand internal data. Data paths for these
two methods are used to indicate:
• When both the transmit and receive sections of the serial port are reset, DRR1 and DXR1 are
connected internally through the companding logic. Values from DXR1 are compressed, as selected by
XCOMPAND, and then expanded, as selected by RCOMPAND. RRDY and XRDY bits are not set.
However, data is available in DRR1 within four CPU clocks after being written to DXR1.
The advantage of this method is its speed. The disadvantage is that there is no synchronization
available to the CPU and DMA to control the flow. DRR1 and DXR1 are internally connected if the
(X/R)COMPAND bits are set to 10b or 11b (compand using μ-law or A-law).
• The McBSP is enabled in digital loopback mode with companding appropriately enabled by
RCOMPAND and XCOMPAND. Receive and transmit interrupts (RINT when RINTM = 0 and XINT
when XINTM = 0) or synchronization events (REVT and XEVT) allow synchronization of the CPU or
DMA to these conversions, respectively. Here, the time for this companding depends on the serial bit
rate selected.
Figure 21-6. Two Methods by Which the McBSP Can Compand Internal Data
RSR1

DR

RBR1

Expand

DRR1

To CPU or DMA controller

Compress

DXR1

From CPU or DMA controller

(1)

(2) (DLB)
XSR1

DX

21.3.2.3 Reversing Bit Order: Option to Transfer LSB First
Generally, the McBSP transmits or receives all data with the most significant bit (MSB) first. However,
certain 8-bit data protocols (that do not use companded data) require the least significant bit (LSB) to be
transferred first. If you set XCOMPAND = 01b in XCR2, the bit ordering of 8-bit words is reversed (LSB
first) before being sent from the serial port. If you set RCOMPAND = 01b in RCR2, the bit ordering of 8-bit
words is reversed during reception. Similar to companding, this feature is enabled only if the appropriate
word length bits are set to 0, indicating that 8-bit words are to be transferred serially. If either phase of the
frame does not have an 8-bit word length, the McBSP assumes the word length is eight bits, and LSB-first
ordering is done.

21.3.3 Clocking and Framing Data
This section explains basic concepts and terminology important for understanding how McBSP data
transfers are timed and delimited.
21.3.3.1 Clocking
Data is shifted one bit at a time from the DR pin to the RSR(s) or from the XSR(s) to the DX pin. The time
for each bit transfer is controlled by the rising or falling edge of a clock signal.
The receive clock signal (CLKR) controls bit transfers from the DR pin to the RSR(s). The transmit clock
signal (CLKX) controls bit transfers from the XSR(s) to the DX pin. CLKR or CLKX can be derived from a
pin at the boundary of the McBSP or derived from inside the McBSP. The polarities of CLKR and CLKX
are programmable.
In the example in Figure 21-7, the clock signal controls the timing of each bit transfer on the pin.
Figure 21-7. Example - Clock Signal Control of Bit Transfer Timing
Internal
CLK(R/X)
Internal
FS(R/X)
D(R/X)

A1

ÁÁ
ÁÁ
ÁÁ
A0

Á
Á
Á

B7

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

B6

B5

B4

B3

B2

B1

ÁÁ
ÁÁ
ÁÁ
B0

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2245

McBSP Operation

www.ti.com

NOTE: The McBSP cannot operate at a frequency faster than ½ the LSPCLK frequency. When
driving CLKX or CLKR at the pin, choose an appropriate input clock frequency. When using
the internal sample rate generator for CLKX and/or CLKR, choose an appropriate input clock
frequency and divide down value (CLKDV) (i.e., be certain that CLKX or CLKR ≤ LSPCLK/2).

21.3.3.2 Serial Words
Bits traveling between a shift register (RSR or XSR) and a data pin (DR or DX) are transferred in a group
called a serial word. You can define how many bits are in a word.
Bits coming in on the DR pin are held in RSR until RSR holds a full serial word. Only then is the word
passed to RBR (and ultimately to the DRR).
During transmission, XSR does not accept new data from DXR until a full serial word has been passed
from XSR to the DX pin.
In the exmaple in Figure 21-7, an 8-bit word size was defined (see bits 7 through 0 of word B being
transferred).
21.3.3.3 Frames and Frame Synchronization
One or more words are transferred in a group called a frame. You can define how many words are in a
frame.
All of the words in a frame are sent in a continuous stream. However, there can be pauses between frame
transfers. The McBSP uses frame-synchronization signals to determine when each frame is
received/transmitted. When a pulse occurs on a frame-synchronization signal, the McBSP begins
receiving/transmitting a frame of data. When the next pulse occurs, the McBSP receives/transmits the next
frame, and so on.
Pulses on the receive frame-synchronization (FSR) signal initiate frame transfers on DR. Pulses on the
transmit frame-sync (FSX) signal initiate frame transfers on DX. FSR or FSX can be derived from a pin at
the boundary of the McBSP or derived from inside the McBSP.
In the example in Figure 21-7, a one-word frame is transferred when a frame-synchronization pulse
occurs.
In McBSP operation, the inactive-to-active transition of the frame-synchronization signal indicates the start
of the next frame. For this reason, the frame-synchronization signal may be high for an arbitrary number of
clock cycles. Only after the signal is recognized to have gone inactive, and then active again, does the
next frame synchronization occur.
21.3.3.4 Generating Transmit and Receive Interrupts
The McBSP can send receive and transmit interrupts to the CPU to indicate specific events in the McBSP.
To facilitate detection of frame synchronization, these interrupts can be sent in response to framesynchronization pulses. Set the appropriate interrupt mode bits to 10b (for reception, RINTM = 10b; for
transmission, XINTM = 10b).
21.3.3.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
Unlike other serial port interrupt modes, this mode can operate while the associated portion of the serial
port is in reset (such as activating RINT when the receiver is in reset). In this case, FSRM/FSXM and
FSRP/FSXP still select the appropriate source and polarity of frame synchronization. Thus, even when the
serial port is in the reset state, these signals are synchronized to the CPU clock and then sent to the CPU
in the form of RINT and XINT at the point at which they feed the receiver and transmitter of the serial port.
Consequently, a new frame-synchronization pulse can be detected, and after this occurs the CPU can
take the serial port out of reset safely.

2246

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Operation

www.ti.com

21.3.3.5 Ignoring Frame-Synchronization Pulses
The McBSP can be configured to ignore transmit and/or receive frame-synchronization pulses. To have
the receiver or transmitter recognize frame-synchronization pulses, clear the appropriate framesynchronization ignore bit (RFIG = 0 for the receiver, XFIG = 0 for the transmitter). To have the receiver or
transmitter ignore frame-synchronization pulses until the desired frame length or number of words is
reached, set the appropriate frame-synchronization ignore bit (RFIG = 1 for the receiver, XFIG = 1 for the
transmitter). For more details on unexpected frame-synchronization pulses, see one of the following
topics:
• Unexpected Receive Frame-Synchronization Pulse (see Section 21.5.3)
• Unexpected Transmit Frame-Synchronization Pulse (see Section 21.5.6)
You can also use the frame-synchronization ignore function for data packing (for more details, see
Section 21.11.2).
21.3.3.6 Frame Frequency
The frame frequency is determined by the period between frame-synchronization pulses and is defined as
shown by Example 1.
Example 1: McBSP Frame Frequency
Frame Frequency +

Clock Frequency
Number of Clock Cycles Between Frame- Sync Pulses

The frame frequency can be increased by decreasing the time between frame-synchronization pulses
(limited only by the number of bits per frame). As the frame transmit frequency increases, the inactivity
period between the data packets for adjacent transfers decreases to zero.
21.3.3.7 Maximum Frame Frequency
The minimum number of clock cycles between frame synchronization pulses is equal to the number of bits
transferred per frame. The maximum frame frequency is defined as shown by Example 2.
Example 2: McBSP Maximum Frame Frequency
Maximum Frame Frequency +

Clock Frequency
Number of Bits Per Frame

Figure 21-8 shows the McBSP operating at maximum packet frequency. At maximum packet frequency,
the data bits in consecutive packets are transmitted contiguously with no inactivity between bits.
Figure 21-8. McBSP Operating at Maximum Packet Frequency
CLK(R/X)
FS(R/X)
D(R/X)

A2

A1

A0

B7

B6

B5

B4

B3

B2

B1

B0

C7

C6

If there is a 1-bit data delay as shown in this figure, the frame-synchronization pulse overlaps the last bit
transmitted in the previous frame. Effectively, this permits a continuous stream of data, making framesynchronization pulses redundant. Theoretically, only an initial frame-synchronization pulse is required to
initiate a multipacket transfer.
The McBSP supports operation of the serial port in this fashion by ignoring the successive framesynchronization pulses. Data is clocked into the receiver or clocked out of the transmitter during every
clock cycle.
NOTE: For XDATDLY = 0 (0-bit data delay), the first bit of data is transmitted asynchronously to the
internal transmit clock signal (CLKX). For more details, see Section 21.9.12.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2247

McBSP Operation

www.ti.com

21.3.4 Frame Phases
The McBSP allows you to configure each frame to contain one or two phases. The number of words and
the number of bits per word can be specified differently for each of the two phases of a frame, allowing
greater flexibility in structuring data transfers. For example, you might define a frame as consisting of one
phase containing two words of 16 bits each, followed by a second phase consisting of 10 words of 8 bits
each. This configuration permits you to compose frames for custom applications or, in general, to
maximize the efficiency of data transfers.
21.3.4.1 Number of Phases, Words, and Bits Per Frame
Table 21-2 shows which bit-fields in the receive control registers (RCR1 and RCR2) and in the transmit
control registers (XCR1 and XCR2) determine the number of phases per frame, the number of words per
frame, and number of bits per word for each phase, for the receiver and transmitter. The maximum
number of words per frame is 128 for a single-phase frame and 256 for a dual-phase frame. The number
of bits per word can be 8, 12, 16, 20, 24, or 32 bits.
Table 21-2. Register Bits That Determine the Number of Phases, Words, and Bits
Operation

Number of Phases

Words per Frame Set With

Bits per Word Set With

Reception

1 (RPHASE = 0)

RFRLEN1

RWDLEN1

Reception

2 (RPHASE = 1)

RFRLEN1 and RFRLEN2

RWDLEN1 for phase 1
RWDLEN2 for phase 2

Transmission

1 (XPHASE = 0)

XFRLEN1

XWDLEN1

Transmission

2 (XPHASE = 1)

XFRLEN1 and XFRLEN2

XWDLEN1 for phase 1
XWDLEN2 for phase 2

21.3.4.2 Single-Phase Frame Example
Figure 21-9 shows an example of a single-phase data frame containing one 8-bit word. Because the
transfer is configured for one data bit delay, the data on the DX and DR pins are available one clock cycle
after FS(R/X) goes active. The figure makes the following assumptions:
• (R/X)PHASE = 0: Single-phase frame
• (R/X)FRLEN1 = 0b: 1 word per frame
• (R/X)WDLEN1 = 000b: 8-bit word length
• (R/X)FRLEN2 and (R/X)WDLEN2 are ignored
• CLK(X/R)P = 0: Receive data clocked on falling edge; transmit data clocked on rising edge
• FS(R/X)P = 0: Active-high frame-synchronization signals
• (R/X)DATDLY = 01b: 1-bit data delay
Figure 21-9. Single-Phase Frame for a McBSP Data Transfer
CLK(R/X)
FS(R/X)
D(R/X) A1

Á
Á
Á
Á

A0

Á
Á
Á
Á

21.3.4.3 Dual-Phase Frame Example

Á
Á
Á
Á

B7 B6 B5 B4 B3 B2 B1 B0

Á
Á
Á
Á

C7 C6 C5

Figure 21-10 shows an example of a frame where the first phase consists of two words of 12 bits each,
followed by a second phase of three words of 8 bits each. The entire bit stream in the frame is contiguous.
There are no gaps either between words or between phases.

2248

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Operation

www.ti.com

ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
Á
ÁÁ
ÁÁ
Á
Á
ÁÁ
Á
Á
Á
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
Á
ÁÁ
ÁÁ
ÁÁ
Á
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Figure 21-10. Dual-Phase Frame for a McBSP Data Transfer
Phase 1 Word 1

Phase 1 Word 2

Phase 2

Phase 2

Phase 2

Word 1

Word 2

Word 3

CLK(R/X)

FS(R/X)
D(R/X)
A

XRDY gets asserted once per phase. So, if there are 2 phases, XRDY gets asserted twice (once per phase).

21.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame
Figure 21-11 shows an example of the Audio Codec ‘97 (AC97) standard, which uses the dual-phase
frame feature. Notice that words, not individual bits, are shown on the D(R/X) signal. The first phase (P1)
consists of a single 16-bit word. The second phase (P2) consists of twelve 20-bit words. The phase
configurations are listed after the figure.
Figure 21-11. Implementing the AC97 Standard With a Dual-Phase Frame
P1W1 P2W1

FS(R/X)

P2W2

P2W3

ÁÁ
ÁÁ
ÁÁ
ÁÁ

P2W4

P2W5

P2W6

P2W7

P2W8

P2W9 P2W10 P2W11 P2W12

1-bit data delay
16 bits
20 bits

D(R/X)

•
•
•
•
•
•
•
•

PxWy = Phase x Word y

(R/X)PHASE = 1: Dual-phase frame
(R/X)FRLEN1 = 0000000b: 1 word in phase 1
(R/X)WDLEN1 = 010b: 16 bits per word in phase 1
(R/X)FRLEN2 = 0001011b: 12 words in phase 2
(R/X)WDLEN2 = 011b: 20 bits per word in phase 2
CLKRP/CLKXP= 0: Receive data sampled on falling edge of internal CLKR / transmit data clocked on
rising edge of internal CLKX
FSRP/FSXP = 0: Active-high frame-sync signal
(R/X)DATDLY = 01b: Data delay of 1 clock cycle (1-bit data delay)

Figure 21-12 shows the timing of an AC97-standard data transfer near frame synchronization. In this
figure, individual bits are shown on D(R/X). Specifically, the figure shows the last two bits of phase 2 of
one frame and the first four bits of phase 1 of the next frame. Regardless of the data delay, data transfers
can occur without gaps. The first bit of the second frame (P1W1B15) immediately follows the last bit of the
first frame (P2W12B0). Because a 1-bit data delay has been chosen, the transition on the frame-sync
signal can occur when P2W12B0 is transferred.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2249

McBSP Operation

www.ti.com

Figure 21-12. Timing of an AC97-Standard Data Transfer Near Frame Synchronization
MCLKRA

MFSRA

MDRA

Á
Á
Á
Á

1-bit data delay

P2W12B1

P1W1B14

P1W1B15

P2W12B0

P1W1B12

P1W1B13

PxWyBz = Phase x Word y Bit z

21.3.5 McBSP Reception
This section explains the fundamental process of reception in the McBSP. For details about how to
program the McBSP receiver, see Section 21.8.
Figure 21-13 and Figure 21-14 show how reception occurs in the McBSP. Figure 21-13 shows the
physical path for the data. Figure 21-14 is a timing diagram showing signal activity for one possible
reception scenario. A description of the process follows the figures.

ÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ

ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ

Figure 21-13. McBSP Reception Physical Data Path

RSR[1,2]

DR

A

RBR[1,2]

DRR[1,2]

To CPU or
DMA controller

RSR[1,2]: Receive shift registers 1 and 2

B

RBR[1,2]: Receive buffer registers 1 and 2

C

DRR[1,2]: Data receive registers 1 and 2

CLKR
FSR
DR
RRDY

A1

Á
Á
Á
Á

Figure 21-14. McBSP Reception Signal Activity

A0

Á
Á
Á
Á

B7

B6

RBR1 to DRR1 copy(A)
A

Expand
or
justify and bit fill

B5

B4

B3

B2

Á
Á
Á
Á

B1 B0

Read from DRR1(A) RBR1 to DRR1 copy(B)

Á
Á
Á
Á

C7 C6

C5

Read from DRR1(b)

CLKR: Internal receive clock

B

FSR: Internal receive frame-synchronization signal

C

DR: Data on DR pin

D

RRDY: Status of receiver ready bit (high is 1)

The following process describes how data travels from the DR pin to the CPU or to the DMA controller:
1. The McBSP waits for a receive frame-synchronization pulse on internal FSR.
2. When the pulse arrives, the McBSP inserts the appropriate data delay that is selected with the
RDATDLY bits of RCR2.
In the preceding timing diagram, a 1-bit data delay is selected.
3. The McBSP accepts data bits on the DR pin and shifts them into the receive shift register(s).
If the word length is 16 bits or smaller, only RSR1 is used. If the word length is larger than 16 bits,
RSR2 and RSR1 are used and RSR2 contains the most significant bits. For details on choosing a word
length, see Section 21.8.8, Set the Receive Word Length(s).
4. When a full word is received, the McBSP copies the contents of the receive shift register(s) to the
receive buffer register(s), provided that RBR1 is not full with previous data.
If the word length is 16 bits or smaller, only RBR1 is used. If the word length is larger than 16 bits,
2250

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Operation

www.ti.com

RBR2 and RBR1 are used and RBR2 contains the most significant bits.
5. The McBSP copies the contents of the receive buffer register(s) into the data receive register(s),
provided that DRR1 is not full with previous data. When DRR1 receives new data, the receiver ready
bit (RRDY) is set in SPCR1. This indicates that received data is ready to be read by the CPU or the
DMA controller.
If the word length is 16 bits or smaller, only DRR1 is used. If the word length is larger than 16 bits,
DRR2 and DRR1 are used and DRR2 contains the most significant bits.
If companding is used during the copy (RCOMPAND = 10b or 11b in RCR2), the 8-bit compressed
data in RBR1 is expanded to a left-justified 16-bit value in DRR1. If companding is disabled, the data
copied from RBR[1,2] to DRR[1,2] is justified and bit filled according to the RJUST bits.
6. The CPU or the DMA controller reads the data from the data receive register(s). When DRR1 is read,
RRDY is cleared and the next RBR-to-DRR copy is initiated.
NOTE: If both DRRs are required (word length larger than 16 bits), the CPU or the DMA controller
must read from DRR2 first and then from DRR1. As soon as DRR1 is read, the next RBR-toDRR copy is initiated. If DRR2 is not read first, the data in DRR2 is lost.

When activity is not properly timed, errors can occur. See the following topics for more details:
• Overrun in the Receiver (see Section 21.5.2)
• Unexpected Receive Frame-Synchronization Pulse (see Section 21.5.3)

21.3.6 McBSP Transmission
This section explains the fundamental process of transmission in the McBSP. For details about how to
program the McBSP transmitter, see Section 21.9.
Figure 21-15 and Figure 21-16 show how transmission occurs in the McBSP. Figure 21-15 shows the
physical path for the data. Figure 21-16 is a timing diagram showing signal activity for one possible
transmission scenario. A description of the process follows the figures.

ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ

ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ

Figure 21-15. McBSP Transmission Physical Data Path
XSR[1,2]

DX

A

XSR[1,2]: Transmit shift registers 1 and 2

B

DXR[1,2]: Data transmit registers 1 and 2

CLKX
FSX
DX A1
XRDY

Á
Á
Á
Á

DXR[1,2]

From CPU or
DMA controller

Figure 21-16. McBSP Transmission Signal Activity

A0

ÁÁ
ÁÁ
ÁÁ
ÁÁ

DXR1 to XSR1 copy(B)
A

Compress
or
do not modify

B7

B6

B5

B4

B3

Write to DXR1(C)

B2

B1

Á
Á
Á
Á

B0

DXR1 to XSR1 copy(C)

Á
Á
Á
Á

C7

C6

C5

Write to DXR1

CLKX: Internal transmit clock

B

FSX: Internal transmit frame-synchronization signal

C

DX: Data on DX pin

D

XRDY: Status of transmitter ready bit (high is 1)

1. The CPU or the DMA controller writes data to the data transmit register(s). When DXR1 is loaded, the
transmitter ready bit (XRDY) is cleared in SPCR2 to indicate that the transmitter is not ready for new
data.
If the word length is 16 bits or smaller, only DXR1 is used. If the word length is larger than 16 bits,
DXR2 and DXR1 are used and DXR2 contains the most significant bits. For details on choosing a word
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2251

McBSP Operation

www.ti.com

length, see Section 21.9.8.
NOTE: If both DXRs are needed (word length larger than 16 bits), the CPU or the DMA controller
must load DXR2 first and then load DXR1. As soon as DXR1 is loaded, the contents of both
DXRs are copied to the transmit shift registers (XSRs), as described in the next step. If
DXR2 is not loaded first, the previous content of DXR2 is passed to the XSR2.

2. When new data arrives in DXR1, the McBSP copies the content of the data transmit register(s) to the
transmit shift register(s). In addition, the transmit ready bit (XRDY) is set. This indicates that the
transmitter is ready to accept new data from the CPU or the DMA controller.
If the word length is 16 bits or smaller, only XSR1 is used. If the word length is larger than 16 bits,
XSR2 and XSR1 are used and XSR2 contains the most significant bits.
If companding is used during the transfer (XCOMPAND = 10b or 11b in XCR2), the McBSP
compresses the 16-bit data in DXR1 to 8-bit data in the μ-law or A-law format in XSR1. If companding
is disabled, the McBSP passes data from the DXR(s) to the XSR(s) without modification.
3. The McBSP waits for a transmit frame-synchronization pulse on internal FSX.
4. When the pulse arrives, the McBSP inserts the appropriate data delay that is selected with the
XDATDLY bits of XCR2.
In the preceding timing diagram (Figure 21-16), a 1-bit data delay is selected.
5. The McBSP shifts data bits from the transmit shift register(s) to the DX pin.
When activity is not properly timed, errors can occur. See the following topics for more details:
• Overwrite in the Transmitter ( Section 21.5.4)
• Underflow in the Transmitter (Section 21.5.5)
• Unexpected Transmit Frame-Synchronization Pulse (Section 21.5.6)

21.3.7 Interrupts and DMA Events Generated by a McBSP
The McBSP sends notification of important events to the CPU and DMA via the internal signals shown in
Table 21-3.
Table 21-3. Interrupts and DMA Events Generated by a McBSP
Internal Signal

Description

RINT

Receive interrupt
The McBSP can send a receive interrupt request to CPU based upon a selected condition in the receiver of
the McBSP (a condition selected by the RINTM bits of SPCR1).

XINT

Transmit interrupt
The McBSP can send a transmit interrupt request to CPU based upon a selected condition in the transmitter
of the McBSP (a condition selected by the XINTM bits of SPCR2).

REVT

Receive synchronization event
An REVT signal is sent to the DMA when data has been received in the data receive registers (DRRs).

XEVT

Transmit synchronization event
An XEVT signal is sent to the DMA when the data transmit registers (DXRs) are ready to accept the next
serial word for transmission.

21.4 McBSP Sample Rate Generator
Each McBSP contains a sample rate generator (SRG) that can be programmed to generate an internal
data clock (CLKG) and an internal frame-synchronization signal (FSG). CLKG can be used for bit shifting
on the data receive (DR) pin and/or the data transmit (DX) pin. FSG can be used to initiate frame transfers
on DR and/or DX. Figure 21-17 is a conceptual block diagram of the sample rate generator.

2252

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Sample Rate Generator

www.ti.com

21.4.1 Block Diagram
Figure 21-17. Conceptual Block Diagram of the Sample Rate Generator
MCLKX pin
1

CLKXP

SRGR1
[CLKGDV]

MCLKR pin

SRGR2
[FPER]

SRGR1
[FWID]

÷

Frame
pulse

0

CLKRP

1

CLKSRG

SRGR2 [CLKSM]

/(CLKGDV + 1)

FSG

0
LSPCLK
1

Reserved

0

CLKG
PCR
[SCLKSME]

GSYNC

Frame pulse
detection
and clock
synchronization

FSR

The source clock for the sample rate generator (labeled CLKSRG in the diagram) can be supplied by the
LSPCLK, or by an external pin (MCLKX or MCLKR ). The source is selected with the SCLKME bit of PCR
and the CLKSM bit of SRGR2. If a pin is used, the polarity of the incoming signal can be inverted with the
appropriate polarity bit (CLKXP of PCR or CLKRP of PCR).
The sample rate generator has a three-stage clock divider that gives CLKG and FSG programmability.
The three stages provide:
• Clock divide-down. The source clock is divided according to the CLKGDV bits of SRGR1 to produce
CLKG.
• Frame period divide-down. CLKG is divided according to the FPER bits of SRGR2 to control the period
from the start of a frame-pulse to the start of the next pulse.
• Frame-synchronization pulse-width countdown. CLKG cycles are counted according to the FWID bits
of SRGR1 to control the width of each frame-synchronization pulse.
NOTE: The McBSP cannot operate at a frequency faster than ½ the source clock frequency.
Choose an input clock frequency and a CLKGDV value such that CLKG is less than or equal
to ½ the source clock frequency.

In addition to the three-stage clock divider, the sample rate generator has a frame-synchronization pulse
detection and clock synchronization module that allows synchronization of the clock divide down with an
incoming frame-synchronization pulse on the FSR pin. This feature is enabled or disabled with the
GSYNC bit of SRGR2.
For details on getting the sample rate generator ready for operation, see Section 21.4.4.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2253

McBSP Sample Rate Generator

www.ti.com

21.4.1.1 Clock Generation in the Sample Rate Generator
The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter, or
both. Use of the sample rate generator to drive clocking is controlled by the clock mode bits (CLKRM and
CLKXM) in the pin control register (PCR). When a clock mode bit is set to 1 (CLKRM = 1 for reception,
CLKXM = 1 for transmission), the corresponding data clock (CLKR for reception, CLKX for transmission)
is driven by the internal sample rate generator output clock (CLKG).
The effects of CLKRM = 1 and CLKXM = 1 on the McBSP are partially affected by the use of the digital
loopback mode and the clock stop (SPI) mode, respectively, as described in Table 21-4. The digital
loopback mode (described in Section 21.8.4) is selected with the DLB bit of SPCR1. The clock stop mode
(described in Section 21.7.2) is selected with the CLKSTP bits of SPCR1.
When using the sample rate generator as a clock source, make sure the sample rate generator is enabled
(GRST = 1).
Table 21-4. Effects of DLB and CLKSTP on Clock Modes
Mode Bit Settings

Effect

CLKRM = 1

DLB = 0
(Digital loopback mode disabled)

CLKR is an output pin driven by the sample rate generator output clock
(CLKG).

DLB = 1
(Digital loopback mode enabled)

CLKR is an output pin driven by internal CLKX. The source for CLKX
depends on the CLKXM bit.

CLKSTP = 00b or 01b
(Clock stop (SPI) mode disabled)

CLKX is an output pin driven by the sample rate generator output clock
(CLKG).

CLKSTP = 10b or 11b
(Clock stop (SPI) mode enabled)

The McBSP is a master in an SPI system. Internal CLKX drives internal
CLKR and the shift clocks of any SPI-compliant slave devices in the
system. CLKX is driven by the internal sample rate generator.

CLKXM = 1

21.4.1.2 Choosing an Input Clock
The sample rate generator must be driven by an input clock signal from one of the three sources
selectable with the SCLKME bit of PCR and the CLKSM bit of SRGR2 (see Table 21-5). When CLKSM =
1, the minimum divide down value in CLKGDV bits is 1. CLKGDV is described in Section 21.4.1.4.
Table 21-5. Choosing an Input Clock for the Sample Rate Generator with the
SCLKME and CLKSM Bits
SCLKME

CLKSM

0

0

Input Clock for Sample Rate Generator
Reserved

0

1

LSPCLK

1

0

Signal on MCLKR pin

1

1

Signal on MCLKX pin

21.4.1.3 Choosing a Polarity for the Input Clock
As shown in Figure 21-18, when the input clock is received from a pin, you can choose the polarity of the
input clock. The rising edge of CLKSRG generates CLKG and FSG, but you can determine which edge of
the input clock causes a rising edge on CLKSRG. The polarity options and their effects are described in
Table 21-6.

2254

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Sample Rate Generator

www.ti.com

Figure 21-18. Possible Inputs to the Sample Rate Generator and the Polarity Bits
MCLKX pin
1

CLKXP
MCLKR pin

0

CLKRP

1

CLKSRG
To clock dividers

CLKSM
0
LSPCLK

1
SCLKME
Reserved

0

Table 21-6. Polarity Options for the Input to the Sample Rate Generator
Input Clock

Polarity Option

Effect

LSPCLK

Always positive polarity

Rising edge of CPU clock generates transitions on CLKG and FSG.

Signal on MCLKR pin

CLKRP = 0 in PCR

Falling edge on MCLKR pin generates transitions on CLKG and FSG.

CLKRP = 1 in PCR

Rising edge on MCLKR pin generates transitions on CLKG and FSG.

CLKXP = 0 in PCR

Rising edge on MCLKX pin generates transitions on CLKG and FSG.

CLKXP = 1 in PCR

Falling edge on MCLKX pin generates transitions on CLKG and FSG.

Signal on MCLKX pin

21.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
The input clock (LSPCLK or external clock) can be divided down by a programmable value to drive CLKG.
Regardless of the source to the sample rate generator, the rising edge of CLKSRG (see Figure 21-1)
generates CLKG and FSG.
The first divider stage of the sample rate generator creates the output clock from the input clock. This
divider stage uses a counter that is preloaded with the divide down value in the CLKGDV bits of SRGR1.
The output of this stage is the data clock (CLKG). CLKG has the frequency represented by the equation.
Equation 1: CLKG Frequency
CLKG frequency +

Input clock frequency
(CLKGDV ) 1)

21.4.1.4.1 CLKG Frequency
Thus, the input clock frequency is divided by a value between 1 and 256. When CLKGDV is odd or equal
to 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide down,
the high-state duration is p+1 cycles and the low-state duration is p cycles.
21.4.1.5 Keeping CLKG Synchronized to External MCLKR
When the MCLKR pin is used to drive the sample rate generator (see Section 21.4.1.2), the GSYNC bit in
SRGR2 and the FSR pin can be used to configure the timing of the output clock (CLKG) relative to the
input clock. Note that this feature is available only when the MCLKR pin is used to feed the external clock.
GSYNC = 1 ensures that the McBSP and an external device are dividing down the input clock with the
same phase relationship. If GSYNC = 1, an inactive-to-active transition on the FSR pin triggers a
resynchronization of CLKG and generation of FSG.
For more details about synchronization, see Section 21.4.3.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2255

McBSP Sample Rate Generator

www.ti.com

21.4.2 Frame Synchronization Generation in the Sample Rate Generator
The sample rate generator can produce a frame-synchronization signal (FSG) for use by the receiver, the
transmitter, or both.
If you want the receiver to use FSG for frame synchronization, make sure FSRM = 1. (When FSRM = 0,
receive frame synchronization is supplied via the FSR pin.)
If you want the transmitter to use FSG for frame synchronization, you must set:
• FSXM = 1 in PCR: This indicates that transmit frame synchronization is supplied by the McBSP itself
rather than from the FSX pin.
• FSGM = 1 in SRGR2: This indicates that when FSXM = 1, transmit frame synchronization is supplied
by the sample rate generator. (When FSGM = 0 and FSXM = 1, the transmitter uses framesynchronization pulses generated every time data is transferred from DXR[1,2] to XSR[1,2].)
In either case, the sample rate generator must be enabled (GRST = 1) and the frame-synchronization
logic in the sample rate generator must be enabled (FRST = 1).
21.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
Each pulse on FSG has a programmable width. You program the FWID bits of SRGR1, and the resulting
pulse width is (FWID + 1) CLKG cycles, where CLKG is the output clock of the sample rate generator.
21.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
You can control the amount of time from the starting edge of one FSG pulse to the starting edge of the
next FSG pulse. This period is controlled in one of two ways, depending on the configuration of the
sample rate generator:
• If the sample rate generator is using an external input clock and GSYNC = 1 in SRGR2, FSG pulses in
response to an inactive-to-active transition on the FSR pin. Thus, the frame-synchronization period is
controlled by an external device.
• Otherwise, you program the FPER bits of SRGR2, and the resulting frame-synchronization period is
(FPER + 1) CLKG cycles, where CLKG is the output clock of the sample rate generator.
21.4.2.3 Keeping FSG Synchronized to an External Clock
When an external signal is selected to drive the sample rate generator (see Section 21.4.1.2 on page
Section 21.4.1.2), the GSYNC bit of SRGR2 and the FSR pin can be used to configure the timing of FSG
pulses.
GSYNC = 1 ensures that the McBSP and an external device are dividing down the input clock with the
same phase relationship. If GSYNC = 1, an inactive-to-active transition on the FSR pin triggers a
resynchronization of CLKG and generation of FSG.
See Section 21.4.3 for more details about synchronization.

21.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
The sample rate generator can produce a clock signal (CLKG) and a frame-synchronization signal (FSG)
based on an input clock signal that is either the CPU clock signal or a signal at the MCLKR or MCLKX pin.
When an external clock is selected to drive the sample rate generator, the GSYNC bit of SRGR2 and the
FSR pin can be used to control the timing of CLKG and the pulsing of FSG relative to the chosen input
clock.
Make GSYNC = 1 when you want the McBSP and an external device to divide down the input clock with
the same phase relationship. If GSYNC = 1:
• An inactive-to-active transition on the FSR pin triggers a resynchronization of CLKG and a pulsing of
FSG.
• CLKG always begins with a high state after synchronization.
• FSR is always detected at the same edge of the input clock signal that generates CLKG, no matter
how long the FSR pulse is.
2256

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Sample Rate Generator

www.ti.com

•

The FPER bits of SRGR2 are ignored because the frame-synchronization period on FSG is determined
by the arrival of the next frame-synchronization pulse on the FSR pin.

If GSYNC = 0, CLKG runs freely and is not resynchronized, and the frame-synchronization period on FSG
is determined by FPER.
21.4.3.1 Operating the Transmitter Synchronously with the Receiver
When GSYNC = 1, the transmitter can operate synchronously with the receiver, provided that:
• FSX is programmed to be driven by FSG (FSGM = 1 in SRGR2 and FSXM = 1 in PCR). If the input
FSR has appropriate timing so that it can be sampled by the falling edge of CLKG, it can be used,
instead, by setting FSXM = 0 and connecting FSR to FSX externally.
• The sample rate generator clock drives the transmit and receive clocking (CLKRM = CLKXM = 1 in
PCR).
21.4.3.2 Synchronization Examples
Figure 21-19 and Figure 21-20 show the clock and frame-synchronization operation with various polarities
of CLKR and FSR. These figures assume FWID = 0 in SRGR1, for an FSG pulse that is one CLKG cycle
wide. The FPER bits of SRGR2 are not programmed; the period from the start of a frame-synchronization
pulse to the start of the next pulse is determined by the arrival of the next inactive-to-active transition on
the FSR pin. Each of the figures shows what happens to CLKG when it is initially synchronized and
GSYNC = 1, and when it is not initially synchronized and GSYNC = 1. The second figure has a slower
CLKG frequency (it has a larger divide-down value in the CLKGDV bits of SRGR1).
Figure 21-19. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1
CLKR
CLKR
FSR external
(FSRP=0)
FSR external
(FSRP=1)
CLKG
(No need to
resynchronize)
CLKG
(Needs resynchronization)
FSG

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2257

McBSP Sample Rate Generator

www.ti.com

Figure 21-20. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3
CLKR
CLKR
FSR external
(FSRP=0)
FSR external
(FSRP=1)
CLKG
(No need to
resynchronize)
CLKG
(Needs resynchronization)
FSG

21.4.4 Reset and Initialization Procedure for the Sample Rate Generator
To reset and initialize the sample rate generator:
Step 1. Place the McBSP/sample rate generator in reset.
During a DSP reset, the sample rate generator, the receiver, and the transmitter reset bits (GRST,
RRST, and XRST) are automatically forced to 0. Otherwise, during normal operation, the sample rate
generator can be reset by making GRST = 0 in SPCR2, provided that CLKG and/or FSG is not used
by any portion of the McBSP. Depending on your system you may also want to reset the receiver
(RRST = 0 in SPCR1) and reset the transmitter (XRST = 0 in SPCR2).
If GRST = 0 due to a device reset, CLKG is driven by the CPU clock divided by 2, and FSG is driven
inactive-low. If GRST = 0 due to program code, CLKG and FSG are driven low (inactive).
Step 2. Program the registers that affect the sample rate generator.
Program the sample rate generator registers (SRGR1 and SRGR2) as required for your application. If
necessary, other control registers can be loaded with desired values, provided the respective portion of
the McBSP (the receiver or transmitter) is in reset.
After the sample rate generator registers are programmed, wait 2 CLKSRG cycles. This ensures
proper synchronization internally.
Step 3. Enable the sample rate generator (take it out of reset).
In SPCR2, make GRST = 1 to enable the sample rate generator.
After the sample rate generator is enabled, wait two CLKG cycles for the sample rate generator logic to
stabilize.
On the next rising edge of CLKSRG, CLKG transitions to 1 and starts clocking with a frequency equal
to the CLKG Frequency equation below.
Table 21-7. Input Clock Selection for Sample Rate Generator

2258

SCLKME

CLKSM

0

0

Reserved

0

1

LSPCLK

1

0

Signal on MCLKR pin

1

1

Signal on MCLKX pin

Multichannel Buffered Serial Port (McBSP)

Input Clock for Sample Rate Generator

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Exception/Error Conditions

www.ti.com

Step 4. If necessary, enable the receiver and/or the transmitter.
If necessary, remove the receiver and/or transmitter from reset by setting RRST and/or XRST = 1.
Step 5. If necessary, enable the frame-synchronization logic of the sample rate generator.
After the required data acquisition setup is done (DXR[1,2] is loaded with data), set GRST = 1 in
SPCR2 if an internally generated frame-synchronization pulse is required. FSG is generated with an
active-high edge after the programmed number of CLKG clocks (FPER + 1) have elapsed.
Equation 2: CLKG Frequency
CLKG frequency +

Input clock frequency
(CLKGDV ) 1)

where the input clock is selected with the SCLKME bit of PCR and the CLKSM bit of SRGR2 in one of the
configurations shown in Table 21-7.

21.5 McBSP Exception/Error Conditions
This chapter describes exception/error conditions and how to handle them.

21.5.1 Types of Errors
There are five serial port events that can constitute a system error:
• Receiver overrun (RFULL = 1)
This occurs when DRR1 has not been read since the last RBR-to-DRR copy. Consequently, the
receiver does not copy a new word from the RBR(s) to the DRR(s) and the RSR(s) are now full with
another new word shifted in from DR. Therefore, RFULL = 1 indicates an error condition wherein any
new data that can arrive at this time on DR replaces the contents of the RSR(s), and the previous word
is lost. The RSRs continue to be overwritten as long as new data arrives on DR and DRR1 is not read.
For more details about overrun in the receiver, see Section 21.5.2.
• Unexpected receive frame-synchronization pulse (RSYNCERR = 1)
This occurs during reception when RFIG = 0 and an unexpected frame-synchronization pulse occurs.
An unexpected frame-synchronization pulse is one that begins the next frame transfer before all the
bits of the current frame have been received. Such a pulse causes data reception to abort and restart.
If new data has been copied into the RBR(s) from the RSR(s) since the last RBR-to-DRR copy, this
new data in the RBR(s) is lost. This is because no RBR-to-DRR copy occurs; the reception has been
restarted. For more details about receive frame-synchronization errors, see Section 21.5.3.
• Transmitter data overwrite
This occurs when the CPU or DMA controller overwrites data in the DXR(s) before the data is copied
to the XSR(s). The overwritten data never reaches the DX pin. For more details about overwrite in the
transmitter, see Section 21.5.4.
• Transmitter underflow (XEMPTY = 0)
If a new frame-synchronization signal arrives before new data is loaded into DXR1, the previous data
in the DXR(s) is sent again. This procedure continues for every new frame-synchronization pulse that
arrives until DXR1 is loaded with new data. For more details about underflow in the transmitter, see
Section 21.5.5.
• Unexpected transmit frame-synchronization pulse (XSYNCERR = 1)
This occurs during transmission when XFIG = 0 and an unexpected frame-synchronization pulse
occurs. An unexpected frame-synchronization pulse is one that begins the next frame transfer before
all the bits of the current frame have been transferred. Such a pulse causes the current data
transmission to abort and restart. If new data has been written to the DXR(s) since the last DXR-toXSR copy, the current value in the XSR(s) is lost. For more details about transmit framesynchronization errors, see Section 21.5.6.

21.5.2 Overrun in the Receiver
RFULL = 1 in SPCR1 indicates that the receiver has experienced overrun and is in an error condition.
RFULL is set when all of the following conditions are met:
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2259

McBSP Exception/Error Conditions

www.ti.com

1. DRR1 has not been read since the last RBR-to-DRR copy (RRDY = 1).
2. RBR1 is full and an RBR-to-DRR copy has not occurred.
3. RSR1 is full and an RSR1-to-RBR copy has not occurred.
As described in the Section 21.3.5, data arriving on DR is continuously shifted into RSR1 (for word length
of 16 bits or smaller) or RSR2 and RSR1 (for word length larger than 16 bits). Once a complete word is
shifted into the RSR(s), an RSR-to-RBR copy can occur only if the previous data in RBR1 has been
copied to DRR1. The RRDY bit is set when new data arrives in DRR1 and is cleared when that data is
read from DRR1. Until RRDY = 0, the next RBR-to-DRR copy does not take place, and the data is held in
the RSR(s). New data arriving on the DR pin is shifted into RSR(s), and the previous content of the
RSR(s) is lost.
You can prevent the loss of data if DRR1 is read no later than 2.5 cycles before the end of the third word
is shifted into the RSR1.
NOTE: If both DRRs are needed (word length larger than 16 bits), the CPU or the DMA controller
must read from DRR2 first and then from DRR1. As soon as DRR1 is read, the next RBR-toDRR copy is initiated. If DRR2 is not read first, the data in DRR2 is lost.

After the receiver starts running from reset, a minimum of three words must be received before RFULL is
set. Either of the following events clears the RFULL bit and allows subsequent transfers to be read
properly:
• The CPU or DMA controller reads DRR1.
• The receiver is reset individually (RRST = 0) or as part of a device reset.
Another frame-synchronization pulse is required to restart the receiver.
21.5.2.1 Example of Overrun Condition
Figure 21-21 shows the receive overrun condition. Because serial word A is not read from DRR1 before
serial word B arrives in RBR1, B is not transferred to DRR1 yet. Another new word ©) arrives and RSR1 is
full with this data. DRR1 is finally read, but not earlier than 2.5 cycles before the end of word C. Therefore,
new data (D) overwrites word C in RSR1. If DRR1 is not read in time, the next word can overwrite D.

CLKR
FSR
DR A1
RRDY
RFULL

ÁÁ
Á
Á
ÁÁ
ÁÁ

A0

Figure 21-21. Overrun in the McBSP Receiver

ÁÁ
Á
Á
ÁÁ
ÁÁ

B7 B6 B5 B4 B3 B2 B1 B0

RBR1 to DRR1 copy(A)
No read from DRR1(A)

ÁÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁÁ

C7 C6 C5 C4 C3 C2 C1 C0
D7
No RSR1 to RBR1 copy(C)

No RBR1 to DRR1 copy(B)

No read from DRR1(A)

21.5.2.2 Example of Preventing Overrun Condition
Figure 21-22 shows the case where RFULL is set, but the overrun condition is prevented by a read from
DRR1 at least 2.5 cycles before the next serial word ©) is completely shifted into RSR1. This ensures that
an RBR1-to-DRR1 copy of word B occurs before receiver attempts to transfer word C from RSR1 to
RBR1.

2260

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Exception/Error Conditions

www.ti.com

Figure 21-22. Overrun Prevented in the McBSP Receiver
CLKR
FSR
DR A1
RRDY
RFULL

ÁÁ
Á
Á
ÁÁ

A0

B7 B6 B5 B4 B3 B2

ÁÁ
Á
Á
ÁÁ

B1 B0

RBR1 to DRR1 copy(A)
No read From DRR1(A)

Á
Á
Á

C7 C6 C5 C4 C3 C2 C1 C0
RBR1 to DRR1(B)

No RBR1 to DRR1 copy(B)

Read from DRR1(A)

21.5.3 Unexpected Receive Frame-Synchronization Pulse
Section 21.5.3.1 shows how the McBSP responds to any receive frame-synchronization pulses, including
an unexpected pulse. Section 21.5.3.2 and Section 21.5.3.3 show an examples of a frame-synchronization
error and an example of how to prevent such an error, respectively.
21.5.3.1 Possible Responses to Receive Frame-Synchronization Pulses
Figure 21-23 shows the decision tree that the receiver uses to handle all incoming frame-synchronization
pulses. The figure assumes that the receiver has been started (RRST = 1 in SPCR1). Case 3 in the figure
is the case in which an error occurs.

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ

Figure 21-23. Possible Responses to Receive Frame-Synchronization Pulses
Receive frame-sync
pulse occurs.

Unexpected
frame-sync
pulse
?

No

Case 2:
Normal reception.
Start receiving data.

Yes

RFIG=1
?

No

Case 3:
Without frame ignore,
abort reception.
Set RSYNCERR.
Start next reception
immediately.
Previous word is lost.

Yes

Case 1:
With frame ignore,
ignore frame pulse.
Receiver continues
running.

Any one of three cases can occur:
• Case 1: Unexpected internal FSR pulses with RFIG = 1 in RCR2. Receive frame-synchronization
pulses are ignored, and the reception continues.
• Case 2: Normal serial port reception. Reception continues normally because the frame-synchronization
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2261

McBSP Exception/Error Conditions

•

www.ti.com

pulse is not unexpected. There are three possible reasons why a receive operation might not be in
progress when the pulse occurs:
– The FSR pulse is the first after the receiver is enabled (RRST = 1 in SPCR1).
– The FSR pulse is the first after DRR[1,2] is read, clearing a receiver full (RFULL = 1 in SPCR1)
condition.
– The serial port is in the interpacket intervals. The programmed data delay for reception
(programmed with the RDATDLY bits in RCR2) may start during these interpacket intervals for the
first bit of the next word to be received. Thus, at maximum frame frequency, frame synchronization
can still be received 0 to 2 clock cycles before the first bit of the synchronized frame.
Case 3: Unexpected receive frame synchronization with RFIG = 0 (frame-synchronization pulses not
ignored). Unexpected frame-synchronization pulses can originate from an external source or from the
internal sample rate generator.
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
received, this pulse is treated as an unexpected frame-synchronization pulse, and the receiver sets the
receive frame-synchronization error bit (RSYNCERR) in SPCR1. RSYNCERR can be cleared only by a
receiver reset or by a write of 0 to this bit.
If you want the McBSP to notify the CPU of receive frame-synchronization errors, you can set a special
receive interrupt mode with the RINTM bits of SPCR1. When RINTM = 11b, the McBSP sends a
receive interrupt (RINT) request to the CPU each time that RSYNCERR is set.

21.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
Figure 21-30 shows an unexpected receive frame-synchronization pulse during normal operation of the
serial port, with time intervals between data packets. When the unexpected frame-synchronization pulse
occurs, the RSYNCERR bit is set, the reception of data B is aborted, and the reception of data C begins.
In addition, if RINTM = 11b, the McBSP sends a receive interrupt (RINT) request to the CPU.
Figure 21-24. An Unexpected Frame-Synchronization Pulse During a McBSP Reception
CLKR
FSR
DR A1

Á
Á
Á
Á

A0

ÁÁ
ÁÁ
ÁÁ
ÁÁ

Unexpected frame synchronization

Á
Á
Á
Á

B7 B6 B5 B4 C7 C6 C5 C4 C3 C2 C1 C0

RBR1 to DRR1(B)

RRDY
RBR1 to DRR1 copy(A)

Read from DRR1(A)

RBR1 to DRR1 copy(C)

Read from DRR1(C)

RSYNCERR

21.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
Each frame transfer can be delayed by 0, 1, or 2 MCLKR cycles, depending on the value in the RDATDLY
bits of RCR2. For each possible data delay, Figure 21-25 shows when a new frame-synchronization pulse
on FSR can safely occur relative to the last bit of the current frame.

2262

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Exception/Error Conditions

www.ti.com

Figure 21-25. Proper Positioning of Frame-Synchronization Pulses
For 2-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 1-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 0-bit delay:
Next frame-synchronization
pulse here or later is OK.

CLKR/CLKX

FSR/FSX

DR/DX

Last bit of
current frame

Earliest possible
time to begin transfer
of next frame

21.5.4 Overwrite in the Transmitter
As described in the section on McBSP transmission (page Section 21.3.6), the transmitter must copy the
data previously written to the DXR(s) by the CPU or DMA controller into the XSR(s) and then shift each bit
from the XSR(s) to the DX pin. If new data is written to the DXR(s) before the previous data is copied to
the XSR(s), the previous data in the DXR(s) is overwritten and thus lost.
21.5.4.1 Example of Overwrite Condition
Figure 21-26 shows what happens if the data in DXR1 is overwritten before being transmitted. Initially,
DXR1 is loaded with data C. A subsequent write to DXR1 overwrites C with D before C is copied to XSR1.
Thus, C is never transmitted on DX.
Figure 21-26. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted
CLKX
FSX
DX A1
XRDY

Á
Á
Á
Á

Á
Á
Á
Á

A0

B7

B6

B5

B4

B3

Write to DXR1(C) Write to DXR1(D)

B2

B1

Á
Á
Á
Á

B0

DXR1 to XSR1 Copy(D)

Á
Á
Á
Á

D7

D6

D5

Write to DXR1(E)

21.5.4.2 Preventing Overwrites
You can prevent CPU overwrites by making the CPU:
• Poll for XRDY = 1 in SPCR2 before writing to the DXR(s). XRDY is set when data is copied from DXR1
to XSR1 and is cleared when new data is written to DXR1.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2263

McBSP Exception/Error Conditions

•

www.ti.com

Wait for a transmit interrupt (XINT) before writing to the DXR(s). When XINTM = 00b in SPCR2, the
transmitter sends XINT to the CPU each time XRDY is set.

You can prevent DMA overwrites by synchronizing DMA transfers to the transmit synchronization event
XEVT. The transmitter sends an XEVT signal each time XRDY is set.

21.5.5 Underflow in the Transmitter
The McBSP indicates a transmitter empty (or underflow) condition by clearing the XEMPTY bit in SPCR2.
Either of the following events activates XEMPTY (XEMPTY = 0):
• DXR1 has not been loaded since the last DXR-to-XSR copy, and all bits of the data word in the XSR(s)
have been shifted out on the DX pin.
• The transmitter is reset (by forcing XRST = 0 in SPCR2, or by a device reset) and is then restarted.
In the underflow condition, the transmitter continues to transmit the old data that is in the DXR(s) for every
new transmit frame-synchronization signal until a new value is loaded into DXR1 by the CPU or the DMA
controller.
NOTE: If both DXRs are needed (word length larger than 16 bits), the CPU or the DMA controller
must load DXR2 first and then load DXR1. As soon as DXR1 is loaded, the contents of both
DXRs are copied to the transmit shift registers (XSRs). If DXR2 is not loaded first, the
previous content of DXR2 is passed to the XSR2.

XEMPTY is deactivated (XEMPTY = 1) when a new word in DXR1 is transferred to XSR1. If FSXM = 1 in
PCR and FSGM = 0 in SRGR2, the transmitter generates a single internal FSX pulse in response to a
DXR-to-XSR copy. Otherwise, the transmitter waits for the next frame-synchronization pulse before
sending out the next frame on DX.
When the transmitter is taken out of reset (XRST = 1), it is in a transmitter ready (XRDY = 1 in SPCR2)
and transmitter empty (XEMPTY = 0) state. If DXR1 is loaded by the CPU or the DMA controller before
internal FSX goes active high, a valid DXR-to-XSR transfer occurs. This allows for the first word of the first
frame to be valid even before the transmit frame-synchronization pulse is generated or detected.
Alternatively, if a transmit frame-synchronization pulse is detected before DXR1 is loaded, zeros are
output on DX.
21.5.5.1 Example of the Underflow Condition
Figure 21-27 shows an underflow condition. After B is transmitted, DXR1 is not reloaded before the
subsequent frame-synchronization pulse. Thus, B is again transmitted on DX.
Figure 21-27. Underflow During McBSP Transmission
CLKX
FSX
DX A1
XRDY

Á
Á
Á

A0

Á
Á
Á

B7

B6

B5

B4

B3

B2

B1

Á
Á
Á

B0

DXR1 to XSR1 copy(B)

Á
Á
Á

B7

B6

B5

Write to DXR1(C)

XEMPTY_

21.5.5.2 Example of Preventing Underflow Condition
Figure 21-28 shows the case of writing to DXR1 just before an underflow condition would otherwise occur.
After B is transmitted, C is written to DXR1 before the next frame-synchronization pulse. As a result, there
is no underflow; B is not transmitted twice.

2264

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Exception/Error Conditions

www.ti.com

Figure 21-28. Underflow Prevented in the McBSP Transmitter
CLKX
FSX
DX A1
XRDY

Á
Á
Á
A0

Á
Á
Á

B7

B6

B5

B4

DXR1 to XSR1 copy

B3

B2

B1

Á
Á
Á

B0

Write to DXR1(C)

Á
Á
Á

C7 C6

C5

DXR1 to XSR1 copy(C)

XEMPTY_

21.5.6 Unexpected Transmit Frame-Synchronization Pulse
Section 21.5.6.1 shows how the McBSP responds to any transmit frame-synchronization pulses, including
an unexpected pulse. Section 21.5.6.2 and Section 21.5.6.3 show examples of a frame-synchronization
error and an example of how to prevent such an error, respectively.
21.5.6.1 Possible Responses to Transmit Frame-Synchronization Pulses
Figure 21-29 shows the decision tree that the transmitter uses to handle all incoming framesynchronization pulses. The figure assumes that the transmitter has been started (XRST = 1 in SPCR2).
Case 3 in the figure is the case in which an error occurs.
Figure 21-29. Possible Responses to Transmit Frame-Synchronization Pulses
Transmit frame-sync
pulse occurs.

Unexpected
frame-sync
pulse
?

No

Case 2:
Normal transmission.
Start new transmit.

Yes

XFIG=1
?

No

Case 3:
Without frame ignore
abort transfer.
Set XSYNCERR.
Restart current
transfer.

Yes
Case 1:
With frame ignore
ignore frame pulse.
Transmit stays
running.

Any one of three cases can occur:
• Case 1: Unexpected internal FSX pulses with XFIG = 1 in XCR2. Transmit frame-synchronization
pulses are ignored, and the transmission continues.
• Case 2: Normal serial port transmission. Transmission continues normally because the frameSPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2265

McBSP Exception/Error Conditions

•

www.ti.com

synchronization pulse is not unexpected. There are two possible reasons why a transmit operations
might not be in progress when the pulse occurs:
This FSX pulse is the first after the transmitter is enabled (XRST = 1).
The serial port is in the interpacket intervals. The programmed data delay for transmission
(programmed with the XDATDLY bits of XCR2) may start during these interpacket intervals before the
first bit of the previous word is transmitted. Thus, at maximum packet frequency, frame synchronization
can still be received 0 to 2 clock cycles before the first bit of the synchronized frame.
Case 3: Unexpected transmit frame synchronization with XFIG = 0 (frame-synchronization pulses not
ignored). Unexpected frame-synchronization pulses can originate from an external source or from the
internal sample rate generator.
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
transmitted, this pulse is treated as an unexpected frame-synchronization pulse, and the transmitter
sets the transmit frame-synchronization error bit (XSYNCERR) in SPCR2. XSYNCERR can be cleared
only by a transmitter reset or by a write of 0 to this bit.
If you want the McBSP to notify the CPU of frame-synchronization errors, you can set a special
transmit interrupt mode with the XINTM bits of SPCR2. When XINTM = 11b, the McBSP sends a
transmit interrupt (XINT) request to the CPU each time that XSYNCERR is set.

21.5.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse
Section 21.5.3.2 shows an unexpected transmit frame-synchronization pulse during normal operation of
the serial port with intervals between the data packets. When the unexpected frame-synchronization pulse
occurs, the XSYNCERR bit is set and the transmission of data B is restarted because no new data has
been passed to XSR1 yet. In addition, if XINTM = 11b, the McBSP sends a transmit interrupt (XINT)
request to the CPU.
Figure 21-30. An Unexpected Frame-Synchronization Pulse During a McBSP Transmission
CLKX
FSX
DX A1

Á
Á
Á
A0

Á
Á
Á

Unexpected frame synchronization

B7

B6 B5

B4 B7

B6

B5 B4

B3 B2

Á
Á
Á

B1 B0

XRDY
DXR1 to XSR1 copy(B)

Write to DXR1(C)

DXR1 to XSR1 (C)

Write to DXR1(D)

XSYNCERR

21.5.6.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
Each frame transfer can be delayed by 0, 1, or 2 CLKX cycles, depending on the value in the XDATDLY
bits of XCR2. For each possible data delay, Figure 21-31 shows when a new frame-synchronization pulse
on FSX can safely occur relative to the last bit of the current frame.

2266

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Multichannel Selection Modes

www.ti.com

Figure 21-31. Proper Positioning of Frame-Synchronization Pulses
For 2-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 1-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 0-bit delay:
Next frame-synchronization
pulse here or later is OK.

CLKR/CLKX

FSR/FSX

DR/DX

Last bit of
current frame

Earliest possible
time to begin transfer
of next frame

21.6 Multichannel Selection Modes
This section discusses the multichannel selection modes for the McBSP.

21.6.1 Channels, Blocks, and Partitions
A McBSP channel is a time slot for shifting in/out the bits of one serial word. Each McBSP supports up to
128 channels for reception and 128 channels for transmission.
In the receiver and in the transmitter, the 128 available channels are divided into eight blocks that each
contain 16 contiguous channels (see Table 21-8 through Table 21-10) :
• It is possible to have two receive partitions (A & B) and 8 transmit partitions (A – H).
• McBSP can transmit/receive on selected channels.
• Each channel partition has a dedicated channel-enable register. Each bit controls whether data flow is
allowed or prevented in one of the channels assigned to that partition.
• There are three transmit multichannel modes and one receive multichannel mode.
Table 21-8. Block - Channel Assignment
Block

Channels

0

0 -15

1

16 - 31

2

32 - 47

3

48 - 63

4

64 - 79

5

80 - 95

6

96 - 111

7

112 - 127

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2267

Multichannel Selection Modes

www.ti.com

The blocks are assigned to partitions according to the selected partition mode. In the two-partition
mode (described in Section 21.6.4), you assign one even-numbered block (0, 2, 4, or 6) to partition A
and one odd-numbered block (1, 3, 5, or 7) to partition B. In the 8-partition mode (described in
Section 21.6.5), blocks 0 through 7 are automatically assigned to partitions, A through H, respectively.
Table 21-9. 2-Partition Mode
Partition

Blocks

A

0 or 2 or 4 or 6

B

1 or 3 or 5 or 7

Table 21-10. 8-Partition mode
Partition

Blocks

A

0

Channels
0 -15

B

1

16 - 31

C

2

32 - 47

D

3

48 - 63

E

4

64 - 79

F

5

80 - 95

G

6

96 - 111

H

7

112 - 127

The number of partitions for reception and the number of partitions for transmission are independent. For
example, it is possible to use two receive partitions (A and B) and eight transmit partitions (A-H).

21.6.2 Multichannel Selection
When a McBSP uses a time-division multiplexed (TDM) data stream while communicating with other
McBSPs or serial devices, the McBSP may need to receive and/or transmit on only a few channels. To
save memory and bus bandwidth, you can use a multichannel selection mode to prevent data flow in
some of the channels.
Each channel partition has a dedicated channel enable register. If the appropriate multichannel selection
mode is on, each bit in the register controls whether data flow is allowed or prevented in one of the
channels that is assigned to that partition.
The McBSP has one receive multichannel selection mode (described in Section 21.6.6) and three transmit
multichannel selection modes (described in Section 21.6.7).

21.6.3 Configuring a Frame for Multichannel Selection
Before you enable a multichannel selection mode, make sure you properly configure the data frame:
• Select a single-phase frame (RPHASE/XPHASE = 0). Each frame represents a TDM data stream.
• Set a frame length (in RFRLEN1/XFRLEN1) that includes the highest-numbered channel to be used.
For example, if you plan to use channels 0, 15, and 39 for reception, the receive frame length must be
at least 40 (RFRLEN1 = 39). If XFRLEN1 = 39 in this case, the receiver creates 40 time slots per
frame but only receives data during time slots 0, 15, and 39 of each frame.

21.6.4 Using Two Partitions
For multichannel selection operation in the receiver and/or the transmitter, you can use two partitions or
eight partitions (described in Section 21.6.5). If you choose the 2-partition mode (RMCME = 0 for
reception, XMCME = 0 for transmission), McBSP channels are activated using an alternating scheme. In
response to a frame-synchronization pulse, the receiver or transmitter begins with the channels in partition
A and then alternates between partitions B and A until the complete frame has been transferred. When the
next frame-synchronization pulse occurs, the next frame is transferred beginning with the channels in
partition A.
2268

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Multichannel Selection Modes

www.ti.com

21.6.4.1 Assigning Blocks to Partitions A and B
For reception, any two of the eight receive-channel blocks can be assigned to receive partitions A and B,
which means up to 32 receive channels can be enabled at any given point in time. Similarly, any two of
the eight transmit-channel blocks (up 32 enabled transmit channels) can be assigned to transmit partitions
A and B.
For reception:
• Assign an even-numbered channel block (0, 2, 4, or 6) to receive partition A by writing to the RPABLK
bits. In the receive multichannel selection mode (described in Section 21.6.6), the channels in this
partition are controlled by receive channel enable register A (RCERA).
• Assign an odd-numbered block (1, 3, 5, or 7) to receive partition B with the RPBBLK bits. In the
receive multichannel selection mode, the channels in this partition are controlled by receive channel
enable register B (RCERB).
For transmission:
• Assign an even-numbered channel block (0, 2, 4, or 6) to transmit partition A by writing to the XPABLK
bits. In one of the transmit multichannel selection modes (described in Section 21.6.7), the channels in
this partition are controlled by transmit channel enable register A (XCERA).
• Assign an odd-numbered block (1, 3, 5, or 7) to transmit partition B with the XPBBLK bits. In one of the
transmit multichannel selection modes, the channels in this partition are controlled by transmit channel
enable register B (XCERB).
Figure 21-32 shows an example of alternating between the channels of partition A and the channels of
partition B. Channels 0-15 have been assigned to partition A, and channels 16-31 have been assigned to
partition B. In response to a frame-synchronization pulse, the McBSP begins a frame transfer with partition
A and then alternates between partitions B and A until the complete frame is transferred.
Figure 21-32. Alternating Between the Channels of Partition A and the Channels of Partition B
Two-partition mode. Example with fixed block assignments
Partition
Block
Channels
FS(R/X)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
A

B

A

B

A

B

A

B

A

0

1

0

1

0

1

0

1

0

0-15

16-31

0-15

16-31

0-15

16-31

0-15

16-31

0-15

As explained in Section 21.6.4.2, you can dynamically change which blocks of channels are assigned to
the partitions.
21.6.4.2 Reassigning Blocks During Reception/Transmission
If you want to use more than 32 channels, you can change which channel blocks are assigned to
partitions A and B during the course of a data transfer. However, these changes must be carefully timed.
While a partition is being transferred, its associated block assignment bits cannot be modified and its
associated channel enable register cannot be modified. For example, if block 3 is being transferred and
block 3 is assigned to partition A, you can modify neither (R/X)PABLK to assign different channels to
partition A nor (R/X)CERA to change the channel configuration for partition A.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2269

Multichannel Selection Modes

www.ti.com

Several features of the McBSP help you time the reassignment:
• The block of channels currently involved in reception/transmission (the current block) is reflected in the
RCBLK/XCBLK bits. Your program can poll these bits to determine which partition is active. When a
partition is not active, it is safe to change its block assignment and channel configuration.
• At the end of every block (at the boundary of two partitions), an interrupt can be sent to the CPU. In
response to the interrupt, the CPU can then check the RCBLK/XCBLK bits and update the inactive
partition. See Section 21.6.8.
Figure 21-33 shows an example of reassigning channels throughout a data transfer. In response to a
frame-synchronization pulse, the McBSP alternates between partitions A and B. Whenever partition B is
active, the CPU changes the block assignment for partition A. Whenever partition A is active, the CPU
changes the block assignment for partition B.
Figure 21-33. Reassigning Channel Blocks Throughout a McBSP Data Transfer
Two-partition mode. Example with changing block assignments

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Partition

A

B

A

B

A

B

A

B

A

Block

0

1

2

3

4

5

6

7

0

0-15

16-31

32-47

48-63

80-95

96-111

112-127

0-15

Channels

64-79

FS(R/X)

Block 2 assigned
to partition A

Block 4 assigned
to partition A

Block 3 assigned
to partition B

Block 6 assigned
to partition A

Block 5 assigned
to partition B

Block 0 assigned
to partition A

Block 7 assigned
to partition B

Block 1 assigned
to partition B

21.6.5 Using Eight Partitions
For multichannel selection operation in the receiver and/or the transmitter, you can use eight partitions or
two partitions (described in Section 21.6.4). If you choose the 8-partition mode (RMCME = 1 for reception,
XMCME = 1 for transmission), McBSP channels are activated in the following order: A, B, C, D, E, F, G,
H. In response to a frame-synchronization pulse, the receiver or transmitter begins with the channels in
partition A and then continues with the other partitions in order until the complete frame has been
transferred. When the next frame-synchronization pulse occurs, the next frame is transferred, beginning
with the channels in partition A.
In the 8-partition mode, the (R/X)PABLK and (R/X)PBBLK bits are ignored and the 16-channel blocks are
assigned to the partitions as shown in Table 21-11 and Table 21-12. These assignments cannot be
changed. The tables also show the registers used to control the channels in the partitions.
Table 21-11. Receive Channel Assignment and Control With Eight Receive Partitions
Receive Partition

2270

Assigned Block of Receive Channels

Register Used For Channel Control

A

Block 0: channels 0 through 15

RCERA

B

Block 1: channels 16 through 31

RCERB

C

Block 2: channels 32 through 47

RCERC

D

Block 3: channels 48 through 63

RCERD

E

Block 4: channels 64 through 79

RCERE

F

Block 5: channels 80 through 95

RCERF

G

Block 6: channels 96 through 111

RCERG

H

Block 7: channels 112 through 127

RCERH

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Multichannel Selection Modes

www.ti.com

Table 21-12. Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used
Transmit Partition

Assigned Block of Transmit Channels

Register Used For Channel Control

A

Block 0: channels 0 through 15

XCERA

B

Block 1: channels 16 through 31

XCERB

C

Block 2: channels 32 through 47

XCERC

D

Block 3: channels 48 through 63

XCERD

E

Block 4: channels 64 through 79

XCERE

F

Block 5: channels 80 through 95

XCERF

G

Block 6: channels 96 through 111

XCERG

H

Block 7: channels 112 through 127

XCERH

Figure 21-34 shows an example of the McBSP using the 8-partition mode. In response to a framesynchronization pulse, the McBSP begins a frame transfer with partition A and then activates B, C, D, E,
F, G, and H to complete a 128-word frame.
Figure 21-34. McBSP Data Transfer in the 8-Partition Mode
Eight-partition mode

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Partition

A

B

C

D

E

F

G

H

A

Block

0

1

2

3

4

5

6

7

0

0-15

16-31

32-47

48-63

80-95

96-111

112-127

0-15

Channels

64-79

FS(R/X)

21.6.6 Receive Multichannel Selection Mode
The RMCM bit of MCR1 determines whether all channels or only selected channels are enabled for
reception. When RMCM = 0, all 128 receive channels are enabled and cannot be disabled. When RMCM
= 1, the receive multichannel selection mode is enabled. In this mode:
• Channels can be individually enabled or disabled. The only channels enabled are those selected in the
appropriate receive channel enable registers (RCERs). The way channels are assigned to the RCERs
depends on the number of receive channel partitions (2 or 8), as defined by the RMCME bit of MCR1.
• If a receive channel is disabled, any bits received in that channel are passed only as far as the receive
buffer register(s) (RBR(s)). The receiver does not copy the content of the RBR(s) to the DRR(s), and
as a result, does not set the receiver ready bit (RRDY). Therefore, no DMA synchronization event
(REVT) is generated and, if the receiver interrupt mode depends on RRDY (RINTM = 00b), no interrupt
is generated.
As an example of how the McBSP behaves in the receive multichannel selection mode, suppose you
enable only channels 0, 15, and 39 and that the frame length is 40. The McBSP:
1. Accepts bits shifted in from the DR pin in channel 0
2. Ignores bits received in channels 1-14
3. Accepts bits shifted in from the DR pin in channel 15
4. Ignores bits received in channels 16-38
5. Accepts bits shifted in from the DR pin in channel 39

21.6.7 Transmit Multichannel Selection Modes
The XMCM bits of XCR2 determine whether all channels or only selected channels are enabled and
unmasked for transmission. More details on enabling and masking are in Section 21.6.7.1. The McBSP
has three transmit multichannel selection modes (XMCM = 01b, XMCM = 10b, and XMCM = 11b), which
are described in the following table.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2271

Multichannel Selection Modes

www.ti.com

Table 21-13. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits
XMCM

Transmit Multichannel Selection Mode

00b

No transmit multichannel selection mode is on. All channels are enabled and unmasked. No channels
can be disabled or masked.

01b

All channels are disabled unless they are selected in the appropriate transmit channel enable registers
(XCERs). If enabled, a channel in this mode is also unmasked.
The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in XCERs.

10b

All channels are enabled, but they are masked unless they are selected in the appropriate transmit
channel enable registers (XCERs).
The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in XCERs.

11b

This mode is used for symmetric transmission and reception.
All channels are disabled for transmission unless they are enabled for reception in the appropriate
receive channel enable registers (RCERs). Once enabled, they are masked unless they are also
selected in the appropriate transmit channel enable registers (XCERs).
The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in RCERs
and XCERs.

As an example of how the McBSP behaves in a transmit multichannel selection mode, suppose that
XMCM = 01b (all channels disabled unless individually enabled) and that you have enabled only channels
0, 15, and 39. Suppose also that the frame length is 40. The McBSP:…
1. Shifts data to the DX pin in channel 0
2. Places the DX pin in the high impedance state in channels 1-14
3. Shifts data to the DX pin in channel 15
4. Places the DX pin in the high impedance state in channels 16-38
5. Shifts data to the DX pin in channel 39
21.6.7.1 Disabling/Enabling Versus Masking/Unmasking
For transmission, a channel can be:
• Enabled and unmasked (transmission can begin and can be completed)
• Enabled but masked (transmission can begin but cannot be completed)
• Disabled (transmission cannot occur)
The following definitions explain the channel control options:
Enabled channel

A channel that can begin transmission by passing data from the data transmit register(s)
(DXR(s)) to the transmit shift registers (XSR(s)).
A channel that cannot complete transmission. The DX pin is held in the high impedance
state; data cannot be shifted out on the DX pin.
In systems where symmetric transmit and receive provides software benefits, this feature
allows transmit channels to be disabled on a shared serial bus. A similar feature is not
needed for reception because multiple receptions cannot cause serial bus contention.
A channel that is not enabled. A disabled channel is also masked.
Because no DXR-to-XSR copy occurs, the XRDY bit of SPCR2 is not set. Therefore, no
DMA synchronization event (XEVT) is generated, and if the transmit interrupt mode
depends on XRDY (XINTM = 00b in SPCR2), no interrupt is generated.
The XEMPTY bit of SPCR2 is not affected.
A channel that is not masked. Data in the XSR(s) is shifted out on the DX pin.

Masked channel

Disabled channel

Unmasked channel

21.6.7.2 Activity on McBSP Pins for Different Values of XMCM
Figure 21-35 shows the activity on the McBSP pins for the various XMCM values. In all cases, the
transmit frame is configured as follows:
• XPHASE = 0: Single-phase frame (required for multichannel selection modes)
• XFRLEN1 = 0000011b: 4 words per frame
2272

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Multichannel Selection Modes

www.ti.com

•
•

XWDLEN1 = 000b: 8 bits per word
XMCME = 0: 2-partition mode (only partitions A and B used)

In the case where XMCM = 11b, transmission and reception are symmetric, which means the
corresponding bits for the receiver (RPHASE, RFRLEN1, RWDLEN1, and RMCME) must have the same
values as XPHASE, XFRLEN1, and XWDLEN1, respectively.
In the figure, the arrows showing where the various events occur are only sample indications. Wherever
possible, there is a time window in which these events can occur.

21.6.8 Using Interrupts Between Block Transfers
When a multichannel selection mode is used, an interrupt request can be sent to the CPU at the end of
every 16-channel block (at the boundary between partitions and at the end of the frame). In the receive
multichannel selection mode, a receive interrupt (RINT) request is generated at the end of each block
transfer if RINTM = 01b. In any of the transmit multichannel selection modes, a transmit interrupt (XINT)
request is generated at the end of each block transfer if XINTM = 01b. When RINTM/XINTM = 01b, no
interrupt is generated unless a multichannel selection mode is on.
These interrupt pulses are active high and last for two CPU clock cycles.
This type of interrupt is especially helpful if you are using the two-partition mode (described in
Section 21.6.4) and you want to know when you can assign a different block of channels to partition A or
B.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2273

SPI Operation Using the Clock Stop Mode

www.ti.com

Figure 21-35. Activity on McBSP Pins for the Possible Values of XMCM

ÁÁ
Á
ÁÁ Á
ÁÁ Á

(a) XMCM = 00b: All channels enabled and unmasked
Internal FSX
DX
XRDY

W0

Write to DXR1(W1)
DXR1 to XSR1 copy(W0)
DXR1 to XSR1 copy(W1)

ÁÁ
ÁÁ
ÁÁ
ÁÁ

W1

Á
Á
Á
Á

W2

W3

Write to DXR1(W3)
DXR1 to XSR1 copy(W2)
DXR1 to XSR1 copy(W3)
Write to DXR1(W2)

Á
Á
Á
Á

Á
Á
Á
Á

(b) XMCM = 01b, XPABLK = 00b, XCERA = 1010b: Only channels 1 and 3 enabled and unmasked
Internal FSX
DX
XRDY

ÁÁ
ÁÁ
ÁÁ
ÁÁ

W1

Write to DXR1(W3)

Á
Á
Á
Á

DXR1 to XSR1 copy(W1)

Á
Á
Á
Á

W3

DXR1 to XSR1 copy(W3)

Á
Á
Á
Á

(c) XMCM = 10b, XPABLK = 00b, XCERA = 1010b: All channels enabled, only 1 and 3 unmasked
Internal FSX
DX
XRDY

W3

Write to DXR1(W3)
DXR1 to XSR1 copy(W2)
DXR1 to XSR1 copy(W3)
Write to DXR1(W2)

Write to DXR1(W1)
DXR1 to XSR1 copy(W0)
DXR1 to XSR1 copy(W1)

Á
Á
Á
Á
Á
Á
Á

W1

Á
Á
Á

Á
Á
Á

Á
Á
Á
Á
Á
Á
Á

(d) XMCM = 11b, RPABLK = 00b, XPABLK = X, RCERA = 1010b, XCERA = 1000b:
Receive channels: 1 and 3 enabled; transmit channels: 1 and 3 enabled, but only 3 unmasked
Internal FS(R/X)
DR
RRDY

DX
XRDY

DXR1 to XSR1 copy (W1)

Á
Á
Á
Á

W1

Read From DRR1(W3)
RBR1 to DRR1 copy (W3)

Write to DXR1(W3)

W3

Á
Á
Á
Á
Á
Á
Á

Read From DRR1(W1)
RBR1 to DRR1 copy (W1)
RBR1 to DRR1 (W3)
W3

DXR1 to XSR1 copy (W3)

21.7 SPI Operation Using the Clock Stop Mode
This chapter explains how to use the McBSP in SPI mode.

21.7.1 SPI Protocol
The SPI protocol is a master-slave configuration with one master device and one or more slave devices.
The interface consists of the following four signals:
• Serial data input (also referred to as master in/slave out, or SPISOMI)
2274

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

SPI Operation Using the Clock Stop Mode

www.ti.com

•
•
•

Serial data output (also referred to as master out/slave in, or SPISIMO)
Shift-clock (also referred to as SPICLK)
Slave-enable signal (also referred to as SPISTE)

A typical SPI interface with a single slave device is shown in Figure 21-36.
Figure 21-36. Typical SPI Interface
SPI-compliant
master

SPI-compliant
slave

SPICLK

SPICLK

SPISIMO

SPISIMO

SPISOMI

SPISOMI

SPISTE

SPISTE

The master device controls the flow of communication by providing shift-clock and slave-enable signals.
The slave-enable signal is an optional active-low signal that enables the serial data input and output of the
slave device (device not sending out the clock).
In the absence of a dedicated slave-enable signal, communication between the master and slave is
determined by the presence or absence of an active shift-clock. When the McBSP is operating in SPI
master mode and the SPISTE signal is not used by the slave SPI port, the slave device must remain
enabled at all times, and multiple slaves cannot be used.

21.7.2 Clock Stop Mode
The clock stop mode of the McBSP provides compatibility with the SPI protocol. When the McBSP is
configured in clock stop mode, the transmitter and receiver are internally synchronized so that the McBSP
functions as an SPI master or slave device. The transmit clock signal (CLKX) corresponds to the serial
clock signal (SPICLK) of the SPI protocol, while the transmit frame-synchronization signal (FSX) is used
as the slave-enable signal (SPISTE).
The receive clock signal (MCLKR) and receive frame-synchronization signal (FSR) are not used in the
clock stop mode because these signals are internally connected to their transmit counterparts, CLKX and
FSX.

21.7.3 Bits Used to Enable and Configure the Clock Stop Mode
The bits required to configure the McBSP as an SPI device are introduced in Table 21-14. Table 21-15
shows how the various combinations of the CLKSTP bit and the polarity bits CLKXP and CLKRP create
four possible clock stop mode configurations. The timing diagrams in Section 21.7.4 show the effects of
CLKSTP, CLKXP, and CLKRP.
Table 21-14. Bits Used to Enable and Configure the Clock Stop Mode
Bit Field

Description

CLKSTP bits of SPCR1

Use these bits to enable the clock stop mode and to select one of two timing variations.
(See also Table 21-15.)

CLKXP bit of PCR

This bit determines the polarity of the CLKX signal. (See also Table 21-15.)

CLKRP bit of PCR

This bit determines the polarity of the MCLKR signal. (See also Table 21-15.)

CLKXM bit of PCR

This bit determines whether CLKX is an input signal (McBSP as slave) or an output
signal (McBSP as master).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP) 2275

Copyright © 2013–2017, Texas Instruments Incorporated

SPI Operation Using the Clock Stop Mode

www.ti.com

Table 21-14. Bits Used to Enable and Configure the Clock Stop Mode (continued)
Bit Field

Description

XPHASE bit of XCR2

You must use a single-phase transmit frame (XPHASE = 0).

RPHASE bit of RCR2

You must use a single-phase receive frame (RPHASE = 0).

XFRLEN1 bits of XCR1

You must use a transmit frame length of 1 serial word (XFRLEN1 = 0).

RFRLEN1 bits of RCR1

You must use a receive frame length of 1 serial word (RFRLEN1 = 0).

XWDLEN1 bits of XCR1

The XWDLEN1 bits determine the transmit packet length. XWDLEN1 must be equal to
RWDLEN1 because in the clock stop mode. The McBSP transmit and receive circuits
are synchronized to a single clock.

RWDLEN1 bits of RCR1

The RWDLEN1 bits determine the receive packet length. RWDLEN1 must be equal to
XWDLEN1 because in the clock stop mode. The McBSP transmit and receive circuits
are synchronized to a single clock.

Table 21-15. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
Bit Settings

Clock Scheme

CLKSTP = 00b or 01b

Clock stop mode disabled. Clock enabled for non-SPI mode.

CLKXP = 0 or 1
CLKRP = 0 or 1
CLKSTP = 10b
CLKXP = 0

Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and
receives data on the falling edge of MCLKR.

CLKRP = 0
CLKSTP = 11b
CLKXP = 0

Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising
edge of CLKX and receives data on the rising edge of MCLKR.

CLKRP = 1
CLKSTP = 10b
CLKXP = 1

High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and
receives data on the rising edge of MCLKR.

CLKRP = 0
CLKSTP = 11b
CLKXP = 1

High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling
edge of CLKX and receives data on the falling edge of MCLKR.

CLKRP = 1

21.7.4 Clock Stop Mode Timing Diagrams
The timing diagrams for the four possible clock stop mode configurations are shown here. Notice that the
frame-synchronization signal used in clock stop mode is active throughout the entire transmission as a
slave-enable signal. Although the timing diagrams show 8-bit transfers, the packet length can be set to 8,
12, 16, 20, 24, or 32 bits per packet. The receive packet length is selected with the RWDLEN1 bits of
RCR1, and the transmit packet length is selected with the XWDLEN1 bits of XCR1. For clock stop mode,
the values of RWDLEN1 and XWDLEN1 must be the same because the McBSP transmit and receive
circuits are synchronized to a single clock.
NOTE: Even if multiple words are consecutively transferred, the CLKX signal is always stopped and
the FSX signal returns to the inactive state after a packet transfer. When consecutive packet
transfers are performed, this leads to a minimum idle time of two bit-periods between each
packet transfer.

2276

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

SPI Operation Using the Clock Stop Mode

www.ti.com

Figure 21-37. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 0, and CLKRP = 0
CLKX/SPICLK
DX or DR/SIMO
(from master)
DX or DR/SOMI
(from slave)

B7
B7

B6

B5

B4

B3

B2

B1

B0

B6

B5

B4

B3

B2

B1

B0

FSX/SPISTE
A

If the McBSP is the SPI master (CLKXM = 1), SIMO = DX. If the McBSP is the SPI slave (CLKXM = 0), SIMO = DR.

B

If the McBSP is the SPI master (CLKXM = 1), SOMI = DR. If the McBSP is the SPI slave (CLKXM = 0), SOMI = DX.

Figure 21-38. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1
CLKX/SPICLK
DX or DR/SIMO
(from master)
DX or DR/SOMI
(from slave)

B7
B7

B6

B5

B4

B3

B2

B1

B0

B6

B5

B4

B3

B2

B1

B0

FSX/SPISTE
A

If the McBSP is the SPI master (CLKXM = 1), SIMO = DX. If the McBSP is the SPI slave (CLKXM = 0), SIMO = DR.

B

If the McBSP is the SPI master (CLKXM = 1), SOMI = DR. If the McBSP is the SPI slave (CLKXM = 0), SOMI = DX.

Figure 21-39. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0
CLKX/SPICLK
DX or DR/SIMO
(from master)
DX or DR/SOMI
(from slave)

B7
B7

B6

B5

B4

B3

B2

B1

B0

B6

B5

B4

B3

B2

B1

B0

FSX/SPISTE
A

If the McBSP is the SPI master (CLKXM = 1), SIMO = DX. If the McBSP is the SPI slave (CLKXM = 0), SIMO = DR.

B

If the McBSP is the SPI master (CLKXM = 1), SOMI = DR. If the McBSP is the SPI slave (CLKXM = 0), SOMI = DX.

Figure 21-40. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1
CLKX/SPICLK
DX or DR/SIMO
(from master)
DX or DR/SOMI
(from slave)

B7
B7

B6

B5

B4

B3

B2

B1

B0

B6

B5

B4

B3

B2

B1

B0

FSX/SPISTE
A

If the McBSP is the SPI master (CLKXM = 1), SIMO=DX. If the McBSP is the SPI slave (CLKXM = 0), SIMO = DR.

B

If the McBSP is the SPI master (CLKXM = 1), SOMI=DR. If the McBSP is the SPI slave (CLKXM = 0), SOMI = DX.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2277

SPI Operation Using the Clock Stop Mode

www.ti.com

21.7.5 Procedure for Configuring a McBSP for SPI Operation
To configure the McBSP for SPI master or slave operation:
Step 1. Place the transmitter and receiver in reset.
Clear the transmitter reset bit (XRST = 0) in SPCR2 to reset the transmitter. Clear the receiver reset bit
(RRST = 0) in SPCR1 to reset the receiver.
Step 2. Place the sample rate generator in reset.
Clear the sample rate generator reset bit (GRST = 0) in SPCR2 to reset the sample rate generator.
Step 3. Program registers that affect SPI operation.
Program the appropriate McBSP registers to configure the McBSP for proper operation as an SPI
master or an SPI slave. For a list of important bits settings, see one of the following topics:
• McBSP as the SPI Master ( Section 21.7.6)
• McBSP as an SPI Slave ( Section 21.7.7)
Step 4. Enable the sample rate generator.
To release the sample rate generator from reset, set the sample rate generator reset bit (GRST = 1) in
SPCR2.
Make sure that during the write to SPCR2, you only modify GRST. Otherwise, you modify the McBSP
configuration you selected in the previous step.
Step 5. Enable the transmitter and receiver.
After the sample rate generator is released from reset, wait two sample rate generator clock periods for
the McBSP logic to stabilize.
If the CPU services the McBSP transmit and receive buffers, then you can immediately enable the
transmitter (XRST = 1 in SPCR2) and enable the receiver (RRST = 1 in SPCR1).
If the DMA controller services the McBSP transmit and receive buffers, then you must first configure
the DMA controller (this includes enabling the channels that service the McBSP buffers). When the
DMA controller is ready, make XRST = 1 and RRST = 1.
In either case, make sure you only change XRST and RRST when you write to SPCR2 and SPCR1.
Otherwise, you modify the bit settings you selected earlier in this procedure.
After the transmitter and receiver are released from reset, wait two sample rate generator clock periods
for the McBSP logic to stabilize.
Step 6. If necessary, enable the frame-synchronization logic of the sample rate generator.
After the required data acquisition setup is done (DXR[1,2] is loaded with data), set FRST = 1 if an
internally generated frame-synchronization pulse is required (that is, if the McBSP is the SPI master).

21.7.6 McBSP as the SPI Master
An SPI interface with the McBSP used as the master is shown in Figure 21-41. When the McBSP is
configured as a master, the transmit output signal (DX) is used as the SPISIMO signal of the SPI protocol
and the receive input signal (DR) is used as the SPISOMI signal.
The register bit values required to configure the McBSP as a master are listed in Table 21-16. After the
table are more details about the configuration requirements.

2278

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

SPI Operation Using the Clock Stop Mode

www.ti.com

Figure 21-41. SPI Interface with McBSP Used as Master
McBSP master
CLKX

SPI-compliant
slave
SPICLK

DX

SPISIMO

DR

SPISOMI

FSX

SPISTE

Table 21-16. Bit Values Required to Configure the McBSP as an SPI Master
Required Bit Setting

Description

CLKSTP = 10b or 11b

The clock stop mode (without or with a clock delay) is selected.

CLKXP = 0 or 1

The polarity of CLKX as seen on the MCLKX pin is positive (CLKXP = 0) or negative (CLKXP =
1).

CLKRP = 0 or 1

The polarity of MCLKR as seen on the MCLKR pin is positive (CLKRP = 0) or negative
(CLKRP = 1).

CLKXM = 1

The MCLKX pin is an output pin driven by the internal sample rate generator. Because
CLKSTP is equal to 10b or 11b, MCLKR is driven internally by CLKX.

SCLKME = 0

The clock generated by the sample rate generator (CLKG) is derived from the CPU clock.

CLKSM = 1
CLKGDV is a value from 1 to 255

CLKGDV defines the divide down value for CLKG.

FSXM = 1

The FSX pin is an output pin driven according to the FSGM bit.

FSGM = 0

The transmitter drives a frame-synchronization pulse on the FSX pin every time data is
transferred from DXR1 to XSR1.

FSXP = 1

The FSX pin is active low.

XDATDLY = 01b

This setting provides the correct setup time on the FSX signal.

RDATDLY = 01b

When the McBSP functions as the SPI master, it controls the transmission of data by producing the serial
clock signal. The clock signal on the MCLKX pin is enabled only during packet transfers. When packets
are not being transferred, the MCLKX pin remains high or low depending on the polarity used.
For SPI master operation, the MCLKX pin must be configured as an output. The sample rate generator is
then used to derive the CLKX signal from the CPU clock. The clock stop mode internally connects the
MCLKX pin to the MCLKR signal so that no external signal connection is required on the MCLKR pin and
both the transmit and receive circuits are clocked by the master clock (CLKX).
The data delay parameters of the McBSP (XDATDLY and RDATDLY) must be set to 1 for proper SPI
master operation. A data delay value of 0 or 2 is undefined in the clock stop mode.
The McBSP can also provide a slave-enable signal (SS_) on the FSX pin. If a slave-enable signal is
required, the FSX pin must be configured as an output and the transmitter must be configured so that a
frame-synchronization pulse is generated automatically each time a packet is transmitted (FSGM = 0).
The polarity of the FSX pin is programmable high or low; however, in most cases the pin must be
configured active low.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2279

SPI Operation Using the Clock Stop Mode

www.ti.com

When the McBSP is configured as described for SPI-master operation, the bit fields for framesynchronization pulse width (FWID) and frame-synchronization period (FPER) are overridden, and custom
frame-synchronization waveforms are not allowed. To see the resulting waveform produced on the FSX
pin, see the timing diagrams in Section 21.7.4. The signal becomes active before the first bit of a packet
transfer, and remains active until the last bit of the packet is transferred. After the packet transfer is
complete, the FSX signal returns to the inactive state.

21.7.7 McBSP as an SPI Slave
An SPI interface with the McBSP used as a slave is shown in Figure 21-42. When the McBSP is
configured as a slave, DX is used as the SPISOMI signal and DR is used as the SPISIMO signal.
The register bit values required to configure the McBSP as a slave are listed in Table 21-17. Following the
table are more details about configuration requirements.
Figure 21-42. SPI Interface With McBSP Used as Slave
McBSP slave
CLKX

SPI-compliant
master
SPICLK

DX

SPISOMI

DR

SPISIMO

FSX

SPISTE

Table 21-17. Bit Values Required to Configure the McBSP as an SPI Slave
Required Bit Setting

Description

CLKSTP = 10b or 11b

The clock stop mode (without or with a clock delay) is selected.

CLKXP = 0 or 1

The polarity of CLKX as seen on the MCLKX pin is positive (CLKXP = 0) or negative (CLKXP =
1).

CLKRP = 0 or 1

The polarity of MCLKR as seen on the MCLKR pin is positive (CLKRP = 0) or negative
(CLKRP = 1).

CLKXM = 0

The MCLKX pin is an input pin, so that it can be driven by the SPI master. Because CLKSTP =
10b or 11b, MCLKR is driven internally by CLKX.

SCLKME = 0

The clock generated by the sample rate generator (CLKG) is derived from the CPU clock. (The
sample rate generator is used to synchronize the McBSP logic with the externally-generated
master clock.)

CLKSM = 1
CLKGDV = 1

The sample rate generator divides the CPU clock before generating CLKG.

FSXM = 0

The FSX pin is an input pin, so that it can be driven by the SPI master.

FSXP = 1

The FSX pin is active low.

XDATDLY = 00b

These bits must be 0s for SPI slave operation.

RDATDLY = 00b

When the McBSP is used as an SPI slave, the master clock and slave-enable signals are generated
externally by a master device. Accordingly, the CLKX and FSX pins must be configured as inputs. The
MCLKX pin is internally connected to the MCLKR signal, so that both the transmit and receive circuits of
the McBSP are clocked by the external master clock. The FSX pin is also internally connected to the FSR
signal, and no external signal connections are required on the MCLKR and FSR pins.

2280

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

Although the CLKX signal is generated externally by the master and is asynchronous to the McBSP, the
sample rate generator of the McBSP must be enabled for proper SPI slave operation. The sample rate
generator must be programmed to its maximum rate of half the CPU clock rate. The internal sample rate
clock is then used to synchronize the McBSP logic to the external master clock and slave-enable signals.
The McBSP requires an active edge of the slave-enable signal on the FSX input for each transfer. This
means that the master device must assert the slave-enable signal at the beginning of each transfer, and
deassert the signal after the completion of each packet transfer; the slave-enable signal cannot remain
active between transfers. Unlike the standard SPI, this pin cannot be tied low all the time.
The data delay parameters of the McBSP must be set to 0 for proper SPI slave operation. A value of 1 or
2 is undefined in the clock stop mode.

21.8 Receiver Configuration
To
1.
2.
3.

configure the McBSP receiver, perform the following procedure:
Place the McBSP/receiver in reset (see Section 21.8.2).
Program McBSP registers for the desired receiver operation (see Section 21.8.1).
Take the receiver out of reset (see Section 21.8.2).

21.8.1 Programming the McBSP Registers for the Desired Receiver Operation
The following is a list of important tasks to be performed when you are configuring the McBSP receiver.
Each task corresponds to one or more McBSP register bit fields.
• Global behavior:
– Set the receiver pins to operate as McBSP pins.
– Enable/disable the digital loopback mode.
– Enable/disable the clock stop mode.
– Enable/disable the receive multichannel selection mode.
• Data behavior:
– Choose 1 or 2 phases for the receive frame.
– Set the receive word length(s).
– Set the receive frame length.
– Enable/disable the receive frame-synchronization ignore function.
– Set the receive companding mode.
– Set the receive data delay.
– Set the receive sign-extension and justification mode.
– Set the receive interrupt mode.
• Frame-synchronization behavior:
– Set the receive frame-synchronization mode.
– Set the receive frame-synchronization polarity.
– Set the sample rate generator (SRG) frame-synchronization period and pulse width.
• Clock behavior:
– Set the receive clock mode.
– Set the receive clock polarity.
– Set the SRG clock divide-down value.
– Set the SRG clock synchronization mode.
– Set the SRG clock mode (choose an input clock).
– Set the SRG input clock polarity.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2281

Receiver Configuration

www.ti.com

21.8.2 Resetting and Enabling the Receiver
The first step of the receiver configuration procedure is to reset the receiver, and the last step is to enable
the receiver (to take it out of reset). Table 21-18 describes the bits used for both of these steps.
Table 21-18. Register Bits Used to Reset or Enable the McBSP Receiver Field Descriptions
Register

Bit

Field

SPCR2

7

FRST

SPCR2

SPCR1

6

Value

Frame-synchronization logic reset
0

Frame-synchronization logic is reset. The sample rate generator does not generate framesynchronization signal FSG, even if GRST = 1.

1

If GRST = 1, frame-synchronization signal FSG is generated after (FPER + 1) number of
CLKG clock cycles; all frame counters are loaded with their programmed values.

GRST

0

Description

Sample rate generator reset
0

Sample rate generator is reset. If GRST = 0 due to a DSP reset, CLKG is driven by the
CPU clock divided by 2, and FSG is driven low (inactive). If GRST = 0 due to program
code, CLKG and FSG are both driven low (inactive).

1

Sample rate generator is enabled. CLKG is driven according to the configuration
programmed in the sample rate generator registers (SRGR[1,2]). If FRST = 1, the
generator also generates the frame-synchronization signal FSG as programmed in the
sample rate generator registers.

RRST

Receiver reset
0

The serial port receiver is disabled and in the reset state.

1

The serial port receiver is enabled.

21.8.2.1 Reset Considerations
The serial port can be reset in the following two ways:
1. The DSP reset (XRS signal driven low) places the receiver, transmitter, and sample rate generator in
reset. When the device reset is removed (XRS signal released), GRST = FRST = RRST = XRST = 0
keep the entire serial port in the reset state, provided the McBSP clock is turned on.
2. The serial port transmitter and receiver can be reset directly using the RRST and XRST bits in the
serial port control registers. The sample rate generator can be reset directly using the GRST bit in
SPCR2.
Table 21-19 shows the state of McBSP pins when the serial port is reset due to a device reset and a
direct receiver/transmitter reset.
For more details about McBSP reset conditions and effects, see Section 21.10.2.
Table 21-19. Reset State of Each McBSP Pin
Pin

Possible
State(s)

State Forced By
Device Reset

State Forced By Receiver Reset
(RRST = 0 and GRST = 1)

MDRx

I

GPIO Input

Input

MCLKRx

I/O/Z

GPIO Input

Known state if input; MCLKR running if output

MFSRx

I/O/Z

GPIO Input

Known state if input; FSRP inactive state if output

MDXx

O/Z

GPIO Input

Low impedance after transmit bit clock provided

MCLKXx

I/O/Z

GPIO Input

Known state if input; CLKX running if output

MFSXx

I/O/Z

GPIO Input

Known state if input; FSXP inactive state if output

Transmitter reset (XRST = 0 and GRST = 1)

21.8.3 Set the Receiver Pins to Operate as McBSP Pins
To configure a pin for its McBSP function , you should configure the bits of the GPxMUXn register
appropriately. In addition to this, bits 12 and 13 of the PCR register must be set to 0. These bits are
defined as reserved.

2282

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

21.8.4 Enable/Disable the Digital Loopback Mode
The DLB bit determines whether the digital loopback mode is on. DLB is described in Table 21-20.
Table 21-20. Register Bit Used to Enable/Disable the Digital Loopback Mode
Register

Bit

Name

Function

Type

Reset
Value

SPCR1

15

DLB

Digital loopback mode

R/W

0

DLB = 0

Digital loopback mode is disabled.

DLB = 1

Digital loopback mode is enabled.

21.8.4.1 Digital Loopback Mode
In the digital loopback mode, the receive signals are connected internally through multiplexers to the
corresponding transmit signals, as shown in Table 21-21. This mode allows testing of serial port code with
a single DSP device; the McBSP receives the data it transmits.
Table 21-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode
This Receive Signal

Is Fed Internally by
This Transmit Signal

MDR (receive data)

MDX (transmit data)

MFSR (receive frame synchronization)

MFSX (transmit frame synchronization)

MCLKR (receive clock)

MCLKX (transmit clock)

21.8.5 Enable/Disable the Clock Stop Mode
The CLKSTP bits determine whether the clock stop mode is on. CLKSTP is described in Table 21-22.
Table 21-22. Register Bits Used to Enable/Disable the Clock Stop Mode
Register
SPCR1

Bit
12-11

Name

Function

CLKSTP

Clock stop mode
CLKSTP = 0Xb

Clock stop mode disabled; normal clocking for
non-SPI mode

CLKSTP = 10b

Clock stop mode enabled, without clock delay

CLKSTP = 11b

Clock stop mode enabled, with clock delay

Type

Reset
Value

R/W

00

21.8.5.1 Clock Stop Mode
The clock stop mode supports the SPI master-slave protocol. If you do not plan to use the SPI protocol,
you can clear CLKSTP to disable the clock stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each data
transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b). The
CLKXP bit determines whether the starting edge of the clock on the MCLKX pin is rising or falling. The
CLKRP bit determines whether receive data is sampled on the rising or falling edge of the clock shown on
the MCLKR pin.
Table 21-23 summarizes the impact of CLKSTP, CLKXP, and CLKRP on serial port operation. In the clock
stop mode, the receive clock is tied internally to the transmit clock, and the receive frame-synchronization
signal is tied internally to the transmit frame-synchronization signal.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP) 2283

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

Table 21-23. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
Bit Settings

Clock Scheme

CLKSTP = 00b or 01b

Clock stop mode disabled. Clock enabled for non-SPI mode.

CLKXP = 0 or 1
CLKRP = 0 or 1
CLKSTP = 10b

Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and receives data on the
falling edge of MCLKR.

CLKXP = 0
CLKRP = 0
CLKSTP = 11b

Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising edge of CLKX and
receives data on the rising edge of MCLKR.

CLKXP = 0
CLKRP = 1
CLKSTP = 10b

High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and receives data on the
rising edge of MCLKR.

CLKXP = 1
CLKRP = 0
CLKSTP = 11b

High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling edge of CLKX and
receives data on the falling edge of MCLKR.

CLKXP = 1
CLKRP = 1

21.8.6 Enable/Disable the Receive Multichannel Selection Mode
The RMCM bit determines whether the receive multichannel selection mode is on. RMCM is described in
Table 21-24. For more details, see Section 21.6.6.
Table 21-24. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode
Register

Bit

Name

Function

0

RMCM

Receive multichannel selection mode

MCR1

RMCM = 0

Type

Reset
Value

R/W

0

The mode is disabled.
All 128 channels are enabled.

RMCM = 1

The mode is enabled.
Channels can be individually enabled or disabled.
The only channels enabled are those selected in the
appropriate receive channel enable registers (RCERs).
The way channels are assigned to the RCERs
depends on the number of receive channel partitions
(2 or 8), as defined by the RMCME bit.

21.8.7 Choose One or Two Phases for the Receive Frame
The RPHASE bit (see Table 21-25) determines whether the receive data frame has one or two phases.
Table 21-25. Register Bit Used to Choose One or Two Phases for the Receive Frame
Register

Bit

Name

Function

Type

Reset
Value

RCR2

15

RPHASE

Receive phase number

R/W

0

Specifies whether the receive frame has 1 or 2 phases.

2284

RPHASE = 0

Single-phase frame

RPHASE = 1

Dual-phase frame

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

21.8.8 Set the Receive Word Length(s)
The RWDLEN1 and RWDLEN2 bit fields (see Table 21-26) determine how many bits are in each serial
word in phase 1 and in phase 2, respectively, of the receive data frame.
Table 21-26. Register Bits Used to Set the Receive Word Length(s)
Registe
r

Bit

Name

Function

Type

Reset
Value

RCR1

7-5

RWDLEN1

Receive word length 1

R/W

000

R/W

000

Specifies the length of every serial word in phase 1 of the receive frame.

RCR2

7-5

RWDLEN2

RWDLEN1 = 000

8 bits

RWDLEN1 = 001

12 bits

RWDLEN1 = 010

16 bits

RWDLEN1 = 011

20 bits

RWDLEN1 = 100

24 bits

RWDLEN1 = 101

32 bits

RWDLEN1 = 11X

Reserved

Receive word length 2
If a dual-phase frame is selected, RWDLEN2 specifies the length of every
serial word in phase 2 of the frame.
RWDLEN2 = 000

8 bits

RWDLEN2 = 001

12 bits

RWDLEN2 = 010

16 bits

RWDLEN2 = 011

20 bits

RWDLEN2 = 100

24 bits

RWDLEN2 = 101

32 bits

RWDLEN2 = 11X

Reserved

21.8.8.1 Word Length Bits
Each frame can have one or two phases, depending on the value that you load into the RPHASE bit. If a
single-phase frame is selected, RWDLEN1 selects the length for every serial word received in the frame. If
a dual-phase frame is selected, RWDLEN1 determines the length of the serial words in phase 1 of the
frame and RWDLEN2 determines the word length in phase 2 of the frame.

21.8.9 Set the Receive Frame Length
The RFRLEN1 and RFRLEN2 bit fields (see Table 21-27) determine how many serial words are in phase
1 and in phase 2, respectively, of the receive data frame.
Table 21-27. Register Bits Used to Set the Receive Frame Length
Regist
er

Bit

RCR1

14-8

Name

Function

Type

Reset
Value

RFRLEN1

Receive frame length 1

R/W

000 0000

(RFRLEN1 + 1) is the number of serial words in phase 1 of the receive frame.
RFRLEN1 = 000 0000

1 word in phase 1

RFRLEN1 = 000 0001

2 words in phase 1

|

|

|

|

RFRLEN1 = 111 1111

128 words in phase 1

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP) 2285

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

Table 21-27. Register Bits Used to Set the Receive Frame Length (continued)
Regist
er

Bit

RCR2

14-8

Name

Function

Type

Reset
Value

RFRLEN2

Receive frame length 2

R/W

000 0000

If a dual-phase frame is selected, (RFRLEN2 + 1) is the number of serial
words in phase 2 of the receive frame.
RFRLEN2 = 000 0000

1 word in phase 2

RFRLEN2 = 000 0001

2 words in phase 2

|

|

|

|

RFRLEN2 = 111 1111

128 words in phase 2

21.8.9.1 Selected Frame Length
The receive frame length is the number of serial words in the receive frame. Each frame can have one or
two phases, depending on value that you load into the RPHASE bit.
If a single-phase frame is selected (RPHASE = 0), the frame length is equal to the length of phase 1. If a
dual-phase frame is selected (RPHASE = 1), the frame length is the length of phase 1 plus the length of
phase 2.
The 7-bit RFRLEN fields allow up to 128 words per phase. See Table 21-28 for a summary of how to
calculate the frame length. This length corresponds to the number of words or logical time slots or
channels per frame-synchronization pulse.
Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For the
example, if you want a phase length of 128 words in phase 1, load 127 into RFRLEN1.
Table 21-28. How to Calculate the Length of the Receive Frame
RPHASE

RFRLEN1

RFRLEN2

Frame Length

0

0 ≤ RFRLEN1 ≤ 127

Don't care

(RFRLEN1 + 1) words

1

0 ≤ RFRLEN1 ≤ 127

0 ≤ RFRLEN2 ≤ 127

(RFRLEN1 + 1) + (RFRLEN2 + 1) words

21.8.10 Enable/Disable the Receive Frame-Synchronization Ignore Function
The RFIG bit (see Table 21-29) controls the receive frame-synchronization ignore function.
Table 21-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore
Function
Registe
r
RCR2

Bit

Name

Function

2

RFIG

Receive frame-synchronization ignore
RFIG = 0

An unexpected receive frame-synchronization pulse causes the
McBSP to restart the frame transfer.

RFIG = 1

The McBSP ignores unexpected receive frame-synchronization
pulses.

Type

Reset
Value

R/W

0

21.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
received, this pulse is treated as an unexpected frame-synchronization pulse.
When RFIG = 1, reception continues, ignoring the unexpected frame-synchronization pulses.

2286

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

When RFIG = 0, an unexpected FSR pulse causes the McBSP to discard the contents of RSR[1,2] in
favor of the new incoming data. Therefore, if RFIG = 0 and an unexpected frame-synchronization pulse
occurs, the serial port:
1. Aborts the current data transfer
2. Sets RSYNCERR in SPCR1 to 1
3. Begins the transfer of a new data word
For more details about the frame-synchronization error condition, see Section 21.5.3.
21.8.10.2 Examples of Effects of RFIG
Figure 21-43 shows an example in which word B is interrupted by an unexpected frame-synchronization
pulse when (R/X)FIG = 0. In the case of reception, the reception of B is aborted (B is lost), and a new data
word © in this example) is received after the appropriate data delay. This condition is a receive
synchronization error, which sets the RSYNCERR bit.
Figure 21-43. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0
CLK(R/X)
FS(R/X)
DR

A0

B7

B6

C7

DX

A0

B7

B6

B7

Frame synchronization aborts current transfer
New data received
C6
C5
C4
C3
C2
C1
C0
Current data retransmitted
B6
B5
B4
B3
B2
B1
B0

ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ

D7

D6

C7

C6

(R/X)SYNCERR

In contrast with Figure 21-43, Figure 21-44 shows McBSP operation when unexpected framesynchronization signals are ignored (when (R/X)FIG = 1). Here, the transfer of word B is not affected by
an unexpected pulse.
Figure 21-44. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 1
CLK(R/X)
Frame synchronization ignored

FS(R/X)
D(R/X)

A0

B7

B6

B5

B4

B3

B2

B1

B0

C7

C6

C5

(R/X)SYNCERR

ÁÁ
ÁÁ
ÁÁ
ÁÁ
C4

21.8.11 Set the Receive Companding Mode
The RCOMPAND bits (see Table 21-30) determine whether companding or another data transfer option is
chosen for McBSP reception.
Table 21-30. Register Bits Used to Set the Receive Companding Mode
Regist
er

Bit

Name

Function

Type

Reset
Value

RCR2

4-3

RCOMPAND

Receive companding mode

R/W

00

Modes other than 00b are enabled only when the appropriate RWDLEN is
000b, indicating 8-bit data.
RCOMPAND = 00

No companding, any size data, MSB received first

RCOMPAND = 01

No companding, 8-bit data, LSB received first (for details,
see Section 21.8.11.4).

RCOMPAND = 10

μ-law companding, 8-bit data, MSB received first

RCOMPAND = 11

A-law companding, 8-bit data, MSB received first

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2287

Receiver Configuration

www.ti.com

21.8.11.1 Companding
Companding (COMpressing and exPANDing) hardware allows compression and expansion of data in
either μ-law or A-law format. The companding standard employed in the United States and Japan is μ-law.
The European companding standard is referred to as A-law. The specifications for μ-law and A-law log
PCM are part of the CCITT G.711 recommendation.
A-law and μ-law allow 13 bits and 14 bits of dynamic range, respectively. Any values outside this range
are set to the most positive or most negative value. Thus, for companding to work best, the data
transferred to and from the McBSP via the CPU or DMA controller must be at least 16 bits wide.
The μ-law and A-law formats both encode data into 8-bit code words. Companded data is always 8 bits
wide; the appropriate word length bits (RWDLEN1, RWDLEN2, XWDLEN1, XWDLEN2) must therefore be
set to 0, indicating an 8-bit wide serial data stream. If companding is enabled and either of the frame
phases does not have an 8-bit word length, companding continues as if the word length is 8 bits.
Figure 21-45 illustrates the companding processes. When companding is chosen for the transmitter,
compression occurs during the process of copying data from DXR1 to XSR1. The transmit data is
encoded according to the specified companding law (A-law or μ-law). When companding is chosen for the
receiver, expansion occurs during the process of copying data from RBR1 to DRR1. The receive data is
decoded to 2's-complement format.
Figure 21-45. Companding Processes for Reception and for Transmission
DR

RSR1

DX

8

RBR1

16
Expand

8

XSR1

Compress

16

DRR1

To CPU or DMA controller

DXR1

From CPU or DMA controller

21.8.11.2 Format of Expanded Data
For reception, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1. The
RJUST bit of SPCR1 is ignored when companding is used.
21.8.11.3 Companding Internal Data
If the McBSP is otherwise unused (the serial port transmit and receive sections are reset), the
companding hardware can compand internal data. See Section 21.3.2.2.
21.8.11.4 Option to Receive LSB First
Normally, the McBSP transmits or receives all data with the most significant bit (MSB) first. However,
certain 8-bit data protocols (that do not use companded data) require the least significant bit (LSB) to be
transferred first. If you set RCOMPAND = 01b in RCR2, the bit ordering of 8-bit words is reversed during
reception. Similar to companding, this feature is enabled only if the appropriate word length bits are set to
0, indicating that 8-bit words are to be transferred serially. If either phase of the frame does not have an 8bit word length, the McBSP assumes the word length is eight bits and LSB-first ordering is done.

21.8.12 Set the Receive Data Delay
The RDATDLY bits (see Table 21-31) determine the length of the data delay for the receive frame.
Table 21-31. Register Bits Used to Set the Receive Data Delay
Register

Bit

Name

Function

RCR2

1-0

RDATDLY

Receive data delay

2288Multichannel Buffered Serial Port (McBSP)

RDATDLY = 00

0-bit data delay

RDATDLY = 01

1-bit data delay

RDATDLY = 10

2-bit data delay

RDATDLY = 11

Reserved

Type

Reset
Value

R/W

00

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

21.8.12.1 Data Delay
The start of a frame is defined by the first clock cycle in which frame synchronization is found to be active.
The beginning of actual data reception or transmission with respect to the start of the frame can be
delayed if required. This delay is called data delay.
RDATDLY specifies the data delay for reception. The range of programmable data delay is zero to two bitclocks (RDATDLY = 00b-10b), as described in Table 21-31 and shown in Figure 21-46. In this figure, the
data transferred is an 8-bit value with bits labeled B7, B6, B5, and so on. Typically a 1-bit delay is
selected, because data often follows a 1-cycle active frame-synchronization pulse.
21.8.12.2 0-Bit Data Delay
Normally, a frame-synchronization pulse is detected or sampled with respect to an edge of internal serial
clock CLK(R/X). Thus, on the following cycle or later (depending on the data delay value), data may be
received or transmitted. However, in the case of 0-bit data delay, the data must be ready for reception
and/or transmission on the same serial clock cycle.
For reception, this problem is solved because receive data is sampled on the first falling edge of MCLKR
where an active-high internal FSR is detected. However, data transmission must begin on the rising edge
of the internal CLKX clock that generated the frame synchronization. Therefore, the first data bit is
assumed to be present in XSR1, and thus on DX. The transmitter then asynchronously detects the framesynchronization signal (FSX) going active high and immediately starts driving the first bit to be transmitted
on the DX pin.
Figure 21-46. Range of Programmable Data Delay
CLK(R/X)

FS(R/X)

Á
Á
Á ÁÁ
Á ÁÁ Á
ÁÁ
ÁÁ Á
Á
Á
0-bit delay

D(R/X)
Data delay 0

B7

B6

B5

B4

B3

B6

B5

B4

B7

B6

B5

1-bit delay

D(R/X)
Data delay 1

B7

2-bit delay

D(R/X)
Data delay 2

21.8.12.3 2-Bit Data Delay

A data delay of two bit periods allows the serial port to interface to different types of T1 framing devices
where the data stream is preceded by a framing bit. During reception of such a stream with data delay of
two bits (framing bit appears after a 1-bit delay and data appears after a 2-bit delay), the serial port
essentially discards the framing bit from the data stream, as shown in Figure 21-47. In this figure, the data
transferred is an 8-bit value with bits labeled B7, B6, B5, and so on.
Figure 21-47. 2-Bit Data Delay Used to Skip a Framing Bit
CLKR

FSR

ÁÁ
ÁÁ
ÁÁ
ÁÁ

2-bit delay
DR

Framing bit

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

B7

B6

B5

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2289

Receiver Configuration

www.ti.com

21.8.13 Set the Receive Sign-Extension and Justification Mode
The RJUST bits (see Table 21-32) determine whether data received by the McBSP is sign-extended and
how it is justified.
Table 21-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode
Register
SPCR1

Bit

Name

14-13 RJUST

Function

Type

Reset
Value

R/W

00

Receive sign-extension and justification mode
RJUST = 00

Right justify data and zero fill MSBs in DRR[1,2]

RJUST = 01

Right justify data and sign extend it into the MSBs in
DRR[1,2]

RJUST = 10

Left justify data and zero fill LSBs in DRR[1,2]

RJUST = 11

Reserved

21.8.13.1 Sign-Extension and the Justification
RJUST in SPCR1 selects whether data in RBR[1,2] is right- or left-justified (with respect to the MSB) in
DRR[1,2] and whether unused bits in DRR[1,2] are filled with zeros or with sign bits.
Table 21-33 and Table 21-34 show the effects of various RJUST values. The first table shows the effect
on an example 12-bit receive-data value ABCh. The second table shows the effect on an example 20-bit
receive-data value ABCDEh.
Table 21-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh
RJUST

Justification

Extension

Value in
DRR2

Value in
DRR1

00b

Right

Zero fill MSBs

0000h

0ABCh

01b

Right

Sign extend data into MSBs

FFFFh

FABCh

10b

Left

Zero fill LSBs

0000h

ABC0h

11b

Reserved

Reserved

Reserved

Reserved

Table 21-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh

2290

RJUST

Justification

Extension

Value in
DRR2

Value in
DRR1

00b

Right

Zero fill MSBs

000Ah

BCDEh

01b

Right

Sign extend data into MSBs

FFFAh

BCDEh

10b

Left

Zero fill LSBs

ABCDh

E000h

11b

Reserved

Reserved

Reserved

Reserved

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

21.8.14 Set the Receive Interrupt Mode
The RINTM bits (see Table 21-35) determine which event generates a receive interrupt request to the
CPU.
The receive interrupt (RINT) informs the CPU of changes to the serial port status. Four options exist for
configuring this interrupt. The options are set by the receive interrupt mode bits, RINTM, in SPCR1.
Table 21-35. Register Bits Used to Set the Receive Interrupt Mode
Register

Bit

Name

Function

SPCR1

5-4

RINTM

Receive interrupt mode
RINTM = 00

RINT generated when RRDY changes from 0 to 1. Interrupt on
every serial word by tracking the RRDY bit in SPCR1.
Regardless of the value of RINTM, RRDY can be read to
detect the RRDY = 1 condition.

RINTM = 01

RINT generated by an end-of-block or end-of-frame condition
in the receive multichannel selection mode. In the multichannel
selection mode, interrupt after every 16-channel block
boundary has been crossed within a frame and at the end of
the frame. For details, see Section 21.6.8. In any other serial
transfer case, this setting is not applicable and, therefore, no
interrupts are generated.

RINTM = 10

RINT generated by a new receive frame-synchronization pulse.
Interrupt on detection of receive frame-synchronization pulses.
This generates an interrupt even when the receiver is in its
reset state. This is done by synchronizing the incoming framesynchronization pulse to the CPU clock and sending it to the
CPU via RINT.

RINTM = 11

RINT generated when RSYNCERR is set. Interrupt on framesynchronization error. Regardless of the value of RINTM,
RSYNCERR can be read to detect this condition. For
information on using RSYNCERR, see Section 21.5.3.

Type

Reset
Value

R/W

00

21.8.15 Set the Receive Frame-Synchronization Mode
The bits described in Table 21-36 determine the source for receive frame synchronization and the function
of the FSR pin.
21.8.15.1 Receive Frame-Synchronization Modes
Table 21-37 shows how you can select various sources to provide the receive frame-synchronization
signal and the effect on the FSR pin. The polarity of the signal on the FSR pin is determined by the FSRP
bit.
In digital loopback mode (DLB = 1), the transmit frame-synchronization signal is used as the receive
frame-synchronization signal.
Also in the clock stop mode, the internal receive clock signal (MCLKR) and the internal receive framesynchronization signal (FSR) are internally connected to their transmit counterparts, CLKX and FSX.
Table 21-36. Register Bits Used to Set the Receive Frame Synchronization Mode
Register

Bit

Name

Function

PCR

10

FSRM

Receive frame-synchronization mode
FSRM = 0

Receive frame synchronization is supplied by an
external source via the FSR pin.

FSRM = 1

Receive frame synchronization is supplied by
the sample rate generator. FSR is an output pin
reflecting internal FSR, except when GSYNC = 1
in SRGR2.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Type

Reset
Value

R/W

0

Multichannel Buffered Serial Port (McBSP) 2291

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

Table 21-36. Register Bits Used to Set the Receive Frame Synchronization Mode (continued)
Register

Bit

Name

Function

Type

Reset
Value

SRGR2

15

GSYNC

Sample rate generator clock synchronization mode

R/W

0

R/W

0

R/W

00

If the sample rate generator creates a frame-synchronization signal
(FSG) that is derived from an external input clock, the GSYNC bit
determines whether FSG is kept synchronized with pulses on the FSR
pin.

SPCR1

SPCR1

15

12-11

DLB

GSYNC = 0

No clock synchronization is used: CLKG
oscillates without adjustment, and FSG pulses
every (FPER + 1) CLKG cycles.

GSYNC = 1

Clock synchronization is used. When a pulse is
detected on the FSR pin:
• CLKG is adjusted as necessary so that it is
synchronized with the input clock on the
MCLKR pin.
• FSG pulses FSG only pulses in response
to a pulse on the FSR pin. The framesynchronization period defined in FPER is
ignored.
For more details, see Section 21.4.3.

Digital loopback mode

CLKSTP

DLB = 0

Digital loopback mode is disabled.

DLB = 1

Digital loopback mode is enabled. The receive
signals, including the receive framesynchronization signal, are connected internally
through multiplexers to the corresponding
transmit signals.

Clock stop mode
CLKSTP = 0Xb

Clock stop mode disabled; normal clocking for
non-SPI mode.

CLKSTP = 10b

Clock stop mode enabled without clock delay.
The internal receive clock signal (MCLKR) and
the internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.

CLKSTP = 11b

Clock stop mode enabled with clock delay. The
internal receive clock signal (MCLKR) and the
internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.

Table 21-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect
on the FSR Pin
Source of Receive Frame
Synchronization

DLB

FSRM

GSYNC

0

0

0 or 1

0

1

0

Internal FSR is driven by the sample rate
generator frame-synchronization signal
(FSG).

Output. FSG is inverted as determined by
FSRP before being driven out on the
FSR pin.

0

1

1

Internal FSR is driven by the sample rate
generator frame-synchronization signal
(FSG).

Input. The external frame-synchronization
input on the FSR pin is used to
synchronize CLKG and generate FSG
pulses.

1

0

0

Internal FSX drives internal FSR.

High impedance

2292Multichannel Buffered Serial Port (McBSP)

FSR Pin Status

An external frame-synchronization signal Input
enters the McBSP through the FSR pin.
The signal is then inverted as determined
by FSRP before being used as internal
FSR.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

Table 21-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect
on the FSR Pin (continued)
Source of Receive Frame
Synchronization

DLB

FSRM

GSYNC

1

0 or 1

1

Internal FSX drives internal FSR.

FSR Pin Status
Input. If the sample rate generator is
running, external FSR is used to
synchronize CLKG and generate FSG
pulses.

1

1

0

Internal FSX drives internal FSR.

Output. Receive (same as transmit)
frame synchronization is inverted as
determined by FSRP before being driven
out on the FSR pin.

21.8.16 Set the Receive Frame-Synchronization Polarity
The FSRP bit (see Table 21-38) determines whether frame-synchronization pulses are active high or
active low on the FSR pin.
Table 21-38. Register Bit Used to Set Receive Frame-Synchronization Polarity
Register
PCR

Bit

Name

Function

2

FSRP

Receive frame-synchronization polarity
FSRP = 0

Frame-synchronization pulse FSR is active high.

FSRP = 1

Frame-synchronization pulse FSR is active low.

Type

Reset
Value

R/W

0

21.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
Receive frame-synchronization pulses can be generated internally by the sample rate generator (see
Section 21.4.2) or driven by an external source. The source of frame synchronization is selected by
programming the mode bit, FSRM, in PCR. FSR is also affected by the GSYNC bit in SRGR2. For
information about the effects of FSRM and GSYNC, see Section 21.8.15. Similarly, receive clocks can be
selected to be inputs or outputs by programming the mode bit, CLKRM, in the PCR (see Section 21.8.17).
When FSR and FSX are inputs (FSXM = FSRM= 0, external frame-synchronization pulses), the McBSP
detects them on the internal falling edge of clock, internal MCLKR, and internal CLKX, respectively. The
receive data arriving at the DR pin is also sampled on the falling edge of internal MCLKR. These internal
clock signals are either derived from an external source via CLK(R/X) pins or driven by the sample rate
generator clock (CLKG) internal to the McBSP.
When FSR and FSX are outputs, implying that they are driven by the sample rate generator, they are
generated (transition to their active state) on the rising edge of the internal clock, CLK(R/X). Similarly, data
on the DX pin is output on the rising edge of internal CLKX.
FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR) configure the polarities of the FSR,
FSX, MCLKR, and CLKX signals, respectively. All frame-synchronization signals (internal FSR, internal
FSX) that are internal to the serial port are active high. If the serial port is configured for external frame
synchronization (FSR/FSX are inputs to McBSP), and FSRP = FSXP = 1, the external active-low framesynchronization signals are inverted before being sent to the receiver (internal FSR) and transmitter
(internal FSX). Similarly, if internal synchronization (FSR/FSX are output pins and GSYNC = 0) is
selected, the internal active-high frame-synchronization signals are inverted, if the polarity bit FS(R/X)P =
1, before being sent to the FS(R/X) pin.
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out
transmit data. Data is always transmitted on the rising edge of internal CLKX. If CLKXP = 1 and external
clocking is selected (CLKXM = 0 and CLKX is an input), the external falling-edge triggered input clock on
CLKX is inverted to a rising-edge triggered clock before being sent to the transmitter. If CLKXP = 1, and
internal clocking selected (CLKXM = 1 and CLKX is an output pin), the internal (rising-edge triggered)
clock, internal CLKX, is inverted before being sent out on the MCLKX pin.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2293

Receiver Configuration

www.ti.com

Similarly, the receiver can reliably sample data that is clocked with a rising edge clock (by the transmitter).
The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is
always sampled on the falling edge of internal MCLKR. Therefore, if CLKRP = 1 and external clocking is
selected (CLKRM = 0 and MCLKR is an input pin), the external rising-edge triggered input clock on
MCLKR is inverted to a falling-edge triggered clock before being sent to the receiver. If CLKRP = 1 and
internal clocking is selected (CLKRM = 1), the internal falling-edge triggered clock is inverted to a risingedge triggered clock before being sent out on the MCLKR pin.
MCLKRP = CLKXP in a system where the same clock (internal or external) is used to clock the receiver
and transmitter. The receiver uses the opposite edge as the transmitter to ensure valid setup and hold of
data around this edge. Figure 21-48 shows how data clocked by an external serial device using a rising
edge can be sampled by the McBSP receiver on the falling edge of the same clock.
Figure 21-48. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a
Falling Edge
Internal
CLKR

Á
Á
Á
Á

DR

Data setup
Data hold
B7

B6

Set the SRG Frame-Synchronization Period and Pulse Width
21.8.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization signal, FSG. If
the sample rate generator is supplying receive or transmit frame synchronization, you must program the
bit fields FPER and FWID.
On FSG, the period from the start of a frame-synchronization pulse to the start of the next pulse is (FPER
+ 1) CLKG cycles. The 12 bits of FPER allow a frame-synchronization period of 1 to 4096 CLKG cycles,
which allows up to 4096 data bits per frame. When GSYNC = 1, FPER is a don't care value.
Each pulse on FSG has a width of (FWID + 1) CLKG cycles. The eight bits of FWID allow a pulse width of
1 to 256 CLKG cycles. It is recommended that FWID be programmed to a value less than the
programmed word length.
The values in FPER and FWID are loaded into separate down-counters. The 12-bit FPER counter counts
down the generated clock cycles from the programmed value (4095 maximum) to 0. The 8-bit FWID
counter counts down from the programmed value (255 maximum) to 0. Table 21-39 shows settings for
FPER and FWID.
Figure 21-49 shows a frame-synchronization period of 16 CLKG periods (FPER = 15 or 00001111b) and a
frame-synchronization pulse with an active width of 2 CLKG periods (FWID = 1).
Table 21-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width
Register

Bit

Name

Function

Type

Reset Value

SRGR2

11-0

FPER

Sample rate generator frame-synchronization period

R/W

0000 0000 0000

R/W

0000 0000

For the frame-synchronization signal FSG, (FPER + 1)
determines the period from the start of a framesynchronization pulse to the start of the next framesynchronization pulse.
Range for (FPER + 1):
1 to 4096 CLKG cycles
SRGR1

15-8

FWID

Sample rate generator frame-synchronization pulse width
This field plus 1 determines the width of each framesynchronization pulse on FSG.

2294Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

Table 21-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse
Width (continued)
Register

Bit

Name

Function

Type

Reset Value

Range for (FWID + 1):
1 to 256 CLKG cycles

Figure 21-49. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLKG
Frame-synchronization period: (FPER+1) x CLKG
Frame-synchronization pulse width: (FWID + 1) x CLKG
FSG

When the sample rate generator comes out of reset, FSG is in its inactive state. Then, when GRST = 1
and FSGM = 1, a frame-synchronization pulse is generated. The frame width value (FWID + 1) is counted
down on every CLKG cycle until it reaches 0, at which time FSG goes low. At the same time, the frame
period value (FPER + 1) is also counting down. When this value reaches 0, FSG goes high, indicating a
new frame.

21.8.17 Set the Receive Clock Mode
Table 21-40 shows the settings for bits used to set receive clock mode.
Table 21-40. Register Bits Used to Set the Receive Clock Mode
Register
PCR

Bit
8

Name

Function

Type

Reset
Value

CLKRM

Receive clock mode

R/W

0

R/W

00

Case 1: Digital loopback mode not set (DLB = 0) in SPCR1.
CLKRM = 0

The MCLKR pin is an input pin that supplies the
internal receive clock (MCLKR).

CLKRM = 1

Internal MCLKR is driven by the sample rate
generator of the McBSP. The MCLKR pin is an
output pin that reflects internal MCLKR.

Case 2: Digital loopback mode set (DLB = 1) in SPCR1.

SPCR1

15

DLB

CLKRM = 0

The MCLKR pin is in the high impedance state.
The internal receive clock (MCLKR) is driven by
the internal transmit clock (CLKX). Internal
CLKX is derived according to the CLKXM bit of
PCR.

CLKRM = 1

Internal MCLKR is driven by internal CLKX. The
MCLKR pin is an output pin that reflects internal
MCLKR. Internal CLKX is derived according to
the CLKXM bit of PCR.

Digital loopback mode
DLB = 0

Digital loopback mode is disabled.

DLB = 1

Digital loopback mode is enabled. The receive
signals, including the receive framesynchronization signal, are connected internally
through multiplexers to the corresponding
transmit signals.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP) 2295

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

Table 21-40. Register Bits Used to Set the Receive Clock Mode (continued)
Register
SPCR1

Bit
12-11

Name

Function

CLKSTP

Clock stop mode
CLKSTP = 0Xb

Clock stop mode disabled; normal clocking for
non-SPI mode.

CLKSTP = 10b

Clock stop mode enabled without clock delay.
The internal receive clock signal (MCLKR) and
the internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.

CLKSTP = 11b

Clock stop mode enabled with clock delay. The
internal receive clock signal (MCLKR) and the
internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.

Type

Reset
Value

R/W

00

21.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
Table 21-41 shows how you can select various sources to provide the receive clock signal and affect the
MCLKR pin. The polarity of the signal on the MCLKR pin is determined by the CLKRP bit.
In the digital loopback mode (DLB = 1), the transmit clock signal is used as the receive clock signal.
Also, in the clock stop mode, the internal receive clock signal (MCLKR) and the internal receive framesynchronization signal (FSR) are internally connected to their transmit counterparts, CLKX and FSX.
Table 21-41. Receive Clock Signal Source Selection
DLB in
SPCR1

CLKRM in
PCR

Source of Receive Clock

MCLKR Pin Status

0

0

The MCLKR pin is an input driven by an
external clock. The external clock signal is
inverted as determined by CLKRP before
being used.

Input

0

1

The sample rate generator clock (CLKG)
drives internal MCLKR.

Output. CLKG, inverted as determined by CLKRP,
is driven out on the MCLKR pin.

1

0

Internal CLKX drives internal MCLKR. To
configure CLKX, see Section 21.9.18.

High impedance

1

1

Internal CLKX drives internal MCLKR. To
configure CLKX, see Section 21.9.18.

Output. Internal MCLKR (same as internal CLKX)
is inverted as determined by CLKRP before being
driven out on the MCLKR pin.

21.8.18 Set the Receive Clock Polarity
Table 21-42. Register Bit Used to Set Receive Clock Polarity
Register
PCR

2296

Bit
0

Name

Function

Type

Reset
Value

CLKRP

Receive clock polarity

R/W

0

CLKRP = 0

Receive data sampled on falling edge of MCLKR

CLKRP = 1

Receive data sampled on rising edge of MCLKR

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

21.8.18.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
Receive frame-synchronization pulses can be generated internally by the sample rate generator (see
Section 21.4.2) or driven by an external source. The source of frame synchronization is selected by
programming the mode bit, FSRM, in PCR. FSR is also affected by the GSYNC bit in SRGR2. For
information about the effects of FSRM and GSYNC, see Section 21.8.15. Similarly, receive clocks can be
selected to be inputs or outputs by programming the mode bit, CLKRM, in the PCR (see Section 21.8.17).
When FSR and FSX are inputs (FSXM = FSRM= 0, external frame-synchronization pulses), the McBSP
detects them on the internal falling edge of clock, internal MCLKR, and internal CLKX, respectively. The
receive data arriving at the DR pin is also sampled on the falling edge of internal MCLKR. These internal
clock signals are either derived from external source via CLK(R/X) pins or driven by the sample rate
generator clock (CLKG) internal to the McBSP.
When FSR and FSX are outputs, implying that they are driven by the sample rate generator, they are
generated (transition to their active state) on the rising edge of internal clock, CLK(R/X). Similarly, data on
the DX pin is output on the rising edge of internal CLKX.
FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR) configure the polarities of the FSR,
FSX, MCLKR, and CLKX signals, respectively. All frame-synchronization signals (internal FSR, internal
FSX) that are internal to the serial port are active high. If the serial port is configured for external frame
synchronization (FSR/FSX are inputs to McBSP) and FSRP = FSXP = 1, the external active-low framesynchronization signals are inverted before being sent to the receiver (internal FSR) and transmitter
(internal FSX). Similarly, if internal synchronization (FSR/FSX are output pins and GSYNC = 0) is
selected, the internal active-high frame-synchronization signals are inverted, if the polarity bit FS(R/X)P =
1, before being sent to the FS(R/X) pin.
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out
transmit data. Data is always transmitted on the rising edge of internal CLKX. If CLKXP = 1 and external
clocking is selected (CLKXM = 0 and CLKX is an input), the external falling-edge triggered input clock on
CLKX is inverted to a rising-edge triggered clock before being sent to the transmitter. If CLKXP = 1 and
internal clocking is selected (CLKXM = 1 and CLKX is an output pin), the internal (rising-edge triggered)
clock, internal CLKX, is inverted before being sent out on the MCLKX pin.
Similarly, the receiver can reliably sample data that is clocked with a rising edge clock (by the transmitter).
The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is
always sampled on the falling edge of internal MCLKR. Therefore, if CLKRP = 1 and external clocking is
selected (CLKRM = 0 and MCLKR is an input pin), the external rising-edge triggered input clock on
MCLKR is inverted to a falling-edge triggered clock before being sent to the receiver. If CLKRP = 1 and
internal clocking is selected (CLKRM = 1), the internal falling-edge triggered clock is inverted to a risingedge triggered clock before being sent out on the MCLKR pin.
CLKRP = CLKXP in a system where the same clock (internal or external) is used to clock the receiver and
transmitter. The receiver uses the opposite edge as the transmitter to ensure valid setup and hold of data
around this edge. Figure 21-50 shows how data clocked by an external serial device using a rising edge
can be sampled by the McBSP receiver on the falling edge of the same clock.
Figure 21-50. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a
Falling Edge
Internal
CLKR

Á
Á
Á
Á

DR

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Data setup
Data hold
B7

B6

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2297

Receiver Configuration

www.ti.com

21.8.19 Set the SRG Clock Divide-Down Value
Table 21-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value
Register

Bit

Name

Function

Type

Reset Value

SRGR1

7-0

CLKGDV

Sample rate generator clock divide-down value

R/W

0000 0001

The input clock of the sample rate generator is divided by
(CLKGDV + 1) to generate the required sample rate generator
clock frequency. The default value of CLKGDV is 1 (divide input
clock by 2).

21.8.19.1 Sample Rate Generator Clock Divider
The first divider stage generates the serial data bit clock from the input clock. This divider stage utilizes a
counter, preloaded by CLKGDV, that contains the divide ratio value.
The output of the first divider stage is the data bit clock, which is output as CLKG and which serves as the
input for the second and third stages of the divider.
CLKG has a frequency equal to 1/(CLKGDV + 1) of sample rate generator input clock. Thus, the sample
generator input clock frequency is divided by a value between 1 and 256. When CLKGDV is odd or equal
to 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide-down,
the high-state duration is p + 1 cycles and the low-state duration is p cycles.

21.8.20 Set the SRG Clock Synchronization Mode
For more details on using the clock synchronization feature, see Section 21.4.3.
Table 21-44. Register Bit Used to Set the SRG Clock Synchronization Mode
Register

Bit

Name

Function

Type

Reset
Value

SRGR2

15

GSYNC

Sample rate generator clock synchronization

R/W

0

GSYNC is used only when the input clock source for the sample rate
generator is external—on the MCLKR or MCLKX pin.

2298

GSYNC = 0

The sample rate generator clock (CLKG) is free
running. CLKG oscillates without adjustment, and
FSG pulses every (FPER + 1) CLKG cycles.

GSYNC = 1

Clock synchronization is performed. When a
pulse is detected on the FSR pin:
• CLKG is adjusted as necessary so that it is
synchronized with the input clock on the
MCLKR or MCLKX pin.
• FSG pulses. FSG only pulses in response to
a pulse on the FSR pin. The framesynchronization period defined in FPER is
ignored.

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Receiver Configuration

www.ti.com

21.8.21 Set the SRG Clock Mode (Choose an Input Clock)
Table 21-45. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
Register

Bit

Name

Function
Sample rate generator clock mode

PCR

7

SCLKME

SRGR2

13

CLKSM
SCLKME = 0
CLKSM = 0
SCLKME = 0

Type

Reset
Value

R/W

0

R/W

1

Reserved
Sample rate generator clock derived from
LSPCLK (default)

CLKSM = 1
SCLKME = 1
CLKSM = 0
SCLKME = 1
CLKSM = 1

Sample rate generator clock derived from MCLKR
pin
Sample rate generator clock derived from MCLKX
pin

21.8.21.1 SRG Clock Mode
The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter, or
both, but CLKG is derived from an input clock. Table 21-45 shows the four possible sources of the input
clock. For more details on generating CLKG, see Section 21.4.1.1.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2299

Receiver Configuration

www.ti.com

21.8.22 Set the SRG Input Clock Polarity
Table 21-46. Register Bits Used to Set the SRG Input Clock Polarity
Register
PCR

Bit

Name

Function

Type

Reset
Value

1

CLKXP

MCLKX pin polarity

R/W

0

R/W

0

CLKXP determines the input clock polarity when the MCLKX pin
supplies the input clock (SCLKME = 1 and CLKSM = 1).

PCR

0

CLKRP

CLKXP = 0

Rising edge on MCLKX pin generates transitions
on CLKG and FSG.

CLKXP = 1

Falling edge on MCLKX pin generates transitions
on CLKG and FSG.

MCLKR pin polarity
CLKRP determines the input clock polarity when the MCLKR pin
supplies the input clock (SCLKME = 1 and CLKSM = 0).
CLKRP = 0

Falling edge on MCLKR pin generates transitions
on CLKG and FSG.

CLKRP = 1

Rising edge on MCLKR pin generates transitions
on CLKG and FSG.

21.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
The sample rate generator can produce a clock signal (CLKG) and a frame-synchronization signal (FSG)
for use by the receiver, the transmitter, or both. To produce CLKG and FSG, the sample rate generator
must be driven by an input clock signal derived from the CPU clock or from an external clock on the CLKX
or MCLKR pin. If you use a pin, choose a polarity for that pin by using the appropriate polarity bit (CLKXP
for the MCLKX pin, CLKRP for the MCLKR pin). The polarity determines whether the rising or falling edge
of the input clock generates transitions on CLKG and FSG.

21.9 Transmitter Configuration
To
1.
2.
3.

configure the McBSP transmitter, perform the following procedure:
Place the McBSP/transmitter in reset (see Section 21.9.2).
Program the McBSP registers for the desired transmitter operation (see Section 21.9.1).
Take the transmitter out of reset (see Section 21.9.2).

21.9.1 Programming the McBSP Registers for the Desired Transmitter Operation
The following is a list of important tasks to be performed when you are configuring the McBSP transmitter.
Each task corresponds to one or more McBSP register bit fields.
• Global behavior:
– Set the transmitter pins to operate as McBSP pins.
– Enable/disable the digital loopback mode.
– Enable/disable the clock stop mode.
– Enable/disable transmit multichannel selection.
•

2300

Data behavior:
– Choose 1 or 2 phases for the transmit frame.
– Set the transmit word length(s).
– Set the transmit frame length.
– Enable/disable the transmit frame-synchronization ignore function.
– Set the transmit companding mode.
– Set the transmit data delay.

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Transmitter Configuration

www.ti.com

•

•

– Set the transmit DXENA mode.
– Set the transmit interrupt mode.
Frame-synchronization behavior:
– Set the transmit frame-synchronization mode.
– Set the transmit frame-synchronization polarity.
– Set the SRG frame-synchronization period and pulse width.
Clock behavior:
– Set the transmit clock mode.
– Set the transmit clock polarity.
– Set the SRG clock divide-down value.
– Set the SRG clock synchronization mode.
– Set the SRG clock mode (choose an input clock).
– Set the SRG input clock polarity.

21.9.2 Resetting and Enabling the Transmitter
The first step of the transmitter configuration procedure is to reset the transmitter, and the last step is to
enable the transmitter (to take it out of reset). Table 21-47 describes the bits used for both of these steps.
Table 21-47. Register Bits Used to Place Transmitter in Reset Field Descriptions
Register

Bit

Field

SPCR2

7

FRST

SPCR2

SPCR2

6

0

Value

Description
Frame-synchronization logic reset

0

Frame-synchronization logic is reset. The sample rate generator does not generate framesynchronization signal FSG, even if GRST = 1.

1

Frame-synchronization is enabled. If GRST = 1, frame-synchronization signal FSG is
generated after (FPER + 1) number of CLKG clock cycles; all frame counters are loaded
with their programmed values.

GRST

Sample rate generator reset
0

Sample rate generator is reset. If GRST = 0 due to a device reset, CLKG is driven by the
CPU clock divided by 2, and FSG is driven low (inactive). If GRST = 0 due to program
code, CLKG and FSG are both driven low (inactive).

1

Sample rate generator is enabled. CLKG is driven according to the configuration
programmed in the sample rate generator registers (SRGR[1,2]). If FRST = 1, the
generator also generates the frame-synchronization signal FSG as programmed in the
sample rate generator registers.

XRST

Transmitter reset
0

The serial port transmitter is disabled and in the reset state.

1

The serial port transmitter is enabled.

21.9.2.1 Reset Considerations
The serial port can be reset in the following two ways:
1. A DSP reset (XRS signal driven low) places the receiver, transmitter, and sample rate generator in
reset. When the device reset is removed, GRST = FRST = RRST = XRST = 0, keeping the entire
serial port in the reset state.
2. The serial port transmitter and receiver can be reset directly using the RRST and XRST bits in the
serial port control registers. The sample rate generator can be reset directly using the GRST bit in
SPCR2.
3. When using the DMA, the order in which McBSP events must occur is important. DMA channel and
peripheral interrupts must be configured prior to releasing the McBSP transmitter from reset.
The reason for this is that an XRDY is fired when XRST = 1. The XRDY signals the DMA to start
copying data from the buffer into the transmit register. If the McBSP transmitter is released from reset
before the DMA channel and peripheral interrupts are configured, the XRDY signals before the DMA
channel can receive the signal; therefore, the DMA does not move the data from the buffer to the
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2301

Transmitter Configuration

www.ti.com

transmit register. The DMA PERINTFLG is edge-sensitive and will fail to recognize the XRDY, which is
continuously high.
For more details about McBSP reset conditions and effects, see Section 21.10.2.

21.9.3 Set the Transmitter Pins to Operate as McBSP Pins
To configure a pin for its McBSP function , you should configure the bits of the GPxMUXn register
appropriately. In addition to this, bits 12 and 13 of the PCR register must be set to 0. These bits are
defined as reserved.

21.9.4 Enable/Disable the Digital Loopback Mode
The DLB bit determines whether the digital loopback mode is on. DLB is described in Table 21-48.
Table 21-48. Register Bit Used to Enable/Disable the Digital Loopback Mode
Register

Bit

Name

Function

SPCR1

15

DLB

Digital loopback mode
DLB = 0

Digital loopback mode is disabled.

DLB = 1

Digital loopback mode is enabled.

Type

Reset
Value

R/W

0

21.9.4.1 Digital Loopback Mode
In the digital loopback mode, the receive signals are connected internally through multiplexers to the
corresponding transmit signals, as shown in Table 21-49. This mode allows testing of serial port code with
a single DSP device; the McBSP receives the data it transmits.
Table 21-49. Receive Signals Connected to Transmit Signals in Digital Loopback Mode
This Receive Signal

Is Fed Internally by
This Transmit Signal

DR (receive data)

DX (transmit data)

FSR (receive frame synchronization)

FSX (transmit frame synchronization)

MCLKR (receive clock)

CLKX (transmit clock)

21.9.5 Enable/Disable the Clock Stop Mode
The CLKSTP bits determine whether the clock stop mode is on. CLKSTP is described in Table 21-50.
Table 21-50. Register Bits Used to Enable/Disable the Clock Stop Mode
Register
SPCR1

2302

Bit
12-11

Name

Function

Type

Reset
Value

CLKSTP

Clock stop mode

R/W

00

CLKSTP = 0Xb

Clock stop mode disabled; normal clocking for
non-SPI mode.

CLKSTP = 10b

Clock stop mode enabled without clock delay

CLKSTP = 11b

Clock stop mode enabled with clock delay

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Transmitter Configuration

www.ti.com

21.9.5.1 Clock Stop Mode
The clock stop mode supports the SPI master-slave protocol. If you do not plan to use the SPI protocol,
you can clear CLKSTP to disable the clock stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each data
transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b). The
CLKXP bit determines whether the starting edge of the clock on the MCLKX pin is rising or falling. The
CLKRP bit determines whether receive data is sampled on the rising or falling edge of the clock shown on
the MCLKR pin.
Table 21-51 summarizes the impact of CLKSTP, CLKXP, and CLKRP on serial port operation. In the clock
stop mode, the receive clock is tied internally to the transmit clock, and the receive frame-synchronization
signal is tied internally to the transmit frame-synchronization signal.
Table 21-51. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
Bit Settings

Clock Scheme

CLKSTP = 00b or 01b

Clock stop mode disabled. Clock enabled for non-SPI mode.

CLKXP = 0 or 1
CLKRP = 0 or 1
CLKSTP = 10b
CLKXP = 0

Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and
receives data on the falling edge of MCLKR.

CLKRP = 0
CLKSTP = 11b
CLKXP = 0

Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising
edge of CLKX and receives data on the rising edge of MCLKR.

CLKRP = 1
CLKSTP = 10b
CLKXP = 1

High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and
receives data on the rising edge of MCLKR.

CLKRP = 0
CLKSTP = 11b
CLKXP = 1

High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling
edge of CLKX and receives data on the falling edge of MCLKR.

CLKRP = 1

21.9.6 Enable/Disable Transmit Multichannel Selection
For more details, see Section 21.6.7.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2303

Transmitter Configuration

www.ti.com

Table 21-52. Register Bits Used to Enable/Disable Transmit Multichannel Selection
Register

Bit

Name

Function

Type

Reset
Value

MCR2

1-0

XMCM

Transmit multichannel selection

R/W

00

XMCM = 00b

No transmit multichannel selection mode is on. All
channels are enabled and unmasked. No channels can
be disabled or masked.

XMCM = 01b

All channels are disabled unless they are selected in the
appropriate transmit channel enable registers (XCERs).
If enabled, a channel in this mode is also unmasked.
The XMCME bit determines whether 32 channels or 128
channels are selectable in XCERs.

XMCM = 10b

All channels are enabled, but they are masked unless
they are selected in the appropriate transmit channel
enable registers (XCERs).
The XMCME bit determines whether 32 channels or 128
channels are selectable in XCERs.

XMCM = 11b

This mode is used for symmetric transmission and
reception.
All channels are disabled for transmission unless they
are enabled for reception in the appropriate receive
channel enable registers (RCERs). Once enabled, they
are masked unless they are also selected in the
appropriate transmit channel enable registers (XCERs).
The XMCME bit determines whether 32 channels or 128
channels are selectable in RCERs and XCERs.

2304

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Transmitter Configuration

www.ti.com

21.9.7 Choose One or Two Phases for the Transmit Frame
Table 21-53. Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame
Register

Bit

Name

Function

Type

Reset
Value

XCR2

15

XPHASE

Transmit phase number

R/W

0

Specifies whether the transmit frame has 1 or 2 phases.
XPHASE = 0

Single-phase frame

XPHASE = 1

Dual-phase frame

21.9.8 Set the Transmit Word Length(s)
Table 21-54. Register Bits Used to Set the Transmit Word Length(s)
Register

Bit

Name

Function

Type

Reset
Value

XCR1

7-5

XWDLEN1

Transmit word length of frame phase 1

R/W

000

R/W

000

XCR2

7-5

XWDLEN2

XWDLEN1 = 000b

8 bits

XWDLEN1 = 001b

12 bits

XWDLEN1 = 010b

16 bits

XWDLEN1 = 011b

20 bits

XWDLEN1 = 100b

24 bits

XWDLEN1 = 101b

32 bits

XWDLEN1 = 11Xb

Reserved

Transmit word length of frame phase 2
XWDLEN2 = 000b

8 bits

XWDLEN2 = 001b

12 bits

XWDLEN2 = 010b

16 bits

XWDLEN2 = 011b

20 bits

XWDLEN2 = 100b

24 bits

XWDLEN2 = 101b

32 bits

XWDLEN2 = 11Xb

Reserved

21.9.8.1 Word Length Bits
Each frame can have one or two phases, depending on the value that you load into the RPHASE bit. If a
single-phase frame is selected, XWDLEN1 selects the length for every serial word transmitted in the
frame. If a dual-phase frame is selected, XWDLEN1 determines the length of the serial words in phase 1
of the frame, and XWDLEN2 determines the word length in phase 2 of the frame.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2305

Transmitter Configuration

www.ti.com

21.9.9 Set the Transmit Frame Length
Table 21-55. Register Bits Used to Set the Transmit Frame Length
Register
XCR1

Bit
14-8

Name

Function

Type

Reset Value

XFRLEN1

Transmit frame length 1

R/W

000 0000

R/W

000 0000

(XFRLEN1 + 1) is the number of serial words in phase 1 of the
transmit frame.

XCR2

14-8

XFRLEN2

XFRLEN1 = 000 0000

1 word in phase 1

XFRLEN1 = 000 0001

2 words in phase 1

|

|

|

|

XFRLEN1 = 111 1111

128 words in phase 1

Transmit frame length 2
If a dual-phase frame is selected, (XFRLEN2 + 1) is the
number of serial words in phase 2 of the transmit frame.
XFRLEN2 = 000 0000

1 word in phase 2

XFRLEN2 = 000 0001

2 words in phase 2

|

|

|

|

XFRLEN2 = 111 1111

128 words in phase 2

21.9.9.1 Selected Frame Length
The transmit frame length is the number of serial words in the transmit frame. Each frame can have one or
two phases, depending on the value that you load into the XPHASE bit.
If a single-phase frame is selected (XPHASE = 0), the frame length is equal to the length of phase 1. If a
dual-phase frame is selected (XPHASE = 1), the frame length is the length of phase 1 plus the length of
phase 2.
The 7-bit XFRLEN fields allow up to 128 words per phase. See Table 21-56 for a summary of how to
calculate the frame length. This length corresponds to the number of words or logical time slots or
channels per frame-synchronization pulse.
NOTE: Program the XFRLEN fields with [w minus 1], where w represents the number of words per
phase. For example, if you want a phase length of 128 words in phase 1, load 127 into
XFRLEN1.

Table 21-56. How to Calculate Frame Length

2306

XPHASE

XFRLEN1

XFRLEN2

Frame Length

0

0 ≤ XFRLEN1 ≤ 127

Don't care

(XFRLEN1 + 1) words

1

0 ≤ XFRLEN1 ≤ 127

0 ≤ XFRLEN2 ≤ 127

Multichannel Buffered Serial Port (McBSP)

(XFRLEN1 + 1) + (XFRLEN2 + 1) words

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Transmitter Configuration

www.ti.com

21.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function
Table 21-57. Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore
Function
Register
XCR2

Bit

Name

Function

2

XFIG

Transmit frame-synchronization ignore
XFIG = 0

An unexpected transmit frame-synchronization
pulse causes the McBSP to restart the frame
transfer.

XFIG = 1

The McBSP ignores unexpected transmit framesynchronization pulses.

Type

Reset
Value

R/W

0

21.9.10.1 Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
transmitted, this pulse is treated as an unexpected frame-synchronization pulse.
When XFIG = 1, normal transmission continues with unexpected frame-synchronization signals ignored.
When XFIG = 0 and an unexpected frame-synchronization pulse occurs, the serial port:
1. Aborts the present transmission
2. Sets XSYNCERR to 1 in SPCR2
3. Reinitiates transmission of the current word that was aborted
For more details about the frame-synchronization error condition, see Section 21.5.6.
21.9.10.2 Examples Showing the Effects of XFIG
Figure 21-51 shows an example in which word B is interrupted by an unexpected frame-synchronization
pulse when (R/X)FIG = 0. In the case of transmission, the transmission of B is aborted (B is lost). This
condition is a transmit synchronization error, which sets the XSYNCERR bit. No new data has been
written to DXR[1,2]; therefore, the McBSP transmits B again.
Figure 21-51. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0
CLK(R/X)
FS(R/X)
DR

A0

B7

B6

C7

DX

A0

B7

B6

B7

Frame synchronization aborts current transfer
New data received
C6
C5
C4
C3
C2
C1
C0
Current data retransmitted
B6
B5
B4
B3
B2
B1
B0

ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ

D7

D6

C7

C6

(R/X)SYNCERR

In contrast with Figure 21-51, Figure 21-52 shows McBSP operation when unexpected framesynchronization signals are ignored (when (R/X)FIG = 1). Here, the transfer of word B is not affected by
an unexpected frame-synchronization pulse.
Figure 21-52. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1
CLK(R/X)
Frame synchronization ignored

FS(R/X)
D(R/X)

A0

B7

B6

B5

B4

B3

B2

B1

B0

(R/X)SYNCERR

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

C7

C6

C5

C4

Á
ÁÁ
Á

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2307

Transmitter Configuration

www.ti.com

21.9.11 Set the Transmit Companding Mode
Table 21-58. Register Bits Used to Set the Transmit Companding Mode
Register

Bit

Name

Function

Type

Reset
Value

XCR2

4-3

XCOMPAND

Transmit companding mode

R/W

00

Modes other than 00b are enabled only when the appropriate
XWDLEN is 000b, indicating 8-bit data.
XCOMPAND = 00b

No companding, any size data, MSB
transmitted first

XCOMPAND = 01b

No companding, 8-bit data, LSB
transmitted first (for details, see
Section 21.8.11.4, Option to Receive
LSB First)

XCOMPAND = 10b

μ-law companding, 8-bit data, MSB
transmitted first

XCOMPAND = 11b

A-law companding, 8-bit data, MSB
transmitted first

21.9.11.1 Companding
Companding (COMpressing and exPANDing) hardware allows compression and expansion of data in
either μ-law or A-law format. The companding standard employed in the United States and Japan is μ-law.
The European companding standard is referred to as A-law. The specifications for μ-law and A-law log
PCM are part of the CCITT G.711 recommendation.
A-law and μ-law allow 13 bits and 14 bits of dynamic range, respectively. Any values outside this range
are set to the most positive or most negative value. Thus, for companding to work best, the data
transferred to and from the McBSP via the CPU or DMA controller must be at least 16 bits wide.
The μ-law and A-law formats both encode data into 8-bit code words. Companded data is always 8 bits
wide; the appropriate word length bits (RWDLEN1, RWDLEN2, XWDLEN1, XWDLEN2) must therefore be
set to 0, indicating an 8-bit wide serial data stream. If companding is enabled and either of the frame
phases does not have an 8-bit word length, companding continues as if the word length is 8 bits.
Figure 21-53 illustrates the companding processes. When companding is chosen for the transmitter,
compression occurs during the process of copying data from DXR1 to XSR1. The transmit data is
encoded according to the specified companding law (A-law or μ-law). When companding is chosen for the
receiver, expansion occurs during the process of copying data from RBR1 to DRR1. The receive data is
decoded to twos-complement format.
Figure 21-53. Companding Processes for Reception and for Transmission
DR

RSR1

DX

RBR1

XSR1

8

16
Expand

8

Compress

16

DRR1

To CPU or DMA controller

DXR1

From CPU or DMA controller

21.9.11.2 Format for Data To Be Compressed
For transmission using μ-law compression, make sure the 14 data bits are left-justified in DXR1, with the
remaining two low-order bits filled with 0s as shown in Figure 21-54.
Figure 21-54. μ-Law Transmit Data Companding Format
15-2
µ-law format in DXR1

2308

Multichannel Buffered Serial Port (McBSP)

1-0

Value

00

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Transmitter Configuration

www.ti.com

For transmission using A-law compression, make sure the 13 data bits are left-justified in DXR1, with the
remaining three low-order bits filled with 0s as shown in Figure 21-55.
Figure 21-55. A-Law Transmit Data Companding Format

A-law format in DXR1

15-3

2-0

Value

000

21.9.11.3 Capability to Compand Internal Data
If the McBSP is otherwise unused (the serial port transmit and receive sections are reset), the
companding hardware can compand internal data. See Section 21.3.2.2, Capability to Compand Internal
Data.
21.9.11.4 Option to Transmit LSB First
Normally, the McBSP transmit or receives all data with the most significant bit (MSB) first. However,
certain 8-bit data protocols (that do not use companded data) require the least significant bit (LSB) to be
transferred first. If you set XCOMPAND = 01b in XCR2, the bit ordering of 8-bit words is reversed (LSB
first) before being sent from the serial port. Similar to companding, this feature is enabled only if the
appropriate word length bits are set to 0, indicating that 8-bit words are to be transferred serially. If either
phase of the frame does not have an 8-bit word length, the McBSP assumes the word length is eight bits
and LSB-first ordering is done.

21.9.12 Set the Transmit Data Delay
Table 21-59. Register Bits Used to Set the Transmit Data Delay
Register

Bit

Name

Function

Type

Reset
Value

XCR2

1-0

XDATDLY

Transmitter data delay

R/W

00

XDATDLY = 00

0-bit data delay

XDATDLY = 01

1-bit data delay

XDATDLY = 10

2-bit data delay

XDATDLY = 11

Reserved

21.9.12.1 Data Delay
The start of a frame is defined by the first clock cycle in which frame synchronization is found to be active.
The beginning of actual data reception or transmission with respect to the start of the frame can be
delayed if necessary. This delay is called data delay.
XDATDLY specifies the data delay for transmission. The range of programmable data delay is zero to two
bit-clocks (XDATDLY = 00b-10b), as described in Table 21-59 and Figure 21-56. In this figure, the data
transferred is an 8-bit value with bits labeled B7, B6, B5, and so on. Typically a 1-bit delay is selected,
because data often follows a 1-cycle active frame-synchronization pulse.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2309

Transmitter Configuration

www.ti.com

Figure 21-56. Range of Programmable Data Delay
CLK(R/X)

FS(R/X)

ÁÁ
ÁÁ
ÁÁ ÁÁ
ÁÁ ÁÁ Á
ÁÁ
ÁÁ Á
Á
Á
0-bit delay

D(R/X)
Data delay 0

B7

B6

B5

B4

B3

B6

B5

B4

B7

B6

B5

1-bit delay

D(R/X)
Data delay 1

B7

2-bit delay

D(R/X)
Data delay 2

21.9.12.2 0-Bit Data Delay

Normally, a frame-synchronization pulse is detected or sampled with respect to an edge of serial clock
internal CLK(R/X). Thus, on the following cycle or later (depending on the data delay value), data can be
received or transmitted. However, in the case of 0-bit data delay, the data must be ready for reception
and/or transmission on the same serial clock cycle.
For reception this problem is solved because receive data is sampled on the first falling edge of MCLKR
where an active-high internal FSR is detected. However, data transmission must begin on the rising edge
of the internal CLKX clock that generated the frame synchronization. Therefore, the first data bit is
assumed to be present in XSR1, and thus DX. The transmitter then asynchronously detects the frame
synchronization, FSX, going active high and immediately starts driving the first bit to be transmitted on the
DX pin.
21.9.12.3 2-Bit Data Delay
A data delay of two bit-periods allows the serial port to interface to different types of T1 framing devices
where the data stream is preceded by a framing bit. During reception of such a stream with data delay of
two bits (framing bit appears after a 1-bit delay and data appears after a 2-bit delay), the serial port
essentially discards the framing bit from the data stream, as shown in the following figure. In this figure,
the data transferred is an 8-bit value with bits labeled B7, B6, B5, and so on.
Figure 21-57. 2-Bit Data Delay Used to Skip a Framing Bit
CLKR

ÁÁ
Á
Á

FSR

2-bit delay
DR

2310

Multichannel Buffered Serial Port (McBSP)

Framing bit

B7

B6

B5

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Transmitter Configuration

www.ti.com

21.9.13 Set the Transmit DXENA Mode
Table 21-60. Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode
Register
SPCR1

Bit
7

Name

Function

DXENA

DX delay enabler mode
DXENA = 0

DX delay enabler is off.

DXENA = 1

DX delay enabler is on.

Type

Reset
Value

R/W

0

21.9.13.1 DXENA Mode
The DXENA bit controls the delay enabler on the DX pin. Set DXENA to enable an extra delay for turn-on
time. This bit does not control the data itself, so only the first bit is delayed.
If you tie together the DX pins of multiple McBSPs, make sure DXENA = 1 to avoid having more than one
McBSP transmit on the data line at one time.

21.9.14 Set the Transmit Interrupt Mode
The transmitter interrupt (XINT) signals the CPU of changes to the serial port status. Four options exist for
configuring this interrupt. The options are set by the transmit interrupt mode bits, XINTM, in SPCR2.
Table 21-61. Register Bits Used to Set the Transmit Interrupt Mode
Register

Bit

Name

Function

SPCR2

5-4

XINTM

Transmit interrupt mode
XINTM = 00

XINT generated when XRDY changes from 0 to 1.

XINTM = 01

XINT generated by an end-of-block or end-of-frame
condition in a transmit multichannel selection mode. In
any of the transmit multichannel selection modes,
interrupt after every 16-channel block boundary has
been crossed within a frame and at the end of the frame.
For details, see Section 21.6.8. In any other serial
transfer case, this setting is not applicable and,
therefore, no interrupts are generated.

XINTM = 10

XINT generated by a new transmit framesynchronization pulse. Interrupt on detection of each
transmit frame-synchronization pulse. This generates an
interrupt even when the transmitter is in its reset state.
This is done by synchronizing the incoming framesynchronization pulse to the CPU clock and sending it to
the CPU via XINT.

XINTM = 11

XINT generated when XSYNCERR is set. Interrupt on
frame-synchronization error. Regardless of the value of
XINTM, XSYNCERR can be read to detect this
condition. For more information on using XSYNCERR,
see Section 21.5.6.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Type

Reset
Value

R/W

00

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2311

Transmitter Configuration

www.ti.com

21.9.15 Set the Transmit Frame-Synchronization Mode
Table 21-62. Register Bits Used to Set the Transmit Frame-Synchronization Mode
Register

Bit

Name

Function

PCR

11

FSXM

Transmit frame-synchronization mode

SRGR2

12

FSGM

FSXM = 0

Transmit frame synchronization is supplied by an
external source via the FSX pin.

FSXM = 1

Transmit frame synchronization is supplied by the
McBSP, as determined by the FSGM bit of SRGR2.

Sample rate generator transmit frame-synchronization mode

Type

Reset
Value

R/W

0

R/W

0

Used when FSXM = 1 in PCR.
FSGM = 0

The McBSP generates a transmit framesynchronization pulse when the content of DXR[1,2] is
copied to XSR[1,2].

FSGM = 1

The transmitter uses frame-synchronization pulses
generated by the sample rate generator. Program the
FWID bits to set the width of each pulse. Program the
FPER bits to set the frame-synchronization period.

21.9.15.1 Transmit Frame-Synchronization Modes
Table 21-63 shows how FSXM and FSGM select the source of transmit frame-synchronization pulses. The
three choices are:
• External frame-synchronization input
• Sample rate generator frame-synchronization signal (FSG)
• Internal signal that indicates a DXR-to-XSR copy has been made
Table 21-63 also shows the effect of each bit setting on the FSX pin. The polarity of the signal on the FSX
pin is determined by the FSXP bit.
Table 21-63. How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses
FSXM

FSGM

0

0 or 1

1
1

Source of Transmit Frame
Synchronization

FSX Pin Status

An external frame-synchronization signal enters the
McBSP through the FSX pin. The signal is then
inverted by FSXP before being used as internal FSX.

Input

1

Internal FSX is driven by the sample rate generator
frame-synchronization signal (FSG).

Output. FSG is inverted by FSXP before being driven
out on FSX pin.

0

A DXR-to-XSR copy causes the McBSP to generate a Output. The generated frame-synchronization pulse is
transmit frame-synchronization pulse that is 1 cycle
inverted as determined by FSXP before being driven
wide.
out on FSX pin.

21.9.15.2 Other Considerations
If the sample rate generator creates a frame-synchronization signal (FSG) that is derived from an external
input clock, the GSYNC bit determines whether FSG is kept synchronized with pulses on the FSR pin. For
more details, see Section 21.4.3.
In the clock stop mode (CLKSTP = 10b or 11b), the McBSP can act as a master or as a slave in the SPI
protocol. If the McBSP is a master and must provide a slave-enable signal (SPISTE) on the FSX pin,
make sure that FSXM = 1 and FSGM = 0 so that FSX is an output and is driven active for the duration of
each transmission. If the McBSP is a slave, make sure that FSXM = 0 so that the McBSP can receive the
slave-enable signal on the FSX pin.

2312

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Transmitter Configuration

www.ti.com

21.9.16 Set the Transmit Frame-Synchronization Polarity
Table 21-64. Register Bit Used to Set Transmit Frame-Synchronization Polarity
Register
PCR

Bit

Name

Function

3

FSXP

Transmit frame-synchronization polarity
FSXP = 0

Frame-synchronization pulse FSX is active high.

FSXP = 1

Frame-synchronization pulse FSX is active low.

Type

Reset
Value

R/W

0

21.9.16.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
Transmit frame-synchronization pulses can be generated internally by the sample rate generator (see
Section 21.4.2) or driven by an external source. The source of frame synchronization is selected by
programming the mode bit, FSXM, in PCR. FSX is also affected by the FSGM bit in SRGR2. For
information about the effects of FSXM and FSGM, see Section 21.9.15). Similarly, transmit clocks can be
selected to be inputs or outputs by programming the mode bit, CLKXM, in the PCR (see Section 21.9.18).
When FSR and FSX are inputs (FSXM = FSRM= 0, external frame-synchronization pulses), the McBSP
detects them on the internal falling edge of clock, internal MCLKR, and internal CLKX, respectively. The
receive data arriving at the DR pin is also sampled on the falling edge of internal MCLKR. These internal
clock signals are either derived from external source via CLK(R/X) pins or driven by the sample rate
generator clock (CLKG) internal to the McBSP.
When FSR and FSX are outputs, implying that they are driven by the sample rate generator, they are
generated (transition to their active state) on the rising edge of internal clock, CLK(R/X). Similarly, data on
the DX pin is output on the rising edge of internal CLKX.
FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR) configure the polarities of the FSR,
FSX, MCLKR, and CLKX signals, respectively. All frame-synchronization signals (internal FSR, internal
FSX) that are internal to the serial port are active high. If the serial port is configured for external frame
synchronization (FSR/FSX are inputs to McBSP) and FSRP = FSXP = 1, the external active-low framesynchronization signals are inverted before being sent to the receiver (internal FSR) and transmitter
(internal FSX). Similarly, if internal synchronization (FSR/FSX are output pins and GSYNC = 0) is selected
and the polarity bit FS(R/X)P = 1, the internal active-high frame-synchronization signals are inverted
before being sent to the FS(R/X) pin.
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out
transmit data. Data is always transmitted on the rising edge of internal CLKX. If CLKXP = 1 and external
clocking is selected (CLKXM = 0 and CLKX is an input), the external falling-edge triggered input clock on
CLKX is inverted to a rising-edge triggered clock before being sent to the transmitter. If CLKXP = 1, and
internal clocking selected (CLKXM = 1 and CLKX is an output pin), the internal (rising-edge triggered)
clock, internal CLKX, is inverted before being sent out on the MCLKX pin.
Similarly, the receiver can reliably sample data that is clocked with a rising edge clock (by the transmitter).
The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is
always sampled on the falling edge of internal MCLKR. Therefore, if CLKRP = 1 and external clocking is
selected (CLKRM = 0 and MCLKR is an input pin), the external rising-edge triggered input clock on
MCLKR is inverted to a falling-edge triggered clock before being sent to the receiver. If CLKRP = 1 and
internal clocking is selected (CLKRM = 1), the internal falling-edge triggered clock is inverted to a risingedge triggered clock before being sent out on the MCLKR pin.
CLKRP = CLKXP in a system where the same clock (internal or external) is used to clock the receiver and
transmitter. The receiver uses the opposite edge as the transmitter to ensure valid setup and hold of data
around this edge. Figure 21-58 shows how data clocked by an external serial device using a rising edge
can be sampled by the McBSP receiver on the falling edge of the same clock.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2313

Transmitter Configuration

www.ti.com

Figure 21-58. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a
Falling Edge
Internal
CLKR

ÁÁ
ÁÁ
ÁÁ
ÁÁ

Data setup

DR

Data hold
B7

B6

21.9.17 Set the SRG Frame-Synchronization Period and Pulse Width
Table 21-65. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width
Register

Bit

Name

Function

Type

Reset Value

SRGR2

11-0

FPER

Sample rate generator frame-synchronization period

R/W

0000 0000 0000

R/W

0000 0000

For the frame-synchronization signal FSG, (FPER + 1)
determines the period from the start of a framesynchronization pulse to the start of the next framesynchronization pulse.
Range for (FPER + 1):
SRGR1

15-8

FWID

1 to 4096 CLKG cycles.

Sample rate generator frame-synchronization pulse width
This field plus 1 determines the width of each framesynchronization pulse on FSG.
Range for (FWID + 1):

1 to 256 CLKG cycles.

21.9.17.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization signal, FSG. If
the sample rate generator is supplying receive or transmit frame synchronization, you must program the
bit fields FPER and FWID.
On FSG, the period from the start of a frame-synchronization pulse to the start of the next pulse is (FPER
+ 1) CLKG cycles. The 12 bits of FPER allow a frame-synchronization period of 1 to 4096 CLKG cycles,
which allows up to 4096 data bits per frame. When GSYNC = 1, FPER is a don't care value.
Each pulse on FSG has a width of (FWID + 1) CLKG cycles. The eight bits of FWID allow a pulse width of
1 to 256 CLKG cycles. It is recommended that FWID be programmed to a value less than the
programmed word length.
The values in FPER and FWID are loaded into separate down-counters. The 12-bit FPER counter counts
down the generated clock cycles from the programmed value (4095 maximum) to 0. The 8-bit FWID
counter counts down from the programmed value (255 maximum) to 0.
Figure 21-59 shows a frame-synchronization period of 16 CLKG periods (FPER = 15 or 00001111b) and a
frame-synchronization pulse with an active width of 2 CLKG periods (FWID = 1).
Figure 21-59. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLKG
Frame-synchronization period: (FPER+1) x CLKG
Frame-synchronization pulse width: (FWID + 1) x CLKG
FSG

2314

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Transmitter Configuration

www.ti.com

When the sample rate generator comes out of reset, FSG is in its inactive state. Then, when GRST = 1
and FSGM = 1, a frame-synchronization pulse is generated. The frame width value (FWID + 1) is counted
down on every CLKG cycle until it reaches 0, at which time FSG goes low. At the same time, the frame
period value (FPER + 1) is also counting down. When this value reaches 0, FSG goes high, indicating a
new frame.

21.9.18 Set the Transmit Clock Mode
Table 21-66. Register Bit Used to Set the Transmit Clock Mode
Register

Bit

PCR

9

Name

Function

CLKXM

Transmit clock mode
CLKXM = 0

The transmitter gets its clock signal from an
external source via the MCLKX pin.

CLKXM = 1

The MCLKX pin is an output pin driven by the
sample rate generator of the McBSP.

Type

Reset
Value

R/W

0

21.9.18.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
Table 21-67 shows how the CLKXM bit selects the transmit clock and the corresponding status of the
MCLKX pin. The polarity of the signal on the MCLKX pin is determined by the CLKXP bit.
Table 21-67. How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the
MCLKX pin
CLKXM in
PCR

Source of Transmit Clock

MCLKX pin Status

0

Internal CLKX is driven by an external clock on the MCLKX pin. Input
CLKX is inverted as determined by CLKXP before being used.

1

Internal CLKX is driven by the sample rate generator clock,
CLKG.

Output. CLKG, inverted as determined by CLKXP,
is driven out on CLKX.

21.9.18.2 Other Considerations
If the sample rate generator creates a clock signal (CLKG) that is derived from an external input clock, the
GSYNC bit determines whether CLKG is kept synchronized with pulses on the FSR pin. For more details,
see Section 21.4.3.
In the clock stop mode (CLKSTP = 10b or 11b), the McBSP can act as a master or as a slave in the SPI
protocol. If the McBSP is a master, make sure that CLKXM = 1 so that CLKX is an output to supply the
master clock to any slave devices. If the McBSP is a slave, make sure that CLKXM = 0 so that CLKX is an
input to accept the master clock signal.

21.9.19 Set the Transmit Clock Polarity
Table 21-68. Register Bit Used to Set Transmit Clock Polarity
Register
PCR

Bit

Name

Function

1

CLKXP

Transmit clock polarity
CLKXP = 0

Transmit data sampled on rising edge of CLKX.

CLKXP = 1

Transmit data sampled on falling edge of CLKX.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Type

Reset
Value

R/W

0

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2315

Emulation and Reset Considerations

www.ti.com

21.9.19.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
Transmit frame-synchronization pulses can be either generated internally by the sample rate generator
(see Section 21.4.2) or driven by an external source. The source of frame synchronization is selected by
programming the mode bit, FSXM, in PCR. FSX is also affected by the FSGM bit in SRGR2. For
information about the effects of FSXM and FSGM, see Section 21.9.15). Similarly, transmit clocks can be
selected to be inputs or outputs by programming the mode bit, CLKXM, in the PCR (see Section 21.9.18).
When FSR and FSX are inputs (FSXM = FSRM= 0, external frame-synchronization pulses), the McBSP
detects them on the internal falling edge of clock, internal MCLKR, and internal CLKX, respectively. The
receive data arriving at the DR pin is also sampled on the falling edge of internal MCLKR. These internal
clock signals are either derived from external source via CLK(R/X) pins or driven by the sample rate
generator clock (CLKG) internal to the McBSP.
When FSR and FSX are outputs, implying that they are driven by the sample rate generator, they are
generated (transition to their active state) on the rising edge of internal clock, CLK(R/X). Similarly, data on
the DX pin is output on the rising edge of internal CLKX.
FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR) configure the polarities of the FSR,
FSX, MCLKR, and CLKX signals, respectively. All frame-synchronization signals (internal FSR, internal
FSX) that are internal to the serial port are active high. If the serial port is configured for external frame
synchronization (FSR/FSX are inputs to McBSP), and FSRP = FSXP = 1, the external active-low framesynchronization signals are inverted before being sent to the receiver (internal FSR) and transmitter
(internal FSX). Similarly, if internal synchronization (FSR/FSX are output pins and GSYNC = 0) is
selected, the internal active-high frame-synchronization signals are inverted, if the polarity bit FS(R/X)P =
1, before being sent to the FS(R/X) pin.
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out
transmit data. Data is always transmitted on the rising edge of internal CLKX. If CLKXP = 1 and external
clocking is selected (CLKXM = 0 and CLKX is an input), the external falling-edge triggered input clock on
CLKX is inverted to a rising-edge triggered clock before being sent to the transmitter. If CLKXP = 1 and
internal clocking is selected (CLKXM = 1 and CLKX is an output pin), the internal (rising-edge triggered)
clock, internal CLKX, is inverted before being sent out on the MCLKX pin.
Similarly, the receiver can reliably sample data that is clocked with a rising edge clock (by the transmitter).
The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is
always sampled on the falling edge of internal MCLKR. Therefore, if CLKRP = 1 and external clocking is
selected (CLKRM = 0 and CLKR is an input pin), the external rising-edge triggered input clock on CLKR is
inverted to a falling-edge triggered clock before being sent to the receiver. If CLKRP = 1 and internal
clocking is selected (CLKRM = 1), the internal falling-edge triggered clock is inverted to a rising-edge
triggered clock before being sent out on the MCLKR pin.
CLKRP = CLKXP in a system where the same clock (internal or external) is used to clock the receiver and
transmitter. The receiver uses the opposite edge as the transmitter to ensure valid setup and hold of data
around this edge (see Figure 21-58).
Figure 21-60 shows how data clocked by an external serial device using a rising edge can be sampled by
the McBSP receiver on the falling edge of the same clock.
Figure 21-60. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a
Falling Edge
Internal
CLKR

ÁÁ
ÁÁ
ÁÁ
ÁÁ

Data setup

DR

Data hold
B7

B6

21.10 Emulation and Reset Considerations
This section covers the following topics:
2316

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Emulation and Reset Considerations

www.ti.com

•
•

How to program McBSP response to a breakpoint in the high-level language debugger (see
Section 21.10.1)
How to reset and initialize the various parts of the McBSP (see Section 21.10.2)

21.10.1 McBSP Emulation Mode
FREE and SOFT are special emulation bits in SPCR2 that determine the state of the McBSP when a
breakpoint is encountered in the high-level language debugger. If FREE = 1, the clock continues to run
upon a software breakpoint and data is still shifted out. When FREE = 1, the SOFT bit is a don't care.
If FREE = 0, the SOFT bit takes effect. If SOFT = 0 when breakpoint occurs, the clock stops immediately,
aborting a transmission. If SOFT = 1 and a breakpoint occurs while transmission is in progress, the
transmission continues until completion of the transfer and then the clock halts. These options are listed in
Table 21-69.
The McBSP receiver functions in a similar fashion. If a mode other than the immediate stop mode (SOFT
= FREE = 0) is chosen, the receiver continues running and an overrun error is possible.
Table 21-69. McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2
FREE

SOFT

McBSP Emulation Mode

0

0

Immediate stop mode (reset condition)
The transmitter or receiver stops immediately in response to a breakpoint.

0

1

Soft stop mode
When a breakpoint occurs, the transmitter stops after completion of the current word. The receiver is
not affected.

1

0 or 1

Free run mode
The transmitter and receiver continue to run when a breakpoint occurs.

21.10.2 Resetting and Initializing McBSPs
21.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
Table 21-70 shows the state of McBSP pins when the serial port is reset due to direct receiver or
transmitter reset on the 2833x device.
Table 21-70. Reset State of Each McBSP Pin
Pin

Possible State(s) (1)

State Forced by Device
Reset

State Forced by
Receiver/Transmitter Reset

Receiver reset (RRST = 0 and GRST = 1)
MDRx

I

GPIO-input

Input

MCLKRx

I/O/Z

GPIO-input

Known state if input; MCLKR running if output

MFSRx

I/O/Z

GPIO-input

Known state if input; FSRP inactive state if output

Transmitter reset (XRST = 0 and GRST = 1)
MDXx

O/Z

GPIO Input

High impedance

MCLKXx

I/O/Z

GPIO-input

Known state if input; CLKX running if output

MFSXx

I/O/Z

GPIO-input

Known state if input; FSXP inactive state if output

(1)

In Possible State(s) column, I = Input, O = Output, Z = High impedance. In the 28x family, at device reset, all I/Os default to
GPIO function and generally as inputs.

21.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
When the McBSP is reset in either of the above two ways, the machine is reset to its initial state, including
reset of all counters and status bits. The receive status bits include RFULL, RRDY, and RSYNCERR. The
transmit status bits include XEMPTY, XRDY, and XSYNCERR.
• Device reset. When the whole DSP is reset (XRS signal is driven low), all McBSP pins are in GPIO
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2317

Emulation and Reset Considerations

•

•

www.ti.com

mode. When the device is pulled out of reset, the clock to the McBSP modules remains disabled.
McBSP reset. When the receiver and transmitter reset bits, RRST and XRST, are loaded with 0s, the
respective portions of the McBSP are reset and activity in the corresponding section of the serial port
stops. Input-only pins such as MDRx, and all other pins that are configured as inputs are in a known
state. The MFSRx and MFSXx pins are driven to their inactive state if they are not outputs. If the
MCLKR and MCLKX pins are programmed as outputs, they are driven by CLKG, provided that GRST
= 1. Lastly, the MDXx pin is in the high-impedance state when the transmitter and/or the device is
reset.
During normal operation, the sample rate generator is reset if the GRST bit is cleared. GRST must be
0 only when neither the transmitter nor the receiver is using the sample rate generator. In this case,
the internal sample rate generator clock (CLKG) and its frame-synchronization signal (FSG) are driven
inactive low.
When the sample rate generator is not in the reset state (GRST = 1), pins MFSRx and MFSXx are in
an inactive state when RRST = 0 and XRST = 0, respectively, even if they are outputs driven by FSG.
This ensures that when only one portion of the McBSP is in reset, the other portion can continue
operation when GRST = 1 and its frame synchronization is driven by FSG.
Sample rate generator reset. The sample rate generator is reset when GRST is loaded with 0.
When neither the transmitter nor the receiver is fed by CLKG and FSG, you can reset the sample rate
generator by clearing GRST. In this case, CLKG and FSG are driven inactive low. If you then set
GRST, CLKG starts and runs as programmed. Later, if GRST = 1, FSG pulses active high after the
programmed number of CLKG cycles has elapsed.

21.10.2.3 McBSP Initialization Procedure
The serial port initialization procedure is as follows:
1. Make XRST = RRST = GRST = 0 in SPCR[1,2]. If coming out of a device reset, this step is not
required.
2. While the serial port is in the reset state, program only the McBSP configuration registers (not the data
registers) as required.
3. Wait for two clock cycles. This ensures proper internal synchronization.
4. Set up data acquisition as required (such as writing to DXR[1,2]).
5. Make XRST = RRST = 1 to enable the serial port. Make sure that as you set these reset bits, you do
not modify any of the other bits in SPCR1 and SPCR2. Otherwise, you change the configuration you
selected in step 2.
6. Set FRST = 1, if internally generated frame synchronization is required.
7. Wait two clock cycles for the receiver and transmitter to become active.
Alternatively, on either write (step 1 or 5), the transmitter and receiver can be placed in or taken out of
reset individually by modifying the desired bit.
The above procedure for reset/initialization can be applied in general when the receiver or transmitter
must be reset during its normal operation and when the sample rate generator is not used for either
operation.

2318

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Data Packing Examples

www.ti.com

NOTE:
1.
2.

3.

4.

The necessary duration of the active-low period of XRST or RRST is at least two
MCLKR/CLKX cycles.
The appropriate bits in serial port configuration registers SPCR[1,2], PCR, RCR[1,2],
XCR[1,2], and SRGR[1,2] must only be modified when the affected portion of the serial
port is in its reset state.
In most cases, the data transmit registers (DXR[1,2]) must be loaded by the CPU or by
the DMA controller only when the transmitter is enabled (XRST = 1). An exception to
this rule is when these registers are used for companding internal data (see
Section 21.3.2.2).
The bits of the channel control registers—MCR[1,2], RCER[A-H], XCER[A-H]—can be
modified at any time as long as they are not being used by the current
reception/transmission in a multichannel selection mode.

21.10.2.4 Resetting the Transmitter While the Receiver is Running
shows values in the control registers that reset and configure the transmitter while the receiver is running.
Example 21-1. Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
SPCR1 = 0001h SPCR2 = 0030h
; The receiver is running with the receive interrupt (RINT) triggered by the
; receiver ready bit (RRDY). The transmitter is in its reset state
. The transmit interrupt (XINT) will be triggered by the transmit frame-sync
; error bit (XSYNCERR). PCR = 0900h
; Transmit frame synchronization is generated internally according to the
; FSGM bit of SRGR2.
; The transmit clock is driven by an external source.
; The receive clock continues to be driven by sample rate generator. The input clock
; of the sample rate generator is supplied by the CPU clock SRGR1 = 0001h SRGR2 = 2000h
; The CPU clock is the input clock for the sample rate generator. The sample
; rate generator divides the CPU clock by 2 to generate its output clock (CLKG).
; Transmit frame synchronization is tied to the automatic copying of data from
; the DXR(s) to the XSR(s). XCR1 = 0740h XCR2 = 8321h
; The transmit frame has two phases. Phase 1 has eight 16-bit words. Phase 2
; has four 12-bit words. There is 1-bit data delay between the start of a
; frame-sync pulse and the first data bit
; transmitted. SPCR2 = 0031h
; The transmitter is taken out of reset.

21.11 Data Packing Examples
This section shows two ways to implement data packing in the McBSP.

21.11.1 Data Packing Using Frame Length and Word Length
Frame length and word length can be manipulated to effectively pack data. For example, consider a
situation where four 8-bit words are transferred in a single-phase frame as shown in Figure 21-61. In this
case:
• (R/X)PHASE = 0: Single-phase frame
• (R/X)FRLEN1 = 0000011b: 4-word frame
• (R/X)WDLEN1 = 000b: 8-bit words
Four 8-bit data words are transferred to and from the McBSP by the CPU or by the DMA controller. Thus,
four reads from DRR1 and four writes to DXR1 are necessary for each frame.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2319

Data Packing Examples

www.ti.com

ÁÁ
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
Á
ÁÁ
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
Á
Á
Á
Á
Á
Á
Figure 21-61. Four 8-Bit Data Words Transferred To/From the McBSP
Word 1

CLKR
FSR
DR

RSR1 to RBR1 copy

CLKX
FSX
DX

Word 3

Word 2

DXR1 to XSR1 copy

RSR1 to RBR1 copy

DXR1 to XSR1 copy

Word 4

RSR1 to RBR1 copy

DXR1 to XSR1 copy

RSR1 to RBR1 copy

DXR1 to XSR1 copy

This data can also be treated as a single-phase frame consisting of one 32-bit data word, as shown in
Figure 21-62. In this case:
• (R/X)PHASE = 0: Single-phase frame
• (R/X)FRLEN1 = 0000000b: 1-word frame
• (R/X)WDLEN1 = 101b: 32-bit word
Two 16-bit data words are transferred to and from the McBSP by the CPU or DMA controller. Thus, two
reads, from DRR2 and DRR1, and two writes, to DXR2 and DXR1, are necessary for each frame. This
results in only half the number of transfers compared to the previous case. This manipulation reduces the
percentage of bus time required for serial port data movement.
NOTE: When the word length is larger than 16 bits, make sure you access DRR2/DXR2 before you
access DRR1/DXR1. McBSP activity is tied to accesses of DRR1/DXR1. During the
reception of 24-bit or 32-bit words, read DRR2 and then read DRR1. Otherwise, the next
RBR[1,2]-to-DRR[1,2] copy occurs before DRR2 is read. Similarly, during the transmission of
24-bit or 32-bit words, write to DXR2 and then write to DXR1. Otherwise, the next DXR[1,2]to-XSR[1,2] copy occurs before DXR2 is loaded with new data.

ÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
Á
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
Á
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
Á
ÁÁ
Á
ÁÁ
Figure 21-62. One 32-Bit Data Word Transferred To/From the McBSP
Word 1

CLKR
FSR
DR

RBR2 to DRR2 copy

RBR1 to DRR1 copy

CLKX
FSX
DX

DXR2 to XSR2 copy

2320

Multichannel Buffered Serial Port (McBSP)

DXR1 to XSR1 copy

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Data Packing Examples

www.ti.com

21.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
When there are multiple words per frame, you can implement data packing by increasing the word length
(defining a serial word with more bits) and by ignoring frame-synchronization pulses. First, consider
Figure 21-63, which shows the McBSP operating at the maximum packet frequency. Here, each frame
only has a single 8-bit word. Notice the frame-synchronization pulse that initiates each frame transfer for
reception and for transmission. For reception, this configuration requires one read operation for each
word. For transmission, this configuration requires one write operation for each word.

ÁÁ
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
ÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
ÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
ÁÁ
ÁÁ
Á
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Á
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁÁÁ
Á
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
Á
Á
Á
Á
Á
Á

Figure 21-63. 8-Bit Data Words Transferred at Maximum Packet Frequency
Word 1

Word 3

Word 2

Word 4

CLKR
FSR

DR

RBR1 to DRR1 copy

RBR1 to DRR1 copy

RBR1 to DRR1 copy

RBR1 to DRR1 copy

CLKX

FSX
DX

DXR1 to XSR1 copy

DXR1 to XSR1 copy

DXR1 to XSR1 copy

DXR1 to XSR1 copy

Figure 21-64 shows the McBSP configured to treat this data stream as a continuous 32-bit word. In this
example, the McBSP responds to an initial frame-synchronization pulse. However, (R/X)FIG = 1 so that
the McBSP ignores subsequent pulses. Only two read transfers or two write transfers are needed every
32 bits. This configuration effectively reduces the required bus bandwidth to half the bandwidth needed to
transfer four 8-bit words.

ÁÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
Á
Á
Á
ÁÁ
ÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁÁÁÁ
ÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
Á
Á
Á
Á

Figure 21-64. Configuring the Data Stream of Figure 21-63 as a Continuous 32-Bit Word
Word 1

CLKR

FSR
DR

Frame ignored

Frame ignored

RBR2 to DRR2 copy

CLKX
FSX
DX

Frame ignored

DXR2 to XSR2 copy

Frame ignored

RBR1 to DRR1 copy

Frame ignored

Frame ignored

DXR1 to XSR1 copy

21.12 Interrupt Generation
McBSP registers can be programmed to receive and transmit data through DRR2/DRR1 and DXR2/DXR1
registers, respectively. The CPU can directly access these registers to move data from memory to these
registers. Interrupt signals will be based on these register pair contents and its related flags.
MRINT/MXINT will generate CPU interrupts for receive and transmit conditions.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2321

Interrupt Generation

www.ti.com

21.12.1 McBSP Receive Interrupt Generation
In the McBSP module, data receive and error conditions generate two sets of interrupt signals. One set is
used for the CPU and the other set is for DMA.
Figure 21-65. Receive Interrupt Generation
00
01
10
11

RRDY
EOBR condition
FSR detected
RSYNCERR

RINT
RINTENA

MRINT

RINTM bits

Table 21-71. Receive Interrupt Sources and Signals
McBSP
Interrupt
Signal

Interrupt Flags

Interrupt Enables
in SPCR1

Interrupt Enables

Type of Interrupt

Interrupt Line

MRINT

RINTM
Bits
RINT

RRDY

0

RINTENA

Every word receive

EOBR

1

RINTENA

Every 16 channel

FSR

10

RINTENA

On every FSR

RSYNCERR

11

RINTENA

Frame sync error

block boundary

NOTE: Since X/RINT, X/REVTA, and X/RXFFINT share the same CPU interrupt, it is recommended
that all applications use one of the above selections for interrupt generation. If multiple
interrupt enables are selected at the same time, there is a likelihood of interrupts being
masked or not recognized.

21.12.2 McBSP Transmit Interrupt Generation
McBSP module data transmit and error conditions generate two sets of interrupt signals. One set is used
for the CPU and the other set is for DMA.
Figure 21-66. Transmit Interrupt Generation
00
01
10
11

XRDY
EOBX condition
FSX detected
XSYNCERR

XINT
XINTENA

MXINT

XINTM bits

Table 21-72. Transmit Interrupt Sources and Signals
McBSP
Interrupt
Signal

Interrupt
Flags

XINT

XRDY
EOBX

Interrupt
Enables in
SPCR2

Interrupt
Enables

Type of Interrupt

0

XINTENA

Every word transmit

1

XINTENA

Every 16-channel block boundary

Interrupt
Line

XINTM Bits

2322Multichannel Buffered Serial Port (McBSP)

MXINT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Interrupt Generation

www.ti.com

Table 21-72. Transmit Interrupt Sources and Signals (continued)
McBSP
Interrupt
Signal

Interrupt
Flags

Interrupt
Enables in
SPCR2

Interrupt
Enables

Type of Interrupt

FSX

10

XINTENA

On every FSX

XSYNCERR

11

XINTENA

Frame sync error

Interrupt
Line

21.12.3 Error Flags
The McBSP has several error flags both on receive and transmit channel. Table 21-73 explains the error
flags and their meaning.
Table 21-73. Error Flags
Error Flags

Function

RFULL

Indicates DRR2/DRR1 are not read and RXR register is overwritten

RSYNCERR

Indicates unexpected frame-sync condition, current data reception will abort and restart. Use RINTM
bit 11 for interrupt generation on this condition.

XSYNCERR

Indicates unexpected frame-sync condition, current data transmission will abort and restart. Use
XINTM bit 11 for interrupt generation on this condition.

21.13 McBSP Modes
McBSP, in its normal mode, communicates with various types of Codecs with variable word size. Apart
from this mode, the McBSP uses time-division multiplexed (TDM) data stream while communicating with
other McBSPs or serial devices. The multichannel mode provides flexibility while transmitting/receiving
selected channels or all the channels in a TDM stream.
Table 21-74 provides a quick reference to McBSP mode selection.
Table 21-74. McBSP Mode Selection
Register Bits Used for Mode Selection
MCR1 bit 9,0
No.

McBSP
Word Size

RMCME

RMCM

MCR2 bit 9,1,0
XMCME

XMCM

Mode and Function Description
Normal Mode

1

8/12/16/20/24/32

0

0

0

0

bit words

All types of Codec interface will use this
selection
Multichannel Mode

2

8-bit words

2 Partition or 32-channel Mode
0

1

0

1

0

1

0

10

0

1

0

11

All channels are disabled,unless selected in
X/RCERA/B
All channels are enabled,but masked unless
selected in X/RCERA/B
Symmetric transmit, receive
8 Partition or 128 Channel Mode Transmit/
Receive
Channels selected by X/RCERA to
X/RCERH bits
Multichannel Mode is ON

1

1

1

1

1

1

1

10

All channels are disabled,unless selected in
XCERs

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

All channels are enabled,but masked unless

Multichannel Buffered Serial Port (McBSP) 2323

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Modes

www.ti.com

Table 21-74. McBSP Mode Selection (continued)
Register Bits Used for Mode Selection
MCR1 bit 9,0
No.

McBSP
Word Size

MCR2 bit 9,1,0

RMCME

RMCM

XMCME

XMCM

1

1

1

11

1

0

1

0

Mode and Function Description
selected in XCERs
Symmetric transmit, receive
Continuous Mode - Transmit
Multi-Channel Mode is OFF
All 128 channels are active and enabled

2324

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

21.14 McBSP Registers
This section describes the McBSP registers.

21.14.1 McBSP Base Addresses
Table 21-75. McBSP Base Address Table
Device Registers

Register Name

Start Address

End Address

McbspaRegs

MCBSP_REGS

0x0000_6000

0x0000_603F

McbspbRegs

MCBSP_REGS

0x0000_6040

0x0000_607F

Table 21-76 shows the registers accessible on each McBSP. Section 21.14.2 through Section 21.14.11
describe the register bits.
Table 21-76. McBSP Register Summary
Name

McBSP-A
Address

McBSP-B
Address

Type

Reset Value

Description

Data Registers, Receive, Transmit
DRR2

0x6000

0x6040

R

0x0000

McBSP Data Receive Register 2

DRR1

0x6001

0x6041

R

0x0000

McBSP Data Receive Register 1

DXR2

0x6002

0x6042

W

0x0000

McBSP Data Transmit Register 2

DXR1

0x6003

0x6043

W

0x0000

McBSP Data Transmit Register 1

McBSP Control Registers
SPCR2

0x6004

0x6044

R/W

0x0000

McBSP Serial Port Control Register 2

SPCR1

0x6005

0x6045

R/W

0x0000

McBSP Serial Port Control Register 1

RCR2

0x6006

0x6046

R/W

0x0000

McBSP Receive Control Register 2

RCR1

0x6007

0x6047

R/W

0x0000

McBSP Receive Control Register 1

XCR2

0x6008

0x6048

R/W

0x0000

McBSP Transmit Control Register 2

XCR1

0x6009

0x6049

R/W

0x0000

McBSP Transmit Control Register 1

SRGR2

0x600A

0x604A

R/W

0x0000

McBSP Sample Rate Generator Register 2

SRGR1

0x600B

0x604B

R/W

0x0000

McBSP Sample Rate Generator Register 1

Multichannel Control Registers
MCR2

0x600C

0x604C

R/W

0x0000

McBSP Multichannel Register 2

MCR1

0x600D

0x604D

R/W

0x0000

McBSP Multichannel Register 1

RCERA

0x600E

0x604E

R/W

0x0000

McBSP Receive Channel Enable Register Partition A

RCERB

0x600F

0x604F

R/W

0x0000

McBSP Receive Channel Enable Register Partition B

XCERA

0x6010

0x6050

R/W

0x0000

McBSP Transmit Channel Enable Register Partition A

XCERB

0x6011

0x6051

R/W

0x0000

McBSP Transmit Channel Enable Register Partition B

PCR

0x6012

0x6052

R/W

0x0000

McBSP Pin Control Register

RCERC

0x6013

0x6053

R/W

0x0000

McBSP Receive Channel Enable Register Partition C

RCERD

0x6014

0x6054

R/W

0x0000

McBSP Receive Channel Enable Register Partition D

XCERC

0x6015

0x6055

R/W

0x0000

McBSP Transmit Channel Enable Register Partition C

XCERD

0x6016

0x6056

R/W

0x0000

McBSP Transmit Channel Enable Register Partition D

RCERE

0x6017

0x6057

R/W

0x0000

McBSP Receive Channel Enable Register Partition E

RCERF

0x6018

0x6058

R/W

0x0000

McBSP Receive Channel Enable Register Partition F

XCERE

0x6019

0x6059

R/W

0x0000

McBSP Transmit Channel Enable Register Partition E

XCERF

0x601A

0x605A

R/W

0x0000

McBSP Transmit Channel Enable Register Partition F

RCERG

0x601B

0x605B

R/W

0x0000

McBSP Receive Channel Enable Register Partition G

RCERH

0x601C

0x605C

R/W

0x0000

McBSP Receive Channel Enable Register Partition H

XCERG

0x601D

0x605D

R/W

0x0000

McBSP Transmit Channel Enable Register Partition G

XCERH

0x601E

0x605E

R/W

0x0000

McBSP Transmit Channel Enable Register Partition H

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP) 2325

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-76. McBSP Register Summary (continued)
Name
MFFINT

McBSP-A
Address

McBSP-B
Address

Type

Reset Value

0x6023

0x6063

R/W

0x0000

Description
McBSP Interrupt Enable Register

21.14.2 Data Receive Registers (DRR[1,2])
The CPU or the DMA controller reads received data from one or both of the data receive registers (see
Figure 21-67). If the serial word length is 16 bits or smaller, only DRR1 is used. If the serial length is larger
than 16 bits, both DRR1 and DRR2 are used and DRR2 holds the most significant bits. Each frame of
receive data in the McBSP can have one phase or two phases, each with its own serial word length.
Figure 21-67. Data Receive Registers (DRR2 and DRR1)
DDR2
15

0
High part of receive data (for 20-, 24- or 32-bit data)
R/W-0

DDR1
15

0
Receive data (for 8-, 12-, or 16-bit data) or low part of receive data (for 20-, 24- or 32-bit data)
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

21.14.2.1 Data Travel From Data Receive Pins to the Registers
If the serial word length is 16 bits or smaller, receive data on the MDRx pin is shifted into receive shift
register 1 (RSR1) and then copied into receive buffer register 1 (RBR1). The content of RBR1 is then
copied to DRR1, which can be read by the CPU or by the DMA controller. The RSRs and RBRs are not
accessible to the user.
If the serial word length is larger than 16 bits, receive data on the MDRx pin is shifted into both of the
receive shift registers (RSR2, RSR1) and then copied into both of the receive buffer registers (RBR2,
RBR1). The content of the RBRs is then copied into both of the DRRs, which can be read by the CPU or
by the DMA controller.
If companding is used during the copy from RBR1 to DRR1 (RCOMPAND = 10b or 11b), the 8-bit
compressed data in RBR1 is expanded to a left-justified 16-bit value in DRR1. If companding is disabled,
the data copied from RBR[1,2] to DRR[1,2] is justified and bit filled according to the RJUST bits.

21.14.3 Data Transmit Registers (DXR[1,2])
For transmission, the CPU or the DMA controller writes data to one or both of the data transmit registers
(see Figure 21-68). If the serial word length is 16 bits or smaller, only DXR1 is used. If the word length is
larger than 16 bits, both DXR1 and DXR2 are used and DXR2 holds the most significant bits. Each frame
of transmit data in the McBSP can have one phase or two phases, each with its own serial word length.
Figure 21-68. Data Transmit Registers (DXR2 and DXR1)
DXR2
15

0
High part of transmit data (for 20-, 24- or 32-bit data)
R/W-0

DXR1
15

0
Transmit data (for 8-, 12-, or 16-bit data) or low part of receive data (for 20-, 24- or 32-bit data)
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2326

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

21.14.3.1 Data Travel From Registers to Data Transmit (DX) Pins
If the serial word length is 16 bits or fewer, data written to DXR1 is copied to transmit shift register 1
(XSR1). From XSR1, the data is shifted onto the DX pin one bit at a time. The XSRs are not accessible.
If the serial word length is more than 16 bits, data written to DXR1 and DXR2 is copied to both transmit
shift registers (XSR2, XSR1). From the XSRs, the data is shifted onto the DX pin one bit at a time.
If companding is used during the transfer from DXR1 to XSR1 (XCOMPAND = 10b or 11b), the McBSP
compresses the 16-bit data in DXR1 to 8-bit data in the μ-law or A-law format in XSR1. If companding is
disabled, the McBSP passes data from the DXR(s) to the XSR(s) without modification.

21.14.4 Serial Port Control Registers (SPCR[1,2])
Each McBSP has two serial port control registers, SPCR1 (Table 21-77) and SPCR2 (Table 21-78). These
registers enable you to:
• Control various McBSP modes: digital loopback mode (DLB), sign-extension and justification mode for
reception (RJUST), clock stop mode (CLKSTP), interrupt modes (RINTM and XINTM), emulation mode
(FREE and SOFT)
• Turn on and off the DX-pin delay enabler (DXENA)
• Check the status of receive and transmit operations (RSYNCERR, XSYNCERR, RFULL, XEMPTY,
RRDY, XRDY)
• Reset portions of the McBSP (RRST, XRST, FRST, GRST)
21.14.4.1 Serial Port Control 1 Register (SPCR1)
The serial port control 1 register (SPCR1) is shown in Figure 21-69 and described in Table 21-77.
Figure 21-69. Serial Port Control 1 Register (SPCR1)
15

14

13

12

11

10

8

DLB

RJUST

CLKSTP

Reserved

R/W-0

R/W-0

R/W-0

R-0

7

6

5

DXENA

Reserved

R/W-0

R/W-0

4

3

2

1

0

RINTM

RSYNCERR

RFULL

RRDY

RRST

R/W-0

R/W-0

R-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-77. Serial Port Control 1 Register (SPCR1) Field Descriptions
Bit

Field

15

DLB

Value

Description
Digital loopback mode bit. DLB disables or enables the digital loopback mode of the McBSP:

0

Disabled
Internal DR is supplied by the MDRx pin. Internal FSR and internal MCLKR can be supplied by their
respective pins or by the sample rate generator, depending on the mode bits FSRM and CLKRM.
Internal DX is supplied by the MDXx pin. Internal FSX and internal CLKX are supplied by their
respective pins or are generated internally, depending on the mode bits FSXM and CLKXM.

1

Enabled
Internal receive signals are supplied by internal transmit signals:
MDRx connected to MDXx
MFSRx connected to MFSXx
MCLKR connected to MCLKXx
This mode allows you to test serial port code with a single DSP. The McBSP transmitter directly
supplies data, frame synchronization, and clocking to the McBSP receiver.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2327

McBSP Registers

www.ti.com

Table 21-77. Serial Port Control 1 Register (SPCR1) Field Descriptions (continued)
Bit
14-13

Field
RJUST

Value
0-3h

Description
Receive sign-extension and justification mode bits. During reception, RJUST determines how data
is justified and bit filled before being passed to the data receive registers (DRR1, DRR2).
RJUST is ignored if you enable a companding mode with the RCOMPAND bits. In a companding
mode, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1.
For more details about the effects of RJUST, see Section 21.8.13.

12-11

CLKSTP

0

Right justify the data and zero fill the MSBs.

1h

Right justify the data and sign-extend the data into the MSBs.

2h

Left justify the data and zero fill the LSBs.

3h

Reserved (do not use)

0-3h

Clock stop mode bits. CLKSTP allows you to use the clock stop mode to support the SPI masterslave protocol. If you will not be using the SPI protocol, you can clear CLKSTP to disable the clock
stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each
data transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP =
11b).
For more details, see Section 21.8.5.

0-1h

10-8
7

6
5-4

Reserved

Clock stop mode, without clock delay

3h

Clock stop mode, with half-cycle clock delay

0

Reserved bits (not available for your use). They are read-only bits and return 0s when read.

DXENA

Reserved
RINTM

Clock stop mode is disabled.

2h

DX delay enabler mode bit. DXENA controls the delay enabler for the DX pin. The enabler creates
an extra delay for turn-on time (for the length of the delay, see the device-specific data sheet). For
more details about the effects of DXENA, see Section 21.9.13.
0

DX delay enabler off

1

DX delay enabler on

0

Reserved

0-3h

Receive interrupt mode bits. RINTM determines which event in the McBSP receiver generates a
receive interrupt (RINT) request. If RINT is properly enabled inside the CPU, the CPU services the
interrupt request; otherwise, the CPU ignores the request.

0

The McBSP sends a receive interrupt (RINT) request to the CPU when the RRDY bit changes from
0 to 1, indicating that receive data is ready to be read (the content of RBR[1,2] has been copied to
DRR[1,2]):
Regardless of the value of RINTM, you can check RRDY to determine whether a word transfer is
complete.
The McBSP sends a RINT request to the CPU when 16 enabled bits have been received on the DR
pin.

1h

In the multichannel selection mode, the McBSP sends a RINT request to the CPU after every 16channel block is received in a frame.
Outside of the multichannel selection mode, no interrupt request is sent.

2h

The McBSP sends a RINT request to the CPU when each receive frame-synchronization pulse is
detected. The interrupt request is sent even if the receiver is in its reset state.

3h

The McBSP sends a RINT request to the CPU when the RSYNCERR bit is set, indicating a receive
frame-synchronization error.
Regardless of the value of RINTM, you can check RSYNCERR to determine whether a receive
frame-synchronization error occurred.

3

2328

RSYNCERR

Receive frame-sync error bit. RSYNCERR is set when a receive frame-sync error is detected by the
McBSP. If RINTM = 11b, the McBSP sends a receive interrupt (RINT) request to the CPU when
RSYNCERR is set. The flag remains set until you write a 0 to it or reset the receiver.
0

No error

1

Receive frame-synchronization error. For more details about this error, see Section 21.5.3.

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-77. Serial Port Control 1 Register (SPCR1) Field Descriptions (continued)
Bit
2

1

Field

Value

RFULL

Description
Receiver full bit. RFULL is set when the receiver is full with new data and the previously received
data has not been read (receiver-full condition). For more details about this condition, see
Section 21.5.2.

0

No receiver-full condition

1

Receiver-full condition: RSR[1,2] and RBR[1,2] are full with new data, but the previous data in
DRR[1,2] has not been read.

RRDY

Receiver ready bit. RRDY is set when data is ready to be read from DRR[1,2]. Specifically, RRDY
is set in response to a copy from RBR1 to DRR1.
If the receive interrupt mode is RINTM = 00b, the McBSP sends a receive interrupt request to the
CPU when RRDY changes from 0 to 1.
Also, when RRDY changes from 0 to 1, the McBSP sends a receive synchronization event (REVT)
signal to the DMA controller.
0

Receiver not ready
When the content of DRR1 is read, RRDY is automatically cleared.

1

Receiver ready: New data can be read from DRR[1,2].
Important: If both DRRs are required (word length larger than 16 bits), the CPU or the DMA
controller must read from DRR2 first and then from DRR1. As soon as DRR1 is read, the next
RBR-to-DRR copy is initiated. If DRR2 is not read first, the data in DRR2 is lost.

0

RRST

Receiver reset bit. You can use RRST to take the McBSP receiver into and out of its reset state.
This bit has a negative polarity; RRST = 0 indicates the reset state.
To read about the effects of a receiver reset, see Section 21.10.2.
0

If you read a 0, the receiver is in its reset state.
If you write a 0, you reset the receiver.

1

If you read a 1, the receiver is enabled.
If you write a 1, you enable the receiver by taking it out of its reset state.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2329

McBSP Registers

www.ti.com

21.14.4.2 Serial Port Control 2 Register (SPCR2)
The serial port control 2 register (SPCR2) is shown in Figure 21-70 and described in Table 21-78.
Figure 21-70. Serial Port Control 2 Register (SPCR2)
15

10

9

8

Reserved

FREE

SOFT

R-0

R/W-0

R/W-0

7

6

3

2

1

0

FRST

GRST

5
XINTM

4

XSYNCERR

XEMPTY

XRDY

XRST

R/W-0

R/W-0

R/W-0

R/W-0

R-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-78. Serial Port Control 2 Register (SPCR2) Field Descriptions
Bit
15-10

Field
Reserved

Value
0

Description
Reserved bits (not available for your use). They are read-only bits and return 0s when read.

9

FREE

Free run bit. When a breakpoint is encountered in the high-level language debugger, FREE determines
whether the McBSP transmit and receive clocks continue to run or whether they are affected as
determined by the SOFT bit. When one of the clocks stops, the corresponding data transfer
(transmission or reception) stops.

8

SOFT

Soft stop bit. When FREE = 0, SOFT determines the response of the McBSP transmit and receive
clocks when a breakpoint is encountered in the high-level language debugger. When one of the clocks
stops, the corresponding data transfer (transmission or reception) stops.

7

FRST

Frame-synchronization logic reset bit. The sample rate generator of the McBSP includes framesynchronization logic to generate an internal frame-synchronization signal. You can use FRST to take
the frame-synchronization logic into and out of its reset state. This bit has a negative polarity; FRST =
0 indicates the reset state.
0

If you read a 0, the frame-synchronization logic is in its reset state.
If you write a 0, you reset the frame-synchronization logic.
In the reset state, the frame-synchronization logic does not generate a frame-synchronization signal
(FSG).

1

If you read a 1, the frame-synchronization logic is enabled.
If you write a 1, you enable the frame-synchronization logic by taking it out of its reset state.
When the frame-synchronization logic is enabled (FRST = 1) and the sample rate generator as a
whole is enabled (GRST = 1), the frame-synchronization logic generates the frame-synchronization
signal FSG as programmed.

6

GRST

Sample rate generator reset bit. You can use GRST to take the McBSP sample rate generator into and
out of its reset state. This bit has a negative polarity; GRST = 0 indicates the reset state.
To read about the effects of a sample rate generator reset, see Section 21.10.2.
0

If you read a 0, the sample rate generator is in its reset state.
If you write a 0, you reset the sample rate generator.
If GRST = 0 due to a reset, CLKG is driven by the CPU clock divided by 2, and FSG is driven low
(inactive). If GRST = 0 due to program code, CLKG and FSG are both driven low (inactive).

1

If you read a 1, the sample rate generator is enabled.
If you write a 1, you enable the sample rate generator by taking it out of its reset state.
When enabled, the sample rate generator generates the clock signal CLKG as programmed in the
sample rate generator registers. If FRST = 1, the generator also generates the frame-synchronization
signal FSG as programmed in the sample rate generator registers.

2330

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-78. Serial Port Control 2 Register (SPCR2) Field Descriptions (continued)
Bit

Field

5-4

XINTM

Value

Description

0-3h

Transmit interrupt mode bits. XINTM determines which event in the McBSP transmitter generates a
transmit interrupt (XINT) request. If XINT is properly enabled, the CPU services the interrupt request;
otherwise, the CPU ignores the request.

0

The McBSP sends a transmit interrupt (XINT) request to the CPU when the XRDY bit changes from 0
to 1, indicating that transmitter is ready to accept new data (the content of DXR[1,2] has been copied
to XSR[1,2]).
Regardless of the value of XINTM, you can check XRDY to determine whether a word transfer is
complete.
The McBSP sends an XINT request to the CPU when 16 enabled bits have been transmitted on the
DX pin.

1h

In the multichannel selection mode, the McBSP sends an XINT request to the CPU after every 16channel block is transmitted in a frame.
Outside of the multichannel selection mode, no interrupt request is sent.

2h

The McBSP sends an XINT request to the CPU when each transmit frame-synchronization pulse is
detected. The interrupt request is sent even if the transmitter is in its reset state.

3h

The McBSP sends an XINT request to the CPU when the XSYNCERR bit is set, indicating a transmit
frame-synchronization error.
Regardless of the value of XINTM, you can check XSYNCERR to determine whether a transmit framesynchronization error occurred.

3

XSYNCERR

Transmit frame-synchronization error bit. XSYNCERR is set when a transmit frame-synchronization
error is detected by the McBSP. If XINTM = 11b, the McBSP sends a transmit interrupt (XINT) request
to the CPU when XSYNCERR is set. The flag remains set until you write a 0 to it or reset the
transmitter.
If XINTM = 11b, writing a 1 to XSYNCERR triggers a transmit interrupt just as if a transmit framesynchronization error occurred.
For details about this error see Section 21.5.6.

2

0

No error

1

Transmit frame-synchronization error

XEMPTY

Transmitter empty bit. XEMPTY is cleared when the transmitter is ready to send new data but no new
data is available (transmitter-empty condition). This bit has a negative polarity; a transmitter-empty
condition is indicated by XEMPTY = 0.
0

Transmitter-empty condition
Typically this indicates that all the bits of the current word have been transmitted but there is no new
data in DXR1. XEMPTY is also cleared if the transmitter is reset and then restarted.
For more details about this error condition, see Section 21.5.5.

1
1

XRDY

No transmitter-empty condition
Transmitter ready bit. XRDY is set when the transmitter is ready to accept new data in DXR[1,2].
Specifically, XRDY is set in response to a copy from DXR1 to XSR1.
If the transmit interrupt mode is XINTM = 00b, the McBSP sends a transmit interrupt (XINT) request to
the CPU when XRDY changes from 0 to 1.
Also, when XRDY changes from 0 to 1, the McBSP sends a transmit synchronization event (XEVT)
signal to the DMA controller.

0

Transmitter not ready
When DXR1 is loaded, XRDY is automatically cleared.

1

Transmitter ready: DXR[1,2] is ready to accept new data.
If both DXRs are needed (word length larger than 16 bits), the CPU or the DMA controller must load
DXR2 first and then load DXR1. As soon as DXR1 is loaded, the contents of both DXRs are copied to
the transmit shift registers (XSRs), as described in the next step. If DXR2 is not loaded first, the
previous content of DXR2 is passed to the XSR2.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2331

McBSP Registers

www.ti.com

Table 21-78. Serial Port Control 2 Register (SPCR2) Field Descriptions (continued)
Bit

Field

0

XRST

Value

Description
Transmitter reset bit. You can use XRST to take the McBSP transmitter into and out of its reset state.
This bit has a negative polarity; XRST = 0 indicates the reset state.
To read about the effects of a transmitter reset, see Section 21.10.2.

0

If you read a 0, the transmitter is in its reset state.
If you write a 0, you reset the transmitter.

1

If you read a 1, the transmitter is enabled.
If you write a 1, you enable the transmitter by taking it out of its reset state.

21.14.5 Receive Control Registers (RCR[1, 2])
Each McBSP has two receive control registers, RCR1 (Table 21-79) and RCR2 (Table 21-81). These
registers enable you to:
• Specify one or two phases for each frame of receive data (RPHASE)
• Define two parameters for phase 1 and (if necessary) phase 2: the serial word length (RWDLEN1,
RWDLEN2) and the number of words (RFRLEN1, RFRLEN2)
• Choose a receive companding mode, if any (RCOMPAND)
• Enable or disable the receive frame-synchronization ignore function (RFIG)
• Choose a receive data delay (RDATDLY)
21.14.5.1 Receive Control Register 1 (RCR1)
The receive control register 1 (RCR1) is shown in Figure 21-71 and described in Table 21-79.
Figure 21-71. Receive Control Register 1 (RCR1)
15

14

8

Reserved

RFRLEN1

R-0

R/W-0

7

5

4

0

RWDLEN1

Reserved

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-79. Receive Control Register 1 (RCR1) Field Descriptions
Bit

Field

15

Reserved

Value
0

14-8

RFRLEN1

0-7Fh

Description
Reserved bits (not available for your use). They are read-only bits and return 0s when read.
Receive frame length 1 (1 to 128 words). Each frame of receive data can have one or two phases,
depending on value that you load into the RPHASE bit. If a single-phase frame is selected, RFRLEN1 in
RCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a dualphase frame is selected, RFRLEN1 determines the number of serial words in phase 1 of the frame, and
RFRLEN2 in RCR2 determines the number of words in phase 2 of the frame. The 7-bit RFRLEN fields
allow up to 128 words per phase. See Table 21-80 for a summary of how you determine the frame
length. This length corresponds to the number of words or logical time slots or channels per framesynchronization period.
Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For
example, if you want a phase length of 128 words in phase 1, load 127 into RFRLEN1.

2332

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-79. Receive Control Register 1 (RCR1) Field Descriptions (continued)
Bit

Field

7-5

RWDLEN1

Value
0-7h

Receive word length 1. Each frame of receive data can have one or two phases, depending on the
value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 in RCR1
selects the length for every serial word received in the frame. If a dual-phase frame is selected,
RWDLEN1 determines the length of the serial words in phase 1 of the frame, and RWDLEN2 in RCR2
determines the word length in phase 2 of the frame.

0

8 bits

1h

12 bits

2h

16 bits

3h

20 bits

4h

24 bits

5h

32 bits

6h-7h
4-0

Description

Reserved

0

Reserved (do not use)
Reserved bits (not available for your use). They are read-only bits and return 0s when read.

Table 21-80. Frame Length Formula for Receive Control 1 Register (RCR1)
RPHASE

RFRLEN1

RFRLEN2

Frame Length

0

0 ≤ RFRLEN1 ≤ 127

Not used

(RFRLEN1 + 1) words

1

0 ≤ RFRLEN1 ≤ 127

0 ≤ RFRLEN2 ≤ 127

(RFRLEN1 + 1) + (RFRLEN2 + 1) words

21.14.5.2 Receive Control Register 2 (RCR2)
The receive control register 2 (RCR2) is shown in Figure 21-72 and described in Table 21-81.
Figure 21-72. Receive Control Register 2 (RCR2)
15

14

8

RPHASE

RFRLEN2

R/W-0

R/W-0

7

5

4

3

2

1

0

RWDLEN2

RCOMPAND

RFIG

RDATDLY

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-81. Receive Control Register 2 (RCR2) Field Descriptions
Bit

Field

15

RPHASE

Value

Description
Receive phase number bit. RPHASE determines whether the receive frame has one phase or two
phases. For each phase you can define the serial word length and the number of serial words in the
phase. To set up phase 1, program RWDLEN1 (word length) and RFRLEN1 (number of words). To set
up phase 2 (if there are two phases), program RWDLEN2 and RFRLEN2.

0

Single-phase frame
The receive frame has only one phase, phase 1.

1

Dual-phase frame
The receive frame has two phases, phase 1 and phase 2.

14-8

0-7Fh

Receive frame length 2 (1 to 128 words). Each frame of receive data can have one or two phases,
depending on value that you load into the RPHASE bit. If a single-phase frame is selected, RFRLEN1
in RCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a
dual-phase frame is selected, RFRLEN1 determines the number of serial words in phase 1 of the
frame, and RFRLEN2 in RCR2 determines the number of words in phase 2 of the frame. The 7-bit
RFRLEN fields allow up to 128 words per phase. See Table 21-82 for a summary of how to determine
the frame length. This length corresponds to the number of words or logical time slots or channels per
frame-synchronization period.
Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For
example, if you want a phase length of 128 words in phase 2, load 127 into RFRLEN2.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2333

McBSP Registers

www.ti.com

Table 21-81. Receive Control Register 2 (RCR2) Field Descriptions (continued)
Bit

Field

7-5

RWDLEN2

4-3

Value

RCOMPAND

0-7h

Description
Receive word length 2. Each frame of receive data can have one or two phases, depending on the
value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 in RCR1
selects the length for every serial word received in the frame. If a dual-phase frame is selected,
RWDLEN1 determines the length of the serial words in phase 1 of the frame, and RWDLEN2 in RCR2
determines the word length in phase 2 of the frame.

0

8 bits

1h

12 bits

2h

16 bits

3h

20 bits

4h

24 bits

5h

32 bits

6h-7h

Reserved (do not use)

0-3h

Receive companding mode bits. Companding (COMpress and exPAND) hardware allows compression
and expansion of data in either μ-law or A-law format.
RCOMPAND allows you to choose one of the following companding modes for the McBSP receiver:
For more details about these companding modes, see Section 21.3.2.

2

0

No companding, any size data, MSB received first

1h

No companding, 8-bit data, LSB received first

2h

μ-law companding, 8-bit data, MSB received first

3h

A-law companding, 8-bit data, MSB received first

RFIG

Receive frame-synchronization ignore bit. If a frame-synchronization pulse starts the transfer of a new
frame before the current frame is fully received, this pulse is treated as an unexpected framesynchronization pulse. For more details about the frame-synchronization error condition, see
Figure 21-30.
Setting RFIG causes the serial port to ignore unexpected frame-synchronization signals during
reception. For more details on the effects of RFIG, see Section 21.8.10.1.
0

Frame-synchronization detect. An unexpected FSR pulse causes the receiver to discard the contents
of RSR[1,2] in favor of the new incoming data. The receiver:
1.
2.
3.

1
1-0

RDATDLY

0-3h

Aborts the current data transfer
Sets RSYNCERR in SPCR1
Begins the transfer of a new data word

Frame-synchronization ignore. An unexpected FSR pulse is ignored. Reception continues
uninterrupted.
Receive data delay bits. RDATDLY specifies a data delay of 0, 1, or 2 receive clock cycles after framesynchronization and before the reception of the first bit of the frame. For more details, see
Section 21.8.12.

0

0-bit data delay

1h

1-bit data delay

2h

2-bit data delay

3h

Reserved (do not use)

Table 21-82. Frame Length Formula for Receive Control 2 Register (RCR2)
RPHASE

RFRLEN1

RFRLEN2

Frame Length

0

0 ≤ RFRLEN1 ≤ 127

Not used

(RFRLEN1 + 1) words

1

0 ≤ RFRLEN1 ≤ 127

0 ≤ RFRLEN2 ≤ 127

(RFRLEN1 + 1) + (RFRLEN2 + 1) words

21.14.6 Transmit Control Registers (XCR1 and XCR2)
Each McBSP has two transmit control registers, XCR1 (Table 21-83) and XCR2 (Table 21-85). These
registers enable you to:
• Specify one or two phases for each frame of transmit data (XPHASE)
• Define two parameters for phase 1 and (if necessary) phase 2: the serial word length (XWDLEN1,
2334

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

•
•
•

XWDLEN2) and the number of words (XFRLEN1, XFRLEN2)
Choose a transmit companding mode, if any (XCOMPAND)
Enable or disable the transmit frame-sync ignore function (XFIG)
Choose a transmit data delay (XDATDLY)

21.14.6.1 Transmit Control 1 Register (XCR1)
The transmit control 1 register (XCR1) is shown in Figure 21-73 and described in Table 21-83.
Figure 21-73. Transmit Control 1 Register (XCR1)
15

14

8

Reserved

XFRLEN1

R-0

R/W-0

7

5

4

0

XWDLEN1

Reserved

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-83. Transmit Control 1 Register (XCR1) Field Descriptions
Bit

Field

15

Reserved

Value
0

14-8

XFRLEN1

0-7Fh

Description
Reserved bit. Read-only; returns 0 when read.
Transmit frame length 1 (1 to 128 words). Each frame of transmit data can have one or two phases,
depending on value that you load into the XPHASE bit. If a single-phase frame is selected, XFRLEN1
in XCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a
dual-phase frame is selected, XFRLEN1 determines the number of serial words in phase 1 of the
frame and XFRLEN2 in XCR2 determines the number of words in phase 2 of the frame. The 7-bit
XFRLEN fields allow up to 128 words per phase. See Table 21-84 for a summary of how you
determine the frame length. This length corresponds to the number of words or logical time slots or
channels per frame-synchronization period.
Program the XFRLEN fields with [w minus 1], where w represents the number of words per phase. For
example, if you want a phase length of 128 words in phase 1, load 127 into XFRLEN1.

7-5

XWDLEN1

0-3h

0

8 bits

1h

12 bits

2h

16 bits

3h

20 bits

4h

24 bits

5h

32 bits

6h-7h
4-0

Reserved

Transmit word length 1. Each frame of transmit data can have one or two phases, depending on the
value that you load into the XPHASE bit. If a single-phase frame is selected, XWDLEN1 in XCR1
selects the length for every serial word transmitted in the frame. If a dual-phase frame is selected,
XWDLEN1 determines the length of the serial words in phase 1 of the frame and XWDLEN2 in XCR2
determines the word length in phase 2 of the frame.

0

Reserved (do not use)
Reserved bits. They are read-only bits and return 0s when read.

Table 21-84. Frame Length Formula for Transmit Control 1 Register (XCR1)
XPHASE

XFRLEN1

XFRLEN2

Frame Length

0

0 ≤ XFRLEN1 ≤ 127

Not used

(XFRLEN1 + 1) words

1

0 ≤ XFRLEN1 ≤ 127

0 ≤ XFRLEN2 ≤ 127

(XFRLEN1 + 1) + (XFRLEN2 + 1) words

21.14.6.2 Transmit Control 2 Register (XCR2)
The transmit control 2 register (XCR2) is shown in Figure 21-74 and described in Table 21-85.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2335

McBSP Registers

www.ti.com

Figure 21-74. Transmit Control 2 Register (XCR2)
15

14

8

XPHASE

XFRLEN2

R/W-0

R/W-0

7

5

4

3

2

1

0

XWDLEN2

XCOMPAND

XFIG

XDATDLY

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-85. Transmit Control 2 Register (XCR2) Field Descriptions
Bit

Field

15

XPHASE

Value

Description
Transmit phase number bit. XPHASE determines whether the transmit frame has one phase or two
phases. For each phase you can define the serial word length and the number of serial words in the
phase. To set up phase 1, program XWDLEN1 (word length) and XFRLEN1 (number of words). To set
up phase 2 (if there are two phases), program XWDLEN2 and XFRLEN2.

0

Single-phase frame
The transmit frame has only one phase, phase 1.

1

Dual-phase frame
The transmit frame has two phases, phase 1 and phase 2.

14-8

XFRLEN2

0-7Fh

Transmit frame length 2 (1 to 128 words). Each frame of transmit data can have one or two phases,
depending on value that you load into the XPHASE bit. If a single-phase frame is selected, XFRLEN1 in
XCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a dualphase frame is selected, XFRLEN1 determines the number of serial words in phase 1 of the frame and
XFRLEN2 in XCR2 determines the number of words in phase 2 of the frame. The 7-bit XFRLEN fields
allow up to 128 words per phase. See Table 21-86 for a summary of how to determine the frame length.
This length corresponds to the number of words or logical time slots or channels per framesynchronization period.
Program the XFRLEN fields with [w minus 1], where w represents the number of words per phase. For
example, if you want a phase length of 128 words in phase 1, load 127 into XFRLEN1.

7-5

4-3

XWDLEN2

XCOMPAN
D

0-7h

Transmit word length 2. Each frame of transmit data can have one or two phases, depending on the
value that you load into the XPHASE bit. If a single-phase frame is selected, XWDLEN1 in XCR1
selects the length for every serial word transmitted in the frame. If a dual-phase frame is selected,
XWDLEN1 determines the length of the serial words in phase 1 of the frame and XWDLEN2 in XCR2
determines the word length in phase 2 of the frame.

0

8 bits

1h

12 bits

2h

16 bits

3h

20 bits

4h

24 bits

5h

32 bits

6h-7h

Reserved (do not use)

0-3h

Transmit companding mode bits. Companding (COMpress and exPAND) hardware allows compression
and expansion of data in either μ-law or A-law format. For more details, see Section 21.3.2.
XCOMPAND allows you to choose one of the following companding modes for the McBSP transmitter.
For more details about these companding modes, see Section 21.3.2.

2336

0

No companding, any size data, MSB transmitted first

1h

No companding, 8-bit data, LSB transmitted first

2h

μ-law companding, 8-bit data, MSB transmitted first

3h

A-law companding, 8-bit data, MSB transmitted first

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-85. Transmit Control 2 Register (XCR2) Field Descriptions (continued)
Bit

Field

2

XFIG

Value

Description
Transmit frame-synchronization ignore bit. If a frame-synchronization pulse starts the transfer of a new
frame before the current frame is fully transmitted, this pulse is treated as an unexpected framesynchronization pulse.
Setting XFIG causes the serial port to ignore unexpected frame-synchronization pulses during
transmission.

0

Frame-synchronization detect. An unexpected FSX pulse causes the transmitter to discard the content
of XSR[1,2]. The transmitter:
1.
2.
3.

1
1-0

XDATDLY

Aborts the present transmission
Sets XSYNCERR in SPCR2
Begins a new transmission from DXR[1,2]. If new data was written to DXR[1,2] since the last
DXR[1,2]-to-XSR[1,2] copy, the current value in XSR[1,2] is lost. Otherwise, the same data is
transmitted.

Frame-synchronization ignore. An unexpected FSX pulse is ignored. Transmission continues
uninterrupted.

0-3h

Transmit data delay bits. XDATDLY specifies a data delay of 0, 1, or 2 transmit clock cycles after frame
synchronization and before the transmission of the first bit of the frame. For more details, see
Section 21.9.12.

0

0-bit data delay

1h

1-bit data delay

2h

2-bit data delay

3h

Reserved (do not use)

Table 21-86. Frame Length Formula for Transmit Control 2 Register (XCR2)
XPHASE

XFRLEN1

XFRLEN2

Frame Length

0

0 ≤ XFRLEN1 ≤ 127

Not used

(XFRLEN1 + 1) words

1

0 ≤ XFRLEN1 ≤ 127

0 ≤ XFRLEN2 ≤ 127

(XFRLEN1 + 1) + (XFRLEN2 + 1) words

21.14.7 Sample Rate Generator Registers (SRGR1 and SRGR2)
Each McBSP has two sample rate generator registers, SRGR1 (Table 21-87) and SRGR2 (Table 21-88).
The sample rate generator can generate a clock signal (CLKG) and a frame-synchronization signal (FSG).
The registers SRGR1 and SRGR2 enable you to:
• Select the input clock source for the sample rate generator (CLKSM, in conjunction with the SCLKME
bit of PCR)
• Divide down the frequency of CLKG (CLKGDV)
• Select whether internally-generated transmit frame-synchronization pulses are driven by FSG or by
activity in the transmitter (FSGM).
• Specify the width of frame-synchronization pulses on FSG (FWID) and specify the period between
those pulses (FPER)
When an external source (via the MCLKR or MCLKX pin) provides the input clock source for the sample
rate generator:
• If the CLKX/MCLKR pin is used, the polarity of the input clock is selected with CLKXP/CLKRP of PCR.
• The GSYNC bit of SRGR2 allows you to make CLKG synchronized to an external framesynchronization signal on the FSR pin, so that CLKG is kept in phase with the input clock.
21.14.7.1 Sample Rate Generator 1 Register (SRGR1)
The sample rate generator 1 register is shown in Figure 21-75 and described in Table 21-87.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2337

McBSP Registers

www.ti.com

Figure 21-75. Sample Rate Generator 1 Register (SRGR1)
15

8
FWID
R/W-0

7

0
CLKGDV
R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-87. Sample Rate Generator 1 Register (SRGR1) Field Descriptions
Bit

Field

Value

Description

15-8

FWID

0-FFh

Frame-synchronization pulse width bits for FSG
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization
signal, FSG. For frame-synchronization pulses on FSG, (FWID + 1) is the pulse width in CLKG
cycles. The eight bits of FWID allow a pulse width of 1 to 256 CLKG cycles:
0 ≤ FWID ≤ 255
1 ≤ (FWID + 1) ≤ 256 CLKG cycles
The period between the frame-synchronization pulses on FSG is defined by the FPER bits.

7-0

CLKGDV

0-FFh

Divide-down value for CLKG. The sample rate generator can accept an input clock signal and
divide it down according to CLKGDV to produce an output clock signal, CLKG. The frequency
of CLKG is:
CLKG frequency = (Input clock frequency)/ (CLKGDV + 1)
The input clock is selected by the SCLKME and CLKSM bits:
SCLKME

CLKSM

Input Clock For
Sample Rate Generator

0

0

Reserved

0

1

LSPCLK

1

0

Signal on MCLKR pin

1

1

Signal on MCLKX pin

21.14.7.2 Sample Rate Generator 2 Register (SRGR2)
The sample rate generator 2 register (SRGR2) is shown in Figure 21-76 and described in Table 21-88.
Figure 21-76. Sample Rate Generator 2 Register (SRGR2)
15

14

13

12

GSYNC

Reserved

CLKSM

FSGM

11
FPER

8

R/W-0

R/W-0

R/W-1

R/W-0

R/W-0

7

0
FPER
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

2338

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-88. Sample Rate Generator 2 Register (SRGR2) Field Descriptions
Bit

Field

15

GSYNC

Value

Description
Clock synchronization mode bit for CLKG. GSYNC is used only when the input clock source
for the sample rate generator is external—on the MCLKR pin.
When GSYNC = 1, the clock signal (CLKG) and the frame-synchronization signal (FSG)
generated by the sample rate generator are made dependent on pulses on the FSR pin.

0

No clock synchronization
CLKG oscillates without adjustment, and FSG pulses every (FPER + 1) CLKG cycles.

1

Clock synchronization
• CLKG is adjusted as necessary so that it is synchronized with the input clock on the
MCLKR pin.
• FSG pulses. FSG only pulses in response to a pulse on the FSR pin.
The frame-synchronization period defined in FPER is ignored.
For more details, see Section 21.4.3.

14

Reserved

13

CLKSM

Reserved
0

Sample rate generator input clock mode bit. The sample rate generator can accept an input
clock signal and divide it down according to CLKGDV to produce an output clock signal,
CLKG. The frequency of CLKG is:)
CLKG frequency = (input clock frequency)/ (CLKGDV + 1
CLKSM is used in conjunction with the SCLKME bit to determine the source for the input
clock.
A reset selects the CPU clock as the input clock and forces the CLKG frequency to ½ the
LSPCLK frequency.
The input clock for the sample rate generator is taken from the MCLKR pin, depending on
the value of the SCLKME bit of PCR:

1

12

FSGM

11-0

FPER

SCLKME

CLKSM

Input Clock For
Sample Rate Generator

0

0

Reserved

1

0

Signal on MCLKR pin

The input clock for the sample rate generator is taken from the LSPCLK or from the MCLKX
pin, depending on the value of the SCLKME bit of PCR:
SCLKME

CLKSM

Input Clock For
Sample Rate Generator

0

1

LSPCLK

1

1

Signal on MCLKX pin

Sample rate generator transmit frame-synchronization mode bit. The transmitter can get
frame synchronization from the FSX pin (FSXM = 0) or from inside the McBSP (FSXM = 1).
When FSXM = 1, the FSGM bit determines how the McBSP supplies frame-synchronization
pulses.
0

If FSXM = 1, the McBSP generates a transmit frame-synchronization pulse when the content
of DXR[1,2] is copied to XSR[1,2].

1

If FSXM = 1, the transmitter uses frame-synchronization pulses generated by the sample
rate generator. Program the FWID bits to set the width of each pulse. Program the FPER bits
to set the period between pulses.

0-FFFh

Frame-synchronization period bits for FSG. The sample rate generator can produce a clock
signal, CLKG, and a frame-synchronization signal, FSG. The period between framesynchronization pulses on FSG is (FPER + 1) CLKG cycles. The 12 bits of FPER allow a
frame-synchronization period of 1 to 4096 CLKG cycles:
0 ≤ FPER ≤ 4095
1 ≤ (FPER + 1) ≤ 4096 CLKG cycles
The width of each frame-synchronization pulse on FSG is defined by the FWID bits.

21.14.8 Multichannel Control Registers (MCR[1,2])
Each McBSP has two multichannel control registers. MCR1 (Table 21-89) has control and status bits (with
an R prefix) for multichannel selection operation in the receiver. MCR2 (Table 21-90) contains the same
type of bits (bit with an X prefix) for the transmitter. These registers enable you to:
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2339

McBSP Registers

•
•
•

www.ti.com

Enable all channels or only selected channels for reception (RMCM)
Choose which channels are enabled/disabled and masked/unmasked for transmission (XMCM)
Specify whether two partitions (32 channels at a time) or eight partitions (128 channels at a time) can
be used (RMCME for reception, XMCME for transmission)
Assign blocks of 16 channels to partitions A and B when the 2-partition mode is selected (RPABLK and
RPBBLK for reception, XPABLK and XPBBLK for transmission)
Determine which block of 16 channels is currently involved in a data transfer (RCBLK for reception,
XCBLK for transmission)

•
•

21.14.8.1 Multichannel Control 1 Register (MCR1)
The multichannel control 1 register (MCR1) is shown in Figure 21-77 and described in Table 21-89.
Figure 21-77. Multichannel Control 1 Register (MCR1)
15

10

7

6

9

8

Reserved

RMCME

RPBBLK

R-0

R/W-0

R/W-0

1

0

RPBBLK

RPABLK

5

4
RCBLK

2

Reserved

RMCM

R/W-0

R/W-0

R-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-89. Multichannel Control 1 Register (MCR1) Field Descriptions
Bit

Field

15-10

Reserved

9

RMCME

Value
0

Description
Reserved bits (not available for your use). They are read-only bits and return 0s when read.
Receive multichannel partition mode bit. RMCME is only applicable if channels can be individually
enabled or disabled for reception (RMCM = 1).
RMCME determines whether only 32 channels or all 128 channels are to be individually selectable.

0

2-partition mode
Only partitions A and B are used. You can control up to 32 channels in the receive multichannel
selection mode (RMCM = 1).
Assign 16 channels to partition A with the RPABLK bits.
Assign 16 channels to partition B with the RPBBLK bits.
You control the channels with the appropriate receive channel enable registers:
RCERA: Channels in partition A
RCERB: Channels in partition B

1

8-partition mode
All partitions (A through H) are used. You can control up to 128 channels in the receive
multichannel selection mode. You control the channels with the appropriate receive channel enable
registers:
RCERA: Channels 0 through 15
RCERB: Channels 16 through 31
RCERC: Channels 32 through 47
RCERD: Channels 48 through 63
RCERE: Channels 64 through 79
RCERF: Channels 80 through 95
RCERG: Channels 96 through 111
RCERH: Channels 112 through 127

2340

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-89. Multichannel Control 1 Register (MCR1) Field Descriptions (continued)
Bit

Field

8-7

RPBBLK

Value
0-3h

Description
Receive partition B block bits
RPBBLK is only applicable if channels can be individually enabled or disabled (RMCM = 1) and the
2-partition mode is selected (RMCME = 0). Under these conditions, the McBSP receiver can accept
or ignore data in any of the 32 channels that are assigned to partitions A and B of the receiver.
The 128 receive channels of the McBSP are divided equally among 8 blocks (0 through 7). When
RPBBLK is applicable, use RPBBLK to assign one of the odd-numbered blocks (1, 3, 5, or 7) to
partition B. Use the RPABLK bits to assign one of the even-numbered blocks (0, 2, 4, or 6) to
partition A.
If you want to use more than 32 channels, you can change block assignments dynamically. You
can assign a new block to one partition while the receiver is handling activity in the other partition.
For example, while the block in partition A is active, you can change which block is assigned to
partition B. The RCBLK bits are regularly updated to indicate which block is active.
When XMCM = 11b (for symmetric transmission and reception), the transmitter uses the receive
block bits (RPABLK and RPBBLK) rather than the transmit block bits (XPABLK and XPBBLK).

6-5

RPABLK

0

Block 1: channels 16 through 31

1h

Block 3: channels 48 through 63

2h

Block 5: channels 80 through 95

3h

Block 7: channels 112 through 127

0-3h

Receive partition A block bits
RPABLK is only applicable if channels can be individually enabled or disabled (RMCM = 1) and the
2-partition mode is selected (RMCME = 0). Under these conditions, the McBSP receiver can accept
or ignore data in any of the 32 channels that are assigned to partitions A and B of the receiver. See
the description for RPBBLK (bits 8-7) for more information about assigning blocks to partitions A
and B.

4-2

RCBLK

1

Reserved

0

RMCM

0

Block 0: channels 0 through 15

1h

Block 2: channels 32 through 47

2h

Block 5: channels 64 through 79

3h

Block 7: channels 96 through 111

0-7h

Receive current block indicator. RCBLK indicates which block fo 16 channels is involved in the
current McBSP reception:

0

Block 0: channels 0 through 15

1h

Block 1: channels 16 through 31

2h

Block 2: channels 32 through 47

3h

Block 3: channels 48 through 63

4h

Block 4: channels 64 through 79

5h

Block 5: channels 80 through 95

6h

Block 6: channels 96 through 111

7h

Block 7: channels 112 through 127

0

Reserved bits (not available for your use). They are read-only bits and return 0s when read.
Receive multichannel selection mode bit. RMCM determines whether all channels or only selected
channels are enabled for reception:

0

All 128 channels are enabled.

1

Multichanneled selection mode. Channels can be individually enabled or disabled.
The only channels enabled are those selected in the appropriate receive channel enable registers
(RCERs). The way channels are assigned to the RCERs depends on the number of receive
channel partitions (2 or 8), as defined by the RMCME bit.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2341

McBSP Registers

www.ti.com

21.14.8.2 Multichannel Control 2 Register (MCR2)
The multichannel control 2 register (MCR2) is shown in Figure 21-78 and described in Table 21-90.
Figure 21-78. Multichannel Control 2 Register (MCR2)
15

10

7

6

9

8

Reserved

XMCME

XPBBLK

R-0

R/W-0

R/W-0

5

4

2

1

0

XPBBLK

XPABLK

XCBLK

XMCM

R/W-0

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-90. Multichannel Control 2 Register (MCR2) Field Descriptions
Bit

Field

15-10

Reserved

9

XMCME

Value
0

Description
Reserved bits (not available for your use). They are read-only bits and return 0s when read.
Transmit multichannel partition mode bit. XMCME determines whether only 32 channels or all 128
channels are to be individually selectable. XMCME is only applicable if channels can be individually
disabled/enabled or masked/unmasked for transmission (XMCM is nonzero).

0

2-partition mode. Only partitions A and B are used. You can control up to 32 channels in the
transmit multichannel selection mode selected with the XMCM bits.
If XMCM = 01b or 10b, assign 16 channels to partition A with the XPABLK bits. Assign 16 channels
to partition B with the XPBBLK bits.
If XMCM = 11b(for symmetric transmission and reception), assign 16 channels to receive partition A
with the RPABLK bits. Assign 16 channels to receive partition B with the RPBBLK bits.
You control the channels with the appropriate transmit channel enable registers:
XCERA: Channels in partition A
XCERB: Channels in partition B

1

8-partition mode. All partitions (A through H) are used. You can control up to 128 channels in the
transmit multichannel selection mode selected with the XMCM bits.
You control the channels with the appropriate transmit channel enable registers:
XCERA: Channels 0 through 15
XCERB: Channels 16 through 31
XCERC: Channels 32 through 47
XCERD: Channels 48 through 63
XCERE: Channels 64 through 79
XCERF: Channels 80 through 95
XCERG: Channels 96 through 111
XCERH: Channels 112 through 127

2342

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-90. Multichannel Control 2 Register (MCR2) Field Descriptions (continued)
Bit

Field

8-7

XPBBLK

Value
0-3h

Description
Transmit partition B block bits
XPBBLK is only applicable if channels can be individually disabled/enabled and masked/unmasked
(XMCM is nonzero) and the 2-partition mode is selected (XMCME = 0). Under these conditions, the
McBSP transmitter can transmit or withhold data in any of the 32 channels that are assigned to
partitions A and B of the transmitter.
The 128 transmit channels of the McBSP are divided equally among 8 blocks (0 through 7). When
XPBBLK is applicable, use XPBBLK to assign one of the odd-numbered blocks (1, 3, 5, or 7) to
partition B, as shown in the following table. Use the XPABLK bit to assign one of the evennumbered blocks (0, 2, 4, or 6) to partition A.
If you want to use more than 32 channels, you can change block assignments dynamically. You
can assign a new block to one partition while the transmitter is handling activity in the other
partition. For example, while the block in partition A is active, you can change which block is
assigned to partition B. The XCBLK bits are regularly updated to indicate which block is active.
When XMCM = 11b (for symmetric transmission and reception), the transmitter uses the receive
block bits (RPABLK and RPBBLK) rather than the transmit block bits (XPABLK and XPBBLK).

6-5

4-2

1-0

0

Block 1: channels 16 through 31

1h

Block 3: channels 48 through 63

2h

Block 5: channels 80 through 95

3h

Block 7: channels 112 through 127

XPABLK

Transmit partition A block bits. XPABLK is only applicable if channels can be individually
disabled/enabled and masked/unmasked (XMCM is nonzero) and the 2-partition mode is selected
(XMCME = 0). Under these conditions, the McBSP transmitter can transmit or withhold data in any
of the 32 channels that are assigned to partitions A and B of the transmitter. See the description for
XPBBLK (bits 8-7) for more information about assigning blocks to partitions A and B.
0

Block 0: channels 0 through 15

1h

Block 2: channels 32 through 47

2h

Block 4: channels 64 through 79

3h

Block 6: channels 96 through 111

XCBLK

XMCM

Transmit current block indicator. XCBLK indicates which block of 16 channels is involved in the
current McBSP transmission:
0

Block 0: channels 0 through 15

1h

Block 1: channels 16 through 31

2h

Block 2: channels 32 through 47

3h

Block 3: channels 48 through 63

4h

Block 4: channels 64 through 79

5h

Block 5: channels 80 through 95

6h

Block 6: channels 96 through 111

7h

Block 7: channels 112 through 127

0-3h

Transmit multichannel selection mode bits. XMCM determines whether all channels or only selected
channels are enabled and unmasked for transmission. For more details on how the channels are
affected, see Section 21.6.7 .

0

No transmit multichannel selection mode is on. All channels are enabled and unmasked. No
channels can be disabled or masked.

1h

All channels are disabled unless they are selected in the appropriate transmit channel enable
registers (XCERs). If enabled, a channel in this mode is also unmasked.
The XMCME bit determines whether 32 channels or 128 channels are selectable in XCERs.

2h

All channels are enabled, but they are masked unless they are selected in the appropriate transmit
channel enable registers (XCERs).
The XMCME bit determines whether 32 channels or 128 channels are selectable in XCERs.

3h

This mode is used for symmetric transmission and reception.
All channels are disabled for transmission unless they are enabled for reception in the appropriate
receive channel enable registers (RCERs). Once enabled, they are masked unless they are also
selected in the appropriate transmit channel enable registers (XCERs).
The XMCME bit determines whether 32 channels or 128 channels are selectable in RCERs and
XCERs.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2343

McBSP Registers

www.ti.com

21.14.9 Pin Control Register (PCR)
Each McBSP has one pin control register (PCR). Table 21-91 describes the bits of PCR. This register
enables you to:
• Choose a frame-synchronization mode for the transmitter (FSXM) and for the receiver (FSRM)
• Choose a clock mode for transmitter (CLKXM) and for the receiver (CLKRM)
• Select the input clock source for the sample rate generator (SCLKME, in conjunction with the CLKSM
bit of SRGR2)
• Choose whether frame-synchronization signals are active low or active high (FSXP for transmission,
FSRP for reception)
• Specify whether data is sampled on the falling edge or the rising edge of the clock signals (CLKXP for
transmission, CLKRP for reception)
The pin control register (PCR) is shown in Figure 21-79 and described in Table 21-91.
Figure 21-79. Pin Control Register (PCR)
15

12

7

11

10

9

8

Reserved

FSXM

FSRM

CLKXM

CLKRM

R-0

R/W-0

R/W-0

R/W-0

R/W-0

3

2

1

0

SCLKME

6
Reserved

4

FSXP

FSRP

CLKXP

CLKRP

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-91. Pin Control Register (PCR) Field Descriptions
Bit

Field

15:12
11

10

2344

Reserved

Value
0

FSXM

Description
Reserved bit (not available for your use). It is a read-only bit and returns a 0 when read.
Transmit frame-synchronization mode bit. FSXM determines whether transmit framesynchronization pulses are supplied externally or internally. The polarity of the signal on the
FSX pin is determined by the FSXP bit.

0

Transmit frame synchronization is supplied by an external source via the FSX pin.

1

Transmit frame synchronization is generated internally by the Sample Rate generator, as
determined by the FSGM bit of SRGR2.

FSRM

Receive frame-synchronization mode bit. FSRM determines whether receive framesynchronization pulses are supplied externally or internally. The polarity of the signal on the
FSR pin is determined by the FSRP bit.
0

Receive frame synchronization is supplied by an external source via the FSR pin.

1

Receive frame synchronization is supplied by the sample rate generator. FSR is an output pin
reflecting internal FSR, except when GSYNC = 1 in SRGR2.

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-91. Pin Control Register (PCR) Field Descriptions (continued)
Bit
9

Field

Value

CLKXM

Description
Transmit clock mode bit. CLKXM determines whether the source for the transmit clock is
external or internal, and whether the MCLKX pin is an input or an output. The polarity of the
signal on the MCLKX pin is determined by the CLKXP bit.
In the clock stop mode (CLKSTP = 10b or 11b), the McBSP can act as a master or as a slave
in the SPI protocol. If the McBSP is a master, make sure that CLKX is an output. If the McBSP
is a slave, make sure that CLKX is an input.
Not in clock stop mode (CLKSTP = 00b or 01b):

0

The transmitter gets its clock signal from an external source via the MCLKX pin.

1

Internal CLKX is driven by the sample rate generator of the McBSP. The MCLKX pin is an
output pin that reflects internal CLKX.
In clock stop mode (CLKSTP = 10b or 11b):

8

0

The McBSP is a slave in the SPI protocol. The internal transmit clock (CLKX) is driven by the
SPI master via the MCLKX pin. The internal receive clock (MCLKR) is driven internally by
CLKX, so that both the transmitter and the receiver are controlled by the external master clock.

1

The McBSP is a master in the SPI protocol. The sample rate generator drives the internal
transmit clock (CLKX). Internal CLKX is reflected on the MCLKX pin to drive the shift clock of
the SPI-compliant slaves in the system. Internal CLKX also drives the internal receive clock
(MCLKR), so that both the transmitter and the receiver are controlled by the internal master
clock.

CLKRM

Receive clock mode bit. The role of CLKRM and the resulting effect on the MCLKR pin depend
on whether the McBSP is in the digital loopback mode (DLB = 1).
The polarity of the signal on the MCLKR pin is determined by the CLKRP bit.
Not in digital loopback mode (DLB = 0):
0

The MCLKR pin is an input pin that supplies the internal receive clock (MCLKR).

1

Internal MCLKR is driven by the sample rate generator of the McBSP. The MCLKR pin is an
output pin that reflects internal MCLKR.
In digital loopback mode (DLB = 1):

7

0

The MCLKR pin is in the high impedance state. The internal receive clock (MCLKR) is driven
by the internal transmit clock (CLKX). CLKX is derived according to the CLKXM bit.

1

Internal MCLKR is driven by internal CLKX. The MCLKR pin is an output pin that reflects
internal MCLKR. CLKX is derived according to the CLKXM bit.

SCLKME

Sample rate generator input clock mode bit. The sample rate generator can produce a clock
signal, CLKG. The frequency of CLKG is:
CLKG freq. = (Input clock frequency) / (CLKGDV + 1)
SCLKME is used in conjunction with the CLKSM bit to select the input clock.
SCLKME

CLKSM

Input Clock For
Sample Rate Generator

0

0

Reserved

0

1

LSPCLK

The input clock for the sample rate generator is taken from the MCLKR pin or from the MCLKX
pin, depending on the value of the CLKSM bit of SRGR2:

6-4
3

2

SCLKME

CLKSM

Input Clock For
Sample Rate Generator

1

0

Signal on MCLKR pin

1

1

Signal on MCLKX pin

Reserved

Reserved

FSXP

Transmit frame-synchronization polarity bit. FSXP determines the polarity of FSX as seen on
the FSX pin.
0

Transmit frame-synchronization pulses are active high.

1

Transmit frame-synchronization pulses are active low.

FSRP

Receive frame-synchronization polarity bit. FSRP determines the polarity of FSR as seen on
the FSR pin.
0

Receive frame-synchronization pulses are active high.

1

Receive frame-synchronization pulses are active low.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP)

Copyright © 2013–2017, Texas Instruments Incorporated

2345

McBSP Registers

www.ti.com

Table 21-91. Pin Control Register (PCR) Field Descriptions (continued)
Bit

Field

1

Value

Description

CLKXP

0

Transmit clock polarity bit. CLKXP determines the polarity of CLKX as seen on the MCLKX pin.
0

Transmit data is sampled on the rising edge of CLKX.

1

Transmit data is sampled on the falling edge of CLKX.

CLKRP

Receive clock polarity bit. CLKRP determines the polarity of CLKR as seen on the MCLKR pin.
0

Receive data is sampled on the falling edge of MCLKR.

1

Receive data is sampled on the rising edge of MCLKR.

Table 21-92. Pin Configuration
Pin

Selected as Output When …

Selected as Input When …

CLKX

CLKXM = 1

CLKXM = 0

FSX

FSXM = 1

FSXM = 0

CLKR

CLKRM = 1

CLKRM = 0

FSR

FSRM = 1

FSRM = 0

21.14.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE,
RCERF, RCERG, RCERH)
Each McBSP has eight receive channel enable registers of the format shown in Figure 21-80. There is
one enable register for each of the receive partitions: A, B, C, D, E, F, G, and H. Table 21-93 provides a
summary description that applies to any bit x of a receive channel enable register.
These memory-mapped registers are only used when the receiver is configured to allow individual
enabling and disabling of the channels (RMCM = 1). For more details about the way these registers are
used, see Section 21.14.10.1.
The receive channel enable registers (RCERA...RCERH) are shown in Figure 21-80 and described in
Table 21-93.
Figure 21-80. Receive Channel Enable Registers (RCERA...RCERH)
15

14

13

12

11

10

9

8

RCE15

RCE14

RCE13

RCE12

RCE11

RCE10

RCE9

RCE8

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

RCE7

RCE6

RCE5

RCE4

RCE3

RCE2

RCE1

RCE0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-93. Receive Channel Enable Registers (RCERA...RCERH) Field Descriptions
Bit

Field

15-0

RCEx

Value

Description
Receive channel enable bit.
For receive multichannel selection mode (RMCM = 1):

0

Disable the channel that is mapped to RCEx.

1

Enable the channel that is mapped to RCEx.

21.14.10.1 RCERs Used in the Receive Multichannel Selection Mode
For multichannel selection operation, the assignment of channels to the RCERs depends on whether 32
or 128 channels are individually selectable, as defined by the RMCME bit. For each of these two cases,
Table 21-94 shows which block of channels is assigned to each of the RCERs used. For each RCER, the
table shows which channel is assigned to each of the bits.
2346

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-94. Use of the Receive Channel Enable Registers
Number of
Selectable
Channels
32
(RMCME = 0)

Block Assignments
RCERx

Block Assigned

Bit in RCERx

Channel Assigned

RCERA

Channels n to (n + 15)

RCE0

Channel n

RCE1

Channel (n + 1)

RCE2

Channel (n + 2)

:

:

RCERB

128
(RMCME = 1)

Channel Assignments

RCERA

RCERB

RCERC

RCERD

RCERE

RCERF

RCERG

The block of channels is chosen with RCE15
the RPABLK bits.

Channel (n + 15)

Channels m to (m + 15)

RCE0

Channel m

RCE1

Channel (m + 1)

RCE2

Channel (m + 2)

:

:

The block of channels is chosen with RCE15
the RPBBLK bits.

Channel (m + 15)

Block 0

RCE0

Channel 0

RCE1

Channel 1

RCE2

Channel 2

:

:

RCE15

Channel 15

RCE0

Channel 16

RCE1

Channel 17

RCE2

Channel 18

:

:

RCE15

Channel 31

RCE0

Channel 32

RCE1

Channel 33

RCE2

Channel 34

:

:

RCE15

Channel 47

RCE0

Channel 48

RCE1

Channel 49

RCE2

Channel 50

:

:

RCE15

Channel 63

RCE0

Channel 64

RCE1

Channel 65

RCE2

Channel 66

:

:

RCE15

Channel 79

RCE0

Channel 80

RCE1

Channel 81

RCE2

Channel 82

:

:

RCE15

Channel 95

RCE0

Channel 96

RCE1

Channel 97

RCE2

Channel 98

:

:

RCE15

Channel 111

Block 1

Block 2

Block 3

Block 4

Block 5

Block 6

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP) 2347

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-94. Use of the Receive Channel Enable Registers (continued)
Number of
Selectable
Channels

Block Assignments

Channel Assignments

RCERx

Block Assigned

Bit in RCERx

Channel Assigned

RCERH

Block 7

RCE0

Channel 112

RCE1

Channel 113

RCE2

Channel 114

:

:

RCE15

Channel 127

21.14.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE,
XCERF, XCERG, XCERH)
Each McBSP has eight transmit channel enable registers of the form shown in Figure 21-81. There is one
for each of the transmit partitions: A, B, C, D, E, F, G, and H. Table 21-95 provides a summary description
that applies to each bit XCEx of a transmit channel enable register.
The XCERs are only used when the transmitter is configured to allow individual disabling/enabling and
masking/unmasking of the channels (XMCM is nonzero).
The transmit channel enable registers (XCERA...XCERH) are shown in Figure 21-81 and described in
Table 21-95.
Figure 21-81. Transmit Channel Enable Registers (XCERA...XCERH)
15

14

13

12

11

10

9

8

XCE15

XCE14

XCE13

XCE12

XCE11

XCE10

XCE9

XCE8

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

XCE7

XCE6

XCE5

XCE4

XCE3

XCE2

XCE1

XCE0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-95. Transmit Channel Enable Registers (XCERA...XCERH) Field Descriptions
Bit

Field

15-0

XCEx

Value

Description
Transmit channel enable bit. The role of this bit depends on which transmit multichannel selection
mode is selected with the XMCM bits.
For multichannel selection when XMCM = 01b
(all channels disabled unless selected):

0

Disable and mask the channel that is mapped to XCEx.

1

Enable and unmask the channel that is mapped to XCEx.
For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):

0

Mask the channel that is mapped to XCEx.

1

Unmask the channel that is mapped to XCEx.
For multichannel selection when XMCM = 11b
(all channels masked unless selected):

2348

0

Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding
receive channel enable bit, this channel's data cannot appear on the DX pin.

1

Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding
receive channel enable bit, full transmission can occur.

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

21.14.11.1 XCERs Used in a Transmit Multichannel Selection Mode
For multichannel selection operation, the assignment of channels to the XCERs depends on whether 32 or
128 channels are individually selectable, as defined by the XMCME bit. These two cases are shown in
Table 21-96. The table shows which block of channels is assigned to each XCER that is used. For each
XCER, the table shows which channel is assigned to each of the bits.
NOTE: When XMCM = 11b (for symmetric transmission and reception), the transmitter uses the
receive channel enable registers (RCERs) to enable channels and uses the XCERs to
unmask channels for transmission.

Table 21-96. Use of the Transmit Channel Enable Registers
Number of
Selectable
Channels
32
(XMCME = 0)

Block Assignments
XCERx

Block Assigned

Bit in XCERx

Channel Assigned

XCERA

Channels n to (n + 15)

XCE0

Channel n

XCE1

Channel (n + 1)

XCE2

Channel (n + 2)

:

:

When XMCM = 01b or 10b, the block
of channels is chosen with the
XPABLK bits. When XMCM = 11b,
the block is chosen with the RPABLK
bits.

XCE15

Channel (n + 15)

Channels m to (m + 15)

XCE0

Channel m

XCE1

Channel (m + 1)

XCE2

Channel (m + 2)

:

:

When XMCM = 01b or 10b, the block
of channels is chosen with the
XPBBLK bits. When XMCM = 11b,
the block is chosen with the RPBBLK
bits.

XCE15

Channel (m + 15)

Block 0

XCE0

Channel 0

XCE1

Channel 1

XCE2

Channel 2

:

:

XCE15

Channel 15

XCE0

Channel 16

XCE1

Channel 17

XCE2

Channel 18

:

:

XCE15

Channel 31

XCE0

Channel 32

XCE1

Channel 33

XCE2

Channel 34

:

:

XCE15

Channel 47

XCE0

Channel 48

XCE1

Channel 49

XCE2

Channel 50

:

:

XCE15

Channel 63

XCERB

128
(XMCME = 1)

Channel Assignments

XCERA

XCERB

XCERC

XCERD

Block 1

Block 2

Block 3

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Multichannel Buffered Serial Port (McBSP) 2349

Copyright © 2013–2017, Texas Instruments Incorporated

McBSP Registers

www.ti.com

Table 21-96. Use of the Transmit Channel Enable Registers (continued)
Number of
Selectable
Channels

Block Assignments

Channel Assignments

XCERx

Block Assigned

Bit in XCERx

Channel Assigned

XCERE

Block 4

XCE0

Channel 64

XCE1

Channel 65

XCE2

Channel 66

:

:

XCE15

Channel 79

XCE0

Channel 80

XCE1

Channel 81

XCE2

Channel 82

:

:

XCE15

Channel 95

XCE0

Channel 96

XCE1

Channel 97

XCE2

Channel 98

:

:

XCE15

Channel 111

XCE0

Channel 112

XCE1

Channel 113

XCE2

Channel 114

:

:

XCE15

Channel 127

XCERF

Block 5

XCERG

Block 6

XCERH

Block 7

21.14.12 McBSP Interrupt Enable Register
Figure 21-82. McBSP Interrupt Enable Register (MFFINT)
15

8
Reserved
R-0

7

2

1

0

Reserved

3

RINT ENA

Reserved

XINT ENA

R-0

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-97. McBSP Interrupt Enable Register (MFFINT) Field Descriptions
Bit

Field

15:3

Reserved

2

RINT ENA

1

Reserved

0

XINT ENA

2350

Value

Description
Reserved
Enable for Receive Interrupt

0

Receive interrupt on RRDY is disabled.

1

Receive interrupt on RRDY is enabled.
Enable for transmit Interrupt

0

Transmit interrupt on XRDY is disabled.

1

Transmit interrupt on XRDY is enabled.

Multichannel Buffered Serial Port (McBSP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 22
SPRUHM8G – December 2013 – Revised September 2017

Controller Area Network (CAN)
This chapter contains a general description of the Controller Area Network (CAN) module. The CAN
module is a serial communications protocol which efficiently supports distributed real-time control with a
high level of reliability. The CAN module supports bit-rates up to 1 Mbit/s and is compliant with the
ISO11898-1 (CAN 2.0B) protocol specification.
Topic

...........................................................................................................................

22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
22.10
22.11
22.12
22.13
22.14
22.15

Overview........................................................................................................
Configuring Device Pins ..................................................................................
Address/Data Bus Bridge .................................................................................
Operating Modes ............................................................................................
Multiple Clock Source .....................................................................................
Interrupt Functionality ....................................................................................
Parity Check Mechanism .................................................................................
Debug Mode ..................................................................................................
Module Initialization .......................................................................................
Configuration of Message Objects ..................................................................
Message Handling ........................................................................................
CAN Bit Timing .............................................................................................
Message Interface Register Sets .....................................................................
Message RAM ..............................................................................................
Registers ......................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Page

2352
2354
2354
2355
2360
2360
2361
2361
2362
2362
2364
2368
2376
2378
2383

Controller Area Network (CAN)

2351

Overview

www.ti.com

22.1 Overview
This device uses the popular CAN IP known as D_CAN.

22.1.1 Features
The CAN module implements the following features:
• CAN protocol version ISO11898-1 (CAN 2.0B)
• Bit rates up to 1 MBit/s
• Multiple clock sources
• 32 message objects (mailboxes)
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus-on after bus-off state by a programmable 32-bit timer
• Message-RAM parity-check mechanism
• Two interrupt lines

22.1.2 Functional Description
The CAN module performs CAN protocol communication according to ISO 11898-1 (identical to Bosch
CAN protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 MBit/s. A CAN
transceiver chip is required for the connection to the physical layer (CAN bus).
For communication on a CAN network, individual message objects can be configured. The message
objects and identifier masks are stored in the Message RAM.
All functions concerning the handling of messages are implemented in the message handler. Those
functions are acceptance filtering, the transfer of messages between the CAN Core and the Message
RAM, and the handling of transmission requests.
The register set of the CAN may be accessed directly by the CPU via the module interface. These
registers are used to control/configure the CAN core and the message handler, and to access the
message RAM.

2352

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Overview

www.ti.com

22.1.3 Block Diagram
Figure 22-1. CAN Block Diagram
CAN_TX

CAN_RX

CAN
CAN Core
Message RAM
Message Handler
Message
RAM
Interface
Registers and Message
Object Access (IFx)

32
Message
Objects
(Mailboxes)

Test Modes
Only
Module Interface

CANINT0

CANINT1

CPU Bus
(8-, 16-, or 32-bit)

22.1.3.1 CAN Core
The CAN core consists of the CAN Protocol Controller and the Rx/Tx Shift register. It handles all ISO
11898-1 protocol functions.
22.1.3.2 Message Handler
The message handler is a state machine which controls the data transfer between the single ported
Message RAM and the CAN Core's Rx/Tx Shift register. It also handles acceptance filtering and the
interrupt request generation as programmed in the control registers.
22.1.3.3 Message RAM
The CAN message RAM enables the storage of 32 CAN messages.
22.1.3.4 Registers and Message Object Access (IFx)
Data consistency is ensured by indirect accesses to the message objects. During normal operation, all
CPU accesses to the message RAM are done through Interface registers.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2353

Configuring Device Pins

www.ti.com

Three Interface Register sets control the CPU read and write accesses to the Message RAM. There are
two Interface register sets for read/write access (IF1 and IF2) and one Interface Register set for read
access only (IF3). See also Section 22.13. The Interface registers have the same word-length as the
message RAM.
In a dedicated test mode, the message RAM is memory mapped and can be directly accessed.

22.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some I/O functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.

22.3 Address/Data Bus Bridge
The CAN module uses a special addressing scheme to support byte accesses. This is the same
addressing that is used on the USB module. It is recommended to only use 32-bit accesses to the CAN
registers using the HWREG_BP() macro which uses the __byte_peripheral_32() intrinsic. If 16-bit
accesses are to be used, the lower 16 bits should be written to the register's address, and the upper 16
bits should be written to the register's address plus 2.
Because of the bus bridge, the view of the CAN module's register space through a CCS memory windows
does not always match the actual addressing. When the view mode is 32-bit or 16-bit, even addresses are
effectively duplicated. Odd addresses should be ignored. When the view mode is 8-bit, even addresses
from within the CAN module are duplicated into the odd addresses in the CCS memory view. Odd
addresses from the module are not displayed.
Table 22-1. CAN Register Access From Software
CAN Register Space

C28x 8 Bit

Address

Reg. Name

Data

Access

Data

0x00

CAN_CTL

0x33221100

__byte((int *)0x00,0)

0x0000

0x04

CAN_ES

0x77665544

__byte((int *)0x01,0)

0x0011

0x08

CAN_ERRC

0xbbaa9988

__byte((int *)0x02,0)

0x0022

0x0C

CAN_BTR

0xffeeddcc

__byte((int *)0x03,0)

0x0033

__byte((int *)0x04,0)

0x0044

__byte((int *)0x05,0)

0x0055

__byte((int *)0x06,0)

0x0066

__byte((int *)0x07,0)

0x0077

__byte((int *)0x08,0)

0x0088

__byte((int *)0x09,0)

0x0099

__byte((int *)0x0A,0)

0x00AA

__byte((int *)0x0B,0)

0x00BB

__byte((int *)0x0C,0)

0x00CC

__byte((int *)0x0D,0)

0x00DD

__byte((int *)0x0E,0)

0x00EE

__byte((int *)0x0F,0)

0x00FF

C28x 16 Bit

C28x 32 Bit

Access

Data

Access

Data

(*((short *)(0x00)))

0x1100

(*((long *)(0x00)))

0x33221100

(*((short *)(0x01)))

0x1100

(*((long *)(0x01)))

0x33221100

2354Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Operating Modes

www.ti.com

Table 22-1. CAN Register Access From Software (continued)
CAN Register Space

C28x 8 Bit

(*((short *)(0x02)))

0x3322

(*((long *)(0x02)))

0x33221100

(*((short *)(0x03)))

0x3322

(*((long *)(0x03)))

0x33221100

(*((short *)(0x04)))

0x5544

(*((long *)(0x04)))

0x77665544

(*((short *)(0x05)))

0x5544

(*((long *)(0x05)))

0x77665544

(*((short *)(0x06)))

0x7766

(*((long *)(0x06)))

0x77665544

(*((short *)(0x07)))

0x7766

(*((long *)(0x07)))

0x77665544

(*((short *)(0x08)))

0x9988

(*((long *)(0x08)))

0xBBAA9988

(*((short *)(0x09)))

0x9988

(*((long *)(0x09)))

0xBBAA9988

(*((short *)(0x0A)))

0xBBAA

(*((long *)(0x0A)))

0xBBAA9988

(*((short *)(0x0B)))

0xBBAA

(*((long *)(0x0B)))

0xBBAA9988

(*((short *)(0x0C)))

0xDDCC

(*((long *)(0x0C)))

0xFFEEDDCC

(*((short *)(0x0D)))

0xDDCC

(*((long *)(0x0D)))

0xFFEEDDCC

(*((short *)(0x0E)))

0xFFEE

(*((long *)(0x0E)))

0xFFEEDDCC

(*((short *)(0x0F)))

0xFFEE

(*((long *)(0x0F)))

0xFFEEDDCC

Table 22-2. CAN Register Access From CCS
CCS 8 Bit

CCS 16 Bit

CCS 32 Bit

Address

Displayed Data

Address

Displayed Data

Address

Displayed Data

0x00

0x00

0x00

0x1100

0x00

0x11001100

0x01

0x00

0x01

0x1100

0x02

0x33223322

0x02

0x22

0x02

0x3322

0x04

0x55445544

0x03

0x22

0x03

0x3322

0x06

0x77667766

0x04

0x44

0x04

0x5544

0x08

0x99889988

0x05

0x44

0x05

0x5544

0x0A

0xBBAABBAA

0x06

0x66

0x06

0x7766

0x0C

0xDDCCDDCC

0x07

0x66

0x07

0x7766

0x0E

0xFFEEFFEE

0x08

0x88

0x08

0x9988

0x09

0x88

0x09

0x9988

0x0A

0xAA

0x0A

0xBBAA

0x0B

0xAA

0x0B

0xBBAA

0x0C

0xCC

0x0C

0xDDCC

0x0D

0xCC

0x0D

0xDDCC

0x0E

0xEE

0x0E

0xFFEE

0x0F

0xEE

0x0F

0xFFEE

22.4 Operating Modes
22.4.1 Initialization
The initialization mode is entered either by software (by setting the Init bit in the CAN_CTL register), by
hardware reset, or by going bus-off. While the Init bit is set, the message transfer from and to the CAN
bus is stopped, and the status of the CAN_TX output is recessive (high). The CAN error counters are not
updated. Setting the Init bit does not change any other configuration register.
To initialize the CAN Controller, the CPU has to configure the CAN Bit timing and those message objects
which have to be used for CAN communication. Message objects which are not needed, can be
deactivated with their MsgVal bits cleared.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2355

Operating Modes

www.ti.com

The access to the Bit Timing register for the configuration of the bit timing is enabled when both Init and
CCE bits in the CAN Control register are set.
Clearing the Init bit finishes the software initialization. Afterwards the bit stream processor (BSP),
synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11
consecutive recessive bits (= Bus Idle) before it can take part in bus activities and start the message
transfer.
The initialization of the message objects is independent of the Init bit, however all message objects should
be configured to particular identifiers or set to "not valid" before the message transfer is started.
It is possible to change the configuration of message objects during normal operation by the CPU. After
setup and subsequent transfer of message object from interface registers to message RAM, the
acceptance filtering will be applied to it, when the modified message object number is same or smaller
than the previously found message object. This assures data consistency even when changing message
objects, for example, while there is a pending CAN frame reception.

22.4.2 CAN Message Transfer (Normal Operation)
Once the CAN is initialized and the Init bit is reset to zero, the CAN Core synchronizes itself to the CAN
bus and is ready for communication.
Received messages are stored into their appropriate message objects if they pass acceptance filtering.
The whole message (MSGID, DLC, and up to eight data bytes) is stored into the message object. As a
consequence, when, for example, the identifier mask is used, the MSGID bits which are masked to "don't
care" may change in the message object when a received message is stored.
The CPU may read or write each message at any time via the Interface registers, as the message handler
guarantees data consistency in case of concurrent accesses.
Messages to be transmitted can be updated by the CPU. If a permanent message object (MSGID and
control bits set up during configuration and leaving unchanged for multiple CAN transfers) exists for the
message, it is possible to only update the data bytes. If several transmit messages should be assigned to
one message object, the whole message object has to be configured before the transmission of this
message is requested.
The transmission of multiple message objects may be requested at the same time. They are subsequently
transmitted, according to their internal priority. Messages may be updated or set to "not valid" at any time,
even if a requested transmission is still pending. However, the data bytes will be discarded if a message is
updated before a pending transmission has started.
Depending on the configuration of the message object, a transmission may be automatically requested by
the reception of a remote frame with a matching identifier.
22.4.2.1 Disabled Automatic Retransmission
According to the CAN Specification (see ISO11898, 6.3.3 Recovery Management), the CAN provides a
mechanism to automatically retransmit frames which have lost arbitration or have been disturbed by errors
during transmission. The frame transmission service will not be confirmed to the user before the
transmission is successfully completed.
By default, this automatic retransmission is enabled. It can be disabled by setting bit DAR in the CAN
Control register. Further details to this mode are provided in Section 22.11.3.
22.4.2.2 Auto-Bus-On
By default, after the CAN has entered bus-off state, the CPU can start a bus-off-recovery sequence by
resetting Init bit. If this is not done, the module will stay in bus-off state.
The CAN provides an automatic auto-bus-on feature which is enabled by the ABO bit. If set, the CAN will
automatically start the bus-off-recovery sequence. The sequence can be delayed by a user-defined
number of clock cycles.

2356

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Operating Modes

www.ti.com

NOTE: If the CAN module goes Bus-Off due to massive occurrence of CAN bus errors, it stops all
bus activities and automatically sets the Init bit. Once the Init bit is cleared by the application
(or due to the auto-bus-on feature), the device will wait for 128 occurrences of Bus Idle
(equal to 128 * 11 consecutive recessive bits) before resuming normal operation. The BusOff recovery sequence cannot be shortened by setting or resetting Init bit. At the end of the
bus-off recovery sequence, the error counters will be reset. After the Init bit is reset, each
time when a sequence of 11 recessive bits is monitored, a Bit0 Error code is written to the
Error and Status Register, enabling the CPU to check whether the CAN bus is stuck at
dominant or continuously disturbed, and to monitor the proceeding of the Bus-Off recovery
sequence.

22.4.3 Test Modes
The CAN provides several test modes which are mainly intended for self-test purposes.
For all test modes, the Test bit in the CAN Control register needs to be set to 1. This enables write access
to the Test register.
22.4.3.1 Silent Mode
The silent mode may be used to analyze the traffic on the CAN bus without affecting it by sending
dominant bits (for example, acknowledge bit, overload flag, active error flag). The CAN is still able to
receive valid data frames and valid remote frames, but it will not send any dominant bits. However, the
received frames are internally routed to the CAN core.
Figure 22-2 shows the connection of signals CAN_TX and CAN_RX to the CAN core in silent mode. Silent
mode can be activated by setting the Silent bit in test register (CAN_TEST) to 1. In ISO 11898-1, the silent
mode is called the bus monitoring mode.
Figure 22-2. CAN Core in Silent Mode

CAN_TX CAN_RX

DCAN

=1
•
Tx

•
Rx

CAN Core

22.4.3.2 Loopback Mode
The loopback mode is mainly intended for hardware self-test functions. In this mode, the CAN core uses
internal feedback from Tx output to Rx input. Transmitted messages are treated as received messages,
and can be stored into message objects if they pass acceptance filtering. The actual value of the CAN_RX
input pin is disregarded by the CAN core. Transmitted messages still can be monitored at the CAN_TX
pin.
In order to be independent from external stimulation, the CAN core ignores acknowledge errors (recessive
bit sampled in the acknowledge slot of a data/remote frame) in loopback mode.
Figure 22-3 shows the connection of signals CAN_TX and CAN_RX to the CAN core in loopback mode.
Loopback mode can be activated by setting bit LBack in the CAN_TEST register to one.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2357

Operating Modes

www.ti.com

NOTE: In loopback mode, the signal path from CAN core to Tx pin, the Tx pin itself, and the signal
path from Tx pin back to CAN Core are disregarded. For including these into the testing, see
Section 22.4.3.3.

Figure 22-3. CAN Core in Loopback Mode

CAN_TX CAN_RX

DCAN

•
Tx

•
Rx

CAN Core

22.4.3.3 External Loopback Mode
The external loopback mode is similar to the loopback mode; however, it includes the signal path from
CAN Core to Tx pin, the Tx pin itself, and the signal path from Tx pin back to the CAN Core. When the
external loopback mode is selected, the CAN core is connected to the input buffer of the Tx pin. With this
configuration, the Tx pin IO circuit can be tested. External loopback mode can be activated by setting bit
ExL in Test Register to one.
Figure 22-4 shows the connection of signals CAN_TX and CAN_RX to the CAN Core in external loopback
mode.
NOTE: When loopback mode is active (LBack bit set), the ExL bit will be ignored.

2358

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Operating Modes

www.ti.com

Figure 22-4. CAN Core in External Loopback Mode

CAN_RX
pin

CAN_TX
pin

DCAN

Rx

Tx

CAN Core

22.4.3.4 Loopback Combined with Silent Mode
It is also possible to combine loopback mode and silent mode by setting bits LBack and Silent at the same
time. This mode can be used for a "Hot Selftest;" that is, the CAN hardware can be tested without
affecting the CAN network. In this mode, the CAN_RX pin is disconnected from the CAN Core and no
dominant bits will be sent on the CAN_TX pin.
Figure 22-5 shows the connection of the signals CAN_TX and CAN_RX to the CAN Core in case of the
combination of loopback mode with silent mode.
Figure 22-5. CAN Core in Loopback Combined with Silent Mode

CAN_TX CAN_RX

DCAN
=1
•
Tx

•
Rx

CAN Core

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2359

Multiple Clock Source

www.ti.com

22.5 Multiple Clock Source
Three clock domains are provided to the CAN module for generating the CAN bit timing: the external
oscillator clock (X1/X2), the system clock, and the GPIO AUXCLKIN.
The system module reference guide and the device data manual provide for more information on how to
configure the relevant clock source registers in the system module.
NOTE: The CAN core has to be programmed to at least eight clock cycles per bit time. To achieve a
transfer rate of 1 Mbps an oscillator frequency of 8 MHz or higher has to be used.

22.6 Interrupt Functionality
Interrupts can be generated on two interrupt lines: CAN0INT and CAN1INT. These lines can be enabled
by setting the IE0 and IE1 bits, respectively, in the CAN Control register.
The CAN provides three groups of interrupt sources: message object interrupts, status change interrupts
and error interrupts. The source of an interrupt can be determined by the interrupt identifiers INT0ID or
INT1ID in the CAN_INT Interrupt register. When no interrupt is pending, the register will hold the value
zero. Each interrupt line remains active until the dedicated field in the Interrupt register (INT0ID or INT1ID)
again reaches zero (this means the cause of the interrupt is reset), or until IE0 or IE1 are reset. The value
0x8000 in the INT0ID field indicates that an interrupt is pending because the CAN Core has updated (not
necessarily changed) the Error and Status register (Error Interrupt or Status Interrupt). This interrupt has
the highest priority. The CPU can update (reset) the status bits RxOk, TxOk and LEC by reading the Error
and Status Register, but a write access of the CPU will never generate or reset an interrupt.
Values between 1 and the number of the last message object indicates that the source of the interrupt is
one of the message objects, INT0ID or INT1ID will point to the pending message interrupt with the highest
priority. The Message Object 1 has the highest priority, the last message object has the lowest priority.
An interrupt service routine which reads the message that is the source of the interrupt, may read the
message and reset the message object's IntPnd at the same time (ClrIntPnd bit in the IF1 or IF2
Command register). When IntPnd is cleared, the Interrupt register will point to the next message object
with a pending interrupt.
The CAN module features a module-level interrupt enable and acknowledge mechanism. To enable the
CAN0 and CAN1 interrupts, set the appropriate bits in the CAN_GLB_INT_EN register. When handling an
interrupt, the individual message or status change flag must be cleared prior to acknowledging the
interrupt via CAN_GLB_INT_CLR and PIEACK.

22.6.1 Message Object Interrupts
Message object interrupts are generated by events from the message objects. They are controlled by the
flags IntPND, TxIE and RxIE which are described in Section 22.14.1. Message object interrupts can be
routed to either CAN0INT or CAN1INT line, controlled by the Interrupt Multiplexer register.

22.6.2 Status Change Interrupts
The events RxOk, TxOk and LEC in Error and Status register belong to the status change interrupts. The
status change interrupt group can be enabled by bit SIE in the CAN Control register. If SIE is set, a status
change interrupt will be generated at each CAN frame, independent of bus errors or valid CAN
communication, and also independent of the Message RAM configuration. Status Change interrupts can
only be routed to interrupt line CAN0INT which has to be enabled by setting IE0 in the CAN
ControlRegister.

22.6.3 Error Interrupts
The events PER, BOff and EWarn, belong to the error interrupts. The error interrupt group can be enabled
by setting bit EIE. Also, error interrupts can only be routed to interrupt line CAN0INT which has to be
enabled by setting IE0 in the CAN_CTL register.

2360

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Interrupt Functionality

www.ti.com

22.6.4 PIE Nomenclature for DCAN Interrupts
Table 22-3 shows the PIE nomenclature for the interrupts.
Table 22-3. PIE Nomenclature for Interrupts
Interrupt

CANA

CANB

CANINT0

CANA_0

CANB_0

CANINT1

CANA_1

CANB_1

22.7 Parity Check Mechanism
The CAN provides a parity check mechanism to ensure data integrity of message RAM data. For each
word (32 bits) in Message RAM, one parity bit will be calculated.
Parity information is stored in the Message RAM on write accesses and will be checked against the stored
parity bit from Message RAM on read accesses.
The parity check functionality can be enabled or disabled by PMD bit field in CAN Control register. In case
of disabled parity check, the parity bits in message RAM will be left unchanged on write access to data
area and no check will be done on read access.
If parity checking is enabled, parity bits will be automatically generated and checked by the CAN. A parity
bit will be set, if the modulo-2-sum of the data bits is 1. This definition is equivalent to: the parity bit will be
set, if the number of 1 bits in the data is odd.

22.7.1 Behavior on Parity Error
On any read access to Message RAM, for example, during the start of a CAN frame transmission, the
parity of the message object will be checked. If a parity error is detected, the PER bit in Error and Status
register will be set. If error interrupts are enabled, an interrupt would also be generated. In order to avoid
the transmission of invalid data over the CAN bus, the MsgVal bit of the message object will be reset.
The message object data can be read by the CPU, independently of parity errors. Thus, the application
has to ensure that the read data is valid, for example, by immediately checking the Parity Error Code
register on parity error interrupt.

22.8 Debug Mode
The module supports the usage of an external debug unit by providing functions like pausing CAN
activities and making message RAM content accessible from the debugger. Debug mode is entered
automatically when an external debugger is connected and the core is halted.
Before entering Debug mode, the circuit will either wait until a started transmission or reception will be
finished and Bus idle state is recognized, or immediately interrupt a current transmission or reception. This
is depending on bit IDS. Afterwards, the CAN enters Debug mode, indicated by the InitDbg flag, in the
CAN Control register. During debug mode, all CAN registers can be accessed. Reading reserved bits will
return '0'. Writing to reserved bits will have no effect. Also, the message RAM will be memory mapped.
This allows the external debug unit to read the message RAM. For the memory organization, see
Section 22.14.3).
NOTE: During debug mode, the Message RAM cannot be accessed via the IFx register sets.

NOTE: Writing to control registers in Debug mode may influence the CAN state machine and further
message handling.

For debug support, the auto clear functionality of the following CAN registers is disabled:
• Error and Status register (clear of status flags by read)
• IF1 and IF2 Command registers
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2361

Module Initialization

www.ti.com

22.9 Module Initialization
After hardware reset, the Init bit in the CAN Control register is set and all CAN protocol functions are
disabled. The configuration of the bit timing and of the message objects should be completed before the
CAN protocol functions are enabled.
For the configuration of the message objects, see Section 22.10.
For the configuration of the Bit Timing, see Section 22.12.2.
The bits MsgVal, NewDat, IntPnd, and TxRqst of the message objects are reset to '0' by a hardware reset.
The configuration of a message object is done by programming Mask, Arbitration, Control and Data bits of
one of the IF1 or IF2 Interface register sets to the desired values. By writing the message object number
to bits [7:0] of the corresponding IF1 or IF2 Command register, the IF1 or IF2 Interface Register content is
loaded into the addressed message object in Message RAM.
The configuration of the bit timing requires that the CCE bit in the CAN Control register is set additionally
to Init. This is not required for the configuration of the message objects.
When the Init bit in the CAN Control register is cleared, the CAN Protocol Controller state machine of the
CAN Core and the message handler State Machine start to control the CAN's internal data flow. Received
messages which pass the acceptance filtering are stored into the Message RAM; messages with pending
transmission request are loaded into the CAN Core's Shift register and are transmitted via the CAN bus.
The CPU may enable the interrupt lines (setting IE0 and IE1 to '1') at the same time when it clears Init and
CCE. The status interrupts EIE and SIE may be enabled simultaneously.
The CAN communication may be controlled in interrupt-driven or in polling mode. The Interrupt Register
points to those message objects with IntPnd = '1'. It is updated even if the interrupt lines to the CPU are
disabled (IE0 or IE1 are zero).
The CPU may poll all MessageObject's NewDat and TxRqst bits in parallel from the NewData registers
and the Transmission Request registers. Polling can be made easier if all Transmit Objects are grouped at
the low numbers, all Receive Objects are grouped at the high numbers.

22.10 Configuration of Message Objects
The entire Message RAM should to be configured before the end of the initialization; however, it is also
possible to change the configuration of message objects during CAN communication.

22.10.1 Configuration of a Transmit Object for Data Frames
Figure 22-6 shows how a transmit object can be initialized.
Figure 22-6. Initialization of a Transmit Object
MsgVal
1

•

•
•
•
•

2362

Arb
appl.

Data
appl.

Mask
appl.

EoB
1

Dir
1

NewDat
0

MsgLst
0

RxIE
0

TxIE
appl.

IntPnd
0

RmtEn
appl.

TxRqst
0

The arbitration bits (ID[28:0] and Xtd bit) are given by the application. They define the identifier and
type of the outgoing message. If an 11-bit Identifier (standard frame) is used (Xtd = '0'), it is
programmed to ID[28:18]. In this case, ID[17:0] can be ignored.
The data registers (DLC[3:0] and Data0-7) are given by the application, TxRqst and RmtEn should not
be set before the data is valid.
If the TxIE bit is set, the IntPnd bit will be set after a successful transmission of the message object.
If the RmtEn bit is set, a matching received remote frame will cause the TxRqst bit to be set; the
remote frame will autonomously be answered by a data frame.
The Mask bits (Msk[28:0], UMask, MXtd, and MDir bits) may be used (UMask='1') to allow groups of
remote frames with similar identifiers to set the TxRqst bit. The Dir bit should not be masked. For
details see Section 22.11.8. Identifier masking must be disabled (UMask = '0') if no remote frames are
allowed to set the TxRqst bit (RmtEn = '0').

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Configuration of Message Objects

www.ti.com

22.10.2 Configuration of a Transmit Object for Remote Frames
It is not necessary to configure transmit objects for the transmission of remote frames. Setting TxRqst for
a receive object will cause the transmission of a remote frame with the same identifier as the data frame
for which this receive object is configured.

22.10.3 Configuration of a Single Receive Object for Data Frames
Figure 22-7 shows how a receive object for data frames can be initialized.
Figure 22-7. Initialization of a single Receive Object for Data Frames
MsgVal
1

•

•

•

•
•

Arb
appl.

Data
appl.

Mask
appl.

EoB
1

Dir
0

NewDat
0

MsgLst
0

RxIE
appl.

TxIE
0

IntPnd
0

RmtEn
0

TxRqst
0

The arbitration bits (ID[28:0] and Xtd bit) are given by the application. They define the identifier and
type of accepted received messages. If an 11-bit Identifier (Standard Frame) is used (Xtd = '0'), it is
programmed to ID[28:18]. In this case, ID[17:0] can be ignored. When a data frame with an 11-bit
Identifier is received, ID[17:0] will be set to '0'.
The data length code (DLC[3:0]) is given by the application. When the message handler stores a data
frame in the message object, it will store the received data length code and eight data bytes. If the data
length code is less than 8, the remaining bytes of the message object may be overwritten by non
specified values.
The mask bits (Msk[28:0], UMask, MXtd, and MDir bits) may be used (UMask = '1') to allow groups of
data frames with similar identifiers to be accepted. The Dir bit should not be masked in typical
applications. If some bits of the Mask bits are set to "don't care", the corresponding bits of the
Arbitration Register will be overwritten by the bits of the stored data frame.
If the RxIE bit is set, the IntPnd bit will be set when a received data frame is accepted and stored in the
message object.
If the TxRqst bit is set, the transmission of a remote frame with the same identifier as actually stored in
the Arbitration bits will be triggered. The content of the Arbitration bits may change if the Mask bits are
used (UMask = '1') for acceptance filtering.

22.10.4 Configuration of a Single Receive Object for Remote Frames
Figure 22-8 shows how a receive object for remote frames can be initialized.
Figure 22-8. Initialization of a single Receive Object for Remote Frames
MsgVal
1

•

•

•

•

•

Arb
appl.

Data
appl.

Mask
appl.

EoB
1

Dir
1

NewDat
0

MsgLst
0

RxIE
appl.

TxIE
0

IntPnd
0

RmtEn
0

TxRqst
0

Receive objects for remote frames may be used to monitor remote frames on the CAN bus. The
remote frame stored in the receive object will not trigger the transmission of a data frame. Receive
objects for remote frames may be expanded to a FIFO buffer, see Section 22.10.5.
UMask must be set to '1'. The Mask bits (Msk[28:0], UMask, MXtd, and MDir bits) may be set to "mustmatch" or to "don't care", to allow groups of remote frames with similar identifiers to be accepted. The
Dir bit should not be masked in typical applications. For details see Section 22.11.8.
The arbitration bits (ID[28:0] and Xtd bit) may be given by the application. They define the identifier and
type of accepted received remote frames. If some bits of the Mask bits are set to "don't care", the
corresponding bits of the arbitration bits will be overwritten by the bits of the stored remote frame. If an
11-bit Identifier (standard frame) is used (Xtd = '0'), it is programmed to ID[28:18]. In this case, ID[17:0]
can be ignored. When a remote frame with an 11-bit Identifier is received, ID[17:0] will be set to '0'.
The data length code (DLC[3:0]) may be given by the application. When the message handler stores a
remote frame in the message object, it will store the received data length code. The data bytes of the
message object will remain unchanged.
If the RxIE bit is set, the IntPnd bit will be set when a received remote frame is accepted and stored in
the message object.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2363

Configuration of Message Objects

www.ti.com

22.10.5 Configuration of a FIFO Buffer
With the exception of the EoB bit, the configuration of receive objects belonging to a FIFO buffer is the
same as the configuration of a single receive object.
To concatenate multiple message objects to a FIFO buffer, the identifiers and masks (if used) of these
message objects have to be programmed to matching values. Due to the implicit priority of the message
objects, the message object with the lowest number will be the first message object of the FIFO buffer.
The EoB bit of all message objects of a FIFO buffer except the last one have to be programmed to zero.
The EoB bits of the last message object of a FIFO buffer is set to one, configuring it as the end of the
block.

22.11 Message Handling
When initialization is finished, the CAN module synchronizes itself to the traffic on the CAN bus. It does
acceptance filtering on received messages and stores those frames that are accepted into the designated
message objects. The application has to update the data of the messages to be transmitted and to enable
and request their transmission. The transmission is requested automatically when a matching remote
frame is received.
The application may read messages which are received and accepted. Messages that are not read before
the next messages is accepted for the same message object will be overwritten. Messages may be read
interrupt-driven or after polling of NewDat.

22.11.1 Message Handler Overview
The message handler state machine controls the data transfer between the Rx/Tx Shift Register of the
CAN Core and the Message RAM. It performs the following tasks:
• Data transfer from Message RAM to CAN Core (messages to be transmitted).
• Data transfer from CAN Core to the Message RAM (received messages).
• Data transfer from CAN Core to the Acceptance Filtering unit.
• Scanning of Message RAM for a matching message object (acceptance filtering).
• Scanning the same message object after being changed by IF1 or IF2 registers when priority is same
or higher as message the object found by last scanning.
• Handling of TxRqst flags.
• Handling of interrupt flags.
The message handler registers contains status flags of all message objects grouped into the following
topics:
• Transmission request flags
• New data flags
• Interrupt pending flags
• Message valid registers
Instead of collecting above listed status information of each message object via IFx registers separately,
these message handler registers provide a fast and easy way to get an overview, for example, about all
pending transmission requests.
All message handler registers are read-only.

22.11.2 Receive/Transmit Priority
The receive/transmit priority for the message objects is attached to the message number, not to the CAN
identifier. Message object 1 has the highest priority, while message object 32 has the lowest priority. If
more than one transmission request is pending, they are serviced due to the priority of the corresponding
message object, so for example, messages with the highest priority can be placed in the message objects
with the lowest numbers.

2364

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Message Handling

www.ti.com

The acceptance filtering for received data frames or remote frames is also done in ascending order of
message objects, so a frame that has been accepted by a message object cannot be accepted by another
message object with a higher message number. The last message object may be configured to accept
any data frame or remote frame that was not accepted by any other message object, for nodes that need
to log the complete message traffic on the CAN bus.

22.11.3 Transmission of Messages in Event Driven CAN Communication
If the shift register of the CAN Core is ready for loading and if there is no data transfer between the IFx
registers and Message RAM, the MsgVal bits in the Message Valid register and the TxRqst bits in the
transmission request register are evaluated. The valid message object with the highest priority pending
transmission request is loaded into the shift register by the message handler and the transmission is
started. The message object's NewDat bit is reset.
After a successful transmission and if no new data was written to the message object (NewDat = '0') since
the start of the transmission, the TxRqst bit will be reset. If TxIE is set, IntPnd will be set after a successful
transmission. If the CAN has lost the arbitration or if an error occurred during the transmission, the
message will be retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of a
message with higher priority has been requested, the messages will be transmitted in the order of their
priority.
If automatic retransmission mode is disabled by setting the DAR bit in the CAN Control register, the
behavior of bits TxRqst and NewDat in the Message Control register of the Interface register set is as
follows:
• When a transmission starts, the TxRqst bit of the respective Interface register set is reset, while bit
NewDat remains set.
• When the transmission has been successfully completed, the NewDat bit is reset.
When a transmission failed (lost arbitration or error) bit NewDat remains set. To restart the transmission,
the application has to set TxRqst again.
Received remote frames do not require a receive object. They will automatically trigger the transmission of
a data frame, if in the matching Transmit Object the RmtEn bit is set.

22.11.4 Updating a Transmit Object
The CPU may update the data bytes of a transmit object any time via the IF1 or IF2 interface registers,
neither MsgVal nor TxRqst have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes in the corresponding IF1 or IF2 Data
A register or the IF1 or /IF2 Data B register have to be valid before the content of that register is
transferred to the message object. Either the CPU has to write all four bytes into the IF1 or IF2 Data
register, or the message object is transferred to the IF1 or IF2 Data register before the CPU writes the
new data bytes.
When only the data bytes are updated, first 0x87 can be written to bits [23:16] of the Command register
and then the number of the message object is written to bits [7:0] of the Command register, concurrently
updating the data bytes and setting TxRqst with NewDat.
To prevent the reset of TxRqst at the end of a transmission that may already be in progress while the data
is updated, NewDat has to be set together with TxRqst in event driven CAN communication. For details
see Section 22.11.3.
When NewDat is set together with TxRqst, NewDat will be reset as soon as the new transmission has
started.

22.11.5 Changing a Transmit Object
If the number of implemented message objects is not sufficient to be used as permanent message objects
only, the transmit objects may be managed dynamically. The CPU can write the whole message
(Arbitration,

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2365

Message Handling

www.ti.com

Control, and Data) into the Interface register. The bits [23:16] of the Command register can be set to 0xB7
for the transfer of the whole message object content into the message object. Neither MsgVal nor TxRqst
have to be reset before this operation.
If a previously requested transmission of this message object is not completed but already in progress, it
will be continued; however it will not be repeated if it is disturbed.
To only update the data bytes of a message to be transmitted, bits [23:16] of the Command register
should be set to 0x87.
NOTE: After the update of the transmit object, the interface register set will contain a copy of the
actual contents of the object, including the part that had not been updated.

22.11.6 Acceptance Filtering of Received Messages
When the arbitration and control bits (Identifier + IDE + RTR + DLC) of an incoming message is
completely shifted into the shift register of the CAN Core, the message handler starts to scan of the
message RAM for a matching valid message object:
• The acceptance filtering unit is loaded with the arbitration bits from the CAN Core shift register.
• Then the arbitration and mask bits (including MsgVal, UMask, NewDat, and EoB) of Message Object 1
are loaded into the Acceptance Filtering unit and are compared with the arbitration bits from the shift
register. This is repeated for all following message objects until a matching message object is found, or
until the end of the Message RAM is reached.
• If a match occurs, the scanning is stopped and the message handler proceeds depending on the type
of the frame (data frame or remote frame) received.

22.11.7 Reception of Data Frames
The message handler stores the message from the CAN Core shift register into the respective message
object in the Message RAM. Not only the data bytes, but all arbitration bits and the data length code are
stored into the corresponding message object. This ensures that the data bytes stay associated to the
identifier even if arbitration mask registers are used.
The NewDat bit is set to indicate that new data (not yet seen by the CPU) has been received. The CPU
should reset the NewDat bit when it reads the message object. If at the time of the reception the NewDat
bit was already set, MsgLst is set to indicate that the previous data (supposedly not seen by the CPU) is
lost. If the RxIE bit is set, the IntPnd bit is set, causing the Interrupt Register to point to this message
object.
The TxRqst bit of this message object is reset to prevent the transmission of a remote frame, while the
requested data frame has just been received.

22.11.8 Reception of Remote Frames
When a remote frame is received, three different configurations of the matching message object have to
be considered:
1. Dir = '1' (direction = transmit), RmtEn = '1', UMask = '1' or '0'
The TxRqst bit of this message object is set at the reception of a matching remote frame. The rest of
the message object remains unchanged.
2. Dir = '1' (direction = transmit), RmtEn = '0', UMask = '0'
The remote frame is ignored, this message object remains unchanged.
3. Dir = '1' (direction = transmit), RmtEn = '0', UMask = '1'
The remote frame is treated similar to a received data frame. At the reception of a matching remote
frame, the TxRqst bit of this message object is reset. The arbitration and control bits (Identifier + IDE +
RTR + DLC) from the shift register are stored in the message object in the Message RAM and the
NewDat bit of this message object is set. The data bytes of the message object remain unchanged

2366

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Message Handling

www.ti.com

22.11.9 Reading Received Messages
The CPU may read a received message any time via the IFx interface registers, the data consistency is
guaranteed by the message handler state machine.
Typically the CPU will write 0x7F to bits [23:16] and then the number of the message object to bits [7:0] of
the Command Register. That combination will transfer the whole received message from the Message
RAM into the Interface Register set. Additionally, the bits NewDat and IntPnd are cleared in the Message
RAM (not in the Interface Register set). The values of these bits in the Message Control Register always
reflect the status before resetting the bits.
If the message object uses masks for acceptance filtering, the arbitration bits show which of the different
matching messages has been received.
The actual value of NewDat shows whether a new message has been received since last time when this
message object was read. The actual value of MsgLst shows whether more than one message have been
received since the last time when this message object was read. MsgLst will not be automatically reset.

22.11.10 Requesting New Data for a Receive Object
By means of a remote frame, the CPU may request another CAN node to provide new data for a receive
object. Setting the TxRqst bit of a receive object will cause the transmission of a remote frame with the
receive object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be transmitted,
the TxRqst bit is automatically reset.
Setting the TxRqst bit without changing the contents of a message object requires the value 0x84 in bits
[23:16] of the Command Register.

22.11.11 Storing Received Messages in FIFO Buffers
Several message objects may be grouped to form one or more FIFO Buffers. Each FIFO Buffer configured
to store received messages with a particular (group of) Identifier(s). Arbitration and Mask registers of the
FIFO Buffer's message objects are identical. The EoB (End of Buffer) bits of all but the last of the FIFO
Buffer's message objects are '0', in the last one the EoB bit is '1'.
Received messages with identifiers matching to a FIFO Buffer are stored into a message object of this
FIFO Buffer, starting with the message object with the lowest message number.
When a message is stored into a message object of a FIFO Buffer the NewDat bit of this message object
is set. By setting NewDat while EoB is '0' the message object is locked for further write accesses by the
message handler until the CPU has cleared the NewDat bit.
Messages are stored into a FIFO Buffer until the last message object of this FIFO Buffer is reached. If
none of the preceding message objects is released by writing NewDat to '0', all further messages for this
FIFO Buffer will be written into the last message object of the FIFO Buffer (EoB = '1') and therefore
overwrite previous messages in this message object.

22.11.12 Reading from a FIFO Buffer
Several messages may be accumulated in a set of message objects which are concatenated to form a
FIFO Buffer before the application program is required (in order to avoid the loss of data) to empty the
buffer. A FIFO Buffer of length N will store N-1 plus the last received message since last time it was
cleared. A FIFO Buffer is cleared by reading and resetting the NewDat bits of all its message objects,
starting at the FIFO Object with the lowest message number. This should be done in a subroutine
following the example shown in Figure 22-9.
NOTE: All message objects of a FIFO buffer needs to be read and cleared before the next batch of
messages can be stored. Otherwise true FIFO functionality can not be guaranteed, since the
message objects of a partly read buffer will be re-filled according to the normal (descending)
priority.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2367

CAN Bit Timing

www.ti.com

Reading from a FIFO Buffer message object and resetting its NewDat bit is handled the same way as
reading from a single message object.
Figure 22-9. CPU Handling of a FIFO Buffer (Interrupt Driven)
START

Message interrupt

Read interrupt identifier

case interrupt identifier
else
0x0000

0x800
Status Change
Interrupt Handling

END

IFx command register [31:16] = 0x007F
Message Number = interrupt identifier

Write Message Number to IF1/IF2 command register
(Transfer message to IF1/IF2 registers,
clear NewDat and IntPnd)

Read IF1/IF2 message control

No

NewDat = 1
Yes
Read data from IF1/IF2 Data A,B

EoB = 1

Yes

No
Next Message Number in this FIFO Buffer

22.12 CAN Bit Timing
The CAN supports bit rates between less than 1 kBit/s and 1000 kBit/s.
Each member of the CAN network has its own clock generator, typically derived from a crystal oscillator.
The Bit timing parameters can be configured individually for each CAN node, creating a common Bit rate
even though the CAN nodes' oscillator periods (fosc) may be different.

2368

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CAN Bit Timing

www.ti.com

The frequencies of these oscillators are not absolutely stable. Small variations are caused by changes in
temperature or voltage and by deteriorating components. As long as the variations remain inside a specific
oscillator tolerance range (df), the CAN nodes are able to compensate for the different bit rates by
resynchronizing to the bit stream.
In many cases, the CAN bit synchronization will amend a faulty configuration of the CAN bit timing to such
a degree that only occasionally an error frame is generated. In the case of arbitration however, when two
or more CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of
the transmitters to become error passive.
The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside
a CAN node and of the CAN nodes' interaction on the CAN bus.
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly.

22.12.1 Bit Time and Bit Rate
According to the CAN specification, the Bit time is divided into four segments (see Figure 22-10):
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
Figure 22-10. Bit Timing
Nominal CAN bit time

Sync_
Seg

Prop_Seg

Phase_Seg1

Phase_Seg2

1 time quantum
(t )
q

Sample point

Each segment consists of a specific number of time quanta. The length of one time quantum (tq), which is
the basic time unit of the bit time, is given by the CAN_CLK and the Baud Rate Prescalers (BRPE and
BRP). With these two Baud Rate Prescalers combined, divider values from 1 to 1024 can be programmed:
tq = Baud Rate Prescaler / CAN_CLK
Apart from the fixed length of the synchronization segment, these numbers are programmable. Table 22-4
describes the minimum programmable ranges required by the CAN protocol.
A given bit rate may be met by different bit time configurations.
Table 22-4. Programmable Ranges Required by CAN Protocol
Parameter

Range

Remark

Sync_Seg

1 tq (fixed)

Synchronization of bus input to CAN_CLK

Prop_Seg

[1 … 8] tq

Compensates for the physical delay times

Phase_Seg1

[1 … 8] tq

May be lengthened temporarily by synchronization

Phase_Seg2

[1 … 8] tq

May be shortened temporarily by synchronization

Synchronization Jump Width (SJW)

[1 … 4] tq

May not be longer than either Phase Buffer Segment

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2369

CAN Bit Timing

www.ti.com

NOTE: For proper functionality of the CAN network, the physical delay times and the oscillator's
tolerance range have to be considered.

22.12.1.1 Synchronization Segment
The Synchronization Segment (Sync_Seg) is the part of the bit time where edges of the CAN bus level are
expected to occur. If an edge occurs outside of Sync_Seg, its distance to the Sync_Seg is called the
phase error of this edge.
22.12.1.2 Propagation Time Segment
This part of the bit time is used to compensate physical delay times within the CAN network. These delay
times consist of the signal propagation time on the bus and the internal delay time of the CAN nodes.
Any CAN node synchronized to the bit stream on the CAN bus can be out of phase with the transmitter of
the bit stream, caused by the signal propagation time between the two nodes. The CAN protocol's
nondestructive bitwise arbitration and the dominant acknowledge bit provided by receivers of CAN
messages require that a CAN node transmitting a bit stream must also be able to receive dominant bits
transmitted by other CAN nodes that are synchronized to that bit stream. The example in Figure 22-11
shows the phase shift and propagation times between two CAN nodes.
Figure 22-11. The Propagation Time Segment
Sync_Seg

Prop_seg

Phase_seg1

Phase_seg2

Node B

Delay A_to_B

B_to_A

Delay

Node A

Delay A_to_B >= node output delay(A) + bus line delay(AÆB) + node input delay(B)
Prop_Seg >= Delay A_to_B + Delay B_to_A
Prop_Seg >= 2 • [max(node output delay+ bus line delay + node input delay)]

In this example, both nodes A and B are transmitters performing an arbitration for the CAN bus. The node
A has sent its Start of Frame bit less than one bit time earlier than node B, therefore node B has
synchronized itself to the received edge from recessive to dominant. Since node B has received this edge
delay(A_to_B) after it has been transmitted, node B's bit timing segments are shifted with regard to node
A. Node B sends an identifier with higher priority and so it will win the arbitration at a specific identifier bit
when it transmits a dominant bit while node A transmits a recessive bit. The dominant bit transmitted by
node B will arrive at node A after the delay(B_to_A).
Due to oscillator tolerances, the actual position of node A's Sample Point can be anywhere inside the
nominal range of node A's Phase Buffer Segments, so the bit transmitted by node B must arrive at node A
before the start of Phase_Seg1. This condition defines the length of Prop_Seg.
If the edge from recessive to dominant transmitted by node B would arrive at node A after the start of
Phase_Seg1, it could happen that node A samples a recessive bit instead of a dominant bit, resulting in a
bit error and the destruction of the current frame by an error flag.

2370

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CAN Bit Timing

www.ti.com

This error only occurs when two nodes arbitrate for the CAN bus which have oscillators of opposite ends
of the tolerance range and are separated by a long bus line; this is an example of a minor error in the Bit
timing configuration (Prop_Seg too short) that causes sporadic bus errors.
Some CAN implementations provide an optional 3 Sample Mode. The CAN does not. In this mode, the
CAN bus input signal passes a digital low-pass filter, using three samples and a majority logic to
determine the valid bit value. This results in an additional input delay of 1 tq, requiring a longer Prop_Seg.
22.12.1.3 Phase Buffer Segments and Synchronization
The phase buffer segments (Phase_Seg1 and Phase_Seg2) and the synchronization jump width (SJW)
are used to compensate for the oscillator tolerance.
The phase buffer segments surround the sample point. The phase buffer segments may be lengthened or
shortened by synchronization.
The synchronization jump width (SJW) defines how far the resynchronizing mechanism may move the
sample point inside the limits defined by the phase buffer segments to compensate for edge phase errors.
Synchronizations occur on edges from recessive to dominant. Their purpose is to control the distance
between edges and sample points.
Edges are detected by sampling the actual bus level in each time quantum and comparing it with the bus
level at the previous sample point. A synchronization may be done only if a recessive bit was sampled at
the previous sample point and if the actual time quantum's bus level is dominant.
An edge is synchronous if it occurs inside of Sync_Seg, otherwise its distance to the Sync_Seg is the
edge phase error, measured in time quanta. If the edge occurs before Sync_Seg, the phase error is
negative, else it is positive.
Two types of synchronization exist: hard synchronization and resynchronizing. A hard synchronization is
done once at the start of a frame; inside a frame only resynchronization is possible.
• Hard Synchronization
After a hard synchronization, the bit time is restarted with the end of Sync_Seg, regardless of the edge
phase error. Thus hard synchronization forces the edge which has caused the hard synchronization to
lie within the synchronization segment of the restarted bit time.
• Bit Resynchronizations
Resynchronization leads to a shortening or lengthening of the bit time such that the position of the
sample point is shifted with regard to the edge.
When the phase error of the edge which causes resynchronization is positive, Phase_Seg1 is
lengthened. If the magnitude of the phase error is less than SJW, Phase_Seg1 is lengthened by the
magnitude of the phase error, else it is lengthened by SJW.
When the phase error of the edge which causes Resynchronization is negative, Phase_Seg2 is
shortened. If the magnitude of the phase error is less than SJW, Phase_Seg2 is shortened by the
magnitude of the phase error, else it is shortened by SJW.
If the magnitude of the phase error of the edge is less than or equal to the programmed value of SJW, the
results of hard synchronization and resynchronization are the same. If the magnitude of the phase error is
larger than SJW, the resynchronization cannot compensate the phase error completely, and an error of
(phase error - SJW) remains.
Only one synchronization may be done between two sample points. The synchronizations maintain a
minimum distance between edges and sample points, giving the bus level time to stabilize and filtering out
spikes that are shorter than (Prop_Seg + Phase_Seg1).
Apart from noise spikes, most synchronizations are caused by arbitration. All nodes synchronize "hard" on
the edge transmitted by the "leading" transceiver that started transmitting first, but due to propagation
delay times, they cannot become ideally synchronized. The "leading" transmitter does not necessarily win
the arbitration, therefore the receivers have to synchronize themselves to different transmitters that
subsequently "take the lead" and that are differently synchronized to the previously "leading" transmitter.
The same happens at the acknowledge field, where the transmitter and some of the receivers will have to
synchronize to that receiver that "takes the lead" in the transmission of the dominant acknowledge bit.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2371

CAN Bit Timing

www.ti.com

Synchronizations after the end of the arbitration will be caused by oscillator tolerance, when the
differences in the oscillator's clock periods of transmitter and receivers sum up during the time between
synchronizations (at most ten bits). These summarized differences may not be longer than the SJW,
limiting the oscillator's tolerance range.
The examples in Figure 22-12 show how the phase buffer segments are used to compensate for phase
errors. There are three drawings of each two consecutive bit timings. The upper drawing shows the
synchronization on a "late" edge, the lower drawing shows the synchronization on an "early" edge, and the
middle drawing is the reference without synchronization.
Figure 22-12. Synchronization on Late and Early Edges
Recessive
dominant

“late” edge

Rx-input

Sample-point

Sample-point

“normal”
edge
Sample-point

Sample-point

Sample-point

Sample-point

Recessive
dominant

“early” edge

Rx-input
Sync_Seg

Prop_Seg

Phase_Seg1

Phase_Seg2

In the first example, an edge from recessive to dominant occurs at the end of Prop_Seg. The edge is
"late" since it occurs after the Sync_Seg. Reacting to the "late" edge, Phase_Seg1 is lengthened so that
the distance from the edge to the sample point is the same as it would have been from the Sync_Seg to
the sample point if no edge had occurred. The phase error of this "late" edge is less than SJW, so it is
fully compensated and the edge from dominant to recessive at the end of the bit, which is one nominal bit
time long, occurs in the Sync_Seg.
In the second example, an edge from recessive to dominant occurs during Phase_Seg2. The edge is
"early" since it occurs before a Sync_Seg. Reacting to the "early" edge, Phase_Seg2 is shortened and
Sync_Seg is omitted, so that the distance from the edge to the sample point is the same as it would have
been from a Sync_Seg to the sample point if no edge had occurred. As in the previous example, the
magnitude of this "early" edge's phase error is less than SJW, so it is fully compensated.
The phase buffer segments are lengthened or shortened temporarily only; at the next bit time, the
segments return to their nominal programmed values.
In these examples, the bit timing is seen from the point of view of the CAN implementation's state
machine, where the bit time starts and ends at the sample points. The state machine omits Sync_Seg
when synchronizing on an "early" edge because it cannot subsequently redefine that time quantum of
Phase_Seg2 where the edge occurs to be the Sync_Seg.
The examples in Figure 22-13 show how short dominant noise spikes are filtered by synchronizations. In
both examples, the spike starts at the end of Prop_Seg and has the length of (Prop_Seg + Phase_Seg1).
In the first example, the synchronization jump width is greater than or equal to the phase error of the
spike's edge from recessive to dominant. Therefore the sample point is shifted after the end of the spike; a
recessive bus level is sampled.
In the second example, SJW is shorter than the phase error, so the sample point cannot be shifted far
enough; the dominant spike is sampled as actual bus level.

2372

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CAN Bit Timing

www.ti.com

Figure 22-13. Filtering of Short Dominant Spikes
Recessive
dominant

Spike

Rx-input

Sample-point

Sample-point

SJW >= phase error

Recessive
dominant

Spike

Rx-Input

Sample-point

Sample-point

SJW < phase error

Sync_Seg

Prop_Seg

Phase_Seg1

Phase_Seg2

22.12.1.4 Oscillator Tolerance Range
With the introduction of CAN protocol version 1.2, the option to synchronize on edges from dominant to
recessive became obsolete. Only edges from recessive to dominant are considered for synchronization.
The protocol update to version 2.0 (A and B) had no influence on the oscillator tolerance.
The tolerance range df for an oscillator's frequency fosc around the nominal frequency fnom with
(1 - df) • fnom≤ fosc≤(1 + df) • fnom
depends on the proportions of Phase_Seg1, Phase_Seg2, SJW, and the bit time. The maximum tolerance
df is the defined by two conditions (both shall be met):
(8)

df £
df £

min (Tseg1, Tseg 2 )
2 ((13 ´ bit time ) - Tseg 2 )
SJW
20 ´ bit _ time

It has to be considered that SJW may not be larger than the smaller of the phase buffer segments and
that the propagation time segment limits that part of the bit time that may be used for the phase buffer
segments.
The combination Prop_Seg = 1 and Phase_Seg1 = Phase_Seg2 = SJW = 4 allows the largest possible
oscillator tolerance of 1.58%. This combination with a Propagation Time Segment of only 10% of the bit
time is not suitable for short bit times; it can be used for bit rates of up to 125 kBit/s (bit time = 8 μs) with a
bus length of 40 m.

22.12.2 Configuration of the CAN Bit Timing
In the CAN, the bit timing configuration is programmed in two register bytes, additionally a third byte for a
baud rate prescaler extension of 4 bits (BRPE) is provided. The sum of Prop_Seg and Phase_Seg1 (as
TSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte, SJW and BRP (plus BRPE in third byte)
are combined in the other byte (see Figure 22-14).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2373

CAN Bit Timing

www.ti.com

Figure 22-14. Structure of the CAN Core's CAN Protocol Controller
Configuration (BRPE/BRP)
System clock

Scaled_Clock (tq)

Baudrate_
prescaler

Control
Sample_Point

Bit stream processor

Sampled_Bit
Bit

Sync_Mode

timing
Bit_to_send

logic
Transmit_Data

IPT

Receive_Data

Status

Bus-Off

Received_Data_Bit
Send_Message

Control
Next_Data_Bit

Shift-Register
Received_Message

Configuration (TSEG1, TSEG2, SJW)

In this bit timing register, the components TSEG1, TSEG2, SJW and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1…n],
values in the range of [0…n-1] are programmed. That way, for example, SJW (functional range of [1…4])
is represented by only two bits.
Therefore the length of the Bit time is (programmed values) [TSEG1 + TSEG2 + 3] tq or (functional values)
[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.
The data in the Bit Timing Register is the configuration input of the CAN protocol controller. The baud rate
prescaler (configured by BRPE/BRP) defines the length of the time quantum (the basic time unit of the bit
time); the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in
the bit time.
The processing of the bit time, the calculation of the position of the Sample Point, and occasional
synchronizations are controlled by the Bit timing state machine, which is evaluated once each time
quantum. The rest of the CAN protocol controller, the Bit Stream Processor (BSP) state machine, is
evaluated once each bit time, at the Sample Point.
The Shift register serializes the messages to be sent and parallelizes received messages. Its loading and
shifting is controlled by the BSP.
The BSP translates messages into frames and vice versa. It generates and discards the enclosing fixed
format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the error
management, and decides which type of synchronization is to be used. It is evaluated at the sample point
and processes the sampled bus input bit. The time after the sample point that is needed to calculate the
next bit to be sent (for example, data bit, CRC bit, stuff bit, error flag, or idle) is called the Information
Processing Time (IPT), which is 0 tq for the CAN.
Generally, the IPT is CAN controller specific, but may not be longer than 2 tq. The IPC length is the lower
limit of the programmed length of Phase_Seg2. In case of a synchronization, Phase_Seg2 may be
shortened to a value less than IPT, which does not affect bus timing.
22.12.2.1 Calculation of the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time. The resulting
Bit time (1 / Bit rate) must be an integer multiple of the CAN clock period.

2374

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

CAN Bit Timing

www.ti.com

NOTE: 8 MHz is the minimum CAN clock frequency required to operate the CAN at a bit rate of 1
MBit/s.

The bit time may consist of 8 to 25 time quanta. The length of the time quantum tq is defined by the Baud
Rate Prescaler with tq = (Baud Rate Prescaler) / CAN_CLK. Several combinations may lead to the desired
bit time, allowing iterations of the following steps.
The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times
measured in the system. A maximum bus length as well as a maximum node delay has to be defined for
expandible CAN bus systems. The resulting time for Prop_Seg is converted into time quanta (rounded up
to the nearest integer multiple of tq).
The Sync_Seg is 1 tq long (fixed), leaving (bit time - Prop_Seg - 1) tq for the two Phase Buffer Segments.
If the number of remaining tq is even, the Phase Buffer Segments have the same length, Phase_Seg2 =
Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.
The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may not be shorter
than any CAN controller's Information Processing Time in the network, which is device dependent and can
be in the range of [0…2] tq.
The length of the synchronization jump width is set to its maximum value, which is the minimum of 4 and
Phase_Seg1.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formulas given
in Section 22.12.1.4.
If more than one configurations are possible to reach a certain Bit rate, it is recommended to choose the
configuration which allows the highest oscillator tolerance range.
CAN nodes with different clocks require different configurations to come to the same bit rate. The
calculation of the propagation time in the CAN network, based on the nodes with the longest delay times,
is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol compliant configuration of the CAN bit
timing.
The resulting configuration is written into the Bit Timing register:
(Phase_Seg2-1)&(Phase_Seg1+Prop_Seg-1)&
(SynchronizationJumpWidth-1)&(Prescaler-1)
22.12.2.2 Example for Bit Timing at High Baudrate
In this example, the frequency of CAN_CLK is 10 MHz, BRP is 0, the bit rate is 1 MBit/s.
tq
delay of bus driver
delay of receiver circuit
delay of bus line (40m)
tProp
tSJW
tTSeg1
tTSeg2
tSync-Seg
bit time

100
90
40
220
700
100
800
100
100
1000

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

=
=
=
=
=
=
=
=
=
=

tCAN_CLK

2*delays = 7 • tq
1 • tq
tProp + tSJW
Information Processing Time + 1 • tq
1 • tq
tSync-Seg + tTSeg1 + tTSeg2

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2375

Message Interface Register Sets

tolerance for CAN_CLK

www.ti.com

0.43 %

min (Tseg1, Tseg 2 )

=

2 ((13 ´ bit time ) - Tseg 2 )
=

0.1 ms
2 ((13 ´ 1 ms ) - 0.1 ms )

In this example, the concatenated bit time parameters are (1-1)3&(8-1)4&(1-1)2&(1-1)6, so the Bit Timing
Register is programmed to = 0x00000700.
22.12.2.3 Example for Bit Timing at Low Baudrate
In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s.
tq
delay of bus driver
delay of receiver circuit
delay of bus line (40m)
tProp
tSJW
tTSeg1
tTSeg2
tSync-Seg
bit time
tolerance for CAN_CLK

1
200
80
220
1
4
5
4
1
10
3.08

μs
ns
ns
ns
μs
μs
μs
μs
μs
μs
%

=
=
=
=
=
=
=
=
=
=
=

2 • tCAN_CLK

1 • tq
4 • tq
tProp + tSJW
Information Processing Time + 4 • tq
1 • tq
tSync-Seg + tTSeg1 + tTSeg2
min (Tseg1, Tseg 2 )

2 ((13 ´ bit time ) - Tseg 2 )
=

4 ms
2 ((13 ´ 10 ms ) - 4 ms )

In this example, the concatenated bit time parameters are (4-1)3&(5-1)4&(4-1)2&(2-1)6, so the Bit Timing
register is programmed to = 0x000034C1.

22.13 Message Interface Register Sets
The interface register sets control the CPU read and write accesses to the Message RAM. There are two
interface register sets for read / write access (IF1 and IF2) and one Interface Register Set for read access
only (IF3).
Due to the structure of the Message RAM, it is not possible to change single bits or bytes of a message
object. Instead, always a complete message object in the Message RAM is accessed. Therefore the data
transfer from the IF1 or IF2 registers to the Message RAM requires the message handler to perform a
read-modifywrite cycle. First those parts of the message object that are not to be changed are read from
the Message RAM into the Interface Register set, and after the update the whole content of the Interface
Register set is written into the message object.
After the partial write of a message object, those parts of the Interface Register set which are not selected
in the Command Register, will be set to the actual contents of the selected message object. After the
partial read of a message object, those parts of the Interface Register set which are not selected in the
Command Register, will be left unchanged.
By buffering the data to be transferred, the Interface Register sets avoid conflicts between concurrent
CPU accesses to the Message RAM and CAN message reception and transmission. A complete message
object (see Section 22.14.1) or parts of the message object may be transferred between the Message
RAM and the IF1 or IF2 Register set in one single transfer. This transfer, performed in parallel on all
selected parts of the message object, guarantees the data consistency of the CAN message.

2376

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Message Interface Register Sets

www.ti.com

That being said, there is one condition that can cause a write access to the message RAM to be lost. If
MsgVal = 1 for the message object which is accessed and CAN communication is ongoing, a transfer from
the IFx register to message RAM may be lost. The reason for this is that it might happen that the IFx
register write to the message RAM occurs in between a read-modify-write access of the Host Message
Handler when it is in the process of receiving a message for the same message object.
To avoid this issue with receive mail boxes, reset MsgVal before changing any of the following: Id28-0,
Xtd, Dir, DLC3-0, RxIE, TxIE, RmtEn, EoB, Umask, Msk28-0, MXtd, and MDir.
To avoid this issue with transmit mail boxes, reset MsgVal before changing any of the following: Dir, RxIE,
TxIE, RmtEn, EoB, Umask, Msk28-0, MXtd, and MDir. Other fields not listed above, like Data, may be
changed without fear of losing a write to the message RAM.

22.13.1 Message Interface Register Sets 1 and 2
The IF1 and IF2 registers Sets control the data transfer to and from the message object. The Command
Register addresses the desired message object in the Message RAM and specifies whether a complete
message object or only parts should be transferred. The data transfer is initiated by writing the message
number to the bits [7:0] of the Command Register.
When the CPU initiates a data transfer between the IF1 or IF2 registers and Message RAM, the message
handler sets the Busy bit in the respective Command Register to '1'. After the transfer has completed, the
Busy bit is set back to '0' (seeFigure 22-15 ).
Figure 22-15. Data Transfer Between IF1 / IF2 Registers and Message RAM
START

No
Write message number to command register
Yes
Busy = 1

No

WR/RD = 1

Yes

Read message object to IF1/IF2
Read message object to IF1/IF2
Write IF1/IF2 to message RAM

Busy = 0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2377

Message Interface Register Sets

www.ti.com

22.13.2 IF3 Register Set
The IF3 register set can automatically be updated with received message objects without the need to
initiate the transfer from Message RAM by CPU. The automatic update functionality can be programmed
for each message object (see IF3 Update Enable register.
All valid message objects in Message RAM which are configured for automatic update, will be checked for
active NewDat flags. If such a message object is found, it will be transferred to the IF3 register, controlled
by IF3 Observation register. If more than one NewDat flag is active, the message object with the lowest
number has the highest priority for automatic IF3 update.
The NewDat bit in the message object will be reset by a transfer to IF3.
If CAN internal IF3 update is complete, an IF3 interrupt can also be generated.
NOTE: The IF3 register set cannot be used for transferring data into message objects.

22.14 Message RAM
The CAN Message RAM contains message objects and parity bits for the message objects. There are 32
message objects in the Message RAM.
During normal operation, accesses to the Message RAM are performed via the Interface Register sets,
and the CPU cannot directly access the Message RAM.
The Interface Register sets IF1 and IF2 provide indirect read/write access from the CPU to the Message
RAM. The IF1 and IF2 register sets can buffer control and user data to be transferred to and from the
message objects.
The third Interface Register set IF3 can be configured to automatically receive control and user data from
the Message RAM when a message object has been updated after reception of a CAN message. The
CPU does not need to initiate the transfer from Message RAM to IF3 Register set.
The message handler avoids potential conflicts between concurrent accesses to Message RAM and CAN
frame reception/transmission.
The message RAM can only be accessed in debug mode. The message RAM base address is 0x1000
above the base address of the CAN peripheral.

22.14.1 Structure of Message Objects
Figure 22-16 shows the structure of a message object.
The grayed fields are those parts of the message object which are represented in dedicated registers. For
example, the transmit request flags of all message objects are represented in centralized transmit request
registers.
Figure 22-16. Structure of a Message Object
UMask
MsgVal

Msk[28:0
]
ID[28:0]

MXtd

MDir

EoB

Xtd

Dir

DLC[3:0]

Message Object
unused NewDat MsgLst
Data 0

Data 1

Data 2

RxIE

TxIE

IntPnd

RmtEn

TxRqst

Data 3

Data 4

Data 5

Data 6

Data 7

Table 22-5. Message Object Field Descriptions
Name

Value

MsgVal

Description
Message valid

0

The message object is ignored by the message handler.

1

The message object is to be used by the message handler.
Note: This bit may be kept at level '1' even when the identifier bits ID[28:0], the control bits Xtd, Dir, or the
data length code DLC[3:0] are changed. It should be reset if the Messages Object is no longer required.

2378

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Message RAM

www.ti.com

Table 22-5. Message Object Field Descriptions (continued)
Name

Value

UMask

Description
Use Acceptance Mask

0

Mask bits (Msk[28:0], MXtd and MDir) are ignored and not used for acceptance filtering.

1

Mask bits are used for acceptance filtering.
Note: If the UMask bit is set to one, the message object's mask bits have to be programmed during
initialization of the message object before MsgVal is set to one.

ID[28:0]

Message Identifier
ID[28:0]

29-bit ("extended") identifier bits

ID[28:18] 11-bit ("standard") identifier bits
Msk[28:0]

Identifier Mask Note: The bit functionality in DCAN module is the opposite of the "Local Acceptance Mask"
bit functionality in the eCAN module found in older C28xx devices, where a "1" means the corresponding
bit is NOT used for filtering and "0" means it is used.
0

The corresponding bit in the message identifier is not used for acceptance filtering (don't care).

1

The corresponding bit in the message identifier is used for acceptance filtering.
Note: The bit functionality in DCAN module is the opposite of the "Local Acceptance Mask" bit functionality
in the eCAN module found in older C28xx devices, where a "1" means the corresponding bit is NOT used
for filtering and "0" means it is used.

Xtd

Extended Identifier
0

The 11-bit ("standard") identifier will be used for this message object.

1

The 29-bit ("extended") identifier will be used for this message object.

MXtd

Mask Extended Identifier
0

The extended identifier bit (IDE) has no effect on the acceptance filtering.

1

The extended identifier bit (IDE) is used for acceptance filtering.
Note: When 11-bit ("standard") Identifiers are used for a message object, the identifiers of received data
frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits
Msk[28:18] are considered.

Dir

Message Direction
0

Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On
reception of a data frame with matching identifier, the message is stored in this message object.

1

Direction = transmit: On TxRqst, a data frame is transmitted. On reception of a remote frame with matching
identifier, the TxRqst bit of this message object is set (if RmtEn = one).

MDir

Mask Message Direction
0

The message direction bit (Dir) has no effect on the acceptance filtering.

1

The message direction bit (Dir) is used for acceptance filtering.

EOB

End of Block
0

The message object is part of a FIFO Buffer block and is not the last message object of this FIFO Buffer
block.

1

The message object is a single message object or the last message object in a FIFO Buffer Block.
Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message
objects (not belonging to a FIFO Buffer), this bit must always be set to one.

NewDat

New Data
0

No new data has been written into the data bytes of this message object by the message handler since the
last time when this flag was cleared by the CPU.

1

The message handler or the CPU has written new data into the data bytes of this message object.

MsgLst

Message Lost (only valid for Message Objects with direction = receive)
0

No message was lost since the last time when this bit was reset by the CPU.

1

The message handler stored a new message into this message object when NewDat was still set, so the
previous message has been overwritten.

RxIE

Receive Interrupt Enable
0

IntPnd will not be triggered after the successful reception of a frame.

1

IntPnd will be triggered after the successful reception of a frame.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2379

Message RAM

www.ti.com

Table 22-5. Message Object Field Descriptions (continued)
Name

Value

TxIE

Description
Transmit Interrupt Enable

0

IntPnd will not be triggered after the successful transmission of a frame.

1

IntPnd will be triggered after the successful transmission of a frame.

IntPnd

Interrupt Pending
0

This message object is not the source of an interrupt.

1

This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point
to this message object if there is no other interrupt source with higher priority.

RmtEn

Remote Enable
0

At the reception of a remote frame, TxRqst is not changed.

1

At the reception of a remote frame, TxRqst is set.
Note: See Section 22.11.8 for details on the setup of RmtEn and UMask for remote frames.

TxRqst

Transmit Request
0

This message object is not waiting for a transmission.

1

The transmission of this message object is requested and is not yet done.

DLC[3:0]

Data length code
0-8

Data frame has 0-8 data bytes.

9-15

Data frame has 8 data bytes.
Note: The data length code of a message object must be defined to the same value as in the
corresponding objects with the same identifier at other nodes. When the message handler stores a data
frame, it will write the DLC to the value given by the received message.

Data 0

1st data byte of a CAN data frame

Data 1

2nd data byte of a CAN data frame

Data 2

3rd data byte of a CAN data frame

Data 3

4th data byte of a CAN data frame

Data 4

5th data byte of a CAN data frame

Data 5

6th data byte of a CAN data frame

Data 6

7th data byte of a CAN data frame

Data 7

8th data byte of a CAN data frame
Note: Byte Data 0 is the first data byte shifted into the shift register of the CAN Core during a reception,
byte Data 7 is the last. When the message handler stores a data frame, it will write all the eight data bytes
into a message object. If the data length code is less than 8, the remaining bytes of the message object
may be overwritten by undefined values.

22.14.2 Addressing Message Objects in RAM
The starting location of a particular message object in RAM is:
Message RAM base address + (message object number) * 0x20.
This means that Message Object 1 starts at offset 0x0020; Message Object 2 starts at offset 0x0040, etc.
NOTE:

'0' is not a valid message object number. At address 0x0000, the last message object (32)
(with the lowest priority) is located. Writing to the address of an unimplemented message
object may overwrite an implemented message object.

Message Object number 1 has the highest priority.

2380

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Message RAM

www.ti.com

Table 22-6. Message RAM Addressing in Debug Mode
Message Object Number

Offset From Base
Address

Word Number

Debug Mode (1)

last implemented (here:32)

0x0000

1

Parity

0x0004

2

MXtd,MDir,Mask

0x0008

3

Xtd,Dir,ID

0x000C

4

Ctrl

0x0010

5

Data Bytes 3-0

0x0014

6

Data Bytes 7-4

0x0020

1

Parity

0x0024

2

MXtd,MDir,Mask
Xtd,Dir,ID

1

2

(1)

0x0028

3

0x002C

4

Ctrl

0x0030

5

Data Bytes 3-0

0x0034

6

Data Bytes 7-4

0x0040

1

Parity

0x0044

2

MXtd,MDir,Mask
Xtd,Dir,ID

0x0048

3

0x004C

4

Ctrl

0x0050

5

Data Bytes 3-0

0x0054

6

Data Bytes 7-4

…

…

…

…

31

0x03E0

1

Parity

0x03E4

2

MXtd,MDir,Mask
Xtd,Dir,ID

0x03E8

3

0x03EC

4

Ctrl

0x03F0

5

Data Bytes 3-0

0x03F4

6

Data Bytes 7-4

See Section 22.14.3.

22.14.3 Message RAM Representation in Debug Mode
In debug mode, the Message RAM will be memory mapped. This allows the external debug unit to access
the Message RAM.
NOTE: During debug mode, the Message RAM cannot be accessed via the IFx register sets.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2381

Message RAM

www.ti.com

Figure 22-17. Message RAM Representation in Debug Mode
31/
15

30/
14

29/
13

28/
12

27/
11

26/
10

25/
9

24/
8

23/
7

22/
6

21/
5

20/
4

19/
3

18/
2

17/
1

16/
0

MsgAddr + 0x00
Reserved
Reserved

Parity[4:0]

MsgAddr + 0x04
MXtd

MDir

Rsvd

Msk[28:16]
Msk[15:0]

MsgAddr + 0x08
Rsvd

Xtd

Dir

ID[28:16]
ID[15:0]

MsgAddr + 0x0C
Reserved
Rsvd

MsgLs
t

Rsvd

UMask

TxIE

RxIE

RmtEn

Rsvd

EOB

Reserved

DLC[3:0]

MsgAddr + 0x10
Data 3
Data 1

Data 2
Data 0

Data 7
Data 5

Data 6
Data 4

MsgAddr + 0x14

2382

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15 Registers
22.15.1 CAN Base Addresses
Table 22-7. CAN Base Addresses Table
Device Registers

Register Name

Start Address

End Address

CanaRegs

CAN_REGS

0x0004_8000

0x0004_87FF

CanbRegs

CAN_REGS

0x0004_A000

0x0004_A7FF

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2383

Registers

www.ti.com

22.15.2 CAN_REGS Registers
Table 22-8 lists the memory-mapped registers for the CAN_REGS. All register offset addresses not listed
in Table 22-8 should be considered as reserved locations and the register contents should not be
modified.
Table 22-8. CAN_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

CAN_CTL

CAN Control Register

Go

4h

CAN_ES

Error and Status Register

Go

8h

CAN_ERRC

Error Counter Register

Go

Ch

CAN_BTR

Bit Timing Register

Go

10h

CAN_INT

Interrupt Register

Go

14h

CAN_TEST

Test Register

Go

1Ch

CAN_PERR

CAN Parity Error Code Register

Go

40h

CAN_RAM_INIT

CAN RAM Initialization Register

Go

50h

CAN_GLB_INT_EN

CAN Global Interrupt Enable Register

Go

54h

CAN_GLB_INT_FLG

CAN Global Interrupt Flag Register

Go

58h

CAN_GLB_INT_CLR

CAN Global Interrupt Clear Register

Go

80h

CAN_ABOTR

Auto-Bus-On Time Register

Go

84h

CAN_TXRQ_X

CAN Transmission Request Register

Go

88h

CAN_TXRQ_21

CAN Transmission Request 2_1 Register

Go

98h

CAN_NDAT_X

CAN New Data Register

Go

9Ch

CAN_NDAT_21

CAN New Data 2_1 Register

Go

ACh

CAN_IPEN_X

CAN Interrupt Pending Register

Go

B0h

CAN_IPEN_21

CAN Interrupt Pending 2_1 Register

Go

C0h

CAN_MVAL_X

CAN Message Valid Register

Go

C4h

CAN_MVAL_21

CAN Message Valid 2_1 Register

Go

D8h

CAN_IP_MUX21

CAN Interrupt Multiplexer 2_1 Register

Go

100h

CAN_IF1CMD

IF1 Command Register

Go

104h

CAN_IF1MSK

IF1 Mask Register

Go

108h

CAN_IF1ARB

IF1 Arbitration Register

Go

10Ch

CAN_IF1MCTL

IF1 Message Control Register

Go

110h

CAN_IF1DATA

IF1 Data A Register

Go

114h

CAN_IF1DATB

IF1 Data B Register

Go

120h

CAN_IF2CMD

IF2 Command Register

Go

124h

CAN_IF2MSK

IF2 Mask Register

Go

128h

CAN_IF2ARB

IF2 Arbitration Register

Go

12Ch

CAN_IF2MCTL

IF2 Message Control Register

Go

130h

CAN_IF2DATA

IF2 Data A Register

Go

134h

CAN_IF2DATB

IF2 Data B Register

Go

140h

CAN_IF3OBS

IF3 Observation Register

Go

144h

CAN_IF3MSK

IF3 Mask Register

Go

148h

CAN_IF3ARB

IF3 Arbitration Register

Go

14Ch

CAN_IF3MCTL

IF3 Message Control Register

Go

150h

CAN_IF3DATA

IF3 Data A Register

Go

154h

CAN_IF3DATB

IF3 Data B Register

Go

160h

CAN_IF3UPD

IF3 Update Enable Register

Go

Complex bit access types are encoded to fit into small table cells. Table 22-9 shows the codes that are
used for access types in this section.
2384

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-9. CAN_REGS Access Type Codes
Access Type

Code

Description

R

Read

W

W

Write

W=1

W

Write

Read Type
R
Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2385

Registers

www.ti.com

22.15.2.1 CAN_CTL Register (Offset = 0h) [reset = 1401h]
CAN_CTL is shown in Figure 22-18 and described in Table 22-10.
Return to Summary Table.
This register is used for configuring the CAN module in terms of interrupts, parity, debug-mode behavior
etc.
Figure 22-18. CAN_CTL Register
31

30

29

28

27

26

25
RESERVED
R-0h

24
RESERVED
R-0h

19

18

17
IE1
R/W-0h

16
INITDBG
R-0h

11

10

9
ABO
R/W-0h

8
IDS
R/W-0h

3
EIE
R/W-0h

2
SIE
R/W-0h

1
IE0
R/W-0h

0
Init
R/W-1h

RESERVED
R-0h
23

22
RESERVED
R-0h

21

20

15
SWR
R/W-0h

14
RESERVED
R-0h

13

12

7
Test
R/W-0h

6
CCE
R/W-0h

5
DAR
R/W-0h

PMD
R/W-5h
4
RESERVED
R-0h

Table 22-10. CAN_CTL Register Field Descriptions
Field

Type

Reset

Description

31-26

Bit

RESERVED

R

0h

Reserved

25

RESERVED

R

0h

Reserved

24

RESERVED

R

0h

Reserved

23-21

RESERVED

R

0h

Reserved

20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18

RESERVED

R

0h

Reserved

17

IE1

R/W

0h

Interrupt line 1 Enable
0 CANINT1 is disabled.
1 CANINT1 is enabled. Interrupts will assert CANINT1 line to 1
line remains active until pending interrupts are processed.
Reset type: SYSRSn

16

INITDBG

R

0h

Debug Mode Status Bit: This bit indicates the internal init state for a
debug access
0 Not in debug mode, or debug mode requested but not entered.
1 Debug mode requested and internally entered
the CAN module is ready for debug accesses.
Reset type: SYSRSn

15

SWR

R/W

0h

Software Reset Enable Bit: This bit activates the software reset.
0 Normal Operation.
1 Module is forced to reset state. This bit will get cleared
automatically one clock cycle after execution of software reset.
Note: To execute software reset, the following procedure is
necessary:
1. Set INIT bit to shut down CAN communication.
2. Set SWR bit.
This bit is EALLOW protected.
Note: This bit is write-protected by Init bit
Reset type: SYSRSn

2386

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-10. CAN_CTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

14

RESERVED

R

0h

Reserved

PMD

R/W

5h

Parity on/off

13-10

0101 Parity function disabled
Any other value - Parity function enabled
Reset type: SYSRSn
9

ABO

R/W

0h

Auto-Bus-On Enable
0 The Auto-Bus-On feature is disabled
1 The Auto-Bus-On feature is enabled
Reset type: SYSRSn

8

IDS

R/W

0h

Interruption Debug Support Enable
0 When Debug mode is requested, the CAN module will wait for a
started transmission or reception to be completed before entering
Debug mode
1 When Debug mode is requested, the CAN module will interrupt
any transmission or reception, and enter Debug mode immediately.
Reset type: SYSRSn

7

Test

R/W

0h

Test Mode Enable
0 Disable Test Mode (Normal operation)
1 Enable Test Mode
Reset type: SYSRSn

6

CCE

R/W

0h

Configuration Change Enable
0 The CPU has no write access to the configuration registers.
1 The CPU has write access to the configuration registers (when Init
bit is set).
Reset type: SYSRSn

5

DAR

R/W

0h

Disable Automatic Retransmission
0 Automatic Retransmission of "not successful" messages enabled.
1 Automatic Retransmission disabled.
Reset type: SYSRSn

4

RESERVED

R

0h

Reserved

3

EIE

R/W

0h

Error Interrupt Enable
0 PER, BOff and EWarn bits cannot generate an interrupt.
1 Enabled- PER, BOff and EWarn bits can generate an interrupt at
CANINT0 line and affect the Interrupt Register.
Reset type: SYSRSn

2

SIE

R/W

0h

Status Change Interrupt Enable
0 RxOk, TxOk and LEC bits cannot generate an interrupt.
1 RxOk, TxOk and LEC can generate an interrupt on the CANINT0
line
Reset type: SYSRSn

1

IE0

R/W

0h

Interrupt line 0 Enable
0 CANINT0 is disabled.
1 CANINT0 is enabled. Interrupts will assert CANINT0 line to 1
line remains active until pending interrupts are processed.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2387

Registers

www.ti.com

Table 22-10. CAN_CTL Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

Init

R/W

1h

Initialization Mode
This bit is used to keep the CAN module inactive during bit timing
configuration and message RAM initialization. It is set automatically
during a bus off event. Clearing this bit will not shorten the bus
recovery time.
0 CAN module processes messages normally
1 CAN module ignores bus activity
Reset type: SYSRSn

2388

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.2 CAN_ES Register (Offset = 4h) [reset = 7h]
CAN_ES is shown in Figure 22-19 and described in Table 22-11.
Return to Summary Table.
This register indicates error conditions, if any, of the CAN module. Interrupts are generated by PER, BOff
and EWarn bits (if EIE bit in CAN Control Register is set) and by RxOk, TxOk, and LEC bits (if SIE bit in
CAN Control Register is set). A change of bit EPass will not generate an Interrupt.
Reading the Error and Status Register clears the PER, RxOk and TxOk bits and sets the LEC to value '7'.
Additionally, the Status Interrupt value (0x8000) in the Interrupt Register will be replaced by the next lower
priority interrupt value.
For debug support, the auto clear functionality of Error and Status Register (clear of status flags by read)
is disabled when in Debug/Suspend mode.
Figure 22-19. CAN_ES Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13
RESERVED
R-0h

12

11

10
RESERVED
R-0h

9
RESERVED
R-0h

8
PER
R-0h

7
BOff
R-0h

6
EWarn
R-0h

5
EPass
R-0h

4
RxOk
R-0h

3
TxOk
R-0h

2

1
LEC
R-7h

0

Table 22-11. CAN_ES Register Field Descriptions
Field

Type

Reset

Description

31-11

Bit

RESERVED

R

0h

Reserved

10

RESERVED

R

0h

Reserved

9

RESERVED

R

0h

Reserved

8

PER

R

0h

Parity Error Detected: This bit will be reset after the CPU reads the
register.
0 No parity error has been detected since last read access.
1 The parity check mechanism has detected a parity error in the
Message RAM.
Reset type: SYSRSn

7

BOff

R

0h

Bus-off Status Bit:
0 The CAN module is not Bus-Off state.
1 The CAN module is in Bus-Off state.
Reset type: SYSRSn

6

EWarn

R

0h

Warning State Bit:
0 Both error counters are below the error warning limit of 96.
1 At least one of the error counters has reached the error warning
limit of 96.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2389

Registers

www.ti.com

Table 22-11. CAN_ES Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5

EPass

R

0h

Error Passive State
0 On CAN Bus error, the CAN could send active error frames.
1 The CAN Core is in the error passive state as defined in the CAN
Specification.
Reset type: SYSRSn

4

RxOk

R

0h

Reception status Bit: This bit indicates the status of reception. The
bit will be reset after the CPU reads the register.
0 No message has been successfully received since the last time
when this bit was read by the CPU. This bit is never reset by CAN
internal events.
1 A message has been successfully received since the last time
when this bit was reset by a read access of the CPU.
Reset type: SYSRSn

3

TxOk

R

0h

Transmission status Bit: This bit indicates the status of transmission.
The bit will be reset after the CPU reads the register.
0 No message has been successfully transmitted since the last time
when this bit was read by the CPU. This bit is never reset by CAN
internal events.
1 A message has been successfully transmitted (error free and
acknowledged by at least one other node) since the last time when
this bit was cleared by a read access of the CPU.
Reset type: SYSRSn

2-0

LEC

R

7h

Last Error Code
The LEC field indicates the type of the last error on the CAN bus.
This field will be cleared to '0' when a message has been transferred
(reception or transmission) without error. This field will be reset to '7'
whenever the CPU reads the register.
0 No Error
1 Stuff Error: More than five equal bits in a row have been detected
in a part of a received message where this is not allowed.
2 Form Error: A fixed format part of a received frame has the wrong
format.
3 Ack Error: The message this CAN Core transmitted was not
acknowledged by another node.
4 Bit1 Error: During the transmission of a message (with the
exception of the arbitration field), the device wanted to send a
recessive level (bit of logical value '1'), but the monitored bus value
was dominant.
5 Bit0 Error: During the transmission of a message (or acknowledge
bit, or active error flag, or overload flag), the device wanted to send a
dominant level (logical value '0'), but the monitored bus level was
recessive. During Bus-Off recovery, this status is set each time a
sequence of 11 recessive bits has been monitored. This enables the
CPU to monitor the proceeding of the Bus-Off recovery sequence
(indicating the bus is not stuck at dominant or continuously
disturbed).
6 CRC Error: In a received message, the CRC check sum was
incorrect. (CRC received for an incoming message does not match
the calculated CRC for the received data).
7 No CAN bus event was detected since the last time when CPU
has read the Error and Status Register. Any read access to the Error
and Status Register re-initializes the LEC to value '7'.
Reset type: SYSRSn

2390

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.3 CAN_ERRC Register (Offset = 8h) [reset = 0h]
CAN_ERRC is shown in Figure 22-20 and described in Table 22-12.
Return to Summary Table.
This register reflects the value of the Transmit and Receive error counters
Figure 22-20. CAN_ERRC Register
31

30

29

28

27

26

25

15
RP
R-0h

14

13

12

11
REC
R-0h

10

9

24
23
RESERVED
R-0h
8

7

22

21

20

6

5

4

19

18

17

16

3

2

1

0

TEC
R-0h

Table 22-12. CAN_ERRC Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

RP

R

0h

Receive Error Passive
0 The Receive Error Counter is below the error passive level.
1 The Receive Error Counter has reached the error passive level as
defined in the CAN Specification.
Reset type: SYSRSn

14-8

REC

R

0h

Receive Error Counter
Actual state of the Receive Error Counter (values from 0 to 127).
Reset type: SYSRSn

7-0

TEC

R

0h

Transmit Error Counter
Actual state of the Transmit Error Counter. (values from 0 to 255).
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2391

Registers

www.ti.com

22.15.2.4 CAN_BTR Register (Offset = Ch) [reset = 2301h]
CAN_BTR is shown in Figure 22-21 and described in Table 22-13.
Return to Summary Table.
This register is used to configure the bit-timing parameters for the CAN module. This register is only
writable if CCE and Init bits in the CAN Control Register are set.
The CAN bit time may be programmed in the range of 8 to 25 time quanta.
The CAN time quantum may be programmed in the range of 1 to1024 CAN_CLK periods.
Figure 22-21. CAN_BTR Register
31

30

29

28

27

26

19

18

25

24

17

16

9

8

1

0

RESERVED
R-0h
23

22

21

20

RESERVED
R-0h
15
RESERVED
R-0h

14

7

6

BRPE
R/W-0h

13
TSEG2
R/W-2h

12

5

4

11

10
TSEG1
R/W-3h

3

2

SJW
R/W-0h

BRP
R/W-1h

Table 22-13. CAN_BTR Register Field Descriptions
Field

Type

Reset

Description

31-20

Bit

RESERVED

R

0h

Reserved

19-16

BRPE

R/W

0h

Baud Rate Prescaler Extension
Valid programmed values are 0 to 15.
By programming BRPE the Baud Rate Prescaler can be extended to
values up to 1024.
Note: This bit is Write Protected by CCE bit.
Reset type: SYSRSn

15
14-12

RESERVED

R

0h

Reserved

TSEG2

R/W

2h

Time segment after the sample point Valid programmed values are 0
to 7.
The actual TSeg2 value which is interpreted for the Bit Timing will be
the programmed TSeg2 value + 1.
Note: This bit is Write Protected by CCE bit.
Reset type: SYSRSn

11-8

TSEG1

R/W

3h

Time segment before the sample point Valid programmed values are
1 to 15.
The actual TSeg1 value interpreted for the Bit Timing will be the
programmed TSeg1 value + 1.
Note: This bit is Write Protected by CCE bit.
Reset type: SYSRSn

7-6

SJW

R/W

0h

Synchronization Jump Width Valid programmed values are 0 to 3.
The actual SJW value interpreted for the Synchronization will be the
programmed SJW value + 1.
Note: This bit is Write Protected by CCE bit.
Reset type: SYSRSn

2392

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-13. CAN_BTR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

BRP

R/W

1h

Baud Rate PrescalerValue by which the CAN_CLK frequency is divided for generating the
bit time quanta. The bit time is built up from a multiple of this quanta.
Valid programmed values are 0 to 63.
The actual BRP value interpreted for the Bit Timing will be the
programmed BRP value + 1.
Note: This bit is Write Protected by CCE bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2393

Registers

www.ti.com

22.15.2.5 CAN_INT Register (Offset = 10h) [reset = 0h]
CAN_INT is shown in Figure 22-22 and described in Table 22-14.
Return to Summary Table.
This register is used to identify the source of the interrupt(s).
Figure 22-22. CAN_INT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
INT1ID
R-0h
R-0h

9

8 7
INT0ID
R-0h

6

5

4

3

2

1

0

Table 22-14. CAN_INT Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R

0h

Reserved

23-16

INT1ID

R

0h

Interrupt 1 Cause
0x00 No interrupt is pending.
0x01-0x20 Number of message object (mailbox) which caused the
interrupt.
0x21-0xFF Unused.
If several interrupts are pending, the CAN Interrupt Register will point
to the pending interrupt with the highest priority.
Note: The CANINT1 interrupt line remains active until INT0ID
reaches value 0 (the cause of the interrupt is reset) or until IE0 is
cleared. A message interrupt is cleared by clearing the mailbox's
IntPnd bit. Among the message interrupts, the mailbox's interrupt
priority decreases with increasing message number.
Reset type: SYSRSn

15-0

INT0ID

R

0h

Interrupt 0 Cause
0x0000 - No interrupt is pending.
0x0001 - 0x0020 - Number of message object which caused the
interrupt.
0x0021 - 0x7FFF - Unused.
0x8000 - Error and Status Register value is not 0x07.
0x8001 - 0xFFFF - Unused.
If several interrupts are pending, the CAN Interrupt Register will point
to the pending interrupt with the highest priority.
Note: The CANINT0 interrupt line remains active until INT0ID
reaches value 0 (the cause of the interrupt is reset) or until IE0 is
cleared. The Status Interrupt has the highest priority. Among the
message interrupts, the message object's interrupt priority decreases
with increasing message number.
Reset type: SYSRSn

2394

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.6 CAN_TEST Register (Offset = 14h) [reset = 0h]
CAN_TEST is shown in Figure 22-23 and described in Table 22-15.
Return to Summary Table.
This register is used to configure the various test options supported. For all test modes, the Test bit in
CAN Control Register needs to be set to one. If Test bit is set, the RDA, EXL, Tx1, Tx0, LBack and Silent
bits are writable. Bit Rx monitors the state of CANRX pin and therefore is only readable. All Test Register
functions are disabled when Test bit is cleared.
Note: Setting Tx[1:0] other than '00' will disturb message transfer.
Note: When the internal loop back mode is active (bit LBack is set), bit EXL will be ignored.
Figure 22-23. CAN_TEST Register
31

30

29

28

27

26

25

24

19

18

17

16

12

11

10

9
RDA
R/W-0h

8
EXL
R/W-0h

4
LBACK
R/W-0h

3
SILENT
R/W-0h

2

1
RESERVED
R-0h

0

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13
RESERVED
R-0h

7
RX
R-0h

6

5
TX
R/W-0h

Table 22-15. CAN_TEST Register Field Descriptions
Bit
31-10
9

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

RDA

R/W

0h

RAM Direct Access Enable:
0 Normal Operation.
1 Direct access to the RAM is enabled while in Test Mode.
Reset type: SYSRSn

8

EXL

R/W

0h

External Loop Back Mode:
0 Disabled.
1 Enabled.
Reset type: SYSRSn

7

RX

R

0h

Monitors the actual value of the CANRX pin:
0 The CAN bus is dominant.
1 The CAN bus is recessive.
Reset type: SYSRSn

6-5

TX

R/W

0h

Control of CANTX pin:
00 Normal operation, CANTX is controlled by the CAN Core.
01 Sample Point can be monitored at CANTX pin.
10 CANTX pin drives a dominant value.
11 CANTX pin drives a recessive value.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2395

Registers

www.ti.com

Table 22-15. CAN_TEST Register Field Descriptions (continued)
Bit
4

Field

Type

Reset

Description

LBACK

R/W

0h

Loop Back Mode:
0 Disabled.
1 Enabled.
Reset type: SYSRSn

3

SILENT

R/W

0h

Silent Mode:
0 Disabled.
1 Enabled.
Reset type: SYSRSn

2-0

2396

RESERVED

Controller Area Network (CAN)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.7 CAN_PERR Register (Offset = 1Ch) [reset = 100h]
CAN_PERR is shown in Figure 22-24 and described in Table 22-16.
Return to Summary Table.
This register indicates the Word/Mailbox number where a parity error has been detected. If a parity error is
detected, the PER flag will be set in the Error and Status Register. This bit is not reset by the parity check
mechanism
it must be reset by reading the Error and Status Register. In addition to the PER flag, the Parity Error
Code Register will indicate the memory area where the parity error has been detected. If more than one
word with a parity error was detected, the highest word number with a parity error will be displayed. After a
parity error has been detected, the register will hold the last error code until power is removed.
Figure 22-24. CAN_PERR Register
31

30

15

14

29

28

27

26

13
12
RESERVED
R-0h

11

10

25

24
23
RESERVED
R-0h

9
8
WORD_NUM
R-1h

7

22

21

20

19

18

17

16

6

5

4
3
MSG_NUM
R-0h

2

1

0

Table 22-16. CAN_PERR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-11

RESERVED

R

0h

Reserved

10-8

WORD_NUM

R

1h

0x01-0x05 Word number where parity error has been detected.
RDA word number (1 to 5) of the mailbox (according to the
Message RAM representation in RDA mode).
Reset type: SYSRSn

7-0

MSG_NUM

R

0h

0x01-0x21 Mailbox number where parity error has been detected
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2397

Registers

www.ti.com

22.15.2.8 CAN_RAM_INIT Register (Offset = 40h) [reset = 5h]
CAN_RAM_INIT is shown in Figure 22-25 and described in Table 22-17.
Return to Summary Table.
This register is used to initialize the Mailbox RAM. It clears the entire mailbox RAM, including the MsgVal
bits.
Figure 22-25. CAN_RAM_INIT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
KEY3

2
KEY2

1
KEY1

0
KEY0

R/W-0h

R/W-1h

R/W-0h

R/W-1h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6
RESERVED
R-0h

5
RAM_INIT_DO
NE
R-0h

4
CAN_RAM_INI
T
R/W-0h

Table 22-17. CAN_RAM_INIT Register Field Descriptions
Bit
31-6
5

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

RAM_INIT_DONE

R

0h

CAN Mailbox RAM initialization status:
0 Read: Initialization is on-going or initialization not initiated.
1 Read: Initialization complete
Reset type: SYSRSn

4

CAN_RAM_INIT

R/W

0h

Initiate CAN Mailbox RAM initialization:
0 Read: Initialization complete or initialization not initiated.
Write: No action
1 Read: Initialization is on-going
Write: Initiate CAN Mailbox RAM initialization. After initialization, this
bit will be automatically cleared to 0.
Reset type: SYSRSn

2398

3

KEY3

R/W

0h

See Key 0
Reset type: SYSRSn

2

KEY2

R/W

1h

See Key 0
Reset type: SYSRSn

1

KEY1

R/W

0h

See Key 0
Reset type: SYSRSn

0

KEY0

R/W

1h

KEY3-KEY0 should be 1010 for any write to this register to be valid.
These bits will be restored to their reset state after the CAN RAM
initialization is complete.
Reset type: SYSRSn

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.9 CAN_GLB_INT_EN Register (Offset = 50h) [reset = 0h]
CAN_GLB_INT_EN is shown in Figure 22-26 and described in Table 22-18.
Return to Summary Table.
This register is used to enable the interrupt lines to the PIE.
Figure 22-26. CAN_GLB_INT_EN Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
GLBINT1_EN
R/W-0h

0
GLBINT0_EN
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 22-18. CAN_GLB_INT_EN Register Field Descriptions
Bit
31-2
1

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

GLBINT1_EN

R/W

0h

Global Interrupt Enable for CANINT1
0 CANINT1 does not generate interrupt to PIE
1 CANINT1 generates interrupt to PIE if interrupt condition occurs
Reset type: SYSRSn

0

GLBINT0_EN

R/W

0h

Global Interrupt Enable for CANINT0
0 CANINT0 does not generate interrupt to PIE
1 CANINT0 generates interrupt to PIE if interrupt condition occurs
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2399

Registers

www.ti.com

22.15.2.10 CAN_GLB_INT_FLG Register (Offset = 54h) [reset = 0h]
CAN_GLB_INT_FLG is shown in Figure 22-27 and described in Table 22-19.
Return to Summary Table.
This register indicates if and when the interrupt line to the PIE is active.
Figure 22-27. CAN_GLB_INT_FLG Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
INT1_FLG
R-0h

0
INT0_FLG
R-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 22-19. CAN_GLB_INT_FLG Register Field Descriptions
Bit
31-2
1

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

INT1_FLG

R

0h

CANINT1 Flag
0 No interrupt generated
1 Interrupt is generated due to CANINT1 (refer to CAN Interrupt
Status Register for the condition)
Reset type: SYSRSn

0

INT0_FLG

R

0h

CANINT0 Flag
0 No interrupt generated
1 Interrupt is generated due to CANINT0 (refer to CAN Interrupt
Status Register for the condition)
Reset type: SYSRSn

2400

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.11 CAN_GLB_INT_CLR Register (Offset = 58h) [reset = 0h]
CAN_GLB_INT_CLR is shown in Figure 22-28 and described in Table 22-20.
Return to Summary Table.
This register is used to clear the interrupt to the PIE.
Figure 22-28. CAN_GLB_INT_CLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
INT1_FLG_CL
R
W-0h

0
INT0_FLG_CL
R
W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 22-20. CAN_GLB_INT_CLR Register Field Descriptions
Bit
31-2
1

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

INT1_FLG_CLR

W

0h

Global Interrupt flag clear for CANINT1
0 No effect
1 Write 1 to clear the corresponding bit of the Global Interrupt Flag
Register and allow the PIE to receive another interrupt from
CANINT1.
Reset type: SYSRSn

0

INT0_FLG_CLR

W

0h

Global Interrupt flag clear for CANINT0
0 No effect
1 Write 1 to clear the corresponding bit of the Global Interrupt Flag
Register and allow the PIE to receive another interrupt from
CANINT0.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2401

Registers

www.ti.com

22.15.2.12 CAN_ABOTR Register (Offset = 80h) [reset = 0h]
CAN_ABOTR is shown in Figure 22-29 and described in Table 22-21.
Return to Summary Table.
This register is used to introduce a variable delay before the Bus-off recovery sequence is started.
Figure 22-29. CAN_ABOTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ABO_Time
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 22-21. CAN_ABOTR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ABO_Time

R/W

0h

Auto-Bus-On Timer
Number of clock cycles before a Bus-Off recovery sequence is
started by clearing the Init bit. "Clock" refers to the input clock to the
CAN module. This function has to be enabled by setting bit ABO in
CAN Control Register.
The Auto-Bus-On timer is realized by a 32-bit counter which starts to
count down to zero when the module goes Bus-Off. The counter will
be reloaded with the preload value of the ABO Time register after
this phase.
NOTE: On write access to the CAN Control register while Auto-BusOn timer is running, the Auto-Bus-On procedure will be aborted.
NOTE: During Debug mode, running Auto-Bus-On timer will be
paused.
Reset type: SYSRSn

2402

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.13 CAN_TXRQ_X Register (Offset = 84h) [reset = 0h]
CAN_TXRQ_X is shown in Figure 22-30 and described in Table 22-22.
Return to Summary Table.
With these bits, the CPU can detect if one or more bits in the CAN Transmission Request 21 Register
(CAN_TXRQ_21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of
the TxRqst bits of these message objects is set, the corresponding bit in this register will be set.
Figure 22-30. CAN_TXRQ_X Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

3

RESERVED
R-0h

TxRqstReg2
R-0h

0
TxRqstReg1
R-0h

Table 22-22. CAN_TXRQ_X Register Field Descriptions
Field

Type

Reset

Description

31-4

Bit

RESERVED

R

0h

Reserved

3-2

TxRqstReg2

R

0h

Transmit Request Register 2 flag:
Bit 2 represents byte 2 of CAN_TXRQ_21. If one or more bits in that
byte are set, then bit 2 will be set.
Bit 3 represents byte 3 of CAN_TXRQ_21 Register. If one or more
bits in that byte are set, then bit 3 will be set.
Reset type: SYSRSn

1-0

TxRqstReg1

R

0h

Transmit Request Register 1 flag:
Bit 0 represents byte 0 of CAN_TXRQ_21 Register. If one or more
bits in that byte are set, then bit 0 will be set.
Bit 1 represents byte 1 of CAN_TXRQ_21 Register. If one or more
bits in that byte are set, then bit 1 will be set.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2403

Registers

www.ti.com

22.15.2.14 CAN_TXRQ_21 Register (Offset = 88h) [reset = 0h]
CAN_TXRQ_21 is shown in Figure 22-31 and described in Table 22-23.
Return to Summary Table.
The bits in this register indicate if a transmission has been requested for a mailbox.
Figure 22-31. CAN_TXRQ_21 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TxRqst
R-0h

9

8

7

6

5

4

3

2

1

0

Table 22-23. CAN_TXRQ_21 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

TxRqst

R

0h

Transmission Request Bits (for all message objects)
0 No transmission has been requested for this message object.
1 The transmission of this message object is requested and is not
yet done.
Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox
3,..., Bit 31 is for mailbox 32
Reset type: SYSRSn

2404

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.15 CAN_NDAT_X Register (Offset = 98h) [reset = 0h]
CAN_NDAT_X is shown in Figure 22-32 and described in Table 22-24.
Return to Summary Table.
With these bits, the CPU can detect if one or more bits in the CAN New Data 21 Register (CAN_NDAT
_21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of the NewDat
bits of these mailboxes are set, the corresponding bit in this register will be set.
Figure 22-32. CAN_NDAT_X Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

3

RESERVED
R-0h

NewDatReg2
R-0h

0
NewDatReg1
R-0h

Table 22-24. CAN_NDAT_X Register Field Descriptions
Field

Type

Reset

Description

31-4

Bit

RESERVED

R

0h

Reserved

3-2

NewDatReg2

R

0h

New Data Register 2 flag:
Bit 2 represents byte 2 of CAN_NDAT _21 Register. If one or more
bits in that byte are set, then bit 2 will be set.
Bit 3 represents byte 3 of CAN_NDAT _21 Register. If one or more
bits in that byte are set, then bit 3 will be set.
Reset type: SYSRSn

1-0

NewDatReg1

R

0h

New Data Register 1 flag:
Bit 0 represents byte 0 of CAN_NDAT _21 Register. If one or more
bits in that byte are set, then bit 0 will be set.
Bit 1 represents byte 1 of CAN_NDAT _21 Register. If one or more
bits in that byte are set, then bit 1 will be set.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2405

Registers

www.ti.com

22.15.2.16 CAN_NDAT_21 Register (Offset = 9Ch) [reset = 0h]
CAN_NDAT_21 is shown in Figure 22-33 and described in Table 22-25.
Return to Summary Table.
The bits in this register indicate if the message handler or the CPU has written new data into the data
portion of this mailbox.
Figure 22-33. CAN_NDAT_21 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NewDat
R-0h

9

8

7

6

5

4

3

2

1

0

Table 22-25. CAN_NDAT_21 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

NewDat

R

0h

New Data Bits (for all message objects)
0 No new data has been written into the data portion of this message
object by the message handler since the last time when this flag was
cleared by the CPU.
1 The message handler or the CPU has written new data into the
data portion of this message object.
Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox
3,..., Bit 31 is for mailbox 32
Reset type: SYSRSn

2406

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.17 CAN_IPEN_X Register (Offset = ACh) [reset = 0h]
CAN_IPEN_X is shown in Figure 22-34 and described in Table 22-26.
Return to Summary Table.
With these bits, the CPU can detect if one or more bits in the CAN Interrupt Pending 21 Register
(CAN_IPEN_21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of the
IntPnd bits of these mailboxes are set, the corresponding bit in this register will be set.
Figure 22-34. CAN_IPEN_X Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

3

RESERVED
R-0h

IntPndReg2
R-0h

0
IntPndReg1
R-0h

Table 22-26. CAN_IPEN_X Register Field Descriptions
Field

Type

Reset

Description

31-4

Bit

RESERVED

R

0h

Reserved

3-2

IntPndReg2

R

0h

Interrupt Pending Register 2 flag:
Bit 2 represents byte 2 of CAN_IPEN_21 Register. If one or more
bits in that byte are set, then bit 2 will be set.
Bit 3 represents byte 3 of CAN_IPEN_21 Register. If one or more
bits in that byte are set, then bit 3 will be set.
Reset type: SYSRSn

1-0

IntPndReg1

R

0h

Interrupt Pending Register 1 flag:
Bit 0 represents byte 0 of CAN_IPEN_21 Register. If one or more
bits in that byte are set, then bit 0 will be set.
Bit 1 represents byte 1 of CAN_IPEN_21 Register. If one or more
bits in that byte are set, then bit 1 will be set.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2407

Registers

www.ti.com

22.15.2.18 CAN_IPEN_21 Register (Offset = B0h) [reset = 0h]
CAN_IPEN_21 is shown in Figure 22-35 and described in Table 22-27.
Return to Summary Table.
The bits in this register indicate if an interrupt is pending for the corresponsding mailbox.
Figure 22-35. CAN_IPEN_21 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IntPnd
R-0h

9

8

7

6

5

4

3

2

1

0

Table 22-27. CAN_IPEN_21 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

IntPnd

R

0h

Interrupt Pending bits: This register contains the bits that indicate the
pending interrupts in each one of the 32 mailboxes.
0 This mailbox is not the source of an interrupt.
1 This mailbox is the source of an interrupt.
Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox
3,..., Bit 31 is for mailbox 32
Reset type: SYSRSn

2408

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.19 CAN_MVAL_X Register (Offset = C0h) [reset = 0h]
CAN_MVAL_X is shown in Figure 22-36 and described in Table 22-28.
Return to Summary Table.
With these bits, the CPU can detect if one or more bits in the CAN Message Valid 2_1 Register
(CAN_MVAL_21) is set.Each bit in this register represents a group of eight mailboxes. If at least one of
the MsgVal bits of these mailboxes are set, the corresponding bit in this register will be set.
Figure 22-36. CAN_MVAL_X Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

3

RESERVED
R-0h

MsgValReg2
R-0h

0
MsgValReg1
R-0h

Table 22-28. CAN_MVAL_X Register Field Descriptions
Field

Type

Reset

Description

31-4

Bit

RESERVED

R

0h

Reserved

3-2

MsgValReg2

R

0h

Message Valid Register 2 flag:
Bit 2 represents byte 2 of CAN_ MVAL _21 Register. If one or more
bits in that byte are set, then bit 2 will be set.
Bit 3 represents byte 3 of CAN_ MVAL _21 Register. If one or more
bits in that byte are set, then bit 3 will be set.
Reset type: SYSRSn

1-0

MsgValReg1

R

0h

Message Valid Register 1 flag:
Bit 0 represents byte 0 of CAN_ MVAL _21 Register. If one or more
bits in that byte are set, then bit 0 will be set.
Bit 1 represents byte 1 of CAN_ MVAL _21 Register. If one or more
bits in that byte are set, then bit 1 will be set.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2409

Registers

www.ti.com

22.15.2.20 CAN_MVAL_21 Register (Offset = C4h) [reset = 0h]
CAN_MVAL_21 is shown in Figure 22-37 and described in Table 22-29.
Return to Summary Table.
The bits in this register are used to enable/disable mailboxes as needed.
Figure 22-37. CAN_MVAL_21 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MsgValReg
R-0h

9

8

7

6

5

4

3

2

1

0

Table 22-29. CAN_MVAL_21 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

MsgValReg

R

0h

Message Valid Bits (for all message objects)
0 This message object is ignored by the message handler.
1 This message object is configured and will be considered by the
message handler.
Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox
3,..., Bit 31 is for mailbox 32
Reset type: SYSRSn

2410

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.21 CAN_IP_MUX21 Register (Offset = D8h) [reset = 0h]
CAN_IP_MUX21 is shown in Figure 22-38 and described in Table 22-30.
Return to Summary Table.
The IntMux bit determines for each mailbox, which of the two interrupt lines (CANINT0 or CANINT1) will
be asserted when the IntPnd bit of that mailbox is set. Both interrupt lines can be globally enabled or
disabled by setting or clearing IE0 and IE1 bits in CAN Control Register. The IntPnd bit of a specific
message object can be set or reset by the CPU via the IF1/IF2 Interface Register sets, or by the Message
Handler after reception or successful transmission of a frame. This will also affect the Int0ID or Int1ID flags
in the Interrupt Register.
Figure 22-38. CAN_IP_MUX21 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IntMux
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 22-30. CAN_IP_MUX21 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

IntMux

R/W

0h

Interrupt Mux bits:
0 CANINT0 line is active if corresponding IntPnd flag is one.
1 CANINT1 line is active if corresponding IntPnd flag is one.
Note: Bit 0 is for mailbox 32, Bit 1 is for mailbox 1, Bit 2 is for
mailbox 2,..., Bit 31 is for mailbox 31
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2411

Registers

www.ti.com

22.15.2.22 CAN_IF1CMD Register (Offset = 100h) [reset = 1h]
CAN_IF1CMD is shown in Figure 22-39 and described in Table 22-31.
Return to Summary Table.
The IF1/IF2 Command Registers configure and initiate the transfer between the IF1/IF2 Register sets and
the Message RAM. It is configurable which portions of the message object should be transferred. A
transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command
Register. With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in
progress. After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM
will be completed and the Busy bit is cleared. The maximum number of cycles is needed when the
message transfer coincides with a CAN message transmission, acceptance filtering, or message storage.
If the CPU writes to both IF1/IF2 Command Registers consecutively (request of a second transfer while
first transfer is still in progress), the second transfer will start after the first one has been completed.
Note: While Busy bit is one, IF1/IF2 Register sets are write protected.
Note: For debug support, the auto clear functionality of the IF1/IF2 Command Registers (clear of
DMAactive flag by R/W, for devices with DMA support) is disabled during Debug/Suspend mode.
Note: If an invalid Message Number is written to bits [7:0] of the IF1/IF2 Command Register, the Message
Handler may access an implemented (valid) message object instead.
Figure 22-39. CAN_IF1CMD Register
31

30

29

28

27

26

25

24

RESERVED
R-0h
23
DIR
R/W-0h

22
Mask
R/W-0h

21
Arb
R/W-0h

20
Control
R/W-0h

19
ClrIntPnd
R/W-0h

18
TXRQST
R/W-0h

17
DATA_A
R/W-0h

16
DATA_B
R/W-0h

15
Busy
R-0h

14

13

12

11

10

9

8

7

6

2

1

0

RESERVED
R-0h
5

4

3
MSG_NUM
R/W-1h

Table 22-31. CAN_IF1CMD Register Field Descriptions
Bit
31-24
23

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

DIR

R/W

0h

Write/Read
0 Direction = Read: Transfer direction is from the message object
addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register
set.
1 Direction = Write: Transfer direction is from the IF1/IF2 Register
set to the message object addressed by Message Number (Bits
[7:0])
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

2412

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-31. CAN_IF1CMD Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

22

Mask

R/W

0h

Access Mask Bits
0 Mask bits will not be changed
1 Direction = Read: The Mask bits (Identifier Mask + MDir + MXtd)
will be transferred from the message object addressed by Message
Number (Bits [7:0]) to the IF1/IF2 Register set.
Direction = Write: The Mask bits (Identifier Mask + MDir + MXtd) will
be transferred from theIF1/IF2 Register set to the message object
addressed by Message Number (Bits [7:0]).
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

21

Arb

R/W

0h

Access Arbitration Bits
0 Arbitration bits will not be changed
1 Direction = Read: The Arbitration bits (Identifier + Dir + Xtd +
MsgVal) will be transferred from the message object addressed by
Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register
set.
1 Direction = Write: The Arbitration bits (Identifier + Dir + Xtd +
MsgVal) will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

20

Control

R/W

0h

Access Control Bits
0 Control bits will not be changed
1 Direction = Read: The Message Control bits will be transferred
from the message object addressed by Message Number (Bits [7:0])
to the IF1/IF2 Register set.
Direction = Write: The Message Control bits will be transferred from
the IF1/IF2 Register set to the message object addressed by
Message Number (Bits [7:0]). If the TxRqst/NewDat bit in this
register (Bit [18]) is set, the TxRqst/ NewDat bit in the IF1/IF2
Message Control Register will be ignored.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

19

ClrIntPnd

R/W

0h

Clear Interrupt Pending Bit
0 IntPnd bit will not be changed
1 Direction = Read: Clears IntPnd bit in the message object.
1 Direction = Write: This bit is ignored. Copying of IntPnd flag from
IF1/IF2 registers to Message RAM can only be controlled by the
Control flag (Bit [20]).
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2413

Registers

www.ti.com

Table 22-31. CAN_IF1CMD Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

18

TXRQST

R/W

0h

Access Transmission Request Bit
0 Direction = Read: NewDat bit will not be changed.
0 Direction = Write: TxRqst/NewDat bit will be handled according to
the Control bit.
1 Direction = Read: Clears NewDat bit in the message object.
1 Direction = Write: Sets TxRqst/NewDat in message object.
Note: If a CAN transmission is requested by setting TxRqst/NewDat
in this register, the TxRqst/NewDat bits in the message object will be
set to one independent of the values in IF1/IF2 Message Control
Register.
Note: A read access to a message object can be combined with the
reset of the control bits IntPnd and NewDat. The values of these bits
transferred to the IF1/IF2 Message Control Register always reflect
the status before resetting them.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

17

DATA_A

R/W

0h

Access Data Bytes 0-3
0 Data Bytes 0-3 will not be changed.
1 Direction = Read: The Data Bytes 0-3 will be transferred from the
message object addressed by the Message Number (Bits [7:0]) to
the corresponding IF1/IF2 Register set.
1 Direction = Write: The Data Bytes 0-3 will be transferred from the
IF1/IF2 Register set to the message object addressed by the
Message Number (Bits [7:0]).
Note: The duration of the message transfer is independent of the
number of bytes to be transferred.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

16

DATA_B

R/W

0h

Access Data Bytes 4-7
0 Data Bytes 4-7 will not be changed.
1 Direction = Read: The Data Bytes 4-7 will be transferred from the
message object addressed by Message Number (Bits [7:0]) to the
corresponding IF1/IF2 Register set.
1 Direction = Write: The Data Bytes 4-7 will be transferred from the
IF1/IF2 Register set to the message object addressed by Message
Number (Bits [7:0]).
Note: The duration of the message transfer is independent of the
number of bytes to be transferred.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

15

Busy

R

0h

Busy Flag
0 No transfer between IF1/IF2 Register Set and Message RAM is in
progress.
1 Transfer between IF1/IF2 Register Set and Message RAM is in
progress.
This bit is set to one after the message number has been written to
bits [7:0]. IF1/IF2 Register Set will be write protected. The bit is
cleared after read/write action has been finished.
Reset type: SYSRSn

14
2414

RESERVED
Controller Area Network (CAN)

R

0h

Reserved
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-31. CAN_IF1CMD Register Field Descriptions (continued)
Field

Type

Reset

Description

13-8

Bit

RESERVED

R

0h

Reserved

7-0

MSG_NUM

R/W

1h

Number of message object in Message RAM which is used for data
transfer
0x00 Invalid message number
0x01-0x20 Valid message numbers
0x21-0xFF Invalid message numbers
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2415

Registers

www.ti.com

22.15.2.23 CAN_IF1MSK Register (Offset = 104h) [reset = FFFFFFFFh]
CAN_IF1MSK is shown in Figure 22-40 and described in Table 22-32.
Return to Summary Table.
The bits of the IF1/IF2 Mask Registers mirror the mask bits of a message object.
Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.
Figure 22-40. CAN_IF1MSK Register
31
MXtd
R/W-1h

30
MDir
R/W-1h

29
RESERVED
R-1h

28

23

22

21

15

14

7

6

27

26
Msk
R/W-1FFFFFFFh

25

24

20

18

17

16

13

12

10

9

8

5

4

2

1

0

19
Msk
R/W-1FFFFFFFh
11
Msk
R/W-1FFFFFFFh
3
Msk
R/W-1FFFFFFFh

Table 22-32. CAN_IF1MSK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MXtd

R/W

1h

Mask Extended Identifier
0 The extended identifier bit (IDE) has no effect on the acceptance
filtering.
1 The extended identifier bit (IDE) is used for acceptance filtering.
When 11-bit ("standard") identifiers are used for a message object,
the identifiers of received data frames are written into bits ID[28:18].
For acceptance filtering, only these bits together with mask bits
Msk[28:18] are considered.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

30

MDir

R/W

1h

Mask Message Direction
0 The message direction bit (Dir) has no effect on the acceptance
filtering.
1 The message direction bit (Dir) is used for acceptance filtering.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

29
28-0

RESERVED

R

1h

Msk

R/W

1FFFFFFFh Identifier Mask-

Reserved

0 The corresponding bit in the identifier of the message object is not
used for acceptance filtering (don't care).
1 The corresponding bit in the identifier of the message object is
used for acceptance filtering.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

2416

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.24 CAN_IF1ARB Register (Offset = 108h) [reset = 0h]
CAN_IF1ARB is shown in Figure 22-41 and described in Table 22-33.
Return to Summary Table.
The bits of the IF1/IF2 Arbitration Registers mirror the arbitration bits of a message object. The Arbitration
bits ID[28:0], Xtd, and Dir are used to define the identifier and type of outgoing messages and (together
with the Mask bits Msk[28:0], MXtd, and MDir) for acceptance filtering of incoming messages.
A received message is stored into the valid message object with matching identifier and Direction =
receive (Data Frame) or Direction = transmit (Remote Frame).
Extended frames can be stored only in message objects with Xtd = one, standard frames in message
objects with Xtd = zero.
If a received message (Data Frame or Remote Frame) matches more than one valid message objects, it
is stored into the one with the lowest message number.
Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.
Figure 22-41. CAN_IF1ARB Register
31
MsgVal
R/W-0h

30
Xtd
R/W-0h

29
Dir
R/W-0h

28

23

22

21

20

27

26
ID
R/W-0h

25

24

19

18

17

16

11

10

9

8

3

2

1

0

ID
R/W-0h
15

14

13

12
ID
R/W-0h

7

6

5

4
ID
R/W-0h

Table 22-33. CAN_IF1ARB Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MsgVal

R/W

0h

Message Valid
0 The mailbox is disabled. (The message object is ignored by the
message handler).
1 The mailbox is enabled. (The message object is to be used by the
message handler).
The CPU should reset the MsgVal bit of all unused Messages
Objects during the initialization before it resets the Init bit in the CAN
Control Register. This bit must also be reset before the identifier
ID[28:0], the control bits Xtd, Dir or DLC[3:0] are modified, or if the
messages object is no longer required.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

30

Xtd

R/W

0h

Extended Identifier
0 The 11-bit ("standard") Identifier is used for this message object.
1 The 29-bit ("extended") Identifier is used for this message object.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2417

Registers

www.ti.com

Table 22-33. CAN_IF1ARB Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

29

Dir

R/W

0h

Message Direction
0 Direction = receive: On TxRqst, a remote frame with the identifier
of this message object is transmitted. On reception of a data frame
with matching identifier, that message is stored in this message
object.
1 Direction = transmit: On TxRqst, the respective message object is
transmitted as a data frame. On reception of a remote frame with
matching identifier, the TxRqst bit of this message object is set (if
RmtEn = one).
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

28-0

ID

R/W

0h

Message Identifier
ID[28:0] 29-bit Identifier ("Extended Frame")
ID[28:18] 11-bit Identifier ("Standard Frame")
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

2418

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.25 CAN_IF1MCTL Register (Offset = 10Ch) [reset = 0h]
CAN_IF1MCTL is shown in Figure 22-42 and described in Table 22-34.
Return to Summary Table.
The bits of the IF1/IF2 Message Control Registers mirror the message control bits of a message object.
This register has control/status bits pertaining to interrupts, acceptance mask, remote frames and FIFO
option.
Figure 22-42. CAN_IF1MCTL Register
31

30

29

28

27

26

25

24

19

18

17

16

9
RmtEn
R/W-0h

8
TxRqst
R/W-0h

1

0

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
NewDat
R/W-0h

14
MsgLst
R/W-0h

13
IntPnd
R/W-0h

12
UMask
R/W-0h

11
TxIE
R/W-0h

10
RxIE
R/W-0h

7
EoB
R/W-0h

6

5
RESERVED
R-0h

4

3

2
DLC
R/W-0h

Table 22-34. CAN_IF1MCTL Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

NewDat

R/W

0h

New Data
0 No new data has been written into the data portion of this message
object by the message handler since the last time when this flag was
cleared by the CPU.
1 The message handler or the CPU has written new data into the
data portion of this message object.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

14

MsgLst

R/W

0h

Message Lost (only valid for message objects with direction =
receive)
0 No message lost since the last time when this bit was reset by the
CPU.
1 The message handler stored a new message into this object when
NewDat was still set, so the previous message has been overwritten.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

13

IntPnd

R/W

0h

Interrupt Pending
0 This message object is not the source of an interrupt.
1 This message object is the source of an interrupt. The Interrupt
Identifier in the Interrupt Register will point to this message object if
there is no other interrupt source with higher priority.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2419

Registers

www.ti.com

Table 22-34. CAN_IF1MCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

12

UMask

R/W

0h

Use Acceptance Mask
0 Mask ignored
1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering
If the UMask bit is set to one, the message object's mask bits have
to be programmed during initialization of the message object before
MsgVal is set to one.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

11

TxIE

R/W

0h

Transmit Interrupt Enable
0 IntPnd will not be triggered after the successful transmission of a
frame.
1 IntPnd will be triggered after the successful transmission of a
frame.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

10

RxIE

R/W

0h

Receive Interrupt Enable
0 IntPnd will not be triggered after the successful reception of a
frame.
1 IntPnd will be triggered after the successful reception of a frame.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

9

RmtEn

R/W

0h

Remote Enable
0 At the reception of a remote frame, TxRqst is not changed.
1 At the reception of a remote frame, TxRqst is set.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

8

TxRqst

R/W

0h

Transmit Request
0 This message object is not waiting for a transmission.
1 The transmission of this message object is requested and is not
yet done.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

7

EoB

R/W

0h

End of Block
0 The message object is part of a FIFO Buffer block and is not the
last message object of the FIFO Buffer block.
1 The message object is a single message object or the last
message object in a FIFO Buffer Block.
Note: This bit is used to concatenate multiple message objects to
build a FIFO Buffer. For single message objects (not belonging to a
FIFO Buffer), this bit must always be set to one.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

6-4

2420

RESERVED

Controller Area Network (CAN)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-34. CAN_IF1MCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

DLC

R/W

0h

Data length code
0-8 Data frame has 0-8 data bytes.
9-15 Data frame has 8 data bytes.
Note: The data length code of a message object must be defined the
same as in all the corresponding objects with the same identifier at
other nodes. When the message handler stores a data frame, it will
write the DLC to the value given by the received message.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2421

Registers

www.ti.com

22.15.2.26 CAN_IF1DATA Register (Offset = 110h) [reset = 0h]
CAN_IF1DATA is shown in Figure 22-43 and described in Table 22-35.
Return to Summary Table.
This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages
are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and
Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will
be transmitted first. All bits in this register are write-protected by the Busy bit.
Figure 22-43. CAN_IF1DATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data_3
Data_2
Data_1
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5

4 3 2
Data_0
R/W-0h

1

0

Table 22-35. CAN_IF1DATA Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

Data_3

R/W

0h

Data Byte 3
Reset type: SYSRSn

23-16

Data_2

R/W

0h

Data Byte 2
Reset type: SYSRSn

15-8

Data_1

R/W

0h

Data Byte 1
Reset type: SYSRSn

7-0

Data_0

R/W

0h

Data Byte 0
Reset type: SYSRSn

2422

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.27 CAN_IF1DATB Register (Offset = 114h) [reset = 0h]
CAN_IF1DATB is shown in Figure 22-44 and described in Table 22-36.
Return to Summary Table.
This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages
are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and
Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will
be transmitted first. All bits in this register are write-protected by the Busy bit.
Figure 22-44. CAN_IF1DATB Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data_7
Data_6
Data_5
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5

4 3 2
Data_4
R/W-0h

1

0

Table 22-36. CAN_IF1DATB Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

Data_7

R/W

0h

Data Byte 7
Reset type: SYSRSn

23-16

Data_6

R/W

0h

Data Byte 6
Reset type: SYSRSn

15-8

Data_5

R/W

0h

Data Byte 5
Reset type: SYSRSn

7-0

Data_4

R/W

0h

Data Byte 4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2423

Registers

www.ti.com

22.15.2.28 CAN_IF2CMD Register (Offset = 120h) [reset = 1h]
CAN_IF2CMD is shown in Figure 22-45 and described in Table 22-37.
Return to Summary Table.
The IF1/IF2 Command Registers configure and initiate the transfer between the IF1/IF2 Register sets and
the Message RAM. It is configurable which portions of the message object should be transferred. A
transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command
Register. With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in
progress. After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM
will be completed and the Busy bit is cleared. The maximum number of cycles is needed when the
message transfer coincides with a CAN message transmission, acceptance filtering, or message storage.
If the CPU writes to both IF1/IF2 Command Registers consecutively (request of a second transfer while
first transfer is still in progress), the second transfer will start after the first one has been completed.
Note: While Busy bit is one, IF1/IF2 Register sets are write protected.
Note: For debug support, the auto clear functionality of the IF1/IF2 Command Registers (clear of
DMAactive flag by R/W, for devices with DMA support) is disabled during Debug/Suspend mode.
Note: If an invalid Message Number is written to bits [7:0] of the IF1/IF2 Command Register, the Message
Handler may access an implemented (valid) message object instead.
Figure 22-45. CAN_IF2CMD Register
31

30

29

28

27

26

25

24

RESERVED
R-0h
23
DIR
R/W-0h

22
Mask
R/W-0h

21
Arb
R/W-0h

20
Control
R/W-0h

19
ClrIntPnd
R/W-0h

18
TxRqst
R/W-0h

17
DATA_A
R/W-0h

16
DATA_B
R/W-0h

15
Busy
R-0h

14

13

12

11

10

9

8

7

6

2

1

0

RESERVED
R-0h
5

4

3
MSG_NUM
R/W-1h

Table 22-37. CAN_IF2CMD Register Field Descriptions
Bit
31-24
23

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

DIR

R/W

0h

Write/Read
0 Direction = Read: Transfer direction is from the message object
addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register
set.
1 Direction = Write: Transfer direction is from the IF1/IF2 Register
set to the message object addressed by Message Number (Bits
[7:0])
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

2424

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-37. CAN_IF2CMD Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

22

Mask

R/W

0h

Access Mask Bits
0 Mask bits will not be changed
1 Direction = Read: The Mask bits (Identifier Mask + MDir + MXtd)
will be transferred from the message object addressed by Message
Number (Bits [7:0]) to the IF1/IF2 Register set.
1 Direction = Write: The Mask bits (Identifier Mask + MDir + MXtd)
will be transferred from theIF1/IF2 Register set to the message
object addressed by Message Number (Bits [7:0]).
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

21

Arb

R/W

0h

Access Arbitration Bits
0 Arbitration bits will not be changed
1 Direction = Read: The Arbitration bits (Identifier + Dir + Xtd +
MsgVal) will be transferred from the message object addressed by
Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register
set.
1 Direction = Write: The Arbitration bits (Identifier + Dir + Xtd +
MsgVal) will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

20

Control

R/W

0h

Access Control Bits
0 Control bits will not be changed
1 Direction = Read: The Message Control bits will be transferred
from the message object addressed by Message Number (Bits [7:0])
to the IF1/IF2 Register set.
1 Direction = Write: The Message Control bits will be transferred
from the IF1/IF2 Register set to the message object addressed by
Message Number (Bits [7:0]). If the TxRqst/NewDat bit in this
register (Bit [18]) is set, the TxRqst/ NewDat bit in the IF1/IF2
Message Control Register will be ignored.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

19

ClrIntPnd

R/W

0h

Clear Interrupt Pending Bit
0 IntPnd bit will not be changed
1 Direction = Read: Clears IntPnd bit in the message object.
1 Direction = Write: This bit is ignored. Copying of IntPnd flag from
IF1/IF2 registers to Message RAM can only be controlled by the
Control flag (Bit [20]).
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2425

Registers

www.ti.com

Table 22-37. CAN_IF2CMD Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

18

TxRqst

R/W

0h

Access Transmission Request Bit
0 Direction = Read: NewDat bit will not be changed.
0 Direction = Write: TxRqst/NewDat bit will be handled according to
the Control bit.
1 Direction = Read: Clears NewDat bit in the message object.
1 Direction = Write: Sets TxRqst/NewDat in message object.
Note: If a CAN transmission is requested by setting TxRqst/NewDat
in this register, the TxRqst/NewDat bits in the message object will be
set to one independent of the values in IF1/IF2 Message Control
Register.
Note: A read access to a message object can be combined with the
reset of the control bits IntPnd and NewDat. The values of these bits
transferred to the IF1/IF2 Message Control Register always reflect
the status before resetting them.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

17

DATA_A

R/W

0h

Access Data Bytes 0-3
0 Data Bytes 0-3 will not be changed.
1 Direction = Read: The Data Bytes 0-3 will be transferred from the
message object addressed by the Message Number (Bits [7:0]) to
the corresponding IF1/IF2 Register set.
1 Direction = Write: The Data Bytes 0-3 will be transferred from the
IF1/IF2 Register set to the message object addressed by the
Message Number (Bits [7:0]).
Note: The duration of the message transfer is independent of the
number of bytes to be transferred.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

16

DATA_B

R/W

0h

Access Data Bytes 4-7
0 Data Bytes 4-7 will not be changed.
1 Direction = Read: The Data Bytes 4-7 will be transferred from the
message object addressed by Message Number (Bits [7:0]) to the
corresponding IF1/IF2 Register set.
1 Direction = Write: The Data Bytes 4-7 will be transferred from the
IF1/IF2 Register set to the message object addressed by Message
Number (Bits [7:0]).
Note: The duration of the message transfer is independent of the
number of bytes to be transferred.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

15

Busy

R

0h

Busy Flag
0 No transfer between IF1/IF2 Register Set and Message RAM is in
progress.
1 Transfer between IF1/IF2 Register Set and Message RAM is in
progress.
This bit is set to one after the message number has been written to
bits [7:0]. IF1/IF2 Register Set will be write protected. The bit is
cleared after read/write action has been finished.
Reset type: SYSRSn

14
2426

RESERVED
Controller Area Network (CAN)

R

0h

Reserved
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-37. CAN_IF2CMD Register Field Descriptions (continued)
Field

Type

Reset

Description

13-8

Bit

RESERVED

R

0h

Reserved

7-0

MSG_NUM

R/W

1h

Number of message object in Message RAM which is used for data
transfer
0x00 Invalid message number
0x01-0x20 Valid message numbers
0x21-0xFF Invalid message numbers
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2427

Registers

www.ti.com

22.15.2.29 CAN_IF2MSK Register (Offset = 124h) [reset = FFFFFFFFh]
CAN_IF2MSK is shown in Figure 22-46 and described in Table 22-38.
Return to Summary Table.
The bits of the IF1/IF2 Mask Registers mirror the mask bits of a message object.
Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.
Figure 22-46. CAN_IF2MSK Register
31
MXtd
R/W-1h

30
MDir
R/W-1h

29
RESERVED
R-1h

28

23

22

21

15

14

7

6

27

26
Msk
R/W-1FFFFFFFh

25

24

20

18

17

16

13

12

10

9

8

5

4

2

1

0

19
Msk
R/W-1FFFFFFFh
11
Msk
R/W-1FFFFFFFh
3
Msk
R/W-1FFFFFFFh

Table 22-38. CAN_IF2MSK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MXtd

R/W

1h

Mask Extended Identifier
0 The extended identifier bit (IDE) has no effect on the acceptance
filtering.
1 The extended identifier bit (IDE) is used for acceptance filtering.
When 11-bit ("standard") identifiers are used for a message object,
the identifiers of received data frames are written into bits ID[28:18].
For acceptance filtering, only these bits together with mask bits
Msk[28:18] are considered.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

30

MDir

R/W

1h

Mask Message Direction
0 The message direction bit (Dir) has no effect on the acceptance
filtering.
1 The message direction bit (Dir) is used for acceptance filtering.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

29
28-0

RESERVED

R

1h

Msk

R/W

1FFFFFFFh Identifier Mask

Reserved

0 The corresponding bit in the identifier of the message object is not
used for acceptance filtering (don't care).
1 The corresponding bit in the identifier of the message object is
used for acceptance filtering.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

2428

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.30 CAN_IF2ARB Register (Offset = 128h) [reset = 0h]
CAN_IF2ARB is shown in Figure 22-47 and described in Table 22-39.
Return to Summary Table.
The bits of the IF1/IF2 Arbitration Registers mirror the arbitration bits of a message object. The Arbitration
bits ID[28:0], Xtd, and Dir are used to define the identifier and type of outgoing messages and (together
with the Mask bits Msk[28:0], MXtd, and MDir) for acceptance filtering of incoming messages.
A received message is stored into the valid message object with matching identifier and Direction =
receive (Data Frame) or Direction = transmit (Remote Frame).
Extended frames can be stored only in message objects with Xtd = one, standard frames in message
objects with Xtd = zero.
If a received message (Data Frame or Remote Frame) matches more than one valid message objects, it
is stored into the one with the lowest message number.
Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.
Figure 22-47. CAN_IF2ARB Register
31
MsgVal
R/W-0h

30
Xtd
R/W-0h

29
Dir
R/W-0h

28

23

22

21

20

27

26
ID
R/W-0h

25

24

19

18

17

16

11

10

9

8

3

2

1

0

ID
R/W-0h
15

14

13

12
ID
R/W-0h

7

6

5

4
ID
R/W-0h

Table 22-39. CAN_IF2ARB Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MsgVal

R/W

0h

Message Valid
0 The mailbox is disabled. (The message object is ignored by the
message handler).
1 The mailbox is enabled. (The message object is to be used by the
message handler).
The CPU should reset the MsgVal bit of all unused Messages
Objects during the initialization before it resets the Init bit in the CAN
Control Register. This bit must also be reset before the identifier
ID[28:0], the control bits Xtd, Dir or DLC[3:0] are modified, or if the
messages object is no longer required.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

30

Xtd

R/W

0h

Extended Identifier
0 The 11-bit ("standard") Identifier is used for this message object.
1 The 29-bit ("extended") Identifier is used for this message object.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2429

Registers

www.ti.com

Table 22-39. CAN_IF2ARB Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

29

Dir

R/W

0h

Message Direction
0 Direction = receive: On TxRqst, a remote frame with the identifier
of this message object is transmitted. On reception of a data frame
with matching identifier, that message is stored in this message
object.
1 Direction = transmit: On TxRqst, the respective message object is
transmitted as a data frame. On reception of a remote frame with
matching identifier, the TxRqst bit of this message object is set (if
RmtEn = one).
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

28-0

ID

R/W

0h

Message Identifier
ID[28:0] 29-bit Identifier ("Extended Frame")
ID[28:18] 11-bit Identifier ("Standard Frame")
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

2430

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.31 CAN_IF2MCTL Register (Offset = 12Ch) [reset = 0h]
CAN_IF2MCTL is shown in Figure 22-48 and described in Table 22-40.
Return to Summary Table.
The bits of the IF1/IF2 Message Control Registers mirror the message control bits of a message object.
This register has control/status bits pertaining to interrupts, acceptance mask, remote frames and FIFO
option.
Figure 22-48. CAN_IF2MCTL Register
31

30

29

28

27

26

25

24

19

18

17

16

9
RmtEn
R/W-0h

8
TxRqst
R/W-0h

1

0

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
NewDat
R/W-0h

14
MsgLst
R/W-0h

13
IntPnd
R/W-0h

12
UMask
R/W-0h

11
TxIE
R/W-0h

10
RxIE
R/W-0h

7
EoB
R/W-0h

6

5
RESERVED
R-0h

4

3

2
DLC
R/W-0h

Table 22-40. CAN_IF2MCTL Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

NewDat

R/W

0h

New Data
0 No new data has been written into the data portion of this message
object by the message handler since the last time when this flag was
cleared by the CPU.
1 The message handler or the CPU has written new data into the
data portion of this message object.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

14

MsgLst

R/W

0h

Message Lost (only valid for message objects with direction =
receive)
0 No message lost since the last time when this bit was reset by the
CPU.
1 The message handler stored a new message into this object when
NewDat was still set, so the previous message has been overwritten.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

13

IntPnd

R/W

0h

Interrupt Pending
0 This message object is not the source of an interrupt.
1 This message object is the source of an interrupt. The Interrupt
Identifier in the Interrupt Register will point to this message object if
there is no other interrupt source with higher priority.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2431

Registers

www.ti.com

Table 22-40. CAN_IF2MCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

12

UMask

R/W

0h

Use Acceptance Mask
0 Mask ignored
1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering
If the UMask bit is set to one, the message object's mask bits have
to be programmed during initialization of the message object before
MsgVal is set to one.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

11

TxIE

R/W

0h

Transmit Interrupt Enable
0 IntPnd will not be triggered after the successful transmission of a
frame.
1 IntPnd will be triggered after the successful transmission of a
frame.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

10

RxIE

R/W

0h

Receive Interrupt Enable
0 IntPnd will not be triggered after the successful reception of a
frame.
1 IntPnd will be triggered after the successful reception of a frame.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

9

RmtEn

R/W

0h

Remote Enable
0 At the reception of a remote frame, TxRqst is not changed.
1 At the reception of a remote frame, TxRqst is set.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

8

TxRqst

R/W

0h

Transmit Request
0 This message object is not waiting for a transmission.
1 The transmission of this message object is requested and is not
yet done.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

7

EoB

R/W

0h

End of Block
0 The message object is part of a FIFO Buffer block and is not the
last message object of the FIFO Buffer block.
1 The message object is a single message object or the last
message object in a FIFO Buffer Block.
Note: This bit is used to concatenate multiple message objects to
build a FIFO Buffer. For single message objects (not belonging to a
FIFO Buffer), this bit must always be set to one.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

6-4

2432

RESERVED

Controller Area Network (CAN)

R

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-40. CAN_IF2MCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

DLC

R/W

0h

Data length code
0-8 Data frame has 0-8 data bytes.
9-15 Data frame has 8 data bytes.
Note: The data length code of a message object must be defined the
same as in all the corresponding objects with the same identifier at
other nodes. When the message handler stores a data frame, it will
write the DLC to the value given by the received message.
Note: This bit is write protected by Busy bit.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2433

Registers

www.ti.com

22.15.2.32 CAN_IF2DATA Register (Offset = 130h) [reset = 0h]
CAN_IF2DATA is shown in Figure 22-49 and described in Table 22-41.
Return to Summary Table.
This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages
are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and
Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will
be transmitted first. All bits in this register are write-protected by the Busy bit.
Figure 22-49. CAN_IF2DATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data_3
Data_2
Data_1
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5

4 3 2
Data_0
R/W-0h

1

0

Table 22-41. CAN_IF2DATA Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

Data_3

R/W

0h

Data Byte 3
Reset type: SYSRSn

23-16

Data_2

R/W

0h

Data Byte 2
Reset type: SYSRSn

15-8

Data_1

R/W

0h

Data Byte 1
Reset type: SYSRSn

7-0

Data_0

R/W

0h

Data Byte 0
Reset type: SYSRSn

2434

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.33 CAN_IF2DATB Register (Offset = 134h) [reset = 0h]
CAN_IF2DATB is shown in Figure 22-50 and described in Table 22-42.
Return to Summary Table.
This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages
are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and
Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will
be transmitted first. All bits in this register are write-protected by the Busy bit.
Figure 22-50. CAN_IF2DATB Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data_7
Data_6
Data_5
R/W-0h
R/W-0h
R/W-0h

9

8

7

6

5

4 3 2
Data_4
R/W-0h

1

0

Table 22-42. CAN_IF2DATB Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

Data_7

R/W

0h

Data Byte 7
Reset type: SYSRSn

23-16

Data_6

R/W

0h

Data Byte 6
Reset type: SYSRSn

15-8

Data_5

R/W

0h

Data Byte 5
Reset type: SYSRSn

7-0

Data_4

R/W

0h

Data Byte 4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2435

Registers

www.ti.com

22.15.2.34 CAN_IF3OBS Register (Offset = 140h) [reset = 0h]
CAN_IF3OBS is shown in Figure 22-51 and described in Table 22-43.
Return to Summary Table.
The IF3 register set can automatically be updated with received message objects without the need to
initiate the transfer from Message RAM by CPU.
The observation flags (Bits [4:0]) in the IF3 Observation register are used to determine, which data
sections of the IF3 Interface Register set have to be read in order to complete a DMA read cycle. After all
marked data sections are read, the DCAN is enabled to update the IF3 Interface Register set with new
data.
Any access order of single bytes or half-words is supported. When using byte or half-word accesses, a
data section is marked as completed, if all bytes are read.
Note: If IF3 Update Enable is used and no Observation flag is set, the corresponding message objects will
be copied to IF3 without activating the DMA request line and without waiting for DMA read accesses.
A write access to this register aborts a pending DMA cycle by resetting the DMA line and enables
updating of IF3 Interface Register set with new data. To avoid data inconsistency, the DMA controller
should be disabled before reconfiguring IF3 observation register. The status of the current read-cycle can
be observed via status flags (Bits [12:8]).
With this, the observation status bits and the IF3Upd bit could be used by the application to realize the
notification about new IF3 content in polling or interrupt mode
Figure 22-51. CAN_IF3OBS Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
IF3Upd
R-0h

14

7

6
RESERVED
R-0h

13

12
IF3SDB
R-0h

11
IF3SDA
R-0h

10
IF3SC
R-0h

9
IF3SA
R-0h

8
IF3SM
R-0h

5

4
Data_B
R/W-0h

3
Data_A
R/W-0h

2
Ctrl
R/W-0h

1
Arb
R/W-0h

0
Mask
R/W-0h

RESERVED
R-0h

Table 22-43. CAN_IF3OBS Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

IF3Upd

R

0h

IF3 Update Data
0 No new data has been loaded since last IF3 read.
1 New data has been loaded since last IF3 read.
Reset type: SYSRSn

14-13
12

RESERVED

R

0h

Reserved

IF3SDB

R

0h

IF3 Status of Data B read access
0 All Data B bytes are already read out, or are not marked to be
read.
1 Data B section has still data to be read out.
Reset type: SYSRSn

2436

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-43. CAN_IF3OBS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

IF3SDA

R

0h

IF3 Status of Data A read access
0 All Data A bytes are already read out, or are not marked to be
read.
1 Data A section has still data to be read out.
Reset type: SYSRSn

10

IF3SC

R

0h

IF3 Status of Control bits read access
0 All Control section bytes are already read out, or are not marked to
be read.
1 Control section has still data to be read out.
Reset type: SYSRSn

9

IF3SA

R

0h

IF3 Status of Arbitration data read access
0 All Arbitration data bytes are already read out, or are not marked to
be read.
1 Arbitration section has still data to be read out.
Reset type: SYSRSn

8

IF3SM

R

0h

IF3 Status of Mask data read access
0 All Mask data bytes are already read out, or are not marked to be
read.
1 Mask section has still data to be read out.
Reset type: SYSRSn

7-5
4

RESERVED

R

0h

Reserved

Data_B

R/W

0h

Data B read observation
0 Data B section not to be read.
1 Data B section has to be read to enable next IF3 update.
Reset type: SYSRSn

3

Data_A

R/W

0h

Data A read observation
0 Data A section not to be read.
1 Data A section has to be read to enable next IF3 update.
Reset type: SYSRSn

2

Ctrl

R/W

0h

Ctrl read observation
0 Ctrl section not to be read.
1 Ctrl section has to be read to enable next IF3 update.
Reset type: SYSRSn

1

Arb

R/W

0h

Arbitration data read observation
0 Arbitration data not to be read.
1 Arbitration data has to be read to enable next IF3 update.
Reset type: SYSRSn

0

Mask

R/W

0h

Mask data read observation
0 Mask data not to be read.
1 Mask data has to be read to enable next IF3 update.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2437

Registers

www.ti.com

22.15.2.35 CAN_IF3MSK Register (Offset = 144h) [reset = FFFFFFFFh]
CAN_IF3MSK is shown in Figure 22-52 and described in Table 22-44.
Return to Summary Table.
This register provides a window to the acceptance mask for the chosen mailbox.
Figure 22-52. CAN_IF3MSK Register
31
MXtd
R-1h

30
MDir
R-1h

29
RESERVED
R-1h

28

23

22

21

20

27

26
Msk
R-1FFFFFFFh

25

24

19

18

17

16

11

10

9

8

3

2

1

0

Msk
R-1FFFFFFFh
15

14

13

12
Msk
R-1FFFFFFFh

7

6

5

4
Msk
R-1FFFFFFFh

Table 22-44. CAN_IF3MSK Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MXtd

R

1h

Mask Extended Identifier
0 The extended identifier bit (IDE) has no effect on the acceptance
filtering.
1 The extended identifier bit (IDE) is used for acceptance filtering.
Note: When 11-bit ("standard") identifiers are used for a message
object, the identifiers of received data frames are written into bits
ID[28:18]. For acceptance filtering, only these bits together with
mask bits Msk[28:18] are considered.
Reset type: SYSRSn

30

MDir

R

1h

Mask Message Direction
0 The message direction bit (Dir) has no effect on the acceptance
filtering.
1 The message direction bit (Dir) is used for acceptance filtering.
Reset type: SYSRSn

29
28-0

RESERVED

R

1h

Msk

R

1FFFFFFFh Identifier Mask Identifier Mask

Reserved

0 The corresponding bit in the identifier of the message object is not
used for acceptance filtering (don't care).
1 The corresponding bit in the identifier of the message object is
used for acceptance filtering. Identifier Mask
Reset type: SYSRSn

2438

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.36 CAN_IF3ARB Register (Offset = 148h) [reset = 0h]
CAN_IF3ARB is shown in Figure 22-53 and described in Table 22-45.
Return to Summary Table.
The bits of the IF3 Arbitration Register mirrors the arbitration bits of a message object.
Figure 22-53. CAN_IF3ARB Register
31
MsgVal
R-0h

30
Xtd
R-0h

29
Dir
R-0h

28

23

22

21

20

27

26
ID
R-0h

25

24

19

18

17

16

11

10

9

8

3

2

1

0

ID
R-0h
15

14

13

12
ID
R-0h

7

6

5

4
ID
R-0h

Table 22-45. CAN_IF3ARB Register Field Descriptions
Bit

Field

Type

Reset

Description

31

MsgVal

R

0h

Message Valid
0 The message object is ignored by the message handler.
1 The message object is to be used by the message handler.
The CPU should reset the MsgVal bit of all unused Messages
Objects during the initialization before it resets bit Init in the CAN
Control Register. This bit must also be reset before the identifier
ID[28:0], the control bits Xtd, Dir or DLC[3:0] are modified, or if the
messages object is no longer required.
Reset type: SYSRSn

30

Xtd

R

0h

Extended Identifier
0 The 11-bit ("standard") Identifier is used for this message object.
1 The 29-bit ("extended") Identifier is used for this message object.
Reset type: SYSRSn

29

Dir

R

0h

Message Direction
0 Direction = receive: On TxRqst, a remote frame with the identifier
of this message object is transmitted. On reception of a data frame
with matching identifier, that message is stored in this message
object.
1 Direction = transmit: On TxRqst, the respective message object is
transmitted as a data frame. On reception of a remote frame with
matching identifier, the TxRqst bit of this message object is set (if
RmtEn = one).
Reset type: SYSRSn

28-0

ID

R

0h

Message Identifier
ID[28:0] 29-bit Identifier ("Extended Frame")
ID[28:18] 11-bit Identifier ("Standard Frame")
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2439

Registers

www.ti.com

22.15.2.37 CAN_IF3MCTL Register (Offset = 14Ch) [reset = 0h]
CAN_IF3MCTL is shown in Figure 22-54 and described in Table 22-46.
Return to Summary Table.
The bits of the IF3 Message Control Register mirrors the message control bits of a message object.
Figure 22-54. CAN_IF3MCTL Register
31

30

29

28

27

26

25

24

19

18

17

16

9
RmtEn
R-0h

8
TxRqst
R-0h

1

0

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15
NewDat
R-0h

14
MsgLst
R-0h

13
IntPnd
R-0h

12
UMask
R-0h

11
TxIE
R-0h

10
RxIE
R-0h

7
EoB
R-0h

6

5
RESERVED
R-0h

4

3

2
DLC
R-0h

Table 22-46. CAN_IF3MCTL Register Field Descriptions
Bit
31-16
15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

NewDat

R

0h

New Data
0 No new data has been written into the data portion of this message
object by the message handler since the last time when this flag was
cleared by the CPU.
1 The message handler or the CPU has written new data into the
data portion of this message object.
Reset type: SYSRSn

14

MsgLst

R

0h

Message Lost (only valid for message objects with direction =
receive)
0 No message lost since the last time when this bit was reset by the
CPU.
1 The message handler stored a new message into this object when
NewDat was still set, so the previous message has been overwritten.
Reset type: SYSRSn

13

IntPnd

R

0h

Interrupt Pending
0 This message object is not the source of an interrupt.
1 This message object is the source of an interrupt. The Interrupt
Identifier in the Interrupt Register will point to this message object if
there is no other interrupt source with higher priority.
Reset type: SYSRSn

12

UMask

R

0h

Use Acceptance Mask
0 Mask ignored
1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering
If the UMask bit is set to one, the message object's mask bits have
to be programmed during initialization of the message object before
MsgVal is set to one.
Reset type: SYSRSn

2440

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 22-46. CAN_IF3MCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

11

TxIE

R

0h

Transmit Interrupt Enable
0 IntPnd will not be triggered after the successful transmission of a
frame.
1 IntPnd will be triggered after the successful transmission of a
frame.
Reset type: SYSRSn

10

RxIE

R

0h

Receive Interrupt Enable
0 IntPnd will not be triggered after the successful reception of a
frame.
1 IntPnd will be triggered after the successful reception of a frame.
Reset type: SYSRSn

9

RmtEn

R

0h

Remote Enable
0 At the reception of a remote frame, TxRqst is not changed.
1 At the reception of a remote frame, TxRqst is set.
Reset type: SYSRSn

8

TxRqst

R

0h

Transmit Request
0 This message object is not waiting for a transmission.
1 The transmission of this message object is requested and is not
yet done.
Reset type: SYSRSn

7

EoB

R

0h

End of Block
0 The message object is part of a FIFO Buffer block and is not the
last message object of the FIFO Buffer block.
1 The message object is a single message object or the last
message object in a FIFO Buffer Block.
Note: This bit is used to concatenate multiple message objects to
build a FIFO Buffer. For single message objects (not belonging to a
FIFO Buffer), this bit must always be set to one.
Reset type: SYSRSn

6-4

RESERVED

R

0h

Reserved

3-0

DLC

R

0h

Data length code
0-8 Data frame has 0-8 data bytes.
9-15 Data frame has 8 data bytes.
Note: The data length code of a message object must be defined the
same as in all the corresponding objects with the same identifier at
other nodes. When the message handler stores a data frame, it will
write the DLC to the value given by the received message.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2441

Registers

www.ti.com

22.15.2.38 CAN_IF3DATA Register (Offset = 150h) [reset = 0h]
CAN_IF3DATA is shown in Figure 22-55 and described in Table 22-47.
Return to Summary Table.
This register provides a window to the data bytes of the CAN message.
Figure 22-55. CAN_IF3DATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data_3
Data_2
Data_1
R-0h
R-0h
R-0h

9

8

7

6

5

4 3
Data_0
R-0h

2

1

0

Table 22-47. CAN_IF3DATA Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

Data_3

R

0h

Data Byte 3
Reset type: SYSRSn

23-16

Data_2

R

0h

Data Byte 2
Reset type: SYSRSn

15-8

Data_1

R

0h

Data Byte 1
Reset type: SYSRSn

7-0

Data_0

R

0h

Data Byte 0
Reset type: SYSRSn

2442

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

22.15.2.39 CAN_IF3DATB Register (Offset = 154h) [reset = 0h]
CAN_IF3DATB is shown in Figure 22-56 and described in Table 22-48.
Return to Summary Table.
This register provides a window to the data bytes of the CAN message.
Figure 22-56. CAN_IF3DATB Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data_7
Data_6
Data_5
R-0h
R-0h
R-0h

9

8

7

6

5

4 3
Data_4
R-0h

2

1

0

Table 22-48. CAN_IF3DATB Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

Data_7

R

0h

Data Byte 7
Reset type: SYSRSn

23-16

Data_6

R

0h

Data Byte 6
Reset type: SYSRSn

15-8

Data_5

R

0h

Data Byte 5
Reset type: SYSRSn

7-0

Data_4

R

0h

Data Byte 4
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Controller Area Network (CAN)

2443

Registers

www.ti.com

22.15.2.40 CAN_IF3UPD Register (Offset = 160h) [reset = 0h]
CAN_IF3UPD is shown in Figure 22-57 and described in Table 22-49.
Return to Summary Table.
The automatic update functionality of the IF3 register set can be configured for each message object. A
message object is enabled for automatic IF3 update, if the dedicated IF3UpdEn flag is set. This means
that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an
automatic copy of the whole message object to IF3 register set. Note: IF3 Update enable should not be
set for transmit objects.
Figure 22-57. CAN_IF3UPD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IF3UpdEn
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 22-49. CAN_IF3UPD Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

IF3UpdEn

R/W

0h

IF3 Update Enabled (for all message objects)
0 Automatic IF3 update is disabled for this message object.
1 Automatic IF3 update is enabled for this message object. A
message object is scheduled to be copied to IF3 register set, if
NewDat flag of the message object is active.
Reset type: SYSRSn

2444

Controller Area Network (CAN)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 23
SPRUHM8G – December 2013 – Revised September 2017

Universal Serial Bus (USB) Controller
This chapter discusses the features and functions of the universal serial bus (USB) controller.
Topic

23.1
23.2
23.3
23.4
23.5
23.6

...........................................................................................................................
Introduction ...................................................................................................
Features ........................................................................................................
Functional Description ....................................................................................
Initialization and Configuration .........................................................................
Register Map ..................................................................................................
Register Descriptions ......................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

2446
2446
2448
2457
2458
2473

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

Page

2445

Introduction

www.ti.com

23.1 Introduction
The USB controller operates as a full-speed function controller during point-to-point communications with
the USB host. The controller complies with the USB 2.0 standard, which includes SUSPEND and
RESUME signaling. It has thirty-two endpoints, sixteen for IN transactions and sixteen for OUT
transactions. One IN and one OUT endpoint are fixed-function endpoints used for control transfers; the
others are defined by firmware. A dynamically sizeable FIFO supports queuing multiple packets. Softwarecontrolled connect and disconnect allow flexibility during USB device startup.

23.2 Features
The USB module has the following features:
• Complies with USB-IF certification standards
• USB 2.0 full-speed (12 Mbps) operation in host and device modes as well as low-speed (1.5 Mbps)
operation in host mode
• Integrated PHY
• Three transfer types: Control, Interrupt, and Bulk
• Thirty-two endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– Fifteen configurable IN endpoints and fifteen configurable OUT endpoints
• Four KB dedicated endpoint memory

23.2.1 Block Diagram
The USB block diagram is shown in Figure 23-1.
Figure 23-1. USB Block Diagram
Endpoint Control
Transmit
EP0 –31
Control
Receive
CPU Interface
Combine
Endpoints

Host
Transaction
Scheduler

Interrupt
Control

Interrupts

EP Reg.
Decoder

USB PHY

USB FS/LS
PHY

UTM
Synchronization

Packet
Encode/Decode

Data Sync

Packet Encode

HNP/SRP

Packet Decode

Timers

CRC Gen/Check

FIFO RAM
Controller
Rx
Rx
Buff
Buff
Tx
Buff

Common
Regs

CPU Bus

Cycle
Control

Tx
Buff

Cycle Control

FIFO
Decoder

USB DataLines
D+ andD-

2446

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Features

www.ti.com

23.2.2 Signal Description
The USB controller requires a total of three signals (D+, D-, and VBus) to operate in device mode and two
signals (D+, D-) to operate in embedded host mode. Because of the differential signaling needed for USB,
the pins D+ and D- have special buffers to support USB. As such, their position on the chip is not userselectable. These pins at reset are, by default, GPIOs. They must be configured before being used as
USB function pins. Bits 10 and 11 in the GPIO B Analog Mode Select register (GPBAMSEL) should be set
to choose the USB function. The signals USB bus voltage (VBUS), external power enable (EPEN), and
power fault (PFLT) are not hardwired to any pin and some applications will require they be implemented in
software via a GPIO. Software that implements these signals is available in the USB software library.

23.2.3 VBus Recommendations
Most applications do not need to monitor VBus. Because of this, a dedicated VBus monitoring pin was not
included on this microcontroller. If you are designing a bus-powered device application or an embedded
host application, you do NOT need to monitor VBus. If you are designing a self-powered device, you will
need to actively monitor the state of the VBus pin in order to ensure compliance with the USB specification.
In Section 7.1.5 and Section 7.2.1 of the USB Specification Revision 2.0™ it is stated respectively that:
• "The voltage source on the [speed identification] pull-up resistor must be derived from or controlled by
the power supplied on the USB cable such that when VBUS is removed, the pull-up resistor does not
supply current on the data line to which it is attached.
• When VBUS is removed, the device must remove power from the D+/D- pull-up resistor within 10
seconds.
• Later in the timing tables (Section 7.3.2) of the USB Specification 2.0 it is also stated that the D+/Dpull-up resistor should be applied within 100ms of VBus reaching a valid level."
Meeting the above specification is easy because of the slow timing requirements. In this chapter we will
discuss the hardware part of the VBus monitoring solution. The corresponding software will be discussed
briefly, but for examples and an explanation, please consult the USB software guide.
The pins of this microcontroller are not 5V tolerant, and because of this, the VBus signal cannot be directly
connected to a GPIO pin. Directly connecting 5V to a pin of the microcontroller will destroy the I/O buffer
of the pin and possibly more of the chip. The most cost-effective way of making any pin capable of reading
a 5V input is to use a series resistance in conjunction with the ESD diode clamps already present inside
the device on every pin. It is recommended to use a 100kΩ series resistor between the VBus signal and the
pin chosen to monitor it. A diagram of this setup is shown in Figure 23-2.

+3V3

Figure 23-2. USB Scheme

100 k

GPIOx
USB-DP/GPIO43
USB-DM/GPIO42

GND

P$1
P$3
P$2
P$4

VBUS
D+
D–
GND

GND

In the above diagram, if VBus is above or below 3.3V and 0V respectively, one of the ESD clamp diodes
will be forward-biased, allowing current to flow through the 100KΩ resistor. The purpose of the diode
clamps is to protect the pins of the microcontroller from very short overvoltage spikes of a high magnitude.
They do this by clamping the voltage excursion to one of the supply rails. We are effectively requiring the
ESD clamps to do the same thing they were designed to do, but instead of a short high magnitude pulse,
we are giving them a long low magnitude static value via the 100kΩ resistor.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2447

Functional Description

www.ti.com

Any pin that has digital input/output functionality could potentially be used to monitor VBus, but the use of
an interrupt-capable GPIO is recommended. A pin that does not have external interrupt capability may
also be used, but the input state of the pin must be polled periodically by the application software to
ensure appropriate action is taken whenever VBus is applied or removed. If an interrupt-capable GPIO is
chosen, it should be configured to generate an interrupt on both the rising and falling edge. More
information on external interrupts can be found in the System Control and Interrupts chapter. Example
code that implements VBus monitoring using external interrupts and takes the appropriate actions is
documented in the USB Software Guide and can be found in the associated USB software package.

23.3 Functional Description
The USB controller can be configured to act as either a dedicated host or device. However, when the USB
controller is acting as a self-powered device, a GPIO input or analog comparator input must be connected
to VBUS and configured to generate an interrupt when the VBUS level drops. This interrupt is used to disable
the pullup resistor on the USB0DP signal.
NOTE: When USB is used in the system, the minimum system frequency is 30 MHz.

23.3.1 Operation as a Device
This section describes how the USB controller performs when it is being used as a USB device. IN
endpoints, OUT endpoints, entry into and exit from SUSPEND mode, and recognition of start of frame
(SOF) are all described.
When in device mode, IN transactions are controlled by the endpoint transmit interface and uses the
transmit endpoint registers for the given endpoint. OUT transactions are handled with the endpoints
receive interface and use the receive endpoint registers for the given endpoint. When configuring the size
of the FIFOs for endpoints, take into account the maximum packet size for an endpoint. Note the following:
• Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum
packet size if double buffering is used (described further in the following section).
• Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum
packet size if double buffering is used.
• It is also possible to specify a separate control endpoint for a USB device. However, in most cases the
USB device should use the dedicated control endpoint on the USB controller’s endpoint 0.
23.3.1.1 Control and Configurable Endpoints
When operating as a device, the USB controller provides two dedicated control endpoints (IN and OUT)
and thirty configurable endpoints (fifteen IN and fifteen OUT) that can be used for communications with a
host controller. The endpoint number and direction associated with an endpoint is directly related to its
register designation. For example, when the Host is transmitting to endpoint 1, all configuration and data is
in the endpoint 1 transmit register interface. Endpoint 0 is a dedicated control endpoint used for all control
transactions to endpoint 0 during enumeration or when any other control requests are made to endpoint 0.
Endpoint 0 uses the first 64 bytes of the USB controller's FIFO RAM as a shared memory for both IN and
OUT transactions. The remaining six endpoints can be configured as control, bulk, or interrupt endpoints.
They should be treated as three configurable IN and three configurable OUT endpoints. The endpoint
pairs are not required to have the same type for their IN and OUT endpoint configuration. For example,
the OUT portion of an endpoint pair could be a bulk endpoint, while the IN portion of that endpoint pair
could be an interrupt endpoint. The address and size of the FIFOs attached to each endpoint can be
modified to fit the application's needs.

2448

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

23.3.1.1.1 IN Transactions as a Device
When operating as a USB device, data for IN transactions is handled through the FIFOs attached to the
transmit endpoints. The sizes of the FIFOs for the fifteen configurable IN endpoints are determined by the
USB Transmit FIFO Start Address (USBTXFIFOADD) register. The maximum size of a data packet that
may be placed in a transmit endpoint’s FIFO for transmission is programmable and is determined by the
value written to the USB Maximum Transmit Data Endpoint n (USBTXMAXPn) register for that endpoint.
The endpoint’s FIFO can also be configured to use double-packet or single-packet buffering. When
double-packet buffering is enabled, two data packets can be buffered in the FIFO, which also requires that
the FIFO is at least two packets in size. When double-packet buffering is disabled, only one packet can be
buffered, even if the packet size is less than half the FIFO size.
Note: The maximum packet size set for any endpoint must not exceed the FIFO size. The USBTXMAXPn
register should not be written to while data is in the FIFO as unexpected results may occur.
Single-Packet Buffering
If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint (as
set in the USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) register), only one packet can be buffered
in the FIFO and single-packet buffering is required. When each packet is completely loaded into the
transmit FIFO, the TXRDY bit in the USB Transmit Control and Status Endpoint n Low (USBTXCSRLn)
register must be set. If the AUTOSET bit in the USB Transmit Control and Status Endpoint n High
(USBTXCSRHn) register is set, the TXRDY bit is automatically set when a maximum-sized packet is
loaded into the FIFO. For packet sizes less than the maximum, the TXRDY bit must be set manually.
When the TXRDY bit is set, either manually or automatically, the packet is ready to be sent. When the
packet has been successfully sent, both TXRDY and FIFONE are cleared, and the appropriate transmit
endpoint interrupt signaled. At this point, the next packet can be loaded into the FIFO.
Double-Packet Buffering
If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint, two
packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is loaded into
the transmit FIFO, the TXRDY bit in the USBTXCSRLn register must be set. If the AUTOSET bit in the
USBTXCSRHn register is set, the TXRDY bit is automatically set when a maximum-sized packet is loaded
into the FIFO. For packet sizes less than the maximum, TXRDY must be set manually. When the TXRDY
bit is set, either manually or automatically, the packet is ready to be sent. After the first packet is loaded,
TXRDY is immediately cleared and an interrupt is generated. A second packet can now be loaded into the
transmit FIFO and TXRDY set again (either manually or automatically if the packet is the maximum size).
At this point, both packets are ready to be sent. After each packet has been successfully sent, TXRDY is
automatically cleared and the appropriate transmit endpoint interrupt signaled to indicate that another
packet can now be loaded into the transmit FIFO. The state of the FIFONE bit in the USBTXCSRLn
register at this point indicates how many packets may be loaded. If the FIFONE bit is set, then another
packet is in the FIFO and only one more packet can be loaded. If the FIFONE bit is clear, then no packets
are in the FIFO and two more packets can be loaded.
Note: Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB
Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) register. This bit is set by default, so it
must be cleared to enable double-packet buffering.
23.3.1.1.2 Out Transactions as a Device
When in device mode, OUT transactions are handled through the USB controller receive FIFOs. The sizes
of the receive FIFOs for the fifteen configurable OUT endpoints are determined by the USB Receive FIFO
Start Address (USBRXFIFOADD) register. The maximum amount of data received by an endpoint in any
packet is determined by the value written to the USB Maximum Receive Data Endpoint n (USBRXMAXPn)
register for that endpoint. When double-packet buffering is enabled, two data packets can be buffered in
the FIFO. When double-packet buffering is disabled, only one packet can be buffered even if the packet is
less than half the FIFO size.
Note: In all cases, the maximum packet size must not exceed the FIFO size.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2449

Functional Description

www.ti.com

Single-Packet Buffering
If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint, only
one data packet can be buffered in the FIFO and single-packet buffering is required. When a packet is
received and placed in the receive FIFO, the RXRDY and FULL bits in the USB Receive Control and
Status Endpoint n Low (USBRXCSRL[n]) register are set and the appropriate receive endpoint is signaled,
indicating that a packet can now be unloaded from the FIFO. After the packet has been unloaded, the
RXRDY bit must be cleared in order to allow further packets to be received. This action also generates the
acknowledge signaling to the Host controller. If the AUTOCL bit in the USB Receive Control and Status
Endpoint n High (USBRXCSRH[n]) register is set and a maximum-sized packet is unloaded from the
FIFO, the RXRDY and FULL bits are cleared automatically. For packet sizes less than the maximum,
RXRDY must be cleared manually.
Double-Packet Buffering
If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint, two
data packets can be buffered and double-packet buffering can be used. When the first packet is received
and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRL[n] register is set and the appropriate
receive endpoint interrupt is signaled to indicate that a packet can now be unloaded from the FIFO.
Note: The FULL bit in USBRXCSRL[n] is not set when the first packet is received. It is only set if a second
packet is received and loaded into the receive FIFO.
After each packet has been unloaded, the RXRDY bit must be cleared to allow further packets to be
received. If the AUTOCL bit in the USBRXCSRH[n] register is set and a maximum-sized packet is
unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than the maximum,
RXRDY must be cleared manually. If the FULL bit is set when RXRDY is cleared, the USB controller first
clears the FULL bit, then sets RXRDY again to indicate that there is another packet waiting in the FIFO to
be unloaded.
Note: Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB
Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) register. This bit is set by default, so it
must be cleared to enable double-packet buffering.
23.3.1.1.3 Scheduling
The device has no control over the scheduling of transactions as scheduling is determined by the Host
controller. The USB controller can set up a transaction at any time. The USB controller waits for the
request from the Host controller and generates an interrupt when the transaction is complete or if it was
terminated due to some error. If the Host controller makes a request and the device controller is not ready,
the USB controller sends a busy response (NAK) to all requests until it is ready.
23.3.1.1.4 Additional Actions
The USB controller responds automatically to certain conditions on the USB bus or actions by the Host
controller such as when the USB controller automatically stalls a control transfer or unexpected zero
length OUT data packets.
Stalled Control Transfer
The USB controller automatically issues a STALL handshake to a control transfer under the following
conditions:
1. The Host sends more data during an OUT data phase of a control transfer than was specified in the
device request during the SETUP phase. This condition is detected by the USB controller when the
Host sends an OUT token (instead of an IN token) after the last OUT packet has been unloaded and
the DATAEND bit in the USB Control and Status Endpoint 0 Low (USBCSRL0) register has been set.
2. The Host requests more data during an IN data phase of a control transfer than was specified in the
device request during the SETUP phase. This condition is detected by the USB controller when the
Host sends an IN token (instead of an OUT token) after the CPU has cleared TXRDY and set
DATAEND in response to the ACK issued by the Host to what should have been the last packet.
3. The Host sends more than USBRXMAXPn bytes of data with an OUT data token.
4. The Host sends more than a zero length data packet for the OUT STATUS phase.
2450

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

Zero Length OUT Data Packets
A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation, such
packets should only be received after the entire length of the device request has been transferred.
However, if the Host sends a zero-length OUT data packet before the entire length of device request has
been transferred, it is signaling the premature end of the transfer. In this case, the USB controller
automatically flushes any IN token ready for the data phase from the FIFO and sets the DATAEND bit in
the USBCSRL0 register.
Setting the Device Address
When a Host is attempting to enumerate the USB device, it requests that the device change its address
from zero to some other value. The address is changed by writing the value that the Host requested to the
USB Device Functional Address (USBFADDR) register. However, care should be taken when writing to
USBFADDR to avoid changing the address before the transaction is complete. This register should only
be set after the SET_ADDRESS command is complete. Like all control transactions, the transaction is
only complete after the device has left the STATUS phase. In the case of a SET_ADDRESS command,
the transaction is completed by responding to the IN request from the Host with a zero-byte packet. Once
the device has responded to the IN request, the USBFADDR register should be programmed to the new
value as soon as possible to avoid missing any new commands sent to the new address.
Note: If the USBFADDR register is set to the new value as soon as the device receives the OUT
transaction with the SET_ADDRESS command in the packet, it changes the address during the control
transfer. In this case, the device does not receive the IN request that allows the USB transaction to exit
the STATUS phase of the control transfer because it is sent to the old address. As a result, the Host does
not get a response to the IN request, and the Host fails to enumerate the device.
23.3.1.1.5 Device Mode Suspend
When no activity has occurred on the USB bus for 3 ms, the USB controller automatically enters
SUSPEND mode. If the SUSPEND interrupt has been enabled in the USB Interrupt Enable (USBIE)
register, an interrupt is generated at this time. When in SUSPEND mode, the PHY also goes into
SUSPEND mode. When RESUME signaling is detected, the USB controller exits SUSPEND mode and
takes the PHY out of SUSPEND. If the RESUME interrupt is enabled, an interrupt is generated. The USB
controller can also be forced to exit SUSPEND mode by setting the RESUME bit in the USB Power
(USBPOWER) register. When this bit is set, the USB controller exits SUSPEND mode and drives
RESUME signaling onto the bus. The RESUME bit must be cleared after 10 ms (a maximum of 15 ms) to
end RESUME signaling. To meet USB power requirements, the controller can be put into Deep Sleep
mode which keeps the controller in a static state.
23.3.1.1.6 Start of Frame
When the USB controller is operating in device mode, it receives a Start-Of-Frame (SOF) packet from the
Host once every millisecond. When the SOF packet is received, the 11-bit frame number contained in the
packet is written into the USB Frame Value (USBFRAME) register, and an SOF interrupt is also signaled
and can be handled by the application. Once the USB controller has started to receive SOF packets, it
expects one every millisecond. If no SOF packet is received after 1.00358 ms, the packet is assumed to
have been lost, and the USBFRAME register is not updated. The USB controller continues and
resynchronizes these pulses to the received SOF packets when these packets are successfully received
again.
23.3.1.1.7 USB Reset
When the USB controller is in device mode and a RESET condition is detected on the USB bus, the USB
controller automatically performs the following actions:
• Clears the USBFADDR register
• Clears the USB Endpoint Index (USBEPIDX) register
• Flushes all endpoint FIFOs
• Clears all control/status registers
• Enables all endpoint interrupts
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2451

Functional Description

•

www.ti.com

Generates a RESET interrupt

23.3.1.1.8 Connect/Disconnect
The USB controller connection to the USB bus is handled by software. The USB PHY can be switched
between normal mode and non-driving mode by setting or clearing the SOFTCONN bit of the
USBPOWER register. When the SOFTCONN bit is set, the PHY is placed in its normal mode, and the
USB0DP/USB0DM lines of the USB bus are enabled. At the same time, the USB controller is placed into
a state, in which it does not respond to any USB signaling except a USB RESET. When the SOFTCONN
bit is cleared, the PHY is put into non-driving mode, USB0DP and USB0DM are tristated, and the USB
controller appears to other devices on the USB bus as if it has been disconnected. The non-driving mode
is the default so the USB controller appears disconnected until the SOFTCONN bit has been set. The
application software can then choose when to set the PHY into its normal mode. Systems with a lengthy
initialization procedure may use this to ensure that initialization is complete, and the system is ready to
perform enumeration before connecting to the USB bus. Once the SOFTCONN bit has been set, the USB
controller can be disconnected by clearing this bit.
Note: The USB controller does not generate an interrupt when the device is connected to the Host.
However, an interrupt is generated when the Host terminates a session.

23.3.2 Operation as a Host
When the USB controller is operating in Host mode, it can either be used for point-to-point
communications with another USB device or, when attached to a hub, for communication with multiple
devices. Full-speed and low-speed USB devices are supported, both for point-to-point communication and
for operation through a hub. The USB controller automatically carries out the necessary transaction
translation needed to allow a low-speed or full-speed device to be used with a USB 2.0 hub. Control, bulk,
and interrupt transactions are supported. This section describes the USB controller's actions when it is
being used as a USB Host. Configuration of IN endpoints, OUT endpoints, entry into and exit from
SUSPEND mode, and RESET are all described.
When in Host mode, IN transactions are controlled by an endpoint’s receive interface. All IN transactions
use the receive endpoint registers and all OUT endpoints use the transmit endpoint registers for a given
endpoint. As in device mode, the FIFOs for endpoints should take into account the maximum packet size
for an endpoint.
• Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum
packet size if double buffering is used (described further in the following section).
• Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum
packet size if double buffering is used.
• It is also possible to specify a separate control endpoint to communicate with a device. However, in
most cases the USB controller should use the dedicated control endpoint to communicate with a
device’s endpoint 0.
23.3.2.1 Endpoint Registers
The endpoint registers are used to control the USB endpoint interfaces which communicate with device(s)
that are connected. The endpoints consist of a dedicated control IN endpoint, a dedicated control OUT
endpoint, fifteen configurable OUT endpoints, and fifteen configurable IN endpoints.
The dedicated control interface can only be used for control transactions to endpoint 0 of devices. These
control transactions are used during enumeration or other control functions that communicate using
endpoint 0 of devices. This control endpoint shares the first 64 bytes of the USB controller’s FIFO RAM for
IN and OUT transactions. The remaining IN and OUT interfaces can be configured to communicate with
control, bulk, or interrupt endpoints.
These USB interfaces can be used to simultaneously schedule as many as fifteen independent OUT and
fifteen independent IN transactions to any endpoints on any device. The IN and OUT controls are paired in
fifteen sets of registers. However, they can be configured to communicate with different types of endpoints
and different endpoints on devices. For example, the first pair of endpoint controls can be split so that the
OUT portion is communicating with a device’s bulk OUT endpoint 1, while the IN portion is communicating
with a device’s interrupt IN endpoint 2.
2452

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

Before accessing any device, whether for point-to-point communications or for communications via a hub,
the relevant USB Receive Functional Address Endpoint n (USBRXFUNCADDRn) or USB Transmit
Functional Address Endpoint n (USBTXFUNCADDRn) registers must be set for each receive or transmit
endpoint to record the address of the device being accessed.
The USB controller also supports connections to devices through a USB hub by providing a register that
specifies the hub address and port of each USB transfer. The FIFO address and size are customizable
and can be specified for each USB IN and OUT transfer. Customization includes allowing one FIFO per
transaction, sharing a FIFO across transactions, and allowing for double-buffered FIFOs.
23.3.2.2 IN Transactions as a Host
IN transactions are handled in a similar manner to the way in which OUT transactions are handled when
the USB controller is in device mode except that the transaction first must be initiated by setting the
REQPKT bit in the USBCSRL0 register, indicating to the transaction scheduler that there is an active
transaction on this endpoint. The transaction scheduler then sends an IN token to the target device. When
the packet is received and placed in the receive FIFO, the RXRDY bit in the USBCSRL0 register is set,
and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be unloaded
from the FIFO.
When the packet has been unloaded, RXRDY must be cleared. The AUTOCL bit in the USBRXCSRHn
register can be used to have RXRDY automatically cleared when a maximum-sized packet has been
unloaded from the FIFO. The AUTORQ bit in USBRXCSRHn causes the REQPKT bit to be automatically
set when the RXRDY bit is cleared. When the RXRDY bit is cleared, the controller sends an acknowledge
to the device. When there is a known number of packets to be transferred, the USB Request Packet
Count in Block Transfer Endpoint n (USBRQPKTCOUNTn) register associated with the endpoint should
be configured to the number of packets to be transferred. The USB controller decrements the value in the
USBRQPKTCOUNTn register following each request. When the USBRQPKTCOUNTn value decrements
to 0, the AUTORQ bit is cleared to prevent any further transactions being attempted. For cases where the
size of the transfer is unknown, USBRQPKTCOUNTn should be cleared. AUTORQ then remains set until
cleared by the reception of a short packet (that is, less than the MAXLOAD value in the USBRXMAXPn
register) such as may occur at the end of a bulk transfer.
If the device responds to a bulk or interrupt IN token with a NAK, the USB Host controller keeps retrying
the transaction until any NAK Limit that has been set has been reached. If the target device responds with
a STALL, however, the USB Host controller does not retry the transaction but sets the STALLED bit in the
USBCSRL0 register. If the target device does not respond to the IN token within the required time, or the
packet contained a CRC or bit-stuff error, the USB Host controller retries the transaction. If after three
attempts the target device has still not responded, the USB Host controller clears the REQPKT bit and
sets the ERROR bit in the USBCSRL0 register.
23.3.2.3 OUT Transactions as a Host
OUT transactions are handled in a similar manner to the way in which IN transactions are handled when
the USB controller is in device mode. The TXRDY bit in the USBTXCSRLn register must be set as each
packet is loaded into the transmit FIFO. Again, setting the AUTOSET bit in the USBTXCSRHn register
automatically sets TXRDY when a maximum-sized packet has been loaded into the FIFO.
If the target device responds to the OUT token with a NAK, the USB Host controller keeps retrying the
transaction until the NAK Limit that has been set has been reached. However, if the target device
responds with a STALL, the USB controller does not retry the transaction but interrupts the main
processor by setting the STALLED bit in the USBTXCSRLn register. If the target device does not respond
to the OUT token within the required time, or the packet contained a CRC or bit-stuff error, the USB Host
controller retries the transaction. If after three attempts the target device has still not responded, the USB
controller flushes the FIFO and sets the ERROR bit in the USBTXCSRLn register.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2453

Functional Description

www.ti.com

23.3.2.4 Transaction Scheduling
Scheduling of transactions is handled automatically by the USB Host controller. The Host controller allows
configuration of the endpoint communication scheduling based on the type of endpoint transaction.
Interrupt transactions can be scheduled to occur in the range of every frame to every 255 frames in 1
frame increments. Bulk endpoints do not allow scheduling parameters, but do allow for a NAK timeout in
the event an endpoint on a device is not responding.
The USB controller maintains a frame counter. If the target device is a full-speed device, the USB
controller automatically sends an SOF packet at the start of each frame and increments the frame counter.
If the target device is a low-speed device, a K state is transmitted on the bus to act as a keep-alive to stop
the low-speed device from going into SUSPEND mode.
After the SOF packet has been transmitted, the USB Host controller cycles through all the configured
endpoints looking for active transactions. An active transaction is defined as a receive endpoint for which
the REQPKT bit is set or a transmit endpoint for which the TXRDY bit and/or the FIFONE bit is set.
An interrupt transaction is started if the transaction is found on the first scheduler cycle of a frame and if
the interval counter for that endpoint has counted down to zero. As a result, only one interrupt transaction
occurs per endpoint every n frames, where n is the interval set via the USB Host Transmit Interval
Endpoint n (USBTXINTERVAL[n]) or USB Host Receive Interval Endpoint n (USBRXINTERVAL[n])
register for that endpoint.
An active bulk transaction starts immediately, provided sufficient time is left in the frame to complete the
transaction before the next SOF packet is due. If the transaction must be retried (for example, because a
NAK was received or the target device did not respond), then the transaction is not retried until the
transaction scheduler has first checked all the other endpoints for active transactions. This process
ensures that an endpoint that is sending a lot of NAKs does not block other transactions on the bus. The
controller also allows the user to specify a limit to the length of time for NAKs to be received from a target
device before the endpoint times out.
23.3.2.5 USB Hubs
The following setup requirements apply to the USB Host controller only if it is used with a USB hub. When
a full- or low-speed device is connected to the USB controller via a USB 2.0 hub, details of the hub
address and the hub port also must be recorded in the corresponding USB Receive Hub Address
Endpoint n (USBRXHUBADDRn) and USB Receive Hub Port Endpoint n (USBRXHUBPORTn) or the
USB Transmit Hub Address Endpoint n (USBTXHUBADDRn) and USB Transmit Hub Port Endpoint n
(USBTXHUBPORTn) registers. In addition, the speed at which the device operates (full or low) must be
recorded in the USB Type Endpoint 0 (USBTYPE0) (endpoint 0), USB Host Configure Transmit Type
Endpoint n (USBTXTYPEn), or USB Host Configure Receive Type Endpoint n (USBRXTYPEn) registers
for each endpoint that is accessed by the device.
For hub communications, the settings in these registers record the current allocation of the endpoints to
the attached USB devices. To maximize the number of devices supported, the USB Host controller allows
this allocation to be changed dynamically by simply updating the address and speed information recorded
in these registers. Any changes in the allocation of endpoints to device functions must be made following
the completion of any on-going transactions on the endpoints affected.
23.3.2.6 Babble
The USB Host controller does not start a transaction until the bus has been inactive for at least the
minimum inter-packet delay. The controller also does not start a transaction unless it can be finished
before the end of the frame. If the bus is still active at the end of a frame, then the USB Host controller
assumes that the target device to which it is connected has malfunctioned, and the USB controller
suspends all transactions and generates a babble interrupt.
23.3.2.7 Host SUSPEND
If the SUSPEND bit in the USBPOWER register is set, the USB Host controller completes the current
transaction then stops the transaction scheduler and frame counter. No further transactions are started
and no SOF packets are generated.

2454

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

To exit SUSPEND mode, set the RESUME bit and clear the SUSPEND bit. While the RESUME bit is set,
the USB Host controller generates RESUME signaling on the bus. After 20 ms, the RESUME bit must be
cleared, at which point the frame counter and transaction scheduler start. The Host supports the detection
of a remote wake-up.
23.3.2.8 USB RESET
If the RESET bit in the USBPOWER register is set, the USB Host controller generates USB RESET
signaling on the bus. The RESET bit must be set for at least 20 ms to ensure correct resetting of the
target device. After the CPU has cleared the bit, the USB Host controller starts its frame counter and
transaction scheduler.
23.3.2.9 Connect/Disconnect
A session is started by setting the SESSION bit in the USB device Control (USBDEVCTL) register,
enabling the USB controller to wait for a device to be connected. When a device is detected, a connect
interrupt is generated. The speed of the device that has been connected can be determined by reading
the USBDEVCTL register where the FSDEV bit is set for a full-speed device, and the LSDEV bit is set for
a low-speed device. The USB controller must generate a RESET to the device, and then the USB Host
controller can begin device enumeration. If the device is disconnected while a session is in progress, a
disconnect interrupt is generated.

23.3.3 DMA Operation
The USB module's DMA trigger signals are not supported on this device. The DMA controller may be used
to read and write the USB FIFOs via software triggering. see the Direct Memory Access (DMA) chapter for
more details about programming the DMA controller.

23.3.4 Address/Data Bus Bridge
The USB controller on this device is the same controller that is on the Stellaris devices. This controller
was originally designed to connect to an ARM AHB bus, but has been modified in order to function with
the C28x device’s bus architecture. The modifications made are largely invisible to the user application,
but there are some things to note.
• The USB memory space is 8 bits wide, while the C28x memory space is 16 bits wide.
• 32 and 16 bit accesses (r/w) are completely transparent to the user application code, no changes need
be made.
• The C28x core only supports 8 bit accesses through a byte intrinsic type. This can be used to perform
8 bit reads or writes to the USB controller.
– int &__byte(int *array, unsigned int byte_index);
– *array = ptr to address to access, byte_index = always 0 (for USB)
See Table 23-1 for example.
– See the TMS320C28x Optimizing C/C++ Compiler User's Guide (SPRU514) and the TMS320C28x
Assembly Language Tools User's Guide (SPRU513)
• Because of the bridge, the memory view of the USB controller memory space in CCS isn’t a 1:1
representation of what is in the controller
– When the view mode is
• 32 bit or 16 bit, even address are effectively duplicated, ignore odd addresses.
• 8 bit, Even addresses from within the controller are duplicated into odd address in the view
window; old addresses from within the controller are not displayed.
See Table 23-2 for example.
Table 23-1. USB Memory Access From Software
USB Controller Memory

C28x 8 Bit

Address

Reg. Name

Data

Access

Data

0x00

FADDR

0x00

__byte((int *)0x00,0)

0x0000

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Serial Bus (USB) Controller 2455

Functional Description

www.ti.com

Table 23-1. USB Memory Access From Software (continued)
USB Controller Memory
0x01

C28x 8 Bit

POWER

0x11

__byte((int *)0x01,0)

0x0011

0x02

TXIS (LSB)

0x22

__byte((int *)0x02,0)

0x0022

0x03

TXIS (MSB)

0x33

__byte((int *)0x03,0)

0x0033

0x04

RXIS (LSB)

0x44

__byte((int *)0x04,0)

0x0044

0x05

RXIS (MSB)

0x55

__byte((int *)0x05,0)

0x0055

0x06

TXIE (LSB)

0x66

__byte((int *)0x06,0)

0x0066

0x07

TXIE (MSB)

0x77

__byte((int *)0x07,0)

0x0077

0x08

RXIE (LSB)

0x88

__byte((int *)0x08,0)

0x0088

0x09

RXIE (MSB)

0x99

__byte((int *)0x09,0)

0x0099

0x0A

USBIS

0xAA

__byte((int *)0x0A,0)

0x00AA

0x0B

USBIE

0xBB

__byte((int *)0x0B,0)

0x00BB

0x0C

FRAME (LSB)

0xCC

__byte((int *)0x0C,0)

0x00CC

0x0D

FRAME (MSB)

0xDD

__byte((int *)0x0D,0)

0x00DD

0x0E

EPIDX

0xEE

__byte((int *)0x0E,0)

0x00EE

0x0F

TEST

0xFF

__byte((int *)0x0F,0)

0x00FF

C28x 16 Bit

C28x 32 Bit

Access

Data

Access

Data

(*((short *)(0x00)))

0x1100

(*((long *)(0x00)))

0x33221100

(*((short *)(0x01)))

0x1100

(*((long *)(0x01)))

0x33221100

(*((short *)(0x02)))

0x3322

(*((long *)(0x02)))

0x33221100

(*((short *)(0x03)))

0x3322

(*((long *)(0x03)))

0x33221100

(*((short *)(0x04)))

0x5544

(*((long *)(0x04)))

0x77665544

(*((short *)(0x05)))

0x5544

(*((long *)(0x05)))

0x77665544

(*((short *)(0x06)))

0x7766

(*((long *)(0x06)))

0x77665544

(*((short *)(0x07)))

0x7766

(*((long *)(0x07)))

0x77665544

(*((short *)(0x08)))

0x9988

(*((long *)(0x08)))

0xBBAA9988

(*((short *)(0x09)))

0x9988

(*((long *)(0x09)))

0xBBAA9988

(*((short *)(0x0A)))

0xBBAA

(*((long *)(0x0A)))

0xBBAA9988

(*((short *)(0x0B)))

0xBBAA

(*((long *)(0x0B)))

0xBBAA9988

(*((short *)(0x0C)))

0xDDCC

(*((long *)(0x0C)))

0xFFEEDDCC

(*((short *)(0x0D)))

0xDDCC

(*((long *)(0x0D)))

0xFFEEDDCC

(*((short *)(0x0E)))

0xFFEE

(*((long *)(0x0E)))

0xFFEEDDCC

(*((short *)(0x0F)))

0xFFEE

(*((long *)(0x0F)))

0xFFEEDDCC

Table 23-2. USB Memory Access From CCS
CCS 8 Bit

CCS 16 Bit

CCS 32 Bit

Address

Displayed Data

Address

Displayed Data

Address

Displayed Data

0x00

0x00

0x00

0x1100

0x00

0x11001100

0x01

0x00

0x01

0x1100

0x02

0x33223322

0x02

0x22

0x02

0x3322

0x04

0x55445544

0x03

0x22

0x03

0x3322

0x06

0x77667766

0x04

0x44

0x04

0x5544

0x08

0x99889988

0x05

0x44

0x05

0x5544

0x0A

0xBBAABBAA

0x06

0x66

0x06

0x7766

0x0C

0xDDCCDDCC

0x07

0x66

0x07

0x7766

0x0E

0xFFEEFFEE

0x08

0x88

0x08

0x9988

2456Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Initialization and Configuration

www.ti.com

Table 23-2. USB Memory Access From CCS (continued)
CCS 8 Bit

CCS 16 Bit

CCS 32 Bit

0x09

0x88

0x09

0x9988

0x0A

0xAA

0x0A

0xBBAA

0x0B

0xAA

0x0B

0xBBAA

0x0C

0xCC

0x0C

0xDDCC

0x0D

0xCC

0x0D

0xDDCC

0x0E

0xEE

0x0E

0xFFEE

0x0F

0xEE

0x0F

0xFFEE

23.4 Initialization and Configuration
To use the USB controller, the peripheral clock must be enabled via the System Control module's
PCLKCR11 register. In addition, the USB PHY signals must be connected to their respective pins via the
GPIO module's GPBAMSEL register. Set bits 10 and 11 for USB0DM (GPIO42) and USB0DP (GPIO43).
Set up the auxiliary PLL so a 60 MHz output clock is provided to the USB module. This fixed frequency is
required for all USB operations. See the System Control chapter for more details.
In host mode, the USB controller is responsible for supplying power to the bus. To avoid incorrectly
supplying voltage to the bus, the external power control signal, USB0EPEN, should be kept inactive on
start-up. This can be done by connecting the USB0EPEN and USB0PFLT pins to the USB controller as
soon as possible.

23.4.1 Pin Configuration
In order to give the user more flexibiliity, the signals External Power Enable (EPEN) and Power Fault
(PFLT) were not implemented in hardware. Instead, it is left up to the user to implement these signals in
software. Examples of how to implement these signals in software can be found in the F2806x USB
Software Guide.
When using the device controller portion of the USB controller in a system that also provides host
functionality, the power to VBUS must be disabled to allow the external host controller to supply power.
Usually, the EPEN signal is used to control the external regulator and should be negated to avoid having
two devices driving the VBUS power pin on the USB connector.
When the USB controller is acting as a host, it is in control of two signals that are attached to an external
voltage supply that provides power to VBUS. The Host controller uses the EPEN signal to enable or disable
power to the VBUS pin on the USB connector. An input pin, PFLT, provides feedback when there has been
a power fault on VBUS. The PFLT signal can be configured to either automatically negate the EPEN signal
to disable power, and/or it can generate an interrupt to the interrupt controller to allow software to handle
the power fault condition. The polarity and actions related to both EPEN and PFLT are fully configurable in
the USB controller. The controller also provides interrupts on device insertion and removal to allow the
Host controller code to respond to these external events.

23.4.2 Endpoint Configuration
To start communication in Host or device mode, the endpoint registers must first be configured. In Host
mode, this configuration establishes a connection between an endpoint register and an endpoint on a
device. In device mode, an endpoint must be configured before enumerating to the Host controller.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2457

Register Map

www.ti.com

In both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size
endpoint. In device and Host modes, the endpoint requires little setup but does require a software-based
state machine to progress through the setup, data, and status phases of a standard control transaction. In
device mode, the configuration of the remaining endpoints is done once before enumerating and then only
changed if an alternate configuration is selected by the Host controller. In Host mode, the endpoints must
be configured to operate as control, bulk, or interrupt mode. Once the type of endpoint is configured, a
FIFO area must be assigned to each endpoint. In the case of bulk, control and interrupt endpoints, each
has a maximum of 64 bytes per transaction. The maximum packet size for the given endpoint must be set
prior to sending or receiving data.
Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to each
endpoint. The total FIFO RAM available is 4 Kbytes with the first 64 bytes reserved for endpoint 0. The
endpoint’s FIFO must be at least as large as the maximum packet size. The FIFO can also be configured
as a double-buffered FIFO so that interrupts occur at the end of each packet and allow filling the other half
of the FIFO.
If operating as a device, the USB device controller's soft connect must be enabled when the device is
ready to start communications, indicating to the host controller that the device is ready to start the
enumeration process. If operating as a Host controller, the device soft connect must be disabled and
power must be provided to VBUS via the USB0EPEN signal.

23.5 Register Map
Table 23-3 lists the registers. All addresses given are relative to the USB base address of 0x40000. Note
that the USB controller clock must be enabled before the registers can be programmed (see the System
Control chapter).
Table 23-3. Universal Serial Bus (USB) Controller Register Map
Offset

Name

Type

Reset

Description

Location

0x000

USBFADDR(1)

R/W

0x00

USB Device
Functional Address

Section 23.6.1

0x001

USBPOWER(1)(2)

R/W

0x20

USB Power

Section 23.6.2

0x002

(1)(2)

USBTXIS

RO

0x0000

USB Transmit
Interrupt Status

Section 23.6.3

0x004

USBRXIS(1)(2)

RO

0x0000

USB Receive Interrupt
Status

Section 23.6.4

0x006

USBTXIE(1)(2)

R/W

0xFFFF

USB Transmit
Interrupt Enable

Section 23.6.5

0x008

USBRXIE(1)(2)

R/W

0xFFFE

USB Receive Interrupt
Enable

Section 23.6.6

0x00A

USBIS(1)(2)

RO

0x00

USB General Interrupt
Status

Section 23.6.7

0x00B

USBIE(1)(2)

R/W

0x06

USB Interrupt Enable

Section 23.6.8

RO

0x0000

USB Frame Value

Section 23.6.9

0x00C

(1)(2)

R/W

0x00

USB Endpoint Index

Section 23.6.10

(1)(2)

R/W

0x00

USB Test Mode

Section 23.6.11

(1)(2)

R/W

0x0000.0000

USB FIFO Endpoint 0

Section 23.6.12

0x024

(1)(2)

USBFIFO1

R/W

0x0000.0000

USB FIFO Endpoint 1

Section 23.6.12

0x028

USBFIFO2(1)(2)

R/W

0x0000.0000

USB FIFO Endpoint 2

Section 23.6.12

0x02C

(1)(2)

R/W

0x0000.0000

USB FIFO Endpoint 3

Section 23.6.12

(2)

R/W

0x80

USB Device Control

Section 23.6.13

0x00E
0x00F
0x020

0x060

2458

USBFRAME

(1)(2)

USBEPIDX
USBTEST

USBFIFO0

USBFIFO3

USBDEVCTL

0x062

USBTXFIFOSZ(1)(2)

R/W

0x00

USB Transmit
Dynamic FIFO Sizing

Section 23.6.14

0x063

USBRXFIFOSZ(1)(2)

R/W

0x00

USB Receive
Dynamic FIFO Sizing

Section 23.6.15

0x064

USBTXFIFOADD(1)(2)

R/W

0x0000

USB Transmit FIFO
Start Address

Section 23.6.16

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)
Offset

Name

Type

Reset

Description

Location

0x066

USBRXFIFOADD(1)(2)

R/W

0x0000

USB Receive FIFO
Start Address

Section 23.6.17

0x07A

USBCONTIM(1)(2)

R/W

0x5C

USB Connect Timing

Section 23.6.18

0x07D

(1)(2)

USBFSEOF

R/W

0x77

USB Full-Speed Last
Transaction to End of
Frame Timing

Section 23.6.19

0x07E

USBLSEOF(1)(2)

R/W

0x72

USB Low-Speed Last
Transaction to End of
Frame Timing

Section 23.6.20

0x080

USBTXFUNCADDR0(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 0

Section 23.6.21

0x082

USBTXHUBADDR0(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 0

Section 23.6.22

0x083

USBTXHUBPORT0(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 0

Section 23.6.23

0x088

USBTXFUNCADDR1(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 1

Section 23.6.21

0x08A

USBTXHUBADDR1(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 1

Section 23.6.22

0x08B

USBTXHUBPORT1(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 1

Section 23.6.23

0x08C

USBRXFUNCADDR1(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 1

Section 23.6.24

0x08E

USBRXHUBADDR1(2)

R/W

0x00

USB Receive Hub
Address Endpoint 1

Section 23.6.25

0x08F

USBRXHUBPORT1(2)

R/W

0x00

USB Receive Hub
Port Endpoint 1

Section 23.6.26

0x090

USBTXFUNCADDR2(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 2

Section 23.6.21

0x092

USBTXHUBADDR2(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 2

Section 23.6.22

0x093

USBTXHUBPORT2(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 2

Section 23.6.23

0x094

USBRXFUNCADDR2(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 2

Section 23.6.24

0x096

USBRXHUBADDR2(2)

R/W

0x00

USB Receive Hub
Address Endpoint 2

Section 23.6.25

0x097

USBRXHUBPORT2(2)

R/W

0x00

USB Receive Hub
Port Endpoint 2

Section 23.6.26

0x098

USBTXFUNCADDR3(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 3

Section 23.6.21

0x09A

USBTXHUBADDR3(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 3

Section 23.6.22

0x09B

USBTXHUBPORT3(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 3

Section 23.6.23

0x09C

USBRXFUNCADDR3(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 3

Section 23.6.24

0x09E

USBRXHUBADDR3(2)

R/W

0x00

USB Receive Hub
Address Endpoint 3

Section 23.6.25

0x09F

USBRXHUBPORT3(2)

R/W

0x00

USB Receive Hub
Port Endpoint 3

Section 23.6.26

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2459

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)

2460

Offset

Name

Type

Reset

Description

Location

0xA0

USBTXFUNCADDR4(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 4

Section 23.6.21

0xA2

USBTXHUBADDR4(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 4

Section 23.6.22

0xA3

USBTXHUBPORT4(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 4

Section 23.6.23

0xA4

USBRXFUNCADDR4(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 4

Section 23.6.24

0xA6

USBRXHUBADDR4(2)

R/W

0x00

USB Receive Hub
Address Endpoint 4

Section 23.6.25

0xA7

USBRXHUBPORT4(2)

R/W

0x00

USB Receive Hub
Port Endpoint 4

Section 23.6.26

0xA8

USBTXFUNCADDR5(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 5

Section 23.6.21

0xAA

USBTXHUBADDR5(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 5

Section 23.6.22

0xAB

USBTXHUBPORT5(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 5

Section 23.6.23

0xAC

USBRXFUNCADDR4(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 5

Section 23.6.24

0xAE

USBRXHUBADDR5(2)

R/W

0x00

USB Receive Hub
Address Endpoint 5

Section 23.6.25

0xAF

USBRXHUBPORT5(2)

R/W

0x00

USB Receive Hub
Port Endpoint 5

Section 23.6.26

0xB0

USBTXFUNCADDR6(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 6

Section 23.6.21

0xB2

USBTXHUBADDR6(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 6

Section 23.6.22

0xB3

USBTXHUBPORT6(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 6

Section 23.6.23

0xB4

USBRXFUNCADDR6(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 6

Section 23.6.24

0xB6

USBRXHUBADDR6(2)

R/W

0x00

USB Receive Hub
Address Endpoint 6

Section 23.6.25

0xB7

USBRXHUBPORT6(2)

R/W

0x00

USB Receive Hub
Port Endpoint 6

Section 23.6.26

0xB8

USBTXFUNCADDR7(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 7

Section 23.6.21

0xBA

USBTXHUBADDR7(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 7

Section 23.6.22

0xBB

USBTXHUBPORT7(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 7

Section 23.6.23

0xBC

USBRXFUNCADDR7(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 7

Section 23.6.24

0xBE

USBRXHUBADDR7(2)

R/W

0x00

USB Receive Hub
Address Endpoint 7

Section 23.6.25

0xBF

USBRXHUBPORT7(2)

R/W

0x00

USB Receive Hub
Port Endpoint 7

Section 23.6.26

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)
Offset

Name

Type

Reset

Description

Location

0x0C0

USBTXFUNCADDR8(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 8

Section 23.6.21

0x0C2

USBTXHUBADDR8(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 8

Section 23.6.22

0x0C3

USBTXHUBPORT8(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 8

Section 23.6.23

0x0C4

USBRXFUNCADDR8(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 8

Section 23.6.24

0x0C6

USBRXHUBADDR8(2)

R/W

0x00

USB Receive Hub
Address Endpoint 8

Section 23.6.25

0x0C7

USBRXHUBPORT8(2)

R/W

0x00

USB Receive Hub
Port Endpoint 8

Section 23.6.26

0xC8

USBTXFUNCADDR9(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 9

Section 23.6.21

0x0CA

USBTXHUBADDR9(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 9

Section 23.6.22

0x0CB

USBTXHUBPORT9(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 9

Section 23.6.23

0x0CC

USBRXFUNCADDR9(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 9

Section 23.6.24

0x0CE

USBRXHUBADDR9(2)

R/W

0x00

USB Receive Hub
Address Endpoint 9

Section 23.6.25

0x0CF

USBRXHUBPORT9(2)

R/W

0x00

USB Receive Hub
Port Endpoint 9

Section 23.6.26

0x0D0

USBTXFUNCADDR10(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 10

Section 23.6.21

0x0D2

USBTXHUBADDR10(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 10

Section 23.6.22

0x0D3

USBTXHUBPORT10(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 10

Section 23.6.23

0x0D4

USBRXFUNCADDR10(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 10

Section 23.6.24

0x0D6

USBRXHUBADDR10(2)

R/W

0x00

USB Receive Hub
Address Endpoint 10

Section 23.6.25

0x0D7

USBRXHUBPORT10(2)

R/W

0x00

USB Receive Hub
Port Endpoint 10

Section 23.6.26

0x0D8

USBTXFUNCADDR11(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 11

Section 23.6.21

0x0DA

USBTXHUBADDR11(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 11

Section 23.6.22

0x0DB

USBTXHUBPORT11(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 11

Section 23.6.23

0x0DC

USBRXFUNCADDR11(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 11

Section 23.6.24

0x0DE

USBRXHUBADDR11(2)

R/W

0x00

USB Receive Hub
Address Endpoint 11

Section 23.6.25

0x0DF

USBRXHUBPORT11(2)

R/W

0x00

USB Receive Hub
Port Endpoint 11

Section 23.6.26

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2461

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)

2462

Offset

Name

Type

Reset

Description

Location

0x0E0

USBTXFUNCADDR12(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 12

Section 23.6.21

0x0E2

USBTXHUBADDR12(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 12

Section 23.6.22

0x0E3

USBTXHUBPORT12(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 12

Section 23.6.23

0x0E4

USBRXFUNCADDR12(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 12

Section 23.6.24

0x0E6

USBRXHUBADDR12(2)

R/W

0x00

USB Receive Hub
Address Endpoint 12

Section 23.6.25

0x0E7

USBRXHUBPORT12(2)

R/W

0x00

USB Receive Hub
Port Endpoint 12

Section 23.6.26

0x0E8

USBTXFUNCADDR13(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 13

Section 23.6.21

0x0EA

USBTXHUBADDR13(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 13

Section 23.6.22

0x0EB

USBTXHUBPORT13(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 13

Section 23.6.23

0x0EC

USBRXFUNCADDR13(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 13

Section 23.6.24

0x0EE

USBRXHUBADDR13(2)

R/W

0x00

USB Receive Hub
Address Endpoint 13

Section 23.6.25

0x0EF

USBRXHUBPORT13(2)

R/W

0x00

USB Receive Hub
Port Endpoint 13

Section 23.6.26

0x0F0

USBTXFUNCADDR14(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 14

Section 23.6.21

0x0F2

USBTXHUBADDR14(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 14

Section 23.6.22

0x0F3

USBTXHUBPORT14(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 14

Section 23.6.23

0x0F4

USBRXFUNCADDR14(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 14

Section 23.6.24

0x0F6

USBRXHUBADDR14(2)

R/W

0x00

USB Receive Hub
Address Endpoint 14

Section 23.6.25

0x0F7

USBRXHUBPORT14(2)

R/W

0x00

USB Receive Hub
Port Endpoint 14

Section 23.6.26

0x0F8

USBTXFUNCADDR15(2)

R/W

0x00

USB Transmit
Functional Address
Endpoint 15

Section 23.6.21

0x0FA

USBTXHUBADDR15(2)

R/W

0x00

USB Transmit Hub
Address Endpoint 15

Section 23.6.22

0x0FB

USBTXHUBPORT15(2)

R/W

0x00

USB Transmit Hub
Port Endpoint 15

Section 23.6.23

0x0FC

USBRXFUNCADDR15(2)

R/W

0x00

USB Receive
Functional Address
Endpoint 15

Section 23.6.24

0x0FE

USBRXHUBADDR15(2)

R/W

0x00

USB Receive Hub
Address Endpoint 15

Section 23.6.25

0x0FF

USBRXHUBPORT15(2)

R/W

0x00

USB Receive Hub
Port Endpoint 15

Section 23.6.26

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)
Offset

Name

Type

Reset

Description

Location

0x102

USBCSRL0(1)(2)

W1C

0x00

USB Control and
Status Endpoint 0
Low

Section 23.6.28

0x103

USBCSRH0(1)(2)

W1C

0x00

USB Control and
Status Endpoint 0
High

Section 23.6.29

0x108

USBCOUNT0(1)(2)

R/o

0x00

USB Receive Byte
Count Endpoint 0

Section 23.6.30

0x10A

USBTYPE0(2)

R/W

0x00

USB Type Endpoint 0

Section 23.6.31

(2)

R/W

0x00

USB NAK Limit

Section 23.6.32

0x110

USBTXMAXP1

(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 1

Section 23.6.27

0x112

USBTXCSRL1(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 1
Low

Section 23.6.33

0x113

USBTXCSRH1(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 1
High

Section 23.6.34

0x114

USBRXMAXP1(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 1

Section 23.6.35

0x116

USBRXCSRL1(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 1
Low

Section 23.6.36

0x117

USBRXCSRH1(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 1
High

Section 23.6.37

0x118

USBRXCOUNT1(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 1

Section 23.6.38

0x11A

USBTXTYPE1(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 1

Section 23.6.39

0x11B

USBTXINTERVAL1(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 1

Section 23.6.40

0x11C

USBRXTYPE1(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 1

Section 23.6.41

0x11D

USBRXINTERVAL1(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 1

Section 23.6.42

0x120

USBTXMAXP2(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 2

Section 23.6.27

0x122

USBTXCSRL2(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 2
Low

Section 23.6.33

0x123

USBTXCSRH2(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 2
High

Section 23.6.34

0x124

USBRXMAXP2(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 2

Section 23.6.35

0x126

USBRXCSRL2(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 2
Low

Section 23.6.36

0x127

USBRXCSRH2(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 2
High

Section 23.6.37

0x10B

USBNAKLMT

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2463

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)

2464

Offset

Name

Type

Reset

Description

Location

0x128

USBRXCOUNT2(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 2

Section 23.6.38

0x12A

USBTXTYPE2(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 2

Section 23.6.39

0x12B

USBTXINTERVAL2(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 2

Section 23.6.40

0x12C

USBRXTYPE2(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 2

Section 23.6.41

0x12D

USBRXINTERVAL2(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 2

Section 23.6.42

0x130

USBTXMAXP3(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 3

Section 23.6.27

0x132

USBTXCSRL3(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 3
Low

Section 23.6.33

0x133

USBTXCSRH3(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 3
High

Section 23.6.34

0x134

USBRXMAXP3(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 3

Section 23.6.35

0x136

USBRXCSRL3(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 3
Low

Section 23.6.33

0x137

USBRXCSRH3(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 3
High

Section 23.6.36

0x138

USBRXCOUNT3(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 3

Section 23.6.38

0x13A

USBTXTYPE3(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 3

Section 23.6.39

0x13B

USBTXINTERVAL3(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 3

Section 23.6.40

0x13C

USBRXTYPE3(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 3

Section 23.6.41

0x13D

USBRXINTERVAL3(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 3

Section 23.6.42

0x140

USBTXMAXP4(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 4

Section 23.6.27

0x142

USBTXCSRL4(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 4
Low

Section 23.6.33

0x143

USBTXCSRH4(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 4
High

Section 23.6.34

0x144

USBRXMAXP4(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 4

Section 23.6.35

0x146

USBRXCSRL4(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 4
Low

Section 23.6.33

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)
Offset

Name

Type

Reset

Description

Location

0x147

USBRXCSRH4(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 4
High

Section 23.6.36

0x148

USBRXCOUNT4(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 4

Section 23.6.38

0x14A

USBTXTYPE4(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 4

Section 23.6.39

0x14B

USBTXINTERVAL4(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 4

Section 23.6.40

0x14C

USBRXTYPE4(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 4

Section 23.6.41

0x14D

USBRXINTERVAL4(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 4

Section 23.6.42

0x150

USBTXMAXP5(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 5

Section 23.6.27

0x152

USBTXCSRL5(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 5
Low

Section 23.6.33

0x153

USBTXCSRH5(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 5
High

Section 23.6.34

0x154

USBRXMAXP5(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 5

Section 23.6.35

0x156

USBRXCSRL5(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 5
Low

Section 23.6.33

0x157

USBRXCSRH5(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
5High

Section 23.6.36

0x158

USBRXCOUNT5(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 5

Section 23.6.38

0x15A

USBTXTYPE5(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 5

Section 23.6.39

0x15B

USBTXINTERVAL5(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 5

Section 23.6.40

0x15C

USBRXTYPE5(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 5

Section 23.6.41

0x15D

USBRXINTERVAL5(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 5

Section 23.6.42

0x160

USBTXMAXP6(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 6

Section 23.6.27

0x162

USBTXCSRL6(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 6
Low

Section 23.6.33

0x163

USBTXCSRH6(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 6
High

Section 23.6.34

0x164

USBRXMAXP6(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 6

Section 23.6.35

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2465

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)

2466

Offset

Name

Type

Reset

Description

Location

0x166

USBRXCSRL6(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 6
Low

Section 23.6.33

0x167

USBRXCSRH6(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 6
High

Section 23.6.36

0x168

USBRXCOUNT6(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 6

Section 23.6.38

0x16A

USBTXTYPE6(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 6

Section 23.6.39

0x16B

USBTXINTERVAL6(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 6

Section 23.6.40

0x16C

USBRXTYPE6(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 6

Section 23.6.41

0x16D

USBRXINTERVAL6(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 6

Section 23.6.42

0x170

USBTXMAXP7(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 7

Section 23.6.27

0x172

USBTXCSRL7(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 7
Low

Section 23.6.33

0x173

USBTXCSRH7(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 7
High

Section 23.6.34

0x174

USBRXMAXP7(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 7

Section 23.6.35

0x176

USBRXCSRL7(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 7
Low

Section 23.6.33

0x177

USBRXCSRH7(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 7
High

Section 23.6.36

0x178

USBRXCOUNT7(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 7

Section 23.6.38

0x17A

USBTXTYPE7(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 7

Section 23.6.39

0x17B

USBTXINTERVAL7(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 7

Section 23.6.40

0x17C

USBRXTYPE7(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 7

Section 23.6.41

0x17D

USBRXINTERVAL7(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 7

Section 23.6.42

0x180

USBTXMAXP8(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 8

Section 23.6.27

0x182

USBTXCSRL8(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 8
Low

Section 23.6.33

0x183

USBTXCSRH8(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 8
High

Section 23.6.34

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)
Offset

Name

Type

Reset

Description

Location

0x184

USBRXMAXP8(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 8

Section 23.6.35

0x186

USBRXCSRL8(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 8
Low

Section 23.6.33

0x187

USBRXCSRH8(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 8
High

Section 23.6.36

0x188

USBRXCOUNT8(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 8

Section 23.6.38

0x18A

USBTXTYPE8(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 8

Section 23.6.39

0x18B

USBTXINTERVAL8(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 8

Section 23.6.40

0x18C

USBRXTYPE8(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 8

Section 23.6.41

0x18D

USBRXINTERVAL8(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 8

Section 23.6.42

0x190

USBTXMAXP9(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 9

Section 23.6.27

0x192

USBTXCSRL9(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 9
Low

Section 23.6.33

0x193

USBTXCSRH9(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint 9
High

Section 23.6.34

0x194

USBRXMAXP9(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 9

Section 23.6.35

0x196

USBRXCSRL9(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 9
Low

Section 23.6.33

0x197

USBRXCSRH9(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint 9
High

Section 23.6.36

0x198

USBRXCOUNT9(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 9

Section 23.6.38

0x19A

USBTXTYPE9(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 9

Section 23.6.39

0x19B

USBTXINTERVAL9(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 9

Section 23.6.40

0x19C

USBRXTYPE9(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 9

Section 23.6.41

0x19D

USBRXINTERVAL9(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 9

Section 23.6.42

0x1A0

USBTXMAXP10(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 10

Section 23.6.27

0x1A2

USBTXCSRL10(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
10 Low

Section 23.6.33

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2467

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)

2468

Offset

Name

Type

Reset

Description

Location

0x1A3

USBTXCSRH10(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
10 High

Section 23.6.34

0x1A4

USBRXMAXP10(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 10

Section 23.6.35

0x1A6

USBRXCSRL10(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
10 Low

Section 23.6.33

0x1A7

USBRXCSRH10(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
10 High

Section 23.6.36

0x1A8

USBRXCOUNT10(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 10

Section 23.6.38

0x1AA

USBTXTYPE10(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 10

Section 23.6.39

0x1AB

USBTXINTERVAL10(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 10

Section 23.6.40

0x1AC

USBRXTYPE10(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 10

Section 23.6.41

0x1AD

USBRXINTERVAL10(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 10

Section 23.6.42

0x1B0

USBTXMAXP11(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 11

Section 23.6.27

0x1B2

USBTXCSRL11(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
11 Low

Section 23.6.33

0x1B3

USBTXCSRH11(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
11 High

Section 23.6.34

0x1B4

USBRXMAXP11(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 11

Section 23.6.35

0x1B6

USBRXCSRL11(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
11 Low

Section 23.6.33

0x1B7

USBRXCSRH11(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
11 High

Section 23.6.36

0x1B8

USBRXCOUNT11(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 11

Section 23.6.38

0x1BA

USBTXTYPE11(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 11

Section 23.6.39

0x1BB

USBTXINTERVAL11(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 11

Section 23.6.40

0x1BC

USBRXTYPE11(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 11

Section 23.6.41

0x1BD

USBRXINTERVAL11(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 11

Section 23.6.42

0x1C0

USBTXMAXP12(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 12

Section 23.6.27

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)
Offset

Name

Type

Reset

Description

Location

0x1C2

USBTXCSRL12(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
12 Low

Section 23.6.33

0x1C3

USBTXCSRH12(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
12 High

Section 23.6.34

0x1C4

USBRXMAXP12(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 12

Section 23.6.35

0x1C6

USBRXCSRL12(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
12 Low

Section 23.6.33

0x1C7

USBRXCSRH12(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
12 High

Section 23.6.36

0x1C8

USBRXCOUNT12(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 12

Section 23.6.38

0x1CA

USBTXTYPE12(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 12

Section 23.6.39

0x1CB

USBTXINTERVAL12(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 12

Section 23.6.40

0x1CC

USBRXTYPE12(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 12

Section 23.6.41

0x1CD

USBRXINTERVAL12(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 12

Section 23.6.42

0x1D0

USBTXMAXP13(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 13

Section 23.6.27

0x1D2

USBTXCSRL13(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
13 Low

Section 23.6.33

0x1D3

USBTXCSRH13(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
13 High

Section 23.6.34

0x1D4

USBRXMAXP13(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 13

Section 23.6.35

0x1D6

USBRXCSRL13(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
13 Low

Section 23.6.33

0x1D7

USBRXCSRH13(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
13 High

Section 23.6.36

0x1D8

USBRXCOUNT13(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 13

Section 23.6.38

0x1DA

USBTXTYPE13(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 13

Section 23.6.39

0x1DB

USBTXINTERVAL13(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 13

Section 23.6.40

0x1DC

USBRXTYPE13(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 13

Section 23.6.41

0x1DD

USBRXINTERVAL13(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 13

Section 23.6.42

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2469

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)

2470

Offset

Name

Type

Reset

Description

Location

0x1E0

USBTXMAXP14(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 14

Section 23.6.27

0x1E2

USBTXCSRL14(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
14 Low

Section 23.6.33

0x1E3

USBTXCSRH14(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
14 High

Section 23.6.34

0x1E4

USBRXMAXP14(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 14

Section 23.6.35

0x1E6

USBRXCSRL14(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
14 Low

Section 23.6.33

0x1E7

USBRXCSRH14(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
14 High

Section 23.6.36

0x1E8

USBRXCOUNT14(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 14

Section 23.6.38

0x1EA

USBTXTYPE14(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 14

Section 23.6.39

0x1EB

USBTXINTERVAL14(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 14

Section 23.6.40

0x1EC

USBRXTYPE14(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 14

Section 23.6.41

0x1ED

USBRXINTERVAL14(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 14

Section 23.6.42

0x1F0

USBTXMAXP15(1)(2)

R/W

0x0000

USB Maximum
Transmit Data
Endpoint 15

Section 23.6.27

0x1F2

USBTXCSRL15(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
15 Low

Section 23.6.33

0x1F3

USBTXCSRH15(1)(2)

R/W

0x00

USB Transmit Control
and Status Endpoint
15 High

Section 23.6.34

0x1F4

USBRXMAXP15(1)(2)

R/W

0x0000

USB Maximum
Receive Data
Endpoint 15

Section 23.6.35

0x1F6

USBRXCSRL15(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
15 Low

Section 23.6.33

0x1F7

USBRXCSRH15(1)(2)

R/W

0x00

USB Receive Control
and Status Endpoint
15 High

Section 23.6.36

0x1F8

USBRXCOUNT15(1)(2)

RO

0x0000

USB Receive Byte
Count Endpoint 15

Section 23.6.38

0x1FA

USBTXTYPE15(2)

R/W

0x00

USB Host Transmit
Configure Type
Endpoint 15

Section 23.6.39

0x1FB

USBTXINTERVAL15(2)

R/W

0x00

USB Host Transmit
Interval Endpoint 15

Section 23.6.40

0x1FC

USBRXTYPE15(2)

R/W

0x00

USB Host Configure
Receive Type
Endpoint 15

Section 23.6.41

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)
Offset

Name

Type

Reset

Description

Location

0x1FD

USBRXINTERVAL15(2)

R/W

0x00

USB Host Receive
Polling Interval
Endpoint 15

Section 23.6.42

0x304

USBRQPKTCOUNT1(2)

R/W

0x0000 1

USB Request Packet
Count in Block
Transfer Endpoint 1

Section 23.6.43

0x308

USBRQPKTCOUNT2(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 2

Section 23.6.43

0x30C

USBRQPKTCOUNT3(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 3

Section 23.6.43

0x310

USBRQPKTCOUNT4(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 4

Section 23.6.43

0x314

USBRQPKTCOUNT5(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 5

Section 23.6.43

0x318

USBRQPKTCOUNT6(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 6

Section 23.6.43

0x31C

USBRQPKTCOUNT7(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 7

Section 23.6.43

0x320

USBRQPKTCOUNT8(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 8

Section 23.6.43

0x324

USBRQPKTCOUNT9(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 9

Section 23.6.43

0x328

USBRQPKTCOUNT10(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 10

Section 23.6.43

0x32C

USBRQPKTCOUNT11(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 11

Section 23.6.43

0x330

USBRQPKTCOUNT12(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 12

Section 23.6.43

0x334

USBRQPKTCOUNT13(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 13

Section 23.6.43

0x338

USBRQPKTCOUNT14(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 14

Section 23.6.43

0x33C

USBRQPKTCOUNT15(2)

R/W

0x0000

USB Request Packet
Count in Block
Transfer Endpoint 15

Section 23.6.43

0x340

USBRXDPKTBUFDIS(1)(2)

R/W

0x0000

USB Receive Double
Packet Buffer Disable

Section 23.6.44

0x342

USBTXDPKTBUFDIS(1)(2)

R/W

0x0000

USB Transmit Double
Packet Buffer Disable

Section 23.6.45

0x400

USBEPC(1)(2)

R/W

0x0000.0000

USB External Power
Control

Section 23.6.46

0x404

USBEPCRIS(1)(2)

RO

0x0000.0000

USB External Power
Control Raw Interrupt
Status

Section 23.6.47

0x408

USBEPCIM(2)(1)

R/W

0x0000.0000

USB External Power
Control Interrupt Mask

Section 23.6.48

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2471

Register Map

www.ti.com

Table 23-3. Universal Serial Bus (USB) Controller Register Map (continued)
Offset

Name

Type

Reset

Description

Location

0x40C

USBEPCISC(1)(2)

R/W

0x0000.0000

USB External Power
Control Interrupt
Status and Clear

Section 23.6.49

0x410

USBDRRIS(1)(2)

RO

0x0000.0000

USB Device RESUME
Raw Interrupt Status

Section 23.6.50

0x414

USBDRIM(1)(2)

R/W

0x0000.0000

USB Device RESUME
Interrupt Mask

Section 23.6.51

0x418

USBDRISC(1)(2)

W1C

0x0000.0000

USB Device RESUME
Interrupt Status and
Clear

Section 23.6.52

0x41C

USBGPCS(1)(2)

R/W

0x0000.0000

USB General-Purpose
Control and Status

Section 23.6.53

0x450

USBDMASEL(1)(2)

R/W

0x0033.2211

USB DMA Select

Section 23.6.54

(1) This register is used in Device mode. Some registers are used for both Host and Device mode and may have different bit
definitions depending on the mode.
(2) This register is used in Host mode. Some registers are used for both Host and Device mode and may have different bit
definitions depending on the mode. The USB controller is in Device mode upon reset, so the reset values shown for these
registers apply to the Device mode definition.

2472

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6 Register Descriptions
23.6.1 USB Device Functional Address Register (USBFADDR), offset 0x000
The USB function address 8-bit register (USBFADDR) contains the 7-bit address of the device part of the
transaction.
When the USB controller is being used in device mode (the HOST bit in the USBDEVCTL register is
clear), this register must be written with the address received through a SET_ADDRESS command, which
is then used for decoding the function address in subsequent token packets.
Mode(s):

Device

For special considerations when writing this register, see the Setting the Device Address in
Section 23.3.1.1.4.
USBFADDR is shown in Figure 23-3 and described in Table 23-4.
Figure 23-3. Function Address Register (USBFADDR)
7

6

0

Reserved

FUNCADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-4. Function Address Register (USBFADDR) Field Descriptions
Bit
7
6-0

Field
Reserved
FUNCADDR

Value
0
0-7Fh

Description
Reserved
Function Address of Device as received through SET_ADDRESS.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2473

Register Descriptions

www.ti.com

23.6.2 USB Power Management Register (USBPOWER), offset 0x001
The power management 8-bit register (USBPOWER) is used for controlling SUSPEND and RESUME
signaling, and some basic operational aspects of the USB controller.
Mode(s):

Host

Device

USBPOWER in Host Mode is shown in Figure 23-4 and described in Table 23-5.
Figure 23-4. Power Management Register (USBPOWER) in Host Mode
7

4

3

2

1

0

Reserved

RESET

RESUME

SUSPEND

PWRDNPHY

R-0

R/W-0

R/W-0

R/W-1S

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-5. Power Management Register (USBPOWER) in Host Mode Field Descriptions
Bit

Field

7-4

Reserved

3

Value
0

RESET

2

RESET signaling.
Ends RESET signaling on the bus.

1

Enables RESET signaling on the bus.
RESUME signaling. The bit should be cleared by software 20 ms after being set.

0

Ends RESUME signaling on the bus.

1

Enables RESUME signaling when the Device is in SUSPEND mode.

SUSPEND

0

Reserved

0
RESUME

1

Description

SUSPEND mode
0

No effect

1

Enables SUSPEND mode.

PWRDNPHY

Power Down PHY
0

No effect

1

Powers down the internal USB PHY.

USBPOWER in Device Mode is shown in Figure 23-5 and described in Table 23-6.
Figure 23-5. Power Management Register (USBPOWER) in Device Mode
7

6

5

Reserved

SOFTCONN

R/W-0

R/W-0

4

3

2

1

0

Reserved

RESET

RESUME

SUSPEND

PWRDNPHY

R-0

R/W-0

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-6. Power Management Register (USBPOWER) in Device Mode Field Descriptions
Bit

Field

7

Reserved

6

SOFTCONN

5-4
3

2474

Reserved

Value

Description
Reserved
Soft Connect/Disconnect

0

The USB D+/D- lines are tri-stated.

1

The USB D+/D- lines are enabled.

0

Reserved

RESET

RESET signaling
0

Ends RESET signaling on the bus.

1

Enables RESET signaling on the bus.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-6. Power Management Register (USBPOWER) in Device Mode Field Descriptions (continued)
Bit
2

1

0

Field

Value

RESUME

Description
RESUME signaling. The bit should be cleared by software 10 ms (a maximum of 15 ms) after being
set.

0

Ends RESUME signaling on the bus.

1

Enables RESUME signaling when the Device is in SUSPEND mode.

SUSPEND

SUSPEND mode.
0

This bit is cleared when software reads the interrupt register or sets the RESUME bit above.

1

The USB controller is in SUSPEND mode.

PWRDNPHY

Power Down PHY
0

No effect

1

Powers down the internal USB PHY.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2475

Register Descriptions

www.ti.com

23.6.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002
NOTE: Use caution when reading this register. Performing a read may change bit status.

The USB transmit interrupt status 16-bit read-only register (USBTXIS) indicates which interrupts are
currently active for endpoint 0 and the transmit endpoints 1–15. The meaning of the EPn bits in this
register is based on the mode of the device. The EP1 through EP15 bits always indicate that the USB
controller is sending data; however, in Host mode, the bits refer to OUT endpoints; while in Device mode,
the bits refer to IN endpoints. The EP0 bit is special in Host and Device modes and indicates that either a
control IN or control OUT endpoint has generated an interrupt.
Mode(s):

Host

Device

USBTXIS is shown in Figure 23-6 and described in Table 23-7.
Figure 23-6. USB Transmit Interrupt Status Register (USBTXIS)
15
EP15

14
EP14

13
EP13

12
EP12

11
EP11

10
EP10

9
EP9

8
EP8

3
EP3

2
EP2

1
EP1

0
EP0

R-0
7
EP7

6
EP6

5
EP5

4
EP4
R-0

Table 23-7. USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions
Bit

Field

15

EP15

14

13

12

11

10

9

8

2476

Value

Description
TX Endpoint 15 Interrupt

0

No interrupt

1

The Endpoint 15 transmit interrupt is asserted.

EP14

TX Endpoint 14 Interrupt
0

No interrupt

1

The Endpoint 14 transmit interrupt is asserted.

EP13

TX Endpoint 13 Interrupt
0

No interrupt

1

The Endpoint 13 transmit interrupt is asserted.

EP12

TX Endpoint 12 Interrupt
0

No interrupt

1

The Endpoint 12 transmit interrupt is asserted.

EP11

TX Endpoint 11 Interrupt
0

No interrupt

1

The Endpoint 11 transmit interrupt is asserted.

EP10

TX Endpoint 10 Interrupt
0

No interrupt

1

The Endpoint 10 transmit interrupt is asserted.

EP9

TX Endpoint 9 Interrupt
0

No interrupt

1

The Endpoint 9 transmit interrupt is asserted.

EP8

TX Endpoint 8 Interrupt
0

No interrupt

1

The Endpoint 8 transmit interrupt is asserted.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-7. USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions (continued)
Bit

Field

7

EP7

6

5

4

3

2

1

0

Value

Description
TX Endpoint 7 Interrupt

0

No interrupt

1

The Endpoint 7 transmit interrupt is asserted.

EP6

TX Endpoint 6 Interrupt
0

No interrupt

1

The Endpoint 6 transmit interrupt is asserted.

EP5

TX Endpoint 5 Interrupt
0

No interrupt

1

The Endpoint 5 transmit interrupt is asserted.

EP4

TX Endpoint 4 Interrupt
0

No interrupt

1

The Endpoint 4 transmit interrupt is asserted.

EP3

TX Endpoint 3 Interrupt
0

No interrupt

1

The Endpoint 3 transmit interrupt is asserted.

EP2

TX Endpoint 2 Interrupt
0

No interrupt

1

The Endpoint 2 transmit interrupt is asserted.

EP1

TX Endpoint 1 Interrupt
0

No interrupt

1

The Endpoint 1 transmit interrupt is asserted.

EP0

TX and RX Endpoint 0 Interrupt
0

No interrupt

1

The Endpoint 0 transmit and receive interrupt is asserted.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2477

Register Descriptions

www.ti.com

23.6.4 USB Receive Interrupt Status Register (USBRXIS), offset 0x004
NOTE: Use caution when reading this register. Performing a read may change bit status.

The USB receive interrupt status 16-bit read-only register (USBRXIS) indicates which interrupts are
currently active for receive endpoints 1–15.
Note: Bits relating to endpoints that have not been configured always return 0. All active interrupts are
cleared when this register is read.
Mode(s):

Host

Device

USBRXIS is shown in Figure 23-7 and described in Table 23-8.
Figure 23-7. USB Transmit Interrupt Status Register (USBRXIS)
15
EP15

14
EP14

13
EP13

12
EP12

11
EP11

10
EP10

9
EP9

8
EP8

EP3

EP2

EP1

EP0
Reserved

R-0
EP7

EP6

EP5

EP4
R-0

Table 23-8. USB Transmit Interrupt Status Register (USBRXIS) Field Descriptions
Bit

Field

15

EP15

14

13

12

11

10

9

8

7

2478

Value

Description
RX Endpoint 15 Interrupt

0

No interrupt

1

The Endpoint 15 receive interrupt is asserted.

EP14

RX Endpoint 14 Interrupt
0

No interrupt

1

The Endpoint 14 receive interrupt is asserted.

EP13

RX Endpoint 13 Interrupt
0

No interrupt

1

The Endpoint 13 receive interrupt is asserted.

EP12

RX Endpoint 12 Interrupt
0

No interrupt

1

The Endpoint 12 receive interrupt is asserted.

EP11

RX Endpoint 11 Interrupt
0

No interrupt

1

The Endpoint 11 receive interrupt is asserted.

EP10

RX Endpoint 10 Interrupt
0

No interrupt

1

The Endpoint 10 receive interrupt is asserted.

EP9

RX Endpoint 9 Interrupt
0

No interrupt

1

The Endpoint 9 receive interrupt is asserted.

EP8

RX Endpoint 8 Interrupt
0

No interrupt

1

The Endpoint 8 receive interrupt is asserted.

EP7

RX Endpoint 7 Interrupt
0

No interrupt

1

The Endpoint 7 receive interrupt is asserted.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-8. USB Transmit Interrupt Status Register (USBRXIS) Field Descriptions (continued)
Bit

Field

6

EP6

5

4

3

2

1

0

Value

RX Endpoint 6 Interrupt
0

No interrupt

1

The Endpoint 6 receive interrupt is asserted.

EP5

RX Endpoint 5 Interrupt
0

No interrupt

1

The Endpoint 5 receive interrupt is asserted.

EP4

RX Endpoint 4 Interrupt
0

No interrupt

1

The Endpoint 4 receive interrupt is asserted.

EP3

RX Endpoint 3 Interrupt
0

No interrupt

1

The Endpoint 3 receive interrupt is asserted.

EP2

RX Endpoint 2 Interrupt
0

No interrupt

1

The Endpoint 2 receive interrupt is asserted.

EP1

EP0

Description

RX Endpoint 1 Interrupt
0

No interrupt

1

The Endpoint 1 receive interrupt is asserted.
Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2479

Register Descriptions

www.ti.com

23.6.5 USB Transmit Interrupt Enable Register (USBTXIE), offset 0x006
The USB transmit interrupt enable 16-bit register (USBTXIE) provides interrupt enable bits for the
interrupts in the USBTXIS register. When a bit is set, the USB interrupt is asserted to the interrupt
controller when the corresponding interrupt bit in the USBTXIS register is set. When a bit is cleared, the
interrupt in the USBTXIS register is still set but the USB interrupt to the interrupt controller is not asserted.
On reset, all interrupts are enabled.
Mode(s):

Host

Device

USBTXIS is shown in Figure 23-8 and described in Table 23-9.
Figure 23-8. USB Transmit Interrupt Status Enable Register (USBTXIE)
15
EP15

14
EP14

13
EP13

12
EP12

EP7

EP6

EP5

EP4

11
EP11

10
EP10

9
EP9

8
EP8

EP3
R/W-1

EP2
R/W-1

EP1
R/W-1

EP0
R/W-1

R-0
R-0

Table 23-9. USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions
Bit

Field

15

EP15

14

13

12

11

10

9

8

7

6

2480

Value

Description
TX Endpoint 15 Interrupt Enable

0

The EP15 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP15 bit in the USBTXIS register is set.

EP14

TX Endpoint 14 Interrupt Enable
0

The EP14 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP14 bit in the USBTXIS register is set.

EP13

TX Endpoint 13 Interrupt Enable
0

The EP13 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP13 bit in the USBTXIS register is set.

EP12

TX Endpoint 12 Interrupt Enable
0

The EP12 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP12 bit in the USBTXIS register is set.

EP11

TX Endpoint 11 Interrupt Enable
0

The EP11 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP11 bit in the USBTXIS register is set.

EP10

TX Endpoint 10 Interrupt Enable
0

The EP10 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP10 bit in the USBTXIS register is set.

EP9

TX Endpoint 9 Interrupt Enable
0

The EP9 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP9 bit in the USBTXIS register is set.

EP8

TX Endpoint 8 Interrupt Enable
0

The EP8 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP8 bit in the USBTXIS register is set.

EP7

TX Endpoint 7 Interrupt Enable
0

The EP7 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP7 bit in the USBTXIS register is set.

EP6

TX Endpoint 6 Interrupt Enable
0

The EP6 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP6 bit in the USBTXIS register is set.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-9. USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions (continued)
Bit

Field

5

EP5

4

3

2

1

0

Value

Description
TX Endpoint 5 Interrupt Enable

0

The EP5 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP5 bit in the USBTXIS register is set.

EP4

TX Endpoint 4 Interrupt Enable
0

The EP4 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP4 bit in the USBTXIS register is set.

EP3

TX Endpoint 3 Interrupt Enable
0

The EP3 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP3 bit in the USBTXIS register is set.

EP2

TX Endpoint 2 Interrupt Enable
0

The EP2 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP2 bit in the USBTXIS register is set.

EP1

TX Endpoint 1 Interrupt Enable
0

The EP1 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP1 bit in the USBTXIS register is set.

EP0

TX and RX Endpoint 0 Interrupt Enable
0

The EP0 transmit and receive interrupt is suppressed and not sent to the interupt controller.

1

An interrupt is sent to the interrupt controller when the EP0 bit in the USBTXIS register is set.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2481

Register Descriptions

www.ti.com

23.6.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008
The USB receive interrupt enable 16-bit register (USBTXIE) provides interrupt enable bits for the interrupts
in the USBRXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when
the corresponding interrupt bit in the USBRXIS register is set. When a bit is cleared, the interrupt in the
USBRXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, all
interrupts are enabled.
Mode(s):

Host

Device

USBRXIE is shown in Figure 23-9 and described in Table 23-10.
Figure 23-9. USB Transmit Interrupt Status Enable Register (USBRXIE)
15
EP15

14
EP14

13
EP13

12
EP12

EP7

EP6

EP5

EP4

11
EP11

10
EP10

9
EP9

8
EP8

EP3
R/W-1

EP2
R/W-1

EP1
R/W-1

EP0
Reserved

R-0
R-0

Table 23-10. USB Transmit Interrupt Status Register (USBRXIE) Field Descriptions
Bit

Field

15

EP15

14

13

12

11

10

9

8

7

6

2482

Value

Description
RX Endpoint 15 Interrupt Enable

0

The EP15 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP15 bit in the USBRXIS register is set.

EP14

RX Endpoint 14 Interrupt Enable
0

The EP14 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP14 bit in the USBRXIS register is set.

EP13

RX Endpoint 13 Interrupt Enable
0

The EP13 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP13 bit in the USBRXIS register is set.

EP12

RX Endpoint 12 Interrupt Enable
0

The EP12 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP12 bit in the USBRXIS register is set.

EP11

RX Endpoint 11 Interrupt Enable
0

The EP11 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP11 bit in the USBRXIS register is set.

EP10

RX Endpoint 10 Interrupt Enable
0

The EP10 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP10 bit in the USBRXIS register is set.

EP9

RX Endpoint 9 Interrupt Enable
0

The EP9 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP9 bit in the USBRXIS register is set.

EP8

RX Endpoint 8 Interrupt Enable
0

The EP8 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP8 bit in the USBRXIS register is set.

EP7

RX Endpoint 7 Interrupt Enable
0

The EP7 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP7 bit in the USBRXIS register is set.

EP6

RX Endpoint 6 Interrupt Enable
0

The EP6 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP6 bit in the USBRXIS register is set.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-10. USB Transmit Interrupt Status Register (USBRXIE) Field Descriptions (continued)
Bit

Field

5

EP5

4

3

2

1

0

Value

Description
RX Endpoint 5 Interrupt Enable

0

The EP5 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP5 bit in the USBRXIS register is set.

EP4

RX Endpoint 4 Interrupt Enable
0

The EP4 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP4 bit in the USBRXIS register is set.

EP3

RX Endpoint 3 Interrupt Enable
0

The EP3 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP3 bit in the USBRXIS register is set.

EP2

RX Endpoint 2 Interrupt Enable
0

The EP2 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP2 bit in the USBRXIS register is set.

EP1

RX Endpoint 1 Interrupt Enable
0

The EP1 transmit interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the EP1 bit in the USBRXIS register is set.

EP0

TX and RX Endpoint 0 Interrupt Enable
0

The EP0 transmit and receive interrupt is suppressed and not sent to the interupt controller.

1

An interrupt is sent to the interrupt controller when the EP0 bit in the USBRXIS register is set.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2483

Register Descriptions

www.ti.com

23.6.7 USB General Interrupt Status Register (USBIS), offset 0x00A
NOTE: Use caution when reading this register. Performing a Rread may change bit status.

The USB general interrupt status 8-bit read-only register (USBIS) indicates which USB interrupts are
currently active. All active interrupts are cleared when this register is read.
Mode(s):

Host

Device

USBIS in Host Mode is shown in Figure 23-10 and described in Table 23-11.
Figure 23-10. USB General Interrupt Status Register (USBIS) in Host Mode
7

6

5

4

3

2

1

0

VBUSERR

SESREQ

DISCON

CONN

SOF

BABBLE

RESUME

Reserved

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-11. USB General Interrupt Status Register (USBIS) in Host Mode Field Descriptions
Bit
7

6

5

4

3

2

1

0

2484

Field

Value

VBUSERR

VBUS Error
0

No interrupt

1

VBUS has dropped below the VBUS Valid threshold during a session.

SESREQ

Session Request
0

No interrupt

1

SESSION REQUEST signaling has been detected.

DISCON

Session Disconnect
0

No interrupt

1

A Device disconnect has been detected.

CONN

Session Connect
0

No interrupt

1

A Device connection has been detected.

SOF

Start of Frame
0

No interrupt

1

A new frame has started.

BABBLE

Babble Detected
0

No interrupt

1

Babble has been detected. This interrupt is active only after the first SOF has been sent.

RESUME

Reserved

Description

RESUME Signaling Detected. This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC
registers should be used.
0

No effect

1

RESUME signaling has been detected on the bus while the USB controller is in SUSPEND mode.

0

Reserved

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

USBIS in Device Mode is shown in Figure 23-11 and described in Table 23-12.
Figure 23-11. USB General Interrupt Status Register (USBIS) in Device Mode
7

5

4

3

2

1

0

Reserved

6

DISCON

Reserved

SOF

RESET

RESUME

SUSPEND

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-12. USB General Interrupt Status Register (USBIS) in Device Mode Field Descriptions
Bit

Field

7-6

Reserved

5

DISCON

4

Reserved

3

SOF

2

1

0

Value
0

Description
Reserved
Session Disconnect

0

No interrupt

1

The device has been disconnected from the host.

0

Reserved
Start of frame

0

No interrupt

1

A new frame has started.

RESET

RESET Signaling Detected
0

No interrupt

1

RESET signaling has been detected on the bus.

RESUME

RESUME Signaling Detected. This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC
registers should be used.
0

No interrupt

1

RESUME signaling has been detected on the bus while the USB controller is in SUSPEND mode.

SUSPEND

SUSPEND Signaling Detected
0

No interrupt

1

SUSPEND signaling has been detected on the bus.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2485

Register Descriptions

www.ti.com

23.6.8 USB Interrupt Enable Register (USBIE), offset 0x00B
NOTE: Use caution when reading this register. Performing a read may change bit status.

The USB interrupt enable 8-bit register (USBIE) provides interrupt enable bits for each of the interrupts in
USBIS. At reset interrupts 1 and 2 are enabled in device mode.
Mode(s):

Host

Device

USBIE in Host Mode is shown in Figure 23-12 and described in Table 23-13.
Figure 23-12. USB Interrupt Enable Register (USBIE) in Host Mode
7

6

5

4

3

2

1

0

VBUSERR

SESREQ

DISCON

CONN

SOF

BABBLE

RESUME

Reserved

R-W

R-W

R-W

R-W

R-W

R-W

R-W

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-13. USB Interrupt Enable Register (USBIE) in Host Mode Field Descriptions
Bit
7

6

5

4

3

2

1

0

2486

Field

Value

VBUSERR

Enable VBUS Error Interrupt
0

The VBUSERR interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the VBUSERR bit in the USBIS register is set.

SESREQ

Enable Session Request
0

The SESREQ interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the SESREEQ bit in the USBIS register is set.

DISCON

Enable Disconnect Interrupt
0

The DISCON interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set.

CONN

Enable Connect Interrupt
0

The CONN interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the CONN bit in the USBIS register is set.

SOF

Start of Frame
0

The SOF interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set.

BABBLE

Babble Detected
0

The BABBLE interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the BABBLE bit in the USBIS register is set.

RESUME

Reserved

Description

RESUME Signaling Detected. This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC
registers should be used.
0

The RESUME interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set.

0

Reserved

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

USBIE in Device Mode is shown in Figure 23-11 and described in Table 23-12.
Figure 23-13. USB Interrupt Enable Register (USBIE) in Device Mode
7

6

5

4

3

2

1

0

Reserved

DISCON

Reserved

SOF

RESET

RESUME

SUSPEND

R-0

R/W-0

R-0

R/W-0

R/W-1

RW-1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-14. USB Interrupt Enable Register (USBIE) in Device Mode Field Descriptions
Bit

Field

7-6

Reserved

5

DISCON

4

Reserved

3

SOF

2

1

0

Value
0

Description
Reserved
Enable Disconnect Interrupt

0

The DISCON interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set.

0

Reserved
Start of frame

0

The SOF interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set.

RESET

RESET Signaling Detected
0

The RESET interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the RESET bit in the USBIS register is set.

RESUME

RESUME Signaling Detected. This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC
registers should be used.
0

The RESUME interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set.

SUSPEND

SUSPEND Signaling Detected
0

The SUSPEND interrupt is suppressed and not sent to the interrupt controller.

1

An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2487

Register Descriptions

www.ti.com

23.6.9 USB Frame Value Register (USBFRAME), offset 0x00C
The frame number 16-bit read-only register (USBFRAME) holds the last received frame number.
Mode(s):

Host

Device

USBFRAME is shown in Figure 23-14 and described in Table 23-15.
Figure 23-14. Frame Number Register (FRAME)
15

11

10

0

Reserved

FRAME

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 23-15. Frame Number Register (FRAME) Field Descriptions
Bit

Field

15-11

Reserved

10-0

FRAME

Value
0

Description
Reserved

0-7FFh Last received frame number

23.6.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E
Each endpoint buffer can be accessed by configuring a FIFO size and starting address. The endpoint
index 16-bit register (USBEPIDX) is used with the USBTXFIFOSZ, USBRXFIFOSZ, USBTXFIFOADD,
and USBRXFIFOADD registers.
Mode(s):

Host

Device

USBEPIDX is shown in Figure 23-15 and described in Table 23-16.
Figure 23-15. USB Endpoint Index Register (USBEPIDX)
7

4

3

0

Reserved

EPIDX

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-16. USB Endpoint Index Register (USBEPIDX) Field Descriptions
Bit

Field

7-4

Reserved

3-0

EPIDX

2488

Value
0
0-4h

Description
Reserved
Endpoint Index. This bit field configures which endpoint is accessed when reading or writing to one of
the USB controller's indexed registers. A value of 0x0 corresponds to Endpoint 0 and a value of 0xF
corresponds to Endpoint 15.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.11 USB Test Mode Register (USBTEST), offset 0x00F
The USB test mode 8-bit register (USBTEST) is primarily used to put the USB controller into one of the
four test modes for operation described in the USB Specification 2.0 , in response to a SET FEATURE:
USBTESTMODE command. This register is not used in normal operation.
Note: Only one of these bits should be set at any time.
Mode(s):

Host

Device

USBTEST in Host Mode is shown in Figure 23-16 and described in Table 23-17.
Figure 23-16. USB Test Mode Register (USBTEST) in Host Mode
7

6

5

FORCEH

FIFOACC

FORCEFS

R/W-0

R/W1S-0

R/W-0

4

0
Reserved
R-0

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 23-17. USB Test Mode Register (USBTEST) in Host Mode Field Descriptions
Bit

Field

7

Value

FORCEH

6

Force Host Mode. While in this mode, status of the bus connection may be read using the DEV
bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit.
0

No effect

1

Forces the USB controller to enter Host mode when the SESSION bit is set, regardless of
whether the USB controller is connected to any peripheral. The state of the USB0DP and
USB0DM signals is ignored. The USB controller then remains in Host mode until the SESSION
bit is cleared, even if a Device is disconnected. If the FORCEH bit remains set, the USB
controller re-enters Host mode the next time the SESSION bit is set.

FIFOACC

5

FIFO Access
0

No effect

1

Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO.

FORCEFS

4-0

Description

Force Full-Speed Mode

Reserved

0

The USB controller operates at Low Speed.

1

Forces the USB controller into Full-Speed mode upon receiving a USB RESET.

0

Reserved

USBTEST in Device Mode is shown in Figure 23-17 and described in Table 23-18.
Figure 23-17. USB Test Mode Register (USBTEST) in Device Mode
7

6

5

Reserved

FIFOACC

FORCEFS

R-0

R/W1S-0

R/W-0

4

0
Reserved
R-0

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 23-18. USB Test Mode Register (USBTEST) in Device Mode Field Descriptions
Bit

Field

7

Reserved

6

FIFOACC

Value

Description
Force Host Mode. While in this mode, status of the bus connection may be read using the DEV
bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit.
FIFO Access

0

No effect

1

Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2489

Register Descriptions

www.ti.com

Table 23-18. USB Test Mode Register (USBTEST) in Device Mode Field Descriptions (continued)
Bit
5

4-0

2490

Field

Value

FORCEFS

Reserved

Description
Force Full-Speed Mode

0

The USB controller operates at Low Speed.

1

Forces the USB controller into Full-Speed mode upon receiving a USB RESET.

0

Reserved

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[15])
NOTE: Use caution when reading these registers. Performing a read may change bit status.

The USB FIFO endpoint n 32-bit registers (USBFIFO[n]) provide an address for CPU access to the FIFOs
for each endpoint. Writing to these addresses loads data into the Transmit FIFO for the corresponding
endpoint. Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
Transfers to and from FIFOs can be 8-bit, 16-bit or 32-bit as required, and any combination of accesses is
allowed provided the data accessed is contiguous. All transfers associated with one packet must be of the
same width so that the data is consistently byte-, halfword- or word-aligned. However, the last transfer
may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word
transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support either
single-packet or double-packet buffering (see Single-Packet Buffering in Section 23.3.1.1.2). Burst writing
of multiple packets is not supported as flags must be set after each packet is written.
Following a STALL response or a transmit error on endpoint 1–3, the associated FIFO is completely
flushed.
For the specific offset for each FIFO register see Table 23-3.
Mode(s):

Host

Device

USBFIFO0-15 are shown in Figure 23-18 and described in Table 23-19.
Figure 23-18. USB FIFO Endpoint n Register (USBFIFO[n])
31

0
EPDATA
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-19. USB FIFO Endpoint n Register (USBFIFO[n]) Field Descriptions
Bit
31-0

Field
EPDATA

Reset
0x0000.0000

Description
Endpoint Data. Writing to this register loads the data into the Transmit FIFO and reading
unloads data from the Receive FIFO.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2491

Register Descriptions

www.ti.com

23.6.13 USB Device Control Register (USBDEVCTL), offset 0x060
The USB device control 8-bit register (USBDEVCTL) is used for controlling and monitoring the USB VBUS
line. If the PHY is suspended, no PHY clock is received and the VBUS is not sampled. In addition, in Host
mode, USBDEVCTL provides the status information for the current operating mode (Host or Device) of the
USB controller. If the USB controller is in Host mode, this register also indicates if a full- or low-speed
Device has been connected.
Mode(s):

Host

Device

USBDEVCTL is shown in Figure 23-19 and described in Table 23-20.
Figure 23-19. USB Device Control Register (USBDEVCTL)
7

6

5

2

1

0

DEV

FSDEV

LSDEV

4
VBUS

3

HOSTMODE

HOSTREQ

SESSION

R-1

R-0

R-0

R-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-20. USB Device Control Register (USBDEVCTL) Field Descriptions
Bit

Field

7

DEV

Value

Description
Device mode

0

The USB controller is operating on the OTG A side of the cable.

1

The USB controller is operating on the OTG B side of the cable.
Only valid while a session is in progress.

6

5

4-3

2

FSDEV

Full-Speed Device Detected
0

A full-speed Device has not been detected on the port.

1

A full-speed Device has been detected on the port.

LSDEV

VBUS

Low-Speed Device Detected
0

A low-speed Device has not been detected on the port.

1

A low-speed Device has been detected on the port.

0-3h

These read-only bits encode the current VBus level as follows:

0

Below Session End. VBUS is detected as under 0.5 V.

1h

Above Session End, below AValid. VBUS is detected as above 0.5 V and under 1.5 V.

2h

Above AValid, below VBusValid. VBUS is detected as above 1.5 V and below 4.75 V.

3h

Above VBusValid. VBUS is detected as above 4.75 V.

HOSTMODE

This read-only bit is set when the USB controller is acting as a Host.
0

The USB controller is acting as a Device.

1

The USB controller is acting as a Host.
Only valid while a session is in progress.

1

2492

HOSTREQ

When set, the USB controller will initiate the Host Negotiation when Suspend mode is entered. It is
cleared when Host Negotiation is completed.
0

No effect

1

Initiates the Host Negotiation when SUSPENDmode is entered.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-20. USB Device Control Register (USBDEVCTL) Field Descriptions (continued)
Bit
0

Field

Value

SESSION

Description
Session Start/End
When operating as a Host:

0

When cleared by software, this bit ends a session.

1

When set by software, this bit starts a session.
When operating as a Device:

0

The USB controller has ended a session. When the USB controller is in SUSPEND mode, this bit
may be cleared by software to perform a software disconnect.

1

The USB controller has started a session. When set by software, the Session Request Protocol is
initiated.
Clearing this bit when the USB controller is not suspended results in undefined behavior.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2493

Register Descriptions

www.ti.com

23.6.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062
The USB transmit dynamic FIFO sizing 8-bit register (USBTXFIFOSZ) allows the selected TX endpoint
FIFOs to be dynamically sized. USBEPIDX is used to configure each transmit endpoint's FIFO size.
Mode(s):

Host

Device

USBTXFIFOSZ is shown in Figure 23-20 and described in Table 23-21.
Figure 23-20. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ)
7

5

4

3

0

Reserved

DPB

SZ

R-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-21. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) Field Descriptions
Bit

Field

7-5

Reserved

4

3-0

Value
0

DPB

Reserved
Double Packet Buffering Support

0

Single packet buffering is supported.

1

Double packet buffering is enabled.

SZ

Maximum packet size to be allowed. If DPB = 0, the FIFO also is this size; if DPB = 1, the FIFO is twice
this size. Packet size in bytes:
0h

8

1h

16

2h

32

3h

64

4h

128

5h

256

6h

512

7h

1024

8h

2048

9-Fh

2494

Description

Reserved

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063
The USB receive dynamic FIFO sizing 8-bit register (USBRXFIFOSZ) allows the selected RX endpoint
FIFOs to be dynamically sized.
Mode(s):

Host

Device

USBRXFIFOSZ is shown in Figure 23-21 and described in Table 23-22.
Figure 23-21. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ)
7

5

4

3

0

Reserved

DPB

SZ

R-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-22. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) Field Descriptions
Bit

Field

7-5

Reserved

4

3-0

Value
0

DPB

Description
Reserved
Double Packet Buffering Support

0

Single packet buffering is supported.

1

Double packet buffering is enabled.

SZ

Maximum packet size to be allowed. If DPB = 0, the FIFO also is this size; if DPB = 1, the FIFO is twice
this size. Packet size in bytes:
0h

8

1h

16

2h

32

3h

64

4h

128

5h

256

6h

512

7h

1024

8h

2048

9-Fh

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2495

Register Descriptions

www.ti.com

23.6.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064
The USB transmit FIFO start address 16-bit register (USBTXFIFOADD) controls the start address of the
selected transmit endpoint FIFOs.
Mode(s):

Host

Device

USBTXFIFOADDR is shown in Figure 23-22 and described in Table 23-23.
Figure 23-22. USB Transmit FIFO Start Address Register (USBTXFIFOADDR])
15

9

8

0

Reserved

ADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-23. USB Transmit FIFO Start Address Register (USBTXFIFOADDR) Field Descriptions
Bit

Field

15-9

Reserved

8-0

ADDR

Value
0

Reserved
Start Address of the endpoint FIFO in units of 8 bytes.

0h

0

1h

8

2h

16

3h

24

4h

32

5h

40

6h

48

7h

56

8h

64

..

..

1FFh

2496

Description

4095

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066
The USB receive FIFO start address 16-bit register (USBRXFIFOADD) controls the start address of the
selected receive endpoint FIFOs.
Mode(s):

Host

Device

USBRXFIFOADDR is shown in Figure 23-23 and described in Table 23-24.
Figure 23-23. USB Receive FIFO Start Address Register (USBRXFIFOADDR)
15

9

8

0

Reserved

ADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-24. USB Receive FIFO Start Address Register (USBRXFIFOADDR) Field Descriptions
Bit

Field

15-9

Reserved

8-0

ADDR

Value
0

Description
Reserved
Start Address of the endpoint FIFO in units of 8 bytes.

0h

0

1h

8

2h

16

3h

24

4h

32

5h

40

6h

48

7h

56

8h

64

..

..

1FFh

4095

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2497

Register Descriptions

www.ti.com

23.6.18 USB Connect Timing Register (USBCONTIM), offset 0x07A
The USB connect timing 8-bit configuration register (USBCONTIM) specifies connection and negotiation
delays.
Mode(s):

Host

Device

USBCONTIM is shown in Figure 23-24 and described in Table 23-25.
Figure 23-24. USB Connect Timing Register (USBCONTIM)
7

4

3

0

WTCON

WTID

R/W-1

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-25. USB Connect Timing Register (USBCONTIM) Field Descriptions
Bit

Field

7-4

WTCON

5h

The connect wait field configures the wait required to allow for the user’s connect/disconnect filter, in
units of 533.3 ns. The default corresponds to 2.667 μs.

3-0

WTID

Ch

The wait ID field configures the delay required from the enable of the ID detection to when the ID value
is valid, in units of 4.369 ms. The default corresponds to 52.43 ms.

2498

Value

Description

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF),
offset 0x07D
USB full-speed last transaction to end of frame timing 8-bit configuration register (USBFSEOF) specifies
the minimum time gap allowed between the start of the last transaction and the EOF for full-speed
transactions.
Mode(s):

Host

Device

USBFSEOF is shown in Figure 23-25 and described in Table 23-26.
Figure 23-25. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF)
7

0
FSEOFG
R/W-0x77

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-26. USB Full-Speed Last Transaction to End of Frame Timing Register
(USBFSEOF) Field Descriptions
Bit

Field

7-0

FSEOFG

Reset
77h

Description
The full-speed end-of-frame gap field is used during full-speed transactions to configure the gap
between the last transaction and the End-of-Frame (EOF), in units of 533.3 ns. The default corresponds
to 63.46 μs.

23.6.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF),
offset 0x07E
The USB low-speed last transaction to end of frame timing 8-bit configuration register (USBLSEOF)
specifies the minimum time gap that is to be allowed between the start of the last transaction and the EOF
for low-speed transactions.
Mode(s):

Host

Device

USBLSEOF is shown in Figure 23-26 and described in Table 23-27.
Figure 23-26. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF)
7

0
LSEOFG
R/W-0x72

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-27. USB Low-Speed Last Transaction to End of Frame Timing Register
(USBLSEOF) Field Descriptions
Bit

Field

7-0

LSEOFG

Reset
72h

Description
The low-speed end-of-frame gap field is used during low-speed transactions to set the gap between the
last transaction and the End-of-Frame (EOF), in units of 1.067 μs. The default corresponds to 121.6 μs.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2499

Register Descriptions

www.ti.com

23.6.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]USBTXFUNCADDR[15])
The transmit functional address endpoint n 8-bit registers (USBTXFUNCADDR[n]) record the address of
the target function to be accessed through the associated endpoint (EPn). USBTXFUNCADDRx must be
defined for each transmit endpoint that is used.
Note: USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBTXFUNCADDR[n] registers are shown in Figure 23-27 and described in Table 23-28.
Figure 23-27. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n])
7

6

0

Reserved

ADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-28. USB Transmit Functional Address Endpoint n Registers
(USBTXFUNCADDR[n]) Field Descriptions
Bit
7
6-0

2500

Field

Value

Description

Reserved

0

Reserved

ADDR

0

Device Address specifies the USB bus address for the target Device.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]USBTXHUBADDR[15])
The transmit hub address endpoint n 8-bit read/write registers (USBTXHUBADDR[n]), like
USBTXHUBPORT[n], must be written only when a USB device is connected to transmit endpoint EPn via
a USB 2.0 hub. This register records the address of the USB 2.0 hub through which the target associated
with the endpoint is accessed.
Note: USBTXHUBADDR0 is used for both receive and transmit for endpoint 0.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBTXHUBADDR[n] registers are shown in Figure 23-27 and described in Table 23-28.
Figure 23-28. USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[n])
7

6

0

Reserved

ADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-29. USB Transmit Hub Address Endpoint n Registers(USBTXHUBADDR[n])
Field Descriptions
Bit
7
6-0

Field

Value

Description

Reserved

0

Reserved

ADDR

0

Device Address specifies the USB bus address for the target Device.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2501

Register Descriptions

www.ti.com

23.6.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]USBTXHUBPORT[15])
The transmit hub port endpoint n 8-bit read/write registers (USBTXHUBPORT[n]), like
USBTXHUBADDR[n], must be written only when a full- or low-speed Device is connected to transmit
endpoint EPn via a USB 2.0 hub. This register records the port of the USB 2.0 hub through which the
target associated with the endpoint is accessed.
Note: USBTXHUBPORT0 is used for both receive and transmit for endpoint 0.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBTXHUBPORTn registers are shown in Figure 23-29 and described in Table 23-30.
Figure 23-29. USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[n])
7

6

0

Reserved

PORT

R-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-30. USB Transmit Hub Port Endpoint n Registers(USBTXHUBPORT[n])
Field Descriptions
Bit
7
6-0

2502

Field

Value

Description

Reserved

0

Reserved

PORT

0

Hub Port specifies the USB hub port number.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]USBRXFUNCADDR[15])
The recieve functional address endpoint n 8-bit read/write registers (USBRXFUNCADDR[n]) record the
address of the target function to be accessed through the associated endpoint (EPn).
USBRXFUNCADDRx must be defined for each receive endpoint that is used.
Note: USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBRXFUNCADDR[n] registers are shown in Figure 23-30 and described in Table 23-31.
Figure 23-30. USB Receive Functional Address Endpoint n Registers (USBFIFO[n])
7

6

0

Reserved

ADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-31. USB Recieve Functional Address Endpoint n Registers(USBFIFO[n])
Field Descriptions
Bit
7
6-0

Field

Value

Description

Reserved

0

Reserved

ADDR

0

Device Address specifies the USB bus address for the target Device.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2503

Register Descriptions

www.ti.com

23.6.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]USBRXHUBADDR[15])
The receive hub address endpoint n 8-bit read/write registers (USBRXHUBADDR[n]), like [n], must be
written only when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub.
Each register records the address of the USB 2.0 hub through which the target associated with the
endpoint is accessed.
Note: USBTXHUBADDR0 is used for both receive and transmit for endpoint 0.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBRXHUBADDR[n] registers are shown in Figure 23-31 and described in Table 23-32.
Figure 23-31. USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[n])
7

6

0

MULTTRAN

ADDR

R/w-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-32. USB Receive Hub Address Endpoint n Registers(USBRXHUBADDR[n])
Field Descriptions
Bit
7

6-0

2504

Field

Value

MULTTRAN

ADDR

Description
Multiple Translators

0

Clear to indicate that the hub has a single transaction translator.

1

Set to indicate that the hub has multiple transaction translators.

0

Device Address specifies the USB bus address for the target Device.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.26 USB Receive Hub Port Endpoint n Registers (USBRXHUBPORT[1]USBRXHUBPORT[15])
The receive hub port endpoint n 8-bit read/write registers (USBRXHUBPORT[n]), like
USBRXHUBADDR[n], must be written only when a full- or low-speed device is connected to receive
endpoint EPn via a USB 2.0 hub. Each register records the port of the USB 2.0 hub through which the
target associated with the endpoint is accessed.
Note: USBTXHUBPORT0 is used for both receive and transmit for endpoint 0.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBRXHUBPORTn registers are shown in Figure 23-32 and described in Table 23-33.
Figure 23-32. USB Transmit Hub Port Endpoint n Registers (USBRXHUBPORT[n])
7

6

0

Reserved

PORT

R-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-33. USB Transmit Hub Port Endpoint n Registers(USBRXHUBPORT[n])
Field Descriptions
Bit
7
6-0

Field

Value

Description

Reserved

0

Reserved

PORT

0

Hub Port specifies the USB hub port number.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2505

Register Descriptions

www.ti.com

23.6.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[15])
The USB maximum transmit data endpoint n 16-bit registers (USBTXMAXP[n]) define the maximum
amount of data that can be transferred through the selected transmit endpoint in a single operation.
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be
up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk
and interrupt transfers in full-speed operation.
The total amount of data represented by the value written to this register must not exceed the FIFO size
for the transmit endpoint, and must not exceed half the FIFO size if double-buffering is required.
If this register is changed after packets have been sent from the endpoint, the transmit endpoint FIFO
must be completely flushed (using the FLUSH bit in USBTXCSRLn) after writing the new value to this
register.
Note: USBTXMAXP[n] must be set to an even number of bytes for proper interrupt generation in DMA
Basic Mode.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

Device

The USBTXMAXP[n] registers are shown in Figure 23-33 and described in Table 23-34.
Figure 23-33. USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[n])
15

11

10

0

Reserved

MAXLOAD

R-0

R/W-000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-34. USB Maximum Transmit Data Endpoint n Registers(USBTXMAXP[n])
Field Descriptions
Bit

Field

15-11

Reserved

10-0

MAXLOAD

2506

Value
0

Description
Reserved
Maximum Payload specifies the maximum payload in bytes per transaction.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102
The USB control and status endpoint 0 low 8-bit register (USBCSRL0) provides control and status bits for
endpoint 0.
Mode(s):

Host

Device

USBCSRL0 in Host mode is shown in Figure 23-34 and described in Table 23-35.
Figure 23-34. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Host Mode
7

6

5

4

3

2

1

0

NAKTO

STATUS

REQPKT

ERROR

SETUP

STALLED

TXRDY

RXRDY

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-35. USB Control and Status Endpoint 0 Low Register(USBCSRL0)
in Host Mode Field Descriptions
Bit
7

6

Field

Value

NAKTO

Description
NAK Timeout. Software must clear this bit to allow the endpoint to continue.

0

No timeout

1

Indicates that endpoint 0 is halted following the receipt of NAK responses for longer than the time set by
the USBNAKLMT register.

STATUS

Status Packet. Setting this bit ensures that the DT bit is set in the USBCSRH0 register so that a DATA1
packet is used for the STATUS stage transaction.
0

No transaction

1

Initiates a STATUS stage transaction. This bit must be set at the same time as the TXRDY or REQPKT
bit is set.
This bit is automatically cleared when the STATUS stage is over.

5

4

3

2

1

0

REQPKT

Request Packet. This bit is cleared when the RXRDY bit is set.
0

No request

1

Requests an IN transaction.

ERROR

Error. Software must clear this bit.
0

No error

1

Three attempts have been made to perform a transaction with no response from the peripheral. The
EP0 bit in the USBTXIS register is also set in this situation.

SETUP

Setup Packet. Setting this bit always clears the DT bit in the USBCSRH0 register to send a DATA0
packet.
0

Sends an OUT token.

1

Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same
time as the TXRDY bit is set.

STALLED

Endpoint Stalled. Software must clear this bit.
0

No handshake has been received.

1

A STALL handshake has been received.

TXRDY

Transmit Packet Ready. If both the TXRDY and SETUP bits are set, a setup packet is sent. If just
TXRDY is set, an OUT packet is sent.
0

No transmit packet is ready.

1

Software sets this bit after loading a data packet into the TX FIFO. The EP0 bit in the USBTXIS register
is also set in this situation.

RXRDY

Receive Packet Ready. Software must clear this bit after the packet has been read from the FIFO to
acknowledge that the data has been read from the FIFO.
0

No receive packet has been received.

1

Indicates that a data packet has been received in the RX FIFO. The EP0 bit in the USBTXIS register is
also set in this situation.

USBCSRL0 in Device mode is shown in Figure 23-35 and described in Table 23-36.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2507

Register Descriptions

www.ti.com

Figure 23-35. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode
7

6

5

4

3

2

1

0

SETENDC

RXRDYC

STALL

SETEND

DATAEND

STALLED

TXRDY

RXRDY

W1C-0

W1C-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-36. USB Control and Status Endpoint 0 Low Register
(USBCSRL0) in Device Mode Field Descriptions
Bit
7

6

5

Field

Value

SETENDC

Description
Setup End Clear

0

No effect

1

Writing a 1 to this bit clears the SETEND bit.

RXRDYC

RXRDY Clear
0

No effect

1

Writing a 1 to this bit clears the RXRDY bit.

STALL

Send Stall
0

No effect

1

Terminates the current transaction and transmits the STALL handshake.
This bit is cleared automatically after the STALL handshake is transmitted.

4

SETEND

Setup end.
0

A control transaction has not ended or ended after the DATAEND bit was set.

1

A control transaction has ended before the DATAEND bit has been set. The EP0 bit in the USBTXIS
register is also set in this situation.
This bit is cleared by writing a 1 to the SETENDC bit.

3

DATAEND

Data end
0

No effect

1

Set this bit in the following situations:
• When setting TXRDY for the last data packet
• When clearing RXRDY after unloading the last data packet
• When setting TXRDY for a zero-length data packet
This bit is cleared automatically.

2

1

0

STALLED

Endpoint Stalled. Software must clear this bit.
0

A STALL handshake has not been transmitted.

1

A STALL handshake has been transmitted.

TXRDY

Transmit Packet Ready. If both the TXRDY and SETUP bits are set, a setup packet is sent. If just
TXRDY is set, an OUT packet is sent.
0

No transmit packet is ready.

1

Software sets this bit after loading an IN data packet into the TX FIFO. The EP0 bit in the USBTXIS
register is also set in this situation.

RXRDY

Receive Packet Ready
0

No receive packet has been received.

1

A data packet has been received. The EP0 bit in the USBTXIS register is also set in this situation.
This bit is cleared by writing a 1 to the RXRDYC bit.

2508

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103
The USB control and status endpoint 0 high 8-bit register (USBCSRH0) provides control and status bits
for endpoint 0.
Mode(s):

Host

Device

USBCSRH0 in Host mode is shown in Figure 23-36 and described in Table 23-37.
Figure 23-36. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode
7

3

2

1

0

Reserved

DTWE

DT

FLUSH

R-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode Field
Descriptions
Bit

Field

7-3

Reserved

2

Value
0

DTWE

1

Description
Reserved
Data Toggle Write Enable. This bit is automatically cleared once the new value is written.

0

The DT bit cannot be written.

1

Enables the current state of the endpoint 0 data toggle to be written (see DT bit).

DT

Data Toggle. When read, this bit indicates the current state of the endpoint 0 data toggle.
If DTWE is set, this bit may be written with the required setting of the data toggle. If DTWE is Low, this
bit cannot be written. Care should be taken when writing to this bit as it should only be changed to
RESET USB endpoint 0.

0

FLUSH

Flush FIFO. This bit is automatically cleared after the flush is performed.
0

No effect

1

Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and
the TXRDY/RXRDY bit is cleared.
Note: This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be
corrupted.

USBCSRH0 in Device mode is shown in Figure 23-37 and described in Table 23-38.
Figure 23-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode
7

1

0

Reserved

FLUSH

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-38. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode Field
Descriptions
Bit

Field

7-1

Reserved

0

Value
0

FLUSH

Description
Reserved
Flush FIFO. This bit is automatically cleared after the flush is performed.

0

No effect

1

Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and
the TXRDY/RXRDY bit is cleared.
Note: This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be
corrupted.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2509

Register Descriptions

www.ti.com

23.6.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108
The USB receive byte count endpoint 0 8-bit read-only register (USBCOUNT0) indicates the number of
received data bytes in the endpoint 0 FIFO. The value returned changes as the contents of the FIFO
change and is only valid while the RXRDY bit is set.
Mode(s):

Host

Device

USBCOUNT0 is shown in Figure 23-38 and described in Table 23-28.
Figure 23-38. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0)
7

6

0

Reserved

COUNT

R-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-39. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0) Field Descriptions
Bit

Field

7
6-0

Value

Description

Reserved

0

Reserved

COUNT

0

FIFO Count. COUNT is a read-only value that indicates the number of received data bytes in the
endpoint 0 FIFO.

23.6.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A
The USB type endpoint 0 8-bit register (USBTYPE0) must be written with the operating speed of the
targeted Device being communicated with using endpoint 0.
Mode(s):

Host

USBTYPE0 is shown in Figure 23-39 and described in Table 23-40.
Figure 23-39. USB Type Endpoint 0 Register (USBTYPE0)
7

6

5

0

SPEED

Reserved

R/W-0

R-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-40. USB Type Endpoint 0 Register (USBTYPE0) Field Descriptions
Bit

Field

7-6

SPEED

Value
0
0-1h

5-0

2510

Reserved

Description
Operating Speed specifies the operating speed of the target Device. If selected, the target is assumed
to have the same connection speed as the USB controller.
Reserved

2h

Full

3h

Low

0

Reserved

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B
The USB NAK limit 8-bit read-only register (USBNAKLMT) sets the number of frames after which endpoint
0 should time out on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be
made through their USBTXINTERVAL[n] and USBRXINTERVAL[n] registers.)
The number of frames selected is 2(m-1) (where m is the value set in the register, with valid values of
2–16). If the Host receives NAK responses from the target for more frames than the number represented
by the limit set in this register, the endpoint is halted.
Note: A value of 0 or 1 disables the NAK timeout function.
Mode(s):

Host

USBNAKLMT is shown in Figure 23-40 and described in Table 23-41.
Figure 23-40. USB NAK Limit Register (USBNAKLMT)
7

5

4

0

Reserved

NAKLMT

R-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-41. USB NAK Limit Register (USBNAKLMT) Field Descriptions
Bit

Field

7-5

Reserved

Value
0

Description
Reserved

4-0

NAKLMT

0

EP0 NAK Limit specifies the number of frames after receiving a stream of NAK responses.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2511

Register Descriptions

www.ti.com

23.6.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]USBTXCSRL[15])
The USB transmit control and status endpoint n low 8-bit registers (USBTXCSRL[n]) provide control and
status bits for transfers through the currently selected transmit endpoint.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

Device

The USBTXCSRL[n] registers in Host Mode are shown in Figure 23-41 and described in Table 23-42.
Figure 23-41. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host
Mode
7

6

5

4

3

2

1

0

NAKTO

CLRDT

STALLED

SETUP

FLUSH

ERROR

FIFONE

TXRDY

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
in Host Mode Field Descriptions
Bit
7

6

5

4

Field

Value

NAKTO

Description
NAK Timeout. Software must clear this bit to allow the endpoint to continue.

0

No timeout

1

Bulk endpoints only: Indicates that the transmit endpoint is halted following the receipt of NAK
responses for longer than the time set by the NAKLMT field in the USBTXINTERVAL[n] register.

CLRDT

Clear DataToggle
0

No effect

1

Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register.

STALLED

Endpoint Stalled. Software must clear this bit.
0

A STALL handshake has not been received

1

Indicates that a STALL handshake has been received. When this bit is set, any DMA request that is in
progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared.

SETUP

Setup Packet.
0

No SETUP token is sent.

1

Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same
time as the TXRDY bit is set.
Note: Setting this bit also clears the DT bit in the USBTXCSRH[n] register.

3

FLUSH

Flush FIFO. This bit can be set simultaneously with the TXRDY bit to abort the packet that is currently
being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice
to completely clear the FIFO.
0

No effect

1

Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit
is cleared. The EPn bit in the USBTXIS register is also set in this situation.
Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be
corrupted.

2

ERROR

Error. Software must clear this bit.
0

No error

1

Three attempts have been made to send a packet and no handshake packet has been received. The
TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed in
this situation.
Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode.

1

2512

FIFONE

FIFO Not Empty
0

The FIFO is empty

1

At least one packet is in the transmit FIFO.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
in Host Mode Field Descriptions (continued)
Bit

Field

0

Value

TXRDY

Description
Transmit Packet Ready.
This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS
register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.

0

No transmit packet is ready.

1

Software sets this bit after loading a data packet into the TX FIFO.

The USBTXCSRL[n] registers in Device Mode are shown in Table 23-42 and described in Figure 23-42.
Figure 23-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
in Device Mode
7

6

5

4

3

2

1

0

Reserved

CLRDT

STALLED

STALL

FLUSH

UNDRN

FIFONE

TXRDY

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-43. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
in Device Mode Field Descriptions
Bit

Field

7

Reserved

6

CLRDT

5

4

3

Value
0

Description
Reserved
Clear Data Toggle

0

No effect

1

Writing a 1 to this bit clears the DT bit in the USBTXCSRH[n] register.

STALLED

Endpoint Stalled. Software must clear this bit.
0

A STALL handshake has not been transmitted.

1

A STALL handshake has been transmitted. The FIFO is flushed and the TXRDY bit is cleared.

STALL

Send Stall. Software clears this bit to terminate the STALL condition.
0

No effect

1

Issues a STALL handshake to an IN token.

FLUSH

Flush FIFO. This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently
being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice
to completely clear the FIFO.
Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be
corrupted.
0

No effect

1

Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit
is cleared. The EPn bit in the USBTXIS register is also set in this situation.
This bit is cleared automatically.

2

1

UNDRN

Underrun. Software must clear this bit.
0

No underrun

1

An IN token has been received when TXRDY is not set.

FIFONE

FIFO Not Empty
0

The FIFO is empty.

1

At least one packet is in the transmit FIFO.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2513

Register Descriptions

www.ti.com

Table 23-43. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n])
in Device Mode Field Descriptions (continued)
Bit
0

Field

Value

TXRDY

Description
Transmit Packet Ready.
This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS
register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.

0

No transmit packet is ready.

1

Software sets this bit after loading a data packet into the TX FIFO.
This bit is cleared by writing a 1 to the RXRDYC bit.

2514

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]USBTXCSRH[15])
The USB transmit control and status endpoint n high 8-bit registers (USBTXCSRH[n]) provide additional
control for transfers through the currently selected transmit endpoint.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

Device

The USBTXCSRH[n] registers in Host Mode are shown in Figure 23-43 and described in Table 23-44.
Figure 23-43. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
in Host Mode
7

6

5

4

3

2

1

0

AUTOSET

Reserved

MODE

DMAEN

FDT

DMAMOD

DTWE

DT

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
in Host Mode Field Descriptions
Bit
7

Field
AUTOSET

6

Reserved

5

MODE

4

3

Value

Description
Auto Set

0

The TXRDY bit must be set manually.

1

Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in
USBTXMAXP[n]) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is
loaded, then the TXRDY bit must be set manually.

0

Reserved. Any writes to these bit(s) must always have a value of 0.
Mode
Note: This bit only has an effect when the same endpoint FIFO is used for both transmit and receive
transactions.

0

Enables the endpoint direction as RX.

1

Enables the endpoint direction as TX.

DMAEN

DMA Request Enable
Note: Three TX and three /RX endpoints can be connected to the DMA module. If this bit is set for a
particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.
0

Disables the DMA request for the transmit endpoint.

1

Enables the DMA request for the transmit endpoint.

FDT

Force Data Toggle
0

No effect

1

Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of
whether an ACK was received.
Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be
corrupted.

2

DMAMOD

DMA Request Mode
Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.
0

An interrupt is generated after every DMA packet transfer.

1

An interrupt is generated only after the entire DMA transfer is complete.
Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode.

1

DTWE

Data Toggle Write Enable. This bit is automatically cleared once the new value is written.
0

The DT bit cannot be written.

1

Enables the current state of the transmit endpoint data to be written (see DT bit).

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2515

Register Descriptions

www.ti.com

Table 23-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
in Host Mode Field Descriptions (continued)
Bit

Field

0

Value

DT

Description
Data Toggle. When read, this bit indicates the current state of the transmit endpoint data toggle.
If DTWE is High, this bit can be written with the required setting of the data toggle. If DTWE is Low, any
value written to this bit is ignored. Care should be taken when writing to this bit as it should only be
changed to RESET the transmit endpoint.

The USBTXCSRH[n] registers in Device Mode are shown in Figure 23-44 and described in Table 23-45.
Figure 23-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
in Device Mode
7

6

5

4

3

2

AUTOSET

Reserved

MODE

DMAEN

FDT

DMAMOD

1
Reserved

0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-45. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
in Device Mode Field Descriptions
Bit
7

Field

Value

AUTOSET

Description
Auto Set

0

The TXRDY bit must be set manually.

1

Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in
USBTXMAXP[n]) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is
loaded, then the TXRDY bit must be set manually.

6

Reserved

Reserved. Should always have a value of 0.

5

MODE

Mode
Note: This bit only has an effect when the same endpoint FIFO is used for both transmit and receive
transactions.

4

3

2

0

2516

0

Enables the endpoint direction as RX.

1

Enables the endpoint direction as TX.

DMAEN

DMA Request Enable
Note: Three TX and three /RX endpoints can be connected to the DMA module. If this bit is set for a
particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.
0

Disables the DMA request for the transmit endpoint.

1

Enables the DMA request for the transmit endpoint.

FDT

Force Data Toggle
0

No effect

1

Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of
whether an ACK was received.

DMAMOD

Reserved

DMA Request Mode
Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.
0

An interrupt is generated after every DMA packet transfer.

1

An interrupt is generated only after the entire DMA transfer is complete.

0

Reserved

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[15])
The USB maximum receive data endpoint n 16-bit registers (USBRXMAXP[n]) define the maximum
amount of data that can be transferred through the selected receive endpoint in a single operation.
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be
up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk,
interrupt transfers in full-speed operation.
The total amount of data represented by the value written to this register must not exceed the FIFO size
for the transmit endpoint, and must not exceed half the FIFO size if double-buffering is required.
Note: USBRXMAXP[n] must be set to an even number of bytes for proper interrupt generation in DMA
Basic Mode.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

Device

The USBRXMAXP[n] registers are shown in Figure 23-45 and described in Table 23-46.
Figure 23-45. USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[n])
15

11

10

0

Reserved

MAXLOAD

R-0

R/W-000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-46. USB Maximum Receive Data Endpoint n Registers (USBTXMAXP[n]) Field
Descriptions
Bit

Field

Value

Description

15-11

Reserved

0

Reserved

10-0

MAXLOAD

00

Maximum Payload specifies the maximum payload in bytes per transaction.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2517

Register Descriptions

www.ti.com

23.6.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]USBRXCSRL[15)]
The USB receive control and status endpoint n low 8-bit register (USBCSRL[n]) provides control and
status bits for transfers through the currently selected receive endpoint.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

Device

The USBCSRL[n] registers in Host mode are shown in Figure 23-46 and described in Table 23-47.
Figure 23-46. USB Receive Control and Status Endpoint n Low Register (USBCSRL[n])
in Host Mode
2

1

0

CLRDT

7

STALLED

6

REQPKT

5

FLUSH

4

DATAERR /
NAKTO

3

ERROR

FULL

RXRDY

W1C-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-47. USB Control and Status Endpoint n Low Register(USBCSRL[n])
in Host Mode Field Descriptions
Bit
7

6

5

4

3

2

1

2518

Field

Value

NAKTO

Clear Data Toggle.
0

No effect

1

Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register.

STALLED

Endpoint Stalled. Software must clear this bit.
0

No handshake has been received.

1

A STALL handshake has been received. The EPn bit in the USBRXIS register is also set.

REQPKT

Request Packet. This bit is cleared when the RXRDY bit is set.
0

No request

1

Requests an IN transaction.

FLUSH

DATAERR /
NAKTO

Description

Flush FIFO. If the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the
FIFO.
Note:This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be
corrupted.
0

No effect

1

Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the
RXRDY bit is cleared.
Data Error / NAK Timeout

0

Normal operation

1

Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses
for longer than the time set by the NAKLMT field in the USBRXINTERVAL[n] register. Software must
clear this bit to allow the endpoint to continue.

ERROR

Error. Software must clear this bit.
Note: This bit is only valid when the receive endpoint is operating in Bulk or Interrupt mode.
0

No error

1

Three attempts have been made to receive a packet and no data packet has been received. The EPn
bit in the USBRXIS register is set in this situation.

FULL

FIFO Full
0

The receive FIFO is not full.

1

No more packets can be loaded into the receive FIFO.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-47. USB Control and Status Endpoint n Low Register(USBCSRL[n])
in Host Mode Field Descriptions (continued)
Bit

Field

0

Value

RXRDY

Description
Receive Packet Ready.
If the AUTOCLR bit in the USBRXCSRH[n] register is set, then the this bit is automatically cleared when
a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is
clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit
manually when the packet has been unloaded from the receive FIFO.

0

No data packet has been received.

1

Indicates that a data packet has been received. The EPn bit in the USBTXIS register is also set in this
situation.

USBCSRL0 in Device mode is shown in Figure 23-47 and described in Table 23-48.
Figure 23-47. USB Control and Status Endpoint n Low Register (USBCSRL[n])
in Device Mode
7

6

5

4

CLRDT

STALLED

STALL

FLUSH

W1C-0

W1C-0

R/W-0

R-0

3

2
Reserved

R/W-0

R/W-0

1

0

FULL

RXRDY

R/W-0

R-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-48. USB Control and Status Endpoint 0 Low Register(USBCSRL[n])
in Device Mode Field Descriptions
Bit
7

6

5

4

Field

Value

CLRDT

Description
Clear Data Toggle

0

No effect

1

Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register.

STALLED

Endpoint Stalled. Software must clear this bit.
0

A STALL handshake has been transmitted.

1

A STALL handshake has been transmitted.

STALL

Send Stall. Software must clear this bit to terminate the STALL condition.
0

No effect

1

Issues a STALL handshake.

FLUSH

Flush FIFO. The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint receive
FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. Note that if the FIFO is double-buffered,
FLUSH may have to be set twice to completely clear the FIFO.
0

No effect

1

Flushes the next packet from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared.
Note: This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be
corrupted.

3

Reserved

Reserved

2

Reserved

Reserved

1

FULL

0

FIFO Full
0

The receive FIFO is not full.

1

No more packets can be loaded into the receive FIFO.

RXRDY

Receive Packet Ready.
If the AUTOCLR bit in the USBRXCSRH[n] register is set, then the this bit is automatically cleared when
a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is
clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit
manually when the packet has been unloaded from the receive FIFO.
0

No data packet has been received.

1

A data packet has been received. The EPn bit in the USBTXIS register is also set in this situation.
This bit is cleared by writing a 1 to the RXRDYC bit.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2519

Register Descriptions

www.ti.com

23.6.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]USBRXCSRH[15])
The USB receive control and status endpoint n high 8-bit register (USBCSRL[n]) provides additional
control and status bits for transfers through the currently selected receive endpoint.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

Device

The USBCSRH[n] registers in OTG A/Host mode are shown in Figure 23-48 and described in Table 2349.
Figure 23-48. USB Receive Control and Status Endpoint n High Register (USBCSRH[n]) in Host
Mode
7

6

5

4

3

2

1

0

AUTOCL

AUTORQ

DMAEN

Reserved

DMAMOD

DTWE

DT

Reserved

W1C-0

R/W-0

R/W-0

R-0

R/W-0

R-0

R-0

R-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-49. USB Control and Status Endpoint n High Register (USBCSRH[n])
in Host Mode Field Descriptions
Bit
7

6

5

Field

Value

AUTOCL

Description
Auto Clear

0

No effect

1

Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been
unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded,
RXRDY must be cleared manually. Care must be taken when using DMA to unload the receive FIFO as
data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in
the USBRXMAXP[n] register, see Section 23.3.3.

AUTORQ

Auto Request
Note: This bit is automatically cleared when a short packet is received.
0

No effect

1

Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared.

DMAEN

DMA Request Enable
Note: Three TX and three RX endpoints can be connected to the DMA module. If this bit is set for a
particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.
0

Disables the DMA request for the receive endpoint.

1

Enables the DMA request for the receive endpoint.

4

Reserved

Reserved

3

DMAMOD

DMAMOD
Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.

2

0

An interrupt is generated after every DMA packet transfer.

1

An interrupt is generated only after the entire DMA transfer is complete.

DTWE

1

DT

0

Reserved

Data Toggle Write Enable. This bit is automatically cleared once the new value is written.
0

The DT bit cannot be written.

1

Enables the current state of the receive endpoint data to be written (see DT bit).
Data Toggle. When read, this bit indicates the current state of the receive data toggle.
If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any
value written to this bit is ignored. Care should be taken when writing to this bit as it should only be
changed to RESET the receive endpoint.

0

Reserved

The USBCSRH[n] registers in Device mode are shown in Figure 23-49 and described in Table 23-50.

2520

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Figure 23-49. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Device Mode
7

6

5

4

3

2

0

AUTOCL

Reserved

DMAEN

DISNYET /
PIDERR

DMAMOD

Reserved

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-50. USB Control and Status Endpoint 0 High Register(USBCSRH[n])
in Device Mode Field Descriptions
Bit
7

Field

Value

AUTOCL

Description
Auto Clear

0

No effect

1

Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been
unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded,
RXRDY must be cleared manually. Care must be taken when using DMA to unload the receive FIFO as
data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in
the USBRXMAXP[n] register, see Section 23.3.3.

6

Reserved

Reserved

5

DMAEN

DMA Request Enable
Note: Three TX and three RX endpoints can be connected to the DMA module. If this bit is set for a
particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.

4

3

0

DISNYET/PI
DERR

0

Disables the DMA request for the receive endpoint.

1

Enables the DMA request for the receive endpoint.
Disable NYET / PID Error

0

No effect

1

For bulk or interrupt transactions: Disables the sending of NYET handshakes. When this bit is set, all
successfully received packets are acknowledged, including at the point at which the FIFO becomes full.

DMAMOD

Reserved

DMA Request Mode
Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.
0

An interrupt is generated after every DMA packet transfer.

1

An interrupt is generated only after the entire DMA transfer is complete.

0

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2521

Register Descriptions

www.ti.com

23.6.38 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[15])
The USB receive byte count endpoint n 16-bit read-only registers hold the number of data bytes in the
packet currently in line to be read from the receive FIFO. If the packet is transmitted as multiple bulk
packets, the number given is for the combined packet.
Note: The value returned changes as the FIFO is unloaded and is only valid while the RXRDY bit in the
USBRXCSRLn register is set.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

Device

The USBRXCOUNT[n] registers are shown in Figure 23-50 and described in Table 23-51.
Figure 23-50. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n])
15

13

12

0

Reserved

COUNT

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-51. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n])
Field Descriptions
Bit

Field

15-13

Reserved

12-0

COUNT

2522

Value
0

Description
Reserved
Receive Packet Count indicates the number of bytes in the receive packet.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.39 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]USBTXTYPE[15])
The USB host transmit configure type endpoint n 8-bit registers (USBTXTYPE[n]) must be written with the
endpoint number to be targeted by the endpoint, the transaction protocol to use for the currently selected
transmit endpoint, and its operating speed.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBTXTYPE[n] registers are shown in Figure 23-51 and described in Table 23-52.
Figure 23-51. USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[n])
7

6

5

4

3

0

SPEED

PROTO

TEP

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-52. USB Host Transmit Configure Type Endpoint n Register(USBTXTYPE[n])
Field Descriptions
Bit

Field

7-6

SPEED

5-4

3-0

Value

Operating Speed. This bit field specifies the operating speed of the target Device:
0h

Default. The target is assumed to be using the same connection speed as the USB controller.

1h

Reserved

2h

Full

3h

Low

PROTO

TEP

Description

Protocol. Software must configure this bit field to select the required protocol for the transmit endpoint:
0h

Control

1h

Reserved

2h

Bulk

3h

Interrupt

0

Target Endpoint Number. Software must configure this value to the endpoint number contained in the
transmit endpoint descriptor returned to the USB controller during Device enumeration.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2523

Register Descriptions

www.ti.com

23.6.40 USB Host Transmit Interval Endpoint n Register
(USBTXINTERVAL[1]USBTXINTERVAL[15])
The USB host transmit interval endpoint n 8-bit registers (USBTXINTERVAL[n]), for interrupt transfers,
define the polling interval for the currently selected transmit endpoint. For bulk endpoints, this register
defines the number of frames after which the endpoint should time out on receiving a stream of NAK
responses.
The USBTXINTERVAL[n] registers values define a number of frames, as follows:
Table 23-53. USBTXINTERVAL[n] Frame Numbers
Transfer Type
Interrupt

Speed

Valid Values (m)

Low-speed or Full-speed

0x01-0xFF

The polling interval is m frames.

Full-speed

0x02-0x10

The NAK Limit is 2(m-1) frames. A value of 0 or 1
disables the NAK timeout function.

Bulk

Interpretation

For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBTXINTERVAL[n] registers are shown in Figure 23-51 and described in Table 23-52.
Figure 23-52. USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[n])
7

0
TXPOLL / NAKLMT
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-54. USB Host Transmit Interval Endpoint n Register(USBTXINTERVAL[n])
Field Descriptions
Bit

Field

7-0

TXPOLL /
NAKLMT

2524

Value
0

Description
TX Polling / NAK Limit The polling interval for interrupt transfers; the NAK limit for bulk transfers. See
Table 23-53 for valid entries; other values are reserved.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]USBRXTYPE[15])
The USB host configure receive type endpoint n 8-bit registers (USBRXTYPE[n]) must be written with the
endpoint number to be targeted by the endpoint, the transaction protocol to use for the currently selected
receive endpoint, and its operating speed.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBRXTYPE[n] registers are shown in Figure 23-53 and described in Table 23-55.
Figure 23-53. USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[n])
7

6

5

4

3

0

SPEED

PROTO

TEP

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-55. USB Host Configure Receive Type Endpoint n Register(USBRXTYPE[n])
Field Descriptions
Bit

Field

7-6

SPEED

5-4

3-0

Value

Operating Speed. This bit field specifies the operating speed of the target Device:
0h

Default. The target is assumed to be using the same connection speed as the USB controller.

1h

Reserved

2h

Full

3h

Low

PROTO

TEP

Description

Protocol. Software must configure this bit field to select the required protocol for the receive endpoint:
0h

Control

1h

Reserved

2h

Bulk

3h

Interrupt

0

Target Endpoint Number. Software must configure this value to the endpoint number contained in the
transmit endpoint descriptor returned to the USB controller during Device enumeration.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2525

Register Descriptions

www.ti.com

23.6.42 USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[1]USBRXINTERVAL[15])
The USB host receive polling interval endpoint n 8-bit registers (USBRXINTERVAL[n]), for interrupt
transfers, define the polling interval for the currently selected transmit endpoint. For bulk endpoints, this
register defines the number of frames after which the endpoint should time out on receiving a stream of
NAK responses.
The USBRXINTERVAL[n] registers values define a number of frames, as follows:
Table 23-56. USBRXINTERVAL[n] Frame Numbers
Transfer Type
Interrupt

Speed

Valid Values (m)

Low-speed or Full-speed

0x01-0xFF

The polling interval is m frames.

Full-speed

0x02-0x10

The NAK Limit is 2(m-1) frames. A value of 0 or 1
disables the NAK timeout function.

Bulk

Interpretation

For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBRXINTERVAL[n] registers are shown in Figure 23-51 and described in Table 23-52.
Figure 23-54. USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[n])
7

0
TXPOLL / NAKLMT
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-57. USB Host Receive Polling Interval Endpoint n Register(USBRXINTERVAL[n])
Field Descriptions
Bit

Field

7-0

TXPOLL /
NAKLMT

2526

Value
0

Description
TX Polling / NAK Limit The polling interval for interrupt transfers, the NAK limit for bulk transfers. See
Table 23-56 for valid entries; other values are reserved.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.43 USB Request Packet Count in Block Transfer Endpoint n Registers
(USBRQPKTCOUNT[1]-USBRQPKTCOUNT[15])
The USB receive packet count in block transfer endpoint n 16-bit read/writer registers are used in Host
mode to specify the number of packets that are to be transferred in a block transfer of one or more bulk
packets to receive endpoint n. The USB controller uses the value recorded in this register to determine the
number of requests to issue where the AUTORQ bit in the USBRXCSRH[n] register has been set. For
more information about IN transactions as a host, see Section 23.3.2.2.
Note: Multiple packets combined into a single bulk packet within the FIFO count as one packet.
For the specific offset for each register see Table 23-3.
Mode(s):

Host

The USBRQPKTCOUNT[n] registers are shown in Figure 23-55 and described in Table 23-58.
Figure 23-55. USB Request Packet Count in Block Transfer Endpoint n Registers
(USBRQPKTCOUNT[n])
15

13

12

0

Reserved

COUNT

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-58. USB Request Packet Count in Block Transfer Endpoint n Registers
(USBRQPKTCOUNT[n]) Field Descriptions
Bit

Field

15-13

Reserved

12-0

COUNT

Value
0

Description
Reserved
Block Transfer Packet Count sets the number of packets of the size defined by the MAXLOAD bit field
that are to be transferred in a block transfer.
Note: This is only used in Host mode when AUTORQ is set. The bit has no effect in Device mode or
when AUTORQ is not set.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2527

Register Descriptions

www.ti.com

23.6.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset
0x340
The USB receive double packet buffer disable 16-bit register (USBTXIE) indicates which of the receive
endpoints have disabled the double-packet buffer functionality (see Double-Packet Buffering in
Section 23.3.1.1.1).
Mode(s):

Host

Device

USBRXDPKTBUFDIS is shown in Figure 23-56 and described in Table 23-59.
Figure 23-56. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS)
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

EP15

EP14

EP13

EP312

EP11

EP10

EP9

EP8

EP7

EP6

EP5

EP4

EP3

EP2

EP1

Rsvd

R/W-1

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-59. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) Field
Descriptions
Bit

Field

15

EP15

14

13

12

11

10

9

8

7

6

2528

Value

Description
EP15 RX Double-Packet Buffer Disable

0

DEnables double-packet buffering.

1

Disables double-packet buffering.

EP14

EP14 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP13

EP13 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP12

EP12 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP11

EP11 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP10

EP10 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP9

EP9 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP8

EP8 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP7

EP7 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP6

EP6 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-59. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) Field
Descriptions (continued)
Bit

Field

5

EP5

4

3

2

1

0

Value

EP5 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP4

EP4 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP3

EP3 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP2

EP2 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP1

EP0

Description

EP1 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.
Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2529

Register Descriptions

www.ti.com

23.6.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset
0x342
The USB transmit double packet buffer disable 16-bit register (USBTXIE) indicates which of the transmit
endpoints have disabled the double-packet buffer functionality (see Double-Packet Buffering in
Section 23.3.1.1.1).
Mode(s):

Host

Device

USBTXDPKTBUFDIS is shown in Figure 23-57 and described in Table 23-60.
Figure 23-57. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS)
15

3

2

1

0

Reserved

4

EP3

EP2

EP1

Rsvd

R-0

R/W-1

R/W-1

R/W-1

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-60. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS)
Field Descriptions
Bit
15-4
3

2

1

0

2530

Field

Value

Reserved

Reserved

EP3

EP3 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP2

EP2 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

EP1

Reserved

Description

EP1 RX Double-Packet Buffer Disable
0

Enables double-packet buffering.

1

Disables double-packet buffering.

0

Reserved

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.46 USB External Power Control Register (USBEPC), offset 0x400
The USB external power control 32-bit register (USBEPC) specifies the function of the two-pin external
power interface (USB0EPEN and USB0PFLT). The assertion of the power fault input may generate an
automatic action, as controlled by the hardware configuration registers. The automatic action is necessary
because the fault condition may require a response faster than one provided by firmware.
Mode(s):

Host

Device

USBEPC is shown in Figure 23-58 and described in Table 23-61.
Figure 23-58. USB External Power Control Register (USBEPC)
31

16
Reserved
R-0
15

10

9

8

Reserved

PFLTACT

R-0

R/W-0

7

6

5

4

3

2

Reserved

PFLTAEN

PFLTSEN

PFLTEN

Reserved

EPENDE

1
EPEN

0

R-0

R/W-0

R/W-0

R/W-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 23-61. USB External Power Control Register (USBEPC) Field Descriptions
Bit

Field

31-10

Reserved

9-8

PFLTACT

7

Reserved

6

PFLTAEN

5

4

3

Value
0

Reserved
Power Fault Action. This bit field specifies how the USB0EPEN signal is changed when detecting a
USB power fault.

0h

Unchanged. USB0EPEN is controlled by the combination of the EPEN and EPENDE bits.

1h

Tristate. USB0EPEN is undriven (tristate).

2h

Low. USB0EPEN is driven Low.

3h

High. USB0EPEN is driven High.

0

Reserved
Power Fault Action Enable. This bit specifies whether a USB power fault triggers any automatic
corrective action regarding the driven state of the USB0EPEN signal.

0

Disabled. USB0EPEN is controlled by the combination of the EPEN and EPENDE bits.

1

Enabled. The USB0EPEN output is automatically changed to the state specified by the PFLTACT field.

PFLTSEN

Power Fault Sense. This bit specifies the logical sense of the USB0PFLT input signal that indicates an
error condition.
The complementary state is the inactive state.
0

Low Fault. If USB0PFLT is driven Low, the power fault is signaled internally (if enabled by the PFLTEN
bit).

1

High Fault. If USB0PFLT is driven High, the power fault is signaled internally (if enabled by the PFLTEN
bit).

PFLTEN

Reserved

Description

Power Fault Input Enable. This bit specifies whether the USB0PFLT input signal is used in internal
logic.
0

Not Used. The USB0PFLT signal is ignored.

1

Used. The USB0PFLT signal is used internally

0

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2531

Register Descriptions

www.ti.com

Table 23-61. USB External Power Control Register (USBEPC) Field Descriptions (continued)
Bit
2

1-0

2532

Field

Value

EPENDE

Description
EPEN Drive Enable. This bit specifies whether the USB0EPEN signal is driven or undriven (tristate).
When driven, the signal value is specified by the EPEN field. When not driven, the EPEN field is
ignored and the USB0EPEN signal is placed in a high-impedance state.
The USB0EPEN signal is undriven at reset because the sense of the external power supply enable is
unknown. By adding the high-impedance state, system designers can bias the power supply enable to
the disabled state using a large resistor (100 kΩ) and later configure and drive the output signal to
enable the power supply.

0

Not Driven. The USB0EPEN signal is high impedance.

1

Driven. The USB0EPEN signal is driven to the logical value specified by the value of the EPEN field.

EPEN

External Power Supply Enable Configuration. This bit field specifies and controls the logical value driven
on the USB0EPEN signal.
0h

Power Enable Active Low. The USB0EPEN signal is driven Low if the EPENDE bit is set.

1h

Power Enable Active High. The USB0EPEN signal is driven High if the EPENDE bit is set.

2h

Power Enable High if VBUS Low. The USB0EPEN signal is driven High when the A device is not
recognized.

3h

Power Enable High if VBUS High. The USB0EPEN signal is driven High when the A device is
recognized.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404
The USB external power control raw interrupt status 32-bit register (USBEPCRIS) specifies the unmasked
interrupt status of the two-pin external power interface.
Mode(s):

Host

Device

USBEPCRIS is shown in Figure 23-59 and described in Table 23-62.
Figure 23-59. USB External Power Control Raw Interrupt Status Register (USBEPCRIS)
31

1

0

Reserved

PF

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-62. USB External Power Control Raw Interrupt Status Register (USBEPCRIS) Field
Descriptions
Bit
31-1
0

Field
Reserved

Value
0

PF

Description
Reserved
USB Power Fault Interrupt Status.
This bit is cleared by writing a 1 to the PF bit in the USBEPCISC register.

0

A Power Fault status has been detected.

1

An interrupt has not occurred.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2533

Register Descriptions

www.ti.com

23.6.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408
The USB external power control interrupt mask 32-bit register (USBEPCIM) specifies the interrupt mask of
the two-pin external power interface.
Mode(s):

Host

Device

USBEPCIM is shown in Figure 23-59 and described in Table 23-62.
Figure 23-60. USB External Power Control Interrupt Mask Register (USBEPCIM)
31

1

0

Reserved

PF

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-63. USB External Power Control Interrupt Mask Register (USBEPCIM) Field Descriptions
Bit
31-1
0

2534

Field
Reserved

Value
0

PF

Description
Reserved
USB Power Fault Interrupt Mask.

0

The raw interrupt signal from a detected power fault is sent to the interrupt controller.

1

A detected power fault does not affect the interrupt status.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC),
offset 0x40C
The USB external power control interrupt status and clear 32-bit register (USBEPCISC) specifies the
unmasked interrupt status of the two-pin external power interface.
Mode(s):

Host

Device

USBEPCISC is shown in Figure 23-61 and described in Table 23-64.
Figure 23-61. USB External Power Control Interrupt Status and Clear Register (USBEPCISC)
31

1

0

Reserved

PF

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-64. USB External Power Control Interrupt Status and
Clear Register (USBEPCISC) Field Descriptions
Bit
31-1
0

Field
Reserved

Value
0

PF

Description
Reserved. Reset is 0x0000.000.
USB Power Fault Interrupt Status and Clear.
This bit is cleared by writing a 1. Clearing this bit also clears the PF bit in the USBEPCISC register.

0

The PF bits in the USBEPCRIS and USBEPCIM registers are set, providing an interrupt to the interrupt
controller.

1

No interrupt has occurred or the interrupt is masked.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2535

Register Descriptions

www.ti.com

23.6.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410
The USB device RESUME raw interrupt status register (USBDRRIS) is the raw interrupt status register.
On a read, this register gives the current raw status value of the corresponding interrupt prior to masking.
A write has no effect.
Mode(s):

Host

Device

USBDRRIS is shown in Figure 23-62 and described in Table 23-65.
Figure 23-62. USB Device RESUME Raw Interrupt Status Register (USBDRRIS)
31

1

0

Reserved

RESUME

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-65. USB Device RESUME Raw Interrupt
Status Register (USBDRRIS) Field Descriptions
Bit
31-1
0

2536

Field
Reserved

Value
0

PF

Description
Reserved. Reset is 0x0000.000.
RESUME Interrupt Status
This bit is cleared by writing a 1 to the RESUME bit in the USBDRISC register.

0

A RESUME status has been detected.

1

An interrupt has not occurred.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414
The USB device RESUME raw interrupt status register (USBDRIM) is the masked interrupt status register.
On a read, this register gives the current masked status value of the corresponding interrupt. A write has
no effect.
Mode(s):

Host

Device

USBDRIM is shown in Figure 23-63 and described in Table 23-66.
Figure 23-63. USB Device RESUME Raw Interrupt Status Register (USBDRRIS)
31

1

0

Reserved

RESUME

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-66. USB Device RESUME Raw Interrupt
Status Register (USBDRRIS) Field Descriptions
Bit
31-1
0

Field
Reserved

Value
0

PF

Description
Reserved. Reset is 0x0000.000.
RESUME Interrupt Mask

0

The raw interrupt signal from a detected RESUME is sent to the interrupt controller. This bit should only
be set when a SUSPEND has been detected (the SUSPEND bit in the USBIS register is set).

1

A detected RESUME does not affect the interrupt status.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2537

Register Descriptions

www.ti.com

23.6.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418
The USB device RESUME interrupt status and clear register (USBDRRIS) is the raw interrupt clear
register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
Mode(s):

Host

Device

USBDRISC is shown in Figure 23-64 and described in Table 23-67.
Figure 23-64. USB Device RESUME Interrupt Status and Clear Register (USBDRISC)
31

1

0

Reserved

RESUME

R-0

R/W1C

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-67. USB Device RESUME Interrupt Status and Clear Register (USBDRISC)
Field Descriptions
Bit

Field

31-1

Reserved

0

RESUME

2538

Value
0

Description
Reserved. Reset is 0x0000.000.
RESUME Interrupt Status and Clear.
This bit is cleared by writing a 1. Clearing this bit also clears the RESUME bit in the USBDRCRIS
register.

0

The RESUME bits in the USBDRRIS and USBDRCIM registers are set, providing an interrupt to the
interrupt controller.

1

No interrupt has occurred or the interrupt is masked.

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

23.6.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C
The USB general-purpose control and status register (USBGPCS) provides the state of the internal ID
signal.
When the USB controller is used as either a dedicated Host or Device, the DEVMODOTG and DEVMOD
bits in the USB General-Purpose Control and Status (USBGPCS) register should be used to connect the
ID inputs to fixed levels internally. For proper self-powered device operation, the VBUS value must be
monitored to assure that if the Host removes VBUS, the self-powered device disables the D+/D- pull-up
resistors. This function can be accomplished by connecting a standard GPIO to VBUS.
Mode(s):

Host

Device

USBGPCS is shown in Figure 23-65 and described in Table 23-68.
Figure 23-65. USB General-Purpose Control and Status Register (USBGPCS)
31

1

0

Reserved

2

DEVMODOTG

DEVMOD

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-68. USB General-Purpose Control and Status
Register (USBGPCS) Field Descriptions
Bit
31-2
1

0

Field
Reserved

Value
0

DEVMODOT
G

Description
Reserved. Reset is 0x0000.000.
Enable Device Mode. This bit enables the DEVMOD bit to control the state of the internal ID signal in
OTG mode.

0

The mode is specified by the state of the internal ID signal.

1

This bit enables the DEVMOD bit to control the internal ID signal.

DEVMOD

Device Mode This bit specifies the state of the internal ID signal in Host mode and in OTG mode when
the DEVMODOTG bit is set.
In Device mode this bit is ignored (assumed set).
0

Host mode

1

Device mode

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2539

Register Descriptions

www.ti.com

23.6.54 USB DMA Select Register (USBDMASEL), offset 0x450
The USB DMA select 32-bit register (USBDMASEL) specifies whether the unmasked interrupt status of
the ID value is valid.
Mode(s):

Host

Device

USBDMASEL is shown in Figure 23-66 and described in Table 23-69.
Figure 23-66. USB DMA Select Register (USBDMASEL)
31

24

15

23

20

19

16

Reserved

DMACTX

DMACRX

R/0

R/W-0

R/W-0

12

11

8

7

4

3

0

DMABTX

DMABRX

DMAATX

DMAARX

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-69. USB DMA Select Register (USBDMASEL) Field Descriptions
Bit

Field

31-24

Reserved

23-20

DMACTX

19-16

15-12

2540

Value
0

Description
Reserved. Reset is 0x0000.000.
DMA C TX Select specifies the TX mapping of the third USB endpoint on DMA channel 5 (primary
assignment).

0h

Reserved

1h

Endpoint 1 TX

2h

Endpoint 2 TX

3h

Endpoint 3 TX

4h
...
15h

Endpoint 4 TX
...
Endpoint 15 TX

DMACRX

DMA C RX Select specifies the RX and TX mapping of the third USB endpoint on DMA channel 4
(primary assignment).
0h

Reserved

1h

Endpoint 1 RX

2h

Endpoint 2 RX

3h

Endpoint 3 RX

4h
...
15h

Endpoint 4 TX
...
Endpoint 15 TX

DMABTX

DMA B TX Select specifies the TX mapping of the second USB endpoint on DMA channel 3 (primary
assignment).
0h

Reserved

1h

Endpoint 1 TX

2h

Endpoint 2 TX

3h

Endpoint 3 TX

4h
...
15h

Endpoint 4 TX
...
Endpoint 15 TX

Universal Serial Bus (USB) Controller

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Register Descriptions

www.ti.com

Table 23-69. USB DMA Select Register (USBDMASEL) Field Descriptions (continued)
Bit
11-8

7-4

3-1

Field

Value

DMABRX

Description
DMA B RX Select Specifies the RX mapping of the second USB endpoint on DMA channel 2 (primary
assignment).

0h

Reserved

1h

Endpoint 1 RX

2h

Endpoint 2 RX

3h

Endpoint 3 RX

4h
...
15h

Endpoint 4 TX
...
Endpoint 15 TX

DMAATX

DMA A TX Select specifies the TX mapping of the first USB endpoint on DMA channel 1 (primary
assignment).
0h

Reserved

1h

Endpoint 1 TX

2h

Endpoint 2 TX

3h

Endpoint 3 TX

4h
...
15h

Endpoint 4 TX
...
Endpoint 15 TX

DMAARX

DMA A RX Select specifies the RX mapping of the first USB endpoint on DMA channel 0 (primary
assignment).
0h

Reserved

1h

Endpoint 1 RX

2h

Endpoint 2 RX

3h

Endpoint 3 RX

4h

Endpoint 4 RX

5h

Endpoint 5 RX

6h

Endpoint 6 RX

7h

Endpoint 7 RX

8h

Endpoint 8 RX

9h

Endpoint 9 RX

10h

Endpoint 10 RX

11h

Endpoint 11 RX

12h

Endpoint 12 RX

13h

Endpoint 13 RX

14h

Endpoint 14RX

15h

Endpoint 15 RX

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Universal Serial Bus (USB) Controller

Copyright © 2013–2017, Texas Instruments Incorporated

2541

Chapter 24
SPRUHM8G – December 2013 – Revised September 2017

Universal Parallel Port (uPP)
This chapter discusses the features and functions of the Universal Parallel Port module (uPP).
Topic

24.1
24.2
24.3
24.4
24.5

2542

...........................................................................................................................
Introduction ...................................................................................................
Configuring Device Pins ..................................................................................
Functional Description ....................................................................................
IO Interface and System Requirements ..............................................................
Registers .......................................................................................................

Universal Parallel Port (uPP)

Page

2543
2544
2544
2547
2557

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

24.1 Introduction
The universal parallel port (uPP) peripheral is a high-speed parallel interface with dedicated data lines and
minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters
(ADCs) or digital-to-analog converters (DACs) with 8-bit data width. It can also be interconnected with
field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer.
It can operate in receive mode or transmit mode (simplex mode).
This peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead
during high-speed data transmission. All uPP transactions uses internal DMA to feed data to or retrieve
data from the I/O channels. Even though there is only one I/O channel, DMA controller includes two DMA
channels to supports data interleave mode, in which all DMA resources service a single I/O channel.
On this device, uPP is dedicated resource for CPU1 subsystem and CPU1, CPU1.CLA1 and CPU1.DMA
have access to this module. There are two dedicated DATA RAMs (also known as MSG RAMs), each of
512B, tightly coupled with uPP module (one for each, TX and RX). These DATA RAMs are used to store
bulk of data to avoid frequent interruption to CPU. Only CPU1 and CPU1.CLA1 has access to these DATA
RAMs. Figure 24-1 shows the integration of uPP on this device.
Figure 24-1. uPP Integration
CPU1
Arbi
Arbiter Y
CPU1.CLA1

READ

t

RX-DATARAM
512 Byte
(Dual Port
Memory)

uPP DMA WRITE

CPU1
Arbi
Arbiter X
CPU1.CLA1

0

CPU1.DMA

1

uPP
(Universal
Parallel Port)

t

I/O Interface

uPP DMA READ

SECMSEL.PF2SEL
CPU1
Arbi
Arbiter Y
CPU1.CLA1

t

WRITE

TX-DATARAM
512 Byte
(Dual Port
Memory)

NOTE: In some other TI devices, uPP IP is also called the Radio Peripheral Interface (RPI) module.

24.1.1 Features Supported
•
•
•
•
•
•
•

Supports mainstream high-speed data converters with parallel conversion interface.
Supports mainstream high-speed streaming interface with frame START indication.
Supports mainstream high-speed streaming interface with data ENABLE indication.
Supports mainstream high-speed streaming interface with synchronization WAIT signal.
Supports SDR (single-data-rate) or DDR (double-data-rate, interleaved) interface.
Supports multiplexing of interleaved data in SDR transmit case.
Supports de-multiplexing and multiplexing of interleaved data in DDR case.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2543

Configuring Device Pins

•
•
•
•

www.ti.com

Supports I/O interface clock frequency up to 50 MHz for SDR case, and 25 MHz for DDR.
Supports single-channel 8-bit input receive or output transmit mode.
Max throughput is 50MB/s for pure read or pure write.
Available as a DSP to FPGA general purpose streaming interface.

24.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.

24.3 Functional Description
24.3.1 Functional Block Diagram
Figure 24-2. Functional Block Diagram
uPP
Configuration
I/F

MMR
Transmit Timing
and Control

ENABLE OUT

G

START OUT

P

WAIT IN

ENABLE/GPIOx

I
O

CPU1.SYSCLK

CLK OUT

CLKDIVIDER

CLK IN

START/GPIOx
M
U

ENABLE IN
Control Mux

Interrupt/Trigger

Receive Timing
and Control

X

WAIT/GPIOx

START IN
WAIT OUT

and
CLK/GPIOx
I/O

Arbi
I-FIFO
t

64 Bit

C
O

MEM WR I/F

DATA OUT
Internal

Data Interleaving

DMA
Arbit

DATA IN

(TX/RX)

DATA[7:0]/GPIOx

T
R
O

64 Bit
MEM RD I/F

N

L

Arbi
Q-FIFO

The uPP IP supports internal FIFO to store the data to and from IOs. To alleviate the load of data transfer
from system memory to and from the uPP FIFOs, the IP supports internal DMA. The internal DMA has two
channels: channel I and channel Q.

24.3.2 Data Flow
The following naming conventions are followed regarding channel numbering:
2544

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

•
•

It has only one I/O channel and that has been labeled as “channel A”
DMA channel are labeled as “channel I and channel Q”.

Figure 24-3 explains the data flow for receive in SDR mode and DDR non-demux mode. In this case, only
one DMA channel (channel I) get used.
Figure 24-3. RX in SDR or DDR (non-demux) Mode

I/O Ch. A

Channel I Buffer

uPP DMA

Ch. I

Figure 24-4 explains the data flow for receive in DDR demux mode. In this case, both DMA channels
(channel I and channel Q) are used.
Figure 24-4. RX in DDR (demux) Mode
Channel I Buffer

Ch. I
uPP DMA

I/O Ch. A

Ch. Q

Channel Q Buffer

Figure 24-5 explains the data flow for transmit in SDR non-interleave or DDR non-demux mode. In this
case, only one DMA channel (channel I) get used.
Figure 24-5. TX in SDR (non-interleave) or DDR (non-demux) Mode

I/O Ch. A

Channel I Buffer

uPP DMA

Ch. I

Figure 24-6 explains the data flow for transmit in SDR interleave or DDR demux mode. In this case, both
DMA channels (channel I and channel Q) are used.
Figure 24-6. TX in SDR (interleave) or DDR (demux) Mode
Channel I Buffer

Ch. I
uPP DMA

I/O Ch. A
Channel Q Buffer

Ch. Q

24.3.3 Clock Generation and Control
The uPP peripheral uses three different clocks:
• A module clock that controls its internal logic and CPU interface. This is driven by CPU1.SYSCLK.
• A transmit clock (internally divided clock from the module clock) that runs the interface channel and
drives the CLK pin out in transmit mode.
• A receive clock (input via CLK pin) that runs the interface channel in receive mode.
Figure 24-7 shows the output clock generation system in transmit mode.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2545

Functional Description

www.ti.com

Figure 24-7. IO Output Clock Generation for TX Mode
Processor
uPP
Transmit
Clock

÷2

÷ (UPICR.CLKDIVx + 1)

Module
Clock

Clock
Pin

Transmit Timing
and control

Output Clock = Module Clock/(2 × (CLKDIVn + 1))
The fixed divisor restricts the maximum speed of the I/O clock to 1/2 the device CPU clock speed. For
DDR mode operation, the CLK output frq must be one eighth (1/8) or less of module clock.
For receive mode, channel requires an external clock to drive its CLK pin. The incoming clock is not
divided, and its maximum allowed speed is one fourth (¼) the module clock speed for SDR mode and one
eighth (1/8) the module clock speed for DDR mode. Figure 24-8 shows the clock generation system for a
channel configured in receive mode.
Figure 24-8. IO Input clock for RX Mode
Processor
uPP
Transmit
Clock

Module
Clock

2546

Universal Parallel Port (uPP)

÷2

÷ (UPICR.CLKDIVx + 1)

Receive Timing
and control

Clock
Pin

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

IO Interface and System Requirements

www.ti.com

24.4 IO Interface and System Requirements
The uPP module provides interfacing logic to external streaming data, both inbound and outbound flow of
data are supported. The interface protocol is a simple streaming interface. It is build on top of the existing
high-speed data converters, and captures most of the high-speed data converters protocol.
The input receive mode and output transmit mode protocol are symmetrical, and source synchronous, that
is, clock is supplied by the transmitter and the same clock is used to receive the data.
Table 24-1 describes the functionality of all the input/output (IO) signals of uPP module.
Table 24-1. uPP Signal Description
Signal

Description

CLK

• Transmit or receive clock
• Input in receive mode
• Output in transmit mode (Clock divider programmable)

START

•
•
•
•
•

Input in receive mode
Output in transmit mode
Polarity programmable
Indicates first data word of each line (frame)
This is optional signal and if this feature is not used, external receiver can ignore this signal.

ENABLE

•
•
•
•
•

Input when in receive mode
Output in transmit mode
Polarity programmable
Indicates data received is valid, or data transmitted is valid
Can be programmed to be ignored in receive mode but in transmit mode always drive active in sync
with valid data.

WAIT

•
•
•
•

Input in transmit mode
Output in receive mode but always drive inactive by uPP in this case
Polarity programmable
In transmit mode when active, indicates that target is not ready to receive data. uPP will stop
transmitting data at next clock cycle right after Wait signal is sampled as active. uPP module can be
programmed to ignored this in transmit mode.

NOTE: The WAIT needs to be asserted for one full cycle of IO clock by
external device.
DATA[7:0]

• 8-bit inputs in receive mode
• 8-bit output in transmit mode

24.4.1 Pin Multiplexing
Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the
smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at
device reset and software programmable register settings. To determine how pin multiplexing affects the
uPP peripheral, see the device-specific data manual.

24.4.2 Internal DMA Controller Description
The uPP peripheral includes an internal DMA controller separate from any device-level DMA. The internal
DMA controller consists of two DMA channels, channel I and channel Q, which moves data to and from
the uPP peripheral interface (I/O) channels in all operating modes. This section describes how to program
the internal DMA channels.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2547

IO Interface and System Requirements

www.ti.com

24.4.2.1 DMA Programming Concepts
The uPP internal DMA controller uses a simplified programming model similar to 2D transfers performed
by any other DMA at system level. Each DMA channel may be configured with four parameters: window
address, byte count, line count, and line offset address.
• Window Address (CHxDESC0.ADDR) - The location in uPP data memory of the first byte in the data
buffer. When the uPP operates in receive mode, the DMA channel begins writing to this address as it
takes incoming data from the uPP I/O channel. When the uPP operates in transmit mode, the DMA
channel begins reading from this address and pass the data to the uPP I/O channel. The window
address must be aligned to a 64-bit boundary (that is, the three LSBs must equal 0). Non-aligned
addresses are automatically adjusted to a properly aligned value when written to configuration register.
• Byte Count (CHxDESC1.BCNT) - The number of bytes per line. The byte count must be an even
number.
• Line Count (UPxDESC1.LCNT) - The number of lines per window. The total number of bytes
transferred equals B x L, where B is the byte count per line and L is the line count.
• Line Offset Address (CHxDESC2.LOFFSET) - The offset address between the first byte in successive
Lines. The line offset address cannot exceed 65528 (FFF8h) bytes, and must be aligned to a 64-bit
boundary in memory (that is, the three LSBs must equal 0).
Figure 24-9 shows a typical DMA window defined by these parameters.
Figure 24-9. Structure of DMA Window and Lines in Memory
uPP Data Memory
Window
Address

Line 1
Line Offset
Address

Byte Count
per Line

Line 2

……
…...

Line N

N = Line Count

Certain values of the line offset address have special implications on the structure of the data buffer:
• Line Offset Address = Byte Count : Data buffer is a contiguous block in memory with size equal to
(Line Count) x (Byte Count).
• Line Offset Address = 0 : Data buffer consists of a single line, with total size equal to Byte Count. If the
I/O channel is configured in transmit mode, this line is transmitted (Line Count) consecutive times
before the DMA transfer completes. If the I/O channel is configured in receive mode, the buffer is
repeatedly written and overwritten by incoming data.
To program a DMA transfer, write the appropriate fields in the DMA channel descriptor registers for DMA
Channel I or for DMA Channel Q. If the associated I/O channel is initialized and idle, the DMA transfer and
I/O transaction begins immediately. Section 24.4.10 describes a step-by-step process for configuring the
I/O channel and DMA channels to start a uPP transfer.
Each DMA channel allows a second descriptor to be queued while the previously programmed DMA
transfer is still running. The PEND status bit in channel status register reports whether a new set of DMA
parameters may be written to the DMA descriptor registers. Each DMA channel can have at most one
active transfer and one queued transfer. This allows each I/O channel to perform uninterrupted,
consecutive transactions across DMA transfer boundaries.

2548

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

IO Interface and System Requirements

www.ti.com

This DMA controller does not support automatically reloading DMA transfer descriptors. Each successive
descriptor set must be explicitly written to the configuration registers by software. All uPP interrupt events
originate in the internal DMA controller. Section 24.4.6 lists and explains all uPP interrupt events.
The internal DMA controller always writes data in bursts of 64 bytes. However, DMA read operations have
configurable burst size, which may be set per channel using the RDSIZEI and RDSIZEQ bits in the uPP
threshold configuration register. A DMA channel waits until the specified number of bytes leaves its
internal buffer before performing another burst read from memory.
Note that the TXSIZEA bit in threshold configuration register is not DMA parameters; instead, it control
transmit thresholds for the uPP interface channel.
24.4.2.2 Data Interleave Mode
The data interleave mode is a special configuration that maps both DMA channels to a single interface I/O
channel. There are two variants on data interleave mode, each with special conditions:
• Single Data Rate (SDR) Interleave
– Single Data Rate (DRA = 0)
– Transmit Only (MODE = 1)
– SDR Transmit interleave enabled (SDRTXILA = 1)
• Double Data Rate (DDR) Interleave
– Double Data Rate (DRA = 1)
– Transmit or Receive (MODE = 0/1)
– SDR Transmit interleave disabled (SDRTXILA = 0)
– DDR interleave enabled (DEMUXA = 1)
In data interleave mode, I/O channel is associated with two data buffers, each serviced by its own DMA
channel (I and Q). In SDR interleave mode, the START signal is used as a buffer selection line: START =
1 indicates that the current word comes from DMA Channel I; START = 0 indicates that the current word
comes from DMA Channel Q. In DDR Interleave mode, the data buffers alternate every word beginning
with Channel I: Channel I Word 0, Channel Q Word 0, Channel I Word 1, Channel Q Word 1, and so forth.
Section 24.4.10 shows signal diagrams for both data interleave modes.

24.4.3 Protocol Description
The uPP peripheral on this device has one I/O channel with 8 data lines, which can be configured to run in
transmit or receive mode. A channel may also be configured to ignore certain control signals using the
uPP interface configuration register. By default it uses all four control signals, unless otherwise configured.
24.4.3.1 DATA[7:0] Signals
DATA[7:0] comprise the channel’s entire data bus. In transmit mode, these pins are outputs that transmit
data supplied by the channel’s associated DMA channel. While the channel is idle, their behavior depends
on the TRISENA bit in IFCFG register. These pins can be configured to drive an idle value (TRISENA = 0,
VALA field in the uPP interface idle value register (IFIVAL)) or be in a high-impedance state while idle
(TRISENA = 1). In receive mode, these pins are inputs that provide data to the channel’s associated DMA
channel.
24.4.3.2 START Signal
The uPP transmitter asserts the START signal when it transfers the first word of a data line. A line is
defined in terms of the channel’s associated DMA channel; for more on DMA programming concepts, see
Section 24.4.2. The START signal is active-high by default, but its polarity is controlled by the
STARTPOLA bit in IFCFG register.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2549

IO Interface and System Requirements

www.ti.com

In transmit mode, START is an output signal and is always driven, in receive mode, START is an input
signal and may be disabled using the STARTA bit in IFCFG register. When the channel is configured in
transmit mode with data interleave enabled (SDRTXILA = 1 in CHCTL register), the START signal function
changes completely. The START signal now asserts on every data word that is provided by DMA Channel
I. For this alternative behavior, see Section 24.4.3.6.
24.4.3.3 ENABLE
The uPP transmitter asserts the ENABLE signal when it transfers a valid data word. The ENABLE signal is
active-high by default, but its polarity is controlled by the ENAPOLA bit in IFCFG register. In transmit
mode, ENABLE is an output signal and is always driven; in receive mode, ENABLE is an input signal and
may be disabled using the ENAA bit in IFCFG register.
24.4.3.4 WAIT Signal
The WAIT signal allows the receiver to request a temporary halt in data transmission. When the receiver
asserts WAIT, the transmitter responds by stopping transmission (starting with the next word) until WAIT
is released. The receiver ignores all incoming data until WAIT is released. Once WAIT is released, the
transmitter can resume transmission on the next word. Section 24.4.3 shows WAIT signal timing. The
WAIT signal is active-high by default, but its polarity is controlled by the WAITPOLA bit in IFCFG register.
In transmit mode, WAIT is an input signal and may be disabled using the WAITA bit in IFCFG register; in
receive mode, WAIT is an output signal and always driven inactive by uPP.
24.4.3.5 CLOCK Signal
The uPP transmitter drives the CLOCK signal to align all other uPP signals. By default, other signals align
on the rising edge of CLOCK, but its polarity is controlled by the CLKINVA bit in IFCFG register. The
active edge(s) of CLOCK should always slightly precede transitions of other uPP signals. In transmit
mode, CLOCK is an output signal; in receive mode, CLOCK is an input signal. For more information on
clock generation and allowed frequencies, see Section 24.4.2.
24.4.3.6 Signal Timing Diagrams
In the following diagrams, signals are marked (I) to indicate that they are inputs to the uPP peripheral and
(o) to indicate that they are outputs from the uPP peripheral. Data words from a single DMA channel are
designated Dx, while data words that must come from a specific DMA channel are designated Ix or Qx to
indicate DMA Channel I or Q, respectively. For more information on DMA channels and data interleave
mode, see Section 24.4.2.
All signal diagrams are drawn with signal polarities in their default states. All signals except DATA are
independently configurable in the uPP interface configuration register (IFCFG).
Figure 24-10. uPP Receive in SDR Mode
CLOCK(i)

START(i)
ENABLE(i)

WAIT(o)

DATA(i)

2550

Universal Parallel Port (uPP)

D1

D2

D3

D4

D5

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

IO Interface and System Requirements

www.ti.com

Figure 24-11. uPP Transmit in SDR Mode
CLOCK(o)

START(o)
ENABLE(o)

WAIT(i)
DATA(o)

D2

D1

D4

D3

Figure 24-12. uPP Transmit in SDR Mode – Interleaving
CLOCK(o)

START(o)

ENABLE(o)

WAIT(i)

DATA(o)

I1

Q2

I2

Q1

Figure 24-13. uPP Receive DDR Case
CLOCK(i)

START(i)

ENABLE(i)

WAIT(o)

DATA(i)

I1

Q1

I2

Q2

I3

Q3

I4

I5

Q4

Figure 24-14. uPP Transmit DDR Case
CLOCK(o)

START(o)

ENABLE(o)

WAIT(i)

DATA(o)

I1

Q1

I2

Q2

I3

Q3

I4

NOTE: START asserts on every data word from DMA Channel I in interleaving mode.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2551

IO Interface and System Requirements

www.ti.com

24.4.4 Data Format
On this device, uPP only support 8-bit interface hence no data packing is performed. User in this case, will
have to make appropriate connection externally, if needed. For example, if a 4-bit ADC is used, then the
user would have to tie the upper 4-bit of the uPP data inputs to ‘0’ or ‘1’ as needed. If external FPGA is
connected, then the user would have to make sure that 8-bit data (or appropriate tie-offs) is driven out
from the FPGA. By default uPP supports little endian data format but to support the data format of one of
the TI device (CC1260), a configuration bit is provided to select 16bit big endian mode also.
Figure 24-15 and Figure 24-16 describe how data goes out and comes in based on these modes.
Figure 24-15. uPP Tx Data Pattern in Non-Interleaved Mode
uPP
D3
D3

D2

D1

D2

D1

CC1260
Mode Disable

D0

D0
D3

I - RAM

TX DATA MEM

D2

D1

D0

uPP DMA

D2

D3

D0

CC1260
Mode Enable

D1
D2

D3

D0

D1

I - RAM

Figure 24-16. uPP Rx Data Pattern in Non-Interleaved Mode
uPP
D3
D3

D2

D1

D2

D1

CC1260
Mode Disable

D0

D0
D3

I - RAM

RX DATA MEM

D2

D1

D0

uPP DMA

D2

D3

D0

CC1260
Mode Enable

D1
D2

D3

D0

D1

I - RAM

24.4.5 Reset Considerations
24.4.5.1 Software Reset
Software reset clears the uPP internal state machines but does not reset the contents of the uPP
registers. The following procedure performs a software reset on the uPP peripheral:
1. Write the PEREN bit in the uPP PERCTL register to 0 (disables the uPP).
2. Poll the DMAST bit in uPP PERCTL register for activity; wait until DMA controller is inactive and idle.
3. Write the SOFTRST bit in uPP PERCTL register to 1 (places uPP in software reset).
2552

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

IO Interface and System Requirements

www.ti.com

4. Write the SOFTRST bit in uPP PERCTL register to 0 to (brings uPP out of software reset).
NOTE: In receive mode, uPP IO input clock must be running to have effect of soft reset.

24.4.5.2 Hardware Reset
When the processor XRSn (or CPU1.SYSRSn) pin is asserted, the entire processor is reset and is held in
the reset state until the RESET pin is released. As part of a device reset, the uPP state machines are
reset, and the uPP registers are forced to their default states. For default states, see the register section.
NOTE: There is no SW method to apply a hard reset to the UPP module on this device.

24.4.6 Interrupt Support
The uPP peripheral generates multiple interrupt events, all tied to internal DMA Channels I and Q. The
uPP peripheral automatically combines all interrupt events into a single chip-level interrupt driven to CPU1
and CPU1.CLA1. Individual events may be enabled using the uPP interrupt enable set register
(INTENSET) and disabled using the uPP interrupt enable clear register (INTENCLR). Only enabled events
generate interrupts and assert bits in the enabled interrupt status register (ENINTST). Disabled events do
not generate interrupts but do assert bits in the raw interrupt status register (RAWINTST). An interrupt
service routine (ISR) may be assigned to handle uPP CPU-level interrupts using the interrupt controller
module. If uPP events occur in close proximity to one another, a single CPU interrupt (and a single call to
the ISR) may represent multiple interrupt events. Thus, the uPP ISR must meet certain structural
requirements:
• The ISR must be able to handle multiple events before returning
• The ISR must handle any subsequent events that occur after it is called but before it returns
Like CPU ISR, CLA tasks can be assigned based on these interrupt events.
24.4.6.1 End of Line (EOL) Event
This event occurs each time when DMA channel reaches the end of a line in the data window. Note that if
the associated uPP interface channel is operating in transmit mode, this event may occur before the line’s
final bytes are actually transmitted over the data pins.
For small line size and fast data transfer, it is possible to “miss” EOL events if they occur faster than the
user’s code can handle them. This does not hinder uPP operation; the uPP peripheral continue processing
data uninterrupted until the EOW event or some error condition is encountered.
24.4.6.2 End of Window (EOW) Event
This event occurs when the DMA channel reaches the end of its current data window. Note that if the
associated uPP interface channel is operating in transmit mode, this event may occur shortly before the
window’s final bytes are actually transmitted over the data pins.
When an EOW event occurs, the DMA channel automatically begins the next DMA transfer if one has
been pre-programmed into the channel descriptor registers. If no new transfer is preprogrammed, the
DMA channel becomes idle. For small window size and fast data transfer, code overhead may make it
impossible to maintain a constant flow of data through the uPP interface channel. This problem can be
solved by increasing the DMA window size or decreasing the peripheral clock speed.
24.4.6.3 Underrun or Overflow (UOR) Event
This event occurs when the DMA channel fails to keep up with incoming or outgoing data on its
associated interface channel. Typically, this error indicates that background system activity has interfered
with normal operation of the peripheral. It does not occur simply when a channel is allowed to idle. After
encountering this error, the uPP peripheral should be reset when this event occurs.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2553

IO Interface and System Requirements

www.ti.com

This error should primarily occur when operating the uPP at high speed with significant system loading. To
avoid this error, run the uPP at slower speeds or reduce background activity, such as non-uPP peripheral
or DMA transactions. Additional tuning tips are given in Section 24.4.10.1.
24.4.6.4 DMA Programming Error (DPE) Event
This event occurs when the DMA channel descriptors are programmed while its PEND bit in the uPP DMA
channel status register is set to 1. A channel’s descriptors should only be programmed while the channel's
PEND bit is cleared to 0.

24.4.7 Emulation Considerations
The uPP peripheral stops running if any of three conditions are met:
• Peripheral Disable - EN bit in the uPP peripheral control register (PERCTL) is 0.
• Clock Stop – Clock to uPP is disabled using PCLKCR.
• Emulation Suspend - JTAG emulator halts chip while FREE = 0 and SOFT = 1 in uPP PERCTL
register.
For other settings of FREE and SOFT, the uPP peripheral continues running during emulation halt. When
the uPP encounters a stop condition, it completes the current DMA burst transaction (if one is active)
before stopping.
I/O channel, configured in transmit mode, immediately places its pins in a high-impedance state and
preserves the state of its internal state machines. Unless some reset event occurs (see Section 24.4.5),
the channel can resume where it left off when the stop condition is cleared. I/O channel configured in
receive mode only captures one additional data word. Further incoming data words are ignored as long as
the stop condition persists.

24.4.8 Transmit and Receive FIFOs
Each of the uPP peripheral I/O channels has a 512-byte FIFO. In receive mode, the FIFO is divided into
eight 64-byte blocks. In transmit mode, the FIFO is divided into blocks that can be set to 64, 128, or 256
bytes, configured by the TXSIZEA field in the uPP threshold configuration register (THCFG).
Transmission will not begin until the channel has loaded enough data to fill at least one full FIFO block.
The internal DMA channels may also be configured to use a read threshold of 64, 128, or 256 bytes using
the RDSIZEI or RDSIZEQ field in uPP THCFG register. The DMA write threshold is fixed at 64 bytes.

24.4.9 Transmit and Receive Data (MSG) RAM
On this device, uPP internal DMA doesn’t have access to system memories. Instead, there are two
dedicated DATA RAMs (also called as MSGRAM) that have been provided: one for each RX and TX;
each of these DATA RAMs are 512B. Since C28 CPU/CLA operates in 16-bit addressing mode, whereas,
uPP internal DMA operates in byte addressing mode, the addresses for these RAMs are different for
different views.
Table 24-2 describes the addresses for these RAMs for two different views.
Table 24-2. CPU/CLA/uPP-DMA Address Map
CPU/CLA Address

uPP DMA (programming) Address

Data (MSG)RAM

Start Address

End Address

Start Address

End Address

TX DATA RAM

0x6C00

0x6CFF

0x6C00

0x6DFF

RX DATA RAM

0x6E00

0x6EFF

0x7000

0x71FF

Table 24-3 describes the different access type for both the DATA(MSG) RAMs.

2554

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

IO Interface and System Requirements

www.ti.com

Table 24-3. CPU/CLA/uPP-DMA Address Map
TX DATA(MSG) RAM

RX DATA(MSG) RAM

Master/Data RAM

Read

Write

Read

Write

CPU1

Yes

Yes

Yes

Yes (Debug Mode Only)

CPU1.CLA1

Yes

Yes

Yes

No

uPP-DMA

Yes

No

No

Yes

NOTE: The message RAMs clocks are gated off when uPP clock is gated by the PCLKCR
configuration. Thus, the message RAMs are not accessible by CPU/CLA when RPI clock is
disabled by CPU.

24.4.10 Initialization and Operation
This section provides step-by-step instructions for initializing and running the uPP peripheral in various
modes. These instructions are given assuming that the device has just come out of a power-on reset
(POR) state.
1. Apply the appropriate pin multiplexing settings. For more information, see the device-specific data
manual, and (or) pin multiplexing utility.
2. Enable the clocks to the uPP peripheral. For more information, see the Clock Control section of this
TRM.
3. Wait for few (~32) device clock cycles, and then clear the “Soft Reset” bit to 0 to bring the module out
of reset.
4. Program the following uPP configuration registers: CHCTL, IFCFG, IFIVAL, THCFG.
a. uPP Channel Control Register (data format, SDR/DDR, TX/RX, single/dual channel, interleave,
demux)
b. uPP Interface configuration Register (IO signal enable, polarity, clock divisor)
c. uPP Interface idle value register (to drive value in idle mode for Tx)
d. uPP Threshold configuration register (TX Size, DMA read burst size)
5. Program the uPP interrupt enable set register to interrupt generation for the desired events. Register
an interrupt service routine (ISR) if desired; otherwise, polling is required.
6. Set the “PerEn” bit in the uPP peripheral control register (PCR) to 1 to turn on the uPP peripheral.
7. Allocate or initialize data buffers for use with uPP.
8. rogram the DMA channels with their first transfers using the uPP DMA channel descriptor register0, 1
and 2 (byte count, line count, line offset).
9. Once the DMA descriptors are written, the module will start to receive and transmit data, and perform
DMA transfers. Below is a simple description of how the DMA works.
10. Watch for interrupt events. Reprogram the DMA as necessary. (check that the PEND bit in the uPP
DMA channel status is ‘0’).
a. If polling, check uPP Interrupt enabled status register. Reading a bit as 1 indicates the
corresponding event has occurred. Write the corresponding bit with 1 to clear.
b. If using ISR, check ENINTST inside your ISR
Once the channel is started, the initial latency between the time when the first data is received or
transmitted on the pin, and the time when the first DMA burst is transferred on the CBA bus, is
unpredictable. This initial latency is determined by several factors:
• Clock ratio between system clock and uPP clock
• Various threshold values being programmed
• Chip-level traffic activities level
However, once the data is moving, all subsequent data movement is continuous (streaming). If such data
movement cannot be maintained, then DMA under-run or over-flow situation may occur.
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2555

IO Interface and System Requirements

www.ti.com

24.4.10.1 System Tuning Tips
The uPP peripheral can operate at high speed and transfer data at a very high rate. When operating the
uPP near its upper limits, tuning certain parameters can help decrease the incidence of errors and the
software overhead incurred servicing uPP data. Table 24-4 lists several parameters that can be useful in
system tuning. A parameter is defined as a “coarse” adjustment, if changing the parameter directly alters
the peripheral throughput. A “fine” adjustment does not change the peripheral throughput, but it does
affect general system performance.
Table 24-4. uPP Parameters Useful for System Tuning
Parameter

Register

Register
Field

Edge
Value

Safe
Value

Data Rate

CHCTL

DRA

1

0

Double data rate increases data transfer by a factor of 2 and
greatly increases system loading for the same clock divisor. This
is a coarse adjustment and is probably fixed due to design
constraints.

Clock Division

IFCFG

CLKDIVA

0

1+

Increasing clock division is the most straight-forward way to
decrease system loading. This is a coarse adjustment; the
difference between CLKDIVx = 0 and 1 is the same (in terms of
data rate) as the difference between single and double data rate.

DMA Read Burst Size

THCFG

RDSIZEQ
RDSIZEI

0

3h

Increasing the DMA read threshold decreases system loading by
generating fewer, larger DMA events. This is a fine adjustment.

DMA Line Size, Count CHxDESC
1

LCNT
BCNT

0

Total Transfer Size

LCNT
BCNT

(1)

(1)

CHxDESC
1

Description

(1)
Condensing uPP transfers into fewer, larger lines generates
fewer end-of-line interrupts and, thus, invokes fewer ISR calls.
This is a fine adjustment.
(1)

Performing many small uPP transfers can require excessive
software overhead (programming DMA descriptors, handling
interrupts, and so forth) at high data rates. This is a fine
adjustment.

(1) These values vary per application. One example could be a 16-KB transfer. The same total data could be transferred as 16 1-KB
lines or 2 8-KB lines.

2556

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5 Registers
24.5.1 UPP Base Addresses
Table 24-5. UPP Base Address Table
Device Registers
UppRegs
(1)

(1)

Register Name
UPP_REGS

Start Address

End Address

0x0000_6200

0x0000_62FF

Only available on CPU1.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2557

Registers

www.ti.com

24.5.2 UPP_REGS Registers
Table 24-6 lists the memory-mapped registers for the UPP_REGS. All register offset addresses not listed
in Table 24-6 should be considered as reserved locations and the register contents should not be
modified.
Table 24-6. UPP_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

PID

Peripheral ID Register

Go

2h

PERCTL

Peripheral Control Register

Go

8h

CHCTL

General Control Register

Go

Ah

IFCFG

Interface Configuration Register

Go

Ch

IFIVAL

Interface Idle Value Register

Go

Eh

THCFG

Threshold Configuration Register

Go

10h

RAWINTST

Raw Interrupt Status Register

Go

12h

ENINTST

Enable Interrupt Status Register

Go

14h

INTENSET

Interrupt Enable Set Register

Go

16h

INTENCLR

Interrupt Enable Clear Register

Go

20h

CHIDESC0

DMA Channel I Descriptor 0 Register

Go

22h

CHIDESC1

DMA Channel I Descriptor 1 Register

Go

24h

CHIDESC2

DMA Channel I Descriptor 2 Register

Go

28h

CHIST0

DMA Channel I Status 0 Register

Go

2Ah

CHIST1

DMA Channel I Status 1 Register

Go

2Ch

CHIST2

DMA Channel I Status 2 Register

Go

30h

CHQDESC0

DMA Channel Q Descriptor 0 Register

Go

32h

CHQDESC1

DMA Channel Q Descriptor 1 Register

Go

34h

CHQDESC2

DMA Channel Q Descriptor 2 Register

Go

38h

CHQST0

DMA Channel Q Status 0 Register

Go

3Ah

CHQST1

DMA Channel Q Status 1 Register

Go

3Ch

CHQST2

DMA Channel Q Status 2 Register

Go

40h

GINTEN

Global Peripheral Interrupt Enable Register

Go

42h

GINTFLG

Global Peripheral Interrupt Flag Register

Go

44h

GINTCLR

Global Peripheral Interrupt Clear Register

Go

46h

DLYCTL

IO clock data skew control Register

Go

Complex bit access types are encoded to fit into small table cells. Table 24-7 shows the codes that are
used for access types in this section.
Table 24-7. UPP_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W1C

1C
W

1 to clear
Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
2558

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 24-7. UPP_REGS Access Type
Codes (continued)
Access Type

Code

Description

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2559

Registers

www.ti.com

24.5.2.1 PID Register (Offset = 0h) [reset = 44231100h]
PID is shown in Figure 24-17 and described in Table 24-8.
Return to Summary Table.
Peripheral ID Register
Figure 24-17. PID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
REVID
R-44231100h

9

8

7

6

5

4

3

2

1

0

Table 24-8. PID Register Field Descriptions
Bit
31-0

2560

Field

Type

Reset

Description

REVID

R

44231100h

Module revision id.
Reset type: CPU1.SYSRSn

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.2 PERCTL Register (Offset = 2h) [reset = 0h]
PERCTL is shown in Figure 24-18 and described in Table 24-9.
Return to Summary Table.
Peripheral Control Register
Figure 24-18. PERCTL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3
PEREN
R/W-0h

2
RTEMU
R/W-0h

1
SOFT
R/W-0h

0
FREE
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7
DMAST
R-0h

6

5

4
SOFTRST
R/W-0h

RESERVED
R=0-0h

Table 24-9. PERCTL Register Field Descriptions
Bit
31-8
7

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

DMAST

R

0h

DMA state machine status.
0: Idle
1: DMA Burst transaction is active.
Reset type: CPU1.SYSRSn

6-5
4

RESERVED

R=0

0h

Reserved

SOFTRST

R/W

0h

This bit reset all the state machines and certain memory elements
inside the RPI module immediately. Software can write this bit to '1',
and later write '0' to bring the RPI module out of reset. Note that
MMR are NOT reset, except for Interrupt-Raw-Status Register. This
reset can be used to recover the RPI from an error condition.
To make sure that a graceful or fail-safe reset is performed, software
can first disable the "PerEn" bit, then poll the DMAStatus bit to make
sure that all pending VBUSP DMA burst are completed, then perform
a software reset.
0: De-assert the reset (out of reset).
1: Assert the reset (in to reset).
Reset type: CPU1.SYSRSn

3

PEREN

R/W

0h

This bit can be used to disable or suspend the RPI module. When
this bit is programmed to be disabled, the RPI will be stopped
(suspended) after all current DMA activity are completed.
0: Disable/Suspend the uPP module.
1: Enable/Resume the uPP module.
Reset type: CPU1.SYSRSn

2

RTEMU

R/W

0h

0: Real Time emulation is disable. Module gets suspended when
CPU is supended.
1: Real Time emulation is enable.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2561

Registers

www.ti.com

Table 24-9. PERCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1

SOFT

R/W

0h

0: Hard Stop.
1: Soft Stop.
Reset type: CPU1.SYSRSn

0

FREE

R/W

0h

0: Software controlled.
1: Free Running.
Reset type: CPU1.SYSRSn

2562

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.3 CHCTL Register (Offset = 8h) [reset = 0h]
CHCTL is shown in Figure 24-19 and described in Table 24-10.
Return to Summary Table.
General Control Register
Figure 24-19. CHCTL Register
31
RESERVED
R=0-0h

30

29

28

27
RESERVED
R/W-0h

26

25

24

23

22

21

20
RESERVED
R/W-0h

19

18

17

16
DRA
R/W-0h

15

14

13

12

11

10

9

8

3
SDRTXILA
R/W-0h

2
RESERVED
R/W-0h

1

RESERVED
R/W-0h
7

6
RESERVED
R/W-0h

5

4
DEMUXA
R/W-0h

0
MODE
R/W-0h

Table 24-10. CHCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R=0

0h

Reserved

30-17

RESERVED

R/W

0h

Reserved

DRA

R/W

0h

Data rate control.

16

0: Single Data Rate (SDR).
1: Double Data Rate (DDR).
Reset type: CPU1.SYSRSn
15-5
4

RESERVED

R/W

0h

Reserved

DEMUXA

R/W

0h

DDR de-multiplexing mode (This bit is only valid for DDR mode):
0: De-multiplexing is disable.
1: De-multiplexing is Enable (split data into 2 DMA channels).
Reset type: CPU1.SYSRSn

3

SDRTXILA

R/W

0h

Tx SDR interleave mode (This bit is only valid for SDR mode):
0: Interleving is disable.
1: Interleving is Enable (split data into 2 DMA channels).
Reset type: CPU1.SYSRSn

2
1-0

RESERVED

R/W

0h

Reserved

MODE

R/W

0h

Operating mode:
00: Pure input receive mode.
01: Pure output transmit mode.
10: Reserved.
11: Reserved.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2563

Registers

www.ti.com

24.5.2.4 IFCFG Register (Offset = Ah) [reset = 0h]
IFCFG is shown in Figure 24-20 and described in Table 24-11.
Return to Summary Table.
Interface Configuration Register
Figure 24-20. IFCFG Register
31

30

29

28

27

RESERVED
R=0-0h
23

22

21

20

19

RESERVED
R=0-0h
15

25

24

18

17

16

9

8

1
ENAPOLA
R/W-0h

0
STARTPOLA
R/W-0h

RESERVED
R/W-0h
14

RESERVED
R=0-0h
7

26
RESERVED
R/W-0h

6
RESERVED
R=0-0h

13
TRISENA
R/W-0h

12
CLKINVA
R/W-0h

11

10

5
WAITA
R/W-0h

4
ENAA
R/W-0h

3
STARTA
R/W-0h

CLKDIVA
R/W-0h
2
WAITPOLA
R/W-0h

Table 24-11. IFCFG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

R=0

0h

Reserved

29-24

RESERVED

R/W

0h

Reserved

23-22

RESERVED

R=0

0h

Reserved

21-16

RESERVED

R/W

0h

Reserved

15-14

RESERVED

R=0

0h

Reserved

TRISENA

R/W

0h

Transmit mode output tri-state control:

13

0: Disable. RPI will not tri-state during idle time and will drive values
from the Interface Idle Value Register.
1: Enable. RPI will tri-state during idle time.
Idle time is the time before and between Window transfers.
Reset type: CPU1.SYSRSn
12

CLKINVA

R/W

0h

Clock inversion:
0: Clock is not inverted
1: Clock is inverted
When in Rx mode, the clock will be treated as inverted if enabled.
When in Tx mode, the clock will be inverted before going out of the
pin.
Reset type: CPU1.SYSRSn

11-8

CLKDIVA

R/W

0h

Clock divider for transmit mode:
TX_IOCLK = CHIP_CLK / 2(N+1)
Where 'N' is the value programmed into this field.
Reset type: CPU1.SYSRSn

7-6

2564

RESERVED

Universal Parallel Port (uPP)

R=0

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 24-11. IFCFG Register Field Descriptions (continued)
Bit
5

Field

Type

Reset

Description

WAITA

R/W

0h

Enable Usage of WAIT signal:
0: Disable (Tx: ignore wait)
1: Enable (Tx: honor wait)
This bit is only valid for transmit mode, receive mode always drive
WAIT signal inactive (except for stop_run situation).
Reset type: CPU1.SYSRSn

4

ENAA

R/W

0h

Enable Usage of ENABLE (WRITE) signal:
0: Disable (Rx: ignore enable)
1: Enable (Rx: honor enable)
This bit is only valid for receive mode, transmit mode always drive
ENABLE signal active.
Reset type: CPU1.SYSRSn

3

STARTA

R/W

0h

Enable Usage of START (SELECT) signal:
0: Disable (Rx: ignore start)
1: Enable (Rx: honor start)
This bit is only valid for receive mode, transmit mode always drive
START signal active.
Reset type: CPU1.SYSRSn

2

WAITPOLA

R/W

0h

Polarity of WAIT signal:
0: Active High.
1: Active Low.
Reset type: CPU1.SYSRSn

1

ENAPOLA

R/W

0h

Polarity of ENABLE(WRITE) signal:
0: Active High.
1: Active Low.
Reset type: CPU1.SYSRSn

0

STARTPOLA

R/W

0h

Polarity of START(SELECT) signal:
0: Active High.
1: Active Low.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2565

Registers

www.ti.com

24.5.2.5 IFIVAL Register (Offset = Ch) [reset = 0h]
IFIVAL is shown in Figure 24-21 and described in Table 24-12.
Return to Summary Table.
Interface Idle Value Register
Figure 24-21. IFIVAL Register
31

30

29

15

14

13

28

27

26

25

12
11
RESERVED
R/W-0h

10

9

24
23
RESERVED
R/W-0h
8

7

22

21

20

19

18

17

16

6

5

4
VALA
R/W-0h

3

2

1

0

Table 24-12. IFIVAL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R/W

0h

Reserved

15-9

RESERVED

R/W

0h

Reserved

8-0

VALA

R/W

0h

When in transmit mode, this field holds the value that will be driven
out when the channel is idle.
This includes both situations when TRISEN field of the RPI Interface
Configuration Register is enabled, and when wait-state is inserted by
the external receiver (WAIT asserted).
Reset type: CPU1.SYSRSn

2566

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.6 THCFG Register (Offset = Eh) [reset = 0h]
THCFG is shown in Figure 24-22 and described in Table 24-13.
Return to Summary Table.
Threshold Configuration Register
Figure 24-22. THCFG Register
31

30

29

28

27

26

25

RESERVED
R=0-0h
23

22

21

20

19

18

17

RESERVED
R=0-0h
15

14

13

6

12

5

16
TXSIZEA
R/W-0h

11

10

9

RESERVED
R=0-0h
7

24
RESERVED
R/W-0h

8
RDSIZEQ
R/W-0h

4

3

2

1

RESERVED
R=0-0h

0
RDSIZEI
R/W-0h

Table 24-13. THCFG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-26

RESERVED

R=0

0h

Reserved

25-24

RESERVED

R/W

0h

Reserved

23-18

RESERVED

R=0

0h

Reserved

17-16

TXSIZEA

R/W

0h

I/O Transmit Threshold:
00: 64 Byte
01: 128 Byte
10: Reserved
11: 256 Byte
The uPP will hold off transmitting until this threshold is reach in the
transmit buffer. The following programming limitation applies:
If TX_SIZE = 64B, there is no programming limitation.
If TX_SIZE = 128B, descriptor Byte-Count must > 64B.
If TX_SIZE = 256B, descriptor Byte-Count must > 192B
Reset type: CPU1.SYSRSn

15-10
9-8

RESERVED

R=0

0h

Reserved

RDSIZEQ

R/W

0h

DMA Read Threshold for DMA Channel Q:
00: 64 Byte
01: 128 Byte
10: Reserved
11: 256 Byte
DMA read burst is based on this value (same as FIFO block size).
Note: DMA Write Threshold (write burst) is fixed at 64B.
Reset type: CPU1.SYSRSn

7-2

RESERVED

R=0

0h

Reserved

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2567

Registers

www.ti.com

Table 24-13. THCFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

RDSIZEI

R/W

0h

DMA Read Threshold for DMA Channel I:
00: 64 Byte
01: 128 Byte
10: Reserved
11: 256 Byte
DMA read burst is based on this value (same as FIFO block size).
Note: DMA Write Threshold (write burst) is fixed at 64B.
Reset type: CPU1.SYSRSn

2568

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.7 RAWINTST Register (Offset = 10h) [reset = 0h]
RAWINTST is shown in Figure 24-23 and described in Table 24-14.
Return to Summary Table.
Raw Interrupt Status Register
Figure 24-23. RAWINTST Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14
RESERVED
R=0-0h

13

12
EOLQ
R/W-0h

11
EOWQ
R/W-0h

10
RESERVED
R/W-0h

9
UOEQ
R/W-0h

8
DPEQ
R/W-0h

7

6
RESERVED
R=0-0h

5

4
EOLI
R/W-0h

3
EOWI
R/W-0h

2
RESERVED
R/W-0h

1
UOEI
R/W-0h

0
DPEI
R/W-0h

Table 24-14. RAWINTST Register Field Descriptions
Bit
31-13
12

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

EOLQ

R/W

0h

Interrupt raw status for end-of-line condition:
0: No event.
1: End Of Line event happened.
Reset type: CPU1.SYSRSn

11

EOWQ

R/W

0h

Interrupt raw status for end-of-line condition:
0: No event.
1: End Of Window event happened.
Reset type: CPU1.SYSRSn

10

RESERVED

R/W

0h

Reserved

9

UOEQ

R/W

0h

Interrupt raw status for DMA under-run or over-run :
0: No event.
1: Under-run/Over-run event happened.
Over-run in receiving or Under-Run in transmitting.
Reset type: CPU1.SYSRSn

8

DPEQ

R/W

0h

Interrupt raw status for DMA programming error:
0: No event.
1: DMA programming error (Writing of DMA descriptors while
PENDING bit is active) occurred.
Reset type: CPU1.SYSRSn

7-5
4

RESERVED

R=0

0h

Reserved

EOLI

R/W

0h

Interrupt raw status for end-of-line condition:
0: No event.
1: End Of Line event happened.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2569

Registers

www.ti.com

Table 24-14. RAWINTST Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

EOWI

R/W

0h

Interrupt raw status for end-of-line condition:
0: No event.
1: End Of Window event happened.
Reset type: CPU1.SYSRSn

2

RESERVED

R/W

0h

Reserved

1

UOEI

R/W

0h

Interrupt raw status for DMA under-run or over-run :
0: No event.
1: Under-run/Over-run event happened.
Over-run in receiving or Under-Run in transmitting.
Reset type: CPU1.SYSRSn

0

DPEI

R/W

0h

Interrupt raw status for DMA programming error:
0: No event.
1: DMA programming error (Writing of DMA descriptors while
PENDING bit is active) occurred.
Reset type: CPU1.SYSRSn

2570

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.8 ENINTST Register (Offset = 12h) [reset = 0h]
ENINTST is shown in Figure 24-24 and described in Table 24-15.
Return to Summary Table.
Enable Interrupt Status Register
Figure 24-24. ENINTST Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14
RESERVED
R=0-0h

13

12
EOLQ
R/W1C-0h

11
EOWQ
R/W1C-0h

10
RESERVED
R/W1C-0h

9
UOEQ
R/W1C-0h

8
DPEQ
R/W1C-0h

7

6
RESERVED
R=0-0h

5

4
EOLI
R/W1C-0h

3
EOWI
R/W1C-0h

2
RESERVED
R/W1C-0h

1
UOEI
R/W1C-0h

0
DPEI
R/W1C-0h

Table 24-15. ENINTST Register Field Descriptions
Bit
31-13
12

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

EOLQ

R/W1C

0h

Interrupt enable status for end-of-line condition. Writing 1 will clear
the interrupt status and writing 0 has no effect.
0: No event.
1: End Of Line event happened.
Reset type: CPU1.SYSRSn

11

EOWQ

R/W1C

0h

Interrupt enable status for end-of-line condition. Writing 1 will clear
the interrupt status and writing 0 has no effect.
0: No event.
1: End Of Window event happened.
Reset type: CPU1.SYSRSn

10

RESERVED

R/W1C

0h

Reserved

9

UOEQ

R/W1C

0h

Interrupt enable status for DMA under-run or over-run. Writing 1 will
clear the interrupt status and writing 0 has no effect.
0: No event.
1: Under-run/Over-run event happened.
Over-run in receiving or Under-Run in transmitting.
Reset type: CPU1.SYSRSn

8

DPEQ

R/W1C

0h

Interrupt enable status for DMA programming error. Writing 1 will
clear the interrupt status and writing 0 has no effect.
0: No event.
1: DMA programming error (Writing of DMA descriptors while
PENDING bit is active) occurred.
Reset type: CPU1.SYSRSn

7-5
4

RESERVED

R=0

0h

Reserved

EOLI

R/W1C

0h

Interrupt enable status for end-of-line condition. Writing 1 will clear
the interrupt status and writing 0 has no effect.
0: No event.
1: End Of Line event happened.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2571

Registers

www.ti.com

Table 24-15. ENINTST Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

EOWI

R/W1C

0h

Interrupt enable status for end-of-line condition. Writing 1 will clear
the interrupt status and writing 0 has no effect.
0: No event.
1: End Of Window event happened.
Reset type: CPU1.SYSRSn

2

RESERVED

R/W1C

0h

Reserved

1

UOEI

R/W1C

0h

Interrupt enable status for DMA under-run or over-run. Writing 1 will
clear the interrupt status and writing 0 has no effect.
0: No event.
1: Under-run/Over-run event happened.
Over-run in receiving or Under-Run in transmitting.
Reset type: CPU1.SYSRSn

0

DPEI

R/W1C

0h

Interrupt enable status for DMA programming error. Writing 1 will
clear the interrupt status and writing 0 has no effect.
0: No event.
1: DMA programming error (Writing of DMA descriptors while
PENDING bit is active) occurred.
Reset type: CPU1.SYSRSn

2572

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.9 INTENSET Register (Offset = 14h) [reset = 0h]
INTENSET is shown in Figure 24-25 and described in Table 24-16.
Return to Summary Table.
Interrupt Enable Set Register
Figure 24-25. INTENSET Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14
RESERVED
R=0-0h

13

12
EOLQ
R/W=1-0h

11
EOWQ
R/W=1-0h

10
RESERVED
R/W=1-0h

9
UOEQ
R/W=1-0h

8
DPEQ
R/W=1-0h

7

6
RESERVED
R=0-0h

5

4
EOLI
R/W=1-0h

3
EOWI
R/W=1-0h

2
RESERVED
R/W=1-0h

1
UOEI
R/W=1-0h

0
DPEI
R/W=1-0h

Table 24-16. INTENSET Register Field Descriptions
Bit
31-13
12

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

EOLQ

R/W=1

0h

Interrupt enable for end-of-line condition. Writing 1 will enable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

11

EOWQ

R/W=1

0h

Interrupt enable for end-of-line condition. Writing 1 will enable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

10

RESERVED

R/W=1

0h

Reserved

9

UOEQ

R/W=1

0h

Interrupt enable for DMA under-run or over-run. Writing 1 will enable
the interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

8

DPEQ

R/W=1

0h

Interrupt enable for DMA programming error. Writing 1 will enable
the interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

7-5
4

RESERVED

R=0

0h

Reserved

EOLI

R/W=1

0h

Interrupt enable for end-of-line condition. Writing 1 will enable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2573

Registers

www.ti.com

Table 24-16. INTENSET Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

EOWI

R/W=1

0h

Interrupt enable for end-of-line condition. Writing 1 will enable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

2

RESERVED

R/W=1

0h

Reserved

1

UOEI

R/W=1

0h

Interrupt enable for DMA under-run or over-run. Writing 1 will enable
the interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Over-run in receiving or Under-Run in transmitting.
Reset type: CPU1.SYSRSn

0

DPEI

R/W=1

0h

Interrupt enable for DMA programming error. Writing 1 will enable
the interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

2574

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.10 INTENCLR Register (Offset = 16h) [reset = 0h]
INTENCLR is shown in Figure 24-26 and described in Table 24-17.
Return to Summary Table.
Interrupt Enable Clear Register
Figure 24-26. INTENCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14
RESERVED
R=0-0h

13

12
EOLQ
R/W=1-0h

11
EOWQ
R/W=1-0h

10
RESERVED
R/W=1-0h

9
UOEQ
R/W=1-0h

8
DPEQ
R/W=1-0h

7

6
RESERVED
R=0-0h

5

4
EOLI
R/W=1-0h

3
EOWI
R/W=1-0h

2
RESERVED
R/W=1-0h

1
UOEI
R/W=1-0h

0
DPEI
R/W=1-0h

Table 24-17. INTENCLR Register Field Descriptions
Bit
31-13
12

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

EOLQ

R/W=1

0h

Interrupt clear for end-of-line condition. Writing 1 will disable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

11

EOWQ

R/W=1

0h

Interrupt clear for end-of-line condition. Writing 1 will disable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

10

RESERVED

R/W=1

0h

Reserved

9

UOEQ

R/W=1

0h

Interrupt clear for DMA under-run or over-run. Writing 1 will disable
the interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

8

DPEQ

R/W=1

0h

Interrupt clear for DMA programming error. Writing 1 will disable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

7-5
4

RESERVED

R=0

0h

Reserved

EOLI

R/W=1

0h

Interrupt clear for end-of-line condition. Writing 1 will disable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2575

Registers

www.ti.com

Table 24-17. INTENCLR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3

EOWI

R/W=1

0h

Interrupt clear for end-of-line condition. Writing 1 will disable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

2

RESERVED

R/W=1

0h

Reserved

1

UOEI

R/W=1

0h

Interrupt clear for DMA under-run or over-run. Writing 1 will disable
the interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Over-run in receiving or Under-Run in transmitting.
Reset type: CPU1.SYSRSn

0

DPEI

R/W=1

0h

Interrupt clear for DMA programming error. Writing 1 will disable the
interrupt and writing 0 has no effect.
0: Interrupt is disable.
1: Interrupt is enable.
Reset type: CPU1.SYSRSn

2576

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.11 CHIDESC0 Register (Offset = 20h) [reset = 0h]
CHIDESC0 is shown in Figure 24-27 and described in Table 24-18.
Return to Summary Table.
DMA Channel I Descriptor 0 Register
Figure 24-27. CHIDESC0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 24-18. CHIDESC0 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

ADDR

R/W

0h

Starting address of the DMA Channel I transfer. It must be 64bit
aligned.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2577

Registers

www.ti.com

24.5.2.12 CHIDESC1 Register (Offset = 22h) [reset = 0h]
CHIDESC1 is shown in Figure 24-28 and described in Table 24-19.
Return to Summary Table.
DMA Channel I Descriptor 1 Register
Figure 24-28. CHIDESC1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LCNT
R/W-0h

9

8 7 6
BCNT
R/W-0h

5

4

3

2

1

0

Table 24-19. CHIDESC1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

LCNT

R/W

0h

Number of lines in a window for DMA Channel I transfer(number of
packets in CPPI 4.1 terminology):
0: Line count of 0 (invalid programming)
1: Line count of 1
So on...
Reset type: CPU1.SYSRSn

15-0

BCNT

R/W

0h

Number of bytes in a line for DMA Channel I transfer(number of
bytes in a packet in CPPI 4.1 terminology):
0: Byte count of 0 (invalid programming)
1: Byte count of 1
So on...
Reset type: CPU1.SYSRSn

2578

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.13 CHIDESC2 Register (Offset = 24h) [reset = 0h]
CHIDESC2 is shown in Figure 24-29 and described in Table 24-20.
Return to Summary Table.
DMA Channel I Descriptor 2 Register
Figure 24-29. CHIDESC2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R=0-0h

9

8 7 6
LOFFSET
R/W-0h

5

4

3

2

1

0

Table 24-20. CHIDESC2 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-0

LOFFSET

R/W

0h

Offset from the current line starting address to the next line starting
address for DMA Channel I transfers. It must be 64bit aligned.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2579

Registers

www.ti.com

24.5.2.14 CHIST0 Register (Offset = 28h) [reset = 0h]
CHIST0 is shown in Figure 24-30 and described in Table 24-21.
Return to Summary Table.
DMA Channel I Status 0 Register
Figure 24-30. CHIST0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 24-21. CHIST0 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

ADDR

R

0h

Current address of the DMA transfer.
Reset type: CPU1.SYSRSn

2580

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.15 CHIST1 Register (Offset = 2Ah) [reset = 0h]
CHIST1 is shown in Figure 24-31 and described in Table 24-22.
Return to Summary Table.
DMA Channel I Status 1 Register
Figure 24-31. CHIST1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LCNT
R-0h

9

8 7
BCNT
R-0h

6

5

4

3

2

1

0

Table 24-22. CHIST1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

LCNT

R

0h

Current line number.
Reset type: CPU1.SYSRSn

15-0

BCNT

R

0h

Current byte number.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2581

Registers

www.ti.com

24.5.2.16 CHIST2 Register (Offset = 2Ch) [reset = 0h]
CHIST2 is shown in Figure 24-32 and described in Table 24-23.
Return to Summary Table.
DMA Channel I Status 2 Register
Figure 24-32. CHIST2 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1
PEND
R-0h

0
ACT
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

3

WM
R-0h

RESERVED
R=0-0h

Table 24-23. CHIST2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

R=0

0h

Reserved

7-4

WM

R

0h

Watermark for FIFO block count for DMA Channel I tranfer.
For RX, this is a recording of the maximum FIFO Block Occupancy
ever reached for a continuous transaction.
For TX, this is a simple capture of the FIFO Block Emptiness count
every clock.
Reset type: CPU1.SYSRSn

3-2
1

RESERVED

R=0

0h

Reserved

PEND

R

0h

Status of DMA:
0: OK to write a new set of DMA descriptor.
1: Writing of new DMA descriptor is disallowed/ignored.
Reset type: CPU1.SYSRSn

0

ACT

R

0h

Status of DMA descriptor.t:
0: Descriptor is currently idle.
1: Descriptor is currently active (transferring data).
"PENDING" bit is used for descriptor programming allowance, while
"ACTIVE" is used for indicating if a descriptor is being in use or not.
Software should not use these bit to indicate "end-of-window"
transfer condition (use the EOW status/interrupt instead).
For RX mode, this bit reflects if any of the 2 pending descriptors on
the CBA clock domain is currently running.
For TX mode, this bit reflects if any of the 2 pending descriptors on
the RPI clock domain is currently running.
A proper way to monitor this signal (after loading a descriptor) is to
first wait for this ACTIVE signal to go active, then wait for this signal
to go inactive. The deassertion of the ACTIVE signal indicates that
the descriptor is completed.
Another side note is that the "DMA_STATUS" of PCR is a low-level
monitoring signal for DMA VBUSP bus activity, while the PENDING,
ACTIVE are higher-lever monitoring for descriptor status.
Reset type: CPU1.SYSRSn

2582

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.17 CHQDESC0 Register (Offset = 30h) [reset = 0h]
CHQDESC0 is shown in Figure 24-33 and described in Table 24-24.
Return to Summary Table.
DMA Channel Q Descriptor 0 Register
Figure 24-33. CHQDESC0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R/W-0h

9

8

7

6

5

4

3

2

1

0

Table 24-24. CHQDESC0 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

ADDR

R/W

0h

Starting address of the DMA Channel Q transfer. This must be 64bit
aligned.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2583

Registers

www.ti.com

24.5.2.18 CHQDESC1 Register (Offset = 32h) [reset = 0h]
CHQDESC1 is shown in Figure 24-34 and described in Table 24-25.
Return to Summary Table.
DMA Channel Q Descriptor 1 Register
Figure 24-34. CHQDESC1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LCNT
R/W-0h

9

8 7 6
BCNT
R/W-0h

5

4

3

2

1

0

Table 24-25. CHQDESC1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

LCNT

R/W

0h

Number of lines in a window for DMA Channel Q transfer(number of
packets in CPPI 4.1 terminology):
0: Line count of 0 (invalid programming)
1: Line count of 1
So on...
Reset type: CPU1.SYSRSn

15-0

BCNT

R/W

0h

Number of bytes in a line for DMA Channel Q transfer(number of
bytes in a packet in CPPI 4.1 terminology):
0: Byte count of 0 (invalid programming)
1: Byte count of 1
So on...
Reset type: CPU1.SYSRSn

2584

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.19 CHQDESC2 Register (Offset = 34h) [reset = 0h]
CHQDESC2 is shown in Figure 24-35 and described in Table 24-26.
Return to Summary Table.
DMA Channel Q Descriptor 2 Register
Figure 24-35. CHQDESC2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R=0-0h

9

8 7 6
LOFFSET
R/W-0h

5

4

3

2

1

0

Table 24-26. CHQDESC2 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R=0

0h

Reserved

15-0

LOFFSET

R/W

0h

Offset from the current line starting address to the next line starting
address for DMA Channel Q transfers. It must be 64bit aligned.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2585

Registers

www.ti.com

24.5.2.20 CHQST0 Register (Offset = 38h) [reset = 0h]
CHQST0 is shown in Figure 24-36 and described in Table 24-27.
Return to Summary Table.
DMA Channel Q Status 0 Register
Figure 24-36. CHQST0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 24-27. CHQST0 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

ADDR

R

0h

Current address of the DMA transfer.
Reset type: CPU1.SYSRSn

2586

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.21 CHQST1 Register (Offset = 3Ah) [reset = 0h]
CHQST1 is shown in Figure 24-37 and described in Table 24-28.
Return to Summary Table.
DMA Channel Q Status 1 Register
Figure 24-37. CHQST1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LCNT
R-0h

9

8 7
BCNT
R-0h

6

5

4

3

2

1

0

Table 24-28. CHQST1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

LCNT

R

0h

Current line number.
Reset type: CPU1.SYSRSn

15-0

BCNT

R

0h

Current byte number.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2587

Registers

www.ti.com

24.5.2.22 CHQST2 Register (Offset = 3Ch) [reset = 0h]
CHQST2 is shown in Figure 24-38 and described in Table 24-29.
Return to Summary Table.
DMA Channel Q Status 2 Register
Figure 24-38. CHQST2 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1
PEND
R-0h

0
ACT
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4

3

WM
R-0h

RESERVED
R=0-0h

Table 24-29. CHQST2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

R=0

0h

Reserved

7-4

WM

R

0h

Watermark for FIFO block count for DMA Channel Q tranfer.
For RX, this is a recording of the maximum FIFO Block Occupancy
ever reached for a continuous transaction.
For TX, this is a simple capture of the FIFO Block Emptiness count
every clock.
Reset type: CPU1.SYSRSn

3-2
1

RESERVED

R=0

0h

Reserved

PEND

R

0h

Status of DMA:
0: OK to write a new set of DMA descriptor.
1: Writing of new DMA descriptor is disallowed/ignored.
Reset type: CPU1.SYSRSn

0

ACT

R

0h

Status of DMA descriptor.t:
0: Descriptor is currently idle.
1: Descriptor is currently active (transferring data).
"PENDING" bit is used for descriptor programming allowance, while
"ACTIVE" is used for indicating if a descriptor is being in use or not.
Software should not use these bit to indicate "end-of-window"
transfer condition (use the EOW status/interrupt instead).
For RX mode, this bit reflects if any of the 2 pending descriptors on
the CBA clock domain is currently running.
For TX mode, this bit reflects if any of the 2 pending descriptors on
the RPI clock domain is currently running.
A proper way to monitor this signal (after loading a descriptor) is to
first wait for this ACTIVE signal to go active, then wait for this signal
to go inactive. The deassertion of the ACTIVE signal indicates that
the descriptor is completed.
Another side note is that the "DMA_STATUS" of PCR is a low-level
monitoring signal for DMA VBUSP bus activity, while the PENDING,
ACTIVE are higher-lever monitoring for descriptor status.
Reset type: CPU1.SYSRSn

2588

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.23 GINTEN Register (Offset = 40h) [reset = 0h]
GINTEN is shown in Figure 24-39 and described in Table 24-30.
Return to Summary Table.
Global Peripheral Interrupt Enable Register
Figure 24-39. GINTEN Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
GINTEN
R/W-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 24-30. GINTEN Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

GINTEN

R/W

0h

0 = uPP does not generate interrupt.
1= uPP generates interrupt to if interrupt flag gets set.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2589

Registers

www.ti.com

24.5.2.24 GINTFLG Register (Offset = 42h) [reset = 0h]
GINTFLG is shown in Figure 24-40 and described in Table 24-31.
Return to Summary Table.
Global Peripheral Interrupt Flag Register
Figure 24-40. GINTFLG Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
GINTFLG
R-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 24-31. GINTFLG Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

GINTFLG

R

0h

0: No interrupt has been generated.
1: Interrupt has been generated.
Reset type: CPU1.SYSRSn

2590

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

24.5.2.25 GINTCLR Register (Offset = 44h) [reset = 0h]
GINTCLR is shown in Figure 24-41 and described in Table 24-32.
Return to Summary Table.
Global Peripheral Interrupt Clear Register
Figure 24-41. GINTCLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
GINTCLR
R=0/W=1-0h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5

4
RESERVED
R=0-0h

Table 24-32. GINTCLR Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R=0

0h

Reserved

GINTCLR

R=0/W=1

0h

Write '1' to this clears the flag in GINTFR. Read always returns '0'.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Universal Parallel Port (uPP)

2591

Registers

www.ti.com

24.5.2.26 DLYCTL Register (Offset = 46h) [reset = 1h]
DLYCTL is shown in Figure 24-42 and described in Table 24-33.
Return to Summary Table.
IO clock data skew control Register
Figure 24-42. DLYCTL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
DLYDIS
R/W-1h

RESERVED
R=0-0h
23

22

21

20
RESERVED
R=0-0h

15

14

13

12
RESERVED
R=0-0h

7

6

5
RESERVED
R=0-0h

4

DLYCTL
R/W-0h

Table 24-33. DLYCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-3

RESERVED

R=0

0h

Reserved

2-1

DLYCTL

R/W

0h

Controls the delay on the input signals for uPP.
00: Data and control pins have 4 cycle dealy, clock pins have 2 cycle
delay.
01: Data and control pins have 6 cycle dealy, clock pins have 2 cycle
delay.
10: Data and control pins have 9 cycle dealy, clock pins have 2 cycle
delay.
11: Data and control pins have 14 cycle dealy, clock pins have 2
cycle delay.
Reset type: CPU1.SYSRSn

0

DLYDIS

R/W

1h

0: Dealy on pins are controlled by setting in DLYCTL field.
1: No extra dealy on pins.
Reset type: CPU1.SYSRSn

2592

Universal Parallel Port (uPP)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Chapter 25
SPRUHM8G – December 2013 – Revised September 2017

External Memory Interface (EMIF)
This chapter describes the external memory interface (EMIF).
Topic

25.1
25.2
25.3
25.4
25.5

...........................................................................................................................
Introduction ...................................................................................................
Configuring Device Pins ..................................................................................
EMIF Module Architecture ................................................................................
Example Configuration ....................................................................................
Registers .......................................................................................................

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Page

2594
2596
2596
2628
2636

External Memory Interface (EMIF)

2593

Introduction

www.ti.com

25.1 Introduction
This device supports dual-core architecture; in order to have a dedicated EMIF for each CPU subsystem,
the device supports two EMIF modules — EMIF1 and EMIF2. Both modules are exactly the same with the
same feature set, but have different address/data sizes. EMIF1 is shared between the CPU1 and CPU2
subsystem, whereas EMIF2 is dedicated to the CPU1 subsystem. Figure 25-1 represents the two
modules.
Figure 25-1. EMIF Module Overview
CPU1
CPU1.DMA

16/32-bit
Interface

Arbiter/
Memory
Protection

CPU2

EMIF1

CPU2.DMA

16-bit
Interface

CPU1
Arbiter/
Memory
Protection

EMIF2

CPU1.CLA1

Table 25-1 gives the configuration for two EMIF modules.
Table 25-1. Configuration for EMIF1 and EMIF2
Modules
EMIF1

EMIF2

176-Pin Package

Yes

NA

337- Pin Package

Yes

Yes

Max Data Width

32

16

Max Address Width 22 (Some of EMIF1 pins are
muxed with each other.
Please refer to the IO mux
section for exact usage)

12

SDRAM CSx
Support

1 (CS0)

1(CS0)

ASRAM CSx
Support

3 (CS2/CS3/CS4)

1(CS2)

NOTE: Subsequent sections in this chapter will provide the details on generic EMIF modules unless
otherwise specified. Pin names are used from EMIF1 to define the functionality.

NOTE: On this device, if EMIF1 is chosen to have a 32-bit data width, EMIF2 cannot be used
because EMIF2 data pins are muxed with EMIF1 MSB data pins.

2594

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Introduction

www.ti.com

25.1.1 Purpose of the Peripheral
This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 32-bit/16bit data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of
external devices including:
• Single data rate (SDR) SDRAM
• Asynchronous devices including NOR Flash and SRAM
A common use for the EMIF is to interface with both a flash device and an SDRAM device simultaneously.
Section 25.4 contains an example of operating the EMIF in this configuration.

25.1.2 Features
The EMIF controller includes many features to enhance the ease and flexibility of connecting to the
external SDR SDRAM and asynchronous devices.
25.1.2.1 Asynchronous Memory Support
The EMIF controller supports asynchronous:
• SRAM memories
• NOR Flash memories
There is an external wait input that allows slower asynchronous memories to extend the memory access.
The EMIF module supports more than one chip select (enable). Each chip select has the following
individually programmable attributes:
• Data bus width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turnaround time
• Extended wait option with programmable timeout
• Select strobe option
25.1.2.2 Synchronous DRAM Memory Support
The EMIF module supports 16-bit/32-bit SDRAM in addition to the asynchronous memories listed in
Section 25.1.2.1. It has a single SDRAM chip select. SDRAM configurations that are supported are:
• One, two and four bank SDRAM devices
• Devices with eight, nine, ten, and eleven column address
• CAS latency of two or three clock cycles
• 16-bit/32-bit data bus width
• 3.3V LVCMOS interface
Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. The selfrefresh mode allows the SDRAM to be put in a low-power state while still retaining memory contents,
since the SDRAM will continue to refresh itself even without clocks from the microcontroller. The powerdown mode achieves even lower power, except the microcontroller must periodically wake up and issue
refreshes if data retention is required.
Note that the EMIF module does not support mobile SDRAM devices.

25.1.3 Functional Block Diagram
Figure 25-2 illustrates the connections between the EMIF and its internal requesters, along with the
external EMIF pins. Section 25.3.2 contains a description of the entities internal to the MCU that can send
requests to the EMIF, along with their prioritization. Section 25.3.3 describes the EMIF external pins and
summarizes their purpose when interfacing with the SDRAM and asynchronous devices.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2595

Configuring Device Pins

www.ti.com

Figure 25-2. EMIF Functional Block Diagram

EMIF
EMxCS0
EMxCAS
EMxRAS
EMxCLK
EMxSDCKE

Master
Access

SDRAM
interface

EMxCS[x:2]
EMxOE
EMxWAIT
EMxRNW

EMxWE
EMxBA[1:0]
EMxDQM[x:0]
EMxD[x:0]
EMxA[x:0]

Asynchronous
interface

Shared SDRAM
and asynchronous
interface

25.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.

25.3 EMIF Module Architecture
This section provides details about the architecture and operation of the EMIF. Both the SDRAM and
asynchronous interface are covered, along with other system-related configurations such as clock control.

25.3.1 EMIF Clock Control
The EMIF clock is output on the EMxCLK pin and should be used when interfacing to external SDRAM
devices. The EMIF module gets the PLLSYSCLK clock domain as the input. The user can choose to run
the EMIF at PLLSYSCLK/1 or PLLSYSCLK/2 clock frequency by configuring the EMIFxCLKDIV field in the
PERCLKDIVSEL register in the Clock Control module.

25.3.2 EMIF Requests
Different sources within the MCU can make requests to the EMIF. These requests consist of accesses to
the SDRAM memory, the asynchronous memory, and the EMIF registers. The EMIF can process only one
request at a time. Therefore, a high performance master arbitration block exists within the MCU to provide
prioritized requests from the different sources to the EMIF. The sources are:
• CPU1
• CPU1.DMA
• CPU2
• CPU2.DMA
2596

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

If a request is submitted from two or more sources simultaneously, the crossbar switch will forward the
highest priority request to the EMIF first. Upon completion of a request, the master arbitration block again
evaluates the pending requests and forwards the highest priority pending request to the EMIF.
The master arbitration block always allows RD access from any of the masters. But for WR access (or
execute access), the master arbitration block only allows access of masters from a CPU subsystem which
grabs master ownership of the EMIF module based on the configuration in the EMIF1MSEL register in the
Memory Controller module. Please note that only the EMIF1 has access from both the CPU subsystems;
hence the concept of grab-semaphore is applicable for the EMIF1 only.
When the EMIF receives a request, it may or may not be immediately processed. In some cases, the
EMIF will perform one or more auto refresh cycles before processing the request. For details on the
EMIF's internal arbitration between performing requests and performing auto refresh cycles, see
Section 25.3.13.

25.3.3 EMIF Signal Descriptions
This section describes the function of each of the EMIF signals.
Table 25-2. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories
Pins(s)

I/O

Description

EM1D[x:0]

I/O

EMIF data bus.

EM1A[x:0]

O

EMIF address bus.
When interfacing to an SDRAM device, these pins are primarily used to provide the row and
column address to the SDRAM. The mapping from the internal program address to the external
values placed on these pins can be found in Table 25-14. EM1A[10] is also used during the PRE
command to select which banks to deactivate.
When interfacing to an asynchronous device, these pins are used in conjunction with the EM1BA
pins to form the address that is sent to the device. The mapping from the internal program
address to the external values placed on these pins can be found in Section 25.3.6.1.

EM1BA[1:0]

O

EMIF bank address.
When interfacing to an SDRAM device, these pins are used to provide the bank address inputs to
the SDRAM. The mapping from the internal program address to the external values placed on
these pins can be found inTable 25-14.
When interfacing to an asynchronous device, these pins are used in conjunction with the EM1A
pins to form the address that is sent to the device. The mapping from the internal program
address to the external values placed on these pins can be found in Section 25.3.6.1.

EM1DQM[x:0]

O

Active-low byte enables.
When interfacing to SDRAM, these pins are connected to the DQM pins of the SDRAM to
individually enable/disable each of the bytes in a data access.
When interfacing to an asynchronous device, these pins are connected to byte enables. See
Section 25.3.6 for details.

EM1WE

O

Active-low write enable.
When interfacing to SDRAM, this pin is connected to the nWE pin of the SDRAM and is used to
send commands to the device.
When interfacing to an asynchronous device, this pin provides a signal which is active-low during
the strobe period of an asynchronous write access cycle.

Table 25-3. EMIF Pins Specific to SDRAM
Pin(s)

I/O

Description

EM1CS0

O

Active-low chip enable pin for SDRAM devices.
This pin is connected to the chip-select pin of the attached SDRAM device and is used for
enabling/disabling commands. By default, EMIF keeps this SDRAM chip select active, even if
EMIF is not interfaced with an SDRAM device. This pin is deactivated when accessing the
asynchronous memory bank and is reactivated on completion of the asynchronous access.

EM1RAS

O

Active-low row address strobe pin.
This pin is connected to the nRAS pin of the attached SDRAM device and is used for sending
commands to the device.

EM1CAS

O

Active-low column address strobe pin.
This pin is connected to the nCAS pin of the attached SDRAM device and is used for sending
commands to the device.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF) 2597

EMIF Module Architecture

www.ti.com

Table 25-3. EMIF Pins Specific to SDRAM (continued)
Pin(s)

I/O

Description

EM1SDCKE

O

Clock enable pin.
This pin is connected to the CKE pin of the attached SDRAM device and is used for issuing the
SELF REFRESH command which places the device in self-refresh mode. See Section 25.3.5.7
for details.

EM1CLK

O

SDRAM clock pin.
This pin is connected to the CLK pin of the attached SDRAM device. See Section 25.3.1 for
details on the clock signal.

Table 25-4. EMIF Pins Specific to Asynchronous Memory
Pin(s)

I/O

Description

EM1CS[4:2]

O

Active-low chip enable pins for asynchronous devices.
These pins are meant to be connected to the chip-select pins of the attached asynchronous
device. These pins are active only during accesses to the asynchronous memory.

EM1WAIT

I

Wait input with programmable polarity.
A connected asynchronous device can extend the strobe period of an access cycle by asserting
the EM1WAIT input to EMIF as described in Section 25.3.6.6. To enable this functionality, the EW
bit in the asynchronous 1 configuration register (ASYNC_CS2_CFG) must be set to 1. In addition,
the WP0 bit in ASYNC_CS2_CFG must be configured to define the polarity of the EM1WAIT pin.

EM1OE

O

Active-low pin enable for asynchronous devices.
This pin provides a signal which is active-low during the strobe period of an asynchronous read
access cycle.

EM1RNW

O

EMIF asynchronous read/write control.
This pin stays high during reads and stays low during writes (same duration as CS).

25.3.4 EMIF Signal Multiplexing Control
Several EMIF signals are multiplexed with other functions on this microcontroller. Please refer to the
multiplexing section of the GPIO chapter for more information on how to enable the output of these EMIF
signals.

25.3.5 SDRAM Controller and Interface
The EMIF controller provides a glueless interface to most standard SDR SDRAM devices and supports
features like self-refresh mode and prioritized refresh. In addition, it provides flexibility through
programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
The following sections include details on how to Interface and properly configure the EMIF to perform read
and write operations to externally connected SDR SDRAM devices. Also, Section 25.4 provides a detailed
example of interfacing the EMIF to a common SDRAM device.
25.3.5.1 SDRAM Commands
The EMIF controller supports the SDRAM commands described in Table 25-5. Table 25-6 shows the truth
table for the SDRAM commands, and an example timing waveform of the PRE command is shown in
Figure 25-3. EM1A[10] is pulled low in this example to deactivate only the bank specified by the EM1BA
pins.
Table 25-5. EMIF SDRAM Commands
Command

Function

PRE

Precharge. Depending on the value of EM1A[10], the PRE command either deactivates the open row in all banks
(EM1A[10] = 1) or only the bank specified by the EM1BA[1:0] pins (EM1A[10] = 0).

ACTV

Activate. The ACTV command activates the selected row in a particular bank for the current access.

2598External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

Table 25-5. EMIF SDRAM Commands (continued)
Command

Function

READ

Read. The READ command outputs the starting column address and signals the SDRAM to begin the burst read
operation. Address EM1A[10] is always pulled low to avoid auto precharge. This allows for better bank interleaving
performance.

WRT

Write. The WRT command outputs the starting column address and signals the SDRAM to begin the burst write
operation. Address EM1A[10] is always pulled low to avoid auto precharge. This allows for better bank interleaving
performance.

BT

Burst terminate. The BT command is used to truncate the current read or write burst request.

LMR

Load mode register. The LMR command sets the mode register of the attached SDRAM devices and is only
issued during the SDRAM initialization sequence described in Section 25.3.5.4.

REFR

Auto refresh. The REFR command signals the SDRAM to perform an auto refresh according to its internal
address.

SLFR

Self refresh. The self-refresh command places the SDRAM into self-refresh mode, during which it provides its own
clock signal and auto refresh cycles.

NOP

No operation. The NOP command is issued during all cycles in which one of the above commands is not issued.

Table 25-6. Truth Table for SDRAM Commands
SDRAM Pins:

CKE

nCS

nRAS

nCAS

nWE

BA[1:0]

A[12:11]

A[10]

A[9:0]

EM1SDCKE

EM1CS[0]

EM1RAS

EM1CAS

EM1WE

EM1BA[1:0]

EM1A[12:11]

EM1A[10]

EM1A[9:0]

PRE

H

L

L

H

L

Bank/X

X

L/H

X

ACTV

H

L

L

H

H

Bank

Row

Row

Row

READ

H

L

H

L

H

Bank

Column

L

Column

WRT

H

L

H

L

L

Bank

Column

L

Column

BT

H

L

H

H

L

X

X

X

X

LMR

H

L

L

L

L

X

Mode

Mode

Mode

REFR

H

L

L

L

H

X

X

X

X

SLFR

L

L

L

L

H

X

X

X

X

NOP

H

L

H

H

H

X

X

X

X

EMIF Pins:

Figure 25-3. Timing Waveform of SDRAM PRE Command
PRE
EM1CLK

EM1CS[0]
EM1DQM

EM1BA

Bank

EM1A

EM1A[10]=0

EM1RAS
EM1CAS
EM1WE

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2599

EMIF Module Architecture

www.ti.com

25.3.5.2 Interfacing to SDRAM
The EMIF supports a glueless interface to SDRAM devices with the following characteristics:
• Pre-charge bit is A[10]
• The number of column address bits is 8, 9, 10, or 11.
• The number of row address bits is 13, 14, 15, or 16.
• The number of internal banks is 1, 2, or 4.
Figure 25-4 shows an interface between the EMIF and a 2M × 16 × 4 bank SDRAM device, and
Figure 25-5 shows an interface between the EMIF and a 512K × 16 × 2 bank SDRAM device. For devices
supporting 16-bit interface, refer to Table 25-7 for list of commonly-supported SDRAM devices and the
required connections for the address pins.
Figure 25-4. EMIF to 2M × 16 × 4 bank SDRAM Interface
EMIF
EM1CS[0]
EM1CAS
EM1RAS
EM1WE
EM1CLK
EM1CKE
EM1BA[1:0]

nCE
nCAS
nRAS
nWE
CLK
CKE
BA[1:0]

EM1A[11:0]
EM1DQM[0]
EM1DQM[1]
EM1D[15:0]

A[11:0]
LDQM
UDQM
DQ[15:0]

SDRAM
2M x 16
x 4 bank

Figure 25-5. EMIF to 512K × 16 × 2 bank SDRAM Interface
EMIF
EM1CS[0]
EM1CAS
EM1RAS
EM1WE
EM1CLK
EM1CKE
EM1BA[0]

nCE
nCAS
nRAS
nWE
CLK
CKE
BA[0]

EM1A[10:0]
EM1DQM[0]
EM1DQM[1]
EM1D[15:0]

SDRAM
512K x 16
x 2 bank

A[10:0]
LDQM
UDQM
DQ[15:0]

Table 25-7. 16-bit EMIF Address Pin Connections
SDRAM Size

Width

Banks

Device

16M bits

×16

2

SDRAM

A[10:0]

EMIF

EM1A[10:0]

SDRAM

A[11:0]

EMIF

EM1A[11:0]

64M bits

×16

2600External Memory Interface (EMIF)

4

Address Pins

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

Table 25-7. 16-bit EMIF Address Pin Connections (continued)
SDRAM Size

Width

Banks

Device

Address Pins

128M bits

×16

4

SDRAM

A[11:0]

EMIF

EM1A[11:0]

256M bits

x16

4

SDRAM

A[12:0]

EMIF

EM1A[12:0]

SDRAM

A[12:0]

EMIF

EM1A[12:0]

512M bits

x16

4

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2601

EMIF Module Architecture

www.ti.com

25.3.5.3 SDRAM Configuration Registers
The operation of the EMIF's SDRAM interface is controlled by programming the appropriate configuration
registers. This section describes the purpose and function of each configuration register, but Section 25.5
should be referred for a more detailed description of each register, including the default registers values
and bit-field positions. The following tables list the four such configuration registers, along with a
description of each of their programmable fields.
NOTE: Writing to any of the fields: NM, CL, IBANK, and PAGESIZE in the SDRAM configuration
register (SDRAM_CR) causes the EMIF to abandon whatever it is currently doing and trigger
the SDRAM initialization procedure described in Section 25.3.5.4.

Table 25-8. Description of the SDRAM Configuration Register (SDRAM_CR)
Parameter

Description

SR

This bit controls entering and exiting of the self-refresh mode

PD

This bit controls entering and exiting of the power-down mode. If both SR and PD bits are set, the EMIF
will go into self-refresh mode.

PDWR

Perform refreshes during power Down. Writing a 1 to this bit will cause the EMIF to exit the power down
state and issue an AUTO REFRESH command every time Refresh May level is set. This bit should be
set along with PD when entering power-down mode.

NM

Narrow Mode. This bit defines the width of the data bus between the EMIF and the attached SDRAM
device. When set to 1, the data bus is set to 16-bits. When set to 0, the data bus is set to 32-bits.

CL

CAS latency. This field defines the number of clock cycles between when an SDRAM issues a READ
command and when the first piece of data appears on the bus. The value in this field is sent to the
attached SDRAM device via the LOAD MODE REGISTER command during the SDRAM initialization
procedure as described in Section 25.3.5.4. Only, values of 2h (CAS latency = 2) and 3h (CAS latency =
3) are supported and should be written to this field. While updating the CL field, BIT11_9LOCK bit field
must be set to '1' simultaneously.

IBANK

Number of Internal SDRAM Banks. This field defines the number of banks inside the attached SDRAM
devices in the following way:
• When IBANK = 0, 1 internal bank is used
• When IBANK = 1h, 2 internal banks are used
• When IBANK = 2h, 4 internal banks are used
This field value affects the mapping of logical addresses to the SDRAM row, column, and bank
addresses. See Section 25.3.5.11 for details.

PAGESIZE

Page Size. This field defines the internal page size of the attached SDRAM devices in the following way:
• When PAGESIZE = 0, 256-word pages are used
• When PAGESIZE = 1h, 512-word pages are used
• When PAGESIZE = 2h, 1024-word pages are used
• When PAGESIZE = 3h, 2048-word pages are used
This field value affects the mapping of logical addresses to the SDRAM row, column, and bank
addresses. See Section 25.3.5.11 for details.

Table 25-9. Description of the SDRAM Refresh Control Register (SDRAM_RCR)

2602

Parameter

Description

RR

Refresh Rate. This field controls the rate at which attached SDRAM devices will be refreshed. The
following equation can be used to determine the required value of RR for an SDRAM device:
• RR = fEM1CLK / (Required SDRAM Refresh Rate)
More information about the operation of the SDRAM refresh controller can be found in Section 25.3.5.6.

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

Table 25-10. Description of the SDRAM Timing Register (SDRAM_TR)
Parameter

Description

T_RFC

SDRAM Timing Parameters. These fields configure the EMIF to comply with the AC timing
requirements of the attached SDRAM devices. This allows the EMIF to avoid violating SDRAM timing
constraints and to more efficiently schedule its operations. More details about each of these parameters
can be found in the SDRAM_TR register description. These parameters should be set to satisfy the
corresponding timing requirements found in the SDRAM data sheet.

T_RP
T_RCD
T_WR
T_RAS
T_RC
T_RRD

Table 25-11. Description of the SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG)
Parameter

Description

T_XS

Self Refresh Exit Parameter. The T_XS field of this register informs the EMIF about the minimum
number of EM1CLK cycles required between exiting self-refresh and issuing any command. This
parameter should be set to satisfy the tXSR value for the attached SDRAM device.

25.3.5.4 SDRAM Auto-Initialization Sequence
The EMIF automatically performs an SDRAM initialization sequence, regardless of whether it is interfaced
to an SDRAM device, when either of the following two events occur:
• The EMIF comes out of reset. No memory accesses to the SDRAM and asynchronous interfaces are
performed until this auto-initialization is complete.
• A write is performed to any of the three least significant bytes of the SDRAM configuration register
(SDRAM_CR)
An SDRAM initialization sequence consists of the following steps:
1. If the initialization sequence is activated by a write to SDRAM_CR, and if any of the SDRAM banks are
open, the EMIF issues a PRE command with EM1A[10] held high to indicate all banks. This is done so
that the maximum ACTV to PRE timing for an SDRAM is not violated.
2. The EMIF drives EM1SDCKE high and begins continuously issuing NOP commands until eight
SDRAM refresh intervals have elapsed. An SDRAM refresh interval is equal to the value of the RR
field of the SDRAM refresh control register (SDRAM_RCR), divided by the frequency of EM1CLK
(RR/fEM1CLK). This step is used to avoid violating the power-up constraint of most SDRAM devices that
requires 200 μs (sometimes 100 μs) between receiving stable Vdd and CLK and the issuing of a PRE
command. Depending on the frequency of EM1CLK, this step may or may not be sufficient to avoid
violating the SDRAM constraint. See Section 25.3.5.5 for more information.
3. After the refresh intervals have elapsed, the EMIF issues a PRE command with EM1A[10] held high to
indicate all banks.
4. The EMIF issues eight AUTO REFRESH commands.
5. The EMIF issues the LMR command with the EM1A[9:0] pins set as described in Table 25-12.
6. Finally, the EMIF performs a refresh cycle, which consists of the following steps:
a. Issuing a PRE command with EM1A[10] held high if any banks are open
b. Issuing an REF command

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF) 2603

EMIF Module Architecture

www.ti.com

Table 25-12. SDRAM LOAD MODE REGISTER Command
EM1A[9:7]

EM1A[6:4]

0 (Write bursts are of These bits control the CAS latency of the
the programmed burst SDRAM and are set according to CL field in
length in EM1A[2:0])
the SDRAM configuration register
(SDRAM_CR) as follows:
• If CL = 2, EM1A[6:4] = 2h
(CAS latency = 2)
• If CL = 3, EM1A[6:4] = 3h
(CAS latency = 3)

EM1A[3]

EM1A[2:0]

0 (Sequential Burst
Type. Interleaved
Burst Type not
supported)

These bits control the burst length of the
SDRAM and are set according to the NM
field in the SDRAM configuration register
(SDRAM_CR) as follows:
• If NM = 0, EM1A[2:0] = 2h
(Burst Length = 4)
• If NM = 1, EM1A[2:0] = 3h
(Burst Length = 8)

25.3.5.5 SDRAM Configuration Procedure
There are two different SDRAM configuration procedures. Although the EMIF automatically performs the
SDRAM initialization sequence described in Section 25.3.5.4 when coming out of reset, it is recommended
to follow one of the procedures listed below before performing any EMIF memory requests. Procedure A
should be followed if it is determined that the SDRAM power-up constraint was not violated during the
SDRAM auto-initialization sequence detailed in Section 25.3.5.4 on coming out of Reset. The SDRAM
power-up constraint specifies that 200 μs (sometimes 100 μs) should exist between receiving stable Vdd
and CLK and the issuing of a PRE command. Procedure B should be followed if the SDRAM power-up
constraint was violated. The 200 μs (100 μs) SDRAM power-up constraint will be violated if the frequency
of EM1CLK is greater than 50 MHz (100 MHz for 100 μs SDRAM power-up constraint) during SDRAM
Auto-Initialization Sequence. Procedure B should be followed if there is any doubt that the power-up
constraint was not met.
Procedure A — Following is the procedure to be followed if the SDRAM power-up constraint was NOT
violated:
1. Place the SDRAM into self-refresh mode by setting the SR bit of SDRAM_CR to 1. The SDRAM
should be placed into self-refresh mode when changing the frequency of the EM1CLK to avoid
incurring the 200 μs power-up constraint again.
2. Configure the desired EMIF1 clock (EM1CLK) frequency. The frequency of the memory clock must
meet the timing requirements in the SDRAM manufacturer's documentation and the timing limitations
shown in the electrical specifications of the device data manual.
3. Remove the SDRAM from self-refresh Mode by clearing the SR bit of the SDRAM_CR to 0.
4. Program SDRAM_TR and SDR_EXT_TMNG to satisfy the timing requirements for the attached
SDRAM device. The timing parameters should be taken from the SDRAM data sheet.
5. Program the RR field of SDRAM_RCR to match that of the attached device's refresh interval. See
Section 25.3.5.6.1 details on determining the appropriate value.
6. Program the SDRAM_CR to match the characteristics of the attached SDRAM device. This will cause
the auto-initialization sequence in Section 25.3.5.4 to be re-run. This second initialization generally
takes much less time due to the increased frequency of EM1CLK.
Procedure B — Following is the procedure to be followed if the SDRAM power-up constraint was
violated:
1. Configure the desired EM1CLK clock frequency. The frequency of the memory clock must meet the
timing requirements in the SDRAM manufacturer's documentation and the timing limitations shown in
the electrical specifications of the device data manual.
2. Program SDRAM_TR and SDR_EXT_TMNG to satisfy the timing requirements for the attached
SDRAM device. The timing parameters should be taken from the SDRAM data sheet.
3. Program the RR field of the SDRAM_RCR such that the following equation is satisfied:
(RR × 8)/(fEM1CLK) > 200 μs (sometimes 100 μs). For example, an EM1CLK frequency of 100 MHz
would require setting RR to 2501 (9C5h) or higher to meet a 200 μs constraint.
4. Program the SDRAM_CR to match the characteristics of the attached SDRAM device. This will cause
the auto-initialization sequence in Section 25.3.5.4 to be re-run with the new value of RR.
2604

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

5. Perform a read from the SDRAM to assure that step 5 of this procedure will occur after the initialization
process has completed. Alternatively, wait for 200 μs instead of performing a read.
6. Finally, program the RR field to match that of the attached device's refresh interval. See
Section 25.3.5.6.1 details on determining the appropriate value.
After following the above procedure, the EMIF is ready to perform accesses to the attached SDRAM
device.
25.3.5.6 EMIF Refresh Controller
An SDRAM device requires that each of its rows be refreshed at a minimum required rate. The EMIF can
meet this constraint by performing auto refresh cycles at or above this required rate. An auto-refresh cycle
consists of issuing a PRE command to all banks of the SDRAM device followed by issuing a REFR
command. To inform the EMIF of the required rate for performing auto refresh cycles, the RR field of the
SDRAM refresh control register (SDRAM_RCR) must be programmed. The EMIF will use this value along
with two internal counters to automatically perform auto refresh cycles at the required rate. The autorefresh cycles cannot be disabled, even if the EMIF is not interfaced with an SDRAM. The remainder of
this section details the EMIF's refresh scheme and provides an example for determining the appropriate
value to place in the RR field of the SDRAM_RCR.
The two counters used to perform auto-refresh cycles are a 13-bit refresh interval counter and a 4-bit
refresh backlog counter. At reset and upon writing to the RR field, the refresh interval counter is loaded
with the value from RR field and begins decrementing, by one, each EMIF clock cycle. When the refresh
interval counter reaches zero, the following actions occur:
• The refresh interval counter is reloaded with the value from the RR field and restarts decrementing.
• The 4-bit refresh backlog counter increments unless it has already reached its maximum value.
The refresh backlog counter records the number of auto refresh cycles that the EMIF currently has
outstanding. This counter is decremented by one each time an auto refresh cycle is performed and
incremented by one each time the refresh interval counter expires. The refresh backlog counter saturates
at the values of 0000b and 1111b. The EMIF uses the refresh backlog counter to determine the urgency
with which an auto refresh cycle should be performed. The four levels of urgency are described in
Table 25-13. This refresh scheme allows the required refreshes to be performed with minimal impact on
access requests.
Table 25-13. Refresh Urgency Levels
Urgency Level

Refresh Backlog
Counter Range

Action Taken

Refresh May

1-3

An auto-refresh cycle is performed only if the EMIF has no requests pending and none
of the SDRAM banks are open.

Refresh Release

4-7

An auto-refresh cycle is performed if the EMIF has no requests pending, regardless of
whether any SDRAM banks are open.

Refresh Need

8-11

An auto-refresh cycle is performed at the completion of the current access unless
there are read requests pending.

Refresh Must

12-15

Multiple auto-refresh cycles are performed at the completion of the current access
until the Refresh Release urgency level is reached. At that point, the EMIF can begin
servicing any new read or write requests.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2605

EMIF Module Architecture

www.ti.com

25.3.5.6.1 Determining the Appropriate Value for the RR Field
The value that should be programmed into the RR field of the SDRAM_RCR can be calculated by using
the frequency of the EM1CLK signal (fEM1CLK) and the required refresh rate of the SDRAM (fRefresh). The
following formula can be used:
RR = fEM1CLK / fRefresh
The SDRAM data sheet often communicates the required SDRAM Refresh Rate in terms of the number of
REFR commands required in a given time interval. The required SDRAM Refresh Rate in the formula
above can therefore be calculated by dividing the number of required cycles per time interval (ncycles) by
the time interval given in the data manual (tRefresh Period) :
fRefresh = ncycles / tRefresh Period
Combining these formulas, the value that should be programmed into the RR field can be computed as:
RR = fEM1CLK × tRefresh Period / ncycles
The following example illustrates calculating the value of RR. Given that:
• fEM1CLK = 100 MHz (frequency of EMIF clock)
• tRefresh Period = 64 ms (required refresh interval of the SDRAM)
• ncycles = 8192 (number of cycles in a refresh interval for the SDRAM)
RR can be calculated as:
RR = 100 MHz × 64 ms/8192
RR = 781.25
RR = 782 cycles = 30Eh cycles
25.3.5.7 Self-Refresh Mode
The EMIF can be programmed to enter the self-refresh state by setting the SR bit of SDRAM_CR to 1.
This will cause the EMIF to issue the SLFR command after completing any outstanding SDRAM access
requests and clearing the refresh backlog counter by performing one or more auto refresh cycles. This
places the attached SDRAM device into self-refresh mode in which it consumes a minimal amount of
power while performing its own refresh cycles.
While in the self-refresh state, the EMIF continues to service asynchronous bank requests and register
accesses as normal, with one caveat. The EMIF will not park the data bus following a read to
asynchronous memory while in the self-refresh state. Instead, the EMIF tri-states the data bus. Therefore,
it is not recommended to perform asynchronous read operations while the EMIF is in the self-refresh state,
in order to prevent floating inputs on the data bus. More information about data bus parking can be found
in Section 25.3.7.
The EMIF will exit from the self-refresh state if either of the following events occur:
• The SR bit of SDRAM_CR is cleared to 0.
• An SDRAM accesses is requested.
The EMIF exits from the self-refresh state by driving EM1SDCKE high and performing an auto refresh
cycle.
The attached SDRAM device should also be placed into self-refresh mode when changing the frequency
of EM1CLK. If the frequency of EM1CLK changes while the SDRAM is not in self-refresh mode,
Procedure B in Section 25.3.5.5 should be followed to reinitialize the device.

2606

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.5.8 Power Down Mode
To support low-power modes, the EMIF can be requested to issue a POWER DOWN command to the
SDRAM by setting the PD bit in the SDRAM configuration register (SDRAM_CR). When this bit is set, the
EMIF will continue normal operation until all outstanding memory access requests have been serviced and
the SDRAM refresh backlog (if there is one) has been cleared. At this point the EMIF will enter the powerdown state. Upon entering this state, the EMIF will issue a POWER DOWN command (same as a NOP
command but driving the EM1SDCKE low on the same cycle). The EMIF then maintains the EM1SDCKE
low until it exits the power-down state.
Since the EMIF services the refresh backlog before it enters the power-down state, all internal banks of
the SDRAM are closed (precharged) prior to issuing the POWER DOWN command. Therefore, the EMIF
only supports precharge power-down. The EMIF does not support active power-down, where internal
banks of the SDRAM are open (active) before the POWER DOWN command is issued.
During the power-down state, the EMIF services the SDRAM, asynchronous memory, and register
accesses as normal, returning to the power-down state upon completion.
The PDWR bit in the SDRAM_CR indicates whether the EMIF should perform refreshes in power-down
state. If the PDWR bit is set, the EMIF exits the power-down state every time the Refresh Must level is
set, performs AUTO REFRESH commands to the SDRAM, and returns back to the power-down state.
This evenly distributes the refreshes to the SDRAM in power-down state. If the PDWR bit is not set, the
EMIF does not perform any refreshes to the SDRAM. Therefore, the data integrity of the SDRAM is not
assured upon power-down exit if the PDWR bit is not set.
If the PD bit is cleared while in the power-down state, the EMIF will come out of the power-down state.
The EMIF:
• Drives EM1SDCKE high
• Enters its idle state

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2607

EMIF Module Architecture

www.ti.com

25.3.5.9 SDRAM Read Operation
When the EMIF receives a read request to the SDRAM from one of the requesters listed in Section 25.3.2,
it performs one or more read access cycles. A read access cycle begins with the issuing of the ACTV
command to select the desired bank and row of the SDRAM device. After the row has been opened, the
EMIF proceeds to issue a READ command while specifying the desired bank and column address.
EM1A[10] is held low during the READ command to avoid auto-precharging. The READ command signals
the SDRAM device to start bursting data from the specified address while EMIF issues NOP commands.
Following a READ command, the CL field of the SDRAM configuration register (SDRAM_CR) defines how
many delay cycles will be present before the read data appears on the data bus. This is referred to as the
CAS latency.
Figure 25-6 shows the signal waveforms for a basic SDRAM read operation in which a burst of data is
read from a single page. When the EMIF SDRAM interface is configured to 16-bit by setting the NM bit of
the SDRAM configuration register (SDRAM_CR) to 1, a burst size of eight is used. Figure 25-6 shows a
burst size of eight.
The EMIF will truncate a series of bursting data if the remaining addresses of the burst are not required to
complete the request. The EMIF can truncate the burst in three ways:
• By issuing another READ to the same page in the same bank.
• By issuing a PRE command in order to prepare for accessing a different page of the same bank.
• By issuing a BT command in order to prepare for accessing a page in a different bank.
Figure 25-6. Timing Waveform for Basic SDRAM Read Operation
CL=3
ACTV
READ
EM1CLK
EM1CS[0]

EM1DQM

Bank

EM1BA
EM1A

Row

Col

EM1D

D1

D2

D3

D4

D5

D6

D7

D8

EM1RAS

EM1CAS
EM1WE

Several other pins are also active during a read access. The EM1DQM[x:0] pins are driven low during the
READ commands and are kept low during the NOP commands that correspond to the burst request. The
state of the other EMIF pins during each command can be found in Table 25-6.
The EMIF schedules its commands based on the timing information that is provided to it in the SDRAM
timing register (SDRAM_TR). The values for the timing parameters in this register should be chosen to
satisfy the timing requirements listed in the SDRAM data manual. The EMIF uses this timing information to
avoid violating any timing constraints related to issuing commands. This is commonly accomplished by
inserting NOP commands between various commands during an access. Refer to the register description
of SDRAM_TR in the SDTIMER register for more details on the various timing parameters.

2608

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.5.10 SDRAM Write Operations
When the EMIF receives a write request to SDRAM from one of the requesters listed in Section 25.3.2, it
performs one or more write-access cycles. A write-access cycle begins with the issuing of the ACTV
command to select the desired bank and row of the SDRAM device. After the row has been opened, the
EMIF proceeds to issue a WRT command while specifying the desired bank and column address.
EM1A[10] is held low during the WRT command to avoid auto-precharging. The WRT command signals
the SDRAM device to start writing a burst of data to the specified address while the EMIF issues NOP
commands. The associated write data will be placed on the data bus in the cycle concurrent with the WRT
command and with subsequent burst continuation NOP commands.
Figure 25-7 shows the signal waveforms for a basic SDRAM write operation in which a burst of data is
read from a single page. When the EMIF SDRAM interface is configured to 16-bit by setting the NM bit of
the SDRAM configuration register (SDRAM_CR) to 1, a burst size of eight is used. Figure 25-7 shows a
burst size of eight.
Figure 25-7. Timing Waveform for Basic SDRAM Write Operation
ACTV
WRT
EM1CLK

EM1CS[0]

EM1DQM

EM1BA

EM1A

EM1D

Bank

Row

Column

D1

D2

D3

D4

D5

D6

D7

D8

EM1RAS

EM1CAS

EM1WE

The EMIF will truncate a series of bursting data if the remaining addresses of the burst are not part of the
write request. The EMIF can truncate the burst in three ways:
• By issuing another WRT to the same page
• By issuing a PRE command in order to prepare for accessing a different page of the same bank
• By issuing a BT command in order to prepare for accessing a page in a different bank
Several other pins are also active during a write access. The EM1DQM[x:0] pins are driven to select which
bytes of the data word will be written to the SDRAM device. They are also used to mask out entire
undesired data words during a burst access. The state of the other EMIF pins during each command can
be found in Table 25-6.
The EMIF schedules its commands based on the timing information that is provided to it in the SDRAM
timing register (SDRAM_TR). The values for the timing parameters in this register should be chosen to
satisfy the timing requirements listed in the SDRAM data sheet. The EMIF uses this timing information to
avoid violating any timing constraints related to issuing commands. This is commonly accomplished by
inserting NOP commands during various cycles of an access. Refer to the register description of
SDRAM_TR in the SDTIMR register for more details on the various timing parameters.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2609

EMIF Module Architecture

www.ti.com

25.3.5.11 Mapping from Logical Address to EMIF Pins: Changed EM1DQM[1:0] to ED
When the EMIF receives an SDRAM access request, it must convert the address of the access into the
appropriate signals to send to the SDRAM device. The details of this address mapping are shown in
Table 25-14 for 16-bit operation. Using the settings of the IBANK and PAGESIZE fields of the SDRAM
configuration register (SDRAM_CR), the EMIF determines which bits of the logical address will be mapped
to the SDRAM row, column, and bank addresses.
As the logical address is incremented by one halfword (16-bit operation), the column address is likewise
incremented by one until a page boundary is reached. When the logical address increments across a
page boundary, the EMIF moves into the same page in the next bank of the attached device by
incrementing the bank address EM1BA and resetting the column address. The page in the previous bank
is left open until it is necessary to close it. This method of traversal through the SDRAM banks helps
maximize the number of open banks inside of the SDRAM and results in an efficient use of the device.
There is no limitation on the number of banks that can be open at one time, but only one page within a
bank can be open at a time.
The EMIF uses the EM1DQM[3:0] pins during a WRT command to mask out selected bytes or entire
words. The EM1DQM[3:0] pins are always low during a READ command.
Table 25-14. Mapping from Logical Address to EMIF Pins for 32-bit SDRAM
Logical Address
IBANK

PAGESIZE

0

0

1

0

2

0

0

1

1

1

2

1

0

2

1

2

2

2

0

3

1

3

2

3

31:27

26

25

24

23

22

21:14

13

12

11

-

10

9

Row Address

-

Row Address

-

EM1BA[0]

Row Address
-

EM1BA[1:0]

Row Address

-

Row Address

-

EM1BA[0]

Row Address
-

EM1BA[1:0]

Row Address

-

Row Address

-

EM1BA[0]

Row Address
-

EM1BA[1:0]

Row Address

-

Row Address

-

EM1BA[0]

Row Address

EM1BA[1:0]

8:1

0

Col Address

EM1DQM[0]/EM1DQM[1]

Col Address

EM1DQM[0]/EM1DQM[1]

Col Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Column Address

EM1DQM[0]/EM1DQM[1]

Table 25-15. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM
Logical Address
IBANK

PAGESIZE

0

0

1

0

2

0

0

1

1

1

2

1

0

2

1

2

2

2

0

3

1

3

2

3

31:26

25

24

23

22

21

20:13

12

11

10

-

EM1BA[0]
EM1BA[1:0]

Row Address

-

EM1BA[0]

Row Address
-

EM1BA[1:0]

Row Address

-

-

EM1BA[0]
EM1BA[1:0]

Row Address
Row Address
Row Address

Col Address

Column Address
Column Address
Column Address

Row Address
Row Address

Col Address

Column Address

Row Address

-

-

7:0
Col Address

Row Address
-

-

8

Row Address

-

-

9

Row Address

Column Address
Column Address
Column Address

EM1BA[0]

Column Address

EM1BA[1:0]

Column Address

NOTE: The upper bit of the row address is used only when addressing 256-Mbit and 512-Mbit
SDRAM memories.

2610

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.6 Asynchronous Controller and Interface
The EMIF easily interfaces to a variety of asynchronous devices including NOR Flash and SRAM. It can
be operated in two major modes (see Table 25-16):
• Normal Mode
• Select Strobe Mode
Table 25-16. Normal Mode vs. Select Strobe Mode
Mode

Function of EM1DQM pins

Operation of EM1CS[4:2]

Normal Mode

Byte enables

Active during the entire asynchronous access cycle

Select Strobe Mode

Byte enables

Active only during the strobe period of an access cycle

The first mode of operation is normal mode, in which the EM1DQM pins of the EMIF function as byte
enables. In this mode, the EM1CS[4:2] pins behave as typical chip select signals, remaining active for the
duration of the asynchronous access. See Section 25.3.6.1 for an example interface with multiple 8-bit
devices.
The second mode of operation is select strobe mode, in which the EM1CS[4:2] pins act as a strobe, active
only during the strobe period of an access. In this mode, the EM1DQM pins of the EMIF function as
standard byte enables for reads and writes. A summary of the differences between the two modes of
operation are shown in Table 25-16. Refer to Section 25.3.6.4 for the details of asynchronous operations
in normal mode, and to Section 25.3.6.5 for the details of asynchronous operations in select strobe mode.
The EMIF hardware defaults to normal mode, but can be manually switched to select strobe mode by
setting the SS bit in the asynchronous m (m = 1, 2, 3, or 4) configuration register (CEnCFG) (n = 2, 3, or
4). Throughout the chapter, m can hold the values 1, 2, 3 or 4; and n can hold the values 2, 3, or 4.
The EMIF also provides configurable cycle timing parameters and an extended wait mode that allows the
connected device to extend the strobe period of an access cycle. The following sections describe the
features related to interfacing with external asynchronous devices.
25.3.6.1 Interfacing to Asynchronous Memory
Figure 25-8 shows the EMIF's external pins used in interfacing with an asynchronous device. In
EM1CS[n], n = 2, 3, or 4.
Figure 25-8. EMIF Asynchronous Interface
EMIF
EM1CS[x]
EM1WE
EM1OE
EM1WAIT

EM1D[x:0]
EM1DQM[x:0]
EM1A[x:0]
EM1BA[1:0]

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2611

EMIF Module Architecture

www.ti.com

Of special note is the connection between the EMIF and the external device's address bus. The EMIF
address pin EM1A[0] always provides the least significant bit of a 32-bit word address. Therefore, when
interfacing to a 16-bit or 8-bit asynchronous device, the EM1BA[1] and EM1BA[0] pins provide the leastsignificant bits of the halfword or byte address, respectively. Figure 25-9 and Figure 25-10 show the
mapping between the EMIF and the connected device's data and address pins for various programmed
data bus widths. The data bus width may be configured in the asynchronous n configuration register
(ASYNC_CSn_CR).
Figure 25-10 shows an interface between the EMIF and an external memory with byte enables. The EMIF
should be operated in either normal mode or select strobe mode when using this interface, so that the
EM1DQM signals operate as byte enables.
Figure 25-9. EMIF to 8-bit/16-bit Memory Interface
EMIF

8−bit
asynchronous
memory

EM1D[7:0]
EM1A[x:0]
EM1BA[1:0]

DQ[7:0]
A[(x+2):2]
A[1:0]

a) EMIF to 8-bit memory interface

EMIF

16−bit asynchronous
memory

EM1D[15:0]
EM1A[x:0]
EM1BA[1]

DQ[15:0]
A[(x+1):1]
A[0]

b) EMIF to 16-bit memory interface

Figure 25-10. Common Asynchronous Interface
EMIF

EM1CS[x]
EM1WE
EM1DQM[1:0]
EM1D[15:0]

2612

External Memory Interface (EMIF)

16−bit
asynchronous
device
nCE
nWE
BE[1:0]
DQ[15:0]

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.6.2 Accessing Larger Asynchronous Memories
If a device such as a large asynchronous flash needs to be attached to the EMIF, then GPIO pins may be
used to control the flash device’s upper address lines.
25.3.6.3 Configuring EMIF for Asynchronous Accesses
The operation of the EMIF's asynchronous interface can be configured by programming the appropriate
register fields. The reset value and bit position for each register field can be found in Section 25.5. The
following tables list the register fields that can be programmed and describe the purpose of each field.
These registers can be programmed prior to accessing the external memory, and the transfer following a
write to these registers will use the new configuration.
Table 25-17. Description of the Asynchronous m Configuration Register (ASYNC_CSn_CR)
Parameter

Description

SS

Select Strobe mode. This bit selects the EMIF's mode of operation in the following way:
• SS = 0 selects Normal Mode
–

EM1DQM pins function as byte enables

– EM1CS[4:2] active for duration of access
• SS = 1 selects Select Strobe Mode
–

EM1DQM pins function as byte enables

–

EM1CS[4:2] acts as a strobe.

EW

Extended Wait Mode enable.
• EW = 0 disables extended wait mode
• EW = 1 enables extended wait mode
When set to 1, the EMIF enables its extended wait mode in which the strobe width of an access
cycle can be extended in response to the assertion of the EM1WAIT pin. The WPn bit in the
asynchronous wait cycle configuration register (ASYNC_WCCR) controls the polarity of the
EM1WAIT pin. See Section 25.3.6.6 for more details on this mode of operation.

W_SETUP/R_SETUP

Read/Write setup widths.
These fields define the number of EMIF clock cycles of setup time for the address pins (EM1A),
byte enables (EM1DQM), and asynchronous chip enable (EM1CS[4:2]) before the read strobe pin
(EM103) or write strobe pin (EM1WE) falls, minus one cycle. For writes, the W_SETUP field also
defines the setup time for the data pins (EM1D). Refer to the asynchronous device 's data sheet
to determine the appropriate setting for this field.

W_STROBE/R_STROBE

Read/Write strobe widths.
These fields define the number of EMIF clock cycles between the falling and rising of the read
strobe pin (EM103) or write strobe pin (EM1WEn), minus one cycle. If Extended Wait Mode is
enabled by setting the EW field in the asynchronous n configuration register (ASYNC_CSn_CR),
these fields must be set to a value greater than zero. Refer to the data manual of the external
asynchronous device to determine the appropriate setting for this field.

W_HOLD/R_HOLD

Read/Write hold widths.
These fields define the number of EMIF clock cycles of hold time for the address pins (EM1A and
EM1BA), byte enables (EM1DQM), and asynchronous chip enable (EM1CS[4:2]) after the read
strobe pin (EM103) or write strobe pin (EM1WE) rises, minus one cycle. For writes, the W_HOLD
field also defines the hold time for the data pins (EM1D). Refer to the data manual of the external
asynchronous device to determine the appropriate setting for this field.

TA

Minimum turnaround time.
This field defines the minimum number of EMIF clock cycles between asynchronous reads and
writes, minus one cycle. The purpose of this feature is to avoid contention on the bus. The value
written to this field also determines the number of cycles that will be inserted between
asynchronous accesses and SDRAM accesses. Refer to the data manual of the external
asynchronous device to determine the appropriate setting for this field.

ASIZE

Asynchronous Device Bus Width.
This field determines the data bus width of the asynchronous interface in the following way:
• ASIZE = 0 selects an 8-bit bus
• ASIZE = 1 selects a 16-bit bus
• ASIZE = 2 selects a 32-bit bus
The configuration of ASIZE determines the function of the EM1A and EM1BA pins as described in
Section 25.3.6.1. This field also determines the number of external accesses required to fulfill a
request generated by one of the sources mentioned in Section 25.3.2. For example, a request for
a 32-bit word would require four external access when ASIZE = 0. Refer to the data manual of the
external asynchronous device to determine the appropriate setting for this field.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF) 2613

EMIF Module Architecture

www.ti.com

Table 25-18. Description of the Asynchronous Wait Cycle Configuration Register (ASYNC_WCCR)
Parameter

Description

WPn

EM_WAIT Polarity.
• WPn = 0 selects active-low polarity
• WPn = 1 selects active-high polarity
When set to 1, the EMIF will wait if the EM1WAIT pin is high. When cleared to 0, the EMIF will
wait if the EM1WAIT pin is low. The EMIF must have the Extended Wait Mode enabled for the
EM1WAIT pin to affect the width of the strobe period.

MAX_EXT_WAIT

Maximum Extended Wait Cycles.
This field configures the number of EMIF clock cycles the EMIF will wait for the EM1WAIT pin to
be deactivated during the strobe period of an access cycle. The maximum number of EMIF clock
cycles it will wait is determined by the following formula:
Maximum Extended Wait Cycles = (MAX_EXT_WAIT + 1) × 16
If the EM1WAIT pin is not deactivated within the time specified by this field, the EMIF resumes the
access cycle, registering whatever data is on the bus and proceeding to the hold period of the
access cycle. This situation is referred to as an Asynchronous Timeout. An Asynchronous
Timeout generates an interrupt, if it has been enabled in the EMIF interrupt mask set register
(INT_MASK_SET). Refer to Section 25.3.9.1 for more information about EMIF interrupts.

Table 25-19. Description of EMIF Interrupt Mask Set Register (INT_MSK_SET)
Parameter

Description

WR_MASK_SET

Wait Rise Mask Set.
Writing a 1 enables an interrupt to be generated when a rising edge on EM1WAIT occurs.

AT_MASK_SET

Asynchronous Timeout Mask Set.
Writing a 1 to this bit enables an interrupt to be generated when an Asynchronous Timeout
occurs.

Table 25-20. Description of EMIF Interrupt Mast Clear Register (INT_MSK_CLR)
Parameter

Description

WR_MASK_CLR

Wait Rise Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the WR_MASK_SET bit in EMIF interrupt
mask set register (INT_MASK_SET).

AT_MASK_CLR

Asynchronous Timeout Mask Clear.
Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout
occurs.

NOTE: The EMIF performs SDRAM refreshes even if the SDRAM interface is not used. If the user is
using only the ASRAM interface, then SDRAM refreshes will impact the ASRAM
performance. To avoid this, the user must set PD=1 in the SDRAM_CR register
(Emif1Regs.SDRAM_CR.bit.PD=1). This bit can be updated only if there are no pending
EMIF accesses.

25.3.6.4 Read and Write Operations in Normal Mode
Normal mode is the asynchronous interface's default mode of operation. It is selected when the SS bit in
the asynchronous n configuration register (ASYNC_CSn_CR) is cleared to 0. In this mode, the EM1DQM
pins operate as byte enables. Section 25.3.6.4.1 and Section 25.3.6.4.2 explain the details of read and
write operations while in normal mode.

2614

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.6.4.1 Asynchronous Read Operations (Normal Mode)
NOTE: During an entire asynchronous read operation, the EM1WE pin is driven high.

An asynchronous read is performed when any of the requesters mentioned in Section 25.3.2 request a
read from the attached asynchronous memory. After the request is received, a read operation is initiated
once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 25.3.13. In the event that the read request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by EMIF until the entire request is fulfilled. The
details of an asynchronous read operation in normal mode are described in Table 25-21. Also, Figure 2511 shows an example timing diagram of a basic read operation.
Table 25-21. Asynchronous Read Operation in Normal Mode
Time Interval

Pin Activity in Normal Mode

Turnaround
period

Once the read operation becomes the highest priority task for EMIF, the EMIF waits for the programmed number
of turn-around cycles before proceeding to the setup period of the operation. The number of wait cycles is taken
directly from the TA field of the asynchronous n configuration register (ASYNC_CSn_CR). Between each access
(write or read) EMIF inserts two cycles of delay even though TA field is programmed as 0.
After the EMIF has waited for the turnaround cycles to complete, it again checks to make sure that the read
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.

Start of the
setup period

The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values in
ASYNC_CSn_CR.
• The address pins EM1A and EM1BA become valid and carry the values described in Section 25.3.6.1.
• EM1CS[4:2] falls to enable the external device (if not already low from a previous operation)

Strobe period

The following actions occur during the strobe period of a read operation:
1.
2.

EM1OE falls at the start of the strobe period
On the rising edge of the clock which is concurrent with the end of the strobe period:
•

EM1OE rises

•
The data on the EM1Dx bus is sampled by EMIF.
In Figure 25-11, EM1WAIT is inactive. If EM1WAIT is instead activated, the strobe period can be extended by the
external device to give it more time to provide the data. Section 25.3.6.6 contains more details on using the
EM1WAIT pin.
End of the hold At the end of the hold period:
period
• The address pins EM1A and EM1BA become invalid
• EM1CS[4:2] rises (if no more operations are required to complete the current request)
The EMIF may be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turn-round cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, EMIF
instead enters directly into the turnaround period for the pending read or write operation.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2615

EMIF Module Architecture

www.ti.com

Figure 25-11. Timing Waveform of an Asynchronous Read Cycle in Normal Mode
Setup
2

Strobe
3

Hold
2

EM1CLK
EM1CS[x]
EM1DQM
EM1A/EM1BA

EM1D

Byte enable
Address

Data

EM1OE

EM1WE

2616

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.6.4.2 Asynchronous Write Operations (Normal Mode)
NOTE:

During an entire asynchronous write operation, the EM1OE pin is driven high.

An asynchronous write is performed when any of the requesters mentioned in Section 25.3.2 request a
write to memory in the asynchronous bank of EMIF. After the request is received, a write operation is
initiated once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 25.3.13. In the event that the write request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous write operation in normal mode are described in Table 25-22. Also,
Figure 25-12 shows an example timing diagram of a basic write operation.
Table 25-22. Asynchronous Write Operation in Normal Mode
Time Interval

Pin Activity in Normal Mode

Turnaround
period

Once the write operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
number of turn-around cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (ASYNC_CSn_CR). Between each
access (write or read) EMIF inserts two cycles of delay even though TA field is programmed as 0.
After the EMIF has waited for the turn-around cycles to complete, it again checks to make sure that the write
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, EMIF terminates the operation.

Start of the
setup period

The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in ASYNC_CSn_CR.
• The address pins EM1A and EM1BA and the data pins EM1Dx become valid. The EM1A and EM1BA pins
carry the values described in Section 25.3.6.1.
• EM1CS[4:2] falls to enable the external device (if not already low from a previous operation).

Strobe period

The following actions occur at the start of the strobe period of a write operation:
1. EM1WE falls
2. The EM1DQM pins become valid as byte enables.
The following actions occur on the rising edge of the clock which is concurrent with the end of the strobe period:
1. EM1WE rises
2. The EM1DQM pins deactivate
In Figure 25-12, EM1WAIT is inactive. If EM1WAIT is instead activated, the strobe period can be extended by the
external device to give it more time to accept the data. Section 25.3.6.6 contains more details on using the
EM1WAIT pin.

End of the hold At the end of the hold period:
period
• The address pins EM1Ax and EM1BAx become invalid
• The data pins become invalid
• EM1CS[n] (n = 2, 3, or 4) rises (if no more operations are required to complete the current request)
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2617

EMIF Module Architecture

www.ti.com

Figure 25-12. Timing Waveform of an Asynchronous Write Cycle in Normal Mode
Setup
2

Strobe
3

Hold
2

EM1CLK
EM1CS[x]
EM1DQM
EM1A/EM1BA

EM1D

Byte enable
Address
Data

EM1OE

EM1WE

2618

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.6.5 Read and Write Operation in Select Strobe Mode
Select Strobe Mode is the EMIF's second mode of operation. It is selected when the SS bit of the
asynchronous n configuration register (ASYNC_CSn_CR) is set to 1. In this mode, the EM1DQM pins
operate as byte enables and the EM1CS[n] (n = 2, 3, or 4) pin is only active during the strobe period of an
access cycle. Section 25.3.6.4.1 and Section 25.3.6.4.2 explain the details of read and write operations
while in select strobe mode.
25.3.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
NOTE:

During the entirety of an asynchronous read operation, the EM1WEn pin is driven high.

An asynchronous read is performed when any of the requesters mentioned in Section 25.3.2 request a
read from the attached asynchronous memory. After the request is received, a read operation is initiated
once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 25.3.13. In the event that the read request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous read operation in select strobe mode are described in Table 25-23. Also,
Figure 25-13 shows an example timing diagram of a basic read operation.
Table 25-23. Asynchronous Read Operation in Select Strobe Mode
Time Interval

Pin Activity in Select Strobe Mode

Turnaround
period

Once the read operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
number of turnaround cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (ASYNC_CSn_CR). Between each
access (Write or Read) EMIF inserts two cycles of delay even though TA field is programmed as 0.
After the EMIF has waited for the turn-around cycles to complete, it again checks to make sure that the read
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.

Start of the
setup period

The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values in
ASYNC_CSn_CR.
• The address pins EM1A and EM1BA become valid and carry the values described in Section 25.3.6.1.
• The EM1DQM pins become valid as byte enables.

Strobe period

The following actions occur during the strobe period of a read operation:
1.
2.

EM1CS[n] (n = 2, 3, or 4) and EM1OE fall at the start of the strobe period
On the rising edge of the clock which is concurrent with the end of the strobe period:
•

EM1CS[n] (n = 2, 3, or 4) and EM10E rise

•
The data on the EM1D bus is sampled by EMIF.
In Figure 25-13, EM1WAIT is inactive. If EM1WAIT is instead activated, the strobe period can be extended by the
external device to give it more time to provide the data. Section 25.3.6.6 contains more details on using the
EM1WAIT pin.
End of the hold At the end of the hold period:
period
• The address pins EM1A and EM1BA become invalid
• The EM1DQM pins become invalid
The EMIF may be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2619

EMIF Module Architecture

www.ti.com

Figure 25-13. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode
Setup
2

Strobe
3

Hold
2

EM1CLK
EM1CS[x]

EM1DQM
EM1A/EM1BA
EM1D

Byte enables
Address
Data

EM1OE
EM1WE

2620

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
NOTE: During the entirety of an asynchronous write operation, the EM1OE pin is driven high.

An asynchronous write is performed when any of the requesters mentioned in Section 25.3.2 request a
write to memory in the asynchronous bank of EMIF. After the request is received, a write operation is
initiated once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 25.3.13. In the event that the write request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous write operation in select strobe mode are described in Table 25-24. Also,
Figure 25-14 shows an example timing diagram of a basic write operation.
Table 25-24. Asynchronous Write Operation in Select Strobe Mode
Time Interval

Pin Activity in Select Strobe Mode

Turnaround
period

Once the write operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
number of turnaround cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (ASYNC_CSn_CR). Between each
access (Write or Read) EMIF inserts two cycles of delay even though TA field is programmed as 0.
After the EMIF has waited for the turnaround cycles to complete, it again checks to make sure that the write
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.

Start of the
setup period

The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in ASYNC_CSn_CR.
• The address pins EM1A and EM1BA and the data pins EM1D become valid. The EM1A and EM1BA pins
carry the values described in Section 25.3.6.1.
• The EM1DQM pins become active as byte enables.

Strobe period

The following actions occur at the start of the strobe period of a write operation:
• EM1CS[n] (n = 2, 3, or 4) and EM1WE fall
The following actions occur on the rising edge of the clock which is concurrent with the end of the strobe period:
• EM1CS[n] (n = 2, 3, or 4) and EM1WE rise
In Figure 25-14, EM1WAIT is inactive. If EM1WAIT is instead activated, the strobe period can be extended by the
external device to give it more time to accept the data. Section 25.3.6.6 contains more details on using the
EM1WAIT pin.

End of the hold At the end of the hold period:
period
• The address pins EM1A and EM1BA become invalid
• The data pins become invalid
• The EM1DQM pins become invalid
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2621

EMIF Module Architecture

www.ti.com

Figure 25-14. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode
Setup
2

Strobe
3

Hold
2

EM1CLK
EM1CS[x]

Byte enables

EM1DQM

Address

EM1A/EM1BA

Data

EM1D
EM1OE

EM1WE

25.3.6.6 Extended Wait Mode and the EM1WAIT Pin
The EMIF supports the extend wait mode. This is a mode in which the external asynchronous device may
assert control over the length of the strobe period. The extended wait mode can be entered by setting the
EW bit in the asynchronous n configuration register (ASYNC_CSn_CR (n = 2, 3, or 4). When this bit is
set, the EMIF monitors the EM1WAIT pin to determine if the attached device wishes to extend the strobe
period of the current access cycle beyond the programmed number of clock cycles.
When the EMIF detects that the EM1WAIT pin has been asserted, it will begin inserting extra strobe
cycles into the operation until the EM1WAIT pin is deactivated by the external device. The EMIF will then
return to the last cycle of the programmed strobe period and the operation will proceed as usual from this
point. Please refer to the device data manual for details on the timing requirements of the EM1WAIT
signal.
The EM1WAIT pin cannot be used to extend the strobe period indefinitely. The programmable
MAX_EXT_WAIT field in the asynchronous wait cycle configuration register (AWCC) determines the
maximum number of EM1CLK cycles the strobe period may be extended beyond the programmed length.
When the counter expires, the EMIF proceeds to the hold period of the operation regardless of the state of
the EM1WAIT pin. The EMIF can also generate an interrupt upon expiration of this counter. See
Section 25.3.9.1 for details on enabling this interrupt.
For the EMIF to function properly in the extended wait mode, the WPn bit of AWCC must be programmed
to match the polarity of the EM1WAIT pin. In its reset state of 1, the EMIF will insert wait cycles when the
EM1WAIT pin is sampled high. When set to 0, the EMIF will insert wait cycles only when EM1WAIT is
sampled low. This programmability allows for a glueless connection to larger variety of asynchronous
devices.
Finally, a restriction is placed on the strobe period timing parameters when operating in extended wait
mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than 4, and the sum
of the R_SETUP and R_STROBE fields must be greater than four for the EMIF to recognize the
EM1WAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are in
ASYNC_CSn_CR.

2622

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.7 Data Bus Parking
The EMIF always drives the data bus to the previous write data value when it is idle. This feature is called
data bus parking. Only when the EMIF issues a read command to the external memory does it stop
driving the data bus. After the EMIF latches the last read data, it immediately parks the data bus again.
The one exception to this behavior occurs after performing an asynchronous read operation while the
EMIF is in the self-refresh state. In this situation, the read operation is not followed by the EMIF parking
the data bus. Instead, the EMIF tri-states the data bus. Therefore, it is not recommended to perform
asynchronous read operations while the EMIF is in the self-refresh state, in order to prevent floating inputs
on the data bus. External pull-ups, such as 10kΩ resistors, should be placed on the 16 EMIF data bus
pins (which do not have internal pull-ups) if it is required to perform reads in this situation. The precise
resistor value should be chosen so that the worst case combined off-state leakage currents do not cause
the voltage levels on the associated pins to drop below the high-level input voltage requirement.
For information about the self-refresh state, see Section 25.3.5.7.

25.3.8 Reset and Initialization Considerations
The EMIF memory controller has two active-low reset signals, CHIP_RST_n and MOD_G_RST_n. Both
these reset signals are driven by the device system reset signal. This device does not offer the flexibility to
reset just the EMIF state machine without also resetting the EMIF controller's memory-mapped registers.
As soon as the device system reset is released (driven high), the EMIF memory controller immediately
begins its initialization sequence. Command and data stored in the EMIF memory controller FIFOs are
lost. Refer to Section 25.3 for more information on conditions that can cause a device system reset to be
asserted.
When system reset is released, the EMIF automatically begins running the SDRAM initialization sequence
described in Section 25.3.5.4. Even though the initialization procedure is automatic, a special procedure,
found in Section 25.3.5.5 must still be followed.

25.3.9 Interrupt Support
The EMIF supports a single interrupt to the CPU. Section 25.3.9.1 details the generation and internal
masking of EMIF interrupts.
25.3.9.1 Interrupt Events
There are three conditions that may cause the EMIF to generate an interrupt to the CPU. These conditions
are:
• A rising edge on the EM1WAIT signal (wait rise interrupt)
• An asynchronous time out
• Usage of unsupported addressing mode (line trap interrupt)
The wait rise interrupt occurs when a rising edge is detected on EM1WAIT signal. This interrupt
generation is not affected by the WPn bit in the asynchronous wait cycle configuration register
(ASYNC_WCCR). The asynchronous time out interrupt condition occurs when the attached asynchronous
device fails to deassert the EM1WAIT pin within the number of cycles defined by the MAX_EXT_WAIT bit
in AWCC (this happens only in extended wait mode). The EMIF supports only linear incrementing and
cache line wrap addressing modes . If an access request for an unsupported addressing mode is
received, the EMIF will set the LT bit in the EMIF interrupt raw register (INTRAW) and treat the request as
a linear incrementing request.
Only when the interrupt is enabled by setting the appropriate bit
(WR_MASK_SET/AT_MASK_SET/LT_MASK_SET) in the EMIF interrupt mask set register
(INT_MASK_SET) to 1, will the interrupt be sent to the CPU. Once enabled, the interrupt may be disabled
by writing a 1 to the corresponding bit in the EMIF interrupt mask clear register (INT_MASK_CLR). The bit
fields in both the INT_MASK_SET and INT_MASK_CLR may be used to indicate whether the interrupt is
enabled. When the interrupt is enabled, the corresponding bit field in both the INT_MASK_SET and
INT_MASK_CLR will have a value of 1; when the interrupt is disabled, the corresponding bit field will have
a value of 0.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2623

EMIF Module Architecture

www.ti.com

The EMIF interrupt raw register (INTRAW) and the IF interrupt mask register (INTMSK) indicate the status
of each interrupt. The appropriate bit (WR/AT/LT) in INTRAW is set when the interrupt condition occurs,
whether or not the interrupt has been enabled. However, the appropriate bit
(WR_MASKED/AT_MASKED/LT_MASKED) in INTMSK is set only when the interrupt condition occurs
and the interrupt is enabled. Writing a 1 to the bit in INTRAW clears the INTRAW bit as well as the
corresponding bit in INTMSK. Table 25-25 contains a brief summary of the interrupt status and control bit
fields. See Section 25.5 for complete details on the register fields.
Table 25-25. Interrupt Monitor and Control Bit Fields
Register Name

Bit Name

Description

EMIF interrupt raw register
(INTRAW)

WR

This bit is set when an rising edge on the EM1WAIT signal occurs.
Writing a 1 clears the WR bit as well as the WR_MASKED bit in
INTMSK.

AT

This bit is set when an asynchronous timeout occurs. Writing a 1 clears
the AT bit as well as the AT_MASKED bit in INTMSK.

LT

This bit is set when an unsupported addressing mode is used. Writing a
1 clears LT bit as well as the LT_MASKED bit in INTMSK.

WR_MASKED

This bit is set only when a rising edge on the EM1WAIT signal occurs
and the interrupt has been enabled by writing a 1 to the
WR_MASK_SET bit in INT_MASK_SET.

AT_MASKED

This bit is set only when an asynchronous timeout occurs and the
interrupt has been enabled by writing a 1 to the AT_MASK_SET bit in
INT_MASK_SET.

LT_MASKED

This bit is set only when line trap interrupt occurs and the interrupt has
been enabled by writing a 1 to the LT_MASK_SET bit in
INT_MASK_SET.

WR_MASK_SET

Writing a 1 to this bit enables the wait rise interrupt.

AT_MASK_SET

Writing a 1 to this bit enables the asynchronous timeout interrupt.

LT_MASK_SET

Writing a 1 to this bit enables the line trap interrupt.

WR_MASK_CLR

Writing a 1 to this bit disables the wait rise interrupt.

AT_MASK_CLR

Writing a 1 to this bit disables the asynchronous timeout interrupt.

LT_MASK_CLR

Writing a 1 to this bit disables the line trap interrupt.

EMIF interrupt mask register
(INTMSK)

EMIF interrupt mask set register
(INT_MASK_SET)

EMIF interrupt mask clear register
(INT_MASK_CLR)

25.3.10 DMA Event Support
The EMIF memory controller is a DMA slave peripheral and therefore does not generate DMA events.
Data read and write requests may be made directly, by masters and the DMA.

25.3.11 EMIF Signal Multiplexing
For details on the EMIF signal multiplexing, see the GPIO chapter, I/O Multiplexing Module section, of this
technical reference manual.

25.3.12 Memory Map
For information describing the device memory-map, see your device-specific data manual.

2624

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.13 Priority and Arbitration
Section 25.3.2 describes the external prioritization and arbitration among requests from different sources
within the microcontroller. The result of this external arbitration is that only one request is presented to the
EMIF at a time. Once the EMIF completes a request, the external arbiter then provides the EMIF with the
next pending request.
Internally, the EMIF undertakes memory device transactions according to a strict priority scheme. The
highest priority events are:
• A device reset.
• A write to any of the three least significant bytes of the SDRAM configuration register (SDRAM_CR).
Either of these events will cause the EMIF to immediately commence its initialization sequence as
described in Section 25.3.5.4.
Once the EMIF has completed its initialization sequence, it performs memory transactions according to the
following priority scheme (highest priority listed first):
1. If the EMIF's backlog refresh counter is at the Refresh Must urgency level, the EMIF performs multiple
SDRAM auto-refresh cycles until the Refresh Release urgency level is reached.
2. If an SDRAM or asynchronous read has been requested, the EMIF performs a read operation.
3. If the EMIF's backlog refresh counter is at the Refresh Need urgency level, the EMIF performs an
SDRAM auto refresh cycle.
4. If an SDRAM or asynchronous write has been requested, the EMIF performs a write operation.
5. If the EMIF's backlog refresh counter is at the Refresh May or Refresh Release urgency level, the
EMIF performs an SDRAM auto refresh cycle.
6. If the value of the SR bit in SDRAM_CR has been set to 1, the EMIF will enter the self-refresh state as
described in Section 25.3.5.7.
After taking one of the actions listed above, the EMIF then returns to the top of the priority list to determine
its next action.
Because the EMIF does not issue auto-refresh cycles when in the self-refresh state, the above priority
scheme does not apply when in this state. See Section 25.3.5.7 for details on the operation of the EMIF
when in the self-refresh state.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2625

EMIF Module Architecture

www.ti.com

25.3.14 System Considerations
This section describes various system considerations to keep in mind when operating the EMIF.
25.3.14.1 Asynchronous Request Times
In a system that interfaces to both SDRAM and asynchronous memory, the asynchronous requests must
not take longer than the smaller of the following two values:
• tRAS (typically 120 μs) - to avoid violating the maximum time allowed between issuing an ACTV and
PRE command to the SDRAM.
• tRefresh Rate × 11 (typically 15.7 μs × 11 = 172.7 μs) - to avoid refresh violations on the SDRAM.
The length of an asynchronous request is controlled by multiple factors, the primary factor being the
number of access cycles required to complete the request. For example, an asynchronous request for
4 bytes will require four access cycles using an 8-bit data bus and only two access cycle using a 16-bit
data bus. The maximum request size that the EMIF can be sent is 16 words, therefore the maximum
number of access cycles per memory request is 64 when the EMIF is configured with an 8-bit data
bus. The length of the individual access cycles that make up the asynchronous request is determined
by the programmed setup, strobe, hold, and turnaround values, but can also be extended with the
assertion of the EM1WAIT input signal up to a programmed maximum limit. It is up to the user to make
sure that an entire asynchronous request does not exceed the timing values listed above when also
interfacing to an SDRAM device. This can be done by limiting the asynchronous timing parameters.

2626

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

EMIF Module Architecture

www.ti.com

25.3.15 Power Management
Power dissipation from the EMIF memory controller may be managed by following methods:
• Self-refresh mode
• Power-down mode
• Gating input clocks to the module off
Gating input clocks off to the EMIF memory controller achieves higher power savings when compared to
the power savings of self-refresh or power down mode. The input clock to EMIF can be turned off through
the use of the Global Clock Module (GCM). Before gating clocks off, the EMIF memory controller must
place the SDR SDRAM memory in self-refresh mode. If the external memory requires a continuous clock,
the VCLK3 clock domain must not be turned off because this may result in data corruption. See the
following subsections for the proper procedures to follow when stopping EMIF memory controller clocks.

25.3.15.1 Power Management Using Self-Refresh Mode
The EMIF memory controller can be placed into a self-refresh state in order to place the attached SDRAM
devices into self-refresh mode, which consumes less power for most SDRAM devices. In this state, the
attached SDRAM device uses an internal clock to perform its own auto refresh cycles. This maintains the
validity of the data in the SDRAM without the need for any external commands. Refer to Section 25.3.5.7
for more details on placing the EMIF into the self-refresh state.
25.3.15.2 Power Management Using Power Down Mode
In the power down mode, the EMIF drives EM1SDCKE low to lower the power consumption. EM1SDCKE
goes high when there is a need to send refresh (REFR) commands, after which EM1SDCKE is again
driven low. EM1SDCKE remains low until any request arrives. Refer to Section 25.3.5.8 for more details
on placing the EMIF in power-down mode.

25.3.16 Emulation Considerations
The EMIF remains fully functional during emulation halts in order to allow emulation access to external
memory.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2627

Example Configuration

www.ti.com

25.4 Example Configuration
This section presents an example of interfacing the EMIF1 to both an SDR SDRAM device and an
asynchronous flash device.

25.4.1 Hardware Interface
Figure 25-15 shows the hardware interface between the EMIF, a Samsung K4S641632H-TC(L)70 64Mb
SDRAM device, and a SHARP LH28F800BJE-PTTL90 8Mb Flash memory. The connection between
EMIF and the SDRAM is straightforward, but the connection between the EMIF and the flash deserves a
detailed look.
The address inputs for the flash are provided by three sources. The A[18:0] address inputs are provided
by a combination of the EM1A and EM1BA pins according to Section 25.3.6.1, and a set of GPIO pins.
The RD/nBY signal from flash is connected to EM1WAIT pin of the EMIF.
Finally, this example configuration connects the EM1WE pin to the nWE input of the flash and operates
the EMIF in select strobe mode.

25.4.2 Software Configuration
The following sections describe how to configure the EMIF registers and bit fields to interface the EMIF
with the Samsung K4S641632H-TC(L)70 SDRAM and the SHARP LH28F800BJE-PTTL90 8Mb Flash
memory.
25.4.2.1 Configuring the SDRAM Interface
This section describes how to configure the EMIF to interface with the Samsung K4S641632H-TC(L)70
SDRAM with a clock frequency of fEM1CLK = 100 MHz. Procedure A described in Section 25.3.5.5 is
followed which assumes that the SDRAM power-up timing constraints were met during the SDRAM autoinitialization sequence after reset.
25.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
If the user has programmed the system PLL to provide SYSCLK frequency > 100 MHz, then the user must
configure the EMIF1CLKDIV field in the PERSYSCLKDIVSEL register to make EM1CLK = SYSCLK/2
(default configuration). Before doing this, the SDRAM should be placed in self-refresh mode by setting the
SR bit in the SDRAM configuration register. Once the EM1CLK frequency has been configured, remove
the SDRAM from self-refresh by clearing the SR bit in SDRAM_CR.
Table 25-26. SR Field Value For EMIF to K4S641632H-TC(L)70 Interface

2628

Field

Value

Purpose

SR

1 then 0

To place the EMIF into the self-refresh state

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Example Configuration

www.ti.com

Figure 25-15. Example Configuration Interface
EMIF
SDRAM
nCE
1M x 16
nCAS
x 4 bank
nRAS
nWE
CLK
CKE
BA[1]
BA[0]
A[11:0]
LDQM
UDQM
DQ[15:0]

EM1CS[0]
EM1CAS
EM1RAS
EM1WE
EM1CLK
EM1SDCKE
EM1BA[1]
EM1BA[0]
EM1A[11:0]
EM1DQM[0]
EMI1DQM[1]
EM1D[15:0]
EM1CS[2]
EM1OE
EM1WAIT
GPIO
(6 pin)

FLASH
A[0]
A[12:1] 512k x 16
DQ[15:0]
nCE
nWE
nOE
A[18:13]
RY/BY
nBYTE0
nBYTE1

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2629

Example Configuration

www.ti.com

25.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
The fields of the SDRAM timing register (SDRAM_TR) should be programmed first as described in
Table 25-27 to satisfy the required timing parameters for the K4S641632H-TC(L)70. Based on these
calculations, a value of 6111 4610h should be written to the SDRAM_TR. Figure 25-16 shows a graphical
description of how the SDRAM_TR should be programmed.
Table 25-27. SDRAM_TR Field Calculations for EMIF to K4S641632H-TC(L)70 Interface
Field Name

Formula

Value from K4S641632H-TC(L)70
Datasheet

Value Calculated for
Field

T_RFC

T_RFC >= (tRFC × fEM1CLK) - 1

tRC = 68 ns (min) (1)

6

T_RP

T_RP >= (tRP × fEM1CLK) - 1

tRP = 20 ns (min)

1

T_RCD

T_RCD >= (tRCD × fEM1CLK) - 1

tRCD = 20 ns (min)

1
(2)

T_WR

T_WR >= (tWR × fEM1CLK) - 1

tRDL = 2 CLK = 20 ns (min)

T_RAS

T_RAS >= (tRAS × fEM1CLK) - 1

tRAS = 49 ns (min)

4

T_RC

T_RC >= (tRC × fEM1CLK) - 1

tRC = 68 ns (min)

6

T_RRD

T_RRD >= (tRRD × fEM1CLK) - 1

tRRD = 14 ns (min)

1

(1)
(2)

1

The Samsung datasheet does not specify a tRFC value. Instead, Samsung specifies tRC as the minimum auto refresh period.
The Samsung datasheet does not specify a tWR value. Instead, Samsung specifies tRDL as last data in to row precharge minimum
delay.

Figure 25-16. SDRAM Timing Register (SDRAM_TR)
31

15

2630

30

29

28

27

26

24

23

22

21

20

19

18

17

0 0110

001

0

001

0

001

T_RFC

T_RP

Rsvd

T_RCD

Rsvd

T_WR

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0100

0110

0

001

0000

T_RAS

T_RC

Rsvd

T_RRD

Reserved

External Memory Interface (EMIF)

16

0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Example Configuration

www.ti.com

25.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to
K4S641632H-TC(L)70 Interface
The SDRAM self-refresh exit timing register (SDSRETR) should be programmed second to satisfy the tXSR
timing requirement from the K4S641632H-TC(L)70 datasheet. Table 25-28 shows the calculation of the
proper value to program into the T_XS field of this register. Based on this calculation, a value of 6h should
be written to the SDSRETR. Figure 25-17 shows how the SDSRETR should be programmed.
Table 25-28. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface
Field Name

Formula

Value from K4S641632H-TC(L)70
Datasheet

Value Calculated for
Field

T_XS

T_XS >= (tXSR × fEM1CLK) - 1

tRC = 68 ns (min) (1)

6

(1)

The Samsung datasheet does not specify a tXSR value. Instead, Samsung specifies tRC as the minimum required time after CKE
going high to complete self-refresh exit.

Figure 25-17. SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG)
31

30

29

28

27

26

25

24

23

22

21

20

19

6

5

4

3

18

17

16

2

1

0

0000 0000 0000 0000
Reserved
15

14

13

12

11

10

9

8

7

000 0000 0000

0 0110

Reserved

T_XS

25.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70
Interface
The SDRAM refresh control register (SDRAM_RCR) should next be programmed to satisfy the required
refresh rate of the K4S641632H-TC(L)70. Table 25-29 shows the calculation of the proper value to
program into the RR field of this register. Based on this calculation, a value of 61Ah should be written to
the SDRAM_RCR. Figure 25-18 shows how the SDRAM_RCR should be programmed.
Table 25-29. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface
Field Name

Formula

Values

RR

RR ≤ fEM1CLK × tRefresh Period / From SDRAM datasheet: tRefresh Period
ncycles
= 64 ms; ncycles = 4096 EMIF clock
rate: fEM1CLK = 100 MHz

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Value Calculated for Field
RR = 1562 cycles = 61Ah cycles

External Memory Interface (EMIF)

2631

Example Configuration

www.ti.com

Figure 25-18. SDRAM Refresh Control Register (SDRAM_RCR)
31

30

15

14

29

28

13

12

27

26

11

25

24

23

22

21

20

19

18

17

16

0 0000 0000 0000

000

Reserved

Reserved

10

9

8

7

6

5

4

000

0 0110 0001 1010 (61Ah)

Reserved

RR

3

2

1

0

25.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70
Interface
Finally, the fields of the SDRAM configuration register (SDRAM_CR) should be programmed as described
in Table 25-26 to properly interface with the K4S641632H-TC(L)70 device. Based on these settings, a
value of 4720h should be written to the SDRAM_CR. Figure 25-19 shows how the SDRAM_CR should be
programmed. The EMIF is now ready to perform read and write accesses to the SDRAM.
Table 25-30. SDRAM_CR Field Values For EMIF to K4S641632H-TC(L)70 Interface
Field

Value

Purpose

SR

0

To avoid placing the EMIF into the self-refresh state

NM

1

To configure the EMIF for a 16-bit data bus

CL

011b

To select a CAS latency of 3

BIT11_9LOCK

1

To allow the CL field to be written

IBANK

010b

To select 4 internal SDRAM banks

PAGESIZE

0

To select a page size of 256 words

Figure 25-19. SDRAM Configuration Register (SDRAM_CR)
31

30

29

0

0

0

28

0 0000

SR

Reserved

Reserved

Reserved

23

22

21

20

27

26

19

18

25

24

17

16

00 0000

0

0

Reserved

Reserved

Reserved

9

8

15

14

13

12

0

1

0

0

11

011

10

1

Reserved

NM

Reserved

Reserved

CL

BIT11_9LOCK

7

6

5

4

3

2

1

0

010

0

000

Reserved

IBANK

Reserved

PAGESIZE

2632

External Memory Interface (EMIF)

0

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Example Configuration

www.ti.com

25.4.2.2 Configuring the Flash Interface
This section describes how to configure the EMIF to interface with the SHARP LH28F800BJE-PTTL90
8Mb Flash memory with a clock frequency of fEM1CLK = 100 MHz.
25.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to
LH28F800BJE-PTTL90 Interface
The asynchronous 1 configuration register (ASYNC_CS2_CFG) is the only register that is necessary to
program for this asynchronous interface. The SS bit should be set to 1 to enable select strobe command
the ASIZE field should be set to 1 to select a 16-bit interface. The other fields in this register control the
shaping of the EMIF signals, and the proper values can be determined by referring to the AC
Characteristics in the Flash data manual and the device data manual. Based on the following calculations,
a value of 8862 25BDh should be written to ASYNC_CS2_CFG. Table 25-31 and Table 25-32 show the
pertinent AC Characteristics for reads and writes to the Flash device, and Figure 25-20 and Figure 25-21
show the associated timing waveforms. Finally, Figure 25-22 shows programming the ASYNC_CS2_CFG
with the calculated values.
Table 25-31. AC Characteristics for a Read Access
Device

Definition

Min

tSU

AC Characteristic

EMIF

Setup time, read EM1D before EM1CLK high

6.5

Max

Unit
ns

tH

EMIF

Data hold time, read EM1D after EM1CLK
high

1

ns

tD

EMIF

Output delay time, EM1CLK high to output
signal valid

7

ns

tELQV

Flash

nCE to Output Delay

90

ns

tEHQZ

Flash

nCE High to Output in High Impedance

55

ns

Max

Unit

Table 25-32. AC Characteristics for a Write Access
AC Characteristic

Device

Definition

tAVAV

Flash

Write Cycle Time

Min
90

ns

tELEH

Flash

nCE Pulse Width Low

50

ns

tEHEL

Flash

nCE Pulse Width High (not shown in
Figure 25-21)

30

ns

Figure 25-20. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms
Setup
Hold

Strobe

TA

EM1CLK
tD

tD
EM1CS[x]
EM1A/EMIBA

tEHQZ

tSU

tH

tELQV
Data

EM1D
EM1OE

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2633

Example Configuration

www.ti.com

Figure 25-21. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms
Setup

Hold
Strobe
tAVAV

EM1CLK
tELEH
EM1CS[x]

EM1A/EM1BA

Address

EM1D

Data

EM1WE

The R_STROBE field should be set to meet the following equation:
R_STROBE >= (tD + tELQV + tSU) × fEM1CLK - 1
R_STROBE >= (7 ns + 90 ns + 6.5 ns) × 100 MHz - 1
R_STROBE >= 9.35
R_STROBE = 10
The R_HOLD field must be large enough to satisfy EMIF Data hold time, tH:
R_HOLD > = tH × fEM1CLK - 1
R_HOLD >= 1 ns × 100 MHz - 1
R_HOLD >= -0.9
The R_HOLD field must also combine with the TA field to satisfy the Flash's nCE High to Output in High
Impedance time, tEHQZ:
R_HOLD + TA >= (tD + tEHQZ) × fEM1CLK - 2
R_HOLD + TA >= (7 ns + 55 ns) × 100 MHz - 2
R_HOLD + TA >= 4.2
The largest value that can be programmed into the TA field is 3h, therefore the following values can be
used:
R_HOLD = 2
TA = 3
For Writes, the W_STROBE field should be set to satisfy the Flash's nCE Pulse Width constraint, tELEH:
W_STROBE >= tELEH × fEM1CLK - 1
W_STROBE >= 50 ns × 100 MHz - 1
W_STROBE >= 4

2634

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Example Configuration

www.ti.com

The W_SETUP and W_HOLD fields should combine to satisfy the Flash's nCE Pulse Width High
constraint, tEHEL:
W_SETUP + W_HOLD > = tEHEL × fEM1CLK - 2
W_SETUP + W_HOLD > = 30 ns × 100 MHz - 2
W_SETUP + W_HOLD > = 1
In addition, the entire Write access length must satisfy the Flash's minimum Write Cycle Time, tAVAV:
W_SETUP + W_STROBE + W_HOLD >= tAVAV × fEM1CLK - 3
W_SETUP + W_STROBE + W_HOLD >= 90 ns × 100 MHz - 3
W_SETUP + W_STROBE + W_HOLD >= 6
Solving the above equations for the Write fields results in the following possible solution:
W_SETUP = 1
W_STROBE = 5
W_HOLD = 0
Adding a 10 ns (1 cycle) margin to each of the periods (excluding TA which is already at its maximum) in
this example produces the following recommended values:
W_SETUP = 2h
W_STROBE = 6h
W_HOLD = 1h
R_SETUP = 1h
R_STROBE = Bh
R_HOLD = 3h
TA = 3h
Figure 25-22. Asynchronous m Configuration Register (m = 1, 2) (ASYNC_CSn_CR(n = 2, 3))

15

31

30

1

0

0010

00

SS

EW

W_SETUP

W_STROBE

23

22

14

13

29

28

21

27

20

26

19

25

18

24

17

16

0110

001

0

W_STROBE

W_HOLD

R_SETUP

12

11

10

9

8

7

6

5

4

3

2

1

0

001

001011

011

11

01

R_SETUP

R_STROBE

R_HOLD

TA

ASIZE

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2635

Registers

www.ti.com

25.5 Registers
25.5.1 EMIF Base Addresses
Table 25-33. EMIF Base Address Table
Device Registers

Start Address

End Address

Emif1Regs

EMIF_REGS

0x0004_7000

0x0004_77FF

Emif2Regs (1)

EMIF_REGS

0x0004_7800

0x0004_7FFF

Emif1ConfigRegs

EMIF1_CONFIG_REGS

0x0005_F480

0x0005_F49F

Emif2ConfigRegs

EMIF2_CONFIG_REGS

0x0005_F4A0

0x0005_F4BF

(1)

2636

Register Name

Only available on CPU1.

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2 EMIF_REGS Registers
Table 25-34 lists the memory-mapped registers for the EMIF_REGS. All register offset addresses not
listed in Table 25-34 should be considered as reserved locations and the register contents should not be
modified.
Table 25-34. EMIF_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

RCSR

Revision Code and Status Register

Go

2h

ASYNC_WCCR

Async Wait Cycle Config Register

Go

4h

SDRAM_CR

SDRAM (EMxCS0n) Config Register

Go

6h

SDRAM_RCR

SDRAM Refresh Control Register

Go

8h

ASYNC_CS2_CR

Async 1 (EMxCS2n) Config Register

Go

Ah

ASYNC_CS3_CR

Async 2 (EMxCS3n) Config Register

Go

Ch

ASYNC_CS4_CR

Async 3 (EMxCS4n) Config Register

Go

10h

SDRAM_TR

SDRAM Timing Register

Go

18h

TOTAL_SDRAM_AR

Total SDRAM Accesses Register

Go

1Ah

TOTAL_SDRAM_ACTR

Total SDRAM Activate Register

Go

1Eh

SDR_EXT_TMNG

SDRAM SR/PD Exit Timing Register

Go

20h

INT_RAW

Interrupt Raw Register

Go

22h

INT_MSK

Interrupt Masked Register

Go

24h

INT_MSK_SET

Interrupt Mask Set Register

Go

26h

INT_MSK_CLR

Interrupt Mask Clear Register

Go

Complex bit access types are encoded to fit into small table cells. Table 25-35 shows the codes that are
used for access types in this section.
Table 25-35. EMIF_REGS Access Type Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

W=1

W

Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2637

Registers

www.ti.com

25.5.2.1 RCSR Register (Offset = 0h) [reset = 40000205h]
RCSR is shown in Figure 25-23 and described in Table 25-36.
Return to Summary Table.
Revision Code and Status Register
Figure 25-23. RCSR Register
31
BE
R-0h

30
FR
R-1h

29

15

14

13

28

27

26

25

24

12
11
10
MAJOR_REVISION
R-2h

9

8

23
22
MODULE_ID
R-0h
7

21

6

5

20

19

4
3
MINOR_REVISION
R-5h

18

17

16

2

1

0

Table 25-36. RCSR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

BE

R

0h

EMIF endian mode.
0: Little Endian.
1: Big Endian.
Reset type: SYSRSn

30

FR

R

1h

EMIF operating rate.
0: Half Rate.
1: Full Rate.
Reset type: SYSRSn

29-16

MODULE_ID

R

0h

EMIF module ID.
0x0000: EMIF_24.
0x000E: EMIF_24 SDRAM.
0x000F: EMIF_24 ASYNC.
Reset type: SYSRSn

15-8

MAJOR_REVISION

R

2h

Major Revision. EMIF code revisions are indicated by a revision
code taking the format major_revision.minor_revision.
Reset type: SYSRSn

7-0

MINOR_REVISION

R

5h

Minor Revision. See major_revision field description.
Reset type: SYSRSn

2638

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2.2 ASYNC_WCCR Register (Offset = 2h) [reset = F0000080h]
ASYNC_WCCR is shown in Figure 25-24 and described in Table 25-37.
Return to Summary Table.
Async Wait Cycle Config Register
Figure 25-24. ASYNC_WCCR Register
31
RESERVED
R-0h

30
RESERVED
R-0h

29
RESERVED
R-0h

28
WP0
R/W-1h

27

23

22

21

20

19

RESERVED
R-0h
15

13

25

24

RESERVED
R-0h

RESERVED
R-0h
14

26

18

17

RESERVED
R-0h
12

16
RESERVED
R-0h

11

10

9

8

4
3
MAX_EXT_WAIT
R/W-80h

2

1

0

RESERVED
R-0h
7

6

5

Table 25-37. ASYNC_WCCR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

RESERVED

R

0h

Reserved

30

RESERVED

R

0h

Reserved

29

RESERVED

R

0h

Reserved

28

WP0

R/W

1h

Defines the polarity of the EMxWAIT port.:
0: Wait if EMxWAIT port is low.
1: Wait if EMxWAIT port is high.
Reset type: SYSRSn

27-24

RESERVED

R

0h

Reserved

23-22

RESERVED

R

0h

Reserved

21-20

RESERVED

R

0h

Reserved

19-18

RESERVED

R

0h

Reserved

17-16

RESERVED

R

0h

Reserved

15-8

RESERVED

R

0h

Reserved

7-0

MAX_EXT_WAIT

R/W

80h

The EMIF will wait for (max_ext_wait + 1) * 16 clock cycles before
an extended asynchronous cycle is terminated.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2639

Registers

www.ti.com

25.5.2.3 SDRAM_CR Register (Offset = 4h) [reset = 620h]
SDRAM_CR is shown in Figure 25-25 and described in Table 25-38.
Return to Summary Table.
SDRAM (EMxCS0n) Config Register
Figure 25-25. SDRAM_CR Register
31
SR
R/W-0h

30
PD
R/W-0h

29
PDWR
R/W-0h

28

23
RESERVED
R-0h

22

21
RESERVED
R-0h

20

15
RESERVED

14
NM

13
RESERVED

12
RESERVED

R-0h

R/W-0h

R-0h

R-0h

7
RESERVED
R-0h

6

5
IBANK
R/W-2h

4

27
RESERVED
R-0h

26

19
RESERVED
R-0h

18

11

10
CL

25

24
RESERVED
R-0h

17

16
RESERVED
R-0h

9

8
BIT_11_9_LOC
K
R=0/W=1-0h

1
PAGESIGE
R/W-0h

0

RESERVED
R-0h

R/W-3h
3
RESERVED
R-0h

2

Table 25-38. SDRAM_CR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

SR

R/W

0h

Self Refresh. Writing a 1 to this bit will cause connected SDRAM
devices to be placed into Self Refresh mode and the EMIF to enter
the self refresh state. In this state the EMIF will service all
asynchronous memory accesses immediately but any SDRAM
access will take at least t_ras + 1 cycles due to the time required for
the SDRAM devices to out of Self Refresh mode. If an SDRAM
access immediately follows the setting of the sr bit, the access will
take t_ras + t_xs + 2 cycles. If both sr and pd bits are set, the EMIF
will go into Self Refresh.
Reset type: SYSRSn

30

PD

R/W

0h

Power Down. Writing a 1 to this bit will cause connected SDRAM
devices to be placed into Power Down mode. If both sr and pd bits
are set, the EMIF will go into Self Refresh.
Reset type: SYSRSn

29

PDWR

R/W

0h

Perform refreshes during Power Down. Writing a 1 to this bit will
cause the EMIF to exit the power down state and issue an AUTO
REFRESH command every time Refresh May level is set.
Reset type: SYSRSn

28-26

RESERVED

R

0h

Reserved

25-23

RESERVED

R

0h

Reserved

22-20

RESERVED

R

0h

Reserved

19

RESERVED

R

0h

Reserved

18-17

RESERVED

R

0h

Reserved

16

RESERVED

R

0h

Reserved

15

RESERVED

R

0h

Reserved

14

NM

R/W

0h

Narrow mode. Set to 1 when system bus width to memory bus width
is 2:1 for SDR SDRAM. Set to 0 when system bus width to memory
bus width is 1:1 for SDR SDRAM.
A write to this field will cause the EMIF to start the SDRAM
initialization sequence.
Reset type: SYSRSn

13
2640

RESERVED
External Memory Interface (EMIF)

R

0h

Reserved
SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

Table 25-38. SDRAM_CR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

12

RESERVED

R

0h

Reserved

CL

R/W

3h

The value of this field defines the CAS latency to be used when
accessing connected SDRAM devices. Only CAS latencies of 2 (cl =
2) and 3 (cl = 3) are supported.

11-9

A write to this field will cause the EMIF to start the SDRAM
initialization sequence.
Reset type: SYSRSn
8

BIT_11_9_LOCK

R=0/W=1

0h

Bits 11 to 9 can only be written if this bit is set to 1.
Reset type: SYSRSn

7

RESERVED

R

0h

Reserved

IBANK

R/W

2h

Defines number of banks inside connected SDRAM devices:

6-4

000: 1 bank SDRAM devices.
001: 2 bank SDRAM devices.
010: 3 bank SDRAM devices.
011: 4 bank SDRAM devices.
1xx: Reserved.
A write to this field will cause the EMIF to start the SDRAM
initialization sequence.
Reset type: SYSRSn
3

RESERVED

R

0h

Reserved

2-0

PAGESIGE

R/W

0h

Defines the internal page size of connected SDRAM devices:
000: 256-word pages requiring 8 column address bits.
001: 512-word pages requiring 9 column address bits.
010: 1024-word pages requiring 10 column address bits.
011: 2048-word pages requiring 11 column address bits.
1xx: Reserved.
A write to this field will cause the EMIF to start the SDRAM
initialization sequence.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2641

Registers

www.ti.com

25.5.2.4 SDRAM_RCR Register (Offset = 6h) [reset = 80h]
SDRAM_RCR is shown in Figure 25-26 and described in Table 25-39.
Return to Summary Table.
SDRAM Refresh Control Register
Figure 25-26. SDRAM_RCR Register
31

30

29

28

27

26

25

24

RESERVED
R-0h
23

22

21
RESERVED
R-0h

20

19

18

17
RESERVED
R-0h

16

15

14
RESERVED
R-0h

13

12

11

10
REFRESH_RATE
R/W-80h

9

8

7

6

5

4
3
REFRESH_RATE
R/W-80h

2

1

0

Table 25-39. SDRAM_RCR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-19

RESERVED

R

0h

Reserved

18-16

RESERVED

R

0h

Reserved

15-13

RESERVED

R

0h

Reserved

12-0

REFRESH_RATE

R/W

80h

Value in this field is used to define the rate at which connected
SDRAM devices will be refreshed, as follows:
SDRAM refresh rate = EMIF rate/refresh_rate
where EMIF rate=clk rate when full_rate=1, or EMIF rate=1/2 clk rate
when full_rate=0.
Writing a value < 0x0020 to this field will cause it to be loaded with
(2 * t_rfc) + 1 value from SDRAM Timing register.
Reset type: SYSRSn

2642

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2.5 ASYNC_CS2_CR Register (Offset = 8h) [reset = 3FFFFFFDh]
ASYNC_CS2_CR is shown in Figure 25-27 and described in Table 25-40.
Return to Summary Table.
Async 1 (EMxCS2n) Config Register
Figure 25-27. ASYNC_CS2_CR Register
31
SS

30
EW

R/W0h

R/W0h

15

14
R_SETUP
R/W-Fh

29

28
27
W_SETUP

26

25

24

R/W-Fh
13

12

11

23
22
W_STROBE

21

20

19

R/W-3Fh
10
9
R_STROBE
R/W-3Fh

8

7

6

18
W_HOLD

17

16
R_SE
TUP
R/WFh

1

0

R/W-7h
5
R_HOLD
R/W-7h

4

3
TA
R/W-3h

2

ASIZE
R/W-1h

Table 25-40. ASYNC_CS2_CR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

SS

R/W

0h

Select Strobe mode. Set to 1 if chip selects need to have write or
read strobe timing.
Reset type: SYSRSn

30

EW

R/W

0h

Extend Wait mode. Set to 1 if extended asynchronous cycles are
required based on EMxWAIT.
Reset type: SYSRSn

29-26

W_SETUP

R/W

Fh

Write Strobe Setup cycles. Number of EMxCLK cycles from EMxAy,
EMxBAy, EMxDQMy, and EMxCS2n being set to EMxWEn asserted,
minus one cycle. The reset value is 16 cycles.
Reset type: SYSRSn

25-20

W_STROBE

R/W

3Fh

Write Strobe Duration cycles. Number of EMxCLK cycles for which
EMxWEn is held active, minus one cycle. The reset value is 64
cycles. This field cannot be zero when ew = 1.
Reset type: SYSRSn

19-17

W_HOLD

R/W

7h

Write Strobe Hold cycles. Number of EMxCLK cycles for which
EMxAy, EMxBAy, EMxDQMy, and EMxCS2n are held after EMxWEn
has been deasserted, minus one cycle. The reset value is 8 cycles.
Reset type: SYSRSn

16-13

R_SETUP

R/W

Fh

Read Strobe Setup cycles. Number of EMxCLK cycles from EMxAy,
EMxBAy, EMxDQMy, and EMxCS2n being set to EMxOEn asserted,
minus one cycle. The reset value is 16 cycles.
Reset type: SYSRSn

12-7

R_STROBE

R/W

3Fh

Read Strobe Duration cycles. Number of EMxCLK cycles for which
EMxOEn is held active, minus one cycle. The reset value is 64
cycles. This field cannot be zero when ew = 1.
Reset type: SYSRSn

6-4

R_HOLD

R/W

7h

Read Strobe Hold cycles. Number of EMxCLK cycles for which
EMxAy, EMxBAy, EMxDQMy, and EMxCS2n are held after EMxOEn
has been deasserted, minus one cycle. The reset value is 8 cycles.
Reset type: SYSRSn

3-2

TA

R/W

3h

Turn Around cycles. Number of EMxCLK cycles between the end of
one asynchronous memory access and the start of another
asynchronous memory access, minus one cycle. This delay is not
incurred between a read followed by a read, or a write followed by a
write to the same chip select. The reset value is 4 cycles.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2643

Registers

www.ti.com

Table 25-40. ASYNC_CS2_CR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

ASIZE

R/W

1h

Asynchronous Memory Size. Defines the width of the asynchronous
device's data bus :
00: 8 Bit data bus.
01: 16 Bit data bus.
10: 32 Bit data bus.
11: Reserved.
Reset type: SYSRSn

2644

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2.6 ASYNC_CS3_CR Register (Offset = Ah) [reset = 3FFFFFFDh]
ASYNC_CS3_CR is shown in Figure 25-28 and described in Table 25-41.
Return to Summary Table.
Async 2 (EMxCS3n) Config Register
Figure 25-28. ASYNC_CS3_CR Register
31
SS

30
EW

R/W0h

R/W0h

15

14
R_SETUP
R/W-Fh

29

28
27
W_SETUP

26

25

24

R/W-Fh
13

12

11

23
22
W_STROBE

21

20

19

R/W-3Fh
10
9
R_STROBE
R/W-3Fh

8

7

6

18
W_HOLD

17

16
R_SE
TUP
R/WFh

1

0

R/W-7h
5
R_HOLD
R/W-7h

4

3
TA
R/W-3h

2

ASIZE
R/W-1h

Table 25-41. ASYNC_CS3_CR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

SS

R/W

0h

Select Strobe mode. Set to 1 if chip selects need to have write or
read strobe timing.
Reset type: SYSRSn

30

EW

R/W

0h

Extend Wait mode. Set to 1 if extended asynchronous cycles are
required based on EMxWAIT.
Reset type: SYSRSn

29-26

W_SETUP

R/W

Fh

Write Strobe Setup cycles. Number of EMxCLK cycles from EMxAy,
EMxBAy, EMxDQMy, and EMxCS3n being set to EMxWEn asserted,
minus one cycle. The reset value is 16 cycles.
Reset type: SYSRSn

25-20

W_STROBE

R/W

3Fh

Write Strobe Duration cycles. Number of EMxCLK cycles for which
EMxWEn is held active, minus one cycle. The reset value is 64
cycles. This field cannot be zero when ew = 1.
Reset type: SYSRSn

19-17

W_HOLD

R/W

7h

Write Strobe Hold cycles. Number of EMxCLK cycles for which
EMxAy, EMxBAy, EMxDQMy, and EMxCS3n are held after EMxWEn
has been deasserted, minus one cycle. The reset value is 8 cycles.
Reset type: SYSRSn

16-13

R_SETUP

R/W

Fh

Read Strobe Setup cycles. Number of EMxCLK cycles from EMxAy,
EMxBAy, EMxDQMy, and EMxCS3n being set to EMxOEn asserted,
minus one cycle. The reset value is 16 cycles.
Reset type: SYSRSn

12-7

R_STROBE

R/W

3Fh

Read Strobe Duration cycles. Number of EMxCLK cycles for which
EMxOEn is held active, minus one cycle. The reset value is 64
cycles. This field cannot be zero when ew = 1.
Reset type: SYSRSn

6-4

R_HOLD

R/W

7h

Read Strobe Hold cycles. Number of EMxCLK cycles for which
EMxAy, EMxBAy, EMxDQMy, and EMxCS3n are held after EMxOEn
has been deasserted, minus one cycle. The reset value is 8 cycles.
Reset type: SYSRSn

3-2

TA

R/W

3h

Turn Around cycles. Number of EMxCLK cycles between the end of
one asynchronous memory access and the start of another
asynchronous memory access, minus one cycle. This delay is not
incurred between a read followed by a read, or a write followed by a
write to the same chip select. The reset value is 4 cycles.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2645

Registers

www.ti.com

Table 25-41. ASYNC_CS3_CR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

ASIZE

R/W

1h

Asynchronous Memory Size. Defines the width of the asynchronous
device's data bus :
00: 8 Bit data bus.
01: 16 Bit data bus.
10: 32 Bit data bus.
11: Reserved.
Reset type: SYSRSn

2646

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2.7 ASYNC_CS4_CR Register (Offset = Ch) [reset = 3FFFFFFDh]
ASYNC_CS4_CR is shown in Figure 25-29 and described in Table 25-42.
Return to Summary Table.
Async 3 (EMxCS4n) Config Register
Figure 25-29. ASYNC_CS4_CR Register
31
SS

30
EW

R/W0h

R/W0h

15

14
R_SETUP
R/W-Fh

29

28
27
W_SETUP

26

25

24

R/W-Fh
13

12

11

23
22
W_STROBE

21

20

19

R/W-3Fh
10
9
R_STROBE
R/W-3Fh

8

7

6

18
W_HOLD

17

16
R_SE
TUP
R/WFh

1

0

R/W-7h
5
R_HOLD
R/W-7h

4

3
TA
R/W-3h

2

ASIZE
R/W-1h

Table 25-42. ASYNC_CS4_CR Register Field Descriptions
Bit

Field

Type

Reset

Description

31

SS

R/W

0h

Select Strobe mode. Set to 1 if chip selects need to have write or
read strobe timing.
Reset type: SYSRSn

30

EW

R/W

0h

Extend Wait mode. Set to 1 if extended asynchronous cycles are
required based on EMxWAIT.
Reset type: SYSRSn

29-26

W_SETUP

R/W

Fh

Write Strobe Setup cycles. Number of EMxCLK cycles from EMxAy,
EMxBAy, EMxDQMy, and EMxCS4n being set to EMxWEn asserted,
minus one cycle. The reset value is 16 cycles.
Reset type: SYSRSn

25-20

W_STROBE

R/W

3Fh

Write Strobe Duration cycles. Number of EMxCLK cycles for which
EMxWEn is held active, minus one cycle. The reset value is 64
cycles. This field cannot be zero when ew = 1.
Reset type: SYSRSn

19-17

W_HOLD

R/W

7h

Write Strobe Hold cycles. Number of EMxCLK cycles for which
EMxAy, EMxBAy, EMxDQMy, and EMxCS4n are held after EMxWEn
has been deasserted, minus one cycle. The reset value is 8 cycles.
Reset type: SYSRSn

16-13

R_SETUP

R/W

Fh

Read Strobe Setup cycles. Number of EMxCLK cycles from EMxAy,
EMxBAy, EMxDQMy, and EMxCS4n being set to EMxOEn asserted,
minus one cycle. The reset value is 16 cycles.
Reset type: SYSRSn

12-7

R_STROBE

R/W

3Fh

Read Strobe Duration cycles. Number of EMxCLK cycles for which
EMxOEn is held active, minus one cycle. The reset value is 64
cycles. This field cannot be zero when ew = 1.
Reset type: SYSRSn

6-4

R_HOLD

R/W

7h

Read Strobe Hold cycles. Number of EMxCLK cycles for which
EMxAy, EMxBAy, EMxDQMy, and EMxCS4n are held after EMxOEn
has been deasserted, minus one cycle. The reset value is 8 cycles.
Reset type: SYSRSn

3-2

TA

R/W

3h

Turn Around cycles. Number of EMxCLK cycles between the end of
one asynchronous memory access and the start of another
asynchronous memory access, minus one cycle. This delay is not
incurred between a read followed by a read, or a write followed by a
write to the same chip select. The reset value is 4 cycles.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2647

Registers

www.ti.com

Table 25-42. ASYNC_CS4_CR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

1-0

ASIZE

R/W

1h

Asynchronous Memory Size. Defines the width of the asynchronous
device's data bus :
00: 8 Bit data bus.
01: 16 Bit data bus.
10: 32 Bit data bus.
11: Reserved.
Reset type: SYSRSn

2648

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2.8 SDRAM_TR Register (Offset = 10h) [reset = 19214610h]
SDRAM_TR is shown in Figure 25-30 and described in Table 25-43.
Return to Summary Table.
SDRAM Timing Register
Figure 25-30. SDRAM_TR Register
31

30

29
T_RFC
R/W-3h

28

27

26

25
T_RP
R/W-1h

24

23
RESERVED
R-0h

22

21
T_RCD
R/W-2h

20

19
RESERVED
R-0h

18

17
T_WR
R/W-1h

16

15

14

13

12

11

10

9

8

1

0

T_RAS
R/W-4h
7
RESERVED
R-0h

6

T_RC
R/W-6h
5
T_RRD
R/W-1h

4

3

2
RESERVED
R-0h

Table 25-43. SDRAM_TR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-27

T_RFC

R/W

3h

Minimum number of EMxCLK cycles from Refresh or Load Mode to
Refresh or Activate, minus one.
Reset type: SYSRSn

26-24

T_RP

R/W

1h

Minimum number of EMxCLK cycles from Precharge to Activate or
Refresh, minus one.
Reset type: SYSRSn

RESERVED

R

0h

Reserved

T_RCD

R/W

2h

Minimum number of EMxCLK cycles from Activate to Read or Write,
minus one.
Reset type: SYSRSn

RESERVED

R

0h

Reserved

18-16

T_WR

R/W

1h

For SDR, this is equal to minimum number of EMxCLK cycles from
last Write transfer to Precharge, minus one.
Reset type: SYSRSn

15-12

T_RAS

R/W

4h

Minimum number of EMxCLK cycles from Activate to Precharge,
minus one. t_ras >= t_rcd.
Reset type: SYSRSn

11-8

T_RC

R/W

6h

Minimum number of EMxCLK cycles from Activate to Activate minus
one.
Reset type: SYSRSn

RESERVED

R

0h

Reserved

6-4

T_RRD

R/W

1h

Minimum number of EMxCLK cycles from Activate to Activate for a
different bank, minus one.
Reset type: SYSRSn

3-0

RESERVED

R

0h

Reserved

23
22-20

19

7

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2649

Registers

www.ti.com

25.5.2.9 TOTAL_SDRAM_AR Register (Offset = 18h) [reset = 0h]
TOTAL_SDRAM_AR is shown in Figure 25-31 and described in Table 25-44.
Return to Summary Table.
Total SDRAM Accesses Register
Figure 25-31. TOTAL_SDRAM_AR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TOTAL_SDRAM_AR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 25-44. TOTAL_SDRAM_AR Register Field Descriptions
Bit
31-0

2650

Field

Type

Reset

Description

TOTAL_SDRAM_AR

R

0h

Indicates the total number of accesses to SDRAM from a master
(CPUx/CPUX.DMA). This counter is incremented by two for a single
access crossing page boundaries.
Reset type: SYSRSn

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2.10 TOTAL_SDRAM_ACTR Register (Offset = 1Ah) [reset = 0h]
TOTAL_SDRAM_ACTR is shown in Figure 25-32 and described in Table 25-45.
Return to Summary Table.
Total SDRAM Activate Register
Figure 25-32. TOTAL_SDRAM_ACTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TOTAL_SDRAM_ACTR
R-0h

9

8

7

6

5

4

3

2

1

0

Table 25-45. TOTAL_SDRAM_ACTR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

TOTAL_SDRAM_ACTR

R

0h

Indicates the total number of SDRAM accesses which require an
activate command.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2651

Registers

www.ti.com

25.5.2.11 SDR_EXT_TMNG Register (Offset = 1Eh) [reset = 7h]
SDR_EXT_TMNG is shown in Figure 25-33 and described in Table 25-46.
Return to Summary Table.
SDRAM SR/PD Exit Timing Register
Figure 25-33. SDR_EXT_TMNG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
RESERVED
RESERVED
R-0h
R-0h

7

6

5

4

3

2 1
T_XS
R/W-7h

0

Table 25-46. SDR_EXT_TMNG Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-5

RESERVED

R

0h

Reserved

4-0

T_XS

R/W

7h

This is equal to minimum number of EMxCLK cycles from Self
Refresh exit to any command, minus one. For SDR SDRAM, this
count should satisfy tXSR.
Reset type: SYSRSn

2652

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2.12 INT_RAW Register (Offset = 20h) [reset = 0h]
INT_RAW is shown in Figure 25-34 and described in Table 25-47.
Return to Summary Table.
Interrupt Raw Register
Figure 25-34. INT_RAW Register
31

30

29

28

27

26

25

15

14

13

12

11
10
RESERVED
R-0h

9

24
23
RESERVED
R-0h
8

7

22

21

20

19

18

6

5

4

3
WR
R/W=1-0h

2

17

16

1
0
LT
AT
R/W=1 R/W=1
-0h
-0h

Table 25-47. INT_RAW Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

5-2

WR

R/W=1

0h

Wait Rise. Set to 1 by hardware to indicate rising edge on the
corresponding EMxWAIT has been detected. The WPx bits in the
Async Wait Cycle Config register has no effect on these bits. Writing
a 1 will clear these bits as well as the wr_masked bits in the Interrupt
Masked register. Writing a 0 has no effect.
Reset type: SYSRSn

1

LT

R/W=1

0h

Line Trap. Set to 1 by hardware to indicate illegal memory access
type or invalid cache line size. Writing a 1 will clear this bit as well as
the lt_masked bit in the Interrupt Masked register. Writing a 0 has no
effect.
Reset type: SYSRSn

0

AT

R/W=1

0h

Asynchronous Timeout. Set to 1 by hardware to indicate that during
an extended asynchronous memory access cycle, the EMxWAIT
signal did not go inactive within the number of cycles defined by the
max_ext_wait field in Async Wait Cycle Config register. Writing a 1
will clear this bit as well as the at_masked bit in the Interrupt Masked
register. Writing a 0 has no effect.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2653

Registers

www.ti.com

25.5.2.13 INT_MSK Register (Offset = 22h) [reset = 0h]
INT_MSK is shown in Figure 25-35 and described in Table 25-48.
Return to Summary Table.
Interrupt Masked Register
Figure 25-35. INT_MSK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1
LT_MASKED
R/W=1-0h

0
AT_MASKED
R/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

RESERVED
R-0h

WR_MASKED
R/W=1-0h

Table 25-48. INT_MSK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

5-2

WR_MASKED

R/W=1

0h

Masked Wait Rise. Set to 1 by hardware to indicate rising edge on
the corresponding EMxWAIT has been detected, only if the
wr_mask_set bit in the Interrupt Mask Set register is set to 1. The
WPx bits in the Async Wait Cycle Config register has no effect on
these bits. Writing a 1 will clear these bits as well as the wr bits in
the Interrupt Raw register. Writing a 0 has no effect.
Reset type: SYSRSn

1

LT_MASKED

R/W=1

0h

Masked Line Trap. Set to 1 by hardware to indicate illegal memory
access type or invalid cache line size, only if the lt_mask_set bit in
the Interrupt Mask Set register is set to 1. Writing a 1 will clear this
bit as well as the lt bit in the Interrupt Raw register. Writing a 0 has
no effect.
Reset type: SYSRSn

0

AT_MASKED

R/W=1

0h

Masked Asynchronous Timeout. Set to 1 by hardware to indicate
that during an extended asynchronous memory access cycle, the
EMxWAIT signal did not go inactive within the number of cycles
defined by the max_ext_wait field in Async Wait Cycle Config
register, only if the at_mask_set bit in the Interrupt Mask Set register
is set to 1. Writing a 1 will clear this bit as well as the at bit in the
Interrupt Raw register. Writing a 0 has no effect.
Reset type: SYSRSn

2654

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.2.14 INT_MSK_SET Register (Offset = 24h) [reset = 0h]
INT_MSK_SET is shown in Figure 25-36 and described in Table 25-49.
Return to Summary Table.
Interrupt Mask Set Register
Figure 25-36. INT_MSK_SET Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

4
3
WR_MASK_SET

2

RESERVED

1
LT_MASK_SET

R-0h

R/W=1-0h

0
AT_MASK_SE
T
R/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

R/W=1-0h

Table 25-49. INT_MSK_SET Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

5-2

WR_MASK_SET

R/W=1

0h

Mask set for wr_masked bits in the Interrupt Masked Register.
Writing a 1 will enable the interrupts, and set these bits as well as
the wr_mask_clr bits in the Interrupt Mask Clear register. Writing a 0
has no effect.
Reset type: SYSRSn

1

LT_MASK_SET

R/W=1

0h

Mask set for lt_masked bit in the Interrupt Masked Register. Writing
a 1 will enable the interrupt, and set this bit as well as the
lt_mask_clr bit in the Interrupt Mask Clear register. Writing a 0 has
no effect.
Reset type: SYSRSn

0

AT_MASK_SET

R/W=1

0h

Mask set for at_masked bit in the Interrupt Masked Register. Writing
a 1 will enable the interrupt, and set this bit as well as the
at_mask_clr bit in the Interrupt Mask Clear register. Writing a 0 has
no effect.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2655

Registers

www.ti.com

25.5.2.15 INT_MSK_CLR Register (Offset = 26h) [reset = 0h]
INT_MSK_CLR is shown in Figure 25-37 and described in Table 25-50.
Return to Summary Table.
Interrupt Mask Clear Register
Figure 25-37. INT_MSK_CLR Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

4
3
WR_MASK_CLR

2

RESERVED

1
LT_MASK_CLR

R-0h

R/W=1-0h

0
AT_MASK_CL
R
R/W=1-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

R/W=1-0h

Table 25-50. INT_MSK_CLR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-6

RESERVED

R

0h

Reserved

5-2

WR_MASK_CLR

R/W=1

0h

Mask clear for wr_masked bits in the Interrupt Masked Register.
Writing a 1 will disable the interrupts, and clear these bits as well as
the wr_mask_set bits in the Interrupt Mask Set register. Writing a 0
has no effect.
Reset type: SYSRSn

1

LT_MASK_CLR

R/W=1

0h

Mask clear for lt_masked bit in the Interrupt Masked Register.
Writing a 1 will disable the interrupt, and clear this bit as well as the
lt_mask_set bit in the Interrupt Mask Set register. Writing a 0 has no
effect.
Reset type: SYSRSn

0

AT_MASK_CLR

R/W=1

0h

Mask clear for at_masked bit in the Interrupt Masked Register.
Writing a 1 will disable the interrupt, and clear this bit as well as the
at_mask_set bit in the Interrupt Mask Set register. Writing a 0 has no
effect.
Reset type: SYSRSn

2656

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.3 EMIF1_CONFIG_REGS Registers
Table 25-51 lists the memory-mapped registers for the EMIF1_CONFIG_REGS. All register offset
addresses not listed in Table 25-51 should be considered as reserved locations and the register contents
should not be modified.
Table 25-51. EMIF1_CONFIG_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

EMIF1LOCK

EMIF1 Config Lock Register

EALLOW

Go

2h

EMIF1COMMIT

EMIF1 Config Lock Commit Register

EALLOW

Go

4h

EMIF1MSEL

EMIF1 Master Sel Register

EALLOW

Go

8h

EMIF1ACCPROT0

EMIF1 Config Register 0

EALLOW

Go

Complex bit access types are encoded to fit into small table cells. Table 25-52 shows the codes that are
used for access types in this section.
Table 25-52. EMIF1_CONFIG_REGS Access Type
Codes
Access Type

Code

Description

R

R

Read

R=0

R

Read

W

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type

Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables
i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2657

Registers

www.ti.com

25.5.3.1 EMIF1LOCK Register (Offset = 0h) [reset = 0h]
EMIF1LOCK is shown in Figure 25-38 and described in Table 25-53.
Return to Summary Table.
EMIF1 Config Lock Register
Figure 25-38. EMIF1LOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
LOCK_EMIF1
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 25-53. EMIF1LOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

LOCK_EMIF1

R/W

0h

Locks the write to access protection and master select fields for
EMIF1:

0

0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn

2658

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.3.2 EMIF1COMMIT Register (Offset = 2h) [reset = 0h]
EMIF1COMMIT is shown in Figure 25-39 and described in Table 25-54.
Return to Summary Table.
EMIF1 Config Lock Commit Register
Figure 25-39. EMIF1COMMIT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
COMMIT_EMIF
1
R/WSOnce-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 25-54. EMIF1COMMIT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

COMMIT_EMIF1

R/WSOnce

0h

Permanently Locks the write to access protection and master select
fields for EMIF1:

0

0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in EMIF1LOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2659

Registers

www.ti.com

25.5.3.3 EMIF1MSEL Register (Offset = 4h) [reset = 0h]
EMIF1MSEL is shown in Figure 25-40 and described in Table 25-55.
Return to Summary Table.
EMIF1 Master Sel Register
Figure 25-40. EMIF1MSEL Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

2

1

KEY
R=0/W-0h
23

22

21

20
KEY
R=0/W-0h

15

14

13

12
KEY
R=0/W-0h

7

6

5

4

3

KEY
R=0/W-0h

RESERVED
R-0h

0
MSEL_EMIF1
R/W-0h

Table 25-55. EMIF1MSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-4

KEY

R=0/W

0h

Writing the value 0x93A5CE7 will allow the writing of the
EMIF1Mselect bits, else writes are ignored. Reads will return 0.
Reset type: CPU1.SYSRSn

3-2

RESERVED

R

0h

Reserved

1-0

MSEL_EMIF1

R/W

0h

Master Select for EMIF1:
00: CPU1 is master but not grabbed. CPU2 can grab the master
ownership by changing this value to "10".
01: CPU1 is master.
10: CPU2 is master.
11: CPU1 is master but not grabbed. CPU2 can grab the master
ownership by changing this value to "10".
Reset type: CPU1.SYSRSn

2660

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.3.4 EMIF1ACCPROT0 Register (Offset = 8h) [reset = 0h]
EMIF1ACCPROT0 is shown in Figure 25-41 and described in Table 25-56.
Return to Summary Table.
EMIF1 Config Register 0
Figure 25-41. EMIF1ACCPROT0 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5
RESERVED

4

3

R-0h

2
1
0
DMAWRPROT CPUWRPROT_ FETCHPROT_
_EMIF1
EMIF1
EMIF1
R/W-0h
R/W-0h
R/W-0h

Table 25-56. EMIF1ACCPROT0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-3

RESERVED

R

0h

Reserved

DMAWRPROT_EMIF1

R/W

0h

DMA WR Protection For EMIF1:

2

0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
1

CPUWRPROT_EMIF1

R/W

0h

CPU WR Protection For EMIF1:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn

0

FETCHPROT_EMIF1

R/W

0h

Fetch Protection For EMIF1:
0: CPU Fetches are allowed.
1: CPU Fetches are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2661

Registers

www.ti.com

25.5.4 EMIF2_CONFIG_REGS Registers
Table 25-57 lists the memory-mapped registers for the EMIF2_CONFIG_REGS. All register offset
addresses not listed in Table 25-57 should be considered as reserved locations and the register contents
should not be modified.
Table 25-57. EMIF2_CONFIG_REGS Registers
Offset

Acronym

Register Name

Write Protection

Section

0h

EMIF2LOCK

EMIF2 Config Lock Register

2h

EMIF2COMMIT

EMIF2 Config Lock Commit Register

EALLOW

Go

8h

EMIF2ACCPROT0

EMIF2 Config Register 0

EALLOW

Go

Go

Complex bit access types are encoded to fit into small table cells. Table 25-58 shows the codes that are
used for access types in this section.
Table 25-58. EMIF2_CONFIG_REGS Access Type
Codes
Access Type

Code

Description

R

Read

W

W

Write

WSOnce

SOnce
W

Set once
Write

Read Type
R
Write Type

Reset or Default Value
-n

Value after reset or the default
value

Register Array Variables

2662

i,j,k,l,m,n

When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.

y

When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.4.1 EMIF2LOCK Register (Offset = 0h) [reset = 0h]
EMIF2LOCK is shown in Figure 25-42 and described in Table 25-59.
Return to Summary Table.
EMIF2 Config Lock Register
Figure 25-42. EMIF2LOCK Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
LOCK_EMIF2
R/W-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 25-59. EMIF2LOCK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

LOCK_EMIF2

R/W

0h

Locks the write to access protection fields for EMIF2:

0

0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: CPU1.SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2663

Registers

www.ti.com

25.5.4.2 EMIF2COMMIT Register (Offset = 2h) [reset = 0h]
EMIF2COMMIT is shown in Figure 25-43 and described in Table 25-60.
Return to Summary Table.
EMIF2 Config Lock Commit Register
Figure 25-43. EMIF2COMMIT Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

1

0
COMMIT_EMIF
2
R/WSOnce-0h

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4
RESERVED
R-0h

Table 25-60. EMIF2COMMIT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-1

RESERVED

R

0h

Reserved

COMMIT_EMIF2

R/WSOnce

0h

Permanently Locks the write to access protection fields for EMIF2:

0

0: Write to ACCPROT fields are allowed based on value of lock field
in EMIF2LOCK register.
1: Write to ACCPROT fields are permanently blocked.
Reset type: CPU1.SYSRSn

2664

External Memory Interface (EMIF)

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Registers

www.ti.com

25.5.4.3 EMIF2ACCPROT0 Register (Offset = 8h) [reset = 0h]
EMIF2ACCPROT0 is shown in Figure 25-44 and described in Table 25-61.
Return to Summary Table.
EMIF2 Config Register 0
Figure 25-44. EMIF2ACCPROT0 Register
31

30

29

28

27

26

25

24

19

18

17

16

11

10

9

8

3

2

RESERVED
R-0h
23

22

21

20
RESERVED
R-0h

15

14

13

12
RESERVED
R-0h

7

6

5

4

1
0
CPUWRPROT_ FETCHPROT_
EMIF2
EMIF2
R/W-0h
R/W-0h

RESERVED
R-0h

Table 25-61. EMIF2ACCPROT0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R

0h

Reserved

15-2

RESERVED

R

0h

Reserved

CPUWRPROT_EMIF2

R/W

0h

CPU WR Protection For EMIF2:

1

0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0

FETCHPROT_EMIF2

R/W

0h

Fetch Protection For EMIF2
0: CPU Fetches are allowed.
1: CPU Fetches are blocked.
Reset type: SYSRSn

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

External Memory Interface (EMIF)

2665

Revision History

www.ti.com

Revision History
Changes from January 1, 2017 to September 15, 2017 .................................................................................................. Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Chapter 1: C28x Processor: No changes in this revision. ........................................................................ 82
Chapter 2: System Control ............................................................................................................ 85
Table 2-4: Changed description for PIE Group 9 Vectors INT9.5 - INT9.8. ..................................................... 97
Table 2-10: Removed 'unless unlocked' from the end of the sentence beginning with "Master select and access
protection".. ............................................................................................................................. 126
Section 2.12.2: Added the last bullet indicating "Users much install updates for Flash Plugin and UniFlash tools....";
replaced reference guide links. ....................................................................................................... 133
Section 2.12.5: Replaced links to references. ...................................................................................... 134
Section 2.13.1.6: Reworded the last sentence in the first paragraph of this section. ......................................... 151
Section 2.14: Added this new section. .............................................................................................. 157
Chapter 3: ROM code and Peripheral Booting .................................................................................. 582
Figure 3-2: Figure has been revised. ................................................................................................ 588
Figure 3-3: Figure has been revised. ................................................................................................ 589
Figure 3-6: Added Enable Watchdog to the figure. ................................................................................ 592
Figure 3-7: Figure has been revised. ................................................................................................ 593
Table 3-24: Added the note following the table..................................................................................... 609
Section 3.9.10.2: Added this table. .................................................................................................. 620
Chapter 4: Direct Memory Access (DMA) ........................................................................................ 623
Section 4.4 : Reworded the sentence beginning "In the case of a bulk DMA transfer.." ..................................... 633
Table 4-8: Added the note to bit 10, ONESHOT description. .................................................................... 647
Chapter 5: Control Law Accelerator (CLA) ....................................................................................... 659
Section 5.4.2: Changed references of PCLKCR3 to PCLKCR0.................................................................. 668
Table 5-9: The text preceding the table beginning with "for instructions that use MRx" and the operand encoding table
have been added. ...................................................................................................................... 680
Chapter 6: Inter-Processor Communication (IPC): No changes in this revision. ........................................... 833
Chapter 7: General-Purpose Input/Output (GPIO) .............................................................................. 905
Chapter 8 Crossbar (X-BAR)....................................................................................................... 1137
Table 8-2: Added the note to ADCSOCAO and ADCSOCBO. ................................................................. 1141
Table 8-3: Added the note to ADCSOCAO and ADCSOCBO. ................................................................. 1143
Chapter 9: Analog Subsystem .................................................................................................... 1372
Section 9.1.1: Revised the features list. ........................................................................................... 1373
Chapter 10: Analog-to-Digital Converter (ADC)................................................................................ 1387
Section 10.1.3.2: Revised the text in this section for better clarity. ............................................................ 1390
Section 10.1.3.4: Revised this section. ............................................................................................ 1390
Table 10-3: Changed when ADCINyP - ADCINyn ≥ VREFHI to when ADCINyP - ADCINyN ≤ -VREFHI. ............... 1392
Section 10.1.5: Removed reference to SOCC and SOCD. ..................................................................... 1396
Figure 10-9: Revised the block diagram. .......................................................................................... 1404
Section 10.1.10: Added this new section. ......................................................................................... 1406
Chapter 11: Buffered Digital to Analog Converter (DAC) - No changes in this revision ................................. 1581
Chapter 12: Comparator Subsystem (CMPSS) ................................................................................ 1592
Section 12.5: Inserted step 4 in the bulleted list. ................................................................................. 1597
Chapter 13: Sigma Delta Filter Module (SDFM): No changes in this revision. ............................................. 1624
Chapter 14: Enhanced Pulse Width Modulator (ePWM) ..................................................................... 1674
Section 14.1: Added Type0 to Type1 Enhancements section. ................................................................. 1676
Figure 14-54: Figure has been updated. .......................................................................................... 1742
Section 14.11.4.3Included: this new section. ..................................................................................... 1743
Figure 14-57: Changed the output signals for CMPSS1 and CMPSS8 from CTRIPOUTH to CTRIPH and CTRIPOUTL to
CTRIPL. ................................................................................................................................ 1745
Figure 14-72: Removed the last BLANKWDW section. ......................................................................... 1760
Chapter 15: High-Resolution Pulse Width Modulator (HRPWM): No changes in this revision. ........................ 2001

2666

Revision History

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Revision History

www.ti.com

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Enhanced Capture (eCAP)Chapter 16: .......................................................................................... 2028
Section 16.3: Changed instances of OUTPUTXBARn to OUTPUTXBARx. .................................................. 2029
Figure 16-11: Included the new figure.............................................................................................. 2039
Chapter 17: : Enhanced QEP (eQEP) ............................................................................................ 2068
Section 17.5.1.1: Revised the final sentence int his section. ................................................................... 2078
Section 17.5.1.2: Revised the second paragraph, beginning "The first index marker..." .................................... 2078
Section 17.5.1.3: Revised the second paragraph beginning "The first index marker..." .................................... 2079
Section 17.8: Modifed the text of the first paragraph. ............................................................................ 2087
Chapter 18 Serial Peripheral Interface (SPI):: No changes in this revision. ................................................ 2124
Chapter 19: Serial Communications Interface (SCI) ......................................................................... 2164
Section 19.12: Revised the text in the second paragraph. ...................................................................... 2174
Table 19-3: Revised the table. ...................................................................................................... 2174
Chapter 20: Inter-Integrated Circuit Module (I2C): No changes in this revision. .......................................... 2199
Chapter 21: Multichannel Buffered Serial Port (McBSP) ..................................................................... 2239
Chapter 22: Controller Area Network (CAN) : Removed the Global Power-down Mode section. ....................... 2351
Section 22.3: Added this new section. ............................................................................................. 2354
Section 22.4.1: Deleted the note. ................................................................................................... 2355
Section 22.4.2.2: Revised the Note................................................................................................. 2357
Section 22.4.3.2: Changed 'setting bit LBack in the TTST register" to "setting bit LBack in the CAN_TEST register.". 2357
Section 22.6.3: Changed the last sentence from 'this register' to "the CAN_CTL register." ................................ 2360
Section 22.6.4: Created this new section. ......................................................................................... 2361
Section 22.8: Deleted "clear of DMAActive..." from the last bullet) ............................................................ 2361
Section 22.13: Deleted the note at the end of the section....................................................................... 2376
Table 22-5: In the IntPnd Description, deleted the incorrect second line indicating the message object is the source of an
interrupt. Also, added a note in the descriptions for Msd[28:0]. ................................................................ 2378
Chapter 23: Universal Serial Bus (USB) Controller ........................................................................... 2445
Section 23.3.1: Deleted the bullet beginning "Isochronous endpoints..." ...................................................... 2448
Section 23.3.2: Deleted the bullet beginning "Isochronous endpoints..." ...................................................... 2452
Table 23-6: Bit 7 is now reserved; ................................................................................................. 2474
Section 23.6.27: Removed 'isochronous ' from the second paragraph. ....................................................... 2506
Table 23-43: Deleted the note in the bit 4, Stall description. ................................................................... 2513
Table 23-44: Revised the description for bit 3, FDT, value 1. .................................................................. 2515
Table 23-45: Revised bit 6 to Reserved; revised text for the FDT bit. ......................................................... 2516
Section 23.6.35: Deleted 'and isochronous' from the second paragraph. ..................................................... 2517
Table 23-47: Revised text in bits 3 and 2. ......................................................................................... 2518
Table 23-48: Changed bits 2 and 3 to Reserved. ................................................................................ 2519
Table 23-49: Changed bit 4 to Reserved. ......................................................................................... 2520
Table 23-50: Changed bit 6 to Reserved; Removed paragraph re "isochronous" from bit 4 description. ................ 2521
Table 23-52: Removed 'isochronous' from bits 5-4 description. ................................................................ 2523
Section 23.6.40: Removed 'isochronous' from this entire section. ............................................................. 2524
Table 23-55: Replaced Isochronous in bits 5-4 with Reserved. ................................................................ 2525
Chapter 24: Universal Parallel Port (uPP) - No changes for this revision. .................................................. 2542
Chapter 25: External Memory Interface (EMIF) ............................................................................... 2593
Section 25.3: Replaced 'system-related issues' with 'system-related configurations.' ....................................... 2596
Section 25.3.5.11: Changed EM1DQM[1:0] to EM1DQM[3:0]. ................................................................ 2610
Table 25-19: Deleted "while in NAND Flash Mode" .............................................................................. 2614

SPRUHM8G – December 2013 – Revised September 2017
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated

Revision History

2667

IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications
(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that
might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you
will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any
testing other than that specifically described in the published documentation for a particular TI Resource.
You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO
ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,
COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR
ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
Linearized                      : No
Page Mode                       : UseOutlines
Page Count                      : 2668
Creator                         : TopLeaf 8.0.022
Producer                        : iText 2.1.7 by 1T3XT
Title                           : TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual (Rev. G)
Keywords                        : SPRUHM8, SPRUHM8G
Subject                         : Technical Reference
Modify Date                     : 2017:10:05 13:32:31-05:00
Author                          : Texas Instruments, Incorporated [SPRUHM8,G.]
Create Date                     : 2017:10:05 13:32:31-05:00

EXIF Metadata provided by EXIF.tools