F9440_Microflame_Data_Sheet_Dec78 F9440 Microflame Data Sheet Dec78

User Manual: F9440_Microflame_Data_Sheet_Dec78

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PRELIMINARY DATA SHEET • DECEMBER 1978

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GENERAL DESCRIPTION - The 9440 MICROFLAME single-chip 16-bit bipolar processor, packaged in a 40-pin DIP, is implemented using Fairchild 's Isoplanar Integrated
Injection Logic technology (13L™). Though structurally different from the CPUs of the
Data General NOVA line of minicomputers, the 9440 offers comparable performance
and executes the same instruction set.

CONNECTION DIAGRAM
DIP (TOP VIEW)

~
C3

()

CLK OUT

DCH REO

XTl

00
34

INT REO

MR
SYN

INTON

MBsY

GND

Vee

RUN

GND

IINJ

CARRY

IBo

iii l3

ii,

i8 2

iB '2
iBn

iii3

18 10

iB4

iii,

IB5

rn8

iii,

iB Is

iii14

SYSTEM DIAGRAM
INFORMATION BUS

VINONlY

IN
OPERATOR CONSOLE

AND OUT

._-,

1110 ill"

IH ! - IB IS

IBo -IB I~

il,

is -

TB · ~ A o- A 6

32K

.r---

Ao- A 6

SYN

MAIN
MEMORY
ARRAY
93481 / 93483

9441
MEMORY
CONTROL

,):J

CSo

CS ,
CS,

SYN

11I

AEO ' oo ~

UNIT

".,.

16-8IT
MICROPROCESSOR C t

,. FLAME

CONSOLE

XTL

RUN

ClKOUT
M8SY

iNf
00
CP
SYN

CARRY

INT
ON

0 , Imllmlllll

I/'

DCH

LOGIC

RUN

CARRY

i'B: -iih

irEi'a" . ~ 'irs'

·~t trB ssBJ

944.

•

00 [:1£
0 ;IE ' ;[1 ' 3[i
8888888888888 8 a
0

';-;

9442
INPUT/ OUTPUT
CONTROL
UNIT

---

t!t
:;:::;:- iBo-iB15

'----

BUS
TRANSCEIVER

C1978 Fairchild Camera and Instrument Corporation

Printed in U.S.A.

•

~
SPECIAL FUNCTIONS
UNIT

•

54·PORT I/ O

~us

.. .

~
INPUT/ OUTPUT
INTERFACE &
CONTROL

I/O
DEVICE

004-11-0010-118 15M

464 ELLIS STREET, MOUNTAIN VIEW, CALIFORNIA, 94042 (415) 962-5011/TWX 910-379-6435

• EIGHT 16-BIT ON-CHIP REGISTERS
• 64 DIRECTLY ADQRESSABLE I/O DEVICES, EACH WITH THREE
BIDIRECTIONAL I/O PORTS
• PRIORITY INTERRUPT HANDLING WITH UP TO 16 PRIORITY LEVELS
• FAST DIRECT MEMORY ACCESS AT MEMORY SPEEDS
• 16-BIT 3-STATE BIDIRECTIONAL INFORMATION BUS
• FLEXIBLE OPERATOR CONSOLE CONTROL USING ONLY FOUR LINES
• POWERFUL, WIDELY USED INSTRUCTION SET
• MULTIFUNCTION INSTRUCTIONS FOR EFFICIENT MEMORY USAGE
• 50 BASIC INSTRUCTIONS FOR A TOTAL OF 2192 DIFFERENT INSTRUCTIONS
• 8 ADDRESSING MODES
• 64K BYTES DIRECT-ADDRESSING RANGE EXTENDED TO 16M BYTES VIA
MEMORY MAPPING
• 5 V POWER SUPPLY
• TTL INPUTS AND OUTPUTS
• TYPICAL 1 W POWER DISSIPATION
• FULL MILITARY TEMPERATURE RANGE VERSION
• SINGLE-CLOCK STATIC ON-CHIP OSCILLATOR, DC TO 12 MHz CLOCK RATE
• COMPATIBLE HIGH SPEED MEMORI.ES AVAILABLE (93481/93483)
• TOTAL SOFTWARE WITH FIRE'· SOFTWARE PACKAGE
• USEABLE IN STAND-ALONE AS WELL AS DISTRIBUTED PROCESSING APPLICATIONS

ItIA~~NOUT

FAIRCHIL..C

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o
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m
Ul
Ul

FAIRCHILD • 9440

PROGRAM
COUNTER

1'-

~.I"
<

INFOR~TION
BUS

-...
/

/'r..

SCRATCH
REGISTER

BUS
REGISTER

~tv7'
IBo -1815

~
~

FOUR
16-BIT
ACCUMULATORS

=>
"-

INST
REGISTER

'\
./
I'

DATA PATH

DST
MUX

ALL!

SRC
MUX

t--

~~~~~-~---)---------~n.~---

If>

CONTROL
CONSOLE
LATCH

STATE
SEQUENCE

I >

MEMORY CONTROL

MICROPROGRAM
PLA

CONTROL
j..

110 CONTROL

NEXT SEQUENCE
STATE

Fig. 1 9440 MICROFLAME CPU Block Diagram

9440 ARCHITECTURE (Figure 1)
The 9440 single-chip 16-bit bipolar processor, packaged in a 40-pin DIP, is implemented using
Fairchild's Isoplanar Integrated Injection Logic technology (13L™l. Though structurally different
from the CPUs of the NOVA line of minicomputers, the 9440, as a microprocessor, offers
comparable performance and executes the same instruction set.
The processor is a stored program machine using homogeneous external memory, i.e., instructions and data are stored in the same memory. Although the processor handles 16 bits of
information, only 15 bits are used for addressing the memory. Thus, the intrinsic memory capacity
of a 9440 system is 32,768 16-bit words.
The 9440 consists of a collection of data paths and all the necessary control circuitry. It governs
peripheral liD equipment, performs the arithmetic, logic and data handling operations and
sequences the program.
Data Paths - The qata path portion includes a bank of four 16-bit general-purpose registers
(accumulators ACO-AC3), two multiplexers, an ALU, and four 16-bit special registers-scratch
register, bus register, instruction register and program counter. Internal data flows between the
various registers via 4-bit-wide data paths.

FAIRCHILD. 9440
The accumulators store the operands required for all arithmetic/logic operations. Accumulators
AC2 and AC3 are also used as index registers and AC3 serves as the subroutine linkage register as
well. All input-output data transfers take place through the accumulators; however, a word in a
memory location may be incremented or decremented without accumulator participation. Data can
be moved in either direction between the memory and any accumulator.
The destination and source multiplexers are connected to all four accumulators and select source
and destination registers for each operation. The multiplexers also receive other inputs from the
bus and instruction registers, which permit the ALU to be used for effective-address calculations
and other purposes.
The ALU is four bits wide and operates on two 16-bit words in four consecutive steps, taking one 4bit nibble per step. By adding the associated Carry bit to the 16-bit result from the ALU, a 17-bit
word is formed which may be rotated either left or right.
Data from the ALU to the destination accumulator is held in the scratch register for one cycle. The
bus register is connected to the bidirectional information bus and can either supply or receive 16
bits of data in parallel. The instruction register is loaded with 16 bits in parallel, directly from the
information bus during an instruction-fetch operation. The 15-bit program counter determines the
sequence in which instructions are executed. It is incremented to take instructions from consecutive locations and the instruction sequence can be altered at any time by changing the PC contents
(jump-class instruction) or by incrementing PC twice (skip-class instruction).

Control- Control signals are supplied to the data path by the internal mask-programmed logic
arrray (PLA). For each of 72 different data-path operations, there is a 24-bit output word in the PLA
selected according to the combination of 19 input lines. These are defined in Figure 2.
The 9440 operates with an on-chip oscillator when a crystal is tied between CP and XTL or it can be
driven by an external oscillator via the CP input. The on-chip clock logic circuit generates the
internal clock signal, a synchronization signal (SYN), and several other timing pulses.
A macro-instruction in the 9440 consists of several microcycles, each with a corresponding one-of16 sequence-control state. Each microcycle consists of several phases, or nanocycles, four of
which are devoted to controlling the data-path circuitry. During each of these phases, the data path
circuitry operates on a 4-bit nibble out of the 16 bits of the operands and clocks its various registers
at half the oscillator rate. Another phase provides the time delay required for a new output word of
the PLA to become valid after the PLA inputs are changed.
The bus register and the instruction register are loaded from the information bus at different times
during the execution cycle.

STATE
SEQUENCE
LOGIC

INSTRUCTION
REGISTER

CONSOLE
LATCHES

MICROPROGRAM PLA

NEXT STATE
SEQUENCE

BUS REG
CONTROL

ALU, AC & MUX
CONTROL

INST REG
CONTROL

PC
CONTROL

~~--------------~v~--------------~J
DATA PATH CONTROL

Fig. 2

Programmed Logic Array

MEMORY
CONTROL

1/0
CONTROL

FAIRCHILD -9440
5

432

DCH
REO
36'

INT
REO

RUN

CARRY

INT ON

ClK OUT
35

XTl
9440
~FlAME

16-BIT
MICROPROCESSOR

IIIIII
24

Vee = PIN 31
hNJ = PIN 12
GND = PIN 10
GND = PIN 30

Fig. 3

Logic Symbol

9440 SIGNAL DESCRIPTIONS (Figure 3)
Information Bus -180-1815 (Inputs/Outputs) - The 16-bit bidirectional 3-state information bus is
used to transfer address, data and instruction information between the processor and main
memory, and to transfer data and control information to and from 1/0 devices. A LOW level defines
a binary '1 '.
Status Lines - RUN, CARRY, INT ON - These lines are used to convey the status information of
the processor mainly for display on an operator console.
RUN (Output) -A HIGH level on this line indicates that the 9440 is not in the WAIT state and is
executing instructions or performing console operations.
CARRY (Output) - Shows the current status of the 9440 Carry flip-flop. A HIGH level is a
binary '1'.
INT ON (Output) - Shows the state of the 9440 Interrupt Enable flip-flop. A HIGH level indicates that the 9440 is enabled to accept interrupts.
Operator Console Control- Co-C3, MR - Using the operator console, a special 1/0 device, the
operator controls 9440 operation via the four C lines and the Master Reset line.
Co-C3 (Inputs) - The various console operations are coded on the Control lines as shown
below. These lines must be active long enough for the 9440 to respond to the command and
indicated by RUN going to the high state, and should be disabled immediately thereafter.
MR (Input) - When a LOW level is applied to Master Reset, the 9440 halts immediately and goes
to a wait state. All internal registers are unaffected. The Interrupt-Enable flip-flop is cleared.
InputlOutput Control- 00-01, INT REO, DCH REO -1/0 devices communicate with the 9440
through the common information bus under either program or interrupt control. Also, high-speed
devices can gain access to main memory via the data channel (DMA mode).

00, 01 (Outputs) - To avoid conflicts on the information bus, the 1/0 devices are sent synchonization signals. A code, defining one of four functions, is conveyed to each 1/0 device
over 00 and 01, which are valid before and during SYN.

FAIRCHILD·9440

OPERATION

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Examine ACO
Examine AC1
Examine AC2
Examine AC3
Examine Next
Examine Memcry
Depcsit Memcry
Halt
Depcsit ACO
Depcsit AC1
Depcsit AC2
Depcsit AC3
Lcad PC
Ccntinue
Depcsit Next
No. cperaticn

FUNCTION

L
L
H
H

L
H
L
H

·Instructicn Fetch
Data Channel Ackncwledge
I/O Execute
No. Operation
I/O-Device Code

Console-Operation Code

INT REO (Input) - The I/O devices can interrupt normal program flow by activating the
Interrupt Request input. The 9440 recognizes an interrupt request at the end of the current
instruction provided its Interrupt-Enable flip-flop is set.
DCH REO (Input) - The I/O devices can gain direct access to the main memory by activating
the Data Channel Request input. After the device is granted data channel access, it can
control memory operation using the Mo-M2 lines.
Of the four functions which can interrupt the normal flow if instruction execution, MASTER
RESET (MR) is the highest priority, followed in order by DCH REO, INT REO and the Console
HALT Command.
Memory Control- Mo-M2, MBSY - The processor controls the main memory via the three opencollector Memory Control lines (Mo-M2) and synchronizes itselfto the memory cycle time indicated
by the Memory-Busy (MBSY) signal.
Mo (Input/Output) - A lOW level on Mo indicates a memory Read operation.
M1 (I nput/Output) - A lOW level on M1 indicates a memory Write operation.
M2 (I nput/Output) - A lOW level on M2 indicates that the memory address register must be
loaded on or before the HIGH-to-lOW transition of SYN.
During DMA operation, the 9440 is not driving the M lines. An external device can control
memory by applying a lOW level on the appropriate M line.
MBSY (Input) -A lOW level on MBSY indicates a memory operation is in progress. When the

9440 starts a memory cycle, MBSY must be HIGH. If it is lOW, the processor clock logic will
defer putting out SYN until MBSY becomes HIGH. For lD MAR or Write memory operations,
the 9440 activates SYN and then waits for MBSY to respond with a lOW level. For a Read
operation, the 9440 waits for MBSY to go lOW and back HIGH before it proceeds.
Timing - CP, XTl, ClK OUT, SYNCP (Input) - The 9440 can operate with an on-chip oscillator when a crystal is tied between CP
and XTL or it can operate from an external clock (CP).
XTl (I nput) - The XTl input is used only when operati ng with a crystal.
ClK OUT (Output) - The internal oscillator is available to the outside world on ClK OUT.
SYN (Output) - SYN is an active lOW synchronization Signal for memory and I/O devices. It is
activated once for each processor microcycle.
Power-Vee, IINJ, GND
Vee requires 5 V, IINJ requires 300 mA current source at 1.0 V.

FAIRCHILD • 9440
9440 INSTRUCTIONS
Memory Reference jnstructions without register are used for branching (JMP, JSR) without
involving accumulators. These instructions are also used for modifying memory (ISZ, DSZl.
Memory Reference instructions with register are used to move 16-bit words between the memory
and the accumulators.
JMP-Jump. The 9440 loads the effective address into the PC. The program sequence
continues from that location.
JSR -Jump to SubRoutine. The 9440 calculates the effective address, then stores PC + 1 into
AC3, loads the effective address into the PC and continues instruction execution from that
location.
ISZ -Increment and Skip if Zero. The 9440 reads a word from the memory location specified
by the effective address, increments the word and writes the result back into the same location.
If the incremented word is zero, the 9440 skips the next instruction.
DSZ - Decrement and Skip if Zero. The 9440 reads a word from the memory location specified
by the effective address; decrements it and writes the result back into the same location. If the
result is zero the 9440 skips the next instruction.
LDA - Load Accumulator. The 9440 loads the contents of the memory location specified by
the effective addre,ss into the accumulator defined by bits 3 and 4 of the instruction.
STA - Store Accumulator. The 9440 stores the contenfs of the selected accumulator into the
memory location specified by the effective address; the accumulator contents are not affected.

OPCODE

DISPLACEMENT

MODE

I
INDIRECT

o
1

ADDRESSING
0
0
1
1

DIRECT
INDIRECT

MEMORY !lEFERENCE
0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

JMP}
JSR
WITHOUT
ISZ
REGISTER
DSZ

0
0

0
1

1
0

A
A

WITH
LOA}
STA
REGISTER

--L

0
1
0
1

PAGE ZERO
PC RELATIVE
INDEXED VIA AC2
INDEXED VIA AC3

0
0
1
1

0
1
0
1

ACO
AC1
AC2
AC3

1
1

____ J
Fig. 4 Memory Ref.rence Instructions

Arithmetic/Logic instructions perform arithmetic (ADD, ADC, INC, NEG, SUB) or Boolean(AND,
COM, MOV) operations on the contents of two r-egisters. The results of each operation together
with the carry bit form a 17-bit word that can be rotated once to the left or to the right.

r...J

0 11 1 2131 41 51&171 8 1

911011111211311+51~

Rotate Left

011 121

314151&171819110111112113114115~
Rotate Right

FAIRCHILD. 9440
The carry bit is calculated according to a base value, as specified by the carry code. That base value
is complemented if the arithmetic operation produces a carry out of bit 0; otherwise the carry bit is
equal to the base value. During a byte swap operation, bits 0-7 and 8-15 of the result are swapped.
The carry bit is not affected.
After the shift and still as part of the same arithmetic/logic instruction, the 9440 checks the shifted
word and the new carry bit for zero or non-zero results. According to the skip code, the 9440 may
skip the next instruction.
The 17-bit shifted word is loaded into the Carry FF and the destination accumulator only ifbit 12 of
the instruction is '0'. Loading is inhibited if bit 12 is '1'.

Arithmetic and Logic Functions
COM - Complement. The 9440 operates on the contents of the source accumulator, logically
complementing it.
NEG -Negate. The 9440 calculates the 2's complement of the contents of the source
accumulator. The base value for the carry bit is complemented only if SRC contained '0'.
MOV - Move. The 9440 takes the contents of the source accumulator, together with the base
value for the carry bit, and performs the operation specified by the shift code as explained
above.
INC-Increment. The 9440 adds '1' to the contents of the source accumulator.
ADC - Add Complement. The 9440 complements the contents of the source accumulator and
adds it to the contents of the destination accumulator.
SUB -Subtract. The 9440 calculates the 2's complement of the contents of the source
accumumlator and adds it to the contents of the destination accumulator (DST - SRcL
ADD -Add. The 9440 adds the contents of the source accumulator and the contents of the
destination accumulator (SRC + DST).
AND -And. The 9440 computes the logic AND function on the source and destination
accumulators (SRC-DSTL

2
1

SRC

4
DST

FUNCTION
I

~ I

AC SELECT
0
0
1
1

0
1
0
1

ACO
AC1
AC2
AC3

SHIFT

0
1
0
1

0
1
0
1
0
1
0
1

CARRY

SKIP

ILOADI
INH

SKIP CODE

ACO
AC1
AC2
AC3

I
0
0
1
1
0
0
1
1

AC SELECT

0
0
1
1

FUNCTION
0
0
0
0
1
1
1
1

COMPLEMENT
NEGATE
MOVE
INCREMENT
ADD COMPLEMENT
SUBTRACT
ADD
AND

I
SHIFT CODE

0
0
1
1

0
1
0
1

DO NOT SHIFT
ROTATE LEFT ONCE
ROTATE RIGHT ONCE
BYTE SWAP

II
0
0
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

DO NOT SKIP
SKIP ALWAYS
SKIP ON ZI'RO CARRY
SKIP ON NON-ZERO CARRY
SKIP ON ZERO RESULT
SKIP ON NON-ZERO RESULT
SKIP IF I'ITHER CARRY OR RESULT ZERO
SKIP IF BOTH CARRY AND RESULT NON-ZERO

CARRY CODE

CURRENT CARRY
ZERO
ONE
COMPLEMENT CURRENT CARRY

0
1
0
1

Fig. 5 Arithmetic/Logic Instructions

II
0
1

LOAD INHIBIT
LOAD RESULT IN DST AC
DO NOT LOAD RESULT IN DST AC

FAIRCHILD. 9440
Input/Output instructions move data between the 9440 accumulators and three buffers in the
peripheral device interface. These instructions also perform control functions in the 1/0 device and
test the status flags in both the peripheral circuitry and the central processor.

NIO-No InputlOutput transfer. The 1/0 device specified by the device code performs the
control function defined by bits 8 and 9 of the instruction.

DIAIB/C-Data In A or B or C. The VO device specified by the device code performs the
control function and sends the contents of its A, B or C buffers to the 9440. The processor loads
that data into the selected accumulator.
DOA/B/C - Data Out A or B or C. The 9440 sends the contents of the selected accumulator to
the 1/0 device specified by the device code. The 1/0 device stores the data in its A, B or C
buffers and performs the control function.
SKPBN - Skip if Busy is Non-Zero. The 9440 skips the next instruction if the busy flag in the
1/0 device specified by the device code is '1'. No control function is executed.
SKPBZ - Skip if Busy is Zero. The 9440 skips the next instruction if the busy flag in the 1/0
devices specified by the device code is '0'. No control function is executed.
SKPDN -Skip if Done is Non-Zero. The 9440 skips the next instruction ifthe done flag in the
1/0 device specified by the device code is '1'. No control function is executed.
SKPDZ - Skip if Done is Zero. The 9440 skips the next instruction if the done flag in the I/O device specified by the device code is '0'. No control function is executed.

Special Device Code-77 Instruction - Device code 77 (octal) is used for some special instructions.
Some like 10RST or Mask Out are common to all 1/0 devices; others, like Interrupt Enable or Halt
are special CPU instructions. In all device code-77 instructions except the skip instructions, bits 8
and 9 control the Interrupt Enable flip-flop in the 9440; An '01' code is used to set it, '10' to reset it.
N lOS CPU -Interrupt Enable. The 9440 sets the Interrupt-Enable flip-flop after a delay of one
instruction to allow for jumping back from an interrupt service routine.

2
OPCODE

I I I

I AD~;ESS I

8
TRANSFER

CONTROL

I I

\I/OINSTRI

AC ADDRESS

10 11 11 1

0
0

0
1
0
1

I ,I

ACO
AC1
AC2
AC3

0
0
1
1

0
1
0
1

DEVICE CODE
USED TO SELECT ONE OF 64 DEVICES

CONTROL
DO NOTHING
START 1/0 DEVICE
CLEAR/IDLE 110 DEVICE
PULSE/SPECIAL FUNCTION

II
FUNCTION
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

NO 110 TRANSFER
DATA INA
DATA OUT A
DATAINB
DATA OUT B
DATAINC
DATA OUT C
SKIP ON BUSY OR DONE

Fig. 6 Input/Output Instrue_lons

{

0
0
1
1

10
1

SKPBN
SKPBZ
SKPDN
SKPDZ

FAIRCHILD • 9440
NIOC CPU -Interrupt Disable. The 9440 clears the Interrupt-Enable flip-flop and does not respond to subsequent Interrupt requests.
DIA CPU - Read Switches. The 9440 loads the contents of the front-panel switches into the
specified accumulator.
DIB CPU -Interrupt Acknowledge. The 9440 loads the device code of the highest priority
1/0 device requesting an interrupt into bits 10-15 of the specified accumulator.
DOB CPU - Mask Out. The 9440 puts the contents of the specified accumulator on the information bus. Each 1/0 device is assigned a particular bit in that word. When the mask bit is
'1', the device disables its interrupt.
DIC CPU - Clear 110 Devices or 10RST. All 1/0 devices connected to the bus must clear
their control flip-flops, including Busy and Done, and disable their interrupts.
DOC CPU - Halt. The 9440 halts after executing this instruction and the console displays
the Halt instruction on the data light. The location of the Halt instruction is displayed on the
address lights.
SKPBN CPU -Skip if Interrupt Enable is Non-Zero. The 9440 will skip the next instruction if
the Interrupt-Enable flip-flop is enabled.
SKPSZ CPU -Skip if Interrupt Enable is Zero. The 9440 skips the next instruction if the
Interrupt-Enable flip-flop is disabled.

9440 MODES OF ADDRESSING
The flexible addressing structure ofthe 9440 consists offourtypes of addressing - one is absolute
addressing of page zero, i.e. the first 256 locations in the memory; the other three are relative
addressing where an a-bit displacment in the memory reference instruction is treated as a signed
number and added to a 15-bit base address in an index register, either AC2, AC3, or PC. Each type
may be either direct or indirect for a total of eight modes. Relative addressing using accumulator
AC2 or AC3 is useful for accessing consecutive entries from a table in the memory, e.g., where a
displacement is added to the incrmented index in the accumulator. Relative addressing utilizing the
program counter is used for jumping to nearby locations when a relocatable program is executed.

In direct addressing, the 15-bit computed value is the actual address used to read or store the
operand. In case of indirect addressing (bit 5 of the instruction is '1'), the computed value is the
address of an address. The data read from an indirectly addressed location can be the final effective
address or another nested indirect address depending on the most significant bit in that word.
Bit 0 of the word read from the indirectly addressed location is treated as another indirect bit. Bits 115 are the effective address ifbitO is'O'.lf bitO is '1', bits 1-15 pOinttoa location in memory where the
next level of indirect address resides. This process can continue indefinitely, as long as bit 0 of each
word read from memory is '1'.
When locations (20)8 through (27)8 are indirectly addressed, the auto-incrementfeature takes over
and the contents of the selected location are first incremented and the new value is treated as the
new address, which can be either direct or indirect. Locations (30)8 through (37)8 are used as autodecrement locations in a sim.ilar fashion.

FAIRCHILD. 9440

ONLY

...,

MEMORY
CONTROL

WEI----!lrIE

UNIT
CONSOLE

--------tCO

LOGIC

SYN

~~---~~r--------~
O, ....- - - - <_ _I--_ _ _ _ _ _ _ _

...2
INPUT/OUTPUT
CONTROL

UNIT

SPECIAL FUNCTIONS

UNIT

INPUT/OUTPUT

INTERFACE
CONTAOL

110

DEVICE

Fig. 7 9440 Mlcroflame System

9440 SYSTEM
The 9440 CPU is a powerful machine that acts as the heart of a minicomputer-class microprocessor. However, to maximize performance, any CPU must be surrounded by support devices. A perfectly matched system can be built as shown in Figure 7.

Here, in addition to the 9440 CPU, the system contains the 9441 Memory Control Unit, the 9442 Input/Output Control Unit, the Special Functions Unit and an array of 93481 or 93483 13L dynamic
memories as follows:
9441 Memory Control Unit contains a 15 bit memory address register, refresh address counter
and a 7-bit address multiplexer. It provides the timing and control signals to operate the 13L
dynamic memory (93481, 93483) for read, write, refresh and DMA operations.
9442 Input/Output Control Unit responds to 1/0 instructions and generates the timing and control signals for 9440 peripheral devices.
93481 4K 13L bipolar dynamic memory. Single 5 V supply, 100 ns performance, compatible
semiconductor memory.
93483 16K 13L bipolar dynamic memory. Single 5 V supply, 100 ns performance, compatible
semiconductor memory.

FAIRCHILD. 9440
ABSOLUTE MAXIMUM RATINGS (beyond which the useful life of the device may be impaired)

-65° to 150°C
-55 to +125°C
-0.5 to +6.0 V
-0.5 to +5.5 V
- 20 ·to +5 mA
-0.5 to +5.5 V
+20 mA
+500 mA
-0.5 to + 1.5 V

Storage Temperature
Ambient Temperature Under Bias
Vee Pin Potential to Ground Pin
Input Voltage (dc)
Input Current (dc)
Output Voltage (Output HIGH)
Output Current (dc) (Output LOW)
Injector Current (IINJ)
Injector Voltage (V INJ )

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (0 to 75°C)
hNJ(min) = 300 mA, hNJ(max) = 400 mA, Vee(min) = 4.75 V, Vee(max) = 5.25 V
LIMITS
SYMBOL

CHARACTERISTIC

VIH

Input HIGH Voltage

MIN

TYP

MAX

UNITS

TEST CONDITIONS

Guaranteed Input HIGH Voltage

0.8

Guaranteed Input lOW Voltage

-1.5

Vee = 4.75 V, liN
IINJ = 300 rnA

2.0

Vll

Input lOW Voltage

VCD

Input Clamp Diode Voltage

VOH

Output HIGH Voltage
RUN, CARRY, INT ON, SYN, ClK OUT, 00' 0 1

2.4

3.4

Vee = 4.75 V, 10H
IINJ = 300 rnA

= -400 pA

Q.utputJ:lIGH Voltage
IBo - IB15

2.4

3.4

Vee = 4.75 V, 10H
IINJ = 300 rnA

= -1.0 rnA

1.0

rnA

Vee = 4.75 V, VOH
tlNJ = 300 rnA

= 5.25 V

0.25

0.5

Vee = 4.75 V, 10l
IINJ = 300 rnA

= 8.0 rnA

-0.9

-18 rnA

tCEx

Output leakage Mo, M1 , M2

VOL

Output lOW Voltage

IIH

Input HIGH Current
Co - C3, DCH REO, tNT REO, MBSY, MR

1.0

Vee = 5.25 V, VIN
IINJ = 300 rnA

= 2.7 V

Input HIGH Current
CP

2.0

Vee = 5.25 V, VIN
IINJ = 300 rnA

= 2.7 V

!!!.put ~GH Current
IBo - IB15 (3-State)

5.0

100

Vee = 4.75 V, VIN
IINJ = 300 rnA

= 2.7 V

1.0

rnA

Vee = 4.75 V, VIN
IINJ = 300 rnA

= 5.5 V

Input HIGH Current
All Inputs
III

- Vee = 5.25V, VIN
IINJ = 300 rnA

= 0.4 V

Input lOW Current
All inputs except CP

-0.21

-0.36

rnA

-Input lOW Current
CP

-0.42

-0.72

rnA

Vee = 5.25 V, V IN
IINJ = 300 rnA

100

Vee = 5.25 V, VOUT
IINJ = 300 rnA

= 2.4 V

-0.36

rnA

Vee = 5.25 V, VOUT
IINJ = 300 rnA

= 0.4 V

-100

rnA

Vee = 5.25 V, VO UT
IINJ = 300 rnA

= 0.0 V

200

rnA

Vee

IINJ

10ZH

OFF State (Hig!! Irnp~ance)
Output Current IBo - IB15

10Zl

OFF State (Hig!!..trnp~ance)
Output Current IBo - IB15

105

Output Short Circui!....Cu~nt_
All Outputs Except Mo, M1 , M2

Icc

Supply Current

150

VINJ

Injector Voltage

1.0

-0.21
-15

= 5.25 V
= 300 rnA

= 0.4 V

FAIRCHILD. 9440
AC CHARACTERISTICS: T A = 0 .to 75° C - Figures 8 & 9 Vcc

= 5.0 V

hNJ

= 300

rnA

LlMITS-ns
SYMBOL

CHARACTERISTIC

tCPSYL

Propagation Delay, CLOCK to SYN going LOW

150

tCPSYH

Propagation Delay, CLOCK to SYN going HIGH

160

tMBSYL

Propagation Delay, MBSY going HIGH to SYN going LOW

tMBw

MBSY Min Pulse Width (HIGH)

tMBs

Set-up Time, MBSY HIGH to CLOCK

-40

tMBHO

Hold Time, MBSY HIGH after CLOCK

tCPMH

Propagation Delay, CLOCK to M2, M1, Mo going HIGH

140

tCPML

Propagation Delay, CLOCK to M2, M1, Mo going LOW

150

tCPOH

Propagation Delay, CLOCK to 01, 00 going HIGH

140

Fig. 9 Only

tCPOL

Propagation Delay, CLOCK to 01,00 going LOW

150

Fig. 8 Only

tCPAH

Propagation Delay, CLOCK to ADDRESS IBo-15 going HIGH

170

tCPAL

Propagation Delay, CLOCK to ADDRESS 180-15 going LOW

180

tMBAF

Propagation Delay, MBSY toADDRESS IBo-15 going 3-state

110

tos

Set-up Time, DATA 180-15 to CLOCK

tOHO

Hold Time, DATA 180-15 after CLOCK

130

tcs

Set-up Time, C3, C2, C1, Co to CLOCK

-110

tCHO

Hold Time, C3, C2, C1, Co after CLOCK

130

tCPRH

Propagation Delay, CLOCK to RUN HIGH

140

tCPRL

Propagation Delay, CLOCK to RUN LOW

150

tocs

Set-up Time, DCH REO to CLOCK

tOCHO

Hold Time, DCH REO after CLOCK

tiS

Set-up Time, INT REO to CLOCK

-100

tlHO

Hold Time. INT REO after CLOCK

120

tCPCYH

Propagation Delay, CLOCK to CARRY HIGH

160

tCPCYL

Propagation Delay, CLOCK to CARRY LOW

150

tCPIOH

Propagation Delay, CLOCK to INT ON HIGH

200

tcPIOL

Propagation Delay, CLOCK to INT ON LOW

190

MIN

TYP

MAX

NOTE

-110

130
Fig. 8 Only

NOTES:
1. The Information Bus is driven as a result of the previous cycle.
2. The Fetch and Read cycles will be stretched out for slower memories.
3. Applies to console operation using this cycle type.
4. When the previous cycle was an 110 IN or 110 OUT cycle.
5. For a CONTINUE operation (#35 in the "9440 Instruction Execution" table on page 18),
6. For a LOAD PC, EXAMINE MEMORY or EXAMINE NEXT operations (#30,31,32 in the "9440 Instruction Execution" table on page 18),

FAIRCHILD • 9440

CLKOUT

Mo
00

--------~------~------------_r--~------~_i,~------~----------------

==~~~------------~-r------~:~~-------------------

Fig. 8

Fetch Cycle

CLK OUT

SVN

---~

--------~--------~----------------+-----------~~~~~-------+--------~---------

oo __________-+________

MEMORY

BUSY
TIME

RUN, DCH REO, INT REO, CARRY, INT ON
unaffected during this cycle.

Fig. 9 Read Cycle

FAIRCHILD • 9440
- AC CHARACTERISTICS: TA

= 0 to 75°C- Figures 10 & 11

Vcc

= 5.0 V,

hNJ

= 300 mA
LlMITS-ns

SYMBOL

CHARACTERISTIC

tCPSYL

Propagation Delay, CLOCK to SYN going LOW

150

tCPSYH

Propagation Delay, CLOCK to SYN gOing HIGH

160

tMBSYL

Propagation Delay, MBSY going HIGH to SYN going LOW

tMBW

MBSY Min Pulse Width (HIGH).

tMBS

Set-up Time, MBSY LOW to CL,OCK

-40

tMBHD

!;Iold Time, MBSY LOW after CLOCK

tCPMH

Propagation Delay, CLOCK to-M2, M1, Mo going HIGH

140

tCPML

Propagation Delay, CLOCK to 1'ii12, M1, Mo going LOW

150

tCPOH

Propagation Delay, CLOCK to 01, 00 going HIGH

140

tCPOL

Propagation Delay, CLOCK to 01,00 going LOW

150

tCPDH

Propagation Delay, CLOCK to DATA 180-15 going HIGH

170

tCPDL

Propagation Delay, CLOCK to DATA 180-15 going LOW

180

tCPDF

Propagation Delay, CLOCK to DATA iBo-15 going 3-state

110

tCPAH

Propagation Delay, CLOCK to AODRES$ 180-15 going HIGH

170

tCPAL

Propagation Delay, CLOCK to ADDRESS 180-15 going LOW

180

tCPAF

Propagation Delay, CLOCK toADDRESS 180-15 going 3-state

160

tcs

Set-up Time, C3, C2, C1, Co to CLOCK

tCHD

Hold Time, C3, C2, C1, Co after CLOCK

MIN

TYP

MAX

NOTE

Fig. 10 Only

Fig. 11 Only

-110
130

NOTES:
7. The Information Bus is driven as a result of the previous cycle.
8. The 9440 waits for MBSY to go LOW. By holding MsSv HIGH, the user may idle the processor.
9. For DEPOSIT MEMORY or DEPOSIT NEXT operations (#33, 34 in-~e "9440 Instruction Execution" table on page 18),
10. For EXAMINE ACCUMULATOR or-DEPOSIT ACCUMULATOR operations (#28:29 in the "9440 Instruction Execution" table on page 18),

ClK OUT
SYN

-----f

Ml==::Ea:====t:=====±====±
M2

==~~~----~------~------~
----+---oO===:$:~~_ _~_ _ _~_ _~

01 __________~~-----'

====::C~===>------------------1----=:"-4::==!!~~=t:========~==:j
CO-3mm~~~~~~~~~~

iiO-15

RUN, DCH REQ,

iNT'iiEci, CARRY, INT ON

unaffected during this cycle.

Flg.10

Write Cycle

FAIRCHILD. 9440
I~---------------------------------------LDMAR--------------------------------------~

SVN

PLA

CLKOUT
SYN
MBSY

ii,
ii2
iio
00
0,
iiO~15

CO-3·

RUN

DCH REO, iNTiiEQ. CARRY, INT ON
unaffected during this cycle.

Flg.11

Load Memory Address Register Cycle

~------------------------I/OOUT------------------------~·~I

PLA

CLKOUT
SYN
MBSY

M,
M2
Mo
00
0,

...-tCPOF

DATA OUT

iiO-15

CO-3
RUN

CARRY

----------------------------------------------------------

INTON _________________________________________________________________________

Fig. 12

1/0 Out Cycle

::1

FAIRCHILD- 9440
AC CHARACTERISTICS: TA = 0 to 75°C- Figures 12,13,14,15 Vcc = 5.0 V, IINJ = 300 mA
LlMITS-ns
SYMBOL

CHARACTERISTIC

tCPSYL

Propagation Delay, CLOCK to SYN going LOW

150

tCPSYH

Propagation Delay, CLOCK to SYN going HIGH

160

tCPMH

Propagation Delay, CLOCK to M2, M1, Mo going HIGH

140

tCPML

Propagation Delay, CLOCK to M2, M1, Mo going LOW

150

tCPOH

Propagation Delay, CLOCK to 01, 00 going HIGH

140

tCPOL

Propagation Delay, CLOCK to 01, 00 going LOW

150

tCPDH

Propagation Delay, CLOCK to DATA 180-15 going HIGH

170

tCPDL

Propagation Delay, CLOCK to DATA 180-15 going LOW

180

tCPDF

Propagation Delay, CLOCK to DATA 180-15 going 3-state

110

tDS

Set-up Time, DATA 180-15 to CLOCK

tDHD

Hold Time, DATA 180-15 after CLOCK

130

tcs

Set-up Time, C3, C2, C1, Co to CLOCK

-110

tCHD

Hold Time, C3, C2, C1, Co after CLOCK

MIN

TYP

MAX

NOTE

Fig. 12 Only

-110
Fig. 13 Only

130

Fig. 14 Only

NOTES:
11. During DCH, the 9440 is not driving the M lines. An external device can control the memory when a LOW is applied to the appropriate M line.
12. The 9440 floats the iSo-,s. The Information Bus is available to the I/O devices, the Console, and the memory as needed.
13. For all the CONSOLE operations (#28-35 in the "9440 Instruction Execution" table on page 18),
14. For CONSOLE operations (#28-34 in the "9440 Instruction Execution" table on page 18),

__-----------I/ON ------------t-I
PLA

CLKOUT
SYN -----r
M1

----+-~--.

----+----

:::::::::t::::::~""\o~-- --- ---- - --- - ----- ---

Oo __________

~--------~~--------------------------~-----------

01 __________~------~

iiiO-15

_lcPMH_1
-j IDS .... IDHD:!j
----------...:.:::..-.:::.-=:.--------------------------4(jD~A~TA~INCJ>I------

CO-3

RUN __________________________----_________________________________

CARRY _________________________________________________________________
INTON _________________________________________________________________
Fig. 13

1/0 In Cycle

FAIR.CHILD • 9440

I~'-------------------------WAIT------------------------~·I
o
3
~A

ClK OUT
SYN

M,
M.

----~

----~~-~

----+-------+----

OO __________~~------~

O, ____________~--------'

CO-3 _ _ _

~-~~~~~

ICPRL~@_______________________________________________
RUN _____________________
~a_

DCH REQ

CARRY __________________________________________~---------------------------INTON ________________________________________________________________________

Fig. 14 Walt Cycle
~-------------------------DCH-------------------------·~I

PLA

ClK OUT
SYN
MBSY

M,
@

Mo
00
0,

mO-'5---------------------------------------------------------------------------------------------------~---~~

~~--------------------------------------------------------------------

RUN ________________________________________________________________________

DCHREQ
INT REQ
CARRY ________________________________________________________________________
INTON ________________________________________________________________________

Flg.15

Data Channel Request Cycle

FAIRCHILD • 9440
9440 INSTRUCTION EXECUTION
INSTRUCTION
OR
OPERATION

NO.

1 Jump
2

Jump Indirect

3 Jump to Subroutine

EXECUTION
TIME (~s) @

CYCLE TYPE AND SEQUENCE"

FETCH

READ

LD
1/0
WRITE MAR OUT

1/0
IN

WAIT

DCH

1
3

1.875

1.5

1.25

5.50

4.4

3.66

1.875

1.5

1.25

5.50

4.4

3.66

JSR Indirect

Increment and Skip if Zero

5.50

4.4

3.66

ISZ Indirect

1,3

2,4

9.125

7.3

6.07

Decrement and Skip if Zero

5.50

4.4

3.66

DSZ Indirect

1,3

2,4

9.125

7.3

6.07

Load Accumulator

3.75

3.0

2.50

LOA Indirect

1,3

7.375

5.9

4.91

Store Accumulator

5.50

4.4

3.66

1,3

2,4

9.125

7.3

6.07

10 MHz 12 MHz

8 MHz

STA Indirect

Complement

1.875

1.5

1.25

Negate

1.875

1.5

1.25

Move

1.875

1.5

1.25

Increment

1.875

1.5

1.25

Add Complement

1.875

1.5

1.25

Subtract

1.875

1.5

1.25

1.875

1.5

1.25

1.875

1.5

1.25

1,2

3.75

3.0

2.50

3.125

2.5

2.08

3.125

2.5

2.08

19 Add
20

AND

ALU with Skip

1/0 Data In

1/0 Data Out

Skip on Busy or Done

2
5

1
1
1
3

2,4

3.125

2.5

2.08

9.0

7.2

5.98

1.25

1.0

0.83

1.25

1.0

0.83

Interrupt

Data Channel

Wait

Examine Accumulator

2.50

2.0

1.66

Deposit Accumulator

3.125

2.5

1.66

Load PC

3.125

2.5

2.08

1
1

Examine Memory

3.125

2.5

2.08

Examine Next

3.125

2.5

2.08

Deposit Memory

4.75

3.8

3.15

Deposit Next

4.75

3.8

3.15

Continue

3.125

2.5

2.08

"e.g., No.6, ISZ Indirect:
1st cycle- READ
2nd cycle-WRITE
3rd cycle - READ
4th cycle-WRITE
5th cycle - FETCH

FAIRCHILD. 9440
9440 SOFTWARE
A performance-matched package of software for the 9440 is provided to optimize the use of the
9440 in a wide range of applications. The entire software package is called the Fairchild Integrated
Real-time Executive (FIR!:"'>' The initial set of available programs consists of:

FIRE-DIAGNOSTICS for testing 9440-based systems
FIRE-1 PACKAGE

FIRE-LOAD bootstrap and binary loaders
FIREBUG interactive assembler, debugger and editor
FIRE-SYMBUG symbolic debugger
FIRE-EDIT text editor
FIRE-BASIC high-level language interactive interperter

Software to be available shortly includes: a macroassembler, a floppy-disk operating system, a
storage module operating system and a FORTRAN compiler.
Cross Macro Assembler, a Cross Linking Loader and a Cross Simulator Debugger are available for
the FIRE Family of processors on a worldwide time sharing basis through the following company.
Mr. Michael Rooney, President
The Boston Systems Office, Inc.
469 Moody Street
Waltham, Massachusetts 02154
Tel. (617) 894-7800
PACKAGE OUTLINE
40-PIN CERAMIC DUAL
IN-LINE SIDE-BRAZED

1--_ _ _ _ 2.020 (5'1.3P8} _ _ _ _--.l
1.980 (50.292)

.025 (0.635)
R

.610 (15,494)
.590 (14,986)

k· rl
(12.700)
6OO
.480
(12.192)

::::;:,
t .085

.-----

.175 (4.445)
.126 (3.175)

(2,159)

NOTES:
All dimensions in inches (bold) and
millimeters (parentheses)
Pin material nickel gold-plated kovar
Cap is kovar
Base is ceramic
Package weight is 6.5 grams

.011 (0.279)
.009 (0.229)

(20:~5}L.675 (17.145}j

.020 (0.5OB)
.016 (0.406)
TYP.

MAX .

ORDERING INFORMATION
ORDER CODE
9440DC

PACKAGE
CERAMIC DIP

TEMPERATURE
o TO 75°C

For other temperature ranges, contact Fairchild Sales Office.

FAIRCHILD. 9440

I=AIRCHIL.C

Fairchild cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in a Fairchild product. No other circuit patent licenses are implied.
Manufactured under one of the following U.S. Patents: 2981877. 3015048. 3064167. 3108359. 3117260; other patents pending.
Fairchild reserves the fight to make changes

the circuitry or speCifications at any time without notice.

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F9440_Microflame_Data_Sheet_Dec78 F9440 Microflame Data Sheet Dec78

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