GD32F1x0 User Manual
User Manual:
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- Table of Contents
- List of Figures
- List of Tables
- 1. System and memory architecture
- 1.1. ARM Cortex-M3 processor
- 1.2. System architecture
- 1.3. Memory map
- 1.4. Boot configuration
- 1.5. System configuration registers (SYSCFG)
- 1.5.1. System configuration register 0 (SYSCFG_CFG0)
- 1.5.2. System configuration register 1 (SYSCFG_CFG1)
- 1.5.3. EXTI sources selection register 0 (SYSCFG_EXTISS0)
- 1.5.4. EXTI sources selection register 1 (SYSCFG_EXTISS1)
- 1.5.5. EXTI sources selection register 2 (SYSCFG_EXTISS2)
- 1.5.6. EXTI sources selection register 3 (SYSCFG_EXTISS3)
- 1.5.7. System configuration register 2 (SYSCFG_CFG2)
- 1.6. Device electronic signature
- 2. Power management unit (PMU)
- 3. Flash memory controller (FMC)
- 3.1. Introduction
- 3.2. Main features
- 3.3. Function description
- 3.4. FMC registers
- 3.4.1. Wait state register (FMC_WS)
- 3.4.2. Unlock key register (FMC_KEY)
- 3.4.3. Option byte unlock key register (FMC_OBKEY)
- 3.4.4. Status register (FMC_STAT)
- 3.4.5. Control register (FMC_CTL)
- 3.4.6. Address register (FMC_ADDR)
- 3.4.7. Option byte status register (FMC_OBSTAT)
- 3.4.8. Write protection register (FMC_WP)
- 3.4.9. Wait state enable register (FMC_WSEN)
- 3.4.10. Product ID register (FMC_PID)
- 4. Reset and clock unit (RCU)
- 4.1. Reset control unit (RCTL)
- 4.2. Clock control unit (CCTL)
- 4.3. RCU registers
- 4.3.1. Control register 0 (RCU_CTL0)
- 4.3.2. Configuration register 0 (RCU_CFG0)
- 4.3.3. Interrupt register (RCU_INT)
- 4.3.4. APB2 reset register (RCU_APB2RST)
- 4.3.5. APB1 reset register (RCU_APB1RST)
- 4.3.6. AHB enable register (RCU_AHBEN)
- 4.3.7. APB2 enable register (RCU_APB2EN)
- 4.3.8. APB1 enable register (RCU_APB1EN)
- 4.3.9. Backup domain control register (RCU_BDCTL)
- 4.3.10. Reset source /clock register (RCU_RSTSCK)
- 4.3.11. AHB reset register (RCU_AHBRST)
- 4.3.12. Configuration register 1 (RCU_CFG1)
- 4.3.13. Configuration register 2 (RCU_CFG2)
- 4.3.14. Control register 1 (RCU_CTL1)
- 4.3.15. Configuration register 3 (RCU_CFG3) of GD32F170xx and GD32F190xx devices
- 4.3.16. Additional enable register (RCU_ADDEN)
- 4.3.17. Additional reset register (RCU_ADDRST)
- 4.3.18. Voltage key register (RCU_VKEY)
- 4.3.19. Deep-sleep mode voltage register (RCU_DSV)
- 4.3.20. Power down voltage select register (RCU_PDVSEL) of GD32F130xx and GD32F150xx devices
- 5. General-purpose and alternate-function I/Os (GPIO and AFIOs)
- 5.1. Introduction
- 5.2. Main features
- 5.3. Function description
- 5.4. GPIO registers
- 5.4.1. Port control register (GPIOx_CTL) (x=A..D,F)
- 5.4.2. Port output mode register (GPIOx_OMODE) (x=A..D,F)
- 5.4.3. Port output speed register (GPIOx_OSPD) (x=A..D,F)
- 5.4.4. Port pull-up/down register (GPIOx_PUD) (x=A..D,F)
- 5.4.5. Port input status register (GPIOx_ISTAT) (x=A..D,F)
- 5.4.6. Port output control register (GPIOx_OCTL) (x=A..D,F)
- 5.4.7. Port bit operate register (GPIOx_BOP) (x=A..D,F)
- 5.4.8. Port configuration lock register (GPIOx_LOCK) (x=A, B)
- 5.4.9. Alternate function selected register0 (GPIOx_AFSEL0) (x=A, B, C)
- 5.4.10. Alternate function selected register1 (GPIOx_AFSEL1) (x=A,B,C)
- 5.4.11. Bit clear register (GPIOx_BC) (x=A..D,F)
- 5.4.12. Port bit toggle register (GPIOx_TGx) (x=A..D,F) of GD32F170xx and GD32F190xx devices
- 6. CRC calculation unit
- 7. Interrupts and events
- 8. Direct memory access controller (DMA)
- 8.1. Introduction
- 8.2. Main features
- 8.3. Function description
- 8.4. DMA registers
- 8.4.1. Interrupt flag register (DMA_INTF)
- 8.4.2. Interrupt flag clear register (DMA_INTC)
- 8.4.3. Channel x control registers (DMA_CHxCTL0)
- 8.4.4. Channel x counter registers (DMA_CHxCNT)
- 8.4.5. Channel x peripheral base address registers (DMA_CHxPADDR)
- 8.4.6. Channel x memory base address registers (DMA_CHxMADDR)
- 9. Timer (TIMERx)
- 9.1. Advanced timer (TIMER0)
- 9.1.1. Introduction
- 9.1.2. Main features
- 9.1.3. Function description
- Prescaler counter
- Upcounting mode
- Downcounting mode
- Center-aligned counting mode
- Counter Repetition
- Clock selection
- Capture/compare channels
- Input Capture Mode
- Output Compare Mode/PWM Mode
- Channel Output Reference Signal
- Outputs Complementary and Dead-time
- Break function
- Single Pulse Mode
- Quadrature Decoder
- Slave Controller
- Timer Interconnection
- Timer debug mode
- 9.1.4. TIMER0 registers
- Control register 0 (TIMERx_CTL0)
- Control register 1 (TIMERx_CTL1)
- Slave mode configuration register (TIMERx_SMCFG)
- DMA and interrupt enable register (TIMERx_DMAINTEN)
- Interrupt flag register (TIMERx_INTF)
- Software event generation register (TIMERx_SWEVG)
- Channel control register 0 (TIMERx_CHCTL0)
- Channel control register 1 (TIMERx_CHCTL1)
- Channel control register 2 (TIMERx_CHCTL2)
- Counter register (TIMERx_CNT)
- Prescaler register (TIMERx_PSC)
- Counter auto reload register (TIMERx_CAR)
- Counter repetition register (TIMERx_CREP)
- Channel 0 capture/compare value register (TIMERx_CH0CV)
- Channel 1 capture/compare value register (TIMERx_CH1CV)
- Channel 2 capture/compare value register (TIMERx_CH2CV)
- Channel 3 capture/compare value register (TIMERx_CH3CV)
- Channel Complementary Protection register (TIMERx_CCHP)
- DMA configuration register (TIMERx_DMACFG)
- DMA Transfer buffer register (TIMERx_DMATB)
- Configuration register (TIMERx_CFG) of GD32F170xx and GD32F190xx devices
- 9.2. General timers (TIMER1/TIMER2)
- 9.2.1. Introduction
- 9.2.2. Main features
- 9.2.3. Function description
- 9.2.4. TIMER1/TIMER2 registers
- Control register 0 (TIMERx_CTL0)
- Control register 1 (TIMERx_CTL1)
- Slave mode configuration register (TIMERx_SMCFG)
- DMA and interrupt enable register (TIMERx_DMAINTEN)
- Interrupt flag register (TIMERx_INTF)
- Software event generation register (TIMERx_SWEVG)
- Channel control register 0 (TIMERx_CHCTL0)
- Channel control register 1 (TIMERx_CHCTL1)
- Channel control register 2 (TIMERx_CHCTL2)
- Counter register (TIMERx_CNT)
- Prescaler register (TIMERx_PSC)
- Counter auto reload register (TIMERx_CAR)
- Channel 0 capture/compare value register (TIMERx_CH0CV)
- Channel 1 capture/compare value register (TIMERx_CH1CV)
- Channel 2 capture/compare value register (TIMERx_CH2CV)
- Channel 3 capture/compare value register (TIMERx_CH3CV)
- DMA configuration register (TIMERx_DMACFG)
- DMA Transfer buffer register (TIMERx_DMATB)
- Configuration register (TIMERx_CFG) of GD32F170xx and GD32F190xx devices
- 9.3. Basic timer (TIMER5)
- 9.3.1. Introduction
- 9.3.2. Main features
- 9.3.3. Function description
- 9.3.4. TIMER5 registers
- Control register 0 (TIMERx_CTL0)
- Control register 1 (TIMERx_CTL1)
- DMA and interrupt enable register (TIMERx_DMAINTEN)
- Interrupt flag register (TIMERx_INTF)
- Software event generation register (TIMERx_SWEVG)
- Counter register (TIMERx_CNT)
- Prescaler register (TIMERx_PSC)
- Counter auto reload register (TIMERx_CAR)
- 9.4. General timer (TIMER13)
- 9.4.1. Introduction
- 9.4.2. Main features
- 9.4.3. Function description
- 9.4.4. TIMER13 registers
- Control register 0 (TIMERx_CTL0)
- Interrupt enable register (TIMERx_DMAINTEN)
- Interrupt flag register (TIMERx_INTF)
- Software event generation register (TIMERx_SWEVG)
- Channel control register 0 (TIMERx_CHCTL0)
- Channel control register 2 (TIMERx_CHCTL2)
- Counter register (TIMERx_CNT)
- Prescaler register (TIMERx_PSC)
- Counter auto reload register (TIMERx_CAR)
- Channel 0 capture/compare value register (TIMERx_CH0CV)
- Channel input remap register(TIMERx_IRMP)
- Configuration register (TIMERx_CFG) of GD32F170xx and GD32F190xx devices
- 9.5. General timer (TIMER14)
- 9.5.1. Introduction
- 9.5.2. Main features
- 9.5.3. Function description
- 9.5.4. TIMER14 registers
- Control register 0 (TIMERx_CTL0)
- Control register 1 (TIMERx_CTL1)
- Slave mode configuration register (TIMERx_SMCFG)
- DMA and interrupt enable register (TIMERx_DMAINTEN)
- Interrupt flag register (TIMERx_INTF)
- Software event generation register (TIMERx_SWEVG)
- Channel control register 0 (TIMERx_CHCTL0)
- Channel control register 2 (TIMERx_CHCTL2)
- Counter register (TIMERx_CNT)
- Prescaler register (TIMERx_PSC)
- Counter auto reload register (TIMERx_CAR)
- Counter repetition register (TIMERx_CREP)
- Channel 0 capture/compare value register (TIMERx_CH0CV)
- Channel 1 capture/compare value register (TIMERx_CH1CV)
- Complementary Channel Protection register (TIMERx_CCHP)
- DMA configuration register (TIMERx_DMACFG)
- DMA Transfer buffer register (TIMERx_DMATB)
- Configuration register (TIMERx_CFG) of GD32F170xx and GD32F190xx devices
- 9.6. General timer (TIMER15/TIMER16)
- 9.6.1. Introduction
- 9.6.2. Main features
- 9.6.3. Function description
- 9.6.4. TIMER15/TIMER16 registers
- Control register 0 (TIMERx_CTL0)
- Control register 1 (TIMERx_CTL1)
- DMA and interrupt enable register (TIMERx_DMAINTEN)
- Interrupt flag register (TIMERx_INTF)
- Software event generation register (TIMERx_SWEVG)
- Channel control register 0 (TIMERx_CHCTL0)
- Channel control register 2 (TIMERx_CHCTL2)
- Counter register (TIMERx_CNT)
- Prescaler register (TIMERx_PSC)
- Counter auto reload register (TIMERx_CAR)
- Counter repetition register (TIMERx_CREP)
- Channel 0 capture/compare value register (TIMERx_CH0CV)
- Channel Complementary Protection register (TIMERx_CCHP)
- DMA configuration register (TIMERx_DMACFG)
- DMA Transfer buffer register (TIMERx_DMATB)
- Configuration register (TIMERx_CFG) of GD32F170xx and GD32F190xx devices
- 9.1. Advanced timer (TIMER0)
- 10. Infrared ray port (IFRR)
- 11. Watchdog timer (WDGT)
- 12. Analog to digital converter (ADC)
- 12.1. Introduction
- 12.2. Main features
- 12.3. Function description
- 12.3.1. Calibration (ADC_CLB)
- 12.3.2. Dual clock domain architecture
- 12.3.3. Regular and inserted channel groups
- 12.3.4. Conversion modes
- 12.3.5. Analog watchdog
- 12.3.6. Inserted channel management
- 12.3.7. Data alignment
- 12.3.8. Programmable sample time
- 12.3.9. External trigger
- 12.3.10. DMA request
- 12.3.11. Temperature sensor and internal reference voltage VREF
- 12.3.12. Battery voltage monitoring
- 12.3.13. ADC interrupts
- 12.3.14. Programmable resolution (RES) - fast conversion mode for GD32F170xx and GD32F190xx devices
- 12.3.15. Oversampling for GD32F170xx and GD32F190xx devices
- 12.4. ADC registers
- 12.4.1. Status register (ADC_STAT)
- 12.4.2. Control register 0 (ADC_CTL0)
- 12.4.3. Control register 1 (ADC_CTL1)
- 12.4.4. Sampling time register 0 (ADC_SAMPT0)
- 12.4.5. Sampling time register 1 (ADC_SAMPT1)
- 12.4.6. Inserted channel data offset registers (ADC_IOFFx) (x=0..3)
- 12.4.7. Watchdog high threshold register (ADC_WDHT)
- 12.4.8. Watchdog low threshold register (ADC_WDLT)
- 12.4.9. Regular sequence register 0 (ADC_RSQ0)
- 12.4.10. Regular sequence register 1 (ADC_RSQ1)
- 12.4.11. Regular sequence register 2 (ADC_RSQ2)
- 12.4.12. Inserted sequence register (ADC_ISQ)
- 12.4.13. Inserted data registers (ADC_IDATAx) (x= 0..3)
- 12.4.14. Regular data register (ADC_RDATA)
- 12.4.15. Oversampling control register (ADC_OVSAMPCTL) of GD32F170xx and GD32F190xx devices
- 13. Digital-to-analog converter (DAC)
- 13.1. DAC Introduction
- 13.2. DAC Main features
- 13.3. DAC Function description
- 13.4. DAC registers
- 13.4.1. Control register (DAC_CTL)
- 13.4.2. Software trigger register (DAC_SWT)
- 13.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)
- 13.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH)
- 13.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)
- 13.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH) of GD32F190xx devices
- 13.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) of GD32F190xx devices
- 13.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH) of GD32F190xx devices
- 13.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) of GD32F190xx devices
- 13.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) of GD32F190xx devices
- 13.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) of GD32F190xx devices
- 13.4.12. DAC0 data output register (DAC0_DO)
- 13.4.13. DAC1 data output register (DAC1_DO) of GD32F190xx devices
- 13.4.14. Status register (DAC_STAT)
- 14. Inter-integrated circuit (I2C) interface
- 14.1. Introduction
- 14.2. Main features
- 14.3. Function description
- 14.4. I2C registers
- 14.4.1. Control register 0 (I2C_CTL0)
- 14.4.2. Control register 1 (I2C_CTL1)
- 14.4.3. Slave address register 0 (I2C_SADDR0)
- 14.4.4. Slave address register 1 (I2C_SADDR1)
- 14.4.5. Transfer buffer register (I2C_DATA)
- 14.4.6. Transfer status register 0 (I2C_STAT0)
- 14.4.7. Transfer status register 1 (I2C_STAT1)
- 14.4.8. Clock configure register (I2C_CKCFG)
- 14.4.9. Rise time register (I2C_RT)
- 14.4.10. SAM control and status register (I2C_SAMCS) of GD32F170xx and GD32F190xx devices
- 15. Serial peripheral interface/Inter-IC sound(SPI/I2S)
- 15.1. Introduction
- 15.2. Main features
- 15.3. SPI function description
- 15.3.1. Pin configuration (Single wire, default)
- 15.3.2. Pin configuration (Quad wire) for GD32F170xx and GD32F190xx devices
- 15.3.3. SPI slave mode
- 15.3.4. SPI master mode
- 15.3.5. SPI quad wire operation in master mode for GD32F170xx and GD32F190xx devices
- 15.3.6. SPI simplex communication
- 15.3.7. Data Rx and Tx procedures
- 15.3.8. CRC calculation
- 15.3.9. Status flags and error flags
- 15.3.10. Disabling the SPI
- 15.3.11. DMA requests
- 15.3.12. SPI interrupts
- 15.4. I2S function description
- 15.5. SPI registers
- 15.5.1. Control register 0 (SPI_CTL0)
- 15.5.2. Control register 1 (SPI_CTL1)
- 15.5.3. Status register (SPI_STAT)
- 15.5.4. Data register (SPI_DATA)
- 15.5.5. CRC polynomial register (SPI_CRCPOLY)
- 15.5.6. Receive CRC register (SPI_RCRC)
- 15.5.7. Transmit CRC register (SPI_TCRC)
- 15.5.8. I2S control register (SPI_I2SCTL)
- 15.5.9. I2S prescaler register (SPI_I2SPSC)
- 15.5.10. Quad wire control register (SPI_QCTL) of GD32F170xx and GD32F190xx devices
- 16. Comparator (CMP)
- 17. Universal synchronous asynchronous receiver transmitter (USART)
- 17.1. Introduction
- 17.2. Main features
- 17.3. Function description
- 17.3.1. USART transmitter
- 17.3.2. USART receiver
- 17.3.3. Reception errors
- 17.3.4. Baud rate generation
- 17.3.5. Auto baudrate detection
- 17.3.6. Multi-processor communication
- 17.3.7. ModBus communication
- 17.3.8. LIN mode
- 17.3.9. Half-duplex communication mode
- 17.3.10. Synchronous mode
- 17.3.11. Smartcard (ISO7816) mode
- 17.3.12. IrDA SIR ENDEC mode
- 17.3.13. Hardware flow control
- 17.3.14. DMA requests
- 17.3.15. Wakeup from Deep-sleep mode
- 17.3.16. USART interrupts
- 17.4. USART registers
- 17.4.1. Control register 0 (USART_CTL0)
- 17.4.2. Control register 1 (USART_CTL1)
- 17.4.3. Control register 2 (USART_CTL2)
- 17.4.4. Baud rate generator register (USART_BAUD)
- 17.4.5. Prescaler and guard time configuration register (USART_GP)
- 17.4.6. Receiver timeout register (USART_RT)
- 17.4.7. Command register (USART_CMD)
- 17.4.8. Status register (USART_STAT)
- 17.4.9. Interrupt status clear register (USART_INTC)
- 17.4.10. Receive data register (USART_RDATA)
- 17.4.11. Transmit data register (USART_TDATA)
- 18. Debug (DBG)
- 19. Universal serial bus full-speed device interface (USBD)
- 19.1. Introduction
- 19.2. Main features
- 19.3. Function description
- 19.4. USB registers
- 19.4.1. Control register (USBD_CTL)
- 19.4.2. Interrupt flag register (USBD_INTF)
- 19.4.3. Status register (USBD_STAT)
- 19.4.4. Device address register (USBD_DADDR)
- 19.4.5. Buffer address register (USBD_BADDR)
- 19.4.6. Endpoint n control/status register (USBD_EPxCS), n=[0..7]
- 19.4.7. Transmission buffer address register x (USBD_TADDRx)
- 19.4.8. Transmission byte count register x (USBD_TCNTx)
- 19.4.9. Reception buffer address register x (USBD_RADDRx)
- 19.4.10. Reception byte count register x (USBD_RCNTx)
- 19.4.11. Sub-endpoint x registers (USBD_SEPx), n=[0..7]
- 19.4.12. LPM control register (USBD_LPMCTL)
- 19.4.13. LPM interrupt flag register (USBD_LPMINTF)
- 20. Real-time clock(RTC)
- 20.1. Introduction
- 20.2. Main features
- 20.3. Function description
- 20.3.1. Block diagram
- 20.3.2. RTC pin
- 20.3.3. Clock and prescalers
- 20.3.4. Real-time clock and calendar
- 20.3.5. Configurable and field maskable alarm
- 20.3.6. RTC initialization and configuration
- 20.3.7. Calendar reading
- 20.3.8. Resetting the RTC
- 20.3.9. RTC synchronization
- 20.3.10. RTC reference clock detection
- 20.3.11. RTC smooth digital calibration
- 20.3.12. Time-stamp function
- 20.3.13. Tamper detection
- 20.3.14. Calibration clock output
- 20.3.15. Alarm output
- 20.3.16. RTC power saving mode management
- 20.3.17. RTC interrupts
- 20.4. RTC registers
- 20.4.1. Time of day register (RTC_TIME)
- 20.4.2. Date register (RTC_DATE)
- 20.4.3. Control register (RTC_CTL)
- 20.4.4. Status register (RTC_STAT)
- 20.4.5. Time prescaler register (RTC_PSC)
- 20.4.6. Alarm 0 Time and date register (RTC_ALRM0TD)
- 20.4.7. Write protection key register (RTC_WPK)
- 20.4.8. Sub second register (RTC_SS)
- 20.4.9. Shift function control register (RTC_SHIFTCTL)
- 20.4.10. Time of time stamp register (RTC_TTS)
- 20.4.11. Date of time stamp register (RTC_DTS)
- 20.4.12. Sub second of time stamp register (RTC_SSTS)
- 20.4.13. High resolution frequency compensation registor (RTC_HRFC)
- 20.4.14. Tamper register (RTC_TAMP)
- 20.4.15. Alarm 0 sub second register (RTC_ALRM0SS)
- 20.4.16. Backup register (RTC_BKPx)(x=0,1,2,3,4)
- 21. Touch sensing interface(TSI)
- 21.1. Introduction
- 21.2. Main features
- 21.3. Function description
- 21.3.1. TSI block diagram
- 21.3.2. Touch sensing technique overview
- 21.3.3. Charge transfer sequence
- 21.3.4. Charge transfer sequence FSM
- 21.3.5. Clock and duration time of states
- 21.3.6. PIN mode control of TSI
- 21.3.7. ASW and hysteresis mode
- 21.3.8. TSI operation flow
- 21.3.9. TSI flags and interrupts
- 21.3.10. TSI GPIOs
- 21.4. TSI registers
- 21.4.1. Control register (TSI_CTL)
- 21.4.2. Interrupt enable register (TSI_INTEN)
- 21.4.3. Interrupt flag clear register (TSI_INTC)
- 21.4.4. Interrupt flag register (TSI_INTF)
- 21.4.5. Pin hysteresis mode register (TSI_PHM)
- 21.4.6. Analog switch register (TSI_ASW)
- 21.4.7. Sample configuration register (TSI_SAMPCFG)
- 21.4.8. Channel configuration register (TSI_CHCFG)
- 21.4.9. Group control register (TSI_GCTL)
- 21.4.10. Group x cycle number registers (TSI_GxCYCN) (x= 0..5)
- 22. HDMI-CEC controller(HDMI-CEC)
- 23. Segment LCD controller (SLCD)
- 24. Operational amplifiers (OPA)/ Programmable current and voltage reference (IVREF)
- 25. Controller area network (CAN)
- 25.1. Introduction
- 25.2. Main features
- 25.3. Function description
- 25.4. CAN registers
- 25.4.1. Control register (CAN_CTL)
- 25.4.2. Status register (CAN_STAT)
- 25.4.3. Transmit status register (CAN_TSTAT)
- 25.4.4. Receive message FIFO0 register (CAN_RFIFO0)
- 25.4.5. Receive message FIFO1 register (CAN_RFIFO1)
- 25.4.6. Interrupt enable register (CAN_INTEN)
- 25.4.7. Error register (CAN_ERR)
- 25.4.8. Bit timing register (CAN_BT)
- 25.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2)
- 25.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2)
- 25.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2)
- 25.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2)
- 25.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0..1)
- 25.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0..1)
- 25.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0..1)
- 25.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0..1)
- 25.4.17. Filter control register (CAN_FCTL)
- 25.4.18. Filter mode configuration register (CAN_FMCFG)
- 25.4.19. Filter scale configuration register (CAN_FSCFG)
- 25.4.20. Filter associated FIFO register (CAN_FAFIFO)
- 25.4.21. Filter working register (CAN_FW)
- 25.4.22. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0..1)
- 25.4.23. PHY control register (CAN_PHYCTL)
- 26. Revision history