GRLIB IP Core User’s Manual
User Manual:
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- 1 Introduction
- 2 AHB2AHB - Uni-directional AHB/AHB bridge
- 2.1 Overview
- 2.2 Operation
- 2.2.1 General
- 2.2.2 AHB read transfers
- 2.2.3 AHB write transfers
- 2.2.4 Deadlock conditions
- 2.2.5 Locked transfers
- 2.2.6 Read and write combining
- 2.2.7 Burst operation
- 2.2.8 Transaction ordering, starvation and AMBA arbitration schemes
- 2.2.9 First-come, first-served ordering
- 2.2.10 Bus arbiter ordering
- 2.2.11 AMBA SPLIT support
- 2.2.12 Core latency
- 2.2.13 Endianness
- 2.3 Registers
- 2.4 Vendor and device identifiers
- 2.5 Implementation
- 2.6 Configuration options
- 2.7 Signal descriptions
- 2.8 Library dependencies
- 2.9 Instantiation
- 3 AHBM2AXI - AHB Master to AXI Adapter
- 4 AHB2AXIB - AHB to AXI Bridge
- 5 AHBBRIDGE - Bi-directional AHB/AHB bridge
- 6 AHBCTRL - AMBA AHB controller with plug&play support
- 7 AHBJTAG - JTAG Debug Link with AHB Master Interface
- 8 AHBRAM - Single-port RAM with AHB interface
- 9 AHBDPRAM - Dual-port RAM with AHB interface
- 10 AHBROM - Single-port ROM with AHB interface
- 11 AHBSTAT - AHB Status Registers
- 12 AHBTRACE - AHB Trace buffer
- 13 AHBUART- AMBA AHB Serial Debug Interface
- 14 AMBAMON - AMBA Bus Monitor
- 15 APBCTRL - AMBA AHB/APB bridge with plug&play support
- 16 APBPS2 - PS/2 host controller with APB interface
- 17 APBUART - AMBA APB UART Serial Interface
- 17.1 Overview
- 17.2 Operation
- 17.3 Baud-rate generation
- 17.4 Loop back mode
- 17.5 FIFO debug mode
- 17.6 Interrupt generation
- 17.7 Registers
- 17.8 Vendor and device identifiers
- 17.9 Implementation
- 17.10 Configuration options
- 17.11 Signal descriptions
- 17.12 Signal definitions and reset values
- 17.13 Timing
- 17.14 Library dependencies
- 17.15 Instantiation
- 18 APBVGA - VGA controller with APB interface
- 19 CAN_OC - GRLIB wrapper for OpenCores CAN Interface core
- 19.1 Overview
- 19.2 Opencores CAN controller overview
- 19.3 AHB interface
- 19.4 BasicCAN mode
- 19.5 PeliCAN mode
- 19.5.1 PeliCAN register map
- 19.5.2 Mode register
- 19.5.3 Command register
- 19.5.4 Status register
- 19.5.5 Interrupt register
- 19.5.6 Interrupt enable register
- 19.5.7 Arbitration lost capture register
- 19.5.8 Error code capture register
- 19.5.9 Error warning limit register
- 19.5.10 RX error counter register (address 14)
- 19.5.11 TX error counter register (address 15)
- 19.5.12 Transmit buffer
- 19.5.13 Receive buffer
- 19.5.14 Acceptance filter
- 19.5.15 RX message counter
- 19.6 Common registers
- 19.7 Design considerations
- 19.8 Vendor and device identifiers
- 19.9 Implementation
- 19.10 Configuration options
- 19.11 Signal descriptions
- 19.12 Signal definitions and reset values
- 19.13 Timing
- 19.14 Library dependencies
- 19.15 Component declaration
- 20 CLKGEN - Clock generation
- 20.1 Overview
- 20.2 Technology specific clock generators
- 20.2.1 Overview
- 20.2.2 Generic technology
- 20.2.3 ProASIC
- 20.2.4 Actel Axcelerator
- 20.2.5 Actel ProASIC3
- 20.2.6 Altera Cyclone III
- 20.2.7 Altera Stratix 1/2
- 20.2.8 Altera Stratix 3
- 20.2.9 RHLIB18t
- 20.2.10 RHUMC
- 20.2.11 Xilinx Spartan 3/3e/6
- 20.2.12 Xilinx Virtex
- 20.2.13 Xilinx Virtex 2/4
- 20.2.14 Xilinx Virtex 5/6
- 20.2.15 eASIC90 (Nextreme)
- 20.2.16 eASIC45 (Nextreme2)
- 20.2.17 Actel Fusion
- 20.2.18 Altera Stratix 4
- 20.3 Configuration options
- 20.4 Signal descriptions
- 20.5 Signal definitions and reset values
- 20.6 Timing
- 20.7 Library dependencies
- 20.8 Instantiation
- 21 DDRSPA - 16-, 32- and 64-bit DDR266 Controller
- 21.1 Overview
- 21.2 Operation
- 21.2.1 General
- 21.2.2 Read cycles
- 21.2.3 Write cycles
- 21.2.4 Initialization
- 21.2.5 Configurable DDR SDRAM timing parameters
- 21.2.6 Extended timing fields
- 21.2.7 Refresh
- 21.2.8 Self Refresh
- 21.2.9 Clock Stop
- 21.2.10 Power-Down
- 21.2.11 Deep Power-Down
- 21.2.12 Status Read Register
- 21.2.13 Temperature-Compensated Self Refresh
- 21.2.14 Drive Strength
- 21.2.15 SDRAM commands
- 21.2.16 Clocking
- 21.2.17 Pads
- 21.2.18 Endianness
- 21.3 Registers
- 21.4 Vendor and device identifiers
- 21.5 Configuration options
- 21.6 Implementation
- 21.7 Signal descriptions
- 21.8 Library dependencies
- 21.9 Component declaration
- 21.10 Instantiation
- 22 DDR2SPA - 16-, 32- and 64-bit Single-Port Asynchronous DDR2 Controller
- 22.1 Overview
- 22.2 Operation
- 22.2.1 General
- 22.2.2 Data transfers
- 22.2.3 Initialization
- 22.2.4 Big memory support
- 22.2.5 Configurable DDR2 SDRAM timing parameters
- 22.2.6 Refresh
- 22.2.7 DDR2 SDRAM commands
- 22.2.8 Registered SDRAM
- 22.2.9 Clocking
- 22.2.10 Read data clock calibration on Xilinx Virtex
- 22.2.11 Read data clock calibration on Altera Stratix
- 22.2.12 Read data clock calibration on Xilinx Spartan-3
- 22.2.13 Pads
- 22.2.14 Endianness
- 22.3 Fault-tolerant operation (preliminary)
- 22.4 Registers
- 22.4.1 DDR2 SDRAM Configuration Register 1
- 22.4.2 DDR2 SDRAM Configuration Register 2
- 22.4.3 DDR2 SDRAM Configuration Register 3
- 22.4.4 DDR2 SDRAM Configuration Register 4
- 22.4.5 DDR2 SDRAM Configuration Register 5
- 22.4.6 DDR2 FT Configuration Register
- 22.4.7 DDR2 FT Diagnostic Address
- 22.4.8 DDR2 FT Diagnostic Checkbits
- 22.4.9 DDR2 FT Diagnostic Data
- 22.4.10 DDR2 FT Boundary Address Register
- 22.5 Vendor and device identifiers
- 22.6 Configuration options
- 22.7 Implementation
- 22.8 Signal descriptions
- 22.9 Library dependencies
- 22.10 Component declaration
- 22.11 Instantiation
- 23 DIV32 - Signed/unsigned 64/32 divider module
- 24 DSU3 - LEON3 Hardware Debug Support Unit
- 24.1 Overview
- 24.2 Operation
- 24.3 AHB trace buffer
- 24.4 Instruction trace buffer
- 24.5 DSU memory map
- 24.6 DSU registers
- 24.6.1 DSU control register
- 24.6.2 DSU Break and Single Step register
- 24.6.3 DSU Debug Mode Mask Register
- 24.6.4 DSU trap register
- 24.6.5 DSU time tag counter
- 24.6.6 DSU ASI register
- 24.6.7 AHB Trace buffer control register
- 24.6.8 AHB trace buffer index register
- 24.6.9 AHB trace buffer filter control register
- 24.6.10 AHB trace buffer filter mask register
- 24.6.11 AHB trace buffer breakpoint registers
- 24.6.12 Instruction trace control register 0
- 24.6.13 Instruction trace control register 1
- 24.7 Vendor and device identifiers
- 24.8 Implementation
- 24.9 Configuration options
- 24.10 Signal descriptions
- 24.11 Signal definitions and reset values
- 24.12 Timing
- 24.13 Library dependencies
- 24.14 Component declaration
- 24.15 Instantiation
- 25 DSU4 - LEON4 Hardware Debug Support Unit
- 25.1 Overview
- 25.2 Operation
- 25.3 AHB trace buffer
- 25.4 Instruction trace buffer
- 25.5 DSU memory map
- 25.6 DSU registers
- 25.6.1 DSU control register
- 25.6.2 DSU Break and Single Step register
- 25.6.3 DSU Debug Mode Mask Register
- 25.6.4 DSU trap register
- 25.6.5 DSU time tag counter
- 25.6.6 DSU ASI register
- 25.6.7 AHB Trace buffer control register
- 25.6.8 AHB trace buffer index register
- 25.6.9 AHB trace buffer filter control register
- 25.6.10 AHB trace buffer filter mask register
- 25.6.11 AHB trace buffer breakpoint registers
- 25.6.12 Instruction trace control register 0
- 25.6.13 Instruction trace control register 1
- 25.6.14 Instruction count register
- 25.6.15 AHB watchpoint control register
- 25.6.16 AHB watchpoint data and mask registers
- 25.7 Vendor and device identifiers
- 25.8 Implementation
- 25.9 Configuration options
- 25.10 Signal descriptions
- 25.11 Signal definitions and reset values
- 25.12 Timing
- 25.13 Library dependencies
- 25.14 Component declaration
- 25.15 Instantiation
- 26 FTAHBRAM - On-chip SRAM with EDAC and AHB interface
- 27 FTMCTRL - 8/16/32-bit Memory Controller with EDAC
- 27.1 Overview
- 27.2 PROM access
- 27.3 Memory mapped IO
- 27.4 SRAM access
- 27.5 8-bit and 16-bit PROM and SRAM access
- 27.6 8- and 16-bit I/O access
- 27.7 Burst cycles
- 27.8 SDRAM access
- 27.9 Memory EDAC
- 27.10 Bus Ready signalling
- 27.11 Access errors
- 27.12 Attaching an external DRAM controller
- 27.13 Output enable timing
- 27.14 Read strobe
- 27.15 Endianness
- 27.16 Registers
- 27.16.1 Memory configuration register 1 (MCFG1)
- 27.16.2 Memory configuration register 2 (MCFG2)
- 27.16.3 Memory configuration register 3 (MCFG3)
- 27.16.4 Memory configuration register 4 (MCFG4)
- 27.16.5 Memory configuration register 5 (MCFG5)
- 27.16.6 Memory configuration register 6 (MCFG6)
- 27.16.7 Memory configuration register 7 (MCFG7)
- 27.17 Vendor and device identifiers
- 27.18 Implementation
- 27.19 Configuration options
- 27.20 Scan support
- 27.21 Signal descriptions
- 27.22 Signal definitions and reset values
- 27.23 Timing
- 27.24 Library dependencies
- 27.25 Instantiation
- 28 FTSDCTRL - 32/64-bit PC133 SDRAM Controller with EDAC
- 28.1 Overview
- 28.2 Operation
- 28.2.1 General
- 28.2.2 Initialization
- 28.2.3 Configurable SDRAM timing parameters
- 28.2.4 Refresh
- 28.2.5 Self Refresh
- 28.2.6 Power-Down
- 28.2.7 Deep Power-Down
- 28.2.8 Temperature-Compensated Self Refresh
- 28.2.9 Drive Strength
- 28.2.10 SDRAM commands
- 28.2.11 Read cycles
- 28.2.12 Write cycles
- 28.2.13 Address bus connection
- 28.2.14 Data bus
- 28.2.15 EDAC
- 28.2.16 Clocking
- 28.2.17 Endianness
- 28.3 Registers
- 28.4 Vendor and device identifiers
- 28.5 Implementation
- 28.6 Configuration options
- 28.7 Signal descriptions
- 28.8 Signal definitions and reset values
- 28.9 Timing
- 28.10 Library dependencies
- 28.11 Instantiation
- 28.12 Constraints
- 29 FTSRCTRL - Fault Tolerant 32-bit PROM/SRAM/IO Controller
- 29.1 Overview
- 29.2 Operation
- 29.3 PROM/SRAM/IO waveforms
- 29.4 Endianness
- 29.5 Registers
- 29.6 Vendor and device identifiers
- 29.7 Implementation
- 29.8 Configuration options
- 29.9 Signal descriptions
- 29.10 Signal definitions and reset values
- 29.11 Timing
- 29.12 Library dependencies
- 29.13 Component declaration
- 29.14 Instantiation
- 30 FTSRCTRL8 - 8-bit SRAM/16-bit IO Memory Controller with EDAC
- 30.1 Overview
- 30.2 Operation
- 30.3 SRAM/IO waveforms
- 30.4 Endianness
- 30.5 Registers
- 30.6 Vendor and device identifiers
- 30.7 Implementation
- 30.8 Configuration options
- 30.9 Signal descriptions
- 30.10 Signal definitions and reset values
- 30.11 Timing
- 30.12 Library dependencies
- 30.13 Component declaration
- 30.14 Instantiation
- 31 GPTIMER - General Purpose Timer Unit
- 32 GR1553B - MIL-STD-1553B / AS15531 Interface
- 32.1 Overview
- 32.2 Electrical interface
- 32.3 Operation
- 32.4 Bus Controller Operation
- 32.5 Remote Terminal Operation
- 32.6 Bus Monitor Operation
- 32.7 Clocking
- 32.8 Registers
- 32.8.1 IRQ Register
- 32.8.2 IRQ Enable Register
- 32.8.3 Hardware Configuration Register
- 32.8.4 BC Status and Config Register
- 32.8.5 BC Action Register
- 32.8.6 BC Tranfer List Next Pointer Register
- 32.8.7 BC Asynchronous List Next Pointer Register
- 32.8.8 BC Timer Register
- 32.8.9 BC Timer Wake-up Register
- 32.8.10 BC Transfer-triggered IRQ Ring Position Register
- 32.8.11 BC per-RT Bus Swap Register
- 32.8.12 BC Transfer List Current Slot Pointer
- 32.8.13 BC Asynchronous List Current Slot Pointer
- 32.8.14 RT Status Register
- 32.8.15 RT Config Register
- 32.8.16 RT Bus Status Register
- 32.8.17 RT Status Words Register
- 32.8.18 RT Sync Register
- 32.8.19 Sub Address Table Base Address Register
- 32.8.20 RT Mode Code Control Register
- 32.8.21 RT Time Tag Control Register
- 32.8.22 RT Event Log Mask Register
- 32.8.23 RT Event Log Position Register
- 32.8.24 RT Event Log Interrupt Position Register
- 32.8.25 BM Status Register
- 32.8.26 BM Control Register
- 32.8.27 BMRT Address Filter Register
- 32.8.28 BMRT Sub address Filter Register
- 32.8.29 BMRT Mode Code Filter Register
- 32.8.30 BMLog Buffer Start
- 32.8.31 BMLog Buffer End
- 32.8.32 BMLog Buffer Position
- 32.8.33 BM Time Tag Control Register
- 32.9 Vendor and device identifiers
- 32.10 Implementation
- 32.11 Configuration options
- 32.12 Signal descriptions
- 32.13 Signal definitions and reset values
- 32.14 Timing
- 32.15 Library dependencies
- 32.16 Instantiation
- 32.17 Constraints
- 32.18 Note: AHB Interface Compatibility
- 32.19 Note: AHB Latency and throughput requirements
- 32.20 Note: BC transfer timing
- 32.21 Note: Time synchronization
- 32.21.1 Introduction
- 32.21.2 Hardware features: BC features
- 32.21.3 Hardware features: RT features
- 32.21.4 Hardware features: Internal timers
- 32.21.5 Synchronization schemes
- 32.21.6 Synchronization schemes: Overview
- 32.21.7 Synchronization schemes: BC without external time base
- 32.21.8 Synchronization schemes: BC with external time base
- 32.21.9 Synchronization schemes: RT without external time base
- 32.21.10 Synchronization schemes: RT with external time base(s)
- 32.21.11 Accuracy
- 32.21.12 Accuracy: Propagation delays
- 32.21.13 Accuracy: Clock drift
- 33 GRTIMER - General Purpose Timer Unit
- 34 GRACECTRL - AMBA System ACE Interface Controller
- 35 GRAES - Advanced Encryption Standard
- 36 GRAES_DMA - Advanced Encryption Standard with DMA
- 36.1 Overview
- 36.2 Operation
- 36.3 Background
- 36.4 Characteristics
- 36.5 Endianness
- 36.6 Registers
- 36.7 Descriptor Processing
- 36.8 Error Handling
- 36.9 Aborting Operation
- 36.10 Vendor and device identifiers
- 36.11 Implementation
- 36.12 Configuration options
- 36.13 Signal descriptions
- 36.14 Library dependencies
- 36.15 Instantiation
- 37 GRCAN - CAN 2.0 Controller with DMA
- 37.1 Overview
- 37.2 Interface
- 37.3 Protocol
- 37.4 Status and monitoring
- 37.5 Transmission
- 37.6 Reception
- 37.7 Global reset and enable
- 37.8 Interrupt
- 37.9 Endianness
- 37.10 Registers
- 37.10.1 Configuration Register
- 37.10.2 Status Register
- 37.10.3 Control Register
- 37.10.4 SYNC Code Filter Register
- 37.10.5 SYNC Mask Filter Register
- 37.10.6 Transmit Channel Control Register
- 37.10.7 Transmit Channel Address Register
- 37.10.8 Transmit Channel Size Register
- 37.10.9 Transmit Channel Write Register
- 37.10.10 Transmit Channel Read Register
- 37.10.11 Transmit Channel Interrupt Register
- 37.10.12 Receive Channel Control Register
- 37.10.13 Receive Channel Address Register
- 37.10.14 Receive Channel Size Register
- 37.10.15 Receive Channel Write Register
- 37.10.16 Receive Channel Read Register
- 37.10.17 Receive Channel Interrupt Register
- 37.10.18 Receive Channel Mask Register
- 37.10.19 Receive Channel Code Register
- 37.10.20 Interrupt registers
- 37.11 Memory mapping
- 37.12 Vendor and device identifiers
- 37.13 Implementation
- 37.14 Configuration options
- 37.15 Signal descriptions
- 37.16 Signal definitions and reset values
- 37.17 Timing
- 37.18 Library dependencies
- 37.19 Instantiation
- 38 GRCLKGATE / GRCLKGATE2X - Clock gating unit
- 39 GRDMAC - DMA Controller with internal AHB/APB bridge
- 39.1 Overview
- 39.2 Configuration
- 39.3 Operation
- 39.4 AHB transfers
- 39.5 Data realignment buffer
- 39.6 Interrupts
- 39.7 Wide Data Bus support
- 39.8 Errors
- 39.9 Internal Buffer Readout Interface
- 39.10 Endianness
- 39.11 Registers
- 39.11.1 Control Register
- 39.11.2 Status Register
- 39.11.3 Interrupt Mask
- 39.11.4 Error Register
- 39.11.5 Channel Vector Pointer
- 39.11.6 Timer Reset Value Register
- 39.11.7 Capability Register
- 39.11.8 Interrupt Flag Register
- 39.11.9 M2B Descriptor Address Register*
- 39.11.10 M2B Descriptor Control Register*
- 39.11.11 M2B Descriptor Status Register*
- 39.11.12 B2M Descriptor Address Register*
- 39.11.13 B2M Descriptor Control Register*
- 39.11.14 B2M Descriptor Status Register*
- 39.11.15 Internal Buffer Pointers Register
- 39.12 Example DMA channel set-up
- 39.13 Vendor and device identifier
- 39.14 Implementation
- 39.15 Configuration options
- 39.16 Signal descriptions
- 39.17 Library dependencies
- 39.18 Instantiation
- 40 GRECC - Elliptic Curve Cryptography
- 41 GRETH - Ethernet Media Access Controller (MAC) with EDCL support
- 41.1 Overview
- 41.2 Operation
- 41.3 Tx DMA interface
- 41.4 Rx DMA interface
- 41.5 MDIO Interface
- 41.6 Ethernet Debug Communication Link (EDCL)
- 41.7 Media Independent Interfaces
- 41.8 Registers
- 41.8.1 Control Register
- 41.8.2 Status Register
- 41.8.3 MAC Address MSB
- 41.8.4 MAC Address LSB
- 41.8.5 MDIO ctrl/status Register
- 41.8.6 Transmitter Descriptor Table Base Address Register
- 41.8.7 Receiver Descriptor Table Base Address Register
- 41.8.8 EDCL IP Register
- 41.8.9 Hash Table Msb Register
- 41.8.10 Hash Table Lsb Register
- 41.8.11 EDCL MAC Address MSB
- 41.8.12 EDCL MAC Address LSB
- 41.9 Vendor and device identifiers
- 41.10 Implementation
- 41.11 Configuration options
- 41.12 Signal descriptions
- 41.13 Library dependencies
- 41.14 Instantiation
- 42 GRETH_GBIT - Gigabit Ethernet Media Access Controller (MAC) w. EDCL
- 42.1 Overview
- 42.2 Operation
- 42.3 Tx DMA interface
- 42.4 Rx DMA interface
- 42.5 MDIO Interface
- 42.6 Ethernet Debug Communication Link (EDCL)
- 42.7 Media Independent Interfaces
- 42.8 Registers
- 42.8.1 Control register
- 42.8.2 Status Register
- 42.8.3 Mac Address MSB
- 42.8.4 Mac Address LSB
- 42.8.5 MDIO control/status Register
- 42.8.6 Transmitter Descripter Table Base Address Register
- 42.8.7 Receiver Descriptor Table Base Address Register
- 42.8.8 IP Register
- 42.8.9 Hash Table MSB Register
- 42.8.10 Hash Table LSB Register
- 42.8.11 MAC Address MSB
- 42.8.12 Mac Address LSB
- 42.9 Vendor and device identifier
- 42.10 Implementation
- 42.11 Configuration options
- 42.12 Signal descriptions
- 42.13 Library dependencies
- 42.14 Instantiation
- 43 GRFIFO - FIFO Interface
- 43.1 Overview
- 43.2 Interface
- 43.3 Waveforms
- 43.4 Transmission
- 43.5 Reception
- 43.6 Operation
- 43.7 Registers
- 43.7.1 Configuration Register [FifoCONF]
- 43.7.2 Status Register [FifoSTAT]
- 43.7.3 Control Register [FifoCTRL]
- 43.7.4 Transmit Channel Control Register [FifoTxCTRL]
- 43.7.5 Transmit Channel Status Register [FifoTxSTAT]
- 43.7.6 Transmit Channel Address Register [FifoTxADDR]
- 43.7.7 Transmit Channel Size Register [FifoTxSIZE]
- 43.7.8 Transmit Channel Write Register [FifoTxWR]
- 43.7.9 Transmit Channel Read Register [FifoTxRD]
- 43.7.10 Transmit Channel Interrupt Register [FifoTxIRQ]
- 43.7.11 Receive Channel Control Register [FifoRxCTRL]
- 43.7.12 Receive Channel Status Register [FifoRxSTAT]
- 43.7.13 Receive Channel Address Register [FifoRxADDR]
- 43.7.14 Receive Channel Size Register [FifoRxSIZE]
- 43.7.15 Receive Channel Write Register [FifoRxWR]
- 43.7.16 Receive Channel Read Register [FifoRxRD]
- 43.7.17 Receive Channel Interrupt Register [FifoRxIRQ]
- 43.7.18 Data Input Register [FifoDIN]
- 43.7.19 Data Output Register [FifoDOUT]
- 43.7.20 Data Register [FifoDDIR]
- 43.7.21 Interrupt registers
- 43.8 Vendor and device identifiers
- 43.9 Implementation
- 43.10 Configuration options
- 43.11 Signal descriptions
- 43.12 Signal definitions and reset values
- 43.13 Timing
- 43.14 Library dependencies
- 43.15 Instantiation
- 44 GRADCDAC - ADC / DAC Interface
- 44.1 Overview
- 44.2 Operation
- 44.3 Operation
- 44.4 Registers
- 44.4.1 Configuration Register [ADCONF]
- 44.4.2 Status Register [ADSTAT]
- 44.4.3 ADC Data Input Register [ADIN]
- 44.4.4 DAC Data Output Register [ADOUT]
- 44.4.5 Address Input Register [ADAIN]
- 44.4.6 Address Output Register [ADAOUT]
- 44.4.7 Address Direction Register [ADADIR]
- 44.4.8 Data Input Register [ADDIN]
- 44.4.9 1Data Output Register [AD DOUT]
- 44.4.10 Data Register [ADDDIR]
- 44.5 Vendor and device identifiers
- 44.6 Implementation
- 44.7 Configuration options
- 44.8 Signal descriptions
- 44.9 Signal definitions and reset values
- 44.10 Timing
- 44.11 Library dependencies
- 44.12 Instantiation
- 45 GRFPU - High-performance IEEE-754 Floating-point unit
- 46 GRFPC - GRFPU Control Unit
- 47 GRFPU Lite - IEEE-754 Floating-Point Unit
- 48 GRLFPC - GRFPU Lite Floating-point unit Controller
- 49 GRGPIO - General Purpose I/O Port
- 49.1 Overview
- 49.2 Operation
- 49.3 Registers
- 49.3.1 I/O Port Data Register
- 49.3.2 I/O Port Output Register
- 49.3.3 I/O Port Direction Register
- 49.3.4 Interrupt Mask Register
- 49.3.5 Interrupt Polarity Register
- 49.3.6 Interrupt Edge Register
- 49.3.7 Bypass Register
- 49.3.8 Capability Register
- 49.3.9 Interrupt Map Register n
- 49.3.10 Interrupt Available Register
- 49.3.11 Interrupt Flag Register
- 49.3.12 Input Enable Register
- 49.3.13 Pulse Register
- 49.3.14 Logical-OR/AND/XOR Register
- 49.4 Vendor and device identifiers
- 49.5 Implementation
- 49.6 Configuration options
- 49.7 Signal descriptions
- 49.8 Signal definitions and reset values
- 49.9 Timing
- 49.10 Library dependencies
- 49.11 Component declaration
- 49.12 Instantiation
- 50 GRGPREG - General Purpose Register
- 51 GRIOMMU - AHB/AHB bridge with access protection and address translation
- 51.1 Overview
- 51.2 Bridge operation
- 51.2.1 General
- 51.2.2 AHB read transfers
- 51.2.3 AHB write transfers
- 51.2.4 Deadlock conditions
- 51.2.5 Locked transfers
- 51.2.6 Read and write combining
- 51.2.7 Burst operation
- 51.2.8 Transaction ordering, starvation and AMBA arbitration schemes
- 51.2.9 First-come, first-served ordering
- 51.2.10 Bus arbiter ordering
- 51.2.11 AMBA SPLIT support
- 51.2.12 Core latency
- 51.2.13 Endianness
- 51.3 General access protection and address translation
- 51.4 Access Protection Vector
- 51.5 IO Memory Management Unit (IOMMU) functionality
- 51.6 Fault-tolerance
- 51.7 Statistics
- 51.8 Multi-bus bridge
- 51.9 ASMP support
- 51.10 Registers
- 51.10.1 Capability Register 0
- 51.10.2 Capability Register 1
- 51.10.3 Capability Register 2
- 51.10.4 Control Register
- 51.10.5 TLB/cache Flush Register
- 51.10.6 Status Register
- 51.10.7 Interrupt Mask Register
- 51.10.8 Failing Access Register
- 51.10.9 Master Configuration Register(s)
- 51.10.10 Group Control Register(s)
- 51.10.11 Diagnostic Cache Access Register
- 51.10.12 Diagnostic Cache Access Data Register 0 - 7
- 51.10.13 Diagnostic Cache Access Tag Register
- 51.10.14 Data RAM Error Injection Register
- 51.10.15 Tag RAM Error Injection Register
- 51.10.16 ASMP Access Control Register
- 51.11 Vendor and device identifiers
- 51.12 Implementation
- 51.13 Configuration options
- 51.14 Signal descriptions
- 51.15 Library dependencies
- 51.16 Instantiation
- 52 GRPCI2 - 32-bit PCI(Initiator/Target) / AHB(Master/Slave) bridge
- 52.1 Overview
- 52.2 Configuration
- 52.3 Operation
- 52.4 PCI Initiator interface
- 52.5 PCI Target interface
- 52.6 DMA Controller
- 52.7 PCI trace buffer
- 52.8 Interrupts
- 52.9 Registers
- 52.9.1 Control Register
- 52.9.2 Status and Capability Register
- 52.9.3 Master Prefetch Burst Limit
- 52.9.4 AHB to PCI Mapping for PCI IO
- 52.9.5 DMA Control and Status Register
- 52.9.6 DMA Descriptor Base Address (/ Active Descriptor) Register
- 52.9.7 DMA Channel Active Register
- 52.9.8 PCI BAR to AHB Address Mapping Register
- 52.9.9 AHB Master to PCI Memory Address Mapping Register
- 52.9.10 PCI Trace Control and Status Register
- 52.9.11 PCI Trace Counter and Mode Register
- 52.9.12 PCI Trace AD Pattern Register
- 52.9.13 PCI Trace AD Mask Register
- 52.9.14 PCI Trace Ctrl Signal Pattern Register
- 52.9.15 PCI Trace Ctrl Signal Mask Register
- 52.9.16 PCI Trace PCI AD State Register
- 52.9.17 PCI Trace PCI Ctrl Signal State Register
- 52.10 Vendor and device identifiers
- 52.11 Implementation
- 52.12 Configuration options
- 52.13 Signal descriptions
- 52.14 Library dependencies
- 52.15 Instantiation
- 53 GRPULSE - General Purpose Input Output
- 54 GRPWM - Pulse Width Modulation Generator
- 54.1 Overview
- 54.2 Operation
- 54.3 Registers
- 54.3.1 Core Control Register
- 54.3.2 Scaler Reload Register
- 54.3.3 Interrupt Pending Register
- 54.3.4 Capability Register 1
- 54.3.5 Capability Register 2
- 54.3.6 Waveform Configuration Register
- 54.3.7 PWM Period Register
- 54.3.8 PWM Compare Register
- 54.3.9 PWM Dead Band Compare Register
- 54.3.10 PWM Control Register
- 54.3.11 Waveform RAM, Word X
- 54.4 Vendor and device identifier
- 54.5 Implementation
- 54.6 Configuration options
- 54.7 Signal descriptions
- 54.8 Signal definitions and reset values
- 54.9 Library dependencies
- 54.10 Timing
- 54.11 Instantiation
- 55 GRRT - MIL-STD-1553B / AS15531 Remote Terminal Back-End
- 56 GRSPW - SpaceWire codec with AHB host Interface and RMAP target
- 56.1 Overview
- 56.2 Operation
- 56.3 Link interface
- 56.4 Receiver DMA engine
- 56.4.1 Basic functionality
- 56.4.2 Setting up the core for reception
- 56.4.3 Setting up the descriptor table address
- 56.4.4 Enabling descriptors
- 56.4.5 Setting up the DMA control register
- 56.4.6 The effect to the control bits during reception
- 56.4.7 Address recognition and packet handling
- 56.4.8 Status bits
- 56.4.9 Error handling
- 56.4.10 Promiscuous mode
- 56.5 Transmitter DMA engine
- 56.6 RMAP
- 56.7 AMBA interface
- 56.8 Implementation
- 56.9 Registers
- 56.9.1 Control Register
- 56.9.2 Status Register
- 56.9.3 Node Address Register
- 56.9.4 Clock Divisor Register
- 56.9.5 Destination Key
- 56.9.6 Time Register
- 56.9.7 Timer and Disconnect Register
- 56.9.8 DMA Control Register
- 56.9.9 RX Maximum Length Register
- 56.9.10 Transmitter Descriptor Table Address Register
- 56.9.11 Receiver Descriptor Table Address Register
- 56.10 Vendor and device identifiers
- 56.11 Configuration options
- 56.12 Signal descriptions
- 56.13 Signal definitions and reset values
- 56.14 Timing
- 56.15 Library dependencies
- 56.16 Instantiation
- 56.17 API
- 56.18 Appendix A Clarifications of the GRSPW implementation of the standard
- 57 GRSPW2 - SpaceWire codec with AHB host Interface and RMAP target
- 57.1 Overview
- 57.2 Operation
- 57.3 Link interface
- 57.4 Time-code distribution
- 57.5 Interrupt distribution
- 57.6 Receiver DMA channels
- 57.6.1 Address comparison and channel selection
- 57.6.2 Basic functionality of a channel
- 57.6.3 Setting up the core for reception
- 57.6.4 Setting up the descriptor table address
- 57.6.5 Enabling descriptors
- 57.6.6 Setting up the DMA control register
- 57.6.7 The effect to the control bits during reception
- 57.6.8 Status bits
- 57.6.9 Error handling
- 57.6.10 Promiscuous mode
- 57.7 Transmitter DMA channels
- 57.8 RMAP
- 57.9 AMBA interface
- 57.10 SpaceWire Plug-and-Play
- 57.11 Implementation
- 57.12 Registers
- 57.12.1 Control Register
- 57.12.2 Status Register
- 57.12.3 Default Address Register
- 57.12.4 Clock Divisor Register
- 57.12.5 Destination Key Register
- 57.12.6 Time-code Register
- 57.12.7 DMA Control/Status
- 57.12.8 DMA RX Maximum Length
- 57.12.9 DMA Transmit Descriptor Table Address
- 57.12.10 DMA Receive Descriptor Table Address
- 57.12.11 DMA Address
- 57.12.12 Interrupt Distribution Control
- 57.12.13 Interrupt Receive
- 57.12.14 Interrupt-acknowledge-code Receive
- 57.12.15 Interrupt Timeout
- 57.12.16 Interrupt Timeout Extended
- 57.12.17 Interrupt Tick-out Mask
- 57.12.18 Interrupt-code Auto Acknowledge Mask
- 57.12.19 Interrupt Distribution Configuration
- 57.12.20 Interrupt Distribution ISR
- 57.12.21 Interrupt Distribution ISR Extended
- 57.12.22 Interrupt Distribution Prescaler Reload
- 57.12.23 Interrupt Distribution ISR Timer Reload
- 57.12.24 Interrupt Distribution INT/ACK Timer Reload
- 57.12.25 Interrupt Distribution Change Timer Reload
- 57.12.26 SpaceWire Plug-and-Play - Device Vendor and Product ID
- 57.12.27 SpaceWire Plug-and-Play - Link Information
- 57.12.28 SpaceWire Plug-and-Play - Owner Address 0
- 57.12.29 SpaceWire Plug-and-Play - Owner Address 1
- 57.12.30 SpaceWire Plug-and-Play - Owner Address 2
- 57.12.31 SpaceWire Plug-and-Play - Device ID
- 57.12.32 SpaceWire Plug-and-Play - Unit Vendor and Product ID
- 57.12.33 SpaceWire Plug-and-Play - Unit Serial Number
- 57.13 Vendor and device identifiers
- 57.14 Configuration options
- 57.15 Signal descriptions
- 57.16 Signal definitions and reset values
- 57.17 Timing
- 57.18 Library dependencies
- 57.19 Instantiation
- 57.20 Constraints
- 57.21 API
- 58 GRSPW2_GEN - GRSPW2 wrapper with Std_Logic interface
- 59 GRSPW2_PHY - GRSPW2 Receiver Physical Interface
- 59.1 Overview
- 59.2 Operation
- 59.2.1 Self-clocking (input_type = 0)
- 59.2.2 Cobham transceiver (input_type = 1)
- 59.2.3 SDR sampling (input_type = 2)
- 59.2.4 DDR sampling (input_type = 3)
- 59.2.5 DDR sampling with internal pad (input_type = 4)
- 59.2.6 Self-clocking with external clock recovery (input_type = 5)
- 59.2.7 Self-clocking with external clock recovery and DDR register (input_type = 6)
- 59.3 Configuration options
- 59.4 Scan support
- 59.5 Signal descriptions
- 59.6 Library dependencies
- 59.7 Instantiation
- 60 GRSPW_CODEC - SpaceWire encoder-decoder
- 61 GRSPW_CODEC_GEN - GRSPW_CODEC wrapper with Std_Logic interface
- 62 GRSPWROUTER - SpaceWire router
- 62.1 Overview
- 62.2 Operation
- 62.2.1 Endianness
- 62.2.2 Port numbering
- 62.2.3 Routing table
- 62.2.4 Output port arbitration
- 62.2.5 Group adaptive routing
- 62.2.6 Packet distribution
- 62.2.7 Port disable
- 62.2.8 Timers
- 62.2.9 On-chip memories
- 62.2.10 Plug and play support
- 62.2.11 System time-distribution
- 62.2.12 Invalid address error
- 62.2.13 Packet counters
- 62.2.14 Global configuration features
- 62.3 SpaceWire ports
- 62.4 FIFO ports
- 62.5 AMBA ports
- 62.6 Configuration port
- 62.7 Configuration options
- 62.8 Registers
- 62.9 Vendor and device identifiers
- 62.10 Signal descriptions
- 62.11 Signal definitions and reset values
- 62.12 Timing
- 62.13 Instantiation
- 63 SPWTDP - SpaceWire - Time Distribution Protocol
- 63.1 Overview
- 63.2 Protocol
- 63.3 Functionality
- 63.3.1 CCSDS Unsegmented Code: Preamble Field (P-Field)
- 63.3.2 CCSDS Unsegmented Code: Time Field (T-Field)
- 63.3.3 Time generation
- 63.3.4 Initiator
- 63.3.5 Target
- 63.3.6 Configuring initiator and target
- 63.3.7 SpaceWire Time-Code
- 63.3.8 Initialization and synchronisation of target through RMAP
- 63.3.9 Latency measurement using Time-Stamps
- 63.3.10 Mitigation of jitter and drift
- 63.3.11 External Datation
- 63.3.12 Pulses
- 63.3.13 Set Elapsed Time using external input
- 63.3.14 Multiple Port
- 63.3.15 Synchronisation of target using SpaceWire Time-Codes
- 63.4 Data formats
- 63.5 Reference documents
- 63.6 Registers
- 63.6.1 Configuration 0
- 63.6.2 Configuration 1
- 63.6.3 Configuration 2
- 63.6.4 Configuration 3
- 63.6.5 Status Register 0
- 63.6.6 Status Register 1
- 63.6.7 Control
- 63.6.8 Command Elapsed Time 0
- 63.6.9 Command Elapsed Time 1
- 63.6.10 Command Elapsed Time 2
- 63.6.11 Command Elapsed Time 3
- 63.6.12 Command Elapsed Time 4
- 63.6.13 Datation Preamble Field
- 63.6.14 Datation Elapsed Time 0
- 63.6.15 Datation Elapsed Time 1
- 63.6.16 Datation Elapsed Time 2
- 63.6.17 Datation Elapsed Time 3
- 63.6.18 Datation Elapsed Time 4
- 63.6.19 Time-Stamp Preamble Field Rx
- 63.6.20 Time Stamp Elapsed Time 0 Rx
- 63.6.21 Time Stamp Elapsed Time 1 Rx
- 63.6.22 Time Stamp Elapsed Time 2 Rx
- 63.6.23 Time Stamp Elapsed Time 3 Rx
- 63.6.24 Time Stamp Elapsed Time 4 Rx
- 63.6.25 Time-Stamp SpaceWire Time-Code and Preamble Field Tx
- 63.6.26 Time Stamp Elapsed Time 0 Tx
- 63.6.27 Time Stamp Elapsed Time 1 Tx
- 63.6.28 Time Stamp Elapsed Time 2 Tx
- 63.6.29 Time Stamp Elapsed Time 3 Tx
- 63.6.30 Time Stamp Elapsed Time 4 Tx
- 63.6.31 Latency Preamble Field
- 63.6.32 Latency Elapsed Time 0
- 63.6.33 Latency Elapsed Time 1
- 63.6.34 Latency Elapsed Time 2
- 63.6.35 Latency Elapsed Time 3
- 63.6.36 Latency Elapsed Time 4
- 63.6.37 Interrupt Enable
- 63.6.38 Interrupt Status
- 63.6.39 Delay Count
- 63.6.40 Disable Sync
- 63.6.41 External Datation 0 Mask
- 63.6.42 External Datation 0 Preamble Field
- 63.6.43 External Datation 0 Elapsed Time 0
- 63.6.44 External Datation 0 Elapsed Time 1
- 63.6.45 External Datation 0 Elapsed Time 2
- 63.6.46 External Datation 0 Elapsed Time 3
- 63.6.47 External Datation 0 Elapsed Time 4
- 63.6.48 Pulse Definition Register 0 to 7
- 63.7 Vendor and device identifiers
- 63.8 Implementation
- 63.9 Configuration options
- 63.10 Signal descriptions
- 63.11 Signal definitions and reset values
- 63.12 Timing
- 63.13 Library dependencies
- 63.14 Instantiation
- 64 GRSPFI_CODEC - SpaceFibre encoder/decoder
- 65 GRSRIO - Serial RapidIO endpoint with AHB or AXI4 bus master interface
- 66 GRSYSMON - AMBA Wrapper for Xilinx System Monitor
- 67 GRUSBDC - USB Device controller
- 67.1 Overview
- 67.2 Operation
- 67.3 DMA operation
- 67.4 Slave data transfer interface operation
- 67.5 Endpoints
- 67.6 Device implementation example in master mode
- 67.7 Device implementation example in slave mode
- 67.8 Registers
- 67.8.1 OUT Endpoint Control Register
- 67.8.2 OUT Slave Control Register
- 67.8.3 OUT Slave Buffer Read Register
- 67.8.4 OUT DMA Control Register
- 67.8.5 OUT Descriptor Address Register
- 67.8.6 OUT Endpoint Status Register
- 67.8.7 IN Endpoint Control Register
- 67.8.8 IN Slave Control Register
- 67.8.9 IN Slave Buffer read/write Register
- 67.8.10 IN DMA Control Register
- 67.8.11 IN Descriptor Address Register
- 67.8.12 IN Endpoint Status Register
- 67.8.13 CTRL Register
- 67.8.14 Status Register
- 67.9 Vendor and device identifier
- 67.10 Implementation
- 67.11 Configuration options
- 67.12 Signal descriptions
- 67.13 Library dependencies
- 67.14 Instantiation
- 68 GRUSB_DCL - USB Debug Communication Link
- 69 GRUSBHC - USB 2.0 Host Controller
- 69.1 Overview
- 69.2 Operation
- 69.3 Port routing
- 69.4 DMA operations
- 69.5 Endianness
- 69.6 Transceiver support
- 69.7 PCI configuration registers and legacy support
- 69.8 Registers
- 69.9 Vendor and device identifiers
- 69.10 Implementation
- 69.11 Configuration options
- 69.12 Signal descriptions
- 69.13 Signal definitions and reset values
- 69.14 Library dependencies
- 69.15 Instantiation
- 70 GRVERSION - Version and Revision information register
- 71 I2C2AHB - I2C to AHB bridge
- 72 I2CMST - I2C-master
- 73 I2CSLV - I2C slave
- 74 IRQMP - Multiprocessor Interrupt Controller
- 74.1 Overview
- 74.2 Operation
- 74.3 Registers
- 74.3.1 Interrupt Level Register
- 74.3.2 Interrupt Pending Register
- 74.3.3 Interrupt Force Register (NCPU = 0)
- 74.3.4 Interrupt Clear Register
- 74.3.5 Multiprocessor Status Register
- 74.3.6 Broadcast Register (NCPU > 0)
- 74.3.7 Error Mode Status Register
- 74.3.8 Processor Interrupt Mask Register
- 74.3.9 Processor Interrupt Force Register (NCPU > 0)
- 74.3.10 Extended Interrupt Acknowledge Register
- 74.3.11 Processor N Boot Address Register
- 74.3.12 Interrupt Map Register N
- 74.4 Vendor and device identifiers
- 74.5 Implementation
- 74.6 Configuration options
- 74.7 Signal descriptions
- 74.8 Library dependencies
- 74.9 Instantiation
- 75 IRQ(A)MP - Multiprocessor Interrupt Controller with extended ASMP support
- 75.1 Overview
- 75.2 Operation
- 75.2.1 Support for Asymmetric Multiprocessing
- 75.2.2 Interrupt prioritization
- 75.2.3 Extended interrupts
- 75.2.4 Processor status monitoring
- 75.2.5 Interrupt broadcasting
- 75.2.6 Interrupt timestamping description
- 75.2.7 Interrupt timestamping usage guidelines
- 75.2.8 Watchdog
- 75.2.9 Interrupt (re)map functionality
- 75.2.10 Dynamic processor reset start address
- 75.3 Registers
- 75.3.1 Interrupt Level Register
- 75.3.2 Interrupt Pending Register
- 75.3.3 Interrupt Force Register (NCPU = 0)
- 75.3.4 Interrupt Clear Register
- 75.3.5 Multiprocessor Status Register
- 75.3.6 Broadcast Register (NCPU > 0)
- 75.3.7 Error Mode Status Register
- 75.3.8 Watchdog Control Register (NCPU > 0)
- 75.3.9 Asymmetric Multiprocessing Control Register
- 75.3.10 Interrupt Controller Select Register for Processors 0 - 7 (NCTRL > 0)
- 75.3.11 Interrupt Controller Select Register for Processors 8 - 15 (NCTRL > 0)
- 75.3.12 Processor Interrupt Mask Register
- 75.3.13 Processor Interrupt Force Register (NCPU > 0)
- 75.3.14 Extended Interrupt Acknowledge Register
- 75.3.15 Interrupt Timestamp Counter Register
- 75.3.16 Timestamp N Control Register
- 75.3.17 Interrupt Assertion Timestamp Register
- 75.3.18 Interrupt Acknowledge Timestamp Register
- 75.3.19 Processor N Boot Address Register
- 75.3.20 Interrupt Map Register N
- 75.4 Vendor and device identifiers
- 75.5 Implementation
- 75.6 Configuration options
- 75.7 Signal descriptions
- 75.8 Library dependencies
- 75.9 Instantiation
- 76 L2C - Level 2 Cache controller
- 76.1 Overview
- 76.2 Configuration
- 76.3 Operation
- 76.4 Registers
- 76.4.1 Control Register
- 76.4.2 Status Register
- 76.4.3 Flush (Memory Address) Register
- 76.4.4 Flush (Set, Index) Register
- 76.4.5 Access Counter Register
- 76.4.6 Hit Counter Register
- 76.4.7 Front-side Bus Cycle Counter Register
- 76.4.8 Front-side Bus Usage Counter Register
- 76.4.9 Error Status/Control
- 76.4.10 Error Address Register
- 76.4.11 Tag-check-bit Register
- 76.4.12 Data-check-bit Register
- 76.4.13 Scrub Control/Status Register
- 76.4.14 Scrub Delay Register
- 76.4.15 Error Injection Register
- 76.4.16 Access control register
- 76.4.17 Priming start register 0
- 76.4.18 Priming stop register 0
- 76.4.19 Priming start register 1
- 76.4.20 Priming stop register 1
- 76.4.21 Error Handling / Injection configuration
- 76.4.22 Memory Type Range Register
- 76.5 Core versions
- 76.6 Vendor and device identifiers
- 76.7 Implementation
- 76.8 Configuration options
- 76.9 Signal descriptions
- 76.10 Library dependencies
- 76.11 Instantiation
- 77 L3STAT - LEON3 Statistics Unit
- 78 L4STAT - LEON4 Statistics Unit
- 79 LEON_DSU_STAT_BASE - LEON3/4 SUBSYSTEM
- 80 LEON3/FT - High-performance SPARC V8 32-bit Processor
- 80.1 Overview
- 80.2 LEON3 integer unit
- 80.2.1 Overview
- 80.2.2 Instruction pipeline
- 80.2.3 SPARC Implementor’s ID
- 80.2.4 Divide instructions
- 80.2.5 Multiply instructions
- 80.2.6 Multiply and accumulate instructions
- 80.2.7 Compare and Swap instruction (CASA)
- 80.2.8 Branch prediction
- 80.2.9 Register file data protection
- 80.2.10 Hardware breakpoints
- 80.2.11 Instruction trace buffer
- 80.2.12 Processor configuration register
- 80.2.13 Exceptions
- 80.2.14 Single vector trapping (SVT)
- 80.2.15 Address space identifiers (ASI)
- 80.2.16 Partial WRPSR
- 80.2.17 Alternative window pointer
- 80.2.18 Register file partitioning
- 80.2.19 Power-down
- 80.2.20 Processor reset operation
- 80.2.21 Multi-processor systems
- 80.2.22 LEON-REX extension
- 80.3 Cache system
- 80.3.1 Overview
- 80.3.2 Cache operation
- 80.3.3 Cache configuration options
- 80.3.4 Address mapping
- 80.3.5 Data cache policy
- 80.3.6 Write buffer
- 80.3.7 Operating with MMU
- 80.3.8 Snooping
- 80.3.9 Enabling and disabling cache
- 80.3.10 Cache freeze
- 80.3.11 Flushing
- 80.3.12 Locking
- 80.3.13 Diagnostic access
- 80.3.14 Local scratch pad RAM
- 80.3.15 Fault tolerance support
- 80.4 Memory management unit
- 80.5 Floating-point unit
- 80.6 Co-processor interface
- 80.7 AMBA interface
- 80.8 Multi-processor system support
- 80.9 Fault tolerance
- 80.10 ASI assignments
- 80.10.1 Summary
- 80.10.2 ASI 0x1, Forced cache miss
- 80.10.3 ASI 0x2, System control registers
- 80.10.4 ASI 0x8-0xB, Data/Instruction
- 80.10.5 ASI 0xC-0xF, ICache tags/data, DCache tags/data
- 80.10.6 ASI 0xF (alternate), FT register file parity read-out
- 80.10.7 ASI 0x10, 0x11, 0x13, 0x18 - Flush
- 80.10.8 ASI 0x19 and 0x04 - MMU registers
- 80.10.9 ASI 0x1C - MMU and cache bypass
- 80.10.10 ASI 0x1E - MMU snoop/physical tags diagnostic access
- 80.11 Configuration registers
- 80.11.1 PSR, WIM, TBR registers
- 80.11.2 ASR17, LEON3 configuration register
- 80.11.3 ASR20, Alternative window register
- 80.11.4 ASR22-23 - Up-counter
- 80.11.5 ASR24-31, Hardware watchpoint/breakpoint registers
- 80.11.6 Cache control register
- 80.11.7 I-cache and D-cache configuration registers
- 80.11.8 ASR16, Register protection control register (FT only)
- 80.11.9 MMU control register
- 80.11.10 MMU context pointer and context registers
- 80.11.11 MMU fault status register
- 80.11.12 MMU fault address register
- 80.12 Software considerations
- 80.13 LEON3 versions
- 80.14 Vendor and device identifiers
- 80.15 Implementation
- 80.16 Configuration options
- 80.17 Signal descriptions
- 80.18 Signal definitions and reset values
- 80.19 Timing
- 80.20 Library dependencies
- 80.21 Component declaration
- 81 LEON4 - High-performance SPARC V8 32-bit Processor
- 81.1 Overview
- 81.2 LEON4 integer unit
- 81.2.1 Overview
- 81.2.2 Instruction pipeline
- 81.2.3 SPARC Implementor’s ID
- 81.2.4 Divide instructions
- 81.2.5 Multiply instructions
- 81.2.6 Multiply and accumulate instructions
- 81.2.7 Compare and Swap instruction (CASA)
- 81.2.8 Branch prediction
- 81.2.9 Register file data protection
- 81.2.10 Hardware breakpoints
- 81.2.11 Instruction trace buffer
- 81.2.12 Processor configuration register
- 81.2.13 Exceptions
- 81.2.14 Single vector trapping (SVT)
- 81.2.15 Address space identifiers (ASI)
- 81.2.16 Partial WRPSR
- 81.2.17 Power-down
- 81.2.18 Processor reset operation
- 81.2.19 Multi-processor systems
- 81.2.20 LEON-REX extension
- 81.3 Cache system
- 81.3.1 Overview
- 81.3.2 Cache operation
- 81.3.3 Cache configuration options
- 81.3.4 Address mapping
- 81.3.5 Data cache policy
- 81.3.6 Write buffer
- 81.3.7 Operating with MMU
- 81.3.8 Snooping
- 81.3.9 Enabling and disabling cache
- 81.3.10 Cache freeze
- 81.3.11 Flushing
- 81.3.12 Locking
- 81.3.13 Diagnostic access
- 81.3.14 Local scratch pad RAM
- 81.3.15 Fault tolerance support
- 81.4 Memory management unit
- 81.5 Floating-point unit
- 81.6 Co-processor interface
- 81.7 AMBA interface
- 81.8 Multi-processor system support
- 81.9 Fault tolerance
- 81.10 ASI assignments
- 81.10.1 Summary
- 81.10.2 ASI 0x1, Forced cache miss
- 81.10.3 ASI 0x2, System control registers
- 81.10.4 ASI 0x8-0xB, Data/Instruction
- 81.10.5 ASI 0xC-0xF, ICache tags/data, DCache tags/data
- 81.10.6 ASI 0x10, 0x11, 0x13, 0x18 - Flush
- 81.10.7 ASI 0x19 and 0x04 - MMU registers
- 81.10.8 ASI 0x1C - MMU and cache bypass
- 81.10.9 ASI 0x1E - MMU physical/snoop tags diagnostic access
- 81.11 Configuration registers
- 81.11.1 PSR, WIM, TBR registers
- 81.11.2 ASR17, LEON4 configuration register
- 81.11.3 ASR22-23 - Up-counter
- 81.11.4 ASR24-31, Hardware watchpoint/breakpoint registers
- 81.11.5 Cache control register
- 81.11.6 I-cache and D-cache configuration registers
- 81.11.7 MMU control register
- 81.11.8 MMU context pointer and context registers
- 81.11.9 MMU fault status register
- 81.11.10 MMU fault address register
- 81.12 Software considerations
- 81.13 Vendor and device identifiers
- 81.14 Implementation
- 81.15 Configuration options
- 81.16 Signal descriptions
- 81.17 Signal definitions and reset values
- 81.18 Timing
- 81.19 Library dependencies
- 81.20 Component declaration
- 82 LOGAN - On-chip Logic Analyzer
- 83 MCTRL - Combined PROM/IO/SRAM/SDRAM Memory Controller
- 83.1 Overview
- 83.2 PROM access
- 83.3 Memory mapped I/O
- 83.4 SRAM access
- 83.5 8-bit and 16-bit PROM and SRAM access
- 83.6 Burst cycles
- 83.7 8- and 16-bit I/O access
- 83.8 SDRAM access
- 83.9 Refresh
- 83.10 Using bus ready signaling
- 83.11 Access errors
- 83.12 Attaching an external DRAM controller
- 83.13 Endianness
- 83.14 Registers
- 83.15 Vendor and device identifiers
- 83.16 Implementation
- 83.17 Configuration options
- 83.18 Signal descriptions
- 83.19 Library dependencies
- 83.20 Instantiation
- 84 MEMSCRUB - AHB Memory Scrubber and Status Register
- 84.1 Overview
- 84.2 Operation
- 84.3 Registers
- 84.3.1 AHB Status Register
- 84.3.2 AHB Failing Address Register
- 84.3.3 AHB Error Configuration Register
- 84.3.4 Scrubber Status Register
- 84.3.5 Scrubber Configuration Register
- 84.3.6 Scrubber Range Low Address Register
- 84.3.7 Scrubber Range High Address Register
- 84.3.8 Scrubber Position Register
- 84.3.9 Scrubber Error Threshold Register
- 84.3.10 Scrubber Initialization Data Register
- 84.3.11 Scrubber Second Range Low Address Register
- 84.3.12 Scrubber Second Range High Address Register
- 84.4 Vendor and device identifiers
- 84.5 Implementation
- 84.6 Configuration options
- 84.7 Signal descriptions
- 84.8 Library dependencies
- 84.9 Instantiation
- 85 MMA - Memory Mapped AMBA bridge
- 86 MUL32 - Signed/unsigned 32x32 multiplier module
- 87 MULTLIB - High-performance multipliers
- 88 NANDFCTRL - NAND Flash Memory Controller
- 89 PHY - Ethernet PHY simulation model
- 90 RGMII - Reduced Ethernet Media Access Controller
- 91 REGFILE_3P 3-port RAM generator (2 read, 1 write)
- 92 RSTGEN - Reset generation
- 93 GR(2^4)(68, 60, 8, T=1) - QEC/QED error correction code encoder/decoder
- 94 RS(24, 16, 8, E=1) - Reed-Solomon encoder/decoder
- 95 RS(48, 32, 16, E=1+1) - Reed-Solomon encoder/decoder - interleaved
- 96 RS(40, 32, 8, E=1) - Reed-Solomon encoder/decoder
- 97 RS(48, 32, 16, E=2) - Reed-Solomon encoder/decoder
- 98 SDCTRL - 32/64-bit PC133 SDRAM Controller
- 98.1 Overview
- 98.2 Operation
- 98.2.1 General
- 98.2.2 Initialization
- 98.2.3 Configurable SDRAM timing parameters
- 98.2.4 Refresh
- 98.2.5 Self Refresh
- 98.2.6 Power-Down
- 98.2.7 Deep Power-Down
- 98.2.8 Temperature-Compensated Self Refresh
- 98.2.9 Drive Strength
- 98.2.10 SDRAM commands
- 98.2.11 Read cycles
- 98.2.12 Write cycles
- 98.2.13 Address bus connection
- 98.2.14 Data bus
- 98.2.15 Clocking
- 98.2.16 Endianness
- 98.3 Registers
- 98.4 Vendor and device identifiers
- 98.5 Implementation
- 98.6 Configuration options
- 98.7 Signal descriptions
- 98.8 Library dependencies
- 98.9 Instantiation
- 99 SPI2AHB - SPI to AHB bridge
- 99.1 Overview
- 99.2 Transmission protocol
- 99.3 System clock requirements and sampling
- 99.4 SPI instructions
- 99.5 Registers
- 99.6 Vendor and device identifier
- 99.7 Implementation
- 99.8 Configuration options
- 99.9 Signal descriptions
- 99.10 Signal definitions and reset values
- 99.11 Library dependencies
- 99.12 Instantiation
- 100 SPICTRL - SPI Controller
- 100.1 Overview
- 100.2 Operation
- 100.3 Registers
- 100.3.1 SPI Controller Capability Register 0
- 100.3.2 SPI Controller Capability Register 1
- 100.3.3 SPI Controller Mode Register
- 100.3.4 SPI Controller Event Register
- 100.3.5 SPI Controller Mask Register
- 100.3.6 SPI Controller Command Register
- 100.3.7 SPI Controller Transmit Register
- 100.3.8 SPI Controller Receive Register
- 100.3.9 SPI Slave Select Register (optional)
- 100.3.10 SPI Controller Automatic Slave Select Register
- 100.3.11 SPI Controller AM Configuration Register
- 100.3.12 SPI Controller AM Period Register
- 100.3.13 SPI Controller AM Mask Register(s)
- 100.3.14 SPI Controller AM Transmit Register(s)
- 100.3.15 SPI Controller AM Receive Register
- 100.4 Vendor and device identifier
- 100.5 Implementation
- 100.6 Configuration options
- 100.7 Signal descriptions
- 100.8 Signal definitions and reset values
- 100.9 Timing
- 100.10 Library dependencies
- 100.11 Instantiation
- 101 SPIMCTRL - SPI Memory Controller
- 102 SPIMASTER - SPI Master Device
- 103 SPISLAVE - Dual Port SPI Slave
- 103.1 Overview
- 103.2 Implementation of SPI protocols
- 103.3 Transmission
- 103.4 Operation
- 103.5 SPI 2 Protocol Handler
- 103.6 Redundancy
- 103.7 Registers
- 103.7.1 Control Register
- 103.7.2 Status Register
- 103.7.3 Transmit Register
- 103.7.4 Nominal Receive Register
- 103.7.5 Redundant Receive Register
- 103.7.6 Interrupt Enable Register
- 103.7.7 Interrupt Register
- 103.7.8 SPI2 Control Register
- 103.7.9 SPI2 Time1 Register
- 103.7.10 SPI2 Time2 Register
- 103.7.11 SPI2 Config Address Write Register
- 103.7.12 SPI2 Config Address Read Register
- 103.8 Vendor and device identifier
- 103.9 Implementation
- 103.10 Configuration options
- 103.11 Signal descriptions
- 103.12 Library dependencies
- 103.13 Instantiation
- 104 SRCTRL- 8/32-bit PROM/SRAM Controller
- 105 SSRCTRL- 32-bit SSRAM/PROM Controller
- 106 SVGACTRL - VGA Controller Core
- 106.1 Overview
- 106.2 Operation
- 106.3 DVI support
- 106.4 Registers
- 106.4.1 Status Register
- 106.4.2 Video Length Register
- 106.4.3 Front Porch Register
- 106.4.4 Sync Length Register
- 106.4.5 Line Length Register
- 106.4.6 Framebutter Memory Position Register
- 106.4.7 Dynamic Clock 0 Register
- 106.4.8 Dynamic Clock 1 Register
- 106.4.9 Dynamic Clock 2 Register
- 106.4.10 Dynamic Clock 3 Register
- 106.4.11 CLUTA Access Register
- 106.5 Vendor and device identifiers
- 106.6 Implementation
- 106.7 Configuration options
- 106.8 Signal descriptions
- 106.9 Library dependencies
- 106.10 Instantiation
- 106.11 Linux 2.6 driver
- 107 SYNCIOTEST - Test block for synchronous I/O interfaces
- 108 SYNCRAM - Single-port RAM generator
- 109 SYNCRAMBW - Single-port RAM generator with byte enables
- 110 SYNCRAM_2P - Two-port RAM generator
- 111 SYNCRAM_DP - Dual-port RAM generator
- 112 SYNCRAMFT - Single-port RAM generator with EDAC
- 113 TAP - JTAG TAP Controller
- 114 GRTM - CCSDS/ECSS Telemetry Encoder
- 114.1 Overview
- 114.2 References
- 114.3 Layers
- 114.4 Data Link Protocol Sub-Layer
- 114.5 Synchronization and Channel Coding Sub-Layer
- 114.6 Physical Layer
- 114.7 Connectivity
- 114.8 Operation
- 114.9 Registers
- 114.9.1 GRTM DMA Control Register
- 114.9.2 GRTM DMA Status Register
- 114.9.3 GRTM DMA Length Register
- 114.9.4 GRTM DMA Descriptor Pointer Register
- 114.9.5 GRTM DMA Configuration Register (read-only)
- 114.9.6 GRTM DMA Revision Register (read-only)
- 114.9.7 GRTM DMA External VC Control & Status Register
- 114.9.8 GRTM DMA External VC Descriptor Pointer Register
- 114.9.9 GRTM Control Register
- 114.9.10 GRTM Configuration Register (read-only)
- 114.9.11 GRTM Physical Layer Register
- 114.9.12 GRTM Coding Sub-Layer Register
- 114.9.13 GRTM Attached Synchronization Marker Register
- 114.9.14 GRTM All Frames Generation Register
- 114.9.15 GRTM Master Frame Generation Register
- 114.9.16 GRTM Idle Frame Generation Register
- 114.9.17 GRTM FSH / IZ Register 0, MSB
- 114.9.18 GRTM FSH / IZ Register 1
- 114.9.19 GRTM FSH / IZ Register 2
- 114.9.20 GRTM FSH / IZ Register 3, LSB
- 114.9.21 GRTM OCF Register
- 114.10 Vendor and device identifier
- 114.11 Configuration options
- 114.12 Signal descriptions
- 114.13 Signal definitions and reset values
- 114.14 Timing
- 114.15 Library dependencies
- 115 GRTM_DESC - CCSDS/ECSS Telemetry Encoder - Descriptor
- 116 GRTM_VC - CCSDS/ECSS Telemetry Encoder - Virtual Channel Generation
- 117 GRTM_PAHB - CCSDS/ECSS Telemetry Encoder - Virtual Channel Generation Input - AMBA
- 118 GRTM_PW - CCSDS/ECSS Telemetry Encoder - Virtual Channel Generation Input - PacketWire
- 119 GRTM_UART - CCSDS/ECSS Telemetry Encoder - Virtual Channel Generation Input - UART
- 120 GEFFE - CCSDS/ECSS Telemetry Encoder - Geffe Generator
- 121 GRTMRX - CCSDS/ECSS Telemetry Receiver
- 121.1 Overview
- 121.2 References
- 121.3 Layers
- 121.4 Operation
- 121.5 Registers
- 121.5.1 GRTMRX DMA Control Register
- 121.5.2 GRTMRX DMA Status Register
- 121.5.3 GRTMRX DMA Descriptor Pointer Register
- 121.5.4 GRTMRX Control Register
- 121.5.5 GRTMRX Status Register (read-only)
- 121.5.6 GRTMRX Configuration Register
- 121.5.7 GRTMRX Size Register
- 121.5.8 GRTMRX Physical Layer Register
- 121.5.9 GRTMRX Coding Sub-Layer Register
- 121.5.10 GRTMRX Attached Synchronization Marker Register
- 121.5.11 GRTMRX Attached Synchronization Mask Register
- 121.5.12 GRTMRX Data Rate Register (read-only)
- 121.5.13 GRTMRX Filter Register
- 121.5.14 GRTMRX Filter Mask Register
- 121.5.15 GRTMRX OCF Register (read-only)
- 121.5.16 GRTMRX FECF Register (read-only)
- 121.5.17 GRTMRX Demodulator Register
- 121.6 Vendor and device identifier
- 121.7 Configuration options
- 121.8 Signal descriptions
- 121.9 Signal definitions and reset values
- 121.10 Timing
- 121.11 Library dependencies
- 122 GRCE/GRCD - CCSDS/ECSS Convolutional Encoder and Quicklook Decoder
- 123 GRTC - CCSDS/ECSS Telecommand Decoder
- 123.1 Overview
- 123.2 Data formats
- 123.3 Coding Layer (CL)
- 123.4 Transmission
- 123.5 Relationship between buffers and FIFOs
- 123.6 Command Link Control Word interface (CLCW)
- 123.7 Configuration Interface (AMBA AHB slave)
- 123.8 Interrupts
- 123.9 Miscellaneous
- 123.10 Registers
- 123.10.1 Global Reset Register (GRR)
- 123.10.2 Global Control Register (GCR)
- 123.10.3 Physical Interfice Mask Register (PMR)
- 123.10.4 Spacecraft Identifier Register (STR)
- 123.10.5 Frame Acceptance Report Register (FAR)
- 123.10.6 CLCW Register (CLCWRx)
- 123.10.7 Physical Interface Register (PHIR)
- 123.10.8 Control Register (COR)
- 123.10.9 Status Register (STR)
- 123.10.10 Address Space Register (ASR)
- 123.10.11 Receive Read Pointer Register (RRP)
- 123.10.12 Receive Write Pointer Register (RWP)
- 123.10.13 Interrupt registers
- 123.11 Vendor and device identifiers
- 123.12 Configuration options
- 123.13 Signal descriptions
- 123.14 Signal definitions and reset values
- 123.15 Timing
- 123.16 Library dependencies
- 123.17 Instantiation
- 124 TCAU - Telecommand Decoder Authentication Unit
- 124.1 Overview
- 124.2 Operation
- 124.3 References
- 124.4 Data structures
- 124.5 Front-end receiver
- 124.6 Authentication Processor
- 124.7 Final Authorisation
- 124.8 Control Command Processor
- 124.9 Control Commands
- 124.10 Programmable Key Memory
- 124.11 Fixed Key
- 124.12 Back-end transmitter
- 124.13 Cold start state
- 124.14 Registers
- 124.15 Implementation
- 124.16 Configuration options
- 124.17 Signal descriptions
- 124.18 Library dependencies
- 124.19 Instantiation
- 125 GRTC_HW - CCSDS/ECSS Telecommand Decoder - Hardware Commands
- 126 GRTC_UART - CCSDS/ECSS Telecommand Decoder - UART
- 127 GRTCTX - CCSDS/ECSS Telecommand Transmitter
- 127.1 Overview
- 127.2 References
- 127.3 Layers
- 127.4 Operation
- 127.5 Registers
- 127.5.1 GRTCTXDMA Control Register
- 127.5.2 GRTCTX DMA Status Register
- 127.5.3 GRTCTXDMA Descriptor Pointer Register
- 127.5.4 GRTCTX Control Register
- 127.5.5 GRTCTX Configuration Register
- 127.5.6 GRTCTX Physical Layer Register
- 127.5.7 GRTCTX Coding Sub-layer Register
- 127.5.8 GRTCTX Start And Tail Register
- 127.5.9 GRTCTX All Frames Register
- 127.6 Vendor and device identifier
- 127.7 Configuration options
- 127.8 Signal descriptions
- 127.9 Signal definitions and reset values
- 127.10 Timing
- 127.11 Library dependencies
- 128 GRCTM - CCSDS Time Manager
- 128.1 Overview
- 128.2 Data formats
- 128.3 Operation
- 128.4 Registers
- 128.4.1 Global Reset Register
- 128.4.2 Global Control Register
- 128.4.3 Global Status Register
- 128.4.4 Preamble Field Register
- 128.4.5 Elapsed Time Coarse Register
- 128.4.6 Elapsed Time Fine Register
- 128.4.7 Datation Time Coarse Register 0
- 128.4.8 Datation Time Fine Register 0
- 128.4.9 Datation Time Coarse Register 1
- 128.4.10 Datation Time Fine Register 1
- 128.4.11 Datation Time Coarse Register 2
- 128.4.12 Datation Time Fine Register 2
- 128.4.13 Spacecraft Time Datation Coarse Register
- 128.4.14 Spacecraft Time Datation Fine Register
- 128.4.15 Pulse Definition Register 0 to 7
- 128.4.16 Elapsed Time Increment Register
- 128.4.17 Frequency Synthesizer Increment Register
- 128.4.18 Serial Configuration Register
- 128.4.19 TimeWire Start Configuration Register
- 128.4.20 TimeWire Adjust Configuration Register
- 128.4.21 TimeWire Transmit Configuration Register
- 128.4.22 TimeWire Receive Configuration Register
- 128.4.23 Set Elapsed Time Coarse Register
- 128.4.24 Set Elapsed Time Fine Register
- 128.4.25 Interrupt registers
- 128.5 Vendor and device identifiers
- 128.6 Configuration options
- 128.7 Signal descriptions
- 128.8 Signal definitions and reset values
- 128.9 Timing
- 128.10 Library dependencies
- 128.11 Instantiation
- 128.12 Configuration tuning
- 129 SPWCUC - SpaceWire - CCSDS Unsegmented Code Transfer Protocol
- 129.1 Overview
- 129.2 Protocol
- 129.3 Functionality
- 129.3.1 SpaceWire Time-Code transmission
- 129.3.2 SpaceWire Time-Code reception
- 129.3.3 CCSDS Unsegmented Code Transfer Protocol (CUCTP) packet reception
- 129.3.4 Verification of Time-Codes to be received within tolerance
- 129.3.5 Synchronization via Time-Codes
- 129.3.6 Synchronization via CUCTP packets
- 129.3.7 Initialization via CUCTP packets
- 129.3.8 CCSDS Unsegmented Code Transfer Protocol (CUCTP) packet transmission support
- 129.4 Data formats
- 129.5 Registers
- 129.5.1 Various T-Field Mappings
- 129.5.2 Various T-Field Mappings - Example (Time-Codes at 64 Hz, CUCTP Packets at 1 Hz)
- 129.5.3 Configuration Register
- 129.5.4 Status Register
- 129.5.5 Control Register
- 129.5.6 Destination Logical Address and Mask Register
- 129.5.7 Protocol Identifier Register
- 129.5.8 Offset Register
- 129.5.9 T-Field Coarse Time Packet Register
- 129.5.10 T-Field Fine Time Packet Register
- 129.5.11 P-Field Packet and CRC Packet Register
- 129.5.12 Elapsed Coarse Time Register
- 129.5.13 Elapsed Fine Time Register
- 129.5.14 Next Elapsed Coarse Time Packet Register
- 129.5.15 Next Elapsed Fine Time Packet Register
- 129.5.16
- 129.6 Vendor and device identifiers
- 129.7 Implementation
- 129.8 Configuration options
- 129.9 Signal descriptions
- 129.10 Signal definitions and reset values
- 129.11 Timing
- 129.12 Library dependencies
- 130 GRPW - PacketWire Interface
- 131 GRPWRX - PacketWire Receiver
- 132 GRPWTX - PacketWire Transmitter
- 133 PW2APB - PacketWire receiver to AMBA APB Interface
- 134 APB2PW - AMBA APB to PacketWire Transmitter Interface
- 135 AHB2PP - AMBA AHB to Packet Parallel Interface
- 136 GRRM - Reconfiguration Module
- 136.1 Overview
- 136.2 Operation
- 136.3 Alarms
- 136.4 Alarm Pattern
- 136.5 Reconfiguration Log
- 136.6 Reconfiguration Sequences
- 136.7 CPDU Packet Generator
- 136.8 Initial Core Configuration
- 136.9 Health Communication
- 136.10 RM Error
- 136.11 Registers
- 136.12 Vendor and device identifiers
- 136.13 Implementation
- 136.14 Configuration options
- 136.15 Signal descriptions
- 136.16 Signal definitions and reset values
- 136.17 Timing
- 136.18 Library dependencies
- 136.19 Instantiation
- Leon3框图
- AHB trace buffer
- Instruction trace buffer
- 基于地址的指令追踪
- 7 stage pipeline