GRLIB IP Core User’s Manual

User Manual:

Open the PDF directly: View PDF .
Page Count: 1709

Download
Open PDF In Browser	View PDF

GRLIB IP Core
GRLIB VHDL IP Core Library
2018 User’s Manual
The most important thing we build is trust

GRLIB IP Core User’s Manual
Apr 2018, Version 2018.1

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table of contents

Introduction.............................................................................................................................. 6

AHB2AHB - Uni-directional AHB/AHB bridge ................................................................... 18

AHBM2AXI - AHB Master to AXI Adapter ......................................................................... 36

AHB2AXIB - AHB to AXI Bridge ........................................................................................ 44

AHBBRIDGE - Bi-directional AHB/AHB bridge................................................................. 53

AHBCTRL - AMBA AHB controller with plug&play support ............................................. 58

AHBJTAG - JTAG Debug Link with AHB Master Interface ................................................ 66

AHBRAM - Single-port RAM with AHB interface .............................................................. 72

AHBDPRAM - Dual-port RAM with AHB interface............................................................ 75

AHBROM - Single-port ROM with AHB interface .............................................................. 77

AHBSTAT - AHB Status Registers........................................................................................ 80

AHBTRACE - AHB Trace buffer.......................................................................................... 85

AHBUART- AMBA AHB Serial Debug Interface................................................................. 93

AMBAMON - AMBA Bus Monitor ...................................................................................... 99

APBCTRL - AMBA AHB/APB bridge with plug&play support ........................................ 105

APBPS2 - PS/2 host controller with APB interface............................................................. 109

APBUART - AMBA APB UART Serial Interface............................................................... 119

APBVGA - VGA controller with APB interface ................................................................. 129

CAN_OC - GRLIB wrapper for OpenCores CAN Interface core ....................................... 133

CLKGEN - Clock generation............................................................................................... 152

DDRSPA - 16-, 32- and 64-bit DDR266 Controller ............................................................ 175

DDR2SPA - 16-, 32- and 64-bit Single-Port Asynchronous DDR2 Controller ................... 189

DIV32 - Signed/unsigned 64/32 divider module ................................................................. 208

DSU3 - LEON3 Hardware Debug Support Unit ................................................................. 211

DSU4 - LEON4 Hardware Debug Support Unit ................................................................. 227

FTAHBRAM - On-chip SRAM with EDAC and AHB interface ....................................... 245

FTMCTRL - 8/16/32-bit Memory Controller with EDAC ................................................. 252

FTSDCTRL - 32/64-bit PC133 SDRAM Controller with EDAC ...................................... 283

FTSRCTRL - Fault Tolerant 32-bit PROM/SRAM/IO Controller ..................................... 295

FTSRCTRL8 - 8-bit SRAM/16-bit IO Memory Controller with EDAC ............................ 314

GPTIMER - General Purpose Timer Unit ........................................................................... 329

GR1553B - MIL-STD-1553B / AS15531 Interface............................................................. 338

GRTIMER - General Purpose Timer Unit ........................................................................... 380

GRACECTRL - AMBA System ACE Interface Controller................................................. 381

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
35

GRAES - Advanced Encryption Standard ........................................................................... 386

GRAES_DMA - Advanced Encryption Standard with DMA.............................................. 392

GRCAN - CAN 2.0 Controller with DMA .......................................................................... 401

GRCLKGATE / GRCLKGATE2X - Clock gating unit ....................................................... 425

GRDMAC - DMA Controller with internal AHB/APB bridge ........................................... 432

GRECC - Elliptic Curve Cryptography ............................................................................... 453

GRETH - Ethernet Media Access Controller (MAC) with EDCL support ......................... 468

GRETH_GBIT - Gigabit Ethernet Media Access Controller (MAC) w. EDCL.................. 488

GRFIFO - FIFO Interface .................................................................................................... 510

GRADCDAC - ADC / DAC Interface................................................................................. 534

GRFPU - High-performance IEEE-754 Floating-point unit................................................ 547

GRFPC - GRFPU Control Unit ........................................................................................... 554

GRFPU Lite - IEEE-754 Floating-Point Unit...................................................................... 556

GRLFPC - GRFPU Lite Floating-point unit Controller ...................................................... 559

GRGPIO - General Purpose I/O Port................................................................................... 561

GRGPREG - General Purpose Register............................................................................... 572

GRIOMMU - AHB/AHB bridge with access protection and address translation ............... 575

GRPCI2 - 32-bit PCI(Initiator/Target) / AHB(Master/Slave) bridge................................... 620

GRPULSE - General Purpose Input Output ........................................................................ 649

GRPWM - Pulse Width Modulation Generator ................................................................... 656

GRRT - MIL-STD-1553B / AS15531 Remote Terminal Back-End .................................... 669

GRSPW - SpaceWire codec with AHB host Interface and RMAP target............................ 676

GRSPW2 - SpaceWire codec with AHB host Interface and RMAP target.......................... 720

GRSPW2_GEN - GRSPW2 wrapper with Std_Logic interface.......................................... 793

GRSPW2_PHY - GRSPW2 Receiver Physical Interface.................................................... 800

GRSPW_CODEC - SpaceWire encoder-decoder ................................................................ 806

GRSPW_CODEC_GEN - GRSPW_CODEC wrapper with Std_Logic interface .............. 824

GRSPWROUTER - SpaceWire router................................................................................. 831

SPWTDP - SpaceWire - Time Distribution Protocol........................................................... 888

GRSPFI_CODEC - SpaceFibre encoder/decoder................................................................ 920

GRSRIO - Serial RapidIO endpoint with AHB or AXI4 bus master interface.................... 935

GRSYSMON - AMBA Wrapper for Xilinx System Monitor .............................................. 991

GRUSBDC - USB Device controller................................................................................... 999

GRUSB_DCL - USB Debug Communication Link .......................................................... 1025

GRUSBHC - USB 2.0 Host Controller.............................................................................. 1032

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
70

GRVERSION - Version and Revision information register............................................... 1049

I2C2AHB - I2C to AHB bridge ......................................................................................... 1051

I2CMST - I2C-master ........................................................................................................ 1061

I2CSLV - I2C slave ............................................................................................................ 1072

IRQMP - Multiprocessor Interrupt Controller ................................................................... 1080

IRQ(A)MP - Multiprocessor Interrupt Controller with extended ASMP support ............. 1090

L2C - Level 2 Cache controller ......................................................................................... 1105

L3STAT - LEON3 Statistics Unit ...................................................................................... 1129

L4STAT - LEON4 Statistics Unit ...................................................................................... 1137

LEON_DSU_STAT_BASE - LEON3/4 SUBSYSTEM.................................................... 1145

LEON3/FT - High-performance SPARC V8 32-bit Processor .......................................... 1151

LEON4 - High-performance SPARC V8 32-bit Processor................................................ 1200

LOGAN - On-chip Logic Analyzer ................................................................................... 1244

MCTRL - Combined PROM/IO/SRAM/SDRAM Memory Controller ............................ 1251

MEMSCRUB - AHB Memory Scrubber and Status Register ........................................... 1271

MMA - Memory Mapped AMBA bridge........................................................................... 1282

MUL32 - Signed/unsigned 32x32 multiplier module ........................................................ 1287

MULTLIB - High-performance multipliers ....................................................................... 1291

NANDFCTRL - NAND Flash Memory Controller ........................................................... 1293

PHY - Ethernet PHY simulation model ............................................................................. 1318

RGMII - Reduced Ethernet Media Access Controller ....................................................... 1321

REGFILE_3P 3-port RAM generator (2 read, 1 write) ..................................................... 1331

RSTGEN - Reset generation .............................................................................................. 1333

GR(2^4)(68, 60, 8, T=1) - QEC/QED error correction code encoder/decoder.................. 1337

RS(24, 16, 8, E=1) - Reed-Solomon encoder/decoder....................................................... 1341

RS(48, 32, 16, E=1+1) - Reed-Solomon encoder/decoder - interleaved ........................... 1344

RS(40, 32, 8, E=1) - Reed-Solomon encoder/decoder....................................................... 1346

RS(48, 32, 16, E=2) - Reed-Solomon encoder/decoder..................................................... 1349

SDCTRL - 32/64-bit PC133 SDRAM Controller.............................................................. 1353

SPI2AHB - SPI to AHB bridge.......................................................................................... 1363

100

SPICTRL - SPI Controller ................................................................................................. 1372

101

SPIMCTRL - SPI Memory Controller............................................................................... 1393

102

SPIMASTER - SPI Master Device .................................................................................... 1401

103

SPISLAVE - Dual Port SPI Slave ...................................................................................... 1410

104

SRCTRL- 8/32-bit PROM/SRAM Controller ................................................................... 1428

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
105

SSRCTRL- 32-bit SSRAM/PROM Controller .................................................................. 1436

106

SVGACTRL - VGA Controller Core................................................................................. 1446

107

SYNCIOTEST - Test block for synchronous I/O interfaces.............................................. 1454

108

SYNCRAM - Single-port RAM generator ........................................................................ 1456

109

SYNCRAMBW - Single-port RAM generator with byte enables..................................... 1460

110

SYNCRAM_2P - Two-port RAM generator ..................................................................... 1464

111

SYNCRAM_DP - Dual-port RAM generator.................................................................... 1468

112

SYNCRAMFT - Single-port RAM generator with EDAC................................................ 1471

113

TAP - JTAG TAP Controller .............................................................................................. 1473

114

GRTM - CCSDS/ECSS Telemetry Encoder ...................................................................... 1477

115

GRTM_DESC - CCSDS/ECSS Telemetry Encoder - Descriptor...................................... 1504

116

GRTM_VC - CCSDS/ECSS Telemetry Encoder - Virtual Channel Generation ............... 1507

117

GRTM_PAHB - CCSDS/ECSS Telemetry Encoder - 
Virtual Channel Generation Input - AMBA....................................................................... 1509

118

GRTM_PW - CCSDS/ECSS Telemetry Encoder - 
Virtual Channel Generation Input - PacketWire ................................................................ 1513

119

GRTM_UART - CCSDS/ECSS Telemetry Encoder - 
Virtual Channel Generation Input - UART ........................................................................ 1515

120

GEFFE - CCSDS/ECSS Telemetry Encoder - Geffe Generator ........................................ 1518

121

GRTMRX - CCSDS/ECSS Telemetry Receiver................................................................ 1524

122

GRCE/GRCD - CCSDS/ECSS Convolutional Encoder and Quicklook Decoder............. 1538

123

GRTC - CCSDS/ECSS Telecommand Decoder ................................................................ 1543

124

TCAU - Telecommand Decoder Authentication Unit........................................................ 1570

125

GRTC_HW - CCSDS/ECSS Telecommand Decoder - Hardware Commands ................. 1581

126

GRTC_UART - CCSDS/ECSS Telecommand Decoder - UART...................................... 1588

127

GRTCTX - CCSDS/ECSS Telecommand Transmitter ...................................................... 1591

128

GRCTM - CCSDS Time Manager ..................................................................................... 1601

129

SPWCUC - SpaceWire - CCSDS Unsegmented Code Transfer Protocol ......................... 1633

130

GRPW - PacketWire Interface ........................................................................................... 1649

131

GRPWRX - PacketWire Receiver ..................................................................................... 1656

132

GRPWTX - PacketWire Transmitter ................................................................................. 1665

133

PW2APB - PacketWire receiver to AMBA APB Interface................................................ 1672

134

APB2PW - AMBA APB to PacketWire Transmitter Interface .......................................... 1678

135

AHB2PP - AMBA AHB to Packet Parallel Interface......................................................... 1684

136

GRRM - Reconfiguration Module ..................................................................................... 1689

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
1

Introduction

1.1

Scope
This document describes specific IP cores provided with the GRLIB IP library. When applicable, the
cores use the GRLIP plug&play configuration method as described in the ‘GRLIB User’s Manual’.

1.2

Other resources
There are several documents that together describe the GRLIB IP Library and Cobham Gaisler’s IP
cores:
•
GRLIB IP Library User’s Manual (grlib.pdf) - Main GRLIB document that describes the library
infrastructure, organization, tool support and on-chip bus.

1.3

•

GRLIB-FT User’s Manual (grlib-ft.pdf) - Describes the FT and FT-FPGA versions of the GRLIB
IP library. The document is an addendum to the GRLIB IP Library User’s Manual. This document is only available in the FT and FT-FPGA distributions of GRLIB.

•

GRLIB FT-FPGA Xilinx Add-on User’s Manual (grlib-ft-fpga-xilinx.pdf) - Describes functionality of the Virtex5-QV and Xilinx TMRTool add-on package to the FT-FPGA version of the
GRLIP IP library. The document should be read as an addendum to the ‘GRLIB IP Library
User’s Manual’ and to the GRLIB FT-FPGA User’s Manual. This document is only available as
part of the add-on package for FT-FPGA.

•

LEON/GRLIB Configuration and Development Guide (guide.pdf) - This configuration and
development guide is intended to aid designers when developing systems based on LEON/
GRLIB. The guide complements the GRLIB IP Library User’s Manual and the GRLIB IP Core
User’s Manual. While the IP Library user’s manual is suited for RTL designs and the IP Core
user’s manual is suited for instantiation and usage of specific cores, this guide aims to help
designers make decisions in the specification stage.

Reference documents
[AMBA]

AMBATM Specification, Rev 2.0, ARM IHI 0011A, 1999, Issue A, ARM Limited

[GRLIB]

GRLIB IP Library User's Manual, Cobham Gaisler, www.gaisler.com

[AS1553]

AS15531 - Digital Time Division Command/Response Multiplex Data Bus, SAE
International, November 1995

[MIL1553]

MIL-STD-1553B, Digital Time Division Command/Response Multiplex Data Bus,
US Department of Defence, September 1978

[MIL1553N2]

MIL-STD-1553B Notice 2, US Department of Defence, September 1986

[ECSS1553]
Interface and Communication Protocol for MIL-STD-1553B Data Bus Onboard
Spacecraft, ECSS-E-ST-50-13C. November 2008

1.4

IP core overview
The tables below lists the provided IP cores and their AMBA plug&play device ID. The columns on
the right indicate in which GRLIB distributions a core is available. GPL is the GRLIB GNU GPL
(free) distribution, COM is the commercial distribution, FT the full fault-tolerant distribution and FTFPGA is the GRLIB release targeted for raditation-tolerant programmable devices. Distributions prefixed with L4- contain the LEON4 processor. Some cores can only be licensed separately or as additions to existing releases, this is marked in the Notes column. Contact Cobham Gaisler for licensing
details.
Note: The open-source version of GRLIB includes only cores marked with “Yes” in the GPL column.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Note: IP core FT features are only supported in FT or FT-FPGA distributions. This includes protection of Level-1 cache and register files for the LEON3 and LEON4 processors and fault-tolerance features for other IP cores such as the PCI, Ethernet and SpaceWire controllers.
Note: For encrypted RTL, contact Cobham Gaisler to ensure that your EDA tool is supported by
GRLIB for encrypted RTL. Supported tools are listed in the GRLIB IP Library user’s manual.

0x01 : 0x003

Yes Yes Yes Yes No

Fault-tolerant SPARC V8 32-bit Processor

0x01 : 0x053

Yes Yes No

2),
5)

DSU3

Multi-processor Debug support unit
(LEON3)

0x01 : 0x004

Yes Yes Yes Yes No

L3STAT

LEON3 statistics unit

0x01 : 0x098

Yes Yes Yes Yes No

LEON4

SPARC V8 32-bit processor

0x01 : 0x048

Yes No

LEON4FT

Fault-tolerant SPARC V8 32-bit Processor

0x01 : 0x048

Notes

L4-FT

SPARC V8 32-bit processor

LEON3FT

FT-FPGA

LEON3

Vendor:Device

COM

Function

GPL

Name

L4-COM

Table 1. Processors and support functions

1,
4),
5)

Yes 1,
4),
5)

L4STAT

LEON4 statistics unit

0x01 : 0x047

Yes Yes 1)

DSU4

Multi-processor Debug support unit
(LEON4)

0x01 : 0x049

Yes Yes 1)

LEON3/4
CLK2x

LEON processor double clocking
(includes special LEON entity, interrupt
controller and qualifier unit)

Yes Yes Yes Yes Yes

CLKGEN

Clock generation

Yes Yes Yes Yes Yes Yes

DIV32

Divider module

Yes Yes Yes Yes Yes Yes

GPTIMER

General purpose timer unit

0x01 : 0x011

Yes Yes Yes Yes Yes Yes

GRCLKGATE

Clock gate unit

0x01 : 0x02C

GRDMAC

DMA controller with AHB/APB bridge

0x01 : 0x095

Yes Yes Yes Yes Yes Yes

GRTIMER

General purpose timer unit

0x01 : 0x038

Yes Yes Yes Yes Yes

GRFPU /
GRFPC

High-performance IEEE-754 Floatingpoint unit with floating-point controller
to interface LEON

1),
2)

GRFPU-Lite /
GRFPC-lite

Low-area IEEE-754 Floating-point unit
with floating point controller to interface
LEON

1),
2)

IRQMP

Multi-processor Interrupt controller

0x01 : 0x00D

Yes Yes Yes Yes Yes Yes

IRQ(A)MP

Multi-processor Interrupt controller

0x01 : 0x00D

Yes Yes Yes Yes Yes Yes

MUL32

32x32 multiplier module

Yes Yes Yes Yes Yes Yes

MULTLIB

High-performance multipliers

Yes Yes Yes Yes Yes Yes

Yes Yes Yes Yes Yes

1) Available as separate package or as addition to existing releases.
2) Delivered as encrypted RTL or in netlist format
3) Requires PHY for selected target technology. Please see IP core documentation for supported technologies.
4) Fault-tolerance (LEON4-FT functionality) is only supported in GRLIB-FT distributions.
5) The LEON3 and LEON3FT cores are functionally equivalent with the addition that fault-tolerance features can be
enabled for the LEON3FT core. The functional behaviour of the LEON4 core is the same in all distributions wiht the addition that fault-tolerance features for the LEON4 core can be enabled in GRLIB FT distributions.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 2. Memory controllers and supporting cores

Name

Function

Vendor:Device

DDRSPA

Single-port 16/32/64 bit DDR controller

0x01 : 0x025

Yes Yes Yes Yes Yes Yes 3)

DDR2SPA

Single-port 16/32/64-bit DDR2 controller

0x01 : 0x02E

Yes Yes Yes Yes Yes Yes 3)

MCTRL

8/16/32-bit PROM/SRAM/SDRAM
controller

0x04 : 0x00F

Yes Yes Yes Yes Yes Yes

SDCTRL

32-bit PC133 SDRAM controller

0x01 : 0x009

Yes Yes Yes Yes Yes Yes

SRCTRL

8/32-bit PROM/SRAM controller

0x01 : 0x008

Yes Yes Yes Yes Yes Yes

SSRCTRL

32-bit Synchronous SRAM (SSRAM)
controller

0x01 : 0x00A

Yes Yes Yes Yes Yes

FTMCTRL

8//32-bit PROM/SRAM/SDRAM controller w. RS/BCH EDAC

0x01 : 0x054

Yes Yes No

Yes

FTSDCTRL

32/64-bit PC133 SDRAM Controller
with EDAC

0x01 : 0x055

Yes Yes No

Yes

FTSDCTRL64

64-bit PC133 SDRAM controller with
EDAC

0x01 : 0x058

FTSRCTRL

8/32-bit PROM/SRAM/IO Controller w.
BCH EDAC

0x01 : 0x051

Yes Yes No

Yes

FTSRCTRL8

8-bit SRAM / 16-bit IO Memory Controller with EDAC

0x01 : 0x056

Yes Yes No

Yes

NANDFCTRL

NAND Flash memory controller

0x01 : 0x059

Yes Yes Yes Yes Yes

SPIMCTRL

SPI Memory controller

0x01 : 0x045

Yes Yes Yes Yes Yes Yes

AHBSTAT

AHB status register

0x01 : 0x052

Yes Yes Yes Yes Yes Yes

MEMSCRUB

Memory scrubber

0x01 : 0x057

Yes Yes No

Yes

AHB2AHB

Uni-directional AHB/AHB Bridge

0x01 : 0x020

AHB2AVLA

Asynchronous AHB to Avalon Bridge

0x01 : 0x096

Yes Yes No

AHB2AXI

AHB to AXI bridge

0x01 : 0x09F

Yes Yes Yes Yes Yes Yes

AHBBRIDGE

Bi-directional AHB/AHB Bridge

0x01 : 0x020

AHBCTRL

AMBA AHB bus controller with
plug&play

Yes Yes Yes Yes Yes Yes

APBCTRL

AMBA APB Bridge with plug&play

0x01 : 0x006

Yes Yes Yes Yes Yes Yes

AHBTRACE

AMBA AHB Trace buffer

0x01 : 0x017

Yes Yes Yes Yes Yes Yes

GRIOMMU

I/O Memory management unit

0x01 : 0x04F

Note

L4-FT

L4-COM

FT-FPGA

Vendor:Device

Function

COM

Name

GPL

Table 3. AMBA Bus control

Yes Yes Yes Yes Yes
No

Yes No

Yes Yes Yes Yes Yes

Yes Yes 1)

1) Available as separate package or as addition to existing releases.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core

Name

Function

Vendor:Device

GRPCI2

Advanced 32-bit PCI bridge

0x01 : 0x07C

Yes Yes Yes Yes Yes Yes

PCITARGET

32-bit target-only PCI interface (deprecated)

0x01 : 0x012

PCIMTF/GRPCI

32-bit PCI master/target interface with
FIFO (deprecated)

0x01 : 0x014

PCITRACE

32-bit PCI trace buffer (deprecated)

0x01 : 0x015

PCIDMA

DMA controller for PCIMTF (deprecated)

0x01 : 0x016

PCIARB

PCI Bus arbiter

0x04 : 0x010

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 4. PCI interface

Name

Function

Vendor:Device

AHBRAM

Single-port RAM with AHB interface

0x01 : 0x00E

Yes Yes Yes Yes Yes Yes

AHBDPRAM

Dual-port RAM with AHB and user
back-end interface

0x01 : 0x00F

Yes Yes Yes Yes Yes Yes

AHBROM

ROM generator with AHB interface

0x01 : 0x01B

Yes Yes Yes Yes Yes Yes

FTAHBRAM

RAM with AHB interface and EDAC
protection

0x01 : 0x050

Yes Yes No

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 5. On-chip memory functions

Yes

L2CACHE

Level-2 cache controller

0x01 : 0x04B

REGFILE_3P

Parametrizable 3-port register file

Yes Yes Yes Yes Yes Yes

Yes Yes 1)

SYNCRAM

Parametrizable 1-port RAM

Yes Yes Yes Yes Yes Yes

SYNCRAM_2P

Parametrizable 2-port RAM

Yes Yes Yes Yes Yes Yes

SYNCRAM_DP

Parametrizable dual-port RAM

Yes Yes Yes Yes Yes Yes

1) Available as separate package or as addition to existing releases.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core

Name

Function

Vendor:Device

AHBUART

Serial/AHB debug interface

0x01 : 0x007

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 6. Serial communication

AHBJTAG

JTAG/AHB debug interface

0x01 : 0x01C

Yes Yes Yes Yes Yes Yes

APBPS2

PS/2 host controller with APB interface

0x01 : 0x060

Yes Yes Yes Yes Yes Yes

APBUART

Programmable UART with APB interface

0x01 : 0x00C

Yes Yes Yes Yes Yes Yes

CAN_OC

Opencores CAN 2.0 MAC with AHB
interface

0x01 : 0x019

Yes Yes Yes Yes Yes Yes

GRCAN

CAN 2.0 Controller with DMA

0x01 : 0x03D

Yes Yes Yes Yes Yes

GRSPW

SpaceWire link with RMAP and AHB
interface

0x01 : 0x01F

1),
2)

GRSPW2

SpaceWire link with RMAP and AHB
interface

0x01 : 0x029

1),
2)

GRSPW_CODEC

SpaceWire Codec

N/A

1),
2)

GRSPW_PHY

Receiver Physical layer for GRSPW

N/A

1),
2)

GRSPW2_PHY

Receiver Physical layer

N/A

1),
2)

GRSPWROUTER

SpaceWire routing switch

0x01 : 0x03E

1),
2),
3)

GRSPWTDP

SpaceWire - Time Distribution Protocol

0x01 : 0x097

GRSRIO

Serial Rapid IO

0x01 : 0x0A8

GRSPFI_CODEC

SpaceFibre Codec

N/A

I2C2AHB

I2C (slave) to AHB bridge

0x01 : 0x00B

Yes Yes Yes Yes Yes Yes

I2CMST

I2C Master with APB interface

0x01 : 0x028

Yes Yes Yes Yes Yes Yes

I2CSLV

I2C Slave with APB interface

0x01 : 0x03E

Yes Yes Yes Yes Yes Yes

SPI2AHB

SPI (slave) to AHB bridge

0x01 : 0x05C

Yes Yes Yes Yes Yes Yes

SPICTRL

SPI Controller with APB interface

0x01 : 0x02D

Yes Yes Yes Yes Yes Yes

SPIMASTER

SPI master device

0x01 : 0x0A6

SPISLAVE

Dual port SPI slave

0x01 : 0x0A7

TAP

JTAG TAP controller

Yes Yes Yes Yes Yes

1) Available as separate package or as addition to existing releases.
2) Delivered as encrypted RTL or in netlist format
3) The GRSPWROUTER is only licensed together with a complete LEON system.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core

Name

Function

Vendor:Device

GRETH

Cobham Gaisler 10/100 Mbit Ethernet
MAC with AHB I/F

0x01 : 0x01D

Yes Yes Yes Yes Yes Yes

GRETH_GBIT

Cobham Gaisler 10/100/1000 Mbit
Ethernet MAC with AHB

0x01 : 0x01D

RGMII

Cobham Gaisler RGMII<-> GMII
adapter

0x01 : 0x093

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 7. Ethernet interface

Yes Yes Yes Yes Yes

Function

Vendor:Device

COM

FT-FPGA

L4-COM

L4-FT

GRUSBHC

USB-2.0 Host controller (UHCI/EHCI)
with AHB I/F

0x01 : 0x027

GRUSBDC /
USB-2.0 device controller / AHB debug
GRUSB_DCL communication link

0x01 : 0x022

Note

Name

GPL

Table 8. USB interface

1) Available as separate package or as addition to existing releases.

Function

Device ID

COM

FT-FPGA

L4-COM

L4-FT

GR1553B

Advanced MIL-ST-1553B / AS15551
Interface

0x01 : 0x04D

1),
2),
3)

GRRT

MIL-STD-1553B / AS15531 Remote
Terminal Back-End

1),
2),
3)

Note

Name

GPL

Table 9. MIL-STD-1553 Bus interface

1) Available as separate package or as addition to existing releases.
2) Delivered as encrypted RTL or in netlist format.
3) Both BR1553B and GRRT are covered by the same IP core license and are delivered in the same package.

Function

Vendor:Device

COM

FT-FPGA

L4-COM

L4-FT

GRAES

128-bit AES Encryption/Decryption
Core

0x01 : 0x073

GRAES_DMA

Advanced Encryption Standard with
DMA

0x01 : 0x07B

GRECC

Elliptic Curve Cryptography Core

0x01 : 0x074

Note

Name

GPL

Table 10. Encryption

1) Available as separate package or as addition to existing releases.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core

Name

Function

Vendor:Device

SRAM

SRAM simulation model with srecord
pre-load

Yes Yes Yes Yes Yes Yes

MT48LC16M16

Micron SDRAM model with srecord
pre-load

Yes Yes Yes Yes Yes Yes

MT46V16M16

Micron DDR model

Yes Yes Yes Yes Yes Yes

CY7C1354B

Cypress ZBT SSRAM model with srecord pre-load

Yes Yes Yes Yes Yes Yes

AHBMSTEM

AHB master simulation model with
scripting (deprecated)

0x01 : 0x040

Yes Yes Yes Yes Yes Yes

AHBSLVEM

AHB slave simulation model with script- 0x01 : 0x041
ing (deprecated)

Yes Yes Yes Yes Yes Yes

AMBAMON

AHB and APB protocol monitor

Yes Yes Yes Yes Yes

ATF

AMBA test framework consisting of
master, slave and arbiter.

0x01 : 
0x068 - 0x06A

Yes Yes Yes Yes Yes

LOGAN

On-chip Logic Analyzer

0x01 : 0x062

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 11. Simulation and debugging

Name

Function

Vendor:Device

APBVGA

VGA controller with APB interface

0x01 : 0x061

Yes Yes Yes Yes Yes Yes

SVGACTRL

VGA controller core with DMA

0x01 : 0x063

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 12. Graphics functions

Name

Function

Vendor:Device

GRACECTRL

AMBA SystemACE interface controller

0x01 : 0x067

Yes Yes Yes Yes Yes Yes

GRADCDAC

Combined ADC / DAC Interface

0x01 : 0x036

Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes

GRFIFO

External FIFO Interface with DMA

0x01 : 0x035

GRGPIO

General purpose I/O port

0x01 : 0x01A

Yes Yes Yes Yes Yes Yes

GRGPREG

General purpose Register

0x01 : 0x087

Yes Yes Yes Yes Yes Yes

GRPULSE

General purpose I/O with pulses

0x01 : 0x037

Yes Yes Yes Yes Yes

GRPWM

PWM generator

0x01 : 0x04A

Yes Yes Yes Yes Yes

GRSYSMON

AMBA Wrapper for Xilinx System
Monitor

0x01 : 0x066

Yes Yes Yes Yes Yes Yes

GRVERSION

Version and revision register

0x01 : 0x03A

Yes Yes Yes Yes Yes Yes

GRIP, Apr 2018, Version 2018.1

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 13. Auxiliary functions

www.cobham.com/gaisler

GRLIB IP Core

Name

Function

RS(24, 16, 8, E=1)

16 bit data, 8 check bits, corrects 4-bit error in 1 nib- No
ble

Yes Yes No

Yes

RS(40, 32, 8, E=1)

32 bit data, 8 check bits, corrects 4-bit error in 1 nib- No
ble

Yes Yes No

Yes

RS(48, 32, 16, E=1+1)

32 bit data, 16 check bits, corrects 4-bit error in 2
nibbles

Yes Yes No

Yes

RS(48, 32, 16, E=2)

32 bit data, 16 check bits, corrects 4-bit error in 2
nibbles

Yes Yes No

Yes

GR(2^4)(68, 60, 8, T=1)

QEC/QED error correction code encoder/decoder

Yes Yes No

Yes

Note

L4-FT

L4-COM

FT-FPGA

COM

GPL

Table 14. Error detection and correction functions

GRIP, Apr 2018, Version 2018.1

Note

L4-FT

L4-COM

Test block for synchronous I/O interfaces

FT-FPGA

Function

SYNCIOTEST

Name

COM

GPL

Table 15. Test functions

Yes Yes Yes Yes Yes Yes

www.cobham.com/gaisler

GRLIB IP Core
1.5

Spacecraft data handling IP cores
The Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the space sector.
These IP cores implement functions commonly used in spacecraft data handling and management systems. They implement international standards from organizations such as Consultative Committee for
Space Data Systems (CCSDS), European Cooperation on Space Standardization (ECSS), and the former Procedures, Standards and Specifications (PSS) from the European Space Agency (ESA).
The table below lists the existing CCSDS/ECSS IP cores and AMBA plug&play device identifiers.
The columns on the right indicate in which GRLIB distributions a core is available. GPL is the
GRLIB GNU GPL (free) distribution, COM is the commercial distribution, FT the full fault-tolerant
distribution and FT-FPGA is the GRLIB release targeted for radiation-tolerant programmable devices.
Distributions prefixed with L4- contain the LEON4 processor.
The TMTC license covers IP cores, with the upper TM and TC layers implemented in software, hardware and also cores for implementing TM and TC test equipment. It can be provided as a separate
package or as an add-on to other GRLIB distributions.

GRTM

CCSDS Telemetry Encoder

0x01 : 0x030

No Yes

GRTM_DESC

CCSDS Telemetry Encoder - Descriptor

0x01 : 0x084

No Yes

GRTM_VC

CCSDS Telemetry Encoder - Virtual Channel Generation

0x01 : 0x085

No Yes

GRTM_PAHB

CCSDS Telemetry Encoder - VC Generation Input - AMBA

0x01 : 0x088

GRTM_PW

CCSDS Telemetry Encoder - VC Generation Input - PacketWire N/A

No Yes

Note

TMTC

L4.FT

L4-COM

FT-FPGA

Vendor : Device

Function

COM

Name

GPL

Table 16. Spacecraft data handling functions

GRTM_UART

CCSDS Telemetry Encoder - VC Generation Input - UART

N/A

No Yes

GRTM_CLCWRX

CCSDS Telemetry Encoder - CLCW Receiver

N/A

No Yes

GRTM_CLCWMUX

CCSDS Telemetry Encoder - CLCW Multiplexer

N/A

No Yes

GRGEFFE

CCSDS Telemetry Encoder - Geffe Generator

0x01 : 0x086

No Yes

GRCE/GRCD

CCSDS Convolutional Encoder and Quicklook Decoder

N/A

No Yes

GRTMRX

CCSDS Telemetry Receiver

0x01 : 0x082

No Yes
No Yes

GRTC

CCSDS Telecommand Decoder - Coding Layer

0x01 : 0x031

TCAU

ESA PSS Telecommand Decoder Authentication Unit

N/A

No Yes

GRTC_HW

CCSDS Telecommand Decoder - Hardware Commands

N/A

No Yes

GRTC_UART

CCSDS Telecommand Decoder - UART

N/A

No Yes

GRTC_CLCWTX

CCSDS Telecommand Decoder - CLCW Transmitter

N/A

No Yes

GRTCTX

CCSDS Telecommand Transmitter

0x01 : 0x083

No Yes

GRCTM

CCSDS Time manager

0x01 : 0x033

No Yes

SPWCUC

SpaceWire - CCSDS Unsegmented Code Transfer Protocol

0x01 : 0x089

No Yes

GRPW

PacketWire receiver with AHB interface

0x01 : 0x032

No Yes

GRPWRX

PacketWire Receiver (rev 1)

0x01 : 0x03C

No Yes

GRPWTX

PacketWire Transmitter (rev 1)

0x01 : 0x03B

No Yes

APB2PW

PacketWire Transmitter Interface (rev 0)

0x01 : 0x03B

No Yes

PW2APB

PacketWire Receiver Interface (rev 0)

0x01 : 0x03C

No Yes

AHB2PP

Packet Parallel Interface

0x01 : 0x039

No Yes

GRRM

Reconfiguration Module

0x01 : 0x09A

Note 1)

Available as separate package or as addition to existing releases.

Note 2)

There is no user manual for these simple cores.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
1.6

Supported technologies

Comment

FT-

GPL

COM

Technology support and instructions for extending GRLIB with support for additional technologies is
documented in the ‘GRLIB User’s Manual’. The table below shows the technology maps available
from Cobham Gaisler for GRLIB and in which GRLIB distributions these technology maps are
included.

Vendor

Technology

Actel /
Microsemi

ProASIC3, ProASIC3e, ProASIC3l,
Axcelerator, Axcelerator DSP, Fusion,
IGLOO2

Yes Yes Yes

Actel /
Microsemi

RTG4

Altera

Cyclone2 - 4, Stratix - StratixV

Yes Yes Yes Yes Note that several parts of the FT and
FT-FPGA versions are distributed as
encrypted RTL. Encrypted RTL is
not provided for the Quartus II tool.

Lattice

Yes Yes No

Xilinx

Unisim (Virtex2 - 7-series)

Yes Yes Yes Yes Xilinx Sirf (Virtex-5QV) and TMRTool support is distributed as a separate add-on package.

Other ASIC

GRIP, Apr 2018, Version 2018.1

RTG4 support is distributed as a separate add-on package.

Contact Cobham Gaisler for details.
See also GRLIB IP Library User’s
Manual.

www.cobham.com/gaisler

GRLIB IP Core
1.7

Implementation characteristics
Implementation characteristics are available in the GRLIB area spreadsheet:
http://www.gaisler.com/products/grlib/grlib_area.xls
The spreadsheet is also included in GRLIB packages together with this document.

1.8

Definitions
This section and the following subsections define the typographic and naming conventions used
throughout this document.
1.8.1

Bit numbering

The following conventions are used for bit numbering:
•

The most significant bit (MSb) of a data type has the leftmost position

•

The least significant bit of a data type has the rightmost position

•

Unless otherwise indicated, the MSb of a data type has the highest bit number and the LSb the
lowest bit number

1.8.2

Radix

The following conventions is used for writing numbers:
•

Binary numbers are indicated by the prefix "0b", e.g. 0b1010.

•

Hexadecimal numbers are indicated by the prefix "0x", e.g. 0xF00F

•

Unless a radix is explicitly declared, the number should be considered a decimal.

1.8.3

Data types

Byte (BYTE)

8 bits of data

Halfword (HWORD)

16 bits of data

Word (WORD)

32 bits of data

Double word (DWORD)

64 bits of data

Quad word (4WORD)

128-bits of data

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
1.9

Register descriptions
An example register, showing the register layout used throughout this document, can be seen in table
17. The values used for the reset value fields are described in table 18, and the values used for the
field type fields are described in table 19. Fields that are named RESERVED, RES, or R are read-only
fields. These fields can be written with zero or with the value read from the same register field.
Table 17. - -
31

24 23

16 15

EF3

EF2

EF1

EF0

31: 24

Example field 3 (EF3) -

23: 16

Example field 2 (EF2) -

15: 8

Example field 1 (EF1) -

7: 0

Example field 0 (EF0) -

Table 18. Reset value definitions
Value

Description

Reset value 0.

Reset value 1. Used for single-bit fields.

0xNN

Hexadecimal representation of reset value. Used for multi-bit fields.

0bNN

Binary representation of reset value. Used for multi-bit fields.

Field not reset. Fields marked with NR will be reset to 0 if full reset of all registers have been
enabled in the global GRLIB configuration options (see GRLIB user manual for more information).

Special reset condition, described in textual description of the field. Used for example when reset
value is taken from a pin.

Don’t care / Not applicable

Table 19. Field type definitions
Value

Description

Read-only. Writes have no effect.

Write-only. Used for a writable field in a register where the field’s read-value has no meaning.

Readable and writable.

rw*

Readable and writable. Special condition for write, described in textual description of field.

Write-clear. Readable, and cleared when written with a 1

cas

Readable, and writable through compare-and-swap. Only applies to SpaceWire Plug-and-Play registers.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
2

AHB2AHB - Uni-directional AHB/AHB bridge

2.1

Overview
The uni-directional AHB/AHB bridge is used to connect two AMBA AHB buses clocked by synchronous clocks with any frequency ratio. The bridge is connected through a pair consisting of an AHB
slave and an AHB master interface. AHB transfer forwarding is performed in one direction, where
AHB transfers to the slave interface are forwarded to the master interface. Applications of the unidirectional bridge include system partitioning, clock domain partitioning and system expansion.
Features offered by the uni-directional AHB to AHB bridge are:
•

Single and burst AHB transfers

•

Data buffering in internal FIFOs

•

Efficient bus utilization through (optional) use of SPLIT response and data prefetching. NOTE:
SPLIT responses require an AHB arbiter that allows assertion of HSPLIT during second cycle of
SPLIT response. This is supported by GRLIB’s AHBCTRL IP core.

•

Posted writes

•

Read and write combining, improves bus utilization and allows connecting cores with differing
AMBA access size restrictions.

•

Deadlock detection logic enables use of two uni-directional bridges to build a bi-directional
bridge (one example is the bi-directional AHB/AHB bridge core (AHBBRIDGE))

MASTER 1

MASTER 2

MASTER N

AHB Bus 0

BUS
CONTROL

SLAVE 1

SLAVE I/F

SLAVE 2

AHB/AHB
BRIDGE

MASTER I/F
MASTER 1

MASTER N

AHB Bus 1

BUS
CONTROL

SLAVE 2

SLAVE 1

Figure 1. Two AHB buses connected with (uni-directional) AHB/AHB bridge

2.2

Operation
2.2.1

General

The address space occupied by the AHB/AHB bridge on the slave bus is configurable and determined
by Bank Address Registers in the slave interface’s AHB Plug&Play configuration record.
The bridge is capable of handling single and burst transfers of all burst types. Supported transfer sizes
(HSIZE) are BYTE, HALF-WORD, WORD, DWORD, 4WORD and 8WORD.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
For AHB write transfers write data is always buffered in an internal FIFO implementing posted
writes. For AHB read transfers the bridge uses GRLIB’s AMBA Plug&Play information to determine
whether the read data will be prefetched and buffered in an internal FIFO. If the target address for an
AHB read burst transfer is a prefetchable location the read data will be prefetched and buffered.
The bridge can be implemented to use SPLIT responses or to insert wait states when handling an
access. With SPLIT responses enabled, an AHB master initiating a read transfer to the bridge is
always splitted on the first transfer attempt to allow other masters to use the slave bus while the bridge
performs read transfer on the master bus.The descriptions of operation in the sections below assume
that the bridge has been implemented with support for AMBA SPLIT responses. The effects of disabling support for AMBA SPLIT responses are described in section 2.2.11.
If interrupt forwarding is enabled the interrupts on the slave bus interrupt lines will be forwarded to
the master bus and vice versa.
2.2.2

AHB read transfers

When a read transfer is registered on the slave interface the bridge gives a SPLIT response. The master that initiated the transfer will be de-granted allowing other bus masters to use the slave bus while
the bridge performs a read transfer on the master side. The master interface then requests the bus and
starts the read transfer on the master side. Single transfers on the slave side are normally translated to
single transfers with the same AHB address and control signals on the master side, however read combining can translate one access into several smaller accesses. Translation of burst transfers from the
slave to the master side depends on the burst type, burst length, access size and the AHB/AHB bridge
configuration.
If the read FIFO is enabled and the transfer is a burst transfer to a prefetchable location, the master
interface will prefetch data in the internal read FIFO. If the splitted burst on the slave side was an
incremental burst of unspecified length (INCR), the length of the burst is unknown. In this case the
master interface performs an incremental burst up to a specified address boundary (determined by the
VHDL generic rburst). The bridge can be configured to recognize an INCR read burst marked as
instruction fetch (indicated on HPROT signal). In this case the prefetching on the master side is completed at the end of a cache line (the cache line size is configurable through the VHDL generic iburst).
When the burst transfer is completed on the master side, the splitted master that initiated the transfer
(on the slave side) is allowed in bus arbitration by asserting the appropriate HSPLIT signal to the
AHB controller. The splitted master re-attempts the transfer and the bridge will return data with zero
wait states.
If the read FIFO is disabled, or the burst is to non-prefetchable area, the burst transfer on the master
side is performed using sequence of NONSEQ, BUSY and SEQ transfers. The first access in the burst
on the master side is of NONSEQ type. Since the master interface can not decide whether the splitted
burst will continue on the slave side or not, the master bus is held by performing BUSY transfers. On
the slave side the splitted master that initiated the transfer is allowed in bus arbitration by asserting the
HSPLIT signal to the AHB controller. The first access in the transfer is completed by returning read
data. The next access in the transfer on the slave side is extended by asserting HREADY low. On the
master side the next access is started by performing a SEQ transfer (and then holding the bus using
BUSY transfers). This sequence is repeated until the transfer is ended on the slave side.
In case of an ERROR response on the master side the ERROR response will be given for the same
access (address) on the slave side. SPLIT and RETRY responses on the master side are re-attempted
until an OKAY or ERROR response is received.
2.2.3

AHB write transfers

The AHB/AHB bridge implements posted writes. During the AHB write transfer on the slave side the
data is buffered in the internal write FIFO and the transfer is completed on the slave side by always
giving an OKAY response. The master interface requests the bus and performs the write transfer when
the master bus is granted. If the burst transfer crosses the write burst boundary (defined by VHDL
GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
generic wburst), a SPLIT response is given. When the bridge has written the contents of the FIFO out
on the master side, the bridge will allow the master on the slave side to perform the remaining
accesses of the write burst transfer.
Writes are accepted with zero wait states if the bridge is idle and the incoming access is not locked. If
the incoming access is locked, each access will have one wait state. If write combining is disabled a
non-locked BUSY cycle will lead to a flush of the write FIFO. If write combining is enabled or if the
incoming access is locked, the bridge will not flush the write FIFO during the BUSY cycle.
2.2.4

Deadlock conditions

When two bridges are used to form a bi-drectional bridge, a deadlock situation can occur if the
bridges are simultaneously accessed from both buses. The bridge that has been configured as a slave
contains deadlock detection logic which will resolve a deadlock condition by giving a RETRY
response, or by issuing SPLIT complete followed by a new SPLIT response. When the core resolves a
deadlock while prefetching data, any data in the prefetch buffer will be dropped when the core’s slave
interface issues the AMBA RETRY response. When the access is retried it may lead to the same
memory locations being read twice.
Deadlock detection logic for bi-directional configurations may lead to deadlocks in other parts of the
system. Consider the case where a processor on bus A on one side of the bidirectional bridge needs to
perform an instruction fetch over the bridge before it can release a semaphore located in memory on
bus A. Another processor on bus B, on the other side of the bridge, may spin on the semaphore wating
for its release. In this scenario, the accesses from the processor on bus B could, depending on system
configuration, continuously trigger a deadlock condition where the core will drop data in, or be prevented from initiating, the instruction fetch for the processor on bus A. Due to scenarios of this kind
the bridge should not be used in bi-directional configurations where dependencies as the one
described above exist between the buses connected by the bridge.
Other deadlock conditions exist with locked transfers, see section 2.2.5.
2.2.5

Locked transfers

The AHB/AHB bridge supports locked transfers. The master bus will be locked when the bus is
granted and remain locked until the transfer completes on the slave side. Locked transfers can lead to
deadlock conditions, the core’s VHDL generic lckdac determines if and how the deadlock conditions
are resolved.
With the VHDL generic lckdac set to 0, locked transfers may not be made after another read access
which received SPLIT until the first read access has received split complete. This is because the
bridge will return split complete for the first access first and wait for the first master to return. This
will cause deadlock since the arbiter is not allowed to change master until a locked transfer has been
completed. The AMBA specification requires that the locked transfer is handled before the previous
transfer, which received a SPLIT response, is completed.
With lckdac set to 1, the core will respond with an AMBA ERROR response to locked access that is
made while an ongoing read access has received a SPLIT response. With lckdac set to 2 the bridge
will save state for the read access that received a SPLIT response, allow the locked access to complete, and then complete the first access. All non-locked accesses from other masters will receive
SPLIT responses until the saved data has been read out.
If the core is used to create a bi-directional bridge there is one more deadlock condition that may arise
when locked accesses are made simultaneously in both directions. If the VHDL generic lckdac is set
to 0 the core will deadlock. If lckdac is set to a non-zero value the slave bridge will resolve the deadlock condition by issuing an AMBA ERROR response to the incoming locked access.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
2.2.6

Read and write combining

Read and write combining allows the bridge to assemble or split AMBA accesses on the bridge’s
slave interface into one or several accesses on the master interface. This functionality can improve bus
utilization and also allows cores that have differing AMBA access size restrictions to communicate
with each other. The functionality attained by read and write combining depends on the VHDL generics rdcomb (defines type of read combining), wrcomb (defines type of write combining), slvmstaccsz
(defines maximum AHB access size supported by the bridge’s slave interface) and mstmaccsz
(defines maximum AHB access size that can be used by bridge’s master interface). These VHDL
generics are described in section 2.6. The table below shows the effect of different settings. BYTE
and HALF-WORD accesses are special cases. The table does not list illegal combinations, for
instance mstmaccsz /= slvmaccsz requires that wrcomb /= 0 and rdcomb /= 0.
Table 20. Read and write combining
Access on slave interface

wrcomb

rdcomb

Resulting access(es) on master interface

BYTE or HALF-WORD sin- gle read access to any area

Single access of same size

BYTE or HALF-WORD
read burst to prefetchable
area

Incremental read burst of same access size as on
slave interface, the length is the same as the
number of 32-bit words in the read buffer, but
will not cross the read burst boundary.

BYTE or HALF-WORD
read burst to non-prefetchable area

Incremental read burst of same access size as on
slave interface, the length is the same as the
length of the incoming burst. The master interface will insert BUSY cycles between the
sequential accesses.

BYTE or HALF-WORD sin- gle write

Single access of same size

BYTE or HALF-WORD
write burst

Incremental write burst of same size and length,
the maximum length is the number of 32-bit
words in the write FIFO.

Single read access to any
area

Access size <=
mstmaccsz

Single access of same size

Single read access to any
area

Access size >
mstmaccsz

Sequence of single accesses of mstmaccsz. Number of accesses: (access size)/mstmaccsz

Single read access to any
area

Access size >
mstmaccsz

Burst of accesses of size mstmaccsz. Length of
burst: (access size)/mstmaccsz

Read burst to prefetchable
area

Burst of accesses of incoming access size up to
address boundary defined by rburst.

Read burst to prefetchable
area

1 or 2

Burst of accesses of size mstmaccsz up to
address boundary defined by rburst.

Read burst to non-prefetchable area

Access size <=
mstmaccsz

Read burst to non-prefetchable area

Access size >
mstmaccsz

1 or 2

Burst of accesses of size mstmaccsz. Length of
burst: 
(incoming burst length)*(access size)/mstmaccsz

Single write

Access size <=
mstmaccsz

Single write access of same size

Single write

Access size >
mstmaccsz

Sequence of single access of mstmaccsz. Number of accesses: (access size)/mstmaccsz.

Single write

Access size >
mstmaccsz

Burst of accesses of mstmaccsz. Length of burst:
(access size)/mstmaccsz.

GRIP, Apr 2018, Version 2018.1

Access size

www.cobham.com/gaisler

GRLIB IP Core
Table 20. Read and write combining
Access on slave interface

Access size

wrcomb

rdcomb

Resulting access(es) on master interface

Write burst

Burst of same size as incoming burst, up to
address boundary defined by VHDL generic
wburst.

Write burst

1 or 2

Burst write of maximum possible size. The
bridge will use the maximum size (up to mstmaccsz) that it can use to empty the writebuffer.

Read and write combining prevents the bridge from propagating fixed length bursts and wrapping
bursts. See section 2.2.7 for a discussion on burst operation.
Read and write combining with VHDL generics wrcomb/rdcomb set to 1 cause the bridge to use single accesses when divding an incoming access into several smaller accesses. This means that another
master on the bus may write or read parts of the memory area to be accessed by the bridge before the
bridge has read or written all the data. In bi-directional configurations, an incoming access on the
master bridge may cause a collision that aborts the operation on the slave bridge. This may cause the
bridge to read the same memory locations twice. This is normally not a problem when accessing
memory areas. The same issues apply when using an AHB arbiter that performs early burst termination. The standard GRLIB AHBCTRL core does not perform early burst termination.
To ensure that the bridge does not re-read an address, and that all data in an access from the bridge’s
slave interface is propagated out on the master interface without interruption the VHDL generics
rdcomb and wrcomb should both be set to 0 or 2. In addition to this, the AHB arbiter may not perform
early burst termination (early burst termination is not performed by the GRLIB AHBCTRL arbiter).
Read and write combining can be limited to specified address ranges. See description of the combmask VHDL generic for more information. Note that if the core is implemented with support for
prefetch and read combining, it will not obey combmask for prefetch operations (burst read to
prefetchable areas). Prefetch operations will always be performed with the maximum allowed size on
the master interface.
2.2.7

Burst operation

The core can be configured to support all AMBA 2.0 burst types (single access, incrementing burst of
unspecified length, fixed length incrementing bursts and wrapping bursts). Single accesses and incrementing bursts of unspecified length have previously been discussed in this document. An incoming
single access will lead to one access, or multiple accesses for some cases with read/write combining,
on the other side of the bridge. An incoming incrementing burst of unspecified length to a prefetchable area will lead to the prefetch buffer (if available) being filled using the same access size, or the
maximum allowed access size if read/write combining is enabled, on the master interface.
If the core is used in a system where no fixed length bursts or incremental bursts will be used in
accesses to the bridge, then set the allbrst generic to 0 and skip the remainder of this section.
The VHDL generic allbrst controls if the core will support fixed length and wrapping burst accesses.
If allbrst is set to 0, the core will treat all burst accesses as incrementing of unspecified length. For
fixed length and wrapping bursts this can lead to performance penalties and malfunctions. Support for
fixed length and wrapping bursts is enabled by setting allbrst to 1 or 2. Table 21 describes how the
core will handle different burst types depending on the setting of allbrst.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 21. Burst handling
Value of
allbrst
generic

Access type* Undefined length
incrementing burst
INCR

Fixed length incrementing
burst
INCR{4,8,16}

Wrapping burst
WRAP{4,8,16}

Reads to
nonprefetchable
area

Incrementing burst with
BUSY cycles inserted.
Same behaviour with
read and write combining.

Fixed length burst with
BUSY cycles inserted. If the
burst is short then the burst
may end with a BUSY cycle.
If access combining is used
the HBURST signal will get
incorrect values.

Malfunction. Not supported

Reads to
prefetchable
area

Incrementing burst of maximum allowed size, filling
prefetch buffer, starting at address boundary defined by
prefetch buffer.

Malfunction. Not supported

Write burst

Incrementing burst

Incrementing burst, if write
combining is enabled, and
triggered, the burst will be
translated to an incrementing burst of undefined
length. VHDL generic
wrcomb should not be set to
1 (but to 0 or 2) in this case

Write combining is not supported. Same access size will be
used on both sides of the bridge.

Reads to
nonprefetchable
area

Incrementing burst with
BUSY cycles inserted.
Same behaviour with
read and write combining.

Same burst type with BUSY
cycles inserted. If read combining is enabled, and triggered by the incoming access
size, an incremental burst of
unspecified length will be
used. If the burst is short then
the burst may end with a
BUSY cycle.

Same burst type with BUSY
cycles inserted. If read combining is enabled, and triggered by
the incoming access size, an
incremental burst of unspecified
length will be used. This will
cause AMBA violations if the
wrapping burst does not start
from offset 0.

Reads to
prefetchable
area

Incrementing burst of
maximum allowed size,
filling prefetch buffer.

For reads, the core will perform full (or part that fits in prefetch
buffer) fixed/wrapping burst on master interface and then
respond with data. No BUSY cycles are inserted.

If the access made to the slave interface is larger than the maximum supported access size on the master interface then a incrementing burst of unspecified length will be used to fill the
prefetch buffer. This (read combining) is not supported for wrapping bursts.
Write burst
2

Same as for allbrst = 0

Reads to
nonprefetchable
area

Incrementing burst with
BUSY cycles inserted.
Same behaviour with
read and write combining.

Reads to
prefetchable
area

Incrementing burst of
maximum allowed size,
filling prefetch buffer,
starting at address
boundary defined by
prefetch buffer.

Reads are treated as a prefetchable burst. See below.

Core will perform full (or part that fits in prefetch buffer) fixed/
wrapping burst on master interface and then respond with data.
No BUSY cycles are inserted.
If the access made to the slave interface is larger than the maximum supported access size on the master interface then a incrementing burst of unspecified length will be used to fill the
prefetch buffer. This (read combining) is not supported for wrapping bursts.

Write burst

Same as for allbrst = 0

* Access to prefetchable area where the core’s prefetch buffer is ised (VHDL generic pfen /= 0).

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
2.2.8

Transaction ordering, starvation and AMBA arbitration schemes

The bridge is configured at implementation to use one of two available schemes to handle incoming
accesses. The bridge will issue SPLIT responses when it is busy and on incoming read accesses. If the
bridge has been configured to use first-come, first-served ordering it will keep track of the order of
incoming accesses and serve the requests in the same order. If first-come, first-served ordering is disabled the bridge will give some advantage to the master it has a response for and then allow all masters in to arbitration simultaneously, moving the decision on which master that should be allowed to
access the bridge to the bus arbitration.
When designing a system containing a bridge the expected traffic patterns should be analyzed. The
designer must be aware how SPLIT responses affect arbitration and how the selected transaction
ordering in the bridge will affect the system. The two different schemes are further described in sections 2.2.9 and 2.2.10.
2.2.9

First-come, first-served ordering

First-come, first served ordering is used when the VHDL generic fcfs is non-zero.
With first-come, first-served ordering the bridge will keep track of the order of incoming accesses.
The accesses will then be served in the same order. For instance, if master 0 initiates an access to the
bridge, followed by master 3 and then master 5, the bridge will propagate the access from master 0
(and respond with SPLIT on a read access) and then respond with SPLIT to the other masters. When
the bridge has a response for master 0, this master will be allowed in arbitration again by the bridge
asserting HSPLIT. When the bridge has finished serving master 0 it will allow the next queued master
in arbitration, in this case master 3. Other incoming masters will receive SPLIT responses and will not
be allowed in arbitration until all previous masters have been served.
An incoming locked access will always be given precedence over any other masters in the queue.
A burst that has initiated a pre-fetch operation will receive SPLIT and be inserted last in the master
queue if the burst is longer than the maximum burst length that the bridge has been configured for.
It should be noted that first-come, first-served ordering may not work well in systems where an AHB
master needs to have higher priority compared to the other masters. The bridge will not prioritize any
master, except for masters performing locked accesses.
2.2.10 Bus arbiter ordering
Bus arbiter ordering is used when VHDL generic fcfs is set to zero.
When several masters have received SPLIT and the bridge has a response for one of these masters, the
master with the queued response will be allowed in to bus arbitration by the bridge asserting the corresponding HSPLIT signal. In the following clock cycle, all other masters that have received SPLIT
responses will also be allowed in bus arbitration as the bridge asserts their HSPLIT signals simultaneously. By doing this the bridge defers the decision on the master to be granted next to the AHB arbiter.
The bridge does not show any preference based on the order in which it issued SPLIT responses to
masters, except to the master that initially started a read or write operation. Care has been taken so
that the bridge shows a consistent behavior when issuing SPLIT responses. For instance, the bridge
could be simplified if it could issue a SPLIT response just to be able to change state, and not initiate a
new operation, to an access coming after an access that read out prefetched data. When the bridge
entered its idle state it could then allow all masters in bus arbitration and resume normal operation.
That solution could lead to starvation issues such as:
T0: Master 1 and Master 2 have received SPLIT responses, the bridge is prefetching data for Master 1
T1: Master 1 is allowed in bus arbitration by setting the corresponding HSPLIT
T2: Master 1 reads out prefetch data, Master 2 HSPLIT is asserted to let Master 2 in to bus arbitration

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
T3: Master 2 performs an access, receives SPLIT, however the bridge does not initiate an access, it
just stalls in order to enter its idle state.
T4: Master 2 is allowed in to bus arbitration, Master 1 initiates an access that leads to a prefetch and
Master 1 receives a SPLIT response
T5: Master 2 performs an access, receives SPLIT since the bridge is prefetching data for master 1
T6: Go back to T0
This pattern will repeat until Master 1 backs away from the bus and Master 2 is able to make an access
that starts an operation over the bridge. In most systems it is unlikely that this behavior would introduce a bus lock. However, the case above could lead to an unexpectedly long time for Master 2 to
complete its access. Please note that the example above is illustrative and the problem does not exist
in the core as the core does not issue SPLIT responses to (non-locked) accesses in order to just change
state but a similar pattern could appear as a result of decisions taken by the AHB arbiter if Master 1 is
given higher priority than Master 2.
In the case of write operations the scenario is slightly different. The bridge will accept a write immediately and will not issue a SPLIT response. While the bridge is busy performing the write on the master side it will issue SPLIT responses to all incoming accesses. When the bridge has completed the
write operation on the master side it will continue to issue SPLIT responses to any incoming access
until there is a cycle where the bridge does not receive an access. In this cycle the bridge will assert
HSPLIT for all masters that have received a SPLIT response and return to its idle state. The first master to access the bridge in the idle state will be able to start a new operation. This can lead to the following behavior:
T0: Master 1 performs a write operation, does NOT receive a SPLIT response
T1: Master 2 accesses the bridge and receives a SPLIT response
T2: The bridge now switches state to idle since the write completed and asserts HSPLIT for Master 2.
T3: Master 1 is before Master 2 in the arbitration order and we are back at T0.
In order to avoid this last pattern the bridge would have to keep track of the order in which it has
issued SPLIT responses and then assert HSPLIT in the same order. This is done with first-come, firstserved ordering described in section 2.2.9.
2.2.11 AMBA SPLIT support
Support for AMBA SPLIT responses is enabled/disabled through the VHDL generic split. SPLIT support should be enabled in most systems. The benefits of using SPLIT responses is that the bus on the
bridge’s slave interface side can be free while the bridge is performing an operation on the master
side. This will allow other masters to access the bus and generally improve system performance. The
use of SPLIT responses also allows First-come, first-served transaction ordering.
For configurations where the bridge is the only slave interface on a bus, it can be beneficial to implement the bridge without support for AMBA SPLIT responses. Removing support for SPLIT responses
reduces the area used by the bridge and may also reduce the time required to perform accesses that
traverse the bridge. It should be noted that building a bi-directional bridge without support for SPLIT
responses will increase the risk of access collisions.
If SPLIT support is disabled the bridge will insert wait states where it would otherwise issue a SPLIT
response to a master initiating an access. This means that the arbitration ordering will be left to the bus
arbiter and the bridge cannot be implemented with the First-come, first-served transaction ordering
scheme. The bridge will still issue RETRY responses to resolve dead lock conditions, to split up long
burst and also when the bridge is busy emptying it’s write buffer on the master side.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
2.2.12 Core latency
The delay incurred when performing an access over the core depends on several parameters such as
core configuration, the operating frequency of the AMBA buses, AMBA bus widths and memory
access patterns. Table 22 below shows core behavior in a system where both AMBA buses are running at the same frequency and the core has been configured to use AMBA SPLIT responses. Table
23 further down shows core behavior in the same system without support for SPLIT responses.
Table 22. Example of single read with FFACT = 1, and SPLIT support
Clock cycle

Core slave side activity

Core master side activity

Discovers access and transitions from idle state

Idle

Slave side waits for master side, SPLIT response
is given to incoming access, any new incoming
accesses also receive SPLIT responses.

Discovers slave side transition. Master interface output
signals are assigned.

2
3

If bus access is granted, perform address phase. Otherwise wait for bus grant.
Register read data and transition to data ready state.

Discovers that read data is ready, assign read
data output and assign SPLIT complete

SPLIT complete output is HIGH

Typically a wait cycle for the SPLIT:ed master to
be allowed into arbitration. Core waits for master
to return. Other masters receive SPLIT
responses.

Master has been allowed into arbitration and performs address phase. Core keeps HREADY high

Access data phase. Core has returned to idle
state.

Idle

Table 23. Example of single read with FFACT = 1, without SPLIT support
Clock cycle

Core slave side activity

Core master side activity

Discovers access and transitions from idle state

Idle

Slave side waits for master side, wait states are
inserted on the AMBA bus.

Discovers slave side transition. Master interface output
signals are assigned.

Bus access is granted, perform address phase.

Discovers that read data is ready, assign
HREADY output register and data output register.

HREADY is driven on AMBA bus. Core has
returned to idle state

Idle

While the transitions shown in tables 22 and 23 are simplified they give an accurate view of the core
delay. If the master interface needs to wait for a bus grant or if the read operation receives wait states,
these cycles must be added to to the cycle count in the tables. The behavior of the core with a fre-

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
quency factor of two between the buses is shown in tables 24 and 25 (best case, delay may be larger
depending on on which slave clock cycle an access is made to the core).
Table 24. Example of single read with FFACT = 2, Master freq. > Slave freq, without SPLIT support
Slave side
clock cycle

Core slave side activity

Master side
clock cycle

Discovers access and transitions from idle
state

Slave side waits for master side, wait states
are inserted on the AMBA bus.

Discovers slave side transition. Master interface output signals are assigned.

Bus access is granted, perform address
phase.

Idle

3
4
5
6

Discovers that read data is ready, assign
HREADY output register and data output
register.

HREADY is driven on AMBA bus. Core
has returned to idle state

Core master side activity

Table 25. Example of single read with FFACT = 2, Master freq. > Slave freq, without SPLIT support
Slave side
clock cycle
0
1

Core slave side activity

Master side
clock cycle

Core master side activity

Discovers access and transitions from idle
state

Idle

Slave side waits for master side, wait states
are inserted on the AMBA bus.

Discovers slave side transition. Master interface output signals are assigned.

Bus access is granted, perform address
phase.

Discovers that read data is ready, assign
HREADY output register and data output
register.

Idle

HREADY is driven on AMBA bus. Core
has returned to idle state

6
7

Table 26 below lists the delays incurred for single operations that traverse the bridge while the bridge
is in its idle state. The second column shows the number of cycles it takes the master side to perform
the requested access, this column assumes that the master slave gets access to the bus immediately
and that each access is completed with zero wait states. The table only includes the delay incurred by
traversing the core. For instance, when the access initiating master reads the core’s prefetch buffer,
each additional read will consume one clock cycle. However, this delay would also have been present
if the master accessed any other slave.
Write accesses are accepted with zero wait states if the bridge is idle, this means that performing a
write to the idle core does not incur any extra latency. However, the core must complete the write
operation on the master side before it can handle a new access on the slave side. If the core has not
transitioned into its idle state, pending the completion of an earlier access, the delay suffered by an
access be longer than what is shown in the tables in this section. Accesses may also suffer increased
delays during collisions when the core has been instantiated to form a bi-directional bridge. Locked
accesses that abort on-going read operations will also mean additional delays.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
If the core has been implemented to use AMBA SPLIT responses there will be an additional delay
where, typically, one cycle is required for the arbiter to react to the assertion of HSPLIT and one clock
cycle for the repetition of the address phase.
Note that if the core has support for read and/or write combining, the number of cycles required for
the master will change depending on the access size and length of the incoming burst access. For
instance, in a system where the bus in the core’s master side is wider than the bus on the slave side,
write combining will allow the core to accept writes with zero wait states and then combine several
accesses into one or several larger access. Depending on memory controller implementation this
could reduce the time required to move data to external memory, and will reduce the load on the master side bus.
Table 26. Access latencies
Access

Master acc. cycles Slave cycles

Delay incurred by performing access over core

Single read

1 * clkslv + 3 * clkmst

Burst read with prefetch

2 + (burst length)x

2 * clkslv + (2 + burst length)* clkmst

Single writexx

(2)

Burst writexx

(2 + (burst length))

x A prefetch
xx The

operation ends at the address boundary defined by the prefetch buffer’s size
core implements posted writes, the number of cycles taken by the master side can only affect the next access.

2.2.13 Endianness
The core is designed for big-endian systems.

2.3

Registers
The core does not implement any registers.

2.4

Vendor and device identifiers
The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x020. For description of
vendor and device identifiers see GRLIB IP Library User’s Manual.

2.5

Implementation
2.5.1

Technology mapping

The uni-directional AHB to AHB bridge has two technology mapping generics memtech and fcfsmtech. memtech selects which memory technology that will be used to implement the FIFO memories.
fcfsmtech selects the memory technology to be used to implement the First-come, first-served buffer,
if FCFS is enaled.
2.5.2

Reset

The core changes reset behaviour depending on settings in the GRLIB configuration package (see
GRLIB User’s Manual).
The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set.
The core does not support grlib_async_reset_enable. All registers that react on the reset signal will
have a synchronous reset.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
2.5.3

RAM usage

The uni-directional AHB to AHB bridge instantiates one or several syncram_2p blocks from the technology mapping library (TECHMAP). If prefetching is enabled max(mstmaccsz, slvaccsz)/32 syncram_2p block(s) with organization (max(rburst,iburst)-max(mstmaccsz, slvaccsz)/32) x 32 is used to
implement read FIFO (max(rburst,iburst) is the size of the read FIFO in 32-bit words). max(mstmaccsz, slvaccsz)/32 syncram_2p block(s) with organization (wburst - max(mstmaccsz, slvaccsz)/32)
x 32, is always used to implement the write FIFO (where wburst is the size of the write FIFO in 32-bit
words).
If the core has support for first-come, first-served ordering then one fcfs x 4 syncram_2p block will be
instantiated, using the technology specified by the VHDL generic fcfsmtech.

2.6

Configuration options
Table 27 shows the configuration options of the core (VHDL generics).
Table 27. Configuration options (VHDL generics)
Generic

Function

memtech

Memory technology

Allowed range

Default

hsindex

Slave I/F AHB index

0 to NAHBMAX-1

hmindex

Master I/F AHB index

0 to NAHBMAX-1

dir

0 - clock frequency on the master bus is lower than or
equal to the frequency on the slave bus
1 - clock frequency on the master bus is higher than or
equal to the frequency on the slave bus

0-1

(for VHDL generic ffact = 1 the value of dir does not
matter)
ffact

Frequency scaling factor between AHB clocks on master
and slave buses.

1 - 15

slv

Slave bridge. Used in bi-directional bridge configuration
where slv is set to 0 for master bridge and 1 for slave
bridge. When a deadlock condition is detected slave
bridge (slv=1) will give RETRY response to current
access, effectively resolving the deadlock situation.

0-1

This generic must only be set to 1 for a bridge where the
frequency of the bus connecting the master interface is
higher or equal to the frequency of the AHB bus connecting to the bridge’s slave interface. Otherwise a race
condition during access collisions may cause the bridge
to deadlock.
pfen

Prefetch enable. Enables read FIFO.

0-1

irqsync

Interrupt forwarding. Forward interrupts from slave
0-3
interface to master interface and vice versa. 
0 - no interrupt forwarding, 1 - forward interrupts 1 - 15, 
2 - forward interrupts 0 - 31.
3 - forward interrupts 0 - 31.
Since interrupts are forwarded in both directions, interrupt forwarding should be enabled for one bridge only in
a bi-directional AHB/AHB bridge.

wburst

Length of write bursts in 32-bit words. Determines write 2 - 32
FIFO size and write burst address boundary. If the
wburst generic is set to 2 the bridge will not perform
write bursts over a 2x4=8 byte boundary. This generic
must be set so that the buffer can contain two of the maximum sized accesses that the bridge can handle.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 27. Configuration options (VHDL generics)
Generic

Function

Allowed range

Default

iburst

Instruction fetch burst length. This value is only used if
the generic ibrsten is set to 1. Determines the length of
prefetching instruction read bursts on the master side.
The maximum of (iburst,rburst) determines the size of
the core’s read buffer FIFO.

4-8

rburst

Incremental read burst length. Determines the maximum
length of incremental read burst of unspecified length
(INCR) on the master interface. The maximum of rburst
and iburst determine the read burst boundary. As an
example, if the maximum value of these generics is 8 the
bridge will not perform read bursts over a 8x4=32 byte
boundary.

4 - 32

This generic must be set so that the buffer can contain
two of the maximum sized accesses that the bridge can
handle.
For systems where AHB masters perform fixed length
burst (INCRx , WRAPx) rburst should not be less than
the length of the longest fixed length burst.
bar0

Address area 0 decoded by the bridge’s slave interface.
Appears as memory address register (BAR0) on the
slave interface. The generic has the same bit layout as
bank address registers with bits [19:18] suppressed (use
functions ahb2ahb_membar and ahb2ahb_iobar in gaisler.misc package to generate this generic).

0 - 1073741823

bar1

Address area 1 (BAR1)

0 - 1073741823

bar2

Address area 2 (BAR2)

0 - 1073741823

bar3

Address area 3 (BAR2)

0 - 1073741823

sbus

The number of the AHB bus to which the slave interface
is connected. The value appears in bits [1:0] of the userdefined register 0 in the slave interface configuration
record and master configuration record.

0-3

mbus

The number of the AHB bus to which the master interface is connected. The value appears in bits [3:2] of the
user-defined register 0 in the slave interface configuration record and master configuration record.

0-3

ioarea

Address of the I/O area containing the configuration area
for AHB bus connected to the bridge’s master interface.
This address appears in the bridge’s slave interface userdefined register 1. In order for a master on the slave
interface’s bus to access the configuration area on the
bus connected to the bridge’s master interface, the I/O
area must be mapped on one of the bridge’s BARs.

0 - 16#FFF#

0-1

If this generic is set to 0, some tools, such as Cobham
Gaisler’s GRMON debug monitor, will not perform
Plug’n’Play scanning over the bridge.
ibrsten

Instruction fetch burst enable. If set, the bridge will perform bursts of iburst length for opcode access
(HPROT[0] = ‘0’), otherwise bursts of rburst length will
be used for both data and opcode accesses.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 27. Configuration options (VHDL generics)
Generic

Function

Allowed range

Default

lckdac

Locked access error detection and correction. Locked
accesses may lead to deadlock if a locked access is made
while an ongoing read access has received a SPLIT
response. The value of lckdac determines how the core
handles this scenario:

0-2

0: Core will deadlock
1: Core will issue an AMBA ERROR response to the
locked access
2: Core will allow both accesses to complete.
If the core is used to create a bidirectional bridge, a deadlock condition may arise when locked accesses are made
simultaneously in both directions. With lckdac set to 0
the core will deadlock. With lckdac set to a non-zero
value the slave bridge will issue an ERROR response to
the incoming locked access.
slvmaccsz

The maximum size of accesses that will be made to the
bridge’s slave interface. This value must equal mstmaccsz unless rdcomb /= 0 and wrcomb /= 0.

32 - 256

mstmaccsz

The maximum size of accesses that will be performed by 32 - 256
the bridge’s master interface. This value must equal mstmaccsz unless rdcomb /= 0 and wrcomb /= 0.

rdcomb

Read combining. If this generic is set to a non-zero value
the core will use the master interface’s maximum AHB
access size when prefetching data and allow data to be
read out using any other access size supported by the
slave interface.

0-2

If slvmaccsz > 32 and mstmaccsz > 32 and an incoming
single access, or access to a non-prefetchable area, is
larger than the size supported by the master interface the
bridge will perform a series of small accesses in order to
fetch all the data. If this generic is set to 2 the core will
use a burst of small fetches. If this generic is set to 1 the
bridge will not use a burst unless the incoming access
was a burst.
Read combining is only supported for single accesses
and incremental bursts of unspecified length.
wrcomb

Write combining. If this generic is set to a non-zero
value the core may assemble several small write accesses
(that are part of a burst) into one or more larger accesses
or assemble one or more accesses into several smaller
accesses. The settings are as follows:
0: No write combining
1: Combine if burst can be preserved
2: Combine if burst can be preserved and allow single
accesses to be converted to bursts (only applicable if
slvmaccsz > 32)
Only supported for single accesses and incremental
bursts of unspecified length

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 27. Configuration options (VHDL generics)
Generic

Function

Allowed range

Default

combmask

Read/write combining mask. This generic determines
which ranges that the core can perform read/write combining to (only available when rdcomb respectively
wrcomb are non-zero). The value given for combmask is
treated as a 16-bit vector with LSB bit (right-most) indicating address 0x0 - 0x10000000. Making an access to
an address in an area marked as ‘0’ in combmask is
equivalent to making an access over a bridge with
rdcomb = 0 and wrcomb = 0. However, combmask is not
taken into account when the core performs a prefetch
operation (see pfen generic). When a prefetch operation
is initiated, the core will always use the maximum supported access size (when rdcomb /= 0).

0 - 16#FFFF#

16#FFFF#

allbrst

Support all burst types

0-2

0-1

0 - NAHBMST

2: Support all types of burst and always prefetch for
wrapping and fixed length bursts.
1: Support all types of bursts
0: Only support incremental bursts of unspecified length
See section 2.2.7 for more information.
When allbrst is enabled, the core’s read buffer (size set
via rburst/iburst generics) must have at least 16 slots.
ifctrlen

Interface control enable. When this generic is set to 1 the
input signals ifctrl.mstifen and ifctrl.slvifen can be used
to force the AMBA slave respectively master interface
into an idle state. This functionality is intended to be
used when the clock of one interface has been gated-off
and any stimuli on one side of the bridge should not be
propagated to the interface on the other side of the
bridge.
When this generic is set to 0, the ifctrl.* input signals are
unused.

fcfs

First-come, first-served operation. When this generic is
set to a non-zero value, the core will keep track of the
order of incoming accesses and handle the requests in the
same order. If this generic is set to zero the bridge will
not preserve the order and leave this up to bus arbitration. If FCFS is enabled the value of this generic must be
higher or equal to the number of masters that may perform accesses over the bridge.

fcfsmtech

Memory technology to use for FCFS buffer. When
0 - NTECH
VHDL generic fcfs is set to a non-zero value, the core
will instantiate a 4 bit x fcfs buffer to keep track of the
incoming master indexes. This generic decides the memory technology to use for the buffer.

0 (inferred)

scantest

Enable scan support

0-1

split

Use AMBA SPLIT responses. When this generic is set to
1 the core will issue AMBA SPLIT responses. When this
generic is set to 0 the core will insert waitstates instead
and may also issue AMBA RETRY responses. If this
generic is set to 0, the fcfs generic must also be set to 0,
otherwise a simulation failure will be asserted.

0-1

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 27. Configuration options (VHDL generics)
Generic

Function

Allowed range

pipe

This setting controls the insertion of pipeline registers
between the master and slave side of the bridge.

0, 1, 128

Default

pipe set to 0 does not include any extra pipeline registers
and the incurred delays for accesses over the bridge is as
described in this documentation.
pipe set to 1 includes extra registers on all signals
between the master and slave side.
pipe set to 2 includes pipeline registers on all signals
going from the slave interface to the master interface and
does NOT insert extra registers on signals going from the
master interface to the slave interface.
pipe set to 3 includes pipeline registers on all signals
going from the master interface to the slave interface and
does NOT insert extra registers on signals going from the
slave interface to the master interface.
pipe set to 128 includes signals on a subset of the signals
to prevent direct paths from the slave clock to the master
side bus and from the master clock to the slave side bus.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
2.7

Signal descriptions
Table 28 shows the interface signals of the core (VHDL ports).
Table 28. Signal descriptions (VHDL ports)
Signal name

Field

Type

Function

Active

RST

Input

Reset

Low

HCLKM

Input

AHB master bus clock

HCLKS

Input

AHB slave bus clock

AHBSI

Input

AHB slave input signals

AHBSO

Output

AHB slave output signals

AHBMI

Input

AHB master input signals

AHBMO

Output

AHB master output signals

AHBSO2

Input

AHB slave input vector signals (on master i/f
side). Used to decode cachability and prefetchability Plug&Play information on bus connected
to the bridge’s master interface.

LCKI

slck
blck
mlck

Input

Used in systems with multiple AHB/AHB
bridges (e.g. bi-directional AHB/AHB bridge) to
detect deadlock conditions. Tie to “000” in systems with only uni-directional AHB/AHB bus.

High

LCKO

slck
blck
mlck

Output

Indicates possible deadlock condition

High

IFCTRL

mstifen

Input

Enable master interface. This input signal is
High
unused if the VHDL generic ifctrlen is 0. If
VHDL generic ifctrlen is 1 this signal must be
set to ‘1’ in order to enable the core’s AMBA
master interface, otherwise the master interface
will always be idle and will not respond to stimuli on the core’s AMBA slave interface. This signal is intended to be used to keep the core’s
master interface in a good state when the core’s
slave interface clock has been gated off. Care
should be taken to ensure that the bridge is idle
when the master interface is disabled.

slvifen

Input

Enable slave interface. This input signal is
unused if the VHDL generic ifctrlen is 0. If
VHDL generic ifctrlen is 1 this signal must be
set to ‘1’ in order to enable the core’s AMBA
slave interface, otherwise the interface will
always be ready and the bridge will not propagate stimuli on the core’s AMBA slave interface
to the core’s AMBA master interface. This signal
is intended to be used to keep the slave interface
in a good state when the core’s master interface
clock has been gated off. Care should be taken to
ensure that the bridge is idle when the slave
interface is disabled.

High

* see GRLIB IP Library User’s Manual

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
2.8

Library dependencies
Table 29 shows the libraries used when instantiating the core (VHDL libraries).
Table 29. Library dependencies

2.9

Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Signals

AMBA signal definitions

GAISLER

MISC

Component

Component declaration

Instantiation
GRLIB contains two example designs with AHB2AHB and LEON processors: designs/leon3ahb2ahb (only available in commercial distributions) and designs/leon4-ahb2ahb (only in distributions that include LEON4 processor). The LEON/GRLIB Configuration and Development Guide contains more information on how to use the bridge to create multi-bus systems.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
3

AHBM2AXI - AHB Master to AXI Adapter

3.1

Overview
The AHBM2AXI adapter allows a single AHB master to be used as an AXI3 or AXI4 master. The
adapter has an AHB slave interface on the AHB side and AXI3 or AXI4 master interface on the AXI
side (see Fig. 2). The adapter has optional read prefetching and write buffering features in order to
improve the latency of burst operations. The adapter is not compatible with AHB2AHB and GRDMAC components which is a part of GRLIB IP library.

AHB
MASTER

AHBM2AXI

AXI
SLAVE

Figure 2. A standalone AHB master is connected to an AXI slave through AHBM2AXI adapter

3.1.1

AHB support

The AHBM2AXI adapter currently supports the following features of the AHB protocol:
Transfer Type: IDLE, NONSEQ, SEQ
Burst Operation: SINGLE, INCR, INCR4, INCR8, INCR16
Data-width: 32-bit, 64-bit, 128-bit, 256-bit
Transfer Size: All possible transfer sizes up to the selected data-width are supported.
Response: AXI read and write error responses are translated to AHB read and write errors.
Unsupported AHB Features:
The following features of AHB protocol are not supported by the AHBM2AXI adapter.
•

BUSY transfer type : Behavior of the AHBM2AXI adapter is unpredictable when a BUSY transaction is received hence the AHBM2AXI adapter can not be used with the AHB2AHB bridge
which is a part of GRLIB IP library.

•

Locked transfers : Locked transfers are ignored by the AHBM2AXI adapter.

Unused AHB Features:
•

3.2

RETRY and SPLIT responses : The adapter does not generate these response types.

Special Considerations
There is a combinatorial path between the incoming HTRANS signal and outgoing HREADY signal
on the AHB side of the adapter, in order to allow write-buffering and write response propagation at
the same time. As a result, this component is only intended to connect to a single IP core with an AHB
master interface in which HTRANS output does not depend on the incoming HREADY signal combinatorially. Propagating the write response correctly is important to make sure that the intended transaction ordering has been met, meaning the AHB master that is connected to the adapter receives the
acknowledgment for the last write beat in the burst when the write response has been received on the

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
AXI side. Being able to propagate correct write response can also simplify the software development.
The AHBM2AXI adapter can not be used with the GRDMAC IP core which is a part of GRLIB IP
library.

3.3

Operation
3.3.1

Read Prefetching and Write Buffering

The adapter has the feature of read prefetching and write buffering for the AHB bursts in which the
transfer size (HSIZE) is equal to the selected data-width. For the transfer sizes that are narrower than
the data-width each beat in the burst treated as a single transaction on the AXI side. Read prefetching
and write buffering reduces the latency of undefined length burst operations since otherwise each beat
in an undefined length burst has to be treated as an independent AXI transaction with a length of one.

3.3.2

Read Prefetching

Read prefetch number that is set through rprefetch_num generic determines the length of the AXI
transaction(s) that is generated when an undefined length AHB read burst is encountered. When an
undefined length AHB read burst is encountered, an AXI transaction is generated with a length of
rprefetch_num. If the AHB read burst has less beats than rprefetch_num then dummy reads are generated on the AXI side to complete the AXI transaction. If the AHB read burst has more beats than
rprefetch_num then a new AXI transaction is generated with a number of beats equal to rprefetch_num and this scheme continuous until the AHB burst ends. If the start address of a burst is not aligned
to the prefetch boundary then the initial prefetch has less number of beats in order to align the upcoming prefetches. For example given a 32-bit (4 Byte) data-width and a rprefetch_num of 16 (16*4=64
Bytes) if the least significant bits of the initial burst address corresponds to byte 48, then the initial
prefetch length is 4 ((64-48)/4). This way the upcoming prefetches are always aligned to 64 Byte
boundary. If a new AHB burst is encountered during dummy read operations on the AXI side, the
AHB burst is stalled until the current AXI transaction ends.
The maximum read prefetch number depends on the AXI protocol. For AXI3 the maximum number is
16, and for AXI4 it can be up to 256 depending on the selected data-width. Prefetch length can only
be a power of two and if it is not set to be a power of two then the number is floored to the closest
power of two automatically. For fixed length AHB bursts (single, INCR4, INCR8, INCR16) the
length of the AXI burst is equal to the AHB burst length since in those cases the burst length is known
at the beginning of the burst. The adapter will not issue a new AXI transaction while dummy cycles
are inserted hence there is a trade-off for performance when selecting the read prefetch number.

3.3.3

Write Buffering

Write buffering gathers a number of consecutive beats in a AHB write burst and initiates an AXI
transaction. A generic called wbuffer_num determines the maximum number of AHB write burst
beats that will be gathered before an AXI write burst transaction is generated. If the number of beats
in the AHB write burst is less than wbuffer_num then the AXI write transaction starts after detecting
the last beat in the burst (transition from SEQ to IDLE). If the number of beats are higher than
wbuffer_num then the first AXI transaction is generated once wbuffer_num number of beats are buffered. It should be noted that once an AXI write transaction is generated and AHB burst still continues
then AXI transaction and buffering for the next write batch happens in parallel to minimize the
latency. This scheme continuous until the AHB burst is ended. When the last data beat of the burst is
reached the HREADY on the AHB side is asserted once the write response is received from the AXI
side. The write buffering feature is used for the fixed size burst also in the same way as undefined
length bursts.
GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Write buffer length can only be a power of two, and if it is not set to be a power of two then the number is floored to the closest power of two automatically. The maximum number has the same constraints as the read prefetch number. A synchronous memory width one read and write port is
generated for write buffering. The size of the memory is determined by the write buffer length. The
type of the memory can be configured with a generic also. The first AXI write transaction will not
start until the buffer is filled or the AHB transaction has written the last beat in the burst. As a result
there is a trade-off for performance while selecting the write buffer length which depends on the AXI
slave behavior.
3.3.4

Endianness

The AHB side of the AHB2AXIB bridge is always assumed to be big-endian. The endianness on the
AXI side is configurable through the endianness_mode generic.
When endianness_mode generic is set to zero a byte-invariant big-endian endianness mode is used on
the AXI side. In order to translate big-endian AHB to byte-invariant big-endian AXI the byte order is
reversed (see Fig. 3). No address translation occurs inside the adapter in this mode.

(Bit position) (31)

AHB DATA-BUS

(0)
B2

MSB
MSB

AXI DATA-BUS

(Bit position) (31)

B3
(0)

Figure 3. Big-endian AHB to byte-invariant Big-endian AXI translation (32-bit data-width)

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
128-bit data bus width:
if HSIZE < “100” :
axi_address(3:0) = (“10000” - “1”<<“HSIZE” - ahb_address(3:0))(3:0)
otherwise:
axi_address(3:0) = ahb_address(3:0)
256-bit data bus width:
if HSIZE < “101” :
axi_address(4:0) = (“100000” - “1”<<“HSIZE” - ahb_address(4:0))(4:0)
otherwise:
axi_address(4:0) = ahb_address(4:0)

(Bit position) (31)

AHB DATA-BUS

(0)
B2

When HSIZE = “010” no translation

When HSIZE = “001”
AHB-side “00” -> AXI-side “10”
AHB-side “10” -> AXI-side “00”

MSB

AXI DATA-BUS

Address translation for 32-bit data-bus width
(address bits 1 and 0 is translated)

(Bit position) (31)

B0
(0)

When HSIZE = “000”
AHB-side “00” -> AXI-side “11”
AHB-side “01” -> AXI-side “10”
AHB-side “10” -> AXI-side “01”
AHB-side “00” -> AXI-side “00”

Figure 4. Big-endian AHB to little-endian AXI through address translation (32-bit data-width)

3.4

AXI AxPROT and AxCACHE Translations
The AxPROT and AxCACHE signals are translated partly according to the HPROT signal of AHB
transactions. The full list of translation can be seen from Table 30.

Table 30. AxPROT and AxCACHE translations
AXI signal

Assignment

AxCACHE[3]

always logic ‘0’

AxCACHE[2]

always logic ‘0’

AxCACHE[1]

HPROT[3]

AxCACHE[0]

HPROT[2]

AxPROT[2]

not (HPROT[0])

AxPROT[1]

See configuration
options (Table. 31)

AxPROT[0]

HPROT[1]

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core

3.5

Configuration Options
Table 31. Configuration options (both AHBM2AXI3 and AHBM2AXI4)
Generic

Function

Allowed range

Default

memtech

Memory technology

aximid

AXI master ID used for Read and Write transactions

0 - 15

always_secure

When set to 1 the AxPROT[1] bit is tied to logic ‘0’
(always secure access), when set to 0 the AxPROT[1] bit
is tied to logic ‘1’ (always unsecure access).

0-1

endianness_mode

Determines the endianness mode (see section 3.3.4 for
more detail)

0-1

0 -> Big-endian AHB to byte-invariant big-endian AXI
1 -> Big-endian AHB to little-endian AXI

Table 32. Configuration options specific for AXI3 (AHBM2AXI3)
Generic

Function

Allowed range

Default

wbuffer_num

Write-buffer length which determines the memory size
also.

1-16

rprefetch_num

Read prefetch length.

1-16

Table 33. Configuration options specific for AXI4 (AHBM2AXI4)
Generic

Function

Allowed range

Default

wbuffer_num

Write-buffer length which determines the memory size
also.

1-256 for data-width of
32-bit,

1-128 for data-width of
64-bit
1-64 for data-width of
128-bit
1-32 for data-width of
256-bit
rprefetch_num

Read prefetch length.

1-256 for data-width of
32-bit,

1-128 for data-width of
64-bit
1-64 for data-width of
128-bit
1-32 for data-width of
256-bit

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
3.6

Signal descriptions
Table 34 shows the interface signals of the core (VHDL ports).
Table 34. Signal descriptions (VHDL ports)
Signal name

Field

Type

Function

Active

RST

Input

Reset

Low

CLK

Input

AHB & AXI bus clock

AHBSI

Input

AHB slave input signals

AHBSO

Output

AHB slave output signals

AXIMI

Input

AXI3/4 master input signals

AXIMO

Output

AXI3/4 master output signals

* see GRLIB IP Library User’s Manual

3.7

Library dependencies
Table 35 shows the libraries used when instantiating the core (VHDL libraries).
Table 35. Library dependencies

3.8

Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Signals

AMBA & AXI signal definitions

GAISLER

AXI

Component

Component declaration

Instantiation
The instantiation of the AHBM2AXI adapter depends on the AXI protocol type. There are two components called AHBM2AXI3 which is built for AXI3 protocl and AHBM2AXI4 which is built for
AXI4 protocol. The difference between these two components are the AXI master output signals and
the maximum values that can be set for read prefetching and write buffering.
Since AHBM2AXI adapter is intended to be used for only a single core, a transaction is sampled and
evaluated directly on the rising edge of the clock, the “hsel” and “hready” inputs are ignored by the
AHBM2AXI adapter. The grant signal for the AHB master that is connected to the adapter should be
hardwired to logic 1.
Following is an example in which a component with an ahb master interface called “ahbm_ex” is connected to the AHBM2AXI4 adapter which can act as an master for AXI4 protocol.
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.axi.all;

entity ahbm2axi4_ex is
port (
rstn : in std_logic;

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
clk
: in std_logic;
aximi : in axi_somi_type;
aximo : out axi4_mosi_type
);
end;

architecture rtl of ahbm2axi4_ex is
signal
signal
signal
signal

ahbsi
ahbso
ahbmi
ahbmo

:
:
:
:

in
out
in
out

ahb_slave_in_type;
ahb_slave_out_type;
ahb_mst_in_type;
ahb_mst_out_type;

component ahbm_ex is
port (
signal rstn
: in std_logic;
signal clk
: in std_logic;
signal ahbmi : in ahb_mst_in_type;
signal ahbmo : out ahb_mst_out_type);
end component;

begin
adapter:ahbm2axi4
generic map (
memtech => 0,
aximid => 0,
wbuffer_num => 16,
rprefetch_num=> 16,
always_secure => 1
)
port map (
rstn => rstn,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
aximi => aximi,
aximo => aximo);
ahbmaster:ahbm_ex
port map (
rstn => rstn,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo);

ahbsi.haddr
ahbsi.hwrite
ahbsi.htrans
ahbsi.hsize
ahbsi.hburst
ahbsi.hwdata
ahbsi.hprot

<=
<=
<=
<=
<=
<=
<=

ahbmo.hadddr;
ahbmo.hwrite;
ahbmo.htrans;
ahbmo.hsize;
ahbmo.hburst;
ahbmo.hwdata;
ahbmo.hprot;

ahbmi.hgrant <= (others=> ‘1’);
ahbmi.hready <= ahbso.hready;
ahbmi.hresp <= ahbso.hresp;
ahbmi.hrdata <= ahbso.hrdata;
--Remaining ahb master inputs are implementation dependent

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
4

AHB2AXIB - AHB to AXI Bridge

4.1

Overview
The AHB2AXIB bridge allows to access an AXI3 or AXI4 slave from an AHB bus through an AHB
slave interface (see Fig. 5). It can also be used to connect a standalone AHB master to an AXI slave
(see Fig. 6). The bridge has an AHB slave interface on the AHB side and AXI3 or AXI4 master interface on the AXI side. The bridge has optional read prefetching and write buffering features in order to
improve the latency of burst operations. The AHB2AXIB bridge is not compatible with the
AHB2AHB bridge which is a part of GRLIB IP library.

AHB
MASTER-0

AHB
MASTER-N

AHB
Controller

AHB BUS

AHB2AXIB

AXI
SLAVE

Figure 5. An AXI slave connected to the AHB bus through AHB2AXIB bridge

AHB
MASTER

AHB2AXIB

AXI
SLAVE

Figure 6. A standalone AHB master is connected to an AXI slave through AHB2AXIB bridge

4.1.1

AHB support

The AHB2AXIB bridge currently supports the following features of the AHB protocol:
Transfer Type: IDLE, NONSEQ, SEQ
Burst Operation: SINGLE, INCR, INCR4, INCR8, INCR16
Data-width: 32-bit, 64-bit, 128-bit, 256-bit
Transfer Size: All possible transfer sizes up to the selected data-width are supported.
Response: AXI read error response is translated to AHB read error.
Unsupported AHB Features:
The following features of AHB protocol are not supported by the AHB2AXIB bridge.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
•

BUSY transfer type : Behavior of the AHB2AXIB bridge is unpredictable when a BUSY transaction is received hence the AHB2AXIB bridge can not be used with the AHB2AHB bridge
which is a part of GRLIB IP library.

•

Locked transfers : Locked transfers are ignored by the AHB2AXIB bridge.

Unused AHB Features:

4.2

•

RETRY and SPLIT responses ; AHB2AXIB bridge does not generate these response types.

•

Write error response : Due to the difference between the write error handling of AXI and AHB
protocol the write errors received from the AXI side is not propagated.

Operation
4.2.1

Read Prefetching and Write Buffering and Postponed Writes

The bridge has the feature of read prefetching and write buffering for the AHB bursts in which the
transfer size (HSIZE) is equal to the selected data-width. For the transfer sizes that are narrower than
the data-width it can still support read prefetching and write buffering if byte invariant big endian
mode is used. Otherwise each beat in the burst treated as a single transaction on the AXI side. Read
prefetching and write buffering reduces the latency of undefined length burst operations since otherwise each beat in an undefined length burst has to be treated as an independent AXI transaction with a
length of one.

4.2.2

Read Prefetching

Read prefetch number that is set through rprefetch_num generic determines the length of the AXI
transaction(s) that is generated when an undefined length AHB read burst is encountered. When an
undefined length AHB read burst is encountered, an AXI transaction is generated with a length of
rprefetch_num. If the AHB read burst has less beats than rprefetch_num then dummy reads are generated on the AXI side to complete the AXI transaction. If the AHB read burst has more beats than
rprefetch_num then a new AXI transaction is generated with a number of beats equal to rprefetch_num and this scheme continuous until the AHB burst ends. If the start address of a burst is not aligned
to the prefetch boundary then the initial prefetch has less number of beats in order to align the upcoming prefetches. For example given a 32-bit (4 Byte) data-width and a rprefetch_num of 16 (16*4=64
Bytes) if the least significant bits of the initial burst address corresponds to byte 48, then the initial
prefetch length is 4 ((64-48)/4). This way the upcoming prefetches are always aligned to 64 Byte
boundary. If a new AHB burst is encountered during dummy read operations on the AXI side, the
AHB burst is stalled until the current AXI transaction ends.
The maximum read prefetch number depends on the AXI protocol. For AXI3 the maximum number is
16, and for AXI4 it can be up to 256 depending on the selected data-width. Prefetch length can only
be a power of two and if it is not set to be a power of two then the number is floored to the closest
power of two automatically. For fixed length AHB bursts (single, INCR4, INCR8, INCR16) the
length of the AXI burst is equal to the AHB burst length since in those cases the burst length is known
at the beginning of the burst. The bridge will not issue a new AXI transaction while dummy cycles are
inserted hence there is a trade-off for performance when selecting the read prefetch number.

4.2.3

Write Buffering

www.cobham.com/gaisler

GRLIB IP Core
in the AHB write burst is less than wbuffer_num then the AXI write transaction starts after detecting
the last beat in the burst (transition from SEQ to IDLE). If the number of beats are higher than
wbuffer_num then the first AXI transaction is generated once wbuffer_num number of beats are buffered. It should be noted that once an AXI write transaction is generated and AHB write burst still continues then AXI transaction and buffering of the next write batch happens in parallel to improve the
latency. This scheme continuous until the AHB burst is ended. The last data beat in the burst is always
acknowledged with OKAY response immediately when it is buffered in the bridge. See section 4.2.5
for more detailed information.
Write buffer length can only be a power of two, and if it is not set to be a power of two then the number is floored to the closest power of two automatically. The maximum number has the same constraints as the read prefetch number. A synchronous memory width one read and write port is
generated for write buffering. The size of the memory is determined by the write buffer length. The
type of the memory can be configured with a generic also. The first AXI write transaction will not
start until the buffer is filled or the AHB transaction has written the last beat in the burst. As a result
there is a trade-off for performance while selecting the write buffer length which depends on the AXI
slave behavior.

4.2.4

Narrow Sized Transactions

When an AHB transaction is encountered which has a narrower size (HSIZE) than the data-width of
the AHB2AXIB bridge, the behavior is configurable through the generics depending on the selected
endianness on the AXI side. When the endianness mode on the AXI side is set as little-endian than
each beat in the narrow sized AXI transaction is treated as single transaction on the AXI side. When
the endinness mode on the AXI side is set as byte invariant big-endian than the narrow_acc_mode
generic determines the behaviour. If the narrow_acc_mode generic is set as zero than each beat in the
narrow sized AXI transaction is treated as single transaction on the AXI side. If it is set to 1 then a
corresponding narrow sized AXI burst is generated with read prefetching and write buffering. But it
should be noted that the length of the narrow sized burst will be determined by rprefetch_num and
wbuffer_num generics and it is same as for all access sizes. When the endianness on the AXI side is
set ass little-endian then narrow_acc_mode generic must be set to zero. See sec. 4.2.6 for more
detailed information about endianness modes.

4.2.5

Postponed Writes

Since the write response from AXI is not propagated to AHB side the last beat in the AHB write transaction is acknowledged immediately when it is buffered in the bridge. Hence the corresponding AXI
write transaction will finish after the AHB write transaction is completed. The transaction order on the
AHB bus side will be preserved because the bridge will block an AHB read, if there is an AXI write
transaction is ongoing, until the AXI write response is received. But if a transaction order has to be
preserved between the AHB side of a AHB2AXIB bridge and an independent AXI master that
accesses to the same AXI slave then special considerations in software might be needed. If the
AHB2AXIB bridge is intended to be used for a single AHB master without an AHB bus then it is possible to use the AHBM2AXI adapter that is a part of GRLIB IP library if the AHB master is compatible. The AHBM2AXI adapter propagates the AXI write response.
4.2.6

Endianness

The AHB side of the AHB2AXIB bridge is always assumed to be big-endian. The endianness on the
AXI side is configurable through the endianness_mode generic.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
When endianness_mode generic is set to zero a byte-invariant big-endian endianness mode is used on
the AXI side. In order to translate big-endian AHB to byte-invariant big-endian AXI the byte order is
reversed (see Fig. 7). No address translation occurs inside the adapter in this mode.

(Bit position) (31)

AHB DATA-BUS

(0)
B2

MSB
MSB

AXI DATA-BUS

(Bit position) (31)

B3
(0)

Figure 7. Big-endian AHB to byte-invariant Big-endian AXI translation (32-bit data-width)

When endianness_mode generic is set to one then big-endian AHB is translated to little-endian AXI.
In order to achieve this the byte order is preserved but the address is translated from big-endian representation to little-endian representation when a narrow sized transaction is encountered (See Fig. 8 for
an example with 32-bit data-bus width.).
The address translation formula for 32-bit, 64-bit, 128-bit and 256-bit data-bus widths are following:
32-bit data bus width:
if HSIZE < “010” :
axi_address(1:0) = (“100” - “1”<<“HSIZE” - ahb_address(1:0))(1:0)
otherwise:
axi_address(1:0) = ahb_address(1:0)
64-bit data bus width:
if HSIZE < “011” :
axi_address(2:0) = (“1000” - “1”<<“HSIZE” - ahb_address(2:0))(2:0)
otherwise:
axi_address(2:0) = ahb_address(2:0)
128-bit data bus width:
if HSIZE < “100” :
axi_address(3:0) = (“10000” - “1”<<“HSIZE” - ahb_address(3:0))(3:0)
otherwise:
axi_address(3:0) = ahb_address(3:0)
256-bit data bus width:
if HSIZE < “101” :
axi_address(4:0) = (“100000” - “1”<<“HSIZE” - ahb_address(4:0))(4:0)
otherwise:
axi_address(4:0) = ahb_address(4:0)

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core

(Bit position) (31)

AHB DATA-BUS

(0)
B2

When HSIZE = “010” no translation

When HSIZE = “001”
AHB-side “00” -> AXI-side “10”
AHB-side “10” -> AXI-side “00”

MSB

AXI DATA-BUS

Address translation for 32-bit data-bus width
(address bits 1 and 0 is translated)

(Bit position) (31)

B0
(0)

When HSIZE = “000”
AHB-side “00” -> AXI-side “11”
AHB-side “01” -> AXI-side “10”
AHB-side “10” -> AXI-side “01”
AHB-side “00” -> AXI-side “00”

Figure 8. Big-endian AHB to little-endian AXI through address translation (32-bit data-width)

4.3

AXI AxPROT and AxCACHE Translations
The AxPROT and AxCACHE signals are translated partly according to the HPROT signal of AHB
transactions. The full list of translation can be seen from Table 36.

Table 36. AxPROT and AxCACHE translations
AXI signal

Assignment

AxCACHE[3]

always logic ‘0’

AxCACHE[2]

always logic ‘0’

AxCACHE[1]

HPROT[3]

AxCACHE[0]

HPROT[2]

AxPROT[2]

not (HPROT[0])

AxPROT[1]

See configuration
options (Table. 37)

AxPROT[0]

HPROT[1]

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
4.4

Configuration Options
Table 37. Configuration options (both AHB2AXI3B and AHB2AXI4B)
Generic

Function

Allowed range

Default

memtech

Memory technology

aximid

AXI master ID used for Read and Write transactions

0 - 15

always_secure

When set to 1 the AxPROT[1] bit is tied to logic ‘0’
(always secure access), when set to 0 the AxPROT[1] bit
is tied to logic ‘1’ (always unsecure access).

0-1

endianness_mode

Determines the endianness mode (see section 4.2.6 for
more detail)

0-1

0 -> Big-endian AHB to byte-invariant big-endian AXI
1 -> Big-endian AHB to little-endian AXI
narrow_acc_mode

Determines if bursts with narrow access size than the
data-bus width should be directly translated to narrow
access size AXI bursts or single AXI transactions with
narrow access size. (see section 4.2.4 for more detail)
0-> Each beat in the narrow sized AHB burst is treated as
single transaction on the AXI side.
1-> Narrow sized AHB bursts are translated to narrow
sized AXI bursts. (supported only when endianness_mode generic is 0)
Note: This generic must be set to 0 if endianness_mode
is set to 1.

vendor

GRLIB plug&play vendor ID

GAISLER

device

GRLIB plug&play device ID

bar0

0 - 1073741823

AHB2AXI

bar1

Address area 1 (BAR1)

0 - 1073741823

bar2

Address area 2 (BAR2)

0 - 1073741823

bar3

Address area 3 (BAR2)

0 - 1073741823

Table 38. Configuration options specific for AXI3 (AHB2AXI3B)
Generic

Function

Allowed range

Default

wbuffer_num

Write-buffer length which determines the memory size
also.

1-16

rprefetch_num

Read prefetch length.

1-16

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 39. Configuration options specific for AXI4 (AHB2AXI4B)
Generic

Function

Allowed range

Default

wbuffer_num

Write-buffer length which determines the memory size
also.

1-256 for data-width of
32-bit,

1-128 for data-width of
64-bit
1-64 for data-width of
128-bit
1-32 for data-width of
256-bit
rprefetch_num

Read prefetch length.

1-256 for data-width of
32-bit,

1-128 for data-width of
64-bit
1-64 for data-width of
128-bit
1-32 for data-width of
256-bit

4.5

Signal descriptions
Table 40 shows the interface signals of the core (VHDL ports).
Table 40. Signal descriptions (VHDL ports)
Signal name

Field

RST
CLK

Type

Function

Active

Input

Reset

Low

Input

AHB & AXI bus clock

AHBSI

Input

AHB slave input signals

AHBSO

Output

AHB slave output signals

AXIMI

Input

AXI3/4 master input signals

AXIMO

Output

AXI3/4 master output signals

* see GRLIB IP Library User’s Manual

4.6

Library dependencies
Table 41 shows the libraries used when instantiating the core (VHDL libraries).
Table 41. Library dependencies
Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Signals

AMBA & AXI signal definitions

GAISLER

AXI

Component

Component declaration

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
4.7

Instantiation
The instantiation of the AHB2AXIB bridge depends on the AXI protocol type. There are two components called AHB2AXI3B which is built for AXI3 protocol and AHB2AXI4B which is built for AXI4
protocol. The difference between these two components are the AXI master output signals and the
maximum values that can be set for read prefetching and write buffering.

4.7.1

AHB2AXIB bridge is used to connect an AXI slave to an AHB bus

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.axi.all;

entity ahb2axib_ex is
port (
rstn : in std_logic;
clk
: in std_logic;
.
.
.
aximi : in axi_somi_type;
aximo : out axi4_mosi_type;
);
end;

architecture rtl of ahb2axib_ex is
.
.
constant hindex_ahb2axi4b : integer := 2;
begin
.
.
ahbctrl & other components
.
.

bridge:ahb2axi4b
generic map (
hindex => hindex_ahb2axi4b,
aximid => 0
)
port map (
rstn => rstn,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso(hindex_ahb2axi4b),
aximi => aximi,
aximo => aximo);

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
4.7.2

AHB2AXIB bridge is used to connect a standalone AHB master to an AXI slave.

If AHB2AXIB bridge is intended to be used to connect a standalone AHB master to an AXI slave
then the following assignments are needed for correct operations:
The hsel input of the AHB2AXIB must be assigned to an array of (others=>’1’) so that it works
regardless of the assigned hindex value.
The hready input of the AHB2AXIB must be connected to the hready output of the AHB2AXIB.
The hgrant input of the AHB master must be assigned to an array of (others=>’1’) so that it works
regardless of the assigned hindex value.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
5

AHBBRIDGE - Bi-directional AHB/AHB bridge

5.1

Overview
A pair of uni-directional bridges (AHB2AHB) can be instantiated to form a bi-directional bridge. The
bi-directional AHB/AHB bridge (AHBBRIDGE) instantiates two uni-directional bridges that are configured to suit the bus architecture shown in figure 9. The bus architecture consists of two AHB buses:
a high-speed AHB bus hosting LEON3 CPU(s) and an external memory controller and a low-speed
AHB bus hosting communication IP-cores.
Note: For other architectures, a more general bi-directional bridge that is more suitable can be created
by instantiating two uni-directional AHB to AHB bridges (see AHB2AHB core). AHBBRIDGE is not
suitable for LEON4 systems and for other systems with wide AHB buses.

LEON3

SDRAM

SDRAM
Controller

Async Mem
Controller

SRAM

DSU3

AHB
CTRL

High-speed bus
AHB/AHB
Bridge

PROM

LEON3

Serial
Dbg Link

JTAG
Dbg Link

AHB
CTRL

Low-speed bus
AHB/APB
Bridge

PCI

Ethernet
MAC

I/O
UARTS

Timers

IrqCtrl

Figure 9. LEON3 system with a bi-directional AHB/AHB bridge

5.2

Operation
5.2.1

General

The AHB/AHB bridge is connected to each AHB bus through a pair consisting of an AHB master and
an AHB slave interface. The address space occupied by the AHB/AHB bridge on each bus is determined by Bank Address Registers which are configured through VHDL generics. The bridge is capable of handling single and burst transfers in both directions. Internal FIFOs are used for data
buffering. The bridge implements the AMBA SPLIT response to improve AHB bus utilization. For
more information on AHB transfers please refer to the documentation for the uni-directional AHB/
AHB bridge (AHB2AHB).
The requirements on the two bus clocks are that they are synchronous. The two uni-directional
bridges forming the bi-directional AHB/AHB bridge are configured asymmetrically. Configuration of
the bridge connecting high-speed bus with the low-speed bus (down bus) is optimized for the bus traffic generated by the LEON3 CPU since the CPU is the only master on the high-speed bus (except for
the bridge itself). Read transfers generated by the CPU are single read transfers generated by single
load instructions (LD), read bursts of length two generated by double load instructions (LDD) or
incremental read bursts of maximal length equal to cache line size (4 or 8 words) generated during
instruction cache line fill. The size of the read FIFO for the down bridge is therefore configurable to 4
or 8 entries which is the maximal read burst length. If a read burst is an instruction fetch (indicated on
AHB HPROT signal) to a prefetchable area the bridge will prefetch data to the end of a instruction
GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
cache line. If a read burst to a prefetchable area is a data access, two words will be prefetched (this
transfer is generated by the LDD instruction). The write FIFO has two entries capable of buffering the
longest write burst (generated by the STD instruction). The down bridge also performs interrupt forwarding, interrupt lines 1-15 on both buses are monitored and an interrupt on one bus is forwarded to
the other one.
Since the low-speed bus does not host a LEON3 CPU, all AHB transfers forwarded by the uni-directional bridge connecting the low-speed bus and the high-speed bus (up bridge) are data transfers.
Therefore the bridge does not make a distinction between instruction and data transfers. The size of
the read and write FIFOs for this bridge is configurable and should be set by the user to suite burst
transfers generated by the cores on the low-speed bus.
Note that the bridge has been optimized for a LEON3 system with a specific set of masters and a specific bus topology. Therefore the core may not be suitable for a design containing later versions of the
LEON processor or other masters. In general it is not recommended instantiate the AHBBRIDGE
core and instead instantiate two uni-directional AHB to AHB bridges (AHB2AHB cores) with configurations tailored for a specific design.
5.2.2

Deadlock conditions

A deadlock situation can occur if the bridge is simultaneously accessed from both buses. The bridge
contains deadlock detection logic which will resolve a deadlock condition by giving a RETRY
response on the low-speed bus.
There are several deadlock conditions that can occur with locked accesses. If the VHDL generic lckdac is 0, the bridge will deadlock if two simultaneous accesses from both buses are locked, or if a
locked access is made while the bridge has issued a SPLIT response to a read access and the splitted
access has not completed. If lckdac is greater than 0, the bridge will resolve the deadlock condition
from two simultaneous locked accesses by giving an ERROR response on the low-speed bus. If lckdac is 1 and a locked access is made while the bridge has issued a SPLIT response to a read access,
the bridge will respond with ERROR to the incoming locked access. If lckdac is 2 the bridge will
allow both the locked access and the splitted read access to complete. Note that with lckdac set to 2
and two incoming locked accesses, the access on the low-speed bus will still receive an ERROR
response.
5.2.3

Read and write combining

The bridge can be configured to support read and write combining so that prefetch operations and
write bursts are always performed with the maximum access size possible on the master interface.
Please see the documentation for the uni-directional AHB/AHB bridge (AHB2AHB) for a description
of read and write combining and note that the same VHDL generics are used to specify both the maximum master and maximum slave access size on the bi-directional AHB/AHB bridge.
5.2.4

Endianness

The core is designed for big-endian systems

5.3

Registers
The core does not implement any registers.

5.4

Vendor and device identifiers
The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x020. For description of
vendor and device identifiers see GRLIB IP Library User’s Manual.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
5.5

Implementation
See documentation for AHB2AHB.

5.6

Configuration options
Table 42 shows the configuration options of the core (VHDL generics).
Table 42. Configuration options
Generic

Function

Allowed range

Default

memtech

Memory technology

ffact

Frequency ratio

hsb_hsindex

AHB slave index on the high-speed bus

0 to NAHBMAX-1

hsb_hmindex

AHB master index on the high-speed bus

0 to NAHBMAX-1

hsb_iclsize

Cache line size (in number of 32-bit words) for CPUs on
the high-speed bus. Determines the number of the words
that are prefetched by the bridge when CPU performs
instruction bursts.

4, 8

hsb_bank0

Address area 0 mapped on the high-speed bus and
decoded by the bridge’s slave interface on the low-speed
bus. Appears as memory address register (BAR0) on the
bridge’s low-speed bus slave interface. The generic has
the same bit layout as bank address registers with bits
[19:18] suppressed (use functions ahb2ahb_membar and
ahb2ahb_iobar in gaisler.misc package to generate this
generic).

0 - 1073741823

hsb_bank1

Address area 1 mapped on the high-speed bus

0 - 1073741823

hsb_bank2

Address area 2 mapped on the high-speed bus

0 - 1073741823

hsb_bank3

Address area 3 mapped on the high-speed bus

0 - 1073741823

hsb_ioarea

Address of high-speed bus I/O area that contains the
high-speed bus configuration area. Will appear in the
bridge’s user-defined register 1 on the low-speed bus.
Note that to allow low-speed bus masters to read the
high-speed bus configuration area, the area must be
mapped on one of the hsb_bank generics.

0 - 16#FFF#

lsb_hsindex

AHB slave index on the low-speed bus

0 to NAHBMAX-1

lsb_hmindex

AHB master index on the low-speed bus

0 to NAHBMAX-1

lsb_rburst

Size of the prefetch buffer for read transfers initiated on
the low-speed-bus and crossing the bridge.

16, 32

lsb_wburst

Size of the write buffer for write transfers initiated on the
low-speed bus and crossing the bridge.

16, 32

lsb_bank0

Address area 0 mapped on the low-speed bus and
decoded by the bridge’s slave interface on the high-speed
bus. Appears as memory address register (BAR0) on the
bridge’s high-speed bus slave interface. The generic has
the same bit layout as bank address registers with bits
[19:18] suppressed (use functions ahb2ahb_membar and
ahb2ahb_iobar in gaisler.misc package to generate this
generic).

0 - 1073741823

lsb_bank1

Address area 1 mapped on the low-speed bus

0 - 1073741823

lsb_bank2

Address area 2 mapped on the low-speed bus

0 - 1073741823

lsb_bank3

Address area 3 mapped on the low-speed bus

0 - 1073741823

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 42. Configuration options
Generic

Function

lsb_ioarea

Address of low-speed bus I/O area that contains the low- 0 - 16#FFF#
speed bus configuration area. Will appear in the bridge’s
user-defined register 1 on the high-speed bus. Note that
to allow high-speed bus masters to read the low-speed
bus configuration area, the area must be mapped on one
of the lsb_bank generics.

lckdac

Locked access error detection and correction. This
generic is mapped to the generic with the same name on
the two AHB2AHB cores instantiated by AHBBRIDGE.
Please see the documentation for the AHB2AHB core’s
VHDL generics for more information.

0-2

maccsz

This generic is propagated to the slvmaccsz and mstmaccsz VHDL generics on the two AHB2AHB cores
instantiated by AHBBRIDGE. The generic determines
the maximum AHB access size supported by the bridge.
Please see the documentation for the AHB2AHB core’s
VHDL generics for more information.

32 - 256

rdcomb

0-2
Read combining, this generic is mapped to the generic
with the same name on the two AHB2AHB cores instantiated by AHBBRIDGE. Please see the documentation
for the AHB2AHB core’s VHDL generics for more
information.

wrcomb

Write combining, this generic is mapped to the generic
0-2
with the same name on the two AHB2AHB cores instantiated by AHBBRIDGE. Please see the documentation
for the AHB2AHB core’s VHDL generics for more
information.

combmask

Read/Write combining mask, this generic is mapped to
0 - 16#FFFF#
the generic with the same name on the two AHB2AHB
cores instantiated by AHBBRIDGE. Please see the documentation for the AHB2AHB core’s VHDL generics for
more information.

16#FFFF#

allbrst

Support all burst types, this generic is mapped to the
generic with the same name on the two AHB2AHB cores
instantiated by AHBBRIDGE. Please see the documentation for the AHB2AHB core’s VHDL generics for
more information.

0-2

fcfs

First-come, first-served operation, this generic is mapped
to the generic with the same name on the two
AHB2AHB cores instantiated by AHBBRIDGE. Please
see the documentation for the AHB2AHB core’s VHDL
generics for more information.

0 - NAHBMST

scantest

Enable scan support

0-1

GRIP, Apr 2018, Version 2018.1

Allowed range

Default

www.cobham.com/gaisler

GRLIB IP Core
5.7

Signal descriptions
Table 43 shows the interface signals of the core (VHDL ports).
Table 43. Signal descriptions

5.8

Signal name

Type

Function

Active

RST

Input

Reset

Low

HSB_HCLK

Input

High-speed AHB clock

LSB_HCLK

Input

Low-speed AHB clock

HSB_AHBSI

Input

High-speed bus AHB slave input signals

HSB_AHBSO

Output

High-speed bus AHB slave output signals

HSB_AHBSOV

Input

High-speed bus AHB slave input signals

HSB_AHBMI

Input

High-speed bus AHB master input signals

HSB_AHBMO

Output

High-speed bus AHB master output signals

LSB_AHBSI

Input

Low-speed bus AHB slave input signals

LSB_AHBSO

Output

Low-speed bus AHB slave output signals

LSB_AHBSOV

Input

Low-speed bus AHB slave input signals

LSB_AHBMI

Input

Low-speed bus AHB master input signals

LSB_AHBMO

Output

Low-speed bus AHB master output signals

Library dependencies
Table 44 shows the libraries used when instantiating the core (VHDL libraries).
Table 44. Library dependencies
Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Signals

AMBA signal definitions

GAISLER

MISC

Component

Component declaration

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
6

AHBCTRL - AMBA AHB controller with plug&play support

6.1

Overview
The AMBA AHB controller is a combined AHB arbiter, bus multiplexer and slave decoder according
to the AMBA 2.0 standard.
The controller supports up to 16 AHB masters, and 16 AHB slaves. The maximum number of masters
and slaves are defined in the GRLIB.AMBA package, in the VHDL constants NAHBSLV and
NAHBMST. It can also be set with the nahbm and nahbs VHDL generics.

MASTER

AHBCTRL

ARBITER/
DECODER

SLAVE

Figure 10. AHB controller block diagram

6.2

Operation
6.2.1

Arbitration

The AHB controller supports two arbitration algorithms: fixed-priority and round-robin. The selection
is done by the VHDL generic rrobin. In fixed-priority mode (rrobin = 0), the bus request priority is
equal to the master’s bus index, with index 0 being the lowest priority. If no master requests the bus,
the master with bus index 0 (set by the VHDL generic defmast) will be granted.
In round-robin mode, priority is rotated one step after each AHB transfer. If no master requests the
bus, the last owner will be granted (bus parking). The VHDL generic mprio can be used to specify one
or more masters that should be prioritized when the core is configured for round-robin mode.
Note that there are AHB slaves that implement split-like functionality by giving AHB retry responses
until the access has finished and the original master tries again. All masters on the bus accessing such
slaves must be round-robin arbitrated without prioritization to avoid deadlock situations. For GRLIB
this applies to the GRPCI and GRPCI2 cores.
During incremental bursts, the AHB master should keep the bus request asserted until the last access
as recommended in the AMBA 2.0 specification, or it might loose bus ownership. For fixed-length
burst, the AHB master will be granted the bus during the full burst, and can release the bus request
immediately after the first access has started. For this to work however, the VHDL generic fixbrst
should be set to 1.
6.2.2

Decoding

Decoding (generation of HSEL) of AHB slaves is done using the plug&play method explained in the
GRLIB User’s Manual. A slave can occupy any binary aligned address space with a size of 1 - 4096
Mbyte. A specific I/O area is also decoded, where slaves can occupy 256 byte - 1 Mbyte. The default
address of the I/O area is 0xFFF00000, but can be changed with the ioaddr and iomask VHDL generics. Access to unused addresses will cause an AHB error response.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
The I/O area can be placed within a memory area occupied by a slave. The slave will not be selected
when the I/O area is accessed.
6.2.3

Plug&play information

GRLIB devices contain a number of plug&play information words which are included in the AHB
records they drive on the bus (see the GRLIB user’s manual for more information). These records are
combined into an array which is connected to the AHB controller unit.
The plug&play information is mapped on a read-only address area, defined by the cfgaddr and cfgmask VHDL generics, in combination with the ioaddr and iomask VHDL generics. By default, the
area is mapped on address 0xFFFFF000 - 0xFFFFFFFF. The master information is placed on the first
2 kbyte of the block (0xFFFFF000 - 0xFFFFF800), while the slave information is placed on the second 2 kbyte block. Each unit occupies 32 bytes, which means that the area has place for 64 masters
and 64 slaves. The address of the plug&play information for a certain unit is defined by its bus index.
The address for masters is thus 0xFFFFF000 + n*32, and 0xFFFFF800 + n*32 for slaves.

31
Identification Register

24 23
VENDOR ID

12 11 10 9
DEVICE ID

USER-DEFINED

IRQ

5 4
VERSION

0
IRQ

BAR0 10

HADDR
ADDR

P C

MASK
MASK

TYPE

BAR1 14

ADDR

P C

MASK

TYPE

BAR2 18

ADDR

P C

MASK

TYPE

BAR3 1C

ADDR

P C

MASK

TYPE

Bank Address Registers

20 19 18 17 16 15
P = Prefetchable
C = Cacheable

4 3

TYPE
0001 = APB I/O space
0010 = AHB Memory space
0011 = AHB I/O space

Figure 11. AHB plug&play information record

6.3

AHB split support
AHB SPLIT functionality is supported if the split VHDL generic is set to 1. In this case, all slaves
must drive the AHB SPLIT signal.
It is important to implement the split functionality in slaves carefully since locked splits can otherwise
easily lead to deadlocks. A locked access to a slave which is currently processing (it has returned a
split response but not yet split complete) an access which it returned split for to another master must
be handled first. This means that the slave must either be able to return an OKAY response to the
locked access immediately or it has to split it but return split complete to the master performing the
locked transfer before it has finished the first access which received split.

6.4

Locked accesses
The GRLIB AHB controller treats HLOCK as coupled to a specific access. If a previous access by a
master received a SPLIT/RETRY response then the arbiter will disregard the current value of
HLOCK. This is done as opposed to always treating HLOCK as being valid for the next access which
can result in a previously non-locked access being treated as locked when it is retried. Consider the
following sequence:

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
T0: MSTx write 0
T1: MSTx write 1, HLOCK asserted as next access performed by master will be locked
T2: MSTx locked read
If (the non-locked) write 0 access at T0 receives a RETRY or SPLIT response (given at time T1), then
the next access to be performed may be a retry of write 0. In this case the arbiter will disregard the
HLOCK setting and the retried access will not have HMASTLOCK set.

6.5

AHB bus monitor
An AHB bus monitor is integrated into the core. It is enabled with the enbusmon generic. It has the
same functionality as the AHB and arbiter parts in the AMBA monitor core (AMBAMON). For more
information on which rules are checked se the AMBAMON documentation.

6.6

Registers
The core does not implement any registers.

6.7

Implementation
6.7.1

Reset

The core changes reset behaviour depending on settings in the GRLIB configuration package (see
GRLIB User’s Manual).
The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set.
The core will use asynchronous reset for all registers if the GRLIB config package setting grlib_async_reset_enable is set.

6.8

Configuration options
Table 45 shows the configuration options of the core (VHDL generics).
Table 45. Configuration options
Generic

Function

Allowed range

Default

ioaddr

The MSB address of the I/O area. Sets the 12 most significant bits in the 32-bit AHB address (i.e. 31 downto
20)

0 - 16#FFF#

16#FFF#

iomask

The I/O area address mask. Sets the size of the I/O area
and the start address together with ioaddr.

0 - 16#FFF#

16#FFF#

cfgaddr

The MSB address of the configuration area. Sets 12 bits
in the 32-bit AHB address (i.e. 19 downto 8).

0 - 16#FFF#

16#FF0#

cfgmask

The address mask of the configuration area. Sets the size
of the configuration area and the start address together
with cfgaddr. If set to 0, the configuration will be disabled.

0 - 16#FFF#

16#FF0#

rrobin

Selects between round-robin (1) or fixed-priority (0) bus
arbitration algorithm.

0-1

split

Enable support for AHB SPLIT response

0-1

defmast

Default AHB master

0 - NAHBMST-1

ioen

AHB I/O area enable. Set to 0 to disable the I/O area

0-1

disirq

Set to 1 to disable interrupt routing

0-1

nahbm

Number of AHB masters

1 - NAHBMST

NAHBMST

nahbs

Number of AHB slaves

1 - NAHBSLV

NAHBSLV

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 45. Configuration options
Generic

Function

Allowed range

Default

timeout
fixbrst

Perform bus timeout checks (NOT IMPLEMENTED).

0-1

Enable support for fixed-length bursts

0-1

debug

Print configuration (0=none, 1=short, 2=all cores)

0-2

fpnpen

Enables full decoding of the PnP configuration records. 0 - 1
When disabled the user-defined registers in the PnP configuration records are not mapped in the configuration
area.

icheck

Check bus index

0-1

devid

Assign unique device identifier readable from plug and
play area.

N/A

enbusmon

Enable AHB bus monitor

0-1

assertwarn

Enable assertions for AMBA recommendations. Violations are asserted with severity warning.

0-1

asserterr

Enable assertions for AMBA requirements. Violations
are asserted with severity error.

0-1

hmstdisable

Disable AHB master rule check. To disable a master rule
check a value is assigned so that the binary representation contains a one at the position corresponding to the
rule number, e.g 0x80 disables rule 7.

N/A

hslvdisable

Disable AHB slave tests. Values are assigned as for
hmstdisable.

N/A

arbdisable

Disable Arbiter tests. Values are assigned as for hmstdis- N/A
able.

mprio

Master(s) with highest priority. This value is converted
to a vector where each position corresponds to a master.
To prioritize masters x and y set this generic to 2x + 2y.

N/A

mcheck

Check if there are any intersections between core mem- 0 - 2
ory areas. If two areas intersect an assert with level failure will be triggered (in simulation). mcheck = 1 does
not report intersects between AHB IO areas and AHB
memory areas (as IO areas are allowed to override memory areas). mcheck = 2 triggers on all overlaps.

See also documentation of VHDL generic shadow
below.
ccheck

Perform sanity checks on PnP configuration records (in
simulation).

0-1

acdm

AMBA compliant data multiplexing (for HSIZE >
word). If this generic is set to 1, and the AMBA bus data
width in the system exceeds 32-bits, the core will ensure
AMBA compliant data multiplexing for access sizes
(HSIZE) over 32-bits. GRLIB cores have an optimization where they drive the same data on all lanes. Read
data is always taken from the lowest lanes. If an AMBA
compliant core from another vendor is introduced in the
design, that core may not always place valid data on the
low part of the bus. By setting this generic to 1, the
AHBCTRL core will replicate the data, allowing the
non-GRLIB cores to be instantiated without modification.

0-1

index

AHB index for trace print-out, currently unused

N/A

ahbtrace

AHB trace print-out to simulator console in simulation.

0-1

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
Table 45. Configuration options
Generic

Function

Allowed range

Default

hwdebug

Enable hardware debug registers. If this generic is set to
1 the configuration area will include to diagnostic registers at offsets 0xFF4 and 0xFF8.

0-1

Offset 0xFF4 will show a 32-bit register where bit n
shows the current status of AHB master n’s HBUSREQ
signal.
Offset 0xFF8 will show a 32-bit register where bit n
shows the current SPLIT status of AHB master n. The bit
will be set when AHB master n receives a SPLIT reply
and will be re-set to ‘0’ when HSPLIT for AHB master n
has been asserted.
This functionality is not intended to be used in production systems but can provide valuable information while
debugging systems with cores that have problems with
AMBA SPLIT replies.
fourgslave

Allow and optimize for case with one single slave that
has one 4 GiB bar

0-1

shadow

Allow memory areas to shadow other memory areas. If
this generic is set to 0 and two slaves map the same
memory area then HSEL/HMBSEL signals will be
asserted for both memory bars / slaves.

0-1

This may lead to system malfunctions and causes a simulation failure if the mcheck VHDL generic is set to a
non-zero value. If the shadow generic is set to 1 then
memory area intersects are allowed and only the lowest
HSEL and HMBSEL (HSEL has priority) will be
asserted - only the slave or bar with the lowest index will
be selected instead of both slaves / bars. The mcheck
simulation failure will instead be asserted as a note about
intersecting memory areas.
Also note that intersections of cacheable and noncacheable areas will be treated as cacheable by GRLB cores
that decode the plug&play information. If a non-cacheable area is placed in a cacheable area then it is recommended to use fixed cacheability.
unmapslv

6.9

If this generic is non-zero then accesses to unmapped
address space (address space not occupied by any slave)
will be redirected to the slave and bar selected via:
256+bar*32+slv.

Signal descriptions
Table 46 shows the interface signals of the core (VHDL ports).
Table 46. Signal descriptions
Signal name

Field

Type

Function

Active

RST

N/A

Input

AHB reset

Low

CLK

N/A

Input

AHB clock

MSTI

Output

AMBA AHB master interface record array

MSTO

Input

AMBA AHB master interface record array

SLVI

Output

AMBA AHB slave interface record array

SLVO

Input

AMBA AHB slave interface record array

* see GRLIB IP Library User’s Manual

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
6.10

Library dependencies
Table 47 shows libraries used when instantiating the core (VHDL libraries).
Table 47. Library dependencies

6.11

Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Types

AMBA signal type definitions

Component declaration
library grlib;
use grlib.amba.all;
component ahbctrl
generic (
defmast : integer := 0;-- default master
split
: integer := 0;-- split support
rrobin : integer := 0;-- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#;
-- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address maskk
nahbm
: integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs
: integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen
: integer range 0 to 15 := 1;
-- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- print configuration to consolee
fpnpen : integer range 0 to 1 := 0;
-- full PnP configuration decoding
icheck : integer range 0 to 1 := 1
devid
: integer := 0;
-- unique device ID
enbusmon
: integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr
: integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio
: integer := 0; --master with highest priority
enebterm
: integer range 0 to 1 := 0 --enable early burst termination
);
port (
rst
: in std_ulogic;
clk
: in std_ulogic;
msti
: out ahb_mst_in_type;
msto
: in ahb_mst_out_vector;
slvi
: out ahb_slv_in_type;
slvo
: in ahb_slv_out_vector;
testen : in std_ulogic := ’0’;
testrst : in std_ulogic := ’1’;
scanen : in std_ulogic := ’0’;
testoen : in std_ulogic := ’1’
);
end component;

6.12

Instantiation
This example shows the core can be instantiated.
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
.
.
-- AMBA signals
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
begin
-- ARBITER
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, nahbm => 8, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);

-- AHB slave
sr0 : srctrl generic map (hindex => 3)
port map (rstn, clkm, ahbsi, ahbso(3), memi, memo, sdo3);
-- AHB master
e1 : eth_oc
generic map (mstndx => 2, slvndx => 5, ioaddr => CFG_ETHIO, irq => 12, memtech =>
memtech)
port map (rstn, clkm, ahbsi, ahbso(5), ahbmi => ahbmi,
ahbmo => ahbmo(2), ethi1, etho1);
...
end;

6.13

Debug print-out
If the debug generic is set to 2, the plug&play information of all attached AHB units are printed to the
console during the start of simulation. Reporting starts by scanning the master interface array from 0
to NAHBMST - 1 (defined in the grlib.amba package). It checks each entry in the array for a valid
vendor-id (all nonzero ids are considered valid) and if one is found, it also retrieves the device-id. The
descriptions for these ids are obtained from the GRLIB.DEVICES package, and are then printed on
standard out together with the master number. If the index check is enabled (done with a VHDL
generic), the report module also checks if the hindex number returned in the record matches the array
number of the record currently checked (the array index). If they do not match, the simulation is
aborted and an error message is printed.
This procedure is repeated for slave interfaces found in the slave interface array. It is scanned from 0
to NAHBSLV - 1 and the same information is printed and the same checks are done as for the master
interfaces. In addition, the address range and memory type is checked and printed. The address information includes type, address, mask, cacheable and pre-fetchable fields. From this information, the
report module calculates the start address of the device and the size of the range. The information
finally printed is type, start address, size, cacheability and pre-fetchability. The address ranges currently defined are AHB memory, AHB I/O and APB I/O. APB I/O ranges are ignored by this module.
# vsim -c -quiet leon3mp
VSIM 1> run
# LEON3 MP Demonstration design
# GRLIB Version 1.0.7
# Target technology: inferred, memory library: inferred
# ahbctrl: AHB arbiter/multiplexer rev 1
# ahbctrl: Common I/O area disabled
# ahbctrl: Configuration area at 0xfffff000, 4 kbyte
# ahbctrl: mst0: Cobham Gaisler
Leon3 SPARC V8 Processor
# ahbctrl: mst1: Cobham Gaisler
AHB Debug UART
# ahbctrl: slv0: European Space Agency
Leon2 Memory Controller

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#

ahbctrl:
memory at 0x00000000, size 512 Mbyte, cacheable, prefetch
ahbctrl:
memory at 0x20000000, size 512 Mbyte
ahbctrl:
memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch
ahbctrl: slv1: Cobham Gaisler
AHB/APB Bridge
ahbctrl:
memory at 0x80000000, size 1 Mbyte
apbctrl: APB Bridge at 0x80000000 rev 1
apbctrl: slv0: European Space Agency
Leon2 Memory Controller
apbctrl:
I/O ports at 0x80000000, size 256 byte
apbctrl: slv1: Cobham Gaisler
Generic UART
apbctrl:
I/O ports at 0x80000100, size 256 byte
apbctrl: slv2: Cobham Gaisler
Multi-processor Interrupt Ctrl.
apbctrl:
I/O ports at 0x80000200, size 256 byte
apbctrl: slv3: Cobham Gaisler
Modular Timer Unit
apbctrl:
I/O ports at 0x80000300, size 256 byte
apbctrl: slv7: Cobham Gaisler
AHB Debug UART
apbctrl:
I/O ports at 0x80000700, size 256 byte
apbctrl: slv11: Cobham Gaisler
General Purpose I/O port
apbctrl:
I/O ports at 0x80000b00, size 256 byte
grgpio11: 8-bit GPIO Unit rev 0
gptimer3: GR Timer Unit rev 0, 8-bit scaler, 2 32-bit timers, irq 8
irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1
apbuart1: Generic UART rev 1, fifo 4, irq 2
ahbuart7: AHB Debug UART rev 0
leon3_0: LEON3 SPARC V8 processor rev 0
leon3_0: icache 1*8 kbyte, dcache 1*8 kbyte

VSIM 2>

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
7

AHBJTAG - JTAG Debug Link with AHB Master Interface

7.1

Overview
The JTAG debug interface provides access to on-chip AMBA AHB bus through JTAG. The JTAG
debug interface implements a simple protocol which translates JTAG instructions to AHB transfers.
Through this link, a read or write transfer can be generated to any address on the AHB bus.
TDI

TCK
TMS

JTAG TAP
Controller

JTAG Communication
Interface

TDO

AHB master interface

AMBA AHB

Figure 12. JTAG Debug link block diagram

7.2

Operation
7.2.1

Transmission protocol

The JTAG Debug link decodes two JTAG instructions and implements two JTAG data registers: the
command/address register and data register. A read access is initiated by shifting in a command consisting of read/write bit, AHB access size and AHB address into the command/address register. The
AHB read access is performed and data is ready to be shifted out of the data register. Write access is
performed by shifting in command, AHB size and AHB address into the command/data register followed by shifting in write data into the data register. Sequential transfers can be performed by shifting
in command and address for the transfer start address and shifting in SEQ bit in data register for following accesses. The SEQ bit will increment the AHB address for the subsequent access. Sequential
transfers should not cross a 1 kB boundary. Sequential transfers are always word based.
Table 48. JTAG debug link Command/Address register
34 33 32 31
W

SIZE

AHB ADDRESS

Write (W) - ‘0’ - read transfer, ‘1’ - write transfer

33 32

AHB transfer size - “00” - byte, “01” - half-word, “10” - word, “11”- reserved

31 30

AHB address

Table 49. JTAG debug link Data register
32

SEQ

AHB DATA

Sequential transfer (SEQ) - If ‘1’ is shifted in this bit position when read data is shifted out or write
data shifted in, the subsequent transfer will be to next word address. When read out from the device,
this bit is ‘1’ if the AHB access has completed and ‘0’ otherwise.

31 30

AHB Data - AHB write/read data. For byte and half-word transfers data is aligned according to bigendian order where data with address offset 0 data is placed in MSB bits.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
As of version 1 of the JTAG debug link the core will signal AHB access completion by setting bit 32
of the data register. In previous versions the debug host could not determine if an AHB accesses had
finished when the read data was shifted out of the JTAG debug link data register. As of version 1 a
debug host can look at bit 32 of the received data to determine if the access was successful. If bit 32 is
‘1’ the access completed and the data is valid. If bit 32 is ‘0’, the AHB access was not finished when
the host started to read data. In this case the host can repeat the read of the data register until bit 32 is
set to ‘1’, signaling that the data is valid and that the AMBA AHB access has completed.
It should be noted that while bit 32 returns ‘0’, new data will not be shifted into the data register. The
debug host should therefore inspect bit 32 when shifting in data for a sequential AHB access to see if
the previous command has completed. If bit 32 is ‘0’, the read data is not valid and the command just
shifted in has been dropped by the core.
Inspection of bit 32 should not be done for JTAG Debug links with version number 0.
7.2.2

Endianness

The core is designed for big-endian systems.

7.3

Implementation
7.3.1

Clocking

Except for the TAP state machine and instruction register, the JTAG debug link operates in the
AMBA clock domain. To detect when to shift the address/data register, the JTAG clock and TDI are
resynchronized to the AMBA domain. The JTAG clock must be less than 1/3 of the AHB clock frequency for the debug link commands to work when nsync=2, and less than 1/2 of the AHB frequency
when nsync=1.
7.3.2

Reset

The core does not change reset behaviour depending on settings in the GRLIB configuration package
(see GRLIB User’s Manual). Registers in the JTAG clock domain have asynchronous reset connected
to the JTAG trst. Registers in the system clock domain have synchronous reset.

7.4

Registers
The core does not implement any registers mapped in the AMBA AHB or APB address space.

7.5

Vendor and device identifiers
The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x01C. For description of
vendor and device identifiers see GRLIB IP Library User’s Manual.

7.6

Implementation
7.6.1

Reset

The core changes reset behaviour depending on settings in the GRLIB configuration package (see
GRLIB User’s Manual).
The core will add reset for all registers, except synchronization registers, if the GRLIB config package setting grlib_sync_reset_enable_all is set.
The core does not support the GRLIB config package setting grlib_async_reset_enable.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
7.7

Configuration options
Table 50 shows the configuration options of the core (VHDL generics).
Table 50. Configuration options
Generic

Function

Allowed range

Default

tech

Target technology

0 - NTECH

hindex

AHB master index

0 - NAHBMST-1

nsync

Number of synchronization registers between clock
regions

1-2

idcode

JTAG IDCODE instruction code (generic tech only)

0 - 255

manf

Manufacturer id. Appears as bits 11-1 in TAP controllers 0 - 2047
device identification register. Used only for generic technology. Default is Cobham Gaisler manufacturer id.

804

part

Part number (generic tech only). Bits 27-12 in device id.
reg.

0 - 65535

ver

Version number (generic tech only). Bits 31-28 in device
id. reg.

0 - 15

ainst

Code of the JTAG instruction used to access JTAG
Debug link command/address register. 
For Actel TAPs (tech VHDL generic is set to an Actel
technology) this generic should be set to 16, for all other
technologies the default value (2) can be used.

0 - 255

dinst

Code of the JTAG instruction used to access JTAG
Debug link data register
For Actel TAPs (tech VHDL generic is set to an Actel
technology) this generic should be set to 17, for all other
technologies the default value (3) can be used.

0 - 255

scantest

Enable scan test support

0-1

oepol

Output enable polarity for TDOEN

0-1

tcknen

Support externally inverted TCK (generic tech only)

0-1

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
7.8

Signal descriptions
Table 51 shows the interface signals of the core (VHDL ports).
Table 51. Signal descriptions
Signal name

Field

Type

Function

Active

RST

N/A

Input

Reset

Low

CLK

N/A

Input

System clock (AHB clock domain)

TCK

N/A

Input

JTAG clock*

TMS

N/A

Input

JTAG TMS signal*

High

TDI

N/A

Input

JTAG TDI signal*

High

TDO

N/A

Output

JTAG TDO signal*

High

AHBI

***

Input

AHB Master interface input

AHBO

***

Output

AHB Master interface output

TAPO_TCK

N/A

Output

TAP Controller User interface TCK signal**

High

TAPO_TDI

N/A

Output

TAP Controller User interface TDI signal**

High

TAPO_INST[7:0]

N/A

Output

TAP Controller User interface INSTsignal**

High

TAPO_RST

N/A

Output

TAP Controller User interface RST signal**

High

TAPO_CAPT

N/A

Output

TAP Controller User interface CAPT signal**

High

TAPO_SHFT

N/A

Output

TAP Controller User interface SHFT signal**

High

TAPO_UPD

N/A

Output

TAP Controller User interface UPD signal**

High

TAPI_TDO

N/A

Input

TAP Controller User interface TDO signal**

High

TRST

N/A

Input

JTAG TRST signal

Low

TDOEN

N/A

Output

Output-enable for TDO

See oepol

TCKN

N/A

Input

Inverted JTAG clock* (if tcknen is set)

TAPO_TCKN

N/A

Output

TAP Controller User interface TCKN signal**

High

TAPO_NINST

N/A

Output

TAP Controller User interface NINSTsignal**

High

TAPO_IUPD

N/A

Output

TAP Controller User interface IUPD signal**

High

*) If the target technology is Xilinx or Altera the cores JTAG signals TCK, TCKN, TMS, TDI and TDO are not used.
Instead the dedicated FPGA JTAG pins are used. These pins are implicitly made visible to the core through TAP controller
instantiation.
**) User interface signals from the JTAG TAP controller. These signals are used to interface additional user defined JTAG
data registers such as boundary-scan register. For more information on the JTAG TAP controller user interface see JTAG
TAP Controller IP-core documentation. If not used tie TAPI_TDO to ground and leave TAPO_* outputs unconnected.
***) see GRLIB IP Library User’s Manual

7.9

Signal definitions and reset values
The signals and their reset values are described in table 52.
Table 52. Signal definitions and reset values
Signal name

Type

Function

Active

Reset value

dsutck

Input

JTAG clock

dsutms

Input

JTAG TMS

High

dsutdi

Input

JTAG TDI

High

dsutdo

Output

JTAG TDO

High

undefined

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
7.10

Timing
The timing waveforms and timing parameters are shown in figure 13 and are defined in table 53.
tAHBJTAG0

tAHBJTAG1

dsutck
tAHBJTAG2
dsutdi, dsutms
tAHBJTAG4

tAHBJTAG3

dsutdo
Figure 13. Timing waveforms
Table 53. Timing parameters

7.11

Name

Parameter

Reference edge

Min

Max

Unit

tAHBJTAG0

clock period

TBD

tAHBJTAG1

clock low/high period

TBD

tAHBJTAG2

data input to clock setup

rising dsutck edge

TBD

tAHBJTAG3

data input from clock hold

rising dsutck edge

TBD

tAHBJTAG4

clock to data output delay

falling dsutck edge

TBD

Library dependencies
Table 54 shows libraries used when instantiating the core (VHDL libraries).
Table 54. Library dependencies

7.12

Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Signals

AMBA signal definitions

GAISLER

JTAG

Signals, component

Signals and component declaration

Instantiation
This example shows how the core can be instantiated.
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.jtag.all;
entity ahbjtag_ex is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
-- JTAG signals
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of ahbjtag_ex is

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
-- AMBA signals
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal gnd : std_ulogic;
constant clkperiod : integer := 100;
begin
gnd <= ‘0’;
-- AMBA Components are instantiated here
...
-- AHB JTAG
ahbjtag0 : ahbjtag generic map(tech => 0, hindex => 1)
port map(rstn, clkm, tck, tckn, tms, tdi, tdo, ahbmi, ahbmo(1),
open, open, open, open, open, open, open, gnd);

jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;

7.13

Simulation
DSU communication over the JTAG debug link can be simulated using jtagcom procedure. The jtagcom procedure sends JTAG commands to the AHBJTAG on JTAG signals TCK, TMS, TDI and TDO.
The commands read out and report the device identification code, optionally put the CPU(s) in debug
mode, perform three write operations to the memory and read out the data from the memory. The
JTAG test works if the generic JTAG tap controller is used and will not work with built-in TAP macros (such as Altera and Xilinx JTAG macros) since these macros don’t have visible JTAG pins. The
jtagcom procedure is part of jtagtst package in gaisler library and has following declaration:
procedure jtagcom(signal tdo
: in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp, start, addr
: in integer;
-- cp - TCK clock period in ns
-- start - time in us when JTAG test is started
-- addr - read/write operation destination address
haltcpu
: in boolean);

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
8

AHBRAM - Single-port RAM with AHB interface

8.1

Overview
AHBRAM implements on-chip RAM with an AHB slave interface. Memory size is configurable in
binary steps through a VHDL generic. Minimum size is 1KiB and maximum size is dependent on target technology and physical resources. Read accesses have zero or one waitstate (configured at implementation time), write access have one waitstate. The RAM supports byte- and half-word accesses, as
well as all types of AHB burst accesses.
Internally, the AHBRAM instantiates a SYNCRAM block with byte writes. Depending on the target
technology map, this will translate into memory with byte enables or to multiple 8-bit wide SYNCRAM blocks.
The size of the RAM implemented within AHBRAM can be read via the core’s AMBA plug&play
version field. The version field will display log2(number of bytes), for a 1 KiB SYNCRAM the version field will have the value 10, where 210 = 1024 bytes = 1 KiB.
8.1.1

Endianness

The core is designed for big-endian systems.

8.2

Vendor and device identifiers
The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x00E. For description of
vendor and device identifiers see GRLIB IP Library User’s Manual.

8.3

Implementation
8.3.1

Reset

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
8.4

Configuration options
Table 55 shows the configuration options of the core (VHDL generics).
Table 55. Configuration options

8.5

Generic

Function

Allowed range

Default

hindex

AHB slave bus index

0 - NAHBSLV-1

haddr

The MSB address of the AHB area. Sets the 12 most sig- 0 - 16#FFF#
nificant bits in the 32-bit AHB address.

16#FFF#

hmask

The AHB area address mask. Sets the size of the AHB
area and the start address together with haddr.

0 - 16#FFF#

16#FF0#

tech

Technology to implement on-chip RAM

0 - NTECH

kbytes

RAM size in KiB. The size of the RAM implemented
will be the minumum size that will hold the size specified by kbytes. A value of 1 here will instantiate a 1 KiB
SYNCRAM, a value of 3 will instantiate a 4 KiB SYNCRAM. The actual RAM usage on the target technology
then depends on the available RAM resources and the
technology map.

target-dependent

pipe

Add registers on data outputs. If set to 0 the AMBA data
outputs will be connected directly to the core’s internal
RAM. If set to 1 the core will include registers on the
data outputs. Settings this generic to 1 makes read
accesses have one waitstate, otherwise the core will
respond to read accesses with zero waitstates.

0-1

maccsz

Maximum access size supported. This generic restricts
the maximum AMBA access size supported by the core
and selects the width of the SYNCRAMBW RAM used
internally. The default value is assigned from AHBDW,
which sets the maximum bus width for the GRLIB
design.

32, 64, 128, 256

AHBDW

scantest

Enable scan test support (passed on to syncram)

0-1

Signal descriptions
Table 56 shows the interface signals of the core (VHDL ports).
Table 56. Signal descriptions
Signal name

Field

Type

Function

Active

RST

N/A

Input

Reset

Low

CLK

N/A

Input

Clock

AHBSI

Input

AMB slave input signals

AHBSO

Output

AHB slave output signals

* see GRLIB IP Library User’s Manual

8.6

Library dependencies
Table 57 shows libraries used when instantiating the core (VHDL libraries).
Table 57. Library dependencies
Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Types

AMBA signal type definitions

GAISLER

MISC

Component

Component declaration

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
8.7

Component declaration
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
component ahbram
generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#;
tech : integer := 0; kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;

8.8

Instantiation
This example shows how the core can be instantiated.
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
.
.
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => 8)
port map ( rstn, clkm, ahbsi, ahbso(7));

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
9

AHBDPRAM - Dual-port RAM with AHB interface

9.1

Overview
AHBDPRAM implements a 32-bit wide on-chip RAM with one AHB slave interface port and one
back-end port for a user application. The AHBDPRAM is therefore useful as a buffer memory
between the AHB bus and a custom IP core with a RAM interface
The memory size is configurable in binary steps through the abits VHDL generic. The minimum size
is 1kB while maximum size is dependent on target technology and physical resources. Read accesses
are zero-waitstate, write access have one waitstate. The RAM optionally supports byte- and half-word
accesses, as well as all types of AHB burst accesses. Internally, the AHBRAM instantiates one 32-bit
or four 8-bit wide SYNCRAM_DP blocks. The target technology must have support for dual-port
RAM cells.
The back-end port consists of separate clock, address, datain, dataout, enable and write signals. All
these signals are sampled on the rising edge of the back-end clock (CLKDP), implementing a synchronous RAM interface. Read-write collisions between the AHB port and the back-end port are not
handled and must be prevented by the user. If byte write is enabled, the WRITE(0:3) signal controls
the writing of each byte lane in big-endian fashion. WRITE(0) controls the writing of
DATAIN(31:24) and so on. If byte write is disabled, WRITE(0) controls writing to the complete 32bit word.
9.1.1

Endianness

The core is designed for big-endian systems.

9.2

Vendor and device identifiers
The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x00F. For description of
vendor and device identifiers see GRLIB IP Library User’s Manual.

9.3

Implementation
9.3.1

Reset

The core does not change reset behaviour depending on settings in the GRLIB configuration package
(see GRLIB User’s Manual). The core makes use of synchronous reset.

9.4

Configuration options
Table 58 shows the configuration options of the core (VHDL generics).
Table 58. Configuration options
Generic

Function

Allowed range

Default

hindex

AHB slave bus index

0 - NAHBSLV-1

haddr

The MSB address of the AHB area. Sets the 12 most sig- 0 - 16#FFF#
nificant bits in the 32-bit AHB address.

16#FFF#

hmask

The AHB area address mask. Sets the size of the AHB
area and the start address together with haddr.

0 - 16#FFF#

16#FF0#

tech

Technology to implement on-chip RAM

0 - NTECH

abits

Address bits. The RAM size in Kbytes is equal to
2**(abits +2)

8 - 19

bytewrite

If set to 1, enabled support for byte and half-word writes

0-1

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
9.5

Signal descriptions
Table 59 shows the interface signals of the core (VHDL ports).
Table 59. Signal descriptions
Signal name

Field

Type

Function

Active

RST

N/A

Input

AHB Reset

Low

CLK

N/A

Input

AHB Clock

AHBSI

Input

AMB slave input signals

AHBSO

Output

AHB slave output signals

CLKDP

Input

Clock for back-end port

ADDRESS(abits-1:0)

Input

Address for back-end port

DATAIN(31 : 0)

Input

Write data for back-end port

DATAOUT(31 : 0)

Output

Read data from back-end port

ENABLE

Input

Chip select for back-end port

High

WRITE(0 : 3)

Input

Write-enable byte select for back-end port

High

* see GRLIB IP Library User’s Manual

9.6

Library dependencies
Table 60 shows libraries used when instantiating the core (VHDL libraries).
Table 60. Library dependencies

9.7

Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Types

AMBA signal type definitions

GAISLER

MISC

Component

Component declaration

Component declaration
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
component ahbdpram
generic (
hindex : integer := 0;
haddr
: integer := 0;
hmask
: integer := 16#fff#;
tech
: integer := 2;
abits
: integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst
: in std_ulogic;
clk
: in std_ulogic;
ahbsi
: in ahb_slv_in_type;
ahbso
: out ahb_slv_out_type;
clkdp
: in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic;-- active high chip select
write : in std_logic_vector(0 to 3)-- active high byte write enable
);
end component;

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
10

AHBROM - Single-port ROM with AHB interface

10.1

Overview
The AHBROM core implements a 32/64/128-bit wide on-chip ROM with an AHB slave interface.
Read accesses take zero waitstates, or one waitstate if the pipeline option is enabled. The ROM supports byte- and half-word accesses, as well as all types of AHB burst accesses.

10.2

PROM generation
The AHBPROM is automatically generated by the make utility in GRLIB. The input format is a
sparc-elf binary file, produced by the BCC cross-compiler (sparc-elf-gcc). To create a PROM, first
compile a suitable binary and the run the make utility:
bash$ sparc-elf-gcc prom.S -o prom.exe
bash$ make ahbrom.vhd
Creating ahbrom.vhd : file size 272 bytes, address bits 9

The default binary file for creating a PROM is prom.exe. To use a different file, run make with the
FILE parameter set to the input file:
bash$ make ahbrom.vhd FILE=myfile.exe

The created PROM is realized in synthesizable VHDL code, using a CASE statement. For FPGA targets, most synthesis tools will map the CASE statement on a block RAM/ROM if available. For ASIC
implementations, the ROM will be synthesized as gates. It is then recommended to use the pipe option
to improve the timing.
The default is to build a 32-bit wide ahbrom, to instead build 64-bit or 128-bit wide ahbrom versions,
use the flow described above but with the “make ahbrom64.vhd” and “make ahbrom128.vhd” make
targets.
10.2.1 Endianness
The core is designed for big-endian systems.

10.3

Vendor and device identifiers
The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x01B. For description of
vendor and device identifiers see GRLIB IP Library User’s Manual.

10.4

Implementation
10.4.1 Reset
The core changes reset behaviour depending on settings in the GRLIB configuration package (see
GRLIB User’s Manual).
The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set.
The core does not support the GRLIB config package setting grlib_async_reset_enable.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
10.5

Configuration options
Table 61 shows the configuration options of the core (VHDL generics).
Table 61. Configuration options
Generic

Function

Allowed range

Default

hindex

AHB slave bus index

0 - NAHBSLV-1

haddr

The MSB address of the AHB area. Sets the 12 most sig- 0 - 16#FFF#
nificant bits in the 32-bit AHB address.

16#FFF#

hmask

The AHB area address mask. Sets the size of the AHB
area and the start address together with haddr.

0 - 16#FFF#

16#FF0#

tech

Not used
0

0-1

pipe

Add a pipeline stage on read data

kbytes

Not used

Only on ahbrom64 and ahbrom128:
wideonly

10.6

Removes muxing logic needed to properly support 32-bit
masters on wide bus

Signal descriptions
Table 62 shows the interface signals of the core (VHDL ports).
Table 62. Signal descriptions
Signal name

Field

Type

Function

Active

RST

N/A

Input

Reset

Low

CLK

N/A

Input

Clock

AHBSI

Input

AMB slave input signals

AHBSO

Output

AHB slave output signals

* see GRLIB IP Library User’s Manual

10.7

Library dependencies
Table 63 shows libraries used when instantiating the core (VHDL libraries).
Table 63. Library dependencies

10.8

Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Types

AMBA signal type definitions

Component declaration
component ahbrom
generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#;
pipe : integer := 0; tech : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
10.9

Instantiation
This example shows how the core can be instantiated.
library grlib;
use grlib.amba.all;
.
.
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
11

AHBSTAT - AHB Status Registers

11.1

Overview
The status registers store information about AMBA AHB accesses triggering an error response. There
is a status register and a failing address register capturing the control and address signal values of a
failing AMBA bus transaction, or the occurrence of a correctable error being signaled from a another
peripheral in the system.
The status register and the failing address register are accessed from the AMBA APB bus.

11.2

Operation
11.2.1 Errors
The registers monitor AMBA AHB bus transactions and store the current HADDR, HWRITE,
HMASTER and HSIZE internally. The monitoring are always active after startup and reset until an
error response (HRESP = “01”) is detected. When the error is detected, the status and address register
contents are frozen and the New Error (NE) bit is set to one. At the same time an interrupt is generated, as described hereunder.
Note that many of the fault tolerant units containing EDAC signal an un-correctable error as an
AMBA error response, so that it can be detected by the processor as described above.
11.2.2 Correctable errors
Not only error responses on the AHB bus can be detected. Many of the fault tolerant units containing
EDAC have a correctable error signal which is asserted each time a correctable error is detected.
When such an error is detected, the effect will be the same as for an AHB error response. The only difference is that the Correctable Error (CE) bit in the status register is set to one when a correctable
error is detected.
When the CE bit is set the interrupt routine can acquire the address containing the correctable error
from the failing address register and correct it. When it is finished it resets the NE bit and the monitoring becomes active again. Interrupt handling is described in detail hereunder.
The correctable error signals from the fault tolerant units should be connected to the stati.cerror input
signal vector of the AHB status register core, which is or-ed internally and if the resulting signal is
asserted, it will have the same effect as an AHB error response.
11.2.3 Interrupts
The interrupt is generated on the line selected by the pirq VHDL generic.
The interrupt is connected to the interrupt controller to inform the processor of the error condition.
The normal procedure is that an interrupt routine handles the error with the aid of the information in
the status registers. When it is finished it resets the NE bit and the monitoring becomes active again.
Interrupts are generated for both AMBA error responses and correctable errors as described above.
11.2.4 Filtering and multiple error detection
The status register can optionally be implemented with two sets of status and failing address register.
In this case the core also supports filtering on errors and has a status bit that gets set in case additional
errors are detected when the New Error (NE) bit is set. The core will only react to the first error in a
burst operation. After the first error has been detected, monitoring of the burst is suspended. An error
event will only be recorded by the first status register that should react based on filter settings. If register set 1 has reacted then register 2 will not be set for the same error event.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
The extra register set, filtering, and multiple error detection is available in revision 1 of the status register. The functionality is enabled through the ver VHDL generic. The value of this generic also
affects the core version in the GRLIB plug&play information.

11.3

Registers
The core is programmed through registers mapped into APB address space.
Table 64. AHB Status registers
APB address offset

Registers

0x00

AHB Status register

0x04

AHB Failing address register

0x08

AHB Status register 2 (optional)

0x0C

AHB Failing Address register 2 (optional)

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
11.3.1 AHB Status register
Table 65. 0x00, 0x08- AHBS - AHB Status register
31

14 13 12 11 10
RESERVED

ME FW CF AF CE NE

HWRITE

HMASTER

HSIZE

rw* w* rw* rw* rw rw

31: 14

RESERVED

Multiple Error detection (ME) - This field is set to 1 when the New Error bit is set and one more
error is detected. Filtering is considered when setting the ME bit.
This field is only available in version 1 of the core (version is selected at implementation).

Filter Write (FW) - This bit needs to be set to ‘1’ during a write operation for CF and AF fields to be
updated in the same write operation. Always reads as zero.
This field is only available in version 1 of the core (version is selected at implementation).

Correctable Error Filter (CF) - If this bit is set to 1 then this status register will ignore correctable
errors. This field will only be written if the FW bit is set.
This field is only available in version 1 of the core (version is selected at implementation).

AMBA ERROR Filter (AF) - If this bit is set to 1 then this status register will ignore AMBA
ERROR. This field will only be written if the FW bit is set.
This field is only available in version 1 of the core (version is selected at implementation).

Correctable Error (CE) - Set if the detected error was caused by a correctable error and zero otherwise.

New Error (NE) - Deasserted at start-up and after reset. Asserted when an error is detected. Reset by
writing a zero to it.

The HWRITE signal of the AHB transaction that caused the error.

6: 3

The HMASTER signal of the AHB transaction that caused the error.

2: 0

The HSIZE signal of the AHB transaction that caused the error

11.3.2 AHB Failing address register
Table 66. 0x04, 0x0C - AHBFAR - AHB Failing address register
31

0
AHB FAILING ADDRESS
NR
t

31: 0

11.4

The HADDR of the AHB transaction that caused the error.

Vendor and device identifiers
The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x052. For description of
vendor and device identifiers see GRLIB IP Library User’s Manual.

11.5

Implementation
11.5.1 Reset
The core does not change reset behaviour depending on settings in the GRLIB configuration package
(see GRLIB User’s Manual). When reset is asserted the new error and correctable error registers are
reset to zero.

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
11.6

Configuration options
Table 67 shows the configuration options of the core (VHDL generics).
Table 67. Configuration options

11.7

Generic

Function

Allowed range

Default

pindex

APB slave index

0 - NAHBSLV-1

paddr

APB address

0 - 16#FFF#

pmask

APB address mask

0 - 16#FFF#

16#FFF#

pirq

Interrupt line driven by the core

0 - 16#FFF#

nftslv

Number of FT slaves connected to the cerror vector

1 - NAHBSLV-1

ver

Selects version of the core. Setting this value to 1 implements the two sets of registers, multiple error detection,
and filter functionality.

0-1

Signal descriptions
Table 68 shows the interface signals of the core (VHDL ports).
Table 68. Signal descriptions
Signal name

Field

Type

Function

Active

RST

N/A

Input

Reset

Low

CLK

N/A

Input

Clock

AHBMI

Input

AHB slave input signals

AHBSI

Input

AHB slave output signals

STATI

CERROR

Input

Correctable Error Signals

High

APBI

Input

APB slave input signals

APBO

Output

APB slave output signals

* see GRLIB IP Library User’s Manual

11.8

Library dependencies
Table 69 shows libraries used when instantiating the core (VHDL libraries).
Table 69. Library dependencies

11.9

Library

Package

Imported unit(s)

Description

GRLIB

AMBA

Signals

AHB signal definitions

GAISLER

MISC

Component

Component declaration

Instantiation
This example shows how the core can be instantiated.
The example design contains an AMBA bus with a number of AHB components connected to it
including the status register. There are three Fault Tolerant units with EDAC connected to the status
register cerror vector. The connection of the different memory controllers to external memory is not
shown.
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
use grlib.tech.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.misc.all;
entity mctrl_ex is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
--other signals
....
);
end;
architecture rtl of mctrl_ex is
-- AMBA bus (AHB and APB)
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
-- signals used to connect memory controller and memory bus
signal memi : memory_in_type;
signal memo : memory_out_type;
signal sdo, sdo2: sdctrl_out_type;
signal sdi : sdctrl_in_type;
-- correctable error vector
signal stati : ahbstat_in_type;
signal aramo : ahbram_out_type;
begin
-- AMBA Components are defined here ...
-- AHB Status Register
astat0 : ahbstat generic map(pindex => 13, paddr => 13, pirq => 11,
nftslv => 3)
port map(rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13));
stati.cerror(3 to NAHBSLV-1) <= (others => ‘0’);
--FT AHB RAM
a0 : ftahbram generic map(hindex => 1, haddr => 1, tech => inferred,
kbytes => 64, pindex => 4, paddr => 4, edacen => 1, autoscrub => 0,
errcnt => 1, cntbits => 4)
port map(rst, clk, ahbsi, ahbso, apbi, apbo(4), aramo);
stati.cerror(0) <= aramo.ce;
-- SDRAM controller
sdc : ftsdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 1, invclk => 0, edacen => 1, errcnt => 1,
cntbits => 4)
port map (rstn, clk, ahbsi, ahbso(3), sdi, sdo);
stati.cerror(1) <= sdo.ce;
-- Memory controller
mctrl0 : ftsrctrl generic map (rmw => 1, pindex => 10, paddr => 10,
edacen => 1, errcnt => 1, cntbits => 4)
port map (rstn, clk, ahbsi, ahbso(0), apbi, apbo(10), memi, memo, sdo2);
stati.cerror(2) <= memo.ce;
end;

GRIP, Apr 2018, Version 2018.1

www.cobham.com/gaisler

GRLIB IP Core
12

AHBTRACE - AHB Trace buffer

12.1

Overview
The trace buffer consists of a circular buffer that stores AMBA AHB data transfers. The address, data
and various control signals of the AHB bus are stored and can be read out for later analysis.
AHB Trace Buffer

Trace buffer RAM

Trace control

AHB slave interface

IRQ
AMBA AHB

Figure 14. Block diagram

When the trace buffer is configured in 32-bit bus mode, it is 128 bits wide. The information stored is
indicated in the table below:
Table 70. AHB Trace buffer data allocation
Bits

Name

Definition

127:96

Time tag

The value of the time tag counter

AHB breakpoint hit

Set to ‘1’ if a DSU AHB breakpoint hit occurred.