GRLIB IP Core User’s Manual

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GRLIB IP Core
GRLIB VHDL IP Core Library
2018 User’s Manual
The most important thing we build is trust

GRLIB IP Core User’s Manual
Apr 2018, Version 2018.1

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GRLIB IP Core
Table of contents

1

Introduction.............................................................................................................................. 6

2

AHB2AHB - Uni-directional AHB/AHB bridge ................................................................... 18

3

AHBM2AXI - AHB Master to AXI Adapter ......................................................................... 36

4

AHB2AXIB - AHB to AXI Bridge ........................................................................................ 44

5

AHBBRIDGE - Bi-directional AHB/AHB bridge................................................................. 53

6

AHBCTRL - AMBA AHB controller with plug&play support ............................................. 58

7

AHBJTAG - JTAG Debug Link with AHB Master Interface ................................................ 66

8

AHBRAM - Single-port RAM with AHB interface .............................................................. 72

9

AHBDPRAM - Dual-port RAM with AHB interface............................................................ 75

10

AHBROM - Single-port ROM with AHB interface .............................................................. 77

11

AHBSTAT - AHB Status Registers........................................................................................ 80

12

AHBTRACE - AHB Trace buffer.......................................................................................... 85

13

AHBUART- AMBA AHB Serial Debug Interface................................................................. 93

14

AMBAMON - AMBA Bus Monitor ...................................................................................... 99

15

APBCTRL - AMBA AHB/APB bridge with plug&play support ........................................ 105

16

APBPS2 - PS/2 host controller with APB interface............................................................. 109

17

APBUART - AMBA APB UART Serial Interface............................................................... 119

18

APBVGA - VGA controller with APB interface ................................................................. 129

19

CAN_OC - GRLIB wrapper for OpenCores CAN Interface core ....................................... 133

20

CLKGEN - Clock generation............................................................................................... 152

21

DDRSPA - 16-, 32- and 64-bit DDR266 Controller ............................................................ 175

22

DDR2SPA - 16-, 32- and 64-bit Single-Port Asynchronous DDR2 Controller ................... 189

23

DIV32 - Signed/unsigned 64/32 divider module ................................................................. 208

24

DSU3 - LEON3 Hardware Debug Support Unit ................................................................. 211

25

DSU4 - LEON4 Hardware Debug Support Unit ................................................................. 227

26

FTAHBRAM - On-chip SRAM with EDAC and AHB interface ....................................... 245

27

FTMCTRL - 8/16/32-bit Memory Controller with EDAC ................................................. 252

28

FTSDCTRL - 32/64-bit PC133 SDRAM Controller with EDAC ...................................... 283

29

FTSRCTRL - Fault Tolerant 32-bit PROM/SRAM/IO Controller ..................................... 295

30

FTSRCTRL8 - 8-bit SRAM/16-bit IO Memory Controller with EDAC ............................ 314

31

GPTIMER - General Purpose Timer Unit ........................................................................... 329

32

GR1553B - MIL-STD-1553B / AS15531 Interface............................................................. 338

33

GRTIMER - General Purpose Timer Unit ........................................................................... 380

34

GRACECTRL - AMBA System ACE Interface Controller................................................. 381

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35

GRAES - Advanced Encryption Standard ........................................................................... 386

36

GRAES_DMA - Advanced Encryption Standard with DMA.............................................. 392

37

GRCAN - CAN 2.0 Controller with DMA .......................................................................... 401

38

GRCLKGATE / GRCLKGATE2X - Clock gating unit ....................................................... 425

39

GRDMAC - DMA Controller with internal AHB/APB bridge ........................................... 432

40

GRECC - Elliptic Curve Cryptography ............................................................................... 453

41

GRETH - Ethernet Media Access Controller (MAC) with EDCL support ......................... 468

42

GRETH_GBIT - Gigabit Ethernet Media Access Controller (MAC) w. EDCL.................. 488

43

GRFIFO - FIFO Interface .................................................................................................... 510

44

GRADCDAC - ADC / DAC Interface................................................................................. 534

45

GRFPU - High-performance IEEE-754 Floating-point unit................................................ 547

46

GRFPC - GRFPU Control Unit ........................................................................................... 554

47

GRFPU Lite - IEEE-754 Floating-Point Unit...................................................................... 556

48

GRLFPC - GRFPU Lite Floating-point unit Controller ...................................................... 559

49

GRGPIO - General Purpose I/O Port................................................................................... 561

50

GRGPREG - General Purpose Register............................................................................... 572

51

GRIOMMU - AHB/AHB bridge with access protection and address translation ............... 575

52

GRPCI2 - 32-bit PCI(Initiator/Target) / AHB(Master/Slave) bridge................................... 620

53

GRPULSE - General Purpose Input Output ........................................................................ 649

54

GRPWM - Pulse Width Modulation Generator ................................................................... 656

55

GRRT - MIL-STD-1553B / AS15531 Remote Terminal Back-End .................................... 669

56

GRSPW - SpaceWire codec with AHB host Interface and RMAP target............................ 676

57

GRSPW2 - SpaceWire codec with AHB host Interface and RMAP target.......................... 720

58

GRSPW2_GEN - GRSPW2 wrapper with Std_Logic interface.......................................... 793

59

GRSPW2_PHY - GRSPW2 Receiver Physical Interface.................................................... 800

60

GRSPW_CODEC - SpaceWire encoder-decoder ................................................................ 806

61

GRSPW_CODEC_GEN - GRSPW_CODEC wrapper with Std_Logic interface .............. 824

62

GRSPWROUTER - SpaceWire router................................................................................. 831

63

SPWTDP - SpaceWire - Time Distribution Protocol........................................................... 888

64

GRSPFI_CODEC - SpaceFibre encoder/decoder................................................................ 920

65

GRSRIO - Serial RapidIO endpoint with AHB or AXI4 bus master interface.................... 935

66

GRSYSMON - AMBA Wrapper for Xilinx System Monitor .............................................. 991

67

GRUSBDC - USB Device controller................................................................................... 999

68

GRUSB_DCL - USB Debug Communication Link .......................................................... 1025

69

GRUSBHC - USB 2.0 Host Controller.............................................................................. 1032

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70

GRVERSION - Version and Revision information register............................................... 1049

71

I2C2AHB - I2C to AHB bridge ......................................................................................... 1051

72

I2CMST - I2C-master ........................................................................................................ 1061

73

I2CSLV - I2C slave ............................................................................................................ 1072

74

IRQMP - Multiprocessor Interrupt Controller ................................................................... 1080

75

IRQ(A)MP - Multiprocessor Interrupt Controller with extended ASMP support ............. 1090

76

L2C - Level 2 Cache controller ......................................................................................... 1105

77

L3STAT - LEON3 Statistics Unit ...................................................................................... 1129

78

L4STAT - LEON4 Statistics Unit ...................................................................................... 1137

79

LEON_DSU_STAT_BASE - LEON3/4 SUBSYSTEM.................................................... 1145

80

LEON3/FT - High-performance SPARC V8 32-bit Processor .......................................... 1151

81

LEON4 - High-performance SPARC V8 32-bit Processor................................................ 1200

82

LOGAN - On-chip Logic Analyzer ................................................................................... 1244

83

MCTRL - Combined PROM/IO/SRAM/SDRAM Memory Controller ............................ 1251

84

MEMSCRUB - AHB Memory Scrubber and Status Register ........................................... 1271

85

MMA - Memory Mapped AMBA bridge........................................................................... 1282

86

MUL32 - Signed/unsigned 32x32 multiplier module ........................................................ 1287

87

MULTLIB - High-performance multipliers ....................................................................... 1291

88

NANDFCTRL - NAND Flash Memory Controller ........................................................... 1293

89

PHY - Ethernet PHY simulation model ............................................................................. 1318

90

RGMII - Reduced Ethernet Media Access Controller ....................................................... 1321

91

REGFILE_3P 3-port RAM generator (2 read, 1 write) ..................................................... 1331

92

RSTGEN - Reset generation .............................................................................................. 1333

93

GR(2^4)(68, 60, 8, T=1) - QEC/QED error correction code encoder/decoder.................. 1337

94

RS(24, 16, 8, E=1) - Reed-Solomon encoder/decoder....................................................... 1341

95

RS(48, 32, 16, E=1+1) - Reed-Solomon encoder/decoder - interleaved ........................... 1344

96

RS(40, 32, 8, E=1) - Reed-Solomon encoder/decoder....................................................... 1346

97

RS(48, 32, 16, E=2) - Reed-Solomon encoder/decoder..................................................... 1349

98

SDCTRL - 32/64-bit PC133 SDRAM Controller.............................................................. 1353

99

SPI2AHB - SPI to AHB bridge.......................................................................................... 1363

100

SPICTRL - SPI Controller ................................................................................................. 1372

101

SPIMCTRL - SPI Memory Controller............................................................................... 1393

102

SPIMASTER - SPI Master Device .................................................................................... 1401

103

SPISLAVE - Dual Port SPI Slave ...................................................................................... 1410

104

SRCTRL- 8/32-bit PROM/SRAM Controller ................................................................... 1428

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105

SSRCTRL- 32-bit SSRAM/PROM Controller .................................................................. 1436

106

SVGACTRL - VGA Controller Core................................................................................. 1446

107

SYNCIOTEST - Test block for synchronous I/O interfaces.............................................. 1454

108

SYNCRAM - Single-port RAM generator ........................................................................ 1456

109

SYNCRAMBW - Single-port RAM generator with byte enables..................................... 1460

110

SYNCRAM_2P - Two-port RAM generator ..................................................................... 1464

111

SYNCRAM_DP - Dual-port RAM generator.................................................................... 1468

112

SYNCRAMFT - Single-port RAM generator with EDAC................................................ 1471

113

TAP - JTAG TAP Controller .............................................................................................. 1473

114

GRTM - CCSDS/ECSS Telemetry Encoder ...................................................................... 1477

115

GRTM_DESC - CCSDS/ECSS Telemetry Encoder - Descriptor...................................... 1504

116

GRTM_VC - CCSDS/ECSS Telemetry Encoder - Virtual Channel Generation ............... 1507

117

GRTM_PAHB - CCSDS/ECSS Telemetry Encoder - 
Virtual Channel Generation Input - AMBA....................................................................... 1509

118

GRTM_PW - CCSDS/ECSS Telemetry Encoder - 
Virtual Channel Generation Input - PacketWire ................................................................ 1513

119

GRTM_UART - CCSDS/ECSS Telemetry Encoder - 
Virtual Channel Generation Input - UART ........................................................................ 1515

120

GEFFE - CCSDS/ECSS Telemetry Encoder - Geffe Generator ........................................ 1518

121

GRTMRX - CCSDS/ECSS Telemetry Receiver................................................................ 1524

122

GRCE/GRCD - CCSDS/ECSS Convolutional Encoder and Quicklook Decoder............. 1538

123

GRTC - CCSDS/ECSS Telecommand Decoder ................................................................ 1543

124

TCAU - Telecommand Decoder Authentication Unit........................................................ 1570

125

GRTC_HW - CCSDS/ECSS Telecommand Decoder - Hardware Commands ................. 1581

126

GRTC_UART - CCSDS/ECSS Telecommand Decoder - UART...................................... 1588

127

GRTCTX - CCSDS/ECSS Telecommand Transmitter ...................................................... 1591

128

GRCTM - CCSDS Time Manager ..................................................................................... 1601

129

SPWCUC - SpaceWire - CCSDS Unsegmented Code Transfer Protocol ......................... 1633

130

GRPW - PacketWire Interface ........................................................................................... 1649

131

GRPWRX - PacketWire Receiver ..................................................................................... 1656

132

GRPWTX - PacketWire Transmitter ................................................................................. 1665

133

PW2APB - PacketWire receiver to AMBA APB Interface................................................ 1672

134

APB2PW - AMBA APB to PacketWire Transmitter Interface .......................................... 1678

135

AHB2PP - AMBA AHB to Packet Parallel Interface......................................................... 1684

136

GRRM - Reconfiguration Module ..................................................................................... 1689

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1

Introduction

1.1

Scope
This document describes specific IP cores provided with the GRLIB IP library. When applicable, the
cores use the GRLIP plug&play configuration method as described in the ‘GRLIB User’s Manual’.

1.2

Other resources
There are several documents that together describe the GRLIB IP Library and Cobham Gaisler’s IP
cores:
•
GRLIB IP Library User’s Manual (grlib.pdf) - Main GRLIB document that describes the library
infrastructure, organization, tool support and on-chip bus.

1.3

•

GRLIB-FT User’s Manual (grlib-ft.pdf) - Describes the FT and FT-FPGA versions of the GRLIB
IP library. The document is an addendum to the GRLIB IP Library User’s Manual. This document is only available in the FT and FT-FPGA distributions of GRLIB.

•

GRLIB FT-FPGA Xilinx Add-on User’s Manual (grlib-ft-fpga-xilinx.pdf) - Describes functionality of the Virtex5-QV and Xilinx TMRTool add-on package to the FT-FPGA version of the
GRLIP IP library. The document should be read as an addendum to the ‘GRLIB IP Library
User’s Manual’ and to the GRLIB FT-FPGA User’s Manual. This document is only available as
part of the add-on package for FT-FPGA.

•

LEON/GRLIB Configuration and Development Guide (guide.pdf) - This configuration and
development guide is intended to aid designers when developing systems based on LEON/
GRLIB. The guide complements the GRLIB IP Library User’s Manual and the GRLIB IP Core
User’s Manual. While the IP Library user’s manual is suited for RTL designs and the IP Core
user’s manual is suited for instantiation and usage of specific cores, this guide aims to help
designers make decisions in the specification stage.

Reference documents
[AMBA]

AMBATM Specification, Rev 2.0, ARM IHI 0011A, 1999, Issue A, ARM Limited

[GRLIB]

GRLIB IP Library User's Manual, Cobham Gaisler, www.gaisler.com

[AS1553]

AS15531 - Digital Time Division Command/Response Multiplex Data Bus, SAE
International, November 1995

[MIL1553]

MIL-STD-1553B, Digital Time Division Command/Response Multiplex Data Bus,
US Department of Defence, September 1978

[MIL1553N2]

MIL-STD-1553B Notice 2, US Department of Defence, September 1986

[ECSS1553]
Interface and Communication Protocol for MIL-STD-1553B Data Bus Onboard
Spacecraft, ECSS-E-ST-50-13C. November 2008

1.4

IP core overview
The tables below lists the provided IP cores and their AMBA plug&play device ID. The columns on
the right indicate in which GRLIB distributions a core is available. GPL is the GRLIB GNU GPL
(free) distribution, COM is the commercial distribution, FT the full fault-tolerant distribution and FTFPGA is the GRLIB release targeted for raditation-tolerant programmable devices. Distributions prefixed with L4- contain the LEON4 processor. Some cores can only be licensed separately or as additions to existing releases, this is marked in the Notes column. Contact Cobham Gaisler for licensing
details.
Note: The open-source version of GRLIB includes only cores marked with “Yes” in the GPL column.

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Note: IP core FT features are only supported in FT or FT-FPGA distributions. This includes protection of Level-1 cache and register files for the LEON3 and LEON4 processors and fault-tolerance features for other IP cores such as the PCI, Ethernet and SpaceWire controllers.
Note: For encrypted RTL, contact Cobham Gaisler to ensure that your EDA tool is supported by
GRLIB for encrypted RTL. Supported tools are listed in the GRLIB IP Library user’s manual.

0x01 : 0x003

Yes Yes Yes Yes No

No

5)

Fault-tolerant SPARC V8 32-bit Processor

0x01 : 0x053

No

Yes Yes No

No

2),
5)

DSU3

Multi-processor Debug support unit
(LEON3)

0x01 : 0x004

Yes Yes Yes Yes No

No

L3STAT

LEON3 statistics unit

0x01 : 0x098

Yes Yes Yes Yes No

No

LEON4

SPARC V8 32-bit processor

0x01 : 0x048

No

No

No

No

Yes No

LEON4FT

Fault-tolerant SPARC V8 32-bit Processor

0x01 : 0x048

No

No

No

No

No

No

Notes

L4-FT

SPARC V8 32-bit processor

LEON3FT

FT-FPGA

LEON3

FT

Vendor:Device

COM

Function

GPL

Name

L4-COM

Table 1. Processors and support functions

1,
4),
5)

Yes 1,
4),
5)

L4STAT

LEON4 statistics unit

0x01 : 0x047

No

No

No

No

Yes Yes 1)

DSU4

Multi-processor Debug support unit
(LEON4)

0x01 : 0x049

No

No

No

No

Yes Yes 1)

LEON3/4
CLK2x

LEON processor double clocking
(includes special LEON entity, interrupt
controller and qualifier unit)

-

No

Yes Yes Yes Yes Yes

CLKGEN

Clock generation

-

Yes Yes Yes Yes Yes Yes

DIV32

Divider module

-

Yes Yes Yes Yes Yes Yes

GPTIMER

General purpose timer unit

0x01 : 0x011

Yes Yes Yes Yes Yes Yes

GRCLKGATE

Clock gate unit

0x01 : 0x02C

No

GRDMAC

DMA controller with AHB/APB bridge

0x01 : 0x095

Yes Yes Yes Yes Yes Yes

GRTIMER

General purpose timer unit

0x01 : 0x038

No

Yes Yes Yes Yes Yes

GRFPU /
GRFPC

High-performance IEEE-754 Floatingpoint unit with floating-point controller
to interface LEON

-

No

No

No

No

No

No

1),
2)

GRFPU-Lite /
GRFPC-lite

Low-area IEEE-754 Floating-point unit
with floating point controller to interface
LEON

-

No

No

No

No

No

No

1),
2)

IRQMP

Multi-processor Interrupt controller

0x01 : 0x00D

Yes Yes Yes Yes Yes Yes

IRQ(A)MP

Multi-processor Interrupt controller

0x01 : 0x00D

Yes Yes Yes Yes Yes Yes

MUL32

32x32 multiplier module

-

Yes Yes Yes Yes Yes Yes

MULTLIB

High-performance multipliers

-

Yes Yes Yes Yes Yes Yes

Yes Yes Yes Yes Yes

1) Available as separate package or as addition to existing releases.
2) Delivered as encrypted RTL or in netlist format
3) Requires PHY for selected target technology. Please see IP core documentation for supported technologies.
4) Fault-tolerance (LEON4-FT functionality) is only supported in GRLIB-FT distributions.
5) The LEON3 and LEON3FT cores are functionally equivalent with the addition that fault-tolerance features can be
enabled for the LEON3FT core. The functional behaviour of the LEON4 core is the same in all distributions wiht the addition that fault-tolerance features for the LEON4 core can be enabled in GRLIB FT distributions.

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Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 2. Memory controllers and supporting cores

Name

Function

Vendor:Device

DDRSPA

Single-port 16/32/64 bit DDR controller

0x01 : 0x025

Yes Yes Yes Yes Yes Yes 3)

DDR2SPA

Single-port 16/32/64-bit DDR2 controller

0x01 : 0x02E

Yes Yes Yes Yes Yes Yes 3)

MCTRL

8/16/32-bit PROM/SRAM/SDRAM
controller

0x04 : 0x00F

Yes Yes Yes Yes Yes Yes

SDCTRL

32-bit PC133 SDRAM controller

0x01 : 0x009

Yes Yes Yes Yes Yes Yes

SRCTRL

8/32-bit PROM/SRAM controller

0x01 : 0x008

Yes Yes Yes Yes Yes Yes

SSRCTRL

32-bit Synchronous SRAM (SSRAM)
controller

0x01 : 0x00A

No

Yes Yes Yes Yes Yes

FTMCTRL

8//32-bit PROM/SRAM/SDRAM controller w. RS/BCH EDAC

0x01 : 0x054

No

No

Yes Yes No

Yes

FTSDCTRL

32/64-bit PC133 SDRAM Controller
with EDAC

0x01 : 0x055

No

No

Yes Yes No

Yes

FTSDCTRL64

64-bit PC133 SDRAM controller with
EDAC

0x01 : 0x058

No

No

No

No

No

FTSRCTRL

8/32-bit PROM/SRAM/IO Controller w.
BCH EDAC

0x01 : 0x051

No

No

Yes Yes No

Yes

FTSRCTRL8

8-bit SRAM / 16-bit IO Memory Controller with EDAC

0x01 : 0x056

No

No

Yes Yes No

Yes

NANDFCTRL

NAND Flash memory controller

0x01 : 0x059

No

Yes Yes Yes Yes Yes

SPIMCTRL

SPI Memory controller

0x01 : 0x045

Yes Yes Yes Yes Yes Yes

No

AHBSTAT

AHB status register

0x01 : 0x052

Yes Yes Yes Yes Yes Yes

MEMSCRUB

Memory scrubber

0x01 : 0x057

No

No

Yes Yes No

4)

Yes

1) Available as separate package or as addition to existing releases.
2) Delivered as encrypted RTL or in netlist format
3) Requires PHY for selected target technology. Please see IP core documentation for supported technologies.
4) Deprecated

AHB2AHB

Uni-directional AHB/AHB Bridge

0x01 : 0x020

No

AHB2AVLA

Asynchronous AHB to Avalon Bridge

0x01 : 0x096

Yes Yes No

AHB2AXI

AHB to AXI bridge

0x01 : 0x09F

Yes Yes Yes Yes Yes Yes

AHBBRIDGE

Bi-directional AHB/AHB Bridge

0x01 : 0x020

No

AHBCTRL

AMBA AHB bus controller with
plug&play

-

Yes Yes Yes Yes Yes Yes

APBCTRL

AMBA APB Bridge with plug&play

0x01 : 0x006

Yes Yes Yes Yes Yes Yes

AHBTRACE

AMBA AHB Trace buffer

0x01 : 0x017

Yes Yes Yes Yes Yes Yes

GRIOMMU

I/O Memory management unit

0x01 : 0x04F

No

Note

L4-FT

L4-COM

FT-FPGA

Vendor:Device

FT

Function

COM

Name

GPL

Table 3. AMBA Bus control

Yes Yes Yes Yes Yes
No

Yes No

Yes Yes Yes Yes Yes

No

No

No

Yes Yes 1)

1) Available as separate package or as addition to existing releases.

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Name

Function

Vendor:Device

GRPCI2

Advanced 32-bit PCI bridge

0x01 : 0x07C

Yes Yes Yes Yes Yes Yes

PCITARGET

32-bit target-only PCI interface (deprecated)

0x01 : 0x012

No

No

No

No

No

No

PCIMTF/GRPCI

32-bit PCI master/target interface with
FIFO (deprecated)

0x01 : 0x014

No

No

No

No

No

No

PCITRACE

32-bit PCI trace buffer (deprecated)

0x01 : 0x015

No

No

No

No

No

No

PCIDMA

DMA controller for PCIMTF (deprecated)

0x01 : 0x016

No

No

No

No

No

No

PCIARB

PCI Bus arbiter

0x04 : 0x010

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 4. PCI interface

Name

Function

Vendor:Device

AHBRAM

Single-port RAM with AHB interface

0x01 : 0x00E

Yes Yes Yes Yes Yes Yes

AHBDPRAM

Dual-port RAM with AHB and user
back-end interface

0x01 : 0x00F

Yes Yes Yes Yes Yes Yes

AHBROM

ROM generator with AHB interface

0x01 : 0x01B

Yes Yes Yes Yes Yes Yes

FTAHBRAM

RAM with AHB interface and EDAC
protection

0x01 : 0x050

No

No

Yes Yes No

No

No

No

Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 5. On-chip memory functions

Yes

L2CACHE

Level-2 cache controller

0x01 : 0x04B

No

REGFILE_3P

Parametrizable 3-port register file

-

Yes Yes Yes Yes Yes Yes

Yes Yes 1)

SYNCRAM

Parametrizable 1-port RAM

-

Yes Yes Yes Yes Yes Yes

SYNCRAM_2P

Parametrizable 2-port RAM

-

Yes Yes Yes Yes Yes Yes

SYNCRAM_DP

Parametrizable dual-port RAM

-

Yes Yes Yes Yes Yes Yes

1) Available as separate package or as addition to existing releases.

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GRLIB IP Core

Name

Function

Vendor:Device

AHBUART

Serial/AHB debug interface

0x01 : 0x007

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 6. Serial communication

AHBJTAG

JTAG/AHB debug interface

0x01 : 0x01C

Yes Yes Yes Yes Yes Yes

APBPS2

PS/2 host controller with APB interface

0x01 : 0x060

Yes Yes Yes Yes Yes Yes

APBUART

Programmable UART with APB interface

0x01 : 0x00C

Yes Yes Yes Yes Yes Yes

CAN_OC

Opencores CAN 2.0 MAC with AHB
interface

0x01 : 0x019

Yes Yes Yes Yes Yes Yes

GRCAN

CAN 2.0 Controller with DMA

0x01 : 0x03D

No

Yes Yes Yes Yes Yes

GRSPW

SpaceWire link with RMAP and AHB
interface

0x01 : 0x01F

No

No

No

No

No

No

1),
2)

GRSPW2

SpaceWire link with RMAP and AHB
interface

0x01 : 0x029

No

No

No

No

No

No

1),
2)

GRSPW_CODEC

SpaceWire Codec

N/A

No

No

No

No

No

No

1),
2)

GRSPW_PHY

Receiver Physical layer for GRSPW

N/A

No

No

No

No

No

No

1),
2)

GRSPW2_PHY

Receiver Physical layer

N/A

No

No

No

No

No

No

1),
2)

GRSPWROUTER

SpaceWire routing switch

0x01 : 0x03E

No

No

No

No

No

No

1),
2),
3)

GRSPWTDP

SpaceWire - Time Distribution Protocol

0x01 : 0x097

No

GRSRIO

Serial Rapid IO

0x01 : 0x0A8

No

No

No

No

No

No

1)

GRSPFI_CODEC

SpaceFibre Codec

N/A

No

No

No

No

No

No

1)

I2C2AHB

I2C (slave) to AHB bridge

0x01 : 0x00B

Yes Yes Yes Yes Yes Yes

I2CMST

I2C Master with APB interface

0x01 : 0x028

Yes Yes Yes Yes Yes Yes

I2CSLV

I2C Slave with APB interface

0x01 : 0x03E

Yes Yes Yes Yes Yes Yes

SPI2AHB

SPI (slave) to AHB bridge

0x01 : 0x05C

Yes Yes Yes Yes Yes Yes

No

No

No

No

No

1)

SPICTRL

SPI Controller with APB interface

0x01 : 0x02D

Yes Yes Yes Yes Yes Yes

SPIMASTER

SPI master device

0x01 : 0x0A6

No

No

No

No

No

No

1)

SPISLAVE

Dual port SPI slave

0x01 : 0x0A7

No

No

No

No

No

No

1)

TAP

JTAG TAP controller

-

No

Yes Yes Yes Yes Yes

1) Available as separate package or as addition to existing releases.
2) Delivered as encrypted RTL or in netlist format
3) The GRSPWROUTER is only licensed together with a complete LEON system.

GRIP, Apr 2018, Version 2018.1

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GRLIB IP Core

Name

Function

Vendor:Device

GRETH

Cobham Gaisler 10/100 Mbit Ethernet
MAC with AHB I/F

0x01 : 0x01D

Yes Yes Yes Yes Yes Yes

GRETH_GBIT

Cobham Gaisler 10/100/1000 Mbit
Ethernet MAC with AHB

0x01 : 0x01D

No

RGMII

Cobham Gaisler RGMII<-> GMII
adapter

0x01 : 0x093

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 7. Ethernet interface

Yes Yes Yes Yes Yes

Function

Vendor:Device

COM

FT

FT-FPGA

L4-COM

L4-FT

GRUSBHC

USB-2.0 Host controller (UHCI/EHCI)
with AHB I/F

0x01 : 0x027

No

No

No

No

No

No

1)

GRUSBDC /
USB-2.0 device controller / AHB debug
GRUSB_DCL communication link

0x01 : 0x022

No

No

No

No

No

No

1)

Note

Name

GPL

Table 8. USB interface

1) Available as separate package or as addition to existing releases.

Function

Device ID

COM

FT

FT-FPGA

L4-COM

L4-FT

GR1553B

Advanced MIL-ST-1553B / AS15551
Interface

0x01 : 0x04D

No

No

No

No

No

No

1),
2),
3)

GRRT

MIL-STD-1553B / AS15531 Remote
Terminal Back-End

-

No

No

No

No

No

No

1),
2),
3)

Note

Name

GPL

Table 9. MIL-STD-1553 Bus interface

1) Available as separate package or as addition to existing releases.
2) Delivered as encrypted RTL or in netlist format.
3) Both BR1553B and GRRT are covered by the same IP core license and are delivered in the same package.

Function

Vendor:Device

COM

FT

FT-FPGA

L4-COM

L4-FT

GRAES

128-bit AES Encryption/Decryption
Core

0x01 : 0x073

No

No

No

No

No

No

1)

GRAES_DMA

Advanced Encryption Standard with
DMA

0x01 : 0x07B

No

No

No

No

No

No

1)

GRECC

Elliptic Curve Cryptography Core

0x01 : 0x074

No

No

No

No

No

No

1)

Note

Name

GPL

Table 10. Encryption

1) Available as separate package or as addition to existing releases.

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GRLIB IP Core

Name

Function

Vendor:Device

SRAM

SRAM simulation model with srecord
pre-load

-

Yes Yes Yes Yes Yes Yes

MT48LC16M16

Micron SDRAM model with srecord
pre-load

-

Yes Yes Yes Yes Yes Yes

MT46V16M16

Micron DDR model

-

Yes Yes Yes Yes Yes Yes

CY7C1354B

Cypress ZBT SSRAM model with srecord pre-load

-

Yes Yes Yes Yes Yes Yes

AHBMSTEM

AHB master simulation model with
scripting (deprecated)

0x01 : 0x040

Yes Yes Yes Yes Yes Yes

AHBSLVEM

AHB slave simulation model with script- 0x01 : 0x041
ing (deprecated)

Yes Yes Yes Yes Yes Yes

AMBAMON

AHB and APB protocol monitor

-

No

Yes Yes Yes Yes Yes

ATF

AMBA test framework consisting of
master, slave and arbiter.

0x01 : 
0x068 - 0x06A

No

Yes Yes Yes Yes Yes

LOGAN

On-chip Logic Analyzer

0x01 : 0x062

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 11. Simulation and debugging

Name

Function

Vendor:Device

APBVGA

VGA controller with APB interface

0x01 : 0x061

Yes Yes Yes Yes Yes Yes

SVGACTRL

VGA controller core with DMA

0x01 : 0x063

Yes Yes Yes Yes Yes Yes

Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 12. Graphics functions

Name

Function

Vendor:Device

GRACECTRL

AMBA SystemACE interface controller

0x01 : 0x067

Yes Yes Yes Yes Yes Yes

GRADCDAC

Combined ADC / DAC Interface

0x01 : 0x036

No

Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes

GRFIFO

External FIFO Interface with DMA

0x01 : 0x035

No

GRGPIO

General purpose I/O port

0x01 : 0x01A

Yes Yes Yes Yes Yes Yes

GRGPREG

General purpose Register

0x01 : 0x087

Yes Yes Yes Yes Yes Yes

GRPULSE

General purpose I/O with pulses

0x01 : 0x037

No

Yes Yes Yes Yes Yes

GRPWM

PWM generator

0x01 : 0x04A

No

Yes Yes Yes Yes Yes

GRSYSMON

AMBA Wrapper for Xilinx System
Monitor

0x01 : 0x066

Yes Yes Yes Yes Yes Yes

GRVERSION

Version and revision register

0x01 : 0x03A

Yes Yes Yes Yes Yes Yes

GRIP, Apr 2018, Version 2018.1

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Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 13. Auxiliary functions

www.cobham.com/gaisler

GRLIB IP Core

Name

Function

RS(24, 16, 8, E=1)

16 bit data, 8 check bits, corrects 4-bit error in 1 nib- No
ble

No

Yes Yes No

Yes

RS(40, 32, 8, E=1)

32 bit data, 8 check bits, corrects 4-bit error in 1 nib- No
ble

No

Yes Yes No

Yes

RS(48, 32, 16, E=1+1)

32 bit data, 16 check bits, corrects 4-bit error in 2
nibbles

No

No

Yes Yes No

Yes

RS(48, 32, 16, E=2)

32 bit data, 16 check bits, corrects 4-bit error in 2
nibbles

No

No

Yes Yes No

Yes

GR(2^4)(68, 60, 8, T=1)

QEC/QED error correction code encoder/decoder

No

No

Yes Yes No

Yes

Note

L4-FT

L4-COM

FT-FPGA

FT

COM

GPL

Table 14. Error detection and correction functions

GRIP, Apr 2018, Version 2018.1

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Note

L4-FT

L4-COM

Test block for synchronous I/O interfaces

FT-FPGA

Function

SYNCIOTEST

FT

Name

COM

GPL

Table 15. Test functions

Yes Yes Yes Yes Yes Yes

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GRLIB IP Core
1.5

Spacecraft data handling IP cores
The Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the space sector.
These IP cores implement functions commonly used in spacecraft data handling and management systems. They implement international standards from organizations such as Consultative Committee for
Space Data Systems (CCSDS), European Cooperation on Space Standardization (ECSS), and the former Procedures, Standards and Specifications (PSS) from the European Space Agency (ESA).
The table below lists the existing CCSDS/ECSS IP cores and AMBA plug&play device identifiers.
The columns on the right indicate in which GRLIB distributions a core is available. GPL is the
GRLIB GNU GPL (free) distribution, COM is the commercial distribution, FT the full fault-tolerant
distribution and FT-FPGA is the GRLIB release targeted for radiation-tolerant programmable devices.
Distributions prefixed with L4- contain the LEON4 processor.
The TMTC license covers IP cores, with the upper TM and TC layers implemented in software, hardware and also cores for implementing TM and TC test equipment. It can be provided as a separate
package or as an add-on to other GRLIB distributions.

GRTM

CCSDS Telemetry Encoder

0x01 : 0x030

No

No

No

No

No

No Yes

GRTM_DESC

CCSDS Telemetry Encoder - Descriptor

0x01 : 0x084

No

No

No

No

No

No Yes

GRTM_VC

CCSDS Telemetry Encoder - Virtual Channel Generation

0x01 : 0x085

No

No

No

No

No

No Yes

GRTM_PAHB

CCSDS Telemetry Encoder - VC Generation Input - AMBA

0x01 : 0x088

GRTM_PW

CCSDS Telemetry Encoder - VC Generation Input - PacketWire N/A

No

No

No

No

No

No Yes

No

No

No

No

No

No Yes

Note

TMTC

L4.FT

L4-COM

FT-FPGA

Vendor : Device

FT

Function

COM

Name

GPL

Table 16. Spacecraft data handling functions

GRTM_UART

CCSDS Telemetry Encoder - VC Generation Input - UART

N/A

No

No

No

No

No

No Yes

GRTM_CLCWRX

CCSDS Telemetry Encoder - CLCW Receiver

N/A

No

No

No

No

No

No Yes

2)

GRTM_CLCWMUX

CCSDS Telemetry Encoder - CLCW Multiplexer

N/A

No

No

No

No

No

No Yes

2)

GRGEFFE

CCSDS Telemetry Encoder - Geffe Generator

0x01 : 0x086

No

No

No

No

No

No Yes

GRCE/GRCD

CCSDS Convolutional Encoder and Quicklook Decoder

N/A

No

No

No

No

No

No Yes

GRTMRX

CCSDS Telemetry Receiver

0x01 : 0x082

No

No

No

No

No

No Yes
No Yes

GRTC

CCSDS Telecommand Decoder - Coding Layer

0x01 : 0x031

No

No

No

No

No

TCAU

ESA PSS Telecommand Decoder Authentication Unit

N/A

No

No

No

No

No

No Yes

GRTC_HW

CCSDS Telecommand Decoder - Hardware Commands

N/A

No

No

No

No

No

No Yes

GRTC_UART

CCSDS Telecommand Decoder - UART

N/A

No

No

No

No

No

No Yes

GRTC_CLCWTX

CCSDS Telecommand Decoder - CLCW Transmitter

N/A

No

No

No

No

No

No Yes

GRTCTX

CCSDS Telecommand Transmitter

0x01 : 0x083

No

No

No

No

No

No Yes

GRCTM

CCSDS Time manager

0x01 : 0x033

No

No

No

No

No

No Yes

SPWCUC

SpaceWire - CCSDS Unsegmented Code Transfer Protocol

0x01 : 0x089

No

No

No

No

No

No Yes

GRPW

PacketWire receiver with AHB interface

0x01 : 0x032

No

No

No

No

No

No Yes

GRPWRX

PacketWire Receiver (rev 1)

0x01 : 0x03C

No

No

No

No

No

No Yes

GRPWTX

PacketWire Transmitter (rev 1)

0x01 : 0x03B

No

No

No

No

No

No Yes

APB2PW

PacketWire Transmitter Interface (rev 0)

0x01 : 0x03B

No

No

No

No

No

No Yes

PW2APB

PacketWire Receiver Interface (rev 0)

0x01 : 0x03C

No

No

No

No

No

No Yes

AHB2PP

Packet Parallel Interface

0x01 : 0x039

No

No

No

No

No

No Yes

GRRM

Reconfiguration Module

0x01 : 0x09A

No

No

No

No

No

No

Note 1)

Available as separate package or as addition to existing releases.

Note 2)

There is no user manual for these simple cores.

GRIP, Apr 2018, Version 2018.1

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No

2)

1)

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GRLIB IP Core
1.6

Supported technologies

Comment

FT-

FT

GPL

COM

Technology support and instructions for extending GRLIB with support for additional technologies is
documented in the ‘GRLIB User’s Manual’. The table below shows the technology maps available
from Cobham Gaisler for GRLIB and in which GRLIB distributions these technology maps are
included.

Vendor

Technology

Actel /
Microsemi

ProASIC3, ProASIC3e, ProASIC3l,
Axcelerator, Axcelerator DSP, Fusion,
IGLOO2

No

Yes Yes Yes

Actel /
Microsemi

RTG4

No

No

Altera

Cyclone2 - 4, Stratix - StratixV

Yes Yes Yes Yes Note that several parts of the FT and
FT-FPGA versions are distributed as
encrypted RTL. Encrypted RTL is
not provided for the Quartus II tool.

Lattice

-

Yes Yes No

Xilinx

Unisim (Virtex2 - 7-series)

Yes Yes Yes Yes Xilinx Sirf (Virtex-5QV) and TMRTool support is distributed as a separate add-on package.

Other ASIC

-

No

GRIP, Apr 2018, Version 2018.1

15

-

*

-

*

RTG4 support is distributed as a separate add-on package.

No

No

Contact Cobham Gaisler for details.
See also GRLIB IP Library User’s
Manual.

www.cobham.com/gaisler

GRLIB IP Core
1.7

Implementation characteristics
Implementation characteristics are available in the GRLIB area spreadsheet:
http://www.gaisler.com/products/grlib/grlib_area.xls
The spreadsheet is also included in GRLIB packages together with this document.

1.8

Definitions
This section and the following subsections define the typographic and naming conventions used
throughout this document.
1.8.1

Bit numbering

The following conventions are used for bit numbering:
•

The most significant bit (MSb) of a data type has the leftmost position

•

The least significant bit of a data type has the rightmost position

•

Unless otherwise indicated, the MSb of a data type has the highest bit number and the LSb the
lowest bit number

1.8.2

Radix

The following conventions is used for writing numbers:
•

Binary numbers are indicated by the prefix "0b", e.g. 0b1010.

•

Hexadecimal numbers are indicated by the prefix "0x", e.g. 0xF00F

•

Unless a radix is explicitly declared, the number should be considered a decimal.

1.8.3

Data types

Byte (BYTE)

8 bits of data

Halfword (HWORD)

16 bits of data

Word (WORD)

32 bits of data

Double word (DWORD)

64 bits of data

Quad word (4WORD)

128-bits of data

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GRLIB IP Core
1.9

Register descriptions
An example register, showing the register layout used throughout this document, can be seen in table
17. The values used for the reset value fields are described in table 18, and the values used for the
field type fields are described in table 19. Fields that are named RESERVED, RES, or R are read-only
fields. These fields can be written with zero or with the value read from the same register field.
Table 17. 
- - 31 24 23 16 15 8 7 0 EF3 EF2 EF1 EF0 31: 24 Example field 3 (EF3) - 23: 16 Example field 2 (EF2) - 15: 8 Example field 1 (EF1) - 7: 0 Example field 0 (EF0) - Table 18. Reset value definitions Value Description 0 Reset value 0. 1 Reset value 1. Used for single-bit fields. 0xNN Hexadecimal representation of reset value. Used for multi-bit fields. 0bNN Binary representation of reset value. Used for multi-bit fields. NR Field not reset. Fields marked with NR will be reset to 0 if full reset of all registers have been enabled in the global GRLIB configuration options (see GRLIB user manual for more information). * Special reset condition, described in textual description of the field. Used for example when reset value is taken from a pin. - Don’t care / Not applicable Table 19. Field type definitions Value Description r Read-only. Writes have no effect. w Write-only. Used for a writable field in a register where the field’s read-value has no meaning. rw Readable and writable. rw* Readable and writable. Special condition for write, described in textual description of field. wc Write-clear. Readable, and cleared when written with a 1 cas Readable, and writable through compare-and-swap. Only applies to SpaceWire Plug-and-Play registers. GRIP, Apr 2018, Version 2018.1 17 www.cobham.com/gaisler GRLIB IP Core 2 AHB2AHB - Uni-directional AHB/AHB bridge 2.1 Overview The uni-directional AHB/AHB bridge is used to connect two AMBA AHB buses clocked by synchronous clocks with any frequency ratio. The bridge is connected through a pair consisting of an AHB slave and an AHB master interface. AHB transfer forwarding is performed in one direction, where AHB transfers to the slave interface are forwarded to the master interface. Applications of the unidirectional bridge include system partitioning, clock domain partitioning and system expansion. Features offered by the uni-directional AHB to AHB bridge are: • Single and burst AHB transfers • Data buffering in internal FIFOs • Efficient bus utilization through (optional) use of SPLIT response and data prefetching. NOTE: SPLIT responses require an AHB arbiter that allows assertion of HSPLIT during second cycle of SPLIT response. This is supported by GRLIB’s AHBCTRL IP core. • Posted writes • Read and write combining, improves bus utilization and allows connecting cores with differing AMBA access size restrictions. • Deadlock detection logic enables use of two uni-directional bridges to build a bi-directional bridge (one example is the bi-directional AHB/AHB bridge core (AHBBRIDGE)) MASTER 1 MASTER 2 MASTER N AHB Bus 0 BUS CONTROL SLAVE 1 SLAVE I/F SLAVE 2 AHB/AHB BRIDGE MASTER I/F MASTER 1 MASTER N AHB Bus 1 BUS CONTROL SLAVE 2 SLAVE 1 Figure 1. Two AHB buses connected with (uni-directional) AHB/AHB bridge 2.2 Operation 2.2.1 General The address space occupied by the AHB/AHB bridge on the slave bus is configurable and determined by Bank Address Registers in the slave interface’s AHB Plug&Play configuration record. The bridge is capable of handling single and burst transfers of all burst types. Supported transfer sizes (HSIZE) are BYTE, HALF-WORD, WORD, DWORD, 4WORD and 8WORD. GRIP, Apr 2018, Version 2018.1 18 www.cobham.com/gaisler GRLIB IP Core For AHB write transfers write data is always buffered in an internal FIFO implementing posted writes. For AHB read transfers the bridge uses GRLIB’s AMBA Plug&Play information to determine whether the read data will be prefetched and buffered in an internal FIFO. If the target address for an AHB read burst transfer is a prefetchable location the read data will be prefetched and buffered. The bridge can be implemented to use SPLIT responses or to insert wait states when handling an access. With SPLIT responses enabled, an AHB master initiating a read transfer to the bridge is always splitted on the first transfer attempt to allow other masters to use the slave bus while the bridge performs read transfer on the master bus.The descriptions of operation in the sections below assume that the bridge has been implemented with support for AMBA SPLIT responses. The effects of disabling support for AMBA SPLIT responses are described in section 2.2.11. If interrupt forwarding is enabled the interrupts on the slave bus interrupt lines will be forwarded to the master bus and vice versa. 2.2.2 AHB read transfers When a read transfer is registered on the slave interface the bridge gives a SPLIT response. The master that initiated the transfer will be de-granted allowing other bus masters to use the slave bus while the bridge performs a read transfer on the master side. The master interface then requests the bus and starts the read transfer on the master side. Single transfers on the slave side are normally translated to single transfers with the same AHB address and control signals on the master side, however read combining can translate one access into several smaller accesses. Translation of burst transfers from the slave to the master side depends on the burst type, burst length, access size and the AHB/AHB bridge configuration. If the read FIFO is enabled and the transfer is a burst transfer to a prefetchable location, the master interface will prefetch data in the internal read FIFO. If the splitted burst on the slave side was an incremental burst of unspecified length (INCR), the length of the burst is unknown. In this case the master interface performs an incremental burst up to a specified address boundary (determined by the VHDL generic rburst). The bridge can be configured to recognize an INCR read burst marked as instruction fetch (indicated on HPROT signal). In this case the prefetching on the master side is completed at the end of a cache line (the cache line size is configurable through the VHDL generic iburst). When the burst transfer is completed on the master side, the splitted master that initiated the transfer (on the slave side) is allowed in bus arbitration by asserting the appropriate HSPLIT signal to the AHB controller. The splitted master re-attempts the transfer and the bridge will return data with zero wait states. If the read FIFO is disabled, or the burst is to non-prefetchable area, the burst transfer on the master side is performed using sequence of NONSEQ, BUSY and SEQ transfers. The first access in the burst on the master side is of NONSEQ type. Since the master interface can not decide whether the splitted burst will continue on the slave side or not, the master bus is held by performing BUSY transfers. On the slave side the splitted master that initiated the transfer is allowed in bus arbitration by asserting the HSPLIT signal to the AHB controller. The first access in the transfer is completed by returning read data. The next access in the transfer on the slave side is extended by asserting HREADY low. On the master side the next access is started by performing a SEQ transfer (and then holding the bus using BUSY transfers). This sequence is repeated until the transfer is ended on the slave side. In case of an ERROR response on the master side the ERROR response will be given for the same access (address) on the slave side. SPLIT and RETRY responses on the master side are re-attempted until an OKAY or ERROR response is received. 2.2.3 AHB write transfers The AHB/AHB bridge implements posted writes. During the AHB write transfer on the slave side the data is buffered in the internal write FIFO and the transfer is completed on the slave side by always giving an OKAY response. The master interface requests the bus and performs the write transfer when the master bus is granted. If the burst transfer crosses the write burst boundary (defined by VHDL GRIP, Apr 2018, Version 2018.1 19 www.cobham.com/gaisler GRLIB IP Core generic wburst), a SPLIT response is given. When the bridge has written the contents of the FIFO out on the master side, the bridge will allow the master on the slave side to perform the remaining accesses of the write burst transfer. Writes are accepted with zero wait states if the bridge is idle and the incoming access is not locked. If the incoming access is locked, each access will have one wait state. If write combining is disabled a non-locked BUSY cycle will lead to a flush of the write FIFO. If write combining is enabled or if the incoming access is locked, the bridge will not flush the write FIFO during the BUSY cycle. 2.2.4 Deadlock conditions When two bridges are used to form a bi-drectional bridge, a deadlock situation can occur if the bridges are simultaneously accessed from both buses. The bridge that has been configured as a slave contains deadlock detection logic which will resolve a deadlock condition by giving a RETRY response, or by issuing SPLIT complete followed by a new SPLIT response. When the core resolves a deadlock while prefetching data, any data in the prefetch buffer will be dropped when the core’s slave interface issues the AMBA RETRY response. When the access is retried it may lead to the same memory locations being read twice. Deadlock detection logic for bi-directional configurations may lead to deadlocks in other parts of the system. Consider the case where a processor on bus A on one side of the bidirectional bridge needs to perform an instruction fetch over the bridge before it can release a semaphore located in memory on bus A. Another processor on bus B, on the other side of the bridge, may spin on the semaphore wating for its release. In this scenario, the accesses from the processor on bus B could, depending on system configuration, continuously trigger a deadlock condition where the core will drop data in, or be prevented from initiating, the instruction fetch for the processor on bus A. Due to scenarios of this kind the bridge should not be used in bi-directional configurations where dependencies as the one described above exist between the buses connected by the bridge. Other deadlock conditions exist with locked transfers, see section 2.2.5. 2.2.5 Locked transfers The AHB/AHB bridge supports locked transfers. The master bus will be locked when the bus is granted and remain locked until the transfer completes on the slave side. Locked transfers can lead to deadlock conditions, the core’s VHDL generic lckdac determines if and how the deadlock conditions are resolved. With the VHDL generic lckdac set to 0, locked transfers may not be made after another read access which received SPLIT until the first read access has received split complete. This is because the bridge will return split complete for the first access first and wait for the first master to return. This will cause deadlock since the arbiter is not allowed to change master until a locked transfer has been completed. The AMBA specification requires that the locked transfer is handled before the previous transfer, which received a SPLIT response, is completed. With lckdac set to 1, the core will respond with an AMBA ERROR response to locked access that is made while an ongoing read access has received a SPLIT response. With lckdac set to 2 the bridge will save state for the read access that received a SPLIT response, allow the locked access to complete, and then complete the first access. All non-locked accesses from other masters will receive SPLIT responses until the saved data has been read out. If the core is used to create a bi-directional bridge there is one more deadlock condition that may arise when locked accesses are made simultaneously in both directions. If the VHDL generic lckdac is set to 0 the core will deadlock. If lckdac is set to a non-zero value the slave bridge will resolve the deadlock condition by issuing an AMBA ERROR response to the incoming locked access. GRIP, Apr 2018, Version 2018.1 20 www.cobham.com/gaisler GRLIB IP Core 2.2.6 Read and write combining Read and write combining allows the bridge to assemble or split AMBA accesses on the bridge’s slave interface into one or several accesses on the master interface. This functionality can improve bus utilization and also allows cores that have differing AMBA access size restrictions to communicate with each other. The functionality attained by read and write combining depends on the VHDL generics rdcomb (defines type of read combining), wrcomb (defines type of write combining), slvmstaccsz (defines maximum AHB access size supported by the bridge’s slave interface) and mstmaccsz (defines maximum AHB access size that can be used by bridge’s master interface). These VHDL generics are described in section 2.6. The table below shows the effect of different settings. BYTE and HALF-WORD accesses are special cases. The table does not list illegal combinations, for instance mstmaccsz /= slvmaccsz requires that wrcomb /= 0 and rdcomb /= 0. Table 20. Read and write combining Access on slave interface wrcomb rdcomb Resulting access(es) on master interface BYTE or HALF-WORD sin- gle read access to any area - - Single access of same size BYTE or HALF-WORD read burst to prefetchable area - - - Incremental read burst of same access size as on slave interface, the length is the same as the number of 32-bit words in the read buffer, but will not cross the read burst boundary. BYTE or HALF-WORD read burst to non-prefetchable area - - - Incremental read burst of same access size as on slave interface, the length is the same as the length of the incoming burst. The master interface will insert BUSY cycles between the sequential accesses. BYTE or HALF-WORD sin- gle write - - Single access of same size BYTE or HALF-WORD write burst - - - Incremental write burst of same size and length, the maximum length is the number of 32-bit words in the write FIFO. Single read access to any area Access size <= mstmaccsz - - Single access of same size Single read access to any area Access size > mstmaccsz - 1 Sequence of single accesses of mstmaccsz. Number of accesses: (access size)/mstmaccsz Single read access to any area Access size > mstmaccsz - 2 Burst of accesses of size mstmaccsz. Length of burst: (access size)/mstmaccsz Read burst to prefetchable area - - 0 Burst of accesses of incoming access size up to address boundary defined by rburst. Read burst to prefetchable area - - 1 or 2 Burst of accesses of size mstmaccsz up to address boundary defined by rburst. Read burst to non-prefetchable area Access size <= mstmaccsz - - Incremental read burst of same access size as on slave interface, the length is the same as the length of the incoming burst. The master interface will insert BUSY cycles between the sequential accesses. Read burst to non-prefetchable area Access size > mstmaccsz - 1 or 2 Burst of accesses of size mstmaccsz. Length of burst:  (incoming burst length)*(access size)/mstmaccsz Single write Access size <= mstmaccsz - - Single write access of same size Single write Access size > mstmaccsz 1 - Sequence of single access of mstmaccsz. Number of accesses: (access size)/mstmaccsz. Single write Access size > mstmaccsz 2 - Burst of accesses of mstmaccsz. Length of burst: (access size)/mstmaccsz. GRIP, Apr 2018, Version 2018.1 Access size 21 www.cobham.com/gaisler GRLIB IP Core Table 20. Read and write combining Access on slave interface Access size wrcomb rdcomb Resulting access(es) on master interface Write burst - 0 - Burst of same size as incoming burst, up to address boundary defined by VHDL generic wburst. Write burst - 1 or 2 - Burst write of maximum possible size. The bridge will use the maximum size (up to mstmaccsz) that it can use to empty the writebuffer. Read and write combining prevents the bridge from propagating fixed length bursts and wrapping bursts. See section 2.2.7 for a discussion on burst operation. Read and write combining with VHDL generics wrcomb/rdcomb set to 1 cause the bridge to use single accesses when divding an incoming access into several smaller accesses. This means that another master on the bus may write or read parts of the memory area to be accessed by the bridge before the bridge has read or written all the data. In bi-directional configurations, an incoming access on the master bridge may cause a collision that aborts the operation on the slave bridge. This may cause the bridge to read the same memory locations twice. This is normally not a problem when accessing memory areas. The same issues apply when using an AHB arbiter that performs early burst termination. The standard GRLIB AHBCTRL core does not perform early burst termination. To ensure that the bridge does not re-read an address, and that all data in an access from the bridge’s slave interface is propagated out on the master interface without interruption the VHDL generics rdcomb and wrcomb should both be set to 0 or 2. In addition to this, the AHB arbiter may not perform early burst termination (early burst termination is not performed by the GRLIB AHBCTRL arbiter). Read and write combining can be limited to specified address ranges. See description of the combmask VHDL generic for more information. Note that if the core is implemented with support for prefetch and read combining, it will not obey combmask for prefetch operations (burst read to prefetchable areas). Prefetch operations will always be performed with the maximum allowed size on the master interface. 2.2.7 Burst operation The core can be configured to support all AMBA 2.0 burst types (single access, incrementing burst of unspecified length, fixed length incrementing bursts and wrapping bursts). Single accesses and incrementing bursts of unspecified length have previously been discussed in this document. An incoming single access will lead to one access, or multiple accesses for some cases with read/write combining, on the other side of the bridge. An incoming incrementing burst of unspecified length to a prefetchable area will lead to the prefetch buffer (if available) being filled using the same access size, or the maximum allowed access size if read/write combining is enabled, on the master interface. If the core is used in a system where no fixed length bursts or incremental bursts will be used in accesses to the bridge, then set the allbrst generic to 0 and skip the remainder of this section. The VHDL generic allbrst controls if the core will support fixed length and wrapping burst accesses. If allbrst is set to 0, the core will treat all burst accesses as incrementing of unspecified length. For fixed length and wrapping bursts this can lead to performance penalties and malfunctions. Support for fixed length and wrapping bursts is enabled by setting allbrst to 1 or 2. Table 21 describes how the core will handle different burst types depending on the setting of allbrst. GRIP, Apr 2018, Version 2018.1 22 www.cobham.com/gaisler GRLIB IP Core Table 21. Burst handling Value of allbrst generic Access type* Undefined length incrementing burst INCR Fixed length incrementing burst INCR{4,8,16} Wrapping burst WRAP{4,8,16} 0 Reads to nonprefetchable area Incrementing burst with BUSY cycles inserted. Same behaviour with read and write combining. Fixed length burst with BUSY cycles inserted. If the burst is short then the burst may end with a BUSY cycle. If access combining is used the HBURST signal will get incorrect values. Malfunction. Not supported Reads to prefetchable area Incrementing burst of maximum allowed size, filling prefetch buffer, starting at address boundary defined by prefetch buffer. Malfunction. Not supported Write burst Incrementing burst Incrementing burst, if write combining is enabled, and triggered, the burst will be translated to an incrementing burst of undefined length. VHDL generic wrcomb should not be set to 1 (but to 0 or 2) in this case Write combining is not supported. Same access size will be used on both sides of the bridge. Reads to nonprefetchable area Incrementing burst with BUSY cycles inserted. Same behaviour with read and write combining. Same burst type with BUSY cycles inserted. If read combining is enabled, and triggered by the incoming access size, an incremental burst of unspecified length will be used. If the burst is short then the burst may end with a BUSY cycle. Same burst type with BUSY cycles inserted. If read combining is enabled, and triggered by the incoming access size, an incremental burst of unspecified length will be used. This will cause AMBA violations if the wrapping burst does not start from offset 0. Reads to prefetchable area Incrementing burst of maximum allowed size, filling prefetch buffer. For reads, the core will perform full (or part that fits in prefetch buffer) fixed/wrapping burst on master interface and then respond with data. No BUSY cycles are inserted. 1 If the access made to the slave interface is larger than the maximum supported access size on the master interface then a incrementing burst of unspecified length will be used to fill the prefetch buffer. This (read combining) is not supported for wrapping bursts. Write burst 2 Same as for allbrst = 0 Reads to nonprefetchable area Incrementing burst with BUSY cycles inserted. Same behaviour with read and write combining. Reads to prefetchable area Incrementing burst of maximum allowed size, filling prefetch buffer, starting at address boundary defined by prefetch buffer. Reads are treated as a prefetchable burst. See below. Core will perform full (or part that fits in prefetch buffer) fixed/ wrapping burst on master interface and then respond with data. No BUSY cycles are inserted. If the access made to the slave interface is larger than the maximum supported access size on the master interface then a incrementing burst of unspecified length will be used to fill the prefetch buffer. This (read combining) is not supported for wrapping bursts. Write burst Same as for allbrst = 0 * Access to prefetchable area where the core’s prefetch buffer is ised (VHDL generic pfen /= 0). GRIP, Apr 2018, Version 2018.1 23 www.cobham.com/gaisler GRLIB IP Core 2.2.8 Transaction ordering, starvation and AMBA arbitration schemes The bridge is configured at implementation to use one of two available schemes to handle incoming accesses. The bridge will issue SPLIT responses when it is busy and on incoming read accesses. If the bridge has been configured to use first-come, first-served ordering it will keep track of the order of incoming accesses and serve the requests in the same order. If first-come, first-served ordering is disabled the bridge will give some advantage to the master it has a response for and then allow all masters in to arbitration simultaneously, moving the decision on which master that should be allowed to access the bridge to the bus arbitration. When designing a system containing a bridge the expected traffic patterns should be analyzed. The designer must be aware how SPLIT responses affect arbitration and how the selected transaction ordering in the bridge will affect the system. The two different schemes are further described in sections 2.2.9 and 2.2.10. 2.2.9 First-come, first-served ordering First-come, first served ordering is used when the VHDL generic fcfs is non-zero. With first-come, first-served ordering the bridge will keep track of the order of incoming accesses. The accesses will then be served in the same order. For instance, if master 0 initiates an access to the bridge, followed by master 3 and then master 5, the bridge will propagate the access from master 0 (and respond with SPLIT on a read access) and then respond with SPLIT to the other masters. When the bridge has a response for master 0, this master will be allowed in arbitration again by the bridge asserting HSPLIT. When the bridge has finished serving master 0 it will allow the next queued master in arbitration, in this case master 3. Other incoming masters will receive SPLIT responses and will not be allowed in arbitration until all previous masters have been served. An incoming locked access will always be given precedence over any other masters in the queue. A burst that has initiated a pre-fetch operation will receive SPLIT and be inserted last in the master queue if the burst is longer than the maximum burst length that the bridge has been configured for. It should be noted that first-come, first-served ordering may not work well in systems where an AHB master needs to have higher priority compared to the other masters. The bridge will not prioritize any master, except for masters performing locked accesses. 2.2.10 Bus arbiter ordering Bus arbiter ordering is used when VHDL generic fcfs is set to zero. When several masters have received SPLIT and the bridge has a response for one of these masters, the master with the queued response will be allowed in to bus arbitration by the bridge asserting the corresponding HSPLIT signal. In the following clock cycle, all other masters that have received SPLIT responses will also be allowed in bus arbitration as the bridge asserts their HSPLIT signals simultaneously. By doing this the bridge defers the decision on the master to be granted next to the AHB arbiter. The bridge does not show any preference based on the order in which it issued SPLIT responses to masters, except to the master that initially started a read or write operation. Care has been taken so that the bridge shows a consistent behavior when issuing SPLIT responses. For instance, the bridge could be simplified if it could issue a SPLIT response just to be able to change state, and not initiate a new operation, to an access coming after an access that read out prefetched data. When the bridge entered its idle state it could then allow all masters in bus arbitration and resume normal operation. That solution could lead to starvation issues such as: T0: Master 1 and Master 2 have received SPLIT responses, the bridge is prefetching data for Master 1 T1: Master 1 is allowed in bus arbitration by setting the corresponding HSPLIT T2: Master 1 reads out prefetch data, Master 2 HSPLIT is asserted to let Master 2 in to bus arbitration GRIP, Apr 2018, Version 2018.1 24 www.cobham.com/gaisler GRLIB IP Core T3: Master 2 performs an access, receives SPLIT, however the bridge does not initiate an access, it just stalls in order to enter its idle state. T4: Master 2 is allowed in to bus arbitration, Master 1 initiates an access that leads to a prefetch and Master 1 receives a SPLIT response T5: Master 2 performs an access, receives SPLIT since the bridge is prefetching data for master 1 T6: Go back to T0 This pattern will repeat until Master 1 backs away from the bus and Master 2 is able to make an access that starts an operation over the bridge. In most systems it is unlikely that this behavior would introduce a bus lock. However, the case above could lead to an unexpectedly long time for Master 2 to complete its access. Please note that the example above is illustrative and the problem does not exist in the core as the core does not issue SPLIT responses to (non-locked) accesses in order to just change state but a similar pattern could appear as a result of decisions taken by the AHB arbiter if Master 1 is given higher priority than Master 2. In the case of write operations the scenario is slightly different. The bridge will accept a write immediately and will not issue a SPLIT response. While the bridge is busy performing the write on the master side it will issue SPLIT responses to all incoming accesses. When the bridge has completed the write operation on the master side it will continue to issue SPLIT responses to any incoming access until there is a cycle where the bridge does not receive an access. In this cycle the bridge will assert HSPLIT for all masters that have received a SPLIT response and return to its idle state. The first master to access the bridge in the idle state will be able to start a new operation. This can lead to the following behavior: T0: Master 1 performs a write operation, does NOT receive a SPLIT response T1: Master 2 accesses the bridge and receives a SPLIT response T2: The bridge now switches state to idle since the write completed and asserts HSPLIT for Master 2. T3: Master 1 is before Master 2 in the arbitration order and we are back at T0. In order to avoid this last pattern the bridge would have to keep track of the order in which it has issued SPLIT responses and then assert HSPLIT in the same order. This is done with first-come, firstserved ordering described in section 2.2.9. 2.2.11 AMBA SPLIT support Support for AMBA SPLIT responses is enabled/disabled through the VHDL generic split. SPLIT support should be enabled in most systems. The benefits of using SPLIT responses is that the bus on the bridge’s slave interface side can be free while the bridge is performing an operation on the master side. This will allow other masters to access the bus and generally improve system performance. The use of SPLIT responses also allows First-come, first-served transaction ordering. For configurations where the bridge is the only slave interface on a bus, it can be beneficial to implement the bridge without support for AMBA SPLIT responses. Removing support for SPLIT responses reduces the area used by the bridge and may also reduce the time required to perform accesses that traverse the bridge. It should be noted that building a bi-directional bridge without support for SPLIT responses will increase the risk of access collisions. If SPLIT support is disabled the bridge will insert wait states where it would otherwise issue a SPLIT response to a master initiating an access. This means that the arbitration ordering will be left to the bus arbiter and the bridge cannot be implemented with the First-come, first-served transaction ordering scheme. The bridge will still issue RETRY responses to resolve dead lock conditions, to split up long burst and also when the bridge is busy emptying it’s write buffer on the master side. GRIP, Apr 2018, Version 2018.1 25 www.cobham.com/gaisler GRLIB IP Core 2.2.12 Core latency The delay incurred when performing an access over the core depends on several parameters such as core configuration, the operating frequency of the AMBA buses, AMBA bus widths and memory access patterns. Table 22 below shows core behavior in a system where both AMBA buses are running at the same frequency and the core has been configured to use AMBA SPLIT responses. Table 23 further down shows core behavior in the same system without support for SPLIT responses. Table 22. Example of single read with FFACT = 1, and SPLIT support Clock cycle Core slave side activity Core master side activity 0 Discovers access and transitions from idle state Idle 1 Slave side waits for master side, SPLIT response is given to incoming access, any new incoming accesses also receive SPLIT responses. Discovers slave side transition. Master interface output signals are assigned. 2 3 If bus access is granted, perform address phase. Otherwise wait for bus grant. Register read data and transition to data ready state. 4 Discovers that read data is ready, assign read data output and assign SPLIT complete 5 SPLIT complete output is HIGH 6 Typically a wait cycle for the SPLIT:ed master to be allowed into arbitration. Core waits for master to return. Other masters receive SPLIT responses. 7 Master has been allowed into arbitration and performs address phase. Core keeps HREADY high 8 Access data phase. Core has returned to idle state. Idle Table 23. Example of single read with FFACT = 1, without SPLIT support Clock cycle Core slave side activity Core master side activity 0 Discovers access and transitions from idle state Idle 1 Slave side waits for master side, wait states are inserted on the AMBA bus. Discovers slave side transition. Master interface output signals are assigned. 2 Bus access is granted, perform address phase. 3 Register read data and transition to data ready state. 4 Discovers that read data is ready, assign HREADY output register and data output register. 5 HREADY is driven on AMBA bus. Core has returned to idle state Idle While the transitions shown in tables 22 and 23 are simplified they give an accurate view of the core delay. If the master interface needs to wait for a bus grant or if the read operation receives wait states, these cycles must be added to to the cycle count in the tables. The behavior of the core with a fre- GRIP, Apr 2018, Version 2018.1 26 www.cobham.com/gaisler GRLIB IP Core quency factor of two between the buses is shown in tables 24 and 25 (best case, delay may be larger depending on on which slave clock cycle an access is made to the core). Table 24. Example of single read with FFACT = 2, Master freq. > Slave freq, without SPLIT support Slave side clock cycle Core slave side activity Master side clock cycle 0 Discovers access and transitions from idle state 1 Slave side waits for master side, wait states are inserted on the AMBA bus. 2 0 Discovers slave side transition. Master interface output signals are assigned. 1 Bus access is granted, perform address phase. 2 Register read data and transition to data ready state. 3 Idle 3 4 5 6 Discovers that read data is ready, assign HREADY output register and data output register. 7 HREADY is driven on AMBA bus. Core has returned to idle state Core master side activity Table 25. Example of single read with FFACT = 2, Master freq. > Slave freq, without SPLIT support Slave side clock cycle 0 1 Core slave side activity Master side clock cycle Core master side activity Discovers access and transitions from idle state 0 Idle Slave side waits for master side, wait states are inserted on the AMBA bus. 2 Discovers slave side transition. Master interface output signals are assigned. 3 Bus access is granted, perform address phase. 1 2 Discovers that read data is ready, assign HREADY output register and data output register. 4 Register read data and transition to data ready state. 5 Idle 3 HREADY is driven on AMBA bus. Core has returned to idle state 6 7 Table 26 below lists the delays incurred for single operations that traverse the bridge while the bridge is in its idle state. The second column shows the number of cycles it takes the master side to perform the requested access, this column assumes that the master slave gets access to the bus immediately and that each access is completed with zero wait states. The table only includes the delay incurred by traversing the core. For instance, when the access initiating master reads the core’s prefetch buffer, each additional read will consume one clock cycle. However, this delay would also have been present if the master accessed any other slave. Write accesses are accepted with zero wait states if the bridge is idle, this means that performing a write to the idle core does not incur any extra latency. However, the core must complete the write operation on the master side before it can handle a new access on the slave side. If the core has not transitioned into its idle state, pending the completion of an earlier access, the delay suffered by an access be longer than what is shown in the tables in this section. Accesses may also suffer increased delays during collisions when the core has been instantiated to form a bi-directional bridge. Locked accesses that abort on-going read operations will also mean additional delays. GRIP, Apr 2018, Version 2018.1 27 www.cobham.com/gaisler GRLIB IP Core If the core has been implemented to use AMBA SPLIT responses there will be an additional delay where, typically, one cycle is required for the arbiter to react to the assertion of HSPLIT and one clock cycle for the repetition of the address phase. Note that if the core has support for read and/or write combining, the number of cycles required for the master will change depending on the access size and length of the incoming burst access. For instance, in a system where the bus in the core’s master side is wider than the bus on the slave side, write combining will allow the core to accept writes with zero wait states and then combine several accesses into one or several larger access. Depending on memory controller implementation this could reduce the time required to move data to external memory, and will reduce the load on the master side bus. Table 26. Access latencies Access Master acc. cycles Slave cycles Delay incurred by performing access over core Single read 3 1 1 * clkslv + 3 * clkmst Burst read with prefetch 2 + (burst length)x 2 2 * clkslv + (2 + burst length)* clkmst Single writexx (2) 0 0 Burst writexx (2 + (burst length)) 0 0 x A prefetch xx The operation ends at the address boundary defined by the prefetch buffer’s size core implements posted writes, the number of cycles taken by the master side can only affect the next access. 2.2.13 Endianness The core is designed for big-endian systems. 2.3 Registers The core does not implement any registers. 2.4 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x020. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 2.5 Implementation 2.5.1 Technology mapping The uni-directional AHB to AHB bridge has two technology mapping generics memtech and fcfsmtech. memtech selects which memory technology that will be used to implement the FIFO memories. fcfsmtech selects the memory technology to be used to implement the First-come, first-served buffer, if FCFS is enaled. 2.5.2 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support grlib_async_reset_enable. All registers that react on the reset signal will have a synchronous reset. GRIP, Apr 2018, Version 2018.1 28 www.cobham.com/gaisler GRLIB IP Core 2.5.3 RAM usage The uni-directional AHB to AHB bridge instantiates one or several syncram_2p blocks from the technology mapping library (TECHMAP). If prefetching is enabled max(mstmaccsz, slvaccsz)/32 syncram_2p block(s) with organization (max(rburst,iburst)-max(mstmaccsz, slvaccsz)/32) x 32 is used to implement read FIFO (max(rburst,iburst) is the size of the read FIFO in 32-bit words). max(mstmaccsz, slvaccsz)/32 syncram_2p block(s) with organization (wburst - max(mstmaccsz, slvaccsz)/32) x 32, is always used to implement the write FIFO (where wburst is the size of the write FIFO in 32-bit words). If the core has support for first-come, first-served ordering then one fcfs x 4 syncram_2p block will be instantiated, using the technology specified by the VHDL generic fcfsmtech. 2.6 Configuration options Table 27 shows the configuration options of the core (VHDL generics). Table 27. Configuration options (VHDL generics) Generic Function memtech Memory technology Allowed range Default hsindex Slave I/F AHB index 0 to NAHBMAX-1 0 hmindex Master I/F AHB index 0 to NAHBMAX-1 0 dir 0 - clock frequency on the master bus is lower than or equal to the frequency on the slave bus 1 - clock frequency on the master bus is higher than or equal to the frequency on the slave bus 0-1 0 (for VHDL generic ffact = 1 the value of dir does not matter) ffact Frequency scaling factor between AHB clocks on master and slave buses. 1 - 15 2 slv Slave bridge. Used in bi-directional bridge configuration where slv is set to 0 for master bridge and 1 for slave bridge. When a deadlock condition is detected slave bridge (slv=1) will give RETRY response to current access, effectively resolving the deadlock situation. 0-1 0 This generic must only be set to 1 for a bridge where the frequency of the bus connecting the master interface is higher or equal to the frequency of the AHB bus connecting to the bridge’s slave interface. Otherwise a race condition during access collisions may cause the bridge to deadlock. pfen Prefetch enable. Enables read FIFO. 0-1 0 irqsync Interrupt forwarding. Forward interrupts from slave 0-3 interface to master interface and vice versa.  0 - no interrupt forwarding, 1 - forward interrupts 1 - 15,  2 - forward interrupts 0 - 31. 3 - forward interrupts 0 - 31. Since interrupts are forwarded in both directions, interrupt forwarding should be enabled for one bridge only in a bi-directional AHB/AHB bridge. 0 wburst Length of write bursts in 32-bit words. Determines write 2 - 32 FIFO size and write burst address boundary. If the wburst generic is set to 2 the bridge will not perform write bursts over a 2x4=8 byte boundary. This generic must be set so that the buffer can contain two of the maximum sized accesses that the bridge can handle. 8 GRIP, Apr 2018, Version 2018.1 29 www.cobham.com/gaisler GRLIB IP Core Table 27. Configuration options (VHDL generics) Generic Function Allowed range Default iburst Instruction fetch burst length. This value is only used if the generic ibrsten is set to 1. Determines the length of prefetching instruction read bursts on the master side. The maximum of (iburst,rburst) determines the size of the core’s read buffer FIFO. 4-8 8 rburst Incremental read burst length. Determines the maximum length of incremental read burst of unspecified length (INCR) on the master interface. The maximum of rburst and iburst determine the read burst boundary. As an example, if the maximum value of these generics is 8 the bridge will not perform read bursts over a 8x4=32 byte boundary. 4 - 32 8 This generic must be set so that the buffer can contain two of the maximum sized accesses that the bridge can handle. For systems where AHB masters perform fixed length burst (INCRx , WRAPx) rburst should not be less than the length of the longest fixed length burst. bar0 Address area 0 decoded by the bridge’s slave interface. Appears as memory address register (BAR0) on the slave interface. The generic has the same bit layout as bank address registers with bits [19:18] suppressed (use functions ahb2ahb_membar and ahb2ahb_iobar in gaisler.misc package to generate this generic). 0 - 1073741823 0 bar1 Address area 1 (BAR1) 0 - 1073741823 0 bar2 Address area 2 (BAR2) 0 - 1073741823 0 bar3 Address area 3 (BAR2) 0 - 1073741823 0 sbus The number of the AHB bus to which the slave interface is connected. The value appears in bits [1:0] of the userdefined register 0 in the slave interface configuration record and master configuration record. 0-3 0 mbus The number of the AHB bus to which the master interface is connected. The value appears in bits [3:2] of the user-defined register 0 in the slave interface configuration record and master configuration record. 0-3 0 ioarea Address of the I/O area containing the configuration area for AHB bus connected to the bridge’s master interface. This address appears in the bridge’s slave interface userdefined register 1. In order for a master on the slave interface’s bus to access the configuration area on the bus connected to the bridge’s master interface, the I/O area must be mapped on one of the bridge’s BARs. 0 - 16#FFF# 0 0-1 0 If this generic is set to 0, some tools, such as Cobham Gaisler’s GRMON debug monitor, will not perform Plug’n’Play scanning over the bridge. ibrsten Instruction fetch burst enable. If set, the bridge will perform bursts of iburst length for opcode access (HPROT[0] = ‘0’), otherwise bursts of rburst length will be used for both data and opcode accesses. GRIP, Apr 2018, Version 2018.1 30 www.cobham.com/gaisler GRLIB IP Core Table 27. Configuration options (VHDL generics) Generic Function Allowed range Default lckdac Locked access error detection and correction. Locked accesses may lead to deadlock if a locked access is made while an ongoing read access has received a SPLIT response. The value of lckdac determines how the core handles this scenario: 0-2 0 0: Core will deadlock 1: Core will issue an AMBA ERROR response to the locked access 2: Core will allow both accesses to complete. If the core is used to create a bidirectional bridge, a deadlock condition may arise when locked accesses are made simultaneously in both directions. With lckdac set to 0 the core will deadlock. With lckdac set to a non-zero value the slave bridge will issue an ERROR response to the incoming locked access. slvmaccsz The maximum size of accesses that will be made to the bridge’s slave interface. This value must equal mstmaccsz unless rdcomb /= 0 and wrcomb /= 0. 32 - 256 32 mstmaccsz The maximum size of accesses that will be performed by 32 - 256 the bridge’s master interface. This value must equal mstmaccsz unless rdcomb /= 0 and wrcomb /= 0. 32 rdcomb Read combining. If this generic is set to a non-zero value the core will use the master interface’s maximum AHB access size when prefetching data and allow data to be read out using any other access size supported by the slave interface. 0-2 0 0-2 0 If slvmaccsz > 32 and mstmaccsz > 32 and an incoming single access, or access to a non-prefetchable area, is larger than the size supported by the master interface the bridge will perform a series of small accesses in order to fetch all the data. If this generic is set to 2 the core will use a burst of small fetches. If this generic is set to 1 the bridge will not use a burst unless the incoming access was a burst. Read combining is only supported for single accesses and incremental bursts of unspecified length. wrcomb Write combining. If this generic is set to a non-zero value the core may assemble several small write accesses (that are part of a burst) into one or more larger accesses or assemble one or more accesses into several smaller accesses. The settings are as follows: 0: No write combining 1: Combine if burst can be preserved 2: Combine if burst can be preserved and allow single accesses to be converted to bursts (only applicable if slvmaccsz > 32) Only supported for single accesses and incremental bursts of unspecified length GRIP, Apr 2018, Version 2018.1 31 www.cobham.com/gaisler GRLIB IP Core Table 27. Configuration options (VHDL generics) Generic Function Allowed range Default combmask Read/write combining mask. This generic determines which ranges that the core can perform read/write combining to (only available when rdcomb respectively wrcomb are non-zero). The value given for combmask is treated as a 16-bit vector with LSB bit (right-most) indicating address 0x0 - 0x10000000. Making an access to an address in an area marked as ‘0’ in combmask is equivalent to making an access over a bridge with rdcomb = 0 and wrcomb = 0. However, combmask is not taken into account when the core performs a prefetch operation (see pfen generic). When a prefetch operation is initiated, the core will always use the maximum supported access size (when rdcomb /= 0). 0 - 16#FFFF# 16#FFFF# allbrst Support all burst types 0-2 0 0-1 0 0 - NAHBMST 0 2: Support all types of burst and always prefetch for wrapping and fixed length bursts. 1: Support all types of bursts 0: Only support incremental bursts of unspecified length See section 2.2.7 for more information. When allbrst is enabled, the core’s read buffer (size set via rburst/iburst generics) must have at least 16 slots. ifctrlen Interface control enable. When this generic is set to 1 the input signals ifctrl.mstifen and ifctrl.slvifen can be used to force the AMBA slave respectively master interface into an idle state. This functionality is intended to be used when the clock of one interface has been gated-off and any stimuli on one side of the bridge should not be propagated to the interface on the other side of the bridge. When this generic is set to 0, the ifctrl.* input signals are unused. fcfs First-come, first-served operation. When this generic is set to a non-zero value, the core will keep track of the order of incoming accesses and handle the requests in the same order. If this generic is set to zero the bridge will not preserve the order and leave this up to bus arbitration. If FCFS is enabled the value of this generic must be higher or equal to the number of masters that may perform accesses over the bridge. fcfsmtech Memory technology to use for FCFS buffer. When 0 - NTECH VHDL generic fcfs is set to a non-zero value, the core will instantiate a 4 bit x fcfs buffer to keep track of the incoming master indexes. This generic decides the memory technology to use for the buffer. 0 (inferred) scantest Enable scan support 0-1 0 split Use AMBA SPLIT responses. When this generic is set to 1 the core will issue AMBA SPLIT responses. When this generic is set to 0 the core will insert waitstates instead and may also issue AMBA RETRY responses. If this generic is set to 0, the fcfs generic must also be set to 0, otherwise a simulation failure will be asserted. 0-1 1 GRIP, Apr 2018, Version 2018.1 32 www.cobham.com/gaisler GRLIB IP Core Table 27. Configuration options (VHDL generics) Generic Function Allowed range pipe This setting controls the insertion of pipeline registers between the master and slave side of the bridge. 0, 1, 128 Default pipe set to 0 does not include any extra pipeline registers and the incurred delays for accesses over the bridge is as described in this documentation. pipe set to 1 includes extra registers on all signals between the master and slave side. pipe set to 2 includes pipeline registers on all signals going from the slave interface to the master interface and does NOT insert extra registers on signals going from the master interface to the slave interface. pipe set to 3 includes pipeline registers on all signals going from the master interface to the slave interface and does NOT insert extra registers on signals going from the slave interface to the master interface. pipe set to 128 includes signals on a subset of the signals to prevent direct paths from the slave clock to the master side bus and from the master clock to the slave side bus. GRIP, Apr 2018, Version 2018.1 33 www.cobham.com/gaisler GRLIB IP Core 2.7 Signal descriptions Table 28 shows the interface signals of the core (VHDL ports). Table 28. Signal descriptions (VHDL ports) Signal name Field Type Function Active RST Input Reset Low HCLKM Input AHB master bus clock - HCLKS Input AHB slave bus clock - AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - AHBMI * Input AHB master input signals - AHBMO * Output AHB master output signals - AHBSO2 * Input AHB slave input vector signals (on master i/f side). Used to decode cachability and prefetchability Plug&Play information on bus connected to the bridge’s master interface. - LCKI slck blck mlck Input Used in systems with multiple AHB/AHB bridges (e.g. bi-directional AHB/AHB bridge) to detect deadlock conditions. Tie to “000” in systems with only uni-directional AHB/AHB bus. High LCKO slck blck mlck Output Indicates possible deadlock condition High IFCTRL mstifen Input Enable master interface. This input signal is High unused if the VHDL generic ifctrlen is 0. If VHDL generic ifctrlen is 1 this signal must be set to ‘1’ in order to enable the core’s AMBA master interface, otherwise the master interface will always be idle and will not respond to stimuli on the core’s AMBA slave interface. This signal is intended to be used to keep the core’s master interface in a good state when the core’s slave interface clock has been gated off. Care should be taken to ensure that the bridge is idle when the master interface is disabled. slvifen Input Enable slave interface. This input signal is unused if the VHDL generic ifctrlen is 0. If VHDL generic ifctrlen is 1 this signal must be set to ‘1’ in order to enable the core’s AMBA slave interface, otherwise the interface will always be ready and the bridge will not propagate stimuli on the core’s AMBA slave interface to the core’s AMBA master interface. This signal is intended to be used to keep the slave interface in a good state when the core’s master interface clock has been gated off. Care should be taken to ensure that the bridge is idle when the slave interface is disabled. High * see GRLIB IP Library User’s Manual GRIP, Apr 2018, Version 2018.1 34 www.cobham.com/gaisler GRLIB IP Core 2.8 Library dependencies Table 29 shows the libraries used when instantiating the core (VHDL libraries). Table 29. Library dependencies 2.9 Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Component Component declaration Instantiation GRLIB contains two example designs with AHB2AHB and LEON processors: designs/leon3ahb2ahb (only available in commercial distributions) and designs/leon4-ahb2ahb (only in distributions that include LEON4 processor). The LEON/GRLIB Configuration and Development Guide contains more information on how to use the bridge to create multi-bus systems. GRIP, Apr 2018, Version 2018.1 35 www.cobham.com/gaisler GRLIB IP Core 3 AHBM2AXI - AHB Master to AXI Adapter 3.1 Overview The AHBM2AXI adapter allows a single AHB master to be used as an AXI3 or AXI4 master. The adapter has an AHB slave interface on the AHB side and AXI3 or AXI4 master interface on the AXI side (see Fig. 2). The adapter has optional read prefetching and write buffering features in order to improve the latency of burst operations. The adapter is not compatible with AHB2AHB and GRDMAC components which is a part of GRLIB IP library. AHB MASTER AHBM2AXI AXI SLAVE Figure 2. A standalone AHB master is connected to an AXI slave through AHBM2AXI adapter 3.1.1 AHB support The AHBM2AXI adapter currently supports the following features of the AHB protocol: Transfer Type: IDLE, NONSEQ, SEQ Burst Operation: SINGLE, INCR, INCR4, INCR8, INCR16 Data-width: 32-bit, 64-bit, 128-bit, 256-bit Transfer Size: All possible transfer sizes up to the selected data-width are supported. Response: AXI read and write error responses are translated to AHB read and write errors. Unsupported AHB Features: The following features of AHB protocol are not supported by the AHBM2AXI adapter. • BUSY transfer type : Behavior of the AHBM2AXI adapter is unpredictable when a BUSY transaction is received hence the AHBM2AXI adapter can not be used with the AHB2AHB bridge which is a part of GRLIB IP library. • Locked transfers : Locked transfers are ignored by the AHBM2AXI adapter. Unused AHB Features: • 3.2 RETRY and SPLIT responses : The adapter does not generate these response types. Special Considerations There is a combinatorial path between the incoming HTRANS signal and outgoing HREADY signal on the AHB side of the adapter, in order to allow write-buffering and write response propagation at the same time. As a result, this component is only intended to connect to a single IP core with an AHB master interface in which HTRANS output does not depend on the incoming HREADY signal combinatorially. Propagating the write response correctly is important to make sure that the intended transaction ordering has been met, meaning the AHB master that is connected to the adapter receives the acknowledgment for the last write beat in the burst when the write response has been received on the GRIP, Apr 2018, Version 2018.1 36 www.cobham.com/gaisler GRLIB IP Core AXI side. Being able to propagate correct write response can also simplify the software development. The AHBM2AXI adapter can not be used with the GRDMAC IP core which is a part of GRLIB IP library. 3.3 Operation 3.3.1 Read Prefetching and Write Buffering The adapter has the feature of read prefetching and write buffering for the AHB bursts in which the transfer size (HSIZE) is equal to the selected data-width. For the transfer sizes that are narrower than the data-width each beat in the burst treated as a single transaction on the AXI side. Read prefetching and write buffering reduces the latency of undefined length burst operations since otherwise each beat in an undefined length burst has to be treated as an independent AXI transaction with a length of one. 3.3.2 Read Prefetching Read prefetch number that is set through rprefetch_num generic determines the length of the AXI transaction(s) that is generated when an undefined length AHB read burst is encountered. When an undefined length AHB read burst is encountered, an AXI transaction is generated with a length of rprefetch_num. If the AHB read burst has less beats than rprefetch_num then dummy reads are generated on the AXI side to complete the AXI transaction. If the AHB read burst has more beats than rprefetch_num then a new AXI transaction is generated with a number of beats equal to rprefetch_num and this scheme continuous until the AHB burst ends. If the start address of a burst is not aligned to the prefetch boundary then the initial prefetch has less number of beats in order to align the upcoming prefetches. For example given a 32-bit (4 Byte) data-width and a rprefetch_num of 16 (16*4=64 Bytes) if the least significant bits of the initial burst address corresponds to byte 48, then the initial prefetch length is 4 ((64-48)/4). This way the upcoming prefetches are always aligned to 64 Byte boundary. If a new AHB burst is encountered during dummy read operations on the AXI side, the AHB burst is stalled until the current AXI transaction ends. The maximum read prefetch number depends on the AXI protocol. For AXI3 the maximum number is 16, and for AXI4 it can be up to 256 depending on the selected data-width. Prefetch length can only be a power of two and if it is not set to be a power of two then the number is floored to the closest power of two automatically. For fixed length AHB bursts (single, INCR4, INCR8, INCR16) the length of the AXI burst is equal to the AHB burst length since in those cases the burst length is known at the beginning of the burst. The adapter will not issue a new AXI transaction while dummy cycles are inserted hence there is a trade-off for performance when selecting the read prefetch number. 3.3.3 Write Buffering Write buffering gathers a number of consecutive beats in a AHB write burst and initiates an AXI transaction. A generic called wbuffer_num determines the maximum number of AHB write burst beats that will be gathered before an AXI write burst transaction is generated. If the number of beats in the AHB write burst is less than wbuffer_num then the AXI write transaction starts after detecting the last beat in the burst (transition from SEQ to IDLE). If the number of beats are higher than wbuffer_num then the first AXI transaction is generated once wbuffer_num number of beats are buffered. It should be noted that once an AXI write transaction is generated and AHB burst still continues then AXI transaction and buffering for the next write batch happens in parallel to minimize the latency. This scheme continuous until the AHB burst is ended. When the last data beat of the burst is reached the HREADY on the AHB side is asserted once the write response is received from the AXI side. The write buffering feature is used for the fixed size burst also in the same way as undefined length bursts. GRIP, Apr 2018, Version 2018.1 37 www.cobham.com/gaisler GRLIB IP Core Write buffer length can only be a power of two, and if it is not set to be a power of two then the number is floored to the closest power of two automatically. The maximum number has the same constraints as the read prefetch number. A synchronous memory width one read and write port is generated for write buffering. The size of the memory is determined by the write buffer length. The type of the memory can be configured with a generic also. The first AXI write transaction will not start until the buffer is filled or the AHB transaction has written the last beat in the burst. As a result there is a trade-off for performance while selecting the write buffer length which depends on the AXI slave behavior. 3.3.4 Endianness The AHB side of the AHB2AXIB bridge is always assumed to be big-endian. The endianness on the AXI side is configurable through the endianness_mode generic. When endianness_mode generic is set to zero a byte-invariant big-endian endianness mode is used on the AXI side. In order to translate big-endian AHB to byte-invariant big-endian AXI the byte order is reversed (see Fig. 3). No address translation occurs inside the adapter in this mode. (Bit position) (31) AHB DATA-BUS B3 (0) B2 B1 B0 MSB MSB AXI DATA-BUS B0 B1 (Bit position) (31) B2 B3 (0) Figure 3. Big-endian AHB to byte-invariant Big-endian AXI translation (32-bit data-width) When endianness_mode generic is set to one then big-endian AHB is translated to little-endian AXI. In order to achieve this the byte order is preserved but the address is translated from big-endian representation to little-endian representation when a narrow sized transaction is encountered (See Fig. 4 for an example with 32-bit data-bus width.). The address translation formula for 32-bit, 64-bit, 128-bit and 256-bit data-bus widths are following: 32-bit data bus width: if HSIZE < “010” : axi_address(1:0) = (“100” - “1”<<“HSIZE” - ahb_address(1:0))(1:0) otherwise: axi_address(1:0) = ahb_address(1:0) 64-bit data bus width: if HSIZE < “011” : axi_address(2:0) = (“1000” - “1”<<“HSIZE” - ahb_address(2:0))(2:0) otherwise: axi_address(2:0) = ahb_address(2:0) GRIP, Apr 2018, Version 2018.1 38 www.cobham.com/gaisler GRLIB IP Core 128-bit data bus width: if HSIZE < “100” : axi_address(3:0) = (“10000” - “1”<<“HSIZE” - ahb_address(3:0))(3:0) otherwise: axi_address(3:0) = ahb_address(3:0) 256-bit data bus width: if HSIZE < “101” : axi_address(4:0) = (“100000” - “1”<<“HSIZE” - ahb_address(4:0))(4:0) otherwise: axi_address(4:0) = ahb_address(4:0) (Bit position) (31) AHB DATA-BUS B3 (0) B2 B1 When HSIZE = “010” no translation B0 When HSIZE = “001” AHB-side “00” -> AXI-side “10” AHB-side “10” -> AXI-side “00” MSB MSB AXI DATA-BUS B3 Address translation for 32-bit data-bus width (address bits 1 and 0 is translated) B2 B1 (Bit position) (31) B0 (0) When HSIZE = “000” AHB-side “00” -> AXI-side “11” AHB-side “01” -> AXI-side “10” AHB-side “10” -> AXI-side “01” AHB-side “00” -> AXI-side “00” Figure 4. Big-endian AHB to little-endian AXI through address translation (32-bit data-width) 3.4 AXI AxPROT and AxCACHE Translations The AxPROT and AxCACHE signals are translated partly according to the HPROT signal of AHB transactions. The full list of translation can be seen from Table 30. Table 30. AxPROT and AxCACHE translations AXI signal Assignment AxCACHE[3] always logic ‘0’ AxCACHE[2] always logic ‘0’ AxCACHE[1] HPROT[3] AxCACHE[0] HPROT[2] AxPROT[2] not (HPROT[0]) AxPROT[1] See configuration options (Table. 31) AxPROT[0] HPROT[1] GRIP, Apr 2018, Version 2018.1 39 www.cobham.com/gaisler GRLIB IP Core 3.5 Configuration Options Table 31. Configuration options (both AHBM2AXI3 and AHBM2AXI4) Generic Function Allowed range Default memtech Memory technology aximid AXI master ID used for Read and Write transactions 0 - 15 0 always_secure When set to 1 the AxPROT[1] bit is tied to logic ‘0’ (always secure access), when set to 0 the AxPROT[1] bit is tied to logic ‘1’ (always unsecure access). 0-1 1 endianness_mode Determines the endianness mode (see section 3.3.4 for more detail) 0-1 0 0 -> Big-endian AHB to byte-invariant big-endian AXI 1 -> Big-endian AHB to little-endian AXI Table 32. Configuration options specific for AXI3 (AHBM2AXI3) Generic Function Allowed range Default wbuffer_num Write-buffer length which determines the memory size also. 1-16 8 rprefetch_num Read prefetch length. 1-16 8 Table 33. Configuration options specific for AXI4 (AHBM2AXI4) Generic Function Allowed range Default wbuffer_num Write-buffer length which determines the memory size also. 1-256 for data-width of 32-bit, 8 1-128 for data-width of 64-bit 1-64 for data-width of 128-bit 1-32 for data-width of 256-bit rprefetch_num Read prefetch length. 1-256 for data-width of 32-bit, 8 1-128 for data-width of 64-bit 1-64 for data-width of 128-bit 1-32 for data-width of 256-bit GRIP, Apr 2018, Version 2018.1 40 www.cobham.com/gaisler GRLIB IP Core 3.6 Signal descriptions Table 34 shows the interface signals of the core (VHDL ports). Table 34. Signal descriptions (VHDL ports) Signal name Field Type Function Active RST Input Reset Low CLK Input AHB & AXI bus clock - AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - AXIMI * Input AXI3/4 master input signals - AXIMO * Output AXI3/4 master output signals - * see GRLIB IP Library User’s Manual 3.7 Library dependencies Table 35 shows the libraries used when instantiating the core (VHDL libraries). Table 35. Library dependencies 3.8 Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA & AXI signal definitions GAISLER AXI Component Component declaration Instantiation The instantiation of the AHBM2AXI adapter depends on the AXI protocol type. There are two components called AHBM2AXI3 which is built for AXI3 protocl and AHBM2AXI4 which is built for AXI4 protocol. The difference between these two components are the AXI master output signals and the maximum values that can be set for read prefetching and write buffering. Since AHBM2AXI adapter is intended to be used for only a single core, a transaction is sampled and evaluated directly on the rising edge of the clock, the “hsel” and “hready” inputs are ignored by the AHBM2AXI adapter. The grant signal for the AHB master that is connected to the adapter should be hardwired to logic 1. Following is an example in which a component with an ahb master interface called “ahbm_ex” is connected to the AHBM2AXI4 adapter which can act as an master for AXI4 protocol. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.axi.all; entity ahbm2axi4_ex is port ( rstn : in std_logic; GRIP, Apr 2018, Version 2018.1 41 www.cobham.com/gaisler GRLIB IP Core clk : in std_logic; aximi : in axi_somi_type; aximo : out axi4_mosi_type ); end; architecture rtl of ahbm2axi4_ex is signal signal signal signal ahbsi ahbso ahbmi ahbmo : : : : in out in out ahb_slave_in_type; ahb_slave_out_type; ahb_mst_in_type; ahb_mst_out_type; component ahbm_ex is port ( signal rstn : in std_logic; signal clk : in std_logic; signal ahbmi : in ahb_mst_in_type; signal ahbmo : out ahb_mst_out_type); end component; begin adapter:ahbm2axi4 generic map ( memtech => 0, aximid => 0, wbuffer_num => 16, rprefetch_num=> 16, always_secure => 1 ) port map ( rstn => rstn, clk => clk, ahbsi => ahbsi, ahbso => ahbso, aximi => aximi, aximo => aximo); ahbmaster:ahbm_ex port map ( rstn => rstn, clk => clk, ahbmi => ahbmi, ahbmo => ahbmo); ahbsi.haddr ahbsi.hwrite ahbsi.htrans ahbsi.hsize ahbsi.hburst ahbsi.hwdata ahbsi.hprot <= <= <= <= <= <= <= ahbmo.hadddr; ahbmo.hwrite; ahbmo.htrans; ahbmo.hsize; ahbmo.hburst; ahbmo.hwdata; ahbmo.hprot; ahbmi.hgrant <= (others=> ‘1’); ahbmi.hready <= ahbso.hready; ahbmi.hresp <= ahbso.hresp; ahbmi.hrdata <= ahbso.hrdata; --Remaining ahb master inputs are implementation dependent GRIP, Apr 2018, Version 2018.1 42 www.cobham.com/gaisler GRLIB IP Core GRIP, Apr 2018, Version 2018.1 43 www.cobham.com/gaisler GRLIB IP Core 4 AHB2AXIB - AHB to AXI Bridge 4.1 Overview The AHB2AXIB bridge allows to access an AXI3 or AXI4 slave from an AHB bus through an AHB slave interface (see Fig. 5). It can also be used to connect a standalone AHB master to an AXI slave (see Fig. 6). The bridge has an AHB slave interface on the AHB side and AXI3 or AXI4 master interface on the AXI side. The bridge has optional read prefetching and write buffering features in order to improve the latency of burst operations. The AHB2AXIB bridge is not compatible with the AHB2AHB bridge which is a part of GRLIB IP library. AHB MASTER-0 AHB MASTER-N AHB Controller AHB BUS AHB2AXIB AXI SLAVE Figure 5. An AXI slave connected to the AHB bus through AHB2AXIB bridge AHB MASTER AHB2AXIB AXI SLAVE Figure 6. A standalone AHB master is connected to an AXI slave through AHB2AXIB bridge 4.1.1 AHB support The AHB2AXIB bridge currently supports the following features of the AHB protocol: Transfer Type: IDLE, NONSEQ, SEQ Burst Operation: SINGLE, INCR, INCR4, INCR8, INCR16 Data-width: 32-bit, 64-bit, 128-bit, 256-bit Transfer Size: All possible transfer sizes up to the selected data-width are supported. Response: AXI read error response is translated to AHB read error. Unsupported AHB Features: The following features of AHB protocol are not supported by the AHB2AXIB bridge. GRIP, Apr 2018, Version 2018.1 44 www.cobham.com/gaisler GRLIB IP Core • BUSY transfer type : Behavior of the AHB2AXIB bridge is unpredictable when a BUSY transaction is received hence the AHB2AXIB bridge can not be used with the AHB2AHB bridge which is a part of GRLIB IP library. • Locked transfers : Locked transfers are ignored by the AHB2AXIB bridge. Unused AHB Features: 4.2 • RETRY and SPLIT responses ; AHB2AXIB bridge does not generate these response types. • Write error response : Due to the difference between the write error handling of AXI and AHB protocol the write errors received from the AXI side is not propagated. Operation 4.2.1 Read Prefetching and Write Buffering and Postponed Writes The bridge has the feature of read prefetching and write buffering for the AHB bursts in which the transfer size (HSIZE) is equal to the selected data-width. For the transfer sizes that are narrower than the data-width it can still support read prefetching and write buffering if byte invariant big endian mode is used. Otherwise each beat in the burst treated as a single transaction on the AXI side. Read prefetching and write buffering reduces the latency of undefined length burst operations since otherwise each beat in an undefined length burst has to be treated as an independent AXI transaction with a length of one. 4.2.2 Read Prefetching Read prefetch number that is set through rprefetch_num generic determines the length of the AXI transaction(s) that is generated when an undefined length AHB read burst is encountered. When an undefined length AHB read burst is encountered, an AXI transaction is generated with a length of rprefetch_num. If the AHB read burst has less beats than rprefetch_num then dummy reads are generated on the AXI side to complete the AXI transaction. If the AHB read burst has more beats than rprefetch_num then a new AXI transaction is generated with a number of beats equal to rprefetch_num and this scheme continuous until the AHB burst ends. If the start address of a burst is not aligned to the prefetch boundary then the initial prefetch has less number of beats in order to align the upcoming prefetches. For example given a 32-bit (4 Byte) data-width and a rprefetch_num of 16 (16*4=64 Bytes) if the least significant bits of the initial burst address corresponds to byte 48, then the initial prefetch length is 4 ((64-48)/4). This way the upcoming prefetches are always aligned to 64 Byte boundary. If a new AHB burst is encountered during dummy read operations on the AXI side, the AHB burst is stalled until the current AXI transaction ends. The maximum read prefetch number depends on the AXI protocol. For AXI3 the maximum number is 16, and for AXI4 it can be up to 256 depending on the selected data-width. Prefetch length can only be a power of two and if it is not set to be a power of two then the number is floored to the closest power of two automatically. For fixed length AHB bursts (single, INCR4, INCR8, INCR16) the length of the AXI burst is equal to the AHB burst length since in those cases the burst length is known at the beginning of the burst. The bridge will not issue a new AXI transaction while dummy cycles are inserted hence there is a trade-off for performance when selecting the read prefetch number. 4.2.3 Write Buffering Write buffering gathers a number of consecutive beats in a AHB write burst and initiates an AXI transaction. A generic called wbuffer_num determines the maximum number of AHB write burst beats that will be gathered before an AXI write burst transaction is generated. If the number of beats GRIP, Apr 2018, Version 2018.1 45 www.cobham.com/gaisler GRLIB IP Core in the AHB write burst is less than wbuffer_num then the AXI write transaction starts after detecting the last beat in the burst (transition from SEQ to IDLE). If the number of beats are higher than wbuffer_num then the first AXI transaction is generated once wbuffer_num number of beats are buffered. It should be noted that once an AXI write transaction is generated and AHB write burst still continues then AXI transaction and buffering of the next write batch happens in parallel to improve the latency. This scheme continuous until the AHB burst is ended. The last data beat in the burst is always acknowledged with OKAY response immediately when it is buffered in the bridge. See section 4.2.5 for more detailed information. Write buffer length can only be a power of two, and if it is not set to be a power of two then the number is floored to the closest power of two automatically. The maximum number has the same constraints as the read prefetch number. A synchronous memory width one read and write port is generated for write buffering. The size of the memory is determined by the write buffer length. The type of the memory can be configured with a generic also. The first AXI write transaction will not start until the buffer is filled or the AHB transaction has written the last beat in the burst. As a result there is a trade-off for performance while selecting the write buffer length which depends on the AXI slave behavior. 4.2.4 Narrow Sized Transactions When an AHB transaction is encountered which has a narrower size (HSIZE) than the data-width of the AHB2AXIB bridge, the behavior is configurable through the generics depending on the selected endianness on the AXI side. When the endianness mode on the AXI side is set as little-endian than each beat in the narrow sized AXI transaction is treated as single transaction on the AXI side. When the endinness mode on the AXI side is set as byte invariant big-endian than the narrow_acc_mode generic determines the behaviour. If the narrow_acc_mode generic is set as zero than each beat in the narrow sized AXI transaction is treated as single transaction on the AXI side. If it is set to 1 then a corresponding narrow sized AXI burst is generated with read prefetching and write buffering. But it should be noted that the length of the narrow sized burst will be determined by rprefetch_num and wbuffer_num generics and it is same as for all access sizes. When the endianness on the AXI side is set ass little-endian then narrow_acc_mode generic must be set to zero. See sec. 4.2.6 for more detailed information about endianness modes. 4.2.5 Postponed Writes Since the write response from AXI is not propagated to AHB side the last beat in the AHB write transaction is acknowledged immediately when it is buffered in the bridge. Hence the corresponding AXI write transaction will finish after the AHB write transaction is completed. The transaction order on the AHB bus side will be preserved because the bridge will block an AHB read, if there is an AXI write transaction is ongoing, until the AXI write response is received. But if a transaction order has to be preserved between the AHB side of a AHB2AXIB bridge and an independent AXI master that accesses to the same AXI slave then special considerations in software might be needed. If the AHB2AXIB bridge is intended to be used for a single AHB master without an AHB bus then it is possible to use the AHBM2AXI adapter that is a part of GRLIB IP library if the AHB master is compatible. The AHBM2AXI adapter propagates the AXI write response. 4.2.6 Endianness The AHB side of the AHB2AXIB bridge is always assumed to be big-endian. The endianness on the AXI side is configurable through the endianness_mode generic. GRIP, Apr 2018, Version 2018.1 46 www.cobham.com/gaisler GRLIB IP Core When endianness_mode generic is set to zero a byte-invariant big-endian endianness mode is used on the AXI side. In order to translate big-endian AHB to byte-invariant big-endian AXI the byte order is reversed (see Fig. 7). No address translation occurs inside the adapter in this mode. (Bit position) (31) AHB DATA-BUS B3 (0) B2 B1 B0 MSB MSB AXI DATA-BUS B0 B1 (Bit position) (31) B2 B3 (0) Figure 7. Big-endian AHB to byte-invariant Big-endian AXI translation (32-bit data-width) When endianness_mode generic is set to one then big-endian AHB is translated to little-endian AXI. In order to achieve this the byte order is preserved but the address is translated from big-endian representation to little-endian representation when a narrow sized transaction is encountered (See Fig. 8 for an example with 32-bit data-bus width.). The address translation formula for 32-bit, 64-bit, 128-bit and 256-bit data-bus widths are following: 32-bit data bus width: if HSIZE < “010” : axi_address(1:0) = (“100” - “1”<<“HSIZE” - ahb_address(1:0))(1:0) otherwise: axi_address(1:0) = ahb_address(1:0) 64-bit data bus width: if HSIZE < “011” : axi_address(2:0) = (“1000” - “1”<<“HSIZE” - ahb_address(2:0))(2:0) otherwise: axi_address(2:0) = ahb_address(2:0) 128-bit data bus width: if HSIZE < “100” : axi_address(3:0) = (“10000” - “1”<<“HSIZE” - ahb_address(3:0))(3:0) otherwise: axi_address(3:0) = ahb_address(3:0) 256-bit data bus width: if HSIZE < “101” : axi_address(4:0) = (“100000” - “1”<<“HSIZE” - ahb_address(4:0))(4:0) otherwise: axi_address(4:0) = ahb_address(4:0) GRIP, Apr 2018, Version 2018.1 47 www.cobham.com/gaisler GRLIB IP Core (Bit position) (31) AHB DATA-BUS B3 (0) B2 B1 When HSIZE = “010” no translation B0 When HSIZE = “001” AHB-side “00” -> AXI-side “10” AHB-side “10” -> AXI-side “00” MSB MSB AXI DATA-BUS B3 Address translation for 32-bit data-bus width (address bits 1 and 0 is translated) B2 B1 (Bit position) (31) B0 (0) When HSIZE = “000” AHB-side “00” -> AXI-side “11” AHB-side “01” -> AXI-side “10” AHB-side “10” -> AXI-side “01” AHB-side “00” -> AXI-side “00” Figure 8. Big-endian AHB to little-endian AXI through address translation (32-bit data-width) 4.3 AXI AxPROT and AxCACHE Translations The AxPROT and AxCACHE signals are translated partly according to the HPROT signal of AHB transactions. The full list of translation can be seen from Table 36. Table 36. AxPROT and AxCACHE translations AXI signal Assignment AxCACHE[3] always logic ‘0’ AxCACHE[2] always logic ‘0’ AxCACHE[1] HPROT[3] AxCACHE[0] HPROT[2] AxPROT[2] not (HPROT[0]) AxPROT[1] See configuration options (Table. 37) AxPROT[0] HPROT[1] GRIP, Apr 2018, Version 2018.1 48 www.cobham.com/gaisler GRLIB IP Core 4.4 Configuration Options Table 37. Configuration options (both AHB2AXI3B and AHB2AXI4B) Generic Function Allowed range Default memtech Memory technology aximid AXI master ID used for Read and Write transactions 0 - 15 0 always_secure When set to 1 the AxPROT[1] bit is tied to logic ‘0’ (always secure access), when set to 0 the AxPROT[1] bit is tied to logic ‘1’ (always unsecure access). 0-1 1 endianness_mode Determines the endianness mode (see section 4.2.6 for more detail) 0-1 0 0-1 0 0 -> Big-endian AHB to byte-invariant big-endian AXI 1 -> Big-endian AHB to little-endian AXI narrow_acc_mode Determines if bursts with narrow access size than the data-bus width should be directly translated to narrow access size AXI bursts or single AXI transactions with narrow access size. (see section 4.2.4 for more detail) 0-> Each beat in the narrow sized AHB burst is treated as single transaction on the AXI side. 1-> Narrow sized AHB bursts are translated to narrow sized AXI bursts. (supported only when endianness_mode generic is 0) Note: This generic must be set to 0 if endianness_mode is set to 1. vendor GRLIB plug&play vendor ID GAISLER device GRLIB plug&play device ID bar0 Address area 0 decoded by the bridge’s slave interface. Appears as memory address register (BAR0) on the slave interface. The generic has the same bit layout as bank address registers with bits [19:18] suppressed (use functions ahb2ahb_membar and ahb2ahb_iobar in gaisler.misc package to generate this generic). 0 - 1073741823 0 AHB2AXI bar1 Address area 1 (BAR1) 0 - 1073741823 0 bar2 Address area 2 (BAR2) 0 - 1073741823 0 bar3 Address area 3 (BAR2) 0 - 1073741823 0 Table 38. Configuration options specific for AXI3 (AHB2AXI3B) Generic Function Allowed range Default wbuffer_num Write-buffer length which determines the memory size also. 1-16 8 rprefetch_num Read prefetch length. 1-16 8 GRIP, Apr 2018, Version 2018.1 49 www.cobham.com/gaisler GRLIB IP Core Table 39. Configuration options specific for AXI4 (AHB2AXI4B) Generic Function Allowed range Default wbuffer_num Write-buffer length which determines the memory size also. 1-256 for data-width of 32-bit, 8 1-128 for data-width of 64-bit 1-64 for data-width of 128-bit 1-32 for data-width of 256-bit rprefetch_num Read prefetch length. 1-256 for data-width of 32-bit, 8 1-128 for data-width of 64-bit 1-64 for data-width of 128-bit 1-32 for data-width of 256-bit 4.5 Signal descriptions Table 40 shows the interface signals of the core (VHDL ports). Table 40. Signal descriptions (VHDL ports) Signal name Field RST CLK Type Function Active Input Reset Low Input AHB & AXI bus clock - AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - AXIMI * Input AXI3/4 master input signals - AXIMO * Output AXI3/4 master output signals - * see GRLIB IP Library User’s Manual 4.6 Library dependencies Table 41 shows the libraries used when instantiating the core (VHDL libraries). Table 41. Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA & AXI signal definitions GAISLER AXI Component Component declaration GRIP, Apr 2018, Version 2018.1 50 www.cobham.com/gaisler GRLIB IP Core 4.7 Instantiation The instantiation of the AHB2AXIB bridge depends on the AXI protocol type. There are two components called AHB2AXI3B which is built for AXI3 protocol and AHB2AXI4B which is built for AXI4 protocol. The difference between these two components are the AXI master output signals and the maximum values that can be set for read prefetching and write buffering. 4.7.1 AHB2AXIB bridge is used to connect an AXI slave to an AHB bus library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.axi.all; entity ahb2axib_ex is port ( rstn : in std_logic; clk : in std_logic; . . . aximi : in axi_somi_type; aximo : out axi4_mosi_type; ); end; architecture rtl of ahb2axib_ex is . . constant hindex_ahb2axi4b : integer := 2; begin . . ahbctrl & other components . . bridge:ahb2axi4b generic map ( hindex => hindex_ahb2axi4b, aximid => 0 ) port map ( rstn => rstn, clk => clk, ahbsi => ahbsi, ahbso => ahbso(hindex_ahb2axi4b), aximi => aximi, aximo => aximo); GRIP, Apr 2018, Version 2018.1 51 www.cobham.com/gaisler GRLIB IP Core 4.7.2 AHB2AXIB bridge is used to connect a standalone AHB master to an AXI slave. If AHB2AXIB bridge is intended to be used to connect a standalone AHB master to an AXI slave then the following assignments are needed for correct operations: The hsel input of the AHB2AXIB must be assigned to an array of (others=>’1’) so that it works regardless of the assigned hindex value. The hready input of the AHB2AXIB must be connected to the hready output of the AHB2AXIB. The hgrant input of the AHB master must be assigned to an array of (others=>’1’) so that it works regardless of the assigned hindex value. GRIP, Apr 2018, Version 2018.1 52 www.cobham.com/gaisler GRLIB IP Core 5 AHBBRIDGE - Bi-directional AHB/AHB bridge 5.1 Overview A pair of uni-directional bridges (AHB2AHB) can be instantiated to form a bi-directional bridge. The bi-directional AHB/AHB bridge (AHBBRIDGE) instantiates two uni-directional bridges that are configured to suit the bus architecture shown in figure 9. The bus architecture consists of two AHB buses: a high-speed AHB bus hosting LEON3 CPU(s) and an external memory controller and a low-speed AHB bus hosting communication IP-cores. Note: For other architectures, a more general bi-directional bridge that is more suitable can be created by instantiating two uni-directional AHB to AHB bridges (see AHB2AHB core). AHBBRIDGE is not suitable for LEON4 systems and for other systems with wide AHB buses. LEON3 SDRAM SDRAM Controller Async Mem Controller SRAM DSU3 AHB CTRL High-speed bus AHB/AHB Bridge PROM LEON3 Serial Dbg Link JTAG Dbg Link AHB CTRL Low-speed bus AHB/APB Bridge PCI Ethernet MAC I/O UARTS Timers IrqCtrl Figure 9. LEON3 system with a bi-directional AHB/AHB bridge 5.2 Operation 5.2.1 General The AHB/AHB bridge is connected to each AHB bus through a pair consisting of an AHB master and an AHB slave interface. The address space occupied by the AHB/AHB bridge on each bus is determined by Bank Address Registers which are configured through VHDL generics. The bridge is capable of handling single and burst transfers in both directions. Internal FIFOs are used for data buffering. The bridge implements the AMBA SPLIT response to improve AHB bus utilization. For more information on AHB transfers please refer to the documentation for the uni-directional AHB/ AHB bridge (AHB2AHB). The requirements on the two bus clocks are that they are synchronous. The two uni-directional bridges forming the bi-directional AHB/AHB bridge are configured asymmetrically. Configuration of the bridge connecting high-speed bus with the low-speed bus (down bus) is optimized for the bus traffic generated by the LEON3 CPU since the CPU is the only master on the high-speed bus (except for the bridge itself). Read transfers generated by the CPU are single read transfers generated by single load instructions (LD), read bursts of length two generated by double load instructions (LDD) or incremental read bursts of maximal length equal to cache line size (4 or 8 words) generated during instruction cache line fill. The size of the read FIFO for the down bridge is therefore configurable to 4 or 8 entries which is the maximal read burst length. If a read burst is an instruction fetch (indicated on AHB HPROT signal) to a prefetchable area the bridge will prefetch data to the end of a instruction GRIP, Apr 2018, Version 2018.1 53 www.cobham.com/gaisler GRLIB IP Core cache line. If a read burst to a prefetchable area is a data access, two words will be prefetched (this transfer is generated by the LDD instruction). The write FIFO has two entries capable of buffering the longest write burst (generated by the STD instruction). The down bridge also performs interrupt forwarding, interrupt lines 1-15 on both buses are monitored and an interrupt on one bus is forwarded to the other one. Since the low-speed bus does not host a LEON3 CPU, all AHB transfers forwarded by the uni-directional bridge connecting the low-speed bus and the high-speed bus (up bridge) are data transfers. Therefore the bridge does not make a distinction between instruction and data transfers. The size of the read and write FIFOs for this bridge is configurable and should be set by the user to suite burst transfers generated by the cores on the low-speed bus. Note that the bridge has been optimized for a LEON3 system with a specific set of masters and a specific bus topology. Therefore the core may not be suitable for a design containing later versions of the LEON processor or other masters. In general it is not recommended instantiate the AHBBRIDGE core and instead instantiate two uni-directional AHB to AHB bridges (AHB2AHB cores) with configurations tailored for a specific design. 5.2.2 Deadlock conditions A deadlock situation can occur if the bridge is simultaneously accessed from both buses. The bridge contains deadlock detection logic which will resolve a deadlock condition by giving a RETRY response on the low-speed bus. There are several deadlock conditions that can occur with locked accesses. If the VHDL generic lckdac is 0, the bridge will deadlock if two simultaneous accesses from both buses are locked, or if a locked access is made while the bridge has issued a SPLIT response to a read access and the splitted access has not completed. If lckdac is greater than 0, the bridge will resolve the deadlock condition from two simultaneous locked accesses by giving an ERROR response on the low-speed bus. If lckdac is 1 and a locked access is made while the bridge has issued a SPLIT response to a read access, the bridge will respond with ERROR to the incoming locked access. If lckdac is 2 the bridge will allow both the locked access and the splitted read access to complete. Note that with lckdac set to 2 and two incoming locked accesses, the access on the low-speed bus will still receive an ERROR response. 5.2.3 Read and write combining The bridge can be configured to support read and write combining so that prefetch operations and write bursts are always performed with the maximum access size possible on the master interface. Please see the documentation for the uni-directional AHB/AHB bridge (AHB2AHB) for a description of read and write combining and note that the same VHDL generics are used to specify both the maximum master and maximum slave access size on the bi-directional AHB/AHB bridge. 5.2.4 Endianness The core is designed for big-endian systems 5.3 Registers The core does not implement any registers. 5.4 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x020. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. GRIP, Apr 2018, Version 2018.1 54 www.cobham.com/gaisler GRLIB IP Core 5.5 Implementation See documentation for AHB2AHB. 5.6 Configuration options Table 42 shows the configuration options of the core (VHDL generics). Table 42. Configuration options Generic Function Allowed range Default memtech Memory technology - 0 ffact Frequency ratio 1- 2 hsb_hsindex AHB slave index on the high-speed bus 0 to NAHBMAX-1 0 hsb_hmindex AHB master index on the high-speed bus 0 to NAHBMAX-1 0 hsb_iclsize Cache line size (in number of 32-bit words) for CPUs on the high-speed bus. Determines the number of the words that are prefetched by the bridge when CPU performs instruction bursts. 4, 8 8 hsb_bank0 Address area 0 mapped on the high-speed bus and decoded by the bridge’s slave interface on the low-speed bus. Appears as memory address register (BAR0) on the bridge’s low-speed bus slave interface. The generic has the same bit layout as bank address registers with bits [19:18] suppressed (use functions ahb2ahb_membar and ahb2ahb_iobar in gaisler.misc package to generate this generic). 0 - 1073741823 0 hsb_bank1 Address area 1 mapped on the high-speed bus 0 - 1073741823 0 hsb_bank2 Address area 2 mapped on the high-speed bus 0 - 1073741823 0 hsb_bank3 Address area 3 mapped on the high-speed bus 0 - 1073741823 0 hsb_ioarea Address of high-speed bus I/O area that contains the high-speed bus configuration area. Will appear in the bridge’s user-defined register 1 on the low-speed bus. Note that to allow low-speed bus masters to read the high-speed bus configuration area, the area must be mapped on one of the hsb_bank generics. 0 - 16#FFF# 0 lsb_hsindex AHB slave index on the low-speed bus 0 to NAHBMAX-1 0 lsb_hmindex AHB master index on the low-speed bus 0 to NAHBMAX-1 0 lsb_rburst Size of the prefetch buffer for read transfers initiated on the low-speed-bus and crossing the bridge. 16, 32 16 lsb_wburst Size of the write buffer for write transfers initiated on the low-speed bus and crossing the bridge. 16, 32 16 lsb_bank0 Address area 0 mapped on the low-speed bus and decoded by the bridge’s slave interface on the high-speed bus. Appears as memory address register (BAR0) on the bridge’s high-speed bus slave interface. The generic has the same bit layout as bank address registers with bits [19:18] suppressed (use functions ahb2ahb_membar and ahb2ahb_iobar in gaisler.misc package to generate this generic). 0 - 1073741823 0 lsb_bank1 Address area 1 mapped on the low-speed bus 0 - 1073741823 0 lsb_bank2 Address area 2 mapped on the low-speed bus 0 - 1073741823 0 lsb_bank3 Address area 3 mapped on the low-speed bus 0 - 1073741823 0 GRIP, Apr 2018, Version 2018.1 55 www.cobham.com/gaisler GRLIB IP Core Table 42. Configuration options Generic Function lsb_ioarea Address of low-speed bus I/O area that contains the low- 0 - 16#FFF# speed bus configuration area. Will appear in the bridge’s user-defined register 1 on the high-speed bus. Note that to allow high-speed bus masters to read the low-speed bus configuration area, the area must be mapped on one of the lsb_bank generics. 0 lckdac Locked access error detection and correction. This generic is mapped to the generic with the same name on the two AHB2AHB cores instantiated by AHBBRIDGE. Please see the documentation for the AHB2AHB core’s VHDL generics for more information. 0-2 0 maccsz This generic is propagated to the slvmaccsz and mstmaccsz VHDL generics on the two AHB2AHB cores instantiated by AHBBRIDGE. The generic determines the maximum AHB access size supported by the bridge. Please see the documentation for the AHB2AHB core’s VHDL generics for more information. 32 - 256 32 rdcomb 0-2 Read combining, this generic is mapped to the generic with the same name on the two AHB2AHB cores instantiated by AHBBRIDGE. Please see the documentation for the AHB2AHB core’s VHDL generics for more information. 0 wrcomb Write combining, this generic is mapped to the generic 0-2 with the same name on the two AHB2AHB cores instantiated by AHBBRIDGE. Please see the documentation for the AHB2AHB core’s VHDL generics for more information. 0 combmask Read/Write combining mask, this generic is mapped to 0 - 16#FFFF# the generic with the same name on the two AHB2AHB cores instantiated by AHBBRIDGE. Please see the documentation for the AHB2AHB core’s VHDL generics for more information. 16#FFFF# allbrst Support all burst types, this generic is mapped to the generic with the same name on the two AHB2AHB cores instantiated by AHBBRIDGE. Please see the documentation for the AHB2AHB core’s VHDL generics for more information. 0-2 0 fcfs First-come, first-served operation, this generic is mapped to the generic with the same name on the two AHB2AHB cores instantiated by AHBBRIDGE. Please see the documentation for the AHB2AHB core’s VHDL generics for more information. 0 - NAHBMST 0 scantest Enable scan support 0-1 0 GRIP, Apr 2018, Version 2018.1 Allowed range 56 Default www.cobham.com/gaisler GRLIB IP Core 5.7 Signal descriptions Table 43 shows the interface signals of the core (VHDL ports). Table 43. Signal descriptions 5.8 Signal name Type Function Active RST Input Reset Low HSB_HCLK Input High-speed AHB clock - LSB_HCLK Input Low-speed AHB clock - HSB_AHBSI Input High-speed bus AHB slave input signals - HSB_AHBSO Output High-speed bus AHB slave output signals - HSB_AHBSOV Input High-speed bus AHB slave input signals - HSB_AHBMI Input High-speed bus AHB master input signals - HSB_AHBMO Output High-speed bus AHB master output signals - LSB_AHBSI Input Low-speed bus AHB slave input signals - LSB_AHBSO Output Low-speed bus AHB slave output signals - LSB_AHBSOV Input Low-speed bus AHB slave input signals - LSB_AHBMI Input Low-speed bus AHB master input signals - LSB_AHBMO Output Low-speed bus AHB master output signals - Library dependencies Table 44 shows the libraries used when instantiating the core (VHDL libraries). Table 44. Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Component Component declaration GRIP, Apr 2018, Version 2018.1 57 www.cobham.com/gaisler GRLIB IP Core 6 AHBCTRL - AMBA AHB controller with plug&play support 6.1 Overview The AMBA AHB controller is a combined AHB arbiter, bus multiplexer and slave decoder according to the AMBA 2.0 standard. The controller supports up to 16 AHB masters, and 16 AHB slaves. The maximum number of masters and slaves are defined in the GRLIB.AMBA package, in the VHDL constants NAHBSLV and NAHBMST. It can also be set with the nahbm and nahbs VHDL generics. MASTER MASTER AHBCTRL ARBITER/ DECODER SLAVE SLAVE Figure 10. AHB controller block diagram 6.2 Operation 6.2.1 Arbitration The AHB controller supports two arbitration algorithms: fixed-priority and round-robin. The selection is done by the VHDL generic rrobin. In fixed-priority mode (rrobin = 0), the bus request priority is equal to the master’s bus index, with index 0 being the lowest priority. If no master requests the bus, the master with bus index 0 (set by the VHDL generic defmast) will be granted. In round-robin mode, priority is rotated one step after each AHB transfer. If no master requests the bus, the last owner will be granted (bus parking). The VHDL generic mprio can be used to specify one or more masters that should be prioritized when the core is configured for round-robin mode. Note that there are AHB slaves that implement split-like functionality by giving AHB retry responses until the access has finished and the original master tries again. All masters on the bus accessing such slaves must be round-robin arbitrated without prioritization to avoid deadlock situations. For GRLIB this applies to the GRPCI and GRPCI2 cores. During incremental bursts, the AHB master should keep the bus request asserted until the last access as recommended in the AMBA 2.0 specification, or it might loose bus ownership. For fixed-length burst, the AHB master will be granted the bus during the full burst, and can release the bus request immediately after the first access has started. For this to work however, the VHDL generic fixbrst should be set to 1. 6.2.2 Decoding Decoding (generation of HSEL) of AHB slaves is done using the plug&play method explained in the GRLIB User’s Manual. A slave can occupy any binary aligned address space with a size of 1 - 4096 Mbyte. A specific I/O area is also decoded, where slaves can occupy 256 byte - 1 Mbyte. The default address of the I/O area is 0xFFF00000, but can be changed with the ioaddr and iomask VHDL generics. Access to unused addresses will cause an AHB error response. GRIP, Apr 2018, Version 2018.1 58 www.cobham.com/gaisler GRLIB IP Core The I/O area can be placed within a memory area occupied by a slave. The slave will not be selected when the I/O area is accessed. 6.2.3 Plug&play information GRLIB devices contain a number of plug&play information words which are included in the AHB records they drive on the bus (see the GRLIB user’s manual for more information). These records are combined into an array which is connected to the AHB controller unit. The plug&play information is mapped on a read-only address area, defined by the cfgaddr and cfgmask VHDL generics, in combination with the ioaddr and iomask VHDL generics. By default, the area is mapped on address 0xFFFFF000 - 0xFFFFFFFF. The master information is placed on the first 2 kbyte of the block (0xFFFFF000 - 0xFFFFF800), while the slave information is placed on the second 2 kbyte block. Each unit occupies 32 bytes, which means that the area has place for 64 masters and 64 slaves. The address of the plug&play information for a certain unit is defined by its bus index. The address for masters is thus 0xFFFFF000 + n*32, and 0xFFFFF800 + n*32 for slaves. 31 Identification Register 00 24 23 VENDOR ID 12 11 10 9 DEVICE ID 04 USER-DEFINED 08 USER-DEFINED 0C USER-DEFINED IRQ 5 4 VERSION 0 IRQ BAR0 10 HADDR ADDR 00 P C MASK MASK TYPE BAR1 14 ADDR 00 P C MASK TYPE BAR2 18 ADDR 00 P C MASK TYPE BAR3 1C ADDR 00 P C MASK TYPE Bank Address Registers 31 20 19 18 17 16 15 P = Prefetchable C = Cacheable 4 3 0 TYPE 0001 = APB I/O space 0010 = AHB Memory space 0011 = AHB I/O space Figure 11. AHB plug&play information record 6.3 AHB split support AHB SPLIT functionality is supported if the split VHDL generic is set to 1. In this case, all slaves must drive the AHB SPLIT signal. It is important to implement the split functionality in slaves carefully since locked splits can otherwise easily lead to deadlocks. A locked access to a slave which is currently processing (it has returned a split response but not yet split complete) an access which it returned split for to another master must be handled first. This means that the slave must either be able to return an OKAY response to the locked access immediately or it has to split it but return split complete to the master performing the locked transfer before it has finished the first access which received split. 6.4 Locked accesses The GRLIB AHB controller treats HLOCK as coupled to a specific access. If a previous access by a master received a SPLIT/RETRY response then the arbiter will disregard the current value of HLOCK. This is done as opposed to always treating HLOCK as being valid for the next access which can result in a previously non-locked access being treated as locked when it is retried. Consider the following sequence: GRIP, Apr 2018, Version 2018.1 59 www.cobham.com/gaisler GRLIB IP Core T0: MSTx write 0 T1: MSTx write 1, HLOCK asserted as next access performed by master will be locked T2: MSTx locked read If (the non-locked) write 0 access at T0 receives a RETRY or SPLIT response (given at time T1), then the next access to be performed may be a retry of write 0. In this case the arbiter will disregard the HLOCK setting and the retried access will not have HMASTLOCK set. 6.5 AHB bus monitor An AHB bus monitor is integrated into the core. It is enabled with the enbusmon generic. It has the same functionality as the AHB and arbiter parts in the AMBA monitor core (AMBAMON). For more information on which rules are checked se the AMBAMON documentation. 6.6 Registers The core does not implement any registers. 6.7 Implementation 6.7.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core will use asynchronous reset for all registers if the GRLIB config package setting grlib_async_reset_enable is set. 6.8 Configuration options Table 45 shows the configuration options of the core (VHDL generics). Table 45. Configuration options Generic Function Allowed range Default ioaddr The MSB address of the I/O area. Sets the 12 most significant bits in the 32-bit AHB address (i.e. 31 downto 20) 0 - 16#FFF# 16#FFF# iomask The I/O area address mask. Sets the size of the I/O area and the start address together with ioaddr. 0 - 16#FFF# 16#FFF# cfgaddr The MSB address of the configuration area. Sets 12 bits in the 32-bit AHB address (i.e. 19 downto 8). 0 - 16#FFF# 16#FF0# cfgmask The address mask of the configuration area. Sets the size of the configuration area and the start address together with cfgaddr. If set to 0, the configuration will be disabled. 0 - 16#FFF# 16#FF0# rrobin Selects between round-robin (1) or fixed-priority (0) bus arbitration algorithm. 0-1 0 split Enable support for AHB SPLIT response 0-1 0 defmast Default AHB master 0 - NAHBMST-1 0 ioen AHB I/O area enable. Set to 0 to disable the I/O area 0-1 1 disirq Set to 1 to disable interrupt routing 0-1 0 nahbm Number of AHB masters 1 - NAHBMST NAHBMST nahbs Number of AHB slaves 1 - NAHBSLV NAHBSLV GRIP, Apr 2018, Version 2018.1 60 www.cobham.com/gaisler GRLIB IP Core Table 45. Configuration options Generic Function Allowed range Default timeout fixbrst Perform bus timeout checks (NOT IMPLEMENTED). 0-1 0 Enable support for fixed-length bursts 0-1 0 debug Print configuration (0=none, 1=short, 2=all cores) 0-2 2 fpnpen Enables full decoding of the PnP configuration records. 0 - 1 When disabled the user-defined registers in the PnP configuration records are not mapped in the configuration area. 0 icheck Check bus index 0-1 1 devid Assign unique device identifier readable from plug and play area. N/A 0 enbusmon Enable AHB bus monitor 0-1 0 assertwarn Enable assertions for AMBA recommendations. Violations are asserted with severity warning. 0-1 0 asserterr Enable assertions for AMBA requirements. Violations are asserted with severity error. 0-1 0 hmstdisable Disable AHB master rule check. To disable a master rule check a value is assigned so that the binary representation contains a one at the position corresponding to the rule number, e.g 0x80 disables rule 7. N/A 0 hslvdisable Disable AHB slave tests. Values are assigned as for hmstdisable. N/A 0 arbdisable Disable Arbiter tests. Values are assigned as for hmstdis- N/A able. 0 mprio Master(s) with highest priority. This value is converted to a vector where each position corresponds to a master. To prioritize masters x and y set this generic to 2x + 2y. N/A 0 mcheck Check if there are any intersections between core mem- 0 - 2 ory areas. If two areas intersect an assert with level failure will be triggered (in simulation). mcheck = 1 does not report intersects between AHB IO areas and AHB memory areas (as IO areas are allowed to override memory areas). mcheck = 2 triggers on all overlaps. 1 See also documentation of VHDL generic shadow below. ccheck Perform sanity checks on PnP configuration records (in simulation). 0-1 1 acdm AMBA compliant data multiplexing (for HSIZE > word). If this generic is set to 1, and the AMBA bus data width in the system exceeds 32-bits, the core will ensure AMBA compliant data multiplexing for access sizes (HSIZE) over 32-bits. GRLIB cores have an optimization where they drive the same data on all lanes. Read data is always taken from the lowest lanes. If an AMBA compliant core from another vendor is introduced in the design, that core may not always place valid data on the low part of the bus. By setting this generic to 1, the AHBCTRL core will replicate the data, allowing the non-GRLIB cores to be instantiated without modification. 0-1 0 index AHB index for trace print-out, currently unused N/A 0 ahbtrace AHB trace print-out to simulator console in simulation. 0-1 0 GRIP, Apr 2018, Version 2018.1 61 www.cobham.com/gaisler GRLIB IP Core Table 45. Configuration options Generic Function Allowed range Default hwdebug Enable hardware debug registers. If this generic is set to 1 the configuration area will include to diagnostic registers at offsets 0xFF4 and 0xFF8. 0-1 0 Offset 0xFF4 will show a 32-bit register where bit n shows the current status of AHB master n’s HBUSREQ signal. Offset 0xFF8 will show a 32-bit register where bit n shows the current SPLIT status of AHB master n. The bit will be set when AHB master n receives a SPLIT reply and will be re-set to ‘0’ when HSPLIT for AHB master n has been asserted. This functionality is not intended to be used in production systems but can provide valuable information while debugging systems with cores that have problems with AMBA SPLIT replies. fourgslave Allow and optimize for case with one single slave that has one 4 GiB bar 0-1 0 shadow Allow memory areas to shadow other memory areas. If this generic is set to 0 and two slaves map the same memory area then HSEL/HMBSEL signals will be asserted for both memory bars / slaves. 0-1 0 This may lead to system malfunctions and causes a simulation failure if the mcheck VHDL generic is set to a non-zero value. If the shadow generic is set to 1 then memory area intersects are allowed and only the lowest HSEL and HMBSEL (HSEL has priority) will be asserted - only the slave or bar with the lowest index will be selected instead of both slaves / bars. The mcheck simulation failure will instead be asserted as a note about intersecting memory areas. Also note that intersections of cacheable and noncacheable areas will be treated as cacheable by GRLB cores that decode the plug&play information. If a non-cacheable area is placed in a cacheable area then it is recommended to use fixed cacheability. unmapslv 6.9 If this generic is non-zero then accesses to unmapped address space (address space not occupied by any slave) will be redirected to the slave and bar selected via: 256+bar*32+slv. 0 Signal descriptions Table 46 shows the interface signals of the core (VHDL ports). Table 46. Signal descriptions Signal name Field Type Function Active RST N/A Input AHB reset Low CLK N/A Input AHB clock - MSTI * Output AMBA AHB master interface record array - MSTO * Input AMBA AHB master interface record array - SLVI * Output AMBA AHB slave interface record array - SLVO * Input AMBA AHB slave interface record array - * see GRLIB IP Library User’s Manual GRIP, Apr 2018, Version 2018.1 62 www.cobham.com/gaisler GRLIB IP Core 6.10 Library dependencies Table 47 shows libraries used when instantiating the core (VHDL libraries). Table 47. Library dependencies 6.11 Library Package Imported unit(s) Description GRLIB AMBA Types AMBA signal type definitions Component declaration library grlib; use grlib.amba.all; component ahbctrl generic ( defmast : integer := 0;-- default master split : integer := 0;-- split support rrobin : integer := 0;-- round-robin arbitration timeout : integer range 0 to 255 := 0; -- HREADY timeout ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address iomask : ahb_addr_type := 16#fff#; -- I/O area address mask cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address cfgmask : ahb_addr_type := 16#ff0#; -- config area address maskk nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves ioen : integer range 0 to 15 := 1; -- enable I/O area disirq : integer range 0 to 1 := 0; -- disable interrupt routing fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts debug : integer range 0 to 2 := 2; -- print configuration to consolee fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding icheck : integer range 0 to 1 := 1 devid : integer := 0; -- unique device ID enbusmon : integer range 0 to 1 := 0; --enable bus monitor assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings asserterr : integer range 0 to 1 := 0; --enable assertions for errors hmstdisable : integer := 0; --disable master checks hslvdisable : integer := 0; --disable slave checks arbdisable : integer := 0; --disable arbiter checks mprio : integer := 0; --master with highest priority enebterm : integer range 0 to 1 := 0 --enable early burst termination ); port ( rst : in std_ulogic; clk : in std_ulogic; msti : out ahb_mst_in_type; msto : in ahb_mst_out_vector; slvi : out ahb_slv_in_type; slvo : in ahb_slv_out_vector; testen : in std_ulogic := ’0’; testrst : in std_ulogic := ’1’; scanen : in std_ulogic := ’0’; testoen : in std_ulogic := ’1’ ); end component; 6.12 Instantiation This example shows the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; GRIP, Apr 2018, Version 2018.1 63 www.cobham.com/gaisler GRLIB IP Core . . -- AMBA signals signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); begin -- ARBITER ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, nahbm => 8, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); -- AHB slave sr0 : srctrl generic map (hindex => 3) port map (rstn, clkm, ahbsi, ahbso(3), memi, memo, sdo3); -- AHB master e1 : eth_oc generic map (mstndx => 2, slvndx => 5, ioaddr => CFG_ETHIO, irq => 12, memtech => memtech) port map (rstn, clkm, ahbsi, ahbso(5), ahbmi => ahbmi, ahbmo => ahbmo(2), ethi1, etho1); ... end; 6.13 Debug print-out If the debug generic is set to 2, the plug&play information of all attached AHB units are printed to the console during the start of simulation. Reporting starts by scanning the master interface array from 0 to NAHBMST - 1 (defined in the grlib.amba package). It checks each entry in the array for a valid vendor-id (all nonzero ids are considered valid) and if one is found, it also retrieves the device-id. The descriptions for these ids are obtained from the GRLIB.DEVICES package, and are then printed on standard out together with the master number. If the index check is enabled (done with a VHDL generic), the report module also checks if the hindex number returned in the record matches the array number of the record currently checked (the array index). If they do not match, the simulation is aborted and an error message is printed. This procedure is repeated for slave interfaces found in the slave interface array. It is scanned from 0 to NAHBSLV - 1 and the same information is printed and the same checks are done as for the master interfaces. In addition, the address range and memory type is checked and printed. The address information includes type, address, mask, cacheable and pre-fetchable fields. From this information, the report module calculates the start address of the device and the size of the range. The information finally printed is type, start address, size, cacheability and pre-fetchability. The address ranges currently defined are AHB memory, AHB I/O and APB I/O. APB I/O ranges are ignored by this module. # vsim -c -quiet leon3mp VSIM 1> run # LEON3 MP Demonstration design # GRLIB Version 1.0.7 # Target technology: inferred, memory library: inferred # ahbctrl: AHB arbiter/multiplexer rev 1 # ahbctrl: Common I/O area disabled # ahbctrl: Configuration area at 0xfffff000, 4 kbyte # ahbctrl: mst0: Cobham Gaisler Leon3 SPARC V8 Processor # ahbctrl: mst1: Cobham Gaisler AHB Debug UART # ahbctrl: slv0: European Space Agency Leon2 Memory Controller GRIP, Apr 2018, Version 2018.1 64 www.cobham.com/gaisler GRLIB IP Core # # # # # # # # # # # # # # # # # # # # # # # # # ahbctrl: memory at 0x00000000, size 512 Mbyte, cacheable, prefetch ahbctrl: memory at 0x20000000, size 512 Mbyte ahbctrl: memory at 0x40000000, size 1024 Mbyte, cacheable, prefetch ahbctrl: slv1: Cobham Gaisler AHB/APB Bridge ahbctrl: memory at 0x80000000, size 1 Mbyte apbctrl: APB Bridge at 0x80000000 rev 1 apbctrl: slv0: European Space Agency Leon2 Memory Controller apbctrl: I/O ports at 0x80000000, size 256 byte apbctrl: slv1: Cobham Gaisler Generic UART apbctrl: I/O ports at 0x80000100, size 256 byte apbctrl: slv2: Cobham Gaisler Multi-processor Interrupt Ctrl. apbctrl: I/O ports at 0x80000200, size 256 byte apbctrl: slv3: Cobham Gaisler Modular Timer Unit apbctrl: I/O ports at 0x80000300, size 256 byte apbctrl: slv7: Cobham Gaisler AHB Debug UART apbctrl: I/O ports at 0x80000700, size 256 byte apbctrl: slv11: Cobham Gaisler General Purpose I/O port apbctrl: I/O ports at 0x80000b00, size 256 byte grgpio11: 8-bit GPIO Unit rev 0 gptimer3: GR Timer Unit rev 0, 8-bit scaler, 2 32-bit timers, irq 8 irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1 apbuart1: Generic UART rev 1, fifo 4, irq 2 ahbuart7: AHB Debug UART rev 0 leon3_0: LEON3 SPARC V8 processor rev 0 leon3_0: icache 1*8 kbyte, dcache 1*8 kbyte VSIM 2> GRIP, Apr 2018, Version 2018.1 65 www.cobham.com/gaisler GRLIB IP Core 7 AHBJTAG - JTAG Debug Link with AHB Master Interface 7.1 Overview The JTAG debug interface provides access to on-chip AMBA AHB bus through JTAG. The JTAG debug interface implements a simple protocol which translates JTAG instructions to AHB transfers. Through this link, a read or write transfer can be generated to any address on the AHB bus. TDI TCK TMS JTAG TAP Controller JTAG Communication Interface TDO AHB master interface AMBA AHB Figure 12. JTAG Debug link block diagram 7.2 Operation 7.2.1 Transmission protocol The JTAG Debug link decodes two JTAG instructions and implements two JTAG data registers: the command/address register and data register. A read access is initiated by shifting in a command consisting of read/write bit, AHB access size and AHB address into the command/address register. The AHB read access is performed and data is ready to be shifted out of the data register. Write access is performed by shifting in command, AHB size and AHB address into the command/data register followed by shifting in write data into the data register. Sequential transfers can be performed by shifting in command and address for the transfer start address and shifting in SEQ bit in data register for following accesses. The SEQ bit will increment the AHB address for the subsequent access. Sequential transfers should not cross a 1 kB boundary. Sequential transfers are always word based. Table 48. JTAG debug link Command/Address register 34 33 32 31 W 0 SIZE AHB ADDRESS 34 Write (W) - ‘0’ - read transfer, ‘1’ - write transfer 33 32 AHB transfer size - “00” - byte, “01” - half-word, “10” - word, “11”- reserved 31 30 AHB address Table 49. JTAG debug link Data register 32 31 0 SEQ AHB DATA 32 Sequential transfer (SEQ) - If ‘1’ is shifted in this bit position when read data is shifted out or write data shifted in, the subsequent transfer will be to next word address. When read out from the device, this bit is ‘1’ if the AHB access has completed and ‘0’ otherwise. 31 30 AHB Data - AHB write/read data. For byte and half-word transfers data is aligned according to bigendian order where data with address offset 0 data is placed in MSB bits. GRIP, Apr 2018, Version 2018.1 66 www.cobham.com/gaisler GRLIB IP Core As of version 1 of the JTAG debug link the core will signal AHB access completion by setting bit 32 of the data register. In previous versions the debug host could not determine if an AHB accesses had finished when the read data was shifted out of the JTAG debug link data register. As of version 1 a debug host can look at bit 32 of the received data to determine if the access was successful. If bit 32 is ‘1’ the access completed and the data is valid. If bit 32 is ‘0’, the AHB access was not finished when the host started to read data. In this case the host can repeat the read of the data register until bit 32 is set to ‘1’, signaling that the data is valid and that the AMBA AHB access has completed. It should be noted that while bit 32 returns ‘0’, new data will not be shifted into the data register. The debug host should therefore inspect bit 32 when shifting in data for a sequential AHB access to see if the previous command has completed. If bit 32 is ‘0’, the read data is not valid and the command just shifted in has been dropped by the core. Inspection of bit 32 should not be done for JTAG Debug links with version number 0. 7.2.2 Endianness The core is designed for big-endian systems. 7.3 Implementation 7.3.1 Clocking Except for the TAP state machine and instruction register, the JTAG debug link operates in the AMBA clock domain. To detect when to shift the address/data register, the JTAG clock and TDI are resynchronized to the AMBA domain. The JTAG clock must be less than 1/3 of the AHB clock frequency for the debug link commands to work when nsync=2, and less than 1/2 of the AHB frequency when nsync=1. 7.3.2 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). Registers in the JTAG clock domain have asynchronous reset connected to the JTAG trst. Registers in the system clock domain have synchronous reset. 7.4 Registers The core does not implement any registers mapped in the AMBA AHB or APB address space. 7.5 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x01C. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 7.6 Implementation 7.6.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers, except synchronization registers, if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support the GRLIB config package setting grlib_async_reset_enable. GRIP, Apr 2018, Version 2018.1 67 www.cobham.com/gaisler GRLIB IP Core 7.7 Configuration options Table 50 shows the configuration options of the core (VHDL generics). Table 50. Configuration options Generic Function Allowed range Default tech Target technology 0 - NTECH 0 hindex AHB master index 0 - NAHBMST-1 0 nsync Number of synchronization registers between clock regions 1-2 1 idcode JTAG IDCODE instruction code (generic tech only) 0 - 255 9 manf Manufacturer id. Appears as bits 11-1 in TAP controllers 0 - 2047 device identification register. Used only for generic technology. Default is Cobham Gaisler manufacturer id. 804 part Part number (generic tech only). Bits 27-12 in device id. reg. 0 - 65535 0 ver Version number (generic tech only). Bits 31-28 in device id. reg. 0 - 15 0 ainst Code of the JTAG instruction used to access JTAG Debug link command/address register.  For Actel TAPs (tech VHDL generic is set to an Actel technology) this generic should be set to 16, for all other technologies the default value (2) can be used. 0 - 255 2 dinst Code of the JTAG instruction used to access JTAG Debug link data register For Actel TAPs (tech VHDL generic is set to an Actel technology) this generic should be set to 17, for all other technologies the default value (3) can be used. 0 - 255 3 scantest Enable scan test support 0-1 0 oepol Output enable polarity for TDOEN 0-1 1 tcknen Support externally inverted TCK (generic tech only) 0-1 0 GRIP, Apr 2018, Version 2018.1 68 www.cobham.com/gaisler GRLIB IP Core 7.8 Signal descriptions Table 51 shows the interface signals of the core (VHDL ports). Table 51. Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input System clock (AHB clock domain) - TCK N/A Input JTAG clock* - TMS N/A Input JTAG TMS signal* High TDI N/A Input JTAG TDI signal* High TDO N/A Output JTAG TDO signal* High AHBI *** Input AHB Master interface input - AHBO *** Output AHB Master interface output - TAPO_TCK N/A Output TAP Controller User interface TCK signal** High TAPO_TDI N/A Output TAP Controller User interface TDI signal** High TAPO_INST[7:0] N/A Output TAP Controller User interface INSTsignal** High TAPO_RST N/A Output TAP Controller User interface RST signal** High TAPO_CAPT N/A Output TAP Controller User interface CAPT signal** High TAPO_SHFT N/A Output TAP Controller User interface SHFT signal** High TAPO_UPD N/A Output TAP Controller User interface UPD signal** High TAPI_TDO N/A Input TAP Controller User interface TDO signal** High TRST N/A Input JTAG TRST signal Low TDOEN N/A Output Output-enable for TDO See oepol TCKN N/A Input Inverted JTAG clock* (if tcknen is set) - TAPO_TCKN N/A Output TAP Controller User interface TCKN signal** High TAPO_NINST N/A Output TAP Controller User interface NINSTsignal** High TAPO_IUPD N/A Output TAP Controller User interface IUPD signal** High *) If the target technology is Xilinx or Altera the cores JTAG signals TCK, TCKN, TMS, TDI and TDO are not used. Instead the dedicated FPGA JTAG pins are used. These pins are implicitly made visible to the core through TAP controller instantiation. **) User interface signals from the JTAG TAP controller. These signals are used to interface additional user defined JTAG data registers such as boundary-scan register. For more information on the JTAG TAP controller user interface see JTAG TAP Controller IP-core documentation. If not used tie TAPI_TDO to ground and leave TAPO_* outputs unconnected. ***) see GRLIB IP Library User’s Manual 7.9 Signal definitions and reset values The signals and their reset values are described in table 52. Table 52. Signal definitions and reset values Signal name Type Function Active Reset value dsutck Input JTAG clock - - dsutms Input JTAG TMS High - dsutdi Input JTAG TDI High - dsutdo Output JTAG TDO High undefined GRIP, Apr 2018, Version 2018.1 69 www.cobham.com/gaisler GRLIB IP Core 7.10 Timing The timing waveforms and timing parameters are shown in figure 13 and are defined in table 53. tAHBJTAG0 tAHBJTAG1 dsutck tAHBJTAG2 dsutdi, dsutms tAHBJTAG4 tAHBJTAG3 dsutdo Figure 13. Timing waveforms Table 53. Timing parameters 7.11 Name Parameter Reference edge Min Max Unit tAHBJTAG0 clock period - TBD - ns tAHBJTAG1 clock low/high period - TBD - ns tAHBJTAG2 data input to clock setup rising dsutck edge TBD - ns tAHBJTAG3 data input from clock hold rising dsutck edge TBD - ns tAHBJTAG4 clock to data output delay falling dsutck edge - TBD ns Library dependencies Table 54 shows libraries used when instantiating the core (VHDL libraries). Table 54. Library dependencies 7.12 Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER JTAG Signals, component Signals and component declaration Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.jtag.all; entity ahbjtag_ex is port ( clk : in std_ulogic; rstn : in std_ulogic; -- JTAG signals tck : in std_ulogic; tms : in std_ulogic; tdi : in std_ulogic; tdo : out std_ulogic ); end; architecture rtl of ahbjtag_ex is GRIP, Apr 2018, Version 2018.1 70 www.cobham.com/gaisler GRLIB IP Core -- AMBA signals signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal gnd : std_ulogic; constant clkperiod : integer := 100; begin gnd <= ‘0’; -- AMBA Components are instantiated here ... -- AHB JTAG ahbjtag0 : ahbjtag generic map(tech => 0, hindex => 1) port map(rstn, clkm, tck, tckn, tms, tdi, tdo, ahbmi, ahbmo(1), open, open, open, open, open, open, open, gnd); jtagproc : process begin wait; jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true); wait; end process; end; 7.13 Simulation DSU communication over the JTAG debug link can be simulated using jtagcom procedure. The jtagcom procedure sends JTAG commands to the AHBJTAG on JTAG signals TCK, TMS, TDI and TDO. The commands read out and report the device identification code, optionally put the CPU(s) in debug mode, perform three write operations to the memory and read out the data from the memory. The JTAG test works if the generic JTAG tap controller is used and will not work with built-in TAP macros (such as Altera and Xilinx JTAG macros) since these macros don’t have visible JTAG pins. The jtagcom procedure is part of jtagtst package in gaisler library and has following declaration: procedure jtagcom(signal tdo : in std_ulogic; signal tck, tms, tdi : out std_ulogic; cp, start, addr : in integer; -- cp - TCK clock period in ns -- start - time in us when JTAG test is started -- addr - read/write operation destination address haltcpu : in boolean); GRIP, Apr 2018, Version 2018.1 71 www.cobham.com/gaisler GRLIB IP Core 8 AHBRAM - Single-port RAM with AHB interface 8.1 Overview AHBRAM implements on-chip RAM with an AHB slave interface. Memory size is configurable in binary steps through a VHDL generic. Minimum size is 1KiB and maximum size is dependent on target technology and physical resources. Read accesses have zero or one waitstate (configured at implementation time), write access have one waitstate. The RAM supports byte- and half-word accesses, as well as all types of AHB burst accesses. Internally, the AHBRAM instantiates a SYNCRAM block with byte writes. Depending on the target technology map, this will translate into memory with byte enables or to multiple 8-bit wide SYNCRAM blocks. The size of the RAM implemented within AHBRAM can be read via the core’s AMBA plug&play version field. The version field will display log2(number of bytes), for a 1 KiB SYNCRAM the version field will have the value 10, where 210 = 1024 bytes = 1 KiB. 8.1.1 Endianness The core is designed for big-endian systems. 8.2 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x00E. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 8.3 Implementation 8.3.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support grlib_async_reset_enable. All registers that react on the reset signal will have a synchronous reset. GRIP, Apr 2018, Version 2018.1 72 www.cobham.com/gaisler GRLIB IP Core 8.4 Configuration options Table 55 shows the configuration options of the core (VHDL generics). Table 55. Configuration options 8.5 Generic Function Allowed range Default hindex AHB slave bus index 0 - NAHBSLV-1 0 haddr The MSB address of the AHB area. Sets the 12 most sig- 0 - 16#FFF# nificant bits in the 32-bit AHB address. 16#FFF# hmask The AHB area address mask. Sets the size of the AHB area and the start address together with haddr. 0 - 16#FFF# 16#FF0# tech Technology to implement on-chip RAM 0 - NTECH 0 kbytes RAM size in KiB. The size of the RAM implemented will be the minumum size that will hold the size specified by kbytes. A value of 1 here will instantiate a 1 KiB SYNCRAM, a value of 3 will instantiate a 4 KiB SYNCRAM. The actual RAM usage on the target technology then depends on the available RAM resources and the technology map. target-dependent 1 pipe Add registers on data outputs. If set to 0 the AMBA data outputs will be connected directly to the core’s internal RAM. If set to 1 the core will include registers on the data outputs. Settings this generic to 1 makes read accesses have one waitstate, otherwise the core will respond to read accesses with zero waitstates. 0-1 0 maccsz Maximum access size supported. This generic restricts the maximum AMBA access size supported by the core and selects the width of the SYNCRAMBW RAM used internally. The default value is assigned from AHBDW, which sets the maximum bus width for the GRLIB design. 32, 64, 128, 256 AHBDW scantest Enable scan test support (passed on to syncram) 0-1 0 Signal descriptions Table 56 shows the interface signals of the core (VHDL ports). Table 56. Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - AHBSI * Input AMB slave input signals - AHBSO * Output AHB slave output signals - * see GRLIB IP Library User’s Manual 8.6 Library dependencies Table 57 shows libraries used when instantiating the core (VHDL libraries). Table 57. Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Types AMBA signal type definitions GAISLER MISC Component Component declaration GRIP, Apr 2018, Version 2018.1 73 www.cobham.com/gaisler GRLIB IP Core 8.7 Component declaration library grlib; use grlib.amba.all; library gaisler; use gaisler.misc.all; component ahbram generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; tech : integer := 0; kbytes : integer := 1); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end component; 8.8 Instantiation This example shows how the core can be instantiated. library grlib; use grlib.amba.all; library gaisler; use gaisler.misc.all; . . ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => 8) port map ( rstn, clkm, ahbsi, ahbso(7)); GRIP, Apr 2018, Version 2018.1 74 www.cobham.com/gaisler GRLIB IP Core 9 AHBDPRAM - Dual-port RAM with AHB interface 9.1 Overview AHBDPRAM implements a 32-bit wide on-chip RAM with one AHB slave interface port and one back-end port for a user application. The AHBDPRAM is therefore useful as a buffer memory between the AHB bus and a custom IP core with a RAM interface The memory size is configurable in binary steps through the abits VHDL generic. The minimum size is 1kB while maximum size is dependent on target technology and physical resources. Read accesses are zero-waitstate, write access have one waitstate. The RAM optionally supports byte- and half-word accesses, as well as all types of AHB burst accesses. Internally, the AHBRAM instantiates one 32-bit or four 8-bit wide SYNCRAM_DP blocks. The target technology must have support for dual-port RAM cells. The back-end port consists of separate clock, address, datain, dataout, enable and write signals. All these signals are sampled on the rising edge of the back-end clock (CLKDP), implementing a synchronous RAM interface. Read-write collisions between the AHB port and the back-end port are not handled and must be prevented by the user. If byte write is enabled, the WRITE(0:3) signal controls the writing of each byte lane in big-endian fashion. WRITE(0) controls the writing of DATAIN(31:24) and so on. If byte write is disabled, WRITE(0) controls writing to the complete 32bit word. 9.1.1 Endianness The core is designed for big-endian systems. 9.2 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x00F. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 9.3 Implementation 9.3.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset. 9.4 Configuration options Table 58 shows the configuration options of the core (VHDL generics). Table 58. Configuration options Generic Function Allowed range Default hindex AHB slave bus index 0 - NAHBSLV-1 0 haddr The MSB address of the AHB area. Sets the 12 most sig- 0 - 16#FFF# nificant bits in the 32-bit AHB address. 16#FFF# hmask The AHB area address mask. Sets the size of the AHB area and the start address together with haddr. 0 - 16#FFF# 16#FF0# tech Technology to implement on-chip RAM 0 - NTECH 2 abits Address bits. The RAM size in Kbytes is equal to 2**(abits +2) 8 - 19 8 bytewrite If set to 1, enabled support for byte and half-word writes 0-1 0 GRIP, Apr 2018, Version 2018.1 75 www.cobham.com/gaisler GRLIB IP Core 9.5 Signal descriptions Table 59 shows the interface signals of the core (VHDL ports). Table 59. Signal descriptions Signal name Field Type Function Active RST N/A Input AHB Reset Low CLK N/A Input AHB Clock - AHBSI * Input AMB slave input signals - AHBSO * Output AHB slave output signals - CLKDP Input Clock for back-end port - ADDRESS(abits-1:0) Input Address for back-end port - DATAIN(31 : 0) Input Write data for back-end port - DATAOUT(31 : 0) Output Read data from back-end port - ENABLE Input Chip select for back-end port High WRITE(0 : 3) Input Write-enable byte select for back-end port High * see GRLIB IP Library User’s Manual 9.6 Library dependencies Table 60 shows libraries used when instantiating the core (VHDL libraries). Table 60. Library dependencies 9.7 Library Package Imported unit(s) Description GRLIB AMBA Types AMBA signal type definitions GAISLER MISC Component Component declaration Component declaration library grlib; use grlib.amba.all; library gaisler; use gaisler.misc.all; component ahbdpram generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; tech : integer := 2; abits : integer range 8 to 19 := 8; bytewrite : integer range 0 to 1 := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; clkdp : in std_ulogic; address : in std_logic_vector((abits -1) downto 0); datain : in std_logic_vector(31 downto 0); dataout : out std_logic_vector(31 downto 0); enable : in std_ulogic;-- active high chip select write : in std_logic_vector(0 to 3)-- active high byte write enable ); end component; GRIP, Apr 2018, Version 2018.1 76 www.cobham.com/gaisler GRLIB IP Core 10 AHBROM - Single-port ROM with AHB interface 10.1 Overview The AHBROM core implements a 32/64/128-bit wide on-chip ROM with an AHB slave interface. Read accesses take zero waitstates, or one waitstate if the pipeline option is enabled. The ROM supports byte- and half-word accesses, as well as all types of AHB burst accesses. 10.2 PROM generation The AHBPROM is automatically generated by the make utility in GRLIB. The input format is a sparc-elf binary file, produced by the BCC cross-compiler (sparc-elf-gcc). To create a PROM, first compile a suitable binary and the run the make utility: bash$ sparc-elf-gcc prom.S -o prom.exe bash$ make ahbrom.vhd Creating ahbrom.vhd : file size 272 bytes, address bits 9 The default binary file for creating a PROM is prom.exe. To use a different file, run make with the FILE parameter set to the input file: bash$ make ahbrom.vhd FILE=myfile.exe The created PROM is realized in synthesizable VHDL code, using a CASE statement. For FPGA targets, most synthesis tools will map the CASE statement on a block RAM/ROM if available. For ASIC implementations, the ROM will be synthesized as gates. It is then recommended to use the pipe option to improve the timing. The default is to build a 32-bit wide ahbrom, to instead build 64-bit or 128-bit wide ahbrom versions, use the flow described above but with the “make ahbrom64.vhd” and “make ahbrom128.vhd” make targets. 10.2.1 Endianness The core is designed for big-endian systems. 10.3 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x01B. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 10.4 Implementation 10.4.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support the GRLIB config package setting grlib_async_reset_enable. GRIP, Apr 2018, Version 2018.1 77 www.cobham.com/gaisler GRLIB IP Core 10.5 Configuration options Table 61 shows the configuration options of the core (VHDL generics). Table 61. Configuration options Generic Function Allowed range Default hindex AHB slave bus index 0 - NAHBSLV-1 0 haddr The MSB address of the AHB area. Sets the 12 most sig- 0 - 16#FFF# nificant bits in the 32-bit AHB address. 16#FFF# hmask The AHB area address mask. Sets the size of the AHB area and the start address together with haddr. 0 - 16#FFF# 16#FF0# tech Not used 0 0 0-1 0 pipe Add a pipeline stage on read data kbytes Not used Only on ahbrom64 and ahbrom128: wideonly 10.6 Removes muxing logic needed to properly support 32-bit masters on wide bus Signal descriptions Table 62 shows the interface signals of the core (VHDL ports). Table 62. Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - AHBSI * Input AMB slave input signals - AHBSO * Output AHB slave output signals - * see GRLIB IP Library User’s Manual 10.7 Library dependencies Table 63 shows libraries used when instantiating the core (VHDL libraries). Table 63. Library dependencies 10.8 Library Package Imported unit(s) Description GRLIB AMBA Types AMBA signal type definitions Component declaration component ahbrom generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; pipe : integer := 0; tech : integer := 0); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end component; GRIP, Apr 2018, Version 2018.1 78 www.cobham.com/gaisler GRLIB IP Core 10.9 Instantiation This example shows how the core can be instantiated. library grlib; use grlib.amba.all; . . brom : entity work.ahbrom generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(8)); GRIP, Apr 2018, Version 2018.1 79 www.cobham.com/gaisler GRLIB IP Core 11 AHBSTAT - AHB Status Registers 11.1 Overview The status registers store information about AMBA AHB accesses triggering an error response. There is a status register and a failing address register capturing the control and address signal values of a failing AMBA bus transaction, or the occurrence of a correctable error being signaled from a another peripheral in the system. The status register and the failing address register are accessed from the AMBA APB bus. 11.2 Operation 11.2.1 Errors The registers monitor AMBA AHB bus transactions and store the current HADDR, HWRITE, HMASTER and HSIZE internally. The monitoring are always active after startup and reset until an error response (HRESP = “01”) is detected. When the error is detected, the status and address register contents are frozen and the New Error (NE) bit is set to one. At the same time an interrupt is generated, as described hereunder. Note that many of the fault tolerant units containing EDAC signal an un-correctable error as an AMBA error response, so that it can be detected by the processor as described above. 11.2.2 Correctable errors Not only error responses on the AHB bus can be detected. Many of the fault tolerant units containing EDAC have a correctable error signal which is asserted each time a correctable error is detected. When such an error is detected, the effect will be the same as for an AHB error response. The only difference is that the Correctable Error (CE) bit in the status register is set to one when a correctable error is detected. When the CE bit is set the interrupt routine can acquire the address containing the correctable error from the failing address register and correct it. When it is finished it resets the NE bit and the monitoring becomes active again. Interrupt handling is described in detail hereunder. The correctable error signals from the fault tolerant units should be connected to the stati.cerror input signal vector of the AHB status register core, which is or-ed internally and if the resulting signal is asserted, it will have the same effect as an AHB error response. 11.2.3 Interrupts The interrupt is generated on the line selected by the pirq VHDL generic. The interrupt is connected to the interrupt controller to inform the processor of the error condition. The normal procedure is that an interrupt routine handles the error with the aid of the information in the status registers. When it is finished it resets the NE bit and the monitoring becomes active again. Interrupts are generated for both AMBA error responses and correctable errors as described above. 11.2.4 Filtering and multiple error detection The status register can optionally be implemented with two sets of status and failing address register. In this case the core also supports filtering on errors and has a status bit that gets set in case additional errors are detected when the New Error (NE) bit is set. The core will only react to the first error in a burst operation. After the first error has been detected, monitoring of the burst is suspended. An error event will only be recorded by the first status register that should react based on filter settings. If register set 1 has reacted then register 2 will not be set for the same error event. GRIP, Apr 2018, Version 2018.1 80 www.cobham.com/gaisler GRLIB IP Core The extra register set, filtering, and multiple error detection is available in revision 1 of the status register. The functionality is enabled through the ver VHDL generic. The value of this generic also affects the core version in the GRLIB plug&play information. 11.3 Registers The core is programmed through registers mapped into APB address space. Table 64. AHB Status registers APB address offset Registers 0x00 AHB Status register 0x04 AHB Failing address register 0x08 AHB Status register 2 (optional) 0x0C AHB Failing Address register 2 (optional) GRIP, Apr 2018, Version 2018.1 81 www.cobham.com/gaisler GRLIB IP Core 11.3.1 AHB Status register Table 65. 0x00, 0x08- AHBS - AHB Status register 31 14 13 12 11 10 RESERVED 9 8 ME FW CF AF CE NE 0 0 r 0 0 0 0 7 6 3 2 0 HWRITE HMASTER HSIZE NR NR NR r r r 0 rw* w* rw* rw* rw rw 31: 14 RESERVED 13 Multiple Error detection (ME) - This field is set to 1 when the New Error bit is set and one more error is detected. Filtering is considered when setting the ME bit. This field is only available in version 1 of the core (version is selected at implementation). 12 Filter Write (FW) - This bit needs to be set to ‘1’ during a write operation for CF and AF fields to be updated in the same write operation. Always reads as zero. This field is only available in version 1 of the core (version is selected at implementation). 11 Correctable Error Filter (CF) - If this bit is set to 1 then this status register will ignore correctable errors. This field will only be written if the FW bit is set. This field is only available in version 1 of the core (version is selected at implementation). 10 AMBA ERROR Filter (AF) - If this bit is set to 1 then this status register will ignore AMBA ERROR. This field will only be written if the FW bit is set. This field is only available in version 1 of the core (version is selected at implementation). 9 Correctable Error (CE) - Set if the detected error was caused by a correctable error and zero otherwise. 8 New Error (NE) - Deasserted at start-up and after reset. Asserted when an error is detected. Reset by writing a zero to it. 7 The HWRITE signal of the AHB transaction that caused the error. 6: 3 The HMASTER signal of the AHB transaction that caused the error. 2: 0 The HSIZE signal of the AHB transaction that caused the error 11.3.2 AHB Failing address register Table 66. 0x04, 0x0C - AHBFAR - AHB Failing address register 31 0 AHB FAILING ADDRESS NR t 31: 0 11.4 The HADDR of the AHB transaction that caused the error. Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x052. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 11.5 Implementation 11.5.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). When reset is asserted the new error and correctable error registers are reset to zero. GRIP, Apr 2018, Version 2018.1 82 www.cobham.com/gaisler GRLIB IP Core 11.6 Configuration options Table 67 shows the configuration options of the core (VHDL generics). Table 67. Configuration options 11.7 Generic Function Allowed range Default pindex APB slave index 0 - NAHBSLV-1 0 paddr APB address 0 - 16#FFF# 0 pmask APB address mask 0 - 16#FFF# 16#FFF# pirq Interrupt line driven by the core 0 - 16#FFF# 0 nftslv Number of FT slaves connected to the cerror vector 1 - NAHBSLV-1 3 ver Selects version of the core. Setting this value to 1 implements the two sets of registers, multiple error detection, and filter functionality. 0-1 0 Signal descriptions Table 68 shows the interface signals of the core (VHDL ports). Table 68. Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - AHBMI * Input AHB slave input signals - AHBSI * Input AHB slave output signals - STATI CERROR Input Correctable Error Signals High APBI * Input APB slave input signals - APBO * Output APB slave output signals - * see GRLIB IP Library User’s Manual 11.8 Library dependencies Table 69 shows libraries used when instantiating the core (VHDL libraries). Table 69. Library dependencies 11.9 Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER MISC Component Component declaration Instantiation This example shows how the core can be instantiated. The example design contains an AMBA bus with a number of AHB components connected to it including the status register. There are three Fault Tolerant units with EDAC connected to the status register cerror vector. The connection of the different memory controllers to external memory is not shown. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; GRIP, Apr 2018, Version 2018.1 83 www.cobham.com/gaisler GRLIB IP Core use grlib.tech.all; library gaisler; use gaisler.memctrl.all; use gaisler.misc.all; entity mctrl_ex is port ( clk : in std_ulogic; rstn : in std_ulogic; --other signals .... ); end; architecture rtl of mctrl_ex is -- AMBA bus (AHB and APB) signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); -- signals used to connect memory controller and memory bus signal memi : memory_in_type; signal memo : memory_out_type; signal sdo, sdo2: sdctrl_out_type; signal sdi : sdctrl_in_type; -- correctable error vector signal stati : ahbstat_in_type; signal aramo : ahbram_out_type; begin -- AMBA Components are defined here ... -- AHB Status Register astat0 : ahbstat generic map(pindex => 13, paddr => 13, pirq => 11, nftslv => 3) port map(rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13)); stati.cerror(3 to NAHBSLV-1) <= (others => ‘0’); --FT AHB RAM a0 : ftahbram generic map(hindex => 1, haddr => 1, tech => inferred, kbytes => 64, pindex => 4, paddr => 4, edacen => 1, autoscrub => 0, errcnt => 1, cntbits => 4) port map(rst, clk, ahbsi, ahbso, apbi, apbo(4), aramo); stati.cerror(0) <= aramo.ce; -- SDRAM controller sdc : ftsdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#, ioaddr => 1, fast => 0, pwron => 1, invclk => 0, edacen => 1, errcnt => 1, cntbits => 4) port map (rstn, clk, ahbsi, ahbso(3), sdi, sdo); stati.cerror(1) <= sdo.ce; -- Memory controller mctrl0 : ftsrctrl generic map (rmw => 1, pindex => 10, paddr => 10, edacen => 1, errcnt => 1, cntbits => 4) port map (rstn, clk, ahbsi, ahbso(0), apbi, apbo(10), memi, memo, sdo2); stati.cerror(2) <= memo.ce; end; GRIP, Apr 2018, Version 2018.1 84 www.cobham.com/gaisler GRLIB IP Core 12 AHBTRACE - AHB Trace buffer 12.1 Overview The trace buffer consists of a circular buffer that stores AMBA AHB data transfers. The address, data and various control signals of the AHB bus are stored and can be read out for later analysis. AHB Trace Buffer Trace buffer RAM Trace control AHB slave interface IRQ AMBA AHB Figure 14. Block diagram When the trace buffer is configured in 32-bit bus mode, it is 128 bits wide. The information stored is indicated in the table below: Table 70. AHB Trace buffer data allocation Bits Name Definition 127:96 Time tag The value of the time tag counter 95 AHB breakpoint hit Set to ‘1’ if a DSU AHB breakpoint hit occurred. 94:80 - Not used 79 Hwrite AHB HWRITE 78:77 Htrans AHB HTRANS 76:74 Hsize AHB HSIZE 73:71 Hburst AHB HBURST 70:67 Hmaster AHB HMASTER 66 Hmastlock AHB HMASTLOCK 65:64 Hresp AHB HRESP 63:32 Load/Store data AHB HRDATA[31:0] or HWDATA[31:0] 31:0 Load/Store address AHB HADDR In addition to the AHB signals, a 32-bit counter is also stored in the trace as time tag. When the trace buffer is configured in 64-bit or 128-bit bus mode, its contents are extended according to the table below. Bits Name Definition 223:160 128-bit extended load/store data AHB HRDATA[127:64] or HWDATA[127:64] 159:128 64-bit extended load/store data AHB HRDATA[63:32] or HWDATA[63:32] GRIP, Apr 2018, Version 2018.1 85 www.cobham.com/gaisler GRLIB IP Core 12.2 Operation 12.2.1 Overview The trace buffer is enabled by setting the enable bit (EN) in the trace control register. Each AMBA AHB transfer is then stored in the buffer in a circular manner. The address to which the next transfer is written is held in the trace buffer index register, and is automatically incremented after each transfer. Tracing is stopped when the EN bit is reset, or when a AHB breakpoint is hit. An interrupt is generated when a breakpoint is hit. Note: the LEON3 and LEON4 Debug Support Units (DSU3/DSU4) also includes an AHB trace buffer. The standalone trace buffer is intended to be used in system without a processor or when the DSU3 is not present. The size of the trace buffer is configured by means of the kbytes VHDL generic, defining the size of the complete buffer in kbytes. The number of lines in the trace buffer is kbytes * 1024 / 16 bytes. The total size of the trace buffer depends on the bwidth generic. When the ahb trace buffer is in 32-bit bus mode, the size of the buffer is simply kbytes kbytes. When the ahb trace buffer is configured in 64-bit or 128-bit bus mode, the kbytes generic will not reflect the exact amount of memory used in the core. You will have to multiply each line, calculated as above, for 20 bytes or 28 bytes, for 64-bit bus mode or 128-bit bus mode respectively. Therefore the total size for the buffer when in 64-bit mode is kbytes * 1.25 kbytes, and for the buffer in 128-bit bus mode it is kbytes * 1.75 kbytes. 12.2.2 AHB statistics The core can be implemented to generate statistics from the traced AHB bus. When statistics collection is enabled the core will assert outputs that are suitable to connect to a LEON statistics unit (L3STAT and L4STAT). The statistical outputs can be filtered by the AHB trace buffer filters, this is controlled by the Performance counter Filter bit (PF) in the AHB trace buffer control register. The core can collect data for the events listed in table 71 below. Table 71. AHB events Event Description Note idle HTRANS=IDLE Active when HTRANS IDLE is driven on the AHB slave inputs and slave has asserted HREADY. busy HTRANS=BUSY Active when HTRANS BUSY is driven on the AHB slave inputs and slave has asserted HREADY. nseq HTRANS=NONSEQ Active when HTRANS NONSEQ is driven on the AHB slave inputs and slave has asserted HREADY. seq HTRANS=SEQ Active when HTRANS SEQUENTIAL is driven on the AHB slave inputs and slave has asserted HREADY. read Read access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and the HWRITE input is low. write Write access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and the HWRITE input is high. hsize[5:0] Transfer size Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and HSIZE is BYTE (hsize[0]), HWORD (HSIZE[1]), WORD (hsize[2]), DWORD (hsize[3]), 4WORD hsize[4], or 8WORD (hsize[5]). ws Wait state Active when HREADY input to AHB slaves is low and AMBA response is OKAY. retry RETRY response Active when master receives RETRY response GRIP, Apr 2018, Version 2018.1 86 www.cobham.com/gaisler GRLIB IP Core Table 71. AHB events Event Description Note split SPLIT response Active when master receives SPLIT response spdel SPLIT delay Active during the time a master waits to be granted access to the bus after reception of a SPLIT response. The core will only keep track of one master at a time. This means that when a SPLIT response is detected, the core will save the master index. This event will then be active until the same master is re-allowed into bus arbitration and is granted access to the bus. This also means that the delay measured will include the time for re-arbitration, delays from other ongoing transfers and delays resulting from other masters being granted access to the bus before the SPLIT:ed master is granted again after receiving SPLIT complete. If another master receives a SPLIT response while this event is active, the SPLIT delay for the second master will not be measured. locked 12.3 Locked access Active while the HMASTLOCK signal is asserted on the AHB slave inputs. (Currently not used by L3STATand L4STAT) Registers 12.3.1 Register address map The trace buffer occupies 128 KiB of address space in the AHB I/O area. The address mapping in parentheses is only available when the core is in 64-bit or 128-bit bus mode. The following register addresses are decoded: Table 72. Trace buffer address space Address Register 0x000000 Trace buffer control register 0x000004 Trace buffer index register 0x000008 Time tag counter 0x00000C Trace buffer master/slave filter register 0x000010 AHB break address 1 0x000014 AHB mask 1 0x000018 AHB break address 2 0x00001C AHB mask 2 0x010000 - 0x020000 Trace buffer ...0 Trace bits 127 - 96 ...4 Trace bits 95 - 64 ...8 Trace bits 63 - 32 ...C Trace bits 31 - 0 (...10) Trace bits 159 - 128, when in 64- or 128-bit bus mode (...14) Trace bits 223 - 192, when in 128-bit bus mode (...18) Trace bits 191 - 160, when in 128-bit bus mode (...1C) Zero GRIP, Apr 2018, Version 2018.1 87 www.cobham.com/gaisler GRLIB IP Core 12.3.2 Trace buffer control register The trace buffer is controlled by the trace buffer control register: Table 73. 0x000000 - CTRL - Trace buffer control register 31 16 15 14 12 11 BSEL 9 8 RESERVED PF 7 6 BW 5 4 3 2 1 0 DCNT BA RF AF FR FW DM EN 0 * 0 0 0 * 0 0 0 * rw r rw r rw r rw rw rw rw r rw 0 0 31: 16 Trace buffer delay counter (DCNT) - Note that the number of bits actually implemented depends on the size of the trace buffer. 15 Bus select Available (BA) - If this field is set to ‘1’, the core has several buses connected. The bus to trace is selected via the BSEL field. If this field is ‘0’, the core is only capable of tracing one AHB bus. 14: 12 Bus select (BSEL) - If the BA field is ‘1’ this field selects the bus to trace. If the BA field is ‘0’, this field is not writable. 11: 9 RESERVED 8 Performance counter Filter (PF) - If this bit is set to ‘1’, the cores performance counter (statistical) outputs will be filtered using the same filter settings as used for the trace buffer. If a filter inhibits a write to the trace buffer, setting this bit to ‘1’ will cause the same filter setting to inhibit the pulse on the statistical output. 7: 6 Bus width (BW) - This value corresponds to log2(Supported bus width / 32) 5 Retry filter (RF) - If this bit is set to ‘1’, AHB retry responses will not be included in the trace buffer. This bit can only be set of the core has been implemented with support for filtering 4 Address Filter (AF) - If this bit is set to ‘1’, only the address range defined by AHB trace buffer breakpoint 2’s address and mask will be included in the trace buffer. This bit can only be set of the core has been implemented with support for filtering 3 Filter Reads (FR) - If this bit is set to ‘1’, read accesses will not be included in the trace buffer. This bit can only be set of the core has been implemented with support for filtering. 2 Filter Writes (FW) - If this bit is set to ‘1’, write accesses will not be included in the trace buffer. This bit can only be set of the core has been implemented with support for filtering. 1 Delay counter mode (DM) - Indicates that the trace buffer is in delay counter mode. 0 Trace enable (EN) - Enables the trace buffer 12.3.3 Trace buffer index register The trace buffer index register indicates the address of the next 128-bit line to be written. Table 74. 0x000004 - INDEX - Trace buffer index register 31 4 3 0 INDEX 0x0 NR 0 rw r 31: 4 Trace buffer index counter (INDEX). Note that the number of bits actually implemented depends on the size of the trace buffer 3: 0 Read as 0x0 GRIP, Apr 2018, Version 2018.1 88 www.cobham.com/gaisler GRLIB IP Core 12.3.4 Trace buffer time tag register The time tag register contains a 32-bit counter that increments each clock when the trace buffer is enabled. The value of the counter is stored in the trace to provide a time tag. Table 75. 0x000008 - TIMETAG - Trace buffer time tag counter 31 0 TIME TAG VALUE 0 r 12.3.5 Trace buffer master/slave filter register The master/slave filter register allows filtering out specified master and slaves from the trace. This register can only be assigned if the trace buffer has been implemented with support for filtering. Table 76. Trace buffer master/slave filter register 31 16 15 SMASK[15:0] 0 MMASK[15:0] 0 0 rw rw 31: 16 Slave Mask (SMASK) - If SMASK[n] is set to ‘1’, the trace buffer will not save accesses performed to slave n. 15: 0 Master Mask (MMASK) - If MMASK[n] is set to ‘1’, the trace buffer will not save accesses performed by master n. 12.3.6 Trace buffer breakpoint registers The DSU contains two breakpoint registers for matching AHB addresses. A breakpoint hit is used to freeze the trace buffer by clearing the enable bit. Freezing can be delayed by programming the DCNT field in the trace buffer control register to a non-zero value. In this case, the DCNT value will be decremented for each additional trace until it reaches zero and after two additional entries, the trace buffer is frozen. A mask register is associated with each breakpoint, allowing breaking on a block of addresses. Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint detection. To break on AHB load or store accesses, the LD and/or ST bits should be set. Table 77. Trace buffer AHB breakpoint address register 31 2 1 0 BADDR[31:2] 0b00 NR 0 rw r 31: 2 Breakpoint address (BADDR) - Bits 31:2 of breakpoint address 1: 0 Reserved, read as 0 Table 78. Trace buffer AHB breakpoint mask register 31 2 BMASK[31:2] 31: 2 1 0 LD ST NR 0 rw rw rw 0 Breakpoint mask (BMASK) - Bits 31:2 of breakpoint mask 1 Load (LD) - Break on data load address 0 Store (ST) - Break on data store address GRIP, Apr 2018, Version 2018.1 89 www.cobham.com/gaisler GRLIB IP Core 12.4 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x017. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 12.5 Implementation 12.5.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. 12.6 Configuration options Table 79 shows the configuration options of the core (VHDL generics). Table 79. Configuration options Generic Function Allowed range Default hindex AHB slave bus index 0 - NAHBSLV-1 0 ioaddr The MSB address of the I/O area. Sets the 12 most significant bits in the 20-bit I/O address. 0 - 16#FFF# 16#000# iomask The I/O area address mask. Sets the size of the I/O area and the start address together with ioaddr. 0 - 16#FFF# 16#E00# irq Interrupt number 0 - NAHBIRQ-1 0 tech Technology to implement on-chip RAM 0 - NTECH 0 kbytes Trace buffer size in kbytes 1 - 64 1 bwidth Traced AHB bus width 32, 64, 128 64 ahbfilt If this generic is set to 1 the core will be implemented with support for AHB trace buffer filters. If ahbpf is larger than 1 then the core’s statistical outputs will be enabled. 0-2 0 ntrace Number of buses to trace. This generic is only available if the entity ahbtrace_mmb is instantiated. 1-8 1 scantest Support scan test and memory BIST 0-1 0 exttimer If set to 1 then the time tag value will be taken from the core’s timer signal input. Otherwise the core will use an internal timer. 0-1 0 GRIP, Apr 2018, Version 2018.1 90 www.cobham.com/gaisler GRLIB IP Core 12.7 Signal descriptions Table 80 shows the interface signals of the core (VHDL ports). Table 80. Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - AHBMI * Input AHB master input signals - AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - TIMER[30:0] N/A Input External timestamp (only used when VHDL generic exttimer is nonzero). Suitable for connection to dbgo.timer signal from debug support unit (DSU IP Core) - ASTAT * Output AHB statistics outputs. Intended to be connected to L3STAT and L4STAT core. - * see GRLIB IP Library User’s Manual 12.8 Library dependencies Table 81 shows libraries used when instantiating the core (VHDL libraries). Table 81. Library dependencies 12.9 Library Package Imported unit(s) Description GRLIB AMBA Types AMBA signal type definitions GAISLER MISC Component Component declaration Component declaration library grlib; use grlib.amba.all; library gaisler; use gaisler.misc.all; component ahbtrace is generic ( hindex : integer := 0; ioaddr : integer := 16#000#; iomask : integer := 16#E00#; tech : integer := 0; irq : integer := 0; kbytes : integer := 1; exttimer : integer range 0 to 1 := 0); port ( rst : in std_ulogic; clk : in std_ulogic; ahbmi : in ahb_mst_in_type; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; timer : in std_logic_vector(30 downto 0) := (others => ‘0’)); end component; -- Tracebuffer that can trace separate bus: component ahbtrace_mb is generic ( hindex : integer := 0; ioaddr : integer := 16#000#; iomask : integer := 16#E00#; GRIP, Apr 2018, Version 2018.1 91 www.cobham.com/gaisler GRLIB IP Core tech : integer := DEFMEMTECH; irq : integer := 0; kbytes : integer := 1; exttimer : integer range 0 to 1 := 0); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; -- Register interface ahbso : out ahb_slv_out_type; tahbmi : in ahb_mst_in_type; tahbsi : in ahb_slv_in_type -- Trace timer : in std_logic_vector(30 downto 0) := (others => ‘0’)); end component; -- Tracebuffer that can trace several separate buses: component ahbtrace_mmb is generic ( hindex : integer := 0; ioaddr : integer := 16#000#; iomask : integer := 16#E00#; tech : integer := DEFMEMTECH; irq : integer := 0; kbytes : integer := 1; ntrace : integer range 1 to 8 := 1; exttimer : integer range 0 to 1 := 0); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; -- Register interface ahbso : out ahb_slv_out_type; tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1) -- Trace timer : in std_logic_vector(30 downto 0) := (others => ‘0’)); end component; GRIP, Apr 2018, Version 2018.1 92 www.cobham.com/gaisler GRLIB IP Core 13 AHBUART- AMBA AHB Serial Debug Interface 13.1 Overview The interface consists of a UART connected to the AMBA AHB bus as a master. A simple communication protocol is supported to transmit access parameters and data. Through the communication link, a read or write transfer can be generated to any address on the AMBA AHB bus. Baud-rate generator RX Serial port Controller 8*bitclk AMBA APB Receiver shift register Transmitter shift register AHB master interface AHB data/response TX AMBA AHB Figure 15. Block diagram 13.2 Operation 13.2.1 Transmission protocol The interface supports a simple protocol where commands consist of a control byte, followed by a 32bit address, followed by optional write data. Write access does not return any response, while a read access only returns the read data. Data is sent on 8-bit basis as shown below. Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Figure 16. Data frame Write Command Send 11 Length -1 Addr[31:24] Addr[23:16] Addr[15:8] Addr[7:0] Addr[7:0] Data[31:24] Data[23:16] Data[15:8] Data[7:0] Read command Send 10 Length -1 Addr[31:24] Addr[23:16] Addr[15:8] Receive Data[31:24] Data[23:16] Data[15:8] Data[7:0] Figure 17. Commands Block transfers can be performed be setting the length field to n-1, where n denotes the number of transferred words. For write accesses, the control byte and address is sent once, followed by the number of data words to be written. The address is automatically incremented after each data word. For GRIP, Apr 2018, Version 2018.1 93 www.cobham.com/gaisler GRLIB IP Core read accesses, the control byte and address is sent once and the corresponding number of data words is returned. 13.2.2 Baud rate generation The UART contains a 18-bit down-counting scaler to generate the desired baud-rate. The scaler is clocked by the system clock and generates a UART tick each time it underflows. The scaler is reloaded with the value of the UART scaler reload register after each underflow. The resulting UART tick frequency should be 8 times the desired baud-rate. If not programmed by software, the baud rate will be automatically discovered. This is done by searching for the shortest period between two falling edges of the received data (corresponding to two bit periods). When three identical two-bit periods has been found, the corresponding scaler reload value is latched into the reload register, and the BL bit is set in the UART control register. If the BL bit is reset by software, the baud rate discovery process is restarted. The baud-rate discovery is also restarted when a ‘break’ or framing error is detected by the receiver, allowing to change to baudrate from the external transmitter. For proper baudrate detection, the value 0x55 should be transmitted to the receiver after reset or after sending break. The best scaler value for manually programming the baudrate can be calculated as follows: scaler = (((system_clk*10)/(baudrate*8))-5)/10 13.3 Registers The core is programmed through registers mapped into APB address space. Table 82. AHB UART registers APB address offset Register 0x4 AHB UART status register 0x8 AHB UART control register 0xC AHB UART scaler register GRIP, Apr 2018, Version 2018.1 94 www.cobham.com/gaisler GRLIB IP Core 13.3.1 AHB UART control register Table 83. 0x08 - CTRL - AHB UART control register 31 2 RESERVED 1 2 BL EN 0 0 r rw rw 0: Receiver enable (EN) - if set, enables both the transmitter and receiver. Reset value: ‘0’. 1: Baud rate locked (BL) - is automatically set when the baud rate is locked. Reset value: ‘0’. 0 13.3.2 AHB UART status register Table 84. 0x04 - STAT - AHB UART status register 31 10 9 8 RESERVED 7 6 5 4 3 2 1 0 RX FE R OV BR TH TS DR 0 MR 0 r r rw 0 0 0 1 1 0 r rw rw r r r 0: Data ready (DR) - indicates that new data has been received by the AMBA AHB master interface. Read only. Reset value: ‘0’. 1: Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty. Read only. Reset value: ‘1’ 2: Transmitter hold register empty (TH) - indicates that the transmitter hold register is empty. Read only. Reset value: ‘1 3: Break (BR) - indicates that a BREAKE has been received. Reset value: ‘0’ 4: Overflow (OV) - indicates that one or more character have been lost due to receiver overflow. Reset value: ‘0’ 6: Frame error (FE) - indicates that a framing error was detected. Reset value: ‘0’ 13.3.3 AHB UART scaler register Table 85. 0x0C - SCALER - AHB UART scaler register 31 18 17 17: 0 13.4 0 RESERVED SCALER RELOAD VALUE 0 0x3FFFB r rw Baudrate scaler reload value = (((system_clk*10)/(baudrate*8))-5)/10. Reset value: “3FFFF“. Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x007. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 13.5 Implementation 13.5.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). GRIP, Apr 2018, Version 2018.1 95 www.cobham.com/gaisler GRLIB IP Core The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support grlib_async_reset_enable. All registers that react on the reset signal will have a synchronous reset. 13.6 Configuration options Table 86 shows the configuration options of the core (VHDL generics). Table 86. Configuration options 13.7 Generic Function Allowed range Default hindex AHB master index 0 - NAHBMST-1 0 pindex APB slave index 0 - NAPBSLV-1 0 paddr ADDR field of the APB BAR. 0 - 16#FFF# 0 pmask MASK field of the APB BAR. 0 - 16#FFF# 16#FFF# Signal descriptions Table 87 shows the interface signals of the core (VHDL ports).. Table 87. Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - UARTI RXD Input UART receiver data High UARTO CTSN Input UART clear-to-send High EXTCLK Input Use as alternative UART clock - RTSN Output UART request-to-send High TXD Output UART transmit data High APBI * Input APB slave input signals - APBO * Output APB slave output signals - AHBI * Input AMB master input signals - AHBO * Output AHB master output signals - * see GRLIB IP Library User’s Manual 13.8 Signal definitions and reset values The signals and their reset values are described in table 88. Table 88. Signal definitions and reset values 13.9 Signal name Type Function Active Reset value dsutx Output UART transmit data line - Logical 1 dsurx Input UART receive data line - - Timing The timing waveforms and timing parameters are shown in figure 18 and are defined in table 89. GRIP, Apr 2018, Version 2018.1 96 www.cobham.com/gaisler GRLIB IP Core clk dsutx tAHBUART0 dsurx tAHBUART1 tAHBUART0 tAHBUART2 Figure 18. Timing waveforms Table 89. Timing parameters Name Parameter Reference edge Min Max Unit tAHBUART0 clock to output delay rising clk edge TBD TBD ns tAHBUART1 input to clock hold rising clk edge - - ns tAHBUART2 input to clock setup rising clk edge - - ns Note: The dsurx input is re-synchronized internally. The signal does not have to meet any setup or hold requirements. 13.10 Library dependencies Table 90 shows libraries used when instantiating the core (VHDL libraries). Table 90. Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER UART Signals, component Signals and component declaration 13.11 Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.uart.all; entity ahbuart_ex is port ( clk : in std_ulogic; rstn : in std_ulogic; -- UART signals ahbrxd : in std_ulogic; ahbtxd : out std_ulogic ); end; architecture rtl of ahbuart_ex is GRIP, Apr 2018, Version 2018.1 97 www.cobham.com/gaisler GRLIB IP Core -- AMBA signals signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); -- UART signals signal ahbuarti : uart_in_type; signal ahbuarto : uart_out_type; begin -- AMBA Components are instantiated here ... -- AHB UART ahbuart0 : ahbuart generic map (hindex => 5, pindex => 7, paddr => 7) port map (rstn, clk, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(5)); -- AHB UART input data ahbuarti.rxd <= ahbrxd; -- connect AHB UART output to entity output signal ahbtxd <= ahbuarto.txd; end; GRIP, Apr 2018, Version 2018.1 98 www.cobham.com/gaisler GRLIB IP Core 14 AMBAMON - AMBA Bus Monitor 14.1 Overview The AMBA bus monitor checks the AHB and APB buses for violations against a set of rules. When an error is detected a signal is asserted and error message is (optionally) printed. 14.2 Rules This section lists all rules checked by the AMBA monitor. The rules are divided into four different tables depending on which type of device they apply to. Some requirements of the AMBA specification are not adopted by the GRLIB implementation (on a system level). These requirements are listed in the table below. Table 91. Requirements not checked in GRLIB Rule Number 1 Description References A slave which issues RETRY must only be accessed by one master at a time. AMBA Spec. Rev 2.0 3-38. Table 92. AHB master rules. Rule Number Description References 1 Busy can only occur in the middle of bursts. That is only after a NON- AMBA Spec. Rev 2.0 3-9. SEQ, SEQ or BUSY. http://www.arm.com/support/faqip/ 492.html 2 Busy can only occur in the middle of bursts. It can be the last access of a burst but only for INCR bursts. AMBA Spec. Rev 2.0 3-9. 3 The address and control signals must reflect the next transfer in the burst during busy cycles. AMBA Spec. Rev 2.0 3-9. 4 The first transfer of a single access or a burst must be NONSEQ (this is ensured together with rule 1). AMBA Spec. Rev 2.0 3-9. 5 HSIZE must never be larger than the bus width. AMBA Spec. Rev 2.0 3-43. 6 HADDR must be aligned to the transfer size. AMBA Spec. Rev 2.0 3-12, 3-25. http://www.arm.com/support/faqip/ 492.html http://www.arm.com/support/faqip/ 582.html 7 Address and controls signals can only change when hready is low if the previous HTRANS value was IDLE, BUSY or if an ERROR, SPLIT or RETRY response is given. http://www.arm.com/support/faqip/ 487.html 8 Address and control signals cannot change between consecutive BUSY cycles. AMBA Spec. Rev 2.0 3-9. 9 Address must be related to the previous access according to HBURST and HSIZE and control signals must be identical for SEQUENTIAL accesses. AMBA Spec. Rev 2.0 3-9. 10 Master must cancel the following transfer when receiving an RETRY response. AMBA Spec. Rev 2.0 3-22. 11 Master must cancel the following transfer when receiving an SPLIT response. AMBA Spec. Rev 2.0 3-22. GRIP, Apr 2018, Version 2018.1 99 http://www.arm.com/support/faqip/ 579.html www.cobham.com/gaisler GRLIB IP Core Table 92. AHB master rules. Rule Number Description 12 Master must reattempt the transfer which received a RETRY response. AMBA Spec. Rev 2.0 3-21. References http://www.arm.com/support/faqip/ 603.html. 13 Master must reattempt the transfer which received a SPLIT response. AMBA Spec. Rev 2.0 3-21. http://www.arm.com/support/faqip/ 603.html. 14 Master can optionally cancel the following transfer when receiving an ERROR response. Only a warning is given if assertions are enabled if it does not cancel the following transfer. AMBA Spec. Rev 2.0 3-23. 15 Master must hold HWDATA stable for the whole data phase when wait states are inserted. Only the appropriate byte lanes need to be driven for subword transfers. AMBA Spec. Rev 2.0 3-7. AMBA Spec. Rev 2.0 3-25. 16 Bursts must not cross a 1 kB address boundary. AMBA Spec. Rev 2.0 3-11. 17 HMASTLOCK indicates that the current transfer is part of a locked sequence. It must have the same timing as address/control. AMBA Spec. Rev 2.0 3-28. 18 HLOCK must be asserted at least one clock cycle before the address phase to which it refers. AMBA Spec. Rev 2.0 3-28. 19 HLOCK must be asserted for the duration of a burst and can only be deasserted so that HMASTLOCK is deasserted after the final address phase. http://www.arm.com/support/faqip/ 597.html 20 HLOCK must be deasserted in the last address phase of a burst. http://www.arm.com/support/faqip/ 588.html 21 HTRANS must be driven to IDLE during reset. http://www.arm.com/support/faqip/ 495.html 22 HTRANS can only change from IDLE to NONSEQ or stay IDLE when HREADY is deasserted. http://www.arm.com/support/faqip/ 579.html Table 93. AHB slave rules. Rule Number Description References 1 AHB slave must respond with a zero wait state OKAY response to BUSY cycles in the same way as for IDLE. AMBA Spec. Rev 2.0 3-9. 2 AHB slave must respond with a zero wait state OKAY response to IDLE. AMBA Spec. Rev 2.0 3-9. 3 HRESP should be set to ERROR, SPLIT or RETRY only one cycle before HREADY is driven high. AMBA Spec. Rev 2.0 3-22. 4 Two-cycle ERROR response must be given. AMBA Spec. Rev 2.0 3-22. 5 Two-cycle SPLIT response must be given. AMBA Spec. Rev 2.0 3-22. 6 Two-cycle RETRY response must be given. AMBA Spec. Rev 2.0 3-22. 7 SPLIT complete signalled to master which did not have pending access. AMBA Spec. Rev 2.0 3-36. 8 Split complete must not be signalled during same cycle as SPLIT. http://www.arm.com/support/faqip/ 616.html 9 It is recommended that slaves drive HREADY high and HRESP to OKAY when not selected. A warning will be given if this is not followed. http://www.arm.com/support/faqip/ 476.html GRIP, Apr 2018, Version 2018.1 100 www.cobham.com/gaisler GRLIB IP Core Table 93. AHB slave rules. Rule Number Description References 10 It is recommended that slaves do not insert more than 16 wait states. If this is violated a warning will be given if assertions are enabled. AMBA Spec. Rev 2.0 3-20. 11 Slaves should not assert the HSPLIT (Split complete) signal for more than one cycle for each SPLIT response. If a slave asserts HSPLIT for more than one cycle it will not cause the system to malfunction. It can however be a indication that a core does not perform as expected. Therefore assertion of HSPLIT during more than one cycle for a SPLIT response is reported as a warning. No reference Table 94. APB slave rules. Rule Number Description References 1 The bus must move to the SETUP state or remain in the IDLE state when in the IDLE state. AMBA Spec. Rev 2.0 5-4. 2 The bus must move from SETUP to ENABLE in one cycle. AMBA Spec. Rev 2.0 5-4. 3 The bus must move from ENABLE to SETUP or IDLE in one cycle. AMBA Spec. Rev 2.0 5-5. 4 The bus must never be in another state than IDLE, SETUP, ENABLE. AMBA Spec. Rev 2.0 5-4. 5 PADDR must be stable during transition from SETUP to ENABLE. AMBA Spec. Rev 2.0 5-5. 6 PWRITE must be stable during transition from SETUP to ENABLE. AMBA Spec. Rev 2.0 5-5. 7 PWDATA must be stable during transition from SETUP to ENABLE. AMBA Spec. Rev 2.0 5-5. 8 Only one PSEL must be enabled at a time. AMBA Spec. Rev 2.0 5-4. 9 PSEL must be stable during transition from SETUP to ENABLE. AMBA Spec. Rev 2.0 5-5. Table 95. Arbiter rules Rule Number Description References 1 HreadyIn to slaves and master must be driven by the currently selected device. http://www.arm.com/support/faqip/ 482.html 2 A master which received a SPLIT response must not be granted the bus until the slave has set the corresponding HSPLIT line. AMBA Spec. Rev 2.0 3-35. 3 The dummy master must be selected when a SPLIT response is received for a locked transfer. http://www.arm.com/support/faqip/ 14307.html GRIP, Apr 2018, Version 2018.1 101 www.cobham.com/gaisler GRLIB IP Core 14.3 Configuration options Table 96 shows the configuration options of the core (VHDL generics). Table 96. Configuration options 14.4 Generic Function Allowed range Default asserterr Enable assertions for AMBA requirements. Violations are asserted with severity error. 0-1 1 assertwarn Enable assertions for AMBA recommendations. Violations are asserted with severity warning. 0-1 1 hmstdisable Disable AHB master rule check. To disable a master rule check a value is assigned so that the binary representation contains a one at the position corresponding to the rule number, e.g 0x80 disables rule 7. - 0 hslvdisable Disable AHB slave tests. Values are assigned as for hmstdisable. - 0 pslvdisable Disable APB slave tests. Values are assigned as for hmst- disable. 0 arbdisable Disable Arbiter tests. Values are assigned as for hmstdis- able. 0 nahbm Number of AHB masters in the system. 0 - NAHBMST NAHBMST nahbs Number of AHB slaves in the system. 0 - NAHBSLV NAHBSLV napb Number of APB slaves in the system. 0 - NAPBSLV NAPBSLV ebterm 0-1 Relax rule checks to allow use in systems with early burst termination. This generic should be set to 0 for systems that use GRLIB’s AHBCTRL core. 0 Signal descriptions Table 97 shows the interface signals of the core (VHDL ports). Table 97. Signal descriptions Signal name Field Type Function Active RST N/A Input AHB reset Low CLK N/A Input AHB clock - AHBMI * Input AHB master interface input record - AHBMO * Input AHB master interface output record array - AHBSI * Input AHB slave interface input record - AHBSO * Input AHB slave interface output record array - APBI * Input APB slave interface input record APBO * Input APB slave interface output record array ERR N/A Output Error signal (error detected) High * see GRLIB IP Library User’s Manual GRIP, Apr 2018, Version 2018.1 102 www.cobham.com/gaisler GRLIB IP Core 14.5 Library dependencies Table 98 shows libraries used when instantiating the core (VHDL libraries). Table 98. Library dependencies 14.6 Library Package Imported unit(s) Description GRLIB AMBA Types AMBA signal type definitions GAISLER SIM Component Component declaration Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.sim.all; entity ambamon_ex is port ( clk : in std_ulogic; rst : in std_ulogic end; architecture rtl of ambamon_ex is -- APB signals signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); -- APB signals signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); begin -- AMBA Components are instantiated here ... library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.sim.all; entity ambamon_ex is port ( clk : in std_ulogic; rst : in std_ulogic; err : out std_ulogic end; architecture rtl of ambamon_ex is -- AHB signals signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => apb_none); -- AHB signals signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => apb_none); -- APB signals GRIP, Apr 2018, Version 2018.1 103 www.cobham.com/gaisler GRLIB IP Core signal apbi signal apbo : apb_slv_in_type; : apb_slv_out_vector := (others => apb_none); begin mon0 : ambamon generic map( assert_err => assert_war => nahbm => nahbs => napb => ) port map( rst => clk => ahbmi => ahbmo => ahbsi => ahbso => apbi => apbo => err => 1, 0, 2, 2, 1 rst, clk, ahbmi, ahbmo, ahbsi, ahbso, apbi, apbo, err); end; GRIP, Apr 2018, Version 2018.1 104 www.cobham.com/gaisler GRLIB IP Core 15 APBCTRL - AMBA AHB/APB bridge with plug&play support 15.1 Overview The AMBA AHB/APB bridge is a APB bus master according the AMBA 2.0 standard. The controller supports up to 16 slaves. The actual maximum number of slaves is defined in the GRLIB.AMBA package, in the VHDL constant NAPBSLV. The number of slaves can also be set using the nslaves VHDL generic. AHB/APB Bridge AHB BUS APBO[0] APB SLAVE AHBSI APBO[n] AHB Slave Interface AHBSO[n] APB SLAVE ••• APBI Figure 19. AHB/APB bridge block diagram 15.2 Operation 15.2.1 Decoding Decoding (generation of PSEL) of APB slaves is done using the plug&play method explained in the GRLIB IP Library User’s Manual. A slave can occupy any binary aligned address space with a size of 256 bytes - 1 Mbyte. Writes to unassigned areas will be ignored, while reads from unassigned areas will return an arbitrary value. AHB error response will never be generated. 15.2.2 Plug&play information GRLIB APB slaves contain two plug&play information words which are included in the APB records they drive on the bus (see the GRLIB IP Library User’s Manual for more information). These records are combined into an array which is connected to the APB bridge. The plug&play information is mapped on a read-only address area at the top 4 kbytes of the bridge address space. Each plug&play block occupies 8 bytes. The address of the plug&play information for a certain unit is defined by its bus index. If the bridge is mapped on AHB address 0x80000000, the address for the plug&play records is thus 0x800FF000 + n*8. 31 APB Plug&play record 24 23 VENDOR ID 0x00 12 11 10 9 DEVICE ID ADDR 0x04 31 C/P 20 19 IRQ 5 VERSION Configuration word IRQ MASK 16 15 0 4 BAR TYPE 4 3 0 Figure 20. APB plug&play information GRIP, Apr 2018, Version 2018.1 105 www.cobham.com/gaisler GRLIB IP Core 15.3 APB bus monitor An APB bus monitor is integrated into the core. It is enabled with the enbusmon generic. It has the same functionality as the APB parts in the AMBA monitor core (AMBAMON). For more information on which rules are checked se the AMBAMON documentation. 15.4 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x006. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 15.5 Implementation 15.5.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core will use asynchronous reset for all registers if the GRLIB config package setting grlib_async_reset_enable is set. 15.6 Configuration options Table 99 shows the configuration options of the core (VHDL generics). Table 99. Configuration options Generic Function Allowed range Default hindex AHB slave index 0 - NAHBSLV-1 0 haddr The MSB address of the AHB area. Sets the 12 most sig- 0 - 16#FFF# nificant bits in the 32-bit AHB address. 0 hmask The AHB area address mask. Sets the size of the AHB area and the start address together with haddr. 0 - 16#FFF# 16#FFF# nslaves The maximum number of slaves 1 - NAPBSLV NAPBSLV debug Print debug information during simulation 0-2 2 icheck Enable bus index checking (PINDEX) 0-1 1 enbusmon Enable APB bus monitor 0-1 0 asserterr Enable assertions for AMBA requirements. Violations are asserted with severity error. 0-1 0 assertwarn Enable assertions for AMBA recommendations. Violations are asserted with severity warning. 0-1 0 pslvdisable Disable APB slave rule check. To disable a slave rule check a value is assigned so that the binary representation contains a one at the position corresponding to the rule number, e.g 0x80 disables rule 7. N/A 0 mcheck Check if there are any intersections between APB slave memory areas. If two areas intersect an assert with level failure will be triggered (in simulation). 0-1 1 ccheck Perform sanity checks on PnP configuration records (in simulation). 0-1 1 GRIP, Apr 2018, Version 2018.1 106 www.cobham.com/gaisler GRLIB IP Core 15.7 Signal descriptions Table 100 shows the interface signals of the core (VHDL ports). Table 100.Signal descriptions Signal name Field Type Function Active RST N/A Input AHB reset Low CLK N/A Input AHB clock - AHBI * Input AHB slave input - AHBO * Output AHB slave output - APBI * Output APB slave inputs - APBO * Input APB slave outputs - * see GRLIB IP Library User’s Manual 15.8 Library dependencies Table 101 shows libraries used when instantiating the core (VHDL libraries). Table 101.Library dependencies 15.9 Library Package Imported unit(s) Description GRLIB AMBA Types AMBA signal type definitions Component declaration library grlib; use grlib.amba.all; component apbctrl generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; nslaves : integer range 1 to NAPBSLV := NAPBSLV; debug : integer range 0 to 2 := 2; -- print config to console icheck : integer range 0 to 1 := 1 ); port ( rst : in std_ulogic; clk : in std_ulogic; ahbi : in ahb_slv_in_type; ahbo : out ahb_slv_out_type; apbi : out apb_slv_in_type; apbo : in apb_slv_out_vector ); end component; 15.10 Instantiation This example shows how an APB bridge can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use work.debug.all; . . GRIP, Apr 2018, Version 2018.1 107 www.cobham.com/gaisler GRLIB IP Core -- AMBA signals signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal apbi signal apbo : apb_slv_in_type; : apb_slv_out_vector := (others => apb_none); begin -- APB bridge apb0 : apbctrl-- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clk, ahbsi, ahbso(1), apbi, apbo ); -- APB slaves uart1 : apbuart generic map (pindex => 1, paddr => 1, pirq => 2) port map (rstn, clk, apbi, apbo(1), u1i, u1o); irqctrl0 : irqmp generic map (pindex => 2, paddr => 2) port map (rstn, clk, apbi, apbo(2), irqo, irqi); ... end; 15.11 Debug print-out The APB bridge can print-out the plug-play information from the attached during simulation. This is enabled by setting the debug VHDL generic to 2. Reporting starts by scanning the array from 0 to NAPBSLV - 1 (defined in the grlib.amba package). It checks each entry in the array for a valid vendor-id (all nonzero ids are considered valid) and if one is found, it also retrieves the device-id. The description for these ids are obtained from the GRLIB.DEVICES package, and is printed on standard out together with the slave number. If the index check is enabled (done with a VHDL generic), the report module also checks if the pindex number returned in the record matches the array number of the record currently checked (the array index). If they do not match, the simulation is aborted and an error message is printed. The address range and memory type is also checked and printed. The address information includes type, address and mask. The address ranges currently defined are AHB memory, AHB I/O and APB I/ O. All APB devices are in the APB I/O range so the type does not have to be checked. From this information, the report module calculates the start address of the device and the size of the range. The information finally printed is start address and size. GRIP, Apr 2018, Version 2018.1 108 www.cobham.com/gaisler GRLIB IP Core 16 APBPS2 - PS/2 host controller with APB interface 16.1 Introduction The PS/2 interface is a bidirectional synchronous serial bus primarily used for keyboard and mouse communications. The APBPS2 core implements the PS2 protocol with a APB back-end. Figure 21 shows a model of APBPS2 and the electrical interface. Vcc FPGA/ASIC PS2Data_out 0 APBPS2 Data Keyboard PS2Data Clock PS2Clk_out 0 PS2Clk Figure 21. APBPS2 electrical interface PS/2 data is sent in 11 bits frames. The first bit is a start bit followed by eight data bits, one odd parity bit and finally one stop bit. Figure 22 shows a typical PS/2 data frame. Data frame with parity: Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop Figure 22. PS/2 data frame 16.2 Receiver operation The receiver of APBPS2 receives the data from the keyboard or mouse, and converts it to 8-bit data frames to be read out via the APB bus. It is enabled through the receiver enable (RE) bit in the PS/2 control register. If a parity error or framing error occurs, the data frame will be discarded. Correctly received data will be transferred to a 16 byte FIFO. The data ready (DR) bit in the PS/2 status register will be set, and retained as long as the FIFO contains at least one data frame. When the FIFO is full, the receiver buffer full (RF) bit in the status register is set. The keyboard will be inhibited and buffer data until the FIFO gets read again. Interrupt is sent when a correct stop bit is received then it’s up to the software to handle any resend operations if the parity bit is wrong. Figure 23 shows a flow chart for the operations of the receiver state machine. GRIP, Apr 2018, Version 2018.1 109 www.cobham.com/gaisler GRLIB IP Core Idle Stop Data 0 rx_en ps2_clk_fall 0 ps2_clk_fall 0 1 ps2_data_sync 1 1 1 update shift register ps2_data_sync 1 0 shift_reg = 1111 1111 shift_reg(0) 1 0 rx_irq = 1 Frame_error = 1 0 Start Parity ps2_clk_fall output buffer full 0 ps2_clk_fall 0 0 1 ps2_data_sync parity_error 1 1 1 1 0 update parity flag update FIFO 0 Idle Figure 23. Flow chart for the receiver state machine 16.3 Transmitter operations The transmitter part of APBPS2 is enabled for through the transmitter enable (TE) bit in the PS/2 control register. The PS/2 interface has a 16 byte transmission FIFO that stores commands sent by the CPU. Commands are used to set the LEDs on the keyboard, and the typematic rate and delay. Typematic rate is the repeat rate of a key that is held down, while the delay controls for how long a key has to be held down before it begins automatically repeating. Typematic repeat rates, delays and possible other commands are listed in table 113. If the TE bit is set and the transmission FIFO is not empty a transmission of the command will start. The host will pull the clock line low for at least 100 us and then transmit a start bit, the eight bit command, an odd parity bit, a stop bit and wait for an acknowledgement bit by the device. When this happens an interrupt is generated. Figure 24 shows the flow chart for the transmission state machine. 16.4 Clock generation A PS/2 interface should generate a clock of 10.0 - 16.7 kHz. To transmit data, a PS/2 host must inhibit communication by pulling the clock low for at least 100 microseconds. To do this, APBPS2 divides the APB clock with either a fixed or programmable division factor. The divider consist of a 17-bit down-counter and can divide the APB clock with a factor of 1 - 131071. The division rate, and the reset value of the timer reload register, is set to the fKHz generic divided by 10 in order to generate the 100 microsecond clock low time. If the VHDL generic fixed is 0, the division rate can be programmed through the timer reload register and should be programmed with the system frequency in kHz divided by ten. The reset value of the reload register is always set to the fKHz value divided by ten. However, the register will not be readable via the APB interface unless the fixed VHDL generic has been set to 0. GRIP, Apr 2018, Version 2018.1 110 www.cobham.com/gaisler GRLIB IP Core Idle 0 tx_en Start Stop ps2clkoe = 1 read FIFO ps2_clk_fall 1 fifo_empty 0 1 Data 1 ps2data = 1 0 ps2_clk_fall 0 ps2clk = 0 ps2clkoe = 0 Ack 1 ps2data = shift_reg(0) update shift_reg ps2data = 1 ps2dataoe = 0 shift_reg empty Waitrequest ps2dataoe = 1 0 0 ps2_clk_fall 1 1 Parity timer = timer + 1 1 ps2_data_sync timer < 5000 1 ps2_clk_fall 0 0 tx_irq = 1, ps2data = 1 ps2dataoe = 1, 0 1 ps2clk = 1, ps2data = 0 timer = 0 ps2data = parity bit Idle Figure 24. Flow chart for the transmitter state machine 16.5 Registers The core is controlled through registers mapped into APB address space. Table 102.APB PS/2 registers APB address offset Register 0x00 PS/2 Data register 0x04 PS/2 Status register 0x08 PS/2 Control register 0x0C PS/2 Timer reload register 16.5.1 PS/2 Data Register Table 103.0x00 - DATA - PS/2 data register 31 8 7: 0 7 0 RESERVED DATA 0 NR r rw Receiver holding FIFO (read access) and Transmitter holding FIFO (write access). If the receiver FIFO is not empty, read accesses retrieve the next byte from the FIFO. Bytes written to this field are stored in the transmitter holding FIFO if it is not full. GRIP, Apr 2018, Version 2018.1 111 www.cobham.com/gaisler GRLIB IP Core 16.5.2 PS/2 Status Register Table 104.0x04 - STAT - PS/2 status register 31 27 26 22 6 5 4 3 2 1 0 RCNT TCNT RESERVED TF RF KI FE PE DR 0 0 0 0 0 0 0 0 r r r r r rw rw rw r 0 0: Data ready (DR) - indicates that new data is available in the receiver holding register (read only). 1: Parity error (PE) - indicates that a parity error was detected 2: Framing error (FE) - indicates that a framing error was detected. 3: Keyboard inhibit (KI) - indicates that the keyboard is inhibited. 4: Receiver buffer full (RF) - indicates that the output buffer (FIFO) is full (read only). 5: Transmitter buffer full (TF) - indicates that the input buffer (FIFO) is full (read only). 26: 22 Transmit FIFO count (TCNT) - shows the number of data frames in the transmit FIFO (read only). 31: 27 Receiver FIFO count (RCNT) - shows the number of data frames in the receiver FIFO (read only). 16.5.3 PS/2 Control Register Table 105.0x08 - CTRL - PS/2 control register 31 4 3 2 TI RI TE RE 0 0 0 r rw rw rw rw RESERVED 0: Receiver enable (RE) - if set, enables the receiver. 1: Transmitter enable (TE) - if set, enables the transmitter. 2: Keyboard interrupt enable (RI) - if set, interrupts are generated when a frame is received. 3: Host interrupt enable (TI) - if set, interrupts are generated when a frame is transmitted. 1 0 0 0 16.5.4 PS/2 Timer Reload Register Table 106.0x0C - TIMER - PS/2 reload register 31 17 16 RESERVED 16: 0 16.6 0 TIMER RELOAD REG 0 * r rw* PS/2 timer reload register - Reset value determined by fktlz VHDL generic. Register only present it “fixed” VHDL generic is zero. Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x060. For a description of vendor and device identifiers see GRLIB IP Library User’s Manual. 16.7 Implementation 16.7.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. GRIP, Apr 2018, Version 2018.1 112 www.cobham.com/gaisler GRLIB IP Core 16.8 Configuration options Table 107 shows the configuration options of the core (VHDL generics). Table 107.Configuration options 16.9 Generic Function Allowed range Default pindex APB slave index 0 - NAPBSLV-1 0 paddr ADDR field of the APB BAR. 0 - 16#FFF# 0 pmask MASK field of the APB BAR. 0 - 16#FFF# 16#FFF# pirq Index of the interrupt line. 0 - NAHBIRQ-1 0 fKHz Frequency of APB clock in KHz. This value divided by 10 is the reset value of the timer reload register. 1 - 1310710 50000 fixed Used fixed clock divider to generate PS/2 clock. 0-1 0 oepol Output enable polarity 0-1 0 Signal descriptions Table 108 shows the interface signals of the core (VHDL ports). Table 108.Signal descriptions Signal name Field Type Function RST N/A Input Reset Low CLK N/A Input Clock - APBI * Input APB slave input signals - APBO * Output APB slave output signals - PS2I PS2O Active PS2_CLK_I Input PS/2 clock input - PS2_DATA_I Input PS/2 data input - PS2_CLK_O Output PS/2 clock output - PS2_CLK_OE Output PS/2 clock output enable Low PS2_DATA_O Output PS/2 data output - PS2_DATA_OE Output PS/2 data output enable Low * see GRLIB IP Library User’s Manual 16.10 Library dependencies Table 109 shows libraries used when instantiating the core (VHDL libraries). Table 109.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals APB signal definitions GAISLER MISC Signals, component PS/2 signal and component declaration 16.11 Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; GRIP, Apr 2018, Version 2018.1 113 www.cobham.com/gaisler GRLIB IP Core use grlib.amba.all; use grlib.gencomp.all; library gaisler; use gaisler.misc.all; entity apbps2_ex is port ( rstn : in std_ulogic; clk : in std_ulogic; -- PS/2 signals ps2clk : inout std_ulogic; ps2data : inout std_ulogic ); end; architecture rtl of apbuart_ex is -- APB signals signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); -- PS/2 signals signal kbdi : ps2_in_type; signal kbdo : ps2_out_type; begin ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 4) port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo); kbdclk_pad : iopad generic map (tech => padtech) port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i); kbdata_pad : iopad generic map (tech => padtech) port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i); end; GRIP, Apr 2018, Version 2018.1 114 www.cobham.com/gaisler GRLIB IP Core 16.12 Keboard scan codes Table 110.Scan code set 2, 104-key keyboard KEY MAKE BREAK A 1C F0,1C B 32 F0,32 C 21 F0,21 D 23 E F G - KEY 9 MAKE BREAK - KEY MAKE BREAK 46 F0,46 [ 54 FO,54 `0E F0,0E INSERT E0,70 E0,F0,70 - 4E F0,4E HOME E0,6C E0,F0,6C F0,23 = 55 FO,55 PG UP E0,7D E0,F0,7D 24 F0,24 \ 5D F0,5D DELETE E0,71 E0,F0,71 2B F0,2B BKSP 66 F0,66 END E0,69 E0,F0,69 34 F0,34 SPACE 29 F0,29 PG DN E0,7A E0,F0,7A H 33 F0,33 TAB 0D F0,0D U ARROW E0,75 E0,F0,75 I 43 F0,43 CAPS 58 F0,58 L ARROW E0,6B E0,F0,6B J 3B F0,3B L SHFT 12 FO,12 D ARROW E0,72 E0,F0,72 K 42 F0,42 L CTRL 14 FO,14 R ARROW E0,74 E0,F0,74 L 4B F0,4B L GUI E0,1F E0,F0,1F NUM 77 F0,77 M 3A F0,3A L ALT 11 F0,11 KP / E0,4A E0,F0,4A N 31 F0,31 R SHFT 59 F0,59 KP * 7C F0,7C O 44 F0,44 R CTRL E0,14 E0,F0,14 KP - 7B F0,7B P 4D F0,4D R GUI E0,27 E0,F0,27 KP + 79 F0,79 Q 15 F0,15 R ALT E0,11 E0,F0,11 KP EN E0,5A E0,F0,5A R 2D F0,2D APPS E0,2F E0,F0,2F KP . 71 F0,71 S 1B F0,1B ENTER 5A F0,5A KP 0 70 F0,70 T 2C F0,2C ESC 76 F0,76 KP 1 69 F0,69 U 3C F0,3C F1 5 F0,05 KP 2 72 F0,72 V 2A F0,2A F2 6 F0,06 KP 3 7A F0,7A W 1D F0,1D F3 4 F0,04 KP 4 6B F0,6B X 22 F0,22 F4 0C F0,0C KP 5 73 F0,73 Y 35 F0,35 F5 3 F0,03 KP 6 74 F0,74 Z 1A F0,1A F6 0B F0,0B KP 7 6C F0,6C 0 45 F0,45 F7 83 F0,83 KP 8 75 F0,75 1 16 F0,16 F8 0A F0,0A KP 9 7D F0,7D 2 1E F0,1E F9 1 F0,01 ] 5B F0,5B 3 26 F0,26 F10 9 F0,09 ; 4C F0,4C 4 25 F0,25 F11 78 F0,78 52 F0,52 5 2E F0,2E F12 7 F0,07 , 41 F0,41 6 36 F0,36 PRNT SCRN E0,12, E0,7C E0,F0, 7C,E0, F0,12 . 49 F0,49 7 3D F0,3D SCROLL 7E F0,7E / 4A F0,4A 8 3E F0,3E PAUSE E1,14,77, E1,F0,14, F0,77 -NONE- GRIP, Apr 2018, Version 2018.1 115 www.cobham.com/gaisler GRLIB IP Core Table 111.Windows multimedia scan codes KEY MAKE BREAK Next Track E0, 4D E0, F0, 4D Previous Track E0, 15 E0, F0, 15 Stop E0, 3B E0, F0, 3B Play/Pause E0, 34 E0, F0, 34 Mute E0, 23 E0, F0, 23 Volume Up E0, 32 E0, F0, 32 Volume Down E0, 21 E0, F0, 21 Media Select E0, 50 E0, F0, 50 E-Mail E0, 48 E0, F0, 48 Calculator E0, 2B E0, F0, 2B My Computer E0, 40 E0, F0, 40 WWW Search E0, 10 E0, F0, 10 WWW Home E0, 3A E0, F0, 3A WWW Back E0, 38 E0, F0, 38 WWW Forward E0, 30 E0, F0, 30 WWW Stop E0, 28 E0, F0, 28 WWW Refresh E0, 20 E0, F0, 20 WWW Favorites E0, 18 E0, F0, 18 Table 112.ACPI scan codes (Advanced Configuration and Power Interface) KEY MAKE BREAK Power E0, 37 E0, F0, 37 Sleep E0, 3F E0, F0, 3F Wake E0, 5E E0, F0, 5E GRIP, Apr 2018, Version 2018.1 116 www.cobham.com/gaisler GRLIB IP Core 16.13 Keyboard commands Table 113.Transmit commands: Command Description 0xED Set status LED’s - keyboard will reply with ACK (0xFA). The host follows this command with an argument byte* 0xEE Echo command - expects an echo response 0xF0 Set scan code set - keyboard will reply with ACK (0xFA) and wait for another byte. 0x01-0x03 which determines the scan code set to use. 0x00 returns the current set. 0xF2 Read ID - the keyboard responds by sending a two byte device ID of 0xAB 0x83 0xF3 Set typematic repeat rate - keyboard will reply with ACK (0xFA) and wait for another byte which determines the typematic rate. 0xF4 Keyboard enable - clears the keyboards output buffer, enables keyboard scanning and returns an acknowledgement. 0xF5 Keyboard disable - resets the keyboard, disables keyboard scanning and returns an acknowledgement. 0xF6 Set default - load default typematic rate/delay (10.9cps/500ms) and scan code set 2 0xFE Resend - upon receipt of the resend command the keyboard will retransmit the last byte 0xFF Reset - resets the keyboard * bit 0 controls the scroll lock, bit 1 the num lock, bit 2 the caps lock, bit 3-7 are ignored Table 114.Receive commands: Command Description 0xFA Acknowledge 0xAA Power on self test passed (BAT completed) 0xEE Echo respond 0xFE Resend - upon receipt of the resend command the host should retransmit the last byte 0x00 Error or buffer overflow 0xFF Error of buffer overflow Table 115.The typematic rate/delay argument byte MSB 0 LSB DELAY DELAY GRIP, Apr 2018, Version 2018.1 RATE RATE 117 RATE RATE RATE www.cobham.com/gaisler GRLIB IP Core Table 116.Typematic repeat rates Bits 04 Rate (cps) Bits 04 Rate (cps) Bits 04 Rate (cps) Bits 04 Rate (cps) 00h 30 08h 15 10h 7.5 18h 3.7 01h 26.7 09h 13.3 11h 6.7 19h 3.3 02h 24 0Ah 12 12h 6 1Ah 3 03h 21.8 0Bh 10.9 13h 5.5 1Bh 2.7 04h 20.7 0Ch 10 14h 5 1Ch 2.5 05h 18.5 0Dh 9.2 15h 4.6 1Dh 2.3 06h 17.1 0Eh 8.6 16h 4.3 1Eh 2.1 07h 16 0Fh 8 17h 4 1Fh 2 Table 117.Typematic delays Bits 5-6 Delay (seconds) 00b 0.25 01b 0.5 10b 0.75 11b 1 GRIP, Apr 2018, Version 2018.1 118 www.cobham.com/gaisler GRLIB IP Core 17 APBUART - AMBA APB UART Serial Interface 17.1 Overview The interface is provided for serial communications. The UART supports data frames with 8 data bits, one optional parity bit and one or two stop bits. To generate the bit-rate, each UART has a programmable 12-bit clock divider. Two FIFOs are used for data transfer between the APB bus and UART, when fifosize VHDL generic > 1. Two holding registers are used data transfer between the APB bus and UART, when fifosize VHDL generic = 1. Hardware flow-control is supported through the RTSN/ CTSN hand-shake signals, when flow VHDL generic is set. Parity is supported, when parity VHDL generic is set. Baud-rate generator RXD 8*bitclk Serial port Controller Receiver shift register Transmitter shift register Receiver FIFO or holding register Transmitter FIFO or holding register CTSN RTSN TXD APB Figure 25. Block diagram 17.2 Operation 17.2.1 Transmitter operation The transmitter is enabled through the TE bit in the UART control register. Data that is to be transferred is stored in the FIFO/holding register by writing to the data register. This FIFO is configurable to different sizes via the fifosize VHDL generic. When the size is 1, only a single holding register is used but in the following discussion both will be referred to as FIFOs. When ready to transmit, data is transferred from the transmitter FIFO/holding register to the transmitter shift register and converted to a serial stream on the transmitter serial output pin (TXD). It automatically sends a start bit followed by eight data bits, an optional parity bit, and one stop bit (figure 26). The least significant bit of the data is sent first. It is also possible to use two stop bits, this is configured via the control register. GRIP, Apr 2018, Version 2018.1 119 www.cobham.com/gaisler GRLIB IP Core Data frame, no parity: Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Data frame with parity: Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop Figure 26. UART data frames Following the transmission of the stop bit, if a new character is not available in the transmitter FIFO, the transmitter serial data output remains high and the transmitter shift register empty bit (TS) will be set in the UART status register. Transmission resumes and the TS is cleared when a new character is loaded into the transmitter FIFO. When the FIFO is empty the TE bit is set in the status register. If the transmitter is disabled, it will immediately stop any active transmissions including the character currently being shifted out from the transmitter shift register. The transmitter holding register may not be loaded when the transmitter is disabled or when the FIFO (or holding register) is full. If this is done, data might be overwritten and one or more frames are lost. The discussion above applies to any FIFO configurations including the special case with a holding register (VHDL generic fifosize = 1). If FIFOs are used (VHDL generic fifosize > 1) some additional status and control bits are available. The TF status bit (not to be confused with the TF control bit) is set if the transmitter FIFO is currently full and the TH bit is set as long as the FIFO is less than halffull (less than half of entries in the FIFO contain data). The TF control bit enables FIFO interrupts when set. The status register also contains a counter (TCNT) showing the current number of data entries in the FIFO. When flow control is enabled, the CTSN input must be low in order for the character to be transmitted. If it is deasserted in the middle of a transmission, the character in the shift register is transmitted and the transmitter serial output then remains inactive until CTSN is asserted again. If the CTSN is connected to a receivers RTSN, overrun can effectively be prevented. 17.2.2 Receiver operation The receiver is enabled for data reception through the receiver enable (RE) bit in the UART control register. The receiver looks for a high to low transition of a start bit on the receiver serial data input pin. If a transition is detected, the state of the serial input is sampled a half bit clocks later. If the serial input is sampled high the start bit is invalid and the search for a valid start bit continues. If the serial input is still low, a valid start bit is assumed and the receiver continues to sample the serial input at one bit time intervals (at the theoretical centre of the bit) until the proper number of data bits and the parity bit have been assembled and one stop bit has been detected. The serial input is shifted through an 8-bit shift register where all bits have to have the same value before the new value is taken into account, effectively forming a low-pass filter with a cut-off frequency of 1/8 system clock. The receiver also has a configurable FIFO which is identical to the one in the transmitter. As mentioned in the transmitter part, both the holding register and FIFO will be referred to as FIFO. During reception, the least significant bit is received first. The data is then transferred to the receiver FIFO and the data ready (DR) bit is set in the UART status register as soon as the FIFO contains at least one data frame. The parity, framing and overrun error bits are set at the received byte boundary, at the same time as the data ready bit would have been set. The data frame is not stored in the FIFO if an error is detected. Also, the new error status bits are or:ed with the old values before they are stored into the status register. Thus, they are not cleared until written to with zeros from the AMBA APB bus. If both the receiver FIFO and shift registers are full when a new start bit is detected, then the GRIP, Apr 2018, Version 2018.1 120 www.cobham.com/gaisler GRLIB IP Core character held in the receiver shift register will be lost and the overrun bit will be set in the UART status register. A break received (BR) is indicated when a BREAK has been received, which is a framing error with all data received being zero. If flow control is enabled, then the RTSN will be negated (high) when a valid start bit is detected and the receiver FIFO is full. When the holding register is read, the RTSN will automatically be reasserted again. When the VHDL generic fifosize > 1, which means that holding registers are not considered here, some additional status and control bits are available. The RF status bit (not to be confused with the RF control bit) is set when the receiver FIFO is full. The RH status bit is set when the receiver FIFO is half-full (at least half of the entries in the FIFO contain data frames). The RF control bit enables receiver FIFO interrupts when set. A RCNT field is also available showing the current number of data frames in the FIFO. 17.3 Baud-rate generation Each UART contains a 12-bit down-counting scaler to generate the desired baud-rate, the number of scaler bits can be increased with VHDL generic sbits. The scaler is clocked by the system clock and generates a UART tick each time it underflows. It is reloaded with the value of the UART scaler reload register after each underflow. The resulting UART tick frequency should be 8 times the desired baud-rate. One appropriate formula to calculate the scaler value for a desired baud rate, using integer division where the remainder is discarded, is: scaler value = (system_clock_frequency) / (baud_rate * 8 + 7). To calculate the exact required scaler value use: scaler value = (system_clock_frequency) / (baud_rate * 8) - 1 If the EC bit is set, the ticks will be generated with the same frequency as the external clock input instead of at the scaler underflow rate. In this case, the frequency of external clock must be less than half the frequency of the system clock. 17.4 Loop back mode If the LB bit in the UART control register is set, the UART will be in loop back mode. In this mode, the transmitter output is internally connected to the receiver input and the RTSN is connected to the CTSN. It is then possible to perform loop back tests to verify operation of receiver, transmitter and associated software routines. In this mode, the outputs remain in the inactive state, in order to avoid sending out data. 17.5 FIFO debug mode FIFO debug mode is entered by setting the debug mode bit in the control register. In this mode it is possible to read the transmitter FIFO and write the receiver FIFO through the FIFO debug register. The transmitter output is held inactive when in debug mode. A write to the receiver FIFO generates an interrupt if receiver interrupts are enabled. 17.6 Interrupt generation Interrupts are generated differently when a holding register is used (VHDL generic fifosize = 1) and when FIFOs are used (VHDL generic fifosize > 1). When holding registers are used, the UART will generate an interrupt under the following conditions: when the transmitter is enabled, the transmitter interrupt is enabled and the transmitter holding register moves from full to empty; when the receiver is enabled, the receiver interrupt is enabled and the receiver holding register moves from empty to full; when the receiver is enabled, the receiver interrupt is enabled and a character with either parity, framing or overrun error is received. GRIP, Apr 2018, Version 2018.1 121 www.cobham.com/gaisler GRLIB IP Core For FIFOs, two different kinds of interrupts are available: normal interrupts and FIFO interrupts. For the transmitter, normal interrupts are generated when transmitter interrupts are enabled (TI), the transmitter is enabled and the transmitter FIFO goes from containing data to being empty. FIFO interrupts are generated when the FIFO interrupts are enabled (TF), transmissions are enabled (TE) and the UART is less than half-full (that is, whenever the TH status bit is set). This is a level interrupt and the interrupt signal is continuously driven high as long as the condition prevails. The receiver interrupts work in the same way. Normal interrupts are generated in the same manner as for the holding register. FIFO interrupts are generated when receiver FIFO interrupts are enabled, the receiver is enabled and the FIFO is half-full. The interrupt signal is continuously driven high as long as the receiver FIFO is half-full (at least half of the entries contain data frames). Note that when using any of the LEON interrupt controllers, the processor acknowledges and clears the corresponding interrupt pending register but as the interrupt signal is continuously driven high another instance of interrupt pending is set in the interrupt controller. To reduce interrupt occurrence a delayed receiver interrupt is available. It is enabled using the delayed interrupt enable (DI) bit. When enabled a timer is started each time a character is received and an interrupt is only generated if another character has not been received within 4 character + 4 bit times. If receiver FIFO interrupts are enabled a pending character interrupt will be cleared when the FIFO interrupt is active since the character causing the pending irq state is already in the FIFO and is noticed by the driver through the FIFO interrupt. In order to not take one additional interrupt (due to the interrupt signal being driven continuously high as described above), software should clear the corresponding pending bit in the interrupt controller after the FIFO has been emptied. There is also a separate interrupt for break characters. When enabled an interrupt will always be generated immediately when a break character is received even when delayed receiver interrupts are enabled. When break interrupts are disabled no interrupt will be generated for break characters when delayed interrupts are enabled. When delayed interrupts are disabled the behavior is the same for the break interrupt bit except that an interrupt will be generated for break characters if receiver interrupt enable is set even if break interrupt is disabled. An interrupt can also be enabled for the transmitter shift register. When enabled the core will generate an interrupt each time the shift register goes from a non-empty to an empty state. 17.7 Registers The core is controlled through registers mapped into APB address space. Table 118.UART registers APB address offset Register 0x0 UART Data register 0x4 UART Status register 0x8 UART Control register 0xC UART Scaler register 0x10 UART FIFO debug register GRIP, Apr 2018, Version 2018.1 122 www.cobham.com/gaisler GRLIB IP Core 17.7.1 UART Data Register Table 119. 0x00 - DATA - UART data register 31 8 7 0 RESERVED DATA NR rw 7: 0 Receiver holding register or FIFO (read access) 7: 0 Transmitter holding register or FIFO (write access) 17.7.2 UART Status Register Table 120. 0x04 - STAT - UART status register 31 26 25 20 19 11 10 9 8 7 6 5 4 3 2 1 0 RCNT TCNT RESERVED 0 0 0 0 0 0 0 0 0 1 1 0 r r r r r r r rw rw rw rw r r r 31: 26 RF TF RH TH FE PE OV BR TE TS DR 0 0 Receiver FIFO count (RCNT) - shows the number of data frames in the receiver FIFO. Reset: 0 25: 20 Transmitter FIFO count (TCNT) - shows the number of data frames in the transmitter FIFO. Reset: 0 10 Receiver FIFO full (RF) - indicates that the Receiver FIFO is full. Reset: 0 9 Transmitter FIFO full (TF) - indicates that the Transmitter FIFO is full. Reset: 0 8 Receiver FIFO half-full (RH) -indicates that at least half of the FIFO is holding data. Reset: 0 7 Transmitter FIFO half-full (TH) - indicates that the FIFO is less than half-full. Reset: 0 6 Framing error (FE) - indicates that a framing error was detected. Reset: 0 5 Parity error (PE) - indicates that a parity error was detected. Reset: 0 4 Overrun (OV) - indicates that one or more character have been lost due to overrun. Reset: 0 3 Break received (BR) - indicates that a BREAK has been received. Reset: 0 2 Transmitter FIFO empty (TE) - indicates that the transmitter FIFO is empty. Reset: 1 1 Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty. Reset: 1 0 Data ready (DR) - indicates that new data is available in the receiver holding register. Reset: 0 GRIP, Apr 2018, Version 2018.1 123 www.cobham.com/gaisler GRLIB IP Core 17.7.3 UART Control Register Table 121. UART control register 31 30 16 15 14 13 12 11 10 FA RESERVED NS SI DI 9 8 7 6 5 4 3 BI DB RF TF EC LB FL PE PS TI 0 NR 0 2 1 0 RI TE RE 0 0 NR NR NR NR NR NR NR r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw NR NR NR NR 0 0 31 FIFOs available (FA) - Set to 1 when receiver and transmitter FIFOs are available. When 0, only holding register are available. 30: 16 RESERVED 15 Number of stop bits (NS) - When set to ‘1’ then two stop bits will be used, otherwise one stop bit will be used. 14 Transmitter shift register empty interrupt enable (SI) - When set, an interrupt will be generated when the transmitter shift register becomes empty. See section 17.6 for more details. 13 Delayed interrupt enable (DI) - When set, delayed receiver interrupts will be enabled and an interrupt will only be generated for received characters after a delay of 4 character times + 4 bits if no new character has been received during that interval. This is only applicable if receiver interrupt enable is set. See section 17.6 for more details. 12 Break interrupt enable (BI) - When set, an interrupt will be generated each time a break character is received. See section 16.6 for more details. 11 FIFO debug mode enable (DB) - when set, it is possible to read and write the FIFO debug register. 10 Receiver FIFO interrupt enable (RF) - when set, Receiver FIFO level interrupts are enabled. 9 Transmitter FIFO interrupt enable (TF) - when set, Transmitter FIFO level interrupts are enabled. 8 External Clock (EC) - if set, the UART scaler will be clocked by UARTI.EXTCLK. 7 Loop back (LB) - if set, loop back mode will be enabled. 6 Flow control (FL) - if set, enables flow control using CTS/RTS (when implemented). 5 Parity enable (PE) - if set, enables parity generation and checking (when implemented). 4 Parity select (PS) - selects parity polarity (0 = even parity, 1 = odd parity) (when implemented). 3 Transmitter interrupt enable (TI) - if set, interrupts are generated when characters are transmitted (see section 17.6 for details). 2 Receiver interrupt enable (RI) - if set, interrupts are generated when characters are received (see section 17.6 for details). 1 Transmitter enable (TE) - if set, enables the transmitter. 0 Receiver enable (RE) - if set, enables the receiver. 17.7.4 UART Scaler Register Table 122.0x0C - SCALER - UART scaler reload register 31 sbits sbits-1:0 sbits-1 0 RESERVED SCALER RELOAD VALUE 0 NR r rw Scaler reload value GRIP, Apr 2018, Version 2018.1 124 www.cobham.com/gaisler GRLIB IP Core 17.7.5 UART FIFO Debug Register Table 123. 0x10 - DEBUG - UART FIFO debug register 31 17.8 8 7 0 RESERVED DATA 0 NR r rw 7: 0 Transmitter holding register or FIFO (read access) 7: 0 Receiver holding register or FIFO (write access) Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x00C. For a description of vendor and device identifiers see GRLIB IP Library User’s Manual. 17.9 Implementation 17.9.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support grlib_async_reset_enable. All registers that react on the reset signal will have a synchronous reset. 17.10 Configuration options Table 124 shows the configuration options of the core (VHDL generics). Table 124.Configuration options Generic Function Allowed range Default pindex APB slave index 0 - NAPBSLV-1 0 paddr ADDR field of the APB BAR. 0 - 16#FFF# 0 pmask MASK field of the APB BAR. 0 - 16#FFF# 16#FFF# console Prints output from the UART on console during VHDL simulation and speeds up simulation by always returning ‘1’ for Data Ready bit of UART Status register. Does not affect synthesis. 0-1 0 pirq Index of the interrupt line. 0 - NAHBIRQ-1 0 parity Enables parity 0-1 1 flow Enables flow control. Flow control must be implemented for FIFO debug mode to be supported. Setting this generic to 0 also disables FIFO debug mode. 0-1 1 fifosize Selects the size of the Receiver and Transmitter FIFOs 1, 2, 4, 8, 16, 32 1 abits Selects the number of APB address bits used to decode the register addresses 3-8 8 sbits Selects the number of bits in the scaler 12-32 12 GRIP, Apr 2018, Version 2018.1 125 www.cobham.com/gaisler GRLIB IP Core 17.11 Signal descriptions Table 125 shows the interface signals of the core (VHDL ports). Table 125.Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - APBI * Input APB slave input signals - APBO * Output APB slave output signals - UARTI RXD Input UART receiver data - CTSN Input UART clear-to-send Low EXTCLK Input Use as alternative UART clock - RTSN Output UART request-to-send Low TXD Output UART transmit data - SCALER Output UART scaler value - UARTO TXEN Output Output enable for transmitter High FLOW Output Unused - RXEN Output Receiver enable High * see GRLIB IP Library User’s Manual 17.12 Signal definitions and reset values The signals and their reset values are described in table 126. Table 126.Signal definitions and reset values Signal name Type Function Active Reset value txd[] Output UART transmit data line - Logical 1 rtsn[] Output Ready To Send Low Logical 1 rxd[] Input UART receive data line - - ctsn[] Input Clear To Send Low - GRIP, Apr 2018, Version 2018.1 126 www.cobham.com/gaisler GRLIB IP Core 17.13 Timing The timing waveforms and timing parameters are shown in figure 27 and are defined in table 127. clk txd[], rtsn[] tAPBUART0 rxd[], ctsn[] tAPBUART1 tAPBUART0 tAPBUART2 Figure 27. Timing waveforms Table 127.Timing parameters Name Parameter Reference edge Min Max Unit tAPBUART0 clock to output delay rising clk edge TBD TBD ns tAPBUART1 input to clock hold rising clk edge - - ns tAPBUART2 input to clock setup rising clk edge - - ns Note: The ctsn[] and rxd[] inputs are re-synchronized internally. These signals do not have to meet any setup or hold requirements. 17.14 Library dependencies Table 128 shows libraries that should be used when instantiating the core. Table 128.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals APB signal definitions GAISLER UART Signals, component Signal and component declaration 17.15 Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.uart.all; entity apbuart_ex is port ( clk : in std_ulogic; rstn : in std_ulogic; -- UART signals rxd : in std_ulogic; txd : out std_ulogic ); end; architecture rtl of apbuart_ex is GRIP, Apr 2018, Version 2018.1 127 www.cobham.com/gaisler GRLIB IP Core -- APB signals signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); -- UART signals signal uarti : uart_in_type; signal uarto : uart_out_type; begin -- AMBA Components are instantiated here ... -- APB UART uart0 : apbuart generic map (pindex => 1, paddr => 1, pirq => 2, console => 1, fifosize => 1) port map (rstn, clk, apbi, apbo(1), uarti, uarto); -- UART input data uarti.rxd <= rxd; -- APB UART inputs not used in this configuration uarti.ctsn <= ’0’; uarti.extclk <= ’0’; -- connect APB UART output to entity output signal txd <= uarto.txd; end; GRIP, Apr 2018, Version 2018.1 128 www.cobham.com/gaisler GRLIB IP Core 18 APBVGA - VGA controller with APB interface 18.1 Introduction The APBVGA core is a text-only video controller with a resolution of 640x480 pixels, creating a display of 80x37 characters. The controller consists of a video signal generator, a 4 Kbyte text buffer, and a ROM for character pixel information. The video controller is controlled through an APB interface. A block diagram for the data path is shown in figure 28. Character ROM Video Generator Video memory HSYNC VSYNC COMP_SYNC BLANK RED[7:0] GREEN[7:0] BLUE[7:0] APB Figure 28. APBVGA block diagram 18.2 Operation The video timing of APBVGA is fixed to generate a 640x480 display with 60 Hz refresh rate. The text font is encoded using 8x13 pixels. The display is created by scanning a segment of 2960 characters of the 4 Kbyte text buffer, rasterizing the characters using the character ROM, and sending the pixel data to an external video DAC using three 8-bit color channels. The required pixel clock is 25.175 MHz, which should be provided on the VGACLK input. Writing to the video memory is made through the VGA data register. Bits [7:0] contains the character to be written, while bits [19:8] defines the text buffer address. Foreground and background colours are set through the background and foreground registers. These 24 bits corresponds to the three pixel colors, RED, GREEN and BLUE. The eight most significant bits defines the red intensity, the next eight bits defines the green intensity and the eight least significant bits defines the blue intensity. Maximum intensity for a color is received when all eight bits are set and minimum intensity when none of the bits are set. Changing the foreground color results in that all characters change their color, it is not possible to just change the color of one character. In addition to the color channels, the video controller generates HSYNC, VSYNC, CSYNC and BLANK. Togetherm the signals are suitable to drive an external video DAC such as ADV7125 or similar. APBVGA implements hardware scrolling to minimize processor overhead. The controller monitors maintains a reference pointer containing the buffer address of the first character on the top-most line. When the text buffer is written with an address larger than the reference pointer + 2960, the pointer is incremented with 80. The 4 Kbyte text buffer is sufficient to buffer 51 lines of 80 characters. To simplify hardware design, the last 16 bytes (4080 - 4095) should not be written. When address 4079 has been written, the software driver should wrap to address 0. Sofware scrolling can be implemented by only using the first 2960 address in the text buffer, thereby never activating the hardware scolling mechanism. GRIP, Apr 2018, Version 2018.1 129 www.cobham.com/gaisler GRLIB IP Core 18.3 Registers The APB VGA is controlled through three registers mapped into APB address space. Table 129.APB VGA registers APB address offset Register 0x0 VGA Data register (write-only, reads will return 0x00000000). 0x4 VGA Background color (write-only, reads will return 0x00000000). 0x8 VGA Foreground color (write-only, reads will return 0x00000000). 18.3.1 VGA Data Register Table 130. 0x00 - DATA - VGA data register 31 20 19 8 RESERVED 7 ADDRESS 0 DATA 0 0 0 r w w 19: 8 Video memory address (write access) 7: 0 Video memory data (write access) 18.3.2 VGA Background Color Table 131. 0x04 - BGCOL - VGA background register 31 24 23 RESERVED 16 15 8 7 0 RED GREEN BLUE w w w 0 r 23: 16 Video background color red. 15: 8 Video background color green. 7: 0 Video background color blue. 18.3.3 VGA Foreground Color Table 132. 0x00 - FGCOL - VGA foreground register 31 24 23 RESERVED 16 15 8 7 0 RED GREEN BLUE w w w 0 r 18.4 23: 16 Video foreground color red. 15: 8 Video foreground color green. 7: 0 Video foreground color blue. Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x061. For a description of vendor and device identifiers see GRLIB IP Library User’s Manual. GRIP, Apr 2018, Version 2018.1 130 www.cobham.com/gaisler GRLIB IP Core 18.5 Implementation 18.5.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. 18.6 Configuration options Table 133 shows the configuration options of the core (VHDL generics). Table 133.Configuration options 18.7 Generic Function Allowed range Default memtech Technology to implement on-chip RAM 0 - NTECH 2 pindex APB slave index 0 - NAPBSLV-1 0 paddr ADDR field of the APB BAR. 0 - 16#FFF# 0 pmask MASK field of the APB BAR. 0 - 16#FFF# 16#FFF# Signal descriptions Table 134 shows the interface signals of the core (VHDL ports). Table 134.Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - VGACLK N/A Input VGA Clock - APBI * Input APB slave input signals - APBO * Output APB slave output signals - HSYNC Output VGAO Horizontal synchronization High VSYNC Vertical synchronization High COMP_SYNC Composite synchronization Low BLANK Blanking Low VIDEO_OUT_R[7:0] Video out, color red - VIDEO_OUT_G[7:0] Video out, color green - VIDEO_OUT_B[7:0] Video out, color blue - BITDEPTH[1:0] Constant High - * see GRLIB IP Library User’s Manual 18.8 Library dependencies Table 135 shows libraries used when instantiating the core (VHDL libraries). Table 135.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals APB signal definitions GAISLER MISC Signals, component VGA signal and component declaration GRIP, Apr 2018, Version 2018.1 131 www.cobham.com/gaisler GRLIB IP Core 18.9 Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.misc.all; . . architecture rtl of apbuart_ex is signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal vgao : apbvga_out_type; begin -- AMBA Components are instantiated here ... -- APB VGA vga0 : apbvga generic map (memtech => 2, pindex => 6, paddr => 6) port map (rstn, clk, vgaclk, apbi, apbo(6), vgao); end; GRIP, Apr 2018, Version 2018.1 132 www.cobham.com/gaisler GRLIB IP Core 19 CAN_OC - GRLIB wrapper for OpenCores CAN Interface core 19.1 Overview CAN_OC is GRLIB wrapper for the CAN core from Opencores. It provides a bridge between AMBA AHB and the CAN Core registers. The AHB slave interface is mapped in the AHB I/O space using the GRLIB plug&play functionality. The CAN core interrupt is routed to the AHB interrupt bus, and the interrupt number is selected through the irq generic. The FIFO RAM in the CAN core is implemented using the GRLIB parametrizable SYNCRAM_2P memories, assuring portability to all supported technologies. This CAN interface implements the CAN 20.A and 2.0B protocols. It is based on the Philips SJA1000 and has a compatible register map with a few exceptions. CAN_OC Wrapper CAN_TXO CAN Core Syncram_2p CAN_RXI AHB slave interface IRQ AMBA AHB Figure 29. Block diagram 19.2 Opencores CAN controller overview This CAN controller is based on the Philips SJA1000 and has a compatible register map with a few exceptions. It also supports both BasicCAN (PCA82C200 like) and PeliCAN mode. In PeliCAN mode the extended features of CAN 2.0B is supported. The mode of operation is chosen through the Clock Divider register. This document will list the registers and their functionality. The Philips SJA1000 data sheet can be used as a reference if something needs clarification. See also the Design considerations chapter for differences between this core and the SJA1000. The register map and functionality is different between the two modes of operation. First the BasicCAN mode will be described followed by PeliCAN. Common registers (clock divisor and bus timing) are described in a separate chapter. The register map also differs depending on whether the core is in operating mode or in reset mode. When reset the core starts in reset mode awaiting configuration. Operating mode is entered by clearing the reset request bit in the command register. To re-enter reset mode set this bit high again. 19.3 AHB interface All registers are one byte wide and the addresses specified in this document are byte addresses. Byte reads and writes should be used when interfacing with this core. The read byte is duplicated on all byte lanes of the AHB bus. The wrapper is big endian so the core expects the MSB at the lowest address. The bit numbering in this document uses bit 7 as MSB and bit 0 as LSB. The core is designed for big-endian systems. GRIP, Apr 2018, Version 2018.1 133 www.cobham.com/gaisler GRLIB IP Core 19.4 BasicCAN mode 19.4.1 BasicCAN register map Table 136.BasicCAN address allocation Address Operating mode Reset mode Read Write Read Write 0 Control Control Control Control 1 (0xFF) Command (0xFF) Command 2 Status - Status - 3 Interrupt - Interrupt - 4 (0xFF) - Acceptance code Acceptance code 5 (0xFF) - Acceptance mask Acceptance mask 6 (0xFF) - Bus timing 0 Bus timing 0 7 (0xFF) - Bus timing 1 Bus timing 1 8 (0x00) - (0x00) - 9 (0x00) - (0x00) - 10 TX id1 TX id1 (0xFF) - 11 TX id2, rtr, dlc TX id2, rtr, dlc (0xFF) - 12 TX data byte 1 TX data byte 1 (0xFF) - 13 TX data byte 2 TX data byte 2 (0xFF) - 14 TX data byte 3 TX data byte 3 (0xFF) - 15 TX data byte 4 TX data byte 4 (0xFF) - 16 TX data byte 5 TX data byte 5 (0xFF) - 17 TX data byte 6 TX data byte 6 (0xFF) - 18 TX data byte 7 TX data byte 7 (0xFF) - 19 TX data byte 8 TX data byte 8 (0xFF) - 20 RX id1 - RX id1 - 21 RX id2, rtr, dlc - RX id2, rtr, dlc - 22 RX data byte 1 - RX data byte 1 - 23 RX data byte 2 - RX data byte 2 - 24 RX data byte 3 - RX data byte 3 - 25 RX data byte 4 - RX data byte 4 - 26 RX data byte 5 - RX data byte 5 - 27 RX data byte 6 - RX data byte 6 - 28 RX data byte 7 - RX data byte 7 - 29 RX data byte 8 - RX data byte 8 - 30 (0x00) - (0x00) - 31 Clock divider Clock divider Clock divider Clock divider GRIP, Apr 2018, Version 2018.1 134 www.cobham.com/gaisler GRLIB IP Core 19.4.2 Control register The control register contains interrupt enable bits as well as the reset request bit. Table 137.Bit interpretation of control register (CR) (address 0) Bit Name Description CR.7 - reserved CR.6 - reserved CR.5 - reserved (reads as 1) CR.4 Overrun Interrupt Enable 1 - enabled, 0 - disabled CR.3 Error Interrupt Enable 1 - enabled, 0 - disabled CR.2 Transmit Interrupt Enable 1 - enabled, 0 - disabled CR.1 Receive Interrupt Enable 1 - enabled, 0 - disabled CR.0 Reset request Writing 1 to this bit aborts any ongoing transfer and enters reset mode. Writing 0 returns to operating mode. 19.4.3 Command register Writing a one to the corresponding bit in this register initiates an action supported by the core. Table 138.Bit interpretation of command register (CMR) (address 1) Bit Name Description CMR.7 - reserved CMR.6 - reserved CMR.5 - reserved CMR.4 - not used (go to sleep in SJA1000 core) CMR.3 Clear data overrun Clear the data overrun status bit CMR.2 Release receive buffer Free the current receive buffer for new reception CMR.1 Abort transmission Aborts a not yet started transmission. CMR.0 Transmission request Starts the transfer of the message in the TX buffer A transmission is started by writing 1 to CMR.0. It can only be aborted by writing 1 to CMR.1 and only if the transfer has not yet started. If the transmission has started it will not be aborted when setting CMR.1 but it will not be retransmitted if an error occurs. Giving the Release receive buffer command should be done after reading the contents of the receive buffer in order to release this memory. If there is another message waiting in the FIFO a new receive interrupt will be generated (if enabled) and the receive buffer status bit will be set again. To clear the Data overrun status bit CMR.3 must be written with 1. GRIP, Apr 2018, Version 2018.1 135 www.cobham.com/gaisler GRLIB IP Core 19.4.4 Status register The status register is read only and reflects the current status of the core. Table 139.Bit interpretation of status register (SR) (address 2) Bit Name Description SR.7 Bus status 1 when the core is in bus-off and not involved in bus activities SR.6 Error status At least one of the error counters have reached or exceeded the CPU warning limit (96). SR.5 Transmit status 1 when transmitting a message SR.4 Receive status 1 when receiving a message SR.3 Transmission complete 1 indicates the last message was successfully transferred. SR.2 Transmit buffer status 1 means CPU can write into the transmit buffer SR.1 Data overrun status 1 if a message was lost because no space in fifo. SR.0 Receive buffer status 1 if messages available in the receive fifo. Receive buffer status is cleared when the Release receive buffer command is given and set high if there are more messages available in the fifo. The data overrun status signals that a message which was accepted could not be placed in the fifo because not enough space left. NOTE: This bit differs from the SJA1000 behavior and is set first when the fifo has been read out. When the transmit buffer status is high the transmit buffer is available to be written into by the CPU. During an on-going transmission the buffer is locked and this bit is 0. The transmission complete bit is set to 0 when a transmission request has been issued and will not be set to 1 again until a message has successfully been transmitted. 19.4.5 Interrupt register The interrupt register signals to CPU what caused the interrupt. The interrupt bits are only set if the corresponding interrupt enable bit is set in the control register. Table 140.Bit interpretation of interrupt register (IR) (address 3) Bit Name Description IR.7 - reserved (reads as 1) IR.6 - reserved (reads as 1) IR.5 - reserved (reads as 1) IR.4 - not used (wake-up interrupt of SJA1000) IR.3 Data overrun interrupt Set when SR.1 goes from 0 to 1. IR.2 Error interrupt Set when the error status or bus status are changed. IR.1 Transmit interrupt Set when the transmit buffer is released (status bit 0->1) IR.0 Receive interrupt This bit is set while there are more messages in the fifo. This register is reset on read with the exception of IR.0. Note that this differs from the SJA1000 behavior where all bits are reset on read in BasicCAN mode. This core resets the receive interrupt bit when the release receive buffer command is given (like in PeliCAN mode). Also note that bit IR.5 through IR.7 reads as 1 but IR.4 is 0. GRIP, Apr 2018, Version 2018.1 136 www.cobham.com/gaisler GRLIB IP Core 19.4.6 Transmit buffer The table below shows the layout of the transmit buffer. In BasicCAN only standard frame messages can be transmitted and received (EFF messages on the bus are ignored). Table 141.Transmit buffer layout Addr Name Bits 7 6 5 4 3 2 1 0 ID byte 1 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3 11 ID byte 2 ID.2 ID.1 ID.0 RTR DLC.3 DLC.2 DLC.1 DLC.0 12 TX data 1 TX byte 1 13 TX data 2 TX byte 2 14 TX data 3 TX byte 3 15 TX data 4 TX byte 4 16 TX data 5 TX byte 5 17 TX data 6 TX byte 6 18 TX data 7 TX byte 7 19 TX data 8 TX byte 8 10 If the RTR bit is set no data bytes will be sent but DLC is still part of the frame and must be specified according to the requested frame. Note that it is possible to specify a DLC larger than 8 bytes but should not be done for compatibility reasons. If DLC > 8 still only 8 bytes can be sent. 19.4.7 Receive buffer The receive buffer on address 20 through 29 is the visible part of the 64 byte RX FIFO. Its layout is identical to that of the transmit buffer. 19.4.8 Acceptance filter Messages can be filtered based on their identifiers using the acceptance code and acceptance mask registers. The top 8 bits of the 11 bit identifier are compared with the acceptance code register only comparing the bits set to zero in the acceptance mask register. If a match is detected the message is stored to the fifo. GRIP, Apr 2018, Version 2018.1 137 www.cobham.com/gaisler GRLIB IP Core 19.5 PeliCAN mode 19.5.1 PeliCAN register map Table 142.PeliCAN address allocation Operating mode Reset mode # Read Write Read Write 0 Mode Mode Mode Mode 1 (0x00) Command (0x00) Command 2 Status - Status - 3 Interrupt - Interrupt - 4 Interrupt enable Interrupt enable Interrupt enable Interrupt enable 5 reserved (0x00) - reserved (0x00) - 6 Bus timing 0 - Bus timing 0 Bus timing 0 7 Bus timing 1 - Bus timing 1 Bus timing 1 8 (0x00) - (0x00) - 9 (0x00) - (0x00) - 10 reserved (0x00) - reserved (0x00) 11 Arbitration lost capture - Arbitration lost capture - 12 Error code capture - Error code capture - 13 Error warning limit - Error warning limit Error warning limit 14 RX error counter - RX error counter RX error counter 15 TX error counter - TX error counter TX error counter 16 RX FI SFF RX FI EFF TX FI SFF TX FI EFF Acceptance code 0 Acceptance code 0 17 RX ID 1 RX ID 1 TX ID 1 TX ID 1 Acceptance code 1 Acceptance code 1 18 RX ID 2 RX ID 2 TX ID 2 TX ID 2 Acceptance code 2 Acceptance code 2 19 RX data 1 RX ID 3 TX data 1 TX ID 3 Acceptance code 3 Acceptance code 3 20 RX data 2 RX ID 4 TX data 2 TX ID 4 Acceptance mask 0 Acceptance mask 0 21 RX data 3 RX data 1 TX data 3 TX data 1 Acceptance mask 1 Acceptance mask 1 22 RX data 4 RX data 2 TX data 4 TX data 2 Acceptance mask 2 Acceptance mask 2 23 RX data 5 RX data 3 TX data 5 TX data 3 Acceptance mask 3 Acceptance mask 3 24 RX data 6 RX data 4 TX data 6 TX data 4 reserved (0x00) - 25 RX data 7 RX data 5 TX data 7 TX data 5 reserved (0x00) - 26 RX data 8 RX data 6 TX data 8 TX data 6 reserved (0x00) - 27 FIFO RX data 7 - TX data 7 reserved (0x00) - 28 FIFO RX data 8 - TX data 8 reserved (0x00) - 29 RX message counter - RX msg counter - 30 (0x00) - (0x00) - 31 Clock divider Clock divider Clock divider Clock divider The transmit and receive buffers have different layout depending on if standard frame format (SFF) or extended frame format (EFF) is to be transmitted/received. See the specific section below. GRIP, Apr 2018, Version 2018.1 138 www.cobham.com/gaisler GRLIB IP Core 19.5.2 Mode register Table 143.Bit interpretation of mode register (MOD) (address 0) Bit Name Description MOD.7 - reserved MOD.6 - reserved MOD.5 - reserved MOD.4 - not used (sleep mode in SJA1000) MOD.3 Acceptance filter mode 1 - single filter mode, 0 - dual filter mode MOD.2 Self test mode If set the controller is in self test mode MOD.1 Listen only mode If set the controller is in listen only mode MOD.0 Reset mode Writing 1 to this bit aborts any ongoing transfer and enters reset mode. Writing 0 returns to operating mode Writing to MOD.1-3 can only be done when reset mode has been entered previously. In Listen only mode the core will not send any acknowledgements. Note that unlike the SJA1000 the Opencores core does not become error passive and active error frames are still sent! When in Self test mode the core can complete a successful transmission without getting an acknowledgement if given the Self reception request command. Note that the core must still be connected to a real bus, it does not do an internal loopback. 19.5.3 Command register Writing a one to the corresponding bit in this register initiates an action supported by the core. Table 144.Bit interpretation of command register (CMR) (address 1) Bit Name Description CMR.7 - reserved CMR.6 - reserved CMR.5 - reserved CMR.4 Self reception request Transmits and simultaneously receives a message CMR.3 Clear data overrun Clears the data overrun status bit CMR.2 Release receive buffer Free the current receive buffer for new reception CMR.1 Abort transmission Aborts a not yet started transmission. CMR.0 Transmission request Starts the transfer of the message in the TX buffer A transmission is started by writing 1 to CMR.0. It can only be aborted by writing 1 to CMR.1 and only if the transfer has not yet started. Setting CMR.0 and CMR.1 simultaneously will result in a so called single shot transfer, i.e. the core will not try to retransmit the message if not successful the first time. Giving the Release receive buffer command should be done after reading the contents of the receive buffer in order to release this memory. If there is another message waiting in the FIFO a new receive interrupt will be generated (if enabled) and the receive buffer status bit will be set again. The Self reception request bit together with the self test mode makes it possible to do a self test of the core without any other cores on the bus. A message will simultaneously be transmitted and received and both receive and transmit interrupt will be generated. GRIP, Apr 2018, Version 2018.1 139 www.cobham.com/gaisler GRLIB IP Core 19.5.4 Status register The status register is read only and reflects the current status of the core. Table 145.Bit interpretation of command register (SR) (address 2) Bit Name Description SR.7 Bus status 1 when the core is in bus-off and not involved in bus activities SR.6 Error status At least one of the error counters have reached or exceeded the error warning limit. SR.5 Transmit status 1 when transmitting a message SR.4 Receive status 1 when receiving a message SR.3 Transmission complete 1 indicates the last message was successfully transferred. SR.2 Transmit buffer status 1 means CPU can write into the transmit buffer SR.1 Data overrun status 1 if a message was lost because no space in fifo. SR.0 Receive buffer status 1 if messages available in the receive fifo. Receive buffer status is cleared when there are no more messages in the fifo. The data overrun status signals that a message which was accepted could not be placed in the fifo because not enough space left. NOTE: This bit differs from the SJA1000 behavior and is set first when the fifo has been read out. When the transmit buffer status is high the transmit buffer is available to be written into by the CPU. During an on-going transmission the buffer is locked and this bit is 0. The transmission complete bit is set to 0 when a transmission request or self reception request has been issued and will not be set to 1 again until a message has successfully been transmitted. 19.5.5 Interrupt register The interrupt register signals to CPU what caused the interrupt. The interrupt bits are only set if the corresponding interrupt enable bit is set in the interrupt enable register. Table 146.Bit interpretation of interrupt register (IR) (address 3) Bit Name Description IR.7 Bus error interrupt Set if an error on the bus has been detected IR.6 Arbitration lost interrupt Set when the core has lost arbitration IR.5 Error passive interrupt Set when the core goes between error active and error passive IR.4 - not used (wake-up interrupt of SJA1000) IR.3 Data overrun interrupt Set when data overrun status bit is set IR.2 Error warning interrupt Set on every change of the error status or bus status IR.1 Transmit interrupt Set when the transmit buffer is released IR.0 Receive interrupt Set while the fifo is not empty. This register is reset on read with the exception of IR.0 which is reset when the fifo has been emptied. GRIP, Apr 2018, Version 2018.1 140 www.cobham.com/gaisler GRLIB IP Core 19.5.6 Interrupt enable register In the interrupt enable register the separate interrupt sources can be enabled/disabled. If enabled the corresponding bit in the interrupt register can be set and an interrupt generated. Table 147.Bit interpretation of interrupt enable register (IER) (address 4) Bit Name Description IR.7 Bus error interrupt 1 - enabled, 0 - disabled IR.6 Arbitration lost interrupt 1 - enabled, 0 - disabled IR.5 Error passive interrupt 1 - enabled, 0 - disabled IR.4 - not used (wake-up interrupt of SJA1000) IR.3 Data overrun interrupt 1 - enabled, 0 - disabled IR.2 Error warning interrupt 1 - enabled, 0 - disabled. IR.1 Transmit interrupt 1 - enabled, 0 - disabled IR.0 Receive interrupt 1 - enabled, 0 - disabled 19.5.7 Arbitration lost capture register Table 148.Bit interpretation of arbitration lost capture register (ALC) (address 11) Bit Name Description ALC.7-5 - reserved ALC.4-0 Bit number Bit where arbitration is lost When the core loses arbitration the bit position of the bit stream processor is captured into arbitration lost capture register. The register will not change content again until read out. 19.5.8 Error code capture register Table 149.Bit interpretation of error code capture register (ECC) (address 12) Bit Name Description ECC.7-6 Error code Error code number ECC.5 Direction 1 - Reception, 0 - transmission error ECC.4-0 Segment Where in the frame the error occurred When a bus error occurs the error code capture register is set according to what kind of error occurred, if it was while transmitting or receiving and where in the frame it happened. As with the ALC register the ECC register will not change value until it has been read out. The table below shows how to interpret bit 7-6 of ECC. Table 150.Error code interpretation ECC.7-6 Description 0 Bit error 1 Form error 2 Stuff error 3 Other GRIP, Apr 2018, Version 2018.1 141 www.cobham.com/gaisler GRLIB IP Core Bit 4 downto 0 of the ECC register is interpreted as below Table 151.Bit interpretation of ECC.4-0 ECC.4-0 Description 0x03 Start of frame 0x02 ID.28 - ID.21 0x06 ID.20 - ID.18 0x04 Bit SRTR 0x05 Bit IDE 0x07 ID.17 - ID.13 0x0F ID.12 - ID.5 0x0E ID.4 - ID.0 0x0C Bit RTR 0x0D Reserved bit 1 0x09 Reserved bit 0 0x0B Data length code 0x0A Data field 0x08 CRC sequence 0x18 CRC delimiter 0x19 Acknowledge slot 0x1B Acknowledge delimiter 0x1A End of frame 0x12 Intermission 0x11 Active error flag 0x16 Passive error flag 0x13 Tolerate dominant bits 0x17 Error delimiter 0x1C Overload flag 19.5.9 Error warning limit register This registers allows for setting the CPU error warning limit. It defaults to 96. Note that this register is only writable in reset mode. 19.5.10 RX error counter register (address 14) This register shows the value of the rx error counter. It is writable in reset mode. A bus-off event resets this counter to 0. 19.5.11 TX error counter register (address 15) This register shows the value of the tx error counter. It is writable in reset mode. If a bus-off event occurs this register is initialized as to count down the protocol defined 128 occurrences of the bus-free signal and the status of the bus-off recovery can be read out from this register. The CPU can force a bus-off by writing 255 to this register. Note that unlike the SJA1000 this core will signal bus-off immediately and not first when entering operating mode. The bus-off recovery sequence starts when entering operating mode after writing 255 to this register in reset mode. GRIP, Apr 2018, Version 2018.1 142 www.cobham.com/gaisler GRLIB IP Core 19.5.12 Transmit buffer The transmit buffer is write-only and mapped on address 16 to 28. Reading of this area is mapped to the receive buffer described in the next section. The layout of the transmit buffer depends on whether a standard frame (SFF) or an extended frame (EFF) is to be sent as seen below. Table 152. # Write (SFF) Write(EFF) 16 TX frame information TX frame information 17 TX ID 1 TX ID 1 18 TX ID 2 TX ID 2 19 TX data 1 TX ID 3 20 TX data 2 TX ID 4 21 TX data 3 TX data 1 22 TX data 4 TX data 2 23 TX data 5 TX data 3 24 TX data 6 TX data 4 25 TX data 7 TX data 5 26 TX data 8 TX data 6 27 - TX data 7 28 - TX data 8 TX frame information (this field has the same layout for both SFF and EFF frames) Table 153.TX frame information address 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FF RTR - - DLC.3 DLC.2 DLC.1 DLC.0 Bit 7 Bit 6 Bit 5:4 Bit 3:0 - FF selects the frame format, i.e. whether this is to be interpreted as an extended or standard frame. 1 = EFF, 0 = SFF. RTR should be set to 1 for an remote transmission request frame. are don’t care. DLC specifies the Data Length Code and should be a value between 0 and 8. If a value greater than 8 is used 8 bytes will be transmitted. TX identifier 1 (this field is the same for both SFF and EFF frames) Table 154.TX identifier 1 address 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 Bit 7:0 - The top eight bits of the identifier. TX identifier 2, SFF frame Table 155.TX identifier 2 address 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.20 ID.19 ID.18 - - - - - Bit 7:5 - Bottom three bits of an SFF identifier. Bit 4:0 - Don’t care. GRIP, Apr 2018, Version 2018.1 143 www.cobham.com/gaisler GRLIB IP Core TX identifier 2, EFF frame Table 156.TX identifier 2 address 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.20 ID.19 ID.18 ID.17 ID.16 ID.15 ID.14 ID.13 Bit 7:0 - Bit 20 downto 13 of 29 bit EFF identifier. TX identifier 3, EFF frame Table 157.TX identifier 3 address 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.12 ID.11 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 Bit 7:0 - Bit 12 downto 5 of 29 bit EFF identifier. TX identifier 4, EFF frame Table 158.TX identifier 4 address 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.4 ID.3 ID.2 ID.1 ID.0 - - - Bit 7:3 - Bit 4 downto 0 of 29 bit EFF identifier Bit 2:0 - Don’t care Data field For SFF frames the data field is located at address 19 to 26 and for EFF frames at 21 to 28. The data is transmitted starting from the MSB at the lowest address. GRIP, Apr 2018, Version 2018.1 144 www.cobham.com/gaisler GRLIB IP Core 19.5.13 Receive buffer Table 159. # Read (SFF) Read (EFF) 16 RX frame information RX frame information 17 RX ID 1 RX ID 1 18 RX ID 2 RX ID 2 19 RX data 1 RX ID 3 20 RX data 2 RX ID 4 21 RX data 3 RX data 1 22 RX data 4 RX data 2 23 RX data 5 RX data 3 24 RX data 6 RX data 4 25 RX data 7 RX data 5 26 RX data 8 RX data 6 27 RX FI of next message in fifo RX data 7 28 RX ID1 of next message in fifo RX data 8 RX frame information (this field has the same layout for both SFF and EFF frames) Table 160.RX frame information address 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FF RTR 0 0 DLC.3 DLC.2 DLC.1 DLC.0 Bit 7 Bit 6 Bit 5:4 Bit 3:0 - Frame format of received message. 1 = EFF, 0 = SFF. 1 if RTR frame. Always 0. DLC specifies the Data Length Code. RX identifier 1(this field is the same for both SFF and EFF frames) Table 161.RX identifier 1 address 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 Bit 7:0 - The top eight bits of the identifier. RX identifier 2, SFF frame Table 162.RX identifier 2 address 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.20 ID.19 ID.18 RTR 0 0 0 0 Bit 7:5 - Bottom three bits of an SFF identifier. Bit 4 - 1 if RTR frame. Bit 3:0 - Always 0. GRIP, Apr 2018, Version 2018.1 145 www.cobham.com/gaisler GRLIB IP Core RX identifier 2, EFF frame Table 163.RX identifier 2 address 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.20 ID.19 ID.18 ID.17 ID.16 ID.15 ID.14 ID.13 Bit 7:0 - Bit 20 downto 13 of 29 bit EFF identifier. RX identifier 3, EFF frame Table 164.RX identifier 3 address 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.12 ID.11 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 Bit 7:0 - Bit 12 downto 5 of 29 bit EFF identifier. RX identifier 4, EFF frame Table 165.RX identifier 4 address 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.4 ID.3 ID.2 ID.1 ID.0 RTR 0 0 Bit 7:3 - Bit 4 downto 0 of 29 bit EFF identifier Bit 21 if RTR frame Bit 1:0 - Don’t care Data field For received SFF frames the data field is located at address 19 to 26 and for EFF frames at 21 to 28. 19.5.14 Acceptance filter The acceptance filter can be used to filter out messages not meeting certain demands. If a message is filtered out it will not be put into the receive fifo and the CPU will not have to deal with it. There are two different filtering modes, single and dual filter. Which one is used is controlled by bit 3 in the mode register. In single filter mode only one 4 byte filter is used. In dual filter two smaller filters are used and if either of these signals a match the message is accepted. Each filter consists of two parts the acceptance code and the acceptance mask. The code registers are used for specifying the pattern to match and the mask registers specify don’t care bits. In total eight registers are used for the acceptance filter as shown in the table below. Note that they are only read/writable in reset mode. GRIP, Apr 2018, Version 2018.1 146 www.cobham.com/gaisler GRLIB IP Core Table 166.Acceptance filter registers Address Description 16 Acceptance code 0 (ACR0) 17 Acceptance code 1 (ACR1) 18 Acceptance code 2 (ACR2) 19 Acceptance code 3 (ACR3) 20 Acceptance mask 0 (AMR0) 21 Acceptance mask 1 (AMR1) 22 Acceptance mask 2 (AMR2) 23 Acceptance mask 3 (AMR3)  Single filter mode, standard frame When receiving a standard frame in single filter mode the registers ACR0-3 are compared against the incoming message in the following way: ACR0.7-0 & ACR1.7-5 are compared to ID.28-18 ACR1.4 is compared to the RTR bit. ACR1.3-0 are unused. ACR2 & ACR3 are compared to data byte 1 & 2. The corresponding bits in the AMR registers selects if the results of the comparison doesn’t matter. A set bit in the mask register means don’t care. Single filter mode, extended frame When receiving an extended frame in single filter mode the registers ACR0-3 are compared against the incoming message in the following way: ACR0.7-0 & ACR1.7-0 are compared to ID.28-13 ACR2.7-0 & ACR3.7-3 are compared to ID.12-0 ACR3.2 are compared to the RTR bit ACR3.1-0 are unused. The corresponding bits in the AMR registers selects if the results of the comparison doesn’t matter. A set bit in the mask register means don’t care.  Dual filter mode, standard frame When receiving a standard frame in dual filter mode the registers ACR0-3 are compared against the incoming message in the following way: Filter 1 ACR0.7-0 & ACR1.7-5 are compared to ID.28-18 ACR1.4 is compared to the RTR bit. ACR1.3-0 are compared against upper nibble of data byte 1 ACR3.3-0 are compared against lower nibble of data byte 1 Filter 2 ACR2.7-0 & ACR3.7-5 are compared to ID.28-18 ACR3.4 is compared to the RTR bit. The corresponding bits in the AMR registers selects if the results of the comparison doesn’t matter. A set bit in the mask register means don’t care. Dual filter mode, extended frame When receiving a standard frame in dual filter mode the registers ACR0-3 are compared against the incoming message in the following way: GRIP, Apr 2018, Version 2018.1 147 www.cobham.com/gaisler GRLIB IP Core Filter 1 ACR0.7-0 & ACR1.7-0 are compared to ID.28-13 Filter 2 ACR2.7-0 & ACR3.7-0 are compared to ID.28-13 The corresponding bits in the AMR registers selects if the results of the comparison doesn’t matter. A set bit in the mask register means don’t care. 19.5.15 RX message counter The RX message counter register at address 29 holds the number of messages currently stored in the receive fifo. The top three bits are always 0. 19.6 Common registers There are three common registers with the same addresses and the same functionality in both BasiCAN and PeliCAN mode. These are the clock divider register and bus timing register 0 and 1. 19.6.1 Clock divider register The only real function of this register in the GRLIB version of the Opencores CAN is to choose between PeliCAN and BasiCAN. The clkout output of the Opencore CAN core is not connected and it is its frequency that can be controlled with this register. Table 167.Bit interpretation of clock divider register (CDR) (address 31) Bit Name Description CDR.7 CAN mode 1 - PeliCAN, 0 - BasiCAN CDR.6 - unused (cbp bit of SJA1000) CDR.5 - unused (rxinten bit of SJA1000) CDR.4 - reserved CDR.3 Clock off Disable the clkout output CDR.2-0 Clock divisor Frequency selector 19.6.2 Bus timing 0 Table 168.Bit interpretation of bus timing 0 register (BTR0) (address 6) Bit Name Description BTR0.7-6 SJW Synchronization jump width BTR0.5-0 BRP Baud rate prescaler The CAN core system clock is calculated as: tscl = 2*tclk*(BRP+1) where tclk is the system clock. The sync jump width defines how many clock cycles (tscl) a bit period may be adjusted with by one re-synchronization. GRIP, Apr 2018, Version 2018.1 148 www.cobham.com/gaisler GRLIB IP Core 19.6.3 Bus timing 1 Table 169.Bit interpretation of bus timing 1 register (BTR1) (address 7) Bit Name Description BTR1.7 SAM 1 - The bus is sampled three times, 0 - single sample point BTR1.6-4 TSEG2 Time segment 2 BTR1.3-0 TSEG1 Time segment 1 The CAN bus bit period is determined by the CAN system clock and time segment 1 and 2 as shown in the equations below: ttseg1 = tscl * ( TSEG1+1) ttseg2 = tscl * ( TSEG2+1) tbit = ttseg1 + ttseg2 + tscl The additional tscl term comes from the initial sync segment. Sampling is done between TSEG1 and TSEG2 in the bit period. 19.7 Design considerations This section lists known differences between this CAN controller and SJA1000 on which is it based: • All bits related to sleep mode are unavailable • Output control and test registers do not exist (reads 0x00) • Clock divisor register bit 6 (CBP) and 5 (RXINTEN) are not implemented • Overrun irq and status not set until fifo is read out BasicCAN specific differences: • The receive irq bit is not reset on read, works like in PeliCAN mode • Bit CR.6 always reads 0 and is not a flip flop with no effect as in SJA1000 PeliCAN specific differences: 19.8 • Writing 256 to tx error counter gives immediate bus-off when still in reset mode • Read Buffer Start Address register does not exist • Addresses above 31 are not implemented (i.e. the internal RAM/FIFO access) • The core transmits active error frames in Listen only mode Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x019. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 19.9 Implementation 19.9.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). See the description of the syncrst VHDL generic for further information. GRIP, Apr 2018, Version 2018.1 149 www.cobham.com/gaisler GRLIB IP Core 19.10 Configuration options Table 170 shows the configuration options of the core (VHDL generics). Table 170.Configuration options Generic Function Allowed range Default slvndx AHB slave bus index 0 - NAHBSLV-1 0 ioaddr The AHB I/O area base address. Compared with bit 19-8 of the 32-bit AHB address. 0 - 16#FFF# 16#FFF# iomask The I/O area address mask. Sets the size of the I/O area and the start address together with ioaddr. 0 - 16#FFF# 16#FF0# irq Interrupt number 0 - NAHBIRQ-1 0 memtech Technology to implement on-chip RAM 0 0 - NTECH syncrst Reset implementation 0-2 0 0-1 0 0: Use asynchronous reset 1: Use synchronous reset, leave internal buffers without reset 2: Use synchronous reset, initialize internal buffers to zero at reset. ft Enable fault-tolerance 19.11 Signal descriptions Table 171 shows the interface signals of the core (VHDL ports). Table 171.Signal descriptions Signal name Field Type Function Active CLK Input AHB clock RESETN Input Reset Low - AHBSI * Input AMBA AHB slave inputs AHBSO * Input AMBA AHB slave outputs CAN_RXI Input CAN receiver input High CAN_TXO Output CAN transmitter output High MTESTI** MTESTO** MTESTCLK** FIFO Input Memory BIST input signal to fifo RAM - INFO Input Memory BIST input signal to info RAM - FIFO Output Memory BIST output signal from fifo RAM - INFO Output Memory BIST output signal from info RAM - N/A Input Memory BIST clock - *1) see AMBA specification ** not available in FPGA releases 19.12 Signal definitions and reset values The signals and their reset values are described in table 172. Table 172.Signal definitions and reset values Signal name Type Function Active Reset value cantx[] Output CAN transmit data Low Logical 1 canen[] Output CAN transmit enabel - Logical 0 canrx[] Input CAN receive data Low - GRIP, Apr 2018, Version 2018.1 150 www.cobham.com/gaisler GRLIB IP Core 19.13 Timing The timing waveforms and timing parameters are shown in figure 30 and are defined in table 173. clk tCAN_OC0 cantx[], canen[] tCAN_OC2 canrx[] tCAN_OC1 Figure 30. Timing waveforms Table 173.Timing parameters Name Parameter Reference edge Min Max Unit tCAN_OC0 clock to data output delay rising clk edge TBD TBD ns tCAN_OC1 data input to clock setup rising clk edge - - ns tCAN_OC2 data input from clock hold rising clk edge - - ns Note: The canrx[] input is re-synchronized internally. The signal does not have to meet any setup or hold requirements. 19.14 Library dependencies Table 174 shows libraries that should be used when instantiating the core. Table 174.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Types AMBA signal type definitions GAISLER CAN Component Component declaration 19.15 Component declaration library grlib; use grlib.amba.all; use gaisler.can.all; component can_oc generic ( slvndx : integer := 0; ioaddr : integer := 16#000#; iomask : integer := 16#FF0#; irq : integer := 0; memtech : integer := 0); port ( resetn : in std_logic; clk : in std_logic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; can_rxi : in std_logic; can_txo : out std_logic ); end component; GRIP, Apr 2018, Version 2018.1 151 www.cobham.com/gaisler GRLIB IP Core 20 CLKGEN - Clock generation 20.1 Overview The CLKGEN clock generator implements internal clock generation and buffering. 20.2 Technology specific clock generators 20.2.1 Overview The core is a wrapper that instantiates technology specific primitives depending on the value of the tech VHDL generic. Each supported technology has its own subsection below. Table 175 lists the subsection applicable for each technology setting. The table is arranged after the technology’s numerical value in GRLIB. The subsections are ordered in alphabetical order after technology vendor. Table 175.Overview of technology specific clock generator sections Technology Numerical value Comment Section inferred 0 Default when no technology specific generator is available. 20.2.2 virtex 1 virtex2 2 memvirage 3 axcel 4 20.2.3 proasic 5 20.2.3 20.2.12 20.2.13 No technology specific clock generator available. No technology specific clock generator available. 20.2.2 atc18s 6 altera 7 20.2.2 umc 8 rhumc 9 20.2.10 apa3 10 20.2.5 spartan3 11 20.2.11 ihp25 12 rhlib18t 13 virtex4 14 lattice 15 No technology specific clock generator available. 20.2.2 ut25 16 No technology specific clock generator available. 20.2.2 spartan3e 17 peregrine 18 No technology specific clock generator available. 20.2.2 memartisan 19 No technology specific clock generator available. 20.2.2 virtex5 20 custom1 21 No technology specific clock generator available. No technology specific clock generator available. 20.2.7 No technology specific clock generator available. No technology specific clock generator available. 20.2.2 20.2.2 20.2.9 20.2.13 20.2.11 20.2.14 20.2.2 ihp25rh 22 stratix1 23 20.2.7 stratix2 24 20.2.7 eclipse 25 No technology specific clock generator available. 20.2.2 20.2.2 stratix3 26 20.2.8 cyclone3 27 20.2.6 memvirage90 28 No technology specific clock generator available. 20.2.2 tsmc90 29 No technology specific clock generator available. 20.2.2 easic90 30 atc18rha 31 GRIP, Apr 2018, Version 2018.1 20.2.15 No technology specific clock generator available. 152 20.2.2 www.cobham.com/gaisler GRLIB IP Core Table 175.Overview of technology specific clock generator sections Technology Numerical value Comment Section smic013 32 No technology specific clock generator available. 20.2.2 tm65gpl 33 No technology specific clock generator available. 20.2.2 axdsp 34 20.2.3 spartan6 35 20.2.11 virtex6 36 20.2.14 actfus 37 20.2.17 stratix4 38 20.2.18 st65lp 39 No technology specific clock generator available. st65gp 40 No technology specific clock generator available. easic45 41 20.2.2 20.2.2 20.2.16 20.2.2 Generic technology This implementation is used when the clock generator does not support instantiation of technology specific primitives or when the inferred technology has been selected. This implementation connects the input clock, CLKIN or PCICLKIN depending on the pcien and pcisysclk VHDL generic, to the SDCLK, CLK1XU, and CLK outputs. The CLKN output is driven by the inverted input clock. The PCICLK output is directly driven by PCICLKIN. Both clock lock signals are always driven to ‘1’ and the CLK2X output is always driven to ‘0’. In simulation, CLK, CLKN and CLK1XU transitions are skewed 1 ns relative to the SDRAM clock output. 20.2.3 ProASIC Generics used in this technology: pcisysclk Instantiated technology primitives: None Signals not driven in this technology: clk4x, clk1xu, clk2xu, clkb, clkc This technology selection does not instantiate any technology specific primitives. The core’s clock output, CLK, is driven by the CLKIN or PCICLKIN input depending on the value of VHDL generics pcien and pcisysclk. The PCICLK is always directly connected to PCICLKIN. Outputs SDCLK, CLKN and CLK2X, are driven to ground. Both clock lock signals, CGO.CLKLOCK and CGO.PCILOCK, are always driven high. 20.2.4 Actel Axcelerator Generics used in this technology: pcisysclk, clk_mul, clk_div, pcien, freq Instantiated technology primitives: PLL Signals not driven in this technology: clk4x, clk1xu, clk2xu, clkb, clkc This technology selection has two modes. The first one is used if VHDL generics clk_mul and clk_div are equal and does not instantiate any technology specific primitives. The core’s clock output, CLK, is driven by the CLKIN or PCICLKIN input depending on the value of VHDL generics pcien and pcisysclk. The second mode is used if VHDL generics clk_mul and clk_div are different and instantiates a PLL. The core’s clock output CLK is either driven by the pciclkin input or the main output from the PLL depending on the values of VHDL generics pcien and pcisysclk. When the PLL drives the CLK output GRIP, Apr 2018, Version 2018.1 153 www.cobham.com/gaisler GRLIB IP Core the resulting frequency is the frequency of CLKIN multiplied by the VHDL generic clk_mul and divided by the VHDL generic clk_div. Clock buffers are not instantiated within the clock generator and has to be done externally. For both modes the following applies: The PCICLK is always directly connected to PCICLKIN. Outputs SDCLK, CLKN and CLK2X, are driven to ground. Both clock lock signals, CGO.CLKLOCK and CGO.PCILOCK, are always driven high. 20.2.5 Actel ProASIC3 Generics used in this technology: clk_mul, clk_div, clk_odiv, pcisysclk, pcien, freq, clkb_odiv, clkc_odiv Instantiated technology primitives: PLLINT, PLL Signals not driven in this technology: clkn, sdclk, clk2x, clk4x, clk1xu, clk2xu This technology instantiates a PLL and a PLLINT to generate the main clock. The instantiation of a PLLINT macro allows the PLL reference clock to be driven from an I/O that is routed through the regular FPGA routing fabric. Figure 31 shows the instantiated primitives, the PLL EXTFB input is not shown and the EXTFB port on the instantiated component is always tied to ground. The figure shows which of the core’s output ports that are driven by the PLL. The PCICLOCK will directly connected to PCICLKIN if VHDL generic pcien is non-zero, while CGO.PCILOCK is always driven high. The VHDL generics pcien and pcisysclk are used to select the reference clock. The values driven on the PLL inputs are listed in tables 176 and 177. PLL PLLINT Selected clock A Y CLKA POWERDOWN OADIV[4:0] OAMUX[2:0] DLYGLA[4:0] OBDIV[4:0] OBMUX[2:0] DLYYB[4:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYYC[4:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0] See tables for values GLA LOCK GLB YB GLC YC CLK CGO.CLKLOCK CLKB CLKC Figure 31. Actel ProASIC3 clock generation GRIP, Apr 2018, Version 2018.1 154 www.cobham.com/gaisler GRLIB IP Core Table 176.Constant input signals on Actel ProASIC3 PLL Signal name Value Comment OADIV[4:0] VHDL generic clk_odiv - 1 Output divider OAMUX[2:0] 0b100 Post-PLL MUXA DLYGLA[4:0] 0 Delay on Global A OBDIV[4:0] VHDL generic clkb_odiv - 1 when clkb_odiv > 0, otherwise 0 Output divider OBMUX[2:0] 0 when VHDL generic clkb_odiv = 0, otherwise 0b100 Post-PLL MUXB DLYYB[4:0] 0 Delay on YB DLYGLB[4:0] 0 Delay on Global B OCDIV[4:0] VHDL generic clkc_odiv - 1 when clkc_odiv > 0, otherwise 0 Output divider OCMUX[2:0] 0 when VHDL generic clkc_odiv = 0, otherwise 0b100 Post-PLL MUXC DLYYC[4:0] 0 Delay on YC DLYGLC[4:0] 0 Delay on Global C FINDIV[6:0] VHDL generic clk_div - 1 Input divider FBDIV[6:0] VHDL generic clk_mul - 1 Feedback divider FBDLY[4:0] 0 Feedback delay FBSEL[1:0] 0b01 2-bit PLL feedback MUX XDLYSEL 0 1-bit PLL feedback MUX VCOSEL[2:0] See table 177 below VCO gear control. Selects one of four frequency ranges. The PLL primitive has one parameter, VCOFREQUENCY, which is calculated with: freq  clkmul VCOFREQUENCY = ---------------------------------  1000 clkdiv The calculations are performed with integer precision. This value is also used to determine the value driven on PLL input VCOSEL[2:0]. Table 177 lists the signal value depending on the value of VCOFREQUENCY. Table 177.VCOSEL[2:0] on Actel ProASIC3 PLL Value of VCOFREQUENCY Value driven on VCOSEL[2:0] < 44 0b000 < 88 0b010 < 175 0b100 >= 175 0b110 GRIP, Apr 2018, Version 2018.1 155 www.cobham.com/gaisler GRLIB IP Core 20.2.6 Altera Cyclone III Generics used in this technology: clk_mul, clk_div, sdramen, pcien, pcisysclk, freq, clk2xen Instantiated technology primitives: ALTPLL Signals not driven in this technology: clk4x, clk1xu, clk2xu, clkb, clkc This technology instantiates an ALTPLL primitive to generate the required clocks, see figure 32. The ALTPLL attributes are listed in table 178. As can be seen in this table the attributes OPERATION_MODE and COMPENSATE_CLOCK depend on the VHDL generic sdramen. Table 178.Altera Cyclone III ALTPLL attributes Attribute name* Value with sdramen = 1 Value with sdramen = 0 INTENDED_DEVICE_FAMILY “Cyclone III” “Cyclone III” OPERATION_MODE “ZERO_DELAY_BUFFER” “NORMAL” COMPENSATE_CLOCK “CLK1” “clock0” INCLK0_INPUT_FREQUENCY 1000000000 / (VHDL generic freq) 1000000000 / (VHDL generic freq) WIDTH_CLOCK 5 5 CLK0_MULTIPLY_BY VHDL generic clk_mul VHDL generic clk_mul CLK0_DIVIDE_BY VHDL generic clk_div VHDL generic clk_div CLK1_MULTIPLY_BY VHDL generic clk_mul VHDL generic clk_mul CLK1_DIVIDE_BY VHDL generic clk_div VHDL generic clk_div CLK2_MULTIPLY_BY VHDL generic clk_mul * 2 VHDL generic clk_mul * 2 CLK2_DIVIDE_BY VHDL generic clk_div VHDL generic clk_div *Any attributes not listed are assumed to have their default value GND INCLK[1] CLKENA[5:0] See text INCLK[1:0] Selected clock ALTPLL CLK[5:0] LOCKED See text CGO.CLKLOCK INCLK[0] Figure 32. Altera Cyclone III ALTPLL The value driven on the ALTPLL clock enable signal is dependent on the VHDL generics clk2xen and sdramen, table 179 lists the effect of these generics. Table 179.Effect of VHDL generics clk2xen and sdramen on ALTPLL clock enable input Value of sdramen Value of clk2xen Value of CLKENA[5:0] 0 0 0b000001 0 1 0b000101 1 0 0b000011 1 1 0b000111 GRIP, Apr 2018, Version 2018.1 156 www.cobham.com/gaisler GRLIB IP Core Table 180 lists the connections of the core’s input and outputs to the ALTPLL ports. Table 180.Connections between core ports and ALTPLL ports Core signal Core direction ALTPLL signal CLKIN/PCICLKIN* Input INCLK[0] CLK Output CLK[0] CLKN Output CLK[0] (CLK[0] through an inverter) CLK2X Output CLK[2] SDCLK Output CLK[1] CGO.CLKLOCK Output LOCKED * Depending on VHDL generics PCIEN and PCISYSCLK, as described below. The clocks can be generated using either the CLKIN input or the PCICLKIN input. This is selected with the VHDL generics pcien and pcisysclk. If pcien is 0 or pcisysclk is 0 the input clock to the ALTPLL will be CLKIN. If pcien is non-zero and pcisysclk is 1 the input to the ALTPLL will be PCICLKIN. The PCICLK output will connected to the PCICLKIN input if VHDL generic pcien is non-zero. Otherwise the PCICLK output will be driven to ground. The CGO.PCILOCK signal is always driven high. 20.2.7 Altera Stratix 1/2 Generics used in this technology: clk_mul, clk_div, sdramen, pcien, pcisysclk, freq, clk2xen Instantiated technology primitives: ALTPLL Signals not driven in this technology: clk4x, clk1xu, clk2xu, clkb, clkc This technology instantiates an ALTPLL primitive to generate the required clocks, see figure 33. The ALTPLL attributes are listed in table 181. As can be seen in this table the OPERATION_MODE attribute depends on the VHDL generic sdramen. Table 181.Altera Stratix 1/2 ALTPLL attributes Attribute name* Value with sdramen = 1 Value with sdramen = 0 OPERATION_MODE “ZERO_DELAY_BUFFER” “NORMAL” INCLK0_INPUT_FREQUENCY 1000000000 / (VHDL generic freq) 1000000000 / (VHDL generic freq) WIDTH_CLOCK 6 6 CLK0_MULTIPLY_BY VHDL generic clk_mul VHDL generic clk_mul CLK0_DIVIDE_BY VHDL generic clk_div VHDL generic clk_div CLK1_MULTIPLY_BY VHDL generic clk_mul * 2 VHDL generic clk_mul * 2 CLK1_DIVIDE_BY VHDL generic clk_div VHDL generic clk_div EXTCLK0_MULTIPLY_BY VHDL generic clk_mul VHDL generic clk_mul EXTCLK0_DIVIDE_BY VHDL generic clk_div VHDL generic clk_div *Any attributes not listed are assumed to have their default value GND INCLK[1] See text CLKENA[5:0] INCLK[1:0] Selected clock INCLK[0] See text EXTCLKENA[3:0] ALTPLL CLK[5:0] See text LOCKED CGO.CLKLOCK EXTCLK[3:0] See text Figure 33. Altera Stratix 1/2 ALTPLL GRIP, Apr 2018, Version 2018.1 157 www.cobham.com/gaisler GRLIB IP Core The values driven on the ALTPLL clock enable signals are dependent on the VHDL generic clk2xen, table 182 lists the effect of clk2xen. Table 182.Effect of VHDL generic clk2xen on ALTPLL clock enable inputs Signal Value with clk2xen = 0 Value with clk2xen /= 0 CLKENA[5:0] 0b000001 0b000011 EXTCLKENA[3:0] 0b0001 0b0011 Table 183 lists the connections of the core’s input and outputs to the ALTPLL ports. Table 183.Connections between core ports and ALTPLL ports Core signal Core direction ALTPLL signal CLKIN/PCICLKIN* Input INCLK[0] CLK Output CLK[0] CLKN Output CLK[0] (CLK[0] through an inverter) CLK2X Output CLK[1] SDCLK Output EXTCLK[0] CGO.CLKLOCK Output LOCKED * Depending on VHDL generics PCIEN and PCISYSCLK, as described below. The clocks can be generated using either the CLKIN input or the PCICLKIN input. This is selected with the VHDL generics pcien and pcisysclk. If pcien is 0 or pcisysclk is 0 the input clock to the ALTPLL will be CLKIN. If pcien is non-zero and pcisysclk is 1 the input to the ALTPLL will be PCICLKIN. The PCICLK output will connected to the PCICLKIN input if VHDL generic pcien is non-zero. Otherwise the PCICLK output will be driven to ground. The CGO.PCILOCK signal is always driven high. 20.2.8 Altera Stratix 3 This technology is not fully supported at this time. 20.2.9 RHLIB18t Generics used in this technology: clk_mul, clk_div Instantiated technology primitives: lfdll_top Signals not driven in this technology: - Please contact Cobham Gaisler for information concerning the use of this clock generator. 20.2.10 RHUMC Generics used in this technology: None Instantiated technology primitives: pll_ip Signals not driven in this technology: - Please contact Cobham Gaisler for information concerning the use of this clock generator. GRIP, Apr 2018, Version 2018.1 158 www.cobham.com/gaisler GRLIB IP Core 20.2.11 Xilinx Spartan 3/3e/6 Generics used in this technology: clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel Instantiated technology primitives: BUFG, BUFMUX, DCM, BUFGDLL Signals not driven in this technology: clk4x, clkb, clkc The main clock is generated with a DCM which is instantiated with the attributes listed in table 184. The input clock source connected to the CLKIN input is either the core’s CLKIN input or the PCICLKIN input. This is selected with the VHDL generics pcien and pcisysclk. The main DCM’s connections is shown in figure 34. Table 184.Spartan 3/e DCM attributes Attribute name* Value CLKDV_DIVIDE 2.0 CLKFX_DIVIDE Determined by core’s VHDL generic clk_div CLKFX_MULTIPLY Determined by core’s VHDL generic clk_mul CLKIN_DIVIDE_BY_2 false CLKIN_PERIOD 10.0 CLKOUT_PHASE_SHIFT “NONE” CLK_FEEDBACK “2X” DESKEW_ADJUST “SYSTEM_SYNCHRONOUS” DFS_FREQUENCY_MODE “LOW” DLL_FREQUENCY_MODE “LOW” DSS_MODE “NONE” DUTY_CYCLE_CORRECTION true FACTORY_JF X”C080” PHASE_SHIFT 0 STARTUP_WAIT false *Any attributes not listed are assumed to have their default value DCM Selected input clock CGI.PLLRST CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST DSSEN PSINCDEC PSEN PSCLK BUFG CLK1XU BUFG CLK2XU BUFG LOCKED clk_i dll0lock STATUS[7:0] PSDONE Figure 34. Spartan 3/e generation of main clock If the VHDL generic clk2xen is non-zero the DCM shown in figure 35 is instantiated. The attributes of this DCM are the same as in table 184, except that the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes are both set to 2 and the CLK_FEEDBACK attribute is set to “1X”. The dll0lock signal is connected to the LOCKED output of the main clock DCM. When this signal is low all the bits in the GRIP, Apr 2018, Version 2018.1 159 www.cobham.com/gaisler GRLIB IP Core shift register connected to the CLK2X DCM’s RST input are set to ‘1’. When the dll0lock signal is asserted it will take four main clock cycles until the RST input is deasserted. Depending on the value of the clksel VHDL generic the core’s CLK2X output is either driven by a BUFG or a BUFGMUX. Figure 36 shows the two alternatives and how the CGI.CLKSEL(0) input is used to selected between the CLK0 and CLK2X output of the CLK2X DCM. DCM CLK dll0lock CLK GND CLKIN CLKFB CLK0 clk_o CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST SHIFTREG DSSEN PSINCDEC PSEN PSCLK BUFG LOCKED clk_p clk_n dll2xlock STATUS[7:0] PSDONE Figure 35. Spartan 3/e generation of CLK2X clock when VHDL generic clk2xen is non-zero CLK2X driver when VHDL generic clksel = 0 CLK2X driver when VHDL generic clksel /= 0 BUFGMUX clk_o I0 O clk_n I1 S BUFG CLK2X clk_n CLK2X CGI.CLKSEL(0) Figure 36. Spartan 3/e selection of CLK2X clock when VHDL generic clk2xen is non-zero The value of the clk2xen VHDL generic also decides which output that drives the core’s CLK output. If the VHDL generic is non-zero the CLK output is driven by the clk_p signal originating from the CLK2X DCM. Otherwise the CLK output is connected to the clk_i signal originating from the main clock DCM. The core’s CLKN output is driven by the selected signal through an inverter. Figure 37 illustrates the connections. CLK/CLKN drivers when VHDL generic clk2xen = 0 CLK/CLKN drivers when VHDL generic clk2xen /= 0 clk_i CLK clk_p CLK clk_i CLKN clk_p CLKN Figure 37. Spartan 3/e clock generator outputs CLK and CLKN If the VHDL generic clk2xen is zero the dll0lock signal from the main clock DCM is either connected to the SDRAM DCM, described below, or if the SDRAM DCM is non-existent, to the core’s CGO.CLKLOCK output. This setting also leads to the core’s CLK2X output being driven by the main clock DCM’s CLK2X output via a BUFG, please see figure 38. GRIP, Apr 2018, Version 2018.1 160 www.cobham.com/gaisler GRLIB IP Core BUFG clk_x CLK2X Figure 38. Spartan 3/e generation of CLK2X clock when VHDL generic clk2xen is zero If the SDRAM clock is enabled, via the sdramen VHDL generic, and the clock generator is configured to use clock feedback the DCM shown in figure 39 is instantiated. This DCM has the same attributes as the CLK2X DCM. The input to the SDRAM DCM input clock is determined via the clk2xen VHDL generic. If the VHDL generic is set to 0 the input is the main CLK, if the generic is set to 1 the input is the clk_p out of the CLK2X DCM shown in figure 36. If the clk2xen VHDL generic is set to 2 the clock input to the SDRAM DCM depends on the clksel VHDL generic. The input in this last case is the CLK2X output shown in figure 38. If the CLK2X DCM has been instantiated the SDRAM DCM RST input depends on the LOCKED output of the CLK2X DCM. If the CLK2X DCM has not been instantiated the SDRAM DCM RST input depends on the LOCKED output from the main clock DCM. The applicable LOCKED signal is utilized to keep the SDRAM DCM in reset until its input clock has been stabilized. This is done with a shift register with the same method used for the CLK2X DCM RST. DCM Selected SDRAM input clock CGI.PLLREF CLKIN CLKFB RST dll0lock or dll2xlock CLK GND SHIFTREG DSSEN PSINCDEC PSEN PSCLK CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED SDCLK CGO.CLKLOCK STATUS[7:0] PSDONE Figure 39. Spartan 3/e generation of SDRAM clock If the SDRAM clock is disabled (sdramen VHDL generic set to 0) or the core has been configured not to use clock feedback (noclockfb VHDL generic set to 1) the driver of the core’s SDCLK output is determined by the value of the clk2xen VHDL generic. If the clk2xen VHDL generic is set to 2, the SDRAM clock output is the same as the CLK2X output shown in figure 36, in other words it also depends on the clksel VHDL generic. If the clk2xen VHDL generic has any other value the SDCLK output is the same as the core’s CLK output. When the sdramen VHDL generic is set to 0 the core’s CGO.CLKLOCK output is connected to the CLK2X DCM’s LOCKED output, if the DCM exists, otherwise the CGO.CLKLOCK output is connected to the main clock DCM’s LOCKED output. If PCI clock generation is enabled via the pcien VHDL generic the core instantiates either a BUFG or a BUFGDLL as depicted in figure 40 below. Note that the PCI clock must be enabled if the main clock is to be driven by the PCICLKIN input. If the PCI clock is disabled the PCICLK output is driven to zero. The CGO.PCILOCK output is always driven high in all configurations. GRIP, Apr 2018, Version 2018.1 161 www.cobham.com/gaisler GRLIB IP Core PCIDLL VHDL generic set to 0 PCIDLL VHDL generic set to 1 BUFGDLL BUFG PCICLKIN PCICLKIN PCICLK PCICLK Figure 40. Spartan 3/e PCI clock generation 20.2.12 Xilinx Virtex Generics used in this technology: clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk Instantiated technology primitives: BUFG, BUFGDLL, CLKDLL Signals not driven in this technology: clk4x, clk1xu, clk2xu, clkb, clkc The main clock is generated with the help of a CLKDLL. Figure 41 below shows how the CLKDLL primitive is connected. The input clock source is either the core’s CLKIN input or the PCICLKIN input. This is selected with the VHDL generics pcien and pcisysclk. The figure shows three potential drivers of the BUFG driving the output clock CLK, the driver is selected via the VHDL generics clk_mul and clk_div. If clk_mul/clk_div is equal to 2 the CLK2X output is selected, if clk_div/clk_mul equals 2 the CLKDV output is selected, otherwise the CLK0 output drives the BUFG. The inverted main clock output, CLKN, is the BUFG output connected via an inverter. The figure shows a dashed line connecting the CLKDLL’s LOCKED output to the core output CGO.CLKLOCK. The driver of the CGO.CLKLOCK output depends on the instantiation of a CLKDLL for the SDRAM clock. See description of the SDRAM clock below. CLKDLL Selected input clock CGI.PLLRST CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV LOCKED RST BUFG BUFG CLK Source selected via VHDL generics CGO.CLKLOCK Figure 41. Virtex generation of main clock If the SDRAM clock is enabled, via the sdramen VHDL generic, and the clock generator is configured to use clock feedback, VHDL generic noclkfb set to 0, a CLKDLL is instantiated as depicted in figure 42. Note how the CLKDLL’s RST input is connected via a shift register clocked by the main clock. The shift register is loaded with all ‘1’ when the LOCKED signal of the main clock CLKDLL is low. When the LOCKED signal from the main clock CLKDLL is asserted the SDRAM CLKDLL’s RST input will be deasserted after four main clock cycles. For all other configurations the SDRAM clock is driven by the main clock and the CGO.CLKLOCK signal is driven by the main clock CLKDLL’s LOCKED output. The SDRAM CLKDLL must be present if the core’s CLK2X output shall be driven. GRIP, Apr 2018, Version 2018.1 162 www.cobham.com/gaisler GRLIB IP Core CLKDLL CLKIN CLKFB CLK CGI.PLLREF CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV LOCKED Main CLKDLL LOCK CLK GND SHIFTREG RST SDCLK CLK2X CGO.CLKLOCK Figure 42. Virtex generation of SDRAM clock with feedback clock enabled If PCI clock generation is enabled via the pcien VHDL generic the core instantiates either a BUFG or a BUFGDLL as depicted in figure 43 below. Note that the PCI clock must be enabled if the main clock is to be driven by the PCICLKIN input. If the PCI clock is disabled the PCICLK output is driven to zero. The CGO.PCILOCK output is always driven high in all configurations. PCIDLL VHDL generic set to 0 PCIDLL VHDL generic set to 1 BUFGDLL BUFG PCICLKIN PCICLKIN PCICLK PCICLK Figure 43. Virtex PCI clock generation 20.2.13 Xilinx Virtex 2/4 Generics used in this technology: clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel Instantiated technology primitives: BUFG, BUFMUX, DCM, BUFGDLL Signals not driven in this technology: clk4x, clkb, clkc The main clock is generated with a DCM which is instantiated with the attributes listed in table 185. The input clock source connected to the CLKIN input is either the core’s CLKIN input or the PCICLKIN input. This is selected with the VHDL generics pcien and pcisysclk. The main DCM’s connections is shown in figure 44. GRIP, Apr 2018, Version 2018.1 163 www.cobham.com/gaisler GRLIB IP Core Table 185.Virtex 2/4 DCM attributes Attribute name* Value CLKDV_DIVIDE 2.0 CLKFX_DIVIDE Determined by core’s VHDL generic clk_div CLKFX_MULTIPLY Determined by core’s VHDL generic clk_mul CLKIN_DIVIDE_BY_2 false CLKIN_PERIOD 10.0 CLKOUT_PHASE_SHIFT “NONE” CLK_FEEDBACK “1X” DESKEW_ADJUST “SYSTEM_SYNCHRONOUS” DFS_FREQUENCY_MODE “LOW” DLL_FREQUENCY_MODE “LOW” DSS_MODE “NONE” DUTY_CYCLE_CORRECTION true FACTORY_JF X”C080” PHASE_SHIFT 0 STARTUP_WAIT false *Any attributes not listed are assumed to have their default value DCM Selected input clock CGI.PLLRST CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST DSSEN PSINCDEC PSEN PSCLK BUFG CLK1XU clk_x CLK2XU BUFG clk_i BUFG LOCKED CLKN dll0lock STATUS[7:0] PSDONE Figure 44. Virtex 2/4 generation of main clock If the VHDL generic clk2xen is non-zero the DCM shown in figure 45 is instantiated. The attributes of this DCM are the same as in table 185, except that the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes are both set to 2. The dll0lock signal is connected to the LOCKED output of the main clock DCM. When this signal is low all the bits in the shift register connected to the CLK2X DCM’s RST input are set to ‘1’. When the dll0lock signal is asserted it will take four main clock cycles until the RST input is deasserted. Depending on the value of the clksel VHDL generic the core’s CLK2X output is either driven by a BUFG or a BUFGMUX. Figure 46 shows the two alternatives and how the CGI.CLKSEL(0) input is used to selected between the CLK0 and CLK2X output of the CLK2X DCM. GRIP, Apr 2018, Version 2018.1 164 www.cobham.com/gaisler GRLIB IP Core DCM CLK dll0lock CLK GND SHIFTREG CLKIN CLKFB CLK0 clk_o CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST DSSEN PSINCDEC PSEN PSCLK BUFG LOCKED clk_p clk_n dll2xlock STATUS[7:0] PSDONE Figure 45. Virtex 2/4 generation of CLK2X clock when VHDL generic clk2xen is non-zero The value of the clk2xen VHDL generic also decides which output that drives the core’s CLK output. If the VHDL generic is non-zero the CLK output is driven by the clk_p signal originating from the CLK2X DCM. Otherwise the CLK output is connected to the clk_i signal originating from the main clock DCM. Note that the CLKN output always originates from the main clock DCM, as shown in figure 44. CLK2X driver when VHDL generic clksel = 0 CLK2X driver when VHDL generic clksel /= 0 BUFGMUX clk_o I0 O clk_n I1 S BUFG CLK2X clk_n CLK2X CGI.CLKSEL(0) Figure 46. Virtex 2/4 selection of CLK2X clock when VHDL generic clk2xen is non-zero If the VHDL generic clk2xen is zero the dll0lock signal from the main clock DCM is either connected to the SDRAM DCM, described below, or if the SDRAM DCM is non-existent, to the core’s CGO.CLKLOCK output. This setting also leads to the core’s CLK2X output being driven by the main clock DCM’s CLK2X output via a BUFG, please see figure 47. BUFG clk_x CLK2X Figure 47. Virtex 2/4 generation of CLK2X clock when VHDL generic clk2xen is zero If the SDRAM clock is enabled, via the sdramen VHDL generic, and the clock generator is configured to use clock feedback the DCM shown in figure 48. The input to the SDRAM DCM input clock is determined via the clk2xen VHDL generic. If the VHDL generic is set to 0 the input is the main CLK, if the generic is set to 1 the input is the clk_p out of the CLK2X DCM shown in figure 45. If the clk2xen VHDL generic is set to 2 the clock input to the SDRAM DCM depends on the clksel VHDL generic. The input in this last case is the CLK2X output shown in figure 46. If the CLK2X DCM has been instantiated the SDRAM DCM RST input depends on the LOCKED output of the CLK2X DCM. If the CLK2X DCM has not been instantiated the SDRAM DCM RST input depends on the LOCKED output from the main clock DCM. The applicable LOCKED signal is GRIP, Apr 2018, Version 2018.1 165 www.cobham.com/gaisler GRLIB IP Core utilized to keep the SDRAM DCM in reset until its input clock has been stabilized. This is done with a shift register with the same method used for the CLK2X DCM RST. DCM CLKIN CLKFB Selected SDRAM input clock CGI.PLLREF CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST dll0lock or dll2xlock CLK GND SHIFTREG DSSEN PSINCDEC PSEN PSCLK LOCKED SDCLK CGO.CLKLOCK STATUS[7:0] PSDONE Figure 48. Virtex 2/4 generation of SDRAM clock If the SDRAM clock is disabled (sdramen VHDL generic set to 0) or the core has been configured not to use clock feedback (noclockfb VHDL generic set to 1) the driver of the core’s SDCLK output is determined by the value of the clk2xen VHDL generic. If the clk2xen VHDL generic is set to 2, the SDRAM clock output is the same as the CLK2X output shown in figure 46, in other words it also depends on the clksel VHDL generic. If the clk2xen VHDL generic has any other value the SDCLK output is the same as the core’s CLK output. When the sdramen VHDL generic is set to 0 the core’s CGO.CLKLOCK output is connected to the CLK2X DCM’s LOCKED output, if the DCM exists, otherwise the CGO.CLKLOCK output is connected to the main clock DCM’s LOCKED output. If PCI clock generation is enabled via the pcien VHDL generic the core instantiates either a BUFG or a BUFGDLL as depicted in figure 49 below. Note that the PCI clock must be enabled if the main clock is to be driven by the PCICLKIN input. If the PCI clock is disabled the PCICLK output is driven to zero. The CGO.PCILOCK output is always driven high in all configurations. PCIDLL VHDL generic set to 0 PCIDLL VHDL generic set to 1 BUFGDLL BUFG PCICLKIN PCICLKIN PCICLK PCICLK Figure 49. Virtex 2/4 PCI clock generation 20.2.14 Xilinx Virtex 5/6 Generics used in this technology: clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel Instantiated technology primitives: BUFG, BUFMUX, DCM, BUFGDLL Signals not driven in this technology: clk4x, clkb, clkc The main clock is generated with a DCM which is instantiated with the attributes listed in table 186. The input clock source connected to the CLKIN input is either the core’s CLKIN input or the PCI- GRIP, Apr 2018, Version 2018.1 166 www.cobham.com/gaisler GRLIB IP Core CLKIN input. This is selected with the VHDL generics pcien and pcisysclk. The main DCM’s connections is shown in figure 50. Table 186.Virtex 5 DCM attributes Attribute name* Value CLKDV_DIVIDE 2.0 CLKFX_DIVIDE Determined by core’s VHDL generic clk_div CLKFX_MULTIPLY Determined by core’s VHDL generic clk_mul CLKIN_DIVIDE_BY_2 false CLKIN_PERIOD 10.0 CLKOUT_PHASE_SHIFT “NONE” CLK_FEEDBACK “1X” DESKEW_ADJUST “SYSTEM_SYNCHRONOUS” DFS_FREQUENCY_MODE “LOW” DLL_FREQUENCY_MODE “LOW” DSS_MODE “NONE” DUTY_CYCLE_CORRECTION true FACTORY_JF X”C080” PHASE_SHIFT 0 STARTUP_WAIT false *Any attributes not listed are assumed to have their default value DCM Selected input clock CGI.PLLRST CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST DSSEN PSINCDEC PSEN PSCLK BUFG LOCKED CLK1XU CLK2XU BUFG clk_i BUFG CLKN dll0lock STATUS[7:0] PSDONE Figure 50. Virtex 5 generation of main clock If the VHDL generic clk2xen is non-zero the DCM shown in figure 51 is instantiated. The attributes of this DCM are the same as in table 186, except that the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes are both set to 2. The dll0lock signal is connected to the LOCKED output of the main clock DCM. When this signal is low all the bits in the shift register connected to the CLK2X DCM’s RST input are set to ‘1’. When the dll0lock signal is asserted it will take four main clock cycles until the RST input is deasserted. Depending on the value of the clksel VHDL generic the core’s CLK2X output is either driven by a BUFG or a BUFGMUX. Figure 52 shows the two alternatives and how the CGI.CLKSEL(0) input is used to selected between the CLK0 and CLK2X output of the CLK2X DCM. GRIP, Apr 2018, Version 2018.1 167 www.cobham.com/gaisler GRLIB IP Core DCM CLK dll0lock CLK GND SHIFTREG CLKIN CLKFB CLK0 clk_o CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST DSSEN PSINCDEC PSEN PSCLK LOCKED BUFG clk_p clk_n dll2xlock STATUS[7:0] PSDONE Figure 51. Virtex 5 generation of CLK2X clock when VHDL generic clk2xen is non-zero The value of the clk2xen VHDL generic also decides which output that drives the core’s CLK output. If the VHDL generic is non-zero the CLK output is driven by the clk_p signal originating from the CLK2X DCM. Otherwise the CLK output is connected to the clk_i signal originating from the main clock DCM. Note that the CLKN output always originates from the main clock DCM, as shown in figure 50. CLK2X driver when VHDL generic clksel = 0 CLK2X driver when VHDL generic clksel /= 0 BUFGMUX clk_o I0 O clk_n I1 S BUFG CLK2X clk_n CLK2X CGI.CLKSEL(0) Figure 52. Virtex 5 selection of CLK2X clock when VHDL generic clk2xen is non-zero If the VHDL generic clk2xen is zero the dll0lock signal from the main clock DCM is either connected to the SDRAM DCM, described below, or if the SDRAM DCM is non-existent, to the core’s CGO.CLKLOCK output. This setting also leads to the core’s CLK2X output being driven directly by the main clock DCM’s CLK2X output. If the SDRAM clock is enabled, via the sdramen VHDL generic, and the clock generator is configured to use clock feedback the DCM shown in figure 53. This DCM has the same attributes as the main clock DCM described in table 186, with the exceptions that CLKFX_MULTIPLY and CLKFX_DIVIDE are both set to 2 and DESKEW_ADJUST is set to “SOURCE_SYNCHRONOUS”. The input to the SDRAM DCM input clock is determined via the clk2xen VHDL generic. If the VHDL generic is set to 0 the input is the main CLK, if the generic is set to 1 the input is the clk_p out of the CLK2X DCM shown in figure 45. If the clk2xen VHDL generic is set to 2 the clock input to the SDRAM DCM depends on the clksel VHDL generic. The input in this last case is the CLK2X output shown in figure 52. If the CLK2X DCM has been instantiated the SDRAM DCM RST input depends on the LOCKED output of the CLK2X DCM. If the CLK2X DCM has not been instantiated the SDRAM DCM RST input depends on the LOCKED output from the main clock DCM. The applicable LOCKED signal is utilized to keep the SDRAM DCM in reset until its input clock has been stabilized. This is done with a shift register with the same method used for the CLK2X DCM RST. GRIP, Apr 2018, Version 2018.1 168 www.cobham.com/gaisler GRLIB IP Core DCM CLKIN CLKFB Selected SDRAM input clock CGI.PLLREF CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 RST dll0lock or dll2xlock CLK GND SHIFTREG DSSEN PSINCDEC PSEN PSCLK BUFG LOCKED SDCLK CGO.CLKLOCK STATUS[7:0] PSDONE Figure 53. Virtex 5 generation of SDRAM clock If the SDRAM clock is disabled (sdramen VHDL generic set to 0) or the core has been configured not to use clock feedback (noclockfb VHDL generic set to 1) the driver of the core’s SDCLK output is determined by the value of the clk2xen VHDL generic. If the clk2xen VHDL generic is set to 2, the SDRAM clock output is the same as the CLK2X output shown in figure 52, in other words it also depends on the clksel VHDL generic. If the clk2xen VHDL generic has any other value the SDCLK output is the same as the core’s CLK output. When the sdramen VHDL generic is set to 0 the core’s CGO.CLKLOCK output is connected to the CLK2X DCM’s LOCKED output, if the DCM exists, otherwise the CGO.CLKLOCK output is connected to the main clock DCM’s LOCKED output. If PCI clock generation is enabled via the pcien VHDL generic the core instantiates either a BUFG or a BUFGDLL as depicted in figure 54 below. Note that the PCI clock must be enabled if the main clock is to be driven by the PCICLKIN input. If the PCI clock is disabled the PCICLK output is driven to zero. The CGO.PCILOCK output is always driven high in all configurations. PCIDLL VHDL generic set to 0 PCIDLL VHDL generic set to 1 BUFGDLL BUFG PCICLKIN PCICLK PCICLKIN PCICLK Figure 54. Virtex 5 PCI clock generation 20.2.15 eASIC90 (Nextreme) Generics used in this technology: clk_mul, clk_div, freq, pcisysclk, pcien Instantiated technology primitives: eclkgen Signals not driven in this technology: sdclk, pciclk, clk1xu, clk2xu, clkb, clkc Please contact Cobham Gaisler for information concerning the use of this clock generator. GRIP, Apr 2018, Version 2018.1 169 www.cobham.com/gaisler GRLIB IP Core 20.2.16 eASIC45 (Nextreme2) Generics used in this technology: clk_mul, clk_div, freq, pcisysclk, pcien, sdramen, clk2xen Instantiated technology primitives: eclkgen Signals not driven in this technology: clk1xu, clk2xu, clkb, clkc An example instantiating eASIC’s clock generator wrapper that generates clk, clkn and clk2x is provided. Note that the example does not instantiate buffers on the clock outputs. Please contact Cobham Gaisler for information concerning the use of this clock generator. 20.2.17 Actel Fusion Generics used in this technology: clk_mul, clk_div, clk_odiv, pcisysclk, pcien, freq, clkb_odiv, clkc_odiv Instantiated technology primitives: PLLINT, PLL Signals not driven in this technology: clkn, sdclk, clk2x, clk4x, clk1xu, clk2xu This technology instantiates a PLL and a PLLINT to generate the main clock. The instantiation of a PLLINT macro allows the PLL reference clock to be driven from an I/O that is routed through the regular FPGA routing fabric. Figure 55 shows the instantiated primitives, the PLL EXTFB input is not shown and the EXTFB port on the instantiated component is always tied to ground. The OADIVRST port on the PLL is driven by CGI.PLLRST. The figure shows which of the core’s output ports that are driven by the PLL. The PCICLOCK will directly connected to PCICLKIN if VHDL generic pcien is non-zero, while CGO.PCILOCK is always driven high. The VHDL generics pcien and pcisysclk are used to select the reference clock. The values driven on the PLL inputs are listed in tables 187 and 188. PLL PLLINT Selected clock A Y CLKA POWERDOWN OADIVHALF OADIV[4:0] OAMUX[2:0] DLYGLA[4:0] OBDIV[4:0] OBMUX[2:0] DLYYB[4:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYYC[4:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0] See tables for values GLA LOCK GLB YB GLC YC CLK CGO.CLKLOCK CLKB CLKC Figure 55. Actel Fusion clock generation Table 187.Constant input signals on Actel Fusion PLL Signal name Value Comment OADIVHALF 0 Division by half OADIV[4:0] VHDL generic clk_odiv - 1 Output divider OAMUX[2:0] 0b100 Post-PLL MUXA DLYGLA[4:0] 0 Delay on Global A OBDIV[4:0] VHDL generic clkb_odiv - 1 when clkb_odiv > 0, otherwise 0 Output divider OBMUX[2:0] 0 when VHDL generic clkb_odiv = 0, otherwise 0b100 Post-PLL MUXB GRIP, Apr 2018, Version 2018.1 170 www.cobham.com/gaisler GRLIB IP Core Table 187.Constant input signals on Actel Fusion PLL Signal name Value Comment DLYYB[4:0] 0 Delay on YB DLYGLB[4:0] 0 Delay on Global B OCDIV[4:0] VHDL generic clkc_odiv - 1 when clkc_odiv > 0, otherwise 0 Output divider OCMUX[2:0] 0 when VHDL generic clkc_odiv = 0, otherwise 0b100 Post-PLL MUXC DLYYC[4:0] 0 Delay on YC DLYGLC[4:0] 0 Delay on Global C FINDIV[6:0] VHDL generic clk_div - 1 Input divider FBDIV[6:0] VHDL generic clk_mul - 1 Feedback divider FBDLY[4:0] 0 Feedback delay FBSEL[1:0] 0b01 2-bit PLL feedback MUX XDLYSEL 0 1-bit PLL feedback MUX VCOSEL[2:0] See table 177 below VCO gear control. Selects one of four frequency ranges. The PLL primitive has one parameter, VCOFREQUENCY, which is calculated with: freq  clkmul VCOFREQUENCY = ---------------------------------  1000 clkdiv The calculations are performed with integer precision. This value is also used to determine the value driven on PLL input VCOSEL[2:0]. Table 177 lists the signal value depending on the value of VCOFREQUENCY. Table 188.VCOSEL[2:0] on Actel Fusion PLL Value of VCOFREQUENCY Value driven on VCOSEL[2:0] < 44 0b000 < 88 0b010 < 175 0b100 >= 175 0b110 20.2.18 Altera Stratix 4 This technology is not fully supported at this time. GRIP, Apr 2018, Version 2018.1 171 www.cobham.com/gaisler GRLIB IP Core 20.3 Configuration options Table 189 shows the configuration options of the core (VHDL generics). Table 189.Configuration options Generic name Function Allowed range Default tech Target technology 0 - NTECH inferred clk_mul Clock multiplier, used in clock scaling. Not all techbologies support clock scaling. 1 clk_div Clock divisor, used in clock scaling. Not all technologies support clock scaling. 1 sdramen When this generic is set to 1 the core will generate a clock on the SDCLK. Not supported by all technologies. See technology specific description. 0 noclkfb When this generic is set to 0 the core will use the CGI.PLLREF input as feedback clock for some technologies. See technology specific description. 1 pcien When this generic is set to 1 the PCI clock is activated. Otherwise the PCICLKIN input is typically unused. See technology specific descriptions. 0 pcidll When this generic is set to 1, a DLL will be instantiated for the PCI input clock for some technologies. See the technology specific descriptions. 0 pcisysclk When this generic is set to 1 the clock generator will use the pciclkin input as the main clock reference. This also requires generic pcien to be set to 1. 0 freq Clock frequency in kHz 25000 clk2xen Enables 2x clock output. Not available in all technolgies and may have additional options. See technology specific description. 0 clksel Enable clock select. Not available in all technologies. 0 clk_odiv ProASIC3/Fusion output divider for GLA. Only used in ProASIC3/Fusion technology. 1 - 32 1 clkb_odiv ProASIC3/Fusion output divider for GLB. Only used in ProASIC3/Fusion technology. Set this value to 0 to disable generation of GLB. 0 - 32 0 clkc_odiv ProASIC3/Fusion output divider for GLC. Only used in ProASIC3/Fusion technology. Set this value to 0 to disable generation of GLC. 0 - 32 0 GRIP, Apr 2018, Version 2018.1 172 www.cobham.com/gaisler GRLIB IP Core 20.4 Signal descriptions Table 190 shows the interface signals of the core (VHDL ports). Table 190.Signal descriptions Signal name Field Type Function Active CLKIN N/A Input Reference clock input - PCICLKIN N/A Input PCI clock input CLK N/A Output Main clock - CLKN N/A Output Inverted main clock - CLK2X N/A Output 2x clock - SDCLK N/A Output SDRAM clock - PCICLK N/A Output PCI clock - CGI PLLREF Input Optional reference for PLL - PLLRST Input Optional reset for PLL PLLCTRL Input Optional control for PLL CLKSEL Input Optional clock select CLKLOCK Output Lock signal for main clock PCILOCK Output Lock signal for PCI clock CLK4X N/A Output 4x clock CLK1XU N/A Output Unscaled 1x clock CLK2XU N/A Output Unscaled 2x clock CLKB N/A Output GLB output from ProASIC3/Fusion PLL CLKC N/A Output GLC output from ProASIC3/Fusion PLL CGO 20.5 - Signal definitions and reset values The signals and their reset values are described in table 191. Table 191.Signal definitions and reset values 20.6 Signal name Type Function Active Reset value clk Input System clock Rising edge - Timing The timing waveforms and timing parameters are shown in figure 56 and are defined in table 192. tCLKGEN0 clk Figure 56. Timing waveforms Table 192.Timing parameters Name Parameter Reference edge Min Max Unit tCLKGEN0 clock period - TBD - ns GRIP, Apr 2018, Version 2018.1 173 www.cobham.com/gaisler GRLIB IP Core 20.7 Library dependencies Table 193 shows the libraries used when instantiating the core (VHDL libraries). Table 193.Library dependencies 20.8 Library Package Imported unit(s) Description TECHMAP GENCOMP Component, signals Core signal definitions TECHMAP ALLCLKGEN Component Technology specific CLKGEN components Instantiation This example shows how the core can be instantiated together with the GRLIB reset generator. library ieee; use ieee.std_logic_1164.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.misc.all; entity clkgen_ex is port ( resetn : in std_ulogic; clk : in std_ulogic; -- 50 MHz main clock pllref : in std_ulogic ); end; architecture example of clkgen_ex is signal lclk, clkm, rstn, rstraw, sdclkl, clk50: std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; begin cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref); clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ) port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50); sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl); resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst); rst0 : rstgen -- reset generator port map (rst, clkm, cgo.clklock, rstn, rstraw); end; GRIP, Apr 2018, Version 2018.1 174 www.cobham.com/gaisler GRLIB IP Core 21 DDRSPA - 16-, 32- and 64-bit DDR266 Controller 21.1 Overview DDRSPA is a DDR266 SDRAM controller with AMBA AHB back-end. The controller can interface two 16-, 32- or 64-bit DDR266 memory banks to a 32-bit AHB bus. The controller acts as a slave on the AHB bus where it occupies a configurable amount of address space for DDR SDRAM access. The DDR controller is programmed by writing to a configuration register mapped located in AHB I/O address space. Internally, DDRSPA consists of a ABH/DDR controller and a technology specific DDR PHY. For currently supported technologies for the PHY see section 21.6.2. The modular design of DDRSPA allows to add support for other target technologies in a simple manner. DDRSPA AHB DDR266 CONTROLLER AHB SLAVE CLK SDCSN[1:0] SDRASN SDCASN SDWEN SDDQM[15:0] SDCKE DDR CLOCK 16/32/64-bit DDR Memory CLK CSN RAS CAS WE DQM CKE ADDRESS[16:2] D[127:0] CLK CLKN CSN DDR RAS PHY CAS WE DQM CKE ADDR[13:0] BA[1:0] DQ[63:0] CLK CLKN CSN RAS CAS WE DQM CKE ADDR[13:0] BA[1:0] DQ[63:0] Figure 57. DDRSPA Memory controller conected to AMBA bus and DDR SDRAM 21.2 Operation 21.2.1 General Double data-rate SDRAM (DDR RAM) access is supported to two banks of 16-, 32- or 64-bit DDR266 compatible memory devices. The controller supports 64M, 128M, 256M, 512M and 1G devices with 9- 12 column-address bits, up to 14 row-address bits, and 4 internal banks. The size of each of each chip select can be programmed in binary steps between 8 Mbyte and 1024 Mbyte. The DDR data width is set by the ddrbits VHDL generic, and will affect the width of DM, DQS and DQ signals. The DDR data width does not change the behavior of the AHB interface, except for data latency. When the VHDL generic mobile is set to a value not equal to 0, the controller supports mobile DDR SDRAM (LPDDR). 21.2.2 Read cycles An AHB read access to the controller will cause a corresponding access to the external DDR RAM. The read cycle is started by performing an ACTIVATE command to the desired bank and row, followed by a READ command. CAS latency of 2 (CL=2) or 3 (CL=3) can be used. Byte, half-word (16bit) and word (32-bit) AHB accesses are supported. Incremental AHB burst access are supported for 32-bit words only. The read cycle(s) are always terminated with a PRE-CHARGE command, no banks are left open between two accesses. DDR read cycles are always performed in (aligned) 8-word bursts, which are stored in a FIFO. After an initial latency, the data is then read out on the AHB bus with zero waitstates. GRIP, Apr 2018, Version 2018.1 175 www.cobham.com/gaisler GRLIB IP Core 21.2.3 Write cycles Write cycles are performed similarly to read cycles, with the difference that WRITE commands are issued after activation. An AHB write burst will store up to 8 words in a FIFO, before writing the data to the DDR memory. As in the read case, only word bursts are supported 21.2.4 Initialization If the pwron VHDL generic is 1, then the DDR controller will automatically perform the DDR initialization sequence as described in the JEDEC DDR266 standard: PRE-CHARGE, LOAD-EXTMODEREG, LOAD-MODE-REG, PRE-CHARGE, 2xREFRESH and LOAD-MODE-REG; or as described in the JEDEC LPDDR standard when mobile DDR is enabled: PRE-CHARGE, 2xREFRESH, LOAD-MODE-REG and LOAD-EXTMODE-REG. The VHDL generics col and Mbyte can be used to also set the correct address decoding after reset. In this case, no further software initialization is needed. The DDR initialization can be performed at a later stage by setting bit 15 in the DDR control register. 21.2.5 Configurable DDR SDRAM timing parameters To provide optimum access cycles for different DDR devices (and at different frequencies), three timing parameters can be programmed through the memory configuration register (SDCFG): TRCD, TRP and TRFCD. The value of these field affects the SDRAM timing as described in table 194. Table 194.DDR SDRAM programmable minimum timing parameters SDRAM timing parameter Minimum timing (clocks) Precharge to activate (tRP) TRP + 2 Auto-refresh command period (tRFC) TRFC + 3 Activate to read/write (tRCD) TRCD + 2 Activate to Activate (tRC) TRCD + 8 Activate to Precharge (tRAS) TRCD + 6 If the TCD, TRP and TRFC are programmed such that the DDR200/266 specifications are fulfilled, the remaining SDRAM timing parameters will also be met. The table below shows typical settings for 100 and 133 MHz operation and the resulting SDRAM timing (in ns): Table 195.DDR SDRAM example programming tRCD DDR SDRAM settings tRC tRP tRFC tRAS 100 MHz: CL=2, TRP=0, TRFC=4, TRCD=0 20 80 20 70 60 133 MHz: CL=2, TRP=1, TRFC=6, TRCD=1 22.5 75 22.5 67.5 52.5 When the DDRSPA controller uses CAS latency (CL) of two cycles a DDR SDRAM speed grade of 75Z or better is needed to meet 133 MHz timing. When mobile DDR support is enabled, two additional timing parameters can be programmed though the Power-Saving configuration register. Table 196.Mobile DDR SDRAM programmable minimum timing parameters SDRAM timing parameter Minimum timing (clocks) Exit Power-down mode to first valid command (tXP) TXP + 1 Exit Self Refresh mode to first valid command (tXSR) TXSR + 1 CKE minimum pulse width (tCKE) TCKE + 1 GRIP, Apr 2018, Version 2018.1 176 www.cobham.com/gaisler GRLIB IP Core 21.2.6 Extended timing fields The DDRSPA controller can be configured with extended timing fields to provide support for DDR333 and DDR400. These fields can be detected by checking the XTF bit in the SDCFG register. When the extended timing fields are enabled, extra upper bits are added to increase the range of the TRP, TRFC, TXSR and TXP fields. A new TWR field allow increasing the write recovery time. A new TRAS field to directly control the Active to Precharge period has been added. Table 197.DDR SDRAM extended timing parameters SDRAM timing parameter Minimum timing (clocks) Activate to Activate (tRC) TRAS+TRCD + 2 Activate to Precharge (tRAS) TRAS + 6 Write recovery time (tWR) TWR+2 Table 198.DDR SDRAM extended timing example programming DDR SDRAM settings tRCD tRC tRP tRFC tRAS tWR 166 MHz: CL=2, TRP=1, TRFC=9, TRCD=1, TRAS=1, TWR=1 18 60 18 72 42 18 200 MHz: CL=3, TRP=1, TRFC=11, TRCD=1, TRAS=2, TWR=1 15 55 15 70 40 15 21.2.7 Refresh The DDRSPA controller contains a refresh function that periodically issues an AUTO-REFRESH command to both SDRAM banks. The period between the commands (in clock periods) is programmed in the refresh counter reload field in the SDCFG register. Depending on SDRAM type, the required period is typically 7.8 us (corresponding to 780 at 100 MHz). The generated refresh period is calculated as (reload value+1)/sysclk. The refresh function is enabled by bit 31 in SDCTRL register. 21.2.8 Self Refresh The self refresh mode can be used to retain data in the SDRAM even when the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking and refresh are handled internally. The memory array that is refreshed during the self refresh operation is defined in the extended mode register. These settings can be changed by setting the PASR bits in the Power-Saving configuration register. The extended mode register is automatically updated when the PASR bits are changed. The supported “Partial Array Self Refresh” modes are: Full, Half, Quarter, Eighth, and Sixteenth array. “Partial Array Self Refresh” is only supported when mobile DDR functionality is enabled. To enable the self refresh mode, set the PMODE bits in the Power-Saving configuration register to “010” (Self Refresh). The controller will enter self refresh mode after every memory access (when the controller has been idle for 16 clock cycles), until the PMODE bits are cleared. When exiting this mode and mobile DDR is disabled, the controller introduce a delay of 200 clock cycles and a AUTO REFRESH command before any other memory access is allowed. When mobile DDR is enabled the delay before the AUTO REFRESH command is defined by tXSR in the Power-Saving configuration register. The minimum duration of this mode is defined by tRFC. This mode is only available when the VHDL generic mobile is >= 1. 21.2.9 Clock Stop In the clock stop mode, the external clock to the SDRAM is stop at a low level (DDR_CLK is low and DDR_CLKB is high). This reduce the power consumption of the SDRAM while retaining the data. To enable the clock stop mode, set the PMODE bits in the Power-Saving configuration register to “100” (Clock Stop). The controller will enter clock stop mode after every memory access (when the controller has been idle for 16 clock cycles), until the PMODE bits are cleared. The REFRESH command GRIP, Apr 2018, Version 2018.1 177 www.cobham.com/gaisler GRLIB IP Core will still be issued by the controller in this mode. This mode is only available when the VHDL generic mobile is >= 1 and mobile DDR functionality is enabled. 21.2.10 Power-Down When entering the power-down mode all input and output buffers, including DDR_CLK and DDR_CLKB and excluding DDR_CKE, are deactivated. This is a more efficient power saving mode then clock stop mode, with a grater reduction of the SDRAM’s power consumption. All data in the SDRAM is retained during this operation. To enable the power-down mode, set the PMODE bits in the Power-Saving configuration register to “001” (Power-Down). The controller will enter powerdown mode after every memory access (when the controller has been idle for 16 clock cycles), until the PMODE bits is cleared. The REFRESH command will still be issued by the controller in this mode. When exiting this mode a delay of one or two (when tXP in the Power-Saving configuration register is ‘1’) clock cycles are added before issue any command to the memory. This mode is only available when the VHDL generic mobile is >= 1. 21.2.11 Deep Power-Down The deep power-down operating mode is used to achieve maximum power reduction by eliminating the power of the memory array. Data will not be retained after the device enters deep power-down mode. To enable the deep power-down mode, set the PMODE bits in the Power-Saving configuration register to “101” (Deep Power-Down). To exit the deep power-down mode the PMODE bits in the Power-Saving configuration register must be cleared followed by the mobile SDRAM initialization sequence. The mobile SDRAM initialization sequence can be performed by setting bit 15 in the DDR control register. This mode is only available when the VHDL generic mobile is >= 1 and mobile DDR functionality is enabled. 21.2.12 Status Read Register The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh multiplier, width type, and density of the SDRAM. To Read the SSR a LOAD MODE REGISTER command with BA0 = 1 and BA1 = 0 must be issued followed by a READ command with the address set to 0. This command sequence is executed then the Status Read Register is read. This register is only available when the VHDL generic mobile is >= 1 and mobile DDR functionality is enabled. Only DDR_CSB[0] is enabled during this operation. 21.2.13 Temperature-Compensated Self Refresh The settings for the temperature-compensation of the Self Refresh rate can be controlled by setting the TCSR bits in the Power-Saving configuration register. The extended mode register is automatically updated when the TCSR bits are changed. Note that some vendors implements a Internal Temperature-Compensated Self Refresh feature, which makes the memory to ignore the TCSR bits. This functionality is only available when the VHDL generic mobile >= 1 and mobile DDR functionality is enabled. 21.2.14 Drive Strength The drive strength of the output buffers can be controlled by setting the DS bits in the Power-Saving configuration register. The extended mode register is automatically updated when the DS bits are changed. The available options are: full, three-quarter, one-half, and one-quarter drive strengths. This functionality is only available when the VHDL generic mobile is >= 1 and mobile DDR functionality is enabled. GRIP, Apr 2018, Version 2018.1 178 www.cobham.com/gaisler GRLIB IP Core 21.2.15 SDRAM commands The controller can issue four SDRAM commands by writing to the SDRAM command field in SDCFG: PRE-CHARGE, LOAD-EXTMODE-REG, LOAD-MODE-REG and REFRESH. If the LEMR command is issued, the PLL Reset bit as programmed in SDCFG will be used, when mobile DDR support is enabled the DS, TCSR and PASR as programmed in Power-Saving configuration register will be used. If the LMR command is issued, the CAS latency as programmed in the Power-Saving configuration register will be used and remaining fields are fixed: 8 word sequential burst. The command field will be cleared after a command has been executed. 21.2.16 Clocking The DDR controller is designed to operate with two clock domains, one for the DDR memory clock and one for the AHB clock. The two clock domains do not have to be the same or be phase-aligned. The DDR input clock (CLK_DDR) can be multiplied and divided by the DDR PHY to form the final DDR clock frequency. The final DDR clock is driven on one output (CLKDDRO), which should always be connected to the CLKDDRI input. If the AHB clock and DDR clock area generated from the same clock source, a timing-ignore constraint should be placed between the CLK_AHB and CLKDDRI to avoid optimization of false-paths during synthesis and place&route. The Xilinx version of the PHY generates the internal DDR read clock using an external clock feedback. The feed-back should have the same delay as DDR signals to and from the DDR memories. The feed-back should be driven by DDR_CLK_FB_OUT, and returned on DDR_CLK_FB. Most Xilinx FPGA boards with DDR provides clock feed-backs of this sort. The supported frequencies for the Xilinx PHY depends on the clock-to-output delay of the DDR output registers, and the internal delay from the DDR input registers to the read data FIFO. Virtex2 and Virtex4 can typically run at 120 MHz, while Spartan3e can run at 100 MHz. The read data clock in the Xilinx version of the PHY is generated using a DCM to offset internal delay of the DDR clock feed back. If the automatic DCM phase adjustment does not work due to unsuitable pin selection, extra delay can be added through the RSKEW VHDL generic. The VHDL generic can be between -255 and 255, and is passed directly to the PHASE_SHIFT generic of the DCM. The Altera version of the PHY use the DQS signals and an internal PLL to generate the DDR read clock. No external clock feed-back is needed and the DDR_CLK_FB_OUT/DDR_CLK_FB signals are not used. The supported frequencies for the Altera PHY are 100, 110, 120 and 130 MHz. For Altera CycloneIII, the read data clock is generated by the PLL. The phase shift of the read data clock is set be the VHDL generic RSKEW in ps (e.g. a value of 2500 equals 90’ phase for a 100MHz system). 21.2.17 Pads The DDRSPA core has technology-specific pads inside the core. The external DDR signals should therefore be connected directly the top-level ports, without any logic in between. 21.2.18 Endianness The core is designed for big-endian systems. GRIP, Apr 2018, Version 2018.1 179 www.cobham.com/gaisler GRLIB IP Core 21.3 Registers The DDRSPA core implements two control registers. The registers are mapped into AHB I/O address space defined by the AHB BAR1 of the core. Table 199.DDR controller registers Address offset - AHB I/O - BAR1 Register 0x00 SDRAM control register 0x04 SDRAM configuration register (read-only) 0x08 SDRAM Power-Saving configuration register 0x0C Reserved 0x10 Status Read Register (Only available when mobile DDR support is enabled) 0x14 PHY configuration register 0 (Only available when VHDL generic confapi = 1, TCI RTL_PHY) 0x18 PHY configuration register 1 (Only available when VHDL generic confapi = 1, TCI TRL_PHY) GRIP, Apr 2018, Version 2018.1 180 www.cobham.com/gaisler GRLIB IP Core 21.3.1 Control Register Table 200. SDRAM control register (SDCTRL) 31 30 29 Refresh tRP 27 tRFC 26 25 tRCD 23 22 SDRAM bank size 21 20 SDRAM col. size 18 17 16 15 14 SDRAM command 0 PR IN CE SDRAM refresh load value 31 SDRAM refresh. If set, the SDRAM refresh will be enabled. This register bit is read only when Power-Saving mode is other then none. 30 SDRAM tRP timing. tRP will be equal to 2 or 3 system clocks (0/1). When mobile DDR support is enabled, this bit also represent the MSB in the tRFC timing. 29: 27 SDRAM tRFC timing. tRFC will be equal to 3 + field-value system clocks. When mobile DDR support is enabled, this field is extended with the bit 30. 26 SDRAM tRCD delay. Sets tRCD to 2 + field value clocks. 25: 23 SDRAM banks size. Defines the decoded memory size for each SDRAM chip select: “000”= 8 Mbyte, “001”= 16 Mbyte, “010”= 32 Mbyte .... “111”= 1024 Mbyte. 22: 21 SDRAM column size. “00”=512, “01”=1024, “10”=2048, “11”=4096 20: 18 SDRAM command. Writing a non-zero value will generate an SDRAM command: “010”=PRECHARGE, “100”=AUTO-REFRESH, “110”=LOAD-COMMAND-REGISTER, “111”=LOADEXTENDED-COMMAND-REGISTER. The field is reset after command has been executed. 17 PLL Reset. This bit is used to set the PLL RESET bit during LOAD-CONFIG-REG commands. 16 Initialize (IN). Set to ‘1’ to perform power-on DDR RAM initialisation. Is automatically cleared when initialisation is completed. This register bit is read only when Power-Saving mode is other then none. 15 Clock enable (CE). This value is driven on the CKE inputs of the DDR RAM. Should be set to ‘1’ for correct operation. This register bit is read only when Power-Saving mode is other then none. 14: 0 The period between each AUTO-REFRESH command - Calculated as follows: tREFRESH = ((reload value) + 1) / DDRCLOCK 21.3.2 Configuration Register Table 201. SDRAM configuration register (SDCFG) 31 21 Reserved 31: 21 20 XTF 19 16 15 14 CONFAPI 12 11 0 MD Data width DDR Clock frequency Reserved 20 Extended timing fields for DDR400 available 19: 16 Register API configuration.  0 = Standard register API. 1 = TCI TSMC90 PHY register API. 15 Mobile DDR support enabled. ‘1’ = Enabled, ‘0’ = Disabled (read-only) 14: 12 DDR data width: “001” = 16 bits, “010” = 32 bits, “011” = 64 bits (read-only) 11: 0 Frequency of the (external) DDR clock (read-only) 21.3.3 Power-Saving Configuration Register Table 202.SDRAM Power-Saving configuration register 31 30 29 28 27 26 ME CL TRAS xXS* 25 xXP GRIP, Apr 2018, Version 2018.1 24 23 tC 20 19 18 16 15 tXSR tXP PMODE 181 12 Reserved 11 10 TWR xTRP 9 8 xTRFC 7 5 DS 4 3 TCSR 2 0 PASR www.cobham.com/gaisler GRLIB IP Core Table 202.SDRAM Power-Saving configuration register 31 Mobile DDR functionality enabled. ‘1’ = Enabled (support for Mobile DDR SDRAM), ‘0’ = disabled (support for standard DDR SDRAM) 30 CAS latency; ‘0’ => CL = 2, ‘1’ => CL = 3 29: 28 SDRAM extended tRAS timing, tRAS will be equal to field-value + 6 system clocks. (Reserved when extended timing fields are disabled) 27: 26 SDRAM extended tXSR field, extend tXSR with field-value * 16 clocks (Reserved when extended timing fields are disabled) 25 SDRAM extended tXP field, extend tXP with 2*field-value clocks (Reserved when extended timing fields are disabled) 24 SDRAM tCKE timing, tCKE will be equal to 1 or 2 clocks (0/1). (Read only when Mobile DDR support is disabled). 23: 20 SDRAM tXSR timing. tXSR will be equal to field-value system clocks. (Read only when Mobile DDR support is disabled). 19 SDRAM tXP timing. tXP will be equal to 2 or 3 system clocks (0/1). (Read only when Mobile DDR support is disabled). 18: 16 Power-Saving mode (Read only when Mobile DDR support is disabled). “000”: none “001”: Power-Down (PD) “010”: Self-Refresh (SR) “100”: Clock-Stop (CKS) “101”: Deep Power-Down (DPD) 15: 12 Reserved 11 SDRAM extended tWR timing, tWR will be equal to field-value + 2 clocks (Reserved when extended timing fields are disabled) 10 SDRAM extended tRP timing, extend tRP with field-value * 2 clocks 9: 8 SDRAM extended tRFC timing, extend tRFC with field-value * 8 clocks 7: 5 Selectable output drive strength (Read only when Mobile DDR support is disabled). “000”: Full “001”: One-half “010”: One-quarter “011”: Three-quarter 4: 3 Reserved for Temperature-Compensated Self Refresh (Read only when Mobile DDR support is disabled). “00”: 70ªC “01”: 45ªC “10”: 15ªC “11”: 85ªC 2: 0 Partial Array Self Refresh (Read only when Mobile DDR support is disabled). “000”: Full array (Banks 0, 1, 2 and 3) “001”: Half array (Banks 0 and 1) “010”: Quarter array (Bank 0) “101”: One-eighth array (Bank 0 with row MSB = 0) “110”: One-sixteenth array (Bank 0 with row MSB = 00) GRIP, Apr 2018, Version 2018.1 182 www.cobham.com/gaisler GRLIB IP Core 21.3.4 Status Read Register Table 203. Status Read Register 31 16 15 0 SRR_16 SRR 31: 16 Status Read Register when 16-bit DDR memory is used (read only) 15: 0 Status Read Register when 32/64-bit DDR memory is used (read only) 21.3.5 PHY Configuration Register 0 Table 204. PHY configuration register 0 (TCI RTL_PHY only) 31 30 29 28 27 R1 R0 P1 P0 22 21 TSTCTRL1 16 15 TSTCTRL0 31 Reset DLL 1 (active high) 30 Reset DLL 1 (active high) 29 Power Down DLL 1 (active high) 8 7 MDAJ_DLL1 0 MDAJ_DLL0 28 Power Down DLL 1 (active high) 27: 22 Test control DLL 1 tstclkin(1) is connected to SIGI_1 on DDL 1 when bit 26:25 is NOT equal to “00“. tstclkin(0) is connected to SIGI_0 on DDL 1 when bit 23:22 is NOT equal to “00“. 21: 16 Test control DLL 0 15: 8 Master delay adjustment input DLL 1 7: 0 Master delay adjustment input DLL 0 21.3.6 PHY Configuration Register 1 Table 205. PHY configuration register 1 (TCI RTL_PHY only) 31 24 23 ADJ_RSYNC 21.4 16 15 ADJ_90 8 ADJ_DQS1 31: 24 Slave delay adjustment input for resync clock (Slave 1 DLL 1) 23: 16 Slave delay adjustment input for 90’ clock (Slave 0 DLL 1) 15: 8 Slave delay adjustment input for DQS 1 (Slave 1 DLL 0) 7: 0 Slave delay adjustment input for DQS 0 (Slave 0 DLL 0) 7 0 ADJ_DQS0 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x025. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. GRIP, Apr 2018, Version 2018.1 183 www.cobham.com/gaisler GRLIB IP Core 21.5 Configuration options Table 206 shows the configuration options of the core (VHDL generics). Table 206.Configuration options Generic Function Allowed range Default fabtech PHY technology selection virtex2, virtex4, spartan3e, altera virtex2 memtech Technology selection for DDR FIFOs infered, virtex2, virtex4, spartan3e, altera infered hindex AHB slave index 0 - NAHBSLV-1 0 haddr ADDR field of the AHB BAR0 defining SDRAM area. Default is 0xF0000000 - 0xFFFFFFFF. 0 - 16#FFF# 16#000# hmask MASK field of the AHB BAR0 defining SDRAM area. 0 - 16#FFF# 16#F00# ioaddr ADDR field of the AHB BAR1 defining I/O address space where DDR control register is mapped. 0 - 16#FFF# 16#000# iomask MASK field of the AHB BAR1 defining I/O address space 0 - 16#FFF# 16#FFF# ddrbits Data bus width of external DDR memory 16, 32, 64 16 MHz DDR clock input frequency in MHz. 10 - 200 100 clkmul, clkdiv The DDR input clock is multiplied with the clkmul generic and divided with clkdiv to create the final DDR clock 2 - 32 2 rstdel Clock reset delay in micro-seconds. 1 - 1023 200 col Default number of column address bits 9 - 12 9 Mbyte Default memory chip select bank size in Mbyte 8 - 1024 16 pwron Enable SDRAM at power-on initialization 0-1 0 oepol Polarity of bdrive and vbdrive signals. 0=active low, 1=active high 0-1 0 ahbfreq Frequency in MHz of the AHB clock domain 1 - 1023 50 rskew Additional read data clock skew Read data clock phase for Altera CycloneIII -255 - 255. 0 - 9999 0 mobile Enable Mobile DDR support 0: Mobile DDR support disabled 1: Mobile DDR support enabled but not default 2: Mobile DDR support enabled by default 3: Mobile DDR support only (no regular DDR support) 0-3 0 confapi Set the PHY configuration register API: 0 = standard register API (conf0 and conf1 disabled). 1 = TCI RTL_PHY register API. conf0 Reset value for PHY register 0, conf[31:0] 0 - 16#FFFFFFFF# 0 conf1 Reset value for PHY register1, conf[63:32] 0 - 16#FFFFFFFF# 0 regoutput Enables registers on signal going from controller to PHY 0 - 1 0 ddr400 Enables extended timing fields for DDR400 support 0-1 1 scantest Enable scan test support 0-1 0 phyiconf PHY implementation configuration. This generic sets technology specific implementation options for the DDR PHY. Meaning of values depend on the setting of VHDL generic fabtech. 0 - 16#FFFFFFFF# 0 For fabtech:s virtex4, virtex5, virtex6: phyiconf selects type of pads used for DDR clock pairs. 0 instantiates a differiental pad and 1 instantiates two outpads. GRIP, Apr 2018, Version 2018.1 184 www.cobham.com/gaisler GRLIB IP Core 21.6 Implementation 21.6.1 Technology mapping The core has two technology mapping VHDL generics: memtech and fabtech. The VHDL generic memtech controls the technology used for memory cell implementation. The VHDL generic fabtech controls the technology used in the PHY implementation. See the GRLIB Users’s Manual for available settings. 21.6.2 FPGA support Complete PHY:s for a number FPGA technologies are included in the distribution, see table below. Unless otherwise noted these have been only functionally tested on evaluation board in lab environment and detailed timing analysis has not been performed. Note also that some of the FPGA phy:s use simplified sampling approaches which may require the memory timing to be better than the JEDEC standard specifies. Scripts for post-layout static timing analysis are not included. Because these PHY:s are based on dedicated hard macros with fixed placement in the FPGA:s pad structure, just a minimal set of constraints are normally neccessary for synthesis purposes. Table 207.FPGA DDR PHYs included in GRLIB Technology fabtech Virtex4,5,6 virtex4, virtex5, virtex6 Clock feedback loop + static shift Yes Virtex2, Spartan3 virtex2, spartan3 Read clock method Built-in pads Clock feedback loop + static shift Yes Spartan3E,6 spartan3 Clock feedback loop + static shift Yes Stratix II stratix2 Tech intrinsics (DQS based) Yes Cyclone 3 cyclone3 Static shift Yes 21.6.3 RAM usage The FIFOs in the core are implemented with the syncram_2p (with separate clock for each port) component found in the technology mapping library (TECHMAP). The number of RAMs used for the FIFO implementation depends on the DDR data width, set by the ddrbits VHDL generic. Table 208.RAM usage RAM dimension (depth x width) Number of RAMs (DDR data width 64) 4 x 128 1 4 x 32 4 Number of RAMs (DDR data width 32) 5 x 64 1 5 x 32 2 6 x 32 GRIP, Apr 2018, Version 2018.1 Number of RAMs (DDR data width 16) 2 185 www.cobham.com/gaisler GRLIB IP Core 21.7 Signal descriptions Table 209 shows the interface signals of the core (VHDL ports). Table 209.Signal descriptions Signal name Type Function Active RST_DDR Input Reset input for DDR clock domain Low RST_AHB Input Reset input for AHB clock domain Low CLK_DDR Input DDR input Clock - CLK_AHB Input AHB clock - LOCK Output DDR clock generator locked High CLKDDRO Internal DDR clock output after clock multiplication CLKDDRI Clock input for the internal DDR clock domain. Must be connected to CLKDDRO. AHBSI Input AHB slave input signals - AHBSO Output AHB slave output signals - DDR_CLK[2:0] Output DDR memory clocks (positive) High DDR_CLKB[2:0] Output DDR memory clocks (negative) Low DDR_CLK_FB_OUT Output Same a DDR_CLK, but used to drive an external clock feedback. - DDR_CLK_FB Input Clock input for the DDR clock feed-back - DDR_CKE[1:0] Output DDR memory clock enable High DDR_CSB[1:0] Output DDR memory chip select Low DDR_WEB Output DDR memory write enable Low DDR_RASB Output DDR memory row address strobe Low DDR_CASB Output DDR memory column address strobe Low DDR_DM[DDRBITS/8-1:0] Output DDR memory data mask Low DDR_DQS[DDRBITS/8-1:0] Bidir DDR memory data strobe Low DDR_AD[13:0] Output DDR memory address bus Low DDR_BA[1:0] Output DDR memory bank address Low DDR_DQ[DDRBITS-1:0] BiDir DDR memory data bus - 1) see GRLIB IP Library User’s Manual 2) Polarity selected with the oepol generic 21.8 Library dependencies Table 210 shows libraries used when instantiating the core (VHDL libraries). Table 210.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals, component Memory bus signals definitions, component declaration GRIP, Apr 2018, Version 2018.1 186 www.cobham.com/gaisler GRLIB IP Core 21.9 Component declaration component ddrspa generic ( fabtech : integer := 0; memtech : integer := 0; hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#f00#; ioaddr : integer := 16#000#; iomask : integer := 16#fff#; MHz : integer := 100; clkmul : integer := 2; clkdiv : integer := 2; col : integer := 9; Mbyte : integer := 16; rstdel : integer := 200; pwron : integer := 0; oepol : integer := 0; ddrbits : integer := 16; ahbfreq : integer := 50 ); port ( rst_ddr : in std_ulogic; rst_ahb : in std_ulogic; clk_ddr : in std_ulogic; clk_ahb : in std_ulogic; lock : out std_ulogic;-- DCM locked clkddro : out std_ulogic;-- DCM locked clkddri : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; ddr_clk : out std_logic_vector(2 downto 0); ddr_clkb: out std_logic_vector(2 downto 0); ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke : out std_logic_vector(1 downto 0); ddr_csb : out std_logic_vector(1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (13 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data ); end component; GRIP, Apr 2018, Version 2018.1 187 www.cobham.com/gaisler GRLIB IP Core 21.10 Instantiation This examples shows how the core can be instantiated. The DDR SDRAM controller decodes SDRAM area at 0x40000000 - 0x7FFFFFFF. The SDRAM registers are mapped into AHB I/O space on address (AHB I/O base address + 0x100). library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.tech.all; library gaisler; use gaisler.memctrl.all; entity ddr_Interface is port ( ddr_clk : out std_logic_vector(2 downto 0); ddr_clkb : out std_logic_vector(2 downto 0); ddr_clk_fb : in std_logic; ddr_clk_fb_out : out std_logic; ddr_cke : out std_logic_vector(1 downto 0); ddr_csb : out std_logic_vector(1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (13 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data ); end; architecture rtl of mctrl_ex is -- AMBA bus signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal clkml, lock : std_ulogic; begin -- DDR controller ddrc : ddrspa generic map ( fabtech => virtex4, ddrbits => 64, memtech => memtech, hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => 1, MHz => 100, col => 9, Mbyte => 32, ahbfreq => 50, ddrbits => 64) port map ( rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4), ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq); GRIP, Apr 2018, Version 2018.1 188 www.cobham.com/gaisler GRLIB IP Core 22 DDR2SPA - 16-, 32- and 64-bit Single-Port Asynchronous DDR2 Controller 22.1 Overview DDR2SPA is a DDR2 SDRAM controller with AMBA AHB back-end. The controller can interface 16-, 32- or 64-bit wide DDR2 memory with one or two chip selects. The controller acts as a slave on the AHB bus where it occupies a configurable amount of address space for DDR2 SDRAM access. The DDR2 controller is programmed by writing to configuration registers mapped located in AHB I/ O address space. Internally, DDR2SPA consists of a ABH/DDR2 controller and a technology specific DDR2 PHY. For currently supported technologies for the PHY, see section 22.7.2. The modular design of DDR2SPA allows to add support for other target technologies in a simple manner. DDR2SPA AHB DDR2 CONTROLLER AHB SLAVE CLK SDCSN[1:0] SDRASN SDCASN SDWEN SDDQM[15:0] SDCKE DDR CLOCK 16/32/64-bit DDR2 Memory CLK CSN RAS CAS WE DQM CKE ADDRESS[16:2] DATA[127:0] CALl CLK CLKN CSN RAS CAS WE DQM CKE ADDR[13:0] BA[1:0] DQ[63:0] DQS[7:0] DQSN[7:0] DDR2 PHY CLK CLKN CSN RAS CAS WE DQM CKE ADDR[13:0] BA[1:0] DQ[63:0] DQS[7:0] DQSN[7:0] Figure 58. DDR2SPA Memory controller connected to AMBA bus and DDR2 SDRAM 22.2 Operation 22.2.1 General Single DDR2 SDRAM chips are typically 4,8 or 16 data bits wide. By putting multiple identical chips side by side, wider SDRAM memory banks can be built. Since the command signals are common for all chips, the memories behave as one single wide memory chip. This memory controller supports one or two (identical) such 16/32/64-bit wide DDR2 SDRAM memory banks. The size of the memory can be programmed in binary steps between 8 Mbyte and 1024 Mbyte, or between 32 Mbyte and 4096 Mbyte. The DDR data width is set by the DDRBITS generic, and will affect the width of DM, DQS and DQ signals. The DDR data width does not change the behavior of the AHB interface, except for data latency. 22.2.2 Data transfers An AHB read or write access to the controller will cause a corresponding access cycle to the external DDR2 RAM. The cycle is started by performing an ACTIVATE command to the desired bank and row, followed by a sequence of READ or WRITE commands (the count depending on memory width and burst length setting). After the sequence, a PRECHARGE command is performed to deactivate the SDRAM bank. All access types are supported, but only incremental bursts of 32 bit width and incremental bursts of maximum width (if wider than 32) are handled efficiently. All other bursts are handled as single- GRIP, Apr 2018, Version 2018.1 189 www.cobham.com/gaisler GRLIB IP Core accesses. For maximum throughput, incremental bursts of full AHB width with both alignment and length corresponding to the burstlen generic should be performed. The maximum supported access size can be limited by using the ahbbits generic, which is set to the full AHB bus size by default. Accesses larger than this size are not supported. The memory controller’s FIFO has room for two write bursts which improves throughput, since the second write can be written into the FIFO while the first write is being written to the DDR memory. In systems with high DDR clock frequencies, the controller may have to insert wait states for the minimum activate-to-precharge time (tRAS) to expire before performing the precharge command. If a new AHB access to the same memory row is performed during this time, the controller will perform the access in the same access cycle. 22.2.3 Initialization If the pwron VHDL generic is 1, then the DDR2 controller will automatically on start-up perform the DDR2 initialization sequence as described in the JEDEC DDR2 standard. The VHDL generics col and Mbyte can be used to also set the correct address decoding after reset. In this case, no further software initialization is needed except for enabling the auto-refresh function. If power-on initialization is not enabled, the DDR2 initialization can be started at a later stage by setting bit 16 in the DDR2 control register DDR2CFG1. 22.2.4 Big memory support The total memory size for each chip select is set through the 3-bit wide SDRAM banks size field, which can be set in binary steps between 8 Mbyte and 1024 Mbyte. To support setting even larger memory sizes of 2048 and 4096 Mbyte, a fourth bit has been added to this configuration field. Only 8 different sizes are supported by the controller, either the lower range of 8 MB - 1 GB, or the higher range of 32 MB - 4 GB. Which range is determined by the bigmem generic, and can be read by software through the DDR2CFG2 register. 22.2.5 Configurable DDR2 SDRAM timing parameters To provide optimum access cycles for different DDR2 devices (and at different frequencies), six timing parameters can be programmed through the memory configuration registers: TRCD, TCL, TRTP, TWR, TRP and TRFC. For faster memories (DDR2-533 and higher), the TRAS setting also needs to be configured to satisfy timing. The value of these fields affects the DDR2RAM timing as described in table 211. Note that if the CAS latency setting is changed after initialization, this change needs also to be programmed into the memory chips by executing the Load Mode Register command. Table 211.DDR2 SDRAM programmable minimum timing parameters DDR2 SDRAM timing parameter Minimum timing (clocks) CAS latency, CL TCL + 3 Activate to read/write command (tRCD) TRCD + 2 Read to precharge (tRTP) TRTP + 2 Write recovery time (tWR) TWR-2 Precharge to activate (tRP) TRP + 2 Activate to precharge (tRAS) TRAS + 1 Auto-refresh command period (tRFC) TRFC + 3 If TRCD, TCL, TRTP, TWR, TRP, TRFC and TRAS are programmed such that the DDR2 specifications are full filled, the remaining SDRAM timing parameters will also be met. The table below GRIP, Apr 2018, Version 2018.1 190 www.cobham.com/gaisler GRLIB IP Core shows typical settings for 130, 200 and 400 MHz operation and the resulting DDR2 SDRAM timing (in ns): Table 212.DDR2 SDRAM example programming DDR2 SDRAM settings CL tRCD tRC tRP tRFC tRAS 130 MHz: TCL=0,TRCD=0,TRTP=0,TRP=0,TRAS=0,TRFC=7 3 15 76 15 76 61 200 MHz: TCL=0,TRCD=1,TRTP=0,TRP=1,TRAS=1,TRFC=13 3 15 60 15 80 45 400 MHz: TCL=2,TRCD=4,TRTP=1,TRP=4,TRAS=10,TRFC=29 5 15 60 15 80 45 22.2.6 Refresh The DDR2SPA controller contains a refresh function that periodically issues an AUTO-REFRESH command to both SDRAM banks. The period between the commands (in clock periods) is programmed in the refresh counter reload field in the DDR2CFG1 register. Depending on SDRAM type, the required period is typically 7.8 us (corresponding to 780 at 100 MHz). The generated refresh period is calculated as (reload value+1)/sysclk. The refresh function is enabled by bit 31 in DDR2CFG1 register. 22.2.7 DDR2 SDRAM commands The controller can issue four SDRAM commands by writing to the SDRAM command field in SDCFG1: PRE-CHARGE, LOAD-EXTMODE-REG, LOAD-MODE-REG and REFRESH. If the LMR command is issued, the PLL Reset bit as programmed in DDR2CFG1, CAS Latency setting as programmed in DDR2CFG4 and the WR setting from DDR2CFG3 will be used, remaining fields are fixed: 4 word sequential burst. If the LEMR command is issued, the OCD bits will be used as programmed in the DDR2CFG1 register, and all other bits are set to zero. The command field will be cleared after a command has been executed. 22.2.8 Registered SDRAM Registered memory modules (RDIMM:s) have one cycle extra latency on the control signals due to the external register. They can be supported with this core by setting the REG bit in the DDR2CFG4 register. This should not be confused with Fully-Buffered DDR2 memory, which uses a different protocol and is not supported by this controller. 22.2.9 Clocking The DDR2 controller operates in two separate clock domains, one domain synchronous to the DDR2 memory and one domain synchronous to the AHB bus. The two clock domains do not have to be the same or be phase-aligned. The clock for the DDR2 memory domain is generated from the controller’s ddr_clk input via a technology-specific PLL component. The multiplication and division factor can be selected via the clkmul/clkdiv configuration options. The final DDR2 clock is driven on one output (CLKDDRO), which should always be connected to the CLKDDRI input. The ddr_rst input asynchronously resets the PHY layer and the built-in PLL. The ahb_rst input should be reset simultaneously and then kept in reset until the PLL has locked (indicated by the lock output). If the AHB and DDR2 clocks are based on the same source clock and are kept phase-aligned by the PLL, the clock domain transition is synchronous to the least common multiple of the two clock frequencies. In this case, the nosync configuration option can be used to remove the synchronization and handshaking between the two clock domains, which saves a few cycles of memory access latency. If nosync is not set in this case, a timing-ignore constraint should be placed between the CLK_AHB and CLKDDRI to avoid optimization of false-paths during synthesis and place&route. GRIP, Apr 2018, Version 2018.1 191 www.cobham.com/gaisler GRLIB IP Core The supported DDR2 frequencies depends on the clock-to-output delay of the DDR output registers, and the internal delay from the DDR input registers to the read data FIFO. Virtex5 can typically run at 200 MHz. When reading data, the data bus (DQ) signals should ideally be sampled 1/4 cycle after each data strobe (DQS) edge. How this is achieved is technology-specific as described in the following sections. 22.2.10 Read data clock calibration on Xilinx Virtex On Xilinx Virtex4/5 the data signal inputs are delayed via the I/O pad IDELAY feature to get the required 1/4 cycle shift. The delay of each byte lane is tuned independently between 0-63 tap delays, each tap giving 78 ps delay, and the initial value on startup is set via the generics ddelayb[7:0]. The delays can be tuned at runtime by using the DDR2CFG3 control register. There are two bits in the control register for each byte. One bit determines if the delay should be increased or decreased and the other bit is set to perform the update. Setting bit 31 in the DDR2CFG3 register resets the delays to the initial value. To increase the calibration range, the controller can add additional read latency cycles. The number of additional read latency cycles is set by the RD bits in the DDR2CFG3 register. 22.2.11 Read data clock calibration on Altera Stratix On Altera StratixIII, the technology’s delay chain feature is used to delay bytes of input data in a similar fashion as the Virtex case above. The delay of each byte lane is tuned between 0-15 tap delays, each tap giving 50 ps delay, and the initial value on startup is 0. The delays are tuned at runtime using the DDR2CFG3 register, and extra read cycles can be added using DDR2CFG3, the same way as described for Virtex. The data sampling clock can also be skewed on Stratix to increase the calibration range. This is done writing the PLL_SKEW bits in the DDR2CFG3 register. 22.2.12 Read data clock calibration on Xilinx Spartan-3 On Spartan3, a clock loop is utilized for sampling of incoming data. The DDR_CLK_FB_OUT port should therefore be connected to a signal path of equal length as the DDR_CLK + DDR_DQS signal path. The other end of the signal path is to be connected to the DDR_CLK_FB port. The fed back clock can then be skewed for alignment with incoming data using the rskew generic. The rskew generic can be set between +/-255 resulting in a linear +/-360 degree change of the clock skew. Bits 29 and 30 in the DDR2CFG3 register can be used for altering the skew at runtime. 22.2.13 Pads The DDR2SPA core has technology-specific pads inside the core. The external DDR2 signals should therefore be connected directly the top-level ports, without any logic in between. 22.2.14 Endianness The core is designed for big-endian systems. 22.3 Fault-tolerant operation (preliminary) 22.3.1 Overview The memory controller can be configured to support bit-error tolerant operation by setting the ft generic (not supported in all versions of GRLIB). In this mode, the DDR data bus is widened and the extra bits are used to store 16 or 32 checkbits corresponding to each 64 bit data word. The variant to GRIP, Apr 2018, Version 2018.1 192 www.cobham.com/gaisler GRLIB IP Core be used can be configured at run-time depending on the connected DDR2 data width and the desired level of fault tolerance. When writing, the controller generates the check bits and stores them along with the data. When reading, the controller will transparently correct any correctable bit errors and provide the corrected data on the AHB bus. However, the corrected bits are not written back to the memory so external scrubbing is necessary to avoid uncorrectable errors accumulating over time. An extra corrected error output signal is asserted when a correctable read error occurs, at the same cycle as the corrected data is delivered. This can be connected to an interrupt input or to a memory scrubber. In case of uncorrectable error, this is signaled by giving an AHB error response to the master. 22.3.2 Memory setup In order to support error-correction, the DDR2 data bus needs to be expanded. The different possible physical configurations are tabulated below. For software, there is no noticeable difference between these configurations. If the hardware is built for the wider code, it is still possible to leave the upper half of the checkbit data bus unconnected and use it for code B. Table 213.Configurations of FT DDR2 memory banks Data bits (DDRBITS) Checkbits (FTBITS) Interleaving modes supported 64 32 A and B 64 16 B only 32 16 A and B 32 8 B only 16 8 A only 22.3.3 Error-correction properties The memory controller uses an interleaved error correcting code which works on nibble (4-bit) units of data. The codec can be used in two interleaving modes, mode A and mode B. In mode A, the basic code has 16 data bits, 8 check bits and can correct one nibble error. This code is interleaved by 4 using the pattern in table 214 to create a code with 64 data bits and 32 check bits. This code can tolerate one nibble error in each of the A,B,C,D groups shown below. This means that we can correct 100% of single errors in two adjacent nibbles, or in any 8/16-bit wide data bus lane, that would correspond to a physical DDR2 chip. The code can also correct 18/23=78% of all possible random two-nibble errors. This interleaving pattern was designed to also provide good protection in case of reduced (32/16-bit) DDR bus width with the same data-checkbit relation, so software will see the exact same checkbits on diagnostic reads. In mode B, the basic code has 32 data bits, 8 check bits and can correct one nibble error. This code is then interleaved by a factor of two to create a code with 64 data bits and 16 check bits. Note that when configured for a 16-bit wide DDR data bus, code A must be used to get protection from multi-column errors since each data bus nibbles holds four code word nibbles. Table 214.Mode Ax4 interleaving pattern (64-bit data width) 63:60 59:56 55:52 51:48 47:44 43:40 39:36 35:32 31:28 27:24 23:20 19:16 15:12 11:8 7:4 C D A B A B C D B A D C D C B A 95:88 87:80 79:72 71:64 Ccb Dcb Acb Bcb 127:120 119:112 111:104 103:96 Ccb GRIP, Apr 2018, Version 2018.1 193 Dcb Acb Bcb 3:0 www.cobham.com/gaisler GRLIB IP Core Table 215.Mode Bx2 interleaving pattern (64-bit data width) 63:60 59:56 55:52 51:48 47:44 43:40 39:36 35:32 31:28 27:24 23:20 19:16 15:12 11:8 7:4 A B A B A B A B B A B A B A B 3:0 A 95:88 87:80 79:72 71:64 Acb Bcb Acb Bcb 22.3.4 Data transfers The read case behaves the same way as the non-FT counterpart, except a few cycles extra are needed for error detection and correction. There is no extra time penalty in the case data is corrected compared to the error-free case. Only writes of 64 bit width or higher will translate directly into write cycles to the DDR memory. Other types of write accesses will generate a read-modify-write cycle in order to correctly update the check-bits. In the special case where an uncorrectable error is detected while performing the RMW cycle, the write is aborted and the incorrect checkbits are left unchanged so they will be detected upon the next read. Only bursts of maximum AHB width is supported, other bursts will be treated as single accesses. The write FIFO only has room for one write (single or burst). 22.3.5 DDR2 behavior The behavior over the DDR2 interface is largely unchanged, the same timing parameters and setup applies as for the non-FT case. The checkbit data and data-mask signals follow the same timing as the corresponding signals for regular data. 22.3.6 Configuration Whether the memory controller is the FT or the non-FT version can be detected by looking at the FTV bit in the DDR2CFG2 register. Checkbits are always written out to memory when writing even if EDACEN is disabled. Which type of code, A or B, that is used for both read and write is controlled by the CODE field in the DDR2FTCFG register. Code checking on read is disabled on reset and is enabled by setting the EDACEN bit in the DDR2FTCFG register. Before enabling this, the code to be used should be set in the CODE field and the memory contents should be (re-)initialized. 22.3.7 Diagnostic checkbit access The checkbits and data can be accessed directly for testing and fault injection. This is done by writing the address of into the DDR2FTDA register. The check-bits and data can then be read and written via the DDR2FTDC and DDR2FTDD register. Note that for checkbits the DDR2FTDA address is 64-bit aligned, while for data it is 32-bit aligned. After the diagnostic data register has been read, the FT control register bits 31:19 can be read out to see if there were any correctable or uncorrectable errors detected, and where the correctable errors were located. For the 64 databit wide version, there is one bit per byte lane describing whether a correctable error occurred. 22.3.8 Code boundary The code boundary feature allows you to gradually switch the memory from one interleaving mode to the other and regenerate the checkbits without stopping normal operation. This can be used when recovering from memory faults, as explained further below. GRIP, Apr 2018, Version 2018.1 194 www.cobham.com/gaisler GRLIB IP Core If the boundary address enable (BAEN) control bit is set, the core will look at the address of each access, and use the interleaving mode selected in the CODE field for memory accesses above or equal to the boundary address, and the opposite code for memory accesses below to the boundary address. If the boundary address update (BAUPD) control bit is also set, the core will shift the boundary upwards whenever the the address directly above the boundary is written to. Since the written data is now below the boundary, it will be written using the opposite code. The write can be done with any size supported by the controller. 22.3.9 Data muxing When code B is used instead of code A, the upper half of the checkbits are unused. The controller supports switching in this part of the data bus to replace another faulty part of the bus. To do this, one sets the DATAMUX field to a value between 1-4 to replace a quarter of the data bus, or to 5 to replace the active checkbit half. 22.3.10 Memory fault recovery The above features are designed to, when combined and integrated correctly, make the system cabable to deal with a permanent fault in an external memory chip. A basic sequence of events is as follows: 1. The system is running correctly with EDAC enabled and the larger code A is used. 2. A memory chip gets a fault and delivers incorrect data. The DDR2 controller keeps delivering error-free data but reports a correctable error on every read access. 3. A logging device (such as the memory scrubber core) registers the high frequency of correctable errors and signals an interrupt. 4. The CPU performs a probe using the DDR2 FT diagnostic registers to confirm that the error is permanent and on which physical lane the error is. 5. After determining that a permanent fault has occurred, the CPU reconfigures the FTDDR2 controller as follows (all configuration register fields changed with a single register write): The data muxing control field is set so the top checkbit half replaces the failed part of the data bus. The code boundary register is set to the lowest memory address. The boundary address enable and boundary address update enable bits are set. The mask correctable error bit is set 6. The memory data and checkbits are now regenerated using locked read-write cycles to use the smaller code and replace the broken data with the upper half of the checkbit bus. This can be done in hardware using an IP core, such as the AHB memory scrubber, or by some other means depending on system design. 7. After the whole memory has been regenerated, the CPU disables the code boundary, changes the code selection field to code B, and unsets the mask correctable error bit. After this sequence, the system is now again fully operational, but running with the smaller code and replacement chip and can again recover from any single-nibble error. Note that during this sequence, it is possible for the system to operate and other masters can both read and write to memory while the regeneration is ongoing. GRIP, Apr 2018, Version 2018.1 195 www.cobham.com/gaisler GRLIB IP Core 22.4 Registers The DDR2SPA core implements between 5 and 12 control registers, depending on the FT generic and target technology. The registers are mapped into AHB I/O address space defined by the AHB BAR1 of the core. Only 32-bit single-accesses are supported to the registers. Older revisions of the core only have registers DDRCFG1-4, which are aliased on the following addresses. For that reason, check the REG5 bit in DDR2CFG2 before using these bits for backward compatibility. For backward compatibility, some of the bits in DDR2CFG5 are mirrored in other registers. Writing to these bits will affect the contents of DDR2CFG5 and vice versa. Table 216.DDR2 controller registers Address offset - AHB I/O - BAR1 Register 0x00 DDR2 SDRAM control register (DDR2CFG1) 0x04 DDR2 SDRAM configuration register (DDR2CFG2) 0x08 DDR2 SDRAM control register (DDR2CFG3) 0x0C DDR2 SDRAM control register (DDR2CFG4) 0x10* DDR2 SDRAM control register (DDR2CFG5) 0x14* Reserved 0x18 DDR2 Technology specific register (DDR2TSR1) 0x1C* DDR2 Technology specific register (DDR2TSR2) 0x20 DDR2 FT Configuration Register (FT only) (DDR2FTCFG) 0x24 DDR2 FT Diagnostic Address register (FT only) (DDR2FTDA) 0x28 DDR2 FT Diagnostic Checkbit register (FT only) (DDR2FTDC) 0x2C DDR2 FT Diagnostic Data register (FT only) (DDR2FTDD) 0x30 DDR2 FT Code Boundary Register (FT only) (DDR2FTBND) * Older DDR2SPA versions contain aliases of DDR2CFG1-4 at these addresses. Therefore, check bit 15 of DDR2CFG2 before using these registers. GRIP, Apr 2018, Version 2018.1 196 www.cobham.com/gaisler GRLIB IP Core 22.4.1 DDR2 SDRAM Configuration Register 1 Table 217. 0x00 - DDR2CFG1 - DDR2 SRAM control register 1 31 Refresh 30 29 28 OCD EMR 27 26 bank (TRCD) size 3 25 23 22 SDRAM bank size2:0 21 20 SDRAM col. size 18 17 16 15 14 SDRAM command 0 PR IN CE 0 SDRAM refresh load value 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw rw rw 31 SDRAM refresh. If set, the SDRAM refresh will be enabled. 30 OCD operation 29: 28 Selects Extended mode register (1,2,3) 27 SDRAM banks size bit 3. By enabling this bit the memory size can be set to “1000” = 2048 Mbyte and “1001” = 4096 Mbyte. See the section on big-memory support. 26 Lowest bit of TRCD field in DDR2CFG, for backward compatibility 25: 23 SDRAM banks size. Defines the decoded memory size for each SDRAM chip select: “000”= 8 Mbyte, “001”= 16 Mbyte, “010”= 32 Mbyte.... “111”= 1024 Mbyte. 22: 21 SDRAM column size. “00”=512, “01”=1024, “10”=2048, “11”=4096 20: 18 SDRAM command. Writing a non-zero value will generate an SDRAM command: “010”=PRECHARGE, “100”=AUTO-REFRESH, “110”=LOAD-COMMAND-REGISTER, “111”=LOADEXTENDED-COMMAND-REGISTER. The field is reset after command has been executed. 17 PLL Reset. This bit is used to set the PLL RESET bit during LOAD-CONFIG-REG commands. 16 Initialize (IN). Set to ‘1’ to perform power-on DDR RAM initialisation. Is automatically cleared when initialisation is completed. 15 Clock enable (CE). This value is driven on the CKE inputs of the DDR RAM. Should be set to ‘1’ for correct operation. 14: 0 The period between each AUTO-REFRESH command - Calculated as follows: tREFRESH = ((reload value) + 1) / DDRCLOCK 22.4.2 DDR2 SDRAM Configuration Register 2 Table 218. 0x04 - DDR2CFG2 - DDR2 SDRAM configuration register 2 31 17 16 15 RESERVED 26 25 PHY Tech 18 BIG FTV REG5 14 Data width 12 11 DDR Clock frequency 0 0 0 0 0 0 0 0 r r r r r r r 31: 26 Reserved 25: 18 PHY technology identifier, value 0 is for generic/unknown 17 Big memory support, if ‘1’ then memory can be set between 32 Mbyte and 4 Gbyte, if ‘0’ then memory size can be set between 8 Mbyte and 1 Gbyte. 16 Reads ‘1’ if the controller is fault-tolerant version and EDAC registers exist. 15 Reads ‘1’ if DDR2CFG5 register exists. 14: 12 SDRAM data width: “001” = 16 bits, “010” = 32 bits, “011” = 64 bits. 11: 0 Frequency of the (external) DDR clock. GRIP, Apr 2018, Version 2018.1 197 www.cobham.com/gaisler GRLIB IP Core 22.4.3 DDR2 SDRAM Configuration Register 3 Table 219.0x08 - DDR2CFG3 - DDR2 SDRAM configuration register 3 31 30 29 PLL 28 27 23 22 (TRP) tWR 18 17 16 15 (TRFC) 8 RD 7 inc/dec delay 0 Update delay 0 0 * * 0 0 rw rw rw rw rw rw 31 Reset byte delay 30: 29 PLL_SKEW Bit 29: Update clock phase Bit 30: 1 = Inc / 0 = Dec clock phase 28 Lowest bit of DDR2CFG4 TRP field for backward compatibility 27: 23 SDRAM write recovery time. tWR will be equal to field value - 2DDR clock cycles 22: 18 Lower 5 bits of DDR2CFG4 TRFC field for backward compatibility. 17: 16 Number of added read delay cycles, default = 1 15: 8 Set to ‘1’ to increment byte delay, set to ‘0’ to decrement delay 7: 0 Set to ‘1’ to update byte delay 22.4.4 DDR2 SDRAM Configuration Register 4 Table 220.0x0C - DDR2CFG4 - DDR2 SDRAM configuration register 4 31 28 27 24 23 22 inc/dec CB delay Update CB delay RDH 21 20 14 REG RESERVED 13 12 11 10 TRTP RES 9 TCL 8 7 B8 0 DQS gating offset 0 0 0 0 0 * 0 * * 0 rw rw rw rw r rw r rw rw rw 31: 28 Set to ‘1’ to increment checkbits byte delay, set to ‘0’ to decrement delay 27: 24 Set to ‘1’ to update checkbits byte delay 23: 22 Read delay high bits, setting this field to N adds 4 x N read delay cycles 21 Registered memory (1 cycle extra latency on control signals) 20: 14 Reserved 13 SDRAM read-to-precharge timing, tRTP will be equal to field value + 2 DDR-clock cycles. 12: 11 Reserved 10: 9 SDRAM CAS latency timing. CL will be equal to field value + 3 DDR-clock cycles. Note: You must reprogram the memory’s MR register after changing this value 8 Enables address generation for DDR2 chips with eight banks 1=addressess generation for eight banks 0=address generation for four banks 7: 0 Number of half clock cycles for which the DQS input signal will be active after a read command is given. After this time the DQS signal will be gated off to prevent latching of faulty data. Only valid if the dqsgating generic is enabled. GRIP, Apr 2018, Version 2018.1 198 www.cobham.com/gaisler GRLIB IP Core 22.4.5 DDR2 SDRAM Configuration Register 5 Table 221. 0x10 - DDR2CFG5 - DDR2 SDRAM configuration register 5 31 30 R 28 27 26 25 18 17 16 15 14 TRP RES TRFC 0 * 0 0 r rw r rw ODT 11 10 DS RESERVED 0 0 rw rw 8 7 5 4 0 TRCD RESERVED TRAS 0 * 0 0 r rw r rw 31 Reserved 30: 28 SDRAM tRP timing. tRP will be equal to 2 + field value DDR-clock cycles 27: 26 Reserved 25: 18 SDRAM tRFC timing. tRFC will be equal to 3 + field-value DDR-clock cycles. 17: 16 SDRAM-side on-die termination setting (0=disabled, 1-3=75/150/50 ohm) Note: You must reprogram the EMR1 register after changing this value. 15 SDRAM-side output drive strength control (0=full strength, 1=half strength) Note: You must reprogram the EMR1 register after changing this value 14: 11 Reserved 10: 8 SDRAM RAS-to-CAS delay (TRCD). tRCD will be equal to field value + 2 DDR-clock cycles 7: 5 Reserved 4: 0 SDRAM RAS to precharge timing. TRAS will be equal to 2+ field value DDR-clock cycles 22.4.6 DDR2 FT Configuration Register Table 222. 0x20 - DDR2FTCFG - DDR2 FT configuration register 31 20 19 Diag data read error location DDERR 0 r 31: 20 18 16 15 8 7 5 DATAMUX 4 CEM 3 2 BAUPD BAEN 1 0 CODE EDEN DM RESERVED 0 0 0 0 0 0 0 0 0 r rw r rw rw rw rw rw rw Bit field describing location of corrected errors for last diagnostic data read (read-only) One bit per byte lane in 64+32-bit configuration 19 Set high if last diagnostic data read contained an uncorrectable error (read-only) 18: 16 Data width, read-only field. 001=16+8, 010=32+16, 011=64+32 bits 15: 8 Reserved 7: 5 Data mux control, setting this nonzero switches in the upper checkbit half with another data lane. For 64-bit interface 000 = no switching 001 = Data bits 15:0, 010 = Data bits 31:16, 011: Data bits 47:32, 100: Data bits 63:48, 101 = Checkbits 79:64, 110,111 = Undefined 4 If set high, the correctable error signal is masked out. 3 Enable automatic boundary shifting on write 2 Enable the code boundary 1 Code selection, 0=Code A (64+32/32+16/16+8), 1=Code B (64+16/32+8) 0 EDAC Enable GRIP, Apr 2018, Version 2018.1 199 www.cobham.com/gaisler GRLIB IP Core 22.4.7 DDR2 FT Diagnostic Address Table 223.0x24 - DDR2FTDA - DDR2 FT Diagnostic Address 31 2 1 0 MEMORY ADDRESS RESERVED 0 0 rw r 31: 3 Address to memory location for checkbit read/write, 64/32-bit aligned for checkbits/data 1: 0 Reserved (address bits always 0 due to alignment) 22.4.8 DDR2 FT Diagnostic Checkbits Table 224. 0x28 - DDR2FTDC - DDR2 FT Diagnostic Checkbits 31 24 23 CHECKBITS D 16 15 CHECKBITS C 8 CHECKBITS B 7 0 CHECKBITS A * * * 0 rw rw rw rw 31: 24 Checkbits for part D of 64-bit data word (undefined for code B) 23: 16 Checkbits for part C of 64-bit data word (undefined for code B) 15: 8 Checkbits for part B of 64-bit data word 7: 0 Checkbits for part A of 64-it data word. 22.4.9 DDR2 FT Diagnostic Data Table 225. 0x2C - DDR2FTDD - DDR2 FT Diagnostic Data 31 0 DATA BITS * r 31: 0 Uncorrected data bits for 32-bit address set in DDR2FTDA 22.4.10 DDR2 FT Boundary Address Register Table 226. 0x30 - DDR2FTBND - DDR2 FT Boundary Address Register 31 22.5 3 2 0 CHECKBIT CODE BOUNDARY ADDRESS R 0 0 rw r 31: 3 Code boundary address, 64-bit aligned 2: 0 Zero due to alignment Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x02E. The revision decribed in this document is revision 1. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. GRIP, Apr 2018, Version 2018.1 200 www.cobham.com/gaisler GRLIB IP Core 22.6 Configuration options Table 227 shows the configuration options of the core (VHDL generics). Table 227.Configuration options Generic Function Allowed range Default fabtech PHY technology selection virtex4, virtex5, stratix3 virtex4 memtech Technology selection for DDR FIFOs inferred, virtex2, virtex4, spartan3e, altera inferred hindex AHB slave index 0 - NAHBSLV-1 0 haddr ADDR field of the AHB BAR0 defining SDRAM area. Default is 0xF0000000 - 0xFFFFFFFF. 0 - 16#FFF# 16#000# hmask MASK field of the AHB BAR0 defining SDRAM area. 0 - 16#FFF# 16#F00# ioaddr ADDR field of the AHB BAR1 defining I/O address space where DDR control register is mapped. 0 - 16#FFF# 16#000# iomask MASK field of the AHB BAR1 defining I/O address space 0 - 16#FFF# 16#FFF# ddrbits Data bus width of external DDR memory 16, 32, 64 16 MHz DDR clock input frequency in MHz. 10 - 200 100 clkmul, clkdiv The DDR input clock is multiplied with the clkmul generic and divided with clkdiv to create the final DDR clock 2 - 32 2 rstdel Clock reset delay in micro-seconds. 1 - 1023 200 col Default number of column address bits 9 - 12 9 Mbyte Default memory chip select bank size in Mbyte 8 - 1024 16 pwron Enable SDRAM at power-on initialization 0-1 0 oepol Polarity of bdrive and vbdrive signals. 0=active low, 1=active high 0-1 0 ahbfreq Frequency in MHz of the AHB clock domain 1 - 1023 50 readdly Additional read latency cycles (used to increase calibration range) 0-3 1 TRFC Reset value for the tRFC timing parameter in ns. 75-155 130 ddelayb0* Input data delay for bit[7:0] 0-63 0 ddelayb1* Input data delay for bit[15:8] 0-63 0 ddelayb2* Input data delay for bit[23:16] 0-63 0 ddelayb3* Input data delay for bit[31:24] 0-63 0 ddelayb4* Input data delay for bit[39:32] 0-63 0 ddelayb5* Input data delay for bit[47:40] 0-63 0 ddelayb6* Input data delay for bit[55:48] 0-63 0 ddelayb7* Input data delay for bit[63:56] 0-63 0 cbdelayb0* Input data delay for checkbit[7:0] 0-63 0 cbdelayb1* Input data delay for checkbit[15:8] 0-63 0 cbdelayb2* Input data delay for checkbit[23:16] 0-63 0 cbdelayb3* Input data delay for checkbit[31:24] 0-63 0 numidelctrl* Number of IDELAYCTRL the core will instantiate - 4 norefclk* Set to 1 if no 200 MHz reference clock is connected to clkref200 input. 0-1 0 odten Enable odt: 0 = Disabled, 1 = 75Ohm, 2 =150Ohm, 3 = 50Ohm 0-3 0 GRIP, Apr 2018, Version 2018.1 201 www.cobham.com/gaisler GRLIB IP Core Table 227.Configuration options Generic Function Allowed range Default rskew** Set the phase relationship between the DDR controller clock and the input data sampling clock. Sets the phase in ps. 0 - 9999 0 octen** Enable on chip termination: 1 = enabled, 0 = disabled 0-1 0 dqsgating*** Enable gating of DQS signals when doing reads. 1 = enable, 0 = disable 0-1 0 nosync Disable insertion of synchronization registers between 0-1 AHB clock domain and DDR clock domain. This can be done if the AHB clock’s rising edges always are in phase with a rising edge on the DDR clock. If this generic is set to 1 the clkmul and clkdiv generics should be equal. Otherwise the DDR controller may scale the incoming clock and loose the clocks’ edge alignment in the process. 0 eightbanks Enables address generation for DDR2 chips with eight banks. The DDR_BA is extended to 3 bits if set to 1. 0-1 0 dqsse Single-ended DQS. The value of this generic is written to bit 10 in the memory’s Extended Mode register. If this bit is 1 DQS is used in a single-ended mode. Currently this bit should only, and must be, set to 1 when the Stratix2 DDR2 PHY is used. This is the only PHY that supports single ended DQS without modification. 0-1 0 burstlen DDR access burst length in 32-bit words 8,16,32,..,256 8 ahbbits AHB bus width 32,64,128,256 AHBDW ft Enable fault-tolerant version 0-1 0 ftbits Extra DDR data bits used for checkbits 0,8,16,32 0 bigmem Big memory support, changes the range of supported total memory bank sizes from 8MB-1GB to 32MB-4GB 0-1 0 raspipe Enables an extra pipeline stage in the address decoding to improve timing at the cost of one DDR-cycle latency 0-1 0 * only available in Virtex4/5 implementation.  ** only available in Altera and Spartan3 implementations.  *** only available on Nextreme/eASIC implementations 22.7 Implementation 22.7.1 Technology mapping The core has two technology mapping VHDL generics: memtech and fabtech. The VHDL generic memtech controls the technology used for memory cell implementation. The VHDL generic fabtech controls the technology used in the PHY implementation. See the GRLIB Users’s Manual for available settings. 22.7.2 FPGA support Complete PHY:s for a number of FPGA technologies are included in the distribution, see table below. Unless otherwise noted these have been only functionally tested on evaluation board in lab environment and detailed timing analysis has not been performed. Note also that some of the FPGA phy:s use simplified sampling approaches which may require the memory timing to be better than the JEDEC standard specifies. Scripts for post-layout static timing analysis are not included. Because these PHY:s are based on dedicated hard macros with fixed placement in the FPGA:s pad structure, just a minimal set of constraints are normally neccessary for synthesis purposes. GRIP, Apr 2018, Version 2018.1 202 www.cobham.com/gaisler GRLIB IP Core Some PHY:s support instantiation without built-in pads, to separate the pads from the PHY the internal ddr2spax entity and the phy must be instantiated manually. Table 228.FPGA DDR2 PHYs included in GRLIB Technology fabtech Read clock method Built-in pads Stratix 2 stratix2 Tech intrinsics (DQS based) Yes Yes Stratix 3 stratix3 Tunable static shift Spartan 3 spartan3 Clock feedback loop + static shift Yes Virtex4,5,6 virtex4, virtex5, virtex6 Fixed clock, DQ shifted using IDELAY Yes or No Spartan6 spartan6 Yes or No Fixed clock, DQ shifted using IDELAY 22.7.3 RAM usage The FIFOs in the core are implemented with the syncram_2p (with separate clock for each port) component found in the technology mapping library (TECHMAP). The number of RAMs used for the FIFO implementation depends om the DDR data width, set by the ddrbits VHDL generic, and the AHB bus width in the system. The RAM block usage is tabulated below for the default burst length of 8 words. If the burst length is doubled, the depths for all the RAMs double as well but the count and width remain the same. Table 229.Block-RAM usage for default burst length Write FIFO block-RAM usage Read-FIFO block-RAM usage Count Depth Width Count Depth Width Total RAM count 32 1 16 32 1 8 32 2 16 64 2 8 32 2 4 32 4 16 128 4 4 32 4 2 32 8 16 256 8 2 32 8 1 32 16 32 32 2 8 32 1 4 64 3 32 64 2 8 32 1 4 64 3 32 128 4 4 32 2 2 64 6 32 256 8 2 32 4 1 64 12 64 32 4 4 32 1 2 128 5 64 64 4 4 32 1 2 128 5 64 128 4 4 32 1 2 128 5 64 256 8 2 32 2 1 128 10 DDR width AHB width 16 22.7.4 Xilinx Virtex-specific issues The Xilinx tools require one IDELAYCTRL macro to be instantiated in every region where the IDELAY feature is used. Since the DDR2 PHY uses the IDELAY on every data (DQ) pin, this affects the DDR2 core. For this purpose, the core has a numidelctrl generic, controlling how many IDELAYCTRL’s get instantiated in the PHY. The tools allow for two ways to do this instantiation: • Instantiate the same number of IDELAYCTRL as the number of clock regions containing DQ pins and place the instances manually using UCF LOC constraints. • Instantiate just one IDELAYCTRL, which the ISE tools will then replicate over all regions. GRIP, Apr 2018, Version 2018.1 203 www.cobham.com/gaisler GRLIB IP Core The second solution is the simplest, since you just need to set the numidelctrl to 1 and no extra constraints are needed. However, this approach will not work if IDELAY is used anywhere else in the FPGA design. For more information on IDELAYCTRL, see Xilinx Virtex4/5 User’s Guide. 22.7.5 Design tools To run the design in Altera Quartus 7.2 you have to uncomment the lines in the .qsf file that assigns the MEMORY_INTERFACE_DATA_PIN_GROUP for the DDR2 interface. These group assignments result in error when Altera Quartus 8.0 is used. GRIP, Apr 2018, Version 2018.1 204 www.cobham.com/gaisler GRLIB IP Core 22.8 Signal descriptions Table 230 shows the interface signals of the core (VHDL ports). Table 230.Signal descriptions Signal name Type Function Active RST_DDR Input Reset input for the DDR PHY Low RST_AHB Input Reset input for AHB clock domain Low CLK_DDR Input DDR input Clock - CLK_AHB Input AHB clock - CLKREF200 Input 200 MHz reference clock - LOCK Output DDR clock generator locked High CLKDDRO Internal DDR clock output after clock multiplication CLKDDRI Clock input for the internal DDR clock domain. Must be connected to CLKDDRO. AHBSI Input AHB slave input signals - AHBSO Output AHB slave output signals - DDR_CLK[2:0] Output DDR memory clocks (positive) High DDR_CLKB[2:0] Output DDR memory clocks (negative) Low DDR_CLK_FB_OUT Output DDR data synchronization clock, connect this to a signal path with equal length of the DDR_CLK trace + DDR_DQS trace - DDR_CLK_FB Input DDR data synchronization clock, connect this to the other end of the signal path connected to DDR_CLK_FB_OUT - DDR_CKE[1:0] Output DDR memory clock enable High DDR_CSB[1:0] Output DDR memory chip select Low DDR_WEB Output DDR memory write enable Low DDR_RASB Output DDR memory row address strobe Low DDR_CASB Output DDR memory column address strobe Low DDR_DM[(DDRBITS+FTBITS)/8-1:0] Output DDR memory data mask Low DDR_DQS[(DDRBITS+FTBITS)/8-1:0] Bidir DDR memory data strobe Low DDR_DQSN[(DDRBITS+FTBITS)/8-1:0] Bidir DDR memory data strobe (inverted) High DDR_AD[13:0] Output DDR memory address bus Low DDR_BA[2 or 1:0] 3) Output DDR memory bank address Low DDR_DQ[DDRBITS+FTBITS-1:0] BiDir DDR memory data bus - DDR_ODT[1:0] Output DDR memory odt Low 1) see GRLIB IP Library User’s Manual  2) Polarity selected with the oepol generic 3) DDR_BA[2:0] if the eightbanks generic is set to 1 else DDR_BA[1:0] 4) Only used on Virtex4/5 5) Only used on Spartan3 GRIP, Apr 2018, Version 2018.1 205 www.cobham.com/gaisler GRLIB IP Core 22.9 Library dependencies Table 231 shows libraries used when instantiating the core (VHDL libraries). Table 231.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals, component Memory bus signals definitions, component declaration 22.10 Component declaration component ddr2spa generic ( fabtech : integer := 0; memtech : integer := 0; hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#f00#; ioaddr : integer := 16#000#; iomask : integer := 16#fff#; MHz : integer := 100; clkmul : integer := 2; clkdiv : integer := 2; col : integer := 9; Mbyte : integer := 16; rstdel : integer := 200; pwron : integer := 0; oepol : integer := 0; ddrbits : integer := 16; ahbfreq : integer := 50; readdly : integer := 1; ddelayb0: integer := 0; ddelayb1: integer := 0; ddelayb2: integer := 0; ddelayb3: integer := 0; ddelayb4: integer := 0; ddelayb5: integer := 0; ddelayb6: integer := 0; ddelayb7: integer := 0 ); port ( rst_ddr : in std_ulogic; rst_ahb : in std_ulogic; clk_ddr : in std_ulogic; clk_ahb : in std_ulogic; clkref200 : in std_ulogic; lock : out std_ulogic;-- DCM locked clkddro : out std_ulogic;-- DCM locked clkddri : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; ddr_clk : out std_logic_vector(2 downto 0); ddr_clkb : out std_logic_vector(2 downto 0); ddr_cke : out std_logic_vector(1 downto 0); ddr_csb : out std_logic_vector(1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs ddr_dqsn : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (13 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (ddrbits-1 downto 0); -- ddr data ddr_odt : out std_logic_vector(1 downto 0) -- odt ); end component; GRIP, Apr 2018, Version 2018.1 206 www.cobham.com/gaisler GRLIB IP Core 22.11 Instantiation This example shows how the core can be instantiated. The DDR SDRAM controller decodes SDRAM area at 0x40000000 - 0x7FFFFFFF. The DDR2 SDRAM registers are mapped into AHB I/O space on address (AHB I/O base address + 0x100). library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.tech.all; library gaisler; use gaisler.memctrl.all; entity ddr_Interface is port ( ddr_clk : out std_logic_vector(2 downto 0); ddr_clkb : out std_logic_vector(2 downto 0); ddr_cke : out std_logic_vector(1 downto 0); ddr_csb : out std_logic_vector(1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs ddr_dqsn : inout std_logic_vector (7 downto 0); -- ddr dqsn ddr_ad : out std_logic_vector (13 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data ddr_odt : out std_logic_vector (1 downto 0) -- ddr odt ); end; architecture rtl of mctrl_ex is -- AMBA bus signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal clkml, lock, clk_200, signal clk_200 : std_ulogic; -- 200 MHz reference clock signal ddrclkin, ahbclk : std_ulogic; -- DDR input clock and AMBA sys clock signal rstn : std_ulogic; -- Synchronous reset signal signal reset : std_ulogic; -- Asynchronous reset signal begin -- DDR controller ddrc : ddr2spa generic map ( fabtech => virtex4, ddrbits => 64, memtech => memtech, hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => 1, MHz => 100, col => 9, Mbyte => 32, ahbfreq => 50, ddrbits => 64, readdly => 1, ddelayb0 => 0, ddelayb1 => 0, ddelayb2 => 0, ddelayb3 => 0, ddelayb4 => 0, ddelayb5 => 0, ddelayb6 => 0, ddelayb7 => 0) port map ( reset, rstn, ddrclkin, ahbclk, clk_200, lock, clkml, clkml, ahbsi, ahbso(4), ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq, ddr_odt); GRIP, Apr 2018, Version 2018.1 207 www.cobham.com/gaisler GRLIB IP Core 23 DIV32 - Signed/unsigned 64/32 divider module 23.1 Overview The divider module performs signed/unsigned 64-bit by 32-bit division. It implements the radix-2 non-restoring iterative division algorithm. The division operation takes 36 clock cycles. The divider leaves no remainder. The result is rounded towards zero. Negative result, zero result and overflow (according to the overflow detection method B of SPARC V8 Architecture manual) are detected. 23.2 Operation The division is started when ‘1’ is samples on DIVI.START on positive clock edge. Operands are latched externally and provided on inputs DIVI.Y, DIVI.OP1 and DIVI.OP2 during the whole operation. The result appears on the outputs during the clock cycle following the clock cycle after the DIVO.READY was asserted. Asserting the HOLD input at any time will freeze the operation, until HOLDN is de-asserted. 23.3 Implementation 23.3.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core will use asynchronous reset for all registers if the GRLIB config package setting grlib_async_reset_enable is set. 23.4 Configurations options Core has only one VHDL generic, scantest, that should be set to 1 if GRLIB has been configured to use asynchronous reset. GRIP, Apr 2018, Version 2018.1 208 www.cobham.com/gaisler GRLIB IP Core 23.5 Signal descriptions Table 232 shows the interface signals of the core (VHDL ports). Table 232.Signal declarations Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - HOLDN N/A Input Hold Low DIVI Y[32:0] Input Dividend - MSB part High Y[32] - Sign bit Y[31:0] - Dividend MSB part in 2’s complement format OP1[32:0] Dividend - LSB part High OP1[32] - Sign bit OP1[31:0] - Dividend LSB part in 2’s complement format DIVO FLUSH Flush current operation High SIGNED Signed division High START Start division High The result is available one clock after the ready signal is asserted. High READY Output NREADY The result is available three clock cycles, assum- High ing hold=HIGH, after the nready signal is asserted. ICC[3:0] Condition codes High ICC[3] - Negative result ICC[2] - Zero result ICC[1] - Overflow ICC[0] - Not used. Always ‘0’. RESULT[31:0] 23.6 Result High TESTEN N/A Input Test enable (only used together with async. reset) High TESTRST N/A Input Test reset (only used together with async. reset) Low Library dependencies Table 233 shows libraries used when instantiating the core (VHDL libraries). Table 233.Library dependencies 23.7 Library Package Imported unit(s) Description GAISLER ARITH Signals, component Divider module signals, component declaration Component declaration The core has the following component declaration. component div32 port ( rst : in clk : in holdn : in std_ulogic; std_ulogic; std_ulogic; GRIP, Apr 2018, Version 2018.1 209 www.cobham.com/gaisler GRLIB IP Core divi divo : in div32_in_type; : out div32_out_type ); end component; 23.8 Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use gaisler.arith.all; . . . signal divi signal divo : div32_in_type; : div32_out_type; begin div0 : div32 port map (rst, clk, holdn, divi, divo); end; GRIP, Apr 2018, Version 2018.1 210 www.cobham.com/gaisler GRLIB IP Core 24 DSU3 - LEON3 Hardware Debug Support Unit 24.1 Overview To simplify debugging on target hardware, the LEON3 processor implements a debug mode during which the pipeline is idle and the processor is controlled through a special debug interface. The LEON3 Debug Support Unit (DSU) is used to control the processor during debug mode. The DSU acts as an AHB slave and can be accessed by any AHB master. An external debug host can therefore access the DSU through several different interfaces. Such an interface can be a serial UART (RS232), JTAG, PCI, USB or Ethernet. The DSU supports multi-processor systems and can handle up to 16 processors. LEON3 LEON3 Processor(s) LEON3 Processor LEON3 Processor(s) Processor(s) Debug I/F Debug Support Unit AHB Slave I/F AHB Master I/F AMBA AHB BUS RS232 PCI Ethernet JTAG USB DEBUG HOST Figure 59. LEON3/DSU Connection 24.2 Operation Through the DSU AHB slave interface, any AHB master can access the processor registers and the contents of the instruction trace buffer. The DSU control registers can be accessed at any time, while the processor registers and caches can only be accessed when the processor has entered debug mode. In debug mode, the processor pipeline is held and the processor state can be accessed by the DSU. Entering the debug mode can occur on the following events: • executing a breakpoint instruction (ta 1) • integer unit hardware breakpoint/watchpoint hit (trap 0xb) • rising edge of the external break signal (DSUBRE) • setting the break-now (BN) bit in the DSU control register • a trap that would cause the processor to enter error mode • occurrence of any, or a selection of traps as defined in the DSU control register • after a single-step operation • one of the processors in a multiprocessor system has entered the debug mode • DSU AHB breakpoint or watchpoint hit GRIP, Apr 2018, Version 2018.1 211 www.cobham.com/gaisler GRLIB IP Core The debug mode can only be entered when the debug support unit is enabled through an external signal (DSUEN). For DSU break (DSUBRE), and the break-now BN bit, to have effect the Break-on-IUwatchpoint (BW) bit must be set in the DSU control register. This bit is set when DSUBRE is active after reset and should also be set by debug monitor software when initializing the DSU. When the debug mode is entered, the following actions are taken: • PC and nPC are saved in temporary registers (accessible by the debug unit) • an output signal (DSUACT) is asserted to indicate the debug state • the timer unit is (optionally) stopped to freeze the LEON timers and watchdog The instruction that caused the processor to enter debug mode is not executed, and the processor state is kept unmodified. Execution is resumed by clearing the BN bit in the DSU control register or by deasserting DSUEN. The timer unit will be re-enabled and execution will continue from the saved PC and nPC. Debug mode can also be entered after the processor has entered error mode, for instance when an application has terminated and halted the processor. The error mode can be reset and the processor restarted at any address. When a processor is in the debug mode, an access to ASI diagnostic area is forwarded to the IU which performs access with ASI equal to value in the DSU ASI register and address consisting of 20 LSB bits of the original address. 24.3 AHB trace buffer The AHB trace buffer consists of a circular buffer that stores AHB data transfers, the monitored AHB bus is either the same bus as the DSU AHB slave interface is connected to, or a completely separate bus. The address, data and various control signals of the AHB bus are stored and can be read out for later analysis. The trace buffer is 128, 160 or 224 bits wide, depending on the AHB bus width. The way information stored is indicated in the table below: Table 234.AHB Trace buffer data allocation Bits Name Definition 223:160 Load/Store data AHB HRDATA/HWDATA(127:64) 159:129 Load/Store data AHB HRDATA/HWDATA(63:32) 127 AHB breakpoint hit Set to ‘1’ if a DSU AHB breakpoint hit occurred. 126 - Not used 125:96 Time tag DSU time tag counter 95:80 - Not used 79 Hwrite AHB HWRITE 78:77 Htrans AHB HTRANS 76:74 Hsize AHB HSIZE 73:71 Hburst AHB HBURST 70:67 Hmaster AHB HMASTER 66 Hmastlock AHB HMASTLOCK 65:64 Hresp AHB HRESP 63:32 Load/Store data AHB HRDATA/HWDATA(31:0) 31:0 Load/Store address AHB HADDR In addition to the AHB signals, the DSU time tag counter is also stored in the trace. The trace buffer is enabled by setting the enable bit (EN) in the trace control register. Each AHB transfer is then stored in the buffer in a circular manner. The address to which the next transfer is written is held in the trace buffer index register, and is automatically incremented after each transfer. TracGRIP, Apr 2018, Version 2018.1 212 www.cobham.com/gaisler GRLIB IP Core ing is stopped when the EN bit is reset, or when a AHB breakpoint is hit. Tracing is temporarily suspended when the processor enters debug mode, unless the trace force bit (TF) in the trace control register is set. If the trace force bit is set, the trace buffer is activated as long as the enable bit is set. The force bit is reset if an AHB breakpoint is hit and can also be cleared by software. Note that neither the trace buffer memory nor the breakpoint registers (see below) can be read/written by software when the trace buffer is enabled. The DSU has an internal time tag counter and this counter is frozen when the processor enters debug mode. When AHB tracing is performed in debug mode (using the trace force bit) it may be desirable to also enable the time tag counter. This can be done using the timer enable bit (TE). Note that the time tag is also used for the instruction trace buffer and the timer enable bit should only be set when using the DSU as an AHB trace buffer only, and not when performing profiling or software debugging. The timer enable bit is reset on the same events as the trace force bit. 24.3.1 AHB trace buffer filters The DSU can be implemented with filters that can be applied to the AHB trace buffer, breakpoints and watchpoints. If implemented, these filters are controlled via the AHB trace buffer filter control and AHB trace buffer filter mask registers. The fields in these registers allows masking access characteristics such as master, slave, read, write and address range so that accesses that correspond to the specified mask are not written into the trace buffer. Address range masking is done using the second AHB breakpoint register set. The values of the LD and ST fields of this register has no effect on filtering. 24.3.2 AHB statistics The DSU can be implemented to generate statistics from the traced AHB bus. When statistics collection is enabled the DSU will assert outputs that are suitable to connect to a LEON3 statistics unit (L3STAT). The statistical outputs can be filtered by the AHB trace buffer filters, this is controlled by the Performance counter Filter bit (PF) in the AHB trace buffer filter control register. The DSU can collect data for the events listed in table 235 below. Table 235.AHB events Event Description Note idle HTRANS=IDLE Active when HTRANS IDLE is driven on the AHB slave inputs and slave has asserted HREADY. busy HTRANS=BUSY Active when HTRANS BUSY is driven on the AHB slave inputs and slave has asserted HREADY. nseq HTRANS=NONSEQ Active when HTRANS NONSEQ is driven on the AHB slave inputs and slave has asserted HREADY. seq HTRANS=SEQ Active when HTRANS SEQUENTIAL is driven on the AHB slave inputs and slave has asserted HREADY. read Read access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and the HWRITE input is low. write Write access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and the HWRITE input is high. hsize[5:0] Transfer size Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and HSIZE is BYTE (hsize[0]), HWORD (HSIZE[1]), WORD (hsize[2]), DWORD (hsize[3]), 4WORD hsize[4], or 8WORD (hsize[5]). ws Wait state Active when HREADY input to AHB slaves is low and AMBA response is OKAY. retry RETRY response Active when master receives RETRY response split SPLIT response Active when master receives SPLIT response GRIP, Apr 2018, Version 2018.1 213 www.cobham.com/gaisler GRLIB IP Core Table 235.AHB events Event Description Note spdel SPLIT delay Active during the time a master waits to be granted access to the bus after reception of a SPLIT response. The core will only keep track of one master at a time. This means that when a SPLIT response is detected, the core will save the master index. This event will then be active until the same master is re-allowed into bus arbitration and is granted access to the bus. This also means that the delay measured will include the time for re-arbitration, delays from other ongoing transfers and delays resulting from other masters being granted access to the bus before the SPLIT:ed master is granted again after receiving SPLIT complete. If another master receives a SPLIT response while this event is active, the SPLIT delay for the second master will not be measured. locked 24.4 Locked access Active while the HMASTLOCK signal is asserted on the AHB slave inputs. Instruction trace buffer The instruction trace buffer consists of a circular buffer that stores executed instructions. The instruction trace buffer is located in the processor, and read out via the DSU. The trace buffer is 128 bits wide, the information stored is indicated in the table below: Table 236.Instruction trace buffer data allocation Bits Name Definition 127 - Unused 126 Multi-cycle instruction Set to ‘1’ on the second and third instance of a multi-cycle instruction (LDD, ST or FPOP) 125:96 Time tag The value of the DSU time tag counter 95:64 Load/Store parameters Instruction result, Store address or Store data 63:34 Program counter Program counter (2 lsb bits removed since they are always zero) 33 Instruction trap Set to ‘1’ if traced instruction trapped 32 Processor error mode Set to ‘1’ if the traced instruction caused processor error mode 31:0 Opcode Instruction opcode During tracing, one instruction is stored per line in the trace buffer with the exception of multi-cycle instructions. Multi-cycle instructions are entered two or three times in the trace buffer. For store instructions, bits [95:64] correspond to the store address on the first entry and to the stored data on the second entry (and third in case of STD). Bit 126 is set on the second and third entry to indicate this. A double load (LDD) is entered twice in the trace buffer, with bits [95:64] containing the loaded data. Bit 126 is set for the second entry. When the processor enters debug mode, tracing is suspended. The trace buffer and the trace buffer control register can be read and written while the processor is in the debug mode. During the instruction tracing (processor in normal mode) the trace buffer and trace buffer control register 0 can not be written. If the two-port trace buffer is enabled (refer to the tbuf generic in section 80.16), then the trace buffer can be read contextually to the instruction tracing (processor in normal mode). The traced instructions can optionally be filtered on instruction types. Which instructions are traced is defined in the instruction trace register [31:28], as defined in the table below: GRIP, Apr 2018, Version 2018.1 214 www.cobham.com/gaisler GRLIB IP Core Table 237.Trace filter operation Trace filter Instructions traced 0x0 All instructions 0x1 SPARC Fomat 2 instructions 0x2 Control-flow changes. All Call, branch and trap instructions including branch targets 0x4 SPARC Format 1 instructions (CALL) 0x8 SPARC Format 3 instructions except LOAD or STORE 0xC SPARC Format 3 LOAD or STORE instructions 0xD SPARC Format 3 LOAD or STORE instructions to alternate space 0xE SPARC Format 3 LOAD or STORE instructions to alternate space 0x80 - 0xFF with ASI last digit base filtering It is also possible to filter traced instructions based on the program counter value. This option is combined with the filtering option if an additional filtering mechanism is activated from Table 237. Refer to section 24.6.13 for detailed information. 24.5 DSU memory map The DSU memory map can be seen in table 238 below. In a multiprocessor systems, the register map is duplicated and address bits 27 - 24 are used to index the processor. Note: The DSU memory interface is intended to be accessed by a debug monitor. Software running on the LEON processors should not access the DSU interface. Registers, such as ASR registers, may not have all fields available via the DSU interface Table 238.DSU memory map Address offset Register 0x000000 DSU control register 0x000008 Time tag counter 0x000020 Break and Single Step register 0x000024 Debug Mode Mask register 0x000040 AHB trace buffer control register 0x000044 AHB trace buffer index register 0x000048 AHB trace buffer filter control register 0x00004c AHB trace buffer filter mask register 0x000050 AHB breakpoint address 1 0x000054 AHB mask register 1 0x000058 AHB breakpoint address 2 0x00005c AHB mask register 2 0x100000 - 0x10FFFF Instruction trace buffer (..0: Trace bits 127 - 96, ..4: Trace bits 95 - 64, ..8: Trace bits 63 - 32, ..C : Trace bits 31 - 0) 0x110000 Instruction Trace buffer control register 0 0x110004 Instruction Trace buffer control register 1 0x200000 - 0x210000 AHB trace buffer (..0: Trace bits 127 - 96, ..4: Trace bits 95 - 64, ..8: Trace bits 63 - 32, ..C : Trace bits 31 - 0) 0x300000 - 0x3007FC IU register file, port1 (%asr16.dpsel = 0) 0x300800 - 0x300FFC IU register file check bits (LEON3FT only) IU register file, port 2 (%asr16.dpsel = 1) GRIP, Apr 2018, Version 2018.1 215 www.cobham.com/gaisler GRLIB IP Core Table 238.DSU memory map Address offset Register 0x301000 - 0x30107C FPU register file 0x301800 - 0x30187C FPU register file check bits (LEON3FT only) 0x400000 - 0x4FFFFC IU special purpose registers 0x400000 Y register 0x400004 PSR register 0x400008 WIM register 0x40000C TBR register 0x400010 PC register 0x400014 NPC register 0x400018 FSR register 0x40001C CPSR register 0x400020 DSU trap register 0x400024 DSU ASI register 0x400040 - 0x40007C ASR16 - ASR31 (when implemented) 0x700000 - 0x7FFFFC ASI diagnostic access (ASI = value in DSU ASI register, address = address[19:0]) ASI = 0x9 : Local instruction RAM, ASI = 0xB : Local data RAM ASI = 0xC : Instruction cache tags, ASI = 0xD : Instruction cache data ASI = 0xE : Data cache tags, ASI = 0xF : Data cache data ASI = 0x1E : Separate snoop tags The addresses of the IU registers depends on how many register windows has been implemented: 24.6 • %on : 0x300000 + (((psr.cwp * 64) + 32 + n*4) mod (NWINDOWS*64)) • %ln : 0x300000 + (((psr.cwp * 64) + 64 + n*4) mod (NWINDOWS*64)) • %in : 0x300000 + (((psr.cwp * 64) + 96 + n*4) mod (NWINDOWS*64)) • %gn : 0x300000 + (NWINDOWS*64) + n*4 • %fn : 0x301000 + n*4 DSU registers 24.6.1 DSU control register The DSU is controlled by the DSU control register: Table 239.0x000000 - CTRL - DSU control register 31 12 11 10 RESERVED 31: 12 9 8 7 6 5 4 3 2 1 0 PW HL PE EB EE DM BZ BX BS BW BE TE 0 0 0 0 * * r r rw rw r r * r * * * * * rw rw rw rw rw rw Reserved 11 Power down (PW) - Returns ‘1’ when processor is in power-down mode. 10 Processor halt (HL) - Returns ‘1’ on read when processor is halted. If the processor is in debug mode, setting this bit will put the processor in halt mode. 9 Processor error mode (PE) - returns ‘1’ on read when processor is in error mode, else ‘0’. If written with ‘1’, it will clear the error and halt mode. 8 External Break (EB) - Value of the external DSUBRE signal (read-only) 7 External Enable (EE) - Value of the external DSUEN signal (read-only) 6 Debug mode (DM) - Indicates when the processor has entered debug mode (read-only). 5 Break on error traps (BZ) - if set, will force the processor into debug mode on all except the following traps: priviledged_instruction, fpu_disabled, window_overflow, window_underflow, asynchronous_interrupt, ticc_trap. GRIP, Apr 2018, Version 2018.1 216 www.cobham.com/gaisler GRLIB IP Core Table 239.0x000000 - CTRL - DSU control register 4 Break on trap (BX) - if set, will force the processor into debug mode when any trap occurs. 3 Break on S/W breakpoint (BS) - if set, debug mode will be forced when an breakpoint instruction (ta 1) is executed. 2 Break on IU watchpoint (BW) - if set, debug mode will be forced on a IU watchpoint (trap 0xb). 1 Break on error (BE) - if set, will force the processor to debug mode when the processor would have entered error condition (trap in trap). 0 Trace enable (TE) - Enables instruction tracing. If set the instructions will be stored in the trace buffer. Remains set when then processor enters debug or error mode 24.6.2 DSU Break and Single Step register This register is used to break or single step the processor(s). This register controls all processors in a multi-processor system, and is only accessible in the DSU memory map of processor 0. Table 240.0x000020 - BRSS - BRSS - DSU Break and Single Step register 31 16 15 SS[15:0] 0 BN[15:0] 31: 16 Single step (SSx) - if set, the processor x will execute one instruction and return to debug mode. The bit remains set after the processor goes into the debug mode. As an exception, if the instruction is a branch with the annul bit set, and if the delay instruction is effectively annulled, the processor will execute the branch, the annulled delay instruction and the instruction thereafter before returning to debug mode. 15: 0 Break now (BNx) -Force processor x into debug mode if the Break on watchpoint (BW) bit in the processors DSU control register is set. If cleared, the processor x will resume execution. 24.6.3 DSU Debug Mode Mask Register When one of the processors in a multiprocessor LEON3 system enters the debug mode the value of the DSU Debug Mode Mask register determines if the other processors are forced in the debug mode. This register controls all processors in a multi-processor system, and is only accessible in the DSU memory map of processor 0. Table 241.0x000024 - DBGM - DSU Debug Mode Mask register 31 16 15 DM[15:0] 0 ED[15:0] 31: 16 Debug mode mask (DMx) - If set, the corresponding processor will not be able to force running processors into debug mode even if it enters debug mode. 15: 0 Enter debug mode (EDx) - Force processor x into debug mode if any of processors in a multiprocessor system enters the debug mode. If 0, the processor x will not enter the debug mode. GRIP, Apr 2018, Version 2018.1 217 www.cobham.com/gaisler GRLIB IP Core 24.6.4 DSU trap register The DSU trap register is a read-only register that indicates which SPARC trap type that caused the processor to enter debug mode. When debug mode is force by setting the BN bit in the DSU control register, the trap type will be 0xb (hardware watchpoint trap). Table 242.0x400020 - DTR - DSU Trap register 31 13 12 11 RESERVED EM 4 3 R 31: 13 RESERVED 12 Error mode (EM) - Set if the trap would have cause the processor to enter error mode. 11: 4 Trap type (TRAPTYPE) - 8-bit SPARC trap type 3: 0 Read as 0x0 0 TRAPTYPE 24.6.5 DSU time tag counter The trace buffer time tag counter is incremented each clock as long as the processor is running. The counter is stopped when the processor enters debug mode and when the DSU is disabled (unless the timer enable bit in the AHB trace buffer control register is set), and restarted when execution is resumed. Table 243.0x000008 - DTTC - DSU time tag counter 31 0 TIMETAG 0 rw 31: 0 DSU Time Tag Value (TIMETAG) The value is used as time tag in the instruction and AHB trace buffer. The width of the timer is configurable at implementation time. 24.6.6 DSU ASI register The DSU can perform diagnostic accesses to different ASI areas. The value in the ASI diagnostic access register is used as ASI while the address is supplied from the DSU. Table 244.0x400024 - DASI - ASI diagnostic access register 31 8 7 0 RESERVED ASI 0 NR r rw 31: 8 RESERVED 7: 0 ASI (ASI) - ASI to be used on diagnostic ASI access 24.6.7 AHB Trace buffer control register The AHB trace buffer is controlled by the AHB trace buffer control register: Table 245.0x000040 - ATBC - AHB trace buffer control register 31 16 15 DCNT GRIP, Apr 2018, Version 2018.1 8 RESERVED 218 7 6 5 DF SF TE TF 4 3 BW 2 1 0 BR DM EN www.cobham.com/gaisler GRLIB IP Core Table 245.0x000040 - ATBC - AHB trace buffer control register 0 0 0 0 0 0 rw r rw rw rw rw 0 0 r rw rw rw 0 0 31: 16 Trace buffer delay counter (DCNT) - Note that the number of bits actually implemented depends on the size of the trace buffer. 15: 9 RESERVED 8 Enable Debug Mode Timer Freeze (DF) - The time tag counter keeps counting in debug mode when at least one of the processors has the internal timer enabled. If this bit is set to ‘1’ then the time tag counter is frozen when the processors have entered debug mode. 7 Sample Force (SF) - If this bit is written to ‘1’ it will have the same effect on the AHB trace buffer as if HREADY was asserted on the bus at the same time as a sequential or non-sequential transfer is made. This means that setting this bit to ‘1’ will cause the values in the trace buffer’s sample registers to be written into the trace buffer, and new values will be sampled into the registers. This bit will automatically be cleared after one clock cycle. Writing to the trace buffer still requires that the trace buffer is enabled (EN bit set to ‘1’) and that the CPU is not in debug mode or that tracing is forced (TF bit set to ‘1’). This functionality is primarily of interest when the trace buffer is tracing a separate bus and the traced bus appears to have frozen. 6 Timer enable (TE) - Activates time tag counter also in debug mode. 5 Trace force (TF) - Activates trace buffer also in debug mode. Note that the trace buffer must be disabled when reading out trace buffer data via the core’s register interface. 4: 3 Bus width (BW) - This value corresponds to log2(Supported bus width / 32) 2 Break (BR) - If set, the processor will be put in debug mode when AHB trace buffer stops due to AHB breakpoint hit. 1 Delay counter mode (DM) - Indicates that the trace buffer is in delay counter mode. 0 Trace enable (EN) - Enables the trace buffer. 24.6.8 AHB trace buffer index register The AHB trace buffer index register contains the address of the next trace line to be written. Table 246.0x000044 - ATBI - AHB trace buffer index register 31 4 3 0 INDEX R NR 0 rw r 31: 4 Trace buffer index counter (INDEX) - Note that the number of bits actually implemented depends on the size of the trace buffer. 3: 0 Read as 0x0 24.6.9 AHB trace buffer filter control register The trace buffer filter control register is only available if the core has been implemented with support for AHB trace buffer filtering. Table 247.0x000048 - ATBFC - AHB trace buffer filter control register 31 14 13 12 11 10 RESERVED 31: 14 WPF R 0 0 r rw 9 8 7 4 3 2 1 0 BPF RESERVED PF AF FR FW 0 0 0 0 r rw r rw rw rw rw 0 0 0 RESERVED GRIP, Apr 2018, Version 2018.1 219 www.cobham.com/gaisler GRLIB IP Core Table 247.0x000048 - ATBFC - AHB trace buffer filter control register 13: 12 AHB watchpoint filtering (WPF) - Bit 13 of this field applies to AHB watchpoint 2 and bit 12 applies to AHB watchpoint 1. If the WPF bit for a watchpoint is set to ‘1’ then the watchpoint will not trigger unless the access also passes through the filter. This functionality can be used to, for instance, set a AHB watchpoint that only triggers if a specified master performs an access to a specified slave. 11: 10 RESERVED 9: 8 AHB breakpoint filtering (BPF) - Bit 9 of this field applies to AHB breakpoint 2 and bit 8 applies to AHB breakpoint 1. If the BPF bit for a breakpoint is set to ‘1’ then the breakpoint will not trigger unless the access also passes through the filter. This functionality can be used to, for instance, set a AHB breakpoint that only triggers if a specified master performs an access to a specified slave. Note that if a AHB breakpoint is coupled with an AHB watchpoint then the setting of the corresponding bit in this field has no effect. 7: 4 RESERVED 3 Performance counter Filter (PF) - If this bit is set to ‘1’, the cores performance counter (statistical) outputs will be filtered using the same filter settings as used for the trace buffer. If a filter inhibits a write to the trace buffer, setting this bit to ‘1’ will cause the same filter setting to inhibit the pulse on the statistical output. 2 Address Filter (AF) - If this bit is set to ‘1’, only the address range defined by AHB trace buffer breakpoint 2’s address and mask will be included in the trace buffer. 1 Filter Reads (FR) - If this bit is set to ‘1’, read accesses will not be included in the trace buffer. 0 Filter Writes (FW) - If this bit is set to ‘1’, write accesses will not be included in the trace buffer. 24.6.10 AHB trace buffer filter mask register The trace buffer filter mask register is only available if the core has been implemented with support for AHB trace buffer filtering. Table 248.0x00004C - ATBFM - AHB trace buffer filter mask register 31 16 15 SMASK[15:0] 0 MMASK[15:0] 0 0 rw rw 31: 16 Slave Mask (SMASK) - If SMASK[n] is set to ‘1’, the trace buffer will not save accesses performed to slave n. 15: 0 Master Mask (MMASK) - If MMASK[n] is set to ‘1’, the trace buffer will not save accesses performed by master n. 24.6.11 AHB trace buffer breakpoint registers The DSU contains two breakpoint registers for matching AHB addresses. A breakpoint hit is used to freeze the trace buffer by automatically clearing the enable bit. Freezing can be delayed by programming the DCNT field in the trace buffer control register to a non-zero value. In this case, the DCNT value will be decremented for each additional trace until it reaches zero, after which the trace buffer is frozen. A mask register is associated with each breakpoint, allowing breaking on a block of addresses. Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint detection. To break on AHB load or store accesses, the LD and/or ST bits should be set. Table 249.0x000050, 0x000058 - ATBBA - AHB trace buffer break address register 31 2 0 R NR 0 rw r 31: 2 Break point address (BADDR) - Bits 31:2 of breakpoint address 1: 0 Read as 0b00 GRIP, Apr 2018, Version 2018.1 1 BADDR[31:2] 220 www.cobham.com/gaisler GRLIB IP Core Table 250.0x000054, 0x00005C - ATBBM - AHB trace buffer break mask register 31 2 BMASK[31:2] 1 0 LD ST NR 0 rw rw rw 31: 2 Breakpoint mask (BMASK) - (see text) 1 Load (LD) - Break on data load address 0 Store (ST) - Break on data store address 0 24.6.12 Instruction trace control register 0 The instruction trace control register 0 contains a pointer that indicates the next line of the instruction trace buffer to be written. Table 251.0x110000 - ITBCO - Instruction trace control register 0 31 29 28 31: 28 16 15 0 RESERVED ITPOINTER 0 NR r rw Trace filter configuration 27: 16 RESERVED 15: 0 Instruction trace pointer (ITPOINTER) - Note that the number of bits actually implemented depends on the size of the trace buffer 24.6.13 Instruction trace control register 1 The instruction trace control register 1 contains settings used for trace buffer overflow detection, in addition it includes settings used for some of the instruction trace buffer filtering options. This register can be written while the processor is running. Bits [31:28] is used to enable or disable Instruction Trace Buffer Address based Filtering (ITBAF). ITBAF is intended to allow the available hardware watch-point (HWP) registers to be used as instruction trace buffer filters when they are not used for breakpoint operation. If a bit is set to ‘1’ in ITBAF, the corresponding address and mask information in the HWP register will be used to filter instruction trace entries based on the program counter (PC) value. Bits[31:28] corresponds to HWP[3:0] respectively. ITBAF can only be used if the corresponding HWP register exist in the hardware. Instruction Trace Buffer Address based Filtering Option (ITBAFO, Bits[19:16]) determines the type of filtering for the corresponding ITBAF entry. If an ITBAFO entry is set to ‘0’ only the PC value(s) that match the address and mask option in the corresponding HWP register will be logged in the instruction trace buffer (ITB). If a bit is set to ‘1’ only the PC value(s) that does not match the address and mask option in the corresponding HWP register will be logged in the ITB. Bits[19:16] corresponds to the option for ITBAF[3:0] respectively. If there is more than one address filtering operation is enabled, the corresponding filtering operations will be combined together. Bits[15:0] corresponds to ASI last digit based filtering mask (ASIFMASK). ASIFMASK is in effect when the trace filter configuration is set to 0xE (SPARC Format 3 LOAD or STORE instructions to alternate space 0x80 - 0xFF with ASI last digit base filtering). Bits[15:0] corresponds to digits [0xF:0x0] respectively. If a bit is set to ‘0’ in the ASIFMASK, the load and store instructions which have an ASI between the range of 0x80-0xFF and have the corresponding last digit are logged in the instruction trace buffer. For example if only the bit0 and bit2 of the ASIFMASK are ‘0’ then only the load and store instructions with ASIs 0x80, 0x82, 0x90, 0x92, 0xA0, 0xA2, 0xB0, 0xB2, 0xC0, 0xC2, 0xD0, 0xD2, 0xE0, 0xE2, 0xF0, 0xF2 are tracked in the ITB. After the reset of processor all the bits GRIP, Apr 2018, Version 2018.1 221 www.cobham.com/gaisler GRLIB IP Core in the ASIFMASK is set to 0x0000 which means by default all the ASIs in the range of 0x80-0xFF are tracked. Table 252.0x110004 - ITBCI - Instruction trace control register 1 31 28 27 26 ITBAF 24.7 W O 24 23 22 TLIM 20 19 OV RESERVED 16 15 ITBAFO 0 ASIFMASK 0 0 0 0 0 0 0 rw rw rw rw r rw rw 31: 28 Instruction Trace Buffer Address based Filtering (ITBAF) (see text) 27 Watchpoint on overflow (WO) - If this bit is set, and Break on iu watchpoint (BW) is enabled in the DSU control register, then a watchpoint will be inserted when a trace overflow is detected (TOV field in this register gets set). 26: 24 Trace Limit (TLIM) - TLIM is compared with the top bits of ITPOINTER in Instruction trace control register 0 to generate the value in the TOV field below. 23 Trace Overflow (TOV) - Gets set to ‘1’ when the DSU detects that TLIM equals the top three bits of ITPOINTER. 22: 20 RESERVED 19: 16 Instruction Trace Buffer Address based Filtering Option (ITBAFO) (see text) 15: 0 ASI last digit based filtering mask (ASIFMASK) (see text) Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x017. For a description of vendor and device identifiers see GRLIB IP Library User’s Manual. 24.8 Implementation 24.8.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support grlib_async_reset_enable. All registers that react on the reset signal will have a synchronous reset. 24.8.2 Technology mapping DSU3 has one technology mapping generic, tech. This generic controls the implementation of which technology that will be used to implement the trace buffer memories. The AHB trace buffer will use two identical SYNCRAM64 blocks to implement the buffer memory (SYNCRAM64 may then result in two 32-bit wide memories on the target technology, depending on the technology map), with one additional 32-bit wide SYNCRAM if the system’s AMBA data bus width is 64-bits, and also one additional 64-bit wide SYNCRAM if the system’s AMBA data bus width exceeds 64 bits. The depth of the RAMs depends on the KBYTES generic. If KBYTES = 1 (1 Kbyte), then the depth will be 64. If KBYTES = 2, then the RAM depth will be 128 and so on. GRIP, Apr 2018, Version 2018.1 222 www.cobham.com/gaisler GRLIB IP Core 24.9 Configuration options Table 253 shows the configuration options of the core (VHDL generics). Table 253.Configuration options Generic Function Allowed range Default hindex AHB slave index 0 - NAHBSLV-1 0 haddr AHB slave address (AHB[31:20]) 0 - 16#FFF# 16#900# hmask AHB slave address mask 0 - 16#FFF# 16#F00# ncpu Number of attached processors 1 - 16 1 tbits Number of bits in the time tag counter 2 - 63 30 tech Memory technology for trace buffer RAM 0 - NTECH-1 0 (inferred) kbytes Size of trace buffer memory in Kbytes. A value of 0 will disable the trace buffer function. 0 - 64 0 (disabled) clk2x Support for LEON3 double-clocking (this generic is only available on dsu3x entity), see next section. 0-1 0 (disabled) testen Scan test support enable 0-1 0 bwidth Traced AHB bus width 32, 64, 128 32 ahbpf AHB performance counters and filtering. If ahbpf is non-zero the core will support AHB trace buffer filtering. If ahbpf is larger than 1 then the core’s statistical outputs will be enabled. 0-2 0 24.10 Signal descriptions Table 254 shows the interface signals of the core (VHDL ports). There are several top-level entities available for the DSU3. The dsu3x entity contains all signals and settings. The other entities are wrappers around dsu3x. The available entities are: • dsu3 - Entity without support for double clocking. AHB trace of same bus as DSU AHB slave interface is connected to. • dsu3_2x - Entity with support for LEON3 double-clocking. AHB trace of same bus as DSU AHB slave interface is connected to. • dsu3_mb - Entity with support for AHB tracing of separate bus • dsu3x - Entity with support for all features (double-clocking and tracing of separate bus) GRIP, Apr 2018, Version 2018.1 223 www.cobham.com/gaisler GRLIB IP Core 24.11 Signal definitions and reset values Table 254.Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input CPU and bus clock, on dsu3 and dsu3_mb entites - HCLK N/A Input Bus clock, on dsu3_2x and dsu3x entities. Only used when double-clocking is enabled. - CPUCLK N/A Input CPU clock, on dsu3_2x and dsu3x entities - AHBMI * Input AHB master input signals, used for AHB tracing - AHBSI * Input AHB slave input signals, used for AHB tracing when using dsu3 and dsu3_2x entities - AHBSO * Output AHB slave output signals - TAHBSI * Input AHB slave input signals, used for AHB tracing when using dsu3_mb and dsu3x entities - DBGI - Input Debug signals from LEON3 - DBGO - Output Debug signals to LEON3 - DSUI ENABLE Input DSU enable High BREAK Input DSU break High ACTIVE Output Debug mode High PWD[n-1 : 0] Output Clock gating enable for processor [n] High ASTAT (record) Output AHB statistic/performance counter events - N/A Input Double-clocking qualifier signal. Only used with double-clocking on dsu4_2x and dsu4x entities High DSUO HCLKEN * see GRLIB IP Library User’s Manual The signals and their reset values are described in table 255. Table 255.Signal definitions and reset values Signal name Type Function Active Reset value dsuen Input DSU enable High - dsubre Input DSU break High - dsuact Output Debug mode High Logical 0 GRIP, Apr 2018, Version 2018.1 224 www.cobham.com/gaisler GRLIB IP Core 24.12 Timing The timing waveforms and timing parameters are shown in figure 60 and are defined in table 256. clk dsuact tDSU0 dsuen, dsubre tDSU1 tDSU0 tDSU2 Figure 60. Timing waveforms Table 256.Timing parameters • Name Parameter Reference edge Min Max Unit tDSU0 clock to output delay rising clk edge TBD TBD ns tDSU1 input to clock hold rising clk edge - - ns tDSU2 input to clock setup rising clk edge - - ns Note: The dsubre and dsuen are re-synchronized internally. These signals do not have to meet any setup or hold requirements. 24.13 Library dependencies Table 257 shows libraries used when instantiating the core (VHDL libraries). Table 257.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER LEON3 Component, signals Component declaration, signals declaration 24.14 Component declaration The core has the following component declaration. component dsu3 generic ( hindex : integer := 0; haddr : integer := 16#900#; hmask : integer := 16#f00#; ncpu : integer := 1; tbits : integer := 30; tech : integer := 0; irq : integer := 0; kbytes : integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; ahbmi : in ahb_mst_in_type; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; dbgi : in l3_debug_out_vector(0 to NCPU-1); dbgo : out l3_debug_in_vector(0 to NCPU-1); dsui : in dsu_in_type; dsuo : out dsu_out_type GRIP, Apr 2018, Version 2018.1 225 www.cobham.com/gaisler GRLIB IP Core ); end component; 24.15 Instantiation This example shows how the core can be instantiated. The DSU is always instantiated with at least one LEON3 processor. It is suitable to use a generate loop for the instantiation of the processors and DSU and showed below. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.leon3.all; constant NCPU : integer := 1; -- select number of processors signal signal signal signal leon3i leon3o irqi irqo : : : : l3_in_vector(0 to NCPU-1); l3_out_vector(0 to NCPU-1); irq_in_vector(0 to NCPU-1); irq_out_vector(0 to NCPU-1); signal dbgi : l3_debug_in_vector(0 to NCPU-1); signal dbgo : l3_debug_out_vector(0 to NCPU-1); signal dsui signal dsuo : dsu_in_type; : dsu_out_type; . begin cpu : for i in 0 to NCPU-1 generate u0 : leon3s-- LEON3 processor generic map (ahbndx => i, fabtech => FABTECH, memtech => MEMTECH) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); irqi(i) <= leon3o(i).irq; leon3i(i).irq <= irqo(i); end generate; dsu0 : dsu3-- LEON3 Debug Support Unit generic map (ahbndx => 2, ncpu => NCPU, tech => memtech, kbytes => 2) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= dsuen; dsui.break <= dsubre; dsuact <= dsuo.active; GRIP, Apr 2018, Version 2018.1 226 www.cobham.com/gaisler GRLIB IP Core 25 DSU4 - LEON4 Hardware Debug Support Unit 25.1 Overview To simplify debugging on target hardware, the LEON4 processor implements a debug mode during which the pipeline is idle and the processor is controlled through a special debug interface. The LEON4 Debug Support Unit (DSU) is used to control the processor during debug mode. The DSU acts as an AHB slave and can be accessed by any AHB master. An external debug host can therefore access the DSU through several different interfaces. Such an interface can be a serial UART (RS232), JTAG, PCI, USB or Ethernet. The DSU supports multi-processor systems and can handle up to 16 processors. LEON4 LEON3 Processor(s) LEON3 Processor LEON3 Processor(s) Processor(s) Debug I/F Debug Support Unit AHB Slave I/F AHB Master I/F AMBA AHB BUS RS232 PCI Ethernet JTAG USB DEBUG HOST Figure 61. LEON4/DSU Connection 25.2 Operation Through the DSU AHB slave interface, any AHB master can access the processor registers and the contents of the instruction trace buffer. The DSU control registers can be accessed at any time, while the processor registers and caches can only be accessed when the processor has entered debug mode. In debug mode, the processor pipeline is held and the processor state can be accessed by the DSU. Entering the debug mode can occur on the following events: • executing a breakpoint instruction (ta 1) • integer unit hardware breakpoint/watchpoint hit (trap 0xb) • rising edge of the external break signal (DSUBRE) • setting the break-now (BN) bit in the DSU control register • a trap that would cause the processor to enter error mode • occurrence of any, or a selection of traps as defined in the DSU control register • after a single-step operation • one of the processors in a multiprocessor system has entered the debug mode • DSU AHB breakpoint or watchpoint hit GRIP, Apr 2018, Version 2018.1 227 www.cobham.com/gaisler GRLIB IP Core The debug mode can only be entered when the debug support unit is enabled through an external signal (DSUEN). For DSU break, and the break-now BN bit, to have effect the Break-on-IU-watchpoint (BW) bit must be set in the DSU control register. This bit is set when DSUBRE is active after reset and should also be set by debug monitor software when initializing the DSU. When the debug mode is entered, the following actions are taken: • PC and nPC are saved in temporary registers (accessible by the debug unit) • an output signal (DSUACT) is asserted to indicate the debug state • the timer unit is (optionally) stopped to freeze the LEON timers and watchdog The instruction that caused the processor to enter debug mode is not executed, and the processor state is kept unmodified. Execution is resumed by clearing the BN bit in the DSU control register or by deasserting DSUEN. The timer unit will be re-enabled and execution will continue from the saved PC and nPC. Debug mode can also be entered after the processor has entered error mode, for instance when an application has terminated and halted the processor. The error mode can be reset and the processor restarted at any address. When a processor is in the debug mode, an access to ASI diagnostic area is forwarded to the IU which performs access with ASI equal to value in the DSU ASI register and address consisting of 20 LSB bits of the original address. 25.3 AHB trace buffer The AHB trace buffer consists of a circular buffer that stores AHB data transfers, the monitored AHB bus is either the same bus as the DSU AHB slave interface is connected to, or a completely separate bus. The address, data and various control signals of the AHB bus are stored and can be read out for later analysis. The trace buffer is 128, 160 or 224 bits wide, depending on the AHB bus width. The way information stored is indicated in the table below: Table 258.AHB Trace buffer data allocation Bits Name Definition 223:160 Load/Store data AHB HRDATA/HWDATA(127:64) 159:129 Load/Store data AHB HRDATA/HWDATA(63:32) 127 AHB breakpoint hit Set to ‘1’ if a DSU AHB breakpoint hit occurred. 126 - Not used 125:96 Time tag DSU time tag counter 95:80 - Not used 79 Hwrite AHB HWRITE 78:77 Htrans AHB HTRANS 76:74 Hsize AHB HSIZE 73:71 Hburst AHB HBURST 70:67 Hmaster AHB HMASTER 66 Hmastlock AHB HMASTLOCK 65:64 Hresp AHB HRESP 63:32 Load/Store data AHB HRDATA/HWDATA(31:0) 31:0 Load/Store address AHB HADDR In addition to the AHB signals, the DSU time tag counter is also stored in the trace. The trace buffer is enabled by setting the enable bit (EN) in the trace control register. Each AHB transfer is then stored in the buffer in a circular manner. The address to which the next transfer is written is held in the trace buffer index register, and is automatically incremented after each transfer. TracGRIP, Apr 2018, Version 2018.1 228 www.cobham.com/gaisler GRLIB IP Core ing is stopped when the EN bit is reset, or when a AHB breakpoint is hit. Tracing is temporarily suspended when the processor enters debug mode, unless the trace force bit (TF) in the trace control register is set. If the trace force bit is set, the trace buffer is activated as long as the enable bit is set. The force bit is reset if an AHB breakpoint is hit and can also be cleared by software. Note that neither the trace buffer memory nor the breakpoint registers (see below) can be read/written by software when the trace buffer is enabled. The DSU has an internal time tag counter and this counter is frozen when the processor enters debug mode. When AHB tracing is performed in debug mode (using the trace force bit) it may be desirable to also enable the time tag counter. This can be done using the timer enable bit (TE). Note that the time tag is also used for the instruction trace buffer and the timer enable bit should only be set when using the DSU as an AHB trace buffer only, and not when performing profiling or software debugging. The timer enable bit is reset on the same events as the trace force bit. 25.3.1 AHB trace buffer filters The DSU can be implemented with filters that can be applied to the AHB trace buffer, breakpoints and watchpoints. If implemented, these filters are controlled via the AHB trace buffer filter control and AHB trace buffer filter mask registers. The fields in these registers allows masking access characteristics such as master, slave, read, write and address range so that accesses that correspond to the specified mask are not written into the trace buffer. Address range masking is done using the second AHB breakpoint register set. The values of the LD and ST fields of this register has no effect on filtering. 25.3.2 AHB statistics The DSU can be implemented to generate statistics from the traced AHB bus. When statistics collection is enabled the DSU will assert outputs that are suitable to connect to a LEON4 statistics unit (L4STAT). The statistical outputs can be filtered by the AHB trace buffer filters, this is controlled by the Performance counter Filter bit (PF) in the AHB trace buffer filter control register. The DSU can collect data for the events listed in table 259 below. Table 259.AHB events Event Description Note idle HTRANS=IDLE Active when HTRANS IDLE is driven on the AHB slave inputs and slave has asserted HREADY. busy HTRANS=BUSY Active when HTRANS BUSY is driven on the AHB slave inputs and slave has asserted HREADY. nseq HTRANS=NONSEQ Active when HTRANS NONSEQ is driven on the AHB slave inputs and slave has asserted HREADY. seq HTRANS=SEQ Active when HTRANS SEQUENTIAL is driven on the AHB slave inputs and slave has asserted HREADY. read Read access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and the HWRITE input is low. write Write access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and the HWRITE input is high. hsize[5:0] Transfer size Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and HSIZE is BYTE (hsize[0]), HWORD (HSIZE[1]), WORD (hsize[2]), DWORD (hsize[3]), 4WORD hsize[4], or 8WORD (hsize[5]). ws Wait state Active when HREADY input to AHB slaves is low and AMBA response is OKAY. retry RETRY response Active when master receives RETRY response split SPLIT response Active when master receives SPLIT response GRIP, Apr 2018, Version 2018.1 229 www.cobham.com/gaisler GRLIB IP Core Table 259.AHB events Event Description Note spdel SPLIT delay Active during the time a master waits to be granted access to the bus after reception of a SPLIT response. The core will only keep track of one master at a time. This means that when a SPLIT response is detected, the core will save the master index. This event will then be active until the same master is re-allowed into bus arbitration and is granted access to the bus. This also means that the delay measured will include the time for re-arbitration, delays from other ongoing transfers and delays resulting from other masters being granted access to the bus before the SPLIT:ed master is granted again after receiving SPLIT complete. If another master receives a SPLIT response while this event is active, the SPLIT delay for the second master will not be measured. locked 25.4 Locked access Active while the HMASTLOCK signal is asserted on the AHB slave inputs. Instruction trace buffer The instruction trace buffer consists of a circular buffer that stores executed instructions. The instruction trace buffer is located in the processor, and read out via the DSU. The trace buffer is 128 bits wide, the information stored is indicated in the table below: Table 260.Instruction trace buffer data allocation Bits Name Definition 126 Multi-cycle instruction Set to ‘1’ on the second instance of a multi-cycle instruction 125:96 Time tag The value of the DSU time tag counter 95:64 Result or Store address/data Instruction result, Store address or Store data 63:34 Program counter Program counter (2 lsb bits removed since they are always zero) 33 Instruction trap Set to ‘1’ if traced instruction trapped 32 Processor error mode Set to ‘1’ if the traced instruction caused processor error mode 31:0 Opcode Instruction opcode During tracing, one instruction is stored per line in the trace buffer with the exception of atomic load/ store instructions, which are entered twice (one for the load and one for the store operation). Bits [95:64] in the buffer correspond to the store address and the loaded data for load instructions. Bit 126 is set for the second entry. When the processor enters debug mode, tracing is suspended. The trace buffer and the trace buffer control register can be read and written while the processor is in the debug mode. During the instruction tracing (processor in normal mode) the trace buffer and trace buffer control register 0 can not be written. If the two-port trace buffer is enabled (refer to the tbuf generic in section 81.15), then the trace buffer can be read contextually to the instruction tracing (processor in normal mode). The traced instructions can optionally be filtered on instruction types. Which instructions are traced is defined in the instruction trace register [31:28], as defined in the table below: GRIP, Apr 2018, Version 2018.1 230 www.cobham.com/gaisler GRLIB IP Core Table 261.Trace filter operation Trace filter Instructions traced 0x0 All instructions 0x1 SPARC Format 2 instructions 0x2 Control-flow changes. All Call, branch and trap instructions including branch targets 0x4 SPARC Format 1 instructions (CALL) 0x8 SPARC Format 3 instructions except LOAD or STORE 0xC SPARC Format 3 LOAD or STORE instructions 0xD SPARC Format 3 LOAD or STORE instructions to alternate space 0xE SPARC Format 3 LOAD or STORE instructions to alternate space 0x80 - 0xFF with ASI last digit base filtering It is also possible to filter traced instructions based on the program counter value. This option is combined with the filtering option if an additional filtering mechanism is activated from Table 261. Refer to section 25.6.13 for detailed information. 25.5 DSU memory map The DSU memory map can be seen in table 262 below. In a multiprocessor systems, the register map is duplicated and address bits 27 - 24 are used to index the processor. Note: The DSU memory interface is intended to be accessed by a debug monitor. Software running on the LEON processors should not access the DSU interface. Registers, such as ASR registers, may not have all fields available via the DSU interface. Table 262.DSU memory map Address offset Register 0x000000 DSU control register 0x000008 Time tag counter 0x000020 Break and Single Step register 0x000024 Debug Mode Mask register 0x000040 AHB trace buffer control register 0x000044 AHB trace buffer index register 0x000048 AHB trace buffer filter control register 0x00004c AHB trace buffer filter mask register 0x000050 AHB breakpoint address 1 0x000054 AHB mask register 1 0x000058 AHB breakpoint address 2 0x00005c AHB mask register 2 0x000070 Instruction count register 0x000080 AHB watchpoint control register 0x000090 - 0x00009C AHB watchpoint 1 data registers 0x0000A0 - 0x0000AC AHB watchpoint 1 mask registers 0x0000B0 - 0x0000BC AHB watchpoint 2 data registers 0x0000C0 - 0x0000CC AHB watchpoint 2 mask registers 0x100000 - 0x10FFFF Instruction trace buffer (..0: Trace bits 127 - 96, ..4: Trace bits 95 - 64, ..8: Trace bits 63 - 32, ..C : Trace bits 31 - 0) GRIP, Apr 2018, Version 2018.1 231 www.cobham.com/gaisler GRLIB IP Core Table 262.DSU memory map Address offset Register 0x110000 Instruction Trace buffer control register 0 0x110004 Instruction Trace buffer control register 1 0x200000 - 0x210000 AHB trace buffer (..0: Trace bits 127 - 96, ..4: Trace bits 95 - 64, ..8: Trace bits 63 - 32, ..C : Trace bits 31 - 0) IU register file. 0x300000 - 0x3007FC The addresses of the IU registers depends on how many register windows has been implemented: %on: 0x300000 + (((psr.cwp * 64) + 32 + n*4) mod (NWINDOWS*64)) %ln: 0x300000 + (((psr.cwp * 64) + 64 + n*4) mod (NWINDOWS*64)) %in: 0x300000 + (((psr.cwp * 64) + 96 + n*4) mod (NWINDOWS*64)) %gn: 0x300000 + (NWINDOWS*64) + n*4 %fn: 0x301000 + n*4 25.6 0x300800 - 0x300FFC IU register file check bits (LEON4FT only) 0x301000 - 0x30107C FPU register file 0x400000 Y register 0x400004 PSR register 0x400008 WIM register 0x40000C TBR register 0x400010 PC register 0x400014 NPC register 0x400018 FSR register 0x40001C CPSR register 0x400020 DSU trap register 0x400024 DSU ASI register 0x400040 - 0x40007C ASR16 - ASR31 (when implemented) 0x700000 - 0x7FFFFC ASI diagnostic access (ASI = value in DSU ASI register, address = address[19:0]) ASI = 0x9 : Local instruction RAM ASI = 0xB : Local data RAM ASI = 0xC : Instruction cache tags ASI = 0xD : Instruction cache data ASI = 0xE : Data cache tags ASI = 0xF : Data cache data ASI = 0x1E : Separate snoop tags DSU registers 25.6.1 DSU control register The DSU is controlled by the DSU control register: Table 263.0x000000 - CTRL - DSU control register 31 12 11 10 RESERVED 31: 12 9 8 7 6 5 4 3 2 1 0 PW HL PE EB EE DM BZ BX BS BW BE TE 0 0 0 0 * * r r rw uc r r * r * 0 * * * rw rw rw rw rw rw Reserved 11 Power down (PW) - Returns ‘1’ when processor is in power-down mode. 10 Processor halt (HL) - Returns ‘1’ on read when processor is halted. If the processor is in debug mode, setting this bit will put the processor in halt mode. GRIP, Apr 2018, Version 2018.1 232 www.cobham.com/gaisler GRLIB IP Core Table 263.0x000000 - CTRL - DSU control register 9 Processor error mode (PE) - returns ‘1’ on read when processor is in error mode, else ‘0’. If written with ‘1’, it will clear the error and halt mode. 8 External Break (EB) - Value of the external DSUBRE signal (read-only) 7 External Enable (EE) - Value of the external DSUEN signal (read-only) 6 Debug mode (DM) - Indicates when the processor has entered debug mode (read-only). 5 Break on error traps (BZ) - if set, will force the processor into debug mode on all except the following traps: priviledged_instruction, fpu_disabled, window_overflow, window_underflow, asynchronous_interrupt, ticc_trap. 4 Break on trap (BX) - if set, will force the processor into debug mode when any trap occurs. 3 Break on S/W breakpoint (BS) - if set, debug mode will be forced when an breakpoint instruction (ta 1) is executed. 2 Break on IU watchpoint (BW) - if set, debug mode will be forced on a IU watchpoint (trap 0xb). 1 Break on error (BE) - if set, will force the processor to debug mode when the processor would have entered error condition (trap in trap). 0 Trace enable (TE) - Enables instruction tracing. If set the instructions will be stored in the trace buffer. Remains set when then processor enters debug or error mode 25.6.2 DSU Break and Single Step register This register is used to break or single step the processor(s). This register controls all processors in a multi-processor system, and is only accessible in the DSU memory map of processor 0. Table 264.0x000020 - BRSS - DSU Break and Single Step register 31 16 15 SS[15:0] 0 BN[15:0] 0 0 rw rw 31: 16 Single step (SSx) - if set, the processor x will execute one instruction and return to debug mode. The bit remains set after the processor goes into the debug mode. As an exception, if the instruction is a branch with the annul bit set, and if the delay instruction is effectively annulled, the processor will execute the branch, the annulled delay instruction and the instruction thereafter before returning to debug mode. 15: 0 Break now (BNx) -Force processor x into debug mode if the Break on watchpoint (BW) bit in the processors DSU control register is set. If cleared, the processor x will resume execution. 25.6.3 DSU Debug Mode Mask Register When one of the processors in a multiprocessor LEON4 system enters the debug mode the value of the DSU Debug Mode Mask register determines if the other processors are forced in the debug mode. This register controls all processors in a multi-processor system, and is only accessible in the DSU memory map of processor 0. Table 265.0x000024 - DBGM - DSU Debug Mode Mask register 31 16 15 DM[15:0] 0 ED[15:0] 0 0 rw rw 31: 16 Debug mode mask (DMx) - If set, the corresponding processor will not be able to force running processors into debug mode even if it enters debug mode. 15: 0 Enter debug mode (EDx) - Force processor x into debug mode if any of processors in a multiprocessor system enters the debug mode. If 0, the processor x will not enter the debug mode. GRIP, Apr 2018, Version 2018.1 233 www.cobham.com/gaisler GRLIB IP Core 25.6.4 DSU trap register The DSU trap register is a read-only register that indicates which SPARC trap type that caused the processor to enter debug mode. When debug mode is force by setting the BN bit in the DSU control register, the trap type will be 0xb (hardware watchpoint trap). Table 266.0x400020 - DTR - DSU Trap register 31 13 12 11 4 3 0 RESERVED EM TRAPTYPE R 0 NR NR 0 r r r r 31: 13 RESERVED 12 Error mode (EM) - Set if the trap would have cause the processor to enter error mode. 11: 4 Trap type (TRAPTYPE) - 8-bit SPARC trap type 3: 0 Read as 0x0 25.6.5 DSU time tag counter The trace buffer time tag counter is incremented each clock as long as the processor is running. The counter is stopped when the processor enters debug mode and when the DSU is disabled (unless the timer enable bit in the AHB trace buffer control register is set), and restarted when execution is resumed. Table 267.0x000008 - DTTL - DSU time tag counter 31 0 TIMETAG 0 rw 31: 0 DSU Time Tag Value (TIMETAG) The value is used as time tag in the instruction and AHB trace buffer. The width of the timer is configurable at implementation time. 25.6.6 DSU ASI register The DSU can perform diagnostic accesses to different ASI areas. The value in the ASI diagnostic access register is used as ASI while the address is supplied from the DSU. Table 268.0x400024 -DASI - ASI diagnostic access register 31 8 0 ASI 0 NR r rw 31: 8 RESERVED 7: 0 ASI (ASI) - ASI to be used on diagnostic ASI access GRIP, Apr 2018, Version 2018.1 7 RESERVED 234 www.cobham.com/gaisler GRLIB IP Core 25.6.7 AHB Trace buffer control register The AHB trace buffer is controlled by the AHB trace buffer control register: Table 269.0x000040 - ATBC - AHB trace buffer control register 31 16 15 9 8 7 6 5 4 DF SF TE TF 3 1 0 RESERVED 0 0 0 0 * 0 rw r rw rw rw rw r rw rw rw 0 0 BW 2 DCNT BR DM EN 0 * 31: 16 Trace buffer delay counter (DCNT) - Note that the number of bits actually implemented depends on the size of the trace buffer. 15: 9 RESERVED 8 Enable Debug Mode Timer Freeze (DF) - The time tag counter keeps counting in debug mode when at least one of the processors has the internal timer enabled. If this bit is set to ‘1’ then the time tag counter is frozen when the processors have entered debug mode. 7 Sample Force (SF) - If this bit is written to ‘1’ it will have the same effect on the AHB trace buffer as if HREADY was asserted on the bus at the same time as a sequential or non-sequential transfer is made. This means that setting this bit to ‘1’ will cause the values in the trace buffer’s sample registers to be written into the trace buffer, and new values will be sampled into the registers. This bit will automatically be cleared after one clock cycle. Writing to the trace buffer still requires that the trace buffer is enabled (EN bit set to ‘1’) and that the CPU is not in debug mode or that tracing is forced (TF bit set to ‘1’). This functionality is primarily of interest when the trace buffer is tracing a separate bus and the traced bus appears to have frozen. 6 Timer enable (TE) - Activates time tag counter also in debug mode. 5 Trace force (TF) - Activates trace buffer also in debug mode. Note that the trace buffer must be disabled when reading out trace buffer data via the core’s register interface. 4: 3 Bus width (BW) - This value corresponds to log2(Supported bus width / 32) 2 Break (BR) - If set, the processor will be put in debug mode when AHB trace buffer stops due to AHB breakpoint hit. 1 Delay counter mode (DM) - Indicates that the trace buffer is in delay counter mode. 0 Trace enable (EN) - Enables the trace buffer. 25.6.8 AHB trace buffer index register The AHB trace buffer index register contains the address of the next trace line to be written. Table 270.0x000044 - ATBI - AHB trace buffer index register 31 4 3 0 INDEX R NR 0 rw r 31: 4 Trace buffer index counter (INDEX) - Note that the number of bits actually implemented depends on the size of the trace buffer. 3: 0 Read as 0x0 25.6.9 AHB trace buffer filter control register The trace buffer filter control register is only available if the core has been implemented with support for AHB trace buffer filtering. Table 271.0x000048 - ATBFC - AHB trace buffer filter control register 31 14 13 12 11 10 RESERVED GRIP, Apr 2018, Version 2018.1 WPF R 0 0 r rw 235 9 8 7 4 3 2 1 0 BPF RESERVED PF AF FR FW 0 0 0 0 r rw r rw rw rw rw 0 0 0 www.cobham.com/gaisler GRLIB IP Core Table 271.0x000048 - ATBFC - AHB trace buffer filter control register 31: 14 RESERVED 13: 12 AHB watchpoint filtering (WPF) - Bit 13 of this field applies to AHB watchpoint 2 and bit 12 applies to AHB watchpoint 1. If the WPF bit for a watchpoint is set to ‘1’ then the watchpoint will not trigger unless the access also passes through the filter. This functionality can be used to, for instance, set a AHB watchpoint that only triggers if a specified master performs an access to a specified slave. 11: 10 RESERVED 9: 8 AHB breakpoint filtering (BPF) - Bit 9 of this field applies to AHB breakpoint 2 and bit 8 applies to AHB breakpoint 1. If the BPF bit for a breakpoint is set to ‘1’ then the breakpoint will not trigger unless the access also passes through the filter. This functionality can be used to, for instance, set a AHB breakpoint that only triggers if a specified master performs an access to a specified slave. Note that if a AHB breakpoint is coupled with an AHB watchpoint then the setting of the corresponding bit in this field has no effect. 7: 4 RESERVED 3 Performance counter Filter (PF) - If this bit is set to ‘1’, the cores performance counter (statistical) outputs will be filtered using the same filter settings as used for the trace buffer. If a filter inhibits a write to the trace buffer, setting this bit to ‘1’ will cause the same filter setting to inhibit the pulse on the statistical output. 2 Address Filter (AF) - If this bit is set to ‘1’, only the address range defined by AHB trace buffer breakpoint 2’s address and mask will be included in the trace buffer. 1 Filter Reads (FR) - If this bit is set to ‘1’, read accesses will not be included in the trace buffer. 0 Filter Writes (FW) - If this bit is set to ‘1’, write accesses will not be included in the trace buffer. 25.6.10 AHB trace buffer filter mask register The trace buffer filter mask register is only available if the core has been implemented with support for AHB trace buffer filtering. Table 272.0x00004C - ATBFM - AHB trace buffer filter mask register 31 16 15 SMASK[15:0] 0 MMASK[15:0] 0 0 rw rw 31: 16 Slave Mask (SMASK) - If SMASK[n] is set to ‘1’, the trace buffer will not save accesses performed to slave n. 15: 0 Master Mask (MMASK) - If MMASK[n] is set to ‘1’, the trace buffer will not save accesses performed by master n. 25.6.11 AHB trace buffer breakpoint registers The DSU contains two breakpoint registers for matching AHB addresses. A breakpoint hit is used to freeze the trace buffer by automatically clearing the enable bit. Freezing can be delayed by programming the DCNT field in the trace buffer control register to a non-zero value. In this case, the DCNT value will be decremented for each additional trace until it reaches zero, after which the trace buffer is frozen. A mask register is associated with each breakpoint, allowing breaking on a block of addresses. Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint detection. To break on AHB load or store accesses, the LD and/or ST bits should be set. Table 273.0x000050, 0x000058 - ATBBA - AHB trace buffer break address register 31 GRIP, Apr 2018, Version 2018.1 2 1 0 BADDR[31:2] R NR 0 rw r 236 www.cobham.com/gaisler GRLIB IP Core Table 273.0x000050, 0x000058 - ATBBA - AHB trace buffer break address register 31: 2 Break point address (BADDR) - Bits 31:2 of breakpoint address 1: 0 Read as 0b00 Table 274.0x000054, 0x00005C - ATBBM - AHB trace buffer break mask register 31 2 BMASK[31:2] 1 0 LD ST NR 0 rw rw rw 31: 2 Breakpoint mask (BMASK) - (see text) 1 Load (LD) - Break on data load address 0 Store (ST) - Break on data store address 0 25.6.12 Instruction trace control register 0 The instruction trace control register 0 contains a pointer that indicates the next line of the instruction trace buffer to be written. Table 275.0x110000 - ITBCO - Instruction trace control register 0 31 28 27 16 15 0 TFILT RESERVED 0 0 0 rw r rw 31: 28 ITPOINTER Trace filter configuration 27: 16 RESERVED 15: 0 Instruction trace pointer (ITPOINTER) - Note that the number of bits actually implemented depends on the size of the trace buffer 25.6.13 Instruction trace control register 1 The instruction trace control register 1 contains settings used for trace buffer overflow detection, in addition it includes settings used for some of the instruction trace buffer filtering options. This register can be written while the processor is running. Bits [31:28] is used to enable or disable Instruction Trace Buffer Address based Filtering (ITBAF). ITBAF is intended to allow the available hardware watch-point (HWP) registers to be used as instruction trace buffer filters when they are not used for breakpoint operation. If a bit is set to ‘1’ in ITBAF, the corresponding address and mask information in the HWP register will be used to filter instruction trace entries based on the program counter (PC) value. Bits[31:28] corresponds to HWP[3:0] respectively. ITBAF can only be used if the corresponding HWP register exist in the hardware. Instruction Trace Buffer Address based Filtering Option (ITBAFO, Bits[19:16]) determines the type of filtering for the corresponding ITBAF entry. If an ITBAFO entry is set to ‘0’ only the PC value(s) that match the address and mask option in the corresponding HWP register will be logged in the instruction trace buffer (ITB). If a bit is set to ‘1’ only the PC value(s) that does not match the address and mask option in the corresponding HWP register will be logged in the ITB. Bits[19:16] corresponds to the option for ITBAF[3:0] respectively. If there is more than one address filtering operation is enabled, the corresponding filtering operations will be combined together. Bits[15:0] corresponds to ASI last digit based filtering mask (ASIFMASK). ASIFMASK is in effect when the trace filter configuration is set to 0xE (SPARC Format 3 LOAD or STORE instructions to alternate space 0x80 - 0xFF with ASI last digit base filtering). Bits[15:0] corresponds to digits [0xF:0x0] respectively. If a bit is set to ‘0’ in the ASIFMASK, the load and store instructions which have an ASI between the range of 0x80-0xFF and have the corresponding last digit are logged in the instruction trace buffer. For example if only the bit0 and bit2 of the ASIFMASK is set then only the load and store instructions with ASIs 0x80, 0x82, 0x90, 0x92, 0xA0, 0xA2, 0xB0, 0xB2, 0xC0, 0xC2, GRIP, Apr 2018, Version 2018.1 237 www.cobham.com/gaisler GRLIB IP Core 0xD0, 0xD2, 0xE0, 0xE2, 0xF0, 0xF2 are tracked. After the reset of processor all the bits in the ASIFMASK is set to 0x0000 which means by default all the ASIs in the range of 0x80-0xFF are tracked. Table 276.0x110004 - ITBCI - Instruction trace control register 1 31 28 27 26 ITBAF W O 24 23 22 TLIM 20 19 OV RESERVED 16 15 0 ITBAFO ASIFMASK 0 0 0 0 0 0 0 rw rw rw rw r rw rw 31: 28 Instruction Trace Buffer Address based Filtering (ITBAF) (see text) 27 Watchpoint on overflow (WO) - If this bit is set, and Break on iu watchpoint (BW) is enabled in the DSU control register, then a watchpoint will be inserted when a trace overflow is detected (TOV field in this register gets set). 26: 24 Trace Limit (TLIM) - TLIM is compared with the top bits of ITPOINTER in Instruction trace control register 0 to generate the value in the TOV field below. 23 Trace Overflow (TOV) - Gets set to ‘1’ when the DSU detects that TLIM equals the top three bits of ITPOINTER. 22: 20 RESERVED 19: 16 Instruction Trace Buffer Address based Filtering Option (ITBAFO) (see text) 15: 0 ASI last digit based filtering mask (ASIFMASK) (see text) 25.6.14 Instruction count register The DSU contains an instruction count register to allow profiling of application, or generation of debug mode after a certain clocks or instructions. The instruction count register consists of a 29-bit down-counter, which is decremented on either each clock (IC=0) or on each executed instruction (IC=1). In profiling mode (PE=1), the counter will set to all ones after an underflow without generating a processor break. In this mode, the counter can be periodically polled and statistics can be formed on CPI (clocks per instructions). In non-profiling mode (PE=0), the processor will be put in debug mode when the counter underflows. This allows a debug tool such as GRMON to execute a defined number of instructions, or for a defined number of clocks. Table 277.0x000070 - ICNT - Instruction count register 31 30 29 28 0 CE IC PE 0 0 ICOUNT[28:0] 0 NR rw rw rw rw 31 Counter Enable (CE) - Counter enable 30 Instruction Count (IC) - Instruction (1) or clock (0) counting 29 Profiling Enable (PE) - Profiling enable 28: 0 Instruction count (ICOUNT) - Instruction count 25.6.15 AHB watchpoint control register The DSU has two AHB watchpoints that can be used to freeze the AHB tracebuffer, or put the processor in debug mode, when a specified data pattern occurs on the AMBA bus. These watchpoints can also be coupled with the two AHB breakpoints so that a watchpoint will not trigger unless the AHB breakpoint is triggered. This also means that when a watchpoint is coupled with an AHB breakpoint, GRIP, Apr 2018, Version 2018.1 238 www.cobham.com/gaisler GRLIB IP Core the breakpoint will not cause an AHB tracebuffer freeze, or put the processor(s), in debug mode unless also the watchpoint is triggered. Table 278.0x000080 - AHBWPC - AHB watchpoint control register 31 7 3 2 IN CP EN R IN CP EN 0 0 0 0 0 r rw rw rw r rw rw rw RESERVED 6 5 0 4 1 0 31: 7 RESERVED 6 Invert (IN) - Invert AHB watchpoint 2. If this bit is set the watchpoint will trigger if data on the AHB bus does NOT match the specified data pattern (typically only usable if the watchpoint has been coupled with an address by setting the CP field). 5 Couple (CP) - Couple AHB watchpoint 2 with AHB breakpoint 1 4 Enable (EN) - Enable AHB watchpoint 2 3 RESERVED 2 Invert (IN) - Invert AHB watchpoint 1. If this bit is set the watchpoint will trigger if data on the AHB bus does NOT match the specified data pattern (typically only usable if the watchpoint has been coupled with an address by setting the CP field). 1 Couple (CP) - Couple AHB watchpoint 1 with AHB breakpoint 1 0 Enable (EN) - Enable AHB watchpoint 1 0 0 25.6.16 AHB watchpoint data and mask registers The AHB watchpoint data and mask registers specify the data pattern for an AHB watchpoint. A watchpoint hit is used to freeze the trace buffer by automatically clearing the enable bit. A watchpoint hit can also be used to force the processor(s) to debug mode. A mask register is associated with each data register. Only data bits with the corresponding mask bit set to ‘1’ are compared during watchpoint detection. Table 279.0x000040 to 0x00004C - 0x0000B0 to 0x0000BC - AHBWPPO-7 - AHB watchpoint data register 31 0 DATA[127-n*32 : 96-n*32] NR rw 31: 0 AHB watchpoint data (DATA) - Specifies the data pattern of one word for an AHB watchpoint. The lower part of the register address specifies with part of the bus that the register value will be compared against: Offset 0x0 specifies the data value for AHB bus bits 127:96, 0x4 for bits 95:64, 0x8 for 63:32 and offset 0xC for bits 31:0. Table 280.0x0000A0 - 0x0000AC - 0x0000C0 to 0x0000CC - AHBWPMO-7 - AHB watchpoint mask register 31 0 MASK[127-n*32 : 96-n*32] NR rw 31: 0 AHB watchpoint mask (MASK) - Specifies the mask to select bits for comparison out of one word for an AHB watchpoint. The lower part of the register address specifies with part of the bus that the register value will be compared against: Offset 0x0 specifies the data value for AHB bus bits 127:96, 0x4 for bits 95:64, 0x8 for 63:32 and offset 0xC for bits 31:0. In a system with 64-bit bus width only half of the data and mask registers must be written. For AHB watchpoint 1, a data value with 64-bits would be written to the AHB watchpoint data registers at offsets 0x98 and 0x9C. The corresponding mask bits would be set in mask registers at offsets 0xA8 and 0xAC. GRIP, Apr 2018, Version 2018.1 239 www.cobham.com/gaisler GRLIB IP Core In most GRLIB systems with wide AMBA buses, the data for an access size that is less than the full bus width will be replicated over the full bus. For instance, a 32-bit write access from a LEON processor on a 64-bit bus will place the same data on bus bits 64:32 and 31:0. 25.7 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x017. For a description of vendor and device identifiers see GRLIB IP Library User’s Manual. 25.8 Implementation 25.8.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers, except synchronization registers, if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core will use asynchronous reset for all registers, except synchronization registers, if the GRLIB config package setting grlib_async_reset_enable is set. 25.8.2 Technology mapping DSU4 has one technology mapping generic, tech. This generic controls the implementation of which technology that will be used to implement the trace buffer memories. The AHB trace buffer will use two identical SYNCRAM64 blocks to implement the buffer memory (SYNCRAM64 may then result in two 32-bit wide memories on the target technology, depending on the technology map), with one additional 32-bit wide SYNCRAM if the system’s AMBA data bus width is 64-bits, and also one additional 64-bit wide SYNCRAM if the system’s AMBA data bus width exceeds 64 bits. The depth of the RAMs depends on the KBYTES generic. If KBYTES = 1 (1 Kbyte), then the depth will be 64. If KBYTES = 2, then the RAM depth will be 128 and so on. GRIP, Apr 2018, Version 2018.1 240 www.cobham.com/gaisler GRLIB IP Core 25.9 Configuration options Table 281 shows the configuration options of the core (VHDL generics). Table 281.Configuration options Generic Function Allowed range Default hindex AHB slave index 0 - NAHBSLV-1 0 haddr AHB slave address (AHB[31:20]) 0 - 16#FFF# 16#900# hmask AHB slave address mask 0 - 16#FFF# 16#F00# ncpu Number of attached processors 1 - 16 1 tbits Number of bits in the time tag counter 2 - 63 30 tech Memory technology for trace buffer RAM 0 - NTECH-1 0 (inferred) kbytes Size of trace buffer memory in KiB. A value of 0 will disable the trace buffer function. 0 - 64 0 (disabled) clk2x Enable LEON4 double-clocking (generic is only available on dsu4_2x and dsu4x entities, see next section) 0-1 0 bwidth Traced AHB bus width 32, 64, 128 64 ahbpf AHB performance counters and filtering. If ahbpf is non-zero the core will support AHB trace buffer filtering. If ahbpf is larger than 1 then the core’s statistical outputs will be enabled. 0-2 0 ahbwp AHB watchpoint enable. If ahbwp is non-zero 0-2 (default) then the core will support AHB watchpoints (also referred to as AHB data breakpoints). Pipeline registers will be added when ahbwp is set to 2 (default value), one register for each bit on the AMBA data bus. This setting is recommended in order to improve timing but has a cost in area. The pipeline registers will also lead to the AHB watchpoint being triggered one cycle later. It is recommended to leave this functionality enabled. However, the added logic can create critical timing paths from the AMBA data vectors and so AHB watchpoints can be completely disabled by setting this generic to 0. 2 scantest Scan test support enable 0-1 0 pipedbg Add pipeline registers on signals from LEON4. If critical timing paths show between, or through, the DSU4 and LEON4 then this value can be set to 1 to add pipeline registers on the dbgi input vector. This adds one additional wait state on some DSU register accesses. 0-1 0 pipeahbt Add pipeline registers on AMBA signals to AHB trace buffer. If there are critical timing paths between the AMBA AHB bus and the DSU AHB trace buffer memory then this value can be set to 1 to add one stage of pipelining between the AHB bus and the trace buffer RAM. 0-1 0 25.10 Signal descriptions Table 282 shows the interface signals of the core (VHDL ports). There are several top-level entities available for the DSU4. The dsu4x entity contains all signals and settings. The other entities are wrappers around dsu4x. The available entities are: GRIP, Apr 2018, Version 2018.1 241 www.cobham.com/gaisler GRLIB IP Core • dsu4 - Entity without support for double clocking. AHB trace of same bus as DSU AHB slave interface is connected to. • dsu4_2x - Entity with support for LEON4 double-clocking. AHB trace of same bus as DSU AHB slave interface is connected to. • dsu4_mb - Entity with support for AHB tracing of separate bus • dsu4x - Entity with support for all features (tracing of separate bus and LEON4 double-clocking). Table 282.Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock, used in dsu4_mb and dsu4 entities - HCLK N/A Input Bus clock, used in dsu4_2x and dsu4x entites, only used when double-clocking is enabled - CPUCLK N/A Input CPU clock, used in dsu4x and dsu4_2x entities - FCPUCLK N/A Input Free running (never gated) CPU clock, only used on dsu4x entity. - AHBMI * Input AHB master input signals, used for AHB tracing - AHBSI * Input AHB slave input signals, used for AHB tracing when using dsu4 and dsu4_2x entities - AHBSO * Output AHB slave output signals - TAHBSI * Input AHB slave input signals, used for AHB tracing when using dsu4_mb and dsu4x entities. - DBGI - Input Debug signals from LEON4 - DBGO - Output Debug signals to LEON4 - DSUI ENABLE Input DSU enable High BREAK Input DSU break High ACTIVE Output Debug mode High PWD[n-1 : 0] Output Clock gating enable for processor [n] High ASTAT (record) Output AHB statistic/performance counter events - N/A Input Double-clocking qualifier signal. Only used with double-clocking on dsu4_2x and dsu4x entities High DSUO HCLKEN * see GRLIB IP Library User’s Manual 25.11 Signal definitions and reset values The signals and their reset values are described in table 283. Table 283.Signal definitions and reset values Signal name Type Function Active Reset value dsuen Input DSU enable High - dsubre Input DSU break High - dsuact Output Debug mode High Logical 0 GRIP, Apr 2018, Version 2018.1 242 www.cobham.com/gaisler GRLIB IP Core 25.12 Timing The timing waveforms and timing parameters are shown in figure 62 and are defined in table 284. clk dsuact tDSU0 dsuen, dsubre tDSU1 tDSU0 tDSU2 Figure 62. Timing waveforms Table 284.Timing parameters Name Parameter Reference edge Min Max Unit tDSU0 clock to output delay rising clk edge TBD TBD ns tDSU1 input to clock hold rising clk edge - - ns tDSU2 input to clock setup rising clk edge - - ns Note: The dsubre and dsuen are re-synchronized internally. These signals do not have to meet any setup or hold requirements. 25.13 Library dependencies Table 285 shows libraries used when instantiating the core (VHDL libraries). Table 285.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER LEON4 Component, signals Component declaration, signals declaration 25.14 Component declaration The core has the following component declaration. component dsu4 generic ( hindex : integer := 0; haddr : integer := 16#900#; hmask : integer := 16#f00#; ncpu : integer := 1; tbits : integer := 30; tech : integer := 0; irq : integer := 0; kbytes : integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; ahbmi : in ahb_mst_in_type; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; dbgi : in l4_debug_out_vector(0 to NCPU-1); dbgo : out l4_debug_in_vector(0 to NCPU-1); dsui : in dsu4_in_type; dsuo : out dsu4_out_type GRIP, Apr 2018, Version 2018.1 243 www.cobham.com/gaisler GRLIB IP Core ); end component; 25.15 Instantiation This example shows how the core can be instantiated. The DSU is always instantiated with at least one LEON4 processor. It is suitable to use a generate loop for the instantiation of the processors and DSU and showed below. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.leon4.all; constant NCPU : integer := 1; -- select number of processors signal signal signal signal leon4i leon4o irqi irqo : : : : l4_in_vector(0 to NCPU-1); l4_out_vector(0 to NCPU-1); irq_in_vector(0 to NCPU-1); irq_out_vector(0 to NCPU-1); signal dbgi : l4_debug_in_vector(0 to NCPU-1); signal dbgo : l4_debug_out_vector(0 to NCPU-1); signal dsui signal dsuo : dsu4_in_type; : dsu4_out_type; . begin cpu : for i in 0 to NCPU-1 generate u0 : leon4s -- LEON4 processor generic map (ahbndx => i, fabtech => FABTECH, memtech => MEMTECH) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); irqi(i) <= leon4o(i).irq; leon4i(i).irq <= irqo(i); end generate; dsu0 : dsu4 -- LEON4 Debug Support Unit generic map (ahbndx => 2, ncpu => NCPU, tech => memtech, kbytes => 2) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= dsuen; dsui.break <= dsubre; dsuact <= dsuo.active; GRIP, Apr 2018, Version 2018.1 244 www.cobham.com/gaisler GRLIB IP Core 26 FTAHBRAM - On-chip SRAM with EDAC and AHB interface 26.1 Overview The FTAHBRAM core is a version of the AHBRAM core with added Error Detection And Correction (EDAC). The on-chip memory is accessed via an AMBA AHB slave interface. The memory implements a configurable amount of accessible memory (configured via the kbytes VHDL generic). Registers are accessed via an AMB APB interface. The on-chip memory implements volatile memory that is protected by means of Error Detection And Correction (EDAC). One error can be corrected and two errors can be detected, which is performed by using a (32, 7) BCH code or by technology specific protection provided by the target technology RAMs (implementation option, if supported by target technology). Some of the optional features available are single error counter, diagnostic reads and writes and additional pipeline registers. Configuration is performed via a configuration register. Figure 63 shows a block diagram of the internals of the controller. The block diagram shows the technology agnostic implementation. If target technology specific protection is selected then the encoder and decoder are not implemented in the FTAHBRAM. AHB Bus AHB Slave Interface FTAHBRAM data Mux AHB/APB Bridge error Configuration Register Mux Encoding Config bits TCB cb APB Bus Decoding Mux data cb Syncram Figure 63. Block diagram 26.2 Operation 26.2.1 Overview The on-chip fault tolerant memory is accessed through an AMBA AHB slave interface. The maximum AMBA access size supported is configurable through the maccsz VHDL generic. The controller supports all access sizes up to maccsz and the default value for maccsz is set to the maximum bus width configured for GRLIB (AHBDW constant). The memory address range is configurable with VHDL generics. As for the standard AHB RAM, the memory technology and size is configurable through the tech and kbytes VHDL generics. The minimum size is 1 KiB and the maximum is technology dependent. If the core is implemented without AHB pipeline registers then the EDAC functionality can be completely removed by setting the edacen VHDL generic to zero during synthesis. The APB interface is GRIP, Apr 2018, Version 2018.1 245 www.cobham.com/gaisler GRLIB IP Core also removed since it is redundant without EDAC. If AHB pipeline registers are included then EDAC is always enabled and the APB interface is present. Run-time configuration is done by writing to a configuration register accessed through an AMBA APB interface. The following can be configured during run-time: EDAC can be enabled and disabled. When it is disabled, reads and writes will behave as the standard memory. Read and write diagnostics can be controlled through separate bits. The single error counter can be reset. 26.2.2 Read and write behaviour If EDAC is disabled (EN bit in configuration register set to 0) write data is passed directly to the memory area and read data will appear on the AHB bus immediately after it arrives from memory. If EDAC is enabled write data is passed to an encoder which outputs a 7-bit checksum. The checksum is stored together with the data in memory and the whole operation is performed without any added waitstates. This applies to word and wider stores (32-bit, 64-bit, 128-bit). If a byte or halfword store is performed, the whole word to which the byte or halfword belongs must first be read from memory (read - modify - write). A new checksum is calculated when the new data is placed in the word and both data and checksum are stored in memory. This is done with 1 - 2 additional waitstates compared to the non EDAC case. Reads with EDAC disabled are performed with 0 or 1 waitstates while there could also be 2 waitstates when EDAC is enabled. There is no difference between wide, word and subword reads. Table 286 shows a summary of the number of waitstates for the different operations with and without EDAC. Table 286.Summary of the number of waitstates for the different operations for the memory. Operation Waitstates with EDAC Disabled Waitstates with EDAC Enabled Read 0-1 0-2 Word, DWord, 4Word write 0 0 Subword write 0 1-2 When EDAC is used, the data is decoded the first cycle after it arrives from the memory and appears on the bus the next cycle if no uncorrectable error is detected. The decoding is done by comparing the stored checksum with a new one which is calculated from the stored data. This decoding is also done during the read phase for a subword write. A so-called syndrome is generated from the comparison between the checksum and it determines the number of errors that occured. One error is automatically corrected and this situation is not visible on the bus. Two or more detected errors cannot be corrected so the operation is aborted and the required two cycle error response is given on the AHB bus (see the AMBA manual for more details). If no errors are detected data is passed through the decoder unaltered. 26.2.3 Read and write diagnostics As mentioned earlier the memory provides read and write diagnostics when EDAC is enabled. When write diagnostics are enabled, the calculated checksum is not stored in memory during the write phase. Instead, the TCB field from the configuration register is used. In the same manner, if read diagnostics are enabled, the stored checksum from memory is stored in the TCB field during a read (and also during a subword write). This way, the EDAC functionality can be tested during run-time. Note that checkbits are stored in TCB during reads and subword writes even if a multiple error is detected. Also note that the TCB field contains the check bits for a 32-bit word. If the controller has been implemented with support for wider accesses then it is recommended to load and bypass via TCB using only word accesses. For larger write accesses, the contents of TCB will be written as the checksum for all of the words within the larger access. For wide read accesses, the TCB field will hold the check bits for the least significant word. GRIP, Apr 2018, Version 2018.1 246 www.cobham.com/gaisler GRLIB IP Core 26.2.4 Error counter An additional feature is the single error counter which can be enabled with the errcnten VHDL generic or by enabling AHB pipeline registers. A single error counter (SEC) field is present in the configuration register, and is incremented each time a single databit error is encountered (reads or subword writes). The number of bits of this counter is 8, set with the cntbits VHDL generic. It is accessed through the configuration register. Each counter bit can be reset to zero by writing a one to it. The counter saturates at the value 28 - 1 (2cntbits - 1). For each access where single errors are detected the aramo.ce signal will be driven high for one cycle. This signal should be connected to an AHB status register which stores information and generates interrupts (see the AHB Status register documentation for more information). Note that if the maximum supported access size is 32 bits then only one single error can be detected. To support wider access sizes, the core implements several EDAC protected memories with 32-bit data in parallel. This means that a 64- or 128-bit access can trigger multiple single errors. If this happens then the error counter will be incremented with one. 26.2.5 Endianness The core is designed for big-endian systems. 26.3 Registers The core is programmed through registers mapped into APB address space. Table 287.FTAHBRAM registers APB Address offset Register 0x0 Configuration Register Table 288. 0x00 - CFG - Configuration Register 31 30 29 28 27 24 23 21 12+8 9 8 7 MEMSIZE WB RB EN 6 0 EDACEN 0 0 * 0 * 0 0 0 NR rw r r wc r * * * rw 24 SEC 10 R 27 MEMSIZE 13 12 DIAG TCB Value of edacen VHDL generic. 0: EDAC not implemented 1: Technology agnostic BCH EDAC (traditional FTAHBRAM EDAC) 2: Technology agnostic BCH EDAC, provided by SYNCRAMFT 3: Technology specific EDAC (SECDED) 23: 21 Log2 of the current memory size, bits 3:0 of value. Only used when ahbpupe VHDL generic is nonzero. 12+8: 13 Single error counter (SEC): Incremented each time a single error is corrected (includes errors on checkbits). Each bit can be set to zero by writing a one to it. This feature is only available if the errcnten VHDL generic is set. 12: Log2 of the current memory size, bits 2:0 of value 10 9 Write Bypass (WB): When set, the TCB field is stored as check bits when a write is performed to the memory. 8 Read Bypass (RB) : When set during a read or subword write, the check bits loaded from memory are stored in the TCB field. 7 EDAC Enable (EN): When set, the EDAC is used otherwise it is bypassed during read and write operations. If edacen (bits 27:24 of this register) is 2 or 3 then the core always behaves as if it is enabled for write and read timing. GRIP, Apr 2018, Version 2018.1 247 www.cobham.com/gaisler GRLIB IP Core Table 288. 0x00 - CFG - Configuration Register 6: 0 Test Check Bits (TCB) : Used as checkbits when the WB bit is set during writes and loaded with the check bits during a read operation when the RB bit is set. When the core makes use of technology specific EDAC then the behaviour of error injection is different. The TCB checkbits are propagated to the error injection bits of the SYNCRAMFT entity used within FTAHBRAM when the WB field is set to 1. Normally only one or two bits are used and the type of error injection supported is technology specific and described further in the SYNCRAMFT documentation. The RB field has no effect for technology specific EDAC. Any unused most significant bits are reserved. Always read as ‘000...0’. All fields except TCB are initialised at reset. The EDAC is initally disabled (EN = 0), which also applies to diagnostics fiels (RB and WB are zero). When available, the single error counter (SEC) field is cleared to zero. 26.4 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x050. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 26.5 Implementation 26.5.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. 26.6 Configuration options Table 289 shows the configuration options of the core (VHDL generics). Table 289.Configuration options Generic Function Allowed range Default hindex Selects which AHB select signal (HSEL) will be used to access the memory. 0 to NAHBMAX-1 0 haddr ADDR field of the AHB BAR 0 to 16#FFF# 0 hmask MASK field of the AHB BAR 0 to 16#FFF# 16#FFF# tech Memory technology 0 to NTECH 0 kbytes SRAM size in KiB. The RAM size needs to be a power of two. Otherwise the RAM size will be rounded up to the nearest power of two. 1 to targetdep. 1 0 to NAPBMAX-1 0 For implementations with ahbpipe=1 it is allowed to specify RAM sizes that are of the form 2^x+2^x-1. For example. Specifying a 192 KiB RAM size with ahbpipe = 0 will lead to a 256 KiB RAM area. Specifying a 192 KiB RAM size with ahbpipe = 0 allows a 192 KiB RAM to be implemented. However, specifying a 160 KiB RAM size will still lead to a 192 KiB RAM. pindex Selects which APB select signal (PSEL) will be used to access the memory configuration registers paddr The 12-bit MSB APB address 0 to 16#FFF# 0 pmask The APB address mask 0 to 16#FFF# 16#FFF# GRIP, Apr 2018, Version 2018.1 248 www.cobham.com/gaisler GRLIB IP Core Table 289.Configuration options Generic Function Allowed range Default hindex Selects which AHB select signal (HSEL) will be used to access the memory. 0 to NAHBMAX-1 0 haddr ADDR field of the AHB BAR 0 to 16#FFF# 0 hmask MASK field of the AHB BAR 0 to 16#FFF# 16#FFF# tech Memory technology 0 to NTECH 0 kbytes SRAM size in KiB. The RAM size needs to be a power of two. Otherwise the RAM size will be rounded up to the nearest power of two. 1 to targetdep. 1 0 to 3 0 Automatically store back corrected data with new check- 0 to 1 bits during a read when a single error is detected. Is ignored when edacen is deasserted. 0 For implementations with ahbpipe=1 it is allowed to specify RAM sizes that are of the form 2^x+2^x-1. For example. Specifying a 192 KiB RAM size with ahbpipe = 0 will lead to a 256 KiB RAM area. Specifying a 192 KiB RAM size with ahbpipe = 0 allows a 192 KiB RAM to be implemented. However, specifying a 160 KiB RAM size will still lead to a 192 KiB RAM. edacen Enable and select on-chip EDAC. Must be set to 1 or larger if ahbpipe generic is set to 1. 0: Disabled 1: Technology agnostic BCH EDAC (traditional FTAHBRAM EDAC) 2: Technology agnostic BCH EDAC, provided by SYNCRAMFT 3: Technology specific EDAC (SECDED) autoscrub This generic must be set to 0 if the ahbpipe generic is set to 1. errcnten Enables a single error counter. 0 to 1 0 1 to 8 1 This generic must be set to 1 if the ahbpipe generic is set to 1. cntbits number of bits in the single error counter. This generic must be set to 8 if the ahbpipe generic is set to 1. ahbpipe Selects to use FTAHBRAM2 architecture. Adds pipeline registers and requires edacen = 1, autoscrub = 0, errcnten = 1, cntbits = 8. 0 to 1 0 testen Test enable 0 to 1 0 maccsz Maximum access size supported by core 32 to 128 AHBDW GRIP, Apr 2018, Version 2018.1 249 www.cobham.com/gaisler GRLIB IP Core 26.7 Signal descriptions Table 290 shows the interface signals of the core (VHDL ports). Table 290.Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - APBI * Input APB slave input signals - APBO * Output APB slave output signals - ARAMO CE Output Single error detected High MTESTI** N/A Input Memory BIST input signal - MTESTO** N/A Output Memory BIST output signal - MTESTCLK** N/A Input Memory BIST clock - * see GRLIB IP Library User’s Manual ** not available in FPGA releases The aramo.ce signal is normally used to generate interrupts which starts an interrupt routine that corrects errors. Since this is not necessary when autoscrubbing is enabled, aramo.ce should not be connected to an AHB status register or the interrupt should be disabled in the interrupt controller 26.8 Library dependencies Tabel 291 shows libraries used when instantiating the core (VHDL libraries). Table 291.Library dependencies 26.9 Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Component Signals and component declaration Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; library gaisler; use grlib.amba.all; use gaisler.misc.all; entity ftram_ex is port( rst : std_ulogic; clk : std_ulogic; .... --others signals ); end; architecture rtl of ftram_ex is GRIP, Apr 2018, Version 2018.1 250 www.cobham.com/gaisler GRLIB IP Core --AMBA signal signal signal signal signals ahbsi : ahbso : apbi : apbo : ahb_slv_in_type; ahb_slv_out_type; apb_slv_in_type; apb_slv_out_vector; --other needed signals here signal stati : ahbstat_in_type; signal aramo : ahbram_out_type; begin --other component instantiations here ... -- AHB Status Register astat0 : ahbstat generic map(pindex => 13, paddr => 13, pirq => 11, nftslv => 3) port map(rstn, clkm, ahbmi, ahbso, stati, apbi, apbo(13)); stati.cerror(1 to NAHBSLV-1) <= (others => ‘0’); --FT AHB RAM a0 : ftahbram generic map(hindex => 1, haddr => 1, tech => inferred, kbytes => 64, pindex => 4, paddr => 4, edacen => 1, autoscrub => 0, errcnt => 1, cntbits => 4) port map(rst, clk, ahbsi, ahbso(1), apbi, apbo(4), aramo); stati.cerror(0) <= aramo.ce; end architecture; GRIP, Apr 2018, Version 2018.1 251 www.cobham.com/gaisler GRLIB IP Core 27 FTMCTRL - 8/16/32-bit Memory Controller with EDAC 27.1 Overview The FTMCTRL combined 8/16/32-bit memory controller provides a bridge between external memory and the AHB bus. The memory controller can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (IO). The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39,7) BCH code. The BCH code provides single-error correction and double-error detection for each 32-bit memory word. The SDRAM area can optionally also be protected using Reed-Solomon coding. In this case a 16-bit checksum is used for each 32-bit word, and any two adjacent 4-bit (nibble) errors can be corrected. The EDAC capability is determined through a VHDL generic. The memory controller is configured through three configuration registers accessible via an APB bus interface. The PROM, IO, and SRAM external data bus can be configured in 8-, 16-, or 32-bit mode, depending on application requirements. The controller decodes three address spaces on the AHB bus (PROM, IO, and SRAM/SDRAM). The addresses are determined through VHDL generics. The IO area is marked as non-cacheable in the core’s AMBA plug’n’play information record. External chip-selects are provided for up to four PROM banks, one IO bank, five SRAM banks and two SDRAM banks. Figure 64 below shows how the connection to the different device types is made. APB A AHB APB ROMSN[3 :0] OEN WRITEN CS OE WE PROM IOSN CS OE WE I/O FTMCTRL RAMSN[4:0] RAMOEN[4:0] RWEN[3:0] MBEN[3:0] AHB SDCSN[1:0] SDRASN SDCASN SDWEN SDDQM[3:0] CS OE WE MBEN CSN RAS CAS WE DQM SRAM SDRAM D CB A D CB A D A D CB A D CB A[27:0] D[31:0] CB[15:0] Figure 64. FTMCTRL connected to different types of 32+cb-bit memory devices 27.2 PROM access Up to four PROM chip-select signals are provided for the PROM area, ROMSN[3:0]. There are two modes: one with two chip-select signals and one with four. The size of the banks can be set in binary steps from 16KiB to 256MiB. If the AHB memory area assigned to the memory controller for PROM accesses is larger than the combined size of the memory banks then the PROM memory area will wrap, starting with the first chip-select being asserted again when accessing addresses higher than the last decoded bank. A read access to PROM consists of two data cycles and between 0 and 30 waitstates (in the default configuration, see wsshift VHDL generic documentation for details). The read data (and optional GRIP, Apr 2018, Version 2018.1 252 www.cobham.com/gaisler GRLIB IP Core EDAC check-bits) are latched on the rising edge of the clock on the last data cycle. On non-consecutive accesses, a idle cycle is placed between the read cycles to prevent bus contention due to slow turn-off time of PROM devices. Figure 65 shows the basic read cycle waveform (zero waitstate) for non-consecutive PROM reads. Note that the address is undefined in the idle cycle. Figure 66 shows the timing for consecutive cycles (zero waitstate). Waitstates are added by extending the data2 phase. This is shown in figure 67 and applies to both consecutive and non-consecutive cycles. Only an even number of waitstates can be assigned to the PROM area. data1 data2 data1 data2 clk address A1 A2 romsn oen data cb D1 D2 CB1 CB2 Figure 65. Prom non-consecutive read cyclecs. data1 data2 data1 data data2 clk address A2 A1 romsn oen data cb D1 D2 CB1 CB2 Figure 66. Prom consecutive read cyclecs. GRIP, Apr 2018, Version 2018.1 253 www.cobham.com/gaisler GRLIB IP Core data1 data2 data2 data data2 clk address A1 romsn oen data D1 cb CB1 Figure 67. Prom read access with two waitstates. lead-in data lead-out clk address A1 romsn rwen data D1 cb CB1 Figure 68. Prom write cycle (0-waitstates) lead-in data data data lead-out clk address A1 romsn rwen data cb D1 CB1 Figure 69. Prom write cycle (2-waitstates) GRIP, Apr 2018, Version 2018.1 254 www.cobham.com/gaisler GRLIB IP Core 27.3 Memory mapped IO Accesses to IO have similar timing as PROM accesses. The IO select (IOSN) and output enable (OEN) signals are delayed one clock to provide stable address before IOSN is asserted. All accesses are performed as non-consecutive accesses as shown in figure 70. The data2 phase is extended when waitstates are added. lead-in data1 data2 lead-out clk address A1 iosn oen data D1 cb CB1 Figure 70. I/O read cycle (0-waitstates) lead-in data lead-out clk address A1 iosn writen data cb D1 CB1 Figure 71. I/O write cycle (0-waitstates) 27.4 SRAM access The SRAM area is divided on up to five RAM banks. The size of banks 1-4 (RAMSN[3:0]) is programmed in the RAM bank-size field (MCFG2[12:9]) and can be set in binary steps from 8KiB to 256MiB. The fifth bank (RAMSN[4]) decodes the upper 512MiB (controlled by means of the sdrasel VHDL generic) and cannot be used simultaneously with SDRAM memory. A read access to SRAM consists of two data cycles and between zero and three waitstates (in the default configuration, see wsshift VHDL generic documentation for details). The read data (and optional EDAC check-bits) are latched on the rising edge of the clock on the last data cycle. Accesses to RAMSN[4] can further be stretched by de-asserting BRDYN until the data is available. On non-consecutive accesses, a idle cycle is added after a read cycle to prevent bus contention due to slow turn-off time of memories. Fig- GRIP, Apr 2018, Version 2018.1 255 www.cobham.com/gaisler GRLIB IP Core ure 72 shows the basic read cycle waveform (zero waitstate). Waitstates are added in the same way as for PROM in figure 67. data1 data2 data1 data2 clk address A1 A2 ramsn oen, ramoen data cb D1 D2 CB1 CB2 Figure 72. Sram non-consecutive read cyclecs. For read accesses to RAMSN[4:0], a separate output enable signal (RAMOEN[n]) is provided for each RAM bank and only asserted when that bank is selected. A write access is similar to the read access but takes a minimum of three cycles. Waitstates are added in the same way as for PROM. Each byte lane has an individual write strobe to allow efficient byte and half-word writes. If the memory uses a common write strobe for the full 16- or 32-bit data, the read-modify-write bit MCFG2 should be set to enable read-modify-write cycles for sub-word writes. lead-in data lead-out clk address A1 ramsn rwen data cb D1 CB1 Figure 73. Sram write cycle (0-waitstates) GRIP, Apr 2018, Version 2018.1 256 www.cobham.com/gaisler GRLIB IP Core rdata1 rdata2 modify wdata lead-out clk address A1 ramsn oen, ramoen rwen data cb D1 nD1 CB1 nCB1 read Figure 74. Sram read-modify-write cycle (0-waitstates) 27.5 8-bit and 16-bit PROM and SRAM access To support applications with low memory and performance requirements efficiently, the SRAM and PROM areas can be individually configured for 8- or 16-bit operation by programming the ROM and RAM width fields in the memory configuration registers. Since reads to memory are always done on 32-bit word basis, read access to 8-bit memory will be transformed in a burst of four read cycles while access to 16-bit memory will generate a burst of two 16-bit reads. During writes, only the necessary bytes will be written. Figure 75 shows an interface example with 8-bit PROM and 8-bit SRAM. Figure 76 shows an example of a 16-bit memory interface. All possible combinations of width, EDAC, and RMW are not supported. The supported combinations are given in table 292, and the behavior of setting an unsupported combination is undefined. It is not allowed to set the ROM or RAM width fields to 8-bit or 16-bit width if the core does not implement support for these widths. Table 292.FTMCTRL supported SRAM and PROM configurations PROM/SRAM bus width RWEN resolution (SRAM) EDA C RMW bit (SRAM) Core configuration 8 Bus width None 0 8-bit support 8 Bus width BCH 1 8-bit support, EDAC 16 Byte None 0 16-bit support 16 Bus width None 1 16-bit support 32 Byte None 0 32 Bus width None 1 32+7 Bus width BCH 1 EDAC support 8-bit width support is set with ram8 VHDL generic and 16-bit width support is set with ram16 VHDL genericis. GRIP, Apr 2018, Version 2018.1 257 www.cobham.com/gaisler GRLIB IP Core 8-bit PROM ROMSN[0] OEN WRITEN CS OE WE MEMORY CONTROLLER RAMSN[0] RAMOEN[0] RWEN[0] PROM A D A D A[25:0] D[31:24] 8-bit RAM CS OE RWE[0] WE SRAM A D A[25:0] D[31:24] A[27:0] D[31:24]/ D[31:24] Figure 75. 8-bit memory interface example 16-bit PROM ROMSN[0] OEN WRITEN CS OE WE MEMORY CONTROLLER RAMSN[0] RAMOEN[0] RWEN[0:1] PROM A D A D A[26:1] D[31:16] 16-bit RAM CS OE RWE[1:0] WE SRAM A D A[26:1] D[31:16] A[27:0] D[31:16]/ D[31:16] Figure 76. 16-bit memory interface example In 8-bit mode, the PROM/SRAM devices should be connected to the MSB byte of the data bus (D[31:24]). The LSB address bus should be used for addressing (A[25:0]). In 16-bit mode, D[31:16] should be used as data bus, and A[26:1] as address bus. 27.6 8- and 16-bit I/O access Similar to the PROM/SRAM areas, the IO area can also be configured to 8- or 16-bits mode. However, the I/O device will NOT be accessed by multiple 8/16 bits accesses as the memory areas, but only with one single access just as in 32-bit mode. To access an IO device on an 8-bit bus, only byte accesses should be used (LDUB/STB instructions for the CPU). To accesses an IO device on a 16-bit bus, only halfword accesses should be used (LDUH/STH instructions for the CPU). GRIP, Apr 2018, Version 2018.1 258 www.cobham.com/gaisler GRLIB IP Core To access the I/O-area in 8- or 16-bit mode, ram8 VHDL generic or ram16 VHDL generic must be set respectively. 27.7 Burst cycles To improve the bandwidth of the memory bus, accesses to consecutive addresses can be performed in burst mode. Burst transfers will be generated when the memory controller is accessed using an AHB burst request. These includes instruction cache-line fills, double loads and double stores. The timing of a burst cycle is identical to the programmed basic cycle with the exception that during read cycles, the idle cycle will only occurs after the last transfer. Burst cycles will not be generated to the IO area. Only word (HSIZE = “010”) bursts of incremental type (HBURST=INCR, INCR4, INCR8 or INCR16) are supported. 27.8 SDRAM access 27.8.1 General Synchronous dynamic RAM (SDRAM) access is supported to two banks of PC100/PC133 compatible devices. This is implemented by a special version of the SDCTRL SDRAM controller core from Cobham Gaisler, which is optionally instantiated as a sub-block. The SDRAM controller supports 64M, 256M and 512M devices with 8 - 12 column-address bits, and up to 13 row-address bits. The size of the two banks can be programmed in binary steps between 4MiB and 512MiB. The operation of the SDRAM controller is controlled through MCFG2 and MCFG3 (see below). Both 32- and 64-bit data bus width is supported, allowing the interface of 64-bit DIMM modules. The memory controller can be configured to use either a shared or separate bus connecting the controller and SDRAM devices. 27.8.2 Address mapping The two SDRAM chip-select signals are decoded. SDRAM area is mapped into the upper half of the RAM area defined by BAR2 register, and cannot be used simultaneously with fifth SRAM bank (RAMSN[4]). When the SDRAM enable bit is set in MCFG2, the controller is enabled and mapped into upper half of the RAM area as long as the SRAM disable bit is not set. If the SRAM disable bit is set, all access to SRAM is disabled and the SDRAM banks are mapped into the lower half of the RAM area. 27.8.3 Initialisation When the SDRAM controller is enabled, it automatically performs the SDRAM initialisation sequence of PRECHARGE, 8x AUTO-REFRESH and LOAD-MODE-REG on both banks simultaneously. The controller programs the SDRAM to use single location access on write. The controller programs the SDRAM to use line burst of length 8 when pageburst VHDL generic is 0. The controller programs the SDRAM to use page burst when pageburst VHDL generic is 1. The controller programs the SDRAM to use page burst or line burst of length 8, selectable via the MCFG2 register, when pageburst VHDL generic is 2. 27.8.4 Configurable SDRAM timing parameters To provide optimum access cycles for different SDRAM devices (and at different frequencies), three SDRAM parameters can be programmed through memory configuration register 2 (MCFG2): TCAS, TRP and TRFCD. The value of these field affects the SDRAM timing as described in table 293. GRIP, Apr 2018, Version 2018.1 259 www.cobham.com/gaisler GRLIB IP Core Table 293.SDRAM programmable minimum timing parameters SDRAM timing parameter Minimum timing (clocks) CAS latency, RAS/CAS delay (tCAS, tRCD) TCAS + 2 Precharge to activate (tRP) TRP + 2 Auto-refresh command period (tRFC) TRFC + 3 Activate to precharge (tRAS) TRFC + 1 Activate to Activate (tRC) TRP + TRFC + 4 If the TCAS, TRP and TRFC are programmed such that the PC100/133 specifications are fulfilled, the remaining SDRAM timing parameters will also be met. The table below shows typical settings for 100 and 133 MHz operation and the resulting SDRAM timing (in ns): Table 294.SDRAM example programming SDRAM settings tCAS tRC tRP tRFC tRAS 100 MHz, CL=2; TRP=0, TCAS=0, TRFC=4 20 80 20 70 50 100 MHz, CL=3; TRP=0, TCAS=1, TRFC=4 30 80 20 70 50 133 MHz, CL=2; TRP=1, TCAS=0, TRFC=6 15 82 22 67 52 133 MHz, CL=3; TRP=1, TCAS=1, TRFC=6 22 82 22 67 52 27.8.5 Refresh The SDRAM controller contains a refresh function that periodically issues an AUTO-REFRESH command to both SDRAM banks. The period between the commands (in clock periods) is programmed in the refresh counter reload field in the MCFG3 register. Depending on SDRAM type, the required period is typically 7.8 or 15.6 s (corresponding to 780 or 1560 clocks at 100 MHz). The generated refresh period is calculated as (reload value+1)/sysclk. The refresh function is enabled by setting bit 31 in MCFG2. 27.8.6 SDRAM commands The controller can issue three SDRAM commands by writing to the SDRAM command field in MCFG2: PRE-CHARGE, AUTO-REFRESH and LOAD-MODE-REG (LMR). If the LMR command is issued, the CAS delay as programmed in MCFG2 will be used. Line burst of length 8 will be set for read when pageburst VHDL generic is 0. Page burst will be set for read when pageburst VHDL generic is 1. Page burst or line burst of length 8, selectable via the MCFG2 register will be set, when pageburst VHDL generic is 2. Remaining fields are fixed: single location write, sequential burst. The command field will be cleared after a command has been executed. When changing the value of the CAS delay, a LOAD-MODE-REGISTER command should be generated at the same time. NOTE: when issuing SDRAM commands, the SDRAM refresh must be disabled. 27.8.7 Read cycles A read cycle is started by performing an ACTIVATE command to the desired bank and row, followed by a READ command after the programmed CAS delay. A read burst is performed if a burst access has been requested on the AHB bus. The read cycle is terminated with a PRE-CHARGE command, no banks are left open between two accesses. GRIP, Apr 2018, Version 2018.1 260 www.cobham.com/gaisler GRLIB IP Core 27.8.8 Write cycles Write cycles are performed similarly to read cycles, with the difference that WRITE commands are issued after activation. A write burst on the AHB bus will generate a burst of write commands without idle cycles in-between. After the WRITE command has completed, if there is an immediately following read or write access (not RMW) to the same 1KiB page on the AHB bus, this access is performed during the same access cycle without closing and re-opening the row. 27.8.9 Read-modify-write cycles If EDAC is enabled and a byte or half-word write is performed, the controller will perform a readmodify-write cycle to update the checkbits correctly. This is done by performing an ACTIVATE command, followed by READ, WRITE and PRE-CHARGE. The write command interrupts the read burst and the data mask signals will be raised two cycles before this happens as required by the SDRAM standard. 27.8.10 Address bus The memory controller can be configured to either share the address and data buses with the SRAM, or to use separate address and data buses. When the buses are shared, the address bus of the SDRAMs should be connected to A[14:2], the bank address to A[16:15]. The MSB part of A[14:2] can be left unconnected if not used. When separate buses are used, the SDRAM address bus should be connected to SA[12:0] and the bank address to SA[14:13]. 27.8.11 Data bus SDRAM can be connected to the memory controller through the common or separate data bus. If the separate bus is used the width is configurable to 32 or 64 bits. 64-bit data bus allows the 64-bit SDRAM devices to be connected using the full data capacity of the devices. 64-bit SDRAM devices can be connected to 32-bit data bus if 64-bit data bus is not available but in this case only half the full data capacity will be used. There is a drive signal vector and separate data vector available for SDRAM. The drive vector has one drive signal for each data bit. These signals can be used to remove timing problems with the output delay when a separate SDRAM bus is used. 27.8.12 Clocking The SDRAM controller is designed for an external SDRAM clock that is in phase or slightly earlier than the internal AHB clock. This provides the maximum margin for setup and hold on the external signals, and allows highest possible frequency. For Xilinx and Altera device, the GRLIB Clock Generator (CLKGEN) can be configured to produce a properly synchronized SDRAM clock. For other FPGA targets, the custom clock synchronization must be designed. For ASIC targets, the SDRAM clock can be derived from the AHB clock with proper delay adjustments during place&route. 27.8.13 Initialisation Each time the SDRAM is enabled (bit 14 in MCFG2), an SDRAM initialisation sequence will be sent to both SDRAM banks. The sequence consists of one PRECHARGE, eight AUTO-REFRESH and one LOAD-COMMAND-REGISTER command. 27.9 Memory EDAC 27.9.1 BCH EDAC The FTMCTRL is provided with an BCH EDAC that can correct one error and detect two errors in a 32-bit word. For each word, a 7-bit checksum is generated according to the equations below. A cor- GRIP, Apr 2018, Version 2018.1 261 www.cobham.com/gaisler GRLIB IP Core rectable error will be handled transparently by the memory controller, but adding one waitstate to the access. If an un-correctable error (double-error) is detected, the current AHB cycle will end with an error response. The EDAC can be used during access to PROM, SRAM and SDRAM areas by setting the corresponding EDAC enable bits in the MCFG3 register. The equations below show how the EDAC checkbits are generated: CB0 CB1 CB2 CB3 CB4 CB5 CB6 = = = = = = = D0 D0 D0 D0 D2 D8 D0 ^ ^ ^ ^ ^ ^ ^ D4 D1 D3 D1 D3 D9 D1 ^ ^ ^ ^ ^ ^ ^ D6 ^ D7 ^ D2 ^ D4 ^ D4 ^ D7 ^ D5 ^ D6 ^ D4 ^ D5 ^ D10 ^ D11 D2 ^ D3 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31 D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28 D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31 D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29 D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 If the SRAM is configured in 8-bit mode, the EDAC checkbit bus (CB[7:0]) is not used but it is still possible to use EDAC protection. Data is always accessed as words (4 bytes at a time) and the corresponding checkbits are located at the address acquired by inverting the word address (bits 2 to 27) and using it as a byte address. The same chip-select is kept active. A word written as four bytes to addresses 0, 1, 2, 3 will have its checkbits at address 0xFFFFFFF, addresses 4, 5, 6, 7 at 0xFFFFFFE and so on. All the bits up to the maximum bank size will be inverted while the same chip-select is always asserted. This way all the bank sizes can be supported and no memory will be unused (except for a maximum of 4 byte in the gap between the data and checkbit area). A read access will automatically read the four data bytes individually from the nominal addresses and the EDAC checkbit byte from the top part of the bank. A write cycle is performed the same way. Byte or half-word write accesses will result in an automatic read-modify-write access where 4 data bytes and the checkbit byte are firstly read, and then 4 data bytes and the newly calculated checkbit byte are writen back to the memory. This 8-bit mode applies to SRAM while SDRAM always uses 32-bit accesses. The size of the memory bank is determined from the settings in MCFG2. The EDAC cannot be used on memory areas configured in 16-bit mode. If the ROM is configured in 8-bit mode, EDAC protection is provided in a similar way as for the SRAM memory described above. The difference is that write accesses are not being handled automatically. Instead, write accesses must only be performed as individual byte accesses by the software, writing one byte at a time, and the corresponding checkbit byte must be calculated and be written to the correct location by the software. NOTE: when the EDAC is enabled in 8-bit bus mode, only the first bank select (RAMSN[0], PROMSN[0]) can be used. The operation of the EDAC can be tested trough the MCFG3 register. If the WB (write bypass) bit is set, the value in the TCB field will replace the normal checkbits during memory write cycles. If the RB (read bypass) is set, the memory checkbits of the loaded data will be stored in the TCB field during memory read cycles. NOTE: when the EDAC is enabled, the RMW bit in memory configuration register 2 must be set. Data access timing with EDAC enabled is identical to access without EDAC, if the edac VHDL generic is set to 1. To improve timing of the HREADY output, a pipeline stage can be inserted in the EDAC error detection by setting the edac VHDL generic to 2. One clock extra latency will then occur on single word reads, or on the first data word in a burst. EDAC is not supported for 64-bit wide SDRAM data buses. 27.9.2 Reed-Solomon EDAC The Reed-Solomon EDAC provides block error correction, and is capable of correcting up to two 4bit nibble errors in a 32-bit data word or 16-bit checksum. The Reed-Solomon EDAC can be enabled for the SDRAM area only, and uses a 16-bit checksum. Operation and timing is identical to the BCH EDAC with the pipeline option enabled. The Reed-Solomon EDAC is enabled by setting the RSE and GRIP, Apr 2018, Version 2018.1 262 www.cobham.com/gaisler GRLIB IP Core RE bits in MCFG3, and the RMW bit in MCFG2. The Reed-Solomon EDAC is not supported for 64bit wide SDRAM buses. The Reed-Solomon data symbols are 4-bit wide, represented as GF(2^4). The basic Reed-Solomon code is a shortened RS(15, 13, 2) code, represented as RS(6, 4, 2). It has the capability to detect and correct a single symbol error anywhere in the codeword. The EDAC implements an interleaved RS(6, 4, 2) code where the overall data is represented as 32 bits and the overall checksum is represented as 16 bits. The codewords are interleaved nibble-wise. The interleaved code can correct two 4-bit errors when each error is located in a nibble and not in the same original RS(6, 4, 2) codeword. The Reed-Solomon RS(15, 13, 2) code has the following definition: • there are 4 bits per symbol; • there are 15 symbols per codeword; • the code is systematic; • the code can correct one symbol error per codeword; • the field polynomial is 4 fx = x + x + 1 • the code generator polynomial is 1 g x = 2  x +   i i=0 =  gj  x j j=0 for which the highest power of x is stored first; • a codeword is defined as 15 symbols: c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14 where c0 to c12 represent information symbols and c13 to c14 represent check symbols. The shortened and interleaved RS(6, 4, 2) code has the following definition: • the codeword length is shortened to 4 information symbols and 2 check symbols and as follows: c0 = c1 = c2 = c3 = c4 = c5 = c6 = c7 = c8 = 0 where the above information symbols are suppressed or virtually filled with zeros; • two codewords are interleaved (i.e. interleaved depth I=2) with the following mapping to the 32bit data and 16-bit checksum, were ci,j is a symbol with codeword index i and symbol index j: c0,9 = sd[31:28] c1,9 = sd[27:24] c0,10 = sd[23:20] c1,10 = sd[19:16] c0,11 = sd[15:12] c1,11 = sd[11:8] c0,12 = sd[7:4] c1,12 = sd[3:0] c0,13 = scb[15:12] c1,13 = scb[11:8] GRIP, Apr 2018, Version 2018.1 263 www.cobham.com/gaisler GRLIB IP Core c0,14 = scb[7:4] c1,14 = scb[3:0] where SD[ ] is interchanable with DATA[] and SCB[ ] is interchangable with CB[ ] Note that the FTMCTRL must have the edac VHDL generic set to 3 to enable the RS EDAC functionality. The Reed-Solomon EDAC is not supported for 64-bit wide SDRAM buses. 27.9.3 EDAC Error reporting As mentioned above an un-correctable error results in an AHB error response which can be monitored on the bus. Correctable errors however are handled transparently and are not visible on the AHB bus. A sideband signal is provided which is asserted during one clock cycle for each access for which a correctable error is detected. This can be used for providing an external scrubbing mechanism and/or statistics. The correctable error signal is most commonly connected to the AHB status register which monitors both this signal and error responses on the bus. Please see the AHB status register section for more information. 27.10 Bus Ready signalling The BRDYN signal can be used to stretch all types of access cycles to the PROM, I/O area and the SRAM area decoded by RAMSN[4]. This covers read and write accesses in general, and additionally read-modify-write accesses to the SRAM area. The accesses will always have at least the pre-programmed number of waitstates as defined in memory configuration registers 1 & 2, but will be further stretched until BRDYN is asserted. BRDYN should be asserted in the cycle preceding the last one. If bit 29 in MCFG1 is set, BRDYN can be asserted asynchronously with the system clock. In this case, the read data must be kept stable until the de-assertion of OEN/RAMOEN and BRDYN must be asserted for at least 1.5 clock cycle. The use of BRDYN can be enabled separately for the PROM, I/O and RAMSN[4] areas. It is recommended that BRDYN is asserted until the corresponding chip select signal is de-asserted, to ensure that the access has been properly completed and avoiding the system to stall. data1 data2 data2 lead-out clk address A1 romsn/iosn/ramsn[4] oen data D1 brdyn Figure 77. READ cycle with one extra data2 cycle added with BRDYN (synchronous sampling). Lead-out cycle is only applicable for I/O accesses. Figure 78 shows the use of BRDYN with asynchronous sampling. BRDYN is kept asserted for more than 1.5 clock-cycle. Two synchronization registers are used so it will take at least one additional cycle from when BRDYN is first asserted until it is visible internally. In figure 78 one cycle is added to the data2 phase. GRIP, Apr 2018, Version 2018.1 264 www.cobham.com/gaisler GRLIB IP Core data1 data2 data2 lead-out clk address A1 romsn/iosn/ramsn[4] oen data D1 brdyn bexcn Figure 78. BRDYN (asynchronous) sampling and BEXCN timing. Lead-out cycle is only applicable for I/O-accesses. data1 clk address data2 data2 ws data2 brdyn lead-out A1 romsn/iosn/ramsn[4] oen data D1 brdyn Figure 79. Read cycle with one waitstate (configured) and one BRDYN generated waitstate (synchronous sampling). If burst accesses and BRDYN signaling are to be used together, special care needs to be taken to make sure BRDYN is raised between the separate accesses of the burst. The controller does not raise the select and OEN signal (in the read case) between accesses during the burst so if BRDYN is kept asserted until the select signal is raised, all remaining accesses in the burst will finish with the configured fixed number of wait states. The core can optionally be implemented with a bus ready timeout counter. The counter value and counter reload value are then available in MCFG7. The counter will be reloaded whenever the bus ready signal is low (asserted). If the reload value is nonzero, then the counter will decrement with one each clock cycle the core is waiting for bus ready to be asserted. If the counter reaches zero, the action taken depends on the state of Bus Error Enable (BEXCN) in MCFG1. If BEXCN is ‘1’, then an AMBA ERROR response will be generated and the counter will be reloaded. If BEXCN is ‘0’, then the bus ready enable for the accessed memory area will be disabled and the core will ignore bus ready for the accessed area. Bus ready timeout functionality is disabled when the bus ready counter reload value is zero (MCFG7.BRDYCNTRLD = 0). GRIP, Apr 2018, Version 2018.1 265 www.cobham.com/gaisler GRLIB IP Core 27.11 Access errors An access error can be signalled by asserting the BEXCN signal for read and write accesses. For reads it is sampled together with the read data. For writes it is sampled on the last rising edge before chip select is de-asserted, which is controlled by means of waitstates or bus ready signalling. If the usage of BEXCN is enabled in memory configuration register 1, an error response will be generated on the internal AHB bus. BEXCN can be enabled or disabled through memory configuration register 1, and is active for all areas (PROM, IO and RAM). BEXCN is only sampled in the last access for 8- and 16bit mode for RAM and PROM. That is, when four bytes are written for a word access to 8-bit wide memory BEXCN is only sampled in the last access with the same timing as a single access in 32-bit mode. data1 data2 lead-out clk address A1 romsn/iosn/ramsn oen data D1 bexcn Figure 80. Read cycle with BEXCN. lead-in data2 lead-out clk address A1 romsn/iosn/ramsn rwen data D1 bexcn Figure 81. Write cycle with BEXCN. Chip-select (iosn) is not asserted in lead-in cycle for io-accesses. 27.12 Attaching an external DRAM controller To attach an external DRAM controller, RAMSN[4] should be used since it allows the cycle time to vary through the use of BRDYN. In this way, delays can be inserted as required for opening of banks and refresh. GRIP, Apr 2018, Version 2018.1 266 www.cobham.com/gaisler GRLIB IP Core 27.13 Output enable timing A drive signal vector for the data I/O-pads is provided which has one drive signal for each data bit. It can be used if the synthesis tool does not generate separate registers automatically for the current technology. This can remove timing problems with output delay. An additional vector is used for the separate SDRAM bus. 27.14 Read strobe The READ signal indicates the direction of the current PROM,SRAM,IO or SDRAM transfer, and it can be used to drive external bi-directional buffers on the data bus. It always is valid at least one cycle before and after the bus is driven, at other times it is held either constant high or low. 27.15 Endianness The core is designed for big-endian systems. 27.16 Registers The core is programmed through registers mapped into APB address space. Table 295.FTMCTRL memory controller registers APB Address offset Register 0x0 Memory configuration register 1 (MCFG1) 0x4 Memory configuration register 2 (MCFG2) 0x8 Memory configuration register 3 (MCFG3) 0xC Memory configuration register 4 (MCFG4) 0x10 Memory configuration register 5 (MCFG5) 0x14 Memory configuration register 6 (MCFG6) 0x18 Memory configuration register 7 (MCFG7) 27.16.1 Memory configuration register 1 (MCFG1) Memory configuration register 1 is used to program the timing of rom and IO accesses. Table 296.0x00 - MCFG1 - Memory configuration register 1 31 30 29 28 PBRDY ABRDY 27 IOBUSW 26 25 24 23 IBRDY BEXCN 20 IO WAITSTATES 19 18 IOEN R ROMBANKSZ 17 0 0 NR 0 0 0 0x00 0 0 0x0 rw rw rw rw rw r rw rw r rw 14 13 11 10 9 8 PWEN RES 0 0 r rw ROMANKS7 rw 12 RESERVED 7 4 3 0 PROM WIDTH PROM WRITE WS PROM READ WS 0 * 0xE 0xE r rw rw rw 31 RESERVED 30 PROM area bus ready enable (PBRDY) - Enables bus ready (BRDYN) signalling for the PROM area. Reset to ‘0’. 29 Asynchronous bus ready (ABRDY) - Enables asynchronous bus ready. 28 : 27 I/O bus width (IOBUSW) - Sets the data width of the I/O area (“00”=8, “01”=16, “10” =32). 26 I/O bus ready enable (IBRDY) - Enables bus ready (BRDYN) signalling for the I/O area. Reset to ‘0’. 25 Bus error enable (BEXCN) - Enables bus error signalling for all areas. Reset to ‘0’. 24 RESERVED GRIP, Apr 2018, Version 2018.1 267 www.cobham.com/gaisler GRLIB IP Core Table 296.0x00 - MCFG1 - Memory configuration register 1 23 : 20 I/O waitstates (IO WAITSTATES) - Sets the number of waitstates during I/O accesses (“0000”=0, “0001”=1, “0010”=2,..., “1111”=15). The values above describe the default configuration The core can be configred at implementation to extend the number of waitstates. The number of wait states inserted will be (IO WAITSTATES)*2wsshift , where wsshift can be read from the first user-defined register in the core’s plug&play area (default is wsshift = 0). 19 I/O enable (IOEN) - Enables accesses to the memory bus I/O area. 18 RESERVED 17: 14 PROM bank size (ROMBANKSZ) - Returns current PROM bank size when read. “0000” is a special case and corresponds to a bank size of 256MiB. All other values give the bank size in binary steps: “0001”=16KiB, “0010”=32KiB, “0011”=64KiB,... , “1111”=256MiB (i.e. 8KiB * 2**ROMBANKSZ). For value “0000” or “1111” only two chip selects are available. For other values, two chip select signals are available for fixed bank sizes. For other values, four chip select signals are available for programmable bank sizes. Programmable bank sizes can be changed by writing to this register field. The written values correspond to the bank sizes and number of chip-selects as above. Reset to “0000” when programmable. Programmable ROMBANKSZ is only available when romasel VHDL generic is 0. For other values this is a read-only register field containing the fixed bank size value. 13:12 RESERVED 11 PROM write enable (PWEN) - Enables write cycles to the PROM area. 10 RESERVED 9:8 PROM width (PROM WIDTH) - Sets the data width of the PROM area (“00”=8, “01”=16, “10”=32). 7:4 PROM write waitstates (PROM WRITE WS) - Sets the number of wait states for PROM write cycles (“0000”=0, “0001”=2, “0010”=4,..., “1111”=30). The values above describe the default configuration The core can be configred at implementation to extend the number of waitstates. The number of wait states inserted will be (PROM WRITE WS)*2*2wsshift, where wsshift can be read from the first user-defined register in the core’s plug&play area (default is wsshift = 0). 3:0 PROM read waitstates (PROM READ WS) - Sets the number of wait states for PROM read cycles (“0000”=0, “0001”=2, “0010”=4,...,”1111”=30). Reset to “1111”. The values above describe the default configuration The core can be configred at implementation to extend the number of waitstates. The number of wait states inserted will be (PROM READ WS)*2*2wsshift, where wsshift can be read from the first user-defined register in the core’s plug&play area (default is wsshift = 0). During reset, the prom width (bits [9:8]) are set with value on BWIDTH inputs. The prom waitstates fields are set to 15 (maximum). External bus error and bus ready are disabled. All other fields are undefined. 27.16.2 Memory configuration register 2 (MCFG2) Memory configuration register 2 is used to control the timing of the SRAM and SDRAM. Table 297.0x04 - MCFG2 - Memory configuration register 2 31 30 18 17 16 SDRF TRP SDRAM TRFC TCAS SDRAM BANKSZ SDRAM COLSZ SDRAM CMD D64 SDPB R 0 1 0x3 1 0 0x2 0 * 0 0 rw rw rw rw rw rw rw r rw r 15 14 13 2 1 0 R SE SI RAM BANK SIZE 0 0 0 NR NR NR NR 0 0 r rw rw rw rw* rw rw rw rw 31 29 27 26 12 25 9 23 8 7 22 21 6 RBRDY RMW 20 5 4 RAM WIDTH 19 3 RAM WRITE WS RAM READ WS SDRAM refresh (SDRF) - Enables SDRAM refresh. GRIP, Apr 2018, Version 2018.1 268 www.cobham.com/gaisler GRLIB IP Core Table 297.0x04 - MCFG2 - Memory configuration register 2 30 SDRAM TRP parameter (TRP) - tRP will be equal to 2 or 3 system clocks (0/1). 29 : 27 SDRAM TRFC parameter (SDRAM TRFC) - tRFC will be equal to 3+field-value system clocks. 26 SDRAM TCAS parameter (TCAS) - Selects 2 or 3 cycle CAS delay (0/1). When changed, a LOADCOMMAND-REGISTER command must be issued at the same time. Also sets RAS/CAS delay (tRCD). 25 : 23 SDRAM bank size (SDRAM BANKSZ) - Sets the bank size for SDRAM chip selects (“000”=4MiB, “001”=8MiB, “010”=16MiB,...,. “111”=512MiB). When configured for 64-bit wide SDRAM data bus (sdbits=64), the meaning of this field doubles so that “000”=8 MiB, .., “111”=1024 MiB 22 : 21 SDRAM column size (SDRAM COLSZ) - “00”=256, “01”=512, “10”=1024, “11”=2048 except when bit[25:23]=˘111˘ then ˘11˘=4096 20 : 19 SDRAM command (SDRAM CMD) - Writing a non-zero value will generate a SDRAM command. “01”=PRECHARGE, “10”=AUTO-REFRESH, “11”=LOAD-COMMAND-REGISTER. The field is reset after the command has been executed. 18 64-bit SDRAM data bus (D64) - Reads ‘1’ if the memory controller is configured for 64-bit SDRAM data bus width, ‘0’ otherwise. Read-only. 17 SDRAM Page Burst (SDPB) - SDRAM programmed for page bursts on read when set, else programmed for line burst lengths of 8 on read. Programmable when pageburst VHDL generic is 2, else read-only. 16 : 15 RESERVED 14 SDRAM enable (SE) - Enables the SDRAM controller and disables fifth SRAM bank (RAMSN[4]). 13 SRAM disable (SI) - Disables accesses to SRAM bank if bit 14 (SE) is set to ‘1’. 12 : 9 RAM bank size (RAM BANK SIZE) - Sets the size of each RAM bank (“0000”=8KiB, “0001”=16KiB, “0010”=32KiB, “0011”= 64KiB,.., “1111”=256MiB)(i.e. 8KiB * 2**RAM BANK SIZE). 8 RESERVED 7 RAM bus ready enable (RBRDY) - Enables bus ready signaling for the RAM area. Bus read signaling for the RAM area is only available for the fifth chip-select and this field is only available if the memory controller has been implemented with the VHDL generic srbanks set to 5. 6 Read-modify-write enable (RMW) - Enables read-modify-write cycles for sub-word writes to 16- bit 32-bit areas with common write strobe (no byte write strobe). 5:4 RAM width (RAM WIDTH) - Sets the data width of the RAM area (“00”=8, “01”=16, “1X”=32). 3:2 RAM write waitstates (RAM WRITE WS) - Sets the number of wait states for RAM write cycles (“00”=0, “01”=1, “10”=2, “11”=3). The values above describe the default configuration The core can be configred at implementation to extend the number of waitstates. The number of wait states inserted will be (RAM WRITE WS)*2wsshift , where wsshift can be read from the first user-defined register in the core’s plug&play area (default is wsshift = 0). 1:0 RAM read waitstates (RAM READ WS) - Sets the number of wait states for RAM read cycles (“00”=0, “01”=1, “10”=2, “11”=3). The values above describe the default configuration The core can be configred at implementation to extend the number of waitstates. The number of wait states inserted will be (RAM READ WS)*2wsshift , where wsshift can be read from the first user-defined register in the core’s plug&play area (default is wsshift = 0). 27.16.3 Memory configuration register 3 (MCFG3) MCFG3 contains the reload value for the SDRAM refresh counter and to control and monitor the memory EDAC. Table 298.0x08 - MCFG3 - Memory configuration register 3 31 28 27 RESERVED 29 RSE ME SDRAM REFRESH COUNTER 0 0 1 NR GRIP, Apr 2018, Version 2018.1 26 269 www.cobham.com/gaisler GRLIB IP Core Table 298.0x08 - MCFG3 - Memory configuration register 3 r rw r 12 11 10 9 8 rw WB RB RE PE TCB 0 0 NR 0 NR rw rw rw rw rw 7 0 31 : 29 RESERVED 28 Reed-Solomon EDAC enable (RSE) - if set, will enable Reed-Solomon protection of SDRAM area when implemented 27 Memory EDAC (ME) - Indicates if memory EDAC is present. (read-only) 26 : 12 SDRAM refresh counter reload value (SDRAM REFRESH COUNTER) 11 EDAC diagnostic write bypass (WB) - Enables EDAC write bypass. 10 EDAC diagnostic read bypass (RB) - Enables EDAC read bypass. 9 RAM EDAC enable (RE) - Enable EDAC checking of the RAM area (including SDRAM). 8 PROM EDAC enable (PE) - Enable EDAC checking of the PROM area. Ar reset, this bit is initialized with the value of MEMI.EDAC. 7:0 Test checkbits (TCB) - This field replaces the normal checkbits during write cycles when WB is set. It is also loaded with the memory checkbits during read cycles when RB is set. The period between each AUTO-REFRESH command is calculated as follows: tREFRESH = ((reload value) + 1) / SYSCLK 27.16.4 Memory configuration register 4 (MCFG4) MCFG4 is only present if the Reed-Solomon EDAC has been enabled with the edac VHDL generic. MCFG4 provides means to insert Reed-Solomon EDAC errors into memory for diagnostic purposes. Table 299.0x0C - MCFG4 - Memory configuration register 4 31 16 RESERVED WB 15 0 TCB[15:0] 31 : 17 RESERVED 16 EDAC diagnostic write bypass (WB) - Enables EDAC write bypass. Identical to WB in MCFG3. 15 : 0 Test checkbits (TCB) - This field replaces the normal checkbits during write cycles when WB is set. It is also loaded with the memory checkbits during read cycles when RB is set. Note that TCB[7:0] are identical to TCB[7:0] in MCFG3 27.16.5 Memory configuration register 5 (MCFG5) MCFG5 contains fields to control lead out cycles for the ROM and IO areas. Table 300.0x10 - MCFG5 - Memory configuration register 5 31 30 29 RESERVED 23 22 IOHWS 16 RESERVED 0x00 rw 15 14 13 RESERVED 7 ROMHWS 6 0 RESERVED 0x00 GRIP, Apr 2018, Version 2018.1 270 www.cobham.com/gaisler GRLIB IP Core Table 300.0x10 - MCFG5 - Memory configuration register 5 rw 31 : 30 RESERVED 29:23 IO lead out (IOHWS) - Lead out cycles added to IO accesses are IOHWS(3:0)*2IOHWS(6:4) 22 : 14 RESERVED 13:7 ROM lead out (ROMHWS) - Lead out cycles added to ROM accesses are ROMHWS(3:0)*2ROMHWS(6:4) 6:0 RESERVED 27.16.6 Memory configuration register 6 (MCFG6) MCFG6 contains fields to control lead out cycles for the (S)RAM area. Table 301.0x14 - MCFG6 - Memory configuration register 6 31 16 RESERVED 0 r 15 14 13 7 6 0 RESERVED RAMHWS RESERVED r 0x00 r 0 rw 0 31 : 14 RESERVED 13:7 RAM lead out (RAMHWS) - Lead out cycles added to RAM accesses are RAMHWS(3:0)*2RAMHWS(6:4) 6:0 RESERVED 27.16.7 Memory configuration register 7 (MCFG7) MCFG7 contains fields to control bus ready timeout. Table 302.0x18 - MCFG7 - Memory configuration register 7 31 16 BRDYNCNT 0 rw 15 0 BRDYNRLD 0 rw 31 : 16 Bus ready count (BRDYNCOUNT) - Counter value. If this register is written then the counter shall be written with the same value as BRDYNRLD. 15: 0 Bus ready reload value (BRDYNRLD) - Reload value for BRDYNCNT 27.17 Vendor and device identifiers The core has vendor identifier 0x01 (GAISLER) and device identifier 0x054. For description of vendor and device identifiers, see GRLIB IP Library User’s Manual. GRIP, Apr 2018, Version 2018.1 271 www.cobham.com/gaisler GRLIB IP Core 27.18 Implementation 27.18.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. See the documentation for the syncrst VHDL generic for information on asynchronous reset affecting external signals. 27.19 Configuration options Table 303 shows the configuration options of the core (VHDL generics). Table 303.Configuration options Generic Function Allowed range Default hindex AHB slave index 1 - NAHBSLV-1 0 pindex APB slave index 0 - NAPBSLV-1 0 romaddr ADDR field of the AHB BAR0 defining PROM address space. Default PROM area is 0x0 - 0x1FFFFFFF. Also see documentation of romasel VHDL generic below. 0 - 16#FFF# 16#000# rommask MASK field of the AHB BAR0 defining PROM address space.. Also see documentation of romasel VHDL generic below. 0 - 16#FFF# 16#E00# ioaddr ADDR field of the AHB BAR1 defining I/O address space. Default I/O area is 0x20000000 - 0x2FFFFFFF. 0 - 16#FFF# 16#200# iomask MASK field of the AHB BAR1 defining I/O address space. 0 - 16#FFF# 16#E00# ramaddr ADDR field of the AHB BAR2 defining RAM address space. Default RAM area is 0x40000000-0x7FFFFFFF. 0 - 16#FFF# 16#400# rammask MASK field of the AHB BAR2 defining RAM address space. 0 -16#FFF# 16#C00# paddr ADDR field of the APB BAR configuration registers address space. 0 - 16#FFF# 0 pmask MASK field of the APB BAR configuration registers address space. 0 - 16#FFF# 16#FFF# wprot RAM write protection. 0-1 0 invclk unused N/A 0 fast Enable fast SDRAM address decoding. 0-1 0 GRIP, Apr 2018, Version 2018.1 272 www.cobham.com/gaisler GRLIB IP Core Table 303.Configuration options Generic Function Allowed range Default romasel Sets the PROM bank size.  romasel 0: selects a programmable mode where the ROMBANKSZ field in the MCFG1 register sets the bank size. When romasel is 0 and the bank size is configured (MCFG1 register, ROMBANKSZ field, via the core’s register interface) to 0b000 or 0b1111 then address bit 28 is used to decode the banks. This means that the core must be mapped at a 512 MiB address boundary (0x0, 0x20000000, 0x40000000, .. see romaddr and rommask VHDL generics) for address decoding to work correctly. 0 - 28 28 romasel 1 - 14: Values 1 - 14 sets the size in binary steps (1 = 16KiB, 2 = 32KiB, 3=64KiB, ...., 14=128MiB). Four chipselects are available for these values. 15 sets the bank size to 256MiB with two chip-selects. romasel 16 - 28: Values 16 - 28 sets the bank size in binary steps (16 = 64 KiB, 17 = 128KiB, ... 28 = 256MiB). Two chip-selects are available for this range. The selected bank size is readable from the rombanksz field in the MCFG1 register for the non-programmable modes. The PROM area will wrap back to the first bank after the end of the last decoded bank. As an example, if romasel is set to 14 the following banks will be decoded: bank 0: 0x00000000 - 0x07FFFFFF bank 1: 0x08000000 - 0x0FFFFFFF bank 2: 0x10000000 - 0x17FFFFFF bank 3: 0x18000000 - 0x1FFFFFFF ...bank 0 starting again at 0x20000000 (the same pattern applies for other values less than 14, addresses will wrap after the last decoded bank). If romasel is 15 then the address decoding will result in the following: bank 0: 0x00000000 - 0x0FFFFFFF bank 1: 0x10000000 - 0x1FFFFFFF .. bank 0 starting again at offset 0x20000000 When instantiating the core care must be taken to see how many chip-selects that will be used as a result of the setting of romasel. This affects the base address at which the core can be placed (setting of romaddr and rommask VHDL generics). As an example, placing the PROM area at a 256 MiB address boundary, like the base address 0x10000000 and using romasel = 0, 14, 15 or 28 will NOT result in ROM chip-select 0 getting asserted for an access to the PROM base address as the address decoding requires that the core has been placed on a 512 MiB address boundary. sdrasel log2(RAM address space size) - 1. E.g if size of the RAM address space is 0x40000000 sdrasel is log2(2^30)-1= 29. 0 - 31 29 srbanks Number of SRAM banks. 0-5 4 ram8 Enable 8-bit PROM, SRAM and I/O access. 0-1 0 ram16 Enable 16-bit PROM, SRAM and I/O access. 0-1 0 sden Enable SDRAM controller. 0-1 0 sepbus SDRAM is located on separate bus. 0-1 1 sdbits 32 or 64 -bit SDRAM data bus. 32, 64 32 oepol Select polarity of drive signals for data pads. 0 = active low, 1 = active high. 0-1 0 GRIP, Apr 2018, Version 2018.1 273 www.cobham.com/gaisler GRLIB IP Core Table 303.Configuration options Generic Function Allowed range Default edac Enable EDAC. 0 = No EDAC; 1 = BCH EDAC; 2 = BCH EDAC with pipelining; 3 = BCH + RS EDAC 0-3 0 sdlsb Select least significant bit of the address bus that is connected to SDRAM. - 2 syncrst Choose between synchronous and asynchronous reset for chipselect, oen and drive signals. 0-1 0 pageburst Line burst read of length 8 when 0, page burst read when 1, programmable read burst type when 2. 0-2 0 scantest Enable scan test support 0-1 0 netlist Use technology specific netlist instead of RTL code 0-1 0 tech Technology to use for netlists 0 - NTECH 0 rahold Unused 0 - 16 0 wsshift Wait state counter shift. This value defines the number of steps to shift the wait state counter. The number of waitstates that the core can generate is limited by 2wsshift. See the wait state fields in the core’s APB register descriptions to see the effect of this generic. The value of this generic can be read out in the first user-defined register of the core’s plug&play area. This means that if wsshift is non-zero then the AHB controller must have full plug&play decoding enabled. - 0 brdynto Bus ready timeout conunter enable. If this generic is non-zero then the core will be implemented with a bus ready timeout counter (see MCFG7). 0-1 0 27.20 Scan support Scan support is enabled by setting the SCANTEST generic to 1. When enabled, the asynchronous reset of any flip-flop will be connected to AHBI.testrst during when AHBI.testen = ‘1’. 27.21 Signal descriptions Table 304 shows the interface signals of the core (VHDL ports). Table 304.Signal descriptions Signal name Field Type Function Active CLK N/A Input Clock - RST N/A Input Reset Low MEMI DATA[31:0] Input Memory data High BRDYN Input Bus ready strobe Low BEXCN Input Bus exception Low CB[15:0] Input EDAC checkbits High WRN[3:0] Input SRAM write enable feedback signal Low BWIDTH[1:0] Input Sets the reset value of the PROM data bus width field in the MCFG1 register High EDAC Input The reset value for the PROM EDAC enable bit High SD[31:0] Input SDRAM separate data bus High SCB[15:0] Input SDRAM separate checkbit bus High GRIP, Apr 2018, Version 2018.1 274 www.cobham.com/gaisler GRLIB IP Core Table 304.Signal descriptions Signal name Field Type Function Active MEMO ADDRESS[31:0] Output Memory address High CB[15:0] Output EDAC Checkbit DATA[31:0] Output Memory data - SDDATA[63:0] Output Sdram memory data - RAMSN[4:0] Output SRAM chip-select Low RAMOEN[4:0] Output SRAM output enable Low IOSN Output Local I/O select Low ROMSN[3:0] Output PROM chip-select Low OEN Output Output enable Low WRITEN Output Write strobe Low WRN[3:0] Output SRAM write enable: Low WRN[0] corresponds to DATA[31:24], WRN[1] corresponds to DATA[23:16], WRN[2] corresponds to DATA[15:8], WRN[3] corresponds to DATA[7:0]. Any WRN[ ] signal can be used for CB[ ]. MBEN[3:0] Output Read/write byte enable: Low MBEN[0] corresponds to DATA[31:24], MBEN[1] corresponds to DATA[23:16], MBEN[2] corresponds to DATA[15:8], MBEN[3] corresponds to DATA[7:0]. Any MBEN[ ] signal can be used for CB[ ]. BDRIVE[3:0] Output Drive byte lanes on external memory bus. Controls I/O-pads connected to external memory bus: Low/High BDRIVE[0] corresponds to DATA[31:24], BDRIVE[1] corresponds to DATA[23:16], BDRIVE[2] corresponds to DATA[15:8], BDRIVE[3] corresponds to DATA[7:0]. Any BDRIVE[ ] signal can be used for CB[ ]. VBDRIVE[31:0] Output Vectored I/O-pad drive signals. Low/High SVBDRIVE[63:0] Output Vectored I/O-pad drive signals for separate sdram bus. Low/High READ Output Read strobe High SA[14:0] Output SDRAM separate address bus High CE Output Single error detected High AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - APBI * Input APB slave input signals - APBO * Output APB slave output signals - WPROT WPROTHIT Input Unused - GRIP, Apr 2018, Version 2018.1 275 www.cobham.com/gaisler GRLIB IP Core Table 304.Signal descriptions Signal name SDO Field Type Function Active SDCASN Output SDRAM column address strobe Low SDCKE[1:0] Output SDRAM clock enable High SDCSN[1:0] Output SDRAM chip select Low SDDQM[7:0] Output SDRAM data mask: Low SDDQM[7] corresponds to SD[63:56], SDDQM[6] corresponds to SD[55:48], SDDQM[5] corresponds to SD[47:40], SDDQM[4] corresponds to SD[39:32], SDDQM[3] corresponds to SD[31:24], SDDQM[2] corresponds to SD[23:16], SDDQM[1] corresponds to SD[15:8], SDDQM[0] corresponds to SD[7:0]. Any SDDQM[ ] signal can be used for CB[ ]. SDRASN Output SDRAM row address strobe Low SDWEN Output SDRAM write enable Low * see GRLIB IP Library User’s Manual GRIP, Apr 2018, Version 2018.1 276 www.cobham.com/gaisler GRLIB IP Core 27.22 Signal definitions and reset values The signals and their reset values are described in table 305. Table 305.Signal definitions and reset values Signal name Type Function Active Reset value address[27:0] Output Memory address High Undefined data[31:0] Input/Output Memory data High Tri-state cb[15:0] Input/Output Check bits High Tri-state ramsn[4:0] Output SRAM chip select Low Logical 1 ramoen[4:0] Output SRAM output enable Low Logical 1 rwen[3:0] Output, SRAM write byte enable: Low Logical 1 Low Logical 1 Output enable Low Logical 1 rwen[0] corresponds to data[31:24], rwen[1] corresponds to data[23:16], rwen[2] corresponds to data[15:8], rwen[3] corresponds to data[7:0]. Any rwen[ ] signal can be used for cb[ ]. ramben[3:0] Output SRAM read/write byte enable: ramben[0] corresponds to data[31:24], ramben[1] corresponds to data[23:16], ramben[2] corresponds to data[15:8], ramben[3] corresponds to data[7:0]. Any ramben[ ] signal can be used for cb[ ]. oen Output writen Output Write strobe Low Logical 1 read Output Read strobe High Logical 1 iosn Output IO area chip select Low Logical 1 romsn[3:0] Output PROM chip select Low Logical 1 brdyn Input Bus ready. Extends accesses to the IO area. Low - bexcn Input Bus exception. Low - sa[15:0] Output SDRAM address High Undefined sd[31:0] Input/Output SDRAM data High Tri-state scb[15:0] Input/Output SDRAM check bits High Tri-state sdcsn[1:0] Output SDRAM chip select Low Logical 1 sdwen Output SDRAM write enable Low Logical 1 sdrasn Output SDRAM row address strobe Low Logical 1 sdcasn Output SDRAM column address strobe Low Logical 1 sddqm[3:0] Output SDRAM data mask: Low Logical 1 sddqm[5] corresponds to scb[15:8], sddqm[4] corresponds to scb[7:0], sddqm[3] corresponds to sd[31:24], sddqm[2] corresponds to sd[23:16], sddqm[1] corresponds to sd[15:8], sddqm[0] corresponds to sd[7:0]. Any sddqm[ ] signal can be used for scb[ ]. GRIP, Apr 2018, Version 2018.1 277 www.cobham.com/gaisler GRLIB IP Core 27.23 Timing The timing waveforms and timing parameters are shown in figure 82 and are defined in table 306. clk tFTMCTRL0 address[] tFTMCTRL1 ramsn[], romsn[] tFTMCTRL1 tFTMCTRL2 tFTMCTRL2 rwen[], writen tFTMCTRL2 tFTMCTRL2 read tFTMCTRL3, tFTMCTRL4 data[], cb[] (output) tFTMCTRL5 clk address[] ramsn[], romsn[] tFTMCTRL6 tFTMCTRL6 ramoen[], ramben[], oen read tFTMCTRL7 tFTMCTRL8 data[], cb[] (input) tFTMCTRL10 tFTMCTRL9 brdyn, bexcn Figure 82. Timing waveforms - SRAM, PROM accesses GRIP, Apr 2018, Version 2018.1 278 www.cobham.com/gaisler GRLIB IP Core clk tFTMCTRL0 address[] tFTMCTRL1 iosn[] tFTMCTRL1 tFTMCTRL2 tFTMCTRL2 rwen[], writen tFTMCTRL2 tFTMCTRL2 read tFTMCTRL3, tFTMCTRL4 data[] (output) tFTMCTRL5 clk address[] iosn[] tFTMCTRL6 tFTMCTRL6 oen read tFTMCTRL8 tFTMCTRL7 data[] (input) tFTMCTRL10 tFTMCTRL9 brdyn, bexcn Figure 83. Timing waveforms - I/O accesses Table 306.Timing parameters - SRAM, PROM and I/O accesses Name Parameter Reference edge Min Max Unit tFTMCTRL0 address clock to output delay rising clk edge TBD TBD ns tFTMCTRL1 clock to output delay rising clk edge TBD TBD ns tFTMCTRL2 clock to output delay rising clk edge TBD TBD ns tFTMCTRL3 clock to data output delay rising clk edge TBD TBD ns tFTMCTRL4 clock to data non-tri-state delay rising clk edge TBD TBD ns tFTMCTRL5 clock to data tri-state delay rising clk edge TBD TBD ns tFTMCTRL6 clock to output delay rising clk edge TBD TBD ns tFTMCTRL7 data input to clock setup rising clk edge TBD - ns tFTMCTRL8 data input from clock hold rising clk edge TBD - ns tFTMCTRL9 input to clock setup rising clk edge TBD - ns tFTMCTRL10 input from clock hold rising clk edge TBD - ns The timing waveforms and timing parameters are shown in figure 82 and are defined in table 306. GRIP, Apr 2018, Version 2018.1 279 www.cobham.com/gaisler GRLIB IP Core clk tFTMCTRL11 sdcasn, sdrasn sdwen, sdcsn[] sddqm[] write read nop nop term nop nop nop tFTMCTRL11 address[], sa[] tFTMCTRL12 data[], cb[], sd[], scb[] nop tFTMCTRL14 tFTMCTRL13 tFTMCTRL15 Figure 84. Timing waveforms - SDRAM accesses Table 307.Timing parameters - SDRAM accesses Name Parameter Reference edge Min Max Unit tFTMCTRL11 clock to output delay rising clk edge TBD TBD ns tFTMCTRL12 clock to data output delay rising clk edge TBD TBD ns tFTMCTRL13 data clock to data tri-state delay rising clk edge TBD TBD ns tFTMCTRL14 data input to clock setup rising clk edge TBD - ns tFTMCTRL15 data input from clock hold rising clk edge TBD - ns 27.24 Library dependencies Table 308 shows libraries used when instantiating the core (VHDL libraries). Table 308.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals Memory bus signals definitions Components FTMCTRL component 27.25 Instantiation This example shows how the core can be instantiated. The example design contains an AMBA bus with a number of AHB components connected to it including the memory controller. The external memory bus is defined on the example designs port map and connected to the memory controller. System clock and reset are generated by GR Clock Generator and Reset Generator. Memory controller decodes default memory areas: PROM area is 0x0 - 0x1FFFFFFF, I/O-area is 0x20000000-0x3FFFFFFF and RAM area is 0x40000000 - 0x7FFFFFFF. SDRAM controller is enabled. SDRAM clock is synchronized with system clock by clock generator. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.tech.all; library gaisler; use gaisler.memctrl.all; use gaisler.pads.all; -- used for I/O pads entity mctrl_ex is GRIP, Apr 2018, Version 2018.1 280 www.cobham.com/gaisler GRLIB IP Core port ( clk : in std_ulogic; resetn : in std_ulogic; pllref : in std_ulogic; -- memory bus address : out std_logic_vector(27 downto 0); -- memory bus data : inout std_logic_vector(31 downto 0); ramsn : out std_logic_vector(4 downto 0); ramoen : out std_logic_vector(4 downto 0); rwen : inout std_logic_vector(3 downto 0); romsn : out std_logic_vector(3 downto 0); iosn : out std_logic; oen : out std_logic; read : out std_logic; writen : inout std_logic; brdyn : in std_logic; bexcn : in std_logic; -- sdram i/f sdcke : out std_logic_vector ( 1 downto 0); -- clk en sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel sdwen : out std_logic; -- write en sdrasn : out std_logic; -- row addr stb sdcasn : out std_logic; -- col addr stb sddqm : out std_logic_vector (7 downto 0); -- data i/o mask sdclk : out std_logic; -- sdram clk output sa : out std_logic_vector(14 downto 0); -- optional sdram address sd : inout std_logic_vector(63 downto 0) -- optional sdram data ); end; architecture rtl of mctrl_ex is -- AMBA bus (AHB and APB) signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); -- signals used to connect memory controller and memory bus signal memi : memory_in_type; signal memo : memory_out_type; signal sdo : sdram_out_type; signal wprot : wprot_out_type; -- dummy signal, not used signal clkm, rstn : std_ulogic; -- system clock and reset -- signals used by clock and reset generators signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal gnd : std_ulogic; begin -- Clock and reset generators clkgen0 : clkgen generic map (clk_mul => 2, clk_div => 2, sdramen => 1, tech => virtex2, sdinvclk => 0) port map (clk, gnd, clkm, open, open, sdclk, open, cgi, cgo); cgi.pllctrl <= "00"; cgi.pllrst <= resetn; cgi.pllref <= pllref; -- Memory controller ftmctrl0 : ftmctrl generic map (srbanks => 1, sden => 1, edac => 1) port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wprot, sdo); -- memory controller inputs not used in this configuration memi.brdyn <= ’1’; memi.bexcn <= ’1’; memi.wrn <= "1111"; GRIP, Apr 2018, Version 2018.1 281 www.cobham.com/gaisler GRLIB IP Core memi.sd <= sd; -- prom width at reset memi.bwidth <= "10"; -- I/O pads driving data memory bus data signals datapads : for i in 0 to 3 generate data_pad : iopadv generic map (width => 8) port map (pad => memi.data(31-i*8 downto 24-i*8), o => memi.data(31-i*8 downto 24-i*8), en => memo.bdrive(i), i => memo.data(31-i*8 downto 24-i*8)); end generate; -- connect memory controller outputs to entity output signals address <= memo.address; ramsn <= memo.ramsn; romsn <= memo.romsn; oen <= memo.oen; rwen <= memo.wrn; ramoen <= "1111" & memo.ramoen(0); sa <= memo.sa; writen <= memo.writen; read <= memo.read; iosn <= memo.iosn; sdcke <= sdo.sdcke; sdwen <= sdo.sdwen; sdcsn <= sdo.sdcsn; sdrasn <= sdo.rasn; sdcasn <= sdo.casn; sddqm <= sdo.dqm; end; GRIP, Apr 2018, Version 2018.1 282 www.cobham.com/gaisler GRLIB IP Core 28 FTSDCTRL - 32/64-bit PC133 SDRAM Controller with EDAC 28.1 Overview The fault tolerant SDRAM memory interface handles PC133 SDRAM compatible memory devices attached to a 32- or 64-bit wide data bus. The interface acts as a slave on the AHB bus where it occupies configurable amount of address space for SDRAM access. An optional Error Detection And Correction Unit (EDAC) logic (only for the 32 - bit bus) corrects one bit error and detects two bit errors. The SDRAM controller function is programmed by means of register(s) mapped into AHB I/O address space. Chip-select decoding is done for two SDRAM banks. AHB A D CB FT SDRAM CONTROLLER SDO.SDCLK SDO.SDCSN[1:0] SDO.SDRASN SDO.SDCASN SDO.SDWEN SDO.SDDQM[7:0] SDO.SDCLK A[16:15] CLK BA CSN RAS CAS WE DQM CKE SDRAM A A[14:2] D CB SDO.ADDRESS[16:2] SDI.D[63:0]/ SDO.D[31:0] CB[6:0] Figure 85. FT SDRAM memory controller connected to AMBA bus and SDRAM 28.2 Operation 28.2.1 General Synchronous Dynamic RAM (SDRAM) access is supported to two banks of PC100/PC133 compatible devices. The controller supports 64, 256 and 512 Mbyte devices with 8 - 12 column-address bits, up to 13 row-address bits, and 4 banks. The size of each of the two banks can be programmed in binary steps between 4 Mbyte and 512 Mbyte. The operation of the SDRAM controller is controlled through the configuration register SDCFG. A second register, ECFG, is available for configuring the EDAC functions. SDRAM banks data bus width is configurable between 32 and 64 bits. 28.2.2 Initialization When the SDRAM controller is enabled, it automatically performs the SDRAM initialization sequence of PRECHARGE, 8x AUTO-REFRESH and LOAD-MODE-REG on both banks simultaneously. When mobile SDRAM functionality is enabled, the initialization sequence is appended with a LOAD-EXTMODE-REG command. The controller programs the SDRAM to use page burst on read accesses and single location access on write accesses. If the pwron VHDL generic is 1, the initialization sequence is also sent automatically when reset is released. Note that some SDRAM devices require a stable clock of 100 us before any commands might be sent. When using on-chip PLL, this might not always be the case and the pwron VHDL generic should be set to 0 in such cases. GRIP, Apr 2018, Version 2018.1 283 www.cobham.com/gaisler GRLIB IP Core 28.2.3 Configurable SDRAM timing parameters To provide optimum access cycles for different SDRAM devices (and at different frequencies), three SDRAM parameters can be programmed through memory configuration register 2 (MCFG2): TCAS, TRP and TRFCD. The value of these fields affect the SDRAM timing as described in table 309. Table 309.SDRAM programmable minimum timing parameters SDRAM timing parameter Minimum timing (clocks) CAS latency, RAS/CAS delay (tCAS, tRCD) TCAS + 2 Precharge to activate (tRP) TRP + 2 Auto-refresh command period (tRFC) TRFC + 3 Activate to precharge (tRAS) TRFC + 1 Activate to Activate (tRC) TRP + TRFC + 4 If the TCAS, TRP and TRFC are programmed such that the PC100/133 specifications are fulfilled, the remaining SDRAM timing parameters will also be met. The table below shows typical settings for 100 and 133 MHz operation and the resulting SDRAM timing (in ns): Table 310.SDRAM example programming SDRAM settings tCAS tRC tRP tRFC tRAS 100 MHz, CL=2; TRP=0, TCAS=0, TRFC=4 20 80 20 70 50 100 MHz, CL=3; TRP=0, TCAS=1, TRFC=4 30 80 20 70 50 133 MHz, CL=2; TRP=1, TCAS=0, TRFC=6 15 82 22 67 52 133 MHz, CL=3; TRP=1, TCAS=1, TRFC=6 22 82 22 67 52 When mobile SDRAM support is enabled, one additional timing parameter (TXSR) can be programmed though the Power-Saving configuration register. Table 311.Mobile SDRAM programmable minimum timing parameters SDRAM timing parameter Minimum timing (clocks) Exit Self Refresh mode to first valid command (tXSR) tXSR 28.2.4 Refresh The SDRAM controller contains a refresh function that periodically issues an AUTO-REFRESH command to both SDRAM banks. The period between the commands (in clock periods) is programmed in the refresh counter reload field in the SDCFG register. Depending on SDRAM type, the required period is typically 7.8 or 15.6 s (corresponding to 780 or 1560 clocks at 100 MHz). The generated refresh period is calculated as (reload value+1)/sysclk. The refresh function is enabled by setting bit 31 in SDCFG register. 28.2.5 Self Refresh The self refresh mode can be used to retain data in the SDRAM even when the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking and refresh are handled internally. The memory array that is refreshed during the self refresh operation is defined in the extended mode register. These settings can be changed by setting the PASR bits in the Power-Saving configuration register. The extended mode register is automatically updated when the PASR bits are changed. The supported “Partial Array Self Refresh” modes are: Full, Half, Quarter, Eighth, and Sixteenth array. “Partial Array Self Refresh” is only supported when mobile SDRAM functionality is enabled. To enable the self refresh mode, set the PMODE bits in the PowerSaving configuration register to “010” (Self Refresh). The controller will enter self refresh mode after GRIP, Apr 2018, Version 2018.1 284 www.cobham.com/gaisler GRLIB IP Core every memory access (when the controller has been idle for 16 clock cycles), until the PMODE bits are cleared. When exiting this mode the controller introduce a delay defined by tXSR in the PowerSaving configuration register and a AUTO REFRESH command before any other memory access is allowed. The minimum duration of this mode is defined by tRAS. This mode is only available when the VHDL generic mobile is >= 1. 28.2.6 Power-Down When entering the power-down mode all input and output buffers, excluding SDCKE, are deactivated. All data in the SDRAM is retained during this operation. To enable the power-down mode, set the PMODE bits in the Power-Saving configuration register to “001” (Power-Down). The controller will enter power-down mode after every memory access (when the controller has been idle for 16 clock cycles), until the PMODE bits is cleared. The REFRESH command will still be issued by the controller in this mode. When exiting this mode a delay of one clock cycles are added before issue any command to the memory. This mode is only available when the VHDL generic mobile is >= 1. 28.2.7 Deep Power-Down The deep power-down operating mode is used to achieve maximum power reduction by eliminating the power of the memory array. Data will not be retained after the device enters deep power-down mode. To enable the deep power-down mode, set the PMODE bits in the Power-Saving configuration register to “101” (Deep Power-Down). To exit the deep power-down mode the PMODE bits in the Power-Saving configuration register must be cleared. The controller will respond with an AMBA ERROR response to an AMBA access, that will result in a memory access, during Deep Power-Down mode. This mode is only available when the VHDL generic mobile is >= 1 and mobile SDRAM functionality is enabled. 28.2.8 Temperature-Compensated Self Refresh The settings for the temperature-compensation of the Self Refresh rate can be controlled by setting the TCSR bits in the Power-Saving configuration register. The extended mode register is automatically updated when the TCSR bits are changed. Note that some vendors implements a Internal Temperature-Compensated Self Refresh feature, which makes the memory ignore the TCSR bits. This functionality is only available when the VHDL generic mobile is >= 1 and mobile SDRAM functionality is enabled. 28.2.9 Drive Strength The drive strength of the output buffers can be controlled by setting the DS bits in the Power-Saving configuration register. The extended mode register is automatically updated when the DS bits are changed. The available options are: full, three-quarter, one-half, and one-quarter drive strengths. This functionality is only available when the VHDL generic mobile is >= 1 and mobile SDRAM functionality is enabled. 28.2.10 SDRAM commands The controller can issue three SDRAM commands by writing to the SDRAM command field in SDCFG: PRE-CHARGE, AUTO-REFRESH and LOAD-MODE-REG (LMR). If the LMR command is issued, the CAS delay as programmed in SDCFG will be used. Line burst of length 8 will be set for read when pageburst VHDL generic is 0. Page burst will be set for read when pageburst VHDL generic is 1. Page burst or line burst of length 8, selectable via the SDCFG register will be set, when pageburst VHDL generic is 2. Remaining fields are fixed: page read burst, single location write, sequential burst. The command field will be cleared after a command has been executed. Note that when changing the value of the CAS delay, a LOAD-MODE-REGISTER command should be generated at the same time. GRIP, Apr 2018, Version 2018.1 285 www.cobham.com/gaisler GRLIB IP Core 28.2.11 Read cycles A read cycle is started by performing an ACTIVATE command to the desired bank and row, followed by a READ command after the programmed CAS delay. A read burst is performed if a burst access has been requested on the AHB bus. The read cycle is terminated with a PRE-CHARGE command, no banks are left open between two accesses. Note that only word bursts are supported by the SDRAM controller. The AHB bus supports bursts of different sizes such as bytes and halfwords but they cannot be used. 28.2.12 Write cycles Write cycles are performed similarly to read cycles, with the difference that WRITE commands are issued after activation. A write burst on the AHB bus will generate a burst of write commands without idle cycles in-between. As in the read case, only word bursts are supported. 28.2.13 Address bus connection The SDRAM address bus should be connected to SA[12:0], the bank address to SA[14:13], and the data bus to SD[31:0] or SD[63:0] if 64-bit data bus is used. 28.2.14 Data bus Data bus width is configurable to 32 or 64 bits. 64-bit data bus allows the 64-bit SDRAM devices to be connected using the full data capacity of the devices. 64-bit SDRAM devices can be connected to 32-bit data bus if 64-bit data bus is not available but in this case only half the full data capacity will be used. 28.2.15 EDAC The controller optionally contains Error Detection And Correction (EDAC) logic, using a BCH(32, 7) code. It is capable of correcting one bit error and detecting two bit errors. The EDAC logic does not add any additional waitstates during normal operation. Detected errors will cause additional waitstates for correction (single errors) or error reporting (multiple errors). Single errors are automatically corrected and generally not visible externally unless explicitly checked. This checking is done by monitoring the ce signal and single error counter. This counter holds the number of detected single errors. The ce signal is asserted one clock cycle when a single error is detected and should be connected to the AHB status register. This module stores the AHB status of the instruction causing the single error and generates interrupts (see the AHB status register documentation for more information). The EDAC functionality can be enabled/disabled during run-time from the ECFG register (and the logic can also be completely removed during synthesis with VHDL generics. The ECFG register also contains control bits and checkbit fields for diagnostic reads. These diagnostic functions are used for testing the EDAC functions on-chip and allows one to store arbitrary checkbits with each written word. Checkbits read from memory can also be controlled. 64-bit bus support is not provided when EDAC is enabled. Thus, the and edacen VHDL generic should never be set to one when the sdbits VHDL generic is set to 64. The equations below show how the EDAC checkbits are generated: CB0 CB1 CB2 CB3 CB4 CB5 CB6 = = = = = = = D0 D0 D0 D0 D2 D8 D0 ^ ^ ^ ^ ^ ^ ^ D4 D1 D3 D1 D3 D9 D1 ^ ^ ^ ^ ^ ^ ^ D6 ^ D7 ^ D2 ^ D4 ^ D4 ^ D7 ^ D5 ^ D6 ^ D4 ^ D5 ^ D10 ^ D11 D2 ^ D3 ^ GRIP, Apr 2018, Version 2018.1 D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31 D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28 D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31 D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29 D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 286 www.cobham.com/gaisler GRLIB IP Core 28.2.16 Clocking The SDRAM controller is designed for an external SDRAM clock that is in phase or slightly earlier than the internal AHB clock. This provides the maximum margin for setup and hold on the external signals, and allows highest possible frequency. For Xilinx and Altera devices, the GRLIB Clock Generator (CLKGEN) can be configured to produce a properly synchronized SDRAM clock. For other FPGA targets, the custom clock synchronization must be designed, or the inverted clock option can be used (see below). For ASIC targets, the SDRAM clock can be derived from the AHB clock with proper delay adjustments during place&route. If the VHDL generic INVCLK is set, then all outputs from the SDRAM controller are delayed for 1/2 clock. This is done by clocking all output registers on the falling clock edge. This option can be used on FPGA targets where proper SDRAM clock synchronization cannot be achieved. The SDRAM clock can be the internal AHB clock without further phase adjustments. Since the SDRAM signals will only have 1/2 clock period to propagate, this option typically limits the maximum SDRAM frequency to 40 - 50 MHz. 28.2.17 Endianness The core is designed for big-endian systems. 28.3 Registers The memory controller is programmed through register(s) mapped into the AHB I/O space defined by the controllers AHB BAR1. If EDAC is enabled through the use of the edacen VHDL generic, an EDAC configuration register will be available. Table 312.FT SDRAM controller registers AHB address offset Register 0x0 SDRAM Configuration register 0x4 EDAC Configuration register 28.3.1 SDRAM configuration register (SDCFG) SDRAM configuration register is used to control the timing of the SDRAM. Table 313. 0x00 - SDCFG - SDRAM configuration register 31 30 29 Refresh tRP 27 tRFC 26 tCD 25 23 SDRAM bank size 22 21 20 19 18 17 16 15 SDRAM SDRAM R col. size command PageBurst R D64 14 SDRAM refresh load value 0 0 1 0b111 1 0 0b10 0 * * * * NR rw rw rw rw rw rw rw r rw* r r rw 31 SDRAM refresh. If set, the SDRAM refresh will be enabled. 30 SDRAM tRP timing. tRP will be equal to 2 or 3 system clocks (0/1). 29: 27 SDRAM tRFC timing. tRFC will be equal to 3 + field-value system clocks. 26 SDRAM CAS delay. Selects 2 or 3 cycle CAS delay (0/1). When changed, a LOAD-COMMANDREGISTER command must be issued at the same time. Also sets RAS/CAS delay (tRCD). 25: 23 SDRAM banks size. Defines the decoded memory size for each SDRAM chip select: “000”= 4 Mbyte, “001”= 8 Mbyte, “010”= 16 Mbyte .... “111”= 512 Mbyte. When configured for 64-bit wide SDRAM data bus (sdbits=64), the meaning of this field doubles so that “000”=8 Mbyte, .., “111”=1024 Mbyte 22: 21 SDRAM column size. “00”=256, “01”=512, “10”=1024, “11”=2048 except when bit[25:23]=˘111˘ then ˘11˘=4096 GRIP, Apr 2018, Version 2018.1 287 www.cobham.com/gaisler GRLIB IP Core Table 313. 0x00 - SDCFG - SDRAM configuration register 20: 19 SDRAM command. Writing a non-zero value will generate an SDRAM command: “01”=PRECHARGE, “10”=AUTO-REFRESH, “11”=LOAD-COMMAND-REGISTER. The field is reset after command has been executed. 17 1 = pageburst is used for read operations, 0 = line burst of length 8 is used for read operations. (Only available when VHDL generic pageburst i set to 2) 15 64-bit data bus (D64) - Reads ‘1’ if memory controller is configured for 64-bit data bus, otherwise ‘0’. Read-only. 14: 0 The period between each AUTO-REFRESH command - Calculated as follows: tREFRESH = ((reload value) + 1) / SYSCLK 28.3.2 EDAC Configuration register (ECFG) The EDAC configuration register controls the EDAC functions of the SDRAM controller during run time. Table 314.0x04 - ECFG - EDAC configuration register 31 30 cntbits + 10 cnbits + 9 10 9 8 7 6 0 EA V RESERVED SEC WB RB EN TCB * 0 NR NR NR 0 NR r r wc rw rw rw rw 6: 0 TCB : Test checkbits. These bits are written as checkbits into memory during a write operation when the WB bit in the ECFG register is set. Checkbits read from memory during a read operation are written to this field when the RB bit is set. 7: EN : EDAC enable. Run time enable/disable of the EDAC functions. If EDAC is disabled no error detection will be done during reads and subword writes. Checkbits will still be written to memory during write operations. 8: RB : Read bypass. Store the checkbits read from memory during a read operation into the TCB field. 9: WB : Write bypass. Write the TCB field as checkbits into memory for all write operations. cntbits + 9: 10 SEC : Single error counter. This field is available when the errcnt VHDL generic is set to one during synthesis. It increments each time a single error is detected. It saturates when the maximum value is reached. The maximum value is the largest number representable in the number of bits used, which in turn is determined by the cntbits VHDL generic. Each bit in the counter can be reset by writing a one to it. 30:cntbits + 10 Reserved. 31: 28.4 EAV : EDAC available. This bit is always one if the SDRAM controller contains EDAC. Vendor and device identifiers The module has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x055. For a description of vendor and device identifiers see GRLIB IP Library User’s Manual. 28.5 Implementation 28.5.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). By default, the core makes use of synchronous reset and resets a subset of its internal registers. The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core will use asynchronous reset for all registers, except synchronization registers, if the GRLIB config package setting grlib_async_reset_enable is set. GRIP, Apr 2018, Version 2018.1 288 www.cobham.com/gaisler GRLIB IP Core The registers driving SDRAM chip select and output enables for the SDRAM data bus have asynchronous reset. 28.6 Configuration options Table 315 shows the configuration options of the core (VHDL generics). Table 315.Configuration options Generic Function Allowed range Default hindex AHB slave index 1 - NAHBSLV-1 0 haddr ADDR field of the AHB BAR0 defining SDRAM area. Default is 0xF0000000 - 0xFFFFFFFF. 0 - 16#FFF# 16#000# hmask MASK field of the AHB BAR0 defining SDRAM area. 0 - 16#FFF# 16#F00# ioaddr ADDR field of the AHB BAR1 defining I/O address space where SDCFG register is mapped. 0 - 16#FFF# 16#000# iomask MASK field of the AHB BAR1 defining I/O address space. 0 - 16#FFF# 16#FFF# wprot Write protection. 0-1 0 invclk Inverted clock is used for the SDRAM. 0-1 0 fast Enable fast SDRAM address decoding. 0-1 0 pwron Enable SDRAM at power-on. 0-1 0 sdbits 32 or 64 -bit data bus width. 32, 64 32 edacen EDAC enable. If set to one, EDAC logic will be included 0 - 1 in the synthesized design. An EDAC configuration register will also be available. 0 errcnt Include an single error counter which is accessible from the EDAC configuration register. 0-1 0 cntbits Number of bits used in the single error counter 1-8 1 pageburst Enable SDRAM page burst operation. 0: Controller uses line burst of length 8 for read operations. 1: Controller uses pageburst for read operations. 2: Controller uses pageburst/line burst depending on PageBurst bit in SDRAM configuration register. 0-2 0 mobile Enable Mobile SDRAM support 0: Mobile SDRAM support disabled 1: Mobile SDRAM support enabled but not default 2: Mobile SDRAM support enabled by default 3: Mobile SDRAM support only (no regular SDR support) 0-3 0 GRIP, Apr 2018, Version 2018.1 289 www.cobham.com/gaisler GRLIB IP Core 28.7 Signal descriptions Table 316 shows the interface signals of the core (VHDL ports). Table 316.Signals declarations Signal name Field Type Function Active CLK N/A Input Clock - RST N/A Input Reset Low AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - SDI WPROT Input Not used - DATA[63:0] Input Data - CB[7:0] Input Checkbits - SDCKE[1:0] Output SDRAM clock enable High SDCSN[1:0] Output SDRAM chip select Low SDWEN Output SDRAM write enable Low SDO RASN Output SDRAM row address strobe Low CASN Output SDRAM column address strobe Low DQM[7:0] Output SDRAM data mask: Low DQM[7] corresponds to DATA[63:56], DQM[6] corresponds to DATA[55:48], DQM[5] corresponds to DATA[47:40], DQM[4] corresponds to DATA[39:32], DQM[3] corresponds to DATA[31:24], DQM[2] corresponds to DATA[23:16], DQM[1] corresponds to DATA[15:8], DQM[0] corresponds to DATA[7:0]. Any DQM[ ] signal can be used for CB[ ]. BDRIVE Output Drive SDRAM data bus Low ADDRESS[16:2] Output SDRAM address - DATA[31:0] Output SDRAM data - CB[7:0] Output Checkbits - CE Output Correctable Error High * see GRLIB IP Library User’s Manual GRIP, Apr 2018, Version 2018.1 290 www.cobham.com/gaisler GRLIB IP Core 28.8 Signal definitions and reset values The signals and their reset values are described in table 317. Table 317.Signal definitions and reset values Signal name Type Function Active Reset value sa[14:0] Output SDRAM address High Undefined sd[31:0] Input/Output SDRAM data High Tri-state scb[15:0] Input/Output SDRAM check bits High Tri-state sdcsn[1:0] Output SDRAM chip select Low Logical 1 sdwen Output SDRAM write enable Low Logical 1 sdrasn Output SDRAM row address strobe Low Logical 1 sdcasn Output SDRAM column address strobe Low Logical 1 sddqm[3:0] Output SDRAM data mask: sddqm[3] corresponds to sd[31:24], Low Logical 1 sddqm[2] corresponds to sd[23:16], sddqm[1] corresponds to sd[15:8], sddqm[0] corresponds to sd[7:0]. Any sddqm[] signal can be used for scb[ ]. 28.9 Timing The timing waveforms and timing parameters are shown in figure 86 and are defined in table 318. clk sdcasn, sdrasn sdwen, sdcsn[] sddqm[] tFTSDCTRL0 write nop read nop nop term nop nop nop tFTSDCTRL0 sa[] tFTSDCTRL1 tFTSDCTRL3 tFTSDCTRL2 sd[], scb[] tFTSDCTRL4 Figure 86. Timing waveforms Table 318.Timing parameters Name Parameter Reference edge Min Max Unit tFTSDCTRL0 clock to output delay rising clk edge TBD TBD ns tFTSDCTRL1 clock to data output delay rising clk edge TBD TBD ns tFTSDCTRL2 data clock to data tri-state delay rising clk edge TBD TBD ns tFTSDCTRL3 data input to clock setup rising clk edge TBD - ns tFTSDCTRL4 data input from clock hold rising clk edge TBD - ns GRIP, Apr 2018, Version 2018.1 291 www.cobham.com/gaisler GRLIB IP Core 28.10 Library dependencies Table 5 shows libraries used when instantiating the core (VHDL libraries). Table 319.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals, component Memory bus signals definitions, component declaration 28.11 Instantiation This example shows how the core can be instantiated. The example design contains an AMBA bus with a number of AHB components connected to it including the FT SDRAM controller. The external SDRAM bus is defined in the example designs port map and connected to the SDRAM controller. System clock and reset are generated by GR Clock Generator and Reset Generator. It is also shown how the correctable error (CE) signal is connected to the ahb status register. It is not mandatory to connect this signal. In this example, 3 units can be connected to the status register. The SDRAM controller decodes SDRAM area: 0x60000000 - 0x6FFFFFFF. SDRAM Configuration and EDAC configuration registers are mapped into AHB I/O space on address (AHB I/O base address + 0x100). library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.tech.all; library gaisler; use gaisler.memctrl.all; use gaisler.pads.all; -- used for I/O pads use gaisler.misc.all; entity mctrl_ex is port ( clk : in std_ulogic; resetn : in std_ulogic; pllref : in std_ulogic; ... -- other signals -- sdram memory bus sdcke : out std_logic_vector ( 1 downto 0); -- clk en sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel sdwen : out std_logic; -- write en sdrasn : out std_logic; -- row addr stb sdcasn : out std_logic; -- col addr stb sddqm : out std_logic_vector (7 downto 0); -- data i/o mask sdclk : out std_logic; -- sdram clk output sa : out std_logic_vector(14 downto 0); -- optional sdram address sd : inout std_logic_vector(63 downto 0); -- optional sdram data cb : inout std_logic_vector(7 downto 0) --EDAC checkbits ); end; architecture rtl of mctrl_ex is -- AMBA bus (AHB and APB) signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; GRIP, Apr 2018, Version 2018.1 292 www.cobham.com/gaisler GRLIB IP Core signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); -- signals used to connect SDRAM controller and SDRAM memory bus signal sdi : sdctrl_in_type; signal sdo : sdctrl_out_type; signal clkm, rstn : std_ulogic; -- system clock and reset signal ce : std_logic_vector(0 to 2); --correctable error signal vector -- signals used by clock and reset generators signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal gnd : std_ulogic; begin -- AMBA Components are defined here ... ... -- Clock and reset generators clkgen0 : clkgen generic map (clk_mul => 2, clk_div => 2, sdramen => 1, tech => virtex2, sdinvclk => 0) port map (clk, gnd, clkm, open, open, sdclk, open, cgi, cgo); cgi.pllctrl <= "00"; cgi.pllrst <= resetn; cgi.pllref <= pllref; rst0 : rstgen port map (resetn, clkm, cgo.clklock, rstn); -- AHB Status Register astat0 : ahbstat generic map(pindex => 13, paddr => 13, pirq => 11, nftslv => 3) port map(rstn, clkm, ahbmi, ahbsi, ce, apbi, apbo(13)); -- SDRAM controller sdc : ftsdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#, ioaddr => 1, fast => 0, pwron => 1, invclk => 0, edacen => 1, errcnt => 1, cntbits => 4) port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo, ce(0)); -- input signals sdi.data(31 downto 0) <= sd(31 downto 0); -- connect SDRAM controller outputs to entity output signals sa <= sdo.address; sdcke <= sdo.sdcke; sdwen <= sdo.sdwen; sdcsn <= sdo.sdcsn; sdrasn <= sdo.rasn; sdcasn <= sdo.casn; sddqm <= sdo.dqm; -- I/O pads driving data bus signals sd_pad : iopadv generic map (width => 32) port map (sd(31 downto 0), sdo.data, sdo.bdrive, sdi.data(31 downto 0)); -- I/O pads driving checkbit signals cb_pad : iopadv generic map (width => 8) port map (cb, sdo.cb, sdo.bdrive, sdi.cb); end; 28.12 Constraints This section contains example constraints for the SDRAM controller. ###### SDRAM interface ### set sdram_freq 100.0 set sdram_clkper [ expr { 1000.0 / $sdram_freq } ] GRIP, Apr 2018, Version 2018.1 293 www.cobham.com/gaisler GRLIB IP Core create_clock -name "c_memclk" -period $sdram_clkper [get_ports "mem_clk"] set sdram_cmd_ports [get_ports {mem_wen mem_rasn mem_cke mem_casn mem_ba mem_addr[12] mem_addr[11] mem_addr[10] mem_addr[9] mem_addr[8] mem_addr[7] mem_addr[6] mem_addr[5] mem_addr[4] mem_addr[3] mem_addr[2] mem_addr[1] mem_addr[0]}] set sdram_cs_ports [get_ports {mem_sn*}] set sdram_dq_ports [get_ports mem_dq] set sdram_dqm_ports [get_ports mem_dqm] # Use Micron datasheet values for SDRAM plus 1 ns margin for PCB propagation and other unmodeled effects set sdram_tAC 6.0 set sdram_tOHN 1.8 set sdram_ts_cmd 1.5 set sdram_th_cmd 0.8 set sdram_ts_cs 1.5 set sdram_th_cs 0.8 set sdram_ts_dq 1.5 set sdram_th_dq 0.8 set sdram_ts_dqm 1.5 set sdram_th_dqm 0.8 set_input_delay -clock "c_memclk" -min $sdram_tOHN $sdram_dq_ports set_input_delay -clock "c_memclk" -max [expr { $sdram_tAC + 1.0 }] $sdram_dq_ports set_output_delay set_output_delay set_output_delay set_output_delay set_output_delay set_output_delay set_output_delay set_output_delay -clock -clock -clock -clock -clock -clock -clock -clock GRIP, Apr 2018, Version 2018.1 "c_memclk" "c_memclk" "c_memclk" "c_memclk" "c_memclk" "c_memclk" "c_memclk" "c_memclk" -max -min -max -min -max -min -max -min [expr {$sdram_ts_cmd+1.0}] $sdram_cmd_ports -$sdram_th_cmd $sdram_cmd_ports [expr {$sdram_ts_cs+1.0}] $sdram_cs_ports -$sdram_th_cs $sdram_cs_ports [expr {$sdram_ts_dq+1.0}] $sdram_dq_ports -$sdram_th_dq $sdram_dq_ports [expr {$sdram_ts_dqm+1.0}] $sdram_dqm_ports -$sdram_th_dqm $sdram_dqm_ports 294 www.cobham.com/gaisler GRLIB IP Core 29 FTSRCTRL - Fault Tolerant 32-bit PROM/SRAM/IO Controller 29.1 Overview The fault tolerant 32-bit PROM/SRAM memory interface uses a common 32-bit memory bus to interface PROM, SRAM and I/O devices. Support for 8-bit PROM banks can also be separately enabled. In addition it also provides an Error Detection And Correction Unit (EDAC), correcting one and detecting two errors. Configuration of the memory controller functions is performed through the APB bus interface. A AHB SRO.ROMSN PROM SRO.RAMSN SRO.RAMOEN SRO.RWEN[3:0] CS OE WE SRAM SRO.IOSN CS OE WE IO SRO.WRITEN CB A CS OE WE SRO.OEN D D CB MEMORY CONTROLLER A D CB A D SRI.A[27:0] SRI.D[31:0] SRO.D[31:0] CB[7:0] AHB/APB APB Bridge Figure 87. 32-bit FT PROM/SRAM/IO controller 29.2 Operation The controller is configured through VHDL generics to decode three address ranges: PROM, SRAM and I/O area. By default the PROM area is mapped into address range 0x0 - 0x00FFFFFF, the SRAM area is mapped into address range 0x40000000 - 0x40FFFFFF, and the I/O area is mapped to 0x20000000 - 0x20FFFFFF. One chip select is decoded for the I/O area, while SRAM and PROM can have up to 8 chip select signals. The controller generates both a common write-enable signal (WRITEN) as well as four bytewrite enable signals (WREN). If the SRAM uses a common write enable signal the controller can be configured to perform read-modify-write cycles for byte and half-word write accesses. Number of waitstates is separately configurable for the three address ranges. The EDAC function is optional, and can be enabled with the edacen VHDL generic. The configuration of the EDAC is done through a configuration register accessed from the APB bus. During nominal operation, the EDAC checksum is generated and checked automatically. Single errors are corrected without generating any indication of this condition in the bus response. If a multiple error is detected, a two cycle error response is given on the AHB bus. GRIP, Apr 2018, Version 2018.1 295 www.cobham.com/gaisler GRLIB IP Core Single errors can be monitored in two ways: • by monitoring the CE signal which is asserted for one cycle each time a single error is detected. • by checking the single error counter which is accessed from the MCFG3 configuration register. The CE signal can be connected to the AHB status register which stores information of the AHB instruction causing the error and also generates interrupts. See the AHB status register documentation for more information. When EDAC is enabled, one extra latency cycle is generated during reads and subword writes.  The EDAC function can be enabled for SRAM and PROM area accesses, but not for I/O area accesses. For the SRAM area, the EDAC functionality is only supported for accessing 32-bit wide SRAM banks. For the PROM area, the EDAC functionality is supported for accessing 32-bit wide PROM banks, as well as for read accesses to 8-bit wide PROM banks. The equations below show how the EDAC checkbits are generated: CB0 CB1 CB2 CB3 CB4 CB5 CB6 = = = = = = = D0 D0 D0 D0 D2 D8 D0 ^ ^ ^ ^ ^ ^ ^ D4 D1 D3 D1 D3 D9 D1 ^ ^ ^ ^ ^ ^ ^ D6 ^ D7 ^ D2 ^ D4 ^ D4 ^ D7 ^ D5 ^ D6 ^ D4 ^ D5 ^ D10 ^ D11 D2 ^ D3 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31 D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28 D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31 D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29 D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 29.2.1 8-bit PROM access The FTSRCTRL controller can be configured to access an 8-bit wide PROM. The data bus of the external PROM should be connected to the upper byte of the 32-bit data bus, i.e. D[31:24]. The 8-bit mode is enabled with the prom8en VHDL generic. When enabled, read accesses to the PROM area will be done in four-byte bursts for all 32-, 16- and 8-bit AMBA AHB accesses. The whole 32-bit word is then output on the AHB data bus, allowing the master to chose the bytes needed (big-endian). Writes should be done one byte at a time. For correct word aligned 32-bit word write accesses, the byte should always be driven on bits 31 to 24 on the AHB data bus. For non-aligned 32-bit word write accesses, the byte should be driven on the bits of the AHB data bus that correspond to the byte address (big-endian). For correct half-word aligned 16-bit half-word write accesses, the byte should always be driven on bits 31 to 24, or 15 to 8, on the AHB data bus. For non-aligned 16-bit half-word write accesses, the byte should be driven on the bits of the AHB data bus that correspond to the byte address (big-endian). For 8-bit word write accesses the byte should always be driven on the AHB data bus bits that corresponds to the byte address (big-endian). To summarize, all legal AMBA AHB write accesses are supported according to the AMBA standard, additional illegal accesses are supported as described above, and it is always the addressed byte that is output. It is possible to dynamically switch between 8- and 32-bit PROM mode by writing to the RBW field of the MCFG1 register. The BWIDTH[1:0] input signal determines the reset value of this RBW register field. When RBW is “00” then 8-bit mode is selected. If RBW is “10” then 32-bit mode is selected. Other RBW values are reserved for future use. SRAM access is not affected by the 8-bit PROM mode. It is also possible to use the EDAC in the 8-bit PROM mode, configured by the edacen VHDL generic, and enabled via the MCFG3 register. Read accesses to the 8-bit PROM area will be done in five-byte bursts for all 32-, 16- and 8-bit AMBA AHB accesses. After a potential correction, the whole 32-bit word is output on the AHB data bus, allowing the master to chose the bytes needed (bigendian). EDAC support is not provided for write accesses, they are instead performed in the same way as without the EDAC enabled. The checksum byte must be written by the user into the correct byte address location. The fifth byte corresponds to the EDAC checksum and is located in the upper part of the effective memory area, as explained in detail in the definition of the MCFG1 memory configuration register. The EDAC checksums are located in the upper quarter of what is defined as available EDAC area by means of the EBSZ field and the ROMBSZ field or rombanksz VHDL generic. When set to 0, the size GRIP, Apr 2018, Version 2018.1 296 www.cobham.com/gaisler GRLIB IP Core of the available EDAC area is defined as the PROM bank size. When set to 1, as twice the PROM bank size. When set to 2, as four times the PROM bank size. And when set to 3, as eight times the PROM bank size. For any other value than 0, the use of multiple PROM banks is required. Example, if ROMBSZ=10 and EBSZ=1, the EDAC area is 8KiB*2^ROMBSZ*2^EBSZ= 16MiB=0x01000000. The checksum byte for the first word located at address 0x00000000 to 0x00000003 is located at 0x00C00000. The checksum byte for the second word located at address 0x00000004 to 0x00000007 is located at 0x00C00001, and so on. Since EBSZ=1, two PROM banks are required for implementing the EDAC area, each bank with size 8MiB=0x00800000. 29.2.2 Access errors The active low Bus Exception signal (BEXCN) can be used to signal access errors. It is enabled by setting the BEXCEN bit in MCFG1 and is active for all types of accesses to all areas (PROM, SRAM and I/O). The BEXCN signal is sampled on the same cycle as read data is sampled. For writes it is sampled on the last rising edge before writen/rwen is de-asserted (writen and rwen are clocked on the falling edge). When a bus exception is detected an error response will be generated for the access. data lead-out clk address A1 romsn/iosn/ramsn oen data D1 bexcn Figure 88. Read cycle with BEXCN. lead-in data1 data2 data3 lead-out clk address A1 romsn/iosn/ramsn rwen data D1 bexcn Figure 89. Write cycle with BEXCN. 29.2.3 Using bus ready signalling The Bus Ready (BRDYN) signal can be used to add waitstates to I/O-area accesses, covering the complete memory area and both read and write accesses. It is enabled by setting the Bus Ready GRIP, Apr 2018, Version 2018.1 297 www.cobham.com/gaisler GRLIB IP Core Enable (BRDYEN) bit in the MCFG1 register. An access will have at least the amount of waitstates set with the VHDL generic or through the register, but will be further stretched until BRDYN is asserted. Additional waitstates can thus be inserted after the pre-set number of waitstates by de-asserting the BRDYN signal. BRDYN should be asserted in the cycle preceding the last one. It is recommended that BRDYN remains asserted until the IOSN signal is de-asserted, to ensure that the access has been properly completed and avoiding the system to stall. Read accesses will have the same timing as when EDAC is enabled while write accesses will have the timing as for single accesses even if bursts are performed. lead-in wait data data clk address A1 iosn oen data D1 brdyn first sample Figure 90. I/O READ cycle, programmed with 1 wait state, and with an extra data cycle added with BRDYN. 29.3 PROM/SRAM/IO waveforms The internal and external waveforms of the interface are presented in the figures hereafter. data1 lead-out data1 lead-out clk address A1 A2 romsn ramsn oen data cb haddr htrans D1 D2 CB1 CB2 A1 A2 A3 10 10 00 hready hrdata D1 D2 Figure 91. PROM/SRAM non-consecutive read cyclecs. GRIP, Apr 2018, Version 2018.1 298 www.cobham.com/gaisler GRLIB IP Core data1 data1 data1 data1 lead-out clk address A1 A3 A2 A4 romsn ramsn oen data cb haddr htrans D1 D2 D3 D4 CB1 CB2 CB3 CB4 A3 A4 A2 A1 A5 00 11 10 hready hrdata D1 D2 D3 D4 Figure 92. 32-bit PROM/SRAM sequential read access with 0 wait-states and EDAC disabled. data1 unused lead-out data1 unused lead-out clk address A1 A2 romsn ramsn oen data cb haddr htrans D1 D2 CB1 CB2 A1 A2 A3 10 10 00 hready hrdata D1 D2 Figure 93. 32-bit PROM/SRAM non-sequential read access with 0 wait-states and EDAC enabled. GRIP, Apr 2018, Version 2018.1 299 www.cobham.com/gaisler GRLIB IP Core data1 data1 data1 data1 unused lead-out clk address A1 A3 A2 A4 romsn ramsn oen data cb haddr htrans D1 D2 D3 D4 CB1 CB2 CB3 CB4 A3 A2 A1 A5 A4 00 11 10 hready hrdata D1 D3 D2 D4 Figure 94. 32-bit PROM/SRAM sequential read access with 0 wait-states and EDAC enabled.. lead-in data1 data2 lead-out lead-in data1 data2 lead-out clk address A1 A2 romsn ramsn writen data cb haddr htrans D1 D2 CB1 CB2 A1 A2 A3 10 10 00 hready hwdata D1 D2 Figure 95. 32-bit PROM/SRAM non-sequential write access with 0 wait-states and EDAC disabled. GRIP, Apr 2018, Version 2018.1 300 www.cobham.com/gaisler GRLIB IP Core lead-in data1 data2 data1 data2 data1 data2 lead-out clk address A1 A2 A3 romsn ramsn writen data cb haddr htrans A1 D1 D2 D3 CB1 CB2 CB3 A2 10 A3 A4 11 00 hready hwdata D1 D2 D3 Figure 96. 32-bit PROM/SRAM sequential write access with 0 wait-states and EDAC disabled. If waitstates are configured through the VHDL generics or registers, one extra data cycle will be inserted for each waitstate in both read and write cycles. The timing for write accesses is not affected when EDAC is enabled while one extra latency cycle is introduced for single access reads and at the beginning of read bursts. GRIP, Apr 2018, Version 2018.1 301 www.cobham.com/gaisler GRLIB IP Core clk address A1 romsn ramsn writen oen data D1 cb D1/M1 CM1 CB1 haddr htrans A1 A2 10 00 hready hwdata M1 Figure 97. 32-bit PROM/SRAM rmw access with 0 wait-states and EDAC disabled. Read-Modify-Write (RMW) accesses will have an additional waitstate inserted to accommodate decoding when EDAC is enabled. I/O accesses are similar to PROM and SRAM accesses but a lead-in and lead-out cycle is always present. lead-in data1 data2 data3 lead-out clk address A1 iosn writen data haddr htrans D1 A1 A2 10 00 hready hwdata D1 Figure 98. I/O write access with 0 wait-states. GRIP, Apr 2018, Version 2018.1 302 www.cobham.com/gaisler GRLIB IP Core lead-in data lead-out clk address A1 iosn oen data haddr htrans D1 A1 A2 10 00 hready hrdata D1 Figure 99. I/O read access with 0 wait-states 29.4 Endianness The core is designed for big-endian systems. 29.5 Registers The core is programmed through registers mapped into APB address space. Table 320.FT PROM/SRAM/IO controller registers APB Address offset Register 0x0 Memory configuration register 1 0x4 Memory configuration register 2 0x8 Memory configuration register 3 GRIP, Apr 2018, Version 2018.1 303 www.cobham.com/gaisler GRLIB IP Core 29.5.1 Memory Configuration Register 1 Table 321.0x00 - MCFG1 - Memory configuration register 1. 31 27 26 25 24 23 RESERVED BR BE R 20 19 18 17 IOWS R 14 13 12 11 10 ROMBSZ EBSZ RW R 9 8 7 4 3 0 RBW RESERVED ROMWS 0 0 0 0 0 0 * * 0 0 * 0 0xF r rw rw r rw r rw* rw* rw r rw r rw 31: 27 RESERVED 26 Bus ready enable (BR) - Enables the bus ready signal (BRDYN) for I/O-area. 25 Bus exception enable (BE) - Enables the bus exception signal (BEXCEN) for PROM, SRAM and I/ O areas 24 RESERVED 23: 20 I/O wait states (IOWS) - Sets the number of waitstates for accesses to the I/O-area. Only available if the wsreg VHDL generic is set to one. 19: 18 RESERVED 17: 14 ROM bank size (ROMBSZ) - Sets the PROM bank size. Only available if the rombanksz VHDL generic is set to zero. Otherwise, the rombanksz VHDL generic sets the bank size and the value can be read from this field. 0 = 8KiB, 1 = 16KiB, 2 = 32KiB, 3 = 64KiB, ..., 15=256 MiB (i.e. 8 KiB * 2**ROMBSZ). 13: 12 EDAC bank size (EBSZ) - Sets the EDAC bank size for 8-bit PROM support. Only available if the rombanksz VHDL generic is zero, and edacen and prom8en VHDL generics are one. Otherwise, the value is fixed to 0. The resulting EDAC bank size is 2^EBSZ * 2^ROMBSZ * 8KiB. Note that only the three lower quarters of the bank can be used for user data. The EDAC checksums are placed in the upper quarter of the bank. 11 ROM write enable (RW) - Enables writes to the PROM memory area. When disabled, writes to the PROM area will generate an ERROR response on the AHB bus. 10 RESERVED 9: 8 ROM data bus width (RBW) - Sets the PROM data bus width. “00” = 8-bit, “10” = 32-bit, others reserved. 7: 4 RESERVED 3: 0 ROM waitstates (ROMWS) - Sets the number of waitstates for accesses to the PROM area. Reset to all-ones. Only available if the wsreg generic is set to one. 29.5.2 Memory Configuration Register 2 Table 322.0x04 - MCFG2 - Memory configuration register 2. 31 13 12 RESERVED 9 8 7 RAMBSZ R 0 * r rw* 6 5 2 1 0 RW RESERVED RAMW 0 * 0 0 r rw* r rw* 31: 13 RESERVED 12: 9 RAM bank size (RAMBSZ) - Sets the RAM bank size. Only available if the banksz VHDL generic is set to zero. Otherwise, the banksz VHDL generic sets the bank size and the value can be read from this field. 0 = 8KiB, 1 = 16KiB, 2 = 32KiB, 3 = 64KiB, ..., 15=256 MiB (i.e. 8 KiB * 2**RAMBSZ) 8: 7 RESERVED 6 Read-modify-write enable (RW) - Enables read-modify-write cycles for write accesses. Only available if the rmw VHDL generic is set to one. 5: 2 RESERVED 1: 0 RAM waitstates (RAMW) - Sets the number of waitstates for accesses to the RAM area. Only available if the wsreg VHDL generic is set to one. GRIP, Apr 2018, Version 2018.1 304 www.cobham.com/gaisler GRLIB IP Core 29.5.3 Memory Configuration Register 3 Table 323.0x08 - MCFG3 - Memory configuration register 3. 31 20 19 12 11 10 RESERVED SEC 0 0 r wc 9 8 WB RB SE PE 0 0 0 7 0 TCB 0 NR rw rw rw rw rw* 31: 20 RESERVED 19: 12 Single error counter.(SEC) - This field increments each time a single error is detected until the maximum value that can be stored in the field is reached. Each bit can be reset by writing a one to it. 11 Write bypass (WB) - Enables EDAC write bypass. When enabled the TCB field will be used as checkbits in all write operations. 10 Read bypass (RB) - Enables EDAC read bypass. When enabled checkbits read from memory in all read operations will be stored in the TCB field. 9 SRAM EDAC enable (SE) - Enables EDAC for the SRAM area. 8 PROM EDAC enable (PE) - Enables EDAC for the PROM area. Reset value is taken from the input signal sri.edac. 7: 0 Test checkbits (TCB) - Used as checkbits in write operations when WB is activated and checkbits from read operations are stored here when RB is activated. All the fields in MCFG3 register are available if the edacen VHDL generic is set to one except SEC field which also requires that the errcnt VHDL generic is set to one. The exact breakpoint between the SEC and RESERVED field depends on the cntbits generic. The breakpoint is 11+cntbits. The values shown in the table is for maximum cntbits value 8. 29.6 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x051. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 29.7 Implementation 29.7.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. The registers driving external chip select, output enable and output enables for the data bus have asynchronous reset. GRIP, Apr 2018, Version 2018.1 305 www.cobham.com/gaisler GRLIB IP Core 29.8 Configuration options Table 320 shows the configuration options of the core (VHDL generics). Table 324. Controller configuration options 29.9 Generic Function Allowed range Default hindex AHB slave index. 1 - NAHBSLV-1 0 romaddr ADDR field of the AHB BAR0 defining PROM address space. Default PROM area is 0x0 - 0xFFFFFF. 0 - 16#FFF# 16#000# rommask MASK field of the AHB BAR0 defining PROM address space. 0 - 16#FFF# 16#FF0# ramaddr ADDR field of the AHB BAR1 defining RAM address space. Default RAM area is 0x40000000-0x40FFFFFF. 0 - 16#FFF# 16#400# rammask MASK field of the AHB BAR1 defining RAM address space. 0 -16#FFF# 16#FF0# ioaddr ADDR field of the AHB BAR2 defining IO address space. Default RAM area is 0x20000000-0x20FFFFFF. 0 - 16#FFF# 16#200# iomask MASK field of the AHB BAR2 defining IO address space. 0 - 16#FFF# 16#FF0# ramws Number of waitstates during access to SRAM area. 0 - 15 0 romws Number of waitstates during access to PROM area. 0 - 15 2 iows Number of waitstates during access to IO area. 0 - 15 2 rmw Enable read-modify-write cycles. 0-1 0 srbanks Set the number of RAM banks. 1-8 1 banksz Set the size of bank 1 - 4. 1 = 16KiB, 2 = 32KiB, 3 = 64KiB, ... , 15 = 256 MiB (i.e. 8 KiB * 2**banksz). If set to zero, the bank size is set with the rambsz field in the MCFG2 register. 0 - 15 15 rombanks Sets the number of PROM banks available. 1-8 1 rombanksz Sets the size of one PROM bank. 1 = 16KiB, 2 = 32KiB, 3 = 64KiB, ... , 15 = 256 MiB (i.e. 8 KiB * 2**rombanksz). If set to zero, the bank size is set with the rombsz field in the MCFG1 register. 0 - 15 15 rombankszdef Sets the reset value of the rombsz register field in MCFG1 if available. 0 - 15 15 pindex APB slave index. 1 - NAPBSLV-1 0 paddr APB address. 1 - 16#FFF# 0 pmask APB address mask. 1 - 16#FFF# 16#FFF# edacen EDAC enable. If set to one, EDAC logic is synthesized. 0-1 0 errcnt If one, a single error counter is added. 0-1 0 cntbits Number of bits in the single error counter. 1-8 1 wsreg Enable programmable waitstate generation. 0-1 0 prom8en Enable 8-bit PROM mode. 0-1 0 oepol Select polarity of output enable signals. 0 = active low, 1 = active high. 0-1 0 Signal descriptions Table 325 shows the interface signals of the core (VHDL ports). Table 325.Signal descriptions Signal name Field Type Function Active CLK N/A Input Clock - RST N/A Input Reset Low GRIP, Apr 2018, Version 2018.1 306 www.cobham.com/gaisler GRLIB IP Core Table 325.Signal descriptions Signal name SRI Field Type Function Active DATA[31:0] Input Memory data High BRDYN Input Bus ready strobe Low BEXCN Input Bus exception Low WRN[3:0] Input Not used - BWIDTH[1:0] Input Sets the reset value of the PROM data bus width field in the MCFG1 register - SD[31:0] Input Not used - CB[7:0] Input Checkbits - PROMDATA[31:0] Input Not used - EDAC Input The reset value for the PROM EDAC enable bit High GRIP, Apr 2018, Version 2018.1 307 www.cobham.com/gaisler GRLIB IP Core Table 325.Signal descriptions Signal name Field Type Function Active SRO ADDRESS[31:0] Output Memory address High DATA[31:0] Output Memory data High RAMSN[7:0] Output SRAM chip-select Low RAMOEN[7:0] Output SRAM output enable Low IOSN Output IO area chip select Low ROMSN[7:0] Output PROM chip-select Low OEN Output Output enable Low WRITEN Output Write strobe Low WRN[3:0] Output SRAM write enable: Low WRN[0] corresponds to DATA[31:24], WRN[1] corresponds to DATA[23:16], WRN[2] corresponds to DATA[15:8], WRN[3] corresponds to DATA[7:0]. Any WRN[ ] signal can be used for CB[ ]. MBEN[3:0] Output Byte enable: MBEN[0] corresponds to DATA[31:24], MBEN[1] corresponds to DATA[23:16], MBEN[2] corresponds to DATA[15:8], MBEN[3] corresponds to DATA[7:0]. Any MBEN[ ] signal can be used for CB[ ]. BDRIVE[3:0] Output Drive byte lanes on external memory bus.Controls I/O-pads connected to external memory bus: Low BDRIVE[0] corresponds to DATA[31:24], BDRIVE[1] corresponds to DATA[23:16], BDRIVE[2] corresponds to DATA[15:8], BDRIVE[3] corresponds to DATA[7:0]. Any BDRIVE[ ] signal can be used for CB[ ]. READ Output Read strobe High RAMN Output Common SRAM Chip Select. Always asserted when one of the 8 RAMSN signals is asserted. Low ROMN Output Common PROM Chip Select. Always asserted when one of the 8 ROMSN signals is asserted. Low SA[14:0] Output Not used - CB[7:0] Output Checkbits - PSEL Output Not used - CE Output Single error detected. High AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - SDO SDCASN Output Not used. All signals are drive to inactive state. Low * see GRLIB IP Library User’s Manual GRIP, Apr 2018, Version 2018.1 308 www.cobham.com/gaisler GRLIB IP Core 29.10 Signal definitions and reset values The signals and their reset values are described in table 326. Table 326.Signal definitions and reset values Signal name Type Function Active Reset value address[27:0] Output Memory address High Undefined data[31:0] Input/Output Memory data High Tri-state cb[7:0] Input/Output Check bits High Tri-state ramsn[3:0] Output SRAM chip select Low Logical 1 ramoen[3:0] Output SRAM output enable Low Logical 1 rwen[3:0] Output, SRAM write byte enable: Low Logical 1 Low Logical 1 Output enable Low Logical 1 rwen[0] corresponds to data[31:24], rwen[1] corresponds to data[23:16], rwen[2] corresponds to data[15:8], rwen[3] corresponds to data[7:0]. Any rwen[ ] signal can be used for cb[ ]. ramben[3:0] Output SRAM read/write byte enable: ramben[0] corresponds to data[31:24], ramben[1] corresponds to data[23:16], ramben[2] corresponds to data[15:8], ramben[3] corresponds to data[7:0]. Any ramben[ ] signal can be used for cb[ ]. oen Output writen Output Write strobe Low Logical 1 read Output Read strobe High Logical 1 iosn Output IO area chip select Low Logical 1 romsn[1:0] Output PROM chip select Low Logical 1 brdyn Input Bus ready. Extends accesses to the IO area. Low - bexcn Input Bus exception. Low - GRIP, Apr 2018, Version 2018.1 309 www.cobham.com/gaisler GRLIB IP Core 29.11 Timing The timing waveforms and timing parameters are shown in figure 100 and are defined in table 327. clk tFTSRCTRL0 address[] ramsn[], romsn[] iosn tFTSRCTRL1 tFTSRCTRL1 tFTSRCTRL2 tFTSRCTRL2 rwen[], writen tFTSRCTRL3, tFTSRCTRL4 data[], cb[] (output) tFTSRCTRL5 tFTSRCTRL3 clk address[] ramsn[], romsn[] iosn tFTSRCTRL6 ramoen[] ramben[], oen, read tFTSRCTRL6 tFTSRCTRL7 tFTSRCTRL8 data[], cb[] (input) tFTSRCTRL10 tFTSRCTRL9 brdyn, bexcn Figure 100. Timing waveforms Table 327.Timing parameters Name Parameter Reference edge Min Max Unit tFTSRCTRL0 address clock to output delay rising clk edge TBD TBD ns tFTSRCTRL1 clock to output delay rising clk edge TBD TBD ns tFTSRCTRL2 clock to output delay rising clk edge TBD TBD ns tFTSRCTRL3 clock to data output delay falling clk edge TBD TBD ns tFTSRCTRL4 clock to data non-tri-state delay rising clk edge TBD TBD ns tFTSRCTRL5 clock to data tri-state delay rising clk edge TBD TBD ns tFTSRCTRL6 clock to output delay rising clk edge TBD TBD ns tFTSRCTRL7 data input to clock setup rising clk edge TBD - ns tFTSRCTRL8 data input from clock hold rising clk edge TBD - ns tFTSRCTRL9 input to clock setup rising clk edge TBD - ns tFTSRCTRL10 input from clock hold rising clk edge TBD - ns GRIP, Apr 2018, Version 2018.1 310 www.cobham.com/gaisler GRLIB IP Core 29.12 Library dependencies Table 328 shows libraries used when instantiating the core (VHDL libraries). Table 328.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals, component Memory bus signals definitions, component declaration 29.13 Component declaration The core has the following component declaration. component ftsrctrl generic ( hindex : romaddr : rommask : ramaddr : rammask : ioaddr : iomask : ramws : romws : iows : rmw : srbanks : banksz : rombanks : rombanksz : rombankszdef : pindex : paddr : pmask : edacen : errcnt : cntbits : wsreg : oepol : prom8en : ); port ( rst : clk : ahbsi : ahbso : apbi : apbo : sri : sro : sdo : ); end component; is integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer in in in out in out in out out := 0; := 0; := 16#ff0#; := 16#400#; := 16#ff0#; := 16#200#; := 16#ff0#; := 0; := 2; := 2; := 0; range 1 to 8 := 1; range 0 to 15 := 15; range 1 to 8 := 1; range 0 to 15 := 15; range 0 to 15 := 15; := 0; := 0; := 16#fff#; range 0 to 1 := 1; range 0 to 1 := 0; range 1 to 8 := 1; := 0; := 0; := 0 std_ulogic; std_ulogic; ahb_slv_in_type; ahb_slv_out_type; apb_slv_in_type; apb_slv_out_type; memory_in_type; memory_out_type; sdctrl_out_type 29.14 Instantiation This example shows how the core can be instantiated. The example design contains an AMBA bus with a number of AHB components connected to it including the memory controller. The external memory bus is defined in the example design’s port map and connected to the memory controller. System clock and reset are generated by GR Clock Generator and Reset Generator. The CE signal of the memory controller is also connected to the AHB status register. GRIP, Apr 2018, Version 2018.1 311 www.cobham.com/gaisler GRLIB IP Core Memory controller decodes default memory areas: PROM area is 0x0 - 0xFFFFFF and RAM area is 0x40000000 - 0x40FFFFF. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.tech.all; library gaisler; use gaisler.memctrl.all; use gaisler.pads.all; -- used for I/O pads use gaisler.misc.all; entity mctrl_ex is port ( clk : in std_ulogic; resetn : in std_ulogic; pllref : in std_ulogic; -- memory bus address : out std_logic_vector(27 downto 0); -- memory bus data : inout std_logic_vector(31 downto 0); ramsn : out std_logic_vector(4 downto 0); ramoen : out std_logic_vector(4 downto 0); rwen : inout std_logic_vector(3 downto 0); romsn : out std_logic_vector(1 downto 0); iosn : out std_logic; oen : out std_logic; read : out std_logic; writen : inout std_logic; brdyn : in std_logic; bexcn : in std_logic; -- sdram i/f sdcke : out std_logic_vector ( 1 downto 0); -- clk en sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel sdwen : out std_logic; -- write en sdrasn : out std_logic; -- row addr stb sdcasn : out std_logic; -- col addr stb sddqm : out std_logic_vector (7 downto 0); -- data i/o mask sdclk : out std_logic; -- sdram clk output sa : out std_logic_vector(14 downto 0); -- optional sdram address sd : inout std_logic_vector(63 downto 0); -- optional sdram data cb : inout std_logic_vector(7 downto 0); --checkbits ); end; architecture rtl of mctrl_ex is -- AMBA bus (AHB and APB) signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); -- signals used to connect memory controller and memory bus signal memi : memory_in_type; signal memo : memory_out_type; signal sdo : sdctrl_out_type; signal wprot : wprot_out_type; -- dummy signal, not used signal clkm, rstn : std_ulogic; -- system clock and reset -- signals used by clock and reset generators signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; GRIP, Apr 2018, Version 2018.1 312 www.cobham.com/gaisler GRLIB IP Core signal gnd : std_ulogic; signal stati : ahbstat_in_type; --correctable error vector begin -- AMBA Components are defined here ... -- Clock and reset generators clkgen0 : clkgen generic map (clk_mul => 2, clk_div => 2, sdramen => 1, tech => virtex2, sdinvclk => 0) port map (clk, gnd, clkm, open, open, sdclk, open, cgi, cgo); cgi.pllctrl <= "00"; cgi.pllrst <= resetn; cgi.pllref <= pllref; rst0 : rstgen port map (resetn, clkm, cgo.clklock, rstn); -- AHB Status Register astat0 : ahbstat generic map(pindex => 13, paddr => 13, pirq => 11, nftslv => 1) port map(rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13)); stati.cerror(0) <= memo.ce; -- Memory controller mctrl0 : ftsrctrl generic map (rmw => 1, pindex => 10, paddr => 10, edacen => 1, errcnt => 1, cntbits => 4) port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(10), memi, memo, sdo); -- I/O pads driving data memory bus data signals datapads : for i in 0 to 3 generate data_pad : iopadv generic map (width => 8) port map (pad => data(31-i*8 downto 24-i*8), o => memi.data(31-i*8 downto 24-i*8), en => memo.bdrive(i), i => memo.data(31-i*8 downto 24-i*8)); end generate; --I/O pads driving checkbit signals cb_pad : iopadv generic map (width => 8) port map (pad => cb, o => memi.cb, en => memo.bdrive(0), i => memo.cb; -- connect memory controller outputs to entity output signals address <= memo.address; ramsn <= memo.ramsn; romsn <= memo.romsn; oen <= memo.oen; rwen <= memo.wrn; ramoen <= memo.ramoen; writen <= memo.writen; read <= memo.read; iosn <= memo.iosn; sdcke <= sdo.sdcke; sdwen <= sdo.sdwen; sdcsn <= sdo.sdcsn; sdrasn <= sdo.rasn; sdcasn <= sdo.casn; sddqm <= sdo.dqm; end; GRIP, Apr 2018, Version 2018.1 313 www.cobham.com/gaisler GRLIB IP Core 30 FTSRCTRL8 - 8-bit SRAM/16-bit IO Memory Controller with EDAC 30.1 Overview The fault tolerant 8-bit SRAM/16-bit I/O memory interface uses a common 16-bit data bus to interface 8-bit SRAM and 16-bit I/O devices. It provides an Error Detection And Correction unit (EDAC), correcting up to two errors and detecting up to four errors in a data byte. The EDAC eight checkbits are stored in parallel with the 8-bit data in SRAM memory. Configuration of the memory controller functions is performed through the APB bus interface. A AHB SRO.RAMSN SRO.OEN SRO.WRITEN D A CS OE WE SRAM CS OE WE IO D MEMORY CONTROLLER SRO.IOSN A D SRI.A[27:0] SRI.D[15:0] SRO.D[15:0] AHB/APB APB Bridge Figure 101. Block diagram 30.2 Operation The controller is configured through VHDL generics to decode two address ranges: SRAM and I/O area. By default the SRAM area is mapped into address range 0x40000000 - 0x40FFFFFF, and the I/ O area is mapped to 0x20000000 - 0x20FFFFFF. One chip select is decoded for the I/O area, while SRAM can have up to 8 chip select signals. The controller generates a common write-enable signal (WRITEN) for both SRAM and I/O. The number of waitstates may be separately configured for the two address ranges. The EDAC function is optional, and can be enabled with the edacen VHDL generic. The configuration of the EDAC is done through a configuration register accessed from the APB bus. During nominal operation, the EDAC checksum is generated and checked automatically. The 8-bit input to the EDAC function is split into two 4-bit nibbles. A modified hamming(8,4,4) coding featuring a single error correction and double error detection is applied to each 4-bit nibble. This makes the EDAC capable of correcting up to two errors and detecting up to four errors per 8-bit data. Single errors (correctable errors) are corrected without generating any indication of this condition in the bus response. If a multiple error (uncorrectable errors) is detected, a two cycle error response is given on the AHB bus. Single errors may be monitored in two ways: • by monitoring the CE signal which is asserted for one cycle each time a correctable error is detected. • by checking the single error counter which is accessed from the MCFG3 configuration register. GRIP, Apr 2018, Version 2018.1 314 www.cobham.com/gaisler GRLIB IP Core The CE signal can be connected to the AHB status register which stores information of the AHB instruction causing the error and also generates interrupts. See the AHB status register documentation for more information.  The EDAC function can only be enabled for SRAM area accesses. If a 16-bit or 32-bit bus access is performed, the memory controller calculates the EDAC checksum for each byte read from the memory but the indication of single error is only signaled when the access is done. (I.e. if more than one byte in a 32-bit access has a single error, only one error is indicated for the hole 32-bit access.) The equations below show how the EDAC checkbits are generated: CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 = = = = = = = = Data[15] Data[15] Data[15] Data[14] Data[11] Data[11] Data[11] Data[10] ^ ^ ^ ^ ^ ^ ^ ^ Data[14] Data[14] Data[13] Data[13] Data[10] Data[10] Data[ 9] Data[ 9] ^ ^ ^ ^ ^ ^ ^ ^ Data[13] Data[12] Data[12] Data[12] Data[ 9] Data[ 8] Data[ 8] Data[ 8] // // // // // // // // i.e. i.e. i.e. i.e. i.e. i.e. i.e. i.e. Data[7] Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] 30.2.1 Memory access The memory controller supports 32/16/8-bit single accesses and 32-bit burst accesses to the SRAM. A 32-bit or a 16-bit access is performed as multiple 8-bit accesses on the 16-bit memory bus, where data is transferred on data lines 8 to 15 (Data[15:8]). The eight checkbits generated/used by the EDAC are transferred on the eight first data lines (Data[7:0]). For 32-bit and 16-bit accesses, the bytes read from the memory are arranged according to the big-endian order (i.e. for a 32-bit read access, the bytes read from memory address A, A+1, A+2, and A+3 correspond to the bit[31:24], bit[23:16], bit[15:8], and bit[7:0] in the 32-bit word transferred to the AMBA bus. The table 338 shows the expected latency from the memory controller. Table 329.FTSCTRL8 access latency Accesses Single data First data (burst) Middle data (burst) Last data (burst) 32-bit write 10 8 8 10 32-bit read 6 6 4 4 16-bit write 4 (+1) - - - 16-bit read 4 - - - 8-bit write 4 - - - 8-bit read 3 - - - One extra cycle is added for 16-bit burst accesses when Bus Exception is enabled. 30.2.2 I/O access The memory controller accepts 32/16/8-bit single accesses to the I/O area, but the access generated towards the I/O device is always 16-bit. The two least significant bits of the AMBA address (byte address) determine which half word that should be transferred to the I/O device. (i.e. If the byte address is 0 and it is a 32-bit access, bits 16 to 31 on the AHB bus is transferred on the 16-bit memory bus. If the byte address is 2 and it is a 16-bit access, bit 0 to 15 on the AHB bus is transferred on the 16-bit memory bus.) If the access is an 8-bit access, the data is transferred on data lines 8 to 15 (Data[15:8]) on the memory bus. In case of a write, data lines 0 to 7 is also written to the I/O device but these data lines do not transfer any valid data. GRIP, Apr 2018, Version 2018.1 315 www.cobham.com/gaisler GRLIB IP Core 30.2.3 Using Bus Exception The active low Bus Exception signal (BEXCN) can be used to signal access errors. It is enabled by setting the BEXCEN bit in MCFG1 and is only active for the I/O area. The BEXCN signal is sampled on the same cycle as data is written to memory or read data is sampled. When a bus exception is detected an error response will be generated for the access. One additional latency cycle is added to the AMBA access when the Bus Exception is enable. 30.2.4 Using Bus Ready The Bus Ready (BRDYN) signal can be used to add waitstates to I/O-area accesses. It is enabled by setting the Bus Ready Enable (BRDYEN) bit in the MCFG1 register. An access will have at least the amount of waitstates set with the VHDL generic or through the register, but will be further stretched until BRDYN is asserted. Additional waitstates can thus be inserted after the pre-set number of waitstates by deasserting the BRDYN signal. BRDYN should be asserted in the cycle preceding the last one. It is recommended that BRDY remains asserted until the IOSN signal is de-asserted, to ensure that the access has been properly completed and avoiding the system to stall. lead-in wait data data clk address A1 iosn oen data D1 brdyn first sample Figure 102. I/O READ cycle, programmed with 1 wait state, and with an extra data cycle added with BRDYN. 30.3 SRAM/IO waveforms The internal and external waveforms of the interface are presented in the figures below. GRIP, Apr 2018, Version 2018.1 316 www.cobham.com/gaisler GRLIB IP Core clk address A0 A1 A2 A3 A4 A5 A6 A7 ramsn oen data B3 haddr htrans B2 A0 A4 10 11 B1 B0 B7 B6 B5 B4 A8 00 hready hrdata D1 D0 Figure 103. 32-bit SRAM sequential read accesses with 0 wait-states and EDAC enabled. clk address A1 A0 A2 A3 A4 ramsn writen data haddr htrans B3 B2 B1 B0 A0 A4 A8 10 11 00 B4 hready hwdata D1 D0 Figure 104. 32-bit SRAM sequential writeaccess with 0 wait-states and EDAC enabled. GRIP, Apr 2018, Version 2018.1 317 www.cobham.com/gaisler GRLIB IP Core clk address A0 A1 ramsn writen data haddr htrans B3 B2 A0 A1 A2 10 11 00 hready hwdata D1 D0 Figure 105. 8-bit SRAM non-sequential write access with 0 wait-states and EDAC enabled. clk address A1 A0 ramsn oen data haddr htrans B3 A0 B2 A1 10 A2 00 10 hready hrdata D[31:24] D[23:16] Figure 106. 8-bit SRAM non-sequential read access with 0 wait-states and EDAC enabled. On a read access, data is sampled one clock cycle before HREADY is asserted. GRIP, Apr 2018, Version 2018.1 318 www.cobham.com/gaisler GRLIB IP Core clk address A0 iosn writen data haddr htrans H1 A0 A1 10 00 hready hwdata D[31:16] Figure 107. 16-bit I/O non-sequential write access with 0 wait-states. clk address A2 A4 ramsn oen data haddr htrans H1 A2 10 H3 A4 00 10 hready hrdata D[15:0] D[31:16] Figure 108. 16-bit I/O non-sequential read access with 0 wait-states. I/O write accesses are extended with one extra latency cycle if the bus exception is enabled. If waitstates are configured through the VHDL generics or registers, one extra data cycle will be inserted for each waitstate in both read and write cycles. 30.4 Endianness The core is designed for big-endian systems. GRIP, Apr 2018, Version 2018.1 319 www.cobham.com/gaisler GRLIB IP Core 30.5 Registers The core is programmed through registers mapped into APB address space. Table 330.FT SRAM/IO controller registers APB Address offset Register 0x00 Memory configuration register 1 0x04 Memory configuration register 2 0x08 Memory configuration register 3 GRIP, Apr 2018, Version 2018.1 320 www.cobham.com/gaisler GRLIB IP Core 30.5.1 Memory Configuration Register 1 Table 331.0x00 - MCFG1 - Memory configuration register 1 31 27 RESERVED 26 25 24 BRDY BEXC R 23 IOWS 20 19 RESERVED 0 0 0 0 0 0xF 0 r rw rw r rw r 31 : 27 RESERVED 26 BRDYEN: Enables the BRDYN signal. 25 BEXCEN: Enables the BEXCN signal. 24 RESERVED 23 : 20 IOWS: Sets the number of waitstates for accesses to the IO area. Only available if the wsreg VHDL generic is set to one. 19 : 0 RESERVED 30.5.2 Memory Configuration Register 2 Table 332.0x04 - MCFG2 - Memory configuration register 2 31 13 12 RESERVED 9 8 2 1 0 RAMBSZ RESERVED RAMWS 0 * 0 * r rw* r rw* 31 : 12 RESERVED 12 : 9 RAMBSZ: Sets the SRAM bank size. Only available if the banksz VHDL generic is set to zero. Otherwise the banksz VHDL generic sets the bank size. 0 = 8 kB, 15 = 256 MB. 8:2 RESERVED 1:0 RAMWS: Sets the number of waitstates for accesses to the RAM area. Only available if the wsreg VHDL generic is set to one. 30.5.3 Memory Configuration 3 Table 333.0x08 - MCFG2 - Memory configuration register 3 31 cnt + 13 cnt + 12 RESERVED 12 SEC 11 10 9 WB RB SEN 8 7 0 TCB 0 0 0 0 0 0 NR r wc rw rw rw r rw 31 : cnt+13 RESERVED cnt+12 : 12 SEC. Single error counter. This field increments each time a single error is detected. It saturates at the maximum value that can be stored in this field. Each bit can be reset by writing a one to it. cnt = the number of counter bits. 11 WB: Write bypass. If set, the TCB field will be used as checkbits in all write operations. 10 RB: Read bypass. If set, checkbits read from memory in all read operations will be stored in the TCB field. 9 SEN: SRAM EDAC enable. If set, EDAC will be active for the SRAM area. 8 RESERVED 7:0 TCB: Used as checkbits in write operations when WB is one and checkbits from read operations are stored here when RB is one. All the fields in the MCFG3 register are available if the edacen VHDL generic is set to one except for the SEC field which also requires that the errcnt VHDL generic is set to one. GRIP, Apr 2018, Version 2018.1 321 www.cobham.com/gaisler GRLIB IP Core 30.6 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x056. For description of vendor and device identifiers see the GRLIB IP Library User’s Manual. 30.7 Implementation 30.7.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. The registers driving external chip select, output enable and output enables for the data bus have asynchronous reset. 30.8 Configuration options Table 330 shows the configuration options of the core (VHDL generics). Table 334. Controller configuration options 30.9 Generic Function Allowed range Default hindex AHB slave index. 1 - NAHBSLV-1 0 ramaddr ADDR field of the AHB BAR1 defining RAM address space. Default RAM area is 0x40000000-0x40FFFFFF. 0 - 16#FFF# 16#400# rammask MASK field of the AHB BAR1 defining RAM address space. 0 -16#FFF# 16#FF0# ioaddr ADDR field of the AHB BAR2 defining IO address space. Default RAM area is 0x20000000-0x20FFFFFF. 0 - 16#FFF# 16#200# iomask MASK field of the AHB BAR2 defining IO address space. 0 - 16#FFF# 16#FF0# ramws Number of waitstates during access to SRAM area. 0 - 15 0 iows Number of waitstates during access to IO area. 0 - 15 2 srbanks Set the number of RAM banks. 1-8 1 banksz Set the size of bank 1 - 4. 1 = 16 kB, ... , 15 = 256 MB. If set to zero, the bank size is set with the rambsz field in the MCFG2 register. 0 - 15 15 pindex APB slave index. 1 - NAPBSLV-1 0 paddr APB address. 1 - 16#FFF# 0 pmask APB address mask. 1 - 16#FFF# 16#FFF# edacen EDAC enable. If set to one, EDAC logic is synthesized. 0-1 0 errcnt If one, a single error counter is added. 0-1 0 cntbits Number of bits in the single error counter. 1-8 1 wsreg Enable programmable waitstate generation. 0-1 0 Signal descriptions Table 335 shows the interface signals of the core (VHDL ports). Table 335.Signal descriptions Signal name Field Type Function Active CLK N/A Input Clock - RST N/A Input Reset Low GRIP, Apr 2018, Version 2018.1 322 www.cobham.com/gaisler GRLIB IP Core Table 335.Signal descriptions Signal name Field Type Function Active SRI DATA[31:0] Input Memory data: High [15:0] used for IO accesses [7:0] used for checkbits for SRAM accesses [15:8] use for data for SRAM accesses SRO BRDYN Input Bus ready strobe Low BEXCN Input Bus exception Low WRN[3:0] Input Not used - BWIDTH[1:0] Input Not used - SD[31:0] Input Not used - CB[7:0] Input Not used - PROMDATA[31:0] Input Not used - EDAC Input Not used - ADDRESS[31:0] Output Memory address High DATA[31:0] Output Memory data: High [15:0] used for IO accesses [7:0] used for checkbits for SRAM accesses [15:8] use for data for SRAM accesses RAMSN[7:0] Output SRAM chip-select Low RAMOEN[7:0] Output SRAM output enable Low IOSN Output IO area chip select Low ROMSN[7:0] Output Not used Low OEN Output Output enable Low WRITEN Output Write strobe Low WRN[3:0] Output SRAM write enable: Low WRN[0] corresponds to DATA[15:8], WRN[1] corresponds to DATA[7:0], WRN[3:2] Not used BDRIVE[3:0] Output Drive byte lanes on external memory bus. Controls I/O-pads connected to external memory bus: Low BDRIVE[0] corresponds to DATA[15:8], BDRIVE[1] corresponds to DATA[7:0], BDRIVE[3:2] Not used VBDRIVE[31:0] Output Vectored I/O-pad drive signal. Low READ Output Read strobe High RAMN Output Common SRAM Chip Select. Always asserted when one of the 8 RAMSN signals is asserted. Low ROMN Output Not used - SA[14:0] Output Not used - CB[7:0] Output Not used - PSEL Output Not used - CE Output Single error detected. High AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - * see GRLIB IP Library User’s Manual GRIP, Apr 2018, Version 2018.1 323 www.cobham.com/gaisler GRLIB IP Core 30.10 Signal definitions and reset values The signals and their reset values are described in table 336. Table 336.Signal definitions and reset values Signal name Type Function Active Reset value address[25:0] Output Memory address High Undefined data[31:0] Input/Output Memory data High Tri-state cb[7:0] Input/Output Check bits High Tri-state ramsn[3:0] Output SRAM chip select Low Logical 1 ramoen[3:0] Output SRAM output enable Low Logical 1 rwen[3:0] Output, SRAM write enable: Low Logical 1 Low Logical 1 rwen[0] corresponds to data[15:8], rwen[1] corresponds to data[7:0], rwen[3:2] Not used ramben[3:0] Output SRAM bank enable: ramben[0] corresponds to data[15:8], ramben[1] corresponds to data[7:8], ramben[3:2] Not used oen Output Output enable Low Logical 1 writen Output Write strobe Low Logical 1 read Output Read strobe High Logical 1 iosn Output IO area chip select Low Logical 1 brdyn Input Bus ready. Extends accesses to the IO area. Low - bexcn Input Bus exception. Low - GRIP, Apr 2018, Version 2018.1 324 www.cobham.com/gaisler GRLIB IP Core 30.11 Timing The timing waveforms and timing parameters are shown in figure 109 and are defined in table 337. clk tFTSRCTRL0 address[] ramsn[], romsn[] iosn tFTSRCTRL1 tFTSRCTRL1 tFTSRCTRL2 tFTSRCTRL2 rwen[], writen tFTSRCTRL3, tFTSRCTRL4 data[], cb[] (output) tFTSRCTRL5 tFTSRCTRL3 clk address[] ramsn[], romsn[] iosn tFTSRCTRL6 ramoen[] ramben[], oen, read tFTSRCTRL6 tFTSRCTRL7 tFTSRCTRL8 data[], cb[] (input) tFTSRCTRL10 tFTSRCTRL9 brdyn, bexcn Figure 109. Timing waveforms Table 337.Timing parameters Name Parameter Reference edge Min Max Unit tFTSRCTRL0 address clock to output delay rising clk edge TBD TBD ns tFTSRCTRL1 clock to output delay rising clk edge TBD TBD ns tFTSRCTRL2 clock to output delay rising clk edge TBD TBD ns tFTSRCTRL3 clock to data output delay falling clk edge TBD TBD ns tFTSRCTRL4 clock to data non-tri-state delay rising clk edge TBD TBD ns tFTSRCTRL5 clock to data tri-state delay rising clk edge TBD TBD ns tFTSRCTRL6 clock to output delay rising clk edge TBD TBD ns tFTSRCTRL7 data input to clock setup rising clk edge TBD - ns tFTSRCTRL8 data input from clock hold rising clk edge TBD - ns tFTSRCTRL9 input to clock setup rising clk edge TBD - ns tFTSRCTRL10 input from clock hold rising clk edge TBD - ns GRIP, Apr 2018, Version 2018.1 325 www.cobham.com/gaisler GRLIB IP Core 30.12 Library dependencies Table 338 shows libraries used when instantiating the core (VHDL libraries). Table 338.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals, component Memory bus signals definitions, component declaration 30.13 Component declaration The core has the following component declaration. component ftsrctrl8 is generic ( hindex : integer := 0; ramaddr : integer := 16#400#; rammask : integer := 16#ff0#; ioaddr : integer := 16#200#; iomask : integer := 16#ff0#; ramws : integer := 0; iows : integer := 2; srbanks : integer range 1 to 8 := 1; banksz : integer range 0 to 15 := 15; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; edacen : integer range 0 to 1 := 1; errcnt : integer range 0 to 1 := 0; cntbits : integer range 1 to 8 := 1; wsreg : integer := 0; oepol : integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; sri : in memory_in_type; sro : out memory_out_type ); end component; 30.14 Instantiation This example shows how the core can be instantiated. The example design contains an AMBA bus with a number of AHB components connected to it including the memory controller. The external memory bus is defined in the example design’s port map and connected to the memory controller. The system clock and reset are generated by GR Clock Generator and Reset Generator. The CE signal of the memory controller is also connected to the AHB status register. The memory controller decodes default memory areas: I/O area is 0x20000000 - 0x20FFFFFF and RAM area is 0x40000000 - 0x40FFFFF. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library techmap; use techmap.gencomp.all; library gaisler; GRIP, Apr 2018, Version 2018.1 326 www.cobham.com/gaisler GRLIB IP Core use gaisler.memctrl.all; use gaisler.misc.all; entity ftsrctrl8_ex is port ( resetn : in std_ulogic; clk : in std_ulogic; address data ramsn ramoen rwen oen writen read iosn brdyn bexcn ); end; : : : : : : : : : : : out std_logic_vector(27 downto 0); inout std_logic_vector(31 downto 0); out std_logic_vector (3 downto 0); out std_logic_vector (3 downto 0); out std_logic_vector (3 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_ulogic; in std_ulogic; -- Bus ready in std_ulogic -- Bus exception architecture rtl of ftsrctrl8_ex is signal memi : memory_in_type; signal memo : memory_out_type; signal signal signal signal signal signal apbi apbo ahbsi ahbso ahbmi ahbmo : : : : : : apb_slv_in_type; apb_slv_out_vector := (others => apb_none); ahb_slv_in_type; ahb_slv_out_vector := (others => ahbs_none); ahb_mst_in_type; ahb_mst_out_vector := (others => ahbm_none); signal clkm, rstn, rstraw : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal stati : ahbstat_in_type; begin -- clock and reset cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref clk_pad : clkpad port map (clk, clkm); rst0 : rstgen -- reset generator port map (resetn, clkm, ’1’, rstn, rstraw); <= ’0’; -- AHB controller ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (rrobin => 1, ioaddr => 16#fff#, devid => 16#201#) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); -- Memory controller sr0 : ftsrctrl8 generic map (hindex => 0, pindex => 0, edacen => 1) port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo); brdyn_pad : inpad port map (brdyn, memi.brdyn); bexcn_pad : inpad port map (bexcn, memi.bexcn); addr_pad : port map rams_pad : port map oen_pad : port map rwen_pad : port map roen_pad : port map wri_pad : port map outpadv generic map (width => 28 ) (address, memo.address(27 downto 0)); outpadv generic map (width => 4) (ramsn, memo.ramsn(3 downto 0)); outpad (oen, memo.oen); outpadv generic map (width => 4) (rwen, memo.wrn); outpadv generic map (width => 4) (ramoen, memo.ramoen(3 downto 0)); outpad (writen, memo.writen); GRIP, Apr 2018, Version 2018.1 327 www.cobham.com/gaisler GRLIB IP Core read_pad : outpad port map (read, memo.read); iosn_pad : outpad port map (iosn, memo.iosn); data_pad : iopadvv generic map (width => 8) -- SRAM and I/O Data port map (data(15 downto 8), memo.data(15 downto 8), memo.vbdrive(15 downto 8), memi.data(15 downto 8)); cbdata_pad : iopadvv generic map (width => 8) -- SRAM checkbits and I/O Data port map (data(7 downto 0), memo.data(7 downto 0), memo.vbdrive(7 downto 0), memi.data(7 downto 0)); -- APB bridge and AHB stat apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => 16#800#) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); stati.cerror(0) <= memo.ce; ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1) port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15)); end; GRIP, Apr 2018, Version 2018.1 328 www.cobham.com/gaisler GRLIB IP Core 31 GPTIMER - General Purpose Timer Unit 31.1 Overview The General Purpose Timer Unit provides a common prescaler and decrementing timer(s). The number of timers is configurable through the ntimers VHDL generic in the range 1 to 7. The prescaler width is configured through the sbits VHDL generic. Timer width is configured through the tbits VHDL generic. The timer unit acts a slave on AMBA APB bus. The unit is capable of asserting interrupts on timer underflow. The interrupt to use is configurable to be common for the whole unit or separate for each timer. timer 1 reload timer 2 reload prescaler reload timer n reload prescaler value timer 1 value pirq timer 2 value pirq+1 timer n value pirqn+(n-1) -1 tick -1 Figure 110. General Purpose Timer Unit block diagram 31.2 Operation The prescaler is clocked by the system clock and decremented on each clock cycle when at least one timer is enabled. When the prescaler underflows, it is reloaded from the prescaler reload register and a timer tick is generated. The operation of each timers is controlled through its control register. A timer is enabled by setting the enable bit in the control register. The timer value is then decremented on each prescaler tick. When a timer underflows, it will automatically be reloaded with the value of the corresponding timer reload register if the restart bit in the control register is set, otherwise it will stop at -1 and reset the enable bit. The timer unit can be configured to generate common interrupt through a VHDL-generic. The shared interrupt will be signaled when any of the timers with interrupt enable bit underflows. The timer unit will signal an interrupt on appropriate line when a timer underflows (if the interrupt enable bit for the current timer is set), when configured to signal interrupt for each timer. The interrupt pending bit in the control register of the underflown timer will be set and remain set until cleared by writing ‘1’. To minimize complexity, timers share the same decrementer. This means that the minimum allowed prescaler division factor is ntimers+1 (reload register = ntimers) where ntimers is the number of implemented timers. By setting the chain bit in the control register timer n can be chained with preceding timer n-1. Timer n will be decremented each time when timer n-1 underflows. Each timer can be reloaded with the value in its reload register at any time by writing a ‘one’ to the load bit in the control register. The last timer acts as a watchdog, driving a watchdog output signal when expired, when the wdog VHDL generic is set to a time-out value larger than 0. The watchdog timer also implements a window functionality when the wdogwin VHDL generic is set to 1. This enables a decrementing counter which reloads each time the timer is reloaded. If the timer is reloaded and the window counter has not reached zero, this will also assert the watchdog output. GRIP, Apr 2018, Version 2018.1 329 www.cobham.com/gaisler GRLIB IP Core Each timer can be configured to latch its value to a dedicated register when an event is detected on the interrupt (functionality enabled via VHDL generic glatch). All timers can be forced to reload when an event is detected on the interrupt bus (functionality enabled via VHDL generic gset). A dedicated mask register is provided to filter the interrupts. At reset, all timers are disabled except the watchdog timer (if enabled by the generics). The prescaler value and reload registers are set to all ones, while the watchdog timer is set to the wdog VHDL generic. All other registers are uninitialized except for the WDOGDIS and WDOGNMI fields that are reset to ‘0’. 31.3 Registers The core is programmed through registers mapped into APB address space. The number of implemented registers depend on the number of implemented timers. Table 339.General Purpose Timer Unit registers APB address offset Register 0x00 Scaler value 0x04 Scaler reload value 0x08 Configuration register 0x0C Timer latch configuration register 0x10 Timer 1 counter value register 0x14 Timer 1 reload value register 0x18 Timer 1 control register 0x1C Timer 1 latch register 0xn0 Timer n counter value register 0xn4 Timer n reload value register 0xn8 Timer n control register 0xnC Timer n latch register 31.3.1 Scaler Value Register Table 340.0x00 - SCALER - Scaler value register 31 16 16-1: 0 16-1 0 RESERVED SCALER 0 all 1 r rw Scaler value. This value will also be set by writes to the Scaler reload value register. Any unused most significant bits are reserved. Always reads as ‘000...0’. 31.3.2 Scaler Reload Value Register Table 341.0x04 - SRELOAD - Scaler reload value register 31 16 16-1: 0 16-1 0 RESERVED SCALER RELOAD VALUE 0 all 1 r rw Scaler reload value. Writes to this register also set the scaler value. Any unused most significant bits are reserved. Always read as ‘000...0’. GRIP, Apr 2018, Version 2018.1 330 www.cobham.com/gaisler GRLIB IP Core 31.3.3 Configuration Register Table 342.0x08 - CONFIG - Configuration register 31 23 22 “000..0” 16 15 14 13 12 11 10 9 TIMEREN 00 0 0 0 0 0 r rw r rw rw rw rw rw 8 7 EV ES EL EE DF SI 0 0 0 3 2 0 IRQ TIMERS * * * r r r 31: 23 Reserved. Always reads as ‘000...0’. 22: 16 Enable bits for each timer. Writing ‘1’ to one of this bits sets the enable bit in the corresponding timers control register. Writing ‘0’ has no effect to the timers. bit[16] corresponds to timer0, bit[17] to timer 1,... 15: 14 Reserved 13 External Events (EV). If set then the latch events are taken from the secondary input. If this field is zero then the source of the latch events is the interrupt bus. 12 Enable set (ES). If set, on the next matching interrupt, the timers will be loaded with the corresponding timer reload values. The bit is then automatically cleared, not to reload the timer values until set again. 11 Enable latching (EL). If set, on the next matching interrupt, the latches will be loaded with the corresponding timer values. The bit is then automatically cleared, not to load a timer value until set again. 10 Enable external clock source (EE). If set the prescaler is clocked from the external clock source. 9 Disable timer freeze (DF). If set the timer unit can not be freezed, otherwise signal GPTI.DHALT freezes the timer unit. 8 Separate interrupts (SI). Reads ‘1’ if the timer unit generates separate interrupts for each timer, otherwise ‘0’. Read-only. 7: 3 APB Interrupt: If configured to use common interrupt all timers will drive APB interrupt nr. IRQ, otherwise timer n will drive APB Interrupt IRQ+n (has to be less the MAXIRQ). Read-only. 2: 0 Number of implemented timers. Read-only. 31.3.4 Timer Latch Configuration Register Table 343.0x0C - CATCHCFG - Timer latch configuration register 31 0 LATCHSEL 0 rw 31: 0 Specifies what bits of the interrupt bus, or external latch vector, bus that shall cause the Timer Latch Registers to latch the timer values. If the configuration register EV field is zero then latching is done based on events on the interrupt bus. If the EV field is ‘1’ then the external latch vecor is used. 31.3.5 Timer N Counter Value Register Table 344.0xn0, when n selects the times - TCNTVALn - Timer n counter value register 32-1 0 TCVAL 0 rw 32-1: 0 Timer Counter value. Decremented by 1 for each prescaler tick. Any unused most significant bits are reserved. Always reads as ‘000...0’. GRIP, Apr 2018, Version 2018.1 331 www.cobham.com/gaisler GRLIB IP Core 31.3.6 Timer N Reload Value Register Table 345.0xn4, when n selects the times - TRLDVALn - Timer n reload value register 32-1 0 TRCDUAL * rw 32-1: 0 Timer Reload value. This value is loaded into the timer counter value register when ‘1’ is written to load bit in the timers control register or when the RS bit is set in the control register and the timer underflows. Any unused most significant bits are reserved. Always reads as ‘000...0’. 31.3.7 Timer N Control Register Table 346.0xn8, when n selects the times - TCTRLn - Timer n control register 31 16 15 9 8 7 6 5 4 WS WN DH CH IP 3 2 1 0 WDOGWINC RESERVED 0 0 0 0 0 0 rw r rw rw r rw wc rw rw rw rw 0 IE LD RS EN * 0 * * 31: 16 Reload value for the watchdog window counter. The window counter is reloaded with this value each time the watchdog counter is reloaded. This functionality is only available when the core has been implemented with VHDL generic wdog /= 0, wdogwin /= 0 and only for the last timer 15: 9 Reserved. Always reads as ‘000...0’. 8 Disable Watchdog Output (WS/WDOGDIS): If this field is set to ‘1’ then the GPTO.WDOG and GPTO.WDOGN outputs are disabled (fixed to ‘0’ and ‘1’ respectively). This functionality is only available when the core has been implemented with VHDL generic wdog /= 0 and only for the last timer. If wdog = 0 then this register is read-only and always ‘0’. 7 Enable Watchdog NMI (WN/WDOGNMI): If this field is set to ‘1’ then the watchdog timer will also generate a non-maskable interrupt (interrupt 15) when an interrupt is signalled. This functionality is only available when the core has been implemented with VHDL generic wdog /= 0 and only for the last timer. If wdog = 0 then this register is read-only and always ‘0’. 6 Debug Halt (DH): Value of GPTI.DHALT signal which is used to freeze counters (e.g. when a system is in debug mode). Read-only. 5 Chain (CH): Chain with preceding timer. If set for timer n, timer n will be decremented each time when timer (n-1) underflows. 4 Interrupt Pending (IP): The core sets this bit to ‘1’ when an interrupt is signalled. This bit remains ‘1’ until cleared by writing ‘1’ to this bit, writes of ‘0’ have no effect. 3 Interrupt Enable (IE): If set the timer signals interrupt when it underflows. The reset value for this bit is ‘0’ unless watchdog functionality has been enabled. If watchdog functionality has been enabled then this bit for the last timer will have reset value ‘1’. 2 Load (LD): Load value from the timer reload register to the timer counter value register. This bit is automatically cleared when the value has been loaded. 1 Restart (RS): If set, the timer counter value register is reloaded with the value of the reload register when the timer underflows 0 Enable (EN): Enable the timer. 31.3.8 Timer N Latch Register Table 347.0xnC, when n selects the times - TLATCHn - Timer n latch register 31 0 LTCV 0 r 31: 0 Latched timer counter value (LTCV): Valued latched from corresponding timer. Read-only. GRIP, Apr 2018, Version 2018.1 332 www.cobham.com/gaisler GRLIB IP Core 31.4 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x011. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 31.5 Implementation 31.5.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support grlib_async_reset_enable. All registers that react on the reset signal will have a synchronous reset. GRIP, Apr 2018, Version 2018.1 333 www.cobham.com/gaisler GRLIB IP Core 31.6 Configuration options Table 348 shows the configuration options of the core (VHDL generics). Table 348.Configuration options Generic Function Allowed range Default pindex Selects which APB select signal (PSEL) will be used to access the timer unit 0 to NAPBSLV-1 0 paddr The 12-bit MSB APB address 0 to 4095 0 pmask The APB address mask 0 to 4095 4095 nbits Defines the number of bits in the timers 1 to 32 32 ntimers Defines the number of timers in the unit 1 to 7 1 pirq Defines which APB interrupt the timers will generate 0 to NAHBIRQ-1 0 sepirq If set to 1, each timer will drive an individual interrupt line, starting with interrupt pirq. If set to 0, all timers will drive the same interrupt line (pirq). 0 to 1 0 (note: ntimers + pirq must be less than or equal to NAHBIRQ if sepirq is set to 1) sbits Defines the number of bits in the scaler wdog Watchdog reset value. When set to a non-zero value, the 0 to 2nbits - 1 last timer will be enabled and pre-loaded with this value at reset. When the timer value reaches 0, the WDOG output is driven active. 0 ewdogen External watchdog enable. When set to a non-zero value, the enable bit of the watchdog timer will be set during core reset via the signal gpti.wdogen.Otherwise the enable bit will be set to ‘1’ during core reset. 0-1 0 glatch Enable external timer latch (via interrupt or external vec- 0 - 1 tor) 0 gextclk Enable external timer clock input 0-1 0 gset Enable external timer reload (via interrupt or external vector) 0-1 0 Enable support for external latch events 0-2 0 0-1 0 gelatch 1 to 32 16 0: Timer latch/set is only support for interrupt bus (if enabled via glatch and gset generics) 1: Timer latch/set is disabled after an, unmasked, event on GPTI.LATCHV 2: Timer latch/set is performed on an, unmasked, event on GPTI.LATCHV and timer latch/set is disabled on GPTI.LATCHD events. wdogwin Enables the watchdog window counter. GRIP, Apr 2018, Version 2018.1 334 www.cobham.com/gaisler GRLIB IP Core 31.7 Signal descriptions Table 349 shows the interface signals of the core (VHDL ports). Table 349.Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - APBI * Input APB slave input signals - APBO * Output APB slave output signals - GPTI DHALT Input Freeze timers High EXTCLK Input Use as alternative clock - WDOGEN Input Sets enable bit of the watchdog timer if VHDL generics wdog and ewdogen are set to non-zero values. - LATCHV[31:0] Input External latch/set vector, used if VHDLgeneric gelatch /=0 High LATCHD[31:0] Input External latch/set disable vector, used if VHDL generic gelatch = 2. High TICK[0:7] Output Timer ticks. TICK[0] is high for one clock each time the scaler underflows. TICK[1-n] are high for one clock each time the corresponding timer underflows. High WDOG Output Watchdog output. Equivalent to interrupt pending bit of last timer. High WDOGN Output Watchdog output. Equivalent to interrupt pending bit of last timer. Low GPTO * see GRLIB IP Library User’s Manual 31.8 Signal definitions and reset values When the watchdog times out, the wdogn output is driven active low, else it is in tri-state and therefore requires an external pull-up. The signals and their reset values are described in table 350. Table 350.Signal definitions and reset values Signal name Type Function Active Reset value wdogn Tri-state output Watchdog output. Equivalent to interrupt pending bit of last timer. Low Tri-state GRIP, Apr 2018, Version 2018.1 335 www.cobham.com/gaisler GRLIB IP Core 31.9 Timing The timing waveforms and timing parameters are shown in figure 111 and are defined in table 351. clk tGPTIMER0 wdogn tGPTIMER1 Figure 111. Timing waveforms Table 351.Timing parameters Name Parameter Reference edge Min Max Unit tGPTIMER0 clock to output delay rising clk edge TBD TBD ns tGPTIMER1 clock to output tri-state rising clk edge TBD TBD ns 31.10 Library dependencies Table 352 shows libraries used when instantiating the core (VHDL libraries). Table 352.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Signals, component Component declaration 31.11 Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library gaisler; use gaisler.misc.all; entity gptimer_ex is port ( clk : in std_ulogic; rstn : in std_ulogic; ... -- other signals ); end; architecture rtl of gptimer_ex is -- AMBA signals signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); -- GP Timer Unit input signals signal gpti : gptimer_in_type; begin GRIP, Apr 2018, Version 2018.1 336 www.cobham.com/gaisler GRLIB IP Core -- AMBA Components are instantiated here ... -- General Purpose Timer Unit timer0 : gptimer generic map (pindex => 3, paddr => 3, pirq => 8, sepirq => 1) port map (rstn, clk, apbi, apbo(3), gpti, open); gpti.dhalt <= ’0’; gpti.extclk <= ’0’; -- unused inputs end; GRIP, Apr 2018, Version 2018.1 337 www.cobham.com/gaisler GRLIB IP Core 32 GR1553B - MIL-STD-1553B / AS15531 Interface 32.1 Overview This interface core connects the AMBA AHB/APB bus to a single- or dual redundant MIL-STD1553B bus, and can act as either Bus Controller, Remote Terminal or Bus Monitor. MIL-STD-1553B (and derived standard SAE AS15531) is a bus standard for transferring data between up to 32 devices over a shared (typically dual-redundant) differential wire. The bus is designed for predictable real-time behavior and fault-tolerance. The raw bus data rate is fixed at 1 Mbit/s, giving a maximum of around 770 kbit/s payload data rate. One of the terminals on the bus is the Bus Controller (BC), which controls all traffic on the bus. The other terminals are Remote Terminals (RTs), which act on commands issued by the bus controller. Each RT is assigned a unique address between 0-30. In addition, the bus may have passive Bus Monitors (BM:s) connected. There are 5 possible data transfer types on the MIL-STD-1553 bus: • BC-to-RT transfer (“receive”) • RT-to-BC transfer (“transmit”) • RT-to-RT transfer • Broadcast BC-to-RTs • Broadcast RT-to-RTs Each transfer can contain 1-32 data words of 16 bits each. The bus controller can also send “mode codes” to the RTs to perform administrative tasks such as time synchronization, and reading out terminal status. 32.2 Electrical interface The core is connected to the MIL-STD-1553B bus wire through single or dual transceivers, isolation transformers and transformer or stub couplers as shown in figure 112. If single-redundancy is used, the unused bus receive P/N signals should be tied both-high or both-low. The transmitter enables are typically inverted and therefore called transmitter inibit (txinh). See the standard and the respective component’s data sheets for more information on the electrical connection. Bus A txinhA txA_P txA_N rxA_P rxA_N rxenA GR1553B Bus B txinhB txB_P txB_N rxB_P rxB_N rxenB Terminal boundary Figure 112. Interface between core and MIL-STD-1553B bus (dual-redundant, transformer coupled) GRIP, Apr 2018, Version 2018.1 338 www.cobham.com/gaisler GRLIB IP Core 32.3 Operation 32.3.1 Operating modes The core contains three separate control units for the Bus Controller, Remote Terminal and Bus Monitor handling, with a shared 1553 codec. All parts may not be present in the hardware, which parts are available can be checked from software by looking at the BCSUP/RTSUP/BMSUP register bits. The operating mode of the core is controlled by starting and stopping of the BC/RT/BM units via register writes. At start-up, none of the parts are enabled, and the core is completely passive on both the 1553 and AMBA bus. The BC and RT parts of the core can not be active on the 1553 bus at the same time. While the BC is running or suspended, only the BC (and possibly BM) has access to the 1553 bus, and the RT can only receive and respond to commands when both the BC schedules are completely stopped (not running or even suspended). The Bus Monitor, however, is only listening on the codec receivers and can therefore operate regardless of the enabled/disabled state of the other two parts. 32.3.2 Register interface The core is configured and controlled through control registers accessed over the APB bus. Each of the BC,RT,BM parts has a separate set of registers, plus there is a small set of shared registers. Some of the control register fields for the BC and RT are protected using a ‘key’, a field in the same register that has to be written with a certain value for the write to take effect. The purpose of the keys are to give RT/BM designers a way to ensure that the software can not interfere with the bus traffic by enabling the BC or changing the RT address. If the software is built without knowledge of the key to a certain register, it is very unlikely that it will accidentally perform a write with the correct key to that control register. 32.3.3 Interrupting The core has one interrupt output, which can be generated from several different source events. Which events should cause an interrupt can be controlled through the IRQ Enable Mask register. 32.3.4 MIL-STD-1553 Codec The core’s internal codec receives and transmits data words on the 1553 bus, and generates and checks sync patterns and parity. Loop-back checking logic checks that each transmitted word is also seen on the receive inputs. If the transmitted word is not echoed back, the transmitter stops and signals an error condition, which is then reported back to the user. GRIP, Apr 2018, Version 2018.1 339 www.cobham.com/gaisler GRLIB IP Core 32.4 Bus Controller Operation 32.4.1 Overview When operating as Bus Controller, the core acts as master on the MIL-STD-1553 bus, initiates and performs transfers. This mode works based on a scheduled transfer list concept. The software sets up in memory a sequence of transfer descriptors and branches, data buffers for sent and received data, and an IRQ pointer ring buffer. When the schedule is started (through a BC action register write), the core processes the list, performs the transfers one after another and writes resulting status into the transfer list and incoming data into the corresponding buffers. 32.4.2 Timing control In each transfer descriptor in the schedule is a “slot time” field. If the scheduled transfer finishes sooner than its slot time, the core will pause the remaining time before scheduling the next command. This allows the user to accurately control the message timing during a communication frame. If the transfer uses more than its slot time, the overshooting time will be subtracted from the following command’s time slot. The following command may in turn borrow time from the following command and so on. The core can keep track of up to one second of borrowed time, and will not insert pauses again until the balance is positive, except for intermessage gaps and pauses that the standard requires. If you wish to execute the schedule as fast as possible you can set all slot times in the schedule to zero. If you want to group a number of transfers you can move all the slot time to the last transfer. The schedule can be stopped or suspended by writing into the BC action register. When suspended, the schedule’s time will still be accounted, so that the schedule timing will still be correct when the schedule is resumed. When stopped, on the other hand, the schedule’s timers will be reset. When the extsync bit is set in the schedule’s next transfer descriptor, the core will wait for a positive edge on the external sync input before starting the command. The schedule timer and the time slot balance will then be reset and the command is started. If the sync pulse arrives before the transfer is reached, it is stored so the command will begin immediately. The trigger memory is cleared when stopping (but not when suspending) the schedule. Also, the trigger can be set/cleared by software through the BC action register. 32.4.3 Bus selection Each transfer descriptor has a bus selection bit that allows you to control on which one of the two redundant buses (‘0’ for bus A, ‘1’ for bus B) the transfer will occur. Another way to control the bus usage is through the per-RT bus swap register, which has one register bit for each RT address. The bus swap register is an optional feature, software can check the BCFEAT read-only register field to see if it is available. Writing a ‘1’ to a bit in the per-RT Bus Swap register inverts the meaning of the bus selection bit for all transfers to the corresponding RT, so ‘0’ now means bus ‘B’ and ‘1’ means bus ‘A’. This allows you to switch all transfers to one or a set of RT:s over to the other bus with a single register write and without having to modify any descriptors. The hardware determines which bus to use by taking the exclusive-or of the bus swap register bit and the bus selection bit. Normally it only makes sense to use one of these two methods for each RT, either the bus selection bit is always zero and the swap register is used, or the swap register bit is always zero and the bus selection bit is used. If the bus swap register is used for bus selection, the store-bus descriptor bit can be enabled to automatically update the register depending on transfer outcome. If the transfer succeeded on bus A, the bus swap register bit is set to ‘0’, if it succeeds on bus B, the swap register bit is set to ‘1’. If the transfer fails, the bus swap register is set to the opposite value. GRIP, Apr 2018, Version 2018.1 340 www.cobham.com/gaisler GRLIB IP Core 32.4.4 Secondary transfer list The core can be set up with a secondary “asynchronous” transfer list with the same format as the ordinary schedule. This transfer list can be commanded to start at any time during the ordinary schedule. While the core is waiting for a scheduled command’s slot time to finish, it will check if the next asynchronous transfer’s slot time is lower than the remaining sleep time. In that case, the asynchronous command will be scheduled. If the asynchronous command doesn’t finish in time, time will be borrowed from the next command in the ordinary schedule. In order to not disturb the ordinary schedule, the slot time for the asynchronous messages must therefore be set to pessimistic values. The exclusive bit in the transfer descriptor can be set if one does not want an asynchronous command scheduled during the sleep time following the transfer. Asynchronous messages will not be scheduled while the schedule is waiting for a sync pulse or the schedule is suspended and the current slot time has expired, since it is then not known when the next scheduled command will start. 32.4.5 Interrupt generation Each command in the transfer schedule can be set to generate an interrupt after certain transfers have completed, with or without error. Invalid command descriptors always generate interrupts and stop the schedule. Before a transfer-triggered interrupt is generated, the address to the corresponding descriptor is written into the BC transfer-triggered IRQ ring buffer and the BC Transfer-triggered IRQ Ring Position Register is incremented. A separate error interrupt signals DMA errors. If a DMA error occurs when reading/writing descriptors, the executing schedule will be suspended. DMA errors in data buffers will cause the corresponding transfer to fail with an error code (see table 356). Whether any of these interrupt events actually cause an interrupt request on the AMBA bus is controlled by the IRQ Mask Register setting. 32.4.6 Transfer list format The BC:s transfer list is an array of transfer descriptors mixed with branches as shown in table 353. Each entry has to be aligned to start on a 128-bit (16-byte) boundary. The two unused words in the branch case are free to be used by software to store arbitrary data. Table 353.GR1553B transfer descriptor format Offset Value for transfer descriptor DMA R/W Value for branch 0x00 Transfer descriptor word 0 (see table 354) R Condition word (see table 358) R DMA R/W 0x04 Transfer descriptor word 1 (see table 355) R Jump address, 128-bit aligned R 0x08 Data buffer pointer, 16-bit aligned. R Unused - W Unused - For write buffers, if bit 0 is set the received data is discarded and the pointer is ignored. This can be used for RT-to-RT transfers where the BC is not interested in the data transferred. 0x0C Result word, written by core (see table 356) GRIP, Apr 2018, Version 2018.1 341 www.cobham.com/gaisler GRLIB IP Core The transfer descriptor words are structured as shown in tables 354-356 below. Table 354.GR1553B BC transfer descriptor word 0 (offset 0x00) 31 30 29 28 27 26 25 0 WTRIG EXCL IRQE IRQN SUSE SUSN 31 24 23 22 RETMD 20 NRET 19 18 STBUS GAP 17 16 RESERVED 15 0 STIME Must be 0 to identify as descriptor 30 Wait for external trigger (WTRIG) 29 Exclusive time slot (EXCL) - Do not schedule asynchronous messages 28 IRQ after transfer on Error (IRQE) 27 IRQ normally (IRQN) - Always interrupts after transfer 26 Suspend on Error (SUSE) - Suspends the schedule (or stops the async transfer list) on error 25 Suspend normally (SUSN) - Always suspends after transfer 24 : 23 Retry mode (RETMD). 00 - Retry on same bus only. 01 - Retry alternating on both buses 10: Retry first on same bus, then on alternating bus. 11 - Reserved, do not use 22 : 20 Number of retries (NRET) - Number of automatic retries per bus The total number of tries (including the first attempt) is NRET+1 for RETMD=00, 2 x (NRET+1) for RETMD=01/ 10 19 Store bus (STBUS) - If the transfer succeeds and this bit is set, store the bus on which the transfer succeeded (0 for bus A, 1 for bus B) into the per-RT bus swap register. If the transfer fails and this bit is set, store the opposite bus instead. (only if the per-RT bus mask is supported in the core) See section 32.4.3 for more information. 18 Extended intermessage gap (GAP) - If set, adds an additional amount of gap time, corresponding to the RTTO field, after the transfer 17 : 16 Reserved - Set to 0 for forward compatibility 15 : 0 Slot time (STIME) - Allocated time in 4 microsecond units, remaining time after transfer will insert delay Table 355.GR1553B BC transfer descriptor word 1 (offset 0x04) 31 30 DUM BUS 31 30 29 26 RTTO 25 21 RTAD2 20 16 RTSA2 15 11 RTAD1 10 TR 9 5 RTSA1 4 0 WCMC Dummy transfer (DUM) - If set to ‘1’ no bus traffic is generated and transfer “succeeds” immediately For dummy transfers, the EXCL,IRQN,SUSN,STBUS,GAP,STIME settings are still in effect, other bits and the data buffer pointer are ignored. Bus selection (BUS) - Bus to use for transfer, 0 - Bus A, 1 - Bus B 29:26 RT Timeout (RTTO) - Extra RT status word timeout above nominal in units of 4 us (0000 -14 us, 1111 -74 us). Note: This extra time is also used as extra intermessage gap time if the GAP bit is set. 25:21 Second RT Address for RT-to-RT transfer (RTAD2) 20:16 Second RT Subaddress for RT-to-RT transfer (RTSA2) 15:11 RT Address (RTAD1) 10 Transmit/receive (TR) 9:5 RT Subaddress (RTSA1) 4:0 Word count/Mode code (WCMC) GRIP, Apr 2018, Version 2018.1 See table 357 for details on how to setup RTAD1,RTSA1,RTAD2,RTSA2,WCMC,TR for different transfer types. Note that bits 15:0 correspond to the (first) command word on the 1553 bus 342 www.cobham.com/gaisler GRLIB IP Core Table 356.GR1553B transfer descriptor result word (offset 0x0C) 31 0 30 24 23 Reserved 16 15 8 RT2ST 31 RTST 7 4 RETCNT 3 2 RES 0 TFRST Always written as 0 30:24 Reserved - Mask away on read for forward compatibility 23:16 RT 2 Status Bits (RT2ST) - Status bits from receiving RT in RT-to-RT transfer, otherwise 0 Same bit pattern as for RTST below 15:8 RT Status Bits (RTST) - Status bits from RT (transmitting RT in RT-to-RT transfer) 15 - Message error, 14 - Instrumentation bit or reserved bit set, 13 - Service request,  12 - Broadcast command received, 11 - Busy bit, 10 - Subsystem flag, 9 - Dynamic bus control acceptance, 8 - Terminal flag 7:4 Retry count (RETCNT) - Number of retries performed 3 Reserved - Mask away on read for forward compatibility 2:0 Transfer status (TFRST) - Outcome of last try 000 - Success (or dummy bit was set) 001 - RT did not respond (transmitting RT in RT-to-RT transfer) 010 - Receiving RT of RT-to-RT transfer did not respond 011 - A responding RT:s status word had message error, busy, instrumentation or reserved bit set (*) 100 - Protocol error (improperly timed data words, decoder error, wrong number of data words) 101 - The transfer descriptor was invalid 110 - Data buffer DMA timeout or error response 111 - Transfer aborted due to loop back check failure * Error code 011 is issued only when the number of data words match the success case, otherwise code 100 is used. Error code 011 can be issued for a correctly executed “transmit last command” or “transmit last status word” mode code since these commands do not reset the status word. Table 357.GR1553B BC Transfer configuration bits for different transfer types RTAD1 (15:11) RTSA1 (9:5) RTAD2 (25:21) RTSA2 (20:16) WCMC (4:0) TR (10) Data buffer direction Data, BC-to-RT RT address (0-30) RT subaddr (1-30) Don’t care 0 Word count (0 for 32) 0 Read (2-64 bytes) Data, RT-to-BC RT address (0-30) RT subaddr (1-30) Don’t care 0 Word count (0 for 32) 1 Write (2-64 bytes) Data, RT-to-RT Recv-RT addr (0-30) Recv-RT subad. (1-30) Xmit-RT Xmit-RT Word count addr (0-30) subad. (1-30) (0 for 32) 0 Write  (2-64 bytes) Mode, no data RT address (0-30) 0 or 31 (*) Don’t care Don’t care Mode code (0-8) 1 Unused Mode, RT-to-BC RT address (0-30) 0 or 31 (*) Don’t care Don’t care Mode code (16/18/19) 1 Write  (2 bytes) Mode, BC-to-RT RT address (0-30) 0 or 31 (*) Don’t care Don’t care Mode code (17/20/21) 0 Read  (2 bytes) Broadcast Data, BC-to-RTs 31 RTs subaddr (1-30) Don’t care 0 Word count (0 for 32) 0 Read  (2-64 bytes) Broadcast Data, RT-to-RTs 31 Recv-RTs subad. (1-30) Xmit-RT Xmit-RT Word count addr (0-30) subad. (1-30) (0 for 32) 0 Write  (2-64 bytes) Broadcast  Mode, no data 31 0 or 31 (*) Don’t care Don’t care Mode code (1, 3-8) 1 Unused Broadcast 31 Mode, BC-to-RT 0 or 31 (*) Don’t care Don’t care Mode code (17/20/21) 0 Read  (2 bytes) Transfer type (*) The standard allows using either of subaddress 0 or 31 for mode commands. The branch condition word is formed as shown in table 358. GRIP, Apr 2018, Version 2018.1 343 www.cobham.com/gaisler GRLIB IP Core Table 358.GR1553B branch condition word (offset 0x00) 31 1 30 27 Reserved (0) 31 26 25 24 IRQC ACT MODE 23 16 RT2CC 15 8 RTCC 7 0 STCC Must be 1 to identify as branch 30 : 27 Reserved - Set to 0 26 Interrupt if condition met (IRQC) 25 Action (ACT) - What to do if condition is met, 0 - Suspend schedule, 1 - Jump 24 Logic mode (MODE): 0 = Or mode (any bit set in RT2CC, RTCC is set in RT2ST,RTST, or result is in STCC mask) 1 - And mode (all bits set in RT2CC,RTCC are set in RT2ST,RTST and result is in STCC mask) 23:16 RT 2 Condition Code (RT2CC) - Mask with bits corresponding to RT2ST in result word of last transfer 15:8 RT Condition Code (RTCC) - Mask with bits corresponding to RTST in result word of last transfer 7:0 Status Condition Code (STCC) - Mask with bits corresponding to status value of last transfer Note that you can get a constant true condition by setting MODE=0 and STCC=0xFF, and a constant false condition by setting STCC=0x00. 0x800000FF can thus be used as an end-of-list marker. GRIP, Apr 2018, Version 2018.1 344 www.cobham.com/gaisler GRLIB IP Core 32.5 Remote Terminal Operation 32.5.1 Overview When operating as Remote Terminal, the core acts as a slave on the MIL-STD-1553B bus. It listens for requests to its own RT address (or broadcast transfers), checks whether they are configured as legal and, if legal, performs the corresponding transfer or, if illegal, sets the message error flag in the status word. Legality is controlled by the subaddress control word for data transfers and by the mode code control register for mode codes. To start the RT, set up the subaddress table and log ring buffer, and then write the address and RT enable bit is into the RT Config Register. 32.5.2 Data transfer handling The Remote Terminal mode uses a three-level structure to handle data transfer DMA. The top level is a subaddress table, where each subaddress has a subaddress control word, and pointers to a transmit descriptor and a receive descriptor. Each descriptor in turn contains a descriptor control/status word, pointer to a data buffer, and a pointer to a next descriptor, forming a linked list or ring of descriptors. Data buffers can reside anywhere in memory with 16-bit alignment. When the RT receives a data transfer request, it checks in the subaddress table that the request is legal. If it is legal, the transfer is then performed with DMA to or from the corresponding data buffer. After a data transfer, the descriptor’s control/status word is updated with success or failure status and the subaddress table pointer is changed to point to the next descriptor. If logging is enabled, a log entry will be written into a log ring buffer area. A transfer-triggered IRQ may also be enabled. To identify which transfer caused the interrupt, the RT Event Log IRQ Position points to the corresponding log entry. For that reason, logging must be enabled in order to enable interrupts. If a request is legal but can not be fulfilled, either because there is no valid descriptor ready or because the data can not be accessed within the required response time, the core will signal a RT table access error interrupt and not respond to the request. Optionally, the terminal flag status bit can be automatically set on these error conditions. Descriptor ctrl/stat SA N-1 Transmit data Data buffer ptr. Next pointer SA ctrl word SA N Transmit descr. ptr Descriptor ctrl/stat Receive descr. ptr Data buffer ptr. Receive buffer Next pointer Descriptor ctrl/stat SA N+1 Data buffer ptr. Next pointer Receive buffer 0x3 Subaddress table Figure 113. RT subaddress data structure example diagram GRIP, Apr 2018, Version 2018.1 345 www.cobham.com/gaisler GRLIB IP Core 32.5.3 Mode Codes Which of the MIL-STD-1553B mode codes that are legal and should be logged and interrupted are controlled by the RT Mode Code Control register. As for data transfers, to enable interrupts you must also enable logging. Inhibit mode codes are controlled by the same fields as their non-inhibit counterpart and mode codes that can be broadcast have two separate fields to control the broadcast and nonbroadcast variants. The different mode codes and the corresponding action taken by the RT are tabulated below. Some mode codes do not have a built-in action, so they will need to be implemented in software if desired. The relation between each mode code to the fields in the RT Mode Code control register is also shown. Table 359.RT Mode Codes Can log/ IRQ Enabled after reset Ctrl. reg bits Mode code Description Built-in action, if mode code is enabled 0 00000 Dynamic bus control If the DBCA bit is set in the RT Bus Status register, a Dynamic Bus Control Acceptance response is sent. Yes No 17:16 1 00001 Synchronize The time field in the RT sync register is updated. Yes Yes 3:0 2 00010 Transmit status word No Yes - The output rtsync is pulsed high one AMBA cycle. Transmits the RT:s status word Enabled always, can not be logged or disabled. 3 00011 Initiate self test No built-in action Yes No 21:18 4 00100 Transmitter shutdown The RT will stop responding to commands on the other bus (not the bus on which this command was given). Yes Yes 11:8 5 00101 Override transmitter shutdown Removes the effect of an earlier transmitter shutdown mode code received on the same bus Yes Yes 11:8 6 00110 Inhibit terminal flag Masks the terminal flag of the sent RT status words Yes No 25:22 7 00111 Override inhibit terminal flag Removes the effect of an earlier inhibit terminal flag mode code. Yes No 25:22 8 01000 Reset remote terminal The fail-safe timers, transmitter shutdown and inhibit terminal flag inhibit status are reset. Yes No 29:26 The Terminal Flag and Service Request bits in the RT Bus Status register are cleared. The extreset output is pulsed high one AMBA cycle. 16 10000 Transmit vector word Responds with vector word from RT Status Words Register Yes No 13:12 17 10001 Synchronize with data word The time and data fields in the RT sync register are updated. The rtsync output is pulsed high one AMBA cycle Yes Yes 7:4 18 10010 Transmit last command Transmits the last command sent to the RT. No Yes - 19 10011 Transmit BIT word Responds with BIT word from RT Status Words Register Yes No 15:14 20 10100 Selected transmitter shutdown No built-in action No No - 21 10101 Override selected transmitter shutdown No built-in action No No - Enabled always, can not be logged or disabled. GRIP, Apr 2018, Version 2018.1 346 www.cobham.com/gaisler GRLIB IP Core 32.5.4 Event Log The event log is a ring of 32-bit entries, each entry having the format given in table 360. Note that for data transfers, bits 23-0 in the event log are identical to bits 23-0 in the descriptor status word. Table 360.GR1553B RT Event Log entry format 31 30 IRQSR 29 28 TYPE 24 23 10 SAMC 31 9 TIMEL 8 3 BC 2 SZ 0 TRES IRQ Source (IRQSRC) - Set to ‘1’ if this transfer caused an interrupt 30 : 29 Transfer type (TYPE) - 00 - Transmit data, 01 - Receive data, 10 - Mode code 28 : 24 Subaddress / Mode code (SAMC) - If TYPE=00/01 this is the transfer subaddress, If TYPE=10, this is the mode code 23 : 10 TIMEL - Low 14 bits of time tag counter. 9 Broadcast (BC) - Set to 1 if request was to the broadcast address 8:3 Transfer size (SZ) - Count in 16-bit words (0-32) 2:0 Transfer result (TRES) 000 = Success 001 = Superseded (canceled because a new command was given on the other bus) 010 = DMA error or memory timeout occurred 011 = Protocol error (improperly timed data words or decoder error) 100 = The busy bit or message error bit was set in the transmitted status word and no data was sent 101 = Transfer aborted due to loop back checker error 32.5.5 Subaddress table format Table 361.GR1553B RT Subaddress table entry for subaddress number N, 0 RXSZ as this might cause reading beyond buffer end 17 Ignore data valid bit (IGNDV) - If this is ‘1’ then receive transfers will proceed (and overwrite the buffer) if the receive descriptor has the data valid bit set, instead of not responding to the request. This can be used for descriptor rings where you don’t care if the oldest data is overwritten. 16 Broadcast receive enable (BCRXEN) - Allow broadcast receive transfers to this subaddress 15 Receive enable (RXEN) - Allow receive transfers to this subaddress 14 Log receive transfers (RXLOG) - Log all receive transfers in event log ring (only used if RXEN=1) 13 Interrupt on receive transfers (RXIRQ) - Each receive transfer will cause an interrupt (only if also RXEN,RXLOG=1) 12 : 8 Maximum legal receive size (RXSZ) to this subaddress - in16-bit words, 0 means 32 7 Transmit enable (TXEN) - Allow transmit transfers from this subaddress 6 Log transmit transfers (TXLOG) - Log all transmit transfers in event log ring (only if also TXEN=1) 5 Interrupt on transmit transfers (TXIRQ) - Each transmit transfer will cause an interrupt (only if TXEN,TXLOG=1) 4:0 Maximum legal transmit size (TXSZ) from this subaddress - in 16-bit words, 0 means 32 GRIP, Apr 2018, Version 2018.1 347 www.cobham.com/gaisler GRLIB IP Core Table 363.GR1553B RT Descriptor format Offset Value DMA R/W 0x00 Control and status word, see table 364 R/W 0x04 Data buffer pointer, 16-bit aligned R 0x08 Pointer to next descriptor, 16-byte aligned R or 0x0000003 to indicate end of list Table 364.GR1553B RT Descriptor control/status word (offset 0x00) 31 30 DV IRQEN 29 26 Reserved (0) 25 10 TIME 9 8 BC 3 SZ 2 0 TRES 31 Data valid (DV) - Should be set to 0 by software before and set to 1 by hardware after transfer. If DV=1 in the current receive descriptor before the receive transfer begins then a descriptor table error will be triggered. You can override this by setting the IGNDV bit in the subaddress table. 30 IRQ Enable override (IRQEN) - Log and IRQ after transfer regardless of SA control word settings Can be used for getting an interrupt when nearing the end of a descriptor list. 29 : 26 Reserved - Write 0 and mask out on read for forward compatibility 25 : 10 Transmission time tag (TTIME) - Set by the core to the value of the RT timer when the transfer finished. 9 Broadcast (BC) - Set by the core if the transfer was a broadcast transfer 8:3 Transfer size (SZ) - Count in 16-bit words (0-32) 2:0 Transfer result (TRES) 000 = Success 001 = Superseded (canceled because a new command was given on the other bus) 010 = DMA error or memory timeout occurred 011 = Protocol error (improperly timed data words or decoder error) 100 = The busy bit or message error bit was set in the transmitted status word and no data was sent 101 = Transfer aborted due to loop back checker error GRIP, Apr 2018, Version 2018.1 348 www.cobham.com/gaisler GRLIB IP Core 32.6 Bus Monitor Operation 32.6.1 Overview The Bus Monitor (BM) can be enabled by itself, or in parallel to the BC or RT. The BM acts as a passive logging device, writing received data with time stamps to a ring buffer. 32.6.2 Filtering The Bus Monitor can also support filtering. This is an optional feature, software can check for this by testing whether the BM filter registers are writable. Transfers can be filtered per RT address and per subaddress or mode code, and the filter conditions are logically AND:ed. If all bits of the three filter registers and bits 2-3 of the control register are set to ’1’, the BM core will log all words that are received on the bus. In order to filter on subaddress/mode code, the BM has logic to track 1553 words belonging to the same message. All 10 message types are supported. If an unexpected word appears, the filter logic will restart. Data words not appearing to belong to any message can be logged by setting a bit in the control register. The filter logic can be manually restarted by setting the BM enable bit low and then back to high. This feature is mainly to improve testability of the BM itself. The filtering capability can be configured out of the BM to save area. If this is done, all words seen are logged and the filter control registers become read-only and always read out as all-ones. You can, however, still control whether Manchester/parity errors are logged. 32.6.3 No-response handling In the MIL-STD-1553B protocol, a command word for a mode code using indicator 0 or a regular transfer to subaddress 8 has the same structure as a legal status word. Therefore ambiguity can arise when the subaddress or mode code filters are used, an RT is not responding on a subaddress, and the BC then commands the same RT again on subaddress 8 or mode code indicator 0 on the same bus. This can lead to the second command word being interpreted as a status word and filtered out. The BM can use the instrumentation bit and reserved bits to disambiguate, which means that this case will never occur when subaddresses 1-7, 9-30 and mode code indicator 31 are used. Also, this case does not occur when the subaddress/mode code filters are unused and only the RT address filter is used. 32.6.4 Log entry format Each log entry is two 32-bit words. Table 365.GR1553B BM Log entry word 0 (offset 0x00) 31 30 1 24 23 0 Reserved 31 TIME Always written as 1 30 : 24 Reserved - Mask out on read for forward compatibility 23 : 0 Time tag (TIME) GRIP, Apr 2018, Version 2018.1 349 www.cobham.com/gaisler GRLIB IP Core Table 366.GR1553B BM Log entry word 1 (offset 0x04) 31 30 0 20 Reserved 31 32.7 19 BUS 18 17 WST 16 15 0 WTP WD Always written as 0 30 : 20 Reserved - Mask out on read for forward compatibility 19 Receive data bus (BUS) - 0:A, 1:B 18 : 17 Word status (WST) - 00=word OK, 01=Manchester error, 10=Parity error 16 Word type (WTP) - 0:Data, 1:Command/status 15 : 0 Word data (WD) Clocking The core needs a separate clock for the 1553 codec. The core operates in two clock domains, the AMBA clock domain and the 1553 codec clock domain, with synchronization and handshaking between the domains. The AMBA clock can be at any frequency but must be at a minimum of 10 MHz. A propagation delay of up to one codec clock cycle (50 ns) can be tolerated in each clock-domain crossing signal. The core has two separate reset inputs for the two clock domains. They should be reset simultaneously, for instance by using two Reset generator cores connected to the same reset input but clocked by the respective clocks. 32.8 Registers The core is programmed through registers mapped into APB address space. If the RT, BC or BM parts of the core have been configured out, the corresponding registers will become unimplemented and return zero when read. Reserved register fields should be written as zeroes and masked out on read. Table 367.MIL-STD-1553B interface registers APB address offset Register R/W Reset value 0x00 IRQ Register RW (write ‘1’ to clear) 0x00000000 0x04 IRQ Enable RW 0x00000000 0x08...0x0F (Reserved) 0x10 Hardware config register R (constant) 0x00000000* 0x14...0x3F (Reserved) 0x40...0x7F BC Register area (see table 368) 0x80...0xBF RT Register area (see table 369) 0xC0...0xFF BM Register area (see table 370) (*) May differ depending on core configuration GRIP, Apr 2018, Version 2018.1 350 www.cobham.com/gaisler GRLIB IP Core Table 368.MIL-STD-1553B interface BC-specific registers APB address offset Register R/W Reset value 0x40 0x44 BC Status and Config register RW 0xf0000000* BC Action register W 0x48 BC Transfer list next pointer RW 0x00000000 0x4C BC Asynchronous list next pointer RW 0x00000000 0x50 BC Timer register R 0x00000000 0x54 BC Timer wake-up register RW 0x00000000 0x58 BC Transfer-triggered IRQ ring position RW 0x00000000 0x5C BC Per-RT bus swap register RW 0x00000000 0x60...0x67 (Reserved) 0x68 BC Transfer list current slot pointer R 0x00000000 0x6C BC Asynchronous list current slot pointer R 0x00000000 0x70...0x7F (Reserved) R/W Reset value (*) May differ depending on core configuration Table 369.MIL-STD-1553B interface RT-specific registers APB address offset Register 0x80 RT Status register R 0x80000000* 0x84 RT Config register RW 0x0000e03e*** 0x88 RT Bus status bits register RW 0x00000000 0x8C RT Status words register RW 0x00000000 0x90 RT Sync register R 0x00000000 0x94 RT Subaddress table base address RW 0x00000000 0x98 RT Mode code control register RW 0x00000555 0x9C...0xA3 (Reserved) RW 0x00000000 0xA4 RT Time tag control register 0xA8 (Reserved) 0xAC RT Event log size mask RW 0xfffffffc 0xB0 RT Event log position RW 0x00000000 0xB4 RT Event log interrupt position R 0x00000000 0xB8.. 0xBF (Reserved) (*) May differ depending on core configuration (***) Reset value is affected by the external RTADDR/RTPAR input signals GRIP, Apr 2018, Version 2018.1 351 www.cobham.com/gaisler GRLIB IP Core Table 370.MIL-STD-1553B interface BM-specific registers APB address offset Register R/W Reset value 0xC0 BM Status register R 0x80000000* 0xC4 BM Control register RW 0x00000000 0xC8 BM RT Address filter register RW 0xffffffff 0xCC BM RT Subaddress filter register RW 0xffffffff 0xD0 BM RT Mode code filter register RW 0xffffffff 0xD4 BM Log buffer start RW 0x00000000 0xD8 BM Log buffer end RW 0x00000007 0xDC BM Log buffer position RW 0x00000000 0xE0 BM Time tag control register RW 0x00000000 0xE4...0xFF (Reserved) (*) May differ depending on core configuration GRIP, Apr 2018, Version 2018.1 352 www.cobham.com/gaisler GRLIB IP Core 32.8.1 IRQ Register Table 371.0x00 - IRQ - GR1553B IRQ Register 31 18 RESERVED 17 16 BMTOF BMD RESERVED 15 11 10 9 8 RTTE RTD RTEV RESERVED 7 3 2 1 0 BCWK BCD BCEV 0 0 0 0 0 0 0 0 0 0 0 r wc wc r wc wc wc r wc wc wc 2 1 0 Bits read ‘1’ if interrupt occurred, write back ‘1’ to acknowledge 17 BM Timer overflow (BMTOF) 16 BM DMA Error (BMD) 10 RT Table access error (RTTE) 9 RT DMA Error (RTD) 8 RT transfer-triggered event interrupt (RTEV) 2 BC Wake-up timer interrupt (BCWK) 1 BC DMA Error (BCD) 0 BC Transfer-triggered event interrupt (BCEV) 32.8.2 IRQ Enable Register Table 372.0x04 - IRQE - GR1553B IRQ Enable Register 31 18 RESERVED 17 16 BMTOE BMDE 15 11 RESERVED 10 RTTEE 9 8 7 RTDE RTEVE 3 RESERVED BCWKE BCDE BCEVE 0 0 0 0 0 0 0 0 0 0 0 r rw rw r rw rw rw r rw rw rw 17 BM Timer overflow interrupt enable (BMTOE) 16 BM DMA error interrupt enable (BMDE) 10 RT Table access error interrupt enable (RTTEE) 9 RT DMA error interrupt enable (RTDE) 8 RT Transfer-triggered event interrupt enable (RTEVE) 2 BC Wake up timer interrupt (BCWKE) 1 BC DMA Error Enable (BCDE) 0 BC Transfer-triggered event interrupt (BCEVE) 32.8.3 Hardware Configuration Register Table 373.GR1553B Hardware Configuration Register 31 30 12 11 10 9 8 7 0 MOD RESERVED XKEYS ENDIAN SCLK * 0 * * * ‘ r r r r r r CCFREQ Note: This register reads 0x0000 for the standard configuration of the core 31 Modified (MOD) - Reserved to indicate that the core has been modified / customized in an unspecified manner 11 Set if safety keys are enabled for the BM Control Register and for all RT Control Register fields. 10 : 9 AHB Endianness - 00=Big-endian, 01=Little-endian, 10/11=Reserved 8 Same clock (SCLK) - Reserved for future versions to indicate that the core has been modified to run with a single clock 7:0 Codec clock frequency (CCFREQ) - Reserved for future versions of the core to indicate that the core runs at a different codec clock frequency. Frequency value in MHz, a value of 0 means 20 MHz. GRIP, Apr 2018, Version 2018.1 353 www.cobham.com/gaisler GRLIB IP Core 32.8.4 BC Status and Config Register Table 374.0x40 - BCSL - GR1553B BC Status and Config Register 31 30 28 27 17 BCSUP BCFEAT RESERVED * * r r 16 15 11 10 9 8 7 3 2 0 BCCHK ASADL R ASST SCADL SCST 0 0 0 0 0 0 0 r rw r r r r r 31 BC Supported (BCSUP) - Reads ‘1’ if core supports BC mode 30 : 28 BC Features (BCFEAT) - Bit field describing supported optional features (‘1’=supported): 30 29 28 BC Schedule timer supported BC Schedule time wake-up interrupt supported BC per-RT bus swap register and STBUS descriptor bit supported 16 Check broadcasts (BCCHK) - Writable bit, if set to ‘1’ enables waiting and checking for (unexpected) responses to all broadcasts. 15 : 11 Asynchronous list address low bits (ASADL) - Bit 8-4 of currently executing (if ASST=01) or next asynchronous command descriptor address 9:8 Asynchronous list state (ASST) - 00=Stopped, 01=Executing command, 10=Waiting for time slot 7:3 Schedule address low bits (SCADL) - Bit 8-4 of currently executing (if SCST=001) or next schedule descriptor address 2:0 Schedule state (SCST) - 000=Stopped, 001=Executing command, 010=Waiting for time slot, 011=Suspended, 100=Waiting for external trigger 32.8.5 BC Action Register Table 375.0x44 - BCA - GR1553B BC Action Register 31 16 15 10 9 8 5 RESERVED 4 3 CLRT SETT 2 1 0 RESERVED - - - - - - - - - - w - w w - w w w w w 31 : 16 ASSTP ASSRT 7 BCKEY SCSTP SCSUS SCSRT Safety code (BCKEY) - Must be 0x1552 when writing, otherwise register write is ignored 9 Asynchronous list stop (ASSTP) - Write ‘1’ to stop asynchronous list (after current transfer, if executing) 8 Asynchronous list start (ASSRT) - Write ‘1’ to start asynchronous list 4 Clear external trigger (CLRT) - Write ‘1’ to clear trigger memory 3 Set external trigger (SETT) - Write ‘1’ to force the trigger memory to set 2 Schedule stop (SCSTP) - Write ‘1’ to stop schedule (after current transfer, if executing) 1 Schedule suspend (SCSUS) - Write ‘1’ to suspend schedule (after current transfer, if executing) 0 Schedule start (SCSRT) - Write ‘1’ to start schedule 32.8.6 BC Tranfer List Next Pointer Register Table 376.0x48 - BCTNP - GR1553B BC Transfer list next pointer register 31 0 SCHEDULE TRANSFER LIST POINTER 0 rw 31 : 0 Read: Currently executing (if SCST=001) or next transfer to be executed in regular schedule. Write: Change address. If running, this will cause a jump after the current transfer has finished. GRIP, Apr 2018, Version 2018.1 354 www.cobham.com/gaisler GRLIB IP Core 32.8.7 BC Asynchronous List Next Pointer Register Table 377.0x4C - BCANP - GR1553B BC Asynchronous list next pointer register 31 0 ASYNCHRONOUS LIST POINTER 0 rw 31 :0 Read: Currently executing (if ASST=01) or next transfer to be executed in asynchronous schedule. Write: Change address. If running, this will cause a jump after the current transfer has finished. 32.8.8 BC Timer Register Table 378.0x50 - BCT - GR1553B BC Timer register 31 24 23 0 RESERVED SCHEDULE TIME (SCTM) 0 0 r r 23 : 0 Elapsed “transfer list” time in microseconds (read-only) Set to zero when schedule is stopped or on external sync. Note: This register is an optional feature, see BC Status and Config Register, bit 30 32.8.9 BC Timer Wake-up Register Table 379.0x54 - BCTW - GR1553B BC Timer Wake-up register 31 30 24 23 0 WKEN RESERVED 0 0 0 rw r rw 31 23 : 0 WAKE-UP TIME (WKTM) Wake-up timer enable (WKEN) - If set, an interrupt will be triggered when WKTM=SCTM Wake-up time (WKTM). Note: This register is an optional feature, see BC Status and Config Register, bit 29 32.8.10 BC Transfer-triggered IRQ Ring Position Register Table 380.0x58 - BCRD - GR1553B BC Transfer-triggered IRQ ring position register 31 0 BC IRQ SOURCE POINTER RING POSITION 0 rw 31 : 0 The current write pointer into the transfer-tirggered IRQ descriptor pointer ring. Bits 1:0 are constant zero (4-byte aligned) The ring wraps at the 64-byte boundary, so bits 31:6 are only changed by user GRIP, Apr 2018, Version 2018.1 355 www.cobham.com/gaisler GRLIB IP Core 32.8.11 BC per-RT Bus Swap Register Table 381.0x5C - BCBS - GR1553B BC per-RT Bus swap register 31 0 BC PER-RT BUS SWAP 0 rw 31 : 0 The bus selection value will be logically exclusive-or:ed with the bit in this mask corresponding to the addressed RT (the receiving RT for RT-to-RT transfers). This register gets updated by the core if the STBUS descriptor bit is used. For more information on how to use this feature, see section 32.4.3. Note: This register is an optional feature, see BC Status and Config Register, bit 28 32.8.12 BC Transfer List Current Slot Pointer Table 382.0x68 - BCTCP - GR1553B BC Transfer list current slot pointer 31 0 BC TRANSFER SLOT POINTER 0 r 31 : 0 Points to the transfer descriptor corresponding to the current time slot (read-only, only valid while transfer list is running). Bits 3:0 are constant zero (128-bit/16-byte aligned) 32.8.13 BC Asynchronous List Current Slot Pointer Table 383.0x6C - BCACP - GR1553B BC Asynchronous list current slot pointer 31 0 BC TRANSFER SLOT POINTER 0 r 31 : 0 Points to the transfer descriptor corresponding to the current asynchronous schedule time slot (read-only, only valid while asynchronous list is running). Bits 3:0 are constant zero (128-bit/16-byte aligned) 32.8.14 RT Status Register Table 384.0x80 - RTS - GR1553B RT Status register (read-only) 31 30 4 RTSUP RESERVED 3 2 1 0 ACT SHDA SHDB RUN 31 RT Supported (RTSUP) - Reads ‘1’ if core supports RT mode 3 RT Active (ACT) - ‘1’ if RT is currently processing a transfer 2 Bus A shutdown (SHDA) - Reads ‘1’ if bus A has been shut down by the BC (using the transmitter shutdown mode command on bus B) 1 Bus B shutdown (SHDB) - Reads ‘1’ if bus B has been shut down by the BC (using the transmitter shutdown mode command on bus A) 0 RT Running (RUN) - ‘1’ if the RT is listening to commands. GRIP, Apr 2018, Version 2018.1 356 www.cobham.com/gaisler GRLIB IP Core 32.8.15 RT Config Register Table 385.0x84 - RTC - GR1553B RT Config register 31 16 RTKEY 15 14 13 SYS SYDS BRS RESERVED 12 7 RTEIS 6 5 1 RTADDR 0 RTEN 0 1 1 1 0 * * 0 w rw rw rw r r rw rw 31 : 16 Safety code (RTKEY) - Must be written as 0x1553 when changing the RT address, otherwise the address field is unaffected by the write. When reading the register, this field reads 0x0000. If extra safety keys are enabled (see Hardware Config Register), the lower half of the key is used to also protect the other fields in this register. 15 Sync signal enable (SYS) - Set to ‘1’ to pulse the rtsync output when a synchronize mode code (without data) has been received 14 Sync with data signal enable (SYDS) - Set to ‘1’ to pulse the rtsync output when a synchronize with data word mode code has been received 13 Bus reset signal enable (BRS) - Set to ‘1’ to pulse the busreset output when a reset remote terminal mode code has been received. 6 Reads ‘1’ if current address was set through external inputs. After setting the address from software this field is set to ‘0’ 5:1 RT Address (RTADDR) - This RT:s address (0-30) 0 RT Enable (RTEN) - Set to ‘1’ to enable listening for requests 32.8.16 RT Bus Status Register Table 386.0x88 - RTBS - GR1553B RT Bus status register 31 9 RESERVED 8 8 TFDE 7 5 RESERVED 4 3 2 1 0 SREQ BUSY SSF DBCA TFLG 0 0 0 0 0 0 0 0 r rw rw rw rw rw rw rw Set Terminal flag automatically on DMA and descriptor table errors (TFDE) 4:0 These bits will be sent in the RT:s status responses over the 1553 bus. 4 Service request (SREQ) 3 Busy bit (BUSY) Note: If the busy bit is set, the RT will respond with only the status word and the transfer “fails” 2 Subsystem Flag (SSF) 1 Dynamic Bus Control Acceptance (DBCA) Note: This bit is only sent in response to the Dynamic Bus Control mode code 0 Terminal Flag (TFLG) The BC can mask this flag using the “inhibit terminal flag” mode command, if legal 32.8.17 RT Status Words Register Table 387.0x8C - RTSW - GR1553B RT Status words register 31 16 BIT WORD (BITW) 15 0 VECTOR WORD (VECW) 0 0 rw rw 31 : 16 BIT Word - Transmitted in response to the “Transmit BIT Word” mode command, if legal 15 : 0 Vector word - Transmitted in response to the “Transmit vector word” mode command, if legal. GRIP, Apr 2018, Version 2018.1 357 www.cobham.com/gaisler GRLIB IP Core 32.8.18 RT Sync Register Table 388.0x90 - RTSY - GR1553B RT Sync register 31 16 15 0 SYNC TIME (SYTM) SYNC DATA (SYD) 0 0 r r 31 : 16 The value of the RT timer at the last sync or sync with data word mode command, if legal. 15 : 0 The data received with the last synchronize with data word mode command, if legal 32.8.19 Sub Address Table Base Address Register Table 389.0x94 - RTSTBA - GR1553B RT Sub address table base address register 31 9 8 0 SUBADDRESS TABLE BASE (SATB) RESERVED 0 0 rw r 31 : 9 Base address, bits 31-9 for subaddress table 8:0 Always read ‘0’, writing has no effect 32.8.20 RT Mode Code Control Register Table 390.0x98 - RTMCC - GR1553B RT Mode code control register 31 30 29 RESERVED 28 27 RRTB 26 25 RRT 24 23 ITFB 22 21 ITF 20 19 ISTB 18 17 IST 16 DBC 0 0 0 0 0 0 0 0 r rw rw rw rw rw rw rw 15 14 TBW 13 12 TVW 11 10 9 TSB 8 TS 7 6 SDB 5 4 SD 3 2 SB 1 0 S 0 0 1 1 1 1 1 1 rw rw rw rw rw rw rw rw For each mode code: “00” - Illegal, “01” - Legal, “10” - Legal, log enabled, “11” - Legal, log and interrupt 29 : 28 Reset remote terminal broadcast (RRTB) 27 : 26 Reset remote terminal (RRT) 25 : 24 Inhibit & override inhibit terminal flag bit broadcast (ITFB) 23 : 22 Inhibit & override inhibit terminal flag (ITF) 21 : 20 Initiate self test broadcast (ISTB) 19 : 18 Initiate self test (IST) 17 : 16 Dynamic bus control (DBC) 15 : 14 Transmit BIT word (TBW) 13 : 12 Transmit vector word (TVW) 11 : 10 Transmitter shutdown & override transmitter shutdown broadcast (TSB) 9:8 Transmitter shutdown & override transmitter shutdown (TS) 7:6 Synchronize with data word broadcast (SDB) 5:4 Synchronize with data word (SD) 3:2 Synchronize broadcast (SB) 1:0 Synchronize (S) GRIP, Apr 2018, Version 2018.1 358 www.cobham.com/gaisler GRLIB IP Core 32.8.21 RT Time Tag Control Register Table 391.0xA4 - RTTTC - GR1553B RT Time tag control register 31 16 15 0 TIME RESOLUTION (TRES) TIME TAG VALUE (TVAL) 0 0 rw rw 31 : 16 Time tag resolution (TRES) - Time unit of RT:s time tag counter in microseconds, minus 1 15 : 0 Time tag value (TVAL) - Current value of running time tag counter 32.8.22 RT Event Log Mask Register Table 392.0xAC - RTELM - GR1553B RT Event Log mask register 31 21 16 2 RESERVED EVENT LOG SIZE MASK 1 0 RES 0xFFFFFFC r 31 : 0 rw r Mask determining size and alignment of the RT event log ring buffer. All bits “above” the size should be set to ‘1’, all bits below should be set to ‘0’ 32.8.23 RT Event Log Position Register Table 393.0xB0 - RTELP - GR1553B RT Event Log position register 31 0 EVENT LOG WRITE POINTER 0 rw 31 : 0 Address to first unused/oldest entry of event log buffer, 32-bit aligned 32.8.24 RT Event Log Interrupt Position Register Table 394.0xB4 - RTELIP - GR1553B RT Event Log interrupt position register 31 0 EVENT LOG IRQ POINTER 0 r 31 : 0 Address to event log entry corresponding to interrupt, 32-bit aligned The register is set for the first interrupt and not set again until the interrupt has been acknowledged. 32.8.25 BM Status Register Table 395.0xC0 - BMS - GR1553B BM Status register 31 30 29 0 BMSUP KEYEN RESERVED * * 0 r r r 31 BM Supported (BMSUP) - Reads ‘1’ if BM support is in the core. 30 Key Enabled (KEYEN) - Reads ‘1’ if the BM validates the BMKEY field when the control register is written. GRIP, Apr 2018, Version 2018.1 359 www.cobham.com/gaisler GRLIB IP Core 32.8.26 BM Control Register Table 396.0xC4 - BMC - GR1553B BM Control register 31 16 15 6 5 4 WRSTP EXST 3 2 1 0 IMCL UDWL MANL BMEN BMKEY RESERVED 0 0 0 0 0 0 0 0 rw r rw rw rw rw rw rw 31 : 16 Safety key - If extra safety keys are enabled (see KEYEN), this field must be 0x1543 for a write to be accepted. Is 0x0000 when read. 5 Wrap stop (WRSTP) - If set to ‘1’, BMEN will be set to ‘0’ and stop the BM when the BM log position wraps around from buffer end to buffer start 4 External sync start (EXST) - If set to ‘1’,BMEN will be set to ‘1’ and the BM is started when an external BC sync pulse is received 3 Invalid mode code log (IMCL) - Set to ‘1’ to log invalid or reserved mode codes. 2 Unexpected data word logging (UDWL) - Set to ‘1’ to log data words not seeming to be part of any command 1 Manchester/parity error logging (MANL) - Set to ‘1’ to log bit decoding errors 0 BM Enable (BMEN) - Must be set to ‘1’ to enable any BM logging 32.8.27 BMRT Address Filter Register Table 397.0xC8 - BMRTAF - GR1553B BM RT Address filter register 31 0 ADDRESS FILTER MASK 0xFFFFFFFF rw 31 Enables logging of broadcast transfers 30 : 0 Each bit position set to ‘1’ enables logging of transfers with the corresponding RT address 32.8.28 BMRT Sub address Filter Register Table 398.0xCC - BMRTSF - GR1553B BM RT Sub address filter register 31 0 SUBADDRESS FILTER MASK 0xFFFFFFFF rw 31 Enables logging of mode commands on sub address 31 30 : 1 Each bit position set to ‘1’ enables logging of transfers with the corresponding RT sub address 0 Enables logging of mode commands on sub address 0 GRIP, Apr 2018, Version 2018.1 360 www.cobham.com/gaisler GRLIB IP Core 32.8.29 BMRT Mode Code Filter Register Table 399.0xCC - BMRTMC - GR1553B BM RT Mode code filter register 31 19 RESERVED 18 17 16 STSB STS TLC 0x1ttt 1 1 1 r rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSW RRTB RRT ITFB ITF ISTB IST DBC TBW TVW TSB TS SDB SD SB S 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Each bit set to ‘1’ enables logging of a mode code: 18 Selected transmitter shutdown broadcast & override selected transmitter shutdown broadcast (STSB) 17 Selected transmitter shutdown & override selected transmitter shutdown (STS) 16 Transmit last command (TLC) 15 Transmit status word (TSW) 14 Reset remote terminal broadcast (RRTB) 13 Reset remote terminal (RRT) 12 Inhibit & override inhibit terminal flag bit broadcast (ITFB) 11 Inhibit & override inhibit terminal flag (ITF) 10 Initiate self test broadcast (ISTB) 9 Initiate self test (IST) 8 Dynamic bus control (DBC) 7 Transmit BIT word (TBW) 6 Transmit vector word (TVW) 5 Transmitter shutdown & override transmitter shutdown broadcast (TSB) 4 Transmitter shutdown & override transmitter shutdown (TS) 3 Synchronize with data word broadcast (SDB) 2 Synchronize with data word (SD) 1 Synchronize broadcast (SB) 0 Synchronize (S) 32.8.30 BMLog Buffer Start Table 400.0xD4 - BMLBS - GR1553B BM Log buffer start 31 0 BM LOG BUFFER START 0 rw 31 : 0 Pointer to the lowest address of the BM log buffer (8-byte aligned) Due to alignment, bits 2:0 are always 0. 32.8.31 BMLog Buffer End Table 401.0xD8 - BMLBE - GR1553B BM Log buffer end 31 22 21 - 3 BM LOG BUFFER END 2 0 - 0x0000007 r 31 : 0 rw r Pointer to the highest address of the BM log buffer Only bits 21:3 are settable, i.e. the buffer can not cross a 4 MB boundary Bits 31:22 read the same as the buffer start address.Due to alignment, bits 2:0 are always equal to 1 GRIP, Apr 2018, Version 2018.1 361 www.cobham.com/gaisler GRLIB IP Core 32.8.32 BMLog Buffer Position Table 402.0xDC - BMLBP - GR1553B BM Log buffer position 31 22 21 3 - BM LOG BUFFER POSITION 2 0 - 0x00000000 r rw 31 : 0 r Pointer to the next position that will be written to in the BM log buffer Only bits 21:3 are settable, i.e. the buffer can not cross a 4 MB boundary Bits 31:22 read the same as the buffer start address.Due to alignment, bits 2:0 are always equal to 0 32.8.33 BM Time Tag Control Register Table 403.0xE0 - BMTTC - GR1553B BM Time tag control register 31 24 23 0 TIME TAG RESOLUTION 32.9 TIME TAG VALUE 0 0 rw rw 31 : 24 Time tag resolution (TRES) - Time unit of BM:s time tag counter in microseconds, minus 1 23 : 0 Time tag value (TVAL) - Current value of running time tag counter Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x04D. For a description of vendor and device identifiers see GRLIB IP Library User’s Manual. 32.10 Implementation 32.10.1 Reset The core does not changs reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core has two separate reset inputs for the two clock domains. They should be reset simultaneously, for instance by using two Reset generator cores connected to the same reset input but clocked by the respective clocks See the documentation of the syncrst VHDL generic for possible reset implementations. GRIP, Apr 2018, Version 2018.1 362 www.cobham.com/gaisler GRLIB IP Core 32.11 Configuration options Table 404 shows the configuration options of the core (VHDL generics). Table 404.Configuration options Generic Function Allowed range Default hindex AHB master index 0 - NAHBMST-1 0 pindex APB slave index 0 - NAPBSLV-1 0 paddr ADDR field of the APB BAR. 0 - 16#FFF# 0 pmask MASK field of the APB BAR. 0 - 16#FFF# 16#FFF# pirq Index of the interrupt line. 0 - NAHBIRQ-1 0 bc_enable Selects whether BC support is built into the core 0-1 1 rt_enable Selects whether RT support is built into the core 0-1 1 bm_enable Selects whether BM support is built into the core 0-1 1 bc_timer Selects whether the BC timer and wake-up interrupt features are built into the core. 0-2 1 0=None, 1=Timer, 2=Timer and wake-up bc_rtbusmask Selects whether the BC per-RT bus swap register is built into the core. 0-1 1 extra_regkeys Enables extra safety keys for the BM control register and for all fields in the RT control registers 0-1 0 syncrst Selects reset configuration: 0-2 1 0: Asynchronous reset, all registers in core are reset 1: Synchronous, minimal set of registers are reset 2: Synchronous, most registers reset (increases area slightly to simplify netlist simulation) ahbendian Selects AHB bus endianness (for use in non-GRLIB sys- 0 - 1 tems), 0=Big endian, 1=Little endian bm_filters Enable BM filtering capability 0-1 1 codecfreq Codec clock domain frequency in MHz 20 or 24 20 sameclk AMBA clock and reset is same as codec (removes internal synchronization) 0-1 0 GRIP, Apr 2018, Version 2018.1 363 0 www.cobham.com/gaisler GRLIB IP Core 32.12 Signal descriptions Tables 405-406 shows the interface signals of the core (VHDL ports). Table 405.Signal descriptions on AMBA side Signal name Field Type Function Active CLK N/A Input Clock, AMBA clock domain - RST N/A Input Reset for registers in CLK clock domain Low AHBMI * Input AHB master input signals - AHBMO * Output AHB master output signals - APBSI * Input APB slave input signals - APBSO * Output APB slave output signals - AUXIN EXTSYNC Input External sync input for Bus Controller Pos. edge Re-synchronized to AMBA clk internally. Edge-detection checks for the sampled pattern “01”, i.e. pulses should be at least one CLK cycle to always get detected. AUXOUT RTADDR Input Reset value for RT address, if parity matches. - RTPAR Input RT address odd parity - RTSYNC Output Pulsed for one CLK cycle after receiving a synchronize mode command in RT mode High BUSRESET Output Pulsed for one CLK cycle after receiving a reset remote terminal mode command in RT mode High VALIDCMDA Output Pulsed for one CLK cycle after receiving a valid command word on bus A/B in RT mode High Asserted when the terminal fail-safe timer has triggered on bus A/B. High VALIDCMDB Output TIMEDOUTA Output TIMEDOUTB Output BADREG Output High High Pulsed for one CLK cycle when an invalid regis- High ter access is performed, either: - an access to an undefined register, - read/write from a write-only/read-only register, - a read/write to a non-implemented part of the core - an incorrect BCKEY/BMKEY IRQVEC Output Auxiliary IRQ vector. Pulsed at the same time as the ordinary PIRQ line, but with a separate line for each interrupt: High 7: BM Timer overflow, 6: BM DMA Error, 5: RT Table error, 4: RT DMA Error, 3: RT Event 2: BC Wake-up, 1: BC DMA Error, 0: BC Event * see GRLIB IP Library User’s Manual GRIP, Apr 2018, Version 2018.1 364 www.cobham.com/gaisler GRLIB IP Core Table 406.Signal descriptions on 1553 side Signal name Field Type Function Active CODEC_CLK N/A Input Codec clock - CODEC_RST N/A Input Reset for registers in CODEC_CLK domain Low TXOUT BUSA_TXP Output Bus A transmitter, positive output High ** BUSA_TXN Output Bus A transmitter, negative output High ** BUSA_TXEN Output Bus A transmitter enable High BUSA_RXEN Output Bus A receiver enable High BUSB_TXP Output Bus B transmitter, positive output High ** BUSB_TXN Output Bus B transmitter, negative output High ** BUSB_TXEN Output Bus B transmitter enable High BUSB_RXEN Output Bus B receiver enable High BUSA_TXIN Output Inverted version of BUSA_TXEN High (for VHDL coding convenience) TXOUT_FB BUSB_TXIN Output Inverted version of BUSB_TXEN High See TXOUT Input Feedback input to the terminal fail-safe timers. See TXOUT Should be tied directly to TXOUT, but are exposed to allow testing the fail-safe timer function. This input is re synchronized to CODEC_CLK so it can be asynchronous. RXIN BUSA_RXP Input Bus A receiver, positive input High ** BUSA_RXN Input Bus A receiver, negative input High ** BUSB_RXP Input Bus B receiver, positive input High ** BUSB_RXN Input Bus B receiver, negative input High ** ** The core will put both P/N outputs low when not transmitting. For input, it accepts either both-low or both-high idle. 32.13 Signal definitions and reset values The signals and their reset values are described in table 407. Table 407.Signal definitions and reset values Signal name Type Function Active Reset value busa_rxen Output busa_rxp Input Enable for the A receiver High Logical 0 Positive data input from the A receiver High* - busa_rxn Input Negative data input from the A receiver High* - busa_txinh Output Enable for the A transmitter Low** Logical 1 busa_txp Output Positive data to the A transmitter High Logical 0 busa_txn Output Negative data to the A transmitter High Logical 0 busb_rxen Output Enable for the B receiver High Logical 0 busb_rxp Input Positive data input from the B receiver High* - busb_rxn Input Negative data input from the B receiver High* - busb_txinh Output Enable for the B transmitter Low** Logical 1 busb_txp Output Positive data to the B transmitter High Logical 0 busb_txn Output Negative data to the B transmitter High Logical 0 * rx inputs can be either both-high or both-low when bus is idle ** txinh inhibits (disables) transmission when high, enables transmission when low GRIP, Apr 2018, Version 2018.1 365 www.cobham.com/gaisler GRLIB IP Core 32.14 Timing The timing waveforms and timing parameters are shown in figure 114 and are defined in table 408. clk tGR1553B1 txinh/rxen tGR1553B2 txp/txn tGR1553B3 rxp/rxn tGR1553B4 Figure 114. Timing waveforms Table 408.Timing parameters Name Parameter Reference edge Min Max Unit tGR1553B1 clock to output delay, control signals rising clk edge - TBD ns tGR1553B2 clock to output delay, transmit data rising clk edge TBD TBD ns tGR1553B3 data input to clock setup rising clk edge TBD * - ns tGR1553B4 data input from clock hold rising clk edge TBD * - ns * The rx input signals are re-synchronized to clk internally 32.15 Library dependencies Table 409 shows libraries used when instantiating the core (VHDL libraries). Table 409.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AHB/APB signal definitions GAISLER GR1553B_PKG Signals, component signal and component declaration 32.16 Instantiation This example shows how the core can be instantiated in a GRLIB design. library ieee; use ieee.std_logic_1164.all; library grlib, gaisler; use grlib.amba.all; use gaisler.gr1553b_pkg.all; use gaisler.misc.rstgen; entity gr1553b_ex generic ( padtech : ); port ( rstn : clk : codec_clk : is integer in std_ulogic; in std_ulogic; in std_ulogic; GRIP, Apr 2018, Version 2018.1 366 www.cobham.com/gaisler GRLIB IP Core -- MIL-STD-1553 signals txAen : out std_ulogic; txAP : out std_ulogic; txAN : out std_ulogic; rxAen : out std_ulogic; rxAP : in std_ulogic; rxAN : in std_ulogic; txAen : out std_ulogic; txAP : out std_ulogic; txAN : out std_ulogic; rxAen : out std_ulogic; rxAP : in std_ulogic; rxAN : in std_ulogic ); end; architecture rtl of gr1553b_ex is -- System-wide synchronous reset signal rst : std_logic; -- AMBA signals signal apbi signal apbo signal ahbi signal ahbo : : : : -- GR1553B signals signal codec_rst : signal txout : signal rxin : signal auxin : signal auxout : apb_slv_in_type; apb_slv_out_vector := (others => apb_none); ahb_mst_in_type; ahb_mst_out_vector := (others => apb_none); std_ulogic; gr1553b_txout_type; gr1553b_rxin_type; gr1553b_auxin_type; gr1553b_auxout_type; begin rg0: rstgen port map (rstn, clk, ’1’, rst, open); -- AMBA Components are instantiated here ... -- Reset generation for 1553 codec rgc: rstgen port map (rstn, codec_clk, ’1’, codec_rst, open); -- GR1553B gr1553b0: gr1553b generic map (hindex => 4, pindex => 7, paddr => 7, pirq => 13, syncrst => 1, bc_enable => 1, rt_enable => 1, bm_enable => 1) port map (clk, rst, ahbi, ahbo(4), apbi, apbo(7), auxin, auxout, codec_clk, codec_rst, txout, txout, rxin); p: gr1553b_pads generic map (padtech => padtech, outen_pol => 0) port map (txout,rxin, rxAen,rxAP,rxAN,txAen,txAP,txAN, rxBen,rxBP,rxBN,txBen,txBP,txBN); auxin <= gr1553b_auxin_zero; end; 32.17 Constraints This section contains example constraints for GR1553B. 0. Define a clock called 'mil_clk' 1. milclkperiod = 1553B Maximum clock frequency GRIP, Apr 2018, Version 2018.1 367 www.cobham.com/gaisler GRLIB IP Core 2. tech_lib_setup = Setup timing for FlipFlop used in technology 3. tech_lib_hold = Hold timing for FlipFlop used in technology set_input_delay -clock [get_clocks mil_clk] -min [expr $tech_lib_hold] [get_ports $mil_inputs] set_input_delay -clock [get_clocks mil_clk] -max [expr $milclkperiod/2 - $tech_lib_setup] [get_ports $mil_inputs] -add_delay set_output_delay -clock [get_clocks mil_clk] -max [expr $milclkperiod/2 + $tech_lib_setup] [get_ports $mil_outputs] -add_delay set_output_delay -clock [get_clocks mil_clk] -min [expr -1 * $tech_lib_hold] [get_ports $mil_outputs] -add_delay GRIP, Apr 2018, Version 2018.1 368 www.cobham.com/gaisler GRLIB IP Core 32.18 Note: AHB Interface Compatibility 32.18.1 Introduction When using the GR1553B core in a non-GRLIB environment, the AHB system designer must make sure that the slaves to be accessed by the core are compatible with the accesses the master makes. 32.18.2 Generic access patterns The GR1553B core performs the following accesses on the AHB bus: • 32-bit sequential read burst, unspecified length, Length 2-3, 128-bit aligned start address. (BC,RT) • 32-bit sequential write burst, length 2 (BM) • Single 32-bit read/write (BC,RT) • Single 16-bit write (BC,RT) • Idle transfers The master supports wait states (hready low) as well as split and retry responses. In either case, it will retry accesses indefinitely until getting an OKAY or ERROR response. Busy cycles and locked transfers are not used by the core. 32.18.3 Endianness The GR1553B core, in its standard configuration, only works on big-endian systems. Byte-swapping in software is not enough because of the 16-bit writes. Little-endian bus support can be configured by setting the ahbendian generic to 1. The endian-ness setting only changes the handling of data buffers, data structures are still read using 32-bit reads/ writes and bit fields extracted from the same bit positions. For data buffers, the core is designed to make 16-bit addressing correct, so that each 16-bit data word in memory is transferred msb to lsb in increasing address order. Note that with little-endian addressing this means that the data will not be sent in byte order. This means that care must be taken to ensure correct ordering when transferring data from 1553 buffers to/from byte streams (files, network packets, etc.). GRIP, Apr 2018, Version 2018.1 369 www.cobham.com/gaisler GRLIB IP Core 1553 traffic example: Time 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 Big-endian operation (both hword and byte consistent): 1553 bus Bus data: 0x3456, 0xF001 GR1553B ahbendian=0 AHB hwdata (31:0): 0x3456F001 Big-endian AHB RAM contents, as hword array: 0x3456, 0xF001 RAM RAM contents, as byte array: 0x34, 0x56, 0xF0, 0x01 Little-endian operation (hword consistent): 1553 bus Bus data: 0x3456, 0xF001 GR1553B ahbendian=1 AHB hwdata (31:0): 0xF0013456 Little-endian AHB RAM RAM contents, as hword array: 0x3456, 0xF001 RAM contents, as byte array: 0x56, 0x34, 0x01, 0xF0 Figure 115. Relation between transferred 1553 data order and RAM contents for little/big- GRIP, Apr 2018, Version 2018.1 370 www.cobham.com/gaisler GRLIB IP Core 32.19 Note: AHB Latency and throughput requirements 32.19.1 Introduction Since the AMBA AHB bus standard does not in itself guarantee any maximum latency or throughput, the AHB bus system must be carefully designed so that the core can satisfy the 1553 requirements reliably. Throughput is not normally a problem, since even at the lowest supported AMBA frequency of 10 MHz, the core can only use a few percent of the bus bandwidth. Latency is a larger concern, especially when there are other bus masters with high bandwidth utilization or large burst access patterns. Some general recommendations: • Make GR1553B the highest priority master on the bus • Limit the maximum length of other master’s bursts to the order of 5 us. • Use local RAM for descriptors and preferably also data. 32.19.2 BC Descriptor processing Between transfers, the BC core first writes the descriptor status word using a 32-bit write, then fetches the following descriptor using a 3 x 32-bit read burst. If the next location in the schedule is a branch, then the burst fetches only the first two 32-bit words, then processes the condition for one cycle, and then continues. The core keeps the bus request signal high continuously until the next descriptor has been read. Between the status write and the descriptor read, there is one idle AHB transaction, i.e. the descriptor read is started the cycle after the status write finishes. Between a branch read and the next descriptor read, there are two idle AHB transactions, i.e. one completely idle cycle between the end of branch read and the start of descriptor read. 32.19.3 BC Asynchronous scheduling If the asynchronous list is started and there is slack in the regular schedule, the BC needs to read the next asynchronous descriptor in order to make the scheduling decision. In case there is less slack than was specified in the asynchronous descriptor, the BC will then read the regular descriptor and proceed with the regular schedule. In this case, the BC remembers the asynchronous time requirement and will not need to re-read the asynchronous descriptor until the asynchronous transfer is actually scheduled. If there is less than 24 us of slack in the regular schedule, then the BC will assume there is no time for the asynchronous transfer, not read the asynchronous descriptor and just proceed with the regular schedule. This means that as long as two BC descriptors can be read within 24 us, the asynchronous descriptor processing can not affect the ordinary schedule. 32.19.4 BC Data Buffer processing When transferring data from BC-to-RT, the core reads the first one or two (depending on alignment) 16-bit data words from memory using a 32-bit read, while the command word is being transferred. The core then reads an additional 32-bit word every time the last previously read data word is sent and there is more to send. For transfers from RT-to-BC, the core either writes the first data word using a 16-bit write, or writes the first two data words using a 32-bit write, depending on data buffer alignment. It will then perform a 32-bit write after every two data words received. While performing the write, the core does not buffer another data word so the write has to complete within 20 us. GRIP, Apr 2018, Version 2018.1 371 www.cobham.com/gaisler GRLIB IP Core If there is one received data word left after the transfer, it is written during the 5 us message gap. If it doesn’t finish in that time, the descriptor processing will be delayed until after the write finishes. 32.19.5 BC Requirements The hard requirement on the BC comes from the data buffers, where one read/write should finish in 20 us. The time needed for descriptor processing will affect the schedule. In order to reduce this time, the time for a 32-bit write followed by a 3x32-bit read burst should be reduced, preferably to the 2-3 us range. This is more of a soft requirement, and for larger schedules it can often be viewed as an average over minor frames or other groups of transfers. If the asynchronous scheduling feature is used, and you do not want the regular schedule to be affected by this, two 3x32-bit read bursts must be able to finish within 24 us. 32.19.6 RT Transfer Processing For the RT there are two cases to consider, receive and transmit. The receive case: 1. The RT gets the receive command 2. While the first data word is transmitted over the bus, the RT looks up the subaddress table and receive descriptor. 3. The data words are stored 4. The RT waits 5-6 us to see that there are no extra (unwanted) data words. 5. The status word is transmitted. In parallel, the results are written to the descriptor and the log and table is updated. The transmit case: 1. The RT gets the transmit command 2. In parallel there are two processes working: Process A: A.1 The RT looks up in the subaddress table that the request is legal. A.2 The RT looks up the descriptor and reads the first word of data Process B: B.1 The RT waits 5-6 us to see that there are no extra (unwanted) data words received. B.2 Wait for A.1 to finish B.3 Send status word B.4 Send data 3. The data words are sent 4. The results are written to the descriptor and the log and table is updated. In the receive case, the subaddress table and descriptor reads (two 3x32-bit read bursts) have to finish within the 20 us period that the data word is transferred. In the transmit case, the subaddress table read (one 2x32-bit read burst) has to finish in time so that the RT satisfies the response time requirement. The RT has a status word response time requirement of 12 us mid-bit to mid-sync, which translates into in 10 us maximum bus dead time before responding. These 10 us also include transceiver delays, so the actual time available is typically closer to 9 us. GRIP, Apr 2018, Version 2018.1 372 www.cobham.com/gaisler GRLIB IP Core The core has a safety limit of 9 us, after which a table error interrupt is generated and no response is generated. However, this should be seen as a fallback solution and triggering this time-out should be considered a fault at the AMBA bus design level. 32.19.7 RT Requirements From the cases above, the following requirements can be derived: One 2x32-bit read burst must finish in 8.5-9 us (from the transmit case above) Two 3x32-bit read bursts plus one 32-bit read must finish in 20 us. Each 32-bit data buffer read/write must finish in 20 us. 32.19.8 Bus Monitor The bus monitor will at full bus traffic, write 2x32-bit data words every 20 us. If run in parallel with the BC or RT, this will need to be added to the requirements. The core is designed so that, after an RT+BM receives a command word, the RT will access the bus first to do the more urgent accesses. GRIP, Apr 2018, Version 2018.1 373 www.cobham.com/gaisler GRLIB IP Core 32.20 Note: BC transfer timing 32.20.1 Introduction In order to design a transfer schedule for the Bus Controller, the worst-case times for each transfer must be calculated. This note is intended to give some hints on how to do this. Understanding of the 1553B protocol is assumed, see the AS15531 standard (in particular, Figure 9) for details. 32.20.2 Overview Except for the case of automatic retries, the longest time a transfer takes is the success case, where all permitted time-outs and slack is used. When reading the standard, there are a few points to note for the calculations: • The time-outs and gaps in the standard are specified mid-parity to mid-sync. To convert into bus dead time, one must subtract 2 us. • The timings are specified on the bus side, so transceiver delays must be taken into account. 32.20.3 Transceiver delay The timings in the 1553 standard are specified on the terminal boundary which is on the bus side of the transceiver. However, the core operates on the other side of the transceiver. Therefore, the transceiver delays must be taken into account. The BC mode uses the loopback checking mechanism to compensate for transceiver delay. After the command words have been sent, it waits for the words to loop back through the receiver and then starts the RT time-out timer. 32.20.4 BC Transfer Steps: Parts A BC transfer can be divided into the following steps: 1. Transmission of control words and receive data This is a continuous transmission which takes 20 us per word sent. Also include 0.2 us starting delay. 2. Transceiver turnaround The core waits for the transmitted command to loop back into the receiver. By doing this before starting the RT time-out clock, we get an accurate RT timeout regardless of transceiver delay. The time this takes is the sum of the transmitter and receiver delay, plus internal decoding delays of 0.15-0.40 us. 3. RT Response Time-out The core allows a maximum of 12.0-12.5 us bus dead time before the beginning of the RT Response. Note that this time can be increased via a descriptor setting. 4. RT Response and transmit data The BC receives the RT status word and the specified number of data words. The Bus Controller checks for message continuity and allows a maximum of 1 us of sync drift over the entire message. The maximum time for this part is thus 20 us/word + 1 us. 5. Second RT Response Time-out For RT-to-RT transfers. See step 3. 6. Second RT Response For RT-to-RT transfers. See step 4. 7. Word count verification GRIP, Apr 2018, Version 2018.1 374 www.cobham.com/gaisler GRLIB IP Core For non-broadcast and RT-to-RT messages, the BC waits an additional 5 us to ensure that there is no additional word sent out by the last transmitting RT. 8. Store result, fetch next descriptor The time this takes to perform depends completely on the AMBA system the core is connected to. 9. Broadcast message gap and descriptor processing For single-RT broadcasts, instead of step 7-8 the core inserts a 3 us message gap, and in parallel starts fetching the next descriptor. This step therefore takes the maximum of 3 us and the time needed for step 8. 32.20.5 BC transfer steps: Composition The different 1553 message types map to the above steps as: BC-to-RT, RT-to-BC, Mode: Steps 1-4,7-8 RT-to-RT: Steps 1-8 BC-to-RT broadcast, Mode broadcast: Steps 1,2,9 RT-to-RT broadcast: Steps 1-4,7-8 If broadcast response checking is enabled in the BC status register, the core waits and checks that no RT produces a response on the bus after each broadcast. Thus, the broadcast case changes to 1-4,7-8, and 30-35 us is added to the worst-case transfer time. 32.20.6 Timing calculation Based on the steps above, and also taking automatic replies into account, we end up with the following calculations: BC-to-RT, RT-to-BC or Mode, N data words: T = Ctry x (20.2 + Nx20 + Tloop + 12.5 + Textra + 21 + 5) + Tdpr  = Ctry x (58.7 + Nx20 + Textra + Tloop) + Tdpr RT-to-RT, N data words: T = Ctry x (40.2 + Tloop + 12.5 + Textra + 21 + Nx20 + 12.5 + Textra + 21 + 5) + Tdpr  = Ctry x (112.2 + Nx20 + 2Textra + Tloop) + Tdpr BC-to-RT broadcast or Mode broadcast, N data words: T = Ctry x (20.2 + Nx20 + Tloop + 3) - 3 + max(Tdpr,3) RT-to-RT broadcast: T = Ctry x (40.2 + Tloop + 12.5 + Textra + 21 + Nx20 + 5) + Tdpr Where: T Worst-case time usage for transfer (i.e. how much the following transfer is delayed when running at maximum rate) Ctry The maximum number of attempts, controlled by descriptor, equal to 1 unless automatic retries are used. Tloop Time from the end of a word transmission to receiver decoding the looped-back word. Sum of transceiver transmit and receive delay, plus internal delay of 400 ns. Tdpr Time needed for data processing between this and the next transfer. This includes storing result, processing any branches, and fetching the next descriptor Textra 4 us. Extra RT response time, equal to the RTTO field in the transfer descriptor multiplied by GRIP, Apr 2018, Version 2018.1 375 www.cobham.com/gaisler GRLIB IP Core 32.20.7 Example Assume for this example that Tloop = 1.4 us (transceiver delay of 500 ns + 500 ns) and Tdpr = 3 us (90 cycles at 30 MHz). An RT-to-RT transfer of 5 data words then needs up to 1 x (112.2 + 5x20 + 2x0 + 1.4) + 3 = 216.6 us of time to execute. GRIP, Apr 2018, Version 2018.1 376 www.cobham.com/gaisler GRLIB IP Core 32.21 Note: Time synchronization 32.21.1 Introduction The purpose of time synchronization is to get a common notion of time between the terminals on the bus. This allows the user to relate time stamps from different terminals and coordinate events. If there is an external time base available on one of the terminals it is also interesting to be able to translate the time stamps over into this time base. This note describes the GR1553B IP core’s BC-to-RT time synchronization capabilities and discusses some applications. 32.21.2 Hardware features: BC features The BC supports sending the 1553 bus standard’s two mode commands dedicated to synchronization, synchronize (code 1) and synchronize with data word (code 17). The commands can be sent either to a specific RT, or sent on the broadcast address to all RT:s on one bus. With the “wait for external trigger” (WTRIG) descriptor bit, any data transfer or mode code in the schedule can be set up to wait for a positive edge on the IP core’s auxin.extsync input signal before starting. The external sync can also be triggered from software by writing to the BC Action Register. It is also possible to use the regular scheduling features of the core to plan synchronization commands within a frame with high precision, just like any other transfer can be planned. This makes it possible to send timed sync pulses at a different interval than the external sync pulses, or to use the internal BC timer as time master with no external time base at all. 32.21.3 Hardware features: RT features The RT supports receiving the two synchronization mode commands that can be emitted by the BC. In case of synchronization with data word, the attached data word can be read out through the RT sync register. The RT has an internal timer with configurable scaler, which can be read-out and configured through the RT Time tag control register. When a mode command is received, the timer value is stored into the RT Sync Register which can be read out by software. There are also a number of core output signals related to synchronization. The validcmdA/B outputs are raised whenever a valid command word is received in the RT, and this happens at the same time as the internal time stamp is taken. There is also an output called rtsync which is set high only after a successfully received sync command. The rtsync output pulse always occurs after the validcmd pulse. If software handling of synchronization is desired, the core can be configured to generate an IRQ after a sync mode command has been received. 32.21.4 Hardware features: Internal timers Both the internal timer used for BC scheduling and the timer used for the RT time stamps are based on 1 MHz clock ticks generated in the codec clock domain that are resynchronized to the AMBA clock domain. When the RT timer register is written, the tick generator and the (optional) scaler gets reset, therefore for best timestamp accuracy, the RT timer should be left free-running and used as differential measurements. In terms of frequency accuracy, the internal timers will have the same characteristics as the codec clock, which is limited by the 1553 standard to 1000 ppm long-term. If the user has a more accurate clock source than this, this will naturally translate into more accurate timing. GRIP, Apr 2018, Version 2018.1 377 www.cobham.com/gaisler GRLIB IP Core 32.21.5 Synchronization schemes 32.21.6 Synchronization schemes: Overview This section describes a few ways to generate and receive synchronization commands on the bus. There are many possible ways to do this, but in this section the basic scheme assumed is by broadcasting sync mode commands from the BC at a regular interval. To handle fault conditions, the sync commands are sent on alternating buses. Typically the user also wants to send a frame number or a coarse time stamp with the sync command. This can be sent either as the attached data word when using the sync with data mode command, or it can be sent beforehand to a dedicated subaddress on the RT:s. This is not described further in the section. 32.21.7 Synchronization schemes: BC without external time base If no external real time base is available on the BC, regular sync commands can still be generated by scheduling as shown in the example below. Table 410.Example BC descriptor structure with synchronization Sum of slot times assigned in each frame = sync period/2 Frame 1 Frame 2 Frame 3 Frame 4 Sync broadcast Transfer Transfer ... Jump to  frame 2 Transfer Transfer ... Jump to  frame 3 Transfer Transfer ... Jump to  frame 4 Transfer Transfer ... Jump to  frame 1 Bus A Sync broadcast Bus B Sync broadcast Bus A Sync broadcast Bus B 32.21.8 Synchronization schemes: BC with external time base If there is an external time base connected to the extsync input of the core, this can be used by setting the wait for external trigger descriptor bit at intervals in the schedule corresponding to the sync interval. The schedule can otherwise be kept as is. As the figure shows it is possible to have the sync pulses at a multiple of the sync interval and use the internal time base for the sync commands in between. Table 411.Example BC descriptor structure with external synchronization Sum of slot times assigned in each frame = sync period/2 Frame 1 Frame 2 Frame 3 Frame 4 Sync broadcast Transfer Transfer ... Jump to  frame 2 Transfer Transfer ... Jump to  frame 3 Transfer Transfer ... Jump to  frame 4 Transfer Transfer ... Jump to  frame 1 Bus A, wtrig set Sync broadcast Bus B Sync broadcast Bus A Sync broadcast Bus B GRIP, Apr 2018, Version 2018.1 378 Sum of slot times in all four frames gives external sync period www.cobham.com/gaisler GRLIB IP Core 32.21.9 Synchronization schemes: RT without external time base If the resolution of the sync period from the BC is good enough, then the simplest solution is to just take the frame number sent by the BC directly and use it as the time stamp. If more resolution is needed, the user can read out the current value of the RT Timer, compare with the last sync time stamp in the RT Sync register, and use the difference as a time offset from the last sync time from the BC. 32.21.10Synchronization schemes: RT with external time base(s) If an external timer is available, its value can be read out at the same time as the sync time stamp by the hardware using a construct like the one shown below. The first register captures the external timer value whenever a command word is received, and the second register records the time stamp if the command was a sync mode code. With this value, the user will then obtain a common time stamp between the BC time, RT time and external time that can be used in different ways. Reg External Timer validcmdA OR validcmdB ahb clock D EN Reg Q D rtsync CLK Q Sync timestamp EN CLK Figure 116. Obtaining an RT sync timestamp in hardware with an external time base 32.21.11Accuracy 32.21.12Accuracy: Propagation delays When the sync command is sent, there is first an approximate 500 ns of delay inside the core, followed by analog delays, consisting of BC pad delays, BC transmitter delay, bus propagation delays, RT receiver delays, and RT pad delays. When using the external BC sync, there is also a 2-3 AHB cycle delay before the sync is detected due to synchronization. This creates a small offset between the external time reference and the internal time. On the RT digital side, there will first be a delay of 20000 ns to receive the whole command word, followed by internal decoding delays of approximately 500 ns before the command word is recognized and the time stamp is taken. Most of this delay is constant, in particular the 20 us word length, and can therefore be easily compensated for by offsetting the time stamps. Offsetting the RT timestamps by 24 us should be a reasonable first-order approach, accurate within +/- 4 us or so. If more accuracy is needed, characterization measurements or further analysis of the bus system would need to be done. 32.21.13Accuracy: Clock drift Relative drift between the clocks determine how often synchronization is necessary. Since the internal timers of the BC and RT are as accurate as the codec clocks, and both the clocks must have the 1000 ppm worst-case accuracy permitted by the 1553 standard, the BC and RT timers can drift apart up to 2 us for a sync period of 1 ms. Assuming the external time base is much more accurate, the internal and external BC time bases will drift apart of up to 1 us for every ms of external sync period. GRIP, Apr 2018, Version 2018.1 379 www.cobham.com/gaisler GRLIB IP Core 33 GRTIMER - General Purpose Timer Unit 33.1 Overview The GRTIMER IP core’s functionality for latching timer values, external clocking and reload on external events has been merged into the GPTIMER core. All new designs should instantiate the GPTIMER IP core. A GRTIMER entity exists that is a wrapper around the GPTIMER IP core for backward compatibility. GRIP, Apr 2018, Version 2018.1 380 www.cobham.com/gaisler GRLIB IP Core 34 GRACECTRL - AMBA System ACE Interface Controller 34.1 Overview The core provides an AMBA AHB interface to the microprocessor interface of a Xilinx System ACE Compact Flash Solution. Accesses to the core’s memory space are directly translated to accesses on the System ACE microprocessor interface (MPU). A M B A System ACE control AHB control A H B MPD[15 / 7:0] MPA[6:0] MPCEN MPWEN MPOEN MPIRQ Figure 117. Block diagram 34.2 Operation 34.2.1 Operational model The core has one AHB I/O area, accesses to this area are directly translated to accesses on the Xilinx System ACE’s Microprocessor Interface (MPU). When an access is made to the I/O area, the core first checks if there already is an ongoing access on the MPU. If an access is currently active, the core will respond with an AMBA SPLIT response. If the MPU bus is available, the core will start an access on the MPU bus and issue a SPLIT response to the AMBA master. If the core has been configured for a system that does not support SPLIT responses, it will insert wait states instead. 34.2.2 Bus widths The AMBA access is directly translated to an MPU access where bits 6:0 of the AMBA address bus are connected to the MPU address bus. The core can be configured to connect to a 16-bit MPU interface or a 8-bit MPU interface. When the core is connected to a 8-bit MPU interface it can emulate 16bit mode by translating 16-bit (half-word) AMBA accesses into two 8-bit MPU accesses. The mode to use is decided at implementation time via the VHDL generic mode. The core does not perform any checks on the size of the AMBA access and software should only make half-word (16-bit), or byte (8-bit) depending on the setting of VHDL generic mode, accesses to the core’s memory area. Any other access size will be accepted by the core but the operation may not have the desired result. On AMBA writes the core uses address bit 1 (or address bits 1:0 for 8-bit mode) to select if it should propagate the high or the low part of the AMBA data bus to the MPU data bus. On read operations the core will propagate the read MPU data to all parts of the AMBA data bus. It is recommended to set the mode VHDL generic to 2 for 8-bit MPU interfaces, and to 0 for 16-bit MPU interfaces. This way software can always assume that it communicates via a 16-bit MPU interface (accesses to the System ACE BUSMODEREG register are overriden by the core with suitable values when mode is set to 2). 34.2.3 Clocking and synchronization The core has two clock inputs; the AMBA clock and the System ACE clock. The AMBA clock drives the AHB slave interface and the System ACE clock drives the System ACE interface state machine. GRIP, Apr 2018, Version 2018.1 381 www.cobham.com/gaisler GRLIB IP Core All signals crossing between the two clock domains are synchronized to prevent meta-stability. The system clock should have a higher frequency than the System ACE clock. 34.2.4 Endianness The core is designed for big-endian systems. 34.3 Registers The core does implement any registers accessible via AMBA. 34.4 Vendor and device identifier The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x067. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 34.5 Implementation 34.5.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. 34.5.2 Technology mapping The core does not instantiate any technology specific primitives. 34.5.3 RAM usage The core does not use any RAM components. 34.6 Configuration options Table 412 shows the configuration options of the core (VHDL generics). Table 412.Configuration options Generic name Function Allowed range Default hindex AHB slave index 0 - (NAHBSLV-1) 0 hirq Interrupt line 0 - (NAHBIRQ-1) 0 haddr ADDR field of the AHB BAR0 0 - 16#FFF# 16#000# hmask MASK field of the AHB BAR0 0 - 16#FFF# 16#FFF# split If this generic is set to 1 the core will issue AMBA SPLIT responses when it is busy performing an access to the System ACE. Otherwise the core will insert wait states until the operation completes. 0-1 0 Note that SPLIT support on the AHBCTRL core MUST be enabled if this generic is set to 1. swap If this generic is set to 0 the core will connect the System ACE data(15:0) to AMBA data(15:0). If this generic is set to 1, the core will swap the System ACE data line and connect: System ACE data(15:8) <-> AMBA data(7:0) System ACE data(7 :0) <-> AMBA data(15:8). This generic only has effect for mode = 0. 0-1 0 oepol Polarity of pad output enable signal 0-1 0 GRIP, Apr 2018, Version 2018.1 382 www.cobham.com/gaisler GRLIB IP Core Table 412.Configuration options Generic name mode Function Allowed range Default Bus width mode 0-2 0 0: Core is connected to 16-bit MPU. Only half-word AMBA accesses should be made to the core. 1: Core is connected to 8-bit MPU. Only byte AMBA accesses should be made to the core. 2: Core is connected to 8-bit MPU but will emulate a 16bit MPU interface. Only half-word AMBA accesses should be made to the core (recommended setting for 8bit MPU interfaces). 34.7 Signal descriptions Table 413 shows the interface signals of the core (VHDL ports). Table 413.Signal descriptions Signal name Field Type Function Active RSTN N/A Input Reset Low CLK N/A Input Clock - CLKACE N/A Input System ACE clock - AHBSI * Input AHB slave input signals - AHBSO * Output AHB slave output signals - ACEI DI(15:0) Input Data line - IRQ Input System ACE interrupt request High ADDR(6:0) Output System ACE address - DO(15:0) Output Data line - CEN Output System ACE chip enable Low WEN Output System ACE write enable Low OEN Output System ACE output enable Low DOEN Output Data line output enable - ACEO * see GRLIB IP Library User’s Manual 34.8 Signal definitions and reset values The signals and their reset values are described in table 414. Table 414.Signal definitions and reset values Signal name Type Function Active Reset value d[15:0] InputOutput System ACE data line - - irq Input System ACE interrupt request Logical 1 - addr[6:0] Output System ACE address - - cen Output System ACE chip enable Logical 0 - wen Output System ACE write enable Logical 0 - oen Output System ACE output enable Logical 0 - GRIP, Apr 2018, Version 2018.1 383 www.cobham.com/gaisler GRLIB IP Core 34.9 Library dependencies Table 415 shows the libraries used when instantiating the core (VHDL libraries). Table 415.Library dependencies Library Package Imported unit(s) Description GAISLER MISC Component, signals Component and signal definitions GRLIB AMBA Signals AMBA signal definitions 34.10 Instantiation This example shows how the core can be instantiated. library ieee; use ieee.std_logic_1164.all; library grlib, techmap; use grlib.amba.all; use techmap.gencomp.all; library gaisler; use gaisler.misc.all; entity gracectrl_ex is port ( clk : in std_ulogic; clkace : in std_ulogic; rstn : in std_ulogic; sace_a : out std_logic_vector(6 downto 0); sace_mpce : out std_ulogic; sace_d : inout std_logic_vector(15 downto 0); sace_oen : out std_ulogic; sace_wen : out std_ulogic; sace_mpirq : in std_ulogic; ); end; architecture rtl of gracectrl_ex is -- AMBA signals signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); ... -- GRACECTRL signals signal acei : gracectrl_in_type; signal aceo : gracectrl_out_type; begin -- AMBA Components are instantiated here ... -- GRACECTRL core is instantiated below grace0 : gracectrl generic map (hindex => 4, hirq => 4, haddr => 16#002#, hmask => 16#fff#, split => 1) port map (rstn, clk, ahbsi, ahbso(4), acei, acoo); sace_a_pads : outpadv generic map (width => 7, tech => padtech) port map (sace_a, aceo.addr); sace_mpce_pad : outpad generic map(tech => padtech) port map (sace_mpce, aceo.cen); sace_d_pads : iopadv generic map (tech => padtech, width => 16) port map (sace_d, aceo.do, aceo.doen, aceo.di); sace_oen_pad : outpad generic map (tech => padtech) port map (sace_oen, aceo.oen); sace_wen_pad : outpad generic map (tech => padtech) port map (sace_wen, aceo.wen); sace_mpirq_pad : inpad generic map (tech => padtech) port map (sace_mpirq, acei.irq); GRIP, Apr 2018, Version 2018.1 384 www.cobham.com/gaisler GRLIB IP Core end; GRIP, Apr 2018, Version 2018.1 385 www.cobham.com/gaisler GRLIB IP Core 35 GRAES - Advanced Encryption Standard 35.1 Overview The Advanced Encryption Standard (AES) is a symmetric encryption algorithm for high throughput application (like audio or video streams). The GRAES core implements the AES-128 algorithm, supporting the Electronic Codebook (ECB) method. The AES-128 algorithm is specified in the “Advanced Encryption Standard (AES)” document, Federal Information Processing Standards (FIPS) Publication 197. The document is established by the National Institute of Standards and Technology (NIST). The core provides the following internal AMBA AHB slave interface, with sideband signals as per [GRLIB] including: • interrupt bus • configuration information • diagnostic information The core can be partition in the following hierarchical elements: • Advanced Encryption Standard (AES) core • AMBA AHB slave • GRLIB plug&play wrapper Note that the core can also be used without the GRLIB plug&play information. 35.2 Operation The input and output for the AES algorithm each consist of sequences of 128 bits (digits with values of 0 or 1). These sequences will sometimes be referred to as blocks and the number of bits they contain will be referred to as their length. The cipher key for the AES-128 algorithm is a sequence of 128 bits (can also be 192 or 256 bits for other algorithms). To transfer a 128 bit key or data block four write operations are necessary since the bus interface is 32 bit wide. After supplying a “key will be input” command to the control register, the key is input via four registers. After supplying a “data will be input” command to the control register, the input data is written via four registers. After the last input data register is written, the encryption or decryption is started. The progress can be observed via the debug register. When the operation is completed, an interrupt is generated. The output data is then read out via four registers. Note that the above sequence must be respected. It is not required to write a new key between each data input. There is no command needed for reading out the result. The implementation requires around 89 clock cycles for a 128 bit data block in encryption direction and around 90 clock cycles for decryption direction. For decryption an initial key calculation is required. This takes around 10 additional clock cycles per every new key. Typically large amounts of data are decrypted (and also encrypted) with the same key. The key initialization for the decryption round does not influence the throughput. 35.3 Background The Federal Information Processing Standards (FIPS) Publication Series of the National Institute of Standards and Technology (NIST) is the official series of publications relating to standards and guidelines adopted and promulgated under the provisions of the Information Technology Management Reform Act. GRIP, Apr 2018, Version 2018.1 386 www.cobham.com/gaisler GRLIB IP Core The Advanced Encryption Standard (AES) standard specifies the Rijndael algorithm, a symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, and 256 bits. Rijndael was designed to handle additional block sizes and key lengths, however they are not adopted in this standard. 35.4 AES-128 parameters The GRAES core implements AES-128. An AES algorithm is defined by the following parameters according to FIPS-197: • Nk number of 32-bit words comprising the cipher key • Nr number of rounds The AES-128 algorithm is specified as Nk=4 and Nr=10. The GRAES core has been verified against the complete set of Known Answer Test vectors included in the AES Algorithm Validation Suite (AESAVS) from National Institute of Standards and Technology (NIST), Information Technology Laboratory, Computer Security Division. 35.5 Throughput The data throughput for the GRAES core is around 128/90 bits per clock cycle, i.e. approximately 1.4 Mbits per MHz. The underlaying AES core has been implemented in a dual crypto chip on 250 nm technology as depicted in the figure below. The throughput at 33 MHz operating frequency was 42 Mbit/s, the power consumption was 9,6 mW, and the size was 14,5 kgates. Figure 118. Dual Crypto Chip 35.6 Characteristics The GRAES core has been synthesized for a Xilinx Virtex-2 XC2V6000-4 devices with the following results: • LUTs: 5040 (7%) • 256x1 ROMs (ROM256X1): 128 GRIP, Apr 2018, Version 2018.1 387 www.cobham.com/gaisler GRLIB IP Core • 35.7 Frequency:125 MHz Registers The core is programmed through registers mapped into AHB I/O address space. Table 416.GRAES registers AHB I/O address offset Register 0x00 Control Register 0x10 Data Input 0 Register 0x14 Data Input 1 Register 0x18 Data Input 2 Register 0x1C Data Input 3 Register 0x20 Data Output 0 Register 0x24 Data Output 1 Register 0x28 Data Output 2 Register 0x2C Data Output 3 Register 0x3C Debug Register 35.7.1 Control Register Table 417.0x00 - CTRL - Control Register 31 1 0 RESERVED DE C KE Y - - - w w w 31-2: 1: 0: 2 DEC KEY Unused 0 = “encrypt”, 1 = “decrypt” (only relevant when KEY=1) 0 = “data will be input”, 1 = “key will be input”  Note that the Data Input Registers cannot be written before a command is given to the Control Register. Note that the Data Input Registers must then be written in sequence, and all four registers must be written else the core ends up in an undefined state. The KEY bit determines whether a key will be input (KEY=1), or data will be input (KEY=0). When a “key will be input” command is written, the DEC bit determines whether decryption (DEC=1) or encryption (DEC=0) should be applied to the subsequent data input. Note that the register cannot be written after a command has been given, until the specific operation completes. A write access will be terminated with an AMBA AHB error response till the Data Input Register 3 has been written, and the with an AMBA AHB retry response till the operation completes. Any read access to this register results in an AMBA AHB error response. GRIP, Apr 2018, Version 2018.1 388 www.cobham.com/gaisler GRLIB IP Core 35.7.2 Debug Register (R) Table 418.0x3C - DEBUG - Debug Register 31 0 FSM r 31-0: FSM Finite State Machine Any write access to this register results in an AMBA AHB error response. 35.7.3 Data Input Registers (W) Table 419.0x10 - DATAI0 - Data Input 0 Register 31 0 Data/Key(127 downto 96) w Table 420.0x14 - DATAI1 - Data Input 1 Register 31 0 Data/Key(95 downto 64) w Table 421.0x18 - DATAI2 - Data Input 2 Register 31 0 Data/Key(63 downto 32) w Table 422.0x1C - DATAI3 - Data Input 3 Register 31 0 Data/Key(31 downto 0) w Note that these registers can only be written with a key after a “key will be input” command has been written to the control register. Note that the registers must then be written in sequence, and all four registers must be written else the core ends up in an undefined state. Note that these registers can only be written with data after a “data will be input” command has been written to the control register, else an AMBA AHB error response is given. Note that the registers must then be written in sequence and all four registers must be written else the core ends up in an undefined state. The encryption or decryption operation is started when the Data Input 3 Register is written to with data. GRIP, Apr 2018, Version 2018.1 389 www.cobham.com/gaisler GRLIB IP Core 35.7.4 Data Output Registers (R) Table 423.0x20 - DATAO0 - Data Output 0 Register 31 0 Data(127 downto 96) r* Table 424.0x24 - DATAO1 - Data Output 1 Register 31 0 Data(95 downto 64) r* Table 425.0x28 - DATAO2 - Data Output 2 Register 31 0 Data(63 downto 32) r* Table 426.0x2C - DATAO3 - Data Output 3 Register 31 0 Data(31 downto 0) r* Note that these registers can only be read after encryption or decryption has been completed. An AMBA AHB retry response is given to read accesses that occur while the encryption or decryption is in progress. If a read access is attempted before an encryption or decryption has even been initiated, then an AMBA AHB erro response is given. Write accesses to these registers result in an AMBA AHB error response. 35.8 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x073. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 35.9 Configuration options Table 427 shows the configuration options of the core (VHDL generics). Table 427.Configuration options Generic Function Allowed range Default hindex AHB slave index 0 - NAHBSLV-1 0 ioaddr Addr field of the AHB I/O BAR 0 - 16#FFF# 0 iomask Mask field of the AHB I/O BAR 0 - 16#FFF# 16#FFC# hirq Interrupt line used by the GRAES 0 - NAHBIRQ-1 0 GRIP, Apr 2018, Version 2018.1 390 www.cobham.com/gaisler GRLIB IP Core 35.10 Signal descriptions Table 428 shows the interface signals of the core (VHDL ports). Table 428.Signal descriptions Signal name Field Type Function Active RSTN N/A Input Reset Low CLK N/A Input Clock - AHBI * Input AHB slave input signals - AHBO * Output AHB slave output signals - DEBUG[0:4] N/A Output Debug information - * see GRLIB IP Library User’s Manual Note that the AES core can also be used without the GRLIB plug&play information. The AMBA AHB signals are then provided as IEEE Std_Logic_1164 compatible scalars and vectors. 35.11 Library dependencies Table 429 shows libraries used when instantiating the core (VHDL libraries). Table 429.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER CRYPTO Component GRAES component declarations 35.12 Instantiation This example shows how the core can be instantiated. library use ieee; ieee.std_logic_1164.all; library use grlib; grlib.amba.all; library gaisler; use gaisler.crypto.all; ... ... signal debug: std_logic_vector(0 to 4); .. .. GRAES0: graes generic map ( hindex => hindex, ioaddr => ioaddr, iomask => iomask, hirq => hirq) port map ( rstn => rstn, clk => clk, ahbi => ahbsi, ahbo => ahbso(hindex), debug => debug); GRIP, Apr 2018, Version 2018.1 391 www.cobham.com/gaisler GRLIB IP Core 36 GRAES_DMA - Advanced Encryption Standard with DMA 36.1 Overview The Advanced Encryption Standard (AES) is a symmetric encryption algorithm for high throughput applications (like audio or video streams). The GRAES_DMA core implements the AES algorithm with 256-bit key length using CTR mode of operation. The AES algorithm is specified in the “Advanced Encryption Standard (AES)” document, Federal Information Processing Standards (FIPS) Publication 197. The document is established by the National Institute of Standards and Technology (NIST). DMA is used for efficiently transferring plaintext and ciphertext to the cryptographic core with minimum CPU involvement. The core provides an AMBA AHB master interface, with sideband signals as per [GRLIB] including: • interrupt bus • configuration information • diagnostic information The core can be partition in the following hierarchical elements: 36.2 • Advanced Encryption Standard (AES) core • AMBA AHB master Operation The input and output for the AES algorithm each consist of sequences of 128 bits (digits with values of 0 or 1). These sequences will sometimes be referred to as blocks and the number of bits they contain will be referred to as their length. The cipher key for the AES algorithm supported in this core is a sequence of 256 bits. To encrypt a message a descriptor must be setup. It contains pointers to memory locations where the key, initialization vector and plaintext are located. The memory addresses for the key and initialization vector must be word aligned while the plaintext can start at any address. If the previous key and/ or init vector are to be reused there are control bits in the descriptor which can be used to make the core skip the fetching of the respective pointers and also subsequently skip the fetching of the actual key and initvector. Currently the initvector and key always have to be loaded for the core to operate correctly. The core can also read the key and initialization vector from input signals. This is done by setting the keyvector and initvector address pointers to all ones. When one or more descriptors have been enabled the core can be enabled and it will automatically start fetching the necessary values from memory, split the data into the required blocks, encrypt/ decrypt and finally write back the result to memory. When each descriptor is finished the core will set the enable bit to 0. An interrupt can also optionally be generated. The result of the encryption or decryption can be either written back to the same memory address from where the plain or ciphertext was read or to a different location specified in an additional pointer. The layout of the descriptor is shown in the tables below. Table 430.GRAES_DMA descriptor word 0 (address offset 0x0) 31 21 20 8 LEN RESERVED 7 6 5 4 3 KE IV DO ED MD 2 1 0 IE EN 31: 21 Length (LEN) - Length in bytes of message to process 20: 8 RESERVED 7 Key (KE) - When set a new key will be fetched and used from the memory address set in the key address descriptor word. If not set the currently stored key is used and the key adddress word should not be included in the descriptor. GRIP, Apr 2018, Version 2018.1 392 www.cobham.com/gaisler GRLIB IP Core Table 430.GRAES_DMA descriptor word 0 (address offset 0x0) 6 Initialization vector (IV) - When set a new initialization vectir will be fetched and used from the memory address set in the initialization vector address descriptor word. If not set the currently stored initialization vector is used and the initialization vector adddress word should not be included in the descriptor. 5 Dataout (DO) - When set the encrypted/decrypted output will be written to the memory address specified in the dataout descriptor word. Otherwise data is written to the same memory address from where the original plaintext/ciphertext was fetched and the dataout address word should not be included in the descriptor. 4 Encrypt-decrypt (ED) - If set to one encryption will be performed otherwise decryption 3 RESERVED 2 RESERVED 1 Interrupt enable (IE) - When set an interrupt will be generated when the processing of the current enabled descriptor is finished and the interrupt enable bit in the control register is set. It should be noted that, the enable bit in the control register might not be cleared yet when a finish interrupt is generated for the last descriptor because the core will read the next descriptor and stop after encountering a ‘0’ on the descriptor control word enable bit which takes some clock cycles. 0 Enable (EN) - When set to ‘1’ indicates that descriptor is enabled and the GRAES core will process it. After the processing is finished this bit will be cleared and the core will jump to the next register. It should be noted that this bit will not be cleared in case a DMA error is encountered at any point of the processing of the current descriptor. If this bit is clear on the first read from the GRAES_DMA core the core will stop processing. Table 431.GRAES_DMA descriptor word 1 (address offset 0x4) 31 0 Data input address 31: 0 Data input address - Memory address pointer where plaintext/ciphertext for encryption/descryption is located. Table 432.GRAES_DMA descriptor word 2( address offset 0x8 if DO is set, otherwise not exist) 31 2 1 0 Dataout address 31: 2 Dataout address - Memory address where encrypted/decrypted data shall be stored. If the data should be stored at the same location as the input data (DO bit in word 0 is 0) then this word shall not be included in the descriptor. 1: 0 Reserved Table 433.GRAES_DMA descriptor word 3( address offset 0xC if DO and IV is set; address offset 0x8 if DO is clear and IV is set; otherwise not exist.) 31 2 1 0 IV address 31: 2 Initialization vector address - Memory address where initialization vector is located. If a new initvector is not needed (IV bit in word 0 is 0) then this word shall not be included in the descriptor. If this value is set to 0xFFFFFFFF then the core will take the initialization value from the ivin input signal instead. 1: 0 Must be set to zero unless the init value shall be taken from signal input. Table 434.GRAES_DMA descriptor word 4(address offset 0x10 if DO, IV and KEY is set; address offset 0xC if one of the following bits are set and one of them is clear (DO, IV) and KEY is set; address offset 0x8 if DO and IV is clear and KEY is set; otherwise not exist) 31 2 1 0 Key address GRIP, Apr 2018, Version 2018.1 393 www.cobham.com/gaisler GRLIB IP Core Table 434.GRAES_DMA descriptor word 4(address offset 0x10 if DO, IV and KEY is set; address offset 0xC if one of the following bits are set and one of them is clear (DO, IV) and KEY is set; address offset 0x8 if DO and IV is clear and KEY is set; otherwise not exist) 31: 2 Key address - Memory address where key is located. If a new key is not needed (KE bit in word 0 is 0) then this word shall not be included in the descriptor. If this value is set to 0xFFFFFFFF then the core will take the key value from the keyin input signal instead. 1: 0 Must be set to zero unless the init value shall be taken from signal input. Table 435.GRAES_DMA descriptor word 5(address offset 0x14 if DO,IV, KEY is set; address offset 0x10 if two of the following bits are set and one of them is clear (DO,IV,KEY); address offset 0xC if two of the following bits are clear and one of them is set (DO,IV,KEY); address offset 0x8 if DO,IV, and KEY is clear) 31 2 1 0 Next descriptor 31: 2 Next descriptor address - Memory address to the next descriptor. 1: 0 Reserved The descriptor control word should be written last. If one or more words are not included the offsets of the following words should be adjusted accordingly. 36.3 Background The Federal Information Processing Standards (FIPS) Publication Series of the National Institute of Standards and Technology (NIST) is the official series of publications relating to standards and guidelines adopted and promulgated under the provisions of the Information Technology Management Reform Act. The Advanced Encryption Standard (AES) standard specifies the Rijndael algorithm, a symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, and 256 bits. Rijndael was designed to handle additional block sizes and key lengths, however they are not adopted in this standard. 36.4 Characteristics The GRAES_DMA core has been synthesized for a Actel AX2000-std device with the following results: 36.5 • Combinational Cells: 9364 of 21504 (44%) • Sequential Cells: • Total Cells: 11738 of 32256 (37%) • Block Rams : 0 of 64 (0%) • Frequency:60 MHz 2374 of 10752 (22%) Endianness The core is designed for big-endian systems. GRIP, Apr 2018, Version 2018.1 394 www.cobham.com/gaisler GRLIB IP Core 36.6 Registers The core is programmed through registers mapped into APB address space. Table 436.GRAES_DMA registers APB address offset Register 0x0 Control 0x4 Status 0x8 Descriptor address GRIP, Apr 2018, Version 2018.1 395 www.cobham.com/gaisler GRLIB IP Core 36.6.1 Control Register Table 437.0x00 - CTRL - GRAES_DMA control register 31 4 RESERVED 3 2 1 0 AB IOE KS IE EN 0 0 r rw rw rw rw rw 0 0 0 0 31: 5 RESERVED 4 Abort (AB) - If set to ‘1’ the core will stop processing after reaching a new descriptor and it will selfclear the Abort and Enable (bit-0) bits. The software can check the status of Abort or Enable bits after setting the Abort bit to see when the core becomes idle.It should be noted that if the last descriptor that is processed when abort bit is set causes a DMA error the DMA error status bit will be set so the software has to make sure to handle a potential error after abort. This bit can only be written if it is clear. Reset value : ‘0’ 3 Interrupt On Error (IOE)- If set to ‘1’ then the core will generate an interrupt when an DMA error is encountered. This bit is independent from the bit-1 (IE). Read the section related to DMA error handling for further details about error handling. This bit can only be written if enable bit is clear.Reset value : ‘0’ 2 Keysize (KS) - If set to ‘1’ then the core will use 128 bit key length. Otherwise the core makes use of 256 bit key length. This bit can only be written if enable bit is clear.Reset value : ‘0’ 1 Interrupt Enable (IE) - If set, an interrupt is generated each time a message has been decrypted. This bit can only be written if enable bit is clear.Reset value: ‘0’. 0 Enable (EN) - Write a one to this bit each time new descriptors are activated in the list. Writing a one will cause the core to read a new descriptor and perform the requested operation. This bit is automatically cleared when the core encounters a descriptor which is not enabled or if a DMA error is encountered. This bit can not be set when the error bit in the status register is set. Software has to clear the error bit in the status register to be able to set the Enable bit again. Read the Status Register section for more details. This bit can only be written when it is clear but it can initiate the processing of the last descriptor again in certain conditions to allow dynamic addition of descriptors to the link list. For further details read the descriptor processing section. Reset value: ‘0’ 36.6.2 Status Register Table 438.0x04 - STAT - GRAES_DMA status register 31 0 RESERVED ER 0 0 r rw 31: 1 RESERVED 0 Error (ER) - The bit is automatically set to 1 when a DMA error is encountered. When it is set, the enable bit in the ctrl register is locked and can not be set until the error bit is cleared. The error bit is cleared by writing ‘1’ to it. 36.6.3 Descriptor Address Table 439.0x08 - ADDR - GRAES_DMA Descriptor address 31 2 1 0 Descriptor address R 0 0 rw r 31: 2 Current descriptor address - Points to current descriptor. Can be initialized with a new pointer when the core is disabled. Is updated by the core while it is progressing through the list of descriptors. 1: 0 RESERVED GRIP, Apr 2018, Version 2018.1 396 www.cobham.com/gaisler GRLIB IP Core 36.7 Descriptor Processing Software should set up the descriptor or descriptor chain as it described in the operation section. There are two ways to finish the processing of a descriptor or a descriptor chain. First way is to link the next descriptor to itself for the last descriptor in the chain. After processing, the enable bit of the descriptor control word is automatically cleared so if the next descriptor points to itself the enable bit will be cleared and when read again and the core will stop. Another way is to allocate an empty pointer in which the enable bit of the descriptor word is cleared and link it as a last descriptor. It should be noted that when an empty pointer is allocated, size of it should be equal to the maximum possible size ( 6 words), although the content of the unused words does not matter as soon as the descriptor is not enabled. If interrupt enable bit is set, an interrupt will be generated after processing an enabled descriptor. But it should be noted that after an interrupt is generated for the last enabled descriptor in the chain, the enable bit in the control word might not be cleared yet due to core being started to process the next descriptor in which it encounters a cleared enable bit and clears the enable bit in the control register. If the software updates the last disabled pointer in the list and enables it while the core is running, and sets the enable bit in the control register while it is already set and it was reading the last pointer, the core will reprocess the last descriptor if the descriptor enable bit was cleared (it did not read the updated descriptor control word), to make sure operation to continue. If the software makes this modification and sets the enable bit in the control register while it was set, then the core will anyway continue operation because it will read the last descriptor as enabled. This feature allows for safe dynamic addition of descriptors to the list while processing is ongoing. It should be noted the control word of a descriptor should always be written last. The core will immediately stop processing on an DMA error and software has to take certain steps which are explained in the next section (Error Handling). 36.8 Error Handling If the core encounters a DMA error, the processing will be immediately stopped (enable bit in the core control register will be cleared) and the error bit in the status register will be set. If interrupt on error is enabled an interrupt will also be generated regardless of interrupt enable bit is set on the descriptor control word. When the error bit in the status register is set, the descriptor address that resides in the descriptor address register is the descriptor that caused the DMA error. It should be noted that the enable bit in the descriptor control word will not be cleared during error. In addition, the enable bit in the control word will be locked if the error bit in the status register is set. So after an error the software has to clear the error bit by writing ‘1’ to the position of error bit in the status register. The software should check the status of error bit after the processing of a descriptor chain is finished ( en bit is cleared in the control register), to make sure no error has occurred and clear the error bit after an error in order to be able to proceed with the next operations. After an error is generated the software should either fix the problem related to the error in the descriptor or set the descriptor address to a new descriptor after clearing the error bit and before starting a new operation. Otherwise it can cause an infinite loop because the enable bit of the descriptor word which causes a DMA error is not automatically cleared and the descriptor address points to the failing descriptor when the core stops due to a DMA error. 36.9 Aborting Operation It is possible to abort the processing of descriptor at a certain point. When the abort bit in the core’s control word is set, the processing will stop when the current descriptor has finished processing. After GRIP, Apr 2018, Version 2018.1 397 www.cobham.com/gaisler GRLIB IP Core the abort operation has successfully finished the abort bit and enable bit in the core’s control word will be cleared. After finishing, the descriptor address register points to the descriptor which is not processed due to stopping. It should be noted that abort bit will not interrupt the processing of the current descriptor when it is set, hence it can not resolve a problem of unresponsive DMA. The abort bit can be used to make sure the core goes into idle state as soon as possible and does not create any transactions on the DMA bus anymore. 36.10 Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x07B. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 36.11 Implementation 36.11.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core will use asynchronous reset for all registers, if the GRLIB config package setting grlib_async_reset_enable is set. 36.12 Configuration options Table 440 shows the configuration options of the core (VHDL generics). Table 440.Configuration options Generic Function Allowed range Default hindex AHB master index 0 - NAHBMST-1 0 pindex APB slave index 0 - NAPBSLV-1 0 paddr Addr field of the APB BAR 0 - 16#FFF# 0 pmask Mask field of the APB BAR 0 - 16#FFF# 16#FFF# pirq Interrupt line used by the GRAES 0 - NAHBIRQ-1 0 extkeyiv Support key and IV initalization from signals. If this generic is 1 then the keyin and ivin signals can be used to set key and IV values. 0-1 0 scantest Enable SCAN test support 0-1 0 GRIP, Apr 2018, Version 2018.1 398 www.cobham.com/gaisler GRLIB IP Core 36.13 Signal descriptions Table 441 shows the interface signals of the core (VHDL ports). Table 441.Signal descriptions Signal name Field Type Function Active RSTN N/A Input Reset Low CLK N/A Input Clock - AHBI * Input AHB master input signals - AHBO * Output AHB master output signals - APBI * Input APB slave input signals - APBO * Output APB slave output signals - KEYIN[255:0] N/A Input Alternative key input - IVIN[127:0] N/A Input Alternative IV input - * see GRLIB IP Library User’s Manual 36.14 Library dependencies Table 442 shows libraries used when instantiating the core (VHDL libraries). Table 442.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER CRYPTO Component GRAES component declarations 36.15 Instantiation This example shows how the core can be instantiated. entity graes_dma_tb is generic( hindex: in pindex: in paddr: in pmask: in pirq: in Integer Integer Integer Integer Integer := := := := := 0; 0; 0; 16#fff#; 1); end entity graes_dma_tb; signal signal signal signal signal signal rstn: clk: apbi: apbo: ahbmi: ahbmo: graes0: graes_dma generic map( hindex pindex paddr pmask pirq port map( rstn clk ahbi GRIP, Apr 2018, Version 2018.1 std_ulogic := ’0’; std_ulogic := ’0’; apb_slv_in_type; apb_slv_out_vector := (others => apb_none); ahb_mst_in_type; ahb_mst_out_vector := (others => ahbm_none); => => => => => hindex, pindex, paddr, pmask, pirq) => rstn, => clk, => ahbmi, 399 www.cobham.com/gaisler GRLIB IP Core ahbo apbi apbo GRIP, Apr 2018, Version 2018.1 => ahbmo(hindex), => apbi, => apbo(pindex)); 400 www.cobham.com/gaisler GRLIB IP Core 37 GRCAN - CAN 2.0 Controller with DMA 37.1 Overview The CAN controller is assumed to operate in an AMBA bus system where both the AMBA AHB bus and the APB bus are present. The AMBA APB bus is used for configuration, control and status handling. The AMBA AHB bus is used for retrieving and storing CAN messages in memory external to the CAN controller. This memory can be located on-chip, as shown in the block diagram, or external to the chip. The CAN controller supports transmission and reception of sets of messages by use of circular buffers located in memory external to the core. Separate transmit and receive buffers are assumed. Reception and transmission of sets of messages can be ongoing simultaneously. After a set of message transfers has been set up via the AMBA APB interface the DMA controller initiates a burst of read accesses on the AMBA AHB bus to fetch messages from memory, which are performed by the AHB master. The messages are then transmitted by the CAN core. When a programmable number of messages have been transmitted, the DMA controller issues an interrupt. After the reception has been set up via the AMBA APB interface, messages are received by the CAN core. To store messages to memory, the DMA controller initiates a burst of write accesses on the AMBA AHB bus, which are performed by the AHB master. When a programmable number of messages have been received, the DMA controller issues an interrupt. The CAN controller can detect a SYNC message and generate an interrupt, which is also available as an output signal from the core. The SYNC message identifier is programmable via the AMBA APB interface. Separate synchronisation message interrupts are provided. The CAN controller can transmit and receive messages on either of two CAN busses, but only on one at a time. The selection is programmable via the AMBA APB interface. DMA Controller FIFO CAN 2.0 Codec Physical Layer AMBA APB Slave Redundant CAN bus AMBA APB AMBA AHB Master Coding Layer Mux / DeMux AMBA AHB AMBA Layer Nominal CAN bus Note that it is not possible to receive a CAN message while transmitting one. GRCAN Figure 119. Block diagram 37.1.1 Function The core implements the following functions: • CAN protocol • Message transmission • Message filtering and reception GRIP, Apr 2018, Version 2018.1 401 www.cobham.com/gaisler GRLIB IP Core • SYNC message reception • Status and monitoring • Interrupt generation • Redundancy selection 37.1.2 Interfaces The core provides the following external and internal interfaces: • CAN interface • AMBA AHB master interface, with sideband signals as per [GRLIB] including: • cacheability information • interrupt bus • configuration information • diagnostic information • AMBA APB slave interface, with sideband signals as per [GRLIB] including: • interrupt bus • configuration information • diagnostic information 37.1.3 Hierarchy The CAN controller core can be partitioned in the following hierarchical elements: 37.2 • CAN 2.0 Core • Redundancy Multiplexer / De-multiplexer • Direct Memory Access controller • AMBA APB slave • AMBA AHB master Interface The external interface towards the CAN bus features two redundant pairs of transmit output and receive input (i.e. 0 and 1). The active pair (i.e. 0 or 1) is selectable by means of a configuration register bit. Note that all reception and transmission is made over the active pair. For each pair, there is one enable output (i.e. 0 and 1), each being individually programmable. Note that the enable outputs can be used for enabling an external physical driver. Note that both pairs can be enabled simultaneously. Note that the polarity for the enable/inhibit inputs on physical interface drivers differs, thus the meaning of the enable output is undefined. Redundancy is implemented by means of Selective Bus Access. Note that the active pair selection above provides means to meet this requirement. 37.3 Protocol The CAN protocol is based on a CAN 2.0 controller VHDL core. The CAN controller complies with CAN Specification Version 2.0 Part B, except for the overload frame generation. Note that there are three different CAN types generally defined: • 2.0A, which considers 29 bit ID messages as an error GRIP, Apr 2018, Version 2018.1 402 www.cobham.com/gaisler GRLIB IP Core • 2.0B Passive, which ignores 29 bit ID messages • 2.0B Active, which handles 11 and 29 bit ID messages Only 2.0B Active is implemented. 37.4 Status and monitoring The CAN interface incorporates status and monitoring functionalities. This includes: • Transmitter active indicator • Bus-Off condition indicator • Error-Passive condition indicator • Over-run indicator • 8-bit Transmission error counter • 8-bit Reception error counter The status is available via a register and is also stored in a circular buffer for each received message. 37.5 Transmission The transmit channel is defined by the following parameters: • base address • buffer size • write pointer • read pointer The transmit channel can be enabled or disabled. 37.5.1 Circular buffer The transmit channel operates on a circular buffer located in memory external to the CAN controller. The circular buffer can also be used as a straight buffer. The buffer memory is accessed via the AMBA AHB master interface. Each CAN message occupies 4 consecutive 32-bit words in memory. Each CAN message is aligned to 4 words address boundaries (i.e. the 4 least significant byte address bits are zero for the first word in a CAN message). The size of the buffer is defined by the CanTxSIZE.SIZE field, specifying the number of CAN messages * 4 that fit in the buffer. E.g. CanTxSIZE.SIZE =2 means 8 CAN messages fit in the buffer. Note however that it is not possible to fill the buffer completely, leaving at least one message position in the buffer empty. This is to simplify wrap-around condition checking. E.g. CanTxSIZE.SIZE =2 means that 7 CAN messages fit in the buffer at any given time. 37.5.2 Write and read pointers The write pointer (CanTxWR.WRITE) indicates the position+1 of the last CAN message written to the buffer. The write pointer operates on number of CAN messages, not on absolute or relative addresses. The read pointer (CanTxRD.READ) indicates the position+1 of the last CAN message read from the buffer. The read pointer operates on number of CAN messages, not on absolute or relative addresses. GRIP, Apr 2018, Version 2018.1 403 www.cobham.com/gaisler GRLIB IP Core The difference between the write and the read pointers is the number of CAN messages available in the buffer for transmission. The difference is calculated using the buffer size, specified by the CanTxSIZE.SIZE field, taking wrap around effects of the circular buffer into account. Examples: • There are 2 CAN messages available CanTxWR.WRITE=2 and CanTxRD.READ=0. for transmit when CanTxSIZE.SIZE=2, • There are 2 CAN messages available for transmit when CanTxSIZE.SIZE=2, CanTxWR.WRITE =0 and CanTxRD.READ =6. • There are 2 CAN messages available for transmit when CanTxSIZE.SIZE=2, CanTxWR.WRITE =1 and CanTxRD.READ =7. • There are 2 CAN messages available for transmit when CanTxSIZE.SIZE=2, CanTxWR.WRITE =5 and CanTxRD.READ =3. When a CAN message has been successfully transmitted, the read pointer (CanTxRD.READ) is automatically incremented, taking wrap around effects of the circular buffer into account. Whenever the write pointer CanTxWR.WRITE and read pointer CanTxRD.READ are equal, there are no CAN messages available for transmission. 37.5.3 Location The location of the circular buffer is defined by a base address (CanTxADDR.ADDR), which is an absolute address. The location of a circular buffer is aligned on a 1kbyte address boundary. 37.5.4 Transmission procedure When the channel is enabled (CanTxCTRL.ENABLE=1), as soon as there is a difference between the write and read pointer, a message transmission will be started. Note that the channel should not be enabled if a potential difference between the write and read pointers could be created, to avoid the message transmission to start prematurely. A message transmission will begin with a fetch of the complete CAN message from the circular buffer to a local fetch-buffer in the CAN controller. After a successful data fetch, a transmission request will be forwarded to the CAN core. If there is at least an additional CAN message available in the circular buffer, a prefetch of this CAN message from the circular buffer to a local prefetch-buffer in the CAN controller will be performed. The CAN controller can thus hold two CAN messages for transmission: one in the fetch buffer, which is fed to the CAN core, and one in the prefetch buffer. After a message has been successfully transmitted, the prefetch-buffer contents are moved to the fetch buffer (provided that there is message ready). The read pointer (CanTxRD.READ) is automatically incremented after a successful transmission, i.e. after the fetch-buffer contents have been transmitted, taking wrap around effects of the circular buffer into account. If there is at least an additional CAN message available in the circular buffer, a new prefetch will be performed. If the write and read pointers are equal, no more prefetches and fetches will be performed, and transmission will stop. If the single shot mode is enabled for the transmit channel (CanTxCTRL.SINGLE=1), any message for which the arbitration is lost, or failed for some other reason, will lead to the disabling of the channel (CanTxCTRL.ENABLE=0), and the message will not be put up for re-arbitration. Interrupts are provided to aid the user during transmission, as described in detail later in this section. The main interrupts are the Tx, TxEmpty and TxIrq which are issued on the successful transmission of a message, when all messages have been transmitted successfully and when a predefined number of messages have been transmitted successfully. The TxLoss interrupt is issued whenever transmission arbitration has been lost, could also be caused by a communications error. The TxSync interrupt is issued when a message matching the SYNC Code Filter Register.SYNC and SYNC Mask Filter Reg- GRIP, Apr 2018, Version 2018.1 404 www.cobham.com/gaisler GRLIB IP Core ister.MASK registers is successfully transmitted. Additional interrupts are provided to signal error conditions on the CAN bus and AMBA bus. 37.5.5 Straight buffer It is possible to use the circular buffer as a straight buffer, with a higher granularity than the 1kbyte address boundary limited by the base address (CanTxADDR.ADDR) field. While the channel is disabled, the read pointer (CanTxRD.READ) can be changed to an arbitrary value pointing to the first message to be transmitted, and the write pointer (CanTxWR.WRITE) can be changed to an arbitrary value. When the channel is enabled, the transmission will start from the read pointer and continue to the write pointer. 37.5.6 AMBA AHB error Definition: • a message fetch occurs when no other messages is being transmitted • a message prefetch occurs when a previously fetched message is being transmitted • the local fetch buffer holds the message being fetched • the local prefetch buffer holds the message being prefetched • the local fetch buffer holds the message being transmitted by the CAN core • a successfully prefetched message is copied from the local prefetch buffer to the local fetch buffer when that buffer is freed after a successful transmission. An AHB error response occurring on the AMBA AHB bus while a CAN message is being fetched will result in a TxAHBErr interrupt. If the CanCONF.ABORT bit is set to 0b, the channel causing the AHB error will skip the message being fetched from memory and will increment the read pointer. No message will be transmitted. If the CanCONF.ABORT bit is set to 1b, the channel causing the AHB error will be disabled (CanTxCTRL.ENABLE is cleared automatically to 0 b). The read pointer can be used to determine which message caused the AHB error. Note that it could be any of the four word accesses required to read a message that caused the AHB error. If the CanCONF.ABORT bit is set to 1b, all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs, as indicated by the CanSTAT.AHBErr bit being 1b. The accesses will be disabled until the CanSTAT register is read, and automatically clearing bit CanSTAT.AHBErr. An AHB error response occurring on the AMBA AHB bus while a CAN message is being prefetched will not cause an interrupt, but will stop the ongoing prefetch and further prefetch will be prevented temporarily. The ongoing transmission of a CAN message from the fetch buffer will not be affected. When the fetch buffer is freed after a successful transmission, a new fetch will be initiated, and if this fetch results in an AHB error response occurring on the AMBA AHB bus, this will be handled as for the case above. If no AHB error occurs, prefetch will be allowed again. 37.5.7 Enable and disable When an enabled transmit channel is disabled (CanTxCTRL.ENABLE=0b), any ongoing CAN message transfer request will not be aborted until a CAN bus arbitration is lost or the message has been sent successfully. If the message is sent successfully, the read pointer (CanTxRD.READ) is automatically incremented. Any associated interrupts will be generated. The progress of the any ongoing access can be observed via the CanTxCTRL.ONGOING bit. The CanTxCTRL.ONGOING must be 0b before the channel can be re-configured safely (i.e. changing GRIP, Apr 2018, Version 2018.1 405 www.cobham.com/gaisler GRLIB IP Core address, size or read pointer). It is also possible to wait for the Tx and TxLoss interrupts described hereafter. The channel can be re-enabled again without the need to re-configure the address, size and pointers. Priority inversion is handled by disabling the transmitting channel, i.e. setting CanTxCTRL.ENABLE=0b as described above, and observing the progress, i.e. reading via the CanTxCTRL.ONGOING bit as described above. When the transmit channel is disabled, it can be reconfigured and a higher priority message can be transmitted. Note that the single shot mode does not require the channel to be disabled, but the progress should still be observed as above. No message transmission is started while the channel is not enabled. 37.5.8 Interrupts During transmission several interrupts can be generated: • TxLoss: Message arbitration lost for transmit (could be caused by communications error, as indicated by other interrupts as well) • TxErrCntr: Error counter incremented for transmit • TxSync: Synchronization message transmitted • Tx: Successful transmission of one message • TxEmpty: Successful transmission of all messages in buffer • TxIrq: Successful transmission of a predefined number of messages • TxAHBErr: AHB access error during transmission • Off: Bus-off condition • Pass: Error-passive condition The Tx, TxEmpty and TxIrq interrupts are only generated as the result of a successful message transmission, after the CanTxRD.READ pointer has been incremented. 37.6 Reception The receive channel is defined by the following parameters: • base address • buffer size • write pointer • read pointer The receive channel can be enabled or disabled. 37.6.1 Circular buffer The receive channel operates on a circular buffer located in memory external to the CAN controller. The circular buffer can also be used as a straight buffer. The buffer memory is accessed via the AMBA AHB master interface. Each CAN message occupies 4 consecutive 32-bit words in memory. Each CAN message is aligned to 4 words address boundaries (i.e. the 4 least significant byte address bits are zero for the first word in a CAN message). The size of the buffer is defined by the CanRxSIZE.SIZE field, specifying the number of CAN messages * 4 that fit in the buffer. E.g. CanRxSIZE.SIZE=2 means 8 CAN messages fit in the buffer. GRIP, Apr 2018, Version 2018.1 406 www.cobham.com/gaisler GRLIB IP Core Note however that it is not possible to fill the buffer completely, leaving at least one message position in the buffer empty. This is to simplify wrap-around condition checking. E.g. CanRxSIZE.SIZE=2 means that 7 CAN messages fit in the buffer at any given time. 37.6.2 Write and read pointers The write pointer (CanRxWR.WRITE) indicates the position+1 of the last CAN message written to the buffer. The write pointer operates on number of CAN messages, not on absolute or relative addresses. The read pointer (CanRxRD.READ) indicates the position+1 of the last CAN message read from the buffer. The read pointer operates on number of CAN messages, not on absolute or relative addresses. The difference between the write and the read pointers is the number of CAN message positions available in the buffer for reception. The difference is calculated using the buffer size, specified by the CanRxSIZE.SIZE field, taking wrap around effects of the circular buffer into account. Examples: • There are 2 CAN messages available for read-out when CanRxSIZE.SIZE=2, CanRxWR.WRITE=2 and CanRxRD.READ=0. • There are 2 CAN messages available for read-out when CanRxSIZE.SIZE=2, CanRxWR.WRITE =0 and CanRxRD.READ=6. • There are 2 CAN messages available for read-out when CanRxSIZE.SIZE=2, CanRxWR.WRITE =1 and CanRxRD.READ=7. • There are 2 CAN messages available for read-out when CanRxSIZE.SIZE=2, CanRxWR.WRITE =5 and CanRxRD.READ=3. When a CAN message has been successfully received and stored, the write pointer (CanRxWR.WRITE) is automatically incremented, taking wrap around effects of the circular buffer into account. Whenever the read pointer CanRxRD.READ equals (CanRxWR.WRITE+1) modulo (CanRxSIZE.SIZE*4), there is no space available for receiving another CAN message. The error behavior of the CAN core is according to the CAN standard, which applies to the error counter, buss-off condition and error-passive condition. 37.6.3 Location The location of the circular buffer is defined by a base address (CanRxADDR.ADDR), which is an absolute address. The location of a circular buffer is aligned on a 1kbyte address boundary. 37.6.4 Reception procedure When the channel is enabled (CanRxCTRL.ENABLE=1), and there is space available for a message in the circular buffer (as defined by the write and read pointer), as soon as a message is received by the CAN core, an AMBA AHB store access will be started. The received message will be temporarily stored in a local store-buffer in the CAN controller. Note that the channel should not be enabled until the write and read pointers are configured, to avoid the message reception to start prematurely After a message has been successfully stored the CAN controller is ready to receive a new message. The write pointer (CanRxWR.WRITE) is automatically incremented, taking wrap around effects of the circular buffer into account. Interrupts are provided to aid the user during reception, as described in detail later in this section. The main interrupts are the Rx, RxFull and RxIrq which are issued on the successful reception of a message, when the message buffer has been successfully filled and when a predefined number of messages have been received successfully. The RxMiss interrupt is issued whenever a message has been received but does not match a message filtering setting, i.e. neither for the receive channel nor for the SYNC message described hereafter. GRIP, Apr 2018, Version 2018.1 407 www.cobham.com/gaisler GRLIB IP Core The RxSync interrupt is issued when a message matching the SYNC Code Filter Register.SYNC and SYNC Mask Filter Register.MASK registers has been successfully received. Additional interrupts are provided to signal error conditions on the CAN bus and AMBA bus. 37.6.5 Straight buffer It is possible to use the circular buffer as a straight buffer, with a higher granularity than the 1kbyte address boundary limited by the base address (CanRxADDR.ADDR) field. While the channel is disabled, the write pointer (CanRxWR.WRITE) can be changed to an arbitrary value pointing to the first message to be received, and the read pointer (CanRxRD.READ) can be changed to an arbitrary value. When the channel is enabled, the reception will start from the write pointer and continue to the read pointer. 37.6.6 AMBA AHB error An AHB error response occurring on the AMBA AHB bus while a CAN message is being stored will result in an RxAHBErr interrupt. If the CanCONF.ABORT bit is set to 0b, the channel causing the AHB error will skip the received message, not storing it to memory. The write pointer will be incremented. If the CanCONF.ABORT bit is set to 1b, the channel causing the AHB error will be disabled (CanRxCTRL.ENABLE is cleared automatically to 0b). The write pointer can be used to determine which message caused the AHB error. Note that it could be any of the four word accesses required to writ a message that caused the AHB error. If the CanCONF.ABORT bit is set to 1b, all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs, as indicated by the CanSTAT.AHBErr bit being 1b. The accesses will be disabled until the CanSTAT register is read, and automatically clearing bit CanSTAT.AHBErr. 37.6.7 Enable and disable When an enabled receive channel is disabled (CanRxCTRL.ENABLE=0b), any ongoing CAN message storage on the AHB bus will not be aborted, and no new message storage will be started. Note that only complete messages can be received from the CAN core. If the message is stored successfully, the write pointer (CanRxWR.WRITE) is automatically incremented. Any associated interrupts will be generated. The progress of the any ongoing access can be observed via the CanRxCTRL.ONGOING bit. The CanRxCTRL.ONGOING must be 0b before the channel can be re-configured safely (i.e. changing address, size or write pointer). It is also possible to wait for the Rx and RxMiss interrupts described hereafter. The channel can be re-enabled again without the need to re-configure the address, size and pointers. No message reception is performed while the channel is not enabled 37.6.8 Interrupts During reception several interrupts can be generated: • RxMiss: Message filtered away for receive • RxErrCntr: Error counter incremented for receive • RxSync: Synchronization message received • Rx: Successful reception of one message • RxFull: Successful reception of all messages possible to store in buffer GRIP, Apr 2018, Version 2018.1 408 www.cobham.com/gaisler GRLIB IP Core • RxIrq: Successful reception of a predefined number of messages • RxAHBErr: AHB access error during reception • OR: Over-run during reception • OFF: Bus-off condition • PASS: Error-passive condition The Rx, RxFull and RxIrq interrupts are only generated as the result of a successful message reception, after the CanRxWR.WRITE pointer has been incremented. The OR interrupt is generated when a message is received while a previously received message is still being stored. A full circular buffer will lead to OR interrupts for any subsequently received messages. Note that the last message stored which fills the circular buffer will not generate an OR interrupt. The overrun is also reported with the CanSTAT.OR bit, which is cleared when reading the register. The error behavior of the CAN core is according to the CAN standard, which applies to the error counter, buss-off condition and error-passive condition. 37.7 Global reset and enable When the CanCTRL.RESET bit is set to 1b, a reset of the core is performed. The reset clears all the register fields to their default values. Any ongoing CAN message transfer request will be aborted, potentially violating the CAN protocol. When the CanCTRL.ENABLE bit is cleared to 0b, the CAN core is reset and the configuration bits CanCONF.SCALER, CanCONF.PS1, CanCONF.PS2, CanCONF.RSJ and CanCONF.BPR may be modified. When disabled, the CAN controller will be in sleep mode not affecting the CAN bus by only sending recessive bits. Note that the CAN core requires that 10 recessive bits are received before any reception or transmission can be initiated. This can be caused either by no unit sending on the CAN bus, or by random bits in message transfers. 37.8 Interrupt Three interrupts are implemented by the CAN interface: Index: Name: Description: 0 IRQ Common output from interrupt handler 1 TxSYNC Synchronization message transmitted (optional) 2 RxSYNC Synchronization message received (optional) The interrupts are configured by means of the pirq VHDL generic and the singleirq VHDL generic. 37.9 Endianness The core is designed for big-endian systems. GRIP, Apr 2018, Version 2018.1 409 www.cobham.com/gaisler GRLIB IP Core 37.10 Registers The core is programmed through registers mapped into APB address space. Table 443.GRCAN registers APB address offset Register 0x000 Configuration Register 0x004 Status Register 0x008 Control Register 0x018 SYNC Mask Filter Register 0x01C SYNC Code Filter Register 0x100 Pending Interrupt Masked Status Register 0x104 Pending Interrupt Masked Register 0x108 Pending Interrupt Status Register 0x10C Pending Interrupt Register 0x110 Interrupt Mask Register 0x114 Pending Interrupt Clear Register 0x200 Transmit Channel Control Register 0x204 Transmit Channel Address Register 0x208 Transmit Channel Size Register 0x20C Transmit Channel Write Register 0x210 Transmit Channel Read Register 0x214 Transmit Channel Interrupt Register 0x300 Receive Channel Control Register 0x304 Receive Channel Address Register 0x308 Receive Channel Size Register 0x30C Receive Channel Write Register 0x310 Receive Channel Read Register 0x314 Receive Channel Interrupt Register 0x318 Receive Channel Mask Register 0x31C Receive Channel Code Register 37.10.1 Configuration Register Table 444.Configuration Register 31 24 23 20 19 SCALER PS1 PS2 0 0 0 rw rw rw 15 31-24: 23-20: 19-16: 14-12: 14 12 11 10 9 8 7 6 16 5 4 3 2 1 0 Sile nt Sele ct Ena ble1 Ena ble0 Abo rt RSJ BPR SAM 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw SCALER PS1 PS2 RSJ Prescaler setting, 8-bit: system clock / (SCALER +1) Phase Segment 1, 4-bit: (valid range 1 to 15) Phase Segment 2, 4-bit: (valid range 2 to 8) ReSynchronization Jumps, 3-bit: (valid range 1 to 4) GRIP, Apr 2018, Version 2018.1 410 www.cobham.com/gaisler GRLIB IP Core 9:8: 5: 4: 3: 2: 1: 0: BPR Baud rate, 2-bit: 00b = system clock / (SCALER +1) / 1 01b = system clock / (SCALER +1) / 2 10b = system clock / (SCALER +1) / 4 11b = system clock / (SCALER +1) / 8 SAM Single sample when 0b. Triple sample when 1b. SILENT Listen only to the CAN bus, send recessive bits. SELECT Selection receiver input and transmitter output: Select receive input 0 as active when 0b, Select receive input 1 as active when 1b Select transmit output 0 as active when 0b, Select transmit output 1 as active when 1b ENABLE1 Set value of output 1 enable ENABLE0 Set value of output 0 enable ABORT Abort transfer on AHB ERROR All bits are cleared to 0 at reset. Note that constraints on PS1, PS2 and RSJ are defined as: • PS1 +1 >= PS2 • PS1 > PS2 • PS2 >= RSJ Note that CAN standard TSEG1 is defined by PS1+1. Note that CAN standard TSEG2 is defined by PS2. Note that the SCALER setting defines the CAN time quantum, together with the BPR setting: system clock / ((SCALER+1) * BPR) where SCALER is in range 0 to 255, and the resulting division factor due to BPR is 1, 2, 4 or 8. For a quantum equal to one system clock period, an additional quantum is added to the node delay. Note that for minimizing the node delay, then set either SCALER > 0 or BRP > 0. Note that the resulting bit rate is: system clock / ((SCALER+1) * BPR * (1+ PS1+1 + PS2)) where PS1 is in the range 1 to 15, and PS2 is in the range 2 to 8. Note that RSJ defines the number of allowed re-synchronization jumps according to the CAN standard, being in the range 1 to 4. For SAM = 0b (single), the bus is sampled once; recommended for high speed buses (SAE class C). For SAM = 1b (triple), the bus is sampled three times; recommended for low/medium speed buses (SAE class A and B) where filtering spikes on the bus line is beneficial. Note that the transmit or receive channel active during the AMBA AHB error is disabled if the ABORT bit is set to 1b. Note that all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs while the ABORT bit is set to 1b. The accesses will be disabled until the CanSTAT register is read. GRIP, Apr 2018, Version 2018.1 411 www.cobham.com/gaisler GRLIB IP Core 37.10.2 Status Register Table 445.Status register 31 28 27 24 23 16 TxChannels RxChannels TxErrCntr 0 0 0 r r r 15 4 3 2 1 0 RxErrCntr Acti ve AH B Err OR Off Pass 0 0 0 0 0 0 r r r r r r 31-28: 27-24: 23-16: 15-8: 4: 3: 2: 1: 0: 8 7 6 5 TxChannelsNumber of TxChannels -1, 4-bit RxChannelsNumber of RxChannels -1, 4-bit TxErrCntr Transmission error counter, 8-bit RxErrCntr Reception error counter, 8-bit ACTIVE Transmission ongoing AHBErr AMBA AHB master interface blocked due to previous AHB error OR Overrun during reception OFF Bus-off condition PASS Error-passive condition All bits are cleared to 0 at reset. The OR bit is set if a message with a matching ID is received and cannot be stored via the AMBA AHB bus, this can be caused by bandwidth limitations or when the circular buffer for reception is already full. The OR and AHBErr status bits are cleared when the register has been read. Note that TxErrCntr and RxErrCntr are defined according to CAN protocol. Note that the AHBErr bit is only set to 1b if an AMBA AHB error occurs while the CanCONF.ABORT bit is set to 1b. 37.10.3 Control Register Table 446.Control Register 31 2 1 0 Rese Ena t ble 1: 0: 0 0 rw rw RESET Reset complete core when 1 ENABLE Enable CAN controller, when 1. Reset CAN controller, when 0 All bits are cleared to 0 at reset. Note that RESET is read back as 0b. Note that ENABLE should be cleared to 0b to while other settings are modified, ensuring that the CAN core is properly synchronized. GRIP, Apr 2018, Version 2018.1 412 www.cobham.com/gaisler GRLIB IP Core Note that when ENABLE is cleared to 0b, the CAN interface is in sleep mode, only outputting recessive bits. Note that the CAN core requires that 10 recessive bits be received before receive and transmit operations can begin. 37.10.4 SYNC Code Filter Register Table 447.SYNC Code Filter Register 31 30 29 28 0 SYNC 0 rw 28-0: SYNC Message Identifier All bits are cleared to 0 at reset. Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0. 37.10.5 SYNC Mask Filter Register Table 448.SYNC Mask Filter Register 31 30 29 28 0 MASK 0x1FFFFFFF rw 28-0: MASK Message Identifier All bits are set to 1 at reset. Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0. A RxSYNC message ID is matched when: ((Received-ID XOR CanCODE.SYNC) AND CanMASK.MASK) = 0 A TxSYNC message ID is matched when: ((Transmitted-ID XOR CanCODE.SYNC) AND CanMASK.MASK) = 0 37.10.6 Transmit Channel Control Register Table 449.Transmit Channel Control Register 31 2: 1: 0: 3 2 1 0 Single Ong oing Ena ble 0 0 0 rw rw rw SINGLE Single shot mode ONGOINGTransmission ongoing ENABLE Enable channel All bits are cleared to 0 at reset. GRIP, Apr 2018, Version 2018.1 413 www.cobham.com/gaisler GRLIB IP Core Note that if the SINGLE bit is 1b, the channel is disabled (i.e. the ENABLE bit is cleared to 0b) if the arbitration on the CAN bus is lost. Note that in the case an AHB bus error occurs during an access while fetching transmit data, and the CanCONF.ABORT bit is 1b, then the ENABLE bit will be reset automatically. At the time the ENABLE is cleared to 0b, any ongoing message transmission is not aborted, unless the CAN arbitration is lost or communication has failed. Note that the ONGOING bit being 1b indicates that message transmission is ongoing and that configuration of the channel is not safe. 37.10.7 Transmit Channel Address Register Table 450.Transmit Channel Address Register 31 10 9 0 ADDR 0 rw 31-10: ADDR Base address for circular buffer All bits are cleared to 0 at reset. 37.10.8 Transmit Channel Size Register Table 451.Transmit Channel Size Register 31 21 20 6 5 0 SIZE 0 rw 20-6: SIZE The size of the circular buffer is SIZE*4 messages All bits are cleared to 0 at reset. Valid SIZE values are between 0 and 16384. Note that each message occupies four 32-bit words. Note that the resulting behavior of invalid SIZE values is undefined. Note that only (SIZE*4)-1 messages can be stored simultaneously in the buffer. This is to simplify wrap-around condition checking. The width of the SIZE field may be made configurable by means of a VHDL generic. In this case it should be set to 16-1 bits width. 37.10.9 Transmit Channel Write Register Table 452.Transmit Channel Write Register 31 20 19 4 3 0 WRITE 0 rw 19-4: WRITE Pointer to last written message +1 GRIP, Apr 2018, Version 2018.1 414 www.cobham.com/gaisler GRLIB IP Core All bits are cleared to 0 at reset. The WRITE field is written to in order to initiate a transfer, indicating the position +1 of the last message to transmit. Note that it is not possible to fill the buffer. There is always one message position in buffer unused. Software is responsible for not over-writing the buffer on wrap around (i.e. setting WRITE=READ). The field is implemented as relative to the buffer base address (scaled with the SIZE field). 37.10.10Transmit Channel Read Register Table 453.Transmit Channel Read Register 31 20 19 4 3 0 READ 0 rw 19-4: READ Pointer to last read message +1 All bits are cleared to 0 at reset. The READ field is written to automatically when a transfer has been completed successfully, indicating the position +1 of the last message transmitted. Note that the READ field can be use to read out the progress of a transfer. Note that the READ field can be written to in order to set up the starting point of a transfer. This should only be done while the transmit channel is not enabled. Note that the READ field can be automatically incremented even if the transmit channel has been disabled, since the last requested transfer is not aborted until CAN bus arbitration is lost. When the Transmit Channel Read Pointer catches up with the Transmit Channel Write Register, an interrupt is generated (TxEmpty). Note that this indicates that all messages in the buffer have been transmitted. The field is implemented as relative to the buffer base address (scaled with the SIZE field). 37.10.11Transmit Channel Interrupt Register Table 454.Transmit Channel Interrupt Register 31 20 19 4 3 0 IRQ 0 rw 19-4: IRQ Interrupt is generated when CanTxRD.READ=IRQ, as a consequence of a message transmission All bits are cleared to 0 at reset. Note that this indicates that a programmed number of messages have been transmitted. The field is implemented as relative to the buffer base address (scaled with the SIZE field). GRIP, Apr 2018, Version 2018.1 415 www.cobham.com/gaisler GRLIB IP Core 37.10.12Receive Channel Control Register Table 455.Receive Channel Control Register 31 2 1 0 OnG Ena oing ble 1: 0: 0 0 r rw ONGOINGReception ongoing (read-only) ENABLE Enable channel All bits are cleared to 0 at reset. Note that in the case an AHB bus error occurs during an access while fetching transmit data, and the CanCONF.ABORT bit is 1b, then the ENALBE bit will be reset automatically. At the time the ENABLE is cleared to 0b, any ongoing message reception is not aborted Note that the ONGOING bit being 1b indicates that message reception is ongoing and that configuration of the channel is not safe. 37.10.13Receive Channel Address Register Table 456.Receive Channel Address Register 31 10 9 0 ADDR 0 rw 31-10: ADDR Base address for circular buffer All bits are cleared to 0 at reset. 37.10.14Receive Channel Size Register Table 457.Receive Channel Size Register 31 21 20 6 5 0 SIZE 0 rw 20-6: SIZE The size of the circular buffer is SIZE*4 messages All bits are cleared to 0 at reset. Valid SIZE values are between 0 and 16384. Note that each message occupies four 32-bit words. Note that the resulting behavior of invalid SIZE values is undefined. Note that only (SIZE*4)-1 messages can be stored simultaneously in the buffer. This is to simplify wrap-around condition checking. The width of the SIZE field may be made configurable by means of a VHDL generic. In this case it should be set to 16-1 bits width. GRIP, Apr 2018, Version 2018.1 416 www.cobham.com/gaisler GRLIB IP Core 37.10.15Receive Channel Write Register Table 458.Receive Channel Write Register 31 20 19 4 3 0 WRITE 0 rw 19-4: WRITE Pointer to last written message +1 All bits are cleared to 0 at reset. The field is implemented as relative to the buffer base address (scaled with the SIZE field). The WRITE field is written to automatically when a transfer has been completed successfully, indicating the position +1 of the last message received. Note that the WRITE field can be use to read out the progress of a transfer. Note that the WRITE field can be written to in order to set up the starting point of a transfer. This should only be done while the receive channel is not enabled. 37.10.16Receive Channel Read Register Table 459.Receive Channel Read Register 31 20 19 4 3 0 READ 0 rw 19-4: READ Pointer to last read message +1 All bits are cleared to 0 at reset. The field is implemented as relative to the buffer base address (scaled with the SIZE field). The READ field is written to in order to release the receive buffer, indicating the position +1 of the last message that has been read out. Note that it is not possible to fill the buffer. There is always one message position in buffer unused. Software is responsible for not over-reading the buffer on wrap around (i.e. setting WRITE=READ). 37.10.17Receive Channel Interrupt Register Table 460.Receive Channel Interrupt Register 31 20 19 4 3 0 IRQ 0 rw 19-4: IRQ Interrupt is generated when CanRxWR.WRITE=IRQ, as a consequence of a message reception All bits are cleared to 0 at reset. Note that this indicates that a programmed number of messages have been received. The field is implemented as relative to the buffer base address (scaled with the SIZE field). GRIP, Apr 2018, Version 2018.1 417 www.cobham.com/gaisler GRLIB IP Core 37.10.18Receive Channel Mask Register Table 461.Receive Channel Mask Register 31 30 29 28 0 AM 0x1FFFFFFF rw 28-0: AM Acceptance Mask, bits set to 1b are taken into account in the comparison between the received message ID and the CanRxCODE.AC field All bits are set to 1 at reset. Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0. 37.10.19Receive Channel Code Register Table 462.Receive Channel Code Register 31 30 29 28 0 AC 0 rw 28-0: AC Acceptance Code, used in comparison with the received message All bits are cleared to 0at reset. Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0. A message ID is matched when: ((Received-ID XOR CanRxCODE.AC) AND CanRxMASS.AM) = 0 37.10.20Interrupt registers The interrupt registers give complete freedom to the software, by providing means to mask interrupts, clear interrupts, force interrupts and read interrupt status. When an interrupt occurs the corresponding bit in the Pending Interrupt Register is set. The normal sequence to initialize and handle a module interrupt is: • Set up the software interrupt-handler to accept an interrupt from the module. • Read the Pending Interrupt Register to clear any spurious interrupts. • Initialize the Interrupt Mask Register, unmasking each bit that should generate the module interrupt. • When an interrupt occurs, read the Pending Interrupt Status Register in the software interrupthandler to determine the causes of the interrupt. • Handle the interrupt, taking into account all causes of the interrupt. • Clear the handled interrupt using Pending Interrupt Clear Register. Masking interrupts: After reset, all interrupt bits are masked, since the Interrupt Mask Register is zero. To enable generation of a module interrupt for an interrupt bit, set the corresponding bit in the Interrupt Mask Register. Clearing interrupts: All bits of the Pending Interrupt Register are cleared when it is read or when the Pending Interrupt Masked Register is read. Reading the Pending Interrupt Masked Register yields the GRIP, Apr 2018, Version 2018.1 418 www.cobham.com/gaisler GRLIB IP Core contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register. Selected bits can be cleared by writing ones to the bits that shall be cleared to the Pending Interrupt Clear Register. Forcing interrupts: When the Pending Interrupt Register is written, the resulting value is the original contents of the register logically OR-ed with the write data. This means that writing the register can force (set) an interrupt bit, but never clear it. Reading interrupt status: Reading the Pending Interrupt Status Register yields the same data as a read of the Pending Interrupt Register, but without clearing the contents. Reading interrupt status of unmasked bits: Reading the Pending Interrupt Masked Status Register yields the contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register, but without clearing the contents. The interrupt registers comprise the following: • Pending Interrupt Masked Status Register [CanPIMSR] R • Pending Interrupt Masked Register [CanPIMR] R • Pending Interrupt Status Register [CanPISR] R • Pending Interrupt Register [CanPIR] R/W • Interrupt Mask Register [CanIMR] R/W • Pending Interrupt Clear Register [CanPICR] W Table 463.Interrupt registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Tx Loss 0 * 15 14 13 12 11 10 9 8 Tx Miss Err Cntr Rx Err Cntr Tx Syn c Rx Syn c Tx Rx 0 0 0 0 0 0 * * * * * * Rx 16: TxLoss 15: 14: 13: 12: 11: 10: 9: 8: 7: 6: 5: 4: 3: 2: 1: RxMiss TxErrCntr RxErrCntr TxSync RxSync Tx Rx TxEmpty RxFull TxIRQ RxIRQ TxAHBErr RxAHBErr OR OFF GRIP, Apr 2018, Version 2018.1 7 6 5 4 3 2 1 0 Tx Rx Emp Full ty Tx IRQ Rx IRQ Tx AH B Err Rx AH B Err OR Off Pass 0 0 0 0 0 0 0 0 0 0 * * * * * * * * * * Message arbitration lost during transmission (could be caused by communications error, as indicated by other interrupts as well) Message filtered away during reception Transmission error counter incremented Reception error counter incremented Synchronization message transmitted Synchronization message received Successful transmission of message Successful reception of message Successful transmission of all messages in buffer Successful reception of all messages possible to store in buffer Successful transmission of a predefined number of messages Successful reception of a predefined number of messages AHB error during transmission AHB error during reception Over-run during reception Bus-off condition 419 www.cobham.com/gaisler GRLIB IP Core 0: PASS Error-passive condition All bits in all interrupt registers are reset to 0b after reset. Note that the TxAHBErr interrupt is generated in such way that the corresponding read and write pointers are valid for failure analysis. The interrupt generation is independent of the CanCONF.ABORT field setting. Note that the RxAHBErr interrupt is generated in such way that the corresponding read and write pointers are valid for failure analysis. The interrupt generation is independent of the CanCONF.ABORT field setting. 37.11 Memory mapping The CAN message is represented in memory as shown in table 464. Table 464.CAN message representation in memory. AHB addr 0x0 31 30 29 28 IDE RT R - bID 15 14 13 12 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 eID 11 10 9 8 7 6 5 4 3 2 1 0 22 21 20 19 18 17 16 2 1 0 eID 0x4 31 DLC 15 14 13 12 27 26 25 24 23 - - - - TxErrCntr 11 10 9 8 7 6 5 4 3 - - - - Ahb OR Err Off Pass 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RxErrCntr 0x8 31 30 29 28 27 26 25 24 Byte 0 (first transmitted) 15 14 13 12 Byte 1 11 10 9 8 Byte 2 0xC 31 30 29 28 27 26 25 24 14 13 12 11 10 9 8 Byte 4 15 7 Byte 3 23 Byte 5 Byte 6 7 Byte 7 (last transmitted) Values: Levels according to CAN standard: 1b is recessive, 0b is dominant Legend: Naming and number in according to CAN standard IDE Identifier Extension: RTR Remote Transmission Request: bID eID DLC Base Identifier Extended Identifier Data Length Code, according to CAN standard: 1b for Extended Format, 0b for Standard Format 1b for Remote Frame, 0b for Data Frame 0000b 0001b 0010b 0011b GRIP, Apr 2018, Version 2018.1 420 0 bytes 1 byte 2 bytes 3 bytes www.cobham.com/gaisler GRLIB IP Core 0100b 0101b 0110b 0111b 1000b OTHERS TxErrCntr RxErrCntr AHBErr OR OFF PASS Byte 00 to 07 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes illegal Transmission Error Counter Reception Error Counter AHB interface blocked due to AHB Error when 1b Reception Over run when 1b Bus Off mode when 1b Error Passive mode when 1b Transmit/Receive data, Byte 00 first Byte 07 last 37.12 Vendor and device identifiers The module has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x03D. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 37.13 Implementation 37.13.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. 37.14 Configuration options Table 465 shows the configuration options of the core (VHDL generics). Table 465.Configuration options Generic name Function Allowed range Default hindex AHB master index. 0 - NAHBMST-1 0 pindex APB slave index 0 - NAPBSLV-1 0 paddr Addr field of the APB bar. 0 - 16#FFF# 0 pmask Mask field of the APB bar. 0 - 16#FFF# 16#FFC# pirq Interrupt line used by the GRCAN. 0 - NAHBIRQ-1 0 singleirq Implement only one common interrupt 0-1 0 txchannels Number of transmit channels 1-1 1 rxchannels Number of receive channels 1-1 1 ptrwidth Width of message pointers 16 - 16 16 GRIP, Apr 2018, Version 2018.1 421 www.cobham.com/gaisler GRLIB IP Core 37.15 Signal descriptions Table 466 shows the interface signals of the core (VHDL ports). Table 466.Signal descriptions Signal name Field Type Function Active RSTN N/A Input Reset Low CLK N/A Input Clock - APBI * Input APB slave input signals - APBO * Output APB slave output signals - AHBI * Input AMB master input signals - AHBO * Output AHB master output signals - CANI Rx[1:0] Input Receive lines - CANO Tx[1:0] Output Transmit lines - Transmit enables - En[1:0] * see GRLIB IP Library User’s Manual 37.16 Signal definitions and reset values The signals and their reset values are described in table 467. Table 467.Signal definitions and reset values Signal name Type Function Active Reset value cantx[] Output CAN transmit data Low Logical 1 canen[] Output CAN transmitter enable High Logical 0 canrx[] Input CAN receive data Low - 37.17 Timing The timing waveforms and timing parameters are shown in figure 120 and are defined in table 468. clk tGRCAN0 cantx[] tGRCAN2 canrx[] tGRCAN3 tGRCAN1 tGRCAN3 canen[] Figure 120. Timing waveforms Table 468.Timing parameters Name Parameter Reference edge Min Max Unit tGRCAN0 clock to data output delay rising clk edge - TBD ns tGRCAN1 data input to clock setup rising clk edge TBD - ns tGRCAN2 data input from clock hold rising clk edge TBD - ns tGRCAN3 clock to output delay rising clk edge - TBD ns GRIP, Apr 2018, Version 2018.1 422 www.cobham.com/gaisler GRLIB IP Core 37.18 Library dependencies Table 469 shows the libraries used when instantiating the core (VHDL libraries). Table 469.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER CAN Signals, component GRCAN component and signal declarations. 37.19 Instantiation This example shows how the core can be instantiated. library use ieee; ieee.std_logic_1164.all; library use gaisler; gaisler.can.all; entity example is generic ( padtech: in port ( -- CAN interface cantx: out canrx: in canen: out integer := 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); ... -- Signal declarations signal rstn: signal clk: std_ulogic; std_ulogic; signal signal ahbmo: ahbmi: ahb_mst_out_vector := (others => ahbm_none); ahb_mst_in_type; signal signal apbi: apbo: apb_slv_in_type; apb_slv_out_vector := (others => apb_none); signal signal cani0: cano0: can_in_type; can_out_type; ... -- Component instantiation grcan0: grcan generic map ( hindex => 1, pindex => 1, paddr => 16#00C", pmask => 16#FFC", pirq => 1, txchannels => 1, rxchannels => 1, ptrwidth => 16) port map ( rstn => rstn, clk => clk, apbi => apbi, apbo => apbo(1), ahbi => ahbmi, ahbo => ahbmo(1), cani => cani0, cano => cano0); GRIP, Apr 2018, Version 2018.1 423 www.cobham.com/gaisler GRLIB IP Core cantx0_pad : outpad generic map (tech => padtech) port map (cantx(0), cani0.tx(0)); canrx0_pad : inpad generic map (tech => padtech) port map (canrx(0), cani0.rx(0)); canen0_pad : outpad generic map (tech => padtech) port map (canen(0), cani0.en(0)); cantx1_pad : outpad generic map (tech => padtech) port map (cantx(1), cani0.tx(1)); canrx1_pad : inpad generic map (tech => padtech) port map (canrx(1), cani0.rx(1)); canen1_pad : outpad generic map (tech => padtech) port map (canen(1), cani0.en(1)); GRIP, Apr 2018, Version 2018.1 424 www.cobham.com/gaisler GRLIB IP Core 38 GRCLKGATE / GRCLKGATE2X - Clock gating unit 38.1 Overview The clock gating unit provides a means to save power by disabling the clock to unused functional blocks. The core provides a mechanism to automatically disabling the clock to LEON processors in power-down mode, and optionally also to disable the clock for floating-point units. The core provides a register interface via its APB slave bus interface. The clock gate unit has two main top-level units, GRCLKGATE and GRCLKGATE2X. GRCLKGATE2X exposes the full functionality and is the recommended top-level for new designs. 38.2 Operation The operation of the clock gating unit is controlled through four registers: the unlock, clock enable, core reset and CPU/FPU override registers. The clock enable register defines if a clock is enabled or disabled. A ‘1’ in a bit location will enable the corresponding clock, while a ‘0’ will disable the clock. The core reset register allows to generate a reset signal for each generated clock. A reset will be generated as long as the corresponding bit is set to ‘1’. The bits in clock enable and core reset registers can only be written when the corresponding bit in the unlock register is 1. If a bit in the unlock register is 0, the corresponding bits in the clock enable and core reset registers cannot be written. To gate the clock for a core, the following procedure should be applied: 1. Disable the core through software to make sure it does not initialize any AHB accesses 2. Write a 1 to the corresponding bit in the unlock register 3. Write a 0 to the corresponding bit in the clock enable register 4. Write a 0 to the corresponding bit in the unlock register To enable the clock for a core, the following procedure should be applied 1. Write a 1 to the corresponding bit in the unlock register 2. Write a 1 to the corresponding bit in the core reset register 3. Write a 1 to the corresponding bit in the clock enable register 4. Write a 0 to the corresponding bit in the clock enable register 5. Write a 0 to the corresponding bit in the core reset register 6. Write a 1 to the corresponding bit in the clock enable register 7. Write a 0 to the corresponding bit in the unlock register The clock gating unit also provides gating for the processor core and, optionally, floating-point units. A processor core will be automatically gated off when it enters power-down mode. With the GRCLKGATE and GRCLKGATE2X units, any shared FPU will be gated off when all processor cores connected to the FPU have floating-point disabled or when all connected processor cores are in power-down mode. With the GRCLKGATE2X unit it is also possible to support dedicated FPU clock gating. In this case a FPU will be gated off when processor core connected to the FPU has floating-point disabled or when the processor core is in power down mode. Processor/FPU clock gating can be disabled by writing ‘1’ to bit 0 of the CPU/FPU override register. 38.2.1 Shared FPU For systems with shared FPU, a processor may be clock gated off while the connected FPU continues to be clocked. The power-down instruction may overtake a previously issued floating-point instruc- GRIP, Apr 2018, Version 2018.1 425 www.cobham.com/gaisler GRLIB IP Core tion and cause the processor to be gated off before the floating-point operation has completed. This can in turn lead to the processor not reacting to the completion of the floating-point operation and to a subsequent processor freeze after the processor wakes up and continues to wait for the completion of the floating-point operation. In order to avoid this, software must make sure that all floating-point operations have completed before the processor enters power-down. This is generally not a problem in real-world applications as the power-down instruction is typically used in a idle loop and floating-point results have been stored to memory before entering the idle loop. To make sure that there are no floating-point operations pending, software should perform a store of the %fsr register before the power-down instruction. 38.3 Registers The core’s registers are mapped into APB address space. Table 470. Clock gate unit registers APB address offset Register 0x00 Unlock register 0x04 Clock enable register 0x08 Core reset register 0x0C CPU/FPU override register 0x10 - 0xFF Reserved GRIP, Apr 2018, Version 2018.1 426 www.cobham.com/gaisler GRLIB IP Core 38.3.1 Unlock register Table 471.0x00 - UNLOCK - Unlock register 31 x+1 x 0 RESERVED UNLOCK 0 0 r rw 31: x+1 RESERVED x: 0 Unlock clock enable and reset registers (UNLOCK) - The bits in clock enable and core reset registers can only be written when the corresponding bit in this field is 1. 38.3.2 Clock enable register Table 472.0x04 - CLKEN - Clock enable register 31 x+1 x 0 RESERVED ENABLE 0 * r rw 31: x+1 RESERVED x: 0 Cock enable (ENABLE) - A ‘1’ in a bit location will enable the corresponding clock, while a ‘0’ will disable the clock. 38.3.3 Core reset register Table 473. 0x08 - RESET - Reset register 31 x+1 x 0 RESERVED RESET 0 0 r rw 31: x+1 RESERVED x: 0 Reset (RESET) - A reset will be generated as long as the corresponding bit is set to ‘1’. 38.3.4 CPU/FPU override register Table 474. 0x0c - OVERRIDE - CPU/FPU override register 31 y+1 y RESERVED 38.4 16 15 x+1 x 0 FOVERRIDE RESERVED OVERRIDE 0 0 0 0 r rw r rw 31: y+1 RESERVED y: 16 Override FPU clock gating (FOVERRIDE) - If bit n of this field is set to ’1’ then the clock for FPU n will be active regardless of the value of %PSR.EF. Only available if FPU clock is enabled at implementation. 15: x+1 RESERVED x: 0 Override CPU clock gating (OVERRIDE) - If bit n of this field is set to ’1’ then the clock for processor n and FPU n will always be active. Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x02C. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. GRIP, Apr 2018, Version 2018.1 427 www.cobham.com/gaisler GRLIB IP Core 38.5 Implementation 38.5.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset for its internal registers. 38.5.2 Clock gate implementation The clock gates are implemented using the CLKAND core in the techmap library, that instantiates the appropriate cell for the selected technology. For ungated clocks, dummy clock gates are instantiated with the same technology but the isdummy generic set to 1. The technology mapping for the technology can decide whether to instantiate real clock gating cells for the technology or to pass the clock through as-is without any gating. 38.5.3 Scan test support The test-enable signal is taken in through the APB input record and passed through to the techmap layer where it can be connected to the clock gating cell’s test enable input or OR:ed into the normal enable if no test-enable input is available. Another alternative is to drive the cell’s test enable input with constant 0 and hook it up to test-enable or scan-enable during the DFT implementation. Refer to the synthesis/DFT tools documentation for more details. A separate ungate active-high input signal that also sets all clock gates to pass-through can be enabled in the core. This is passed in through the functional path. 38.5.4 Simulation The underlying technology-specific gating in the techmap layer should ensure that all the gated and ungated clocks generated are delay and delta aligned to avoid zero-delay simulation problems. The standard solution is to add a 5 ps delay that gets removed on synthesis, however some technologies may use a different approach. 38.6 Configuration options Table 475 shows the configuration options of the core (VHDL generics). Table 475.Configuration options Generic Function Allowed range Default tech Clock/fabrication technology 0 to NTECH-1 0 pindex Selects which APB select signal (PSEL) will be used to access the unit paddr The 12-bit MSB APB address 0 to 16#FFF# 0 pmask The APB address mask 0 to 16#FFF# 16#FFF# ncpu Number of processors that will connect to the unit - 1 nclks Number of peripheral units (clock/reset pairs) in addition to any processors and floating-point units that will connect to the unit. 0 - 31 8 emask Bit mask where bit n (0 is the least significant bit) decides if a unit should be enabled (1) or disabled (0) after system reset. 0 - 16#FFFFFFFF# 0 extemask If this generic is set to a non-zero value then the afterreset-enable-mask will be taken from the input signal epwen. 0-1 0 scantest Enable scan test support 0-1 0 GRIP, Apr 2018, Version 2018.1 428 www.cobham.com/gaisler GRLIB IP Core Table 475.Configuration options Generic Function Allowed range Default edges Extra clock edges provided by the clock gate unit after reset completes. CPUs get edges + 3 rising edges after reset and other cores get edges + 1 rising edges after system reset. 0 noinv Do not use inverted clock for clock gate enable register. This generic can be set to one for technologies that have glitch free clock gates. 0-1 0 fpush Selects FPU configuration 0-2 0 0-1 1 0: System has processors without, or with dedicated, FPUs 1: System has one FPU shared between all processors 3: System has one FPU for each parir of processors. (FPU0 is connected to CPU0 and CPU1, FPU1 is connected to CPU2 and CPU3, ...) clk2xen Enable double clocking. Only available on GRCLKGATE2X entity ungateen Enable separate ungate input for asynchronous un-gating of all clocks. 0 - 16#FFFFFFFF# 0 fpuclken Enable separate clocks for FPU. Requires that generic fpush is set to 0. 0-1 0 0 - 16#FFFFFFFF# 1 0 - 16#FFFFFFFF# 1 1-1 1 Only available on GRCLKGATE2X entity nahbclk Length of clkahb output vector Only available on GRCLKGATE2X entity nahbclk2x Length of clkahb2x output vector Only available on GRCLKGATE2X entity balance If balance is set to 1 then an always-enabled clock gate is inserted on each clkahb output. This option is obsolete as the techmap layer can now decide what to do with dummy clock gates, and only the value 1 is supported in the core. GRIP, Apr 2018, Version 2018.1 429 www.cobham.com/gaisler GRLIB IP Core 38.7 Signal descriptions Table 476 shows the interface signals of the core (VHDL ports). Table 476.Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLKIN N/A Input Clock - CLKIN2X N/A Input Clock with higher frequency. - Only present on GRCLKGATE2X entity. PWD N/A Input Power-down signal from processor cores High FPEN N/A Input Floating-point enable signal from processor cores, only used in configurations with shared FPU when using the GRCLKGATE entity. For GRCLKGATE2X this input is also used when VHDL generic fpuclken is set to 1. High APBI * Input APB slave input signals - APBO * Output APB slave output signals - GCLK[nclks-1:0] N/A Output Clock(s) to peripheral unit - RESET[nclks-1:0] N/A Output Reset(s) to peripheral units Low CLKAHB[nahbclk**-1:0] N/A Output Clock to non-gated units - CLKAHB2X[nahbclk2x**-1:0] N/A Output 2x Clock to non-gated units - CLKCPU[ncpu-1:0] N/A Output Clock to processor cores - ENABLE[nclks-1:0] N/A Output Enable signal(s) for peripheral units High CLKFPU[nfpu***:0] N/A Output Clock to shared floating-point units, only used in configurations with shared FPU. - EPWEN N/A Input External enable reset vector High UNGATE N/A Input Ungate all clocks for test mode (only used if enabled in configuration) High * see GRLIB IP Library User’s Manual ** Single output on GRCLKGATE entity, vector on GRCLKGATE2X entity. *** where nfpu = (fpush/2)*(ncpu/2-1) for GRCLKGATE and (fpush/2+fpuclken)*(ncpu/(2-fpuclken)-1) for GRCLKGATE2X 38.8 Library dependencies Table 477 shows libraries used when instantiating the core (VHDL libraries). Table 477.Library dependencies 38.9 Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Component Component declaration Instantiation This example shows how the core can be instantiated. clkg0: grclkgate generic map ( tech => pindex => paddr => pmask => ncpu => fabtech, 4, 16#040#, 16#fff#, CFG_NCPU, GRIP, Apr 2018, Version 2018.1 430 www.cobham.com/gaisler GRLIB IP Core nclks emask extemask scantest edges noinv fpush port map( rst clkin pwd fpen apbi apbo gclk reset clkahb clkcpu enable clkfpu epwen ungate => => => => => => => NCLKS, 0, 1, scantest, CG_EDGES, CG_NOINV, CFG_GRFPUSH) => => => => => => => => => => => => => => rstn, -ahb_clk, -pwd, -- from fpen, -- from apbi, apbo(4), gclk, -grst, -clkm, -cpuclk, -clkenable, -fpuclk, -pwenmask, -gnd); GRIP, Apr 2018, Version 2018.1 -- Don’t care -- Reset value defined by input vector (epwen below) from reset generator from clock generator processors, typically dsuo.pwd(CFG_NCPU-1 downto 0) processors, if shared FPU is used clock to (gated) peripheral cores reset to (gated) peripheral cores clock to AMBA system (not gated) clock to processor cores enable(n) signals that peripheral n is enabled clock to any shared FPU cores signal to set enable-after-reset 431 www.cobham.com/gaisler GRLIB IP Core 39 GRDMAC - DMA Controller with internal AHB/APB bridge 39.1 Overview The GRDMAC core provides a flexible direct memory access controller. The core can perform burst transfers of data between AHB and APB peripherals at aligned or unaligned memory addresses. The core can be instantiated with one or two AHB master interfaces to perform transfers among different AHB buses. The core's configuration registers are accessible through an APB interface. Up to 16 DMA channels are supported. Each channel can be configured flexibly by means of two descriptor chains residing in main memory: a Memory to Buffer (M2B) chain and a Buffer to Memory (B2M) chain. Each chain is composed of a linked list of descriptors, where each descriptor specifies an AHB address and the size of the data to read/write, supporting a scatter/gather behavior. Once enabled, the core will proceed in reading the descriptor chains, then reading memory mapped addresses specified by the M2B chain and filling its internal buffer. It will then write the content of the buffer back to memory mapped addresses by elaborating the B2M descriptor chain. The core supports a simplified mode of operation, with only one channel. In this mode of operation only one descriptor is present for each of the M2B and B2M chains. These two descriptors are written directly in the core's register via APB. Figure 121. Block diagram 39.2 Configuration The GRDMAC core consists of four main components: the DMA control unit, the AHB Master interface, the internal buffer with realignment support and an optional second AHB Master interface. The core supports being attached to any AHB bus with a data width of 32-bit, 64-bit or 128-bit. For every DMA channel the core will perform two types of DMA transfers through one of the AMBA AHB Master interfaces: from memory to the internal buffer (M2B) and from the internal buffer to memory (B2M). The core will read data from memory until its internal buffer is filled or until the M2B GRIP, Apr 2018, Version 2018.1 432 www.cobham.com/gaisler GRLIB IP Core descriptor chain is completed. When one of these two events is detected, GRDMAC will start writing the buffer content into memory, by switching to the B2M chain. The internal buffer size is configurable through the generic bufsize. In case the buffer size is smaller that the total size of the M2B chain, the core will switch multiple times from the M2B chain to the B2M chain and vice versa. The second AHB Master Interface is enabled by setting the en_ahbm1 generic to 1. If the second interface is not enabled, all settings related to it will be ignored and the core will default to the main AHB Master Interface for all transfers. 39.2.1 Core setup The GRDMAC core reads its configuration from any AHB mapped address (typically main memory) through its main AMBA AHB Master interface (AHBM0 if instantiated with support for two master interfaces). The core supports up to 16 DMA channels, a number configurable through the ndmach generic. For each channel, the M2B and B2M descriptor linked lists must be set up, and a pointer to the first descriptor in the two chains must be provided. These pointers are organized in a structure called Channel Vector. The Channel Vector is organized as in Table 478, below. For each of the GRDMAC channels there are two pointers: one pointer to the M2B descriptor linked list and one pointer to the B2M descriptor linked list. The Channel Vector array must be created at a 128-byte-aligned address. The GRDMAC core will read the Channel Vector entries for each channel up to ndmach channels. Table 478.GRDMAC Channel Vector format Address offset Field 0x00 Channel 0: M2B descriptor pointer 0x04 Channel 0: B2M descriptor pointer 0x08 Channel 1: M2B descriptor pointer 0x0C Channel 1: B2M descriptor pointer ... ... ... ... 0x78 Channel 15: M2B descriptor pointer 0x7C Channel 15: B2M descriptor pointer 39.2.2 Descriptor types Each descriptor consists of a four-field structure as provided in the tables below and must be created at a 16-byte-aligned address. There are three descriptor types: M2B descriptors, B2M descriptors and conditional descriptors. The former two descriptors, categorized as data descriptors, are only allowed in the respective descriptor linked lists (M2B descriptor linked list and B2M descriptor linked list). Conditional descriptors on the other hand, are required to be followed by a data descriptor, to which they bond to, and they can be specified in both the M2B and B2M descriptor linked lists. They are special descriptors that enable conditional behavior in a descriptor linked list and they are described in more detail in paragraph 39.3.2. 39.2.3 Data descriptors For data descriptors, the first field, the next_descriptor field, is the address of the next descriptor in the chain. The chain ends with a descriptor whose next_descriptor field is all zeroes (NULL pointer). GRIP, Apr 2018, Version 2018.1 433 www.cobham.com/gaisler GRLIB IP Core The second field of an M2B descriptor, the address field, defines the address to read the data from. It can be any address in the system, and there are no alignment requirements. The number of bytes to transfer from memory to the internal buffer is specified in the third field, the control field, as seen in the table below. Table 479.GRDMAC M2B descriptor format Address offset Field 0x0 M2B next_descriptor 0x4 M2B address 0x8 M2B control 0xC M2B status Table 480. GRDMAC M2B descriptor next_descriptor field (address offset 0x00) 31 4 NEXT_PTR 31: 4 0 3 1 0 RESERVED DT M2B Next descriptor pointer address (NEXT_PTR) - MSb of 16 Byte aligned address of the next descriptor in the M2B descriptor chain or NULL. M2B descriptor type (DT) - Descriptor type field, ‘0’ for data descriptors, ‘1’ for conditional descriptors. Must be set to ‘0’ for this type of descriptor. Table 481. GRDMAC M2B descriptor address field (address offset 0x04) 31 0 ADDR 31: 0 M2B Address (ADDR) - Starting address the core will read data from. Table 482. GRDMAC M2B descriptor control field (address offset 0x08) 31 16 15 SIZE 31: 16 5 RESERVED 4 3 2 1 0 FA AN IE WB EN M2B descriptor size (SIZE) - Size in Bytes of the data that will be fetched from the address specified in the M2B address register. 4 M2B descriptor Fixed Address (FA) - If set to ‘1’, the data will be fetched from the same address for the entire size of the descriptor transfer. This is useful when reading from IO peripheral registers in combination with a conditional descriptor. If set to ‘0’, normal operation mode is attained. 3 M2B descriptor AHB Master Interface Number (AN) - If set to ‘0’, the descriptor’s transfer will be performed by the main AHB Master Interface (AHBM0). If set to ‘1’, the descriptor’s transfer will be performed by the second AHB Master Interface (AHBM1). If this interface is not enabled by the configuration generic en_ahbm1, then the transfer will fall back to the main AHB Master Interface (AHBM0). 2 M2B descriptor Interrupt Enable (IE) - If set to one, an interrupt will be generated when the M2B descriptor is completed. Descriptor interrupt generation also depends on interrupt mask for channel 0 and global interrupt enable. 1 M2B descriptor write-back (WB) - If set to one, the descriptor’s status field will be written back in main memory after completion. 0 M2B descriptor Enable (EN) - If set to one, the descriptor will be enabled, otherwise it will be skipped and the next descriptor fetched from memory. GRIP, Apr 2018, Version 2018.1 434 www.cobham.com/gaisler GRLIB IP Core Table 483. GRDMAC M2B descriptor status field (address offset 0x0C) 31 3 RESERVED 2 1 0 E S C 2 M2B descriptor error (E) - If set to one, an error was generated during execution of the M2B descriptor. See error register for more information. 1 M2B descriptor status (S) - If set to one, the descriptor is being executed and running. Otherwise set to zero. 0 M2B descriptor completion (C) - If set to one, the descriptor was completed successfully. For the B2M chain, the same holds true, with the exception of the address field, which specifies the address in main memory to write to. Table 484.GRDMAC B2M descriptor format Address offset Field 0x0 B2M next_descriptor 0x4 B2M address 0x8 B2M control 0xC B2M status Table 485. GRDMAC B2M descriptor next_descriptor field (address offset 0x00) 31 4 NEXT_PTR 31: 4 0 3 1 0 RESERVED DT B2M Next descriptor pointer address (NEXT_PTR) - Address of the next descriptor in the B2M descriptor chain or NULL. B2M descriptor type (DT) - Descriptor type field, ‘0’ for data descriptors, ‘1’ for conditional descriptors. Must be set to ‘0’ for this type of descriptor. Table 486. GRDMAC B2M descriptor address field (address offset 0x04) 31 0 ADDR 31: 0 B2M Address (ADDR) - Starting address the core will write data to. Table 487. GRDMAC B2M descriptor control field (address offset 0x08) 31 16 15 SIZE 31: 16 4 5 RESERVED 4 3 2 1 0 FA AN IE WB EN B2M descriptor size (SIZE) - Size in Bytes of the data that will be written to the address specified in the B2M address register. B2M descriptor Fixed Address (FA) - If set to ‘1’, the data will be fetched from the same address for the entire size of the descriptor transfer. This is useful when writing to IO peripheral registers in combination with a conditional descriptor. If set to ‘0’, normal operation mode is attained. GRIP, Apr 2018, Version 2018.1 435 www.cobham.com/gaisler GRLIB IP Core 3 Table 487. GRDMAC B2M descriptor control field (address offset 0x08) B2M descriptor AHB Master Interface Number (AN) - If set to ‘0’, the descriptor’s transfer will be performed by the main AHB Master Interface (AHBM0). If set to ‘1’, the descriptor’s transfer will be performed by the second AHB Master Interface (AHBM1). If this interface is not enabled by the configuration generic en_ahbm1, then the transfer will fall back to the main AHB Master Interface (AHBM0). 2 B2M descriptor Interrupt Enable (IE) - If set to one, an interrupt will be generated when the B2M descriptor is completed. Descriptor interrupt generation also depends on interrupt mask for channel 0 and global interrupt enable. 1 B2M descriptor write-back (WB) - If set to one, the descriptor’s status field will be written back in main memory after completion. 0 B2M descriptor Enable (EN) - If set to one, the descriptor will be enabled, otherwise it will be skipped and the next descriptor fetched from memory. Table 488. GRDMAC B2M descriptor status field (address offset 0x0C) 31 3 RESERVED 2 1 0 E S C 2 B2M descriptor error (E) - If set to one, an error was generated during execution of the B2M descriptor. See error register for more information. 1 B2M descriptor status (S) - If set to one, the descriptor is being executed and running. Otherwise set to zero. 0 B2M descriptor completion (C) - If set to one, the descriptor was completed successfully. If a descriptor’s write-back bit in its control field is set to one, the descriptor’s status field will be written back to memory after completion. The transfer uses the AMBA AHB Master interface of the core. 39.2.4 Conditional descriptors A conditional descriptor is a special kind of descriptor which bonds to a data descriptor and provides additional conditional behavior to it. A conditional descriptor can be used to create a DMA channel that retrieves data from IO cores, therefore off loading the CPU from the task. Usually IO cores provide a status register or an interrupt line to notify the CPU of the availability of new data. A conditional descriptor can be set up to poll this status register or to be triggered by an interrupt, signaling for instance, the availability of new data. Once data is available, the bond data descriptor is executed, accumulating the data in the internal buffer of the DMA core, before bursting it to memory for the software to handle it. There are, hence, two kinds of conditional descriptors: polling conditional descriptors or triggering conditional descriptors. The former kind will continuously poll an address for data, and once a termination condition on the retrieved data is met, will yield to the data descriptor. The latter kind will instead have the core entering a state where it waits for a monitored input signal line to trigger. When the monitored input line is sampled to a value of ‘1’, the data descriptor will be executed. To set up a triggering conditional descriptor, the IT bit field in the descriptor’s control field needs to be set to ‘1’. Bits 5:0 of the conditional address/triggering line field will specify which of the 64 input lines of the IRQ_TRIG signal will be monitored. During the execution of the triggering conditional descriptor, the triggering line is monitored every clock cycle, and when the value of the line is ‘1’, the conditional execution will terminate and the data descriptor will be yield, fetching COND_SIZE bytes before going back to executing the conditional triggering. The data descriptor will be considered completed when all the bytes from the data descriptor, specified in the SIZE field, have been transfered, in amounts of COND_SIZE at each triggering. If the timer_en VHDL configuration generic is set to ‘1’, an optional timeout counter can be enabled during the triggering conditional descriptor execution. By setting the TE bit field in the core’s control register to ‘1’ and by setting the Timer Reset Value Register to the required number of clock cycles, the descriptor execution is halted with a Timeout Error if GRIP, Apr 2018, Version 2018.1 436 www.cobham.com/gaisler GRLIB IP Core an interrupt is not received before the timer expires. The error halts the channel execution after eventual descriptor write-back is performed. To set up a polling conditional descriptor, the IT bit field in the descriptor’s control field needs to be set to ‘0’. Bits 31:0 of the conditional address/triggering line field will point to the address that the DMA core will poll for data until the termination condition is TRUE. The condition is specified as the bitwise AND between the 32-bit word pointed by COND_ADDR and the COND_MASK. This value is compared to 0 according to the following formulas, according to the termination condition type selected in the conditional control field (CT). Table 489. GRDMAC Conditional descriptor Termination condition type 0  *COND_ADDR  COND_MASK  = 0 Table 490. GRDMAC Conditional descriptor Termination condition type 1 *COND_ADDR  COND_MASK  0 When the condition is TRUE, the conditional descriptor will stop polling and will proceed with fetching COND_SIZE bytes from the data descriptor pointed by NEXT_PTR. The behavior of conditional descriptors is explained in depth in paragraph 39.3.2. Also in paragraph 39.3.2 is an example configuration of a conditional DMA channel for UART reading. Table 491.GRDMAC Conditional descriptor format Address offset Field 0x0 Conditional next_descriptor 0x4 Conditional address/triggering line 0x8 Conditional control 0xC Conditional mask Table 492. GRDMAC Conditional descriptor next_descriptor field (address offset 0x00) 31 4 NEXT_PTR 31: 4 0 3 1 0 RESERVED DT Conditional Next descriptor pointer address (NEXT_PTR) - Address of the data descriptor in the descriptor chain which the conditional descriptor is bond to. Cannot be NULL. Conditional descriptor type (DT) - Descriptor type field, ‘0’ for data descriptors, ‘1’ for conditional descriptors. Must be set to ‘1’ for this type of descriptor. Table 493. GRDMAC Conditional descriptor address field (address offset 0x04) 31 6 COND_ADDR[31:6] GRIP, Apr 2018, Version 2018.1 437 5 0 COND_ADDR[5:0] / IRQN www.cobham.com/gaisler GRLIB IP Core 31: 0 5: 0 Table 493. GRDMAC Conditional descriptor address field (address offset 0x04) Conditional Address (COND_ADDR) - Address of the 32-bit word the core will read for the conditional termination expression matching. IRQ Trigger Line Number (IRQN) - Index of the IRQ_TRIG signal input vector which is used as the triggering line for triggered conditional descriptors, 0 to 63. Table 494. GRDMAC Conditional descriptor control field (address offset 0x08) 31 16 15 COND_SIZE 4 COUNTER_RST 3 2 1 0 AN CT IT EN 31: 16 Conditional descriptor total size (COND_SIZE) - Total size in Bytes of the data that will be fetched from the bond data descriptor each time the conditional termination expression matches to true. 15: 4 Conditional descriptor counter reset value (COUNTER_RST) - Reset value of the conditional counter timer that is executed before every polling or triggering. The unit is number of clock cycles and the purpose is to provide a timer between polling requests onto the AMBA AHB bus with enough clock cycles in order not to clog the bus. 3 Conditional descriptor AHB Master Interface Number (AN) - If set to ‘0’, the descriptor’s transfer will be performed by the main AHB Master Interface (AHBM0). If set to ‘1’, the descriptor’s transfer will be performed by the second AHB Master Interface (AHBM1). If this interface is not enabled by the configuration generic en_ahbm1, then the transfer will fall back to the main AHB Master Interface (AHBM0). 2 Conditional descriptor Termination Condition type (CT) - If the conditional descriptor is of type “polling”, this bits specifies which type of termination condition is used. If ‘0’, the termination condition is of type 0 as specified in this paragraph. If ‘1’, the termination condition is of type 1. 1 Conditional Descriptor Irq Trigger (IT) - If set to ‘1’, the conditional descriptor will wait for the input interrupt line to go high before executing the bond data descriptor. The selected interrupt line is the one indexed by IRQN in the IRQ_TRIG signal input vector. This bit enables triggering behavior of conditional descriptors. If this bit is set to ‘0’, normal polling behavior with termination condition is enabled. 0 Conditional descriptor Enable (EN) - If set to one, the descriptor will be enabled, otherwise it will be skipped and the next descriptor fetched from memory. Table 495. GRDMAC Conditional descriptor mask field (address offset 0x0C) 31 0 COND_MASK 31: 0 Conditional Mask (COND_MASK) - Bit mask used in the conditional descriptor termination condition matching. 39.2.5 Register setup Once the channel vector and the relative descriptor chains are setup in main memory, the GRDMAC register must be also setup. The 128-byte-aligned address, where the Channel Vector resides, must be written in the Channel Vector Pointer register. The control register must also be setup. Once the enable bit of the control register is set to one, the core will start running and will execute all the channels which are enabled. 39.3 Operation 39.3.1 Normal mode of operation In normal mode of execution, GRDMAC will start executing all the enabled channels until they are complete or an error is generated. GRIP, Apr 2018, Version 2018.1 438 www.cobham.com/gaisler GRLIB IP Core When executing a DMA channel, the core will initially fetch the two descriptor pointers from the address provided in the CVP register which are relative to the channel. It will then fetch the first M2B and B2M descriptors from main memory. The M2B descriptor chain is then executed until either the internal buffer is full, or the M2B chain is completed. If one of this events happen, the core will switch to the B2M descriptor chain. The B2M chain will switch back to the M2B chain when the buffer is empty. The DMA channel is marked complete when the last descriptor in the B2M chain is executed, finally emptying the buffer. During the execution of a chain, the core will fetch a new descriptor after the successful completion of the previous one, following the pointers in the linked list. When the core reaches a NULL pointer in the M2B chain, it will switch to the B2M chain. When it reaches a NULL pointer in the B2M chain, the core will update the DMA channel status and switch to the next enabled DMA channel, until all the channels are completed. 39.3.2 Operation with conditional descriptors Conditional descriptors bond to the following data descriptor in the linked list and provide conditional behavior to the execution of the data descriptor. During the execution of a DMA channel, when the core fetches a conditional descriptor from memory, it will proceed and fetch the following descriptor in the chain as well, which must be a data descriptor. After the descriptors’ pair has been fetched, the conditional execution will follow these steps: a) the core will execute the conditional counter, down counting for COUNTER_RST clock cycles b) if the conditional descriptor is a polling descriptor, go to step c1, if it’s a triggering descriptor, go to step c2. c1) the core will fetch a 32-bit word at the COND_ADDR address. d1) if the conditional termination condition of Table 490 is false then the core will go back to step a, if the conditional termination condition of Table 490 is true, the core will fetch a portion of the data from the data descriptor which is COND_SIZE bytes, then go back to step a. c2) the core will monitor line IRQN of the IRQ_TRIG input signal, indefinitely or until the trigger counter expires. d2) when the monitored line has a value of ‘1’, the core will fetch a portion of the data from the data descriptor which is COND_SIZE bytes, then go back to step a. The total SIZE of the bond data descriptor will be decremented by COND_SIZE bytes every time the bond data descriptor is executed, and the ADDRESS will be incremented by the same amount (unless the FA flag is set). The FA (Fixed Address) bit field in the data descriptor control field is useful when accessing data to/ from a peripheral data register, i.e. UART data register, when you need to read/write always from/to the same address. The execution of the descriptor pair (conditional and bond data descriptors) ends when the SIZE field of the data descriptor reaches 0. In other words, the execution ends when SIZE bytes have been fetched in total from the data descriptor, by fetching COND_SIZE byte amounts every time the conditional condition (polling or triggering) is true. 39.3.3 Simplified mode of operation In Simplified Mode of Operation, the GRDMAC core configuration resides entirely in its configuration registers and the Channel Vector structure is not used. The core will not perform any memory access to fetch configuration data. This mode of operation makes use of only two data descriptors, respectively one descriptor for M2B transfers and one for B2M transfers. Conditional descriptors are not supported in this mode. The descriptors are written directly onto GRDMAC via APB at offsets 0x20 and 0x30. Their next_descriptor field is hardwired to zeroes. Their status is always written-back to their relative descriptor status register. GRIP, Apr 2018, Version 2018.1 439 www.cobham.com/gaisler GRLIB IP Core When the core is configured in Simplified mode of operation, the relative bit (SM) must be set to one in the control register. The core will execute the two internal descriptors on channel zero. Channel zero must therefore be enabled, and the core status can be read on channel zero’s status bits in the status register. 39.4 AHB transfers For every descriptor executed, GRDMAC will perform an AHB data transfer at the address and of the size specified. The AHB accesses that it can perform are up to 128-bit wide and can be at aligned or unaligned memory addresses. The maximum AHB access width depends on the AHB bus width and on the busw and wbmask generics, as described in paragraph 39.7. The core will perform unaligned memory access if defined by the descriptors. It will perform byte (8 bit) accesses at byte-aligned addresses, half-word (16 bit) accesses at half-word aligned addresses, and so on. The core will perform burst transfers of the maximum supported width for as long as possible according to the total transfer size. For example, if the maximum supported bus width for one transfer is 64-bit, and a descriptor requests 18 bytes at address 0x40000006, the core will perform one 16-bit half-word access, and one two-beat burst of double words. In some cases, the total transfer size might require GRDMAC to perform additional word, half-word and/or byte accesses at the end of the transfer. The burst accesses performed by GRDMAC are of type incrementing burst of unspecified length. These bursts will never cross a 1KB memory boundary, or a smaller boundary that can be set with the generic burstbound. At the specified memory boundary set by burstbound, the burst will be interrupted, an idle cycle will be inserted and the incrementing burst of unspecified length will restart from the next address. This generic can be used to limit the maximum burst length performed by the core, making re-arbitration on the AHB bus more frequent. When the core is configured with the VHDL generic en_ahbm1 set to ‘1’, a secondary AHB Master interface will be instantiated inside the GRDMAC core. This interface can be connected to a second AHB bus to provide bridging capabilities to the DMA controller. The core will fetch data from this interface when the AN flag in the descriptor’s control field is set accordingly. This flag will be ignored in case the core is configured with the en_ahbm1 VHDL generic set to ‘0’. 39.5 Data realignment buffer The realignment buffer is the data buffer used internally by the GRDMAC core. The component allows the core to store the data in a tightly packed way, being optimized to store AMBA AHB transfer data of different size and at different address offsets. The internal buffer uses RAM implemented using GRLIB parameterizable SYNCRAMBW memories, assuring portability to all supported technologies. Internally two SYNCRAMBW are used, one for even words and one for odd words. The total number of RAMs used depends on the bufsize generic, and its minimum size is two words, 8 bytes. To control the implementation technology of the internal RAMs, the technology mapping generic memtech may be used. Additionally, the generic testen will be propagated to the SYNCRAMBW and is used to enable scan test support. Fault tolerance can be added to the RAM by setting the ft generic to a value different than 0. To obtain byte parity DMR memories, set the ft generic to 1. To use TMR set it to 2. Note that the ft generic needs to be set to 0 unless the core is used together with the fault tolerant version of GRLIB, which is not available under the terms of the GPL. 39.6 Interrupts GRDMAC provides fine-grained control of interrupt generation. At the highest level, the global Interrupt Enable bit (IE) in the control register can be set to zero to mask every interrupt setting in the core. If set to one, interrupt generation depends on the following settings. The Interrupt on Error Enable bit (IEE) in the control register provides a way to generate interrupts in the event of errors. Error generation is discussed further in the next paragraph. GRIP, Apr 2018, Version 2018.1 440 www.cobham.com/gaisler GRLIB IP Core An interrupt can be also generated by the successful completion of a descriptor, if the Interrupt Enable (IE) bit is set to one in the descriptor’s control field. The Interrupt Mask bit (Ix) in the Interrupt Mask register can be set to zero to mask all the descriptor completion interrupts. If descriptor write-back is enabled, the interrupt will be generated after writing back the descriptor’s status in main memory. For both interrupts on error and interrupts on descriptor completion events, a flag will be raised in the interrupt flag register at the bit corresponding to the channel where the interrupt event happened (IFx). As an example of interrupt generation setup, one can enable interrupt on channel completion by performing the following steps. The Interrupt Enable (IE) bit in GRDMAC control register must be set to one, as must be the relevant channel’s interrupt mask bit in the Interrupt mask register. Finally the Interrupt Enable (IE) bit in the control field of the last descriptor in the B2M chain of the channel must be set to one, while the same field must be set to zero in every other descriptor in the channel. This way, when the last descriptor in the buffer to memory chain is completed successfully, an interrupt will be generated. 39.7 Wide Data Bus support The size of AMBA accesses supported through GRDMAC’s AHB master interfaces depends on the maximum bus width and if the accessed memory area has been marked as being on the wide bus. The generic wbmask is treated as a 16 bit mask where every bit represents a 256 MiB block of memory, with the least significative bit representing the range 0 - 0x10000000. If the corresponding bit is set to one, GRDMAC with perform wide accesses to that memory area. The size of the accesses is controlled with the busw generic. If the generic is set to 0, only 32 bit accesses will be performed. Furthermore, the size of the AHB accesses can be limited with the Transfer Size Limit (TSL) field in the control register of GRDMAC. If the field is set to 1, the core will limit its maximum AHB transfer size to 32 bits. If it is set to 2, the limit will be 64 bits, and if it is set to 3, the limit will be 128 bits. The field must be interpreted as an upper limit on the transfer size and is subject to the wbmask and busw generic. 39.8 Errors Four types of errors can be generated by GRDMAC. Transfer errors, descriptor errors, Channel Vector Pointer errors, conditional errors and timeout errors, as defined in the Error Register. Transfer errors are generated when the core is accessing DMA data from and to memory and it encounters an AMBA AHB ERROR response. When a transfer error occurs on a descriptor which has the write-back flag enabled, the descriptor status will be written back to main memory with the error field set to one. An eventual interrupt will be generated only after the write back. Descriptor errors are generated when an ERROR response is received while reading or writing back a descriptor in main memory. Channel Vector Pointer errors are generated when the core receives an ERROR response when accessing the Channel Vector data structure in main memory. Conditional errors are generated when a conditional polling descriptor encounters a problem during an AHB polling operation such as an ERROR response. Finally timeout errors are caused by the timeout counter expiring before receiving an interrupt during triggered conditional descriptor execution. This requires the timer_en VHDL configuration generic to be set to ‘1’ and the TE bit field in the control register to be configured to ‘1’ during execution. The core will enable the corresponding error type bit in the error register in addition to the error flag bit (E). The channel number where the error happened can be also read directly from the channel error field (CHERR) of the error register. Additionally an interrupt will be generated if the Interrupt on Error Enable bit (IEE) and the global Interrupt Enable (IE) bit in GRDMAC control register are set to one, and a flag will be raised in the interrupt flag register bit corresponding to the channel where the error event occurred (IFx). GRIP, Apr 2018, Version 2018.1 441 www.cobham.com/gaisler GRLIB IP Core 39.9 Internal Buffer Readout Interface In case of an error, the execution of the DMA channels will halt and the error will be reported as described in the previous session. It can happen that data that has been accumulated in the internal buffer during the M2B chain transactions, is not written out as part of the B2M chain, due to the channel halting. This internal data can still be read via the APB interface of the GRDMAC core, through the Internal Buffer Readout Interface memory area. The memory area is located at offset 0x800 to 0xFFF of the GRDMAC core memory address, totaling 2 KiB of accessible Internal Buffer space, as seen in Table 496. This area can only be read when the core is in an idle state and bit flag EN of the Control Register is set to ‘0’. The amount of valid data in the internal buffer can be inferred by reading the read pointer and write pointers to the buffer from the Internal Buffer Pointers Register (offset 0x40). 39.10 Endianness The core is designed for big-endian systems. 39.11 Registers The core is programmed through registers mapped into APB address space. The APB address is configured with the paddr and pmask generics. If the core is instantiated with the internal AHB/APB bridge, the haddr and hmask generics will configure the APB address space. Table 496.GRDMAC controller registers APB address offset Register 0x00 Control register 0x04 Status register 0x08 Interrupt mask register 0x0C Error register 0x10 Channel Vector Pointer 0x14 Timer Reset Value register 0x18 Capability register 0x1C Interrupt flag register 0x20 Reserved 0x24 M2B Descriptor Address register* 0x28 M2B Descriptor Control register* 0x2C M2B Descriptor Status register* 0x30 Reserved 0x34 B2M Descriptor Address register* 0x38 B2M Descriptor Control register* 0x3C B2M Descriptor Status register* 0x40 Internal Buffer Pointers Register 0x800-0xFFF Internal Buffer Readout Area *Only used in Simplified Mode of Operation GRIP, Apr 2018, Version 2018.1 442 www.cobham.com/gaisler GRLIB IP Core 39.11.1 Control Register Table 497.GRDMAC control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 6 RESERVED 5 4 3 2 EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 TSL NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR 0 NR NR NR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw * 1 0 TE SM IEE IE RS EN 0 0 rw rw rw rw rw 31: 16 Enable channel x (Ex) - Set to one to enable DMA channel x, from 0 to 15. 15 12 Transfer Size limit (TSL) - If set to 1, the GRDMAC core will limit its maximum transfer size to 32b accesses. If set to 2, it will limit the transfer size to 64 bits. If set to 3, it will limit the maximum transfer size to 128 bit. If set to 0 no limit is imposed. The maximum transfer size is controlled by the wbmask and busw generics. 5 Timer Enable (TE) - Set to ‘1’ to enable the timeout timer during triggered conditional descriptor execution. If the timer_en generic is set to ‘1’, the field is rw, read-only otherwise. 4 Simplified mode (SM) - Set to one to use the core in simplified mode of operation 3 Interrupt enable for Errors (IEE) - Set to one to enable interrupt generation on error. Interrupt generation on error depends on the global Interrupt Enable (IE). 2 Interrupt Enable (IE) - Global Interrupt Enable. If set to zero, no interrupt will be generated. If set to one, interrupts from errors, descriptor completion, won’t be masked. 1 Reset (RS) - Resets the core register if set to one. 0 Enable/Run (EN) - When set to one, the core will be enabled and start running. 39.11.2 Status Register Table 498.GRDMAC status register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SF SE SD SC SB SA S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 CF CE CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r 31: 16 Status of channel x (Sx) - Set to one if DMA channel x is running, set to zero otherwise. 15: 0 Completion of channel x(Cx) - Set to one if DMA channel x has completed successfully, zero otherwise. 39.11.3 Interrupt Mask Table 499.GRDMAC Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IF IE ID IC IB IA 9 8 7 6 5 4 3 2 1 0 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15: 0 Interrupt Mask for channel x (Ix) - Set to 0 to mask descriptor interrupt generation from channel x. Interrupt generation depends on the global Interrupt Enable in the control register. GRIP, Apr 2018, Version 2018.1 443 www.cobham.com/gaisler GRLIB IP Core 39.11.4 Error Register Table 500.GRDMAC error register 31 20 19 RESERVED 16 15 6 CHERR 5 RESERVED 4 3 2 1 0 ME OE TE DE CE E 0 r 0 0 0 0 0 wc wc wc wc wc wc 19: 16 Channel error (CHERR) - Channel number where last error was generated. 5 Timeout Error (ME) - One if the last generated error was of type timeout error. This field is cleared by writing a one to it. 4 Conditional Error (OE) - One if the last generated error was of type conditional execution error. This field is cleared by writing a one to it. 3 Transfer Error (TE) - One if the last generated error was of type transfer error. This field is cleared by writing a one to it. 2 Descriptor Error (DE) - One if the last generated error was of type descriptor error. This field is cleared by writing a one to it. 1 CVP Error (CE) - One if the last generated error was of type CVP error. This field is cleared by writing a one to it. 0 Error (E) - If set to one, an error was generated by the entity. This field is cleared by writing a one to it. 39.11.5 Channel Vector Pointer Table 501.GRDMAC Channel Vector Pointer 31 7 6 0 CVP RESERVED NR rw 31: 7 Channel Vector Pointer (CVP) - 128 Byte aligned memory address pointing to the vector of up to 16 couples of descriptor chain pointers. 39.11.6 Timer Reset Value Register Table 502.GRDMAC Timer Reset Value Register 31 0 TIMER_RST 0x00000000 * 31: 0 Timer Reset Value (TIMER_RST) - Reset value for the triggered conditional descriptor timeout timer. If the timer_en generic is set to ‘1’, the field is rw, read-only otherwise. 39.11.7 Capability Register Table 503.GRDMAC capability register 31 16 15 BUFSZ 31: 16 11 12 11 10 RESERVED 9 8 7 4 3 0 TT FT H1 NCH VER * * * * * * r r r r r r Buffer size (BUFSZ) - Binary logarithm of the internal buffer size of the entity. Timer (TT) - If set to ‘1’, the timeout timer is enabled. GRIP, Apr 2018, Version 2018.1 444 www.cobham.com/gaisler GRLIB IP Core Table 503.GRDMAC capability register 10: 9 Fault Tolerant buffer (FT) - These bits indicate if the internal buffers in the core is implemented with fault tolerance. When 0, no fault tolerance, when 1, byte parity DMR, when 2, TMR. Reflects the VHDL generic ft. 8 Second AHB Master (H1) - If set to one, the second AHB master interface (AHBM1) is enabled. 7: 4 Channel Number (NCH) - The maximum number of supported DMA channels in the core is NCH+1. 3: 0 Version (VER) - GRDMAC version number. GRIP, Apr 2018, Version 2018.1 445 www.cobham.com/gaisler GRLIB IP Core 39.11.8 Interrupt Flag Register Table 504.GRDMAC interrupt flag register 31 16 15 14 13 12 11 10 RESERVED 9 8 7 6 5 4 3 2 1 0 IFF IFE IFD IFC IFB IFA IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 IF0 NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR NR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15: 0 Interrupt flag for channel x (IFx) - When set to one, an interrupt event (descriptor completion or error) was generated on channel x. This field is cleared by writing a one to it. 39.11.9 M2B Descriptor Address Register* Table 505.GRDMAC M2B descriptor address register* 31 0 ADDR NR rw 31: 0 M2B Address (ADDR) - Starting address the core will read data from. 39.11.10M2B Descriptor Control Register* Table 506.GRDMAC M2B descriptor control register* 31 16 15 SIZE 31: 16 3 RESERVED 2 1 IE R EN 0 NR NR NR rw rw rw* M2B descriptor size (SIZE) - Size in Bytes of the data that will be fetched from the address specified in the M2B address register. 2 M2B descriptor Interrupt Enable (IE) - If set to one, an interrupt will be generated when the M2B descriptor is completed. Descriptor interrupt generation also depends on interrupt mask for channel 0 and global interrupt enable. 0 M2B descriptor Enable (EN) - Set to one when the descriptor is written the first time. Write value ignored. 39.11.11 M2B Descriptor Status Register* Table 507.GRDMAC M2B descriptor status register* 31 3 RESERVED 2 1 0 E S C 0 0 0 rw rw rw 2 M2B descriptor error - If set to one, an error was generated during execution of the M2B descriptor. See error register for more information. 1 M2B descriptor status (S) - If set to one, the descriptor is being executed and running. Otherwise set to zero. 0 M2B descriptor completetion (C) - If set to one, the descriptor was completed successfully. 39.11.12 B2M Descriptor Address Register* Table 508.GRDMAC B2M descriptor address register* 31 0 ADDR GRIP, Apr 2018, Version 2018.1 446 www.cobham.com/gaisler GRLIB IP Core Table 508.GRDMAC B2M descriptor address register* NR rw 31: 0 B2M Address (ADDR) - Starting address the core will write data to. 39.11.13 B2M Descriptor Control Register* Table 509.GRDMAC B2M descriptor control register* 31 16 15 SIZE 31: 16 3 RESERVED 2 1 IE R EN 0 NR NR NR rw rw rw* B2M descriptor size (SIZE) - Size in Bytes of the data that will be written to the address specified in the B2M address register. 2 B2M descriptor Interrupt Enable (IE) - If set to one, an interrupt will be generated when the B2M descriptor is completed. Descriptor interrupt generation also depends on interrupt mask for channel 0 and global interrupt enable. 0 B2M descriptor Enable (EN) - Set to one when the descriptor is written the first time. Write value ignored. 39.11.14 B2M Descriptor Status Register* Table 510.GRDMAC B2M descriptor status register* 31 3 RESERVED 2 1 0 E S C 0 0 0 rw rw rw 2 B2M descriptor error - If set to one, an error was generated during execution of the B2M descriptor. See error register for more information. 1 B2M descriptor status (S) - If set to one, the descriptor is being executed and running. Otherwise set to zero. 0 B2M descriptor completion (C) - If set to one, the descriptor was completed successfully. 39.11.15 Internal Buffer Pointers Register Table 511.GRDMAC internal buffer pointers register* 31 16 15 0 READ_P WRITE_P 0 0 r r 31: 16 B2M Internal Buffer Read Pointer (READ_P)- Points to the last offset in the internal buffer which was correctly read by the core and output on the bus. 15: 0 B2M Internal Buffer Write Pointer (WRITE_P) - Points to the last offset in the internal buffer which was correctly written by the core as an input from the bus. *Register used only when the core is set to work in Simplified mode of operation. 39.12 Example DMA channel set-up In this example a single DMA channel will be set-up, using conditional descriptors, to gather data from the UART core (APBUART) and write it into main memory. GRIP, Apr 2018, Version 2018.1 447 www.cobham.com/gaisler GRLIB IP Core The GRDMAC core is configured with its register address-space starting at address 0xCCC00200 and main memory starts at 0x40000000. The APBUART core’s register is mapped at 0xCCC00100 and the UART receiver FIFO queue is configured as 4 bytes. The DMA channel will need two descriptors in the M2B chain: a conditional descriptor bound to a data descriptor. The B2M chain will only need one data descriptor. The conditional descriptor will poll the UART status register, mapped at 0xCCC00104, and will use the mask 0x00000100 for the termination condition. This mask will be ANDed with the status register, and the result of this operation will only show the value of the “Receiver FIFO half-full” field in the status register. This will enable the conditional register to stop polling when this bit becomes ‘1’. At this point the data descriptor will be executed for the amount of bytes specified in the conditional descriptor, which in this case is 1 bytes (half of the FIFO size). For the data transfer to read and accumulate correct data, the core must perform a single-byte access. The UART data register contains only one byte of relevant data. The size limit per transfer is therefore 1 byte and the address is marked as fixed, so the core will not increment it after every transfer. The polling counter for the conditional descriptor is set according to the UART speed. If the UART baud rate is 38.4K and the system frequency is 100 MHz, one can assume that there is going to be 1 Byte available in the UART every 26k clock cycles. Setting the polling period to a value less than 26K will let the DMA get all the characters from the UART without missing any. The conditional counter reset value is set to its maximum, a period of 4095 clock cycles (0xFFF). The polling will restart after the last read and the transfers will go on until the total size specified in the SIZE field of the data descriptor is reached. At this point the M2B chain is completed and the core will proceed with the B2M chain, emptying the contents of its buffer into memory, at the address specified. GRIP, Apr 2018, Version 2018.1 448 www.cobham.com/gaisler GRLIB IP Core Table 512 shows the memory layout of the system with the required data to set-up this example. Note that the Channel Vector is 128-byte aligned and the descriptors are 16-byte aligned, Table 512. Memory Content Address Data 0x40000080 0x40020010 Channel Vector - Channel 0 M2B descriptor chain pointer 0x40000084 0x40020040 Channel Vector - Channel 0 B2M descriptor chain pointer ... ... 0x40020010 0x40020031 0x40020014 0xCCC00104 M2B conditional descriptor 0 - address (UART status register address) 0x40020018 0x0001FFF1 M2B conditional descriptor 0 - control (poll every 4095 cycles, get 1 Byte) 0x4002001C 0x00000080 M2B conditional descriptor 0 - mask (only check “Receiver FIFO half-full”) ... ... 0x40020030 0x00000000 M2B data descriptor 0 - next descriptor pointer (NULL, end of chain) 0x40020034 0xCCC00100 M2B data descriptor 0 - address (UART data register address) 0x40020038 0x04000011 M2B data descriptor 0 - control (1024 Bytes from fixed address) 0x4002003C - ... ... 0x40020040 0x00000000 0x40020044 0x40030000 B2M data descriptor 0 - address (DMA write address for UART data) 0x40020048 0x04000001 B2M data descriptor 0 - control (1024 Bytes) 0x4002004C - ... ... 0x40030000 - ... ... 0xCCC00200 0x0001000C 0xCCC00204 - 0xCCC00208 0x00000001 0xCCC0020C - 0xCCC00200 0x40000080 0xCCC00204 - 0xCCC00208 0x02000812 0xCCC0020C - Description M2B conditional descriptor 0 - next descriptor pointer (lsb set to 1 for cond. desc.) M2B data descriptor 0 - status (written by core) B2M data descriptor 0 - next descriptor pointer (NULL, end of chain) B2M data descriptor 0 - status (written by core) UART data written by the DMA core GRDMAC Control register GRDMAC Status register (updated by the DMA core) GRDMAC interrupt mask register GRDMAC error register (updated by the DMA core) GRDMAC channel vector pointer Reserved GRDMAC capability register GRDMAC interrupt flag register (updated by the DMA core) as required by the core. The core is configured with only one DMA channel (channel 0) and one master interface, as can be seen in the capability register. Additionally the internal core’s buffer is 512 Bytes and the time-out timer is available. The core’s control register is pre-set to enable channel 0 and to enable interrupts and interrupts on errors. To start the execution of the channel the software will write a ‘1’ to the enable bit in the control register, usually by reading the register, performing a logical OR with 0x00000001, and writing the value back to the register. In this case the value that needs to be written to address 0xCCC00200 to correctly start execution is 0x0001000D. 39.13 Vendor and device identifier The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x095. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 39.14 Implementation 39.14.1 Reset The core changes reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). GRIP, Apr 2018, Version 2018.1 449 www.cobham.com/gaisler GRLIB IP Core The core will add reset for all registers if the GRLIB config package setting grlib_sync_reset_enable_all is set. The core does not support grlib_async_reset_enable. All registers that react on the reset signal will have a synchronous reset. 39.15 Configuration options Table 513 shows the configuration options of the GRDMAC core (VHDL generics). These options are specific to the generic entity grdmac. See the chapter Instantiation for more details on specialized versions of GRDMAC. Table 513.Configuration options Generic Function Allowed range Default hmindex AHB master index (AHBM0) 0 - NAHBMST-1 0 hirq IRQ line used by GRDMAC 0 - NAHBIRQ-1 0 pindex APB slave index 0 - NAPBSLV-1 0 paddress Addr field of the APB bar. 0 - 16#FFF# 1 pmask Mask field of the APB bar. 0 - 16#FFF# 16#FFF# en_ahbm1 Enable second AHB master interface (AHBM1) 0 - NAHBMST-1 0 hmindex1 Second AHB master (AHBM1) index 0 - NAHBMST-1 1 ndmach Number of available DMA channels. 1 - 16 1 bufsize Internal buffer size. Must be a power of 2. 8 - 65536 256 burstbound Boundary that the burst will never cross. Maximum is 1KB as per the AMBA AHB standard. Could be set to smaller values to ease re-arbitration. Must be a multiple of 2. 4 - 1024 512 timer_en Enables the implementation of the timeout counter which can be set during triggered conditional descriptor execution. 0-1 0 memtech Internal buffer’s memory technology selection 0 - NTECH 0 testen Enable bypass logic for scan testing 0-1 0 ft This generic determines if fault tolerance should be added to the internal data realignment buffer. 0 = no fault tolerance, 1 = byte parity DMR, 2 = TMR. Note that this generic needs to be set to 0 if the core is used together with the GPL version of GRLIB, since that version does not include any fault tolerance capability. 0-2 0 wbmask Wide-bus mask. Indicates which address ranges are 64/ 0 - 16#FFFF# 128 bit capable. Treated as a 16-bit vector with LSB bit (right-most) indicating address 0 - 0x10000000. See section 39.7 for more information. 0 busw Bus width of the wide bus area (64 or 128). See section 39.7 for more information. 64 GRIP, Apr 2018, Version 2018.1 450 64, 128 www.cobham.com/gaisler GRLIB IP Core 39.16 Signal descriptions Table 514 shows the interface signals of the core (VHDL ports). Table 514.Signal descriptions Signal name Field Type Function Active RST N/A Input AHB reset Low CLK N/A Input AHB clock - AHBMI * Input AHB master input - AHBMO * Output AHB master output - AHBMI1 * Input AHB second master input - AHBMO1 * Output AHB second master output - APBI * Output APB slave inputs - APBO * Input APB slave outputs - Input Descriptor triggering input IRQ_TRIG[63:0] * see GRLIB IP Library User’s Manual 39.17 Library dependencies Table 515 shows the libraries used when instantiating the core (VHDL libraries). Table 515.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER GRDMAC_PKG Components, signals GRDMAC internal components and signals. 39.18 Instantiation In addition to the generic GRDMAC version, grdmac, a single-port version of the core is available, grdmac_1p, where the en_ahbm1 generic is preset to ‘0’, and the generics and ports related to the dual-port functionality are removed for convenience. library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.misc.all; use gaisler.grdmac_pkg.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; entity grdmac_ex is end entity; architecture rtl of grdmac_ex is -- AMBA signals signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); GRIP, Apr 2018, Version 2018.1 451 www.cobham.com/gaisler GRLIB IP Core begin -- ... AHBCTRL -- GRDMAC one-AHB-port, AHB master index 1, APB index 0 -- internal buffer size 1024 bytes, will break bursts at 512 byte boundaries -- APB registers at address 0xCCC00200 dma0 : grdmac_1p generic map ( hmindex => 1, pindex => 0, paddr => 16#002#, hirq => 1, ndmach => 2, bufsize => 1024, --bytes burstbound => 512 -- bytes ) port map (rstn, clk, ahbmi, ahbmo(1), apbi, apbo(0)); -- AHB/APB bridge, AHB slave index 2 apb0: apbctrl generic map (hindex => 2, haddr => 16#CCC#) port map (rstn, clk, ahbsi, ahbso(2), apbi, apbo); -- ... APB peripherals end architecture ; -- rtl GRIP, Apr 2018, Version 2018.1 452 www.cobham.com/gaisler GRLIB IP Core 40 GRECC - Elliptic Curve Cryptography 40.1 Overview Elliptic Curve Cryptography (ECC) is used as a public key mechanism. The computational burden that is inhibited by ECC is less than the one of RSA. ECC provides the same level of security as RSA but with a significantly shorter key length. ECC is well suited for application in mobile communication. The GRECC core implements encryption and decryption for an elliptic curve based on 233-bit key and point lengths. The implemented curve is denoted as sect233r1 or B-233. The sect233r1 elliptic curve domain parameters are specified in the “Standards for Efficient Cryptography (SEC) - SEC2: Recommended Elliptic Curve Domain Parameters” document. The document is established by the Standards for Efficient Cryptography Group (SECG). The B-233 elliptic curve domain parameters are specified in the “Digital Signature Standard (DSS)” document, Federal Information Processing Standards (FIPS) Publication 186-2. The document is established by the National Institute of Standards and Technology (NIST). The GRECC can be used with algorithms such as: • Elliptic Curve Digital Signature Algorithm DSA (ECDSA), which appears in FIPS 186-2, IEEE 1363-2000 and ISO/IEC 15946-2 • Elliptic Curve El Gamal Method (key exchange protocol) • Elliptic Curve Diffie-Hellman (ECDH) (key agreement protocol) The core provides the following internal AMBA APB slave interface, with sideband signals as per [GRLIB] including: • interrupt bus • configuration information • diagnostic information The core can be partition in the following hierarchical elements: • Elliptic Curve Cryptography (ECC) core • AMBA APB slave • GRLIB plug&play wrapper Note that the core can also be used without the GRLIB plug&play information. 40.2 Operation Elliptic Curve Cryptography (ECC) is an asymmetric cryptographic approach (also known as public key cryptography) that applies different keys for encryption and decryption. The most expensive operation during both encryption and decryption is the elliptic curve point multiplication. Hereby, a point on the elliptic curve is multiplied with a long integer (k*P multiplication). The bit sizes of the coordinates of the point P=(x, y) and the factor k have a length of hundreds of bits. In this implementation the key and the point lengths are 233 bit, so that for every key there are 8 write cycles necessary and for every point (consisting of x and y) there are 16 write cycles necessary. After at least 16700 clock cycles the result can be read out. GRIP, Apr 2018, Version 2018.1 453 www.cobham.com/gaisler GRLIB IP Core The key is input via eight registers. The input point Pin=(x, y) is written via eight registers for x and eight registers for y. After the last y input register is written, the encryption or decryption is started. The progress can be observed via the status register. When the operation is completed, an interrupt is generated. The output point Pout=(x, y) is then read out via eight registers for x and eight registers for y. 40.3 Advantages The main operation in ECC is the k*P multiplication. One k*P multiplication requires about 1500 field multiplications in the base field, which is the most expensive base operation. The complexity of a field multiplication can be reduced by applying the Karatsuba method. Normally the Karatsuba approach is applied recursively. The GRECC core includes an iterative implementation of the Karatsuba method which allows to realize area efficient hardware accelerators for the k*P multiplication. Hardware accelerators which are realized applying an iterative approach need up to 60 per cent less area and about 30 per cent less energy per multiplication than the recursive variants. 40.4 Background The Standards for Efficient Cryptography Group (SECG) was initiated by Certicom Corporation to address the difficulty vendors and users face when building and deploying interoperable security solutions. The SECG is a broad international coalition comprised of leading technology companies and key industry players in the information security industry. One of the goals is to enable the effective incorporation of Elliptic Curve Cryptographic (ECC) technology into these various cryptographic solutions. The Standards for Efficient Cryptography Group (SECG) has develop two sets of documents. The first set, under the name SEC, specifies interoperable cryptographic technologies and solutions. The second set, Guidelines for Efficient Cryptography (GEC), provides background information on elliptic curve cryptography and recommendations for ECC parameter and curve selection. The Federal Information Processing Standards Publication Series of the National Institute of Standards and Technology (NIST) is the official series of publications relating to standards and guidelines adopted under the provisions of the Information Technology Management Reform Act. This Digital Signature Standard (DSS) specifies a suite of algorithms which can be used to generate a digital signature. Digital signatures are used to detect unauthorized modifications to data and to authenticate the identity of the signatory. In addition, the recipient of signed data can use a digital signature in proving to a third party that the signature was in fact generated by the signatory. This is known as nonrepudiation since the signatory cannot, at a later time, repudiate the signature. 40.5 233-bit elliptic curve domain parameters The core implements the 233-bit elliptic curve domain parameters sect233r1, or the equivalent B-233, which are verifiably random parameters. The following specification is established in “Standards for Efficient Cryptography (SEC) - SEC 2: Recommended Elliptic Curve Domain Parameters”. The verifiably random elliptic curve domain parameters over F2m are specified by the septuple T = (m; f (x); a; b; G; n; h) where m = 233 and the representation of F2233 is defined by: f (x) = x233+x74 +1 The curve E: y2+xy = x3+ax2+b over F2m is defined by: a = 0000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 b = 0066 647EDE6C 332C7F8C 0923BB58 213B333B 20E9CE42 81FE115F 7D8F90AD The base point G in compressed form is: G = 0300FA C9DFCBAC 8313BB21 39F1BB75 5FEF65BC 391F8B36 F8F8EB73 71FD558B and in uncompressed form is: GRIP, Apr 2018, Version 2018.1 454 www.cobham.com/gaisler GRLIB IP Core G = 04 00FAC9DF CBAC8313 BB2139F1 BB755FEF 65BC391F 8B36F8F8 EB7371FD 558B0100 6A08A419 03350678 E58528BE BF8A0BEF F867A7CA 36716F7E 01F81052 Finally the order n of G and the cofactor are: n = 0100 00000000 00000000 00000000 0013E974 E72F8A69 22031D26 03CFE0D7 h = 02 40.6 Throughput The data throughput for the GRECC core is around 233/16700 bits per clock cycle, i.e. approximately 13.9 kbits per MHz. The underlaying EEC core has been implemented in a dual crypto chip on 250 nm technology as depicted in the figure below. The throughput at 33 MHz operating frequency was 850 kbit/s, the power consumption was 56,8 mW, and the size was 48,5 kgates. Figure 122. Dual Crypto Chip 40.7 Characteristics The GRECC core has been synthesized for a Xilinx Virtex-2 XC2V6000-4 devices with the following results: • LUTs: 12850 (19%) • Frequency:93 MHz GRIP, Apr 2018, Version 2018.1 455 www.cobham.com/gaisler GRLIB IP Core 40.8 Registers The core is programmed through registers mapped into APB address space. Table 516.GRECC registers APB address offset Register 0x20 Key 0 Register 0x24 Key 1 Register 0x28 Key 2 Register 2C Key 3 Register 0x30 Key 4 Register 0x34 Key 5 Register 0x38 Key 6 Register 0x3C Key 7 Register 0x40 Point X Input 0 Register 0x044 Point X Input 1 Register 0x048 Point X Input 2 Register 0x04C Point X Input 3 Register 0x050 Point X Input 4 Register 0x054 Point X Input 5 Register 0x58 Point X Input 6 Register 0x5C Point X Input 7 Register 0x60 Point Y Input 0 Register 0x64 Point Y Input 1 Register 0x68 Point Y Input 2 Register 0x6C Point Y Input 3 Register 0x70 Point Y Input 4 Register 0x74 Point Y Input 5 Register 0x78 Point Y Input 6 Register 0x7C Point Y Input 7 Register 0xA0 Point X Output 0 Register 0xA4 Point X Output 1 Register 0xA8 Point X Output 2 Register 0xAC Point X Output 3 Register 0xB0 Point X Output 4 Register 0xB4 Point X Output 5 Register 0xB8 Point X Output 6 Register 0xBC Point X Output 7 Register 0xC0 Point Y Output 0 Register 0xC4 Point Y Output 1 Register 0xC8 Point Y Output 2 Register 0xCC Point Y Output 3 Register 0xD0 Point Y Output 4 Register 0xD4 Point Y Output 5 Register 0xD8 Point Y Output 6 Register 0xDC Point Y Output 7 Register 0xFC Status Register GRIP, Apr 2018, Version 2018.1 456 www.cobham.com/gaisler GRLIB IP Core 40.8.1 Key 0 to 7 Registers Table 517.0x20 - KEY0 - Key 0 Register (least significant) 31 0 KEY(31 downto 0) 0 w Table 518.0x24 - KEY1 - Key 1 Register 31 0 KEY(63 downto32) 0 w Table 519.0x28 - KEY2 - Key 2 Register 31 0 KEY(95 downto 64) 0 w Table 520.0x2C - KEY3 - Key 3 Register 31 0 KEY(127 downto 96) 0 w Table 521.0x30 - KEY4 - Key 4 Register 31 0 KEY(159 downto 128) 0 w Table 522.0x34 - KEY5 - Key 5 Register 31 0 KEY(191 downto 160) 0 w Table 523.0x38 - KEY6 - Key 6 Register 31 0 KEY(223 downto 192) 0 w GRIP, Apr 2018, Version 2018.1 457 www.cobham.com/gaisler GRLIB IP Core Table 524.0x3C - KEY7 - Key 7 Register (most significant) 31 9 8 0 RESERVED KEY(232 downto 224) 0 0 - w GRIP, Apr 2018, Version 2018.1 458 www.cobham.com/gaisler GRLIB IP Core 40.8.2 Point X Input 0 to 7 Registers Table 525.0x40 - PXI0 - Point X Input 0 Register (least significant) 31 0 X(31 downto 0) 0 w Table 526.0x44 - PXI1 - Point X Input 1 Register 31 0 X(63 downto32) 0 w Table 527.0x48 - PXI2 - Point X Input 2 Register 31 0 X(95 downto 64) 0 w Table 528.0x4C - PXI3 - Point X Input 3 Register 31 0 X(127 downto 96) 0 w Table 529.0x50 - PXI4 - Point X Input 4 Register 31 0 X(159 downto 128) 0 w Table 530.0x54 - PXI5 - Point X Input 5 Register 31 0 X(191 downto 160) 0 w Table 531.0x58 - PXI6 - Point X Input 6 Register 31 0 X(223 downto 192) 0 w GRIP, Apr 2018, Version 2018.1 459 www.cobham.com/gaisler GRLIB IP Core Table 532.0x5C - PXI7 - Point X Input 7 Register (most significant) 31 9 8 0 RESERVED X(232 downto 224) 0 0 - w GRIP, Apr 2018, Version 2018.1 460 www.cobham.com/gaisler GRLIB IP Core 40.8.3 Point Y Input 0 to 7 Registers (W) Table 533.0x60 - PYI0 - Point Y Input 0 Register (least significant) 31 0 Y(31 downto 0) Table 534.0x64 - PYI1 - Point Y Input 1 Register 31 0 Y(63 downto32) Table 535.0x68 - PYI2 - Point Y Input 2 Register 31 0 Y(95 downto 64) Table 536.0x6C - PYI3 - Point Y Input 3 Register 31 0 Y(127 downto 96) Table 537.0x70 - PYI4 - Point Y Input 4 Register 31 0 Y(159 downto 128) Table 538.0x74 - PYI5 - Point Y Input 5 Register 31 0 Y(191 downto 160) Table 539.0x78 - PYI6 - Point Y Input 6 Register 31 0 Y(223 downto 192) GRIP, Apr 2018, Version 2018.1 461 www.cobham.com/gaisler GRLIB IP Core Table 540.0x7C - PYI7 - Point Y Input 7 Register (most significant) 31 9 RESERVED 8 0 Y(232 downto 224) 0 w The encryption or decryption operation is started when the Point Y Input 7 Register is written. GRIP, Apr 2018, Version 2018.1 462 www.cobham.com/gaisler GRLIB IP Core 40.8.4 Point X Output 0 to 7 Registers (R) Table 541.0xA0 - PXO0 - Point X Output 0 Register (least significant) 31 0 X(31 downto 0) NR r Table 542.0xA4 - PXO1 - Point X Output 1 Register 31 0 X(63 downto32) NR r Table 543.0xA8 - PXO2 - Point X Output 2 Register 31 0 X(95 downto 64) NR r Table 544.0xAC - PXO3 - Point X Output 3 Register 31 0 X(127 downto 96) NR r Table 545.0xB0 - PXO4 - Point X Output 4 Register 31 0 X(159 downto 128) NR r Table 546.0xB4 - PXO5 - Point X Output 5 Register 31 0 X(191 downto 160) NR r Table 547.0xB8 - PXO6 - Point X Output 6 Register 31 0 X(223 downto 192) NR r GRIP, Apr 2018, Version 2018.1 463 www.cobham.com/gaisler GRLIB IP Core Table 548.0xBC - PXO7 - Point X Output 7 Register (most significant) 31 9 8 0 RESERVED X(232 downto 224) - NR r r GRIP, Apr 2018, Version 2018.1 464 www.cobham.com/gaisler GRLIB IP Core 40.8.5 Point Y Output 0 to 7 Registers (R) Table 549.0xC0 - PYO0 - Point Y Output 0 Register (least significant) 31 0 Y(31 downto 0) NR r Table 550.0xC4 - PYO1 - Point Y Output 1 Register 31 0 Y(63 downto32) NR r Table 551.0xC8 - PYO2 - Point Y Output 2 Register 31 0 Y(95 downto 64) NR r Table 552.0xCC - PYO3 - Point Y Output 3 Register 31 0 Y(127 downto 96) NR r Table 553.0xD0 - PYO4 - Point Y Output 4 Register 31 0 Y(159 downto 128) NR r Table 554.0xD4 - PYO5 - Point Y Output 5 Register 31 0 Y(191 downto 160) NR r Table 555.0xD8 - PYO6 - Point Y Output 6 Register 31 0 Y(223 downto 192) NR r GRIP, Apr 2018, Version 2018.1 465 www.cobham.com/gaisler GRLIB IP Core Table 556.0xDC - PYO7 - Point Y Output 7 Register (most significant) 31 9 8 0 RESERVED Y(232 downto 224) - NR r r 40.8.6 Status Register (R) Table 557.0xFC - STAT - Status Register 31 0 . FS M 0 1 r r 31-1: 0: 40.9 1 FSM Unused 0 when ongoing, 1 when idle or ready Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x074. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 40.10 Configuration options Table 558 shows the configuration options of the core (VHDL generics). Table 558.Configuration options Generic Function Allowed range Default pindex APB slave index 0 - NAPBSLV-1 0 paddr Addr field of the APB BAR 0 - 16#FFF# 0 pmask Mask field of the APB BAR 0 - 16#FFF# 16#FFC# pirq Interrupt line used by the GRECC 0 - NAHBIRQ-1 0 40.11 Signal descriptions Table 559 shows the interface signals of the core (VHDL ports). Table 559.Signal descriptions Signal name Field Type Function Active RSTN N/A Input Reset Low CLK N/A Input Clock - APBI * Input APB slave input signals - APBO * Output APB slave output signals - DEBUG[10:0] N/A Output Debug information - * see GRLIB IP Library User’s Manual Note that the ECC core can also be used without the GRLIB plug&play information. The AMBA APB signals are then provided as IEEE Std_Logic_1164 compatible scalars and vectors. GRIP, Apr 2018, Version 2018.1 466 www.cobham.com/gaisler GRLIB IP Core 40.12 Library dependencies Table 560 shows libraries used when instantiating the core (VHDL libraries). Table 560.Library dependencies Library Package Imported unit(s) Description GRLIB AMBA Signals AMBA signal definitions GAISLER CRYPTO Component GRECC component declarations 40.13 Instantiation This example shows how the core can be instantiated. library use ieee; ieee.std_logic_1164.all; library use grlib; grlib.amba.all; library gaisler; use gaisler.crypto.all; ... ... signal debug: std_logic_vector(10 downto 0); .. .. grecc0: grecc generic map ( pindex => pindex, paddr => paddr, pmask => pmask, pirq => pirq) port map ( rstn => rstn, clk => clk, apbi => apbi, apbo => apbo(pindex), debug => debug); GRIP, Apr 2018, Version 2018.1 467 www.cobham.com/gaisler GRLIB IP Core 41 GRETH - Ethernet Media Access Controller (MAC) with EDCL support 41.1 Overview Cobham Gaisler’s Ethernet Media Access Controller (GRETH) provides an interface between an AMBA-AHB bus and an Ethernet network. It supports 10/100 Mbit speed in both full- and halfduplex. The AMBA interface consists of an APB interface for configuration and control and an AHB master interface which handles the dataflow. The dataflow is handled through DMA channels. There is one DMA engine for the transmitter and one for the receiver. Both share the same AHB master interface. The ethernet interface supports both the MII and RMII interfaces which should be connected to an external PHY. The GRETH also provides access to the MII Management interface which is used to configure the PHY. Optional hardware support for the Ethernet Debug Communication Link (EDCL) protocol is also provided. This is an UDP/IP based protocol used for remote debugging. APB AHB Ethernet MAC MDIO_OE MDIO_O Registers MDIO MDIO_I MDC Transmitter DMA Engine AHB Master Interface FIFO Transmitter EDCL Transmitter EDCL Receiver Receiver DMA Engine Receiver FIFO TX_EN TX_ER TXD(3:0) TX_CLK RX_CRS RX_COL RX_DV RX_ER RXD(3:0) RX_CLK Figure 123. Block diagram of the internal structure of the GRETH. 41.2 Operation 41.2.1 System overview The GRETH consists of 3 functional units: The DMA channels, MDIO interface and the optional Ethernet Debug Communication Link (EDCL). The main functionality consists of the DMA channels which are used to transfer data between an AHB bus and an Ethernet network. There is one transmitter DMA channel and one Receiver DMA channel. The operation of the DMA channels is controlled through registers accessible through the APB interface. The MDIO interface is used for accessing configuration and status registers in one or more PHYs connected to the MAC. The operation of this interface is also controlled through the APB interface. The optional EDCL provides read and write access to an AHB bus through Ethernet. It uses the UDP, IP, ARP protocols together with a custom application layer protocol to accomplish this. The EDCL contains no user accessible registers and always runs in parallel with the DMA channels. GRIP, Apr 2018, Version 2018.1 468 www.cobham.com/gaisler GRLIB IP Core The Media Independent Interface (MII) is used for communicating with the PHY. There is an Ethernet transmitter which sends all data from the AHB domain on the Ethernet using the MII interface. Correspondingly, there is an Ethernet receiver which stores all data from the Ethernet on the AHB bus. Both of these interfaces use FIFOs when transferring the data streams. The GRETH also supports the RMII which uses a subset of the MII signals. The EDCL and the DMA channels share the Ethernet receiver and transmitter. 41.2.2 Protocol support The GRETH is implemented according to IEEE standard 802.3-2002 and IEEE standard 802.3Q2003. There is no support for the optional control sublayer. This means that packets with type 0x8808 (the only currently defined ctrl packets) are discarded. The support for 802.3Q is optional and need to be enabled via generics. 41.2.3 Clocking GRETH has three clock domains: The AHB clock, Ethernet receiver clock and the Ethernet transmitter clock. The ethernet transmitter and receiver clocks are generated by the external ethernet PHY, and are inputs to the core through the MII interface. The three clock domains are unrelated to each other and all signals crossing the clock regions are fully synchronized inside the core. Both full-duplex and half-duplex operating modes are supported and both can be run in either 10 or 100 Mbit. The minimum AHB clock for 10 Mbit operation is 2.5 MHz, while 18 MHz is needed for 100 Mbit. Using a lower AHB clock than specified will lead to excessive packet loss. 41.2.4 RAM debug support Support for debug accesses the core’s internal RAM blocks can be optionally enabled using the ramdebug VHDL generic. Setting it to 1 enables accesses to the transmitter and receiver RAM buffers and setting it to 2 enables accesses to the EDCL buffer in addition to the previous two buffers. The transmitter RAM buffer is accessed starting from APB address offset 0x10000 which corresponds to location 0 in the RAM. There are 512 32-bit wide locations in the RAM which results in the last address being 0x107FC corresponding to RAM location 511 (byte addressing used on the APB bus). Correspondingly the receiver RAM buffer is accessed starting from APB address offset 0x20000. The addresses, width and depth is the same. The EDCL buffers are accessed starting from address 0x30000. The number of locations depend on the configuration and can be from 256 to 16384. Each location is 32-bits wide so the maximum address is 0x3FC and 0xFFFC correspondingly. Before any debug accesses can be made the ramdebugen bit in the control register has to be set. During this time the debug interface controls the RAM blocks and normal operations is stopped. EDCL packets are not received. The MAC transmitter and receiver could still operate if enabled but the RAM buffers would be corrupt if debug accces are made simultaneously. Thus they MUST be disabled before the RAM debug mode is enabled. 41.2.5 Multibus version There is a version of the core which has an additional master interface that can be used for the EDCL. Otherwise this version is identical to the basic version. The additional master interface is enabled with the edclsepahb VHDL generic. Then the ethi.edclsepahb signal control whether EDCL accesses are done on the standard master interface or the additional interface. Setting the signal to ‘0’ makes the EDCL use the standard master interface while ‘1’ selects the additional master. This signal is only sampled at reset and changes to this signal have no effect until the next reset. GRIP, Apr 2018, Version 2018.1 469 www.cobham.com/gaisler GRLIB IP Core 41.2.6 Endianness The core is designed for big-endian systems. 41.3 Tx DMA interface The transmitter DMA interface is used for transmitting data on an Ethernet network. The transmission is done using descriptors located in memory. 41.3.1 Setting up a descriptor. A single descriptor is shown in table 561 and 562. The number of bytes to be sent should be set in the length field and the address field should point to the data. The address must be word-aligned. If the interrupt enable (IE) bit is set, an interrupt will be generated when the packet has been sent (this requires that the transmitter interrupt bit in the control register is also set). The interrupt will be generated regardless of whether the packet was transmitted successfully or not. The Wrap (WR) bit is also a control bit that should be set before transmission and it will be explained later in this section. Table 561.GRETH transmit descriptor word 0 (address offset 0x0) 31 16 15 14 13 12 11 10 RESERVED AL UE IE WR EN 0 LENGTH 31: 16 RESERVED 15 Attempt Limit Error (AL) - The packet was not transmitted because the maximum number of attempts was reached. 14 Underrun Error (UE) - The packet was incorrectly transmitted due to a FIFO underrun error. 13 Interrupt Enable (IE) - Enable Interrupts. An interrupt will be generated when the packet from this descriptor has been sent provided that the transmitter interrupt enable bit in the control register is set. The interrupt is generated regardless if the packet was transmitted successfully or if it terminated with an error. 12 Wrap (WR) - Set to one to make the descriptor pointer wrap to zero after this descriptor has been used. If this bit is not set the pointer will increment by 8. The pointer automatically wraps to zero when the 1 kB boundary of the descriptor table is reached. 11 Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor fields. 10: 0 LENGTH - The number of bytes to be transmitted. Table 562.GRETH transmit descriptor word 1 (address offset 0x4) 31 2 ADDRESS 1 0 RES 31: 2 Address (ADDRESS) - Pointer to the buffer area from where the packet data will be loaded. 1: 0 RESERVED To enable a descriptor the enable (EN) bit should be set and after this is done, the descriptor should not be touched until the enable bit has been cleared by the GRETH. 41.3.2 Starting transmissions Enabling a descriptor is not enough to start a transmission. A pointer to the memory area holding the descriptors must first be set in the GRETH. This is done in the transmitter descriptor pointer register. The address must be aligned to a 1 kB boundary. Bits 31 to 10 hold the base address of descriptor area while bits 9 to 3 form a pointer to an individual descriptor.The first descriptor should be located at the base address and when it has been used by the GRETH the pointer field is incremented by 8 to point at the next descriptor. The pointer will automatically wrap back to zero when the next 1 kB boundary has GRIP, Apr 2018, Version 2018.1 470 www.cobham.com/gaisler GRLIB IP Core been reached (the descriptor at address offset 0x3F8 has been used). The WR bit in the descriptors can be set to make the pointer wrap back to zero before the 1 kB boundary. The pointer field has also been made writable for maximum flexibility but care should be taken when writing to the descriptor pointer register. It should never be touched when a transmission is active. The final step to activate the transmission is to set the transmit enable bit in the control register. This tells the GRETH that there are more active descriptors in the descriptor table. This bit should always be set when new descriptors are enabled, even if transmissions are already active. The descriptors must always be enabled before the transmit enable bit is set. 41.3.3 Descriptor handling after transmission When a transmission of a packet has finished, status is written to the first word in the corresponding descriptor. The Underrun Error bit is set if the FIFO became empty before the packet was completely transmitted while the Attempt Limit Error bit is set if more collisions occurred than allowed. The packet was successfully transmitted only if both of these bits are zero. The other bits in the first descriptor word are set to zero after transmission while the second word is left untouched. The enable bit should be used as the indicator when a descriptor can be used again, which is when it has been cleared by the GRETH. There are three bits in the GRETH status register that hold transmission status. The Transmitter Error (TE) bit is set each time an transmission ended with an error (when at least one of the two status bits in the transmit descriptor has been set). The Transmitter Interrupt (TI) is set each time a transmission ended successfully. The transmitter AHB error (TA) bit is set when an AHB error was encountered either when reading a descriptor or when reading packet data. Any active transmissions were aborted and the transmitter was disabled. The transmitter can be activated again by setting the transmit enable register. 41.3.4 Setting up the data for transmission The data to be transmitted should be placed beginning at the address pointed by the descriptor address field. The GRETH does not add the Ethernet address and type fields so they must also be stored in the data buffer. The 4 B Ethernet CRC is automatically appended at the end of each packet. Each descriptor will be sent as a single Ethernet packet. If the size field in a descriptor is greater than defined by maxsize generic + header size bytes, the packet will not be sent. 41.4 Rx DMA interface The receiver DMA interface is used for receiving data from an Ethernet network. The reception is done using descriptors located in memory. 41.4.1 Setting up descriptors A single descriptor is shown in table 563 and 564. The address field should point to a word-aligned buffer where the received data should be stored. The GRETH will never store more than defined by the maxisize generic + header size bytes to the buffer. If the interrupt enable (IE) bit is set, an interrupt will be generated when a packet has been received to this buffer (this requires that the receiver interrupt bit in the control register is also set). The interrupt will be generated regardless of whether the packet was received successfully or not. The Wrap (WR) bit is also a control bit that should be set before the descriptor is enabled and it will be explained later in this section. Table 563.GRETH receive descriptor word 0 (address offset 0x0) 31 27 26 25 RESERVED 31: 27 MC 19 18 17 16 15 14 13 12 11 10 RESERVED LE OE CE FT AE IE WR EN 0 LENGTH RESERVED GRIP, Apr 2018, Version 2018.1 471 www.cobham.com/gaisler GRLIB IP Core Table 563.GRETH receive descriptor word 0 (address offset 0x0) 26 Multicast address (MC) - The destination address of the packet was a multicast address (not broadcast). 25: 19 RESERVED 18 Length error (LE) - The length/type field of the packet did not match the actual number of received bytes. 17 Overrun error (OE) - The frame was incorrectly received due to a FIFO overrun. 16 CRC error (CE) - A CRC error was detected in this frame. 15 Frame too long (FT) - A frame larger than the maximum size was received. The excessive part was truncated. 14 Alignment error (AE) - An odd number of nibbles were received. 13 Interrupt Enable (IE) - Enable Interrupts. An interrupt will be generated when a packet has been received to this descriptor provided that the receiver interrupt enable bit in the control register is set. The interrupt is generated regardless if the packet was received successfully or if it terminated with an error. 12 Wrap (WR) - Set to one to make the descriptor pointer wrap to zero after this descriptor has been used. If this bit is not set the pointer will increment by 8. The pointer automatically wraps to zero when the 1 kB boundary of the descriptor table is reached. 11 Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor fields. 10: 0 LENGTH - The number of bytes received to this descriptor. Table 564.GRETH receive descriptor word 1 (address offset 0x4) 31 2 ADDRESS 1 0 RES 31: 2 Address (ADDRESS) - Pointer to the buffer area from where the packet data will be loaded. 1: 0 RESERVED 41.4.2 Starting reception Enabling a descriptor is not enough to start reception. A pointer to the memory area holding the descriptors must first be set in the GRETH. This is done in the receiver descriptor pointer register. The address must be aligned to a 1 kB boundary. Bits 31 to 10 hold the base address of descriptor area while bits 9 to 3 form a pointer to an individual descriptor. The first descriptor should be located at the base address and when it has been used by the GRETH the pointer field is incremented by 8 to point at the next descriptor. The pointer will automatically wrap back to zero when the next 1 kB boundary has been reached (the descriptor at address offset 0x3F8 has been used). The WR bit in the descriptors can be set to make the pointer wrap back to zero before the 1 kB boundary. The pointer field has also been made writable for maximum flexibility but care should be taken when writing to the descriptor pointer register. It should never be touched when reception is active. The final step to activate reception is to set the receiver enable bit in the control register. This will make the GRETH read the first descriptor and wait for an incoming packet. 41.4.3 Descriptor handling after reception The GRETH indicates a completed reception by clearing the descriptor enable bit. The other control bits (WR, IE) are also cleared. The number of received bytes is shown in the length field. The parts of the Ethernet frame stored are the destination address, source address, type and data fields. Bits 17-14 in the first descriptor word are status bits indicating different receive errors. All four bits are zero after a reception without errors. The status bits are described in table 563. Packets arriving that are smaller than the minimum Ethernet size of 64 B are not considered as a reception and are discarded. The current receive descriptor will be left untouched an used for the first packet arriving with an accepted size. The TS bit in the status register is set each time this event occurs. GRIP, Apr 2018, Version 2018.1 472 www.cobham.com/gaisler GRLIB IP Core If a packet is received with an address not accepted by the MAC, the IA status register bit will be set. Packets larger than maximum size cause the FT bit in the receive descriptor to be set. The length field is not guaranteed to hold the correct value of received bytes. The counting stops after the word containing the last byte up to the maximum size limit has been written to memory. The address word of the descriptor is never touched by the GRETH. 41.4.4 Reception with AHB errors If an AHB error occurs during a descriptor read or data store, the Receiver AHB Error (RA) bit in the status register will be set and the receiver is disabled. The current reception is aborted. The receiver can be enabled again by setting the Receive Enable bit in the control register. 41.4.5 Accepted MAC addresses In the default configuration the core receives packets with either the unicast address set in the MAC address register or the broadcast address. Multicast support can also be enabled and in that case a hash function is used to filter received multicast packets. A 64-bit register, which is accessible through the APB interface, determines which addresses should be received. Each address is mapped to one of the 64 bits using the hash function and if the bit is set to one the packet will be received. The address is mapped to the table by taking the 6 least significant bits of the 32-bit Ethernet crc calculated over the destination address of the MAC frame. A bit in the receive descriptor is set if a packet with a multicast address has been received to it. 41.5 MDIO Interface The MDIO interface provides access to PHY configuration and status registers through a two-wire interface which is included in the MII interface. The GRETH provided full support for the MDIO interface. If it is not needed in a design it can be removed with a VHDL generic. The MDIO interface can be used to access from 1 to 32 PHY containing 1 to 32 16-bit registers. A read transfer i set up by writing the PHY and register addresses to the MDIO Control register and setting the read bit. This caused the Busy bit to be set and the operation is finished when the Busy bit is cleared. If the operation was successful the Linkfail bit is zero and the data field contains the read data. An unsuccessful operation is indicated by the Linkfail bit being set. The data field is undefined in this case. A write operation is started by writing the 16-bit data, PHY address and register address to the MDIO Control register and setting the write bit. The operation is finished when the busy bit is cleared and it was successful if the Linkfail bit is zero. 41.5.1 PHY interrupts The core also supports status change interrupts from the PHY. A level sensitive interrupt signal can be connected on the mdint input. The mdint_pol vhdl generic can be used to select the polarity. The PHY status change bit in the status register is set each time an event is detected in this signal. If the PHY status interrupt enable bit is set at the time of the event the core will also generate an interrupt on the AHB bus. 41.6 Ethernet Debug Communication Link (EDCL) The EDCL provides access to an on-chip AHB bus through Ethernet. It uses the UDP, IP and ARP protocols together with a custom application layer protocol. The application layer protocol uses an ARQ algorithm to provide reliable AHB instruction transfers. Through this link, a read or write transfer can be generated to any address on the AHB bus. The EDCL is optional and must be enabled with a generic. GRIP, Apr 2018, Version 2018.1 473 www.cobham.com/gaisler GRLIB IP Core 41.6.1 Operation The EDCL receives packets in parallel with the MAC receive DMA channel. It uses a separate MAC address which is used for distinguishing EDCL packets from packets destined to the MAC DMA channel. The EDCL also has an IP address which is set through generics. Since ARP packets use the Ethernet broadcast address, the IP-address must be used in this case to distinguish between EDCL ARP packets and those that should go to the DMA-channel. Packets that are determined to be EDCL packets are not processed by the receive DMA channel. When the packets are checked to be correct, the AHB operation is performed. The operation is performed with the same AHB master interface that the DMA-engines use. The replies are automatically sent by the EDCL transmitter when the operation is finished. It shares the Ethernet transmitter with the transmitter DMA-engine but has higher priority. 41.6.2 EDCL protocols The EDCL accepts Ethernet frames containing IP or ARP data. ARP is handled according to the protocol specification with no exceptions. IP packets carry the actual AHB commands. The EDCL expects an Ethernet frame containing IP, UDP and the EDCL specific application layer parts. Table 565 shows the IP packet required by the EDCL. The contents of the different protocol headers can be found in TCP/IP literature. Table 565.The IP packet expected by the EDCL. Ethernet IP UDP 2B 4B 4B Data 0 - 242 Ethernet Header Header Header Offset Control word Address 4B Words CRC The following is required for successful communication with the EDCL: A correct destination MAC address as set by the generics, an Ethernet type field containing 0x0806 (ARP) or 0x0800 (IP). The IP-address is then compared with the value determined by the generics for a match. The IP-header checksum and identification fields are not checked. There are a few restrictions on the IP-header fields. The version must be four and the header size must be 5 B (no options). The protocol field must always be 0x11 indicating a UDP packet. The length and checksum are the only IP fields changed for the reply. The EDCL only provides one service at the moment and it is therefore not required to check the UDP port number. The reply will have the original source port number in both the source and destination fields. UDP checksum are not used and the checksum field is set to zero in the replies. The UDP data field contains the EDCL application protocol fields. Table 566 shows the application protocol fields (data field excluded) in packets received by the EDCL. The 16-bit offset is used to align the rest of the application layer data to word boundaries in memory and can thus be set to any value. The R/W field determines whether a read (0) or a write(1) should be performed. The length Table 566.The EDCL application layer fields in received frames. 16-bit Offset 14-bit Sequence number 1-bit R/W 10-bit Length 7-bit Unused field contains the number of bytes to be read or written. If R/W is one the data field shown in table 565 contains the data to be written. If R/W is zero the data field is empty in the received packets. Table 567 shows the application layer fields of the replies from the EDCL. The length field is always zero for replies to write requests. For read requests it contains the number of bytes of data contained in the data field. Table 567.The EDCL application layer fields in transmitted frames. 16-bit Offset 14-bit sequence number GRIP, Apr 2018, Version 2018.1 1-bit ACK/NAK 474 10-bit Length 7-bit Unused www.cobham.com/gaisler GRLIB IP Core The EDCL implements a Go-Back-N algorithm providing reliable transfers. The 14-bit sequence number in received packets are checked against an internal counter for a match. If they do not match, no operation is performed and the ACK/NAK field is set to 1 in the reply frame. The reply frame contains the internal counter value in the sequence number field. If the sequence number matches, the operation is performed, the internal counter value is stored in the sequence number field, the ACK/ NAK field is set to 0 in the reply and the internal counter is incremented, . The length field is always set to 0 for ACK/NAK=1 frames. The unused field is not checked and is copied to the reply. It can thus be set to hold for example some extra identifier bits if needed. 41.6.3 EDCL IP and Ethernet address settings The default value of the EDCL IP and MAC addresses are set by ipaddrh, ipaddrl, macaddrh and macaddrl generics. The IP address can later be changed by software, but the MAC address is fixed. To allow several EDCL enabled GRETH controllers on the same sub-net, the 4 LSB bits of the IP and MAC address can optionally be set by an input signal. This is enabled by setting the edcl generic = 2, and driving the 4-bit LSB value on ethi.edcladdr. 41.6.4 EDCL buffer size The EDCL has a dedicated internal buffer memory which stores the received packets during processing. The size of this buffer is configurable with a VHDL generic to be able to obtain a suitable compromise between throughput and resource utilization in the hardware. Table 568 lists the different buffer configurations. For each size the table shows how many concurrent packets the EDCL can handle, the maximum size of each packet including headers and the maximum size of the data payload. Sending more packets before receiving a reply than specified for the selected buffer size will lead to dropped packets. The behavior is unspecified if sending larger packets than the maximum allowed. Table 568.EDCL buffer sizes 41.7 Total buffer size (kB) Number of packet buffers Packet buffer size (B) Maximum data payload (B) 1 4 256 200 2 4 512 456 4 8 512 456 8 8 1024 968 16 16 1024 968 32 32 1024 968 64 64 1024 968 Media Independent Interfaces There are several interfaces defined between the MAC sublayer and the Physical layer. The GRETH supports two of them: The Media Independent Interface (MII) and the Reduced Media Independent Interface (RMII). The MII was defined in the 802.3 standard and is most commonly supported. The ethernet interface have been implemented according to this specification. It uses 16 signals. To support lower speed where the operation and clock frequency of the core and phy remains unchanged i.e. running at 10Mb/s when the IP is configured for 100Mb/s speed enable signals should be created to mimic the desired bit rate. When operating at 10Mb/s, every byte of the MAC frame is repeated 10 clock periods to achieve the correct bit rate. The GRETH_GBIT core does not take care of this operation and enable signals with toggling frequency of the correct bit rate needs to be created. GRIP, Apr 2018, Version 2018.1 475 www.cobham.com/gaisler GRLIB IP Core The RMII was developed to meet the need for an interface allowing Ethernet controllers with smaller pin counts. It uses 6 (7) signals which are a subset of the MII signals. Table 569 shows the mapping between the RMII signals and the GRLIB MII interface. Table 569.Signal mappings between RMII and the GRLIB MII interface. 41.8 RMII MII txd[1:0] txd[1:0] tx_en tx_en crs_dv rx_crs rxd[1:0] rxd[1:0] ref_clk rmii_clk rx_er not used Registers The core is programmed through registers mapped into APB address space. Table 570.GRETH registers APB address offset Register 0x0 Control register 0x4 Status/Interrupt-source register 0x8 MAC Address MSB 0xC MAC Address LSB 0x10 MDIO Control/Status 0x14 Transmit descriptor pointer 0x18 Receiver descriptor pointer 0x1C EDCL IP 0x20 Hash table msb 0x24 Hash table lsb 0x28 EDCL MAC address MSB 0x2C EDCL MAC address LSB 0x10000 - 0x107FC Transmit RAM buffer debug access 0x20000 - 0x207FC Receiver RAM buffer debug access 0x30000 - 0x3FFFC EDCL buffer debug access GRIP, Apr 2018, Version 2018.1 476 www.cobham.com/gaisler GRLIB IP Core 41.8.1 Control Register Table 571.0x00 - CTRL - GRETH control register 31 30 28 27 26 25 24 MA MC 15 14 13 12 11 10 EA BS RESERVED * * * * * 0 r r r r r r ED RD DD ME PI * * 0 0 9 8 RES 7 6 5 4 3 SP RS PM FD RI 0 0 0 0 2 1 0 TI RE TE 0 0 1 rw rw rw rw rw r rw wc rw rw rw rw rw rw 0 0 0 31 EDCL available (EA) - Set to one if the EDCL is available. 30: 28 EDCL buffer size (BS) - Shows the amount of memory used for EDCL buffers. 0 = 1 kB, 1 = 2 kB, ...., 6 = 64 kB. 27 RESERVED 26 MDIO interrupts available (MA) - Set to one when the core supports mdio interrupts. Read only. 25 Multicast available (MC) - Set to one when the core supports multicast address reception. Read only. 24: 15 RESERVED 14 EDCL Disable (ED) - Set to one to disable the EDCL and zero to enable it. Reset value taken from the ethi.edcldisable signal. Only available if the EDCL hardware is present in the core. 13 RAM debug enable (RD) - Set to one to enable the RAM debug mode. Reset value: ‘0’. Only available if the VHDL generic ramdebug is nonzero. 12 Disable duplex detection (DD) - Disable the EDCL speed/duplex detection FSM. If the FSM cannot complete the detection the MDIO interface will be locked in busy mode. If software needs to access the MDIO the FSM can be disabled here and as soon as the MDIO busy bit is 0 the interface is available. Note that the FSM cannot be reenabled again. 11 Multicast enable (ME) - Enable reception of multicast addresses. Reset value: ‘0’. 10 PHY status change interrupt enable (PI) - Enables interrupts for detected PHY status changes. 9: 8 RESERVED 7 Speed (SP) - Sets the current speed mode. 0 = 10 Mbit, 1 = 100 Mbit. Only used in RMII mode (rmii = 1). A default value is automatically read from the PHY after reset. Reset value: ‘1’. 6 Reset (RS) - A one written to this bit resets the GRETH core. Self clearing. No other accesses should be done .to the slave interface other than polling this bit until it is cleared. 5 Promiscuous mode (PM) - If set, the GRETH operates in promiscuous mode which means it will receive all packets regardless of the destination address. Reset value: ‘0’. 4 Full duplex (FD) - If set, the GRETH operates in full-duplex mode otherwise it operates in halfduplex. Reset value: ‘0’. 3 Receiver interrupt (RI) - Enable Receiver Interrupts. An interrupt will be generated each time a packet is received when this bit is set. The interrupt is generated regardless if the packet was received successfully or if it terminated with an error. Reset value: ‘0’. 2 Transmitter interrupt (TI) - Enable Transmitter Interrupts. An interrupt will be generated each time a packet is transmitted when this bit is set. The interrupt is generated regardless if the packet was transmitted successfully or if it terminated with an error. Reset value: ‘0’. 1 Receive enable (RE) - Should be written with a one each time new descriptors are enabled. As long as this bit is one the GRETH will read new descriptors and as soon as it encounters a disabled descriptor it will stop until RE is set again. This bit should be written with a one after the new descriptors have been enabled. Reset value: ‘0’. 0 Transmit enable (TE) - Should be written with a one each time new descriptors are enabled. As long as this bit is one the GRETH will read new descriptors and as soon as it encounters a disabled descriptor it will stop until TE is set again. This bit should be written with a one after the new descriptors have been enabled. Reset value: ‘0’. 41.8.2 Status Register Table 572.0x04 - STAT - GRETH status register 31 9 RESERVED 8 7 6 5 4 3 PS IA TS TA RA TI 0 0 0 2 1 0 RI TE RE NR NR NR NR NR NR wc wc wc wc wc wc wc wc wc GRIP, Apr 2018, Version 2018.1 477 www.cobham.com/gaisler GRLIB IP Core Table 572.0x04 - STAT - GRETH status register 8 PHY status changes (PS) - Set each time a PHY status change is detected. 7 Invalid address (IA) - A packet with an address not accepted by the MAC was received. Cleared when written with a one. Reset value: ‘0’. 6 Too small (TS) - A packet smaller than the minimum size was received. Cleared when written with a one. Reset value: ‘0’. 5 Transmitter AHB error (TA) - An AHB error was encountered in transmitter DMA engine. Cleared when written with a one. Not Reset. 4 Receiver AHB error (RA) - An AHB error was encountered in receiver DMA engine. Cleared when written with a one. Not Reset. 3 Transmitter interrupt (TI) - A packet was transmitted without errors. Cleared when written with a one. Not Reset. 2 Receiver interrupt (RI) - A packet was received without errors. Cleared when written with a one. Not Reset. 1 Transmitter error (TE) - A packet was transmitted which terminated with an error. Cleared when written with a one. Not Reset. 0 Receiver error (RE) - A packet has been received which terminated with an error. Cleared when written with a one. Not Reset. GRIP, Apr 2018, Version 2018.1 478 www.cobham.com/gaisler GRLIB IP Core 41.8.3 MAC Address MSB Table 573.0x08 - MACMSB - GRETH MAC address MSB. 31 16 15 0 RESERVED Bit 47 downto 32 of the MAC address NR rw 31: 16 RESERVED 15: 0 The two most significant bytes of the MAC Address. Not Reset. 41.8.4 MAC Address LSB Table 574.0x0C - MACLSB - GRETH MAC address LSB. 31 0 Bit 31 downto 0 of the MAC address 31: 0 The four least significant bytes of the MAC Address. Not Reset. 41.8.5 MDIO ctrl/status Register Table 575.0x10 - MDIO - GRETH MDIO ctrl/status register. 31 16 15 DATA 11 10 PHYADDR 6 REGADDR 5 4 RES 3 2 1 0 BU LF RD WR 0 * 0 0 1 0 rw rw rw r r rw rw 0 31: 16 Data (DATA) - Contains data read during a read operation and data that is transmitted is taken from this field. Reset value: 0x0000. 15: 11 PHY address (PHYADDR) - This field contains the address of the PHY that should be accessed during a write or read operation. Reset value: “00000”. 10: 6 Register address (REGADDR) - This field contains the address of the register that should be accessed during a write or read operation. Reset value: “00000”. 5:4 RESERVED 3 Busy (BU) - When an operation is performed this bit is set to one. As soon as the operation is finished and the management link is idle this bit is cleared. Reset value: ‘0’. 2 Linkfail (LF) - When an operation completes (BUSY = 0) this bit is set if a functional management link was not detected. Reset value: ‘1’. 1 Read (RD) - Start a read operation on the management interface. Data is stored in the data field. Reset value: ‘0’. 0 Write (WR) - Start a write operation on the management interface. Data is taken from the Data field. Reset value: ‘0’. GRIP, Apr 2018, Version 2018.1 479 www.cobham.com/gaisler GRLIB IP Core 41.8.6 Transmitter Descriptor Table Base Address Register Table 576.0x14 - TXBASE - GRETH transmitter descriptor table base address register. 31 10 9 BASEADDR 3 2 0 DESCPNT RES NR 0 0 rw rw r 31: 10 Transmitter descriptor table base address (BASEADDR) - Base address to the transmitter descriptor table.Not Reset. 9: 3 Descriptor pointer (DESCPNT) - Pointer to individual descriptors. Automatically incremented by the Ethernet MAC. 2: 0 RESERVED 41.8.7 Receiver Descriptor Table Base Address Register Table 577.0x18 - RXBASE - GRETH receiver descriptor table base address register. 31 10 BASEADDR 9 3 2 0 DESCPNT RES NR 0 0 rw rw r 31: 10 Receiver descriptor table base address (BASEADDR) - Base address to the receiver descriptor table.Not Reset. 9: 3 Descriptor pointer (DESCPNT) - Pointer to individual descriptors. Automatically incremented by the Ethernet MAC. 2: 0 RESERVED 41.8.8 EDCL IP Register Table 578.0x1C - EDCLIP - GRETH EDCL IP register 31 0 EDCL IP ADDRESS * rw 31: 0 EDCL IP address. Reset value is set with the ipaddrh and ipaddrl generics. 41.8.9 Hash Table Msb Register Table 579.0x20 - HhSB - GRETH Hash table msb register 31 0 Hash table (64:32) NR rw 31: 0 Hash table msb. Bits 64 downto 32 of the hash table. GRIP, Apr 2018, Version 2018.1 480 www.cobham.com/gaisler GRLIB IP Core 41.8.10 Hash Table Lsb Register Table 580.0x24 - HCSB - GRETH Hash table lsb register 31 0 Hash table (64:32) NR rw 31: 0 Hash table lsb. Bits 31downto 0 of the hash table. 41.8.11 EDCL MAC Address MSB Table 581.0x28 - EMACMSB - GRETH EDCL MAC address MSB. 31 16 15 RESERVED 0 Bit 47 downto 32 of the EDCL MAC Address * rw 31: 16 RESERVED 15: 0 The two most significant bytes of the EDCL MAC Address. Hardcoded reset value set with the VHDL generic macaddrh. 41.8.12 EDCL MAC Address LSB Table 582.0x2C - EMACLSB - GRETH EDCL MAC address LSB. 31 0 Bit 31 downto 0 of the EDCL MAC Address * rw 31: 0 41.9 The 4 least significant bytes of the EDCL MAC Address. Hardcoded reset value set with the VHDL generics macaddrh and macaddrl. If the VHDL generic edcl is set to 2 bits 3 downto 0 are set with the edcladdr input signal. Vendor and device identifiers The core has vendor identifier 0x01 (Cobham Gaisler) and device identifier 0x1D. For description of vendor and device identifiers see GRLIB IP Library User’s Manual. 41.10 Implementation 41.10.1 Reset The core does not change reset behaviour depending on settings in the GRLIB configuration package (see GRLIB User’s Manual). The core makes use of synchronous reset and resets a subset of its internal registers. 41.11 Configuration options Table 583 shows the configuration options of the core (VHDL generics). Table 583.Configuration options Generic Function Allowed range Default hindex AHB master index. 0 - NAHBMST-1 0 pindex APB slave index 0 - NAPBSLV-1 0 GRIP, Apr 2018, Version 2018.1 481 www.cobham.com/gaisler GRLIB IP Core Table 583.Configuration options Generic Function Allowed range Default paddr Addr field of the APB bar. 0 - 16#FFF# 0 pmask Mask field of the APB bar. 0 - 16#FFF# 16#FFF# pirq Interrupt line used by the GRETH. 0 - NAHBIRQ-1 0 memtech Memory technology used for the FIFOs. 0 - NTECH inferred ifg_gap Number of ethernet clock cycles used for one interframe gap. Default value as required by the standard. Do not change unless you know what you are doing. 1 - 255 24 attempt_limit Maximum number of transmission attempts for one packet. Default value as required by the standard. 1 - 255 16 backoff_limit Limit on the backoff size of the backoff time. Default value as required by the standard. Sets the number of bits used for the random value. Do not change unless you know what your doing. 1 - 10 10 slot_time Number of ethernet clock cycles used for one slot- time. Default value as required by the ethernet standard. Do not change unless you know what you are doing. 1 - 255 128 mdcscaler Sets the divisor value use to generate the mdio clock (mdc). The mdc frequency will be clk/(2*(mdcscaler+1)). 0 - 255 25 enable_mdio Enable the Management interface, 0-1 0 fifosize Sets the size in 32-bit words of the receiver and transmit- 4 - 32 ter FIFOs. 8 nsync Number of synchronization registers used. 1-2 2 edcl Enable EDCL. 0 = disabled. 1 = enabled. 2 = enabled and 4-bit LSB of IP and ethernet MAC address programmed by ethi.edcladdr, 3=in addition to features for value 2 the reset value for the EDCL disable bit is taken from the ethi.edcldisable signal instead of being hardcoded to 0. 4=in addition to features for value 2 and 3 the an option is given to disable the EDCL via external input signal. 0-4 0 edclbufsz Select the size of the EDCL buffer in kB. 1 - 64 1 macaddrh Sets the upper 24 bits of the EDCL MAC address. Not all addresses are allowed and most NICs and protocol implementations will discard frames with illegal addresses silently. Consult network literature if unsure about the addresses. 0 - 16#FFFFFF# 16#00005E# macaddrl Sets the lower 24 bits of the EDCL MAC address. Not all addresses are allowed and most NICs and protocol implementations will discard frames with illegal addresses silently. Consult network literature if unsure about the addresses. 0 - 16#FFFFFF# 16#000000# ipaddrh Sets the upper 16 bits of the EDCL IP address reset value. 0 - 16#FFFF# 16#C0A8# ipaddrl Sets the lower 16 bits of the EDCL IP address reset value. 0 - 16#FFFF# 16#0035# phyrstadr Sets the reset value of the PHY address field in the MDIO register. 0 - 31 0 rmii Selects the desired PHY interface. 0 = MII, 1 = RMII. 0-1 0 oepol Selects polarity on output enable (ETHO.MDIO_OE). 0-1 0 0 = active low, 1 = active high GRIP, Apr 2018, Version 2018.1 482 www.cobham.com/gaisler GRLIB IP Core Table 583.Configuration options Generic Function Allowed range Default mdint_pol Selects polarity for level sensitive PHY interrupt line. 0 = active low, 1 = active high 0-1 0 enable_mdint Enable mdio interrupts 0-1 0 multicast Enable multicast support 0-1 0 ramdebug Enables debug access to the core’s RAM blocks through the APB interface. 1=enables access to the receiver and transmitter RAM buffers, 2=enables access to the EDCL buffers in addition to the functionality of value 1. Setting this generic to 2 will have no effect if the edcl generic is 0. 0-2 0 ehindex AHB master index for the separate EDCL master interface. Only used if edclsepahb is 1. 0 - NAHBMST-1 0 edclsepahb Enables separate EDCL AHB master interface. A signal 0 - 1 determines if the separate interface or the common interface is used. Only available in the GRETH_GBIT_MB version of the core. 0 mdiohold Set output hold time for MDIO in number of AHB cycles. Should be 10 ns or more. 1 - 30 1 maxsize Set maximum length of the data field of Ethernet 802.3 frame. Values of ‘maxsize’ and below for this field indicate that the ethernet type field is used as the size of the payload of the Ethernet Frame while values of above ‘maxsize’ indicate that the field is used to represent EtherType. For 802.3q support set the length of the payload to 1504 64 - 2047 1500 gmiimode Enable the use of receive and transmit valid signals to enter data to/from the PHY at the correct rate. 0-1 0 41.12 Signal descriptions Table 584 shows the interface signals of the core (VHDL ports). Table 584.Signal descriptions Signal name Field Type Function Active RST N/A Input Reset Low CLK N/A Input Clock - AHBMI * Input AMB master input signals - AHBMO * Output AHB master output signals - APBI * Input APB slave input signals - APBO * Output APB slave output signals - GRIP, Apr 2018, Version 2018.1 483 www.cobham.com/gaisler GRLIB IP Core Table 584.Signal descriptions Signal name ETHI ETHO MTESTI** MTESTO** MTESTCLK** Field Type Function Active gtx_clk Input Ethernet gigabit transmit clock. - rmii_clk Input Ethernet RMII clock. - tx_clk Input Ethernet transmit clock. - tx_dv Input Ethernet transmitter enable - rx_clk Input Ethernet receive clock. - rxd Input Ethernet receive data. - rx_dv Input Ethernet receive data valid. High rx_er Input Ethernet receive error. High rx_col Input Ethernet collision detected. (Asynchronous, sampled with tx_clk) High rx_crs Input Ethernet carrier sense. (Asynchronous, sampled with tx_clk) High rx_en Input Ethernet receiver enable. - mdio_i Input Ethernet management data input - mdint Input Ethernet management interrupt - phyrstaddr Input Reset address for GRETH PHY address field. - edc