HC05JB4GRS, 68HC05JB4, 68HC705JB4, SPECIFICATION (General Release) Data Sheet HC05JB4GRS
User Manual: HC05JB4GRS
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- TABLE OF CONTENTS
- LIST OF FIGURES
- LIST OF TABLES
- SECTION1 GENERAL DESCRIPTION
- SECTION2 MEMORY
- SECTION3 CENTRAL PROCESSING UNIT
- SECTION4 INTERRUPTS
- SECTION5 RESETS
- SECTION6 LOW POWER MODES
- SECTION7 INPUT/OUTPUT PORTS
- SECTION8 MULTI-FUNCTION TIMER
- SECTION9 16-BIT TIMER
- SECTION10 UNIVERSAL SERIAL BUS MODULE
- 10.1 FEATURES
- 10.2 OVERVIEW
- 10.3 CLOCK REQUIREMENTS
- 10.4 HARDWARE DESCRIPTION
- 10.5 I/O REGISTER DESCRIPTION
- 10.5.1 USB Address Register (UADDR)
- 10.5.2 USB Interrupt Register 0 (UIR0)
- 10.5.3 USB Interrupt Register 1 (UIR1)
- 10.5.4 USB Control Register 0 (UCR0)
- 10.5.5 USB Control Register 1 (UCR1)
- 10.5.6 USB Control Register 2 (UCR2)
- 10.5.7 USB Status Register (USR)
- 10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)
- 10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)
- 10.6 USB INTERRUPTS
- SECTION11 ANALOG TO DIGITAL CONVERTER
- SECTION12 INSTRUCTION SET
- 12.1 ADDRESSING MODES
- 12.1.1 Inherent
- 12.1.2 Immediate
- 12.1.3 Direct
- 12.1.4 Extended
- 12.1.5 Indexed, No Offset
- 12.1.6 Indexed, 8Bit Offset
- 12.1.7 Indexed, 16Bit Offset
- 12.1.8 Relative
- 12.1.9 Instruction Types
- 12.1.10 Register/Memory Instructions
- 12.1.11 Read-Modify-Write Instructions
- 12.1.12 Jump/Branch Instructions
- 12.1.13 Bit Manipulation Instructions
- 12.1.14 Control Instructions
- 12.1.15 Instruction Set Summary
- 12.1 ADDRESSING MODES
- SECTION13 ELECTRICAL SPECIFICATIONS
- SECTION14 MECHANICAL SPECIFICATIONS
- APPENDIXA MC68HC705JB4