HDW 500 HDW500
User Manual: HDW500
Open the PDF directly: View PDF 
.
Page Count: 638
| Download | |
| Open PDF In Browser | View PDF |
HD DIGITAL VIDEOCASSETTE RECORDER HDW-500 PARALLEL INTERFACE KIT BKDW-509 HD-525 DOWN CONVERTER BOARD HKDV-501 HD LINE CONVERTER BOARD HKDV-502 HD DIGITAL VIDEO CONTROLLER HKDV-503 HD DUBBING INTERFACE BOARD HKDV-504 HD EDITING PROCESSOR BOARD HKDV-505 MAINTENANCE MANUAL Part 2 Volume 2 1st Edition (Revised 1) ! WARNING This manual is intended for qualified service personnel only. To reduce the risk of electric shock, fire or injury, do not perform any servicing other than that contained in the operating instructions unless you are qualified to do so. Refer all servicing to qualified service personnel. ! WARNUNG Die Anleitung ist nur für qualifiziertes Fachpersonal bestimmt. Alle Wartungsarbeiten dürfen nur von qualifiziertem Fachpersonal ausgeführt werden. Um die Gefahr eines elektrischen Schlages, Feuergefahr und Verletzungen zu vermeiden, sind bei Wartungsarbeiten strikt die Angaben in der Anleitung zu befolgen. Andere als die angegeben Wartungsarbeiten dürfen nur von Personen ausgeführt werden, die eine spezielle Befähigung dazu besitzen. ! AVERTISSEMENT Ce manual est destiné uniquement aux personnes compétentes en charge de l’entretien. Afin de réduire les risques de décharge électrique, d’incendie ou de blessure n’effectuer que les réparations indiquées dans le mode d’emploi à moins d’être qualifié pour en effectuer d’autres. Pour toute réparation faire appel à une personne compétente uniquement. HDW-500 BKDW-509 HKDV-501 HKDV-502 HKDV-503 HKDV-504 HKDV-505 Serial No. 10001 and Higher Serial No. 10001 and Higher Serial No. 10001 and Higher Serial No. 10001 and Higher Serial No. 10001 and Higher Serial No. 10001 and Higher Serial No. 10001 and Higher Table of Contents Manual Structure Purpose of this manual ......................................................................................................... 5(E) Related manuals .................................................................................................................... 5(E) Contents ................................................................................................................................ 6(E) 1. Location of Mounted Circuit Boards 2. Semiconductor Pin Assignments 3. Spare Parts 3-1. Notes on Repair Parts .................................................................................................. 3-1 3-2. Exploded Views .......................................................................................................... 3-3 3-3. Spare Parts List ........................................................................................................... 3-4 3-4. Electrical Parts List for Boards ................................................................................. 3-53 3-5. Parts List for Frame ................................................................................................. 3-194 3-6. Packing Materials & Supplied Accessories ............................................................ 3-200 3-7. Optional Fixtures ..................................................................................................... 3-200 4. Block Diagrams Overall ................................................................................................................... 4-2 APR-32, CP-298/299/299A ..................................................................................... 4-4 CUE-10 ................................................................................................................... 4-6 DCP-11 ................................................................................................................... 4-7 DIF-43 ................................................................................................................... 4-8 DPR-89 ................................................................................................................. 4-12 EQ-65 ................................................................................................................. 4-14 PSW-51 ................................................................................................................. 4-15 SS-75 ................................................................................................................. 4-16 HDW-500 MMP2V2 1 (E) 5. Board Layouts AC-169 ................................................................................................................... 5-3 APR-32 ................................................................................................................... 5-4 CCM-15 ................................................................................................................... 5-6 CL-29 ................................................................................................................... 5-6 CP-266A .................................................................................................................. 5-7 CP-298 ................................................................................................................... 5-8 CP299/299A .......................................................................................................... 5-10 CUE-10 ................................................................................................................. 5-12 DCP-11 ................................................................................................................. 5-14 DIF-43A ................................................................................................................ 5-16 DPR-89 ................................................................................................................. 5-18 DPR-104 ................................................................................................................ 5-21 DR-307 ................................................................................................................. 5-22 DT-34C ................................................................................................................. 5-25 EQ-65 ................................................................................................................. 5-26 FP-103 ................................................................................................................. 5-29 HN-249 ................................................................................................................. 5-30 HN-250 ................................................................................................................. 5-32 HN-251 ................................................................................................................. 5-32 KY-330A ............................................................................................................... 5-33 LP-81 ................................................................................................................. 5-37 MB-697 ................................................................................................................. 5-34 PC-70 ................................................................................................................. 5-37 PD-35 ................................................................................................................. 5-37 PSW-51 ................................................................................................................. 5-38 PTC-54 ................................................................................................................. 5-41 PTC-59 ................................................................................................................. 5-41 PTC-69 ................................................................................................................. 5-41 PTC-71 ................................................................................................................. 5-41 RM-82 ................................................................................................................. 5-41 SS-75 ................................................................................................................. 5-42 SW-749 ................................................................................................................. 5-44 SWC-17D .............................................................................................................. 5-45 SWC-32 ................................................................................................................. 5-46 TR-78 ................................................................................................................. 5-46 TR-79 ................................................................................................................. 5-46 VR-152 ................................................................................................................. 5-47 VR-153 ................................................................................................................. 5-47 2 (E) HDW-500 MMP2V2 6. Schematic Diagrams 6-1. Frame Wiring .............................................................................................................. 6-2 6-2. Schematic Diagrams .................................................................................................... 6-8 AC-169 (Frame Wiring) .......................................................................................... 6-7 APR-32 ................................................................................................................... 6-8 CCM-15 (Frame Wiring) ......................................................................................... 6-4 CL-29 (Frame Wiring) ............................................................................................ 6-4 CP-266A ................................................................................................................ 6-26 CP-298 ................................................................................................................. 6-30 CP-299 ................................................................................................................. 6-32 CP-299A ................................................................................................................ 6-34 CUE-10 ................................................................................................................. 6-37 DCP-11 ................................................................................................................. 6-48 DIF-43A ................................................................................................................ 6-58 DPR-89 ................................................................................................................. 6-78 DPR-104 .............................................................................................................. 6-108 DR-307 ............................................................................................................... 6-112 DT-34C ............................................................................................................... 6-121 EQ-65 ............................................................................................................... 6-123 FP-103 ............................................................................................................... 6-136 HN-249 ............................................................................................................... 6-138 HN-250 ............................................................................................................... 6-139 HN-251 ............................................................................................................... 6-140 KY-330A ............................................................................................................. 6-141 LP-81 (Frame Wiring) ............................................................................................. 6-4 MB-697 ............................................................................................................... 6-143 PC-70 (Frame Wiring) ............................................................................................. 6-4 PD-35 (Frame Wiring) ............................................................................................ 6-4 PSW-51 ............................................................................................................... 6-152 PTC-54 (Frame Wiring) .......................................................................................... 6-4 PTC-59 (Frame Wiring) .......................................................................................... 6-5 PTC-69 (Frame Wiring) .......................................................................................... 6-3 PTC-71 (Frame Wiring) .......................................................................................... 6-4 RM-82 (Frame Wiring) ........................................................................................... 6-5 SS-75 ............................................................................................................... 6-154 SE-344 (Frame Wiring) ........................................................................................... 6-5 SW-749 ............................................................................................................... 6-181 SWC-17D ............................................................................................................ 6-182 SWC-32 ............................................................................................................... 6-185 TR-78 (Frame Wiring) ............................................................................................ 6-4 TR-79 (Frame Wiring) ............................................................................................ 6-4 VR-152 (Frame Wiring) .......................................................................................... 6-6 VR-153 (Frame Wiring) .......................................................................................... 6-6 HDW-500 MMP2V2 3 (E) Manual Structure Purpose of this manual This manual is the maintenance manual part 2 of the HD digital video cassette recorder HDW-500. This manual is intended for use by trained system and service engineers, and is provided information that is premised the parts level service (adjustments, board layouts, schematic diagrams, detailed parts list and the like) for this unit and the optional board. Related manuals Besides this maintenance manual part 2, the following manuals are available. The part numbers for the manuals are as of December 1997. . Operation Manual (Supplied with this unit) This manual is necessary for the use and operation (and installation) of this unit. Part No. : 3-194-349-02 . Maintenance Manual Part 1 (Supplied with this unit) This manual is provided the information required for the installation (including with option board), maintenance information and information for the service such as replacement of plug-in boards. Part No. : 3-194-348-02 . Protocol Manual for Remote (9-pin) (Available on your request) This manual is explained the protocols for controlling this unit by the RS-422A (9-pin serial remote). If this manual is required, please contact to your local Sony’s sale/service office. Part No. : 9-968-513-61 . BKDW-509 Interface Manual (Available on your request) This manual is explained the protocols for controlling this unit by the parallel 50pin. If this manual is required, please contact to your local Sony’s sale/service office. Part No. : 9-967-559-04 . ISR Protocol Manual (Available on your request) This manual is explained the ISR functions (Interactive Status Reporting System/ Integrated Equipment Management Function) of this unit. If this manual is required, please contact to your local Sony’s sale/service office. ISR: Interactive Status Reporting / Integrated Equipment Management Function Part No. : 9-968-521-61 HDW-500 MMP2V2 5(E) Contents The maintenance manuals part 2 are organized by following sections. Maintenance Manual Part 2 Volume 1 Section 1 Service Overview This section is described about the extension board, NV-RAM and flash-memory. Section 2 General Information for Electrical Alignment This section is described about the tools, measurement equipments and internal test signals. Section 3 Electrical Alignment This section is described about the electrical adjustment for the power supply, system control, servo, analog audio, RF, digital video, digital audio and the like. Section 4 Electrical Alignment (Option Board HKDV-501) This section is described about the electrical alignment for option board HKDV-501. Section 5 Replacement of Main Parts This section is described about the replacement for the drum head, capstan motor, reel motor, tape guides, cassette compartment, fan motor, power supply unit and the like. Section 6 Alignment after Replacement of Main Parts This section is described about the tape path alignment and electrical alignment after replacement of main parts. Maintenance Manual Part 2 Volume 2 Section 1 Location of Mounted Circuit Boards This section is described about the location of mounted circuit boards. Section 2 Semiconductor Pin Assignments This section is described about the semiconductor pin assignments. Section 3 Spare Parts This section is described about the detailed spare parts list and exploded views. Section 4 Block Diagrams This section is described about the block diagrams in the alphabetical order. Section 5 Board Layouts This section is described about the board layouts of mounted circuit boards in the alphabetical order. Section 6 Schematic Diagrams This section is described about the frame wiring and schematic diagrams of the mounted circuit boards in the alphabetical order. 6(E) HDW-500 MMP2V2 Section 1 Location of Mounted Circuit Boards System configuration No. Board name Circuit function Model name Page Digital process 1 DIF-43A HD serial digital interface with Embedded audio HDW-500 1-3 2 DPR-89 Digital data processor (Encoder/Decoder, Error correction) 3 RX-35 HD serial digital interface RX module Standard-equipped with HDW-500, or HK-102 (J only) 4 TX-52 HD serial digital interface TX module Standard-equipped with HDW-500, or HK-101 (J only) 5 APR-32 Audio signal processor (A-D, D-A, AES/EBU interface) HDW-500 6 CUE-10 CUE, TC REC/PB and LAU PB circuit 7 EQ-65 RF equalizer (REC current cont., PB EQ, Analog BETACAM PB buffer) 8 DR-307 Motors (Drum, Reel, Capstan, etc.) driver, Solenoids driver 9 DT-34C DT driver 10 SS-75 System , Servo, DT control Motherboard 11 MB-697 Motherboard HDW-500 1-3 and 1-4 Connect 12 HN-249 Connection board (Drum, etc.) with REC inhibit sensor HDW-500 1-3 13 HN-250 Connection board (Threading motor, etc.) HDW-500 1-3 and 1-5 14 HN-251 Connection board with Dew sensor 1-3 RF/Analog process System/Servo control Option Power Front panel function Rear panel function HDW-500 MMP2V2 15 DCP-11 HD-525 Down-converter HKDV-501 16 DPR-104 Digital data processor (Editing process board) HKDV-505 17 RX-35 HD serial digital interface RX module for Dub-in HKDV-504 (RX-35 and TX-52) 18 TX-52 HD serial digital interface TX module for Dub-out (Dubbing interface board) 19 AC-169 AC connector board with Breaker 20 PSW-51 DC-DC converter 21 PS unit Switching regulator (PS = Power supply) 22 CP-266A CPU board for Control panel HDW-500 1-4 23 FP-103 Panel function (Switches, LEDs) control, CAV control level conversion HDW-500 1-3 and 1-4 24 KY-330A SW board for Control panel HDW-500 1-4 25 PTC-69 Search dial sensor 26 SWC-17D Upper panel function (Switches, LEDs) 27 SW-749 Function control switches 28 SWC-32 Int/Ext Control panel select 29 VR-152 Audio REC level VRs 30 VR-153 Audio PB level VRs 31 CP-298 Rear panel connector board (Analog video signal buffer) 32 CP-299/299A Rear panel connector board (Analog/Digital audio, TC) HDW-500 CP-299 : HDW-500 (J) CP-299A : HDW-500 (UC) 1-1 System configuration No. Board name Circuit function Model name Page Mech. deck driver/sensor 33 CCM-15 Reel shift motor HDW-500 1-5 34 CCM-15 Threading motor 35 PD-35 Pinch solenoid connection 36 PTC-54 Threading FG 37 PTC-59 Cassette’s holes sensor 38 PTC-71 Reel position sensor 39 RM-82 S reel motor 40 RM-82 T reel motor 41 SE-344 S reel FG 42 SE-344 T reel FG 43 TR-78 S tension sensor 44 TR-79 T tension sensor, Threading-end and Unthreading-end sensors 45 CL-29 Cassette up/down motor, Cassette down sensors 46 LP-81 Lamp of cassette compartment 47 PC-70 Cassette-in sensors, Cassette size sensor Cassette compartment driver/sensor 1-2 HDW-500 MMP2V2 7 6 !\ @/ !. 1 !, @- 4 !; !] ![ 2 5 3 != !/ !' @[Rear !- 9 8 Front HDW-500 MMP2V2 1-3 @[ @. #/ @; @] @= @\ @, @' #- #= !- 1-4 HDW-500 MMP2V2 #; #] $] ![ !] #\ #' $[ $= $- #. #, #[ $/ $\ $; $' HDW-500 MMP2V2 1-5 Index Section 2 Semiconductor Pin Assignments Semiconductors of which functions are equivalent are described here. For parts replacement, refer to the section of Spare Parts in this manual. The circuit diagram of each IC is obtained from the IC data book published by the manufacturer. DIODE Page 1S2835-T1 ........................ 2-4 1S2836 ............................. 2-4 1SS123-T1 ........................ 2-4 1SS193 ............................ 2-4 1SS193-TE85L ................. 2-4 1SS226 ............................ 2-4 1SS300-TE85L ................. 2-4 1SS301-TE85L ................. 2-4 1SS302 ............................ 2-4 1SS302-TE85L ................. 2-4 DA204U ........................... 2-4 DA204UT106 .................... 2-4 DAN202U ......................... 2-4 DAN202UT106 .................. 2-4 DAP202U ......................... 2-4 DAP202UT106 .................. 2-4 EC10DS2 ......................... 2-4 EC10DS2-TE12L5 ............ 2-4 ECL06B025-F ................... 2-4 ECL06B025-TE16F2 ........ 2-4 ECL06B025-TE16F2 ........ 2-4 ERB81-004 ....................... 2-4 ERC84-009 ....................... 2-4 MA141WK ........................ 2-4 RB420D ........................... 2-4 SB007-03CP ..................... 2-4 SB007-03CP-TB ............... 2-4 SB007T03Q ...................... 2-4 SB007T03Q-TL ................. 2-4 SB01-05CP ....................... 2-4 SB01-05CP-TB ................. 2-4 SB02-03C-TB ................... 2-4 TRANSISTOR Page 2SA812-T1-M5M6 ............ 2-4 2SA1162G ........................ 2-4 2SA1213Y-TE12L ............. 2-4 2SA1314C-TE12L ............. 2-4 2SA1610-T1Y33 ............... 2-4 2SA1610-Y33 ................... 2-4 2SA1611-M5M6 ................ 2-4 2SA1611T1-M5M6 ............ 2-4 2SB798-DL ....................... 2-4 2SB1115-T1YL ................. 2-4 2SB1115A-YQ .................. 2-4 2SB1151-K ....................... 2-4 2SB1151-L ........................ 2-4 2SC1623 .......................... 2-4 2SC1623-T1-L5L6 ............ 2-4 2SC2120-Y ....................... 2-4 2SC2120-Y-TPE2 ............. 2-4 2SC2603TP-F ................... 2-4 2SC2785-HFE .................. 2-4 2SC3356-(R25) ................. 2-4 2SC3356-T1(R25) ............ 2-4 2SC4177-L6 ...................... 2-4 2SC4177-T1L5L6 ............. 2-4 2SC4213-B ....................... 2-4 2SC4213B-TE85L ............. 2-4 2SD596-DV5 ..................... 2-4 2SD596-T1DV5 ................. 2-4 2SD773 ............................ 2-4 2SD773-T-3 ....................... 2-4 2SD1615A-GP .................. 2-4 2SD1615A-T1GQGP ........ 2-4 2SD1683-T ....................... 2-4 2SJ106-Y ......................... 2-5 2SJ106Y-TE85L ................ 2-5 2SJ294 ............................. 2-5 2SK94-T1X3 ..................... 2-5 2SK94-X4 ........................ 2-5 2SK208-Y ........................ 2-5 2SK2084L ........................ 2-5 2SK208Y-TE85L ............... 2-5 2SK711-BL ....................... 2-5 2SK711-BL/V-TE85L ........ 2-5 2SK2232 .......................... 2-5 TRANSISTOR Page DTA144EUT106 ................ 2-5 DTC114EU ....................... 2-5 DTC114EUA-T106 ............ 2-5 DTC114YKA-T146 ............ 2-5 DTC123JUA-T106 ............ 2-5 DTC144ES ........................ 2-5 DTC144ESA ..................... 2-5 DTC144EUA-T106 ............ 2-5 OTHERS Page CL-150D-CD ..................... 2-5 CL-150D-CD-T .................. 2-5 CL-150PG-CD .................. 2-5 CL-150PG-CD-T ............... 2-5 CL-150R-CD ..................... 2-5 CL-150R-CD-T .................. 2-5 CL-150UR-CD .................. 2-5 GL5HD8 ........................... 2-5 SI-9430DY-T1 .................... 2-5 TLG182P ......................... TLG255A ......................... TLS255A .......................... TLY255A .......................... LED 2-5 2-5 2-5 2-5 Page DM-211A .......................... 2-5 GP1A52HR ....................... 2-5 GP1A53HR ....................... 2-5 DTA114EUA ...................... 2-5 DTA114EUA-T106 ............ 2-5 DTA114TKA-T146 ............. 2-5 DTA123JKA-T146 ............. 2-5 DTA144EU ........................ 2-5 DTA144EUA-T106 ............ 2-5 HDW-500 MMP2V2 2-1 Index IC Page 74AC245SJ ....................... 2-6 74AC245SJX .................... 2-6 74LCX00MTCX ................. 2-6 74LCX04MTCX ................. 2-6 74LCX04SJX .................... 2-6 74LCX08MTCX ................. 2-6 74LCX14SJX .................... 2-7 74LCX125SJX .................. 2-7 74LCX240MTCX ............... 2-7 74LCX240SJX .................. 2-7 74LCX244MTCX ............... 2-7 74LCX244SJX .................. 2-7 74LCX245MTCX ............... 2-6 74LCX245SJX .................. 2-6 74LCX540MTCX ............... 2-8 74LCX541MTCX ............... 2-8 74LCX574MTCX ............... 2-9 74LCX574SJX .................. 2-9 74LCX16244MTDX ........... 2-7 74LCX16374MTDX ........... 2-8 74LVX4245QSCX ............. 2-9 74VHC04SJ ...................... 2-6 74VHC245SJ .................... 2-6 74VHCT574MTCX ............ 2-9 AD1890JP ........................ 2-9 AD7528JN ...................... 2-10 AK5390-VS ..................... 2-10 AK5390-VS-E2 ............... 2-10 AM26LS32ACNS .............. 2-8 AM26LS32ACNS-E20 ...... 2-8 CA3094M ......................... 2-9 CXA1432M ..................... 2-11 CXA1432M-T4 ................ 2-11 CXA1451M ..................... 2-11 CXA1451M-TH ............... 2-11 CXD1095BQ ................... 2-12 CXD2202Q ..................... 2-14 CXD2306Q ..................... 2-11 CXD2306Q-T4 ................ 2-11 CXD2308Q ..................... 2-13 CXD8110K ...................... 2-16 CXD8115Q ..................... 2-12 CXD8117P ...................... 2-13 CXD8176AQ ................... 2-17 CXD8277Q ..................... 2-18 CXD8278AQ ................... 2-20 CXD8281Q ..................... 2-22 CXD8384Q ..................... 2-24 CXD8385Q ..................... 2-26 CXD8591Q ..................... 2-23 CXD8804Q ..................... 2-28 CXD8811AQ ................... 2-30 CXD8814Q ..................... 2-32 CXD8820AR ................... 2-29 CXD8824AQ ................... 2-32 CXD8845Q ..................... 2-17 CXD8859AQ ................... 2-21 CXD8953Q ..................... 2-33 2-2 IC Page CXD9000CR ................... 2-31 CXD9001AR ................... 2-34 CXD9003BR ................... 2-38 CXD9008Q ..................... 2-36 CXD9013AR ................... 2-35 CXD9014AR ................... 2-39 CXD9015BR ................... 2-40 CXD9016AR ................... 2-39 CXD9017BR ................... 2-41 CXD9018BR ................... 2-40 CXD9019AR ................... 2-41 CXD9020BR ................... 2-42 CXD9021AR ................... 2-43 CXD9032R ...................... 2-42 CXG8003Q ..................... 2-45 CXG8004Q ..................... 2-46 CXK1203AR ................... 2-44 CXK1203AR-T4 .............. 2-44 CXP80P624AQ-1 ............ 2-48 CXP80P624AQ-1-008 .... 2-48 CY7C199-20VC .............. 2-45 DBX2151 ....................... 2-46 DBX2155 ....................... 2-46 DS90LV031TMX ............. 2-48 DS90LV032TMX ............. 2-48 EL2244CS-TE2 ............... 2-46 EPM7032LC44-10 .......... 2-44 EPM7032QC44-15 ......... 2-47 EPM7032VTC44-12 ........ 2-47 EPM7064TC44-7 ............ 2-50 GAL16LV8C-15LJ ........... 2-47 GAL16V8B-25LP ............ 2-47 HD63484CP8 .................. 2-51 HD63487CP .................... 2-52 HD6415108RF10 ............ 2-54 HD6417032F20 .............. 2-56 HM514402CZ-8 .............. 2-57 HM62W8127HBJP-27Z ... 2-50 IDT79R3041-20J ............ 2-59 IDT6116SA25S0 ............. 2-53 IDT6116SA25SO-T ......... 2-53 IDT71024S20Y-TL .......... 2-53 L78M05T-FA .................... 2-51 L78M05T-FA-TL .............. 2-51 L79M05T-FA .................... 2-51 L79M05T-FA-TL .............. 2-51 LC3564SM-70-TLM ........ 2-58 LM311PS ....................... 2-58 LM311PS-E05 ................ 2-58 LM324NS ....................... 2-58 LM324NS-E05 ................ 2-58 LM1881M ....................... 2-58 LM1881MX ..................... 2-58 LM2576T-ADJ ................. 2-59 IC Page LM2577T-ADJ ................. 2-58 LM2903P ....................... 2-53 LT1021DCS8-5 ............... 2-60 LT1227CS8 ..................... 2-60 LT1227CS8-E2 ............... 2-60 LT1252CS8 ..................... 2-60 LT1252CS8-E2 ............... 2-60 LT1431CS8-E1 ............... 2-60 M4T28-BR12SH1 ........... 2-61 M5M5408AFP-55LL ........ 2-62 M5M5408AFP-55LL-E2 .... 2-62 M27C512-12F1 ............... 2-60 M48T18-100MH1TR ....... 2-61 M5238FP ....................... 2-61 M5238FP-600D .............. 2-61 M51957BFP .................... 2-60 M51958AFP600D ........... 2-61 M54532P ....................... 2-61 M62301FP ...................... 2-62 M62301FP-70ND ............ 2-62 MB90T736 ...................... 2-68 MB8421-90LPFQ ............ 2-63 MB8441-45PFQ .............. 2-65 MB90091A-120 ............... 2-66 MB811161622A-100FN .... 2-63 MBM29F040A-12PD ....... 2-64 MBM29F040A-90PD ....... 2-65 MBM29F400BA-90PF .... 2-66 MC10EL07DR2 ............... 2-64 MC10EL11DR2 ............... 2-64 MC10EL16DR2 ............... 2-64 MC10H124M ................... 2-64 MC10H124MEL .............. 2-64 MC74HC133F ................. 2-76 MC74HC163AF .............. 2-69 MC74HC175F ................. 2-69 MC74HC4053F ............... 2-69 MC74HC4053FEL .......... 2-69 MC1488MEL ................... 2-67 MC1489AM ..................... 2-67 MC1489AM-T2 ............... 2-67 MC14051BF .................... 2-67 MC14051BFEL ............... 2-67 MC14053BF .................... 2-67 MC14053BFEL ............... 2-67 MC14538BF .................... 2-67 MC14538BFE ................. 2-67 MC14538BFEL ............... 2-67 MC34051M ..................... 2-67 MC34051MEL ................. 2-67 MC34182DR2 ................. 2-61 MC34182M ..................... 2-61 MC34182MEL ................. 2-61 MN47V77ST1 ................. 2-70 MSM514221B-30JS ........ 2-70 NJM78L05A .................... 2-69 NJM78L05A-T3 ............... 2-69 NJM78L05UA .................. 2-69 IC Page NJM78L05UA-TE1 .......... 2-69 NJM78L09UA .................. 2-69 NJM78L09UA(TE1) ........ 2-69 NJM78L12A .................... 2-69 NJM78L12A-T3 ............... 2-69 NJM79L05A .................... 2-69 NJM79L05A-T3 ............... 2-69 NJM79L05UA .................. 2-71 NJM79L05UA-TE1 .......... 2-71 NJM79L09UA(TE1) ........ 2-71 NJM360M ...................... 2-70 NJM360M-TE2 ................ 2-70 NJM2041M-D .................. 2-61 NJM2041M-D(TE2) ......... 2-61 NJM2068M-D-TE2 .......... 2-61 NJM2903D ...................... 2-53 NJM2903M ..................... 2-53 NJM2903M-TE2 .............. 2-53 NJM4556M-A .................. 2-61 NJM4560M ..................... 2-61 NJM4560MD ................... 2-61 NJM4565M-A .................. 2-61 NJM5532M ..................... 2-61 NJM5532M-D .................. 2-61 NJM5532S-D .................. 2-70 PCM69AP-K ................... 2-71 PCM1702U-J .................. 2-71 PCM1702U-J-T2 ............. 2-71 S-8052-ANY-NH .............. 2-71 S-8052ANY-NH-T1 ......... 2-71 S-8054HN-CB-S ............. 2-71 S-8054HN-CB-T1 ........... 2-71 SBX1601A ...................... 2-72 SC7S32F ....................... 2-71 SM5842APT ................... 2-72 SN74CBT3345PW-E05 ... 2-73 SN74HC00ANS ................ 2-6 SN74HC00ANS-E05 ......... 2-6 SN74HC02ANS .............. 2-73 SN74HC02ANS-E05 ....... 2-73 SN74HC04ANS ................ 2-6 SN74HC04ANS-E05 ......... 2-6 SN74HC08ANS ................ 2-6 SN74HC08ANS-E05 ......... 2-6 SN74HC10ANS .............. 2-73 SN74HC10ANS-E05 ....... 2-73 SN74HC32ANS .............. 2-74 SN74HC32ANS-E05 ....... 2-74 SN74HC74ANS .............. 2-75 SN74HC74ANS-E05 ....... 2-75 SN74HC86ANS-E05 ....... 2-76 SN74HC109ANS ............ 2-73 SN74HC109ANS-E05 .... 2-73 SN74HC125ANS .............. 2-7 SN74HC125ANS-E05 ...... 2-7 SN74HC138ANS ............ 2-73 SN74HC138ANS-E05 .... 2-73 SN74HC157ANS ............ 2-73 HDW-500 MMP2V2 Index IC Page SN74HC157ANS-E05 .... 2-73 SN74HC163ANS-E05 .... 2-69 SN74HC193ANS ............ 2-74 SN74HC193ANS-E05 .... 2-74 SN74HC244ANS .............. 2-7 SN74HC244ANS-E05 ...... 2-7 SN74HC245ANS .............. 2-6 SN74HC245ANS-E05 ...... 2-6 SN74HC373ANS ............ 2-74 SN74HC373ANS-E05 .... 2-74 SN74HC393ANS ............ 2-74 SN74HC393ANS-E05 .... 2-74 SN74HC541ANS .............. 2-8 SN74HC541ANS-E05 ...... 2-8 SN74HC574ANS .............. 2-9 SN74HC574ANS-E05 ...... 2-9 SN74HC4040ANS .......... 2-75 SN74HC4040ANS-E05 ... 2-75 SN74HCT04ANS .............. 2-6 SN74HCT04ANS-E05 ...... 2-6 SN74HCT244ANS ............ 2-7 SN74HCT244ANS-E05 .... 2-7 SN74HCT245ANS ............ 2-6 SN74HCT245ANS-E05 .... 2-6 SN74HCT541ANS ............ 2-8 SN74HCT541ANS-E05 .... 2-8 SN74HCU04ANS .............. 2-6 SN74HCU04ANS-E05 ...... 2-6 SN74LS164NS ............... 2-75 SN74LS164NS-E05 ........ 2-75 SN75207BNS ................. 2-75 SN75207BNS-E05 .......... 2-75 SN751177NS .................. 2-75 SN75C1168NS-E05 ........ 2-76 TA78L05F ....................... 2-69 TA78L05F-TE12L ............ 2-69 TA78L09F-TE12L ............ 2-69 TA78L12F ....................... 2-69 TA78L12F-TE12L ............ 2-69 TA79L12F(TE12L) .......... 2-71 TA79L12F-TE12L ............ 2-71 TC4W66F ...................... 2-76 TC4W66F(TE12R) .......... 2-76 TC7S32F(TE85R) ........... 2-71 TC74AC00F ...................... 2-6 TC74AC00F-EL ................ 2-6 TC74AC08F ...................... 2-6 TC74AC08F-EL ................ 2-6 TC74AC32F .................... 2-74 TC74AC32F(EL) ............. 2-74 TC74AC139F .................. 2-76 TC74AC139F(EL) ........... 2-76 TC74HC08AF(EL) ............ 2-6 TC74HC86AF ................. 2-76 TC74HC123AF ............... 2-76 TC74HC123AF(EL) ........ 2-76 TC74HC133AF ............... 2-76 TC74HC175AF-TP2 ....... 2-69 TC74HC688AF ............... 2-77 HDW-500 MMP2V2 IC Page TC74HC688AF(EL) ........ 2-77 TC74HC4024AF ............. 2-77 TC74HC4024AF(EL) ...... 2-77 TC74HC4053AF(EL) ...... 2-69 TC74HC4538AF ............. 2-77 TC74HC4538AF(EL) ...... 2-77 TC74HCT04AF ................. 2-6 TC74HCT04AF(EL) .......... 2-6 TC74VHC00F ................... 2-6 TC74VHC00F(EL) ............ 2-6 TC74VHC00FS(EL) .......... 2-6 TC74VHC04F ................... 2-6 TC74VHC04FS(EL) .......... 2-6 TC74VHC08FS(EL) .......... 2-6 TC74VHC10F ................. 2-73 TC74VHC10F(EL) .......... 2-73 TC74VHC10FS(EL) ........ 2-73 TC74VHC21F ................. 2-78 TC74VHC21F(EL) .......... 2-78 TC74VHC32F ................. 2-74 TC74VHC32F(EL) .......... 2-74 TC74VHC32FS(EL) ........ 2-74 TC74VHC74F ................. 2-75 TC74VHC74F(EL) .......... 2-75 TC74VHC74FS(EL) ........ 2-75 TC74VHC86FS(EL) ........ 2-76 TC74VHC125FS(EL) ........ 2-7 TC74VHC153FS(EL) ...... 2-77 TC74VHC157FS(EL) ...... 2-73 TC74VHC164F ............... 2-78 TC74VHC164FS(EL) ...... 2-78 TC74VHC174F ............... 2-78 TC74VHC174F(EL) ........ 2-78 TC74VHC174FS(EL) ...... 2-78 TC74VHC221AFS(EL) ... 2-78 TC74VHC244F ................. 2-7 TC74VHC244FS(EL) ........ 2-7 TC74VHC245F ................. 2-6 TC74VHC245F(EL) .......... 2-6 TC74VHC245FS(EL) ........ 2-6 TC74VHC541F ................. 2-8 TC74VHC541F(EL) .......... 2-8 TC74VHC541FS(EL) ........ 2-8 TC74VHC573F ............... 2-78 TC74VHC573F(EL) ........ 2-78 TC74VHC574F ................. 2-9 TC74VHC574FS ............... 2-9 TC74VHC574FS(EL) ........ 2-9 TC74VHCT00FS(EL) ........ 2-6 TC74VHCT04FS(EL) ........ 2-6 TC74VHCT138FS(EL) .... 2-73 TC74VHCT244F ............... 2-7 TC74VHCT244FS(EL) ...... 2-7 TC74VHCT245FS(EL) ...... 2-6 TC74VHCT541FS(EL) ...... 2-8 TD62003P ...................... 2-79 TL064CNS ...................... 2-79 TL064CNS-E05 .............. 2-79 TL082M .......................... 2-61 TL084CNS ...................... 2-79 IC Page TL084CNS-E05 .............. 2-79 TL431CPS ...................... 2-79 TL431CPS-E05 ............... 2-79 TL1451ACNS .................. 2-79 TL1451ACNS-E05 .......... 2-79 TLC272CPW-E05 ........... 2-79 TLC2932IPW .................. 2-80 TLC2932IPW-E20 ........... 2-80 TMS4C2973-26DTR ....... 2-80 UPA102G ....................... 2-79 UPC812G2 ..................... 2-61 UPC2708T-E3 ................. 2-79 UPC2712T-E3 ................. 2-80 UPC4558C ...................... 2-61 UPC4570G2 ................... 2-61 UPD78P014GC-AB8 ...... 2-85 UPD78P218AGC-AB8 .... 2-86 UPD485505G-25 ............ 2-85 UPD485505G-25-E2 ....... 2-85 UPD485505G-35 ............ 2-85 UPD485505G-35-E2 ....... 2-85 UPD70325L-10 ............... 2-81 UPD71054GB-3B4 ......... 2-81 UPD71055GB-10-3B4 .... 2-83 UPD71059GB-3B4 ......... 2-83 UPD72001GC-11-3B6 .... 2-84 2-1 Diode, Transistor DIODE TRANSISTOR TYPE NO. PRINTED —TOP VIEW— —TOP VIEW— 1S2835-T1 1S2836 1SS300-TE85L DAP202U DAP202UT106 ECL06B025-F ECL06B025-TE16F2 1SS193 1SS193-TE85L SB007-03CP SB007-03CP-TB SB01-05CP SB01-05CP-TB 2SC2603TP-F 2SC2785-HFE 2SA812-T1-M5M6 2SA1162G 2SA1610-T1Y33 2SA1610-Y33 2SA1611-M5M6 2SA1611T1-M5M6 —TOP VIEW— —TOP VIEW— —TOP VIEW— NC —TOP VIEW— ECL06B025-TE16F2 2SA1213Y-TE12L 2SA1314C-TE12L 2SB798-DL 2SB1115-T1YL 2SB1115A-YQ —TOP VIEW— 2SC4213-B 2SC4213B-TE85L —TOP VIEW— 1SS123-T1 1SS226 1SS302 1SS302-TE85L DA204U DA204UT106 RB420D SB007T03Q SB007T03Q-TL SB02-03C-TB 2SB1151-K 2SB1151-L ERB81-004 ERC84-009 TYPE NO. PRINTED 2SD1683-T —TOP VIEW— —TOP VIEW— 1SS301-TE85L DAN202U DAN202UT106 MA141WK 2SD1615A-GP 2SD1615A-T1GQGP (NEC) 2SC1623 2SC1623-T1-L5L6 2SC3356-(R25) 2SC3356-T1(R25) 2SC4177-L6 2SC4177-T1L5L6 2SD596-DV5 2SD596-T1DV5 —TOP VIEW— EC10DS2 EC10DS2-TE12L5 2-4 2SC2120-Y 2SC2120-Y-TPE2 2SD773 2SD773-T-3 HDW-500 MMP2V2 Transistor, Others, LED OTHERS —TOP VIEW— —TOP VIEW— DTA114EUA (R1=10 K, R2=10 K) DTA114EUA-T106 DTA114TKA-T146 (R1=10 K, R2=OPEN) DTA123JKA-T146 (R1=2.2 K, R2=47 K) DTA144EU (R1=47 K, R2=47 K) DTA144EUA-T106 (R1=47 K,R2=47 K) DTA144EUT106 2SJ106-Y 2SJ106Y-TE85L S R1 R2 CL-150D-CD ; ORANGE CL-150D-CD-T CL-150PG-CD ; GREEN CL-150PG-CD-T CL-150R-CD ; RED CL-150R-CD-T CL-150UR-CD ; RED GL5HD8 ; RED TLG182P ; GREEN 2SJ294 —TOP VIEW— DTC114EU (R1=10 K, R2=10 K) DTC114EUA-T106 (R1=10 K, R2=10 K) DTC114YKA-T146 (R1=10 K, R2=47 K) DTC123JUA-T106 (R1=2.2 K,R2=47 K) DTC144EUA-T106 (R1=47 K, R2=47 K) R1 R2 S TLG255A ; GREEN TLS255A ; RED TLY255A ; YELLOW —TOP VIEW— 2SK94-T1X3 2SK94-X4 2SK208-Y 2SK208Y-TE85L 2SK711-BL 2SK711-BL/V-TE85L S DTC144ES (R1=47 K, R2=47 K) DTC144ESA (R1=47 K, R2=47 K) R1 R2 LED 2SK2084L 1 8 2 3 7 SI-9430DY-T1 6 4 5 DM-211A 1 4 3 2 1 Magneto–Sensing Element –Equivalent Circuit– 1 VCC 2 V2 S V3 3 4 GND 4 S 5 6 7 8 2SK2232 GP1A52HR GP1A53HR 5 4 1 3 2 5 CONSTANT–VOLTAGE CIRCUIT 15K S 1 2 HDW-500 MMP2V2 4 3 2-5 IC 74LCX04MTCX (NS)FLAT PACKAGE 74LCX04SJX (NS)FLAT PACKAGE 74VHC04SJ (NS)FLAT PACKAGE SN74HC04ANS (TI)FLAT PACKAGE SN74HC04ANS-E05 SN74HCT04ANS (TI)FLAT PACKAGE SN74HCT04ANS-E05 (TI)FLAT PACKAGE SN74HCU04ANS (TI)FLAT PACKAGE SN74HCU04ANS-E05 TC74HCT04AF (TOSHIBA)FLAT PACKAGE TC74HCT04AF(EL) TC74VHC04F (TOSHIBA)FLAT PACKAGE TC74VHC04FS(EL) TC74VHCT04FS(EL) (TOSHIBA)FLAT PACKAGE 74AC245SJ (NS)FLAT PACKAGE 74AC245SJX 74LCX245MTCX (NS)FLAT PACKAGE 74LCX245SJX (NS)FLAT PACKAGE 74VHC245SJ (NS)FLAT PACKAGE SN74HC245ANS (TI)FLAT PACKAGE SN74HC245ANS-E05 SN74HCT245ANS (TI)FLAT PACKAGE SN74HCT245ANS-E05 TC74VHC245F (TOSHIBA)FLAT PACKAGE TC74VHC245F(EL) (TOSHIBA)FLAT PACKAGE TC74VHC245FS(EL) (TOSHIBA)FLAT PACKAGE TC74VHCT245FS(EL) (TOSHIBA)FLAT PACKAGE C-MOS BILATERAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS —TOP VIEW— C-MOS HEX INVERTERS DIR IN 1 VDD 20 A1 2 19 EN IN A2 3 18 B1 A3 4 17 B2 DIR 3 17 5 A 14 7 13 DIR 16 B3 6 15 B4 A6 7 14 B5 A7 8 13 B6 9 12 B7 10 GND 11 B8 A8 B1 EN DIR 0 1 X HI-Z 11 1 EN 19 DIR OPERATION 0 B to A A to B 1 HI-Z X ; ; ; ; LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE 14 VDD 13 12 11 10 9 8 A VDD +2 to +6V TYPE 74HC 74ABT 74ACT 74BCT 74HCT 74AC 74VHC 74LCX 74LVT B3 16 17 A Y A Y 0 1 1 0 1 2 3 4 5 6 GND 7 0 ; LOW LEVEL 1 ; HIGH LEVEL NOTE: TYPE 74AC/74VHC/74VHCT 74ACT/74HCT 74LCX OTHER TYPE +4.5 to +5.5V +2 to +5.5V VDD +2 to +5.5V +4.5 to +5.5V +2 to +3.6V +2 to +6V +2 to +3.6V +2.7 to +3.6V B4 B5 15 Y = Y=A NOTE: B2 18 12 9 DIR 5 15 B 6 8 A5 EN 0 0 1 16 4 A4 —TOP VIEW— 18 2 B6 14 B7 13 12 B8 11 19 1 2 A1 4 3 A3 A2 5 6 A4 A5 7 8 A6 A7 9 A8 74LCX08MTCX (NS)FLAT PACKAGE SN74HC08ANS (TI)FLAT PACKAGE SN74HC08ANS-E05 TC74AC08F (TOSHIBA)FLAT PACKAGE TC74AC08F-EL TC74HC08AF(EL) (TOSHIBA)FLAT PACKAGE TC74VHC08FS(EL) (TOSHIBA)FLAT PACKAGE C-MOS QUAD 2-INPUT AND GATE —TOP VIEW— 14 VDD 74LCX00MTCX (NS)FLAT PACKAGE SN74HC00ANS (TI)FLAT PACKAGE SN74HC00ANS-E05 TC74AC00F (TOSHIBA)FLAT PACKAGE TC74AC00F-EL TC74VHC00F (TOSHIBA)FLAT PACKAGE TC74VHC00F(EL) TC74VHC00FS(EL) (TOSHIBA)FLAT PACKAGE TC74VHCT00FS(EL) (TOSHIBA)FLAT PACKAGE 1 12 11 10 9 11 10 9 8 A A B Y= Y B 2 3 4 5 6 GND 7 A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1 0 ; LOW LEVEL 1 ; HIGH LEVEL NOTE; TYPE 74AC 40H 74ACT/74HCT/74VHCT 74LCX OTHER TYPES —TOP VIEW— 13 12 Y=A B=A+B C-MOS QUAD 2-INPUT NAND GATES 14 VDD 13 VDD +2 to +5.5V +2 to +8V +4.5 to +5.5V +2 to +3.6V +2 to +6V 8 A B Y = A B Y Y=A•B=A+B 1 2 3 4 5 6 GND 7 A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 0 ; LOW LEVEL 1 ; HIGH LEVEL NOTE: TYPE 74AC/74VHC 74ACT/74HCT/74VHCT LCX OTHER TYPES 2-6 VDD +2 to +5.5V +4.5 to +5.5V +2 to +3.6V +2 to +6V HDW-500 MMP2V2 IC 74LCX125SJX (NS)FLAT PACKAGE SN74HC125ANS (TI)FLAT PACKAGE SN74HC125ANS-E05 TC74VHC125FS(EL) (TOSHIBA)FLAT PACKAGE 74LCX16244MTDX (NS)FLAT PACKAGE C-MOS BUS BUFFER GATES WITH 3-STATE OUTPUT 1OE 1 C-MOS 16-BIT BUFFER/DRIVER —TOP VIEW— —TOP VIEW— 14 VDD 48 1Y1 2 13 12 11 10 9 8 47 1A1 1Y2 3 G A 1 2 3 4 5 6 GND 7 0 1 X HI-Z NOTE : TYPE 74AC/ 74VHC 74ACT/74HCT 74LCX 74LVT/74LVC OTHER TYPES A 0 1 X VDD ; ; ; ; Y 0 1 HI-Z 41 3 40 9 44 5 38 11 8 43 6 37 12 1OE 2OE 1 48 44 1A3 1Y4 6 43 1A4 VDD 42 7 VDD 2Y1 8 LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE 2 46 46 1A2 1Y3 5 G 0 0 1 47 GND 45 4 GND Y 2OE 41 2A1 2Y2 9 36 13 30 19 35 14 29 20 33 16 27 32 17 26 40 2A2 10 GND GND 39 38 2A3 +2 to +5.5V 2Y4 12 37 2A4 +4.5 to +5.5V +2 to +3.6V +2.7 to +3.6V +2 to +6V 3Y1 13 36 3A1 0 0 1 GND 34 3Y3 16 33 3A3 3Y4 17 32 3A4 0 1 X HI-Z VDD 31 18 VDD 4Y1 19 24 INPUTS xAx 0 1 X xOE 35 3A2 15 GND 23 4OE 25 2Y3 11 3Y2 14 22 3OE ; ; ; ; OUTPUTS xYx 0 1 HI-Z LOW LEVEL HIGH LEVEL DON’T CARE HIGH IMPEDANCE 30 4A1 NOTE : 4Y2 20 29 4A2 74LCX14SJX (NS)FLAT PACKAGE C-MOS HEX SCHMITT TRIGGER INVERTERS —TOP VIEW— 14 13 12 11 10 9 8 Y= A A 1 V IN 2 3 4 5 6 V OUT 0 ; LOW LEVEL 1 ; HIGH LEVEL V IN VN VP NOTE : VDD +2 to +3.6V +2 to +5.5V +2 to +6V TYPE 74LCX TC74AC/VHC OTHER TYPES 26 4A4 4OE 24 25 3OE V OUT VDD VN VP 2.0V 0.75V 1.25V 4.5V 1.9V 2.7V 6.0V 2.6V 3.6V A Y 0 1 1 0 GND 7 27 4A3 4Y4 23 Y VDD Y=A 4Y3 22 VDD +5V +2 to +3.6V TYPE IDT74FCT IDT74LCX GND 28 21 GND 74LCX244MTCX (NS)FLAT PACKAGE 74LCX244SJX (NS)FLAT PACKAGE SN74HC244ANS (TI)FLAT PACKAGE SN74HC244ANS-E05 SN74HCT244ANS (TI)FLAT PACKAGE SN74HCT244ANS-E05 TC74VHC244F (TOSHIBA)FLAT PACKAGE TC74VHC244FS(EL) (TOSHIBA)FLAT PACKAGE TC74VHCT244F (TOSHIBA)FLAT PACKAGE TC74VHCT244FS(EL) C-MOS BUS BUFFER WITH 3-STATE OUTPUTS —TOP VIEW— 74LCX240MTCX (NS)FLAT PACKAGE 74LCX240SJX (NS)FLAT PACKAGE G2 19 20 VDD 18 17 16 15 14 13 12 11 A Y = A Y C-MOS 3-STATE INVERTER/LINE DRIVER G —TOP VIEW— G2 20 VDD 19 18 17 16 15 14 13 12 GND 1 2 3 4 5 6 7 8 9 G1 2 18 2 18 4 16 4 16 6 6 14 8 8 12 11 12 OR 1 13 7 15 5 11 9 17 3 13 7 15 5 17 3 G1 1 OR G2 19 A Y G 0 0 1 A Y 0 1 1 0 X HI-Z 0 1 X HI-Z ; ; ; ; LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE 14 G 9 10 G 0 0 X G 11 NOTE: TYPE 74HC 74ACT/74BC/74HCT 74LCX 74AC/74VHC VDD +2 to +6 V +4.5 to +5.5 V +2 to +3.6 V +2 to +5.5 V 1 2 3 4 5 6 7 8 9 0 1 X HI-Z G1 2 18 4 16 6 2 18 4 16 6 14 8 12 11 9 13 7 15 5 17 3 G1 1 GND 10 G2 19 14 8 12 G 1 OR 11 9 13 7 15 5 17 G A 0 1 X ; ; ; ; Y 0 1 HI-Z LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE NOTE: TYPE 74HC 40H 74ACT 74BCT 74FCT 74HCT 74LCX 74AC/74VHC VDD +2 to +6V +4.5 to +5.5V +2 to +3.6V +2 to +5.5V 3 G G 19 19 HDW-500 MMP2V2 2-7 IC 74LCX16374MTDX (NS)FLAT PACKAGE 74LCX540MTCX (NS)FLAT PACKAGE C-MOS 3-STATE 16-BIT D-TYPE FLIP-FLOP C-MOS 3-STATE OCTAL INVERTING BUFFERS/DRIVERS —TOP VIEW— —TOP VIEW— 47 1OE IN 1 1Q1 OUT 2 1Q2 OUT 3 48 1CLK 4 GND 46 IN 47 1D1 IN 46 1D2 IN 44 43 41 40 GND 45 38 1Q3 OUT 5 44 1D3 IN 1Q4 OUT 6 43 1D4 IN 7 VDD(+5V) OUT 35 VDD(+5V) 42 33 41 1D5 8 40 1D6 9 IN 32 30 IN 29 10 GND GND 39 27 1Q7 OUT 11 38 1D7 IN 1Q8 OUT 12 37 1D8 IN 2Q1 OUT 13 36 2D1 IN 2Q2 OUT 35 2D2 14 26 1 24 15 GND OUT 16 2Q4 OUT 17 GND 34 18 VDD(+5V) 2Q5 OUT 19 2Q6 OUT 20 25 33 2D3 IN 32 2D4 IN VDD(+5V) 31 21 GND 30 2D5 IN 29 2D6 IN OUT 22 27 2D7 IN 2Q8 OUT 23 26 2D8 IN OE 0 0 0 1 IN INPUTS CLK D 1 0 0 X X X NOTE : TYPE ABT LCX 1OE 1CLK 25 2CLK 24 OUTPUT Q 1 0 Qo HI-Z 1D4 1Q4 1D5 1Q5 1D6 1Q6 1D7 1Q7 1D8 1Q8 2D1 2Q1 2D2 2Q2 2D3 2Q3 2D4 2Q4 2D5 2Q5 2D6 2Q6 2D7 2Q7 2D8 2Q8 47 IN LOW LEVEL HIGH LEVEL DON’T CARE HIGH IMPEDANCE 46 44 2 3 43 41 40 5 3D 6 12 13 14 1 2 3 4 5 6 7 8 9 16 G1 A1 A2 A3 A4 A5 A6 A7 A8 17 19 2 18 20 3 17 22 4 16 23 5 15 6 14 7 13 1OE 2OE 38 37 8 9 6D 8 36 35 33 32 30 29 27 26 2-8 17 4D 19 5D 20 6D 22 7D C8 2D8 16 3D C7 2D7 14 2D C6 2D6 13 1D C5 2D5 TYPE TC74AC/TC74VHC HCT/ACT OTHER TYPES 74LCX VDD +2 to +5.5V +5V +2 to +6V +2 to +3.6V ; ; ; ; LOW LEVEL HIGH LEVEL DON’T CARE HIGH IMPEDANCE 11 G1 1 G2 19 2CLK ; DATA 74LCX541MTCX (NS)FLAT PACKAGE SN74HC541ANS (TI)FLAT PACKAGE SN74HC541ANS-E05 SN74HCT541ANS (TI)FLAT PACKAGE SN74HCT541ANS-E05 TC74VHC541F (TOSHIBA)FLAT PACKAGE TC74VHC541F(EL) TC74VHC541FS(EL) (TOSHIBA)FLAT PACKAGE TC74VHCT541FS(EL) (TOSHIBA)FLAT PACKAGE G2 19 Y1 18 Y2 17 Y3 16 Y4 15 Y5 14 Y6 13 Y7 12 Y8 11 A G2 1 G1 1Q1 G1 G2 0 0 0 0 1 X X 1 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 GND 10 0 1 X HI-Z 1Q2 1Q3 3 1Q4 5 7 1Q5 8 9 1Q6 Y G1 A1 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 Y8 A8 G1 NOTE : 18 ; ; ; ; A 0 1 X X Y 0 1 HI-Z HI-Z LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE TYPE VDD TC74AC/TC74VHC +2 to +5.5V ABT/ACT/BCT/HCT/VHCT +5V 74LCX +2 to +3.6V OTHER TYPES +2 to +6V 17 16 15 14 13 12 11 G2 19 1Q7 1Q8 24 C4 2D4 0 1 X HI-Z NOTE : Y 1 0 HI-Z HI-Z 12 9 1CLK GND 10 A 0 1 X X 25 C3 2D3 12 8D C2 2D2 11 7D C1 2D1 Y G1 G2 0 0 0 0 1 X X 1 9 11 6 5D C8 2CLK A 8 4 4D C7 2OE Y8 11 6 1 1D8 Y7 12 G1 20 VDD 2D C6 1D7 Y6 13 Y5 14 —TOP VIEW— 1D C5 1D6 Y4 15 48 C4 1D5 Y3 16 Y2 17 G2 2 1D4 Y1 18 1 C3 1D3 19 C-MOS BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS C2 1D2 ; ; ; ; OUTPUT 1Q1 - 1Q8 2Q1 - 2Q8 VDD +5V +2 to +3.6V C1 1D1 0 1 X HI-Z 1Q3 5 INPUT 1CLK, 2CLK ; CLOCK 1D1 - 1D8 ; DATA 2D1 - 2D8 1OE, 2OE ; OUTPUT ENABLE GND 28 2Q7 2OE 1D3 G2 20 VDD 3 IN 48 2Q3 1Q2 8D 23 2Q1 2Q2 AM26LS32ACNS (TI)FLAT PACKAGE AM26LS32ACNS-E20 HIGH SPEED DIFFERENTIAL LINE RECEIVER 2Q3 2Q4 2Q5 —TOP VIEW— EN2 16 VCC 15 14 13 12 11 10 + _ 1Q6 OUT 36 1Q1 1D2 (+5v) 9 _ + 1Q5 37 1D1 2 2Q6 _ + 2Q7 2Q8 1 3 4 5 6 7 EN2 EN1 0 0 0 1 1 0 1 1 OUTPUT ENABLE ENABLE HI-Z ENABLE GND 8 0 ; LOW LEVEL 1 ; HIGH LEVEL HI-Z ; HIGH IMPEDANCE C32/LS32 LS33 SENSE ±200mV ±500mV + _ 2 FUNCTION TABLE INPUT VOLT ±7V ±15V HDW-500 MMP2V2 IC 74LCX574MTCX (NS)FLAT PACKAGE 74LCX574SJX (NS)FLAT PACKAGE 74VHCT574MTCX (NS)FLAT PACKAGE SN74HC574ANS (TI)FLAT PACKAGE SN74HC574ANS-E05 TC74VHC574F (TOSHIBA)FLAT PACKAGE TC74VHC574FS (TOSHIBA)FLAT PACKAGE TC74VHC574FS(EL) AD1890JP (AD) C-MOS STEREO ASYNCHRONOUS SAMPLE RATE CONVERTER 7 VDD(+5V) 23 D2 IN 3 18 Q2 OUT D3 IN 4 17 Q3 OUT D4 IN 5 16 Q4 OUT 7 8 9 11 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 17 16 15 14 13 0 1 X HI-Z Q0 12 Q8 EN 1 D5 IN 6 15 Q5 OUT D6 IN 7 ; ; ; ; ; LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE NO CHANGE 14 Q6 OUT D7 IN 8 13 Q7 OUT D8 IN 9 12 Q8 OUT 10 GND 11 CK IN D1 Q1 D2 2 19 Q2 D3 3 18 Q3 D4 4 17 Q4 D5 5 16 Q5 D6 6 15 Q6 D7 7 14 Q7 D8 8 13 11 Q EN Q EN 11 1 NOTE; VDD +2 to +6V +2 to +5.5V +4.5 to +5.5V +2 to +3.6V +2.7 to +3.6V 19 PIN I/O No. SIGNAL PIN I/O No. 1 2 3 4 5 6 7 8 9 10 GPDLYS MCLK DATA I BCLK I WCLK I LR I VDD GND NC BKPOL I 11 12 13 14 15 16 17 18 19 20 I I I I I I — — — I SIGNAL VDD B 24 VDD B 23 A1 3 22 EN A2 4 21 B1 A3 5 20 B2 A4 6 19 B3 20 5 19 6 18 7 17 8 16 9 15 10 18 B4 A6 8 17 B5 A7 9 16 B6 A8 10 12 GND EN DIR 25 2 10 19 15 GPDLYS RESET SETLSLW BCLK I BCLK O MSBDLY I MSBDLY O TRGLR I TRGLR O WCLK I WCLK O MCLK BKPOL I BKPOL O MUTE I MUTE O 16 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; OUTPUT DATA O MUTE O ; SERIAL OUTPUT, MSB FIRST ; MUTE OUTPUT 6 24 BIT CLOCK INPUT FOR INPUT DATA BIT CLOCK INPUT FOR OUTPUT DATA BIT CLOCK POLARITY SERIAL INPUT, MSB FIRST GROUP DELAY-SHORT LEFT/RIGHT CLOCK INPUT FOR INPUT DATA LEFT/RIGHT CLOCK INPUT FOR OUTPUT DATA MASTER CLOCK INPUT MSB DELAY MUTE INPUT ACTIVE LOW RESET SETTLE SLOW TO CHANGES IN SAMPLE RATES TRIGGER ON LR WORD CLOCK INPUT FOR INPUT DATA WORD CLOCK INPUT FOR OUTPUT DATA CLOCK TRACKING MULTIPLEXER DATA I 3 SERIAL IN ACCUMULATOR SERIAL OUT 23 DATA O FIFO 14 CA3094M (HARRIS)FLAT PACKAGE EN 0 0 1 0 1 HI-Z X DIR OUTPUT 0 B TO A 1 A TO B X HI-Z ; ; ; ; PROGRAMMABLE POWER SWITCH/AMPLIFIER —TOP VIEW— EXT. FREQUENCY COMPENSATION 1 OR IN-HIBIT INPUT LOW LEVEL HIGH LEVEL HIGH IMPEDANCE DON'T CARE TYPE 74LVX3245 74LVX4245 GND 13 B1 5 LR O COEF ROM DIFFERENTIAL VOLTAGE INPUT 14 B8 21 — GND — VDD O DATA O I LR O I WCLK O I BCLK O — GND I SETLSLW LR I 22 2 15 B7 11 GND 18 23 EN DIR A5 7 11 SIGNAL INPUT BCLK I BCLK O BKPOL I, BKPOL O DATA I GPDLYS LR I LR O MCLK MSBDLY I, MSBDLY O MUTE I RESET SETLSLW TRGLR I, TRGLR O WCLK I WCLK O LR O 4 PIN I/O No. I TRGLR I 21 I MSBDLY I 22 I RESET 23 — GND 24 I MUTE I 25 O MUTE O 26 I MSBDLY O 27 I TRGLR O 28 I BKPOL O NC — —TOP VIEW— 1 VDD A 12 (VDD = +5V) C-MOS 8-BIT DUAL SUPPLY VOLTAGE TRANSLATING TRANSCEIVER DIR 2 26 17 LR I 74LVX4245QSCX (NS)FLAT PACKAGE 21 4 DATA O 12 D Q 3 28 DATA I Q8 9 D Q TYPE 74HC 74AC/74VHC 74ACT/74FCT 74HCT/74VHCT 74LCX 74LVC 13 18 6 D2 17 5 18 16 19 Q1 OUT Q1 15 4 D1 IN 2 D1 1 NC 20 14 GND 3 24 GND 21 13 VDD 20 6 VDD(+5V) 22 10 12 EN IN 1 EACH FLIP-FLOP INPUTS OUT EN CK D Q 0 1 1 0 0 0 0 X Q0 1 X HI-Z X 19 26 GND 27 1 28 24 9 NC 2 3 25 6 8 GND —TOP VIEW— EN 2 5 C-MOS 3-STATE D-TYPE EDGE-TRIGGERED FLIP-FLOP CK 3 4 —TOP VIEW— B2 20 B3 19 VDD A +5V +3V B4 18 VDD B +3V +5V B5 17 B6 B7 15 B8 14 + _ 3 4 16 8 2 V(_) OPERATION SINGLE SUPPLY DUAL SUPPLIES V(+) SHINK OUTPUT(COLLECTOR) 7 6 DRIVE OUTPUT(EMITTER) 5 CURRENT(PROGRAMMABLE INPUT) V(+) +24V +12V V(_) GND _12V 22 2 HDW-500 MMP2V2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 10 A8 2-9 IC AK5390-VS (ASAHI KASEI)FLAT PACKAGE AK5390-VS-E2 AD7528JN (ANALOG DEVICES) 18-BIT STEREO A-D CONVERTER —TOP VIEW— C-MOS 8-BIT D/A CONVERTER —TOP VIEW— 4 3 1 28 VREF+ OUT A GND 4 2 APD IN 2 27 VREF_ OUT 5 22 AINL+ IN 3 26 AINR+ IN AINL_ IN 4 25 AINR_ IN 26 25 10 VA_(_5V) 24 ACAL IN 5 11 12 14 7 VL+(+5V) 22 ICLK IN 13 16 NC 21 8 NC DCAL OUT 9 AINL+ AINL_ VREF+ APD VREF_ 28 27 ACAL OUT A 2 19 RFB B RFB A 3 18 VREF B VDD (+5 to +15 V) VREF A 4 5 DGND 17 16 13 WR D GND 18 SMODE IN 12 VD+(+5V) 17 L/R I/O 13 OUT A DB6 OUT B 2 20 14 DB4 RFB A DB3 RFB B 3 19 DB2 DB1 DB0 DPD SDATA 15 DAC A/DAC B 6 15 CS 6 DAC A/DAC B CMODE SMODE OCLK SCLK DCAL WR 20 14 DB0 (LSB) (MSB) DB7 7 9 L/R DB6 8 13 DB1 DB5 9 12 DB2 DB4 10 11 DB3 FSYNC DAC A/ DAC B 0 1 X X 16 FSYNC I/O SCLK I/O 14 DB7 DB5 10 AINR+ 19 CLK IN CMODE IN 11 9 12 20 OCLK OUT DPD IN 10 8 11 AINR_ 18 VREF A VREF B 7 ICLK 19 VA+(+5V) 23 6 L GND 20 OUT B 1 AGND 15 SDATA OUT CS WR DAC A DAC B 0 0 1 X 0 0 X 1 WRITE HOLD HOLD HOLD CS 16 15 INPUT ; DIGITAL DATA DB0 - DB7 DAC A/DAC B ; CONTROL INPUT ; CHIP SELECT CS ; WRITE WR VREFA, VREFB ; REFERENCE VOLTAGE ; FEEDBACK RESISTOR RFBA, RFBB OUTPUT OUT A, OUT B ; D/A HOLD WRITE HOLD HOLD 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON’T CARE 3 VREF A 4 INPUT ACAL ; ANALOG CALIBRATION (H : AGND) (L : ANALOG SIGNAL INPUT = AINL, AINR) AINL + ; CAHNNEL L ANALOG POSITIVE INPUT AINL _ ; CAHNNEL L ANALOG NEGATIVE INPUT AINR + ; CAHNNEL R ANALOG POSITIVE INPUT AINR _ ; CAHNNEL R ANALOG NEGATIVE INPUT ; POWER DOWN FOR ANALOG SECTION APD ; MASTER CLOCK CLK (CMODE = H : 384fs) (CMODE = L : 256fs) CMODE ; MASTER CLOCK SELECT (L : CLK = 256fs, 12.288 MHz @fs = 48 KHz) (H : CLK = 384fs, 18.432 MHz @fs = 48 KHz) ; POWER DOWN FOR DIGITAL SECTION DPD ; 128fs CLOCK ICLK SMODE ; INTERFACE CLOCK SELECT (L : SUB MODE) (H : MASTER MODE) OUTPUT ; DCAL ; OCLK SDATA ; VREF + ; VREF _ ; DB0 - DB7 7 - 14 8 DAC A/DAC B INPUT SUFFER 2 LATCH DAC A 6 15 CS 16 WR 19 CONTROL LOGIC 20 LATCH DAC B 18 VREF B RFB A OUT A RFB B OUT B 1 AGND DIGITAL CALIBRATION 128fs CLOCK SERIAL DATA REFERENCE POSITIVE VOLTAGE (+3.68 V) REFERENCE NEGATIVE VOLTAGE (_3.68 V) INPUT/OUTPUT FSYNC ; FRAME SYNC CLOCK ; INPUT CAHNNEL SELECT L/R (SUB MODE : fs CLK INPUT) (MASTER MODE : fs CLK OUTPUT) ; SERIAL DATA CLOCK SCLK (SUB MODE : 64fs CLK INPUT) (MASTER MODE : 64fs CLK OUTPUT) ANALOG BLOCK ICLK 2 28 VOLTAGE REFERENCE 27 AINL_ 3 4 + _ – _ + LP FILTER + _ ACAL VREF_ DIGITAL BLOCK DAC AINL+ VREF+ 22 5 DECIMATION FILTER APD 25 + _ 15 _ + LP FILTER + _ DPD CLK OCLK CMODE SMODE 10 19 16 DECIMATION FILTER AINR_ 26 13 SERIAL OUTPUT I/F DAC AINR+ 14 CONTROLLER 9 SCLK L/R FSYNC SDATA DCAL 20 11 12 2-10 CALIBRATION S-RAM HDW-500 MMP2V2 IC CXA1432M (SONY)FLAT PACKAGE CXA1432M-T4 CXD2306Q (SONY) CXD2306Q-T4 (SONY) VIDEO SIGNAL CLAMPER C-MOS 10-BIT 1CH D/A CONVERTER —TOP VIEW— IN 12 (+5V) 11 VEE PEDE SENS 10 9 V IN 24 2 8 3 FV IN 9 (_5V) 22 21 20 19 18 17 30 31 NC 16 32 V OUT 7 DGND 15 26 NC 27 DGND 14 NC 5 2 3 4 V E FV TP5 IN OUT IN CP IN E OUT FV IN PEDE SENS TP5, TP12 V IN V OUT V IN FV IN PEDE SENS CP IN NC 6 29 NC 10 1 E OUT 7 E. F V OUT D0 (LSB) CXA1451M (SONY)FLAT PACKAGE CXA1451M-TH D1 D2 D3 WIDEBAND VIDEO SWITCH —TOP VIEW— 2 1 VCC1 16 SW OUT (+4V to +6V) VCC2 (+4V to +6V) IN1 2 4 SW OUT IN2 OUT1 14 CONT1 IN2 4 IN1 15 6 3 GND 7 OUT2 3 16 13 11 I/O SIGNAL I I I I I I I — I I I — — O — — D3 D4 D5 D6 D7 D8 D9(MSB) NC CK BLK CE NC DVDD VB DGND NC 19 BLK CE VREF 4 5 6 7 SREF IREF 9 VB 8 18 VG 14 22 PIN No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O SIGNAL I O I — — O O O — — — — — I I I IREF SREF VREF AVDD AVDD VG IO IO AGND NC DGND DVDD NC D0(LSB) D1 D2 BLANKING PULSE INPUT CHIP ENABLE CLOCK INPUT DIGITAL DATA INPUTS CURRENT OUTPUT INVERT CURRENT OUTPUT IO IREF CURRENT REFERENCE INPUT SREF INDEPENDENT CONSTANT VOLTAGE OUTPUT VB, VG ; FOR CAPACITOR VREF ; VOLTAGE REFERENCE INPUT BLK CE CK D0 - 7 IO ; ; ; ; ; ; ; ; MAXIMUM CONVERSION RATE CXD2306Q CXD2315Q 75MSPS 80MSPS 30 31 1 2 3 D6 4 D7 5 D8 6 D9 7 24 4LSB'S CURRENT CELLS 32 D5 IO LATCHES DECODER DECODER 6MSB'S CURRENT CELLS CURRENT CELLS (FOR FULL SCALE) 10 23 22 19 – + 17 IO VG VREF IREF SWIN2 CLK GND 12 SWIN1 6 2 D4 BLK SWIN1 13 OUT1 5 GND 10 (AVDD, DVDD = +5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MODE SELECTOR 10 31 32 SAMPLE & HOLD _ 11 17 + + 30 11 2 3 8 D9 9 OUT E. F 9 D8 NC 12 V ; CLAMP PULSE INPUT ; BUFFER AMP OUTPUT ; FLOATING VIDEO SIGNAL INPUT ; CLAMP LEVEL DC INPUT ; CLAMP POINT SIGNAL INPUT ; FOR TEST ; VIDEO SIGNAL INPUT ; VIDEO SIGNAL OUTPUT 1 D7 6 7 7 NC 1 23 D6 5 (+5V) 24 D5 4 DVDD 13 (+5V) 28 DVDD IO D4 3 CP IN IO D1 D3 2 SENS 10 D0 D2 1 PEDE 8 23 25 AGND (+5V) 13 NC E OUT (+5V) TP12 14 VCC 1 AVDD CP AVDD —TOP VIEW— CONT1 CONT2 VB 14 10 CE 9 CLOCK GENERATOR BIAS VOLTAGE GENERATOR BAND GAP REFERENCE 18 SREF 14 11 11 OUT2 SWIN2 7 10 CONT2 EE1 8 V (_4V to _6V) VEE2 (_4V to _6V) 9 INPUT CONT1, 2 ; POWER SAVE CONTROL PIN OF DRV. 1 AND DRV. 2 INT1, 2 ; 1/2-CHANNEL INPUT PIN SWIN1, 2 ; IN1/IN2 PINS SWITCH CONTROL PIN OUTPUT OUT1, 2 ; OUTPUT PIN OF DRV. 1/2 SWOUT ; OUTPUTS IN1 PIN OR IN2 PIN WHICH HAS BEEN SELECTED BY SWITCH IN1 IN2 2 16 X2 4 DRV 13 14 SWIN1 SWIN2 6 7 + – DRV 11 10 HDW-500 MMP2V2 SW OUT OUT1 CONT1 OUT2 CONT2 2-11 IC CXD1095BQ (SONY) C-MOS I/O PORT EXPANDER 30 - 32, D0 - D7 35 - 39 8 (DATA BUS) 33 34 35 36 37 38 39 40 41 43 52 GND 42 44 45 46 47 48 49 50 51 —TOP VIEW— 8 8 LATCH 54-56, 8 59-63 PA0 - PA7 (PORT A) 32 53 31 54 30 55 29 56 28 8 8 LATCH 3 - 9, 8 64 PB0 - PB7 (PORT B) 8 27 57 GND 58 VDD VDD 26 (+5V) 59 GND 25 60 24 61 23 62 22 63 21 8 11 - 18 PC0 - PC7 (PORT C) 8 19 18 17 16 15 14 13 12 CLR DATA SELECT PA1 PA2 PA3 PA4 PA5 30 31 32 35 36 37 38 39 D0 PA6 D1 PA7 PB0 D4 PB1 D5 PB2 D6 PB3 D7 PB4 PB5 46 47 48 A0 A1 PB6 PB7 45 44 43 CS PC1 RD PC2 WR PC3 PC4 41 40 RST CLR PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PX0 PX1 PX2 PX3 2-12 PC6 PC7 NC PD0 PD1 PD2 PD3 PD4 GND VDD PD5 PD6 PD7 D0 D1 D2 I/O SIGNAL — — I/O I/O I/O I/O I/O I I — I I I I I I NC NC D3 D4 D5 D6 D7 CLR RST GND WR RD CS A0 A1 A2 PIN No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 A1 A0 0 0 1 0 0 0 PORT A → DATA BUS 0 0 1 0 0 1 PORT B → DATA BUS 0 0 1 0 1 0 PORT C → DATA BUS 0 0 1 0 1 1 PORT D → DATA BUS 62 0 0 1 1 0 0 PORT X → DATA BUS 63 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 DATA BUS → PORT A 59 60 61 64 3 4 CS RD WR A2 PIN No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 56 1 0 0 0 1 DATA BUS → PORT B 0 1 0 0 1 0 DATA BUS → PORT C 7 0 1 0 0 1 1 DATA BUS → PORT D 8 0 1 0 1 0 0 DATA BUS → PORT X 11 12 13 14 15 16 17 0 1 0 1 0 0 1 0 1 1 0 DATA BUS → CTL REG. 1 0 1 0 1 1 1 DATA BUS → CTL REG. 2 1 X X X X X DATA BUS ; HI-Z 0 1 X HI-Z ; ; ; ; LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE 20 22 23 24 27 28 29 49 50 52 53 PX0 PX1 NC PX2 PX3 PA0 PA1 PA2 GND VDD PA3 PA4 PA5 PA6 PA7 PB0 1 18 21 SIGNAL I/O I/O — I/O I/O I/O I/O I/O — — I/O I/O I/O I/O I/O I/O D0 - D7 CS RD WR A0 - A2 RST CLR PA0 - PA7 PB0 - PB7 PC0 - PC7 PD0 - PD7 PX0 - PX3 ; ; ; ; ; ; ; ; ; ; ; ; A2 A1 A0 WR RD CS RST 48 47 CONTROL 46 43 44 45 41 CXD8115Q (SONY) 0 9 I/O MODE 6 5 A2 PC0 SIGNAL I/O I/O — I/O I/O I/O I/O I/O — — I/O I/O I/O I/O I/O I/O 55 54 D2 D3 I/O DATA BUS INPUTS/OUTPUTS CHIP SELECT INPUT READ STROBE INPUT WRITE STROBE INPUT ADDRESS INPUT RESET INPUT CLEAR INPUT PORT A INPUTS/OUTPUTS PORT B INPUTS/OUTPUTS PORT C INPUTS/OUTPUTS PORT D INPUTS/OUTPUTS PORT X INPUTS/OUTPUTS C-MOS ADDRESS DECODER —TOP VIEW— CS23 42 34 34 35 36 37 38 39 40 41 42 43 44 GND PA0 PIN No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 GND VDD(+5V) VDD(+5V) GND GND NC NC PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND PC0 PC1 PC2 PC3 PC4 PC5 49, 50, 4 52, 53 PX0 - PX3 (PORT X) 40 33 32 31 30 29 28 27 26 25 24 23 SIGNAL — — I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O 4 LATCH 22 21 20 19 18 17 16 15 14 13 12 32 24 23 21 12 11 10 2 1 A15 CS22 A14 CS21 A13 CS20 A12 CS19 A11 CS18 A10 CS17 A9 CS16 A8 CS15 A7 CS14 A6 CS13 A5 CS12 A4 CS11 CS10 CS9 CS8 1 2 3 4 5 6 7 8 9 10 11 I/O 20 - 24, 8 27 - 29 PD0 - PD7 (PORT D) 4 (VDD = +5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8 LATCH 20 11 9 8 7 6 5 4 3 2 1 64 10 GND (+5V) 8 LATCH CS7 CS6 CS5 A4 - A15 ; ADDRESS INPUTS CS1 - CS23 ; DECODE DATA OUTPUTS CS4 CS3 CS2 CS1 41 40 37 36 35 31 30 29 27 26 25 20 19 18 15 14 13 9 8 7 5 4 3 (VDD = +5V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 I I O O O — O O O I I A4 A5 CS1 CS2 CS3 GND CS4 CS5 CS6 A6 A7 12 13 14 15 16 17 18 19 20 21 22 I O O O — — O O O I — A8 CS7 CS8 CS9 GND VDD CS10 CS11 CS12 A9 NC 23 24 25 26 27 28 29 30 31 32 33 I I O O O — O O O I I A10 A11 CS13 CS14 CS15 GND CS16 CS17 CS18 A12 A13 34 35 36 37 38 39 40 41 42 43 44 I O O O — — O O I — — A14 CS19 CS20 CS21 GND VDD CS22 CS23 A15 NC NC HDW-500 MMP2V2 IC CXD2308Q (SONY) 33 35 R2 R3 D GND 52 A GND A GND 40 R1 45 R0 —TOP VIEW— 51 50 C-MOS 10-BIT HIGH SPEED D/A CONVERTER R4 32 R5 R6 A VDD(+5V) A VDD(+5V) 55 3 R9 G0 G1 A VDD(+5V) A VDD(+5V) D VDD G2 46 4 6 DECODER G3 G4 19 15 10 5 1 G5 LATCHES G6 PIN I/O No. SIGNAL R0 (LSB) R1 R2 R3 R4 R5 R6 R7 R8 R9 G0 (LSB) 14 15 16 17 18 19 20 21 22 23 24 25 26 G1 G2 SIGNAL I I I I I I I I I I I I I PIN I/O No. SIGNAL 27 28 29 30 31 32 33 34 35 36 37 38 39 B6 B7 B8 B9 BLK CE RCK GCK BCK D GND VB A GND IRR G3 G4 G5 G6 G7 G8 G9 B0 (LSB) B1 B2 B3 B4 B5 I I I I I I I I I — I — I PIN I/O No. PIN SIGNAL No. I/O 40 41 42 43 44 45 46 47 48 49 50 51 52 IRG IRB VRR VRG VRB ROR VGR ROG VGG ROB VGB A GND RO I I I I I I I I I I I — O 53 54 55 56 57 58 59 60 61 62 63 64 SIGNAL G7 G8 O — — O O — — O O — — — RO A VDD A VDD GO GO A VDD A VDD BO BO A VDD A VDD D VDD G9 B0 B1 B2 B3 B4 B5 B6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 9 DECODER CURRENT CELLS 10 11 13 B7 R3 R4 RO R5 RO ROR VRR IRR 58 48 15 16 DECODER 56 LATCHES 57 A VDD A VDD VGG GO GO 17 34 47 18 19 DECODER CURRENT CELLS 20 21 43 _ + 40 55 4 LSB'S CURRENT CELLS 22 23 54 50 24 26 DECODER 60 6 MSB'S CURRENT CELLS 25 LATCHES 61 GCK ROG VRG IRG A VDD A VDD VGB BO BO 27 35 49 28 29 DECODER CURRENT CELLS 30 44 _ + 41 BCK ROB VRB IRB BIAS VOLTAGE GENERATOR 52 53 BLK CE 31 37 38 51 32 36 VB A GND A GND D GND G1 G2 G3 G4 GO G5 GO 56 CXD8117P (SONY) 57 G6 C-MOS DIAL DATA DECODER G7 —TOP VIEW— G8 G9 VDD 18 (+5V) 10 DIAL A B0 DATA 0 DATA 1 DATA 4 OUT 2 B1 17 DATA 2 OUT 11 DIAL B B2 DATA 2 DATA 3 DATA 5 OUT 3 B3 B4 BO B5 BO 16 DATA 1 OUT DATA 4 60 61 DATA 5 REV/FWD OUT 4 15 DATA 0 OUT 12 13 B6 5 GND B7 CK IN 6 ; ; ; ; ; ; ; ; ; ; ; ROB ROG ROR VB VGB VGG VGR VRB VRG VRR ; ; ; ; ; ; ; ; ; ; IRB VRB ROB BCK VB 37 41 44 49 35 VGB 50 VRG ROG IRG 40 43 47 34 GCK VGG IRR VRR Bch DIGITAL DATA Bch CLOCK BLANKING SIGNAL CHIP ENABLE Gch DIGITAL DATA Gch CLOCK CONNECT 1.2KZ TO A GND CONNECT 1.2KZ TO A GND CONNECT 1.2KZ TO A GND Rch DIGITAL DATA Rch CLOCK 48 39 31 INPUT B0 - B9 BCK BLK CE G0 - G9 GCK IRB IRG IRR R0 - R9 RCK ROR B9 OUTPUT AMPLITUDE CONTROL OUTPUT AMPLITUDE CONTROL OUTPUT AMPLITUDE CONTROL CONNECT CAPACITOR TO D GND CONNECT CAPACITOR CONNECT CAPACITOR CONNECT CAPACITOR SET FULL SCALE (2.0V) OF OUTPUT SET FULL SCALE (2.0V) OF OUTPUT SET FULL SCALE (2.0V) OF OUTPUT OUTPUT BO, BO ; Bch CURRENT OUTPUT GO, GO ; Gch CURRENT OUTPUT RO, RO ; Rch CURRENT OUTPUT CK1 OUT 7 12 DIAL STILL IN CK2 OUT 8 11 DIAL B IN RESTART IN 9 10 DIAL A IN 17 1 2 3 RESTART 6 CK1 CK2 4 7 8 15 DIAL A DIAL B EDGE DETECTOR 10 DIRECTION DETECTOR 11 FWD/REV DETECTOR (SHUTTLE) DIAL STILL JOG/ SHUTTLE RESTART CK CK1 CK2 HDW-500 MMP2V2 13 JOG/SHUTTLE IN 16 JOG/SHUTTLE REV/FWD 9 15 DIAL STILL GND 14 B8 BLK 30 RCK G0 42 29 RO R9 45 28 RO R8 RCK 27 VGR R7 VGR 26 A VDD R6 33 25 59 6 MSB'S CURRENT CELLS R2 46 24 39 14 R1 CE 23 A VDD R0 32 22 42 4 LSB'S CURRENT CELLS 12 DATA 3 OUT 1 21 45 _ + CLOCK GENERATOR B9 2 33 8 CLOCK GENERATOR B8 1 53 D VDD 7 (VDD = +5V) I I I I I I I I I I I I I 52 6 MSB'S CURRENT CELLS 5 20 (+5V) 1 2 3 4 5 6 7 8 9 10 11 12 13 62 25 60 PIN I/O No. 63 CLOCK GENERATOR R8 A VDD(+5V) A VDD(+5V) 64 4 LSB'S CURRENT CELLS 2 30 R7 64 1 12 STILL BUFFER 13 16 17 UP/DOWN COUNTER UP/DOWN GEN FWD/REV SELECTOR U/D 1 LATCH 2 3 4 DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 FWD/REV RESET GEN 9 6 7 CLOCK 8 2-13 IC CXD2202Q (SONY) SERVO IC —TOP VIEW— 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GND VDD (+5V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (VDD = +5V) GND PWMVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND VDD (+5V) GND 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 41 42 43 44 45 46 47 48 49 50 A15 D7 A14 D6 A13 D5 A6 D4 A5 D3 A4 D2 A3 D1 A2 D0 40 IOP7 A0 AS14 IOP5 AS13 IOP4 IOP3 98 99 100 6 7 8 1 2 FG12/IP27 IOP2 FG11/IP26 IOP1 FG10/IP25 IOP0 5 FG01/IP13 PWM7/OP37 FG00/IP12 PWM6/OP36 FG1/IP24 PWM5/OP35 FG0/IP23 PWM4/OP34 SYNC1/IP21 PWM2/OP32 SYNC0/IP20 PWM1/OP31 PWM0/OP30 3 10 12 13 CTL/IP11 PPG0E/OP16 LAT/IP10 PPG0D/OP15 UD/IP07 PPG0C/OP14 PPG0B/OP13 CCLK/IP06 PPG0A/OP12 14 15 16 17 18 19 61 62 60 70 87 54 55 56 58 21 24 25 26 PPG13/OP23 FGC1/IP05 FGC0/IP04 PPG12/OP22 FGB1/IP03 PPG11/OP21 FGB0/IP02 PPG10/OP20 FGA1/IP01 PPG09/OP11 FGA0/IP00 PPG08/OP10 MD1 PPG07/OP07 MD0 PPG06/OP06 RES PPG05/OP05 FXSEL PPG04/OP04 EXTAL PPG03/OP03 PPG02/OP02 PPG01/OP01 PPG00/OP00 OP26 EXCS1/OP25 EXCS0/OP24 IREQ2 IREQ1 IREQ0 CLKO XTAL WR 64 2-14 RD 65 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 I/O I/O I/O I/O I/O I/O I/O I/O — I I I — I I I O O O I O O O O O FGC0 ; FGC1 ; FXSEL LAT MD0, 1 PBH ; ; ; ; RD RES SYNC0, 1 UD WR ; ; ; ; ; ; ; ; ; ; ; CLOCK OUTPUT DECODE AT ADDRESS A3 LEVEL INTERRUPTION SIGNAL OF FRC CAPTURE UNIT COINCIDENCE INTERRUPTION OF PPG0 COINCIDENCE INTERRUPTION OF PPG1 EXCLUSIVELY OUTPUT PORT 77 91 IOP2 IOP1 IOP0 PWM VDD PWM7/OP37 PWM6/OP36 PWM5/OP35 PWM4/OP34 PWM3/OP33 PWM2/OP32 PWM1/OP31 PWM0/OP30 GND AS14 AS13 A15 A14 A13 A6 A5 A4 A3 A2 A1 A0 ; 82 90 I/O I/O I/O — O O O O O O O O — I I I I I I I I I I I I FGB1 81 85 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ; 79 84 FG1/IP24 FG0/IP23 PBH/IP22 SYNC1/IP21 SYNC0/IP20 FG02/IP14 FG01/IP13 FG00/IP12 CTL/IP11 LAT/IP10 VDD UD/IP07 CCLK/IP06 FGC1/IP05 FGC0/IP04 FGB1/IP03 FGB0/IP02 FGA1/IP01 FGA0/IP00 GND IOP7 IOP6 IOP5 IOP4 IOP3 FGB0 37 76 I I I I I I I I I I — I I I I I I I I — I/O I/O I/O I/O I/O ; 35 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FGA1 33 74 I/O ; ; ; ; 32 83 PIN No. FG1 FG10 FG11, FG12 FGA0 31 80 SIGNAL ; ; ; 30 78 I/O EXTAL FG0 FG00 - FG02 28 36 PIN No. ADDRSSS BUS SELECTING CONDITION OF ADDRESS DECODER AS13 AND AS14 BITS 8-BIT COUNTER CLOCK INPUT CHIP ENABLE RESOLUTION 2.5MHz WITH EDGE SELECT FUNCTION. WITH FREQUENCY DIVISION MASK TIMER CRYSTAL OSCILLATION OR EXTERNAL CLOCK INPUT RESOLUTON 2.5MHz FREQUENCY DIVISION ENABLE RESOLUTION 2.5MHz. WITH FREQUENCY DIVISION MASK TIMER RESOLUTION 2.5MHz BOTH EDGES EDGE SELECTION ENABLE RESOLUTION 10MHz FREQUENCY DIVISION ENABLE RESOLUTION 10MHz PERFORMS FORWARD/REVERSE ROTATION DETECTION AND 4FG COUNT (UP/DOWN) BY FGA0 AND FGA1. 10BITS. UP/DOWN IS MADE BY CONTROLLING THE UP/DOWN OF 8-BIT COUNTER. 4FG PERFORMS FREQUENCY DIVISION AND FRC CAPTURE THROUGH MASK TIMER. *1 : SELECTS ONE OF FGA0 TO FGC1 INPUT AND DETECTS BOTH EDGES AND PERFORM THE FRC CAPTURE THROUGH THE MASK TIMER. PERFORMS FORWARD/REVERSE ROTATION DETECTION AND 4FG COUNT BY FGB0 AND FGB1. *1 : SELECTS ONE OF FGA0 TO FGC1 INPUT AND DETECTS BOTH EDGES AND PERFORM THE FRC CAPTURE THROUGH THE MASK TIMER. PERFORMS FORWARD/REVERSE ROTATION DETECTION AND 4FG COUNT BY FGC0 AND FGC1. *1 : SELECTS ONE OF FGA0 TO FGC1 INPUT AND DETECTS BOTH EDGES AND PERFORM THE FRC CAPTURE THROUGH THE MASK TIMER. FREQUENCY DIVISION SELECTION CLOCK INPUT EXTERNAL LATCH TIMING OF UP/DOWN COUNTER TEST MODE DESIGNATION INPUT OF COMPOSITE SYNC OR H SYNC. RESOLUTION 10MHz. WITH HALF H KILLER. REDE RESET INPUT OF COMPOSITE SYNC OR V SYNC. RESOLUTION 2.5MHz 8-BIT COUNTER UP/ DOWN INPUT WRITE 27 34 SIGNAL ; ; ; ; ; 22 23 I/O INPUT A0 - A15 AS13, AS14 CCLK CE CTL 57 PBH/IP22 PPG0F/OP17 9 53 FG02/IP14 PWM3/OP33 4 52 A1 IOP6 39 51 PIN No. PIN No. I/O SIGNAL D7 76 D6 77 D5 78 D4 79 D3 80 D2 81 D1 82 D0 83 GND 84 RES 85 MD1 86 MD0 87 VDD 88 WR 89 RD 90 CE 91 IREQ2 92 IREQ1 93 IREQ0 94 FXSEL 95 OP26 96 EXCS1/OP25 97 EXCS0/OP24 98 PPG13/OP23 99 PPG12/OP22 100 O O O O O O O O O O O I O — O O O O O O O O I I I PPG11/OP21 PPG10/OP20 PPG0F/OP17 PPG0E/OP16 PPG0D/OP15 PPG0C/OP14 PPG0B/OP13 PPG0A/OP12 PPG09/OP11 PPG08/OP10 CLKO EXTAL XTAL GND PPG07/OP07 PPG06/OP06 PPG05/OP05 PPG04/OP04 PPG03/OP03 PPG02/OP02 PPG01/OP01 PPG00/OP00 FG12/IP27 FG11/IP26 FG10/IP25 SIGNAL 92 93 94 95 96 97 71 72 OUTPUT CLKO EXCS0, 1 IREQ0 IREQ1 IREQ2 OP26 PPG00 - PPG0F PPG10 - PPG13 73 PWM0 - PWM5 67 68 69 86 88 PWM6, 7 XTAL ; PROGRAMMABLE PULSE GENERATOR RESOLUTION 1.25MHz PPG00 : WITH HLOCK ; PWM OUTPUT NORMALLY PWM, OR PWM0 AND PWM1, PWM2 AND PWM3, OR PWM4 AND PWM5 OUTPUT SIGNAL CORRESPONDED TO PUSH-PULL. ; PWM OUTPUT ; CRYSTAL OSCILLATION INPUT/OUTPUT D0 - D7 ; DATA BUS IOP0 - IOP7 ; SELECTS AND USES INPUT AND OUTPUT BY EVERY 1 BIT. CE 66 HDW-500 MMP2V2 IC 67 - 69 FG10 / IP25 FG11 / IP26 FG12 / IP27 FG00 / IP12 FG01 / IP13 FG02 / IP14 99 98 8 7 6 IREQ2 - IREQ0 1/N 100 FIFO 14-BIT *14 1/N 51 - 58 16-BIT *14 1/N 1/N 1/N MASK TIM 1/N MASK TIM 41 - 50 39, 40 ADDRESS DECORD MASK TIM 64 65 LATCH 66 D7 - D0 A15 - A13, A6 - A0 AS14, 13 WR RD CE LATCH FG0 / IP23 FG1 / IP24 SYNC0 / IP20 2 1 5 LATCH VSEP FRM LATCH SYNC1 / IP21 PBH / IP22 4 VSEP FRM 3 FRC 19-BIT HALF H KILL 1/N COMPARE CTL / IP11 9 1/N SELECT SELECT UD / IP07 CCLK / IP06 FGA1 / IP01 FGB0 / IP02 FGB1 / IP03 FGC0 / IP04 FGC1 / IP05 LAT / IP10 HDW-500 MMP2V2 1/N 12 8-BIT U/D COUNT 13 FGA0 / IP00 MASK TIM LATCH F/R 4FG 10-BIT U/D COUNT LATCH F/R 4FG 10-BIT U/D COUNT LATCH F/R 4FG 10-BIT U/D COUNT LATCH 17 16 15 14 16-BIT *9 MASK TIM 78 - 85, 90 - 97 COMPARE H-LOCK 97 PPGOF-OO / OP17 - 00 V-SWITCHING PULSE LATCH PULSE FIFO 16-BIT *2 19 18 MASK TIM FIFO 16-BIT *9 8-BIT *2 PWM 74 - 77 30 - 37 PPG10 - 13 / OP23 - 20 PWM7 - 0 / OP37 - 30 10 2-15 IC CXD8110K (SONY) C-MOS SERIAL INTERFACE TRANSMITTER FOR NTSC/PAL 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 —TOP VIEW— DSP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 — O O O I I I I I I I I I I I I I SIGNAL GND DIE ENMOD0 ENMOD1 AUX4 AUX5 AUX6 AUX7 AUX8 DBN7 DBN6 DBN5 DBN4 DBN3 DBN2 DBN1 DBN0 PIN NO. I/O 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 — — I I I I I I I I I I O O O O O SIGNAL PIN NO. I/O 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 — I I I I I I I I I I I I I I I I VDD GND 4 fsc *VAREN VID9 VID8 VID7 VID6 VID5 SYNC DSP DIP MD9 MD8 MD7 MD6 MD5 SIGNAL GND VID4 VID3 VID2 VID1 VID0 CF2 CF1 CF0 SPADJ2 SPADJ1 SPADJ0 *ENM1 *ENM0 *SWCH *EXCH *RESET AUDM0 VID0 - VID9 59 22 - 26, 36 - 40 10 40 39 38 37 36 26 25 24 23 22 10 11 12 13 14 15 16 17 61 62 63 64 5 6 7 8 9 59 VID0 MD0 VID1 MD1 VID2 MD2 VID3 MD3 VID4 MD4 VID5 MD5 VID6 MD6 VID7 MD7 VID8 MD8 VID9 MD9 57 56 55 54 34 33 32 31 30 DBN0 DBN1 DBN2 DBN3 DBN4 DBN5 PIN NO. I/O 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 — — O O O O O I I I I I I I O O O SYNC SIGNAL 4 fsc VDD GND MD4 MD3 MD2 MD1 MD0 AUDMD HPLN AUX0 AUX1 AUX2 AUX3 *OEPOLSEL ERROR VPULSE ITRSTMG 41 - 43 INPUT 4 fsc AUDMD AUX0 - AUX8 CF0 - CF2 DBN0 - DBN7 DIP DSP HPLN SPADJ0 - SPADJ2 SYNC VID0 - VID9 : : : : : : : : : : : SYSTEM CLOCK AUDIO MODE (SET TO HIGH) AUXILIARY DATA COLOR FRAMING PULSE DATA BLOCK NO. FOR AUDIO MODE DATA DATA INSERT PULSE DATA START PULSE NTSC/PAL SELECT (NTSC: LOW/PAL: HIGH) SYNC PHASE ADJUST COMPOSITE SYNC COMPOSITE DIGITAL VIDEO DATA ENM0 - ENM1 SWCH EXCH RESET OEPOLSEL VAREN : : : : : : USED FOR DEVICE TEST USED FOR DEVICE TEST USED FOR DEVICE TEST USED FOR DEVICE TEST USED FOR DEVICE TEST USED FOR DEVICE TEST OUTPUT DIE ENMOD0, ENMOD1 ERROR ITRS TMG MD0 - MD9 VPULSE : : : : : : DATA INSERT ENABLE ENABLE MODE ERROR FLAG INPUT TRS TIMING MIXED DATA V PULSE (INDICATES THE FIELD START POINT) 29 43 42 41 27 60 44 45 46 2 2 ENABLE MODE GEN 3, 4 67 V & THE 1st LINE DET TRS TIMING & ID GEN 68 DIE ENMOD0, ENMOD1 V PULSE ITRSTMG 20 INPUT TIMING DIAGRAM AUDIO MODE ONLY A D D D D I B F D N C UD C A D D D D I B F D N C UD S DSP DIP OTHER AUX. MODE C S DSP DIP SWITCING CHARACTERISTICS INPUT OUTPUT TIMING 4 fsc SET UP TIME TO 4 fsc HOLD TIME INPUT VIDEO DATA 4 fsc TO OUTPUT DBN6 DBN7 AUX0 AUX1 AUX2 AUX3 AUX4 OUTPUT MIXED DATA PREVIOUS DATA VALID DATA VALID SET UP TIME TO 4 fsc HOLD TIME 4 fsc TO OUTPUT 0 ns 10 ns 13 ns AUX5 AUX6 CLOCK WAVEFORMS AUX7 AUX8 4 fsc AUDMD MIN CLOCK HIGH DSP DIP ERROR CF2 DIE CF1 ENMOD0 CF0 SYNC ENMOD1 VPULSE ITRSTMG 20 MD0 - MD9 10 3 27 MIN CLOCK LOW 28 30 - 34, 54 - 58 DATA MIX (INSERT) TRS & ID ADD DATA INSERT ENABLE GEN * : USED FOR DEVICE TEST 58 CS GEN & CS ADD ADF ADD CF0 - CF2 I/O DBN ADD ADF & DID ADD 5 - 9, 61 - 64 9 (VDD = +5 V) PIN NO. ERROR 10 - 17 8 AUX0 - AUX8 66 DATA TNSERT TIMING GEN TIMING ERROR DET TRS SW GND DBN0 - DBN7 28 29 ID DATA GND GND VDD (+5 V) VDD (+5 V) GND 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DIP 66 2 3 MIN CLOCK LOW MIN CLOCK HIGH 20 ns 20 ns 4 67 68 4 fsc HPLN SPADJ2 SPADJ1 SPADJ0 2-16 HDW-500 MMP2V2 IC CXD8176AQ (SONY) CXD8845Q (SONY) C-MOS D1 SUPERIMPOSER —TOP VIEW— —TOP VIEW— 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 36 35 34 33 32 31 30 29 28 27 26 25 C-MOS DUAL PORT RAM CONTROLLER 2 NC NC 38 39 40 41 42 43 44 45 46 47 48 I/O SIGNAL I/O I I O I I — — I I I — I I I I I I I I DOL WRL RDL WAITL CSL CKL NC NC A10R A9R A8R GND A7R A6R A5R A4R A3R A2R A1R A0R INPUT A0L - A10L A0R - A10R CKL CKR CKT CSL CSR RDL RDR WRL WRR PIN NO. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O SIGNAL I/O I/O I/O I/O I/O I/O I/O I/O I I O I — — I I O O O I/O D7R D6R D5R D4R D3R D2R D1R D0R WRR RDR WAITR CSR GND VDD CKR CKT WEM OEM CEM D7M PIN NO. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O SIGNAL I/O I/O I/O I/O I/O — I/O I/O O O O O — O O O O O O O D6M D5M D4M D3M D2M VDD D1M D0M A0M A1M A2M A3M GND A4M A5M A6M A7M A8M A9M A10M 73 ; ; ; ; ; ; ; ; ; ; ; ADDRESS BUS OF PORT L ADDRESS BUS OF PORT R CLOCK OF PORT L CLOCK OF PORT R CLOCK CHIP SELECT OF PORT L CHIP SELECT OF PORT R READ STROBE OF PORT L READ STROBE OF PORT R WRITE STROBE OF PORT L WRITE STROBE OF PORT R 70 69 68 67 66 65 64 63 62 61 1 OUTPUT A0M - A10M CEM OEM WAITL WAITR WEM 80 ; ; ; ; ; ; ADDRESS BUS FOR MEMORY DEVICE CHIP ENABLE FOR MEMORY DEVICE OUTPUT ENABLE FOR MEMORY DEVICE WAIT OF PORT L WAIT OF PORT R WRITE ENABLE FOR MEMORY DEVICE INPUT/OUTPUT D0L - D7L ; DATA BUS OF PORT L D0M - D7M ; DATA BUS FOR MEMORY DEVICE D0R - D7R ; DATA BUS OF PORT R 79 78 77 76 75 74 2 3 4 5 6 36 PIN NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SIGNAL I I I I I I I I I I — — I I/O I/O I/O I/O I/O I/O I/O A10L A9L A8L A7L A6L A5L A4L A3L A2L A1L GND VDD A0L D7L D6L D5L D4L D3L D2L D1L A0R A1R A2L A2R A3L A3R A4L A4R A5L A5R A6L A6R A7L A7R A8L A8R A9L A9R A10L A10R D0L D0R D1L D1R D2L D2R D3L D3R D4L D4R D5L D5R D6L D6R D7L D7R WAITL WRR RDR WAITR CSL CSR CKL CKR 47 45 44 43 42 41 40 D0M A1M D1M A2M D2M A3M D3M A4M D4M A5M D5M A6M D6M A7M D7M A8M A9M A10M CEM OEM WEM GND 8 9 10 11 12 1 17 20 21 47 20 19 18 17 16 15 14 13 11 10 PIN No. I/O SIGNAL PIN No. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I I I I I — I I I I I I I I I I I — — I I O O O SLNP VD 9 VD 8 VD 7 VD 6 GND VD 5 VD 4 VD 3 VD 2 VD 1 VD 0 Y BLK 4 Y BLK 5 Y BLK 6 Y BLK 7 CK 27 GND VDD OC 13 OC 6 GP422 SIVD 0 SIVD 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 O O O O I I — I O O O O O O O O O — — I I I I I SIVD 2 SIVD 3 SIVD 4 SIVD 5 Y WHITE 6 Y WHITE 7 GND Y WHITE 8 SIVD 6 SIVD 7 SIVD 8 SIVD 9 SEL A SEL B C FRAME Y FRAME Y CHARA GND VDD CFR DLY Y DLY A Y DLY B FRAME CHARA SIVD 8 VD 7 SIVD 7 VD 6 SIVD 6 VD 5 SIVD 5 VD 4 SIVD 4 VD 3 SIVD 3 VD 2 SIVD 2 VD 1 SIVD 1 VD 0 SIVD 0 SLNP GP422 CK 27 SEL A OC 13 SEL B 32 30 29 16 15 14 13 44 45 46 36 35 34 33 28 27 26 25 24 23 22 37 38 OC 6 FRAME Y FRAME CHARA Y CHARA 39 40 41 Y WHITE 8 Y WHITE 7 Y WHITE 6 Y BLK 7 Y BLK 6 Y BLK 5 Y BLK 4 CFR DLY Y DLY A Y DLY B INPUT CFR DLY CHARA CK 27 FRAME SLNP VD 0 - 9 Y BLK 4 - 7 Y DLY A, B Y WHITE 6 - 8 ; ; ; ; ; ; ; ; ; DELAY CONTROL OF C FRAME SIGNAL SUPERIMPOSE CHARACTER SIGNAL 27 MHz CLOCK SUPER IMPOSE CHARACTER FRAME 525/625 LINE SELECTE DIGITAL VIDEO PARALLEL DATA Y BLANKING LEVEL DELAY CONTROL OF Y CHARA AND Y FRAME SIGNALS Y WHITE LEVEL OUTPUT C FRAME GP422 OC 13 OC 6 SEL A, B SIVD 0 - 9 Y CHARA Y FRAME ; ; ; ; ; ; ; ; CHROMA FRAME PULSE 4 : 2 : 2 GROUP PULSE 13.5 MHz CLOCK 6.75 MHz CLOCK SELECTION SIGNAL OF INNER MULTIPLEXER DIGITAL VIDEO PARALLEL DATA AFTER SUPERIMPOSED Y CHARACTER PULSE Y FRAME PULSE 9 28 27 26 25 24 23 22 21 29 30 31 32 SEL A B 0 0 1 0 0 1 1 1 MPX THROUGH Y BLK C BLK Y WHITE 35 49 MULTIPLEXER 50 51 VD 0 - 9 52 55 13 - 16 Y BLK 4 - 7 56 57 12 - 7, 5 - 2 / 10 LATCH / 10 THROUGH Y BLK / 10 LATCH 23 - 28, 33 - 36 / SIVD 0 - 9 10 C BLK 54 Y WHITE 6 - 8 29, 30, 32 58 / 4 Y WHITE A B 37 / 3 LATCH 38 SEL A SEL B 59 60 39 38 SLNP 37 CK 27 OC 13 OC 6 FRAME CHARA CFR DLY Y DLY A Y DLY B HDW-500 MMP2V2 7 SIVD 9 VD 8 CKT A0M 48 5 48 I/O A1L RDL VDD(+5V) GND (VDD = +5V) A0L WRL GND VDD(+5V) 24 23 22 21 20 19 18 17 16 15 14 13 VD 9 C FRAME (VDD = +5V) PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND 37 4 1 2 3 4 5 6 7 8 9 10 11 12 GND VDD(+5V) GND GND GND VDD(+5V) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VDD(+5V) 3 MULTIPLEX CONTROL 1 17 39 20 21 47 48 TIMING GEN. 40 41 22 C FRAME Y FRAME Y CHARA GP422 44 45 46 2-17 IC CXD8277Q (SONY) C-MOS DIGITAL AUDIO (AES/EBU) ENCODER 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 —TOP VIEW— 6 GND 7 VDD(+5V) VDD(+5V) NC GND 52 53 54 55 56 57 58 59 60 61 62 63 64 8 32 31 30 29 28 27 26 25 24 23 22 21 20 9 13 14 15 16 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 25 27 (VDD = +5V) PIN No. I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I I I I I I I I I — I I I I I I SIGNAL PIN No. I/O BIPHCLK LRPOLL LRCKO BCKPOLL BCKO TDATAI VIN UIN CIN GND TxBLKID BLKIDSEL DTMODE0 DTMODE1 DTMODE2 DTMODE3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 O O — I I I I I I — I I I I I I SIGNAL PIN No. I/O MONIT4 MONIT5 NC AD0 AD1 AD2 AD3 AD4 AD5 VDD DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I I I I I I I I I — I I I I I I 28 29 SIGNAL PIN No. I/O SIGNAL DATA6 DATA7 WR CS CPU AUTO TBITLN0 TBITLN1 TBITLN2 TMONO GND TEMP0A TEMP1A TEMP2A TEMP0B TEMP1B TEMP2B 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I I I I I I I O O — I I I I O O TFSID0 TFSID1 TFSID2 RESET CSEL TEST0 TEST1 MONIT2 MONIT3 VDD TEST5 TEST2 TEST3 POS MONIT1 TxDATA 30 31 32 33 34 53 36 35 11 12 37 38 39 40 41 43 44 45 46 47 48 49 50 51 62 54 55 60 61 59 1 3 5 4 2 52 2-18 INPUT AD0 - AD5 TDATAI VIN UIN CIN DTMODE0 DTMODE1 DTMODE2 DTMODE3 AD0 AD1 AD2 AD3 AD4 AD5 TXDATA 64 DATA0 DATA1 DATA2 DATA3 DATA4 MONIT1 63 MONIT2 56 DATA6 MONIT3 57 MONIT4 17 DATA7 MONIT5 18 DATA5 CSEL CS WR TXBLKID BLKIDSEL CPU AUTO TBITLN0 TBITLN1 TBITLN2 TMON0 TEMP0A TEMP1A TEMP2A ; ADDRESS BUS FOR WRITING CHANNEL STATUS DATA FROM EXTERNAL CPU TO CHANNEL STATUS RESISTER BCKO ; BIT CLOCK (64Fs, 32Fs) FOR TDATAI BCKPOLL ; POLARITY SWITCHING OF BCKO (PIN No.5) BIPHCLK ; 128Fs FOR DO OUTPUT BLKIDSEL ; BLOCK ID EXTERNAL/INTERNAL SELECTION ("H" : INTERNAL MODE) CIN ; SERIAL INPUT OF EACH SUB FRAME CHANNEL STATUS CPU AUTO ; SWITCHING SIGNAL OF CPU AND AUTO MODE ("H" : AUTO MODE) CS ; CHIP SELECT SIGNAL FROM EXTERNAL CPU TO CHANNEL STATUS RESISTER ("L" : SELECT, "H" : UNSELECT) CSEL ; SELECTS THE USE OF CIN (EXTERNAL INPUT) OR INTERNAL RESISTER FOR CHANNEL STATUS DATA. ("H" : INTERNAL RESISTER) DATA0 - DATA7 ; DATA BUS FOR WRITING CHANNEL STATUS DATA FROM EXTERNAL CPU TO CHANNEL STATUS RESISTER DTMODE0 - 3 ; DECISION OF DIGITAL AUDIO SIGNAL INPUT FORMAT LRCKO ; L/R CLOCK FOR DIGITAL AUDIO SIGNAL OUTPUT LRPOLL ; POLARITY SWITCHING OF LRCKO (PIN No.3) POS ; FORCIBLY SETS PREAMBLE TO BE POSITIVE POLARITY ("H" : ACTIVE) RESET ; SETS TxDATA OUTPUT (AUDIO DATA, AND VALIDITY BIT, USER DATA AND CHANNEL STATUS DATA) TO BE "0". ("L" : ACTIVE) TBITLN0 - 2 ; SUBFRAME A/B CHANNEL STATUS SETTING (DATA BIT LENGTH) TDATAI ; DIGITAL AUDIO SIGNAL INPUT TEMP0A - 2A ; SUBFRAME A EMP INFORMATION TEMP0B - 2B ; SUBFRAME B EMP INFORMATION TEST0 ; TEST RESET (CONNECTION TO GND) TEST1 ; TEST RESET (CONNECTION TO GND) TEST2 ; TEST TEST3 ; TEST TEST5 ; CONTROL SIGNAL OF MONIT1 TO 5 TFSID0 - 2 ; SUBFRAME A/B Fs INFORMATION TMONO ; SUBFRAME A/B CHANNEL STATUS SETTING (MONOPHONIC/TWO CHANNEL MODE) TxBLKID ; EXTERNAL BLOCK ID SIGNAL UNI ; SERIAL INPUT OF EACH SUB FRAME USER DATA VIN ; SERIAL INPUT OF EACH SUB FRAME VALIDITY BIT WR ; CHANNEL STATUS DATA WRITING FROM EXTERNAL CPU TO CHANNELSTATUS RESISTER TEMP0B TEMP1B TEMP2B TFSID0 OUTPUT MONIT1 - 5 TxDATA ; MONITOR ; AES/EBU FORMAT DIGITAL AUDIO OUTPUT TFSID1 TFSID2 POS TEST0 TEST1 TEST2 TEST3 TEST5 BIPHCLK LRCKO BCKO BCKPOLL LRPOLL RESET HDW-500 MMP2V2 IC LRCKO LRPOLL BCKO BCKPOLL BIPHCLK TDATAI DTMODE3 DTMODE2 DTMODE1 DTMODE0 VIN UIN CIN CSEL TEST0 AD0 AD1 AD2 AD3 AD4 AD5 CS WR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 BLKIDSEL TEMP2A TEMP1A TEMP0A TEMP2B TEMP1B TEMP0B TFSID2 TFSID1 TFSID0 TMONO TBDTLN2 TBDTLN1 TBDTLN0 CPU AUTO TXBLKID TEST1 TEST2 TEST3 POS 3 2 5 4 1 17 MONIT4 6 16 15 14 13 7 FORMAT CONVERT INPUT SHIFT REGISTER 8 9 53 54 20 21 22 23 24 25 36 35 27 28 CRC GENERATOR 29 30 57 31 32 18 33 HDW-500 MMP2V2 MONIT5 34 12 45 44 48 BYTES CHANNEL STATUS REGISTER 43 48 47 46 51 50 49 41 40 39 38 37 11 55 60 EVEN PARITY GENERATOR PREAMBLE ADDER BI-PHASE MARK MODULATOR 64 63 TXDATA MONIT1 61 62 56 TEST5 MONIT3 MONIT2 59 2-19 IC CXD8278AQ (SONY) C-MOS DIGITAL AUDIO SIGNAL (AES/EBU) DECODER VDD(+5V) GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 —TOP VIEW— 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND VDD(+5V) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND GND VDD(+5V) GND VDD(+5V) GND 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 48 49 50 51 I/O SIGNAL NOSGNL O UNLOCK O O SYNCERR RXDATA I CLKIN I GND — CLKOUT O GND — O FMASTER PLLSEL I O PLLVAR GND — VDD — PLLREF O I/O LOCKPH0 I/O LOCKPH1 I/O LOCKPH2 I/O LOCKPH3 I/O LOCKPH4 I/O LOCKPH5 PIN NO. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DTMODE0 CONT DTMODE1 VOUT DTMODE2 UOUT DTMODE3 RDATA ERROR 74 70 71 63 60 64 61 23 9 5 7 4 10 59 11 14 MUTE0 SLIP0 MUTE1 SLIP1 LRCKI NOSGNL BCKI UNLOCK 15 16 17 18 19 20 BCKPOL PE1 FM12 TS4 VE1A F128 TS2 VE1B FMASTER VE3A CLKIN VE3B CLKOUT SYNCERR RXDATA CRCA PLLSEL CRCB RXBCK CSAVLDTY PLLVAR CSBVLDTY 26 27 28 29 30 41 42 44 58 57 46 47 1 2 79 80 77 78 75 76 3 68 69 SIGNAL FM12 TS4 FIXDPLLZ F128 TS2 TST3 AD0 CON AD1 NOA AD2 FS0 AD3 FS1 AD4 FS2 AD5 E0A D0 E1A VDD GND D1 E2A D2 E0B D3 E1B D4 E2B D5 MON D6 LN0 D7 LN1 PIN NO. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O SIGNAL I/O RD LN2 I CS O INT I CPU AUTO I TST1 O SLIP0 O SLIP1 I DTMODE0 I DTMODE1 I DTMODE2 I DTMODE3 — GND — VDD COUT O UOUT O VOUT O ERROR O RDATA O RXBCK O BCKI I PIN NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O SIGNAL I O I I O O O O O I I — — I O O O O O O BCKPOL RXLR LRCKI LRPOL RXBLKID CSAVLDTY CSBVLDTY CRCA CRCB MUTE0 MUTE1 VDD GND MUTEON VE3A VE3B VE1A VE1B PE1 PE3 CS DTMODE0-3 LRCKI LRPOL MUTE0, 1 MUTEON PLLSEL RXDATA TST1 TST3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; REFERENCE BIT CLOCK (64/32Fs) POLARITY SWITCHING SIGNAL OF BCKI (PIN NO.60) AND RXBCK (PIN NO.59) MASTER CLOCK OSCILLATOR INPUT AT DIGITAL PLL SELECTS CPU INTERFACE OR AUTO INTERFACE. ("H" : AUTO INTERFACE, "L" : CPU INTERFACE) CHIP SELECT SIGNAL (INPUT FOR CHANNEL STATUS REGISTER) ("L" : SELECT) OUTPUT FORMAT SPECIFYING CODE OF RDATA SIGNAL (PIN NO.58) REFERENCE L/R CLOCK INPUT (Fs PERIOD) POLARITY SWITCHING SIGNAL OF LRCKI (PIN NO.63) AND RXLR (PIN NO.62) RDATA (PIN NO.58) MUTE PERIOD SETTING CODE "L" : AUDIO OUTPUT BE FORCIBLY MUTE ON FOR A CERTAIN PERIOD "L" : ANALOG PLL. "H" : DIGITAL PLL AES/EBU INPUT TEST INPUT (NORMALLY FIXED TO "L") TEST PIN (FIXED TO "L") OUTPUT ; MASTER CLOCK OSCILLATOR OUTPUT AT DIGITAL PLL CLKOUT ; C BIT STATUS SIGNAL EXTRACTED FROM AES/EBU INPUT SIGNAL. COUT CRCA, CRCB ; OUTPUTS THE RESULT OF CHANNEL STATUS CRC CHECK OF SUBFRAME A AND B AT ERROR OCCURRING CSAVLDTY, ; SUBFRAME A AND B CHANNEL STATUS CSBVLDTY ; SUBFRAME A CHANNEL STATUS (CPU AUTO : "H") D0 E1A ; SUBFRAME A CHANNEL STATUS (CPU AUTO : "H") D1 E2A ; SUBFRAME B CHANNEL STATUS (CPU AUTO : "H") D2 E0B ; SUBFRAME B CHANNEL STATUS (CPU AUTO : "H") D3 E1B ; SUBFRAME B CHANNEL STATUS (CPU AUTO : "H") D4 E2B ; SUBFRAME A CHANNEL STATUS (CPU AUTO : "H") D5 MON ; SUBFRAME A/B CHANNEL STATUS (CPU AUTO : "H") D6 LN0 ; SUBFRAME A/B CHANNEL STATUS (CPU AUTO : "H") D7 LN1 ; ERROR INFORMATION OUTPUT (PARITY, SLIP ERROR , etc. ) IN SERIAL ERROR ; MASTER CLOCK OUTPUT FMASTER ; INTERRUPTION SIGNAL OUTPUT INT ; NO SIGNAL DETECTION NOSGNL ; PARITY ERROR DETECTION OUTPUT (1 SUBFRAM) PE1 ; PARITY ERROR DETECTION OUTPUT (3 SUBFRAMS CONTINUOUSLY) PE3 ; RXDATA SYNC DETECTION PLLREF ; ANALOG PLL MASTER CLOCK 1/256 (2Fs) SIGNAL PLLVAR ; AES/EBU INPUT SIGNAL DEMODULATED SIGNAL OUTPUT RDATA ; BIT CLOCK OUTPUT GENERATED FROM AES/EBU INPUT SIGNAL RXBCK ; BLOCK ID SIGNAL RXBLKID ; REFERENCE L/R CLOCK OUTPUT (Fs PERIOD) RXLR SLIP0, SLIP1 ; DATA SLIP DETECTION ; SYNC ERROR DETECTION OUTPUT. SYNCERR ; DIGITAL PLL UNLOCK DETECTION OUTPUT. UNLOCK ; U BIT (USER DATA BIT) STATUS SIGNAL EXTRACTED FROM RXDATA SIGNAL UOUT ; VALIDITY ERROR DETECTION OUTPUT (ONE SUBFRAM A). VE1A ; VALIDITY ERROR DETECTION OUTPUT (ONE SUBFRAM B). VE1B ; VALIDITY ERROR DETECTION OUTPUT VE3A (3FRAMS CONTINUOUSLY FOR SUBFRAM A) ; VALIDITY ERROR DETECTION OUTPUT VE3B (3FRAMS CONTINUOUSLY FOR SUBFRAM B) ; V BIT (VALIDITY BIT) STATUS SIGNAL EXTRACTED FROM RXDATA SIGNAL VOUT INPUT/OUTPUT ; AD0 CON ; AD1 NOA ; AD2 FS0 ; AD3 FS1 ; AD4 FS2 ; AD5 EOA ; F128 TS2 ; FIXDPLL CHANNEL STATUS (CPU AUTO : "H") CHANNEL STATUS (CPU AUTO : "H") CHANNEL STATUS (CPU AUTO : "H") CHANNEL STATUS (CPU AUTO : "H") CHANNEL STATUS (CPU AUTO : "H") SUBFRAME A CHANNEL STATUS (CPU AUTO : "H") OUTPUTS 128Fs OF DIGITAL PLL. PLLSEL : "H", DIGITAL PLL OPERATION MODE SELECTION SIGNAL ("N" : NARROW MODE, "H" : WIDE MODE) ; 1/2 MCK OUTPUT FM12 TS4 LOCKPH0 - 5 ; PLLSEL : "H", FIXDPLL : "H" OPERATION PERIOD SETTING DATA INPUT AT NARROW MODE (DIGITAL PLL MODE) ; SUBFRAME A/B CHANNEL STATUS (CPU AUTO : "H") RD LN2 66 67 PLLREF FIXDPLLZ RXBLKID 62 65 LOCKPH0 LOCKPH1 D0 E1A LOCKPH2 D1 E2A LOCKPH3 D2 E0B LOCKPH4 D3 E1B LOCKPH5 D4 E2B D5 MON 25 55 LRPOL RXLR 22 56 MUTEON PE3 21 54 I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O O — — O O O O O O O INPUT BCKI BCKPOL CLKIN CPU AUTO AD0 CON D6 LN0 AD1 NOA D7 LN1 31 34 35 36 37 38 39 40 AD2 FS0 AD3 FS1 INT 43 AD4 FS2 AD5 EOA RD LN2 CS CPU AUTO 2-20 HDW-500 MMP2V2 IC CXD8859AQ (SONY) C-MOS AUXILIARY IC FOR AUDIO PROCESSOR —TOP VIEW— OOUT VOUT UOUT RDATA ERROR 63 LRCKI 60 BCKI 64 LRPOL 61 BCKPOL 46 SLIP FM12 TS4 F128 TS2 FMASTER CLKIN CLKOUT RXDATA PLLSEL RXBCK PLLVAR PLLREF FIXDPLLZ LOCKPH0 LOCKPH1 LOCKPH2 LOCKPH3 LOCKPH4 LOCKPH5 47 SLIP1 21 23 9 5 7 4 10 59 11 14 PLL (ANALOG OR DIGITAL) 1 2 22 15 16 17 18 19 20 VALIDITY & PARITY CHECK 69 CRC CHECK 66 67 62 25 26 27 28 29 30 VDD(+3.3V) GND NC 24 23 22 21 20 19 18 17 16 15 14 13 28 17 20 34 35 36 33 23 24 38 65 46 BYTES CHANNEL STATUS REGISTER & STATUS COMPARATOR 31 34 35 36 37 38 39 40 43 40 MSTRT MSCK MSIN MSOUT FS XCK STRTI STRTO SCKI SCKO SINI SINO SOUTO CA1 RSTR CA2 SRCK CA3 RSTW CA4 SWCK CRCA CRCB CSAVLDTY CSBVLDTY RXLR RXBLKID D0 E1A D1 E2A D2 E0B D3 E1B D4 E2B D5 MON D6 LN0 D7 LN1 (VDD = +3.3V) PIN No. I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I I O O O — O O O I I I I I I — I — — I I I I I SIGNAL FDLY2 FDLY3 RSTR SRCK RSTW GND SWCK FDO12 FDO34 IVR12 IVR34 FDI12 FDI34 CVR12 CVR34 NC FS GND VDD XCK FFSEL VRFSL CA0 CA1 PIN No. I/O 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I I I I O O — O O I I I I I I I I — — I I I I I 30 32 37 3 4 5 7 CA5 45 PE1 PE3 VE1A VE1B VE3A VE3B SYNCERR SOUTI 29 CA0 44 CA6 46 CA7 SIGNAL 12 MSTRT MSCK MSIN MSOUT STRTO SCKO GND SINO SOUTO STRTI SCKI SINI SOUTI CA2 CA3 CA4 FDI12 13 FDI34 10 11 14 FDO12 IVR34 FDO34 8 9 CVR12 15 CVR34 47 FDLY0 48 FDLY1 1 FDLY2 2 41 IVR12 FDLY3 RESET 21 22 FFSEL VRFSL RESET GND VDD CA5 CA6 CA7 FDLY0 FDLY1 INT FS XCK MSTRT MSCK MSIN MSOUT STRTI SCKI SINI SOUTI 17 TIMING GENERATOR 20 25 SIGNAL MASK GENERATOR 26 27 28 29 34 35 36 37 23, 24, 38 - 40, 44 - 45 / CA0 - 9 8 FDI12 FDI34 IVR12 IVR34 CVR12 CVR34 FDLY0 FDLY1 FDLY2 FDLY3 RESET FFSEL VRFSL HDW-500 MMP2V2 27 GND VDD(+3.3V) NOSGNL UNLOCK DATA LATCH 68 41 RD LN2 42 CS 44 CPU AUTO 26 37 38 39 40 41 42 43 44 45 46 47 48 39 79 80 77 78 75 76 3 SYNC HUNT & DETECT AD0 CON AD1 NOA AD2 FS0 AD3 FS1 AD4 FS2 AD5 EOA SLIP0 25 GND 54 56 55 58 57 GND AUTO MUTE FORMAT CONVERTER OUTPUT SHIFT REGISTER 1 2 3 4 5 6 7 8 9 10 11 12 MUTEON 74 70 MUTE0 MUTE1 71 36 35 34 33 32 31 30 29 28 27 26 25 48 DTMODE0 49 DTMODE1 50 DTMODE2 51 DTMODE3 CPU DATA DECODER AND DATA LATCH CREATE NEW STRT/SCK/ SIN/SOUT GENERATOR 30 32 33 12 8 13 9 10 11 STRTO SCKO SINO SOUTO FDO12 FDO34 AUDIO DELAY 14 REC VERIFY GENERATOR 15 3 47 4 48 FIFO TIMING GENERATOR 1 2 5 7 RSTR SRCK RSTW SWCK 41 21 22 } FOR TEST 2-21 IC CXD8281Q (SONY) C-MOS DIGITAL AUDIO TIME BASE COMPRESSION FOR SIF TRANSMITER 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 GND GND NC GND 78 77 76 75 74 73 72 71 VDD(+5V) NC 91 92 93 94 95 GND 90 89 88 87 86 85 84 83 82 81 80 79 —TOP VIEW— VDD(+5V) 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 GND GND NC NC VDD(+5V) NC VDD(+5V) NC NC NC NC GND 111 112 113 114 115 116 117 118 119 120 GND NC NC GND GND VDD(+5V) GND NC GND VDD(+5V) 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 22 23 73 72 112 85 84 83 82 104 69 68 67 49 2 29 30 32 33 34 35 36 37 27 28 29 30 21 22 23 24 25 26 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 27 25 24 I/O — IU IU — O O O O O O — O O O O — O O O O — IU IU IU IU IU IU IU ID ID SIGNAL GND IT1 CLR NC OT1 OT2 OT3 OT4 OT5 OT6 GND OT7 OT8 OT9 OT10 VDD OT11 OT12 OT13 OT14 GND CHEX1 CHEX0 AFS LRS DIR 20/16 ZCS Z3/4 Z1/2 PIN NO. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O — ID ID ID ID ID ID ID ID ID — ID IU — — — — — IU IU — IU IU IU IU IU IU IU IU — SIGNAL GND C3/4 C1/2 U3/4 U1/2 V3/4 V1/2 AD3/4 AD1/2 BCK GND 128CK LRCK NC NC VDD NC NC IT2 CWCK GND CWD7 (MSB) CWD6 CWD5 CWD4 CWD3 CWD2 CWD1 CWD0 (LSB) VDD PIN NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 I/O — IU IU IU IU IU IU IU IU — — IU IU IU IU — IU IU IU IU — IU IU IU IU IU — O O O PIN SIGNAL NO. 91 GND CWA0 (LSB) 92 93 CWA1 94 CWA2 CWA3 (MSB) 95 96 CWEN 97 IT3 98 IT4 99 IT5 100 NC 101 GND 102 DID0 103 DID1 104 LIM0 105 LIM1 106 VDD 107 CHS1 108 CHS2 109 CHS3 110 CHS4 111 GND DLY0 (LSB) 112 113 DLY1 114 DLY2 115 DLY3 DLY4 (MSB) 116 117 NC 118 AUXT 119 UDT 120 ADFT I/O — OT OT OT OT OT OT OT OT OT — OT O ID — — — — IU ID — IU — — O O O O O — SIGNAL GND AUX0 (LSB) AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 AUX8 GND AUX9 (MSB) ADBT OEAUX NC VDD NC NC SYNC VCK GND D2/D1 NC NC OT15 OT16 OT17 OT18 OY19 VDD CHS2 NC CHS1 NC CHEX1 NC CHEX0 NC DID1 NC DID0 NC D2/D1 NC NC 86 26 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CHS3 NC 28 (VDD = +5V) CHS4 39 38 43 42 40 75 74 52 53 54 55 56 57 58 59 65 64 63 62 66 50 110 3 109 DLY4 NC DLY3 NC DLY2 NC 114 113 108 107 105 87 70 48 47 45 44 4 DLY1 DLY0 OEAUX OT19 IT5 OT18 IT4 OT17 IT3 OT16 IT2 OT15 IT1 OT14 Z3/4 OT13 Z1/2 OT12 C3/4 OT11 C1/2 OT10 U3/4 OT9 U1/2 OT8 V3/4 OT7 V1/2 OT6 ZCS OT5 20/16 OT4 DIR OT3 LRS OT2 AFS OT1 119 118 117 116 115 20 19 18 17 15 14 13 12 10 9 8 7 6 UDT LRCK ADFT 128CK AUXT BCK ADBT LIM1 AUX9 LIM0 AUX8 CWD7 AUX7 CWD6 AUX6 CWD5 AUX5 CWD4 AUX4 CWD3 AUX3 CWD2 AUX2 CWD1 AUX1 CWD0 AUX0 INPUT (WITH PULL-UP REGISTER) ; DIGITAL AUDIO 20BIT/16BIT SELECT 20/16 ; DIGITAL AUDIO FORMAT SELECT AFS ; CHANNEL EXCHANGE 0, 1 CHEX0, 1 CHS1 - CHS4 ; AUDIO CH1–CH4 OUTPUT SELECT (L) ; POWER ON CLEAR (L) CLR CWA0 - CWA3 ; CHANNEL STATUS REGISTER WRITE ADDRESS 0 - 3 ; CHANNEL STATUS REGISTER WRITE CLOCK CWCK CWD0 - CWD7 ; CHANNEL STATUS REGISTER WRITE DATA 0 - 7 ; CHANNEL STATUS REGISTER WRITE ENABLE CWEN ; VIDEO FORMAT D2/D1 SELECT D2/D1 ; DATA ID BIT0, 1 DID0, 1 ; DIGITAL AUDIO MSB FIRST/LSB FIRST SELECT DIR DLY0 - DLY4 ; DELAY CONTROL BIT0 - BIT3 ; TEST (L) IT1 - IT5 ; LINE MODE 0, 1 LIM0, 1 ; DIGITAL AUDIO L/R CLOCK (=Fs) LRCK ; DIGITAL AUDIO LEFT/RIGHT BIT POSITION SELECT LRS ; VIDEO SYNC INPUT SYNC ; DIGITAL AUDIO Z-FLAG C-BIT SELECT ZCS 5 AD1/2 AD3/4 INPUT (WITH PULL-DOWN REGISTER) ; DIGITAL AUDIO 128 x Fs CLOCK 128CK ; DIGITAL AUDIO CH-1/2 DATA AD1/2 ; DIGITAL AUDIO CH-3/4 DATA AD3/4 ; DIGITAL AUDIO BIT CLOCK (=64 x Fs) BCK ; DIGITAL AUDIO CH-1/2 CHANNEL STATUS BIT C1/2 ; DIGITAL AUDIO CH-3/4 CHANNEL STATUS BIT C3/4 ; OUTPUT ENABLE FOR AUX0–9 (L) OEAUX : DIGITAL AUDIO CH-1/2 USER DATA BIT U1/2 : DIGITAL AUDIO CH-3/4 USER DATA BIT U3/4 : DIGITAL AUDIO CH-1/2 VALIDITY FLAG V1/2 : DIGITAL AUDIO CH-3/4 VALIDITY FLAG V3/4 ; VIDEO CLOCK (=4Fsc) INPUT VCK : DIGITAL AUDIO CH-1/2 BLOCK SYNC (Z-FLAG) Z1/2 : DIGITAL AUDIO CH-3/4 BLOCK SYNC (Z-FLAG) Z3/4 89 90 88 103 102 100 99 98 OUTPUT ADBT ADFT AUXT OT1 = OT19 UDT ; ; ; ; ; AUX. DATA BLOCK TIMING AUX. DATA FLAG TIMING AUX. DATA TIMING TEST USER DATA TIMING OUTPUT (TRI-STATE) AUX0 - AUX9 ; AUX. DATA 0 - 9 97 96 95 94 93 92 CWA3 CWA2 CWA1 CWA0 CWEN CWCK VCK CLR SYNC U ; INPUT WITH PULL-UP REGISTER D ; INPUT WITH PULL-DOWN REGISTER OT ; TRI-STATE OUTPUT 2-22 HDW-500 MMP2V2 IC CXD8591Q (SONY) C-MOS SAMPLING RATE CONVERTER NC VDD (+3.0 to +3.6 V) GND GND NC VDD (+3.0 to +3.6 V) NC GND 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC VDD (+3.0 to +3.6 V) NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 —TOP VIEW— (VDD = +3.0 to +3.6 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 O I O I I I I — — — O O I I I I DO SEL SRDT SWDT SCK XLAT INIT NC VDD NC RBPH STA FRS FRM SLAVE TEST5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O I I I O I/O I/O I — I — O O — — I/O TB7 MDO0 MDO1 MUTE DATAO BCKO LRCKO TEST4 GND XI GND XO XOO VDD NC TB6 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I I O O — — — O O I I I I I/O TB5 TB4 MAO0 MAO1 ALRKO ABCKO NC VDD NC DAOR DAOL TEST3 DEMP FS1 FS2 TB3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O I/O I I I I O — I I I I I I I I/O TB2 TB1 DATAI LRCKI BCKI FIMCK FIMO GND TEST2 TEST1 FIS MI0 MI1 DI0 DI1 TB0 BCKI DATAI MI0 MI1 52 53 51 60 : : : : : : : : : : : : : : : : : : : : : : BIT CLOCK FOR THE INPUT SERIAL DATA SERIAL DATA DEEMPHASIS SETTING DATA MASTER CLOCK FOR THE INPUT DATA SYSTEM FIMCK DIVIDING RATIO SETTING Fs RATIO MEASURING MODE SELECT Fs RATIO MEASURING TIME SELECT Fsi FREQUENCY SELECT FOR DEEMPHASIS SETTING INITIALIZE 1 Fs WORD CLOCK FOR THE INPUT SERIAL DATA SERIAL DATA FORMAT SETTING FOR D/A OUTPUT SERIAL DATA FORMAT SETTING FOR THE STANDARD DATA OUTPUT INPUT SERIAL DATA FORMAT SETTING OUTPUT MUTING ATTENUATION/MODE SETTING CLOCK DATA SELECT CONTROL OUTPUT SYNCHRONIZATION MODE SELECT ATTENUATION/MODE SETTING DATA IC CHIP TEST CRYSTAL OSCILLATOR ATTENUATION/MODE SETTING DATA LATCH PULSE OUTPUT ABCKO ALRKO DAOL DAOR DATAO DO FIMO RBPH SRDT STA XO XOO : : : : : : : : : : : : BIT CLOCK FOR D/A OUTPUT WORD CLOCK FOR D/A OUTPUT 8 Fso/4 Fso DATA FOR L-CHANNEL D/A CONVERSION 8 Fso/4 Fso DATA FOR R-CHANNEL D/A CONVERSION STANDARD SERIAL DATA DATA INVERTING OUTPUT OF THE MASTER CLOCK RING BUFFER READ/WRITE PHASE CONTROL MONITOR ATTENUATION/MODE SETTING DATA Fs CONVERTING RATIO MONITOR CRYSTAL OSCILLATOR MASTER CLOCK FOR THE OUTPUT SYSTEM INPUT/OUTPUT : TEST BUS TB0 - TB7 : BIT CLOCK FOR THE STANDARD SERIAL DATA BCKO : WORD CLOCK FOR THE STANDARD SERIAL DATA LRCKO ATT & DEMP & 1 Fsi TO 8 Fsi FILTER BLOCK LRCKI INPUT BCKI DATAI DEMP DI0, DI1 FIMCK FIS FRM FRS FS1, FS2 INIT LRCKI MAO0, MAO1 MDO0, MDO1 MI0, MI1 MUTE SCK SEL SLAVE SWDT TEST1 - TEST5 XI XLAT SRC & DECIMATION LOW PASS FILTER BLOCK Lch RAM A Lch RAM LPF LPF COEFFI ROM 22 BITS x 64 WORDS 22 BITS x 256 WORDS 26 BITS x 102 WORDS 23 OUTPUT I/F INPUT I/F (SIPO) (PISO) 61 COEFFICIENT ROM Lch RAM B Rch RAM LPF SRC COEFFI ROM 26 BITS x 123 WORDS 22 BITS x 64 WORDS 22 BITS x 256 WORDS 26 BITS x 256 WORDS 22 21 18 19 37 DEMP FS1 FS2 MUTE SRDT SWDT SCK XLAT 45 46 47 20 IIR FIR FILTER CONTROLL (RAM/ROM/ ACC) 38 MPY 23 BITS x 26 BITS 23 BITS x 26 BITS Rch RAM B Rch RAM SRC 22 BITS x 64 WORDS 22 BITS x 64 WORDS 31 BITS OUTPUT 43 I/F 42 (PISO) 35 36 ALU FIMO FIS FRM FRS STA RBPH DI0 DI1 SEL HDW-500 MMP2V2 DATAO MDO0 MDO1 ALRKO ABCKO DAOL DAOR MAO0 MAO1 31 BITS 22 BITS x 16 WORDS ATT/ MODE 6 26 FIMCK BCKO FI-FO 4 5 Lch RAM SRC 22 BITS x 64 WORDS MPY ALU 3 Rch RAM A 22 BITS x 64 WORDS LRCKO SYSTEM 54 CONTROLLER-1 55 59 14 13 12 SAMPLE RATE-DET. & RESAMPLE POINTER GENERATER CONTROLLER-1 PROGRAM ROM CONTROLLER-2 PROGRAM ROM SYSTEM CONTROLLER-2 28 FLAME 29 COUNTER 7 15 1 XI XO XOO INIT SLAVE DO 11 62 TEST1 - TEST5 63 2 TB0 - TB7 57, 58, 44, 24, 16 64, 50 - 48, 34 - 32, 17 2-23 IC CXD8384Q (SONY) C-MOS LTC READER/GENERATOR 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 —TOP VIEW— 12 GND VDD(+3.3V) GND VDD(+3.3V) 14 GND GND VDD(+3.3V) GND GND GND VDD(+3.3V) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GND 13 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 16 17 18 9 10 11 42 43 71 27 26 24 25 20 72 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 87 37 44 49 PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I/O I/O I/O — — I/O I/O I/O I/O I I I I I I — I I I O I O O O I I 2-24 SIGNAL D2 D3 VDD GND D4 D5 D6 D7 CS WR RD A0 A1 A2 GND A3 A4 A5 X1BE X1TC REC OUT READ PBTC LTCI PIN No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O I I — — O O O O O I I I O I — O I I I O O O O I O SIGNAL CTLI FWD VDD GND RSYC LREV DCLK DATA BER DMCK DEMI K16I XBK BKIN GND BKO CSHD CSVD HDI HDO VDO IFRM FRAM DLYI DLYO PIN No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 I/O I I — — O O I I O O I O O I — O O O O I I/O O I I O SIGNAL FRMI LSHI VDD GND LSHO VCEO VCI1 VCI2 LTCO CFNG REF XOUT PORT NORM GND NT4F PL4F PL8F PM8F TEST11 LRRV XINT XRES BKUP INTM PIN No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O SIGNAL 51 52 57 O O — — O O O I I I I I O I — O O I I I I I I I/O I/O INTG INTL VDD GND INTC INTR INTX TEST1 TEST2 TEST3 TEST4 ALCK CK2M CK1I GND CK1O DCCK INTE TEST5 TEST6 TEST7 TEST8 TEST9 D0 D1 NT4F A1 PL4F A2 PL8F A3 PM8F A4 A5 D0 CS D1 WR D2 RD D3 D4 CSHD D5 CSVD D6 D7 74 (VDD = +3.3V) A0 58 61 35 36 39 89 93 83 84 85 86 94 95 96 97 98 64 70 LRRV RSYC FWD LREV CTLI DCLK PBTC DATA LTCI BER X1TC X1BE XINIT REC XRES OUT BKUP READ ALCK XBK K16I HDO HDI VDO DLYI IFRM FRMI FRAM LSHI DLYO VCI1 LSHO VCI2 VCEO REF LTCO CFNG DMCK DEMI INTG BKIN INTL CK1I INTC INTE INTR TEST1 INTX TEST2 TEST3 CK2M TEST4 BKO TEST5 CK1O TEST6 DCCK TEST7 INTM TEST8 XOUT TEST9 PORT NORM XINT TEST11 66 67 68 69 99 100 1 2 5 6 7 8 30 31 32 INPUT A0 - A5 ALCK BKIN BKUP CK1I CSHD CSVD CTLI DEMI DLYI DMCK FRMI FWD HDI INTE K16I ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ADDRESS BUS IN ARITHMETIC LOGIC UNIT CLOCK IN BACKUP IN (NEGATIVE LOGIC) BACKUP EXECUTION IN (NEGATIVE LOGIC) SYSTEM CLOCK IN COMPOSITE SYNC/HD IN COMPOSITE SYNC/VD IN CTL SIGNAL IN LONGITUDINAL TIME AND CONTROL CODE IN INPUT TO DELAY CIRCUIT LTC DEMODULATE CLOCK IN FRAME SIGNAL IN CTL DIRECTION SIGNAL IN HORIZONTAL SYNC INPUT EXTERNAL INTERRUPT IN (POSITIVE LOGIC) 16KHz CLOCK IN BACKUP CLOCK IN DIRECTION INPUT FOR LTC READER CALCULATION GENERATED LTC IN LTC SYNCHRINOUS H INPUT NORMAL/BACKUP MODE SELECT TEST IN ; ; ; ; ; ; ; ; PLAYBACK LTC IN READ IN (NEGATIVE LOGIC) REFERENCE OF LTC GENERATOR LTC CLOCK IN-1 EXTERNAL LTC IN LTC CLOCK IN-2 SYSTEM RESET IN (NEGATIVE LOGIC) WRITE IN (NEGATIVE LOGIC) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; BI-PHASE MARK ERROR (BIT ERROR) BACKUP CONTROL OUT-2 (POSITIVE LOGIC) COLOR FRAME ERROR FLAG OUT SYSTEM CLOCK OUT CLOCK 2M OUT CHIP SELECT IN (NEGATIVE LOGIC) DATA BUS DEMODULATED SERIAL DATA OUT LTC DECODE CLOCK OUT DEMODULATED CLOCK OUT OUTPUT FROM DELAY CIRCUIT FRAME SIGNAL OUT -2 HORIZONTAL SYNC DRIVE OUT FRAME SIGNAL OUT -1 CTL INTERRUPT OUT (POSITIVE LOGIC) GENERATOR INTERRUPT OUT (POSITIVE LOGIC) READER INTERRUPT -1 OUT (POSITIVE LOGIC) INTERRUPT MIX OUT (POSITIVE LOGIC) READER INTERRUPT -2 OUT (POSITIVE LOGIC) EXTERNAL LTC INTERRUPT OUT (POSITIVE LOGIC) READ REV/FWD BIT OUT LTC SYNCHRONOUS SIGNAL H OUT LTC SIGNAL OUT DEMODULATED COLOR FRAME OUT ; ; ; ; ; ; ; ; ; ; ; EXTERNAL OUTPUT LTC OUT PORT READ LTC OUT RECORD LTC OUT READ SYNC WORD DATA OUT LTC CLOCK OUT VERTICAL SYNC DRIVE OUT BI-PHASE MARK ERROR (NORMAL SPEED READER) BACKUP CONTROL OUT-1 (NEGATIVE LOGIC) INVERTED INTERRUPT MIX OUT (NEGATIVE LOGIC) INVERTED EXTERNAL OUTPUT LTC OUT 33 34 19 21 22 23 38 45 46 47 48 50 55 LRRV LTCI LSHI NORM TEST1 - TEST9 TEST11 PBTC RD REF VCI1 VCI2 X1TC XRES WR 56 59 60 76 77 80 81 82 88 41 91 92 75 62 63 72 OUTPUT BER BKO CFNG CK1O CK2M CS D0 - D7 DATA DCCK DCLK DLYO FRAM HDO IFRM INTC INTG INTL INTM INTR INTX LREV LSHO LTCO NT4F, PL4F, PL8F, PM8F OUT PORT READ REC RSYC VCEO VDO X1BE XBK XINT XOUT HDW-500 MMP2V2 RD1 CLOCK 13.5M DEMO STBY DECS1 DECS0 1/16 1/16 1/8 P/N 3/4 DET CK SYNC DET CK DETECT CTL LTRREV OVF DLYI 49 MUTEA COUNTER CR R COUNTER CK R REF 61 BYPASS DATA DATA READ ERROR FRMI 51 READ 1/8 P/N K20-2 CTLREV 1/1 VCI1 57 VCE0 56 DLYO 50 LSHO 55 K16I 37 HDI 44 RGOUT X1 ROM CTL LAI LRA TC RGREV ENCODE (1/320) M/32K TIMGEN ALU B A PHASE CF CHECK P/N 1/8 PB CF CHECK X1LD LRDLD BYPASS OR AUTO INTERRUPT STBRES STANDBY TIMER A UB X1 TIME X1 UB READ TIME READ INTTM, INTTO CSSTBY CSX1UB CSX1TM CSLUBR CSLTCR OUT0 OUT1 INTXO CTLREV XINT 72 PL8F 68 PL4F 67 NT4F 66 PM8F 69 SK16 RGMSK X1MSK LRMSK EXMSK CTMSK TMMSK RGREV AUTO BYPAS REAL RGRUN RLRUN TMRUN CMPST DIRCT RD1 RD0 INTLO INTRO INTEO MMV RECI CTLLD TIMLD RECO INTTO INTCO RGOUT INTRM MUTEA PHASE INTEM MUTE INTCM INTTM RISE VARDT LTRREV APLL XI+2 XIDER RELLD NORMAL P/N OVF PALM DECS1 STBY DER DECS0 ENCEN BER XI_2 RD 74 BKUP 73 XRES 93 INTE INTRM, INTRO INTXM, INTXO INTLM, INTLO INTEM, INTEO INTCM, INTCO 9 INTR 81 INTX 82 INTC 80 INTL 77 11 WR 10 CS A0 - A5 D0 - D7 DLY0 - 7 SEPEN K20 - 2 K10 - 2 CTLHSN FLAG XW00 - 05 07, 08, 09 DECODE ADDRESS LRALD CSCTL CSTCG CSREAL XR06, XR07, XR08 CSRGTM.CSU(X) CSREAL.CSTCG CSCTL.CSLTCR CSLUBR.CSXITM CSXIUB.CSSTBY STBRES.XR06 XR07.XR08 RGNLD CTL TIME REAL CSUBG CFOM MUTE TMRUN RLRUN GEN UB FLD1 REAL CSRGTM INTLM R0OUT TIME REGEN INTXM 1/8 FL01 RGREV SELECT & PHASE CORRECT RGRUN UB INTG 76 1/1 1/8 CK SELECT LTC OUT CK SYNC DET CK 3/4 DET REGEN CLOCK GEN 1/16 DPLL VCI2 58 INTM 75 1/2 1/16 CK DEMO RELL 1 TEST PATTERN GEN DIRCT A B LTCO 59 89 CK1I 1/16 10 P/N BACK UP CONTROL P/N DELAY DLY0-7 LSHI 52 AUTO VDO 46 FRMGEN CMPST HDO 45 P/N SK16 1/1 CFNG 60 91 CK1O 88 CK2M 92 DCCK 87 ALCK 19 X1BE 20 X1TC 24 PBTC 62 XOUT 23 READ 22 OUT 21 REC 25 LTCI 27 FWD 26 CTLI 30 RSYC 31 LREV 32 DCLK 33 DATA 34 BER 35 DMCK 36 DEMI 83 - 86, TEST 94 - 98, 1-9, 11 70 38 XBK 41 BKO 64 NORM CMPST REC0 39 BKIN 1/2 RD0 P/N SEPENA SEPENA REC1 ENCENA HDSEP OUT0 BYPASS 42 CSHD OUT1 XW0B K10-2 RELL1 IFRM 47 VARDT XW0B DER 1/16 RISE XI+2 CTLHSN APLL IMTT FRAM 48 MUTE XI-2 INTC HVGEN INTX VDET P/N 43 CSVD CFOM HDW-500 MMP2V2 PALM REGEN 12 - 14, 16 - 18 99, 100, 1, 2, 5 - 8 IC 2-25 IC CXD8385Q (SONY) C-MOS ENCODER 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 —TOP VIEW— 30 GND VDD(+5V) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GND GND VDD(+5V) 96 GND VDD(+5V) GND GND VDD(+5V) GND GND 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 43 27 26 25 24 23 22 21 20 19 18 86 87 92 95 31 97 12 11 10 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 8 7 6 5 2 1 (VDD = +5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I/O SIGNAL I I — — I I I I I I I I I I — I I I I I I I I I I ANC9 ANC8 VDD GND ANC7 ANC6 ANC5 ANC4 ANC3 ANC2 ANC1 ANC0 EXTH EXTF GND CF1 CF2 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 2-26 PIN No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIN I/O SIGNAL No. I VD1 51 I VD0 52 — VDD 53 — GND 54 I PIN 55 I PARAENC 56 I HDELAY0 57 I HDELAY1 58 I INX ON/OFF 59 I VC13 60 I VC12 61 I TRS MODE 62 I CK27 63 I INX B0/B2 64 — GND 65 I VC11 66 I VC10 67 I XZLD 68 I TCL 69 I THCNT 70 I TFCNT 71 I TFCK 72 I TCNTO 73 O SAVPNT 74 O POUT 75 I/O SIGNAL O O — — O O O I O O O O O O — O O O O O O O O O O MUD0 MUD1 VDD GND MUD2 MUD3 MUD4 VIEFENA CM0 TFO TVO MUD5 MUD6 MUD7 GND MUD8 MUD9 SYNC2 MFP CM1 CM2 CM3 ANEH ANEV CM4 PIN No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O SIGNAL O O — — O O O O O O I I O O — O I I I I I I I I I CM5 CM6 VDD GND CM7 CM8 CM9 SYNC PERROR1 PERROR2 MD0 MD1 OC6 OC13 GND OC27 TX COMP CFINFO SEL RE INCH D1/J2 SLNP ANIS 37 93 34 39 58 94 16 17 38 14 13 98 32 33 42 41 36 35 44 45 46 47 48 PIN PERROR1 RE PERROR2 XZLD POUT VD0 MUD0 VD1 MUD1 VD2 MUD2 VD3 MUD3 VD4 MUD4 VD5 MUD5 VD6 MUD6 VD7 MUD7 VD8 MUD8 VD9 MUD9 84 85 50 51 52 55 56 57 62 63 64 66 67 MD0 MD1 TX SEL PARAENC INCH ANC0 SYNC2 68 ANC1 ANC2 SYNC 83 ANC3 ANC4 ANEH ANC5 ANEV 73 74 ANC6 ANC7 OC27 ANC8 OC13 ANC9 OC6 91 89 88 TRSMODE COMP SAVPNT 49 INX ON/OFF INX B0/B2 TFO VIEFENA TVO 60 61 CFINFO CF1 CM0 CF2 CM1 CK27 CM2 EXTF CM3 EXTH CM4 D1/J2 CM5 HDELAY0 CM6 HDELAY1 CM7 VC10 CM8 VC11 CM9 INPUT ANC0 - ANC9 ; ANCILLARY DATA ; ANC GATE CONTROL ANIS ; CF DATA CF1/CF2 ; CFINFO CONTROL CFINFO ; 27 MHZ CLOCK CK27 ; COMPOSIT/COMPONENT COMP ; MODE CONTROL D1/J2, SLNP ; REF F EXTF ; REF H EXTH HDELAY0, HDELAY1 ; JZ REF H TRS ADVANCE CONTROL INCH, TCL, TCNTO, TFCK, TFCNT, THCNT, XZLD ; TEST PIN INX ON/OFF, INX B0/B2 VIEFENA ; V. INX. CONTROL ; SCRAMBLE NRZ CONVERT ON/OFF PARAENC ; PARITY PIN ; ROUND CONTROL RE ; TRS 10-BIT/8-BIT SELECT TRSMODE ; TEST PIN TX ; 525/60 V BLANK CONTROL VC10 - VC13 ; VIDEO DATA VD0 - VD9 59 70 71 72 OUTPUT ; PULSE ANEH, ANEV ; H, F COUNTER CM0 - CM9 ; MULTIPLEX F COUNTER PULSE MFP MUD0 - MUD9 ; VIDEO DATA ; 13.5 MHZ CLOCK OC13 ; 27 MHZ CLOCK OC27 ; 6.75 MHZ CLOCK OC6 PERROR1, PERROR2 ; PARITY ERROR DETECT ; PARITY POUT ; SAV PULSE SAVPNT SYNC, SYNC2 ; TIMING PULSE ; F MONITOR TFO ; V MONITOR TVO 75 76 77 80 81 82 VC12 VC13 MFP 69 TCL THCNT TFCNT TFCK TCNTO HDW-500 MMP2V2 SEL 95 92 TX XZLD CXD8385Q(4/4) 43 96 RE IC 30 LATCH PIN 84 VD9 - VD0 MD0, MD1 AN9 - ANC0 18 - 27 10 10 8 ROUNDIN LATCH 86, 87 2 1, 2 5 - 12 10 27MHZ TEST YP LATCH P GEN LIMITER 2 CLOCK DELAY SELECTOR MULTIPLEXER SYNC2 COMP INX ON/OFF INX B0/B2 VIEFENA P GEN PERTOR2 PARALLEL ENCODE 000,3FF,3FF,2FF DETECTOR 50 LATCH OFF 27MHZ TRSMODE 85 DL 27MHZ DC COUNT PERTOR1 LATCH 27MHZ 27MHZ LATCH 68 P CHK P OUT 10 LATCH 67, 66, 64 - 62 57 - 55, 52, 51 MUD9 - MUD0 ON 27MHZ 31 37 97 PARAENC INCH 93 34 39 CONNECTION CODE GEN 58 94 CFINFO 2 16, 17 CF1, CF2 83 CF0-2 CF INFO CF0 SYNC V. INX. 73 MULTIPLEXER GATE GEN VIEF ANEH 74 ANEV H 99 F V 100 SLNP ANIS 91 OC27 89 88 38 CK27 EXTF EXTH D1/J2 HDELAY0, 1 VC13 - VC10 OC6 49 ADDRESS DECODE 27MHZ OC13 SAVCPNT 13.5MHZ 14 13 LATCH SELECTOR & LATCH 98 27MHZ 32, 33 2 35, 36, 41, 42 4 HDW-500 MMP2V2 CLOCK GEN & COUNTER CLR PULSE GEN 6.75MHZ H COUNTER F COUNTER 60 TFO 61 TVO 82 - 80, 77 - 75 72 - 70, 59 CM9 - CM0 ADDRESS DECODE MULTIPLEXER & LATCH 10 10 69 MFP BUFFER & SHIFT RESISTOR FOR TEST 44 TCL 45 46 47 48 THCNT TFCNT TFCK TCNTO 2-27 IC CXD8804Q (SONY) C-MOS 8-MPU COMMUNICATION CONTROLLER WITH PARALLEL PORT —TOP VIEW— GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (VDD = +5V) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VDD(+5V) GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC GND GND VDD(+5V) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 55 54 53 MPUIF CS CPU RD CPU WR WAIT RAM WR RAM OE RAM CE 51 50 49 48 47 46 45 44 43 42 39 38 37 64 63 62 61 60 59 58 57 A0CPU A0RAM A1CPU A1RAM A2CPU A2RAM A3CPU A3RAM A4CPU A4RAM A5CPU A5RAM A6CPU A6RAM A7CPU A7RAM A8CPU A8RAM A9CPU A9RAM A10CPU A10RAM A11CPU A11RAM A12CPU A12RAM D0CPU D0RAM D1CPU D1RAM D2CPU D2RAM D3CPU D3RAM D4CPU D4RAM D5CPU D5RAM D6CPU D6RAM D7CPU D7RAM MPUCS0 34 P ON RST MPUCS1 MPUCS2 MPUCS3 MPUCS4 35 36 SYSTEM CK CPU CK MPUCS5 MPUCS6 MPUCS7 9 10 11 H SNC INT S RDY SCK S RESP SCMD STRB 56 31 99 98 97 96 95 94 93 92 30 29 28 27 33 67 68 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 72 71 70 69 23 22 21 20 19 18 17 16 SIGNAL O O O O O O O O I I I O O O — O O O O O O O O — O OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 INT H SNC S RDY S RESP SCK SCMD STRB GND MPUCS7 MPUCS6 MPUCS5 MPUCS4 MPUCS3 MPUCS2 MPUCS1 MPUCS0 N.C H SYNC PIN NO. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O O I I I I I O I I I I I I I — — I I I I I I I I I PIN NO. 51 V SYNC 52 VSNC LEN 53 HV CLK 54 HD 55 VD 56 S PULS IN S PULS OUT 57 58 TES 1 59 P ON RST SYSTEM CK 60 61 CPU CK 62 A12 CPU 63 A11 CPU 64 A10 CPU 65 GND 66 VDD 67 A9 CPU 68 A8 CPU 69 A7 CPU 70 A6 CPU 71 A5 CPU 72 A4 CPU 73 A3 CPU 74 A2 CPU 75 A1 CPU SIGNAL I/O SIGNAL I O I I I I I/O I/O I/O I/O I/O I/O I/O I/O O — O O I/O I/O I/O I/O I/O I/O I/O A0 CPU WAIT CPU WR CPU RD MPUIF CS CONT CS D7 CPU D6 CPU D5 CPU D4 CPU D3 CPU D2 CPU D1 CPU D0 CPU RAM WR GND RAM OE RAMCE D7 RAM D6 RAM D5 RAM D4 RAM D3 RAM D2 RAM D1 RAM ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CPU ADDRESS BUS INTERNAL/PARALLEL PORT CPU CLOCK CPU READ STROBE CPU WRITE STROBE VIDEO HORIZONTAL SYNCHRONIZING PULSE SERIAL RECEIVE WAIT VIDEO VERTICAL SAMPLING PULSE (13.5 MHz) PARALLEL PORT EXTERNAL RAM CHIP SELECT POWER IN RESET (L) MEDIOCRITY CLOCK PULSE SERIAL TRANSMISSION LEADY SERIAL RECEIVE DATA SYSTEM CLOCK TEST (L) VIDEO VERTICAL SYNCHRONIZING PULSE VIDEO VERTICAL SYNCHRONIZING PULSE OUTPUT WIDTH CONTROL OUTPUT A0RAM - A12RAM H SYNC INT MPUCS0 - MPUCS7 OUT 20 - 27 RAM CE RAM OE RAM WR SCK SCMD S PULS STRB V SYNC WAIT ; ; ; ; ; ; ; ; ; ; ; ; ; ; EXTERNAL RAM ADDRESS BUS VIDEO HORIZONTAL SYNCHRONIZING PULSE SERIAL RECEIVE END SERIAL CORRESPONDENCE ENABLE PARALLEL PORT EXTERNAL RAM CHIP SELECT EXTERNAL RAM OUTPUT ENABLE EXTERNAL RAM WRITE STROBE SERIAL CORRESPONDENCE CLOCK SERIAL TRANSMISSION DATA MEDIOCRITY CLOCK PULSE FREQUENCY (1/2-1/27) SERIAL TRANSMISSION STROBE VIDEO VERTICAL SYNCHRONIZING PULSE CPU WAIT INPUT/OUTPUT D0CPU - D7CPU D0RAM - D7RAM ; CPU DATA BUS ; EXTERNAL RAM DATA BUS PIN NO. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O SIGNAL I/O O O O O O O O O O O O O O — — I I I I I I I I O D0 RAM A12 RAM A11 RAM A10 RAM A9 RAM A8 RAM A7 RAM A6 RAM A5 RAM A4 RAM A3 RAM A2 RAM A1 RAM A0 RAM GND VDD INP 07 INP 06 INP 05 INP 04 INP 03 INP 02 INP 01 INP 00 OUT 27 16 - 23 H SNC INPUT A0CPU - A12CPU CONT CS CPU CK CPU RD CPU WR HD H SNC HV CLK INP 00 - 07 MPUIF CS P ON RST S PULS S RDY S RESP SYSTEM CK TES 1 VD VSNC LEN 74 73 I/O CXD8804Q(3/4) 52 65 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 S RDY S RESP MPUIF CS 9 MPUCS0 - MPUCS7 10 11 TRANSMITTER P S CONVERTER 55 8 12 13 14 P ON PST SYSTEM CK CPU CK CPU WR CPU RD INT SCK SCMD STRB 34 35 36 52 53 65 54 67 68 37 - 39, 42 - 51 A0CPU - A12CPU DATA/ADDRESS BUS CONTROL 57 - 64 WAIT RAMWR RAMOE RAMCE 77 - 89 A0RAM - A12RAM 69 - 76 D0CPU - D7CPU D0RAM - D7RAM 92 - 99 INP 00 - INP 07 1 - 7, 100 PARALLEL PORT CONT CS S PULS IN TES 1 HD VD VSNC LEN HV CLK OUT20 - OUT27 56 37 CLOCK PRESCALER 32 S PULS OUT 33 29 30 27 25 SYNC GENERATOR 26 H SYNC V SYNC 28 8 12 13 14 CONT CS S PULS IN S PULS OUT INP 00 OUT 20 INP 01 OUT 21 INP 02 OUT 22 INP 03 OUT 23 INP 04 OUT 24 INP 05 OUT 25 INP 06 OUT 26 INP 07 OUT 27 VD H SYNC HD V SYNC 32 7 6 5 4 3 2 1 100 25 26 HV CLK VSNC LEN TES 1 2-28 HDW-500 MMP2V2 IC CXD8820AR (SONY) C-MOS VITC READER GENERATOR 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 —TOP VIEW— 41 46 47 48 49 50 39 38 37 36 31 51 52 55 56 57 58 59 60 32 33 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 67 61 62 HDW-500 MMP2V2 IHD OHD IVD OVD ICF OCF IPA OPA ALLTH PERR DATA0 GSAV DATA2 VGATE DATA3 BGATE DATA4 GVITC DATA5 XCFI DATA6 IDEN DATA7 NT4F ICAD0 PL8F ICAD1 PM8F ICAD3 EXP0 SIGNAL DATA0 DATA1 VDD GND DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 STS0 STS1 STRB RD GND CS LPARA SCK START SIN SOUT RINT REND OSVI ISVI 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 O O — — O O O O O O O O O O — O O O O O O O O O O RVITC RLTCH VDD GND GVITC VGATE BGATE XCFI NT4F PL4F PL8F PM8F HMSK VMASK GND CK135 IDEN PERR IFBUSY RCF RDF RFM RERR G SAV EXP0 69 64 66 SIN SOUT LPARA RVITC STS0 RLTCH STS1 RINT STRB REND START RCF RD RDF CS RFM RERR 26 75 HRTH HMSK ISVI VMASK OSVI 30 27 14 13 12 7 6 5 2 1 18 19 20 21 93 99 81 82 80 83 92 84 85 86 87 100 94 71 SCK 76 77 72 73 95 96 97 98 88 89 74 27CK RESET CK135 TST7 I/O 63 16 ICAD2 TST6 SIGNAL PIN NO. 17 DATA1 TST5 I/O I/O — — I/O I/O I/O I/O I/O I/O I I I I — I I I I I O O O O I OVD9 25 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 OVD8 IVD9 TST4 HRTH RESET VDD GND 27CK ALLTH ICAD0 ICAD1 ICAD2 ICAD3 IPA ICF IVD IHD GND IVD0 IVD1 IVD2 IVD3 IVD4 IVD5 IVD6 IVD7 IVD8 IVD9 OVD7 IVD8 24 I I — — I I I I I I I I I I — I I I I I I I I I I IVD7 TST3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O OVD6 23 OVD9 OVD8 VDD GND OVD7 OVD6 OVD5 TST0 TST1 TST2 TST3 OVD4 OVD3 OVD2 GND OVD1 OVD0 OHD OVD OCF OPA TST4 TST5 TST6 TST7 SIGNAL OVD5 IVD6 TST2 O O — — O O O I I I I O O O — O O O O O O I I I I I/O IVD5 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SIGNAL OVD4 TST1 I/O PIN NO. OVD3 IVD4 IFBUSY 70 68 PIN NO. IVD3 PL4F 35 PIN NO. OVD2 11 GND 45 IVD2 TST0 GND VDD(+3.3V) 44 OVD1 9 GND 43 OVD0 IVD1 8 GND 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 IVD0 10 GND VDD(+3.3V) GND VDD(+3.3V) GND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GND VDD(+3.3V) 42 91 INPUT 27CK ALLTH CS TST0 - TST7 ; 27MHz CLOCK ; ALL THOUGH MODE ; CHIP SELECT (FOR PARALLEL INTERFACE) ; READER THOUGH MODE ; IC ADDRESS ; COLOR FRAMING ; HD ; PARITY ; SLICED VITC ; VIDEO DATA ; VD ; PARARELL INTERFACE SELECT ; READ (FOR PARALLEL INTERFACE) ; POWER ON RESET ; SERIAL INTERFACE CLOCK ; SERIAL DATA ; SERIAL INTERFACE START ; STROBE (FOR PARALLEL INTERFACE) ; STATUS 0, 1 (FOR PARALLEL INTERFACE) ; FOR TEST 0-7 OUTPUT BGATE CK135 EXP0 GSAV GVITC HMSK IDEN IFBUSY NT4F OCF OHD OPA OSVI OVD0 - OVD9 OVD PERR PL4F PL8F PM8M RCF RDF REND RERR RFM RINT RLTCH RVITC SOUT VGATE VMASK XCFI ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; HRTH ICAD0 - ICAD3 ICF IHD IPA ISVI IVD0 - IVD9 IVD LPARA RD RESET SCK SIN START STRB STS0, STS1 BLANKING LINE PULSE 13.5MHz CLOCK EXPANDED OUTPUT PORT (G) SAV PULSE GNENRATED VITC (R) VITC SEARCH LINE IC INTERFACE ENABLE INTERFACE BUSY NTSC 4FIELD COLOR FRAMING HD PARITY SLICED VITC VIDEO DATA VD PARITY ERROR PAL 4FIELD PAL 8FIELD PALM 8FIELD READ COLOR FRAME BIT READ DROP FRAME BIT READ END READ ERROR SIGNAL READ FEILD MARK BIT READ END INTERRUPT READ VITC LATCH PULSE READ VITC SERIAL DATA INSERT LINE PULSE (R) EAV_SAV MASK PULSE COLOR FRAMING INFORMATION INPUT/OUTPUT DATA0 - DATA7 ; PARARELL INTERFACE DATA BUS 2-29 IC CXD8811AQ (SONY) C-MOS AUDIO PROCESSOR GND GND GND VDD(+3.3V) GND VDD(+3.3V) GND GND GND VDD(+3.3V) VDD(+3.3V) GND GND VDD(+3.3V) GND GND VDD(+3.3V) GND VDD(+3.3V) GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 VDD(+3.3V) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 —TOP VIEW— (VDD = +3.3V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O SIGNAL — I I I I I I O O — O O I I I I I I I — I I I I I O O O O — O O I I I I I I O — GND RST TEST0 TEST1 TEST2 TEST3 MTRI MTRO CUE GND LIN1/2 LIN3/4 ADC1/2 ADC2 ADC3/4 ADC4 TMODE2 TMODE3 TMODE4 VDD TMODE5 TMODE6 TMODE7 SIFI1/2 SIFI3/4 SIFO1/2 SIFO3/4 AESO1/2 AESO2 GND AESO3/4 AESO4 AESI1/2 AESI2 AESI3/4 AESI4 DSPI1/2 DSPI3/4 VTRG VDD 2-30 PIN No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O SIGNAL — I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O — — O O O O O O O O O — O O O O O O O O O — GND I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND VDD OE WE A0 A1 A2 A3 A4 A5 A6 GND A7 A8 A9 A10 A11 A12 A13 A14 A15 VDD PIN No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 I/O SIGNAL — O O I I I I I I — I I I I I I I I I — I I I I I I I I I — I I I I I I I I I — GND A16 A17 AEIM1 AEIM2 AEIM3 AEIM4 SIIM1 SIIM2 GND SIIM3 SIIM4 ADVM1 ADVM2 ADVM3 ADVM4 CNFM1 CNFM2 CNFM3 VDD CNFM4 ENCM SIOM AEOM LINM MTRM IFLG1 IFLG2 IFLG3 GND IFLG4 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TMODE0 TMODE1 VDD PIN No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 I/O SIGNAL — I I I I I I I I — I I I I I I I I — — I I I I I I I I O — O O I I I I I I I — GND TEST10 TEST11 ADV1/2 ADV3/4 VAR1/2 VAR3/4 PPL1/2 PPL3/4 GND CNF1/2 CNF3/4 REFV CA0 CA1 CA2 CA3 FS256 GND VDD FS CA4 CA5 CA6 CA7 START CLOCK SIN SOUT GND ENC1/2 ENC3/4 TEST12 TEST13 TEST14 TEST15 TEST16 TEST17 POM VDD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 INPUT ADC1/2 ADC2 ADC3/4 ADC4 ADV1/2 ADV3/4 ADVM1 ADVM2 ADVM3 ADVM4 AEIM1 AEIM2 AEIM3 AEIM4 AEOM AESI1/2 AESI2 AESI3/4 AESI4 CA0 -CA7 CLOCK CNF1/2 CNF3/4 CNFM1 CNFM2 CNFM3 CNFM4 DSPI1/2 DSPI3/4 ENCM FS FS256 IFLG1 IFLG2 IFLG3 IFLG4 LINM MTRI MTRM POM PPL1/2 PPL3/4 REFV RST SIFI1/2 SIFI3/4 SIN SIIM1 SIIM2 SIIM3 SIIM4 SIOM START TEST0 - TEST17 TMODE0 TMODE1 TMODE2 TMODE3 TMODE4 TMODE5 TMODE6 TMODE7 VAR1/2 VAR3/4 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; A/D INPUT CH1/CH2 A/D INPUT CH2 A/D INPUT CH3/CH4 A/D INPUT CH4 DECODER INPUT CH1/CH2 (ADVANCE IN) DECODER INPUT CH3/CH4 (ADVANCE IN) ADVANCE INPUT MUTE CH1 (ACTIVE LOW) ADVANCE INPUT MUTE CH2 (ACTIVE LOW) ADVANCE INPUT MUTE CH3 (ACTIVE LOW) ADVANCE INPUT MUTE CH4 (ACTIVE LOW) AES INPUT MUTE CH1 (ACTIVE LOW) AES INPUT MUTE CH2 (ACTIVE LOW) AES INPUT MUTE CH3 (ACTIVE LOW) AES INPUT MUTE CH4 (ACTIVE LOW) AES OUTPUT MUTE (ACTIVE HIGH) AES INPUT CH1/CH2 AES INPUT CH2 AES INPUT CH3/CH4 AES INPUT CH4 IC ADDRESS CPU I/F CLOCK DECODER INPUT CH1/CH2 (CONFI IN) DECODER INPUT CH3/CH4 (CONFI IN) CONFI INPUT MUTE CH1 (ACTIVE LOW) CONFI INPUT MUTE CH2 (ACTIVE LOW) CONFI INPUT MUTE CH3 (ACTIVE LOW) CONFI INPUT MUTE CH4 (ACTIVE LOW) DSP INPUT CH1/CH2 DSP INPUT CH3/CH4 ENCODER OUTPUT MUTE (ACTIVE HIGH) SYSTEM CLOCK (Fs) SYSTEM CLOCK (256 X Fs) INSERT FLAG CH1 (ACTIVE HIGH) INSERT FLAG CH2 (ACTIVE HIGH) INSERT FLAG CH3 (ACTIVE HIGH) INSERT FLAG CH4 (ACTIVE HIGH) LINE OUTPUT MUTE (ACTIVE HIGH) MONITOR INPUT FOR 8-CHANNEL SYSTEM MONITOR OUTPUT MUTE (ACTIVE HIGH) POWER ON MUTE (ACTIVE LOW) DECODER INPUT CH1/CH2 (P. PLAY IN) DECODER INPUT CH3/CH4 (P. PLAY IN) SYSTEM CLOCK (V PULSE) RESET (ACTIVE LOW) SIF INPUT CH1/CH2 SIF INPUT CH3/CH4 CPU I/F SERIAL IN SIF INPUT MUTE CH1 (ACTIVE LOW) SIF INPUT MUTE CH2 (ACTIVE LOW) SIF INPUT MUTE CH3 (ACTIVE LOW) SIF INPUT MUTE CH4 (ACTIVE LOW) SIF OUTPUT MUTE (ACTIVE HIGH) CPU I/F START (PULSE) TEST INPUT (DEFAULT LOW) TEST MODE 0 (DEFAULT LOW) TEST MODE 1 (DEFAULT LOW) TEST MODE 2 (DEFAULT LOW) TEST MODE 3 (DEFAULT LOW) TEST MODE 4 (DEFAULT LOW) OUTPUT AESO1/2 AESO2 AESO3/4 AESO4 A0 - A17 CUE ENC1/2 ENC3/4 LIN1/2 LIN3/4 MTRO SIFO1/2 SIFO3/4 SOUT OE VTRG WE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; AES OUTPUT CH1/CH2 AES OUTPUT CH2 AES OUTPUT CH3/CH4 AES OUTPUT CH4 EXTERNAL RAM ADDRESS CUE (D-MIX) ENCODER OUTPUT CH1/CH2 ENCODER OUTPUT CH3/CH4 LINE OUTPUT CH1/CH2 LINE OUTPUT CH3/CH4 MONITOR OUTPUT FOR 8-CHANNEL SYSTEM SIF OUTPUT CH1/CH2 SIF OUTPUT CH3/CH4 CPU I/F SERIAL OUT EXTERNAL RAM OUTPUT ENABLE (ACTIVE LOW) TRIGGER OUT (5V PULSE) EXTERNAL RAM WRITE ENABLE (ACTIVE LOW) INPUT/OUTPUT I/O0 - I/O15 ; EXTERNAL RAM TEST MODE 5 (DEFAULT LOW) TEST MODE 6 (DEFAULT LOW) TEST MODE 7 (DEFAULT LOW) DECODER INPUT CH1/CH2 (VARIABLE IN) DECODER INPUT CH3/CH4 (VARIABLE IN) HDW-500 MMP2V2 IC CXD9000CR (SONY) C-MOS HD-SDI COPROCESSOR 73 75 NC NC NC NC NC NC NC GND NC 80 85 90 NC GND VDD(+3.3V) NC NC 95 100 GND 109 110 105 108 —TOP VIEW— NC 72 VDD(+3.3V) 70 115 GND 65 GND 120 60 125 VDD(+3.3V) GND GND VDD(+3.3V) 55 130 50 135 GND 45 NC GND NC NC NC NC NC 37 35 36 30 25 GND NC NC NC NC NC NC NC 20 10 1 15 GND VDD(+3.3V) 144 NC NC NC NC NC NC NC VDD(+3.3V) GND 40 5 140 (VDD = +3.3V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 — I I I I I I I — I — — — — — — — — — O O O O O O O O O O — — — — — — — VDD IP AUDA12 IP AUDA34 IP AUDA56 IP AUDA78 IP CKAUA IP FSA IP CKAUB GND IP FSB NC NC NC NC NC NC NC VDD GND OP AUCKPH1 OP AUCKPH2 OP AUEFLG12 OP AUEFLG34 OP AUEFLG56 OP AUEFLG78 OP AUDA12 OP AUDA34 OP AUDA56 OP AUDA78 GND NC NC NC NC NC NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 — O O O — O O O — O O O O O O O O — — O O O O O O O O O O — O O O O O — NC OP AUEFLG OP YADFLG OP CADFLG NC OP CK74 OP EXTV OP EXTH GND OP EXTF OP CDATA10 OP CDATA9 OP CDATA8 OP CDATA7 OP CDATA6 OP CDATA5 OP CDATA4 VDD GND OP CDATA3 OP CDATA2 OP CDATA1 OP CDATA0 OP YDATA10 OP YDATA9 OP YDATA8 OP YDATA7 OP YDATA6 OP YDATA5 GND OP YDATA4 OP YDATA3 OP YDATA2 OP YDATA1 OP YDATA0 NC 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 — O O O O O I — — — — — — — — — O — — I — I I I I I I/O I/O I/O — I/O I/O I/O I/O I/O — VDD OP MYFLG1 OP MYFLG2 OP MYFLG3 OP MYFLG4 OP MYFLG5 IP RESET NC GND NC NC NC NC NC NC NC OP SYRW VDD GND IP SYRW NC IP XMM IP SYCS IP SYCK IP SYSTA1 IP SYSTA0 BP SYIF7 BP SYIF6 BP SYIF5 GND BP SYIF4 BP SYIF3 BP SYIF2 BP SYIF1 BP SYIF0 NC 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 — I I I I I I I — I I I I I I I I — — I I I I I I I I I — — I — — — — O NC IP YDATA0 IP YDATA1 IP YDATA2 IP YDATA3 IP YDATA4 IP YDATA5 IP YDATA6 GND IP YDATA7 IP YDATA8 IP YDATA9 IP YDATA10 IP CDATA0 IP CDATA1 IP CDATA2 IP CDATA3 VDD GND IP CDATA4 IP CDATA5 IP CDATA6 IP CDATA7 IP CDATA8 IP CDATA9 IP CDATA10 IP EXTF IP EXTH NC GND IP CK74 NC NC NC NC OP ERR HDW-500 MMP2V2 2-31 IC CXD8824AQ (SONY) C-MOS JOG AUDIO SOUND PROCESSOR GND NC GND VDD(+3.3V) GND NC GND GND VDD(+3.3V) GND GND GND GND VDD(+3.3V) VDD(+3.3V) NC NC GND PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 — I I I I O O O O — I O O O — O O I I I I I I I I I/O I/O I/O I/O — I/O I/O I/O I/O I I I I I — GND RESET JMPSL LIMON ENMUTE TDO7 TDO6 TDO5 OBUSEN GND IBUSEN TDO4 TDO3 TDO2 GND TDO1 TDO0 STAT1 STAT0 VDD STRB SCS TAI10 TAI9 TAI8 SYSIO7 SYSIO6 SYSIO5 SYSIO4 GND SYSIO3 SYSIO2 SYSIO1 SYSIO0 CHIPID1 CHIPID0 TAI7 TAI6 TAI5 VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 — — I I I I I I I — I O O O — I I I — — I I — I I I O O O — O O O I I I I O O — GND NC TAI4 TAI3 TAI2 TAI1 TAI0 TDI7 TDI6 GND TDI5 MNDN MNUP MNMUTE NC TDI4 TDI3 TDI2 GND VDD TDI1 TDI0 NC TWE TRE XMM CNFVD CNF2 CNF1 GND ADV1 ADV2 ADVVD MDTES3 MDTES2 MDTES1 MDTES0 OE WE VDD 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 — O O O O — O O O — O O O O — O O O O — O O O O — O O O O — O O O — O O O O I/O — GND A16 A15 A14 TESO8 GND A13 A12 A11 GND A10 A9 A8 A7 GND TESO7 TESO6 TESO5 TESO4 VDD TESO3 TESO2 TESO1 TESO0 GND A6 A5 A4 A3 GND A2 A1 A0 NC SPD3 SPD2 SPD1 SPD0 IO7 VDD 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 — I/O I/O I/O I I I I/O I/O — I/O I/O I I I I I I — — I I I I I I I I I — I I I I I O O O O — GND IO6 IO5 IO4 DE2X1 DE2X2 DE2XV IO3 IO2 GND IO1 IO0 DE2XJP TESI8 TESI7 TESI6 TESI5 FS GND VDD DE2Y1 DE2Y2 DE2YV TESI4 TESI3 TESI2 TESI1 TESI0 FS256 GND DTJMP TRJMP DIR CAPFG FRNORM SPD7 SPD6 SPD5 SPD4 VDD 2-32 OUTPUT A16 - A0 ADV1, ADV2 ADVVD CNF1, CNF2 CNFVD MNDN, MNUP MNMUTE OBUSEN OE SPD7 - SPD0 TDO7 - TDO0 TESO8 - TESO0 WE ; ; ; ; ; ; ; ; ; ; ; ; ; INPUT/OUTPUT I07 - IO0 SYSIO7 - SYSIO0 ; DATA FOR EXTERNAL MEMORY ; DATA FOR SYSTEM CONTROL ADDRESS LINE FOR EXTERNAL MEMORY PROCESS SIGNAL (CH1/CH2, CH3/CH4) PROCESS SIGNAL (VD) INPUT SIGNAL SELECT (CH1/CH2, CH3/CH4) INPUT SIGNAL SELECT (VD) MONITOR OF SPEED DATA WINDOW POSITION MONITOR OF MUTE I/O CONTROL FOR SYSTEM CONTROL TERMINAL I/O CONTROL FOR EXTERNAL MEMORY SPEED DATA MONITOR TEST DATA TEST DATA AND DIFFERENCE ADDRESS WRITE AND READ WRITE ENABLE FOR EXTERNAL MEMORY CXD8814Q (SONY) C-MOS COUNTER FOR A/D CONVERTER —TOP VIEW— 33 32 31 30 29 28 27 26 25 24 23 3 2 34 35 36 37 38 39 40 41 42 43 44 1 GND GND VDD(+5V) GND VDD(+5V) GND GND GND GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND VDD(+3.3V) INPUT ; CAPSTAN FG CAPFG CHIPID1, CHIPID0 ; ID NUMBER ; AUDIO SERIAL DATA (X1 = CH1/CH2, X2 = CH3/CH4) DE2X1, DE2X2 ; DISCONTINUITY OF FIELD DE2XJP ; VD AT FIELD START OF AUDIO DATA DE2XV, DE2YV ; AUDIO SERIAL DATA (Y1 = CH1/CH2, Y2 = CH3/CH4) DE2Y1, DE2Y2 ; TAPE DRIVE DIRECTION DIR ; DT HEAD JUMP SIGNAL DTJMP ; MUTE FLAG (H : NORMAL) ENMUTE ; DT HEAD JUMP AT FRAME OR FEILD FRNORM ; AUDIO SAMPLING FREQUENCY FS ; REFERENCE CLOCK (FSx256) FS256 ; I/O CONTROL FOR SYSTEM CONTROL TERMINAL IBUSEN ; CONTROL LINE SELECT FOR EXIT MEMORY JMPSL ; CONTROL WIDTH OF SELECT SPEED-DATA (H : NORMAL) LIMON MDTES3 - MDTES0 ; TEST MODE SELECT ; SYSTEM RESET RESET ; CLOCK SELECT FOR SYSTEM CONTROL SCS ; ATTRIBUTE DISCRIMINATE OF SYSTEM CONTROL DATA STAT1, STAT0 ; CLOCK FOR SYSTEM CONTROL STRB TAI10 - TAI0, TDI7 - TDI0, TESI8 - TESI0 ; TEST DATA ; JUMP SIGNAL AT FIELD DATA DISCONTINUITY TRJMP ; TEST DATA FOR INTERNAL MEMORY TWE, TRE ; SELECT INTERNAL MEMORY TEST XMM GND VDD(+5V) VDD(+5V) GND GND GND GND VDD(+3.3V) GND NC GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 VDD(+3.3V) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 —TOP VIEW— 22 21 20 19 18 17 16 15 14 13 12 4 5 7 10 16 14 13 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 43 42 41 40 (VDD = +5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I/O SIGNAL I I I I I — I O O I — — I/O I/O — I — O O — — — A2 A1 A0 CLR TEST GND INV OUT OUTN CLK GND DDD XT2 XT1 GND SEL GND ICK ICKN VDD GND GND PIN No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O SIGNAL O O O O O O O O — — — — I I I I — I I I I I D7 D6 D5 D4 D3 D2 D1 D0 VDD VDD GND GND EN3R EN2R EN1R EN0R VDD EN3L EN2L EN1L EN0L LCL 44 A0 D0 A1 D1 A2 D2 D3 CLR D4 TEST D5 INV D6 CLK D7 SEL XT1 ICK XT2 ICKN EN0R OUT EN1R OUTN 30 29 27 26 25 24 23 22 18 19 8 9 EN2R EN3R EN0L EN1L EN2L EN3L LCL INPUT A0 - A3 CLK CLR EN0L - EN3L EN0R - EN3R INV LCL SEL TEST ; COUNTER CONTROL ; CLOCK IN ; COUNTER CLEAR ; COUNTER ENABLE(LOCAL) ; COUNTER ENABLE(REMOTE) ; BUFFER IN ; LOCAL/REMOTE ; CLOCK SELECT ”H” : XTAL ”L” : CLK ; IC TEST PIN OUTPUT D0 - D7 ICK ICKN OUT OUTN ; ; ; ; ; COUNTER DATA CLOCK OUT (+) CLOCK OUT (_) BUFFER OUT (+) BUFFER OUT (_) INPUT/OUTPUT XT1, XT2 ; XTAL HDW-500 MMP2V2 IC CXD8953Q (SONY) C-MOS ERROR DETECTION AND HANDLING 51 55 GND VDD(+5V) VDD(+5V) 60 65 VDD(+5V) 70 GND GND GND 81 VDD(+5V) 75 GND 80 —TOP VIEW— INPUT A0 - A3 AUTO CS FORM0, FORM1 ICLOCK IDATA0 - IDATA9 MODE0 50 85 45 VDD(+5V) 90 40 MODE1 GND 95 MODE2 READ RESET TEST3, TEST4, TEST6, TEST8, TEST14, TEST15 WRITE OUTPUT ANCER APERR DPR EDHVLB FFERR INTR OCLOCK OD1 ODATA0 - ODATA9 OL525 OTHANC TEST0 - TEST2, TEST5, TEST7, TEST9 - TEST13 (VDD = +5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O O — — O O I I O I I I I I — — — I I I I PIN No. 21 TEST0 22 VDD VDD 23 TEST1 24 TEST2 25 TEST3 26 TEST4 27 TEST5 28 ICLOCK 29 IDATA0 30 IDATA1 31 IDATA2 32 IDATA3 33 GND 34 GND 35 GND 36 IDATA4 37 IDATA5 38 IDATA6 39 IDATA7 40 SIGNAL PIN No. IDATA8 41 I IDATA9 42 I FORM0 43 I FORM1 44 I AUTO I 45 MODE0 46 I MODE1 47 I MODE2 48 I O OTHANC 49 O EDHVLD 50 DPR O 51 INTR O 52 D7 I/O 53 D6 I/O 54 D5 I/O 55 D4 I/O 56 D3 I/O 57 D2 I/O 58 D1 I/O 59 D0 I/O 60 I/O SIGNAL I/O SIGNAL I I I I I I I I O I I — — O O O — O O O TEST6 A3 A2 A1 A0 WRITE READ CS TEST7 TEST8 RESET VDD VDD TEST9 TEST10 TEST11 GND TEST12 OCLOCK ODATA9 PIN No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O SIGNAL O O — O — — — O O O O — O — O O O O I I ODATA8 ODATA7 VDD ODATA6 GND GND GND ODATA5 ODATA4 ODATA3 ODATA2 VDD ODATA1 GND ODATA0 TEST13 OD1 OL525 TEST14 TEST15 PIN No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O SIGNAL APERR O FFERR O ANCER O I/O ANCEDH I/O ANCEDA I/O ANCIDH I/O ANCIDA VDD — I/O ANCUES I/O APEDH I/O APEDA GND — APIDH I/O APIDA I/O I/O APUES I/O FFEDH I/O FFEDA FFIDH I/O FFIDA I/O I/O FFUES INPUT / OUTPUT ANCEDA ANCEDH ANCIDA ANCIDH ANCUES APEDA APEDH APIDA APIDH APUES D0 - D7 FFEDA FFEDH FFIDA FFIDH FFUES ENABLE TIMING EAV TRS DPR TIMING GEN DETECT AP CRC GEN AUTO OD1 OL525 OTHANC MODE1 MODE2 RESET 23 FORMAT SELECT 24 25 ; TEST 422/4FC 29 FF CRC GEN 51 EDH DATA INSERT 3FF 000 DID BNO DC HDW-500 MMP2V2 33 34 35 36 45 44 43 42 23 24 25 26 27 28 ODATA8 IDATA7 ODATA7 IDATA6 ODATA6 IDATA5 ODATA5 IDATA4 ODATA4 IDATA3 ODATA3 IDATA2 ODATA2 IDATA1 ODATA1 IDATA0 ODATA0 D7 ANCER D6 APERR D5 FFERR D4 D3 D2 TNTR DPR D1 OD1 D0 OL525 A3 A2 A1 A0 OTHANC OCLOCK ANCEDH ANCEDA FORM0 ANCIDH FORM1 ANCIDA AUTO MODE0 MODE1 MODE2 ANCUES APEDH APEDA APIDH APIDA READ APUES WRITE FFEDH CS FFEDA RESET FFIDH FFUES 6 7 41 50 79 80 TEST3 TEST0 TEST4 TEST1 TEST6 TEST2 TEST8 TEST5 TEST14 TEST7 TEST15 TEST9 TEST10 9 TEST11 ICLOCK TEST12 TEST13 60 61 62 64 68 69 70 71 73 75 83 81 82 32 31 77 78 29 59 84 85 86 87 89 90 91 93 94 95 96 97 98 99 100 1 4 5 8 49 54 55 56 58 76 75, 73, 71 - 68, 64, 63 - 60 ODATA0 ODATA9 HEADER AP CRC DATA MIX CHECK SUM GEN ERROR DETECT AP ERROR 81 FF ERROR 82 INTERRUPT MODE CONT FF CRC DATA INTERRUPT MODE 45 - 42 WRITE DATA 46 48 FLAG DATA FLAG DATA DETECT 32 40 - 33 ERROR FLAG CONVERTER (EDH →EDA) FLAG DATA ANCER APERR FFERR INTR D0-D7 A0-A3 WRITE CS FLAG DATA SELECTOR CRC DATA ERROR READ DATA SELECT 47 OCLOCK ICLOCK 9 TEST0 - TEST2, 1, 4, 5, 8, 49, 54-56, 58, 76 TEST5, TEST7, TEST9 - TEST13 10 ODATA9 IDATA8 FFIDA ; ANCILLARY EDA FLAG ; ANCILLARY EDH FLAG ; ANCILLARY IDA FLAG ; ANCILLARY IDH FLAG ; ANCILLARY UES FLAG ; ACTIVE PICTURE EDA FLAG ; ACTIVE PICTURE EDH FLAG ; ACTIVE PICTURE IDA FLAG ; ACTIVE PICTURE IDH FLAG ; ACTIVE PICTURE UES FLAG ; CPU DATA ; FULL FIELD EDA FLAG ; FULL FIELD EDH FLAG ; FULL FIELD IDA FLAG ; FULL FIELD IDH FLAG ; FULL FIELD UES FLAG 59 TEST3, TEST4, 6, 7, 41, 50, 79, 80 TEST6, TEST8, TEST14, TEST15 11 46 ANC & EDH HEADER FF CRC DATA DETECT 27 28 12 48 ERROR DETECT 525/625 13 IDATA9 INTRRUPT PULSE 77 78 17 47 83 FORM1 18 39 ; ANCILLARY DATA ERROR ; ACTIVE PICTURE ERROR ; INPUT SIGNAL DETECT ; ERROR DETECTION & HANDLING CORRESPOND DETECT ; FULL FIELD ERROR ; INTERRUPT ; OUTPUT CLOCK ; D1/D2 FORMAT SELECT ; OUTPUT DATA ; 525/625, 422/4FC FORMAT SELECT ; OTHER ANC DATA DETECT EDH DATA ADD TIMING AP CRC DATA DETECT FORM0 19 38 ; WRITE EDH DATA GENERATOR 3FC VIDEO0-9 31 FORMAT 20 51 ANC CHECK SUM ANCILLARY ERROR & PARITY CHECK DELAY LATCH 21 37 ; TEST DELAY 10 - 3, 17 - 22 IDATA0 IDATA9 22 40 30 25 20 31 15 10 5 1 100 GND GND GND VDD(+5V) VDD(+5V) 35 ; ADDRESS ; AUTO DETECT ; CHIP SELECT ; VIDEO FORMAT ; CLOCK ; VIDEO DATA ; 1 = Detect each FLAG and calculate CRC. Add the result and output. 0 = Input each FLAG from outside and calculate CRC. Add the result and output. ; 1 = If other ANCILLARY DATA existe EDH, such as AUDIO, no EDH is added. 0 = EDH is added unconditionally. ; MODE SELECT ; READ ; RESET 26 FLAG DATA from CPU (EDH IDH UES) FLAG DATA from EXT FLAG DATA to CPU FLAG DATA to EXT 84 - 87, 89 - 91, 93 - 100 READ MODE0 ANCEDA, ANCEDH, ANCIDA, ANCIDH, ANCUES, APEDA, APEDH, APIDA, APIDH, APUES, FFEDA, FFEDH, FFIDA, FFIDH, FFUES 2-33 IC CXD9001AR (SONY) C-MOS CPU R3041 PERIPHERAL 90 89 95 100 105 115 120 125 130 110 VDD(+5V) 135 GND VDD(+5V) GND GND 133 VDD(+5V) 132 —TOP VIEW— GND GND 88 85 INPUT A0, A1 A23 - A28 BEN0 - BEN3 VARWAITN WRN ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ADDRESS BUS ADDRESS BUS 1st TO 4th BYTE SELECT CPU BURST CTC CLOCK CTC GATE CTC2 CLOCK CTC2 GATE CPU DATA ENABLE EXTERNAL FRAME INTERRUPT CPU LAST CPU READ CPU RESET SIO1 RECEIVE DATA SIO2 CTS SIO2 DSR SIO2 RECEIVE DATA SIO CLOCK CPU SYSTEM CLOCK TEST VARIABLE WAIT CPU WRITE OUTPUT ACKN CTC1OUT0 - CTC1OUT2 CTC2OUT0 - CTC2OUT2 EXTDENN FIFORCKN FIFOREN1 - FIFOREN4 FIFOWEN1 - FIFOWEN4 FLASHCSN FRAME HALFCLK INT IOENN IOENN2 RDCENN RDENN S16W2CSN S16W3CSN S8W3CSN1 - S8W3CSN6 S8W4CSN SIO1INT SIO1TXD SIO2INT SIO2TXD SIOBAN SIOCDN SIORDN SIOWRN SRAM1CS SRAM2CS V8W3CSN V8W6CSN VINT WRENN WRENNA - WRENND ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CPU ACKNOWLEDGE CTC1 OUT CTC2 OUT READ/WRITE SELECT FIFO READ CLOCK FIFO READ ENABLE FIFO WRITE ENABLE FLASH ROM CHIP SELECT FRAME DIVIDED-BY-TWO SYSTEM CLOCK INTERRUPT DATA BUS DRIVER ENABLE 2nd DATA BUS DRIVER ENABLE CPU READ CHIP ENABLE READ 16-BIT 2-WAIT CHIP ENABLE 16-BIT 3-WAIT CHIP ENABLE 8-BIT 3-WAIT CHIP ENABLE 8-BIT 4-WAIT CHIP ENABLE SIO1 INTERRUPT SIO1 TRANSMIT DATA SIO2 INTERRUPT SIO2 TRANSMIT DATA SIO B/A SIO C/D SIO READ SIO WRITE SRAM1 CHIP SELECT SRAM2 CHIP SELECT VARIABLE WAIT 8-BIT 3-WAIT CHIP ENABLE VARIABLE WAIT 8-BIT 6-WAIT CHIP ENABLE FRAME INTERRUPT WRITE SRAM 1st TO 4th BYTE WRITE INPUT/OUTPUT D0 - D7 PIO1P00 - PIO1P07 PIO1P10 - PIO1P17 PIO1P20 - PIO1P27 PIO2P00 - PIO2P07 PIO2P10 - PIO2P17 PIO2P20 - PIO2P27 SIO2BRK ; ; ; ; ; ; ; ; DATA BUS PIO1 PORT0 PIO1 PORT1 PIO1 PORT2 PIO2 PORT0 PIO2 PORT1 PIO2 PORT2 SIO2 SYNC/BRK BURSTN CTC1CLK0 - CTC1CLK2 CTC1G0 - CTC1G2 CTC2CLK0 - CTC2CLK2 CTC2G0 - CTC2G2 DATAENN 140 80 EXTFRAME INTP0 - INTP7 LASTN RDN RESETN SIO1RXD 145 75 150 70 155 65 NC 160 60 165 55 170 I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 — O O I I O I I O I I O O O I I I I I I I — — I I I I I I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O — VDD RDENN WRENN CTC1CLK0 CTC1G0 CTC1OUT0 CTC1CLK1 CTC1G1 CTC1OUT1 CTC1CLK2 CTC1G2 CTC1OUT2 EXTDENN IOENN 2-34 BEN0 BEN1 BEN2 BEN3 A0 A1 A23 VDD GND A24 A25 A26 A27 A28 D0 D1 D2 D3 D4 D5 D6 D7 FLASHCSN SRAM1CS SRAM2CS WRENNA WRENNB WRENNC WRENND VDD PIN NO. I/O SIGNAL 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 — — I I O I O I I O I O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O — — GND GND RESETN SIOCLK SIO1TXD SIO1RXD SIO1INT SIO2CTS SIO2DSR SIO2TXD SIO2RXD SIO2INT SIORDN SIOWRN SIOCDN SIOBAN PIO1P00 PIO1P01 PIO1P02 PIO1P03 PIO1P04 PIO1P05 PIO1P06 PIO1P07 TEST0 PIO1P10 PIO1P11 PIO1P12 PIO1P13 PIO1P14 PIO1P15 PIO1P16 PIO1P17 TEST1 PIO1P20 PIO1P21 PIO1P22 PIO1P23 PIO1P24 PIO1P25 PIO1P26 PIO1P27 GND GND PIN NO. I/O SIGNAL 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 — I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O — — I/O I/O I/O I/O I/O I/O O O I I O I I O I I O O O I — VDD PIO2P00 PIO2P01 PIO2P02 PIO2P03 PIO2P04 PIO2P05 PIO2P06 PIO2P07 TEST2 PIO2P10 PIO2P11 PIO2P12 PIO2P13 PIO2P14 PIO2P15 PIO2P16 PIO2P17 TEST3 PIO2P20 PIO2P21 VDD GND PIO2P22 PIO2P23 PIO2P24 PIO2P25 PIO2P26 PIO2P27 S16W2CSN S16W3CSN CTC2CLK0 CTC2G0 CTC2OUT0 CTC2CLK1 CTC2G1 CTC2OUT1 CTC2CLK2 CTC2G2 CTC2OUT2 HALFCLK V8W6CSN VARWAITN VDD PIN NO. I/O SIGNAL 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 — — I I I I I I I I O I/O I O O O I I I I I I O O — O O O O O O O O O O O O O O O O O — — GND GND INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INT SIO2BRK EXTFRAME FRAME VINT S8W4CSN SYSCLKN GND GND 44 VDD(+5V) (VDD = +5V) PIN NO. 40 35 30 25 VDD(+5V) GND 20 15 10 1 5 GND 175 176 VDD(+5V) 50 45 SIO2CTS SIO2DSR SIO2RXD SIOCLK SYSCLKN TEST0 - TEST3 DATAENN BURSTN LASTN RDN WRN ACKN RDCENN NC S8W3CSN1 S8W3CSN2 S8W3CSN3 S8W3CSN4 S8W3CSN5 S8W3CSN6 V8W3CSN FIFOREN1 FIFOREN2 FIFOREN3 FIFOREN4 FIFOWEN1 FIFOWEN2 FIFOWEN3 FIFOWEN4 FIFORCKN IOENN2 GND GND HDW-500 MMP2V2 IC CXD9013AR (SONY) C-MOS TIMING GENERATOR 38 A23 - 28 A0, A1 DATAENN BURSTN LASTN RDN WRN VARWAITN BEN0 - 3 RESETN SYSCLKN 21, 24 - 28 S-RAM INTERFACE 19, 20 39 40 - 43 150 165 - 168 151 169 - 172 152 FIFO (µPD42280) INTERFACE 173 SIOWRN 109 110 73 75 80 85 95 90 GND SIORDN SRAM1CS 72 70 SRAM2CS WRENNA - D FIFOREN1 - 4 115 GND 65 FIFOWEN1 - 4 GND FIFORCKN 153 155 154 131 15 - 18 156 CPU PERIPHERAL INTERFACE 47 14, 174 2 3 149 13 158 - 163 164 148 ADDRESS DECODER 130 118 119 37 D0 - 7 SIOBAN VDD (+3.3 V) 58 SIOCDN GND VDD (+3.3 V) 57 GND 60 100 108 59 SIO (µPD72001) INTERFACE 105 —TOP VIEW— PERIPHERAL INTERFACE BLOCK 29 - 36 ACKN RDCENN 120 IOENN, 2 60 RDENN WRENN EXTDENN S8W3CSN1 - 6 125 VDD (+3.3 V) GND V8W3CSN S8W4CSN GND VDD (+3.3 V) 55 V8W6CSN S16W2CSN S16W3CSN 130 50 FLASHCSN PERIPHERAL BLOCK 135 CTC2G0 - 2 SIOCLK SIO2CTS SIO2DSR PIO2P20 - 27 VDD (+3.3 V) 144 4, 7, 10 5, 8, 11 CTC 1 6, 9, 12 121, 124, 127 48 CTC 2 49 SIO 1 50 51 54 55 56 144 145 147 FRAME GEN HALF CLK GEN HDW-500 MMP2V2 CTC2OUT0 - 2 SIO BLOCK (BAUD RATE GEN) 52 53 122, 125, 128 146 129 37 CTC1OUT0 - 2 120, 123, 126 SIO 2 EXTFRAME NC PIO2P10 - 17 10 CTC1G0 - 2 CTC2CLK0 - 2 108, 109, 112 - 117 40 PIO2P00 - 07 1 CTC1CLK0 - 2 99 - 106 140 PIO1P20 - 27 35 36 PIO 2 PIO1P10 - 17 GND 90 - 97 45 PIO1P00 - 07 30 79 - 86 25 70 - 77 VDD (+3.3 V) GND PIO 1 GND GND 20 61 - 68 INT 15 143 GND INTERRUPT CONTROLLER 5 INTP0 - 7 135 - 142 (VDD = +3.3 V) SIO1TXD SIO1RXD SIO1INT SIO2TXD SIO2RXD SIO2INT SIO2BRK VINT FRAME HALFCLK PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 — I I I I I/O I/O I/O — I/O I/O I/O I/O I/O O O O — — I I O O O O O O O O — I O O O O O VDD IP SYCS IP SYSTRB IP SYSTAT 0 IP SYSTAT 1 BP SYSIO 0 BP SYSIO 1 BP SYSIO 2 GND BP SYSIO 3 BP SYSIO 4 BP SYSIO 5 BP SYSIO 6 BP SYSIO 7 OVSS 1 OP VAR 2458 OP REF 2458 VDD GND IP VCO 2458 IP RST5FRM OP LR 48K OP FS64 48K OP FS128 48K OP FS256 48K OP FS512 48K OVSS 2 OP VAR 2455 OP REF 2455 GND IP VCO 2455 OVDD1 OP LR 479K OP FS64 479K OP FS128 479K OP FS256 479K 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 O O O O O O O O — O O O O O I I I — — I O O O O O O O O O — O O O O O O OP FS512 479K OP AUDFRM OP CFINF OP CFRM0 OP CFRM1 OP H525 0 OP V525 0 OP F525 0 GND OP CKO 27M OP CKO 13M OVSS 3 OP VAR 27 OP REF 27 XSM XTST IP VCO 2700 VDD GND IP VCO 2703 OVDD 2 OP SYNC1125 0 OP SYNC1125 1 OP SYNC1125 2 OP SYNC1125 3 OP SYNC1125 4 OP SYNC1125 5 OP SYNC1125 6 OP SYNC1125 7 GND OP SYNC1125 8 OP SYNC1125 9 OP H1125 3 OP F1125 3 OP H1125 4 OP F1125 4 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 — O O O O O I O — O I O I O O O O — — O O I O O O O I O I — O O I O O O VDD OP H1125 5 OP F1125 5 OP H1125 6 OP F1125 6 OP CKO 46M IP TEST4 OP LOCK 46 GND OP CKO 56M IP TEST5 OP LOCK 56 IP TEST3 OP H1125 0 OP F1125 0 OP H1125 1 OP F1125 1 VDD GND OP H1125 2 OP F1125 2 IP PLLTEST OP CKO 74M OP CKO 37M OP CKO 18M OVSS 4 IP VCO 7425 OVDD 3 IP VCO 7418 GND OP VAR 74 OP REF 74 IP VARCMP 74 OP FRUN OP VARDADT 0 OP VARDADT 1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 O O O O O O O O — I I I I I O I I — — O I I I I I I I I I — O I I O — I OP VARDADT 2 OP VARDADT 3 OP VARDADT 4 OP VARDADT 5 OP VARDADT 6 OP VARDADT 7 OP VARDADT 8 OP VARDADT 9 GND IP SDI F IP SDI V IP SDI H IP SDI FLG IP SDI CK OVSS 5 IP CMP 1125 IP CMP 525 VDD GND SDO0 IP SUBCAR IP SDIA F IP SDIA V IP SDIA H IP SDIA CK IP TEST0 IP TEST1 IP TEST2 VPDEA GND OP LOCKAUD IP TEST6 IP TEST7 OVDD 4 NC IP RESET 2-35 IC CXD9008Q (FUJITSU)FLAT PACKAGE C-MOS DIGITAL ENCODER INPUT CADDR 0 - 2 CK 8FSC CK27 DD SCK DD START ICADDR 0 - 3 MODE DATA PAL/NTSC PB CF PB DATA 00 - 09 PB HD PB VD PB PARITY POWER ON RESET REF CF REF HD REF VD 99 110 120 GND 140 150 130 GND VDD(+3.3V) GND GND VDD(+3.3V) 160 GND 157 GND VDD(+3.3V) 156 —TOP VIEW— 98 GND 90 170 VDD(+3.3V) GND GND VDD(+3.3V) 80 180 VDD(+3.3V) GND GND VDD(+3.3V) OUTPUT ADD CHECK GND GND 59 58 VDD(+3.3V) GND 50 GND 40 GND VDD(+3.3V) GND 30 1 196 20 GND 10 190 VDD(+3.3V) GND 70 (VDD = +3.3V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I I I I I I — — I I I I I I I I I — I I I I I I I I O O — — I I I I I I O O O O PIN No. REF HD 41 REF VD 42 REF CF 43 T00 44 T01 45 T02 46 VDD 47 GND 48 POWER ON RESET 49 T26 50 PB DATA 09 51 PB DATA 08 52 PB DATA 07 53 PB DATA 06 54 PB DATA 05 55 PB DATA 04 56 PB DATA 03 57 GND 58 PB DATA 02 59 PB DATA 01 60 PB DATA 00 61 PB HD 62 PB VD 63 PB CF 64 PB PARITY 65 T03 66 WRADDR 67 RDADDR 68 VDD 69 70 GND 71 T06 72 T07 73 T08 74 T09 75 T10 76 T11 77 DDATA 9 78 DDATA 8 79 DDATA 7 80 DDATA 6 SIGNAL I/O SIGNAL — O O O O O O — O O — — O O O O I O O O O — O O O O O O I O O — — O I O O O O O GND DDATA 5 DDATA 4 DDATA 3 DDATA 2 DDATA 1 DDATA 0 T12 D1 HD DDCF 2 VDD GND DDCF 1 DDCF 0 DPRITY D2SYNC T13 VISC 0 VISC 1 VISC 2 VISC 3 GND VISC 4 VISC 5 VISC 6 VISC 7 VISC 8 VISC 9 T14 HSHIFT VSHIFT VDD GND CK 4FSC T15 CMPSTE 0 CMPSTE 1 CMPSTE 2 CMPSTE 3 CMPSTE 4 PIN No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 I/O SIGNAL — I I — — O O O O O I O O O — O O O O O O O I I — — I O O O O O O O O — O O I I * T04 R05 VDD GND CMPSTE 5 CMPSTE 6 CMPSTE 7 CMPSTE 8 CMPSTE 9 T16 CMPNTY 0 CMPNTY 1 CMPNTY 2 GND CMPNTY 3 CMPNTY 4 CMPNTY 5 CMPNTY 6 CMPNTY 7 CMPNTY 8 CMPNTY 9 T17 T18 VDD GND T19 CMPNTR 0 CMPNTR 1 CMPNTR 2 CMPNTR 3 CMPNTR 4 CMPNTR 5 CMPNTR 6 CMPNTR 7 GND CMPNTR 8 CMPNTR 9 T20 T21 PIN No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 I/O SIGNAL O O O O O O — — O O O O O I I I I I — I O O O O O O O O — — O O I O O I I I I — CMPNTB 0 CMPNTB 1 CMPNTB 2 CMPNTB 3 CMPNTB 4 CMPNTB 5 VDD GND CMPNTB 6 CMPNTB 7 CMPNTB 8 CMPNTB 9 CLAMP P T22 T23 CADDR 0 CADDR 1 CADDR 2 GND T24 BBRST 0 BBRST 1 BBRST 2 BBRST 3 BBRST 4 BBRST 5 BBRST 6 BBRST 7 VDD GND BBRST 8 BBRST 9 T25 FAIHD H.H MUTE ICADDR 0 ICADDR 1 ICADDR 2 ICADDR 3 GND PIN No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 I/O SIGNAL I O I I I I I I I — — I O O O O O O I I I — — O I I I I O O I I — I I I CK8FSC F4HD PAL/NTSC TSEL 1 TSEL 2 TSEL 3 MUTE/TSEL 4 TSEL 5 TSEL 6 VDD GND TSEL 7 DREF CF 0 DREF CF 1 DREF CF 2 DPB CF 0 DPB CF 1 DPB CF 2 T33 T34 T28 VDD GND WCK4FSC T27 DB START DD SCK MODE DATA STSDATA ADD CHECK T29 T30 GND CK27 T31 T32 BBRST 0 - 9 CK 4FSC CLAMP P CMPNTB 0 - 9 CMPNTR 0 - 9 CMPNTY 0 - 9 CMPSTE 0 - 9 DDATA 0 - 9 D PARITY D1 HD DDCF 0 DDCF 1 DDCF 2 DPB CF 0 - 2 DREF CF 0 - 2 F4 HD FAIHD H. H MUTE HSHIFT RDADDR STSDATA VSHIFT VISC 0 - 9 WCK 4FSC WRADDR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; SCH SETUP OF OUTPUT SIGNAL STANDARD CLOCK FOR 8fsc MODE STANDARD CLOCK FOR 27MHz MODE CLOCK FOR SERIAL COMMUNICATION BETWEEN MICROCOMPUTER STATUS PULSE FOR SERIAL COMMUNICATION BETWEEN MICROCOMPUTER ADDRESS AUTHORIZE DATA FOR SERIAL COMMUNICATION BETWEEN MICROCOMPUTER INITAL SETUP COLOR FRAME (3-BIT) OF IMAGE DATA IMAGE DATA HD OF IMAGE DATA VD OF IMAGE DATA PARITY BIT OF IMAGE DATA RESET TERMINAL COLOR FRAME OF REFERENCE HD OF REFERENCE VD OF REFERENCE ; CLOCK FOR SERIAL COMMUNICATION RECEIVE CHECK BETWEEN MICROCOMPUTER ; DIGITAL DATA FOR BLACK BURST ; 4fsc CLOCK AT 8fsc COUNT DOWN ; CLAMP PULSE ; COMPONENT B DIGITAL DATA ; COMPONENT R DIGITAL DATA ; COMPONENT Y DIGITAL DATA ; COMPONENT DIGITAL DATA ; IMAGE DATA AT D1 OUTPUT MODE, D2 DATA AT D2 OUTPUT MODE ; PARITY BIT FOR DIGITAL DATA ; HD OF 27MHz (PHASE AGREE WITH DDATA) ; ON THE BIT 0 OF COLOR FRAME AT D1 AND D2 OUTPUT MODE ; COLOR FRAME (3-BIT) AT D1 OUTPUT MODE ON THE BIT1 OF COLOR FRAME AT D2 OUTPUT MODE ; ON THE BIT2 OF COLOR FRAME AT D2 OUTPUT MODE ; PB CF DECODER DATA ; REF CF DECODER DATA ; HD MAKE OF 4fsc ; HD OF 27MHz SYNC PHASE AGREE WITH ANALOG DATA ; MAKE DATA FAIHD ; H SHIFT MODE ; FIFO READ ADDRESS MSB DATA FOR RATE CONVERT ; RESPONCE FOR SERIAL COMMUNICATION BETWEEN MICROCOMPUTER ; V SHIFT MODE ; VISC DIGITAL DATA ; 4fsc CLOCK FOR RATE CONVERT ; FIFO WRITE ADDRESS MSB DATA FOR RATE CONVERT * Connect Pin 81 to the ground. 2-36 HDW-500 MMP2V2 POWER ON RESET TSEL 4 CADDR 0 - 2 ICADDR 0 - 3 PAL/NTSC REF CF REF VD HEF HD CK27 STSDATA ADD CHECK MODE DATA DD START DD SCK PB PARITY PB VD PB CF PB HD PB DATA 09 - 00 3 136 - 138 9 167 4 1 156 - 159 163 3 2 1 194 189 190 188 186 187 25 23 24 22 11 - 17, 19 - 21 10 PB HD DEC CK6.75 R.C.F 3 BURST ROM 27MHz SYSTEM Address BF, BLK1 R. C. F PULS CK13.5 CK27 27 WRADDR D. F. & RATE CONV WCK 4fsc SYNC ROM T. G. C CK 4fsc 8fsc SYSTEM H SHIFT RDADDR 28 CK8FSC 161 T. G. B DELAY su R. C. F RATE CONV DPB CF DREF CF/VD DLY T. G. A MODE MODE GEN. V SHIFT V SHIFT DEC REF HD 4 3 PARALLEL TO SERIAL SERIAL TO PARALLEL P. C. SEP. T. G. DATA SEP MULTI WCK 6fsc SW 184 CK 4fsc HDW-500 MMP2V2 Y 162 F4HD 8fsc H SHIFT WCK 4FSC B-Y R-Y T. G. D VISC MUTE for CXD8382BQ BURST BLK BURST BLK B. F FORM COMPOSITE LEVEL CONV TAKE SYNC SYNC FORM COMPOSITE LEVEL CONV PEDESTAL COEFFI COMPONENT LEVEL CONV VISC MUTE 12 12 + 10 10 COMPONENT LEVEL CONV CONF I R CONF I B V SHIFT Address Address LALT SW BURST BLK SW OUT BLK SW REF CF OUT CF OUT SYNC VISC GATE VISC GATE BLK PLS SW 10 12 12 BLK 12 10 10 SW & ROUND 49 50 53 56 55 54 37 - 40, 42 - 47 3 CMPNTY 0-9 173 - 175 71 74 70 DREF CF 0 - 2 VSHIFT CK 4FSC HSHIFT 108 - 115, 117, 118 CMPNTR 0-9 CMPNTB 121 - 126, 0-9 129 - 132 92 - 94, 96 - 104 VISC 0-9 BBRST 0-9 CMPSTE 0-9 DDCF 2 DDCF 1 D2SYNC DPRITY DDATA 9-0 DDCF 0 D1 HD 155 H. M. MUTE 176 - 178 DPB CF 0 - 2 3 133 CLAMP P 154 FAIHE 10 10 10 58 - 61, 10 63 - 68 141 - 148, 10 151, 152 76 - 80, 10 86 - 90 10 CXD8382AQ (4/4) IC 2-37 IC CXD9003BR (SONY) C-MOS DOWN CONVERTER NC 130 129 135 140 VDD (+3.3 V) GND 145 150 160 155 VDD (+3.3 V) GND GND GND VDD (+3.3 V) 165 170 175 185 180 VDD (+3.3 V) 205 VDD (+3.3 V) GND 190 195 VDD (+3.3 V) GND 200 204 —TOP VIEW— 128 VDD (+3.3 V) GND 125 VDD (+3.3 V) VDD (+3.3 V) 120 GND VDD (+3.3 V) VDD (+3.3 V) GND 115 GND VDD (+3.3 V) 210 215 220 110 225 230 105 NC VDD (+3.3 V) GND GND VDD (+3.3 V) 100 NC 235 NC NC 240 95 NC NC GND VDD (+3.3 V) VDD (+3.3 V) GND 90 VDD (+3.3 V) VDD (+3.3 V) 85 GND VDD (+3.3 V) NC VDD (+3.3 V) GND 80 245 GND VDD (+3.3 V) 75 76 77 70 65 60 55 GND VDD (+3.3 V) 50 VDD (+3.3 V) 45 40 35 GND VDD (+3.3 V) 30 NC 25 GND VDD (+3.3 V) 20 15 10 5 1 255 256 GND VDD (+3.3 V) 250 (VDD = +3.3 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I I I I O I I I I I — — I I I I O I I I I I I — — I — I I O — O IP C9 IP C8 IP C7 IP C6 VDE1 IP C5 IP C4 IP C3 IP C2 IP C1 GND VDD IP C0 IP HDF IP HDH IP CLR SYS VDE2 IP PCONSEL IP SCONSEL IP SID0 IP SID1 IP SID2 IP CK 74 GND VDD IP CK 27 NC IP EXI H IP EXI F OP OCK 27 VDD OP OF 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 O O O O O — O O O O O O O — O O O O O — — O O O O O O O O O O O VS1 OP OV OP OH OP SUB9 OP SUB8 GND OP SUB7 OP SUB6 OP SUB5 OP SUB4 OP SUB3 OP SUB2 VS2 VDD OP SUB1 OP SUB0 OP MAIN9 OP MAIN8 OP MAIN7 GND VDD OP MAIN6 OP MAIN5 OP MAIN4 OP MAIN3 OP MAIN2 VS3 VDE3 OP MAIN1 OP MAIN0 OP OTEST0 OP OTEST1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 — — O O O O O O O O O O I I — — — I I I — I I I I — — I I — I I GND VDD OP OTEST2 OP OTEST3 OP OTEST4 OP OTEST5 OP OTEST6 VS4 VDE4 OP OTEST7 OP OTEST8 OP OTEST9 IP CFG IP XMM GND VDD NC IP TSEL0 IP TSEL1 IP TSEL2 VDD IP TSEL3 IP TSEL4 IP TSEL5 IP TSEL6 GND VDD IP TSEL7 IP TSEL8 NC IP TMUX0 IP TMUX1 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 I I I I I — — — I I I I I I I I I — — I I I I — I I I I — — I I IP TMUX2 IP TMUX3 IP TMUX4 IP TWE IP TIH GND VDD NC IP ITEST0 IP ITEST1 IP ITEST2 IP ITEST3 IP ITEST4 IP ITEST5 IP ITEST6 IP ITEST7 IP ITEST8 GND VDD IP ITEST9 IP ITEST10 IP ITEST11 IP ITEST12 VDD IP ITEST13 IP ITEST14 IP ITEST15 IP ITEST16 GND VDD IP ITEST17 IP ITEST18 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 — I I I I I I I I I — — I I I I I I I I I I I — — I I I I I — — NC IP EXI R0 IP EXI R1 IP EXI R2 IP EXI R3 IP EXI R4 IP EXI R5 IP EXI R6 IP EXI R7 IP EXI R8 GND VDD IP EXI R9 IP EXI G0 IP EXI G1 IP EXI G2 IP EXI G3 IP EXI G4 IP EXI G5 IP EXI G6 IP EXI G7 IP EXI G8 IP EXI G9 GND VDD IP EXI B0 IP EXI B1 IP EXI B2 IP EXI B3 IP EXI B4 VDD GND 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 I I I I I — O O O O O O O — O O O O O — — O O O O O O O O O O O IP EXI B5 IP EXI B6 IP EXI B7 IP EXI B8 IP EXI B9 GND OP FFRSTR OP FFREN OP FFRCK0 OP FFRCK1 OP FFRSTW OP FFWEN VS6 VDD OP FFWCK0 OP FFWCK1 OP EXO R0 OP EXO R1 OP EXO R2 GND VDD OP EXO R3 OP EXO R4 OP EXO R5 OP EXO R6 VS7 VDE5 OP EXO R7 OP EXO R8 OP EXO R9 OP EXO G0 OP EXO G1 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 — — O O O O O O O O O O O O — — O O O O — O O O O — — O O O I I GND VDD OP EXO G2 OP EXO G3 OP EXO G4 OP EXO G5 OP EXO G6 VS8 VDE6 OP EXO G7 OP EXO G8 OP EXO G9 OP EXO B0 OP EXO B1 GND VDD VDE7 OP EXO B2 OP EXO B3 OP EXO B4 VDD OP EXO B5 OP EXO B6 OP EXO B7 OP EXO B8 GND VDD OP EXO B9 OP EXTIE EN SDA IP SYIO0 IP SYIO1 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 I I I I I — — I — I — I — I — I I — — I I I I — I I I I — — I I IP SYIO2 IP SYIO3 IP SYIO4 IP SYIO5 IP SYIO6 GND VDD IP SYIO7 NC IP SCL NC IP STRB NC IP CS NC IP STAT0 IP STAT1 GND VDD IP Y9 IP Y8 IP Y7 IP Y6 VDD IP Y5 IP Y4 IP Y3 IP Y2 GND VDD IP Y1 IP Y0 2-38 HDW-500 MMP2V2 90 80 GND 105 110 115 GND VDD (+3.3 V) 125 VDD (+3.3 V) 130 VDD (+3.3 V) VDD (+3.3 V) GND 135 140 VDD (+3.3 V) 145 GND 150 GND 65 VDD (+3.3 V) GND VDD (+3.3 V) VDD (+3.3 V) 60 55 53 52 GND 50 45 GND 40 35 52 VDD (+3.3 V) GND GND VDD (+3.3 V) 208 1 GND 50 80 70 205 53 85 NC 30 VDD (+3.3 V) 200 60 55 45 40 GND VDD (+3.3 V) 35 30 GND VDD (+3.3 V) 25 VDD (+3.3 V) 20 15 10 5 1 GND 208 VDD (+3.3 V) 205 GND GND 90 VDD (+3.3 V) GND GND VDD (+3.3 V) 195 65 95 75 GND 190 70 GND VDD (+3.3 V) VDD (+3.3 V) VDD (+3.3 V) 185 75 VDD (+3.3 V) GND VDD (+3.3 V) 180 VDD (+3.3 V) GND GND VDD (+3.3 V) 195 200 85 VDD (+3.3 V) GND 25 190 175 100 GND VDD (+3.3 V) VDD (+3.3 V) VDD (+3.3 V) 185 GND 20 GND VDD (+3.3 V) 180 170 104 VDD (+3.3 V) VDD (+3.3 V) GND GND VDD (+3.3 V) GND GND VDD (+3.3 V) 15 175 95 165 VDD (+3.3 V) 170 VDD (+3.3 V) 10 VDD (+3.3 V) GND GND VDD (+3.3 V) 157 160 GND VDD (+3.3 V) 156 155 100 GND GND 105 110 115 GND VDD (+3.3 V) 120 125 VDD (+3.3 V) 130 135 VDD (+3.3 V) GND 104 5 165 VDD (+3.3 V) 160 GND VDD (+3.3 V) GND 157 140 —TOP VIEW— 145 C-MOS ERROR CORRECTION DECODER —TOP VIEW— 150 CXD9016AR (SONY) C-MOS VIDEO FILTER 156 155 CXD9014AR (SONY) 120 IC (VDD = +3.3 V) (VDD = +3.3 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 I I — I I I I I I — I I I I — I/O I/O I/O — I/O I/O I/O I/O I/O O — CD 1 CD 0 GND DATA EN SDI H SDI F REF 74F REF 46F OP ENABLE VDD CHIP SELECT STROBE STATUS 0 STATUS 1 GND SYS BUS 0 SYS BUS 1 SYS BUS 2 VDD SYS BUS 3 SYS BUS 4 SYS BUS 5 SYS BUS 6 SYS BUS 7 F GND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 — O O O O O O — O O O — O O O O — O O O O O O — O O VDD H CD 0 CD 1 CD 2 CD 3 CD 4 VDD CD 5 CD 6 CD 7 GND CD 8 CD 9 YD 0 YD 1 VDD YD 2 YD 3 YD 4 YD 5 YD 6 YD 7 GND YD 8 YD 9 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 O O O O O O O — — O O O O O O O O O O — — O O O O O OP FRAME OP SYNC EVEN OD 0 EVEN OD 1 EVEN OD 2 EVEN OD 3 EVEN OD 4 GND VDD EVEN OD 5 EVEN OD 6 EVEN OD 7 EVEN OD 8 EVEN OD 9 ODD OD 0 ODD OD 1 ODD OD 2 ODD OD 3 ODD OD 4 GND VDD ODD OD 5 ODD OD 6 ODD OD 7 ODD OD 8 ODD OD 9 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 — I I I I I — — I I I I I I I I I — — I I I I I I I VDD XSM XTST DUB FRAME DUB SYNC MST GND VDD DUB BD 0 DUB BD 1 DUB BD 2 DUB BD 3 DUB BD 4 DUB BD 5 DUB BD 6 DUB BD 7 DUB AD 0 GND VDD DUB AD 1 DUB AD 2 DUB AD 3 DUB AD 4 DUB AD 5 DUB AD 6 DUB AD 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 I O — I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O — O O O — O O O O O O — RST RESET VDD2 ADD0 GND BP AXRQ BP AXE BP AXD 0 BP AXD 1 BP AXD 2 BP AXD 3 VDD BP AXD 4 BP AXD 5 BP AXD 6 BP AXD 7 GND OP TRREF OP ACEF OP PBSYM VDD OP PBSYS OP SEG 0 OP SEG 1 OP SEG 2 OP SEG 3 OP ADERR GND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 — O O O O O O — O O O — I I I I — I/O I/O I/O I/O I/O I/O — I/O I/O VDD OP ADPO 0 OP ADPO 1 OP ADPO 2 OP ADPO 3 OP ADPO 4 OP ADPO 5 VDD OP ADPO 6 OP ADPO 7 OP ADPSTO GND IP SYCS CLK CKSY IP SYSTA 0 IP SYSTA 1 VDD BP SYIO 0 BP SYIO 1 BP SYIO 2 BP SYIO 3 BP SYIO 4 BP SYIO 5 GND BP SYIO 6 BP SYIO 7 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 I O O O O I I — — I I I I I — I I I I — — I I I I I IP SYRW OP SYRW OP ADOUT12 OP ADOUT34 OP AVSTO IP DEBUG IP VPD GND VDD IP JUMP IP REV IP FRAME IP FS CLK FS256 NC IP EESWPS IP EESWPM IP PBSWPS IP PBSWPM GND VDD IP SPINS 0 IP SPINS 1 IP SPINS 2 IP SPINS 3 IP SPINS 4 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 — I I I I I — — I I I I — I I I I — — I I I I I I — VDD IP SPINS 5 IP SPINS 6 IP SPINS 7 CLK CKSPS IP SPSTOS GND VDD CLK CKEEMY CLK CKEEMX IP EERFSY IP EERFSX GND IP EERFMY IP EERFMX CLK CKPBSY CLK CKPBSX GND VDD IP PBRFSY IP PBRFSX CLK CKPBMY CLK CKPBMX IP PBRFMY IP PBRFMX VDD PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 I I/O — I/O I/O I/O I/O I/O I/O — I/O I/O I/O I — I/O I/O I/O — I/O I/O I/O O O O — VPD SDR DATA 15 GND SDR DATA 14 SDR DATA 13 SDR DATA 12 SDR DATA 11 SDR DATA 10 SDR DATA 9 VDD SDR DATA 8 SDR DATA 7 SDR DATA 6 VREF GND SDR DATA 5 SDR DATA 4 SDR DATA 3 VDD SDR DATA 2 SDR DATA 1 SDR DATA 0 SDR DQM SDR WE SDR CK GND 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 — O O O O O O — O O O — O O O O — O O O I I I — I I VDD SDR CAS SDR CKE SDR RAS SDR CS SDR ADDR 11 SDR ADDR 10 VDD SDR ADDR 9 SDR ADDR 8 SDR ADDR 7 GND SDR ADDR 6 SDR ADDR 5 SDR ADDR 4 SDR ADDR 3 VDD SDR ADDR 2 SDR ADDR 1 SDR ADDR 0 ODD ID 9 ODD ID 8 ODD ID 7 GND ODD ID 6 ODD ID 5 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 I I I I I I I — — I I I I I I I I O O — — O O I I I ODD ID 4 ODD ID 3 ODD ID 2 ODD ID 1 ODD ID 0 EVEN ID 9 EVEN ID 8 GND VDD EVEN ID 7 EVEN ID 6 EVEN ID 5 EVEN ID 4 EVEN ID 3 EVEN ID 2 EVEN ID 1 EVEN ID 0 VS1 VDI1 GND VDD VS2 VDI2 IP HSYNC RESET PLLS 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 — I I I I I — — I I I I I I I I I — — I I I I I I I VDD SMCK CK46 CK74 YD 9 YD 8 GND VDD YD 7 YD 6 YD 5 YD 4 YD 3 YD 2 YD 1 YD 0 CD 9 GND VDD CD 8 CD 7 CD 6 CD 5 CD 4 CD 3 CD 2 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 I I — I I I I I I — I I O O — O O O — O I I — I/O I/O — IP SPSTOM CLK CKSPM GND IP SPINM 7 IP SPINM 6 IP SPINM 5 IP SPINM 4 IP SPINM 3 IP SPINM 2 VDD IP SPINM 1 IP SPINM 0 OP ECMONM 2 OP ECMONM 1 GND OP ECMONM 0 OP ECMONS 2 OP ECMONS 1 VDD OP ECMONS 0 IP MBSEL IP MRW VDD BP MDQ 15 BP MDQ 14 GND 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 — I/O I/O I/O I/O I/O I/O — I I/O I/O — I/O I/O I/O I/O — — I/O I/O O O O — O O VDD BP MDQ 13 BP MDQ 12 BP MDQ 11 BP MDQ 10 BP MDQ 9 BP MDQ 8 VDD IP MREF BP MDQ 7 BP MDQ 6 GND BP MDQ 5 BP MDQ 4 BP MDQ 3 BP MDQ 2 VDD GND BP MDQ 1 BP MDQ 0 OP MDQM OP MWE CLK CKM46 GND OP MCAS OP MCKE 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 O O — O O O O — — O O O O — O O O O I — — I I I O O OP MRAS OP MCS VDD OP MA 11 OP MA 10 OP MA 9 OP MA 8 GND VDD OP MA 7 OP MA 6 OP MA 5 OP MA 4 GND OP MA 3 OP MA 2 OP MA 1 OP MA 0 IP MINIT GND VDD IP CID 2 IP CID 1 IP CID 0 OP MCMON 2 OP MCMON 1 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 — O I I — I — — I O I I I O O O O — — O O O O O O O VDD OP MCMON 0 XTST XSM GND CLK CK46 GND VDD CLK CKT46 VDD1 ADD1 IP SELCK MST SMCK OP VDOUT 7 OP VDOUT 6 OP VDOUT 5 OP VDOUT 4 GND VDD OP VDOUT 3 OP VDOUT 2 OP VDOUT 1 OP VDOUT 0 OP VEOUT OP VSTO OP VFRAME HDW-500 MMP2V2 2-39 121 125 130 GND VDD (+3.3 V) 135 140 145 VDD (+3.3 V) GND VDD (+3.3 V) 150 160 GND VDD (+3.3 V) 165 GND VDD (+3.3 V) 170 175 70 VDD (+3.3 V) GND 60 (VDD = +3.3 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I I I I I — — I I I I O I I I I I — — I I I I I — O I I I — IP CAM IP VPD IP ITSI0 IP BRR0 7 IP BRR0 6 VDD GND IP BRR0 5 IP BRR0 4 IP BRR0 3 IP BRR0 2 OVDD1 1 IP BRR0 1 IP BRR0 0 IP SYNC0 IP XTST IP BRR1 7 VDD GND IP BRR1 6 IP BRR1 5 IP BRR1 4 IP BRR1 3 IP BRR1 2 VDD OVSS 1 IP BRR1 1 IP BRR1 0 IP SYNC1 GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I O O O O — O O I I I — — I I I I O I I I I I — — I I/O I/O I/O I/O CLK46S0 OVDD2 1 OP 47MFF OP 94MFF OP 47ML VDD OVSS 2 OP 94ML IP RSTSYS IP SMCK IP XSM VDD GND IP MST IP TSI2 IP TSI1 IP TSI0 OVDD1 2 IP RECINH IP SYSREF IP SYSCS IP SYSTBR IP SYSTAT 1 VDD GND IP SYSTAT 0 BP SYSBUS 0 BP SYSBUS 1 BP SYSBUS 2 BP SYSBUS 3 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 I PB AC SEL CONF 151 I PB BD SEL ADV 152 I PB AC SEL ADV 153 I IP REC BD SEL 154 I IP REC AC SEL 155 VDD 156 — GND 157 — O OP REC DATDN 158 O OP REC DATDP 159 O OP REC DATCN 160 O OP REC DATCP 161 OVDD2 5 162 O OVSS 9 O 163 O OP REC DATBN 164 O OP REC DATBP 165 O OP REC DATAN 166 O OP REC DATAP 167 VDD — 168 GND 169 — O OP REC CKON 170 O OP REC CKOP 171 OP MPXCKN 172 O OP MPXCKP 173 O NC 174 — VDD — 175 OVSS 10 176 O OP MPXON 177 O OP MPXOP 178 O OVDD2 6 179 O GND — 180 O O O O O — I I O I I — — O O O O O O O O O O — — O O O O O OP EE CKO1N OP EE CKO1P OVDD2 7 OP EE CKO0N OP EE CKO0P VDD EAN EXN OVSS 11 EXP EAP VDD GND OVDD2 8 OVSS 12 OP EE DATDN OP EE DATDP OP EE DATCN OP EE DATCP OP EE DATBN OP EE DATBP OP EE DATAN OP EE DATAP VDD GND OP RECEND OP RECENC OP RECENB OP RECENA OVDD2 9 2-40 65 61 55 1 240 60 GND VDD (+3.3 V) VDD (+3.3 V) GND 50 235 VDD (+3.3 V) GND VDD (+3.3 V) GND 61 55 50 VDD (+3.3 V) GND 45 VDD (+3.3 V) 40 GND 30 35 VDD (+3.3 V) 25 VDD (+3.3 V) GND 20 15 10 VDD (+3.3 V) GND 5 1 240 65 75 230 45 70 GND VDD (+3.3 V) VDD (+3.3 V) GND GND VDD (+3.3 V) VDD (+3.3 V) 75 230 80 VDD (+3.3 V) GND 225 40 GND VDD (+3.3 V) 90 85 35 80 VDD (+3.3 V) GND GND VDD (+3.3 V) 215 220 100 95 VDD (+3.3 V) GND GND 85 225 235 90 210 30 GND VDD (+3.3 V) 205 VDD (+3.3 V) 95 VDD (+3.3 V) GND 215 220 100 GND VDD (+3.3 V) 25 205 105 VDD (+3.3 V) GND 200 VDD (+3.3 V) GND GND VDD (+3.3 V) 115 110 195 20 VDD (+3.3 V) GND 200 GND VDD (+3.3 V) VDD (+3.3 V) GND 15 105 120 190 VDD (+3.3 V) GND 110 195 210 115 185 10 GND VDD (+3.3 V) VDD (+3.3 V) GND 190 181 5 120 GND VDD (+3.3 V) 180 121 125 130 GND VDD (+3.3 V) 135 140 145 VDD (+3.3 V) NC GND VDD (+3.3 V) 150 GND 160 155 VDD (+3.3 V) GND VDD (+3.3 V) VDD (+3.3 V) GND 181 185 165 —TOP VIEW— 170 C-MOS VIDEO PROCESSOR —TOP VIEW— 175 CXD9018BR (SONY) 180 CXD9015BR (SONY) C-MOS ERROR CORRECTION ENCODER 155 IC (VDD = +3.3 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL O OVSS 3 I/O BP SYSBUS 4 I/O BP SYSBUS 5 I/O BP SYSBUS 6 I/O BP SYSBUS 7 VDD — GND — IP AUDFP I IP 256FS I IP AUD1 I IP AUD0 I OVDD2 2 O IP FS I OP CHEN O OP MONEN O O OP MONSYNCB VDD — GND — OP TRSB O OP MONB 7 O OP MONB 6 O OP MONB 5 O OVDD2 3 O OP MONB 4 O OP MONB 3 O OP MONB 2 O OP MONB 1 O OP MONB 0 O VDD — GND — 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 I O I O I O I O I O — — O O O O O O O O O O O — — O O I I I PLL THROUGH OVDD2 4 IP TESTCK94M OVSS 4 IP TESTCK47M OVDD1 3 CLK47M 60H OVSS 5 CLK47M 59H OVSS 6 VDD GND OVDD1 4 OVSS 7 OP MONSYNCA OP TRSA OP MONA 7 OP MONA 6 OP MONA 5 OVSS 8 OP MONA 4 OP MONA 3 OP MONA 2 VDD GND OP MONA 1 OP MONA 0 IP F ERASEB IP F ERASEA PB BD SEL CONF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 O O O O O — — O O O O O O O O O O — — O O O O O — O O O O — MY WDATA 19 MY WDATA 18 MY WDATA 17 MY WDATA 16 MY WDATA 15 VDD GND MY WDATA 14 MY WDATA 13 MY WDATA 12 MY WDATA 11 MY WDATA 10 MY WDATA 9 MY WDATA 8 MY WDATA 7 MY WDATA 6 MY WDATA 5 VDD GND MY WDATA 4 MY WDATA 3 MY WDATA 2 MY WDATA 1 MY WDATA 0 VDD OMY H OMY F OMY PF MY WCKA GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 O O O O O — O I I/O I/O I/O — — I/O I/O I/O I/O I/O I I I I I — — I I I I I MY WCKB MY WR VDD2 1 MY RCKA MY RCKB VDD MY RR FIFO VSP SY BUS 7 SY BUS 6 SY BUS 5 VDD GND SY BUS 4 SY BUS 3 SY BUS 2 SY BUS 1 SY BUS 0 STATUS 1 STATUS 0 STROBE CHIP SELECT RESET VDD GND F H CD 0 CD 1 CD 2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 I I I I I — — I I I I I I I I I — — I I I I I I O O I I — — CD 3 CD 4 CD 5 CD 6 CD 7 VDD GND CD 8 CD 9 YD 0 YD 1 YD 2 YD 3 YD 4 YD 5 YD 6 VDD GND YD 7 YD 8 YD 9 CK74 SMCK MST VDD1 1 VSS 1 PLLS ICHK CK74 VDD GND 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 O O I I I I I I I I — — I I I I I I I I I I I — — I I I I I VSS 2 VDD1 2 ICHK F ICHK H ICHK CD 0 ICHK CD 1 ICHK CD 2 ICHK CD 3 ICHK CD 4 ICHK CD 5 VDD GND ICHK CD 6 ICHK CD 7 ICHK CD 8 ICHK CD 9 ICHK YD 0 ICHK YD 1 ICHK YD 2 ICHK YD 3 ICHK YD 4 ICHK YD 5 ICHK YD 6 VDD GND ICHK YD 7 ICHK YD 8 ICHK YD 9 IMY F IMY H PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 O O O O O — — I/O I/O I/O O O I/O I/O I/O I/O — — I/O I I/O I/O I/O O O I/O I/O I/O — — OVSS 13 EE REC AF SEL EE REC BF SEL EE REC CG SEL EE REC DH SEL VDD GND BP DQ 15 BP DQ 14 BP DQ 13 OVDD2 10 OVSS 14 BP DQ 12 BP DQ 11 BP DQ 10 BP DQ 9 VDD GND BP DQ 8 SDRAM VREF BP DQ 7 BP DQ 6 BP DQ 5 OVDD2 11 OVSS 15 BP DQ 4 BP DQ 3 BP DQ 2 VDD GND 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 I/O I/O O O O O O O O O — — O O O O O O O O O O O — — O O O O I BP DQ 1 BP DQ 0 OP LDQM OP UDQM OP WE OVDD2 12 OP SDRAMCLK OP CASN OP CKE OP RASN VDD GND OP CS OP ADDRESS 11 OP ADDRESS 10 OP ADDRESS 9 OP ADDRESS 8 OVSS 16 OP ADDRESS 7 OP ADDRESS 6 OP ADDRESS 5 OP ADDRESS 4 OP ADDRESS 3 VDD GND OP ADDRESS 2 OP ADDRESS 1 OP ADDRESS 0 OVSS 17 IP SDRAMINIT 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 I I I I I — — I I I I I I I I I I — — I I I I I — I I I I — MY RDATA 0 MY RDATA 1 MY RDATA 2 MY RDATA 3 MY RDATA 4 VDD GND MY RDATA 5 MY RDATA 6 MY RDATA 7 MY RDATA 8 MY RDATA 9 MY RDATA 10 MY RDATA 11 MY RDATA 12 MY RDATA 13 MY RDATA 14 VDD GND MY RDATA 15 MY RDATA 16 MY RDATA 17 MY RDATA 18 MY RDATA 19 VDD DOCK IN IRED IGREEN IBLUE GND 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 I I O O O — O O O O O — — O O O O O O O O O O — — O O O O O IINTEN IVOB CG H CG V CG ENEN VDD MONI CD 0 MONI CD 1 MONI CD 2 MONI CD 3 MONI CD 4 VDD GND MONI CD 5 MONI CD 6 MONI CD 7 MONI CD 8 MONI CD 9 MONI YD 0 MONI YD 1 MONI YD 2 MONI YD 3 MONI YD 4 VDD GND MONI YD 5 MONI YD 6 MONI YD 7 MONI YD 8 MONI YD 9 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 I I O O O — — O O O O O O O O O — — O O O O O O O O O O — — OUT ENABLE VP CD 0 CD 1 CD 2 VDD GND CD 3 CD 4 CD 5 CD 6 CD 7 CD 8 CD 9 YD 0 YD 1 VDD GND YD 2 YD 3 YD 4 YD 5 YD 6 YD 7 YD 8 YD 9 H F VDD GND 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 O I I O O O O O O O — — O O O O O O O O O O O — — O O O O O VDD2 2 XTST XSM DNC CD 0 DNC CD 1 DNC CD 2 DNC CD 3 DNC CD 4 DNC CD 5 DNC CD 6 VDD GND DNC CD 7 DNC CD 8 DNC CD 9 DNC YD 0 DNC YD 1 DNC YD 2 DNC YD 3 DNC YD 4 DNC YD 5 DNC YD 6 DNC YD 7 VDD GND DNC YD 8 DNC YD 9 DNC H DNC F DNC PF I/O SIGNAL HDW-500 MMP2V2 170 90 VDD (+3.3 V) GND GND VDD (+3.3 V) 180 VDD (+3.3 V) VDD (+3.3 V) GND VDD (+3.3 V) 185 195 VDD (+3.3 V) GND VDD (+3.3 V) VDD (+3.3 V) 60 55 53 GND 45 40 GND VDD (+3.3 V) 35 1 30 208 25 205 GND VDD (+3.3 V) GND VDD (+3.3 V) 200 65 52 50 GND 53 70 20 VDD (+3.3 V) 60 55 45 40 GND VDD (+3.3 V) 35 30 GND VDD (+3.3 V) 25 VDD (+3.3 V) 20 15 10 5 GND VDD (+3.3 V) 205 GND GND 80 75 GND GND VDD (+3.3 V) 85 VDD (+3.3 V) GND GND VDD (+3.3 V) 15 VDD (+3.3 V) 105 110 115 GND VDD (+3.3 V) 120 125 VDD (+3.3 V) 135 VDD (+3.3 V) GND 140 VDD (+3.3 V) 145 GND 150 VDD (+3.3 V) GND VDD (+3.3 V) 180 190 95 90 VDD (+3.3 V) GND VDD (+3.3 V) 70 65 1 175 10 75 208 100 170 VDD (+3.3 V) GND GND VDD (+3.3 V) 195 200 80 104 VDD (+3.3 V) GND GND VDD (+3.3 V) VDD (+3.3 V) 185 190 85 165 5 175 95 160 52 VDD (+3.3 V) GND GND VDD (+3.3 V) 157 50 100 GND GND 156 155 105 110 115 GND VDD (+3.3 V) 120 125 VDD (+3.3 V) 130 135 VDD (+3.3 V) GND 104 GND 165 VDD (+3.3 V) 160 GND VDD (+3.3 V) GND 157 140 —TOP VIEW— 145 C-MOS BIT REDUCTION ENCODER —TOP VIEW— 150 CXD9019AR (SONY) C-MOS VIDEO CONCEALMENT 156 155 CXD9017BR (SONY) 130 IC (VDD = +3.3 V) (VDD = +3.3 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 I I — O I/O I/O I/O I/O I/O — O I/O I/O I/O — I I/O I/O — O I/O I/O I/O I/O I/O — IP SYS STATUS 0 IP SYS STATUS 1 GND OVDD 0 BP SDRAM DAT 0 BP SDRAM DAT 1 BP SDRAM DAT 2 BP SDRAM DAT 3 BP SDRAM DAT 4 VDD OVSS 0 BP SDRAM DAT 5 BP SDRAM DAT 6 BP SDRAM DAT 7 GND IP SDRAM REF 0 BP SDRAM DAT 8 BP SDRAM DAT 9 VDD OVSS 1 BP SDRAM DAT 10 BP SDRAM DAT 11 BP SDRAM DAT 12 BP SDRAM DAT 13 BP SDRAM DAT 14 GND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 — I/O I/O I/O I/O I/O O — I/O I/O I/O — I/O I I/O I/O — O I/O I/O I/O I/O O — I/O I/O VDD BP SDRAM DAT 15 BP SDRAM DAT 16 BP SDRAM DAT 17 BP SDRAM DAT 18 BP SDRAM DAT 19 OVSS 2 VDD BP SDRAM DAT 20 BP SDRAM DAT 21 BP SDRAM DAT 22 GND BP SDRAM DAT 23 IP SDRAM REF 1 BP SDRAM DAT 24 BP SDRAM DAT 25 VDD OVSS 3 BP SDRAM DAT 26 BP SDRAM DAT 27 BP SDRAM DAT 28 BP SDRAM DAT 29 OVDD 1 GND BP SDRAM DAT 30 BP SDRAM DAT 31 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 O O O O O O O — — O O O O O O O O O O — — O O O O O OP SDRAM CS OP SDRAM RAS OVDD 2 OVSS 4 OP SDRAM CAS OP SDRAM WE OP SDRAM CKE GND VDD OP SDRAM DQM OP SDRAM CK OP SDRAM ADDR 0 OP SDRAM ADDR 1 OVDD 3 OVSS 5 OP SDRAM ADDR 2 OP SDRAM ADDR 3 OP SDRAM ADDR 4 OP SDRAM ADDR 5 GND VDD OP SDRAM ADDR 6 OP SDRAM ADDR 7 OP SDRAM ADDR 8 OP SDRAM ADDR 9 OVSS 6 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 — O O I I I — — I I I I O I I I I — — I I I I O O I VDD OP SDRAM ADDR 10 OP SDRAM ADDR 11 IP HD SYNC A IP Q INDEX A 0 IP Q INDEX A 1 GND VDD IP VIDEO A 0 IP VIDEO A 1 IP VIDEO A 2 IP VIDEO A 3 OVSS 7 IP VIDEO A 4 IP VIDEO A 5 IP VIDEO A 6 IP VIDEO A 7 GND VDD IP HD SYNC B IP Q INDEX B 0 IP Q INDEX B 1 IP VIDEO B 0 OVSS 8 OVDD 4 IP VIDEO B 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 I I — I I I I I I — I I I I — I I I — I I I I I I — IP TBUS10 IP TBUS11 GND IP TBUS12 IP TBUS13 IP TBUS14 IP TBUS15 IP TBUS16 IP TBUS17 VDD IP TBUS18 IP TBUS19 IP TBUS20 IP TBUS21 GND IP TBUS22 IP TBUS23 IP TBUS24 VDD IP TBUS25 IP TBUS26 IP TBUS27 IP TBUS28 IP TBUS29 IP TOMX0 GND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 — I I I I I I — I I I — I I I/O I/O — I/O I/O I/O I/O I/O O — I/O I VDD IP TOMX1 IP TOMX2 IP TOMX3 IP TSEL0 IP TSEL1 IP TSEL2 VDD IP TSEL3 IP CS IP STRB GND IP STAT0 IP STAT1 BI SYSIO0 BI SYSIO1 VDD BI SYSIO2 BI SYSIO3 BI SYSIO4 BI SYSIO5 BI SYSIO6 VD2 1 GND BI SYSIO7 MST 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 I I I O O O O — — O O O O O O O O O O — — O O O O O SDI SM SMCK VS1 1 OP TBUS0 OP TBUS1 OP TBUS2 GND VDD OP TBUS3 OP TBUS4 OP TBUS5 OP TBUS6 VS1 2 OP TBUS7 OP TBUS8 OP TBUS9 OP TBUS10 VD2 2 GND VDD OP TBUS11 OP TBUS12 OP TBUS13 OP TBUS14 OP TBUS15 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 — O O O O O — — O O O O O O O O O — — O O O O O O I VDD VS1 3 OP TBUS16 OP TBUS17 OP TBUS18 OP TBUS19 GND VDD SDO OP SEG P OP FRM P OP SYNC VD2 3 VD1 4 OP CVID0 OP CVID1 OP CVID2 GND VDD OP CVID3 OP CVID4 OP CVID5 OP CVID6 OP CVID7 VS1 5 VPD PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 I IP VIDEO B 2 131 I IP VIDEO B 3 132 133 — GND I IP VIDEO B 4 134 I IP VIDEO B 5 135 I IP VIDEO B 6 136 I IP VIDEO B 7 137 O OP FIFO WRST 138 139 O OVSS 9 140 — VDD O OP FIFO WCK A 141 O OP FIFO RCK A 142 O OP FIFO OE A 143 O OP FIFO WE A 144 145 — GND O OP FIFO RE A 146 O OP FIFO WCK B 147 O OP FIFO RCK B 148 149 — VDD O 150 OVSS10 O OP FIFO OE B 151 O OP FIFO WE B 152 O OP FIFO RE B 153 I IP CONCEAL CTL 0 154 I IP CONCEAL CTL 1 155 — 156 GND 157 — VDD I IP CONCEAL CTL 2 158 I IP OUTPUT MASK 159 I IP FREEZE CTL 0 160 I IP FREEZE CTL 1 161 I IP FREEZE CTL 2 162 O 163 OVSS 11 164 — VDD 165 O OP PLL FF O OP FIFO RRST 166 167 I SDI0 — 168 GND 169 I SDI1 170 O SDO0 171 O SDO1 172 I XSM 173 — VDD 174 O OVSS 12 175 I XTST I 176 SMCK I 177 MST I 178 IP OE I 179 IP VP — 180 GND O OP VIDEO 15 181 O OP VIDEO 14 182 O O O O O O O — — O O O O O O O O O O — — O O O O O OP VIDEO 13 OP VIDEO 12 OVSS 13 OP VIDEO 11 OP VIDEO 10 OP VIDEO 9 OP VIDEO 8 GND VDD OP VIDEO 7 OP VIDEO 6 OP VIDEO 5 OP VIDEO 4 OVSS 14 OP VIDEO 3 OP VIDEO 2 OP VIDEO 1 OP VIDEO 0 OP Q INDEX 3 GND VDD OP Q INDEX 2 OP Q INDEX 1 OP Q INDEX 0 OP HD SYNC OP SUB HD SYNC 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 — O I O I O — — O I O I I I/O I/O I/O I/O — — I/O I/O I/O O I/O I I VDD OVDD 5 IP CKL SEL OVSS 15 IP CLK74 OVDD PLL GND VDD OVSS PLL IP CKL46 OVDD6 IP SYSTEM RESET IP RAM INIT BP SYS DATA 7 BP SYS DATA 6 BP SYS DATA 5 BP SYS DATA 4 GND VDD BP SYS DATA 3 BP SYS DATA 2 BP SYS DATA 1 OVSS 16 BP SYS DATA 0 IP SYS CS IP SYS STROBE 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 O I/O — I/O I/O I/O I/O I/O O — I/O I/O I/O I — O I/O I/O — I/O I/O O I/O I/O I/O — VD2 4 BI EXT D15 GND BI EXT D14 BI EXT D13 BI EXT D12 BI EXT D11 BI EXT D10 VS1 6 VDD BI EXT D9 BI EXT D8 BI EXT D7 VREF IN GND VD2 5 BI EXT D6 BI EXT D5 VDD BI EXT D4 BI EXT D3 VS1 7 BI EXT D2 BI EXT D1 BI EXT D0 GND 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 — O I O I O O — O O O — O O O O — O O O O O O — O O VDD DIR OUT DIR IN VD2 6 IP EXT CLK VS1 8 OP EXT DQM VDD OP EXT WE VD2 7 OP EXT CK GND OP EXT CAS OP EXT RAS OP EXT CS2 OP EXT CS1 VDD OP EXT A11 OP EXT A10 OP EXT A9 OP EXT A8 OP EXT A7 OP EXT A6 GND OP EXT A5 OP EXT A4 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 O O O O O I I — — I I I I I I I I O I — — O O I O I VD2 8 OP EXT A3 OP EXT A2 OP EXT A1 OP EXT A0 IP IH IP VID0 GND VDD IP VID1 IP VID2 IP VID3 IP VID4 IP VID5 IP VID6 IP VID7 IP H SYNC VD1 1 CLK TST1 GND VDD VS1 9 VD1 2 CK VID VS1 10 CLR SYS 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 — I I O I O — — O I O O O O O O O — — I I I I I I I VDD CLK TST0 IP SEL OP SEL IP LOFFSEL OP LOCK GND VDD OP PLLFF IP TEN OP TIMX0 OP TIMX1 OP TIMX2 OP TIMX3 OP TBUS0 OP TBUS1 OP TBUS2 GND VDD IP TBUS3 IP TBUS4 IP TBUS5 IP TBUS6 IP TBUS7 IP TBUS8 IP TBUS9 HDW-500 MMP2V2 2-41 IC VDD (+3.3 V) GND 170 NC 175 180 VDD (+3.3 V) GND GND VDD (+3.3 V) NC VDD (+3.3 V) VDD (+3.3 V) 185 90 85 80 75 VDD (+3.3 V) GND GND VDD (+3.3 V) NC NC NC NC NC VDD(+3.3V) GND GND VDD(+3.3V) NC NC NC NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 190 95 NC NC NC NC NC GND VDD (+3.3 V) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND 100 GND GND NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 105 110 115 GND VDD (+3.3 V) 120 125 VDD (+3.3 V) 130 VDD (+3.3 V) GND 104 NC 165 VDD (+3.3 V) 160 GND VDD (+3.3 V) GND 157 135 —TOP VIEW— 140 —TOP VIEW— 145 C-MOS AUDIO DATA RATE CONVERTER 150 CXD9032R (SONY) C-MOS BIT REDUCTION DECODER 156 155 CXD9020BR (SONY) 195 GND VDD (+3.3 V) VDD (+3.3 V) 60 55 53 52 GND 50 45 40 GND VDD (+3.3 V) 35 30 GND VDD (+3.3 V) NC 25 NC VDD (+3.3 V) 20 15 5 1 GND 208 VDD (+3.3 V) 205 GND GND 10 200 65 VDD (+3.3 V) (VDD = +3.3 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 O O — O O O I I I — I I I I — O I I — I — I I I I — OP TBUS3 OP TBUS2 GND VD2 1 OP TBUS1 OP TBUS0 MMS 0 MMS 1 MMS 2 VDD MST SM SMCK SDI GND SDO MMS 3 VPD VDD MMS 4 NC IP CS IP STRB IP STAT0 IP STAT1 GND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 — — I/O I/O I/O I/O I/O — I/O I/O I/O — I I I I — I I I I I I — I I VDD NC BI SYSIO0 BI SYSIO1 BI SYSIO2 BI SYSIO3 BI SYSIO4 VDD BI SYSIO5 BI SYSIO6 BI SYSIO7 GND IP TEN IP TIMX0 IP TIMX1 IP TBUS0 VDD IP TBUS1 IP TBUS2 IP TBUS3 IP TBUS4 IP TBUS5 IP TBUS6 GND IP TBUS7 IP TBUS8 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 I I I I I I I — — I I I I I I I I I O — — O I O I I IP TBUS9 IP TBUS10 IP TBUS11 IP TBUS12 IP TBUS13 IP TBUS14 IP TBUS15 GND VDD IP TBUS16 IP TBUS17 IP TOMX0 IP TOMX1 IP TSEL0 IP TSEL1 IP TSEL2 IP TSEL3 IP TSEL4 OP PLLFF GND VDD OP LOCK IP LOFFSEL OP SEL IP SEL CLK TST0 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 — I O I O O — — I O — I I I I I I — — I I I I I I O VDD CLR SYS VS1 1 CK VID VS1 PLL VD1 PLL GND VDD CLK TST1 VD1 1 NC IP F0 F1 IP FRM P IP SYNC IP CERR IP CVID0 IP CVID1 GND VDD IP CVID2 IP CVID3 IP CVID4 IP CVID5 IP CVID6 IP CVID7 VS1 2 (VDD = +3.3V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I O O — I O O O O — I O O O O — F2LRCK LATCH2 LOAD NC DL1IN DL1TAP1 DL1TAP2 DL1TAP3 DL1TAP4 GND DL2IN DL2TAP1 DL2TAP2 DL2TAP3 DL2TAP4 NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I — — — I O I O — — I O I O — I DLBCK NC NC NC S4IN1 S4OUT1 S4IN2 S4OUT2 GND VDD S4IN3 S4OUT3 S4IN4 S4OUT4 NC S4BCK 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 — — — — — I O I O — I O I O — I NC NC NC NC NC F1IN1 F1OUT1 F1IN2 F1OUT2 GND F1IN3 F1OUT3 F1IN4 F1OUT4 NC F1BCK 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I O — — I O I O — — I O I O — I F1LRCK LATCH1 NC NC F2IN1 F2OUT1 F2IN2 F2OUT2 GND VDD F2IN3 F2OUT3 F2IN4 F2OUT4 NC F2BCK FORMAT CHANGE 1 38 F1IN1 40 F1IN2 43 F1IN3 45 F1IN4 SERIAL-TOPARALLEL CONVERTER PARALLELTO-SERIAL CONVERTER 39 41 44 46 50 F1OUT1 F1OUT2 F1OUT3 F1OUT4 LATCH1 48 F1BCK 49 F1LRCK FORMAT CHANGE 2 4-BIT SHIFTER 21 S4IN1 23 S4IN2 S4IN3 27 29 S4IN4 S4BCK 22 24 28 30 S4OUT1 S4OUT2 S4OUT3 S4OUT4 32 FORMAT CHANGE 3 PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 O I/O — I/O I/O I/O I/O I/O O — I/O I/O I/O I — O I/O I/O — O I/O I/O I/O I/O I/O — VD2 2 BI EXT D15 GND BI EXT D14 BI EXT D13 BI EXT D12 BI EXT D11 BI EXT D10 VS1 3 VDD BI EXT D9 BI EXT D8 BI EXT D7 VREF IN GND VD2 3 BI EXT D6 BI EXT D5 VDD VS1 4 BI EXT D4 BI EXT D3 BI EXT D2 BI EXT D1 BI EXT D0 GND 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 — O I O I/O O O — O O O — O O O O — O O O O O O — O O VDD DIR OUT DIR IN VD2 4 IP EXT CLK VS1 5 IP EXT DQM VDD IP EXT WE VD2 5 OP EXT CK GND OP EXT CAS OP EXT RAS OP EXT CS2 OP EXT CS1 VDD OP EXT A11 OP EXT A10 OP EXT A9 OP EXT A8 OP EXT A7 OP EXT A6 GND OP EXT A5 OP EXT A4 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 O O O O O I — — — O O O O O O O O O O — — O O O — O VD2 6 OP EXT A3 OP EXT A2 OP EXT A1 OP EXT A0 IP IH NC GND VDD OP VID7 OP VID6 OP VID5 OP VID4 VS1 6 VD2 7 OP VID3 OP VID2 OP VID1 OP VID0 GND VDD OP QI1 OP QI0 OP H SYNC NC VS1 7 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 — O O O O O — — O O O O O O O O O — — O O O O O O O VDD OP TBUS20 OP TBUS19 OP TBUS18 OP TBUS17 VD1 8 GND VDD OP TBUS16 OP TBUS15 OP TBUS14 OP TBUS13 VS1 8 OP TBUS12 OP TBUS11 OP TBUS10 OP TBUS9 GND VDD OP TBUS8 OP TBUS7 OP TBUS6 OP TBUS5 OP TBUS4 VD2 9 VS1 9 2-42 53 F2IN1 55 F2IN2 59 F2IN3 61 F2IN4 F2BCK F2LRCK DL1IN DLBCK DL2IN SERIAL-TOPARALLEL CONVERTER PARALLELTO-SERIAL CONVERTER 2 3 64 1 5 F2OUT1 F2OUT2 F2OUT3 F2OUT4 LATCH2 LOAD START PULSE GENERATOR DELAY LINE 64-BIT SHIFTER 6 64-BIT SHIFTER 7 64-BIT SHIFTER 17 11 54 56 60 62 64-BIT SHIFTER 8 64-BIT SHIFTER 9 12 64-BIT SHIFTER 13 64-BIT SHIFTER 14 64-BIT SHIFTER 15 DL1TAP1 DL1TAP2 DL1TAP3 DL1TAP4 DL2TAP1 DL2TAP2 DL2TAP3 DL2TAP4 HDW-500 MMP2V2 IC CXD9021AR (SONY) C-MOS VIDEO NOISE FILTER 130 129 135 140 VDD (+3.3 V) GND 145 150 160 155 VDD (+3.3 V) GND GND VDD (+3.3 V) 165 170 180 185 175 VDD (+3.3 V) 205 VDD (+3.3 V) GND 190 195 VDD (+3.3 V) GND 200 204 —TOP VIEW— 128 VDD (+3.3 V) GND 125 VDD (+3.3 V) VDD (+3.3 V) 120 GND VDD (+3.3 V) VDD (+3.3 V) GND 115 GND VDD (+3.3 V) 210 215 220 110 225 105 230 VDD (+3.3 V) GND GND VDD (+3.3 V) 100 235 95 240 NC GND VDD (+3.3 V) VDD (+3.3 V) GND 90 VDD (+3.3 V) VDD (+3.3 V) 85 GND VDD (+3.3 V) VDD (+3.3 V) 80 245 GND VDD (+3.3 V) GND 75 76 77 70 65 60 55 GND VDD (+3.3 V) 50 VDD (+3.3 V) 45 40 35 GND VDD (+3.3 V) 30 25 GND VDD (+3.3 V) 20 15 10 5 1 255 256 GND VDD (+3.3 V) 250 (VDD = +3.3 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I O I O O I/O I/O I/O I/O I/O — — I/O I/O I/O O O I I I I I I — — I I I I I — I ISYSCS OSYSRW ISYSRW OVSS 0 OVDD2 0 BSYSIOD 0 BSYSIOD 1 BSYSIOD 2 BSYSIOD 3 BSYSIOD 4 GND VDD BSYSIOD 5 BSYSIOD 6 BSYSIOD 7 OVSS 1 OVDD2 1 IHD SY IVIDEO0 0 IVIDEO0 1 IVIDEO0 2 IVIDEO0 3 IVIDEO0 4 GND VDD IVIDEO0 5 IVIDEO0 6 IVIDEO0 7 IVIDEO1 0 IVIDEO1 1 VDD IVIDEO1 2 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I I I I I — I I I I I/O I/O O — I/O I/O I/O I/O I/O — — I/O I/O I/O I/O I O O I/O I/O I/O I/O IVIDEO1 3 IVIDEO1 4 IVIDEO1 5 IVIDEO1 6 IVIDEO1 7 GND IQ INDEX0 0 IQ INDEX0 1 IQ INDEX1 0 IQ INDEX1 1 BSDIOD 0 BSDIOD 1 OVSS 2 VDD BSDIOD 2 BSDIOD 3 BSDIOD 4 BSDIOD 5 BSDIOD 6 GND VDD BSDIOD 7 BSDIOD 8 BSDIOD 9 BSDIOD 10 VREF0 OVSS 3 OVDD2 2 BSDIOD 11 BSDIOD 12 BSDIOD 13 BSDIOD 14 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 — — I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O O — — I/O I/O I/O I/O — O I I/O I/O — — I/O I/O I/O I/O O GND VDD BSDIOD 15 BSDIOD 16 BSDIOD 17 BSDIOD 18 BSDIOD 19 BSDIOD 20 OVSS 4 BSDIOD 21 BSDIOD 22 BSDIOD 23 BSDIOD 24 OVDD2 3 GND VDD BSDIOD 25 BSDIOD 26 BSDIOD 27 BSDIOD 28 VDD OVSS 5 VREF1 BSDIOD 29 BSDIOD 30 GND VDD BSDIOD 31 BSDIOD 32 BSDIOD 33 BSDIOD 34 OVSS 6 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 I/O I/O I/O I/O I/O — — I/O I/O I/O I/O O O I/O I/O I/O I/O — — I/O I O I/O — I/O I/O I/O I/O — — I/O I/O BSDIOD 35 BSDIOD 36 BSDIOD 37 BSDIOD 38 BSDIOD 39 GND VDD BSDIOD 40 BSDIOD 41 BSDIOD 42 BSDIOD 43 OVSS 7 OVDD2 4 BSDIOD 44 BSDIOD 45 BSDIOD 46 BSDIOD 47 GND VDD BSDIOD 48 VREF2 OVSS 8 BSDIOD 49 VDD BSDIOD 50 BSDIOD 51 BSDIOD 52 BSDIOD 53 GND VDD BSDIOD 54 BSDIOD 55 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 I/O I/O I/O I/O O O I/O I/O I/O I/O — — I/O I/O I/O I/O O O I/O I/O O I I/O — — I/O I/O I/O I/O O — O BSDIOD 56 BSDIOD 57 BSDIOD 58 BSDIOD 59 OVSS 9 OVDD2 5 BSDIOD 60 BSDIOD 61 BSDIOD 62 BSDIOD 63 GND VDD BSDIOD 64 BSDIOD 65 BSDIOD 66 BSDIOD 67 OVSS 10 OVDD2 6 BSDIOD 68 BSDIOD 69 OVSS 11 VREF3 BSDIOD 70 GND VDD BSDIOD 71 BSDIOD 72 BSDIOD 73 BSDIOD 74 OVSS 12 VDD OVSS 13 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 I/O I/O I/O I/O I/O — O I O O O O O — O O O O O — — O O O O O O O O O O O BSDIOD 75 BSDIOD 76 BSDIOD 77 BSDIOD 78 BSDIOD 79 GND OVDD2 7 ISDRW OSDRW OSDWE OSDCAS OSDRAS OVSS 14 VDD OSDCS OSDDQM OVSS 15 OSDCKB OSDCKA GND VDD OSDCKE OSDADD 0 OSDADD 1 OSDADD 2 OSDADD 3 OVSS 16 OVDD2 8 OSDADD 4 OSDADD 5 OSDADD 6 OSDADD 7 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 — — O O O O O O O O I I I I — — I I I O — O O O O — — O O O O O GND VDD OSDADD 8 OSDADD 9 OSDADD 10 OSDADD 11 OVSS 17 OVDD2 9 OLOCK PLL OVSS 18 XTST XSM SMCK MST GND VDD RESET IH VPD OFF PLL VDD OVSS 19 OHD SY OVIDEO0 0 OVIDEO0 1 GND VDD OVIDEO0 2 OVIDEO0 3 OVIDEO0 4 OVIDEO0 5 OVSS 20 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 O O O O O — — O O O O O O O O — I — — I I I I — I O I O — — O O OVDD2 10 OVIDEO0 6 OVIDEO0 7 OVIDEO1 0 OVIDEO1 1 GND VDD OVIDEO1 2 OVIDEO1 3 OVIDEO1 4 OVIDEO1 5 OVSS 21 OVDD2 11 OVIDEO1 6 OVIDEO1 7 NC ISTRB GND VDD ISTATUS 0 ISTATUS 1 TSEL PLL CKT46 VDD CKT74 OVSS 22 CKM46 OVSS PLL2 GND VDD OVDD1 PLL1 OVDD 1 HDW-500 MMP2V2 2-43 IC CXK1203AR (SONY) CXK1203AR-T4 EPM7032LC44-10 (ALTERA) C-MOS ERASABLE PLD C-MOS DIGITAL LINE MEMORY —TOP VIEW— —TOP VIEW— VDD(+5V) VDD(+5V) NC NC NC NC NC 4 5 7 8 9 D2 DOT2 D3 DOT3 D4 DOT4 D5 DOT5 D6 DOT6 11 21 DOT7 D8 DOT8 D9 DOT9 35 7 34 8 32 31 OEN PSW2 17 PSB0 14 13 PSW5 PSB1 PSW6 PSB2 44 43 42 41 40 43 1 39 44 38 2 9 37 4 10 GND 36 5 11 VDD(+5V) 35 27 12 34 13 33 14 32 15 VDD(+5V) 31 6 7 8 26 25 16 PSW4 15 1 28 PSW3 16 2 29 PSW1 18 3 24 17 23 9 11 12 13 14 GND 30 16 17 29 18 22 18 19 20 21 22 23 24 25 26 19 27 28 20 PSW7 21 PIN I/O No. 41 12 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (VDD = +5V) PIN PIN PIN PIN NO. I/O SIGNAL NO. I/O SIGNAL NO. I/O SIGNAL NO. I/O SIGNAL D0 D1 D2 D3 D4 GND D5 D6 D7 D8 D9 TINT AEN CLK DIN0 - DIN9 DOT0 - DOT9 N/P OEN PSB0 - PSB2 PSW0 - PSW7 SCLK TINT I I I I I I — I I I I I 25 26 27 28 29 30 31 32 33 34 35 36 I O O O O — O O O O O O OEN DOT9 DOT8 DOT7 DOT6 GND DOT5 DOT4 DOT3 DOT2 DOT1 DOT0 37 38 39 40 41 42 43 44 45 46 47 48 — — I I I I — — — — — — OE2/IN I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 24 25 26 27 28 29 31 32 33 34 36 37 38 39 40 41 N.C N.C AEN N/P SCLK CLK VDD N.C N.C N.C N.C N.C I I — I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O — I/O GCLK/IN GCLR/IN OE1/IN OE2/IN 4-9 11 - 14 16 - 21 I/O 16 SIGNAL PIN I/O No. GCLR/IN OE2/IN VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDD I/O 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O I/O I/O I/O I/O — — I/O I/O I/O I/O I/O I/O — I/O I/O SIGNAL PIN I/O No. SIGNAL I/O I/O — I/O I/O I/O I/O I/O I/O — I I I/O I/O VDD I/O I/O I/O I/O I/O I/O GND GCLK/IN OE1/IN 33 34 35 36 37 38 39 40 41 42 43 44 I/O I/O I/O I/O I/O GND VDD I/O I/O I/O I/O I/O I/O GND I/O I/O 43 1 44 2 I/O CONTROL BLOCK MACROCELL (1-16) 16 MACROCELL (17-32) PIA 16 16 24 - 29 31 - 34 36 - 41 I/O CONTROL BLOCK 16 I/O 16 26 - 29 31 - 36 BUFF DIN9 PSW7 PSW6 PSW5 PSW4 PSW3 PSW2 VDD PSW1 PSW0 PSB2 PSB1 PSB0 LINE MEMORY SELECT CLOCK VIDEO DATA INPUT VIDEO DATA OUTPUT NTSC/PAL/SECAM SELECT OUTPUT ENABLE DELAY STEP SELECT (1 BITxN) DELAY STEP SELECT (8 BITxN) CLOCK EDGE SELECT TEST 1-5 7 - 11 — DIN0 ; ; ; ; ; ; ; ; ; ; 13 14 15 16 17 18 19 20 21 22 23 24 OE1/IN 1 LINE MEMORY (1138 x 10bit) SMALL DELAY CONTROLLER BUFF 16 DOT0 16 — I I I I I — I I I I I I GCLR/IN (VDD = +5V) N/P AEN TINT SCLK 42 1 2 3 4 5 6 7 8 9 10 11 12 GCLK 33 PSW0 20 4 36 GND DOT1 D7 10 1 2 3 4 5 6 7 8 9 10 11 12 D1 5 VDD(+5V) 3 24 23 22 21 20 19 18 17 16 15 14 13 DOT0 VDD(+5V) NC NC GND 37 38 39 40 41 42 43 44 45 46 47 48 GND 2 D0 GND 36 35 34 33 32 31 30 29 28 27 26 25 6 1 DOT9 OEN PSB0 — 25 22-24 *ABOVE DIAGRAM SHOWS CONDITIONS BEFORE PROGRAMMING PSB2 ADDRESS COUNTER PSW7 N/P CLK 41 SCLK 12 ADDRESS MULTIPLEXER — PSW0 13 - 18 20, 21 TIMING CONTROLLER 42 TINT 40 39 AEN 2-44 HDW-500 MMP2V2 IC CXG8003Q (SONY) 1.5 Gbps OPTICAL INTERFACE TRANSMITTER —TOP VIEW— 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 (VTTL = +3.3 V, VDD = +1.2 V, VECL = _2 V, VSS = _5 V) 55 VSS (_5 V) VSS (_5 V) VSS (_5 V) VDD (+1.2 V) VDD (+1.2 V) GND GND GND GND VTTL (+3.3 V) 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND VTTL (+3.3 V) 56 58 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND GND VECL (_2 V) GND VTTL (+3.3 V) GND GND GND VECL (_2 V) VECL (_2 V) VTTL (+3.3 V) VDD (+1.2 V) VDD (+1.2 V) GND GND GND VTTL (+3.3 V) VTTL (+3.3 V) NC NC VDD (+1.2 V) VECL (_2 V) GND GND 59 61 62 64 65 67 68 70 71 73 74 76 77 79 80 2 3 25 24 33 32 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 13 14 15 16 39 53 INPUT IB ICLK74 ICLK74N ICNT0 - ICNT3 ID00 - ID19 IP IREF ISD TCLK148 TCLK148N XRST XTEST1 : : : : : : : : : : : : LD DRIVER BIAS CURRENT CONTROL PLL REFERENCE CLOCK (74.25 MHz) INVERTED PLL REFERENCE CLOCK (74.25 MHz) PARALLEL CLOCK DELAY CONTROL 20 BITS PARALLEL SIGNAL LD DRIVER PEAK CURRENT CONTROL LD DRIVER DUTY CONTROL LD DRIVER OUTPUT CONTROL EXTERNAL CLOCK (1.485 GHz) INVERTED EXTERNAL CLOCK (1.485 GHz) RESET SCRAMBLE/NRZ TO NRZI CONVERSION CONTROL OUTPUT OBM OCLK74E OCLK74EN OCLK74T OD ODN OP OPFDD OPFDU : : : : : : : : : LD DRIVER BIAS CURRENT MONITOR 74.25 MHz PARALLEL CLOCK (ECL LEVEL) INVERTED 74.25 MHz PARALLEL CLOCK (ECL LEVEL) 74.25 MHz PARALLEL CLOCK (LVTTL LEVEL) 1.485 Gbps SERIAL DATA INVERTED 1.485 Gbps SERIAL DATA LD DRIVER PEAK CURRENT LOWER SIDE OF THE PHASE COMPARATOR (PFD) UPPER SIDE OF THE PHASE COMPARATOR (PFD) 41 40 8 ID00 ID01 ID02 ID03 ID04 ID05 ID06 ID07 OP ID08 OP ID09 OBM ID10 OD ID11 ODN ID12 OCLK74T ID13 OCLK74E ID14 OCLK74EN ID15 OPFDU ID16 OPFDD 46 47 44 37 36 6 29 28 20 21 ID17 ID18 ID19 ICLK74 ICLK74N PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 — I I — — O I I — — — — I I I I — — — O VTTL ID18 ID19 GND VTTL OCLK74T XRST XTEST1 VDD VDD GND GND ICNT0 ICNT1 ICNT2 ICNT3 NC NC VDD OPFDU 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 O — — I I — — O O — — I I — — O O — I I OPFDD GND VECL ICLK74N ICLK74 VECL VECL OCLK74EN OCLK74E GND GND TCLK148N TCLK148 GND VECL ODN OD GND IREF IP 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I — — O — O O — — — — — I — I I — I I — IB VSS VSS OBM VSS OP OP GND GND GND VDD VDD ISD VTTL ID00 ID01 GND ID02 ID03 VTTL 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I I — I I — I I — I I — I I — I I — I I ID04 ID05 GND ID06 ID07 GND ID08 ID09 VTTL ID10 ID11 GND ID12 ID13 VTTL ID14 ID15 GND ID16 ID17 TCLK148 TCLK148N XRST ICNT0 ICNT1 ICNT2 ICNT3 IREF ISD IB IP IP IB XTEST1 40 41 53 ISD 39 IREF 8 XTEST1 46, 47 X9 + X 4 + 1 SCRAMBLE 20 : 1 MULTIPLEXER 20 ID00 - ID19 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80, 2, 3 NRZ NRZI CONV. SW 44 37 LOAD PULSE GEN. VARIABLE DELAY ÷ 20 13 - 16 ICNT0 - ICNT3 OP LDD 36 6 29 OBM OD ODN OCLK74T OCLK74E 25 ICLK74 28 PFD 24 ICLK74N 20 33 TCLK148 21 32 TCLK148N OCLK74EN OPFDU OPFDD 7 XRST CY7C199-20VC (CYPRESS)J-LEADED PACKAGE C-MOS 256K (32,768 x 8)-BIT STATIC RAM —TOP VIEW— 4 A9 5 24 A2 A10 6 23 A1 5 6 7 8 A11 7 22 OE A12 8 21 A0 A13 9 20 CE A14 10 19 D7 D0 11 18 D6 D1 12 17 D5 D2 13 16 D4 9 10 D5 A6 D6 A7 D7 INPUT GATE 16 17 18 19 A0 A1 A8 A2 A9 A3 A10 A4 A11 A5 A12 A6 A13 A7 A14 A8 A9 CE 20 WE 27 HDW-500 MMP2V2 15 D3 24 25 26 1 2 3 INPUT BUFFER 1024 x 32 x 8 ARRAY 4 5 11 - 13, 15 - 19 D0 - D7 OE CE 14 GND 23 22 WE A0 - A14 ; ; CE D0 - D7 ; ; OE ; WE 21 OUTPUT GATE 3 A5 15 SENSE AMPS 2 D4 ADDRESS INPUTS CHIP ENABLE DATA INPUTS / OUTPUTS OUTPUT ENABLE WRITE ENABLE OE 20 COLUMN DECODER 27 POWER DOWN 22 9 25 A3 A4 13 A14 A8 4 1 D3 8 26 A4 A3 12 10 A7 3 D2 A13 26 A2 11 7 25 D1 6 27 WE D0 A1 A12 24 A6 2 A0 A11 23 A10 VDD(+5V) 28 ROW DECODER 21 A5 1 2-45 IC CXG8004Q (SONY) 1.5 Gbps OPTICAL INTERFACE TRANSMITTER NC NC VSS (_5 V) VTTL (+3.3 V) GND VDD (+1.2 V) VDD (+1.2 V) GND GND NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VTTL (+3.3 V) GND 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 —TOP VIEW— NC NC GND VECL (_2 V) GND GND VTTL (+3.3 V) GND GND GND VTTL (+3.3 V) VTTL (+3.3 V) NC NC VDD (+1.2 V) VDD (+1.2 V) GND GND GND VTTL (+3.3 V) GND 3 OD01 2 OD02 80 OD03 79 OD04 77 OD05 76 OD06 74 OD07 73 INPUT ICNT0 - ICNT3 ID IDN TCLK148 TCLK148N XRST XTEST1 XTEST2 XTEST3 : : : : : : : : : PARALLEL CLOCK DELAY CONTROL 1.485 Gbps SERIAL DATA INVERTED 1.485 Gbps SERIAL DATA EXTERNAL CLOCK (1.485 GHz) INVERTED EXTERNAL CLOCK (1.485 GHz) RESET NRZI → NRZ CONVERSION AND DESCRAMBLER CONTROL TRS DETECTOR CONTROL CH/YH FLAG DETECTOR CONTROL OUTPUT OD00 - OD19 OCLK74E OCLK74EN OCLK74T OLT OLTN TRSFG : : : : : : : 20 BITS PARALLEL SIGNAL 74.25 MHz PARALLEL CLOCK (ECL LEVEL) INVERTED 74.25 MHz PARALLEL CLOCK (ECL LEVEL) 4.25 MHz PARALLEL CLOCK (LVTTL LEVEL) RETIMING DATA OF DISCRIMINATOR INVERTED DATA OF DISCRIMINATOR TRS DETECTOR OD08 71 OD09 70 OD10 68 13 ICNT0 OD11 67 14 ICNT1 OD12 65 15 ICNT2 OD13 64 16 ICNT3 OD14 62 33 TCLK148 OD15 61 32 TCLK148N OD16 59 37 ID OD17 58 36 IDN OD18 56 47 XRST OD19 55 XTEST1 46 44 46 XTEST1 NC VECL (_2 V) VECL (_2 V) NC NC VECL (_2 V) VDD (+1.2 V) GND NC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OD00 7 XTEST2 8 XTEST3 41 OCLK74T X9 + X4 + 1 DE- SCRAMBLER NRZI NRZ CONV. OCLK74E 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OLT OLTN 6 OCLK74EN 28 SW OLT 44 OLTN 41 TRSFG 53 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O SIGNAL — O O — — O I I — — — — I I I I — — — — VTTL OD01 OD00 GND VTTL OCLK74T XTEST2 XTEST3 VDD VDD GND GND ICNT0 ICNT1 ICNT2 ICNT3 NC NC VDD NC PIN NO. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O SIGNAL — — — — — — — O O — — I I — — I I — — — NC GND VECL NC NC VECL VECL OCLK74EN OCLK74E GND GND TCLK148N TCLK148 GND VECL IDN ID GND NC NC PIN NO. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DBX2151 (THAT) DBX2155 (DBX INC.) I/O SIGNAL O — — O — I I — — — — — O — O O — O O — OLTN NC NC OLT VSS XTEST1 XRST NC GND GND VDD VDD TRSFG VTTL OD19 OD18 GND OD17 OD16 VTTL PIN NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O SIGNAL O O — O O — O O — O O — O O — O O — O O OD15 OD14 GND OD13 OD12 GND OD11 OD10 VTTL OD09 OD08 GND OD07 OD06 VTTL OD05 OD04 GND OD03 OD02 XTEST2 XTEST3 ICNT0 - ICNT3 28 8 ID IDN 1 GC3 ISET 7 2-46 OCLK74T TRSEG 37 DISCRIMINATOR 36 DATA TCLK148 TCLK148N 4 VEE 8 CURRENT MODE AMP GAIN CELL BIAS CIRCUIT IDLING CURRENT CIRCUIT 5 I SET OCLK74EN CBR 3 VCC (+12V) 3 I IN OCLK74E 1.485 GHz HIGH-SPEED CLOCK 33 SP 32 —TOP VIEW— I OUT GC1 I IN GC2 GND 6 5 6 53 2 4 VARIABLE DELAY 4 13 - 16 1 3 29 ÷ 20 7 OD00 - OD19 EL2244CS-TE2 (ELANTEC INC.)FLAT PACKAGE —SIDE VIEW— 2 20 DUAL OPERATIONAL AMPLIFIERS (SINGLE-SUPPLY TYPE) VOLTAGE CONTROLLED AMP 1 1 : 20 SEPARATOR TIMING REF. DETECTOR (VTTL = +3.3 V, VDD = +1.2 V, VECL = _2 V, VSS = _5 V) 3, 2, 80, 79, 77, 76, 74, 73, 71, 70, 68, 67, 65, 64, 62, 61, 59, 58, 56, 55 8 4 VCC 8 _+ 7 +_ 6 5 TYPE 828 TYPE 2244 TYPE 2904 TYPE 3404 TYPE 3414 TYPE 4572 TYPE 5216 TYPE 7022 TYPE 75W01 TYPE 33172 TYPE OTHERS VCC - VEE +5 to +36V +2.5 to +36V +3 to +24V +4 to +32V +3 to +10V +4 to +14V +4 to +32V +3 to +16V +3 to +10V +3 to +44V +3 to +36V GC1 I OUT GC3 2 GC2 HDW-500 MMP2V2 IC EPM7032QC44-15 (ALTERA) EPM7032VTC44-12 (ALTERA) C-MOS ERASABLE PLD C-MOS ERASABLE PLD —TOP VIEW— GND VDD(+5V) VDD(+5V) 42 43 44 1 2 3 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 10 11 12 13 14 15 OE1/IN 34 35 36 37 38 39 40 41 42 43 44 OE2/IN I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 18 19 20 21 22 23 25 26 27 GND GND 40 39 GCLR/IN 38 22 21 20 19 18 17 16 15 14 13 12 VDD(+3.3V) GND VDD(+3.3V) VDD(+5V) GND 22 21 20 19 18 17 16 15 14 13 12 37 GCLK/IN VDD(+3.3V) GND 38 GND 39 40 41 42 43 44 1 2 3 5 6 7 28 8 30 10 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 37 GND VDD(+5V) 33 32 31 30 29 28 27 26 25 24 23 33 32 31 30 29 28 27 26 25 24 23 —TOP VIEW— 31 11 32 12 33 13 PD ; POWER-SAVER MODE 34 14 35 15 GCLK/IN GCLR/IN OE1/IN OE2/IN PD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 18 19 20 21 22 23 25 26 27 28 30 31 32 33 34 35 (VDD = +5V) PIN NO. 1 2 3 4 5 6 7 8 9 10 11 I/O SIGNAL I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDD I/O I/O PIN NO. 12 13 14 15 16 17 18 19 20 21 22 I/O SIGNAL I/O I/O I/O I/O — — I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDD I/O I/O I/O I/O I/O PIN NO. 23 24 25 26 27 28 29 30 31 32 33 I/O SIGNAL I/O — I/O I/O I/O I/O — I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDD I/O I/O I/O I/O PIN NO. 34 35 36 37 38 39 40 41 42 43 44 I/O SIGNAL I/O I/O — I I I I — I/O I/O I/O I/O I/O GND GCLK/IN OE1/IN GCLR/IN OE2/IN VDD I/O I/O I/O (VDD = +3.3V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDD I/O I/O 12 13 14 15 16 17 18 19 20 21 22 I/O I/O I/O I/O — — I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDD I/O I/O I/O I/O I/O 23 24 25 26 27 28 29 30 31 32 33 I/O — I/O I/O I/O I/O — I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDD I/O I/O I/O I/O 34 35 36 37 38 39 40 41 42 43 44 I/O I/O — I I I I I I/O I/O I/O I/O I/O GND GCLK/IN OE1/IN GCLR/IN OE2/IN PD I/O I/O I/O 37 GCLK/IN 39 GCLR/IN 38 OE1/IN 40 OE2/IN GCLK/IN GCLR/IN 42 - 44, 1 - 3, 5 - 8, 10 - 15 I/O CONTROL BLOCK I/O 16 16 MACROCELL (1-16) 36 36 MACROCELL (17 - 32) PIA 16 I/O CONTROL BLOCK OE1/IN OE2/IN I/O 39 38 40 42 - 44 1-3 5-8 10 - 15 16 I/O CONTROL BLOCK I/O 16 16 * ABOVE 16 18 - 23, 25 - 28, 30 - 35 37 16 16 DIAGRAM SHOWS CONDITIONS BEFORE PROGRAMMING PD 36 16 MACROCELL (1 - 16) 16 MACROCELL (17 - 32) PIA I/O CONTROL BLOCK 18 - 23 25 - 28 30 - 35 I/O 16 16 16 41 36 16 16 * ABOVE DIAGRAM SHOWS CONDITIONS BERORE PROGRAMMING GAL16LV8C-15LJ (LATTICE) GAL16V8B-25LP (LATTICE) C-MOS ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC DEVICE C-MOS ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC DEVICE —TOP VIEW— 19 I/O 7 20 1 CK 2 IN1 3 IN2 —TOP VIEW— VDD (+5V) CK 1 CK IN 1 (+5V) VDD IN4 5 IN5 6 18 I/O 6 19 17 I/O 5 18 2 16 I/O 4 14 I/O 2 IN 6 NOTE : TYPE GAL16LV GAL16V I/O 1 13 I/O 0 12 7 OE 11 IN8 9 10 GND 5 AND/OR LOGIC ARRAY 8 MACRO CELL 4 15 I/O 3 IN7 8 20 IN 1 2 19 I/O 7 19 IN 2 3 18 I/O 6 18 IN 3 4 17 I/O 5 IN 4 5 16 I/O 4 IN 5 6 15 I/O 3 IN 6 7 14 I/O 2 IN 7 8 13 I/O 1 IN 8 9 12 I/O 0 17 2 17 3 IN6 7 VDD (+5V) CK CK IN3 4 CK 1 20 16 I/O 15 14 9 IN 3 4 5 6 7 16 AND/OR LOGIC ARRAY MACRO CELL 8 9 14 13 13 12 12 VDD +5V +3.3V I/O 15 10 GND 11 OE IN OE 10 GND 11 OE OE 11 OE * ABOVE DIAGRAM SHOWS CONDITIONS BEFORE PROGRAMMING. HDW-500 MMP2V2 2-47 IC CXP80P624AQ-1 (SONY) CXP80P624AQ-1-008 (SONY) C-MOS 8-BIT MICROPROCESSOR 81 51 GND 55 VDD (+5 V) 60 65 70 75 80 —TOP VIEW— 50 85 45 90 GND VDD (+5 V) VDD (+5 V) GND 40 95 35 31 30 25 20 15 10 5 1 100 (VDD = +5 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O I/O I/O I/O I/O O O O O O O O O O I/O — O I I I O I/O I/O I/O I/O PD4 PD3 PD2 PD1 PD0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 MP RST GND XTAL EXTAL CSO SIO SOO SCKO PF7/AN11 PF6/AN10 PF5/AN9 PIN NO. I/O SIGNAL PIN NO. I/O 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 I/O — — — I I I I I I I I I I I I I I I I O O O O O PF4/AN8 GND VREF VDD PF3/AN7 PF2/AN6 PF1/AN5 PF0/AN4 AN3 AN2 AN1 AN0 PG7/EXI1 PG6/EXI0 PG5/SYNC1 PG4/SYNC0 PG3/PBCTL PG2/DPG PG1/DFG PG0/CFG PE7/DAB1 PE6/DAB0 PE5/DAA1 PE4/DAA0 PE3/PWM1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 O PE2/PWM0 I PE1/EC/INT2 PE0/INT0 I PI7/SI1 I/O PI6/SO1 I/O PI5/SCK1 I/O I/O PI4/INT1/NMI I/O PI3/TO/DDO/ADJ PI2/PWM I/O PI1/PO I/O PI0/PCK I PK0 I GND — VDD — VDD — PA7/PPO7 O PA6/PPO6 O PA5/PPO5 O PA4/PPO4 O PA3/PPO3 O PA2/PPO2 O PA1/PPO1 O PA0/PPO0 O PB7/PPO15 O PB6/PPO14 O SIGNAL INPUT AN0 - AN11 CFG CS0 DFG DPG EC EXI0, EXI1 EXTAL INT0 - INT3 MP PBCTL PCK PE0, PE1 PF0 - PF3 PG0 - PG7 PI0 PK0 SI0 SI1 SYNC0, SYNC1 : : : : : : : : : : : : : : : : : : : : ANALOG SIGNAL CAPSTAN FG SERIAL CHIP SELECT DRUM FG DRUM PG EXTERNAL EVENT EXTERNAL INPUTS FOR FRC CAPTURE UNIT CRYSTAL OSCILLATOR FOR SYSTEM CLOCK EXTERNAL INTERRUPT REQUEST MICROPROCESSOR MODE PLAYBACK CTL EXTERNAL CLOCK PORT E PORT F PORT G PORT I INPUT PORT SERIAL DATA SERIAL DATA COMPOSITE SYNC OUTPUT DAA0, DAA1 DAB0, DAB1 PA0 - PA7 PB0 - PB7 PE2 - PE7 PF4 - PF7 PH0 - PH7 PO PPO0 - PPO18 PWM PWM0, PWM1 RTO3 - RTO7 SO0, SO1 TO XTAL : : : : : : : : : : : : : : : D/A GATE PULSE D/A GATE PULSE PORT A PORT B PORT E PORT F PORT H GENERAL PURPOSE PRESCALER PROGRAMMABLE PATTERN GENERATOR 14-BIT PWM PULSE WIDTH MODULATION REAL TIME PULSE GENERATOR SERIAL DATA TIMER/COUNTER CRYSTAL OSCILLATOR FOR SYSTEM CLOCK INPUT/OUTPUT PC0 - PC7 PD0 - PD7 PI1 - PI7 PJ0 - PJ7 RST SCK0, SCK1 : : : : : : PORT C PORT D PORT I PORT J SYSTEM RESET SERIAL CLOCK DS90LV031TMX (NS)FLAT PACKAGE DS90LV032TMX (NS)FLAT PACKAGE C-MOS QUAD DIFFERENTIAL LINE DRIVER C-MOS QUAD DIFFERENTIAL LINE RECEIVER —TOP VIEW— —TOP VIEW— 16 DIN DOUT+ DOUT_ EN2 COUT_ COUT+ CIN 15 14 13 12 11 10 9 16 VDD VDD (+3.3V) (+3.3V) DIN_ DIN+ DOUT EN2 COUT CIN+ CIN_ 15 14 13 12 11 10 9 + _ + _ _ + _ + GND 1 2 3 4 5 6 7 AIN AOUT+ AOUT_ EN1 BOUT_ BOUT+ BIN EN2 1 INPUTS EN1 0 ALL OTHER COMBINATIONS OF ENABLE INPUTS 2-48 IN x L H OUTPUTS + _ HI-Z HI-Z L H H L GND 8 0 1 x HI-Z 1 2 3 4 5 6 7 AIN_ AIN+ AOUT EN1 BOUT BIN+ BIN_ ; ; ; ; LOW LEVEL HIGH LEVEL DON’T CARE HIGH IMPEDANCE EN2 1 INPUTS EN1 0 ALL OTHER COMBINATIONS OF ENABLE INPUTS IN+ - IN_ x VID ≥ 0.1V VID ≤ _0.1V FULL FAILSAFE OPEN/SHORT OR TERMINATED 8 OUTPUTS OUT HI-Z 1 0 1 0 1 x HI-Z ; ; ; ; LOW LEVEL HIGH LEVEL DON’T CARE HIGH IMPEDANCE HDW-500 MMP2V2 HDW-500 MMP2V2 PE7/DAB1 PE5/DAA1 PE3/PWM1 PE6/DAB0 PE4/DAA0 PE2/PWM0 P12/PWM PI1/PO PI0/PCK PG3/PBCTL PG2/DPG PG1/DFG PG0/CFG PG7/EXI1 PG6/EXI0 PG5/SYNC1 PG4/SYNC0 P13/TO PE1/EC P15/SCK1 P16/SO1 P17/SI1 SCK0 SO0 SI0 CS0 AN0 - AN3, PF0/AN4 - PF7/AN11 71 73 75 72 74 76 84 85 86 67 68 69 70 63 64 65 66 83 77 81 80 79 47 46 45 44 12 62 - 55, 51 - 48 FIF0 FIF0 SERVO INPUT CONTROL 12 BITS PWM GENERATOR (CH1) 12 BITS PWM GENERATOR (CH0) 14 BITS PWM GENERATOR PROGRAMMABLE PRESCALER CTL DRUM CAPSTAN V SYNC SEPARATOR 8 BITS TIMER 1 8 BITS TIMER/COUNTER 0 SERIAL INTERFACE UNIT (CH1) SERIAL INTERFACE UNIT (CH0) A/D CONVERTER 4 2 3 2 2 2 INTERRUPT CONTROLLER PE0/INT0 IPI4/INT1 PE1/INT2 78 82 77 98 - 96 PA0/PPO0 - PC2/PPO18 19 PROGRAMMABLE PATTERN GENERATOR FRC CAPTURE UNIT 2 RAM 96 BYTES FIF0 PROM 24 K BYTES SPC700 CPU CORE 11 - 7 CH1 PC3/RTO3 - PC7/RTO7 5 RST 40 RAM 704 BYTES PRESCALER/ TIME BASE TIMER REALTIME PULSE GENERATOR CH0 XTAL 42 MP 39 CLOCK GENERATOR/ SYSTEM CONTROL EXTAL 43 PORT K PORT J PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A 1 87 8 22 - 15 7 85 - 79 86 1 8 38 - 31 8 70 - 63 4 51 - 48 4 58 - 55 6 76 - 71 2 78, 77 8 30 - 23 8 14 - 7 8 6 - 1, 100, 99 8 98 - 91 PK0 PJ0 - PJ7 PI1 - PI7 PI0 PH0 - PH7 PG0 - PG7 PF4 - PF7 PF0 - PF3 PE2 - PE7 PE0, PE1 PD0 - PD7 PC0 - PC7 PB0 - PB7 PA0 - PO7 IC 2-49 IC EPM7064TC44-7 (ALTERA) HM62W8127HBJP-27Z (HITACHI)PLCC C-MOS EEPROM C-MOS 1M (131,072 x 8)-BIT STATIC RAM —TOP VIEW— 44 43 42 41 40 39 38 37 36 35 34 —TOP VIEW— GND VDD (+5 V) 39 1 2 3 4 5 6 7 8 9 10 11 38 GND VDD (+5 V) VDD (+5 V) GND GND VDD (+5 V) (VDD = +3.3V) 37 33 32 31 30 29 28 27 26 25 24 23 40 GCLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GCLR OE1 OE2 1 2 3 5 6 7 8 10 11 12 13 12 13 14 15 16 17 18 19 20 21 22 14 15 18 19 20 I/O (TDI) I/O I/O I/O I/O I/O I/O I/O I/O (TCK) I/O I/O (TMS) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (TD0) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 21 22 23 25 26 27 28 30 31 32 33 34 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD(+3.3V) GND GND VDD(+3.3V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 35 42 43 INPUT A0 - A16 44 CS OE WE (VDD = +5 V) PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O (TDI) I/O I/O GND I/O I/O I/O (TMS) I/O VDD I/O I/O 12 13 14 15 16 17 18 19 20 21 22 I/O I/O I/O I/O — — I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDD I/O I/O I/O I/O I/O 23 24 25 26 27 28 29 30 31 32 33 I/O — I/O I/O I/O I/O — I/O I/O I/O I/O I/O GND I/O I/O (TCK) I/O I/O VDD I/O I/O I/O I/O (TD0) 34 35 36 37 38 39 40 41 42 43 44 I/O I/O — I I I I — I/O I/O I/O I/O I/O GND GCLK1 OE1 GCLR OE2 VDD I/O I/O I/O ; ; ; ; ADDRESS INPUTS CHIP SELECT OUTPUT ENABLE INPUT WRITE ENABLE INPUT INPUT/OUTPUT I/O1 - I/O8 ; DATA INPUTS/OUTPUTS I/O SIGNAL I I I I I I/O I/O — — I/O I/O I I I I I A3 A2 A1 A0 CS I/O1 I/O2 VDD GND I/O3 I/O4 WE A16 A15 A14 A13 4 3 2 1 32 31 30 29 CS 1 0 0 0 OE X 1 0 X ; ; ; ; 0 1 X HI-Z MODE WE I/O HI-Z X NON SELECT 1 OUTPUT DISABLE HI-Z 1 OUTPUT READ 0 WRITE INPUT LOW LEVEL HIGH LEVEL DON’T CARE HIGH IMPEDANCE 21 20 19 18 17 16 15 14 13 PIN No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GLOBAL CLOCK GLOBAL CLEAR DATA INPUTS/OUTPUTS OUTPUT ENABLE 1 INPUT OUTPUT ENABLE 2 INPUT A4 GCLK1 GCLR OE1 OE2 37 A3 39 38 A2 40 LAB B LAB A 8 MACROCELLS 1-8 MACROCELLS 9 - 16 36 36 16 16 MACROCELLS 17 - 24 8 MACROCELLS 25 - 32 8 8 I/O CONTROL BLOCK 8 I/O CONTROL BLOCK A1 A0 8 A7 A6 A5 A12 A11 A10 A9 A8 I/O5 I/O6 VDD GND I/O7 I/O8 OE A7 A6 A5 A4 I/O1 A1 I/O2 A2 I/O3 A3 I/O4 A4 I/O5 A5 I/O6 A6 I/O7 A7 I/O8 6 7 10 11 22 23 26 27 A8 A9 A10 A11 A12 A13 A14 A15 A16 CS 12 : : : : : SIGNAL I I I I I I/O I/O — — I/O I/O I I I I I A0 WE GCLK1 GCLR I/O OE1 OE2 I/O 5 OE 28 32 1 2 3 ROW DECODER 4 MEMORY MATRIX 256 ROWS X 512 x 8 COLUMNS 29 30 31 PIA LAB D MACROCELLS 33 - 40 36 8 I/O8 *ABOVE DIAGRAM SHOWS CONDITIONS BEFORE PROGRAMMING. 6 COLUMN I/O INPUT DATA CONTROL COLUMN DECODER CS - 8 8 CS I/O1 - 16 MACROCELLS 57 - 64 8 - 16 MACROCELLS 49 - 56 - MACROCELLS 41 - 48 36 I/O CONTROL BLOCK 8 - 8 I/O CONTROL BLOCK LAB C WE CS OE 27 12 5 28 CS 16 17 18 13 14 15 19 20 21 A13 A12 A11 A16 A15 A14 A10 A9 A8 2-50 HDW-500 MMP2V2 IC HD63484CP8 (HITACHI) C-MOS ADVANCED CRT CONTROLLER 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 —TOP VIEW— DREQ VDD(+5V) DACK 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VDD(+5V) GND GND GND GND GND VDD(+5V) DONE 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 DMA CONTROL UNIT 10 8 REGISTER ADDRESS DRAWING PROCESSOR DATA IRQ INTERRUPT CONTROL UNIT 12 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 I/O — O O I I I I I/O O I I O O O — I/O — PIN No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SIGNAL VDD CUD1 CUD2 R/W CS RS RES DONE DREQ DACK DTACK IRQ HSYNC VSYNC VDD EXSYNC GND D0 MAD0 D1 MAD1 D2 MAD2 D3 MAD3 D4 MAD4 D5 MAD5 D6 MAD6 D7 MAD7 D8 MAD8 D9 MAD9 D10 MAD10 D11 MAD11 D12 MAD12 D13 MAD13 D14 MAD14 D15 MAD15 MA16/RA0 MA17/RA1 MA18/RA2 MA19/RA3 RA4 MCYC 8 10 11 4 DONE AS DACK DRAW DTACK MRD R/W CHR CUD1 5 6 53 CS RS 2CK CUD2 DISP1 DISP2 DREQ 7 68 RES LPSTB IRQ EXSYNC VSYNC HSYNC HDW-500 MMP2V2 65 64 63 62 61 51 50 49 48 I/O — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PIN No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 I/O — O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 16 DRAWING DATA GND RA4 MA19/RA3 MA18/RA2 MA17/RA1 MA16/RA0 MAD15 MAD14 MAD13 MAD12 MAD11 MAD10 MAD9 MAD8 MAD7 MAD6 MAD5 59 DRAW MRD MAD0 - MAD15 DISPLAY PROCESSOR 16 20 DISPLAY ADDRESS 40 - 37 5 RASTER ADDRESS 4 MA16/RA0 - MA19/RA3 CHR CRT INTERFACE CCUD 36 60 68 19 - 34 D0 - D15 2 MPU INTERFACE 3 2 SIGNAL 58 WRITE 65 - 61 51 - 41 16 SIGNAL DRAWING ADDRESS DRAW ENABLE 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 20 PIN No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 I/O — I — — O O O O O I/O I/O I/O I/O I/O O O I HSYNC 13 VSYNC 14 SIGNAL EXSYNC 16 VDD 2CK GND GND MCYC AS DRAW MRD CHR MAD4 MAD3 MAD2 MAD1 MAD0 DISP2 DISP1 LPSTB INPUT 2CK CS DACK DTACK LPSTB R/W RWS RS ; ; ; ; ; ; ; ; 2CLOCK CHIP SELECT DMA ACKNOWLEDGE DATA TRANSFER ACKNOWLEDGE LIGHT PEN STROBE READ/WRITE RESET REGISTER SELECT OUTPUT AS CHR CUD1, CUD2 DISP1, DISP2 DRAW DREQ HSYNC IRQ MA16 - MA19 MCYC MRD RA0 - RA4 VSYNC ; ; ; ; ; ; ; ; ; ; ; ; ; ADDRESS STROBE CHARACTER CURSOR DISPLAY DISPLAY TIMING DRAW DMA REQUEST HORIZONTAL SYNC INTERRUPT REQUEST MEMORY ADDRESS MEMORY CYCLE MEMORY READ RASTER ADDRESS VERTICAL SYNC CS RS R/W DTACK RES 5 2 CHR LPSTB CUD1 CUD2 GCUD (VDD = +5V) TIMING PROCESSOR RA4 67 DISP 66 6 MCLK 56 4 AS 57 11 2CLK 53 HSYNC VSYNC EXSYNC DISP1 DISP2 MCYC AS 2CK 7 L78M05T-FA (SANYO)+5 V 0.5 A L78M05T-FA-TL 47 46 45 44 43 42 41 40 39 38 37 36 56 57 POSITIVE VOLTAGE REGULATOR (2) 1 2 1 3 IN OUT 3 GND 2 58 59 60 2 3 67 INPUT/OUTPUT ; D0 - D15 ; DONE EXSYNC ; MAD0 - MAD15 ; DATA BUS DONE EXTERNAL SYNC MEMORY ADDRESS/DATA L79M05T-FA (SANYO)_5 V L79M05T-FA-TL NEGATIVE VOLTAGE REGULATOR 66 (2) 9 12 2 16 14 13 1 2 3 OUT IN 3 GND 1 2-51 IC HD63487CP (HITACHI) C-MOS MEMORY INTERFACE AND VIDEO ATTRIBUTE CONTROLLER 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 —TOP VIEW— MA OUTPUT CONTROL VDD(+5V) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND GND VDD(+5V) GND GND 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 6 - 10, 16, 19 - 28, MAD0 - MAD15 29 - 32 MA16 - MA19 L 56, 58 60, 62 63, 61 59, 57 55, 54 MPX FA0 - FA9 COLUMN ADDRESS COUNTER 13, 14, 12, 11, AS, MCYC 67, 64, DRAW, MRD 2, 1 VSYNC, HSYNC DISP1, CUD1 50, 49 53, 48 MEMORY CONTROL RAS, CS OE, WE L STATE DECODER 65 INCLK 15 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 2CLK INCLK 2CLK GENERATOR INCLK DIVIDER 3 MPX DOTCLK (VDD = +5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 I/O SIGNAL I I O O O I/O I/O I/O I/O I/O I I I I O I/O — CUD1 DISP1 DOTCLK VSYNC/2 SHFTEN MAD0 MAD1 MAD2 MAD3 MAD4 MRD DRAW AS MCYC 2CLK MAD5 GND PIN No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 I/O SIGNAL — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I O O GND MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 MA16 MA17 MA18 MA19 VIDEO A VIDEO B PIN No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 I/O SIGNAL — O O O I I/O I/O I/O I/O I/O I/O I/O I/O O O O — VDD V VIDEO C VIDEO D BL2IRQ IRQCLR FD4 FD7 FD5 FD6 FD0 FD3 FD1 FD2 WE CS RAS GND PIN No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 I/O SIGNAL — O O O O O O O O O O O I I I I — GND OE FA9 FA8 FA0 FA7 FA1 FA6 FA2 FA5 FA3 FA4 HSYNC INCLK TEST VSYNC VDD ATTRIBUTE LATCH VCF DECODER 6 7 8 9 10 16 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MAD0 FA0 MAD1 FA1 MAD2 FA2 MAD3 FA3 MAD4 FA4 MAD5 FA5 MAD6 FA6 MAD7 FA7 MAD8 FA8 MAD9 FA9 MAD10 MAD11 MAD12 MAD13 WE CS RAS OE 2 11 12 13 14 64 67 MAD15 FD0 MA16 FD1 MA17 FD2 MA18 FD3 MA19 FD4 CUD1 FD6 DISP1 FD7 15 DRAW VIDEO A AS VIDEO B MCYC VIDEO C HSYNC VIDEO D VSYNC INCLK VSYNC/2 2CLK SHFTEN BL2IRQ 66 60 62 63 61 59 57 55 54 48 49 INPUT DATA LATCH READ DATA LATCH LATCH CONTROL TEST 2-52 IRQCLR ADDRESS STROBE CURSOR DISPLAY DISPLAY TIMING DRAW HORIZONTAL SYNC MASTER CLOCK BL2IRQ CLEAR MEMORY ADDRESS MEMORY CYCLE MEMORY READ TEST VERTICAL SYNC OUTPUT 2CLK BL2IRQ CS DOTCLK FA0 - FA9 OE RAS SHFTEN VIDEO A - VIDEO D VSYNC/2 WE ; ; ; ; ; ; ; ; ; ; ; 2 CLOCK SETTED MA19 CHIP SELECT DOT CLOCK FRAME BUFFER ADDRESS OUTPUT ENABLE RAS TIMING FOR DRAM VIDEO SIGNAL OUTPUT ENABLE VIDEO SIGNAL HALF-VSYNC WRITE ENABLE INPUT/OUTPUT FD0 - FD7 MAD0 - MAD15 ; FRAME BUFFER DATA ; MEMORY ADDRESS/DATA MPX DISPLAY DATA LATCH SHIFTER 39 SHIFTER CLOCK ; ; ; ; ; ; ; ; ; ; ; ; FD0 - FD7 IRQCLR LATCH BL2IRQ 38 OUTPUT MULTIPLEXER 4 5 SKEW CURSOR/ BLINK MPX MASK 33, 34 36, 37 BL2IRQ VSYNC/2 SHFTEN VIDEO A, VIDEO B VIDEO C, VIDEO D 50 53 44 46 47 45 40 42 43 41 MRD DOTCLK 65 58 MAD14 FD5 1 56 44, 46 47, 45 40, 42 43, 41 MPX LATCH CONTROL INPUT AS CUD1 DISP1 DRAW HSYNC INCLK IRQCLR MA16 - MA19 MCYC MRD TEST VSYNC FD OUTPUT CONTROL 33 34 36 37 3 4 5 38 39 HDW-500 MMP2V2 IC IDT6116SA25S0 (INTEGRATED DEVICE TECHNOLOGY) IDT6116SA25SO-T IDT71024S20Y-TL (IDT) C-MOS 16K (2048 x 8)-BIT STATIC RAM —TOP VIEW— C-MOS 1M (128 x 8)BIT STATIC RAM —TOP VIEW— 12 8 A7 IN 1 VDD(+5V) 24 7 6 A6 IN 2 23 A8 IN 5 4 A5 IN 3 22 A9 IN 3 2 A4 IN 4 21 WE 1 5 20 OE 6 A1 D2 A2 D3 A3 D4 A4 D5 A5 D6 A6 D7 D8 1 NC 9 10 31 A15 IN A16 IN 2 11 13 14 A14 IN 3 30 CS2 IN A12 IN 4 29 WE IN 6 16 27 A7 IN 5 28 A13 IN A6 IN 6 27 A8 IN 8 23 A10 CE OE WE D2 I/O 10 15 D6 I/O 4 A5 IN 7 26 A9 IN D3 I/O 11 25 A11 IN 24 OE IN 29 A0 - A10 CE D1 - D8 OE WE 13 D4 I/O CONTROL INPUTS CE WE OE 1 X X 0 1 1 0 1 0 0 0 X ; ; ; ; ; ADDRESS INPUTS CHIP ENABLE INPUT DATA INPUTS / OUTPUTS OUTPUT ENABLE INPUT WRITE ENABLE INPUT MODE D1 - D8 STANDBY DISABLE OUTPUT FEAD WRITE A1 IN 11 22 CS1 IN A0 IN 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 HI-Z HI-Z OUTPUT INPUT 16 GND A1 A2 A6 A5 A4 A3 19 ROW DECODER 22 23 1 A4 A5 A6 BUFFER A7 2 A8 3 A9 4 A10 MEMORY MATRIX 128 x 128 A11 A12 A13 9 A3 A2 A1 A0 5 10 6 7 24 30 A0 I/O0 A1 I/O1 A2 I/O2 A3 I/O3 A4 I/O4 A5 I/O5 A6 I/O6 A7 I/O7 14 15 17 18 19 20 21 A8 A9 A10 A11 A12 A13 A14 A15 A16 WE OE CS1 CS2 INPUTS CS1 CS2 1 X X 0 0 1 0 1 0 1 WE X X 1 1 0 17 I/O3 13 1 0 X HI-Z ; ; ; ; OE X X 1 0 X I/O FUNCTION HI-Z STANDBY HI-Z STANDBY HI-Z OUTPUTS DISABLED DATA OUT READ DATA DATA IN WRITE DATA HIGH LEVEL LOW LEVEL DON'T CARE HIGH IMPEDANCE LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE A0 A7 23 A10 IN 22 FUNCTION TABLE A8 31 2 14 D5 I/O 12 GND A9 28 3 A2 IN 10 A10 25 17 D8 I/O 16 D7 I/O ; ; ; ; 26 18 CE 9 0 1 X HI-Z 5 17 A3 IN 9 D1 I/O 7 15 A4 IN 8 A0 IN 9 8 A9 19 A10 IN 7 11 10 18 20 21 A1 IN VDD(+5V) 32 A8 22 19 A2 IN D1 A7 23 A3 IN A0 BUFFER 8 11 I/O GATE COLUMN DECODER I/O BUFFER 13 14 15 16 17 A14 D1 D2 A15 A16 12 11 10 9 8 7 6 5 ADDRESS DECODER 27 26 1,048,576-BIT MEMORY ARRAY 23 25 4 28 3 31 2 D3 D4 D5 D6 I/O0 - I/O7 13 - 15 17 - 21 8 8 I/O CONTROLLER D7 D8 8 OE 20 BUFFER WE 21 WE OE CS1 CE 18 CS2 29 24 22 30 CONTROL LOGIC LM2903P (TI) NJM2903D (JRC) NJM2903M (JRC)FLAT PACKAGE NJM2903M-TE2 DUAL VOLTAGE COMPARATORS —TOP VIEW— 8 7 VCC (+2 to +36V) 6 5 _ + + _ 1 HDW-500 MMP2V2 2 3 GND 4 2-53 IC HD6415108RF10 (HITACHI) C-MOS 16-BIT MICROCOMPUTER UNIT —TOP VIEW— 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 (VDD = +5V) GND VDD(+5V) A-VDD(+5V) VDD(+5V) GND GND GND GND GND GND VDD(+5V) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 A-GND GND PIN NO. PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I/O I — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O — O O O O O O O O O O O O O O O O — I/O I/O I/O 2-54 EXPANSION MINIMUM MODE MODE 1 MODE 2 SIGNAL I/O SIGNAL RES I/O RES NMI I NMI GND — GND P10 I/O D0 P11 I/O D1 P12 I/O D2 P13 I/O D3 P14 I/O D4 P15 I/O D5 P16 I/O D6 P17 I/O D7 D8 I/O D8 D9 I/O D9 D10 I/O D10 D11 I/O D11 D12 I/O D12 D13 I/O D13 D14 I/O D14 D15 I/O D15 GND — GND A0 O A0 A1 O A1 A2 O A2 A3 O A3 A4 O A4 A5 O A5 A6 O A6 A7 O A7 A8 O A8 A9 O A9 A10 O A10 A11 O A11 A12 O A12 A13 O A13 A14 O A14 A15 O A15 GND — GND P20 I/O P20 P21 I/O P21 P22 I/O P22 I/O I/O I — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O — O O O O O O O O O O O O O O O O — O O O EXPANSION MAXIMUM MODE MODE 3 MODE 4 SIGNAL I/O SIGNAL RES I/O RES NMI I NMI GND — GND D0 I/O P10 D1 I/O P11 D2 I/O P12 D3 I/O P13 D4 I/O P14 D5 I/O P15 D6 I/O P16 D7 I/O P17 D8 I/O D8 D9 I/O D9 D10 I/O D10 D11 I/O D11 D12 I/O D12 D13 I/O D13 D14 I/O D14 D15 I/O D15 GND — GND A0 O A0 A1 O A1 A2 O A2 A3 O A3 A4 O A4 A5 O A5 A6 O A6 A7 O A7 A8 O A8 A9 O A9 A10 O A10 A11 O A11 A12 O A12 A13 O A13 A14 O A14 A15 O A15 GND — GND P20 O A16 P21 O A17 P22 O A18 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN NO. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O — — I I I I — — I/O I/O I/O I/O I/O I/O I/O I/O — I I — O O O O O O O — I I I I EXPANSION MINIMUM MODE MODE 1 MODE 2 SIGNAL SIGNAL I/O P23 P23 I/O P24 P24 I/O P25 P25 I/O P26 P26 I/O P27 P27 I/O GND GND — P30 / WAIT P30 / WAIT I/O P31 / BACK P31 / BACK I/O P32 / BREQ P32 / BREQ I/O P33 P33 I/O P34 P34 I/O P35 P35 I/O P36 P36 I/O P37 P37 I/O VDD VDD — P40 / ADTRG I/O P40 / ADTRG P41 / TMCI P41 / TMCI I/O P42 / TMRI P42 / TMRI I/O P43 / TMO P43 / TMO I/O P44 / FTI1 P44 / FTI1 I/O P45 / FTCI1 P45 / FTCI1 I/O P46 / FTI2 P46 / FTI2 I/O P47 / FTCI2 P47 / FTCI2 I/O GND GND — P50 / FTOA1 P50 / FTOA1 I/O P51 / FTOB1 P51 / FTOB1 I/O P52 / FTOA2 P52 / FTOA2 I/O P53 / FTOB2 P53 / FTOB2 I/O P54 P54 I/O P55 P55 I/O P56 P56 I/O P57 P57 I/O P60 P60 I/O P61 P61 I/O P62 P62 I/O P63 P63 I/O P64 P64 I/O P65 P65 I/O P66 P66 I/O P67 P67 I/O I/O O O O O O — I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O EXPANSION MINIMUM MODE MODE 1 MODE 2 SIGNAL I/O SIGNAL GND — GND A-GND — A-GND P70 / AN0 I P70 / AN0 P71 / AN1 I P71 / AN1 P72 / AN2 I P72 / AN2 P73 / AN3 I P73 / AN3 A-VDD — A-VDD VDD — VDD P80 / IRQ0 I/O P80 / IRQ0 P81 / IRQ1 I/O P81 / IRQ1 P82 / IRQ2 / SCK1 I/O P82 / IRQ2 / SCK1 P83 / IRQ3 / SCK2 I/O P83 / IRQ3 / SCK2 P84 / RXD1 I/O P84 / RXD1 P85 / TXD1 I/O P85 / TXD1 P86 / RXD2 I/O P86 / RXD2 P87 / TXD2 I/O P87 / TXD2 GND — GND EXTAL I EXTAL XTAL I XTAL GND — GND ø O ø E O E AS O AS RD O RD HWR O HWR LWR O LWR RFSH O RFSH VDD — VDD MD0 I MD0 MD1 I MD1 MD2 I MD2 STBY I STBY EXPANSION MAXIMUM MODE MODE 3 MODE 4 SIGNAL SIGNAL I/O A19 A19 O A20 A20 O A21 A21 O A22 A22 O A23 A23 O GND GND — P30 / WAIT P30 / WAIT I/O P31 / BACK P31 / BACK I/O P32 / BREQ P32 / BREQ I/O P33 P33 I/O P34 P34 I/O P35 P35 I/O P36 P36 I/O P37 P37 I/O VDD VDD — P40 / ADTRG I/O P40 / ADTRG P41 / TMCI P41 / TMCI I/O P42 / TMRI P42 / TMRI I/O P43 / TMO P43 / TMO I/O P44 / FTI1 P44 / FTI1 I/O P45 / FTCI1 P45 / FTCI1 I/O P46 / FTI2 P46 / FTI2 I/O P47 / FTCI2 P47 / FTCI2 I/O GND GND — P50 / FTOA1 P50 / FTOA1 I/O P51 / FTOB1 P51 / FTOB1 I/O P52 / FTOA2 P52 / FTOA2 I/O P53 / FTOB2 P53 / FTOB2 I/O P54 P54 I/O P55 P55 I/O P56 P56 I/O P57 P57 I/O P60 P60 I/O P61 P61 I/O P62 P62 I/O P63 P63 I/O P64 P64 I/O P65 P65 I/O P66 P66 I/O P67 P67 I/O I/O — — I I I I — — I/O I/O I/O I/O I/O I/O I/O I/O — I I — O O O O O O O — I I I I (VDD = +5V) EXPANSION MAXIMUM MODE MODE 3 MODE 4 SIGNAL I/O SIGNAL GND — GND A-GND — A-GND P70 / AN0 I P70 / AN0 P71 / AN1 I P71 / AN1 P72 / AN2 I P72 / AN2 P73 / AN3 I P73 / AN3 A-VDD — A-VDD — VDD VDD I/O P80 / IRQ0 P80 / IRQ0 I/O P81 / IRQ1 P81 / IRQ1 P82 / IRQ2 / SCK1 I/O P82 / IRQ2 / SCK1 P83 / IRQ3 / SCK2 I/O P83 / IRQ3 / SCK2 I/O P84 / RXD1 P84 / RXD1 I/O P85 / TXD1 P85 / TXD1 I/O P86 / RXD2 P86 / RXD2 I/O P87 / TXD2 P87 / TXD2 — GND GND I EXTAL EXTAL I XTAL XTAL — GND GND O ø ø O E E O AS AS O RD RD O HWR HWR O LWR LWR O RFSH RFSH — VDD VDD MD0 MD0 I MD1 MD1 I MD2 MD2 I STBY STBY I HDW-500 MMP2V2 111 IRQ0/P80 A14 IRQ1/P81 A15 SCK2/IRQ3/P83 MD0 RXD1/P84 MD1 TXD1/P85 MD2 TXD2/P87 EXTAL HDW-500 MMP2V2 107 RFSH 106 LWR 105 HWR 104 RD E 2 NMI ø 103 AS XTAL 1 RES 102 86 A13 112 STBY 99 101 85 89 90 91 92 93 94 95 96 RES SCK1, SCK2 P10/D0 P12/D2 P13/D3 P14/D4 P11/D1 4 5 6 7 8 P17/D7 P15/D5 9 11 D8 D10 D11 D12 D13 D14 D15 D9 12 13 14 15 16 17 18 19 10 PORT 2 ADDRESS BUS PORT 3 63 62 INPUTS OPERATION MODE MD2 MD1 MD0 CONTENTS 0 0 1 MODE 1 EXTENSION MINIMUM MODE (8BIT BUS) 0 1 0 MODE 2 EXTENSION MINIMUM MODE (16BIT BUS) 0 1 1 MODE 3 EXTENSION MAXIMUM MODE (8BIT BUS) 1 0 0 MODE 4 EXTENSION MAXIMUM MODE (16BIT BUS) 1 1 1 0 1 1 1 0 1 MODE 5 MODE 6 MODE 7 SINGLE CHIP MODE 61 PORT 4 AN3/P73 A12 RXD2/P86 98 DATA BUS PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 8 RESET SERIAL CLOCK (CH1, CH2) 60 59 58 57 56 PORT 8 PORT 7 PORT 6 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 P20/A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 P37 P36 P35 P34 P33 P32/BREQ P31/BACK P30/WAIT P47/FTCI2 P46/FTI2 P45/FTCI1 P44/FTI1 P43/TW0 P42/TMRI P41/TMCI P40/ADTRG PORT 5 65 AN2/P72 INPUT/OUTPUT D0 - D15 P10 - P17 P20 - P27 P30 - P37 P40 - P47 P50 - P57 P60 - P67 P80 - P87 49 P27/A23 P26/A22 FTOA1/P50 A11 84 66 110 ; ; ; ; ; ; ; ; ; ; 83 FTOB1/P51 AN1/P71 67 A10 FTOA2/P52 AN0/P70 50 47 68 A9 51 48 SERIAL COMUNICATION INTERFACE (x 2CH) A/D CONVERTER A8 SCK1/IRQ2/P82 109 80 TMO TXD1, TXD2 ø FTOB2/P53 P67 A7 79 8-BIT TIMER 69 P66 A6 78 52 P54 P65 A5 77 53 WAIT STATE CONTROLLER P55 P64 A4 76 ; ; ; ; ; ; ; 70 P63 HWR LWR RD RFSH 71 P62 A3 75 54 72 A2 74 26 21 P56 P61 FTOB1, FTOB2 ; 27 22 P57 A1 73 16-BIT FREE RUNNING TIMER (x 2CH) REFRESH CONTROLLER 73 36 P60 28 23 74 35 A0 72 29 24 P60 34 P57 30 25 P61 33 P56 P27/A23 71 INTERRUPT CONTROLLER P62 32 P26/A22 70 ADDRESS BUS ADDRESS STROBE BUS RIGHT REQUEST ACKNOWLEDGE ENABLE CLOCK FREE RUNNING TIMER OUTPUT COMPARE A (CH1, CH2) FREE RUNNING TIMER OUTPUT COMPARE B (CH1, CH2) HIGH WRITE LOW WRITE READ REFRESH CYCLE 8-BIT TIMER TRANSMISSION DATA (CH1, CH2) SYSTEM CLOCK 75 31 P55 P25/A21 69 ; ; AS ; BACK E ; FTOA1, FTOA2 ; 76 30 P54 2 P63 29 FTOB2/P53 P24/A20 RFSH P64 28 P23/A19 68 DTC 107 NMI OUTPUT A0 - A23 H8 / 500 CPU 106 LWR 77 27 FTOA2/P52 P22/A18 67 105 HWR 66 31 P65 26 FTOB1/P51 RD 78 25 FTOA1/P50 P21/A17 65 32 104 79 24 P20/A16 63 TMCI TMRI WAIT XTAL 102 E 33 P66 23 FTCI2/P47 P17/D7 62 STBY 34 P67 22 FTI2/P46 P16/D6 61 CLOCK GEN 101 ø 35 WATCH DOG TIMER 80 21 FTCI1/P45 99 XTAL AN0/P70 45 FTI1/P44 P15/D5 60 EXTAL 83 44 P14/D4 59 40 36 DATA BUS (LOW) 98 84 43 TMO/P43 P13/D3 58 103 AS 41 38 DATA BUS (HIGH) 112 85 42 TMRI/P42 MD0 - MD2 NMI P70 - P73 RXD1, RXD2 RE S STBY 42 39 AN1/P71 41 P12/D2 57 ; ; ; ; ; ; ; ; ; ; ADDRESS BUS 1 86 40 TMCI/P41 IRQ0 - IRQ3 MD0 AN2/P72 39 P11/D1 56 ; 109 AN3/P73 38 ADTRG/P40 FTCI1, FTCI2 110 89 11 P10/D0 54 44 PORT 1 DATA BUS 111 MD2 MD1 90 10 P37 53 IRQ0/P80 9 D15 52 91 8 P36 45 43 IRQ1/P81 7 P35 D14 EXTAL FTI1, FTI2 92 6 P34 D13 51 EXTERNAL TRIGGER ANALOG BUS RIGHT REQUEST CRYSTAL OSCILLATOR FREE RUNNING TIMER INPUT CAPTURE (CH1, CH2) FREE RUNNING TIMER COUNTER CLOCK (CH1, CH2) INTERRUPT REQUEST MODE SET UP NON-MASKABLE INTERRUPT PORT 7 RECEIVE DATA (CH1, CH2) STANDBY 8-BIT TIMER CLOCK 8-BIT TIMER COUNTER RESET WAIT CRYSTAL OSCILLATOR SCK1/IRQ2/P82 5 D12 50 ; ; ; ; ; BREQ 93 4 P33 AN0 - AN3 SCK2/IRQ3/P83 19 D11 ADTRG 49 94 18 BREQ/P32 INPUT 48 RXD1/P84 17 D10 47 95 16 BACK/P31 TXD1/P85 15 WAIT/P30 D9 96 14 D8 TXD2/P87 13 RXD2/P86 12 P16/D6 IC 2-55 IC HD6417032F20 (HITACHI) C-MOS 32-BIT RISC MICROCOMPUTER 90 AVSS 57 60 INPUT VSS 70 VSS VDD(+5V) VDD(+5V) 80 VDD(+5V) 85 VDD(+5V) 84 —TOP VIEW— ADTRG AN0 - AN7 BREQ DREQ0, 1 EXTAL IRQ0 - IRQ7 LBS MD0 - MD2 NMI RES RXD0, 1 TCLKA - TCLKD WAIT WR WRH WRL XTAL 56 VSS 50 AVDD(+5V) AVREF(+4.5 to AVDD) VSS 100 VDD(+5V) VDD(+5V) VSS 40 VDD(+5V) 30 29 28 VSS VSS 20 10 VSS 1 VSS VSS 110 112 VSS = GND AVSS = AGND 21 20 19 18 17 16 14 13 11 10 9 8 7 6 5 4 95 94 93 92 90 89 88 87 79 82 81 80 76 73 74 AD15 PA15/IRQ3/DREQ1 AD14 PA14/IRQ2/DACK1 AD13 PA13/IRQ1/DREQ0/TCLKB AD12 PA12/IRQ0/DACK0/TCLKA AD11 PA11/DPH/TIOCB1 AD10 PA10/DPL/TIOCA1 AD9 PA9/AH/IRQOUT/ADTRG AD8 PA8/BREQ AD7 PA7/BACK AD6 PA6/RD AD5 PA5/WRH(LBS) AD4 PA4/WRH (WR) AD3 PA3/CS7/WAIT AD2 PA2/CS6/TIOCB0 AD1 PA1/CS5/RAS AD0 PA0/CS4/TIOCA0 69 68 67 66 65 64 63 62 60 59 58 56 INPUT/OUTPUT 55 AD0 - AD15 DPH DPL PA0 - PA15 PB0 - PB15 PC0 - PC7 SCK0, 1 TIOCA0 - TIOCA4 TIOCB0 - TIOCB4 54 53 2 PB15/TP15/IRQ7 PC6/AN6 PB14/TP14/IRQ6 PC5/AN5 112 PB13/TP13/IRQ5/SCK1 PC4/AN4 111 PB12/TP12/IRQ4/SCK0 PC3/AN3 110 PB11/TP11/TXD1 PC2/AN2 109 PB10/TP10/RXD1 PC1/AN1 108 PB9/TP9/TXD0 PC0/AN0 107 PB8/TP8/RXD0 105 PB7/TP7/TOCXB4/TCLKD RES 104 PB6/TP6/TOCXA4/TCLKC MD2 103 PB5/TP5/TIOCB4 MD1 102 PB4/TP4/TIOCA4 MD0 101 PB3/TP3/TIOCB3 NMI 100 PB2/TP2/TIOCA3 98 1 EXTAL PB1/TP1/TIOCB2 XTAL 97 PB0/TP0/TIOCA2 WDTOVF 78 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (HBS) CK CS3/CASL CS2 CS1/CASH CS0 2-56 A0 (HBS) - A21 AH BACK CASH CASL CK CS0 - CS7 DACK0, 1 IRQOUT RAS RD TOCXA4 TOCXB4 TP0 - TP15 TXD0, 1 WDTOVF ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ADDRESS BUS ADDRESS HOLD BUS REQUEST ACKNOWLEDGE HIGH ORDER COLUMN ADDRESS STROBE LOW ORDER COLUMN ADDRESS STROBE SYSTEM CLOCK CHIP SELECT DMA ACKNOWLEDGE SLAVE INTERRUPT REQUEST ROW ADDRESS STROBE READ ITU OUTPUT COMPARE A (CH4) ITU OUTPUT COMPARE B (CH4) TIMING PATTERN TRANSMISSION DATA WATCHDOG TIMER OVERFLOW ; ; ; ; ; ; ; ; ; DATA BUS HIGH ORDER DATA BUS PARITY LOW ORDER DATA BUS PARITY PORT A PORT B PORT C SERIAL CLOCK ITU INPUT CAPTURE/OUTPUT COMPARE A (CH0 - 4) ITU INPUT CAPTURE/OUTPUT COMPARE B (CH0 - 4) 57 PC7/AN7 AVREF A/D CONVERSION TRIGGER ANALOG BUS REQUEST DMA REQUEST CRYSTAL OSCILLATION OR EXTERNAL CLOCK MASKABLE INTERRUPT REQUEST LOW BYTE STROBE MODE CONTROL NON-MASKABLE INTERRUPT REQUEST RESET RECEIVE DATA ITU TIMER CLOCK WAIT WRIGHT HIGH ORDER WRIGHT LOW ORDER WRIGHT CRYSTAL OSCILLATION OUTPUT A21 86 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 47 46 45 44 42 41 39 38 37 36 35 34 33 32 30 29 28 27 26 25 24 23 71 51 50 49 48 PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O — I/O I/O I/O I/O I/O I/O — O O O O O O O O — O O O O O O O SIGNAL PB14/TP14/IRQ6 PB15/TP15/IRQ7 VSS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS AD8 AD9 VDD AD10 AD11 AD12 AD13 AD14 AD15 VSS A0 (HBS) A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 PIN No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 I/O O — O O — O O O O O O O O — I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O — O — I I — I SIGNAL A15 VSS A16 A17 VDD A18 A19 A20 A21 CS0 CS1/CASH CS2 CS3/CASL VSS PA0/CS4/TIOCA0 PA1/CS5/RAS PA2/CS6/TIOCB0 PA3/CS7/WAIT PA4/WRL (WR) PA5/WRH (LBS) PA6/RD PA7/BACK VSS PA8/BREQ PA9/AH/IRQOUT/ADTRG PA10/DPL/TIOCA1 PA11/DPH/TIOCB1 PA12/IRQ0/DACK0/TCLKA PA13/IRQ1/DREQ0/TCLKB PA14/IRQ2/DACK1 PA15/IRQ3/DREQ1 VDD CK VSS EXTAL XTAL VDD NMI VDD = GND VDD = +5V AVSS = AGND AVDD = +5V AVREF = +4.5V to AVDD PIN I/O SIGNAL No. 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 — O I I I I — — — I I I I I — I I I I — I/O I/O — I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O VDD WDTOVF RES MD0 MD1 MD2 VDD VDD AVDD AVREF PC0/AN0 PC1/AN1 PC2/AN2 PC3/AN3 AVSS PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 VSS PB0/TP0/TIOCA2 PB1/TP1/TIOCB2 VDD PB2/TP2/TIOCA3 PB3/TP3/TIOCB3 PB4/TP4/TIOCA4 PB5/TP5/TIOCB4 PB6/TP6/TOCXA4/TCLKC PB7/TP7/TOCXB4/TCLKD VSS PB8/TP8/RXD0 PB9/TP9/TXD0 PB10/TP10/RXD1 PB11/TP11/TXD1 PB12/TP12/IRQ4/SCK0 PB13/TP13/IRQ5/SCK1 HDW-500 MMP2V2 WDTOVF MD2 MD1 MD0 NMI XTAL RES 79 78 82 81 80 76 71 73 74 CK EXTAL IC OSC. 112 PB13/TP13/IRQ5/SCK1 111 PB12/TP12/IRQ4/SCK0 PORT A 60 59 57 ADDRESS BUS PB14/TP14/IRQ6 62 58 DATA BUS (LOW) 1 DATA BUS (HIGH) 2 CPU 87 USER BREAK INTERRUPT CONTROLLER CONTROLLER 63 88 PB15/TP15/IRQ7 64 56 55 54 53 PA15/IRQ3/DREQ1 PA14/IRQ2/DACK1 PA13/IRQ1/DREQ0/TCLKB PA12/IRQ0/DACK0/TCLKA PA11/DPH/TIOCB1 PA10/DPL/TIOCA1 PA9/AH/IRQOUT/ADTRG PA8/BREQ PA7/BACK PA5/RD PA5/WRH (LBS) PA4/WRL (WR) PA3/CS7/WAIT PA2/CS6/TIOCB0 PA1/CS5/RAS PA0/CS4/TIOCA0 110 PB11/TP11/TXD1 108 PB9/TP9/TXD0 107 PB8/TP8/RXD0 105 PB7/TP7/TOCXB4/TCLKC 104 PB6/TP6/TOCXA4/TCLKC 103 PB5/TP5/TIOCB4 102 PB4/TP4/TIOCA4 101 PB3/TP3/TIOCB3 100 PB2/TP2/TIOCA3 DIRECT MEMORY ACCESS CONTROLLER PB10/TP10/RXD1 51 50 49 ADDRESS 98 PB1/TP1/TIOCB2 RAM 8K BYTES 109 BUS STATE CONTROLLER PC0/AN0 89 65 DATA BUS (16-BIT) SERIAL COMMUNICATION INTERFACE (2 CHANNEL) PC1/AN1 90 16-BIT INTEGRATED TIMER PULSE UNIT PC2/AN2 66 92 PROGRAMMABLE TIMING PATTERN CONTROLLER PC3/AN3 67 93 A/D CONVERTER PC4/AN4 68 WATCH DOG TIMER PC5/AN5 69 ADDRESS BUS (24-BIT) 94 PORT C PC6/AN6 PORT B PC7/AN7 95 97 PB0/TP0/TIOCA2 48 47 46 45 44 42 41 CS1/CASH CS0 A21 A20 A19 A18 A17 A16 38 37 39 A15 A14 A13 A12 35 36 A11 34 A9 A10 33 30 32 A8 A7 A6 28 27 29 A5 A4 A3 26 A2 24 23 25 A1 AD15 A0 (HSB) 20 19 18 17 21 AD14 AD13 AD12 AD11 16 CS2 ADDRESS AD10 AD9 11 13 14 AD8 AD7 9 8 7 6 5 10 AD6 AD5 AD4 AD3 AD2 AD1 AD0 4 DATA/ADDRESS CS3/CASL HM514402CZ-8 (HITACHI) C-MOS 4M (1,048,576 x 4)-BIT DYNAMIC RAM —SIDE VIEW— 11 - 20, 10 11 12 13 14 16 17 18 19 20 10 1 2 8 9 I/O3 A3 I/O4 7 3 4 A4 INPUT A0 - A9 CS OE RAS WE ; ; ; ; ; ROW ADDRESS BUFFER ROW DECODER & PERIPHERAL CIRCUIT 256K ROW MEMORY DRIVER ARRAY MATRIX I/O BUS & COLUMN DECODER A8 IN 18 19 20 A7 IN 15 16 17 A6 IN 13 14 A5 IN 12 A4 IN 10 11 A3 IN 9 A2 IN 8 A1 IN I/O4 I/O2 A2 6 7 A0 IN I/O3 I/O1 A1 6 A9 IN CS IN A0 5 RAS IN 4 I/O2 3 WE IN 2 I/O1 1 OE IN GND VDD(+5V) A0 - A9 6, 7, 3, 4 BUFFER I/O1 - I/O4 256K ROW MEMORY DRIVER ARRAY MATRIX ADDRESS CHIP SELECT OUTPUT ENABLE ROW ADDRESS STROBE READ/WRITE ENABLE COLUMN ADDRESS BUFFER I/O BUS & COLUMN DECODER A5 A6 A7 INPUT/OUTPUT I/O1 - I/O4 ; DATA OE A8 CS A9 WE RAS 1 2 8 CONTROL CIRCUIT 9 OE CS WE RAS HDW-500 MMP2V2 2-57 IC LC3564SM-70-TLM (SANYO)FLAT PACKAGE LM2577T-ADJ (NS) C-MOS 64K (8192 x 8)-BIT STATIC RAM STEP-UP AND FLYBACK SWITCHING REGULATOR —TOP VIEW— —TOP VIEW— 10 VDD (+5V) 1 NC 28 9 8 A12 2 27 WE 7 6 A7 3 26 CE2 5 4 A6 4 25 A8 3 25 A5 5 24 A9 A4 6 23 A11 24 21 23 2 A3 7 22 OE A2 8 21 A10 A1 9 20 CE1 A0 10 19 I/O 8 I/O 1 11 18 I/O 7 I/O 2 12 17 I/O 6 I/O 3 13 16 I/O 5 A0 A1 A2 I/O 1 A3 I/O 2 A4 I/O 3 A5 I/O 4 A6 I/O 5 A7 I/O 6 A8 I/O 7 A9 I/O 8 11 12 13 15 16 COMP (1) 17 FEED BACK (2) 18 19 GND (3) UIN (5) SWITH (4) A10 UIN 5 A11 SWITCH 4 A12 CURRENT LIMIT THRMAL LIMIT AND UNDERVOLTAGE SHUTDOWN OE WE CE1 CE2 22 27 20 26 A0 - A12 ; ADDRESS INPUTS CE1, CE2 ; CHIP ENABLE INPUT I/O 1 - I/O 8 ; DATA INPUT/OUTPUT ; OUTPUT ENABLE INPUT OE ; WRITE ENABLE INPUT WE 2.5V REGULATOR DRIVER STAGE LOGIC 52 kHz OSCILLATOR + 14 GND + ∑ A5 A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 A3 A4 OE X X 1 0 X WE X X 1 1 0 MODE NOT SELECT NOT SELECT OUTPUT DISABLE READ WRITE WE CE1 CE2 2 FEED BACK + 1.23V REF I/O TERMINAL HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE OUTPUT DATA INPUT DATA 1 COMP 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE 3 5 4 3 25 BUFFER 24 ROW DECODER 21 LM311PS (TI)FLAT PACKAGE LM311PS-E05 MEMORY MATRIX 256 x 256 VOLTAGE COMPARATOR WITH STROBE 23 —TOP VIEW— 2 1 GND 10 19 9 8 I/O GATE COLUMN DECODER BUFFER 7 18 17 6 I/O BUFFER 16 15 13 OE AMP _ SOFT START CE1 CE2 X 1 X 0 0 1 0 1 0 1 + _ 15 I/O 4 12 22 11 BUFFER 27 I/O 8 V+ 8 IN + 2 + 7 OUT IN _ 3 _ 6 BALANCE STROBE I/O 7 I/O 6 I/O 5 I/O 4 4 V_ 5 BALANCE I/O 3 I/O 2 I/O 1 20 26 LM324NS (TI)FLAT PACKAGE LM324NS-E05 QUAD OPERATIONAL AMPLIFIERS LM1881M (NS)FLAT PACKAGE LM1881MX —TOP VIEW— OUT IN_ IN+ 13 12 14 VIDEO SYNC SEPARATOR —TOP VIEW— (+5 to +12V) VCC C 8 COMPOSITE VIDEO IN 2 7 VERTICAL 3 SYNC OUT 6 RSET 5 BURST/BACK 2 COMPOSITE VIDEO ODD/EVEN OUT COMPOSITE SYNC 1 VERTICAL SYNC 3 C ODD/EVEN OUT TIMING CHART COMPOSITE VIDEO IN 6 RSET BURST/BACK 9 8 _ + + _ +V 7 1 2 OUT IN_ 4 GND IN_ OUT _ + 1 10 _V + _ COMPOSITE SYNC OUT IN+ 11 3 4 IN+ 5 IN+ 6 7 IN_ OUT 5 R SINGLE SUPPLY DUAL SUPPLIES +V _V +3 to +32V GND +1.5 to +16V _1.5 to _16V COMPOSITE SYNC OUT VERTICAL SYNC OUT BURST OUT ODD/EVEN OUT 2-58 HDW-500 MMP2V2 IC IDT79R3041-20J (IDT)J-LEADED PACKAGE C-MOS RISC CPU —TOP VIEW— 1 80 GND VDD(+5V) INPUT ACK BUSERROR BUSREQ CLK INT(3) - (5) 75 VDD(+5V) GND 5 GND VDD(+5V) 10 ACKNOWLEDGE BUS ERROR DMA ARBITER BUS REQUEST MASTER CLOCK PROCESSOR INTERRUPT 3 - 5 READ BUFFER CLOCK ENABLE RDCEN MASTER PROCESSOR RESET RESET BRANCH CONDITION PORT SBRCOND/IO STROBE /IO STROBE SBRCOND/EXT DATA EN ; BRANCH CONDITION PORT /EXT DATA EN ; PROCESSOR INTERRUPT 0 - 2 SINT(0) - (2) ; TRL-STATE TRISTATE GND VDD(+5V) 15 70 20 VDD(+5V) GND GND VDD(+5V) 36 65 ; ; ; ; ; ; ; ; ACK ADDR0 ADDR1 37 34 BUS ERROR ADDR2 BUS REQ ADDR3 14 24 23 20 35 38 25 60 30 55 GND VDD(+5V) GND VDD(+5V) 35 40 45 ; LOW ADDRESS 0 - 3 ; BYTE ENABLE STROBES FOR 16-BIT MEMORY PORT 0, 1 ; BURST TRANSFER WRITE NEAR ; DMA ARBITER BUS GRANT ; DATA ENABLE ; DIAGNOSTIC ; LAST DATUM IN MINI BURST ; MEMORY STROBE ; READ ; SYSTEM REFERENCE CLOCK ; TERMINAL COUNT BURST/WRNEAR BUSGNT DATA EN DIAG LAST MEMSTROBE RD SYSCLK TC GND VDD(+5V) GND VDD(+5V) 28 INT(3) BUSGNT INT(4) DATA EN 50 26 25 RDCEN DIAG SBRCOND(2) A/D0 SBRCOND(3) A/D1 SINT(0) A/D3 SINT(1) A/D4 SINT(2) A/D5 A/D7 A/D8 ALE A/D9 A/D10 15 TRISTATE A/D11 A/D12 (VDD = +5V) PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 PIN PIN SIGNAL I/O NO. NO. 22 — VDD 43 44 INT (4) 23 I 45 INT (3) 24 I 46 SINT (2) 25 I 47 SINT (1) 26 I 48 SINT (0) 27 I 28 I/O *1/IOSTROBE 49 29 I/O *2/EXTDATAEN 50 51 TC 30 O 52 GND 31 — 53 VDD 32 — 33 O MEMSTROBE 54 55 BUSREQ 34 I 56 RDCEN 35 I 57 ACK 36 I 58 BUSERROR 37 I 59 RESET 38 I 60 BUSGNT 39 O 61 SYSCLK 40 O 62 GND 41 — 63 VDD 42 — SIGNAL I/O A/D (23) A/D (24) A/D (25) A/D (26) I/O I/O I/O I/O — — I/O I/O I/O I/O I/O — — I I O O O O I — VDD GND A/D (27) A/D (28) A/D (29) A/D (30) A/D (31) GND VDD CLK IN TRISTATE BE16 (1) BE16 (0) ADDR (1) ADDR (0) INT (5) GND *1 ; SBRCOND (3) SIGNAL I/O A/D (8) GND VDD A/D (9) A/D (10) A/D (11) A/D (12) A/D (13) A/D (14) I/O — — I/O I/O I/O I/O I/O I/O — — I/O I/O I/O I/O I/O I/O — — I/O I/O A/D13 A/D14 INPUT/OUTPUT A/D0 - 31 ALE WR SYSTEM CONTROL COPROCESSOR GENERAL REGISTERS (32 x 32) BUS INTERFACE REGISTERS ALU SHIFTER MULT/DIY UNIT ADDRESS ADDER COUNTER REGISTERS 30 TC PC CONTROL VIRTUAL ADDRESS A/D19 A/D20 A/D21 A/D22 A/D23 A/D24 A/D25 A/D26 16 30 RD/WR CTRL SYS CLK 40 DATA CACHE 512B DATA BUS 45, 44 A/D27 BE16(1) A/D28 TC A/D29 A/D30 A/D31 WR 47 GND VDD A/D (21) A/D (22) LAST 2 RD 40 54 55 56 59 60 61 62 63 64 67 68 69 70 71 72 75 76 77 78 79 80 83 84 1 2 3 4 7 8 9 10 11 44 45 28, 29 SBRCOND 2, 3 LM2576T-ADJ (NS) STEP-DOWN TYPE VOLTAGE REGULATOR —SIDE VIEW— BENT AND STAGGERED LEADS LB03 TYPE SERIES INSTRUCTION CACHE 2KB 32 BE16(0) 33 MEMSTO ROBE PHYSICAL ADDRESS BUS 34, 39 A/D17 A/D18 STRAIGHT LEADS 32 DMA CTRL A/D16 17 48 INTEGER CPU CORE EXCEPTION/CONTROL REGISTERS PORT SIZE REGISTER 54 - 56, 59 - 64, 67 - 72, 75 - 80, 83 - 4, 7 - 11 ADDRESS/ DATA 0 - 31 A/D15 ; ADDRESS DATA 0 - 31 ; ADDRSS LATCH ENABLE ; WRITE VDD GND A/D (15) A/D (16) A/D (17) A/D (18) A/D (19) A/D (20) 43 MASTER PIPELINE CONTROL 24, 23, 20 INT3-5 SIGNAL 39 *2 ; SBRCOND (2) CLOCK GENERATOR UNIT 14 CLK IN PIN NO. O DATA EN 64 O WR 65 O RD 66 O ALE 67 O LAST 68 O DIAG 69 — GND 70 — VDD 71 O ADDR (2) 72 O ADDR (3) 73 O BURST/WRNEAR 74 I/O A/D (0) 75 I/O A/D (1) 76 I/O A/D (2) 77 — VDD 78 — GND 79 I/O A/D (3) 80 I/O A/D (4) 81 (5) I/O A/D 82 I/O A/D (6) 83 I/O A/D (7) 84 I/O 52 RESET A/D6 46 51 INT(5) A/D2 27 18 BURST/ 53 WRNEAR SYSCLK 29 OUTPUT ADDR0 - 3 BE16(0), (1) 19 DATA 4-DEEP UNPACK WRITE UNUT BUFFER DATA PACK UNIT 4-DEEP READ BUFFER DMA TIMING/ ARBITER INTERFACE BIU CONTROL CONTROL R3051 SUPERSET BUS INTERFACE UNIT 12 34 1 5 VIN FEED BACK 2 3 4 4 INTERNAL REGULATOR R2 0Z 1A LM2576 LM2576HV 3A 5 1 ON/OFF 5 ON/OFF R1 (OPEN) FIXED GAIN ERROR AMP + _ 1.25V BAND-CAP REFERENCE HDW-500 MMP2V2 1 : VIN 2 : OUTPUT 3 : GND 4 : FEED BACK 5 : ON/OFF 32 OUTPUT CURRENT LM2575 LM2575HV COMPARATOR + _ 52kHz OSCILLATOR 0.5 AMP SWITCH DRIVER RESET THERMAL SHUTDOWN 2 OUTPUT CURRENT LIMIT 2-59 IC LT1021DCS8-5 (LINEAR TECHNOLOGY)+5 V FLAT PACKAGE M27C512-12F1 (SGS) PRECISION VOLTAGE REFERENCE C-MOS 512K (65,536 x 8)-BIT ERASABLE PROM —TOP VIEW— —TOP VIEW— 10 NC 1 GND 8 NC A15 1 VDD(+5V) 28 9 8 V IN 2 7 NC 27 A14 A12 2 7 _ + 6 REF NC 3 4 6 V OUT A7 3 26 A13 5 TRIM A6 4 25 A8 5 4 3 25 A5 5 24 A9 A4 6 23 A11 24 21 23 2 22 OE / VPP A3 7 26 27 A2 8 21 A10 A1 9 20 CE 1 A0 D0 A1 D1 A2 D2 A3 D3 A4 D4 A5 D5 A6 D6 A7 D7 HIGH SPEED OPERATIONAL AMPLIFIER A0 10 19 D7 D0 11 18 D6 D1 12 17 D5 D2 13 16 D4 —TOP VIEW— NULL 1 8 SHUTDOWN _IN 2 _ +IN 3 + 6 OUT 4 VEE (_15V) 5 NULL VCC (+15V) 7 14 GND 17 18 19 A11 A12 A13 A14 A15 OE/VPP 22 ADDRESS INPUTS CHIP ENABLE INPUT DATA OUTPUTS OUTPUT ENABLE INPUT PROGRAM POWER SUPPLY Dn DOUT HI-Z HI-Z DIN DOUT HI-Z FUNCTION READ OUTPUT DISABLE STANDBY PGM PGM VERIFY PGM INH 0 1 X HI-Z ; ; ; ; LOW LEVEL HIGH LEVEL DON'T CARE HIGH IMPEDANCE D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 OE / VPP CE —TOP VIEW— 22 OUTPUT ENABLE / VPP CHIP ENABLE CIRCUIT 20 OUTPUT BUFFER OUT 7 16 A10 LT1252CS8 (LINEAR TECH)FLAT PACKAGE LT1252CS8-E2 8 15 15 D3 An CE OE/VPP VDD 0 AIN 0 +5V 1 AIN 0 +5V X 1 X +5V AIN 0 +12.5V +6V AIN 0 0 +6V X 1 +12.5V +6V VIDEO AMPLIFIER 13 A9 20 A0 - A15 ; ; CE D0 - D7 ; ; OE ; VPP 12 A8 CE LT1227CS8 (LINEAR TECH)FLAT PACKAGE LT1227CS8-E2 11 8 5 6 NC VCC (+5 to +12V) NC IN(+) IN(_) 3 2 + DATA INPUT BUFFER PROGRAM CONTROL 6 8 OUT _ COLUMN GATE VEE NC 1 (_5 to _12V) 2 3 IN(_) IN(+) A0 - A5 4 A6 - A15 5 - 10 COLUMN DECODER 1 - 4, 21 23 - 27 ROW DECODER 63 524,288-BIT (1024 x 512) CELL MATRIX 1024 LT1431CS8-E1 (LINEAR TECH) PROGRAMMABLE REFERENCE M51957BFP (MITSUBISHI)FLAT PACKAGE —TOP VIEW— VOLTAGE DETECTOR COLLECTOR 1 COMP 2 R 8 REF 7 R V+ 3 6 GND-F 4 5 GND-S TOP —TOP VIEW— MID 1 NC 8 IN 2 NC VCC(+2 to +17V) 7 3 NC 6 OUT 4 GND 5 CD VCC 6 OUT 5µA IN _ 2 _ + 1.25V 5 CD 2-60 HDW-500 MMP2V2 IC M48T18-100MH1TR (SGS) M51958AFP600D (MITSUBISHI)FLAT PACKAGE C-MOS 64k (8184 x 8)-BIT TIMEKEEPER RAM VOLTAGE DETECT DELAY —TOP VIEW— —TOP VIEW— INT 1 VDD (+5V) 28 A12 2 27 W A7 3 26 E2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 M4T28-BR12SH1 TOP HAT M48T18-100MH1TR 1 8 x 8 BIPORT SRAM ARRAY OSCILLATOR AND CLOCK CHAIN 32768Hz CRYSTAL NC 8 NC VCC IN 2 2 - 10, 23 - 25 A0 - A12 (+2V to +17V) 7 3 NC 6 OUT 4 GND 5 CD 8184 x 8 11 - 13, 15 - 19 SRAM ARRAY DQ0 - DQ7 A3 7 LITHIUM CELL 22 G A2 8 21 A10 A1 9 20 E1 A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VCC VOLTAGE SENSE AND SWITCHING CIRCUITRY POK 20 26 E1 6 OUT E2 5 µA 27 W 22 G IN 2.5 µA + 2 _ + 28 14 GND 1 14 1.25 V INT VDD GND 5 CD ; ADDRESS INPUTS A0 - A12 DQ0 - DQ7 ; DATA INPUTS/OUTPUTS ; POWER FAIL INTERRUPT INT ; CHIP ENABLE 1 E1 ; CHIP ENABLE 2 E2 ; OUTPUT ENABLE G ; WRITE ENABLE W 15 DQ3 M5238FP (MITSUBISHI)FLAT PACKAGE M5238FP-600D MC34182DR2 (MOTOROLA)FLAT PACKAGE MC34182M (MOTOROLA)FLAT PACKAGE MC34182MEL NJM2041M-D (JRC)FLAT PACKAGE NJM2041M-D(TE2) NJM2068M-D-TE2 (JRC) NJM4556M-A (JRC)FLAT PACKAGE NJM4560M (JRC)FLAT PACKAGE NJM4560MD (JRC)FLAT PACKAGE NJM4565M-A (JRC)FLAT PACKAGE NJM5532M (JRC)FLAT PACKAGE NJM5532M-D (JRC)FLAT PACKAGE TL082M (TI)FLAT PACKAGE UPC4558C (NEC)FLAT PACKAGE UPC4570G2 (NEC)FLAT PACKAGE UPC812G2 (NEC)FLAT PACKAGE M4T28-BR12SH1 (SGS) TIMEKEEPER SNAP HAT LITHIUM BATTERY —SIDE VIEW— M4T28-BR12SH1 TOP HAT M48T18-100MH1TR 8 x 8 BIPORT SRAM ARRAY OSCILLATOR AND CLOCK CHAIN 32768Hz CRYSTAL 2 - 10, 23 - 25 A0 - A12 8184 x 8 SRAM ARRAY DUAL OPERATIONAL AMPLIFIERS (DUAL-SUPPLY TYPE) —TOP VIEW— 11 - 13, 15 - 19 1 VCC 8 DQ0 - DQ7 LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY 20 26 27 22 28 VDD 1 INT _ + 2 POK 7 E1 + _ E2 3 W G 4 VEE 6 5 14 TYPE 062/072/082/4556A/ M5218/BA15218/ 33178/34182 TYPES 4580 TYPE 5532 TYPE CXA1297 TYPE M5219/M5220 TYPES MC33077DR2 NJM2100 TYPE OP-297 TYPE OTHERS VSS VCC VEE +2 to +16V _2 to _16V +2 to +18V +3 to +20V +5 to +12V +5 to +22.5V +2.5 to +18V +1 to +3.5V +2 to +20V +5 to +16V _2 to _18V _3 to _20V _5 to _12V _5 to _22.5V _2.5 to _18V _1 to _3.5V _2 to _20V _5 to _16V M54532P (MITSUBISHI) DARLINGTON TRANSISTOR ARRAY WITH CLAMP DIODE —TOP VIEW— 16 NC 15 14 13 12 GND GND 11 * 2 * 7 8 * 3 GND GND 4 5 COM IN 9 NC * * 1 10 6 COM OUT OUT IN GND HDW-500 MMP2V2 2-61 IC M5M5408AFP-55LL (MITSUBISHI)FLAT PACKAGE M5M5408AFP-55LL-E2 (MITSUBISHI)FLAT PACKAGE M62301FP (MITSUBISHI)FLAT PACKAGE M62301FP-70ND (MITSUBISHI)FLAT PACKAGE C-MOS 4M (524,288 x 8)-BIT STATIC RAM 4 CHANNELS INTEGRATION A/D CONVERTER SUPPORTER —TOP VIEW— —TOP VIEW— 12 A18 IN 1 VDD(+5V) 32 11 10 A16 IN 2 31 A15 IN 9 8 A14 IN 3 30 A17 IN 7 6 A12 IN 4 29 WE IN A7 IN 5 28 A13 IN 5 27 26 23 A6 IN 6 27 A8 IN 25 4 A5 IN 7 26 A9 IN 28 3 A4 IN 8 25 A11 IN A3 IN 9 24 OE IN 31 2 30 1 A2 IN 10 23 A10 IN A1 IN 11 22 CS IN A0 IN 12 21 I/O 8 I/O 1 13 20 I/O 7 INPUT A0 - A18 I/O 2 14 19 I/O 6 I/O 3 15 18 I/O 5 CS OE WE 22 29 24 16 GND A10 17 I/O 4 A0 I/O1 A1 I/O2 A2 I/O3 A3 I/O4 A4 I/O5 A5 I/O6 A6 I/O7 A7 I/O8 13 12 15 19 17 19 21 A9 A6 A2 A1 A0 5 6 10 C2 4 17 A3 15 INT 5 16 A4 RESET 6 A11 A12 A14 A15 A16 GRD2 9 A17 A18 A11 A9 A8 A13 A17 26 27 28 30 31 5 A2 A3 A4 REFI REFO VRST RESET C0 GRD1 C1 GRD2 6 7 9 C2 A.VCC 11 (+4.5 to +12V) WE OE ; ; ; ; MODE 1 2 3 C0 0 1 0 C1 1 0 0 C2 0 0 0 — DISCHARGE GND VREF ADDRESS CHIP SELECT OUTPUT ENABLE WRITE ENABLE INPUT A1 - 4 C0 - C2 CUR REFI VRST 15 17 18 19 20 I/O1 I/O2 OUTPUT GRD1 - GRD2 GREF INT REFO RESET 4 1 1 0 A1 5 0 0 1 A2 6 1 0 1 A3 7 0 1 1 A4 ; ; ; ; ; ANALOG DATA INPUT MODE SELECT CURRENT CONTROL VREF INPUT VCC FOR RESET ; ; ; ; ; GUARDLING (1 - 2) CONNECT INTEGRATE CAPACITY INTERVAL VREF OUT RESET OUTPUT 8 1 1 1 — I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 CUR A1 A2 A3 12 19 A1 18 A2 17 A3 16 A4 15 VREF 5 0.49V LOGIC DISPOSAL REFO VRST C0 C1 C2 13 8 VREF 1.22V 6 1 4 GREF RESET DELAY CIRCUIT 2 3 INT 0.36V GND INPUT DATA CONTROL COLUMN ADDRESS DECODER COLUMN INPUT BUFFER 25 INT 8 DECODER DISCHARGE 7 9 GRD1 GRD2 CLOCK GENERATOR A15 9 A1 GREF 12 CUR 10 A.GND A4 BLOCK ADDRESS DECODER A3 CUR CS 12 8 13 REFO GREF 8 21 BLOCK INPUT BUFFER A4 3 (+5V) 4 11 7 D.VDD 14 GRD1 7 A13 REFI A5 15 REFI 2 SENSE AMP 4 16 1 A10 INPUT/OUTPUT I/O1 - I/O8 ; I-O DATA 524288 WORD x 8-BIT RAM (1024 ROW x 4096 COLUMN) A7 ROW ADDRESS DECODER A12 3 18 A2 13 A8 1 ROW INPUT BUFFER A14 C1 3 20 14 A16 18 18 23 2 19 A1 C0 2 17 13 A18 D.GND 20 VRST 1 14 WE CS OE 29 22 24 2-62 HDW-500 MMP2V2 IC MB8421-90LPFQ (FUJITSU)(ACCESS TIME=90 nS) C-MOS 16 M (2,048,000 x 4 x 2)-BIT SYNCHRONOUS DYNAMIC RAM C-MOS 16384 (2K x 8) BIT DUAL PORT STATIC RAM —TOP VIEW— —TOP VIEW— GND VDD (+3.3 V) VDD (+3.3 V) GND GND VDD (+3.3 V) VDD (+3.3 V) NC VDD (+3.3 V) GND 22 23 24 27 28 29 30 31 32 20 19 36 14 34 35 15 16 17 18 33 A0 DO0 A1 DO1 A2 DO2 A3 DO3 A4 DO4 A5 DO5 A6 DO6 A7 DO7 A8 DO8 A9 DO9 A10 DO10 A11 DO11 DO12 DOMU DOML DO13 CKE DO14 CLK DO15 2 2 3 3 5 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 8 9 11 12 39 40 42 43 45 46 48 49 WE CAS RAS CS DU VDD(+5V) VDD(+5V) GND 21 NC 4 NC NC GND NC NC NC NC NC NC GND GND VDD(+5V) NC VDD (+3.3 V) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 NC GND 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 5 6 7 8 9 10 11 12 63 48 47 46 45 44 43 42 41 40 39 52 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 64 63 62 61 60 59 58 57 56 55 54 53 52 MB811161622A-100FN (FUJITSU)FLAT PACKAGE 49 OEL A0L A1L A2L A3L A4L A5L A6L A7L OER 16 I/O 0L 17 I/O 1L 18 I/O 2L 19 I/O 3L 20 I/O 4L 21 I/O 5L 22 I/O 6L 23 I/O 7L A8L BUSYL A9L INTL A10L A0R I/O 0R A1R I/O 1R A2R I/O 2R A3R I/O 3R A4R I/O 4R A5R I/O 5R A6R I/O 6R A7R I/O 7R 61 62 28 29 30 31 32 33 34 35 A8R A9R BUSYR 54 INTR 53 A10R CSL WEL CSR WER 59 60 56 55 (VDD = +3.3 V) I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 — I/O I/O — I/O I/O — I/O I/O — I/O I/O — I I I I I I I I I I I — VDD DO0 DO1 GND DO2 DO3 VDD DO4 DO5 GND DO6 DO7 VDD DOML CLK CKE WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD PIN NO. I/O SIGNAL 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 — I I I I I I — I I I — — I/O I/O — I/O I/O — I/O I/O — I/O I/O — GND A4 A5 A6 A7 A8 A9 DU CKE CLK DOMU NC VDD DO8 DO9 GND DO10 DO11 VDD DO12 DO13 GND DO14 DO15 GND 35 34 CLOCK BUFFER INPUT A0 - A10 A11 CAS CKE CLK CS DOML, DOMU RAS WE : : : : : : : : : CS RAS CAS WE 17 16 15 COMMAND DECODER 21 - 24, 27 - 32, 20 A0 - A10 A11 DOMU 19 ADDRESS BUFFER/ REGISTER AND BANKSELLCT 62 WEL CSL OEL 2 MATRIX DECODER A0R | A10R WER BANK 0 CSR OER I/O BUFFER I/O 0L | I/O 7L I/O BUFFER I/O 0R | I/O 7R MEMORY ARRAY MATRIX DECODER 55 56 49 54 CAS INTL 59 A0L | A10L BANK 1 BUSYL 60 53 BUSYR INTR WE DRAM CORE (2048 x 1024 x 4) (2048 x 512 x 8) (2048 x 256 x 16) LOAD ADDRESS COLUMN ADDRESS COUNTER 36 14 DOML 2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42, 43, 45, 46, 48, 49, MODE REGISTER ADDRESS INPUTS DATA INPUTS/OUTPUTS CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT BUSY OUTPUT INTERRUPT OUTPUT 61 TO EACH BLOCK CONTROL SIGNAL LATCH ; ; ; ; ; ; ; INPUT/OUTPUT DO0 - DO15 : DATA RAS 18 ADDRESS BANK SELECT COLUMN ADDRESS STROBE CLOCK ENABLE CLOCK CHIP SELECT DATA OUTPUT MASKING LOAD ADDRESS STROBE WRITE ENABLE A0L - A10L, A0R - A10R I/O0L - I/O7L, I/O0R - I/O7R CSL, CSR WEL, WER OEL, OER BUSYL, BUSYR INTL, INTR ARBITRATION INTERRUPUT CIRCUIT PIN NO. COLUMN ADDRESS I/O I/O DATA BUFFER/ REGISTER DO0 - DO15 HDW-500 MMP2V2 2-63 IC MBM29F040A-12PD (FUJITSY) MC10EL07DR2 (MOTOROLA)FLAT PACKAGE C-MOS 4M (524,288 x 8)-BIT SECTOR ERASE FLASH MEMORY ECL 2-INPUT XOR/XNOR —TOP VIEW— —TOP VIEW— 3 2 1 32 31 30 VDD(+5V) 4 5 12 11 29 6 28 7 27 8 26 9 25 10 24 11 23 22 13 21 GND 12 14 15 16 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 22 17 18 19 20 24 31 A0 1 NC A1 A2 D0 IN 2 A3 A4 7 Q OUT D1 IN 3 6 Q OUT A5 A6 A7 DQ0 A8 DQ1 A9 DQ2 A10 DQ3 A11 DQ4 A12 DQ5 A13 DQ6 A14 DQ7 4 NC 13 GND 5 14 15 17 18 19 20 21 A15 A16 MC10EL11DR2 (MOTOROLA)FLAT PACKAGE A17 A18 ECL 1:2 DIFFERENTIAL FANOUT BUFFER CE —TOP VIEW— OE (VDD = +5V) I/O I I I I I I I I I I I I I/O I/O I/O — SIGNAL A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND PIN No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O I/O I/O I/O I/O I/O I I I I I I I I I I — SIGNAL DQ3 DQ4 DQ5 DQ6 DQ7 CE A10 OE A11 A9 A8 A13 A14 A17 WE VDD INPUT A0 - A18 CE OE WE ; ; ; ; ADDRESS INPUTS CHIP ENABLE OUTPUT ENABLE WRITE ENABLE VCC(+5V) 8 Q0 OUT 2 7 D IN Q1 OUT 3 6 D IN Q1 OUT 4 GND 5 INPUT/OUTPUT DQ0 - DQ7 ; DATA INPUT/OUTPUT MC10EL16DR2 (MOTOROLA)FLAT PACKAGE ECL DIFFERENTIAL RECEIVER —TOP VIEW— 1 NC WE 31 STATE CONTROL ERASE VOLTAGE GENERATOR INPUT OUTPUT BUFFERS 13 - 15 17 - 21 D IN 2 7 Q OUT DQ0 - DQ7 D IN 3 6 Q OUT OE CHIP ENABLE OUTPUT ENABLE LOGIC 22 24 VDD DETECTOR 1 - 12, 23 25 - 30 GND 5 PGM VOLTAGE GENERATOR TIMER ADDRESS LATCH CE D ; DATA INPUT Q ; DATA OUTPUT VBB ; REFERENCE VOLTAGE OUTPUT VCC(+5V) 8 VBB OUT 4 COMMAND REGISTER D ; DATA INPUT Q0, Q1 ; DATA OUTPUT WE Q0 OUT 1 PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0, D1 ; DATA INPUT Q ; DATA OUTPUT VCC(+5V) 8 DATA LATCH Y-DECODER Y-GATING X-DECODER CELL MATRIX MC10H124M (MOTOROLA)FLAT PACKAGE MC10H124MEL ECL TTL-TO-ECL TRANSLATOR —TOP VIEW— 16 GND 15 1 2 14 13 12 11 10 9 VCC (+5 V) A0 - A18 VEE (_5.2 V) 2-64 3 4 5 6 7 8 HDW-500 MMP2V2 IC MB8441-45PFQ (FUJITSU)FLAT PACKAGE C-MOS 64K-BIT DUAL PORT STATIC RAM 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 —TOP VIEW— 2 NC NC NC 3 52 53 54 55 56 57 58 59 60 61 62 63 64 VDD(+5V) VDD(+5V) GND VDD(+5V) GND GND NC NC NC NC 4 32 31 30 29 28 27 26 25 24 23 22 21 20 5 6 7 8 9 10 11 12 63 61 48 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 46 45 44 (VDD = +5V) PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O I I I I I I I I I I I I — — O I/O SIGNAL A12L OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC BE I/O1L PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O SIGNAL I/O I/O I/O I/O I/O I/O I/O — — — — I/O I/O I/O I/O I/O I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L GND GND VDD GND I/O1R I/O2R I/O3R I/O4R I/O5R PIN NO. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O — — — I I I I I I I I I I SIGNAL I/O6R I/O7R I/O8R NC NC NC A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R PIN NO. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 43 I/O I I I I O I I I — — I I I O I I SIGNAL 42 OER 41 A12R A11R A10R 40 39 52 INTR BUSYR WER CSR 54 OER I/O1L A1L I/O2L A2L I/O3L A3L I/O4L A4L I/O5L A5L I/O6L A6L I/O7L A7L I/O8L 16 ; ADDRESS INPUTS ; BUSY OUTPUT ENABLE BE BUSYL, BUSYR ; BUSY INPUTS ; CHIP SELECT INPUTS CSL, CSR 17 18 19 I/O0L - I/O10L, I/O0R - I/O10R 20 21 INTL, INTR OEL, OER WEL, WER 22 23 ; ; ; ; DATA INPUTS/OUTPUTS INTERRUPT OUTPUTS OUTPUT ENABLE INPUTS WRITE ENABLE INPUTS A8L INTL A9L 62 A10L BUSYL A0R I/O1R A1R I/O2R A2R I/O3R A3R I/O4R A4R I/O5R A5R I/O6R A6R I/O7R A7R I/O8R 28 29 30 31 32 33 34 35 A8R INTR A9R 53 A10R BUSYR CSL 59 VDD VDD A0L - A10L, A0R - A10R 49 OEL A0L WEL 60 CSR 56 WER 55 CSL WEL BUSYL INTL A10L A11L MBM29F040A-90PD (FUJITSU) C-MOS 4M (536,576 x 8)-BIT FLASH MEMORY OEL 59 2 56 49 WER WE CSR OER A7 5 30 A17 OER 31 OEL 55 1 A18 WER 2 A16 WEL VDD(+5V) 32 CSL 60 3 A15 WEL 4 A12 —TOP VIEW— 0 11 29 A14 10 9 I/O8L A12L A11L A10L A9L A8L A7L A6L A5L A4L A3L A2L A1L A0L 32 I/O BUFFER I/O BUFFER 32 33 33 34 34 35 35 1 50 64 51 63 12 ROW DECODER ROW DECODER 52 39 11 40 10 41 9 42 8 7 6 43 COLUMN DECODER 5 4 8.192 x 8 BIT MEMORY CELL ARRAY COLUMN DECODER 44 45 46 47 3 48 13 I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R A12R A11R A10R A9R A8R 27 A8 7 A4 8 26 A9 62 A3 9 25 A11 A2 10 24 OE 3 A1 11 23 A10 30 A0 12 22 CE 26 28 29 2 1 23 DQ0 13 21 DQ7 A7R A6R A5R A4R 25 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 CE WE OE 22 31 24 A3R A2R A1R A0R 13 A0 - A18 ; ADDRESS INPUTS DQ0 - DQ7 ; DATA INPUTS/OUTPUTS ; CHIP ENABLE CE ; OUTPUT ENABLE OE ; WRITE ENABLE WE DQ0 - DQ7 54 53 15 ERASE CIRCUITS DATA I/O BUFFER BUSYR WE INTLR CONTROL CIRCUITS BE WRITE CIRCUITS CE OE LOW VDD DETECTOR A0 - A18 HDW-500 MMP2V2 27 4 WRITE/ERASE PULSE TIMER CHIP ENABLE/ OUTPUT ENABLE CIRCUITS ADDRESS LATCH INTL 61 6 5 INTERRUPT BUSYL 8 DQ6 20 I/O7L 31 A5 7 DQ5 19 I/O6L 31 I/O2R DQ4 18 I/O5L 30 DQ3 17 I/O4L 29 30 28 A13 16 GND I/O3L 29 I/O1R A6 6 DQ2 15 I/O2L 28 DQ1 14 I/O1L 28 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DATA LATCH Y DECODER Y GATE X DECODER 4,194,304 MEMORY CELL MATRIX 2-65 IC MB90091A-120 (FUJITSU) C-MOS ON SCREEN DISPLAY CONTROLLER 52 53 54 55 56 57 58 59 60 61 62 63 64 GND VDD(+5V) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 —TOP VIEW— GND VDD(+5V) VDD(+5V) GND 32 31 30 29 28 27 26 25 24 23 22 21 20 I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I I I O — I — O I — I I I I I I SIGNAL PIN NO. I/O HSYNC VSYNC EVEN FLTIN AGND FLTOUT AVDD FH RESET VDD RD0 RD1 RD2 RD3 RD4 RD5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I I I — O O O O O O O O O — O — SIGNAL PIN NO. I/O RD6 RD7 TEST GND TA16 TA17 TA18 FCS TCS RA0 RA1 RA2 RA3 VDD RA4 GND 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 O O O O O O O — O O O O I I I I 48 SIN 47 SCLK SERIAL INPUT CONTROL B OUTPUT COLOR/BW SELECT DOT CLOCK EXTERNAL FONT ROM CHIP SELECT HORIZONTAL PULSE PHASE COMPARED SIGNAL G OUTPUT I OUTPUT EXTERNAL ROM ADDRESSES R OUTPUT TEST SIGNALS EXTERNAL COMMAND TABLE ROM CHIP SELECT INTERNAL OPERATION STATUS COLOR SIGNAL OUTPUT PERIOD SPECIFIED CHARACTER OUTPUT PERIOD SCLK SCS SIN TEST TESTCK TESTSW TSEL VBLNK VSYNC SIGNAL PIN NO. I/O SIGNAL RA5 RA6 RA7 RA8 RA9 RA10 RA11 GND RA12 RA13 RA14 RA15 TSEL FSEL SCLK SIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I — O O O O O O O O O — I I I I SCS VDD TRE R OUT G OUT B OUT I OUT VOB1 VOB2 COLOR DOCK GND TESTCK TESTSW HBLNK VBLNK 45 49 SCS ; ; ; ; FCS ; FH FLTIN ; GOUT ; IOUT ; RA0 - RA15 ; ROUT ; TA16 - TA18 ; ; TCS ; TRE ; VOB1 ; VOB2 RESET 51 COMMAND TABLE ROM CONTROL ODD/EVEN FIELD CONTROL (H = EVEN, L = ODD) INTERNAL VCO VOLTAGE FONT ROM INT/EXT SELECT HORIZONTAL BLANKING HORIZONTAL SYNC EXTERNAL ROM DATA SYSTEM RESET SERIAL SHIFT CLOCK CHIP SELECT SERIAL DATA TEST SIGNAL TEST SIGNAL TEST SIGNAL COMMAND TABLE ROM ADDRESS CONTROL VERTICAL BLANKING VERTICAL SYNC RD0 - RD7 (VDD, AVDD = +5V) PIN NO. ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; HBLNK HSYNC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AGND AVDD(+5V) GND INPUTS EVEN FLTOUT FSEL 25 26 - 29, 31, 33 - 39, 41 - 44 11 - 18 OUTPUTS BOUT COLOR DOCK TRE TSEL TCS RA0 - 15 MBM29F400BA-90PF (FUJITSU)FLAT PACKAGE RD0 - 7 C-MOS 4M (256K x 16) -BIT FLASH MEMORY —TOP VIEW— 4 FLTIN 6 FLTOUT 8 FH DOT CLOCK GENERATE CIRCUIT COMMAND TABLE ROM 3 1 NC RY/BY 59 DOCK 1 HSYNC 2 VSYNC 3 EVEN DISPLAY MEMORY CONTROL OUT A17 FONT ROM CONTROL 24 46 FCS FSEL FOR DISPLAY MEMORY FONT ROM IN A7 IN 44 RESET 2 43 WE 3 42 A8 4 41 A9 34 IN 35 IN 36 IN 37 IN 38 39 A6 IN 5 40 A10 IN A5 IN 6 39 A11 IN A4 IN 7 38 A12 IN A3 IN 8 37 A13 IN A2 IN 9 36 A14 40 41 42 4 5 6 IN 7 52 53 RESET 9 EACH RESET DISPLAY DATA OUTPUT CONTROL 54 55 56 57 58 A1 R OUT G OUT B OUT IN A0 IN CE IN I OUT VOB1 VOB2 COLOR 10 35 A15 11 34 A16 12 IN 8 IN 9 33 BYTE 13 GND 10 IN IN 14 31 DQ15/A-1 DQ0 I/O 15 30 DQ7 DQ8 I/O 16 29 DQ14 DQ1 I/O 17 28 DQ6 DQ9 I/O 18 27 DQ13 DQ2 I/O 19 26 DQ5 DQ10 I/O 20 25 DQ12 DQ3 I/O 21 DQ11 I/O 22 OE 24 DQ4 I/O I/O I/O DQ14 A15 DQ13 A14 DQ12 A13 DQ11 A12 DQ10 A11 DQ9 A10 DQ8 A9 DQ7 A8 DQ6 A7 DQ5 A6 DQ4 A5 DQ3 A4 DQ2 A3 DQ1 A2 DQ0 31 29 27 25 22 20 18 16 30 28 26 24 21 19 17 15 A1 A0 I/O 43 33 44 I/O DQ15/A-1 A16 12 14 WE RY/BY 2 BYTE RESET CE OE I/O I/O I/O VDD(+5V) 23 INPUT A0 - A17, A - 1 ; ; BYTE ; CE ; OE ; RESET ; WE OUTPUT RY/BY 11 GND 32 A17 ADDRESS 8-BIT, 16-BIT MODE SELECT CHIP ENABLE OUTPUT ENABLE HARDWARE RESET WRITE ENABLE ; READY/BUSY INPUT/OUTPUT DQ0 - DQ15 ; DATA 2-66 HDW-500 MMP2V2 IC MC14051BF (MOTOROLA)FLAT PACKAGE MC14051BFEL MC1488MEL (MOTOROLA) C-MOS 8-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER —TOP VIEW— 2-INPUT (1-INPUT) POSITIVE-NAND LINE DRIVER —TOP VIEW— 14 CONTROL INPUTS SELECTED SELECT EN CHANNEL C B A 0 0 0 0 X0 1 X1 0 0 0 1 0 X2 0 0 0 0 1 1 X3 0 1 0 0 X4 0 1 0 1 X5 0 X6 0 1 1 1 1 X7 0 1 1 X X X OPEN 13 X0 X4 I/O 1 VDD (+3 to +18V) 16 14 X1 15 X2 15 X2 I/O X6 I/O 2 12 X3 XC 3 1 X4 XC I/O 3 14 X1 I/O X7 I/O 4 13 X0 I/O X5 I/O 5 12 X3 I/O EN I/O 6 11 A IN 5 X5 2 X6 4 X7 6 EN OPEN B A 7 VEE* 10 B IN 8 GND 9 C IN C 11 10 X0 to X7 XC A, B, C EN * VEE ; VDD _ VEE = +3 to +18V ; ; ; ; 9 13 12 11 10 9 A B 8 VCC (+12V) Y = A B Y Y=A•B=A+B VEE (–12V) 1 2 3 4 5 6 A 0 0 1 1 GND 7 B 0 1 0 1 Y 1 1 1 0 ; LOW LEVEL 0 1 ; HIGH LEVEL 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE ANALOG INPUTS/OUTPUTS COMMON INPUT/OUTPUT CHANNEL SELECT INPUT ENABLE INPUT MC1489AM (MOTOROLA)FLAT PACKAGE MC1489AM-T2 QUADRUPLE LINE RECEIVER —TOP VIEW— 14 13 12 11 10 9 8 2 3 4 5 6 GND 7 VCC (+5V) MC14053BF (MOTOROLA)FLAT PACKAGE MC14053BFEL C-MOS TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS —TOP VIEW— 1 VDD (+3V to +18V) X1 IN/OUT 1 X0 IN/OUT 2 16 X0 1 X1 XC 15 OPEN 10 AX 15 XC IN/OUT Y1 IN/OUT 3 2 14 ZC IN/OUT Y0 3 Y1 OPEN AY YC IN/OUT 4 13 Z1 IN/OUT 9 Y0 IN/OUT 5 12 Z0 IN/OUT 12 Z0 INPUT THRESHOLD SHIFTING VCC 5 14 +5V YC 4 VI VO VO V 4 RC = 5K VC = 5V RC = 11K VC = _5V RC = RC 13 Z1 EN IN 6 VC ZC 14 11 AZ IN/OUT OPEN 11 AZ 7 VEE * 10 AX IN/OUT EN VEE 6 7 8 GND 9 AY IN/OUT 0.2 VI _2 _1 0 1 2 3 4 V 0.97V 1.9V INPUT NOISE FILTERING VCC 14 CONT. INPUTS ON EN A (X, Y, Z) CHANNEL 0 0 0 0 1 1 1 X OPEN VEE *; VDD _ VEE + 3V + 18V 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE +5V VI VO CC MC14538BF (MOTOROLA)FLAT PACKAGE MC14538BFE (MOTOROLA)FLAT PACKAGE MC14538BFEL MC34051M (MOTOROLA)FLAT PACKAGE MC34051MEL (MOTOROLA) C-MOS DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS RS-422 DRIVER / RECEIVER —TOP VIEW— —TOP VIEW— VDD 1-C 1 R C VDD 16 (+3 to +18V) 1 1-CR 2 15 2-C 1-RD 3 14 2-CR VDD 2 Q 4 15 13 2-RD 12 2-CK Q 12 10 11 2-CK 1-Q 7 10 2-Q 8 GND DR EN 0 1 IN _ 1 Q 9 REC1 IN + 2 15 DR1 IN 3 14 DR1 OUT IN 4 13 DR1 OUT OUT 5 12 DR2 EN REC1 RD 3 13 OUT DR1 EN OUTPUT PULSE WIDTH = C . R REC2 1-Q 6 VCC (+5V) REC1 16 MODE DISABLE ENABLE 0 ; LOW LEVEL 1 ; HIGH LEVEL 11 7 RD 1-CK 5 14 6 5 Q 1-CK 4 R C DR ; DRIVER DR EN ; DRIVER ENABLE REC ; RECEIVER IN REC2 IN + 6 11 DR2 OUT REC2 IN _ 7 10 DR2 OUT 9 2-Q 8 GND RETRIGGERABLE M.M.V IN NON-RETRIGGERABLE M.M.V VDD VDD VDD VDD DRIVER CIRCUIT DR IN 15 (9) Q Q Q Q Q Q Q Q RD RD RD RD VDD VDD VDD VDD DR EN RECEIVER CIRCUIT 14 (10) 13 (11) VDD HDW-500 MMP2V2 9 DR2 DR DR OUT OUT REC IN _ REC IN + 1 (7) 2 (6) _ 3 (5) REC OUT + 4 (12) IN 2-67 IC MB90T736 (FUJITSU) C-MOS 16-BIT 1-CHIP MICROCONTROLLER 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 —TOP VIEW— GND VDD(+5V) GND AGND GND AVDD(+5V) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 (AVDD, VDD = +5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PIN No. P20/A16/A00 21 P21/A17/A01 22 P22/A18/A02 23 P23/A19/A03 24 P24/A20/A04 25 P25/A21/A05 26 P26/A22/A06 27 P27/A23/A07 28 GND 29 P30/ALE/A16 30 31 P31/RD 32 P32/WRL P33/WRH/A17 33 P34/HRQ 34 35 P35/HAK P36/RDY 36 37 P37/CLK P40/SIN1 38 39 P41/SOT1 P42/SCK1 40 INPUT AVR+, AVR_ ; ; HST ; MD0 - MD2 ; RST X0, X1 ; SIGNAL I/O I/O I/O I/O I/O I/O — I I — I/O I/O — I/O I/O I/O I/O I/O I/O I I PIN No. P43/SIN2 41 P44/SOT2 42 P45/SCK2 43 P46 44 P47/ATG/IRQ0 45 AVDD 46 47 AVR+ 48 AVR_ 49 AGND P50/AN0 50 P51/AN1 51 GND 52 P52/AN2 53 P53/AN3 54 P54/AN4 55 P55/AN5 56 P56/AN6 57 P57/AN7 58 MD0 59 MD1 60 SIGNAL I/O SIGNAL I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I MD2 HST P60/PPG0 P61/PPG1 P62/PPG2 P63/PPG3 P64/TRG0 P65/TRG1 P66/TRG2/CKOT P67/TRG3/IRQ1 P70/PWM0 P71/PWM1 P72/PWM2 P73/PWM3 P74/MIN0 P75/MIN1 P76/MIN2 P80/MIN3/IRQ2 P81/MIN4/IRQ3 RST EXTERNAL REFERENCE VOLTAGE FOR A/D CONVERTER HARDWARE STANDBY MB90T736 OPERATION MODE SELECT RESET CRYSTAL CONNECTION 62 63 PIN No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O SIGNAL — I I — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND X0 X1 VDD P00/AD00/D00 P01/AD01/D01 P02/AD02/D02 P03/AD03/D03 P04/AD04/D04 P05/AD05/D05 P06/AD06/D06 P07/AD07/D07 P10/AD08/D08 P11/AD09/D09 P12/AD10/D10 P13/AD11/D11 P14/AD12/D12 P15/AD13/D13 P16/AD14/D14 P17/AD15/D15 X0 P00/AD00/D00 X1 P01/AD01/D01 P02/AD02/D02 42 60 HST P03/AD03/D03 RST P04/AD04/D04 P05/AD05/D05 39 40 41 MD0 P06/AD06/D06 MD1 P07/AD07/D07 MD2 P10/AD08/D08 P11/AD09/D09 27 AVR+ P12/AD10/D10 P13/AD11/D11 28 AVR_ P14/AD12/D12 P15/AD13/D13 30 31 33 34 35 36 37 38 P50/AN0 P16/AD14/D14 P51/AN1 P17/AD15/D15 P52/AN2 P20/A16/A00 P53/AN3 P21/A17/A01 P54/AN4 P22/A18/A02 P55/AN5 P23/A19/A03 P56/AN6 P24/A20/A04 P57/AN7 P25/A21/A05 P26/A22/A06 43 44 45 46 47 48 49 50 P60/PPG0 P27/A23/A07 P61/PPG1 P30/ALE/A16 P62/PPG2 P31/RD P63/PPG3 P32/WRL P64/TRG0 P33/WRH/A17 P65/TRG1 P34/HRQ P66/TRG2/CKOT P35/HAK P67/TRG3/IRQ1 P36/RDY P37/CLK 51 52 53 54 55 56 57 58 59 2-68 P70/PWM0 P40/SIN1 P71/PWM1 P41/SOT1 P72/PWM2 P42/SCK1 P73/PWM3 P43/SIN2 P74/MIN0 P44/SOT2 P75/MIN1 P45/SCK2 P75/MIN2 P46 P47/ATG/IRQ0 P80/MIN3/IRQ2 P81/MIN4/IRQ3 65 66 67 INPUT/OUTPUT P00/AD00/D00 - P07/AD07/A07 ; I/O PORT 00 - 07 (SINGLE CHIP MODE) ADDRESS/DATA BUS LINE 0 - 7 (MULTIPLEX BUS MODE) DATA BUS LINE 0 - 7 (NON-MULTIPLEX BUS MODE) P10/AD08/A08 - P17/AD15/A15 ; I/O PORT 10 - 17 (SINGLE CHIP MODE) ADDRESS/DATA BUS LINE 8 - 15 (MULTIPLEX BUS MODE) ADDRESS BUS LINE 8 - 15 (NON-MULTIPLEX BUS MODE) P20/A16/A00 - P27/A23/A07 ; I/O PORT 20 - 27 (SINGLE CHIP MODE) ADDRESS BUS LINE 16 - 23 (MULTIPLEX BUS MODE) ADDRESS BUS LINE 0 - 7 (NON-MULTIPLEX BUS MODE) P30/ALE/A16 ; I/O PORT 30 (SINGLE CHIP MODE) ADDRESS LATCH ENABLE OUT (MULTIPLEX BUS MODE) ADDRESS BUS LINE 16 (NON-MULTIPLEX BUS MODE) P31/RD ; I/O PORT 31 (SINGLE CHIP MODE) READ STROBE OUT (EXCEPT SINGLE CHIP MODE) P32/WRL ; I/O PORT 32 (SINGLE CHIP MODE) LOWER DATA WRITE STROBE OUT (EXCEPT SINGLE CHIP MODE) P33/WRH/A17 ; I/O PORT 33 (SINGLE CHIP MODE) UPPER DATA WRITE STROBE OUT (MULTIPLEX BUS MODE) ADDRESS BUS LINE 17 (NON-MULTIPLEX BUS MODE) P34/HRQ ; I/O PORT 34 (SINGLE CHIP MODE) HOLD REQUEST IN (EXCEPT SINGLE CHIP MODE) P35/HAK ; I/O PORT 35 (SINGLE CHIP MODE) HOLD ACKNOWLEDGE OUT (EXCEPT SINGLE CHIP MODE) P36/RDY ; I/O PORT 36 (SINGLE CHIP MODE) EXTERNAL READY IN (EXCEPT SINGLE CHIP MODE) P37/CLK ; I/O PORT 37 (SINGLE CHIP MODE) MECHAN-CYCLE CLOCK OUT (EXCEPT SINGLE CHIP MODE) P40/SIN1 ; I/O PORT 40 SERIAL DATA IN WHEN UART OPERATION MODE P41/SOT1 ; I/O PORT 41 SERIAL DATA OUT OF UART P42/SCK1 ; I/O PORT 42 SERIAL CLOCK OUT WHEN UART OPERATION IS EXTERNAL CLOCK MODE P43/SIN2 ; I/O PORT 43 SERIAL DATA IN WHEN EXTENDED I/O SERIAL OPERATION MODE P44/SOT2 ; I/O PORT 44 SERIAL DATA OUT OF EXTENDED I/O SERIAL I/F P45/SCK2 ; I/O PORT 45 SERIAL CLOCK OUT WHEN EXTENDED I/O SERIAL OPERATION MODE P46 ; I/O PORT 46 P47/ATG/IRQ0 ; I/O PORT 47 (INTERRUPT REQUEST O IN) A/D CONVERTER STARTING TRIGGER IN ; I/O PORT 50 - 57 P50/AN0 - P57/AN7 ANALOG IN PORT 0 - 7 WHEN A/D CONVERTER OPERATION MODE ; I/O PORT 60 - 63 P60/PPG0 - P63/PPG3 PPG OUT 0 - 3 WHEN PPG OPERATION MODE ; I/O PORT 64, 65 P64/TRG0, P65/TRG1 PPG 0/1 STARTING TRIGGER IN WHEN PPG OPERATION IS EXTERNAL STARTING TRIGGER MODE ; I/O PORT 66 P66/TRG2/CKOT PPG 2 STARTING TRIGGER IN WHEN PPG OPERATION IS EXTERNAL STARTING TRIGGER MODE CLOCK OUT ; I/O PORT 67 (INTERRUPT REQUEST 1 IN) P67/TRG3/IRQ1 PPG 3 STARTING TRIGGER IN WHEN PPG OPERATION IS EXTERNAL STARTING TRIGGER MODE ; I/O PORT 70 - 73 P70/PWM0 - P73/PWM3 PWM OUT 0 - 3 WHEN PWM OPERATION MODE ; I/O PORT 74 - 76 P74/MIN0 - P76/MIN2 MIC TIMER 0/1/2 START/END TRIGGER IN WHEN MIC TIMER OPERATION MODE ; I/O PORT 80, 81 (INTERRUPT REQUEST 2, 3 IN) P80/MIN3/IRQ2, MIC TIMER 3/4 START/END TRIGGER IN WHEN MIC TIMER OPERATION MODE P81/MIN4/IRQ3 68 69 70 CPU CORE 71 72 73 74 75 76 77 X0 X1 RST HST 62 63 CLOCK CONTROLLER 60 INTERRUPT CONTROLLER 42 78 79 43 - 46 PPG x4 4 MULTI INPUT MEASURING TIMER 5 PWM x 4 4 EXTERNAL INTERRUPT 4 47 - 50 4 PPG0 - PPG3 TRG0 - TRG3 RAM 2K BYTES 80 1 2 3 55 - 59 MIN0 - MIN4 4 5 6 7 8 10 11 12 13 SIN1 SOT1 SCK1 SIN2 SOT2 SCK2 18 19 UART 20 51 - 54 PWM0 - PWM3 21 I/O EXTENDED SERIAL INTERFACE 22 23 14 27, 28 15 16 17 18 AVR+, AVR_ ATG AN0 - AN7 25 2 30, 31, 33 - 38 8 A/D CONVERTER 25, 50, 58, 59 19 65 - 72 20 21 CKOT 22 23 24 25 MD0 MD1 MD2 49 8 PRE-SCALER 8 39 8 40 8 41 I/O PORT 8 8 8 7 2 73 - 80 1-8 10 - 17 18 - 25 30, 31, 33 - 38 43 - 50 51 - 57 58, 59 IRQ0 - IRQ3 P00 - P07 P10 - P17 P20 - P27 P30 - P37 P40 - P47 P50 - P57 P60 - P67 P70 - P76 P80, P81 HDW-500 MMP2V2 IC MC74HC163AF (MOTOROLA)FLAT PACKAGE SN74HC163ANS-E05 C-MOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER —TOP VIEW— C-MOS TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER RD IN 1 CK IN 2 VDD 15 CO OUT IN 3 14 QA OUT B(DATA B) IN 4 13 QB OUT C(DATA C) IN 5 12 QC OUT D(DATA D) IN 6 11 QD OUT IN 7 —TOP VIEW— MODE SELECTION CONTROL INPUTS RD LD EN1 EN2 16 A(DATA A) EN1 MC74HC4053F (MOTOROLA)FLAT PACKAGE MC74HC4053FEL (MOTOROLA)FLAT PACKAGE TC74HC4053AF(EL) 10 EN2 X 0 X X MODE RESET (SYNCHRONOUS) 1 0 X X PRESET (SYNCHRONOUS) 1 1 1 1 1 1 0 X 1 X 0 1 NO COUNT NO COUNT COUNT Z1 I/O 3 14 X I/O Z I/O 4 13 X1 I/O Z0 I/O 5 12 X0 I/O 3 Z1 EN IN 6 11 A IN 9 2 Y0 QA QB QC QD VDD +2 to +6V +2 to +5.5V +5V TYPE HC AC/VHC HCT/ACT/FCT CO IS HIGH WHEN EN2 INPUT IS HIGH AND COUNT IS "15". COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 9 3 4 5 6 LD A QA B QB C QC D QD 14 13 12 11 2 7 10 EN1 CO 15 EN2 RD 1 QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OUTPUTS QC QB QA 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 MC74HC175F (MOTOROLA)FLAT PACKAGE TC74HC175AF-TP2 C-MOS QUAD D-TYPE FLIP-FLOPS WITH RESET —TOP VIEW— 16 VDD Q4 15 Q4 14 Q RD D4 13 D3 12 Q Q3 11 Q D D D D Q Q Q3 10 CK 9 Q RD 4 5 12 13 RD Q RD Q 1 2 3 4 5 6 7 RD Q1 Q1 D1 D2 Q2 Q2 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 D1 D2 D3 D4 9 GND 8 RD 1 2 3 7 6 10 11 15 14 RD CK D Q Q 0 X X 0 1 1 1 1 0 1 0 0 1 1 0 X Q0 Q0 7 VEE* 10 B IN 8 GND 9 C IN CONTROL INPUTS SELECT A C B 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 0 X X X 1 NJM78L05A (JRC)+5 V(100 mA) NJM78L05A-T3 (JRC) NJM78L12A (JRC)+12 V(100 mA) NJM78L12A-T3 4 EN VEE 6 7 ON CHANNEL EN Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 OPEN X0 X1 X0 X1 X0 X1 X0 X1 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE NJM78L05UA (JRC)+5 V(100 mA) NJM78L05UA-TE1 NJM78L09UA NJM78L09UA(TE1) (JRC)+12 V(100 mA) TA78L05F (TOSHIBA)+5 V (100 mA) TA78L05F-TE12L TA78L09F-TE12L (TOSHIBA)+12 V(100 mA) TA78L12F (TOSHIBA)+12 V (100 mA) TA78L12F-TE12L POSITIVE VOLTAGE REGULATOR —SIDE VIEW— 0 1 ; LOW LEVEL ; HIGH LEVEL X ; DON'T CARE Q0 ; NO CHANGE 3 IN OUT 1 GND 2 NOTE: VDD +2V to +5.5V +4.5V to +5.5V +2V to +6V Z OPEN C VEE*; VDD _ VEE = +3V to +12V VEE < GND Q0 ; NO CHANGE TYPE AC TYPE 74ACT175 TYPE OTHER TYPES Y 15 1 Y1 OPEN 10 B CO COUNT SEQUENCE NOTE: X 14 13 X1 OPEN 11 A 15 Y I/O 5 Z0 CARRY OUTPUT "CO" IN IN 12 X0 16 Y0 I/O 2 EN2 9 LD 8 GND VDD (+2V to +6V) Y1 I/O 1 OUT 1 GND 2 IN 3 NJM79L05A (JRC)_5 V(100 mA) NJM79L05A-T3 NEGATIVE VOLTAGE REGULATOR POSITIVE VOLTAGE REGULATOR 2 OUT IN 3 GND 1 GND (1) OUT GND 1 2 3 IN (2) OUT (3) IN 3 IN OUT 1 GND 2 HDW-500 MMP2V2 2-69 IC MN47V77ST1 (MATSUSHITA)FLAT PACKAGE MSM514221B-30JS (OKI) C-MOS 2M (262,272-WORD x 8)-BIT FIFO (3.3V) MEMORY C-MOS 1M (262,263 x 4)-BIT FIELD MEMORY —TOP VIEW— —TOP VIEW— 14 DI0 IN 28 DO0 1 13 OUT 12 DI1 IN 27 DO1 2 11 OUT 4 DI2 IN 3 26 DO2 OUT DI3 IN 4 25 DO3 OUT 3 2 1 DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 DI3 DO3 DI2 DO2 DI1 DO1 DI0 DO0 15 4 16 WE VDD (+5V) 1 IN 26 10 17 11 18 RSTW IN 2 25 RE SWCK IN 3 24 RSTR IN D in 0 4 23 SRCK IN IN 12 25 26 25 27 1 28 24 WE IN 24 RE 5 20 IN 24 6 GND GND 23 21 5 NC RCK NC 22 2 D in 0 D out 0 D in 1 D out 1 D in 2 D out 2 D in 3 D out 3 IN 22 OE 7 9 IN 5 WRST IN 8 21 RRST WCK IN 9 20 RCK 8 IN 22 IN VDD 19 (+3.3V) DD 10 V (+3.3V) 7 RSTR RSTW SRCK SWCK WCK WE WRST 9 NC OE NC 18 D in 1 10 17 D out 0 11 18 DO4 OUT D in 2 11 16 D out 1 DI5 IN 12 17 DO5 OUT D in 3 12 15 D out 2 DI6 IN 13 16 DO6 OUT DI7 IN 14 15 DO7 OUT INPUT DI0 - DI7 OE RCK RE RRST TEST WCK WE WRST ; ; ; ; ; ; ; ; ; TEST 13 GND D in 0 - D in 3 D out 0 - D out 3 RE RSTR RSTW SRCK SWCK WE 14 D out 3 ; ; ; ; ; ; ; ; DATA INPUTS DATA OUTPUTS READ ENABLE INPUT RESET READ INPUT RESET WRITE INPUT SERIAL READ CLOCK SERIAL WRITE CLOCK WRITE ENABLE INPUT MSM514222B-30JS (2/2) DATA OUTPUT ENABLE READ CLOCK READ ENABLE READ RESET TEST WRITE CLOCK WRITE ENABLE WRITE RESET D out 0 - D out 3 RE 25 RSTR 24 SRCK 23 14 - 17 4 DATA-OUT BUFFER (x4) SERIAL READ CONTROLLER 512 WORD SERIAL READ REGISTER (x4) READ LINE BUFFER READ LINE BUFFER HIGH-HALF (x4) LOW-HALF (x4) OUTPUT DO0 - DO7 ; DATA 256K (x4) 256K (x4) 120 WORD SUB-REGISTER (x4) 9 WRITE CLOCK GENERATOR 8 5 READ CLOCK GENERATOR WRITE ADDRESS GENERATOR TEST READ/WRITE AND REFRESH CONTROLLER 120 WORD SUB-REGISTER (x4) 20 ARBITER X DECODER 256K (x4) MEMORY ARRAY REFRESH REFRESH CLOCK ADDRESS GENERATOR GENERATOR WE 14 WE 23 RRST IN WRST 15 RE DI4 WCK 16 RE 3 TEST 17 21 24 22 CLOCK OSCILLATOR RCK 256K (x4) 256K (x4) RRST WRITE LINE BUFFER WRITE LINE BUFFER LOW-HALF (x4) HIGH-HALF (x4) RE OE 512 WORD SERIAL WRITE REGISTER (x4) READ ADDRESS GENERATOR DATA-IN BUFFER (x4) 7 VBB GENERATOR SERIAL WRITE CONTROLLER 4 4, 10 - 12 DECODER 1 1 - 4, 11 - 14 DI0 - DI7 262,144-WORD x 8-BIT POINTER LINE REGISTER 128-WORD x 8-BIT DATA INPUT BUFFER NJM360M (JRC)FLAT PACKAGE NJM360M-TE2 HIGH SPEED VOLTAGE COMPARATOR —TOP VIEW— 2 WE 3 RSTW SWCK READ ADDRESS POINTER MEMORY CELL ARRAY READ DATA REGISTER 128-WORD x 8-BIT WRITE DATA REGISTER 256-WORD x 8-BIT WRITE ADDRESS POINTER D in 0 - D in 3 DATA OUTPUT BUFFER 28 - 25, 18 - 15 DO0 - DO7 NJM5532S-D (JRC) DUAL OPERATIONAL AMPLIFIER —SIDE VIEW— VCC(+5V) 8 1 NC 2 3 4 VCC(_5V) __ + + 7 _ 6 GND 5 1 2-70 + VCC1 (+3 to +20V) 2 + _ 6 7 VEE (_3 to _20V) 3 4 5 VCC2 (+3 to +20V) 8 9 HDW-500 MMP2V2 IC PCM69AP-K (BURR-BROWN) NJM79L05UA (JRC)_5 V(100 mA) NJM79L05UA-TE1 NJM79L09UA(TE1) (JRC)_9 V(100 mA) TA79L12F(TE12L) TA79L12F-TE12L (TOSHIBA)_12 V(0.15 A) C-MOS DUAL 18-BIT D/A CONVERTER —TOP VIEW— 10 A VDD 1 (+5V) D VDD 16 (+5V) 11 12 VOLTAGE REGULATOR VCOM (L) OUT 2 15 TP1 13 14 14 DATA (L) IN I-OUT (L) OUT 3 NC 2 IN OUT 15 BCK SYS-CLK VCOM (L) WDCK I-OUT (L) DATA (L) VCOM (R) I-OUT (R) 2 3 7 6 3 SERVO DC 4 COMMON 1 COMMON IN 1 2 TP1 DATA (R) 13 WDCK IN REF DC 5 OUT 3 SERVO DC REF DC 12 SYS-CLK IN I-OUT (R) OUT 6 4 5 11 BCK IN VCOM (R) OUT 7 10 DATA (R) IN 8 AGND PCM1702U-J (BURR-BROWN)FLAT PACKAGE PCM1702U-J-T2 DGND 9 REF. + SERVO CIRCUIT 2 BUFFER 7 BUFFER VCOM (L) VCOM (R) 20-BIT SERIAL INPUT D/A CONVERTER —TOP VIEW— AVEE DATA IN 1 (_5V) CLOCK IN 2 I OUT 20 1 19 REF DC IN/OUT 3 NC NC 18 DVCC 4 DVEE 6 (_5V) CLOCK LE BPO DC SERVO DC 19 12 DATA (L) DATA (R) 17 BCK SYS-CLK WDCK 17 SERVO DC IN/OUT (+5V) 5 DGND 7 I-OUT (L) ADVANCED 1-BIT DAC 14 10 4 INPUT INTERFACE CIRCUIT 11 12 5 10-BIT DAC + ANALOG CORRECTION CIRCUIT 13 AGND 16 6 SERVO DC REF DC I-OUT (R) ADVANCED 1-BIT DAC AGND 15 LE IN 7 3 DATA REF DC 2 10-BIT DAC + ANALOG CORRECTION CIRCUIT 14 14 I OUT OUT 8 NC NC 13 12 BPO DC IN/OUT 9 NC 10 NC AVCC (+5V) S-8054HN-CB-S (SEIKO I AND E) S-8054HN-CB-T1 11 C-MOS VOLTAGE DETECTOR WITH N-CHANNEL OPEN DRAIN OUTPUT BPO DC CLOCK DATA I OUT LE REF DC SERVO DC ; ; ; ; ; ; ; BIPOLAR OFFSET FILTER BIT CLOCK INPUT SERIAL DATA INPUT CURRENT OUTPUT LATCH ENABLE INPUT REFERENCE FILTER SERVO FILTER —TOP VIEW— 2 VDD 1 OUT GND 3 1 OUT 2 VDD 3 GND VDD 2 VOLTAGE DETECT S-8052-ANY-NH (SEIKO I AND E) S-8052ANY-NH-T1 1 OUT 3 C-MOS VOLTAGE DETECTOR GND —TOP VIEW— 2 1 OUT 2 VDD VDD OUT GND 3 1 3 GND SC7S32F (MOTOROLA)CHIP PACKAGE TC7S32F(TE85R) VDD 2 C-MOS 2-INPUT OR GATE VOLTAGE DETECT —TOP VIEW— 1 1 OUT GND 3 3 GND 5 VDD 2 A 1 B 4 Y = A B Y Y=A+B=A • B A 0 0 1 1 B 0 1 0 1 TYPE 7S32F 7S32FU 4S71F 7SH32FU HDW-500 MMP2V2 4 2 Y 0 1 1 1 0 ; LOW LEVEL 1 ; HIGH LEVEL VDD +2 to +6V +3 to +18V +2 to +5.5V 2-71 IC SM5842APT (NPC) C-MOS 8TIMES OVER SAMPLING DIGITAL FILTER FOR DIGITAL AUDIO —TOP VIEW— CKSLN 28 LRCI OUT DI/INF2N IN 1 1 5 27 DG OUT BCKI IN 2 10 4 26 BCKO OUT CKSLN IN 3 2 25 WCKO OUT INF1N IN 4 21 24 DOL OUT IW1N/DIL IN 5 14 13 23 DOR OUT XTI IN 6 28 VDD(+5V) 22 XTO OUT 7 8 GND 3 21 DITHN IN 16 15 CKO OUT 9 20 MUTEL IN IW2N/DIR IN 10 19 MUTER IN 18 18 FSEL2 IN 20 17 OW1N IN 11 19 OW2N IN 12 17 FSEL1 IN 11 SYNCN IN 13 16 DEMPL IN RSTN IN 14 15 DEMPR IN 12 DI/INF2N DOL IW1N/DIL DOR IW2N/DIR INF1N BCKO WCKO BCKI DG DITHN CKO LRCI 3 24 DI/INF2N BCKI 28 1 2 5 23 10 26 25 XTI 27 XTO 9 CKO INPUT DATA INTERFACE 6 7 9 LRCI DEMPL SYNCN 14 TIMING CONTROLLER 21 13 FSEL1 FSEL2 DEMPL DEMPR 16 26 15 DEEMPHASIS CONTROL MUTEL MUTER FSEL1 OW1N FSEL2 25 OUTPUT DATA 24 INTERFACE 23 17 18 OW2N 7 MUTEL 20 27 MUTE CONTROL 19 11 12 8 INPUT BIT CLOCK OSCILLATE AND INPUT FREQUENCY SELECT (H : 384 fs, L : 256 fs) Lch DEEMPHASIS SIGNAL (L : OFF, H : ON) Rch DEEMPHASIS SIGNAL (L : OFF, H : ON) INPUT DATA (INF1N = L)/INPUT FORMAT SELECT 2 (INF1N = H) DITHER ON/OFF SELECT (L : ON, H : OFF) DEEMPHASIS FILTER SELECT 1 DEEMPHASIS FILTER SELECT 2 fs (Hz) FSEL1 FSEL2 32 k H H 44.1 k L L GND 48 k L H SETTING TERMINAL FUNCTION LR MUTUALLY BELOW STUFFING LR MUTUALLY ABOVE STUFFING L DI TERMINAL DI IW1N IW2N ; ; ; ; H L INF2N DIL DIR H LR MUTUALLY LR SIMULTANEOUSLY ABOVE STUFFING ABOVE STUFFING 24 (USED AS DIL TERMINAL) (USED AS DIR TERMINAL) H L H MUTE SIGNAL Lch (L : NORMAL OUTPUT, H : MUTING) MUTE SIGNAL Rch (L : NORMAL OUTPUT, H : MUTING) OUTPUT WORD LENGTH SELECT 1 OUTPUT WORD LENGTH SELECT 2 OUTPUT WORD LENGTH (BIT) OW1N SETTING OW2N 18 H H 20 L H 22 H L 24 L L RSTN ; SYSTEM RESET (L : SYSTEM RESET, H : NORMAL OPERATION) SYNCN ; SYNCHRONIZATION MODE SELECT (L : FORCED SYNCHRONIZATION MODE, H : JITTER FREE MODE) XTI ; OSCILLATOR INPUT TERMINAL OUTPUT BCKO ; CKO ; DG ; DOL ; DOR ; LRCI ; WCKO ; XTO ; 2-72 DG OW1N OW2N 22 VDD INDEX 29 1 2 3 36 37 4 5 6 7 8 9 OUTPUT BIT CLOCK OSCILLATOR BLOCK OUTPUT CLOCK DEGLITCH OUTPUT Lch DATA OUTPUT Rch DATA OUTPUT INPUT DATA SAMPLING RATE (fs) CLOCK OUTPUT WORD CLOCK OSCILLATOR OUTPUT TERMINAL TTL/ECL 10 6 11 35 12 34 13 33 MUTEL MUTER OW1N OW2N DOR —BOTTOM VIEW— LR SIMULTANEOUSLY ABOVE STUFFING IW1N/DIL ; INPUT WORD LENGTH SELECT 1 (INF1N = L)/Lch DATA INPUT (INF1N = H) IW2N/DIR ; INPUT WORD LENGTH SELECT 2 (INF1N = L)/Rch INPUT DATA (INF1N = H) INPUT FORMAT LR MUTUALLY INPUT WORD BELOW STUFFING 16 18 20 24 LENGTH (BIT) H L H L 5 IW1N/DIL H H L L 10 IW2N/DIR L 4 INF1N (USED AS DI TERMINAL) 1 INF2N/DI DOL 8- OR 10-BIT PARALLEL-TO-SERIAL CONVERTER INPUT FORMAT INF1N INF2N NO. 1 NO. 5 NO. 10 WCKO SBX1601A (SONY) INF1N ; INPUT FORMAT SELECT 1 TERMINAL BCKO XTI XTO MUTER ; ; ; ; ; ; ; ; DITHN DEMPR 6 INPUT BCKI CKSLN DEMPL DEMPR DI/INF2N DITHN FSEL1 FSEL2 INF1N FILTER OPERATION & ATTENUATOR OPERATION BLOCK SYNCN RSTN IW2N/DIR SYSTEM CLOCK RSTN CKSLN 4 IW1N/DIL 7 8 9 10 11 14 12 32 15 31 13 14 16 30 29 15 17 16 18 17 18 28 27 26 25 24 23 22 21 20 19 19 20 21 INPUT D9X - D0X, D9Y - D0Y ; PARALLEL DATA INPUTS PCX, PCY ; PARALLEL CLOCK INPUTS FV ; VCO FREQ. ADJ. INPUT RSE ; VCO RANGE SELECT INPUT (H : HIGH RANGE) TE1 ; TEST TERMINAL (LOW = TEST) TTL/ECL ; VCC FOR INPUT LEVEL SELECT (+5 V = TTL, GND = ECL) OUTPUT LST ; PLL LOCK DETECT OUTPUT (H : LOCK) PCK ; PARALLEL CLOCK OUTPUT SX, SY ; SERIAL DATA OUTPUTS TE2 ; TEST TERMINAL 22 23 24 25 30 31 D9X(MSB) D9Y D8X D8Y D7X D7Y D6X D6Y D5X SX D5Y SY 3 4 D4X D4Y D3X D3Y D2X D2Y D1X LST 1 D1Y D0X(LSB) TE2 34 D0Y PCK PCX 36 PCY FV RSE TE1 33 28 35 VEE1 = _5V VEE2 = _3.5V PIN NO. I/O 1 2 3 4 5 6 7 8 9 10 O — O O — I I I I I SIGNAL PIN NO. I/O LST GND SX SY GND D9X(MSB) D9Y D8X D8Y D7X 11 12 13 14 15 16 17 18 19 20 I I I I I I I I I I SIGNAL PIN NO. I/O SIGNAL D7Y D6X D6Y D5X D5Y D4X D4Y D3X D3Y D2X 21 22 23 24 25 26 27 28 29 30 I I I I I — — I — I D2Y D1X D1Y D0X(LSB) D0Y VEE1 VEE2 RSE TTL/ECL PCX PIN NO. I/O SIGNAL 31 32 33 34 35 36 37 I — I O I O — PCY GND FV TE2 TE1 PCK NC HDW-500 MMP2V2 IC SN74HC10ANS (TI)FLAT PACKAGE SN74HC10ANS-E05 TC74VHC10F (TOSHIBA) FLAT PACKAGE TC74VHC10F(EL) TC74VHC10FS(EL) (TOSHIBA)FLAT PACKAGE SN74CBT3345PW-E05 (TI)FLAT PACKAGE BI-CMOS 8-BIT BUS SWITCH —TOP VIEW— OE1 1 VDD (+4.5 to +5.5 V) 20 A1 2 19 OE2 A2 3 18 B1 A3 4 17 B2 16 B3 A4 5 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 A8 9 12 B7 INPUTS x 1 0 0 x 1 A1 B1 18 3 A2 B2 17 C-MOS 3-INPUT NAND GATE 4 A3 B3 16 —TOP VIEW— 5 A4 B4 15 6 A5 B5 14 7 A6 B6 13 8 A7 B7 12 9 A8 B8 11 14 VDD INPUTS/OUTPUS A, B A=B A=B HI-Z 0 1 x HI-Z 13 12 11 1 OE1 19 OE2 9 8 A B C 1 2 3 4 NOTE : TYPE 40H 74VHC OTHERS : : : : 10 A B C Y= Y Y = ABC = A + B + C 11 B8 10 GND OE2 OE1 2 LOW LEVEL HIGH LEVEL DON’T CARE HIGH IMPEDANCE 5 A 0 0 0 0 1 1 1 1 GND 7 6 VDD +2 to +8V +2 to +5.5V +2 to +6V B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 1 1 1 1 1 1 1 0 0 ; LOW LEVEL 1 ; HIGH LEVEL SN74HC138ANS (TI)FLAT PACKAGE SN74HC138ANS-E05 TC74VHCT138FS(EL) (TOSHIBA)FLAT PACKAGE C-MOS 3-TO-8 LINE DECODER / DEMULTIPLEXER —TOP VIEW— 1 A SN74HC02ANS (TI)FLAT PACKAGE SN74HC02ANS-E05 IN 1 VDD 16 2 3 C-MOS QUAD 2-INPUT NOR GATES B IN C IN 2 15 Y0 OUT 3 14 Y1 OUT EN1 14 VDD 13 EN2 12 11 10 9 8 A A Y = Y B 1 2 3 4 5 6 GND 7 NOTE: VDD +2 to +6V +2 to +5.5V +4.5 to +5.5V +2 to +3.6V TYPE 74HC 74AC/74VHC 74HCT/74ACT 74LCX OUT IN 5 12 Y3 OUT IN 6 11 Y4 OUT OUT 7 10 Y5 OUT 8 GND 9 Y6 OUT TYPE 74HCT 74ACT/74HCT/74VHCT 74AC/74VHC OTHER TYPES VDD +5 V +4.5 to+5.5 V +2 to +5.5 V +2 to +6 V EN2 EN3 Y7 Y 1 0 0 0 B 0 1 0 1 13 Y2 EN3 B Y=A+B=A•B A 0 0 1 1 4 IN SN74HC109ANS (TI)FLAT PACKAGE SN74HC109ANS-E05 Y1 C Y2 15 14 13 12 5 11 Y4 4 10 Y5 EN 9 Y6 6 7 Y7 INPUTS EN C B 0 X X 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 NOTE: 0 ; LOW LEVEL 1 ; HIGH LEVEL Y0 B Y3 —TOP VIEW— EN1 A A Y7 Y6 X 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 0 1 EN = EN1 • EN2 • EN3 Y5 1 1 1 1 1 1 0 1 1 OUTPUTS Y4 Y3 Y2 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 Y1 1 1 0 1 1 1 1 1 1 Y0 1 0 1 1 1 1 1 1 1 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE SN74HC157ANS (TI)FLAT PACKAGE SN74HC157ANS-E05 TC74VHC157FS(EL) (TOSHIBA)FLAT PACKAGE C-MOS J-K FLIP-FLOP WITH DIRECT SET/RESET —TOP VIEW— C-MOS QUAD 2-LINE-TO-1-LINE DATA SELECTOR/ DEMULTIPLEXER —TOP VIEW— 1RD 1 VDD 16 5 (+2V to +6V) 1J 2 15 2RD 1K 3 14 2J 1CK 4 13 2K 1SD 5 12 2CK 1Q 6 11 2SD 1Q 7 10 2Q 8 GND 9 2Q 2 J SD Q 6 14 4 3 INH 11 SD J 10 Q 12 K Q 7 13 RD K 9 Q Y1 YC X1 XC IN IN IN OUT IN IN OUT 15 Y0 14 13 12 11 10 9 15 RD CK J K 0 1 X X X 1 0 1 0 X X X 0 1 0 0 X X X 1* 1* 0 1 Qn Qn 1 1 0 0 0 1 1 1 1 0 1 0 Qn Qn X Qn Qn 0 X Qn+1 Qn+1 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE * ; NONSTABLE VC 4 W0 W1 WC 7 11 X0 10 X1 XC 9 14 Y0 13 Y1 YC 12 3 5 6 0 1 OUTPUTS INPUTS SD V0 V1 2 1 0 0 1 1 X0 1 0 RD 1 1 HDW-500 MMP2V2 16 VDD 1 2 3 4 5 6 A V0 IN IN 7 V1 VC W0 W1 WC IN OUT IN IN OUT GND 8 A 1 NOTE: TYPE 74ACT/74FCT TC74AC157P TC74AC157 TC40H OTHER TYPES VDD +5V +2 to +5.5V +2 to +8V +2 to +6V CONT.IN INH A 0 0 0 1 1 X ON CHANNEL 0 1 GND INH 15 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE 2-73 IC SN74HC193ANS (TI)FLAT PACKAGE SN74HC193ANS-E05 SN74HC373ANS (TI)FLAT PACKAGE SN74HC373ANS-E05 C-MOS PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN COUNTER C-MOS 3-STATE OUTPUT OCTAL LATCHES —TOP VIEW— —TOP VIEW— VDD (+2 to +6V) B (DATA B) IN 1 16 15 1 QB OUT 2 15 A (DATA A) IN 10 9 QA OUT 3 14 RD (RESET) IN 5 CKDN (DOWN CLOCK) IN 4 13 BRW (BORROW) OUT CKUP (UP CLOCK) IN 5 3 11 4 LD QA A B QB C QC D QD CO CKUP BRW CKDN RD 12 CO (CARRY) OUT 14 3 EN IN 1 VDD 20 4 7 2 6 Q1 OUT 2 19 Q8 OUT 8 13 7 D1 IN 3 18 D8 IN 14 17 12 13 D2 IN 4 17 D7 IN 18 11 Q2 OUT 5 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 LE 16 Q7 OUT 2 EN 0 0 0 1 5 6 9 12 15 16 INPUTS D 1 0 X X HI-Z 0 1 X 19 EN ; ; ; ; OUT Q 1 0 QO HI-Z LE 1 1 0 X HIGH IMPEDANCE LOW LEVEL HIGH LEVEL DON'T CARE 1 Q3 OUT 6 15 Q6 OUT QC OUT 6 11 LD (LOAD) IN QD OUT 7 10 C (DATA C) IN D3 IN 7 14 D6 IN 9 D (DATA D) IN D4 IN 8 13 D5 IN 8 GND Q4 OUT 9 RESET TO ZERO PRESET UP COUNT DOWN COUNT NO COUNT CO = CKUP • QA • QB • QC • QD CKUP COUNT = 15 (A = B = C = D = HIGH) CO BRW = CKDN • QA • QB • QC • QD CKDN OUTPUT QD QC QB 0 0 0 0 1 0 0 0 2 0 0 1 3 0 0 1 4 0 1 0 5 0 1 0 6 0 1 1 7 0 1 1 8 1 0 0 9 1 0 0 10 1 0 1 11 1 0 1 12 1 1 0 13 1 1 0 14 1 1 1 15 1 1 1 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE COUNT MODE COUNT = 0 (A = B = C = D = LOW) BRW 12 Q5 OUT VDD +2 to +6V +5V 11 LE IN 10 GND (LATCH ENABLE) QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 2 D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 D Q EN EN LE EN Q LE LE UP COUNT DOWN COUNT CONTROL INPUT RD LD CKUP CKDN X X 1 X X X 0 0 1 0 1 1 0 1 1 1 0 1 NOTE; TYPE AC HC ACT HCT 11 1 SN74HC393ANS (TI)FLAT PACKAGE SN74HC393ANS-E05 C-MOS DUAL 4-BIT BINARY COUNTER —TOP VIEW— QA 3 VDD 14 1CK 1 SN74HC32ANS (TI)FLAT PACKAGE SN74HC32ANS-E05 TC74AC32F (TOSHIBA)FLAT PACKAGE TC74AC32F(EL) TC74VHC32F (TOSHIBA)FLAT PACKAGE TC74VHC32F(EL) TC74VHC32FS(EL) (TOSHIBA)FLAT PACKAGE 1 1RD 2 13 2CK 1QA 3 12 2RD 1QB 4 11 2QA 1QC 5 10 2QB 1QD 6 9 2QC 8 2QD RD 2 QB 4 QC 5 QD 6 QA 11 C-MOS QUAD 2-INPUT OR GATES 7 GND QB 10 QC 9 QD 8 13 RD 12 —TOP VIEW— 14 VDD 13 12 11 10 9 8 A B Y = A B QA 3 (11) 1 2 3 4 5 6 GND 7 B 0 1 0 1 Y 0 1 1 1 NOTE: TYPE 74AC/74VHC 74HC 74HCT 2-74 VDD +2 to +5.5V +2 to +6V +4.5 to +5.5V 0 ; LOW LEVEL 1 ; HIGH LEVEL COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y Y=A+B=A•B A 0 0 1 1 COUNT SEQUENCE CK Q 1 (13) RD RD QB 4 (10) QC 5 (9) Q RD Q RD 2 (12) NOTE: TYPE AC/VHC HC QD 6 (8) Q RD RESET/COUNT FUNCTION RD 1 0 QD 0 QC QB 0 0 COUNT QA 0 0 ; LOW LEVEL 1 ; HIGH LEVEL VDD +2 to +5.5 V +2 to +6 V HDW-500 MMP2V2 IC SN74HC4040ANS (TI)FLAT PACKAGE SN74HC4040ANS-E05 SN74LS164NS (TI)FLAT PACKAGE SN74LS164NS-E05 C-MOS 12-STAGE RIPPLE CARRY BINARY COUNTER/DRIVER TTL 8-BIT PARALLEL OUT SERIAL SHIFT REGISTER —TOP VIEW— —TOP VIEW— Q11 1 Q0 VDD 16 Q1 Q5 2 15 Q10 Q4 3 14 Q9 Q6 4 13 Q7 Q2 Q3 Q4 Q5 10 Q3 5 12 Q8 Q2 6 11 RD Q1 7 10 CK Q6 Q7 Q8 Q9 Q10 Q11 9 VCC (+5 V) A 1 7 5 B 2 13 Q8 Q1 3 12 Q7 Q2 4 11 Q6 A B Q5 CK J J 1 Q7 Q8 Q2 6 J 14 3 K RD 11 H J J 4 K RD H Q 1 Q3 5 10 Q5 Q4 6 9 RD (DIRECT RESET) 7 GND Q K H H 12 13 9 INPUTS RD CK A 0 x x 1 0 x 1 1 1 0 1 x 8 CK (CLOCK) Q11 1 Q1 3 CK (CLOCK) J 5----11 K RD H 11 15 Q3 ----------- Q10 5 --------------- 15 H H H Q 10 RD 11 H Q 2 K RD RD Q1 7 H Q Q6 12 9 Q0 Q0 9 H 10 6 Q4 8 RD 8 GND 5 Q3 D 2 4 13 4 Q2 1 3 2 3 Q1 14 6 8 Q 12 SERIAL IN A K RD SERIAL IN B Q2 4 Q3 5 OUTPUTS B Q1 Q2 ---- Q8 x 0 0 0 0 x Q1o Q2o ---- Q8o 1 1 Q1n ---- Q7n 0 : LOW LEVEL x 0 Q1n ---- Q7n 1 : HIGH LEVEL 0 0 Q1n ---- Q7n x : DON’T CARE Q4 6 Q5 10 Q6 11 Q7 12 Q8 13 1 D 2 Q D Q D Q D Q D Q D Q D Q D Q H RD RD (RESET) RD RD RD RD RD RD RD 9 COUNT Q11 Q10 0 0 0 1 0 0 2 0 0 3 0 0 4095 1 NOTE : TYPE HC VHC 1 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RD Q11--------Q0 1 ALL LOW 0 COUNT 0 ; LOW LEVEL 1 ; HIGH LEVEL 1 SN751177NS (TI)FLAT PACKAGE VDD +2 to +6V +2 to +5.5V DUAL DIFFERENTIAL LINE DRIVER/RECEIVER —TOP VIEW— 16 VCC 1D 1Y 1Z DE 2Z 2Y 2D IN OUT OUT IN OUT OUT IN 15 14 13 12 11 10 9 GND 8 (+5 V) DRIVER BLOCK INPUT ENABLE D DE 1 1 0 1 X 0 OUTPUTS Y Z 1 0 0 1 HI-Z HI-Z RECEIVER BLOCK SN74HC74ANS (TI)FLAT PACKAGE SN74HC74ANS-E05 TC74VHC74F (TOSHIBA)FLAT PACKAGE TC74VHC74F(EL) TC74VHC74FS(EL) (TOSHIBA)FLAT PACKAGE C-MOS DUAL D-TYPE FLIP-FLOPS WITH DIRECT SET/RESET 1 2 3 4 1B IN 1A 1R IN OUT INPUT 1A, 1B, 2A, 2B 1D, 2D DE RE ; ; ; ; 5 6 7 RE 2R 2A 2B IN OUT IN IN RECEIVER DRIVER DRIVER OUTPUT CONTROL RECEIVER OUTPUT CONTROL DIFFERENTIAL INPUT A-B VID > 0.2 V _0.2 V < VID < 0.2 V VID < _0.2 V 0 OR 1 0 1 x HI-Z VID ; ; ; ; ; ENABLE OUTPUT RE R 0 1 0 x 0 0 1 HI-Z LOW LEVEL HIGH LEVEL DON’T CARE HIGH IMPEDANCE XA-XB —TOP VIEW— 14 VDD 13 12 11 10 9 Q SD D Q SD D Q RD 2 3 1 4 5 6 SD 0 1 0 1 1 1 Q RD GND 7 SD D Q 5 12 Q 9 11 3 8 6 RD Q 1 D X X X 1 0 X OUTPUTS Qn+1 Qn+1 1 0 0 1 1 1 1 0 0 1 Qn Qn OUTPUT 1R, 2R ; RECEIVER 1Y, 2Y, 1Z, 2Z ; DRIVER SN75207BNS (TI)FLAT PACKAGE SN75207BNS-E05 NOTE: SD D INPUTS RD CK 1 X X 0 0 X 1 1 1 0 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE 10 4 2 8 RD Q TYPE 74HCT/74ACT 74LVC 74AC/74VHC OTHERS VDD +4.5 to +5.5V +2.7 to +3.6V +2 to +5.5V +2 to +6V BIPOLAR LINE RECEIVER (TTL COMPATIBLE) —TOP VIEW— 14 VCC 13 VEE (+5V) (_5V) A 12 B 11 10 NC Y 9 EN 8 + _ 13 _ + 1 A HDW-500 MMP2V2 2 B NC 3 4 Y 5 EN 6 ENC GND 7 INPUTS EN B–A X B – A > 10mV 0 1 X |B – A| < 10mV 0 1 X B – A < _10mV ENC 0 X 1 0 X 1 X OUT Y 1 1 0 1 1 * 1 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE * ; INDETERMINATE 2-75 IC SN75C1168NS-E05 (TI)FLAT PACKAGE TC74HC123AF (TOSHIBA)FLAT PACKAGE TC74HC123AF(EL) BI-CMOS DUAL DIFFERENTIAL LINE DRIVER/RECEIVER —TOP VIEW— C-MOS DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS 1A 1B IN 1 VDD (+5 V) 16 1A IN 2 1B 15 1D IN 2A 1R OUT 3 14 1Y OUT 1DE IN 4 13 1Z OUT 2R OUT 5 12 2DE IN 1D 2A IN 6 11 2Z OUT 1DE 2B IN 7 2B 2D 10 2Y OUT 2DE 9 2D IN 8 GND —TOP VIEW— 2 3 1 1R R C VDD 6 5 7 16 VDD 2R 15 14 1Y 13 1Z 15 RD 10 2Y 11 2Z 0 1 ? x HI-Z : : : : : Q Q Q 9 2 3 4 5 A B RD Q Q A 9 INPUTS RD A B 0 X X 1 1 X 1 X 0 1 0 1 1 1 0 6 GND 8 7 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON'T CARE OUTPUT PULSE WIDTH = 0.46 CR VDD R C OUTPUTS Q Q 0 1 0 1 0 1 12 RECEIVER BLOCK 2 Q DIFFERENTIAL INPUT OUTPUT A-B R VID > 0.2 V 1 _0.2 V < VID < 0.2 V ? VID < 0.2 V 0 OPEN 1 6 15 CR 13 Q C OUTPUTS Y Z 1 0 0 1 HI-Z HI-Z B 10 RD Q 1 14 INPUT ENABLE D DE 1 1 0 1 x 0 RD 11 Q 12 4 1 DRIVER BLOCK Q 13 14 C 9 10 4 Q RD 3 NOTE : 7 CR 5 Q TYPE TC74HC123AF TC74VHC OTHER TYPES 12 RD 11 VDD +5V +2V to +5.5V +2V to +6V LOW LEVEL HIGH LEVEL INDETERMINATE DON’T CARE HIGH IMPEDANCE TC74HC133AF (TOSHIBA)FLAT PACKAGE MC74HC133F C-MOS 13-INPUT NAND GATE —TOP VIEW— 16 VCC TC4W66F (TOSHIBA)CHIP PACKAGE TC4W66F(TE12R) M 15 L 14 K 13 J 12 I 11 H 10 2 B 3 S 4 D 5 E 6 F 7 G Y 9 (+2 to +6V) C-MOS DUAL BILATERAL SWITCH (SCALE 3/1) —TOP VIEW— 1 8 VDD(+3 to+18V) 2 7 3 6 GND 4 5 1 A 2 1 GND 8 7 IN/OUT Y=A•B•C•D•E•F•G•H•I•J•K•L•M 6 5 IN/OUT 3 CONTROL CONTROL 0 1 SWITCH OFF ON 0 ; LOW LEVEL 1 ; HIGH LEVEL TC74HC86AF (TOSHIBA)FLAT PACKAGE TC74VHC86FS(EL) (TOSHIBA)FLAT PACKAGE SN74HC86ANS-E05 C-MOS QUAD EXCLUSIVE OR GATES —TOP VIEW— 14 TC74AC139F (TOSHIBA)FLAT PACKAGE TC74AC139F(EL) 13 12 11 10 9 8 C-MOS DUAL 2-TO-4 DECODER/DEMULTIPLEXER IN 1 1A IN 2 VDD 16 2 3 15 2EN IN Y0 A Y1 Y2 B EN 1B IN 3 14 2A IN 1Y0 OUT 4 13 2B IN 1Y1 OUT 5 12 2Y0 OUT 1Y2 OUT 6 11 2Y1 OUT 1Y3 OUT 7 10 2Y2 OUT 8 GND 9 2Y3 OUT NOTE : TYPE TC74AC/TC74VHC HCT/ACT OTHER TYPES 2-76 Y Y=A•B+A•B —TOP VIEW— 1EN A B VDD Y3 4 5 14 6 13 7 Y1 B Y2 EN 1 INPUTS EN B A 0 0 0 1 0 0 0 1 0 1 1 0 1 X X Y0 A Y3 15 OUTPUTS Y3 Y2 Y1 Y0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 12 11 1 2 3 4 5 6 GND 7 A 0 0 1 1 B 0 1 0 1 Y 0 1 1 0 0 ; LOW LEVEL 1 ; HIGH LEVEL 10 9 NOTE : TYPE 74AC/74VHC 74ACT/74HCT 74LCX OTHER TYPES VDD +2 to +5.5V +4.5 to +5.5V +2 to +3.6V +2 to +6V 0 ; LOW LEVEL 1 ; HIGH LEVEL X ; DON’T CARE VDD +2 to +5.5V +5V +2 to +6V HDW-500 MMP2V2 IC TC74HC4024AF (TOSHIBA)FLAT PACKAGE TC74HC4024AF(EL) TC74HC688AF (TOSHIBA)FLAT PACKAGE TC74HC688AF(EL) C-MOS 7-STAGE BINARY COUNTER C-MOS 8-BIT EQUALITY DETECTOR —TOP VIEW— —TOP VIEW— VDD (+2 to +6V) G 1 CK IN 1 Q1 VDD (+2 to +6 V) 14 CLR IN 2 Q7 OUT 3 12 Q1 OUT Q6 OUT 4 18 Q7 P1 4 17 P7 17 Q1 5 16 Q6 3 Q7 CLR 15 P6 P2 6 7 9 Q2 7 9 Q3 OUT 14 Q5 12 14 7 GND P3 8 NC 8 13 P5 16 18 Q3 9 Q1 12 Q2 11 Q3 9 Q4 6 Q5 5 Q6 4 P6 CK CLR D D D D D CK Q R CK Q R CK Q R CK Q R Q6 Q 1 CK Q R CK Q R CK R P5 Q5 2 P4 Q4 P3 COUNT 0 1 2 3 Q3 OUTPUTS Q7 Q6 Q5 Q4 Q3 Q2 Q1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 INPUTS CK CLR x 1 0 0 0 P2 Q2 P1 Q1 P0 Q0 G 125 126 127 — — 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 12 Q4 10 GND P7 D P2 P3 P4 P5 P6 P7 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 G 1 Q7 3 Q7 D P1 P=Q 5 NC 10 Q4 OUT 6 P0 3 2 Q5 OUT 5 13 15 4 Q6 11 Q2 OUT Q0 3 5 Q5 8 11 6 Q4 CK 19 P = Q P0 2 9 Q3 1 4 6 11 Q2 NC 13 2 20 12 11 P4 17 18 15 16 13 14 11 12 19 8 9 6 7 4 OUTPUTS P=Q 0 1 1 1 INPUTS P, Q G P=Q 0 P>Q 0 P
Source Exif Data:File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.2 Linearized : No Create Date : 1998:01:14 17:39:19 Producer : Acrobat Distiller 3.0 for Power Macintosh Modify Date : 1998:01:22 14:16:56 Title : HDW-500 Subject : PDF Author : K.Ohi Page Count : 638EXIF Metadata provided by EXIF.tools