Calpella_dis_uma_090413 HP Compaq CQ36 LA 4743P

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A

B

C

D

E

1

1

Compal confidential

2

2

Schematics Document
Mobile Auburndale rPGA989 with
Intel PCH(Ibex Peak-M) core logic

3

3

2009-04-13

4

4

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

Cover Sheet
Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
B

C

D

Compal Electronics, Inc.

Da te:

Rev
0.1

LA4743P
Sheet

Monday, April 13, 2009
E

1

of

49

A

B

Compal confidential

Fan conn

C

D

Calpella Consumer 13.3" UMA +Switchable

Page 6

CK505

1

P19

PCIE-Express 16X

2C CPU + GMCH

page 24,25,26,27

Socket-rPGA989
VRAM DDR3
128/512MB

page 21

Dis

SO-DIMM X2
DDR3 1066/1333 MHz 1.5V DDR3
BANK 0, 1, 2, 3

P17, 18

LCD Conn.

page 28,29

32QFN

Clock Generator
SLG8SP585VTR

Mobile Arrandale

1

Nvidia
NB10M-GE

E

Page 6,7,8,9,10

UMA

Dual Channel

Dis(UMA)

MUX

USB Card Reader
P33

CRT

DMI X4

page 20
UMA

Dis

USB conn x3

Dis(UMA)

MUX

P36

2

2

USB2.0 X12

Dis

HDMI Conn.
page 23

Level Shifter

BT Conn

Intel PCH

UMA

USB Camera

page 23

P21

Azalia

Ibex Peak-M
FCBGA 951

PCI-E BUS*4

P36

SATA Master-1

Finger print

P36

SATA Slave
Page 11,12,13,14,15,16

Audio CKT
Audio Jack

Codec_IDT92HD81

JMC261 (LAN
+Card reader)
P31

Mini-Card
WLAN

P34

Mini-Card
New Card

WWAN
P32

P35

SPI

P32

LPC BUS

P32

3

3

P34

SPI ROM 16M
MX25L1605AM2C-15G

RJ45/11 CONN

SATA HDD Connector

P31

P30

ENE
KB926

SATA ODD Connector

P30

P38

RTC CKT.

P38

P39

P36

P21

Int.KBD

Touch Pad CONN.

LED

SPI ROM
SST25VF080

ACCELEROMETER
P27
ST

USB Board Conn
USB conn x2

P37

P33

4

4

K/B backlight Conn

Capsense switch Conn
P36

P36

Compal Secret Data

Security Classification

DC/DC Interface CKT.
P38

A

2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Block Diagram
Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
B

C

D

Compal Electronics, Inc.

Da te:

Rev
0.1

LA4743P
Sheet

Monday, April 13, 2009
E

2

of

49

A

Symbol Note :

Voltage Rails

O

MEANS ON

USB assignment:

X MEANS OFF

: means Digital Ground

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)

: means Analog Ground
power
plane

USB-3

X

USB-4

Camera

USB-5 WLAN
+5VALW

+B

+1.8V

+5VS
+3VS

+3VALW

45@ : means need be mounted when 45 level assy or rework stage.

+1.5VS
+0.9V

+2.5VS

USB-11 X

UMA@ : means stuff when UMA skus

PCIe assignment:
PCIe-1 WWAN

VRAM@ : X76 level
S0

O

O

O

O

8111DL@ : Only for Giga LAN

S1

O

O

O

O

DEBUG@ : For debug

O

O

O

MiniCard(WWAN/TV)

SG@ : means stuff when Switchable graphic

+1.8VS

S3

Finger Printer

USB-8

USB-10 X

CONN@ : means ME part

+CPU_CORE

USB-7

USB-9 Express card

BATT @ : means need be mounted when 45 level assy or rework stage.

+VCCP

State

USB-6 Bluetooth

@ : means just reserve , no build

PCIe-2 WLAN
PCIe-3 LAN
PCIe-4

X

New card

PCIe-5 X

Cypress@ : Only For Cypress Capacitor sensor board

PCIe-6 X

ENE@ : Only For ENE Capacitor sensor board
S5 S4/AC

O

O

X

X

M3@ : Only For Intel DDR3 VREF

SATA assignment:

PA@ : Only For PA

SATA0 HDD

S5 S4/ Battery only

O

X

X

X

S5 S4/AC & Battery
don't exist

X

X

X

X

SATA1 ODD

PR@ : Only For PR

SATA2 X
SATA3 X

1

1

SATA4 ESATA
SATA5 X

SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

SOURCE

XDP

KB926

X

BATT

Thermal
Sensor

SODIMM

V

X

X

WLAN
CLK CHIP WWAN

X

X

NEW
CARD

NB10M
Thermal NB10M-GE Cap sensor
board
Sensor

X

X

V

X

PCH I2C / SMBUS ADDRESSING
G sensor

X

DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

D2

11010010

KB926

X

X

X

X

X

X

X

X

X

X

X

CLOCK GENERATOR (EXT.)

PCH

V

X

X

V

V

V

X

X

X

V

V

45172932L01ΚSwitchable graphic

PCH

X

X

X

X

X

X

X

X

X

X

X

PCH

X

X

X

X

X

X

X

X

X

X

X

+3VS

+5VL

+3VS

+3VS

+3VALW

+5VL

+3VALW

45172932L02ΚUMA only

+3VS

NB10M-GE SMBUS Control Table
SOURCE
D_EDID_DATA
D_EDID_CLK
D_CRT_DDC_DATA
D_CRT_DDC_DATA
HDMIDAT_VGA
HDMICLK_VGA

LVDS

CRT

HDMI

NB10M

V

X

X

NB10M

X

V

X

NB10M

X

X

V

Compal Secret Data

Security Classification
2007/08/28

Issued Date

Deciphered Date

Title

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Notes List
Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
A

Compal Electronics, Inc.

Da te:

Rev
0 .1

LA 4743P

Monday, April 13, 2009

Sheet

3

of

49

5

4

3

2

1

60mA

50mA

25mA
1A
D

+V_BATTERY

Dock con

35mA

MDC 1.5

169mA

INVPWR_B+

ICH9

1A

1.7A

+3VALW

811mA

LAN

VIN

2A

10mA

LVDS CON
300mA

AC

5.89A

3.39A

B++

+3VS

??mA

C

+1.5VS

1.5A

0.58A

+5VALW

???A

1.3A

Mini card

1A

New card

1A

35mA

+5VS

B+
7A

10mA

1.8A

700mA
B

3A

3.7 X 3=11.1V

B+++

11.05A

8 A

+1.5V
50mA

DDR3

800Mhz

1.05V_B+

PCH
+LCDVDD

LVDS CON

+1.05VS

10mA

+VCC_CORE

+3VS_CK505
C

Mini card (WLAN)
Mini card (TV tu/WWAN/Robeson)

+VDDA
IDT 9271B7
+5VAMP
ODD
SATA
PC Camera(4.75V)

PCH

38A/1.05V

CPU

A

2.59A

PCH

CPU

Compal Secret Data

Security Classification
Issued Date

2007/08/28

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

http://laptop-motherboard-schematic.blogspot.com/
4

B

+VCCP

A

5

New card

+0.75V

??A

CPU_B+

SPI ROM

4G x2

162mA
4.7A

2A

+3VALW_EC

CPU
50mA

BATT
1.9A

+3VS_DVDD
ALC268

RT5158
250mA

DC

Finger printer

D

20mA

0.3A

+3VAUX_BT

3

2

Title

Compal Electronics, Inc.
Power delevry

Size
C
Da te:

Do cu me n t Number

Rev
0.1

Calpella DIS LA4743P
Mo n d a y, April 13, 2009

Sheet
1

4

of

49

A

1

1

Compal Secret Data

Security Classification
2007/08/28

Issued Date

Deciphered Date

Title

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Notes List
Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
A

Compal Electronics, Inc.

Da te:

Rev
0 .1

LA 4743P

Monday, April 13, 2009

Sheet

5

of

49

5

Layout rule Κ 10m il
width trace length <
0.5", spacing 20mil

4

R7 1

2 49.9_0402_1% C O M P0 AT26
T P _ S KTOCC#

T1

H _ P E C I_ISO
0_0402_5%

1

2

R 15

AK14

AT15

H _ P R O C HOT# AN26

<46> H _ P R O C HOT#

<14> H _ T H E R MTRIP#

AH24

H _ T H E R M TRIP#_R AK15
0_0402_5%

1

2

COMP2
COMP1
COMP0
SKTOCC#
CATERR#

THERMAL

H _ C A T E RR#

G16

PECI

PROCHOT#

THERMTRIP#

BCLK
BCLK#

CLOCKS

2 49.9_0402_1% C O M P1

BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]

2

H _ C P U R S T#_R
0_0402_5%

AP26

R 20

1

2

H _ P M _ S Y N C_R
0_0402_5%

AL15

R 21

1

2S Y S _ A G E N T _PWROK AN14
0_0402_5%

<14> H _ C P U P W R G D

C<13> P M _ D R A M _ P WRGD

R 23

1

2

R 24

1

2

RESET_OBS#
PM_SYNC
VCCPWRGOOD_1

V C C P W R G O OD_0 AN27
0_0402_5%

VCCPWRGOOD_0

V D D P W R G O O D _R AK13
0_0402_5%

SM_DRAMPWROK

From power

AM15

<44> V T T P W R GOOD
R 25

1

2

R 26

1

2

H _ P W R G D _XDP_R AM26
0_0402_5%

1.5K_0402_1%

P L T_RST#_R

AL14

TAPPWRGOOD

TDI
TDO
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

E16
D16

C L K_EXP
C LK_EXP#

A18
A17

J P1

C L K _ C P U_BCLK <14>
C L K _ C P U_BCLK# <14>

C LK_EXP <12>
C LK_EXP# <12>

X D P _PREQ#
X D P _ P R DY#
X DP_BPM#0
X DP_BPM#1

OK
+VCCP

X DP_BPM#2
X DP_BPM#3

eDP

F6

@ C1
0 .1U_0402_16V4Z

D R A M R ST# <17,18>

AL1
AM1
AN1

S M _ R COMP0
S M _ R COMP1
S M _ R COMP2

AN15
AP15

PM_EXTTS#0
PM_EXTTS#1

AT28
AP27

X D P _ P R DY#
X D P _PREQ#

AN28
AP28
AT27

X D P_TCK
X DP_TMS
X D P_TRST#

AT29
AR27
AR29
AP29

X D P _TDI_R
X D P _TDO_R
X D P_TDI_M
X D P_TDO_M

AN25

X D P _ D BRESET#

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

X DP_BPM#0
X DP_BPM#1
X DP_BPM#2
X DP_BPM#3
X DP_BPM#4
X DP_BPM#5
X DP_BPM#6
X DP_BPM#7

X DP_BPM#4
X DP_BPM#5

2

R 13
1K_0402_5%
R 14

1

T63 P A D
2 0_0402_5%

H_CPUPWRGD

1

2

<13> P M _ P W R B TN#_R

P M_EXTTS#1_R <17,18>

H _ P W R G D _XDP R 1 61

X DP_BPM#6
X DP_BPM#7
H _ C P U P W R G D _R
P M _ P W R B TN#_R

2 0_0402_5%

X D P_TCK

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

SAMTE_BSH-030-01-L-D-A

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

X D P_TDI

@ R2 1

2 51_0402_1%

X DP_TMS

@ R4 1

2 51_0402_1%

X D P _PREQ# @ R6 1

2 51_0402_1%

X D P_TDO

2 51_0402_1%

R8 1

This shall place near CPU
X D P_TCK

@ R9 1

D

+VCCP

C L K _ C PU_XDP
C L K _ C PU_XDP#

R 17
1K_0402_5%

X D P _RST#_R
X D P _ D BRESET#_R 1

1

@ R22

X D P _ D BRESET# <13>

+ 3VS

C O NN@

2 0_0402_5%

1

H _ C P U R ST#

2
2

R18
0_0402_5%

X D P_TDO
X D P_TRST#
X D P_TDI
X DP_TMS

R 603 1

X D P _ D BRESET#

X D P _RST#_R

2 51_0402_1%

2 1K_0402_5%

P L T_RST# <14,31,32>

C

+ V C CP

I C , A U B _ C F D_rPGA,R1P0
C ONN@

PM_EXTTS#0

R27

1

2 10K_0402_5%

PM_EXTTS#1

R29

1

2 10K_0402_5%

2

R28
750_0402_1%

C L K _ C PU_XDP
C L K _ C PU_XDP#

XDP Connector

RSTIN#

1

H _ P W R G D _XDP

<14> B U F _ PLT_RST#

VTTPWRGOOD

TCK
TMS
TRST#

JTAG & BPM

H_CPUPWRGD

1

PWR MANAGEMENT

<13> H _ P M _ S Y NC

R 19

C L K _ C P U_BCLK
C L K _ C P U_BCLK#

from DDR

PRDY#
PREQ#
H _ C P U R ST#

A16
B16
AR30
AT30

1

DDR3
MISC

2 20_0402_1% C O M P2 AT24

R5 1

COMP3

MISC

R3 1

R 10

1

+VCCP

2 20_0402_1% C O M P3 AT23

D

H_PECI

2

JCPU1B

R1 1

P AD

<14>

3

JTAG MAPPING
R30

X D P _TDI_R

2 0_0402_5%

1

+ 1.5V

X D P_TDI
V D D P W R G O O D _R

X D P_TDO_M

R33

1

2 12K_0402_1%

2

1

2 49.9_0402_1%

1

2 68_0402_5%

R 11

2

1 68_0402_5%

H _ P R O C HOT#

X D P_TDO

2 4.75K_0402_1%

R34
0_0402_5%

CRB 0.9 R38 change to 1K

1

R 35

H _ C P U R S T#_R @ R 36
B

2 0_0402_5%

1

1

+ V C CP

Processor Pullups
H _ C A T E RR#

@ R32

R31

B

X D P_TDI_M @ R 3 7

1

2 0_0402_5%

X D P _TDO_R

R38

1

2 0_0402_5%

X D P_TRST#

R39

1

2 51_0402_1%

Fan Voltage Control circuit
SI-1 Change to voltage control circuit

DDR3 Compensation Signals
S M _ R COMP0

R40

1

2 100_0402_1%

+ 3VS

S M _ R COMP1

R41

1

2 24.9_0402_1%

2

+ 5 VS

S M _ R COMP2

R42

2 130_0402_1%

1

R 678
10K_0402_5%

<37> F A N _ S P E ED

F A N _ S P E ED

C 775
1000P_0402_50V7K

1

9
8
7
6
5

C2
2 .2U_0603_6.3V4Z

1

2

U 32

1

Layout Note:Please these
resistors near Processor

1

Thermal Pad VEN
GND
VIN
GND
VO
GND
VSET
GND

1
2
3
4

G 9 9 6 RD1U_TDFN8_3X3

C3
0 .1U_0402_16V4Z

2
+ 5 V S _FAN
F A N _ S P E ED

1

2

C 774
2 .2U_0603_6.3V4Z

C ONN@
JFAN1

1
2
3

1
2
3

G1
G2

4
5

ACES_85204-03001

+ 5VS
D1

2

<37>

3
2
1

F A N _ S ET

Vcc
Line to be protected
GND
DLPT05-7-F_SOT23-3

A

A

Compal Secret Data

S ecurity Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Title

Compal Electronics, Inc.
Auburndale(1/5)-Thermal/XDP

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P

Monday, April 13, 2009

Sheet
1

6

of

49

5

4

3

2

1

Layout ruleΚ trace
length < 0.5"
J CPU1E
J CPU1A

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B24
D23
B23
A22

<13>
<13>
<13>
<13>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

D24
G24
F23
H23

<13>
<13>
<13>
<13>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

D25
F24
E23
G23

<13>
<13>
<13>
<13>
<13>
<13>
<13>
<13>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

E22
D21
D19
D18
G21
E19
F21
G18

<13>
<13>
<13>
<13>
<13>
<13>
<13>
<13>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

D22
C21
D20
C18
G22
E20
F20
G19

<13> F DI_ F S YNC0
<13> F DI_ F S YNC1

F17
E17

<13> F DI_INT

C17

<13> F DI_ L SYNC0
<13> F DI_ L SYNC1

F18
D17

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

RSVD32
RSVD33

B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N15

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P15

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

PCIE_CTX_GRX_C_N0
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N15

SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@

C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PCIE_CTX_GRX_C_P0
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P15

SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@

C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

EXP_RBIAS

R44
R45

2 49.9_0402_1%

1

2 750_0402_1%
PCIE_CRX_GTX_N[0..15] <24>

1

+ V _ DDR_CPU_REF0
+ V _ DDR_CPU_REF1

AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

RSVD34
RSVD35
RSVD36
RSVD_NCTF_37
RSVD38
RSVD39

RSVD_NCTF_40
RSVD_NCTF_41
RSVD_NCTF_42
RSVD_NCTF_43

PCIE_CRX_GTX_P[0..15] <24>
CF G0
CF G1
CF G2
CF G3
CF G4
CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17
CF G18

PCIE_CTX_GRX_N[0..15] <24>

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16

B19
A19
@ R50
@ R51

1
1

2 0_0402_5%
2 0_0402_5%

A20
B20
U9
T9
AC9
AB9

PCIE_CTX_GRX_P[0..15] <24>

C1
A3

J29
J28
A34
A33
C35
B35

B

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RESERVED

<13>
<13>
<13>
<13>

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

PCI EXPRESS -- GRAPHICS

A24
C23
B22
A21

Intel(R) FDI

C

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI

D

<13>
<13>
<13>
<13>

EXP_ICOMPI

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65

AJ13
AJ12
AH25
AK26
AL26
AR2
D

AJ26
AJ27

AP1
AT2
AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
E15
F15
A2
D15
C15
AJ15
AH15

C

@ R48
@ R49

2 0_0402_5%
2 0_0402_5%

1
1

RSVD15
RSVD16
RSVD17
RSVD18
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD19
RSVD20
RSVD21
RSVD22

RSVD_NCTF_23
RSVD_NCTF_24

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

RSVD26
RSVD27
RSVD_NCTF_28
RSVD_NCTF_29
RSVD_NCTF_30
RSVD_NCTF_31

IC,A UB_CFD_rPGA,R1P0
C ONN@

VSS

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

B

AP34

IC,A UB_CFD_rPGA,R1P0
C ONN@

CRB 0.9 change to GND

CFG Straps for PROCESSOR
CF G0

@ R52

2 3.01K_0402_1%

1

CF G4

PCI-Express Configuration Select

A

1: D i s abled; No Physical
D isplay Port

*

N o t a p p l i cable for Clarksfield Processor
C FG4
CF G3

R54

2 3.01K_0402_1%

1

C F G 3 - P C I Express Static Lane Reversal
C FG3

1: N o rmal Operation
0 : L a n e Numbers Reversed
15 - > 0, 14 ->1, .....

*

5

2 3.01K_0402_1%

C F G 4 - Display Port Presence

1: Single PEG
0: B i f urcation enabled

C FG0

@ R53 1

*

a t t a c h e d to Embedded Display Port
0: E n a bled; An external
D isplay Port
d e v i c e is connected to the
E m b e d ded Display Port

CF G7 @ R55

1

2 3.01K_0402_1%

Only temporary for early
CFD samples (rPGA/BGA)
Only for pre ES1 sample

A

CFG7

WW33 GPD 3.01K on CFG7 for PCIE Jitter
WW41Κ don't staff
Compal Secret Data

Security Classification
2008/03/13

Issued Date

2009/05/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.
Auburndale(2/5)-DMI/PEG/FDI

Da te:

Rev
0.1

LA4743P
Sheet

Monday, April 13, 2009
1

7

of

49

5

4

3

2

1

J CP U1D
J CP U1C

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

<17> DDR_ A _D[0..63]

C

B

A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

<17> DDR_A_BS0
<17> DDR_A_BS1
<17> DDR_A_BS2

AC3
AB2
U7

<17> DDR_A_CAS#
<17> DDR_A_RAS#
<17> DDR_A_WE#

AE1
AB3
AE9

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

DDR SYSTEM MEMORY A

DDR_ A_D0
DDR_ A_D1
DDR_ A_D2
DDR_ A_D3
DDR_ A_D4
DDR_ A_D5
DDR_ A_D6
DDR_ A_D7
DDR_ A_D8
DDR_ A_D9
DDR _A_D10
DDR _A_D11
DDR _A_D12
DDR _A_D13
DDR _A_D14
DDR _A_D15
DDR _A_D16
DDR _A_D17
DDR _A_D18
DDR _A_D19
DDR _A_D20
DDR _A_D21
DDR _A_D22
DDR _A_D23
DDR _A_D24
DDR _A_D25
DDR _A_D26
DDR _A_D27
DDR _A_D28
DDR _A_D29
DDR _A_D30
DDR _A_D31
DDR _A_D32
DDR _A_D33
DDR _A_D34
DDR _A_D35
DDR _A_D36
DDR _A_D37
DDR _A_D38
DDR _A_D39
DDR _A_D40
DDR _A_D41
DDR _A_D42
DDR _A_D43
DDR _A_D44
DDR _A_D45
DDR _A_D46
DDR _A_D47
DDR _A_D48
DDR _A_D49
DDR _A_D50
DDR _A_D51
DDR _A_D52
DDR _A_D53
DDR _A_D54
DDR _A_D55
DDR _A_D56
DDR _A_D57
DDR _A_D58
DDR _A_D59
DDR _A_D60
DDR _A_D61
DDR _A_D62
DDR _A_D63

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

<18> DDR_ B _D[0..63]

AA6
AA7
P7

M _ CLK_DDR0 <17>
M _CLK_DDR#0 <17>
DDR_CKE0_DIMMA <17>

Y6
Y5
P6

M _ CLK_DDR1 <17>
M _CLK_DDR#1 <17>
DDR_CKE1_DIMMA <17>

AE2
AE8

DDR_CS0_DIMMA# <17>
DDR_CS1_DIMMA# <17>

AD8
AF9

M_ODT0 <17>
M_ODT1 <17>

B9
D7
H7
M7
AG6
AM7
AN10
AN13

DDR _A_DM0
DDR _A_DM1
DDR _A_DM2
DDR _A_DM3
DDR _A_DM4
DDR _A_DM5
DDR _A_DM6
DDR _A_DM7

C9
F8
J9
N9
AH7
AK9
AP11
AT13

DDR _A_DQS#0
DDR _A_DQS#1
DDR _A_DQS#2
DDR _A_DQS#3
DDR _A_DQS#4
DDR _A_DQS#5
DDR _A_DQS#6
DDR _A_DQS#7

C8
F9
H9
M9
AH8
AK10
AN11
AR13

DDR _A_DQS0
DDR _A_DQS1
DDR _A_DQS2
DDR _A_DQS3
DDR _A_DQS4
DDR _A_DQS5
DDR _A_DQS6
DDR _A_DQS7

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

D DR_A_MA0
D DR_A_MA1
D DR_A_MA2
D DR_A_MA3
D DR_A_MA4
D DR_A_MA5
D DR_A_MA6
D DR_A_MA7
D DR_A_MA8
D DR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_ B_D0
DDR_ B_D1
DDR_ B_D2
DDR_ B_D3
DDR_ B_D4
DDR_ B_D5
DDR_ B_D6
DDR_ B_D7
DDR_ B_D8
DDR_ B_D9
DDR _B_D10
DDR _B_D11
DDR _B_D12
DDR _B_D13
DDR _B_D14
DDR _B_D15
DDR _B_D16
DDR _B_D17
DDR _B_D18
DDR _B_D19
DDR _B_D20
DDR _B_D21
DDR _B_D22
DDR _B_D23
DDR _B_D24
DDR _B_D25
DDR _B_D26
DDR _B_D27
DDR _B_D28
DDR _B_D29
DDR _B_D30
DDR _B_D31
DDR _B_D32
DDR _B_D33
DDR _B_D34
DDR _B_D35
DDR _B_D36
DDR _B_D37
DDR _B_D38
DDR _B_D39
DDR _B_D40
DDR _B_D41
DDR _B_D42
DDR _B_D43
DDR _B_D44
DDR _B_D45
DDR _B_D46
DDR _B_D47
DDR _B_D48
DDR _B_D49
DDR _B_D50
DDR _B_D51
DDR _B_D52
DDR _B_D53
DDR _B_D54
DDR _B_D55
DDR _B_D56
DDR _B_D57
DDR _B_D58
DDR _B_D59
DDR _B_D60
DDR _B_D61
DDR _B_D62
DDR _B_D63

DDR_ A _DM[0..7] <17>

DDR_ A_DQS#[0..7] <17>

DDR_ A _DQS[0..7] <17>

DDR_A_MA[0..15] <17>

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10

<18> DDR_B_BS0
<18> DDR_B_BS1
<18> DDR_B_BS2

AB1
W5
R7

<18> DDR_B_CAS#
<18> DDR_B_RAS#
<18> DDR_B_WE#

AC5
Y7
AC6

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

W8
W9
M3

M _ CLK_DDR2 <18>
M _ CLK_DDR#2 <18>
DDR_CKE2_DIMMB <18>

V7
V6
M2

M _ CLK_DDR3 <18>
M _ CLK_DDR#3 <18>
DDR_CKE3_DIMMB <18>

AB8
AD6

DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>

AC7
AD1

M_ODT2 <18>
M_ODT3 <18>

D4
E1
H3
K1
AH1
AL2
AR4
AT8

DDR _B_DM0
DDR _B_DM1
DDR _B_DM2
DDR _B_DM3
DDR _B_DM4
DDR _B_DM5
DDR _B_DM6
DDR _B_DM7

D5
F4
J4
L4
AH2
AL4
AR5
AR8

DDR _B_DQS#0
DDR _B_DQS#1
DDR _B_DQS#2
DDR _B_DQS#3
DDR _B_DQS#4
DDR _B_DQS#5
DDR _B_DQS#6
DDR _B_DQS#7

C5
E3
H4
M5
AG2
AL5
AP5
AR7

DDR _B_DQS0
DDR _B_DQS1
DDR _B_DQS2
DDR _B_DQS3
DDR _B_DQS4
DDR _B_DQS5
DDR _B_DQS6
DDR _B_DQS7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

D DR_B_MA0
D DR_B_MA1
D DR_B_MA2
D DR_B_MA3
D DR_B_MA4
D DR_B_MA5
D DR_B_MA6
D DR_B_MA7
D DR_B_MA8
D DR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

D

DDR_ B _DM[0..7] <18>

C

DDR SYSTEM MEMORY - B

D

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#

DDR_ B _DQS#[0..7] <18>

DDR_ B _ DQS[0..7] <18>

DDR_B_MA[0..15] <18>

B

IC,A UB_CFD_rPGA,R1P0
C ONN@
IC,A UB_CFD_rPGA,R1P0
C ONN@

A

A

Compal Secret Data

Security Classification
2008/03/13

Issued Date

2009/05/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title

Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.
Cantiga(2/6)-DDR3 A/B CH

Da te:

Rev
0.1

LA4743P
Sheet

Monday, April 13, 2009
1

8

of

49

5

4

3

2

1

+ V CC_CORE
+VGA_CORE

1

2 0_0603_5%

POWER

P10
N10
L10
K10

1

1

2

1

2

1

2

H_PSI# <46>
H_ VID0
H_ VID1
H_ VID2
H_ VID3
H_ VID4
H_ VID5
H_ VID6
PM_DPRSLPVR_R R58

VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

SENSE
LINES
0.6A

H_ V ID[0..6] <46>

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

J22
J20
J18
H21
H20
H19
1

2

L26
L27
M26

to power
1

2 0_0402_5%

1

H_ DPRSLPVR <46>

2

IC,A UB_CFD_rPGA,R1P0
C ONN@

1

2

1

2

1

2

1

2

2

1

2

+ V CCP

2

2

+1.5V

C

+ V CCP

1

1

C60
1U_0603_10V4Z

2

1

C59
1U_0603_10V4Z

C58
1U_0603_10V4Z

2

1

C66
22U_0805_6.3V6M

C57
1U_0603_10V4Z

1

C65
22U_0805_6.3V6M

2

2
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25

PEG & DMI

CPU VIDS

+

+ V CCP

to power
AN33
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

1

C79
1U_0603_10V4Z

R57

1.1V

+VTT_43

1.8V

2 0_0603_5%

C76
22U_0805_6.3V6M

1

C75
22U_0805_6.3V6M

R56

2

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR

VTT0_59
VTT0_60
VTT0_61
VTT0_62

2

+ VCCP
+VTT_44

1

PSI#

VTT1_45
VTT1_46
VTT1_47

1

1

2

1

2

+1.8VS

C83
4.7U_0603_6.3V6K

+VTT_43
+VTT_44

2

J24
J23
H25

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

C82
22U_0805_6.3V6M

2

1

C7 0
22U_0805_6.3V6M

1

C6 9
22U_0805_6.3V6M

2

C74
22U_0805_6.3V6M

2

1

C73
22U_0805_6.3V6M

1

C68
22U_0805_6.3V6M

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

FDI

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

C67
22U_0805_6.3V6M

+ V CCP

3A

@ R128 2
1
1K_0402_5%
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

C72
10U_0805_6.3V6M

2

<43>
<43>
<43>
<43>
<43>
<43>
<43>

GFXVR_EN <43>
GFXVR_DPRSLPVR <43>
GFXVR_IMON <43>

C78
22U_0805_6.3V6M

2

+

GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6

C81
2.2U_0603_6.3V4Z

2

1

VCC_AXG_SENSE <43>
VSS_AXG_SENSE <43>

GFXVR_EN
GFXVR_DPRSLPVR
GFXVR_IMON

AR25
AT25
AM24

C56
1U_0603_10V4Z

2

1

C63
22U_0805_6.3V6M

2

1

C62
22U_0805_6.3V6M

1

C61
22U_0805_6.3V6M

+

GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON

C64
330U_D2_2VY_R7M

1

GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6

C71
10U_0805_6.3V6M

+ V CCP

2

AM22
AP22
AN22
AP23
AM23
AP24
AN24

C77
22U_0805_6.3V6M

2

2

1

VCC_AXG_SENSE
VSS_AXG_SENSE

C80
1U_0603_10V4Z

2

2

@

AR22
AT22

D

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

- 1.5V RAILS

2 @

1

1

VAXG_SENSE
VSSAXG_SENSE

DDR3

1

C52
10U_0805_6.3V6M

2 @

C51
10U_0805_6.3V6M

C50
10U_0805_6.3V6M

1

@

2

15A

GRAPHICS VIDs

C43
10U_0805_6.3V6M

C42
10U_0805_6.3V6M

C41
10U_0805_6.3V6M

C40
10U_0805_6.3V6M

1

C49
10U_0805_6.3V6M

2

C48
10U_0805_6.3V6M

1

1

2

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

GRAPHICS

@

2

C996
330U_D2_2VY_R7M

1.1V RAIL POWER

2

2

C990
10U_0805_6.3V6M

2

1

1

C994
22U_0805_6.3V6M

2

1

C993
22U_0805_6.3V6M

2

1

C989
10U_0805_6.3V6M

1

C991
22U_0805_6.3V6M

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

1

CPU

A

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

1

+ V CCP

CPU CORE SUPPLY

B

to power
VTT_SELECT

G15

VTT_SELECT <44>

H_VTTVID1 = Low, 1.1V(Clarksfield)
H_VTTVID1 = High, 1.05V(Auburndale)

ISENSE

AN35

IMVP_IMON <46>
to power

SENSE LINES

B

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

C995
330U_D2_2VY_R7M

C

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

1

C988
22U_0805_6.3V6M

D

+ V CCP

18A

C987
22U_0805_6.3V6M

48A

J CP U1G
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16

POWER

J CP U1F

VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT

AJ34 V C CSENSE_R
AJ35 VSSSENSE_R
B15
A15

R5 9
R6 0

1
1

2
2

VSS_SENSE_VTT R203 1

0_0402_5%
0_0402_5%

V CCSENSE
VSSSENSE

2 0_0402_5%

V CCSENSE <46>
VSSSENSE <46>

VTT_SENSE <44>

A

Near Processor
+ V CC_CORE

IC,A UB_CFD_rPGA,R1P0
C ONN@
5

V CCSENSE

R61

1

2 100_0402_1%

VSSSENSE

R62

1

2 100_0402_1%

Compal Secret Data

Security Classification
2008/03/13

Issued Date

2009/05/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.
Auburndale(4/5)-PWR

Da te:

Rev
0.1

LA4743P
Sheet

Monday, April 13, 2009
1

9

of

49

3

2

C

B

VSS

IC,A UB_CFD_rPGA,R1P0
C ONN@

2

1

2

1
+
2

1
+
2

1

2

1
+
2

2

1

2

1
+
2

C95
10U_0805_6.3V6M

C94
10U_0805_6.3V6M

C93
10U_0805_6.3V6M

1

Inside cavity
D

C107
10U_0805_6.3V6M

2

2

C106
10U_0805_6.3V6M

2

1

C105
10U_0805_6.3V6M

C92
10U_0805_6.3V6M
C104
10U_0805_6.3V6M

C91
10U_0805_6.3V6M
C103
10U_0805_6.3V6M

C90
10U_0805_6.3V6M
C102
10U_0805_6.3V6M

C89
10U_0805_6.3V6M
C101
10U_0805_6.3V6M

C87
10U_0805_6.3V6M

C86
10U_0805_6.3V6M

C88
10U_0805_6.3V6M
C100
10U_0805_6.3V6M

2

1

2

1

2

1

between
Inductor and
socket

C111
470U_D2_2VM_R4.5M

2

1

2

1

2

1

C110
470U_D2_2VM_R4.5M

2

1

2

1

2

1

C109
470U_D2_2VM_R4.5M

1

2

1

2

1

C108
470U_D2_2VM_R4.5M

2

2

1

2

1

C121
22U_0805_6.3V6M

2

1

1

2

1

C120
22U_0805_6.3V6M

2

1

2

2

1

C119
22U_0805_6.3V6M

2

1

1

1

C118
22U_0805_6.3V6M

@

1

2

2

C98
10U_0805_6.3V6M

2

1

1

C116
10U_0805_6.3V6M

1

2

C85
10U_0805_6.3V6M

2

1

C97
10U_0805_6.3V6M

1

C115
10U_0805_6.3V6M

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

C96
10U_0805_6.3V6M

K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9

C114
10U_0805_6.3V6M

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

C982

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

47P_0402_50V8J

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

C84
10U_0805_6.3V6M

J CP U1I

470uF 4.5mohm

VSS

C

NCTF

D

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35

1

CPU CORE

+ V CC_CORE
J CP U1H

C99
10U_0805_6.3V6M

4

C117
10U_0805_6.3V6M

5

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

VSS_NCTF1_R
VSS_NCTF2_R
VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R
VSS_NCTF6_R
VSS_NCTF7_R

B

IC,A UB_CFD_rPGA,R1P0
C ONN@

A

A

Compal Secret Data

Security Classification
2008/03/13

Issued Date

2009/05/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title

Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.
Auburndale(5/5)-GND/Bypass

Da te:

Rev
0.1

LA4743P
Sheet

Monday, April 13, 2009
1

10

of

49

5

4

+ R T C V CC

I C H _ RTCX1

1

+ 3VS

2 1M_0402_5% S M _ I N T R UDER#

1

2 330K_0402_5%P C H _ I N T V RMEN

R64

1

2 10K_0402_5%

@ R67

1

2 1K_0402_5% S B _ S PKR

SIRQ

LOW=Default
HIGH=No Reboot*

*

D

C 125
1 U_0603_10V4Z

<33>
<33>
<33>
<33>

R72
R73
R74
R75

H D A _ B I T C LK_MDC
H D A _ B I T C L K_CODEC
HDA_ SYNC_ MDC
H D A _ S Y N C _ C O D EC

2

1
1
1
1
1
1

R 77
R 78

C L R P2
S H O R T P ADS

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

2
2
2
2
<33>

<33> H D A _ R S T #_MDC
<33,37> H D A _ R S T # _CODEC

C14

I C H _ S R T CRST#

D17

S M _ I N T R UDER#

A16

P C H _ I N T V RMEN

A14

S B _ S PKR

H D A _ B IT_CLK

A30

H DA_SYNC

D29

S B _ S PKR

P1

H D A _ R ST#
2
2 33_0402_5%

C30

H D A _ S D IN0

G30

<33> H D A _ S D IN1

H D A _ S D IN1

F30
E32

C

F32
R 81
R 82

<33> H D A _ S D O U T _MDC
<33> H D A _ S D O U T _ CODEC

RTCRST#

INTRUDER#

SERIRQ

HDA_BCLK
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

HDA_SYNC
SPKR
HDA_RST#

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

1
1

@ R 670 1

2 33_0402_5% H D A _ S D OUT
2 33_0402_5%

B29

2 100K_0402_5%H D A _ D O C K _EN#

H32

P AD

J30

T16

P C H _ J T AG_TCK

M3

P C H _ J TAG_TMS

K3

P C H _ J TAG_TDI

K1

P C H _ J TAG_TDO

J2

P C H _ J TAG_RST#

J4

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13

JTAG_TDO
TRST#

SIRQ

AK7
AK6
AK11
AK9

S A TA_TXN0_C
S ATA_TXP0_C

C 126
C 127

1
1

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

S A T A_RXN0_C
S A T A_RXP0_C
S ATA_TXN0
SATA_TXP0

AH6
AH5
AH9
AH8

S A TA_TXN4_C
S ATA_TXP4_C

C 130
C 131

1
1

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

S A T A_RXN4_C
S A T A_RXP4_C
S ATA_TXN4
SATA_TXP4

SIRQ

<37>

S A T A_RXN0_C <30>
S A TA_RXP0_C <30>
S ATA_TXN0 <30>
S ATA_TXP0 <30>

S A T A_RXN4_C <30>
S A TA_RXP4_C <30>
S ATA_TXN4 <30>
S ATA_TXP4 <30>

HDD

ODD

C

S A TA_TXN2_C
S ATA_TXP2_C

C 128
C 129

1
1

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

S A T A_RXN2_C
S A T A_RXP2_C
S ATA_TXN2
SATA_TXP2

S A T A_RXN2_C <35>
S A TA_RXP2_C <35>
S ATA_TXN2 <35>
S ATA_TXP2 <35>

E SATA

AD3
AD1
AB3
AB1

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TDI

AB9

AD9
AD8
AD6
AD5

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

JTAG_TMS

P AD
P AD

AH3
AH1
AF3
AF1

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

JTAG_TCK

T13
T14

AF11
AF9
AF7
AF6

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDO

<31,36,37>
<31,36,37>
<31,36,37>
<31,36,37>

L P C _ F RAME# <31,36,37>
L D R Q0#
L D R Q1#

A34
F34

LDRQ0#
LDRQ1# / GPIO23

INTVRMEN

L P C _AD0
L P C _AD1
L P C _AD2
L P C _AD3

C34

FWH4 / LFRAME#
SRTCRST#

33_0402_5%

<33> H D A _ S D IN0

D33
B33
C32
A32

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

1

RTCX1
RTCX2

RTC

2 20K_0402_1%

I C H _ R T CRST#

IHDA

1

C L R P1
S H O R T P ADS

SATA

R70

2

B13
D13

JTAG

1

2 20K_0402_1%

I C H _ RTCX1
I C H _ RTCX2

2

C 124
1 U_0603_10V4Z
R69

1

U1A

1

+RTCVCC

1

2

1

R66

2

1

R65

INTVRMEN
H Κ In tegrated VRM enable
L Κ In tegrated VRM disable

C 123
18P_0402_50V8J

4

Y1
3 2 .768KHZ_12.5PF_Q13MC14610002

1
OSC

OSC
NC

NC
2

2

3

1
D

2

2 10M_0402_5% I C H _ RTCX2

1

C 122
18P_0402_50V8J

R63

3

AF16

SATAICOMPO

R89

AF15

SATAICOMPI

2 37.4_0402_1%

1

+ 1.05VS

+ 3 V ALW

+ 3 V ALW

+ 3 V ALW

+ 3 V ALW

2 10K_0402_5%

S P I _SO_R
<36>

R 655 1

2 15_0402_5%

S P I _SO_R

S P I _ SO_R

AY1
AV1

SPI_MISO

V1

SATA1GP / GPIO19

H D D H A L T_LED#

R 6 84
@ 100_0402_1%

H D D H A L T _LED# <38>

2

2

1
P C H _ J TAG_TDO

G PIO21

Y9

R 85
20K_0402_5%

R84
@ 200_0402_5%

R 87
@ 20K_0402_5%

1

SATA0GP / GPIO21

R86
@ 200_0402_5%

+ 3VS
S A T A_LED# <38>

1

SPI_MOSI

2 10K_0402_1%

1

T3

P C H _ J TAG_TMS

P C H _ J TAG_TDI

P C H _ J TAG_RST#

R 685
10K_0402_1%

R 6 83
@ 100_0402_1%

2

<36>

S P I_SI

S P I _SI

SATALED#

1

1

SPI_CS1#

B

R88
@ 10K_0402_5%

2

R 657
B

R 91

SPI_CS0#

2

AY3

SPI_CLK

1

AV3

2

BA2

1

2 15_0402_5%

S P I _ SB_CS#

<36> S P I _ SB_CS#

2

S P I _ SB_CS#

2

2 10K_0402_5%

1

1

SPI

S P I _ C L K_PCH R 654 1

<36> S P I _ C L K_PCH
R 656

1

+ 3VS

I B E X P EAK-M_FCBGA1071

1

HDA_SDO
HDA_SYNC
This signal has a weak internal pull down.
H=>On Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V

*

R90

This signal has a weak internal pull down.
This signal can't PU

*

P C H _ J T AG_TCK
2
51_0402_5%

PCH JTAG Enable
PCH Pin

Disable iTPM=No Stuff

PCH JTAG Disable

RefDes
ES1

Enable iTPM=Stuff

ES2

ES1

ES2

@ B ATT1

R86

No Install 200ohm

No Install No Install

R684

No Install 100ohm

No Install No Install

PCH_JTAG_TDO

HDA_DOCK_EN#

+ R T C V CC

+ 3VL

B ATT1.1

ME debug mode , this signal has a weak internal PU

*

D3

H=>security measures defined in the Flash
Descriptor will be in effect (default)

J BATT1

1

W=20mils

3

R 94 1

2 1K_0402_5%

W=20mils

L=>Flash Descriptor Security will be overridden
1

SPI_MOSI

D A N 2 0 2U_SC70
C 132
2 .2U_0603_6.3V4Z

1
2
3
4

200ohm

200ohm

No Install No Install

R683

100ohm

100ohm

No Install No Install

R85

200ohm

200ohm

20Kohm

No Install

R685

100ohm

100ohm

10Kohm

No Install

R90

51ohm

51ohm

51ohm

R87

20Kohm

20Kohm

No Install No Install

R88

10Kohm

10Kohm

No Install No Install

PCH_JTAG_TDI

1
2
GND
GND

PCH_JTAG_TCK

ACES_85205-02001
C ONN@

2 Place near IBEX-M

51ohm
A

PCH_JTAG_RST#

This signal has a weak internal pull down.

*

R84
PCH_JTAG_TMS

2

W=20mils

A

CR2032 RTC BATTERY

Disable iTPM=No Stuff

Enable iTPM=Stuff
+ 3VS

iTPM ENABLE/DISABLE
+ 3 VS
@ R 68

5

1

2 1K_0402_5%

G PIO21

R 92

2

1 10K_0402_5%

H D D H A L T_LED# R 93

2

1 10K_0402_5%

Compal Secret Data

S ecurity Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

S P I_SI

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Title

Compal Electronics, Inc.
IBEX-M(1/6)-HDA/JTAG/SATA

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P

Monday, April 13, 2009

Sheet
1

11

of

49

3

2

E C _ L ID_OUT# R 9 5

1

2 10K_0402_5%

S M B CLK

R96

1

2 2.2K_0402_5%

S M B D ATA

R97

1

2 2.2K_0402_5%

S M L0CLK

R98

1

2 2.2K_0402_5%

S M L 0DATA

R99

1

2 2.2K_0402_5%

S M L0ALERT#

R 100 1

2 10K_0402_5%

S M L1ALERT#

R 101 1

2 10K_0402_5%

S M L1CLK

R 103 1

2 2.2K_0402_5%

S M L 1DATA

R 104 1

2 2.2K_0402_5%

D

1

+ 3 V ALW
+ 3VS
+ 3VS

+ 3VS

D

S M B D ATA

6
Q1B

S M B CLK
U1B

C 137 1
C 138 1

P C I E _RXN4
P C I E_RXP4
P C IE_TXN4
P CIE_TXP4

C 139 1
C 140 1

2 0 .1U_0402_16V4Z
2 0 .1U_0402_16V4Z

2 0 .1U_0402_16V4Z
2 0 .1U_0402_16V4Z

P C I E _RXN3
P C I E_RXP3
G L A N_C_TXN
G L AN_C_TXP

AU30
AT30
AU32
AV32

2 0 .1U_0402_16V4Z
2 0 .1U_0402_16V4Z

P C I E _RXN4
P C I E_RXP4
P C I E_C_TXN4
P C IE_C_TXP4

BA32
BB32
BD32
BE32
BF33
BH33
BG32
BJ32

C

+ 3 VALW

+ 3 VS

+ 3 VS

+ 3 VALW

R 4 05 1

2

R 4 11 1

2

10K_0402_5%

10K_0402_5%

C L K R E Q _ W W AN#_R

BA34
AW34
BC34
BD34

C L K R E Q _ WLAN#

R 6 77 1

2

10K_0402_5%

C L K R E Q_LAN#

R 4 15 1

2

10K_0402_5%

C L K R EQ_EXP#_R

AT34
AU34
AU36
AV36
BG34
BJ34
BG36
BJ36

OK

OK

WWAN

WLAN

<31> C L K _ P C I E _ WWAN#
<31> C L K _ P C I E _ WWAN

R 107 1
R 108 1

2 0_0402_5%
2 0_0402_5%

<31> C L K R E Q _ W W AN#

R 80

2 100_0402_5% C L K R E Q _ W W AN#_R

<31> C L K _ P C I E_WLAN#
<31> C L K _ P C I E_WLAN

R 109 1
R 110 1

1

2 0_0402_5%
2 0_0402_5%

C L K _ P C I E _ W WAN#_R
C L K _ P C I E _ W WAN_R

C L K _ P C I E _WLAN#_R
C L K _ P C I E _WLAN_R

AK48
AK47
P9
AM43
AM45
U4

<31> C L K R E Q _ WLAN#

B

OK

LAN

R 111 1
R 112 1

<32> C L K _ P CIE_LAN#
<32> C L K _ P CIE_LAN

2 0_0402_5%
2 0_0402_5%

C L K _ P C IE_LAN#_R
C L K _ P C IE_LAN_R

AM47
AM48
N4

<32> C L K R E Q_LAN#

SMBALERT# / GPIO11
SMBCLK
SMBDATA

PERN2
PERP2
PETN2
PETP2

SML0ALERT# / GPIO60

PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

XDP Ε SODIMM Ε Clock genΕ
ΕG sensor
S M B _CLK_S3

4

SML0CLK
SML0DATA

SML1DATA / GPIO75

PERN7
PERP7
PETN7
PETP7

CL_DATA1
CL_RST1#

PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P

S M B CLK <31>

C8

S M B D ATA

S M B D ATA <31>

J14

S M L0ALERT#

C6

S M L0CLK

G8

S M L 0DATA

M14

S M L1ALERT#

E10

S M L1CLK R 2 15

0_0402_5%

G12

S M L 1DATA R 2 31

0_0402_5%

WLANΕ WWANΕ New card

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P

+ 3VS
+ 3VS

For Intel LAN only

R 681
2.2K_0402_5%

S M B _ EC_CK2 <37>
Q4A

S M B _ EC_DA2 <37>
S M B _ EC_DA2

6

T13
Q 4B

R 682
2.2K_0402_5%

S M B _ E C_DA2_R

1

Nvidisa thermall sensor

T11
S M B _ EC_CK2

3

S M B _ E C_CK2_R

4

R 114 1
R 115 1

2 0_0402_5%
2 0_0402_5%

<31> C L K REQ_EXP#

R 83

2 100_0402_5% C L K R EQ_EXP#_R

1

C L K _ PCIE_EXP#_R
C L K _ PCIE_EXP_R

P AD
P AD

T57
T58

+ 3 V ALW

R 756 1

2 10K_0402_5%

P C I E C L KREQ4#

+ 3 V ALW

R 757 1

2 10K_0402_5%

P C I E C L KREQ5#

P AD
P AD

P AD
P AD
+ 3 V ALW

R 606 1

2 10K_0402_5%

T59
T60

T61
T62

P E G _ B_CLKRQ#

AH42
AH41
A8
AM51
AM53
M9
AJ50
AJ52
H6
AK53
AK51
P13

CLKOUT_PCIE3N
CLKOUT_PCIE3P

REFCLK14IN

2 N7002DW-7-F_SOT363-6

H1

P E G _ C LKREQ# R 102 1

AD43
AD45

L _ C L K_PCIE_VGA#
L _ C L K_PCIE_VGA

AN4
AN2
AT1
AT3

2 10K_0402_5%
R 604 1
R 605 1
C LK_EXP# < 6>
C LK_EXP <6>

C L K _DP#
C L K _ DP

T71
T72

2 0_0402_5%
2 0_0402_5%

C L K _ PCIE_VGA# <24>
C L K _ P CIE_VGA <24>

OK

OK

P AD
P AD

AW24
BA24

C L K _DMI# <19>
C L K _DMI <19>

AP3
AP1

C L K _ B U F_BCLK# <19>
C L K _ B U F_BCLK <19>

F18
E18

C L K _ B UF_DOT96# <19>
C L K _ B UF_DOT96 <19>

OK

AH13
AH12

C L K _ B U F _ C KSSCD# <19>
C L K _ B U F _ C KSSCD <19>

OK

OK
OK

XTAL25_OUT

R 113 1

2 1M_0402_5%
B

Y2

CLKIN_PCILOOPBACK

CLKOUT_PCIE4N
CLKOUT_PCIE4P

XTAL25_IN
XTAL25_OUT

PCIECLKRQ4# / GPIO26

XCLK_RCOMP

CLKOUT_PCIE5N
CLKOUT_PCIE5P

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56

P41

2

OK

C L K _ 14M_PCH <19>

2 5 M HZ_20P_1BG25000CK1A

PCIECLKRQ3# / GPIO25

PCIECLKRQ5# / GPIO44

C

S M B _ E C _CK2_R <24>

T9

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

J42
AH51
AH53
AF38

OK

C L K _ P CI_FB <14>

1

XTAL25_IN
XTAL25_OUT
R 116 1

2
2 90.9_0402_1%

+ 1.05VS

C 141
18P_0402_50V8J

<31> C L K _PCIE_EXP#
<31> C L K _ PCIE_EXP

Clock Flex

EXP

S M B _ E C _DA2_R <24>

2 N7002DW-7-F_SOT363-6

XTAL25_IN

CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

PCIECLKRQ2# / GPIO20

PCH

P E G _ CLKREQ# <14>

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKOUT_PCIE0N
CLKOUT_PCIE0P

S M B CLK

DTS , read from EC
CL_CLK1

PEG_A_CLKRQ# / GPIO47

PERN8
PERP8
PETN8
PETP8

E C _ L ID_OUT# <37>

H14

1

OK

S M B _CLK_S3 <17,18,19,30>

+ 3VS

SML1ALERT# / GPIO74
SML1CLK / GPIO58

PERN6
PERP6
PETN6
PETP6

B9

E C _ L ID_OUT#

1

2

C 142
18P_0402_50V8J

<31>
<31>
<31>
<31>

C 135 1
C 136 1

AW30
BA30
BC30
BD30

3

S M B _DATA_S3 <17,18,19,30>

2

P C I E _RXN3
P C I E_RXP3
P C IE_TXN3
P CIE_TXP3

P C I E _RXN2
P C I E_RXP2
P C I E_C_TXN2
P C IE_C_TXP2

PERN1
PERP1
PETN1
PETP1

SMBus

<32>
<32>
<32>
<32>

BG30
BJ30
BF29
BH29

Link

P C I E _RXN2
P C I E_RXP2
P C IE_TXN2
P CIE_TXP2

2 0 .1U_0402_16V4Z
2 0 .1U_0402_16V4Z

Controller

New Card

<31>
<31>
<31>
<31>

C 133 1
C 134 1

PEG

LAN

P C I E _RXN1
P C I E_RXP1
P C IE_TXN1
P CIE_TXP1

PCI-E*

WLAN

<31>
<31>
<31>
<31>

S M B _DATA_S3

1

2 N7002DW-7-F_SOT363-6

2 N7002DW-7-F_SOT363-6

From CLK BUFFER

WWAN

P C I E _RXN1
P C I E_RXP1
P C I E_C_TXN1
P C IE_C_TXP1

R 1 06
2.2K_0402_5%

2

R 105
2.2K_0402_5%
Q 1A

5

4

5

5

T45
P43
T42
N50

I B E X PEAK-M_FCBGA1071

A

A

Compal Secret Data

S ecurity Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Title

Compal Electronics, Inc.
IBEX-M(2/6)-PCI-E/SMBUS/CLK

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P

Monday, April 13, 2009

Sheet
1

12

of

49

3

2

D M I_CTX_PRX_P0
D M I_CTX_PRX_P1
D M I_CTX_PRX_P2
D M I_CTX_PRX_P3

D M I_CTX_PRX_P0
D M I_CTX_PRX_P1
D M I_CTX_PRX_P2
D M I_CTX_PRX_P3

<7>
<7>
<7>
<7>

D M I_CRX_PTX_N0
D M I_CRX_PTX_N1
D M I_CRX_PTX_N2
D M I_CRX_PTX_N3

D M I_CRX_PTX_N0 BE22
D M I_CRX_PTX_N1 BF21
D M I_CRX_PTX_N2 BD20
D M I_CRX_PTX_N3 BE18

<7>
<7>
<7>
<7>

D M I_CRX_PTX_P0
D M I_CRX_PTX_P1
D M I_CRX_PTX_P2
D M I_CRX_PTX_P3

D M I_CRX_PTX_P0
D M I_CRX_PTX_P1
D M I_CRX_PTX_P2
D M I_CRX_PTX_P3

+ 1.05VS

BD24
BG22
BA20
BG20

BD22
BH21
BC20
BD18
BH25

R 118 1

2 49.9_0402_1%

D M I _ I R COMP

BF25

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP

FDI

<7>
<7>
<7>
<7>

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI

D M I_CTX_PRX_N0 BC24
D M I_CTX_PRX_N1 BJ22
D M I_CTX_PRX_N2 AW20
D M I_CTX_PRX_N3 BJ20

FDI_INT
FDI_FSYNC0
FDI_FSYNC1

DMI_IRCOMP
FDI_LSYNC0

4mil width and place
within 500mil of the PCH

FDI_LSYNC1

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

F D I _ CTX_PRX_N0
F D I _ CTX_PRX_N1
F D I _ CTX_PRX_N2
F D I _ CTX_PRX_N3
F D I _ CTX_PRX_N4
F D I _ CTX_PRX_N5
F D I _ CTX_PRX_N6
F D I _ CTX_PRX_N7

I G P U _BKLT_EN

U 1D

<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>

<22> I G P U _ BKLT_EN
<21> I _ E N A V DD

I G P U _BKLT_EN
I _ E N A V DD

T48
T47

<22> D P S T _ PWM

D P S T _ PWM

Y48

F D I _CTX_PRX_P0
F D I _CTX_PRX_P1
F D I _CTX_PRX_P2
F D I _CTX_PRX_P3
F D I _CTX_PRX_P4
F D I _CTX_PRX_P5
F D I _CTX_PRX_P6
F D I _CTX_PRX_P7

BJ14

F D I _ I NT <7>

BF13

F D I _ F S Y N C 0 <7>

BH13

F D I _ F S Y N C 1 <7>

BJ12

F D I _ L S Y N C0 <7>

BG14

F D I _ L S Y N C1 <7>

<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>

AB46
2
2 10K_0402_5% V48

1
1 R 771

+ 3VS

F D I _CTX_PRX_P0
F D I _CTX_PRX_P1
F D I _CTX_PRX_P2
F D I _CTX_PRX_P3
F D I _CTX_PRX_P4
F D I _CTX_PRX_P5
F D I _CTX_PRX_P6
F D I _CTX_PRX_P7

AB48
Y45

<22> I _ E D I D_CLK
<22> I _ E D I D _DATA

R 772
R 7731

10K_0402_5%

2 2.37K_0402_1% AP39
AP41
P AD

T69

AT43
AT42

Close PCH and mini space 20mil
<22> I _ L V DS_ACLK<22> I _ L V DS_ACLK+

AV53
AV51

<22> I _ LVDS_A0<22> I _ LVDS_A1<22> I _ LVDS_A2-

BB47
BA52
AY48
AV47

<22> I _ L VDS_A0+
<22> I _ L VDS_A1+
<22> I _ L VDS_A2+

BB48
BA50
AY49
AV48

2 0_0402_5%

@ R 120 2

C

<37> M _ P W ROK

B17
10K_0402_5%

1

R 121 1
@ R 379 1

2 0_0402_5%
2 0_0402_5%

R 122

P M _ D R A M _ P WRGD

R 123 1

D9

P M _ R SMRST# C16

2
100_0402_5%

SYS_PWROK

CLKRUN# / GPIO32

PWROK
MEPWROK
LAN_RST#
DRAMPWROK
RSMRST#

1 10K_0402_5%
+ 3 VALW

R 151 1

2 10K_0402_5%

M1
P5

<6> P M _ P W R BTN#_R
R 125 1

<37> P W R B T N _OUT#
<37>

SUS_PWR_DN_ACK / GPIO30
PWRBTN#

2 0_0402_5%
E C _ A C IN

E C _ A C IN

A6

ACPRESENT / GPIO31
BATLOW# / GPIO72

I C H _ P C I E _WAKE#

Y1

P M _ C L K RUN#

AY53
AT49
AU52
AT53

I C H _ P C I E _WAKE# <31,32>

AY51
AT48
AU50
AT51
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_M#
TP23
PMSYNCH

P8

P M _ SUS_STAT#

F3

S U S _ CLK

T18

E4

S L P_S5# <37>

H7

S L P_S4# <37>

P12
K8

P M _RI#

D37
P M _ P W ROK 2

F14

RI#

SLP_LAN# / GPIO29

I _ B LUE
I _ G R EEN
I_RED

<22> I _ B LUE
<22> I _ G R E EN
<22> I _ R E D

F6

V51
V53

S L P_S3# <37>

1 R 774
1

<22> I _ C R T _ H S Y NC
<22> I _ C R T _ V S YNC

Can be left NC when IAMT is
not support on the platfrom

2
2

R 775

0_0402_5%
H S Y NC
V S YNC
0_0402_5%

CRB0.9 change to 0 ohm

SDVO_INTN
SDVO_INTP

H _ P M _ S Y N C <6>

Y53
Y51
AD48
AB51

BJ46
BG46
BJ48
BG48
BF45
BH45

L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

CRT_HSYNC
CRT_VSYNC

D

BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
Y49
AB49
BE44
BD44
AV40
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

C

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT_DDC_CLK
CRT_DDC_DATA

DAC_IREF
CRT_IRTN

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

T51
T53

U50
U52
BC46
BD46
AT38

H D M I D _ C T RLCLK
H D M I D _ C T RLDATA

T M D S _ B_HPD#

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

H D M I D _ C T RLCLK <23>
H D M I D _ C T RLDATA <23>

T M D S _ B_HPD# <23>
T M D S D _DATA0# <23>
T M D S D _DATA0 <23>
T M D S D _DATA1# <23>
T M D S D _DATA1 <23>
T M D S D _DATA2# <23>
T M D S D _DATA2 <23>
T M D S D_CLK# <23>
T M D S D _CLK <23>

I B E X PEAK-M_FCBGA1071

If not using integrated
LAN,signal may be left as NC.

I B E X P EAK-M_FCBGA1071

CRB0.9 change to 1K_0402_0.5%

P M _ R SMRST#

1

AA52
AB53
AD53

<20> I _ C R T _ D DC_CLK
<20> I _ C R T _ D D C_DATA

N2
BJ10

L_DDC_CLK
L_DDC_DATA

T17

2

L O W _BAT#

P7

J12

SDVO_STALLN
SDVO_STALLP

Display Port D

R 124 2

K5

2 10K_0402_5%A10

1

<6> P M _ D R A M _ PWRGD
<42> R _ E C _ R SMRST#
<37> E C _ R S MRST#

M6

WAKE#

1

2 0_0402_5%

SYS_RESET#

R 126
1K_0402_0.5%

R 365 1
@ R 373 1

V G A TE

<37> P M _ P W R OK

2 0_0402_5% S Y S _ R ST# T6

System Power Management

R 119 1

<6> X D P _ DBRESET#

<19,46>

AP48
AP47

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTCTL

Display Port C

Checklist0.8 Κ MEPWROK
can be connect to
PWROK if iAMT disable

L_BKLTEN
L_VDD_EN

Display Port B

D M I_CTX_PRX_N0
D M I_CTX_PRX_N1
D M I_CTX_PRX_N2
D M I_CTX_PRX_N3

F D I _ CTX_PRX_N0
F D I _ CTX_PRX_N1
F D I _ CTX_PRX_N2
F D I _ CTX_PRX_N3
F D I _ CTX_PRX_N4
F D I _ CTX_PRX_N5
F D I _ CTX_PRX_N6
F D I _ CTX_PRX_N7

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

SDVO

D

<7>
<7>
<7>
<7>

2

100K_0402_5%

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

Digital Display Interface

1
U 1C

1

EDID_CLK and EDID_DATA single
end and keep 30 mil with other
LVDS signal avoid noise

R 770

LVDS

4

CRT

5

C H 751H-40PT_SOD323-2
I _ B LUE

1

I _ G R EEN

1

+ 3 VS
S Y S _ R ST#

@ R 133

1

2 10K_0402_5%

R 129

1

2 8.2K_0402_5%

2

R 777 150_0402_1%
I_RED

B

P M _ C L K RUN#

2

R 776 150_0402_1%

1

2

B

R 778 150_0402_1%
Place the 3 resistors close to IBEX

+ 3 V ALW
L O W _BAT#

R 134

1

2 8.2K_0402_5%

P M _RI#

R 136

1

2 10K_0402_5%

I C H _ P C I E _WAKE# R 137

1

2 1K_0402_5%

E C _ A C IN

2

1 8.2K_0402_5%

R 138

Check PM_SLP_LAN#

A

A

Compal Secret Data

S ecurity Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Title

Compal Electronics, Inc.
IBEX-M(3/6)-DMI/GPIO/LVDS

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P
Sheet

Monday, April 13, 2009
1

13

of

49

4

R P5
P C I _ REQ3#
P C I _ P I RQF#
P C I _ P ERR#
P C I _ LOCK#

1
2
3
4

8
7
6
5
8 .2K_0804_8P4R_5%
+ 3VS
R P6

P C I _ P IRQA#
P C I _ P IRQD#
P C I _ PIRQG#
P C I _ P IRQC#

1
2
3
4

8
7
6
5
8 .2K_0804_8P4R_5%
R P7

P C I _ P IRQE#
P C I _STOP#
P C I _ I R D Y#
D G P U _ SELECT#

1
2
3
4

J50
G42
H47
G34

8
7
6
5
P C I _ P IRQA#
P C I _ P IRQB#
P C I _ P IRQC#
P C I _ P IRQD#

G38
H51
B37
A44

P C I _ REQ0#
P C I _ REQ1#
D G P U _ SELECT#
P C I _ REQ3#

F51
A46
B45
M53

8 .2K_0804_8P4R_5%

<22> D G P U _ S ELECT#

C

P C I _GNT0#
P C I _GNT1#
D G P U _ P W M_SELECT#
P C I _GNT3#

T70 P A D

P C I _ P IRQE#
P C I _ P I RQF#
P C I _ PIRQG#
P C I _ P IRQH#

R 150
A C C E L _INT

<30> A C C E L _INT

2

1

F48
K45
F36
H53
B41
K53
A36
A48

0_0402_5%

K6

<36,37> P C I _RST#
<37> P C I _ S E RR#

P C I _ S ERR#
P C I _ P ERR#

E44
E50

P C I _ I R D Y#
P C I _ D EVSEL#
P C I _ F R AME#

A42
H44
F46
C46

P C I _ LOCK#

D49

P C I _STOP#
P C I _ T R DY#

D41
C48

NV_ALE
NV_CLE
NV_RCOMP

C/BE0#
C/BE1#
C/BE2#
C/BE3#

NV_RB#
NV_WR#0_RE#
NV_WR#1_RE#
NV_WE#_CK0
NV_WE#_CK1

PIRQA#
PIRQB#
PIRQC#
PIRQD#

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PCIRST#
SERR#
PERR#

GNT2
Default-Internal pull up

*

Low=Configures DMI for ESI
compatible operation(for
servers only.Not for
mobile/desktops)

M7

<37> P C I _PME#
P L T_RST#

<6,31,32> P LT_RST#

D5

B

N52
P53
P46
P51
P48

R _ C L K _ PCI_FB
R _ C L K _ PCI_EC
R _ C L K _ D EBUG_PORT_0
R _ C L K _ D EBUG_PORT_1

IRDY#
PAR
DEVSEL#
FRAME#
PLOCK#

USBRBIAS#
STOP#
TRDY#

USBRBIAS

PME#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

D G P U _ H P D_INT#

D37

<37>

E C _ S CI#

E C _ S CI#

J32

<37>

E C _ SMI#

E C _ SMI#

F10

<23> D G P U _ H P D_INT#

*

it have weak internal PU 20K

<24> D G P U _ H OLD_RST#

Check list Rev0.8 section1.23.2 If not
implemented, the Braidwood interface
signals can be left as No Connect (NC).

C38

K9

P C H _ GPIO15

T7

D G P U _ H O LD_RST#

AA2

D G P U _ P W R OK

F38

C R _ W A K E#

<32> C R _ W A K E#
<31>

P C H _ GPIO12

X M I T_OFF

X M I T_OFF

Y7
H10

Internal VccVRM Option AB12
N V _ ALE
N V _ C LE

BD3
AY6

P C H _ GPIO28
R 145 1

+ 3VS

2 10K_0402_5%

H _ S T P_PCI#
G PIO35

AU2
AV7

<23,39,45,47> D G P U _ P W R _EN

GPIO27

AY8
AY5

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

AV11
BF5

*

H Κ On-D ie voltage regulator enable
L Κ On-Di e PLL Voltage Regulator disable

U S B 20_N0
U S B20_P0
U S B 20_N1
U S B20_P1
U S B 20_N2
U S B20_P2

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

U S B 20_N0
U S B20_P0
U S B 20_N1
U S B20_P1
U S B 20_N2
U S B20_P2

U S B R B I AS

D25

U S B 20_N4
U S B20_P4
U S B 20_N5
U S B20_P5
U S B 20_N6
U S B20_P6
U S B 20_N7
U S B20_P7
U S B 20_N8
U S B20_P8
U S B 20_N9
U S B20_P9

R 155 1

<21>
<21>
<31>
<31>
<35>
<35>
<35>
<35>
<31>
<31>
<31>
<31>

U S B _ OC#0
U S B _ OC#1 R 156 2
U S B _ OC#2
W X M I T_OFF#
U S B _ OC#4
U S B _ OC#5
U S B _ OC#6
U S B _ OC#7

AB7

V G A _ PRSNT_L#

AB13

G PIO38

V3

G PIO39

P3

P C I E C L KREQ6#

H3
F1

MB
MB

G PIO48

AB6

MB USB/ESATA

P C H _ T EMP_ALERT#

AA4

P C H _ T EMP_ALERT#

G PIO57

F8

CLKOUT_PCIE6N
CLKOUT_PCIE6P

TACH2 / GPIO6
CLKOUT_PCIE7N
CLKOUT_PCIE7P

LAN_PHY_PWR_CTRL / GPIO12

A20GATE

TACH3 / GPIO7

A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53

BT
Finger print
WWAN
New Card

B T _ OFF

<35>

W X M I T_OFF# <31>

T19
T20

P AD
P AD

AF48
AF47

T21
T22

P AD
P AD

GPIO8
U2

G A TEA20

G A TEA20 <37>

GPIO15

D

SATA4GP / GPIO16

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24

CLKOUT_BCLK0_P / CLKOUT_PCIE8P
PECI
RCIN#

GPIO27
GPIO28

PROCPWRGD
THRMTRIP#

AM3

C L K _ C P U_BCLK# <6>

AM1
P C H _ P E C I_R

T1

K B _ RST#

R 144

2 0_0402_5%

1

H _ P E CI < 6>

K B _ RST# <37>

BE10

H _ C P U P W R G D <6>

BD10 H _ T H E RMTRIP#_L

2 54.9_0402_1%

1

R 146

H _ T H E R MTRIP# <6>

R 147
56_0402_5%

SATACLKREQ# / GPIO35
SATA2GP / GPIO36

TP1

SATA3GP / GPIO37

TP2

SLOAD / GPIO38

TP3

SDATAOUT0 / GPIO39

TP4

PCIECLKRQ6# / GPIO45

TP5

PCIECLKRQ7# / GPIO46

TP6

SDATAOUT1 / GPIO48

TP7

SATA5GP / GPIO49

TP8

GPIO57

TP9

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

OK

C L K _ C P U_BCLK < 6>

BG10

STP_PCI# / GPIO34

TP10

WLAN

AH45
AH46

TACH1 / GPIO1

USB Camera

2 22.6_0402_1%

1 0_0402_5%

V6

D G P U _ P W R _EN

Within 500
mils

N16
J16
F16
L16
E14
G16
F12
T15

M11

P C I E C L KREQ7#

DOCK

U S B 20_N4
U S B20_P4
U S B 20_N5
U S B20_P5
U S B 20_N6
U S B20_P6
U S B 20_N7
U S B20_P7
U S B 20_N8
U S B20_P8
U S B 20_N9
U S B20_P9

B25

<35>
<35>
<35>
<35>
<35>
<35>

V13

BMBUSY# / GPIO0

1

8 .2K_0804_8P4R_5%

GPIO15
L Κ Int el ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality
H Κ Int el ME Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality

AV9
BG8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

Y3

D G P U _ E D IDSEL#

TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
NC_2
NC_3
NC_4
NC_5
INIT3_3V#
TP24

BA22

2

D

8
7
6
5

2 1K_0402_1% P C H _ GPIO0

<20> D G P U _ E D IDSEL#

MISC

1
2
3
4

R 1 40 1

+ 3VS

CPU

P C I _ REQ1#
P C I _ F R AME#
P C I _ T R DY#
P C I _ P IRQH#

NV_DQS0
NV_DQS1
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

This signal has a weak internal
pull up ,can't Pull low

AY9
BD1
AP15
BD8

GPIO

R P4

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

1

NCTF

8 .2K_0804_8P4R_5%

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

NVRAM

H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36

8
7
6
5

USB

1
2
3
4

2

U 1F

GPIO8

PCI

P C I _ D EVSEL#
P C I _ S ERR#
P C I _ REQ0#
P C I _ P IRQB#

3

U 1E

+ 3VS

RSVD

5

R P3

+VCCP

AW22
BB22
AY45

+ 3VS

AY46
AV43

E C _ S CI#

R 166 1

2 10K_0402_5%

AV45

D G P U _ E D IDSEL#

R 167 1

2 10K_0402_5%

AF13

K B _ RST#

R 171 1

2 10K_0402_5%

M18

D G P U _ P W R _EN

R 172 1

2 10K_0402_5%

N18

D G P U _ H P D_INT#

R 173 1

2 10K_0402_5%

AJ24

V G A _ PRSNT_L#

R 175 1

2 10K_0402_5%

AK41

D G P U _ H O LD_RST# R 176 1

2 10K_0402_5%

AK42

G PIO38

R 178 1

2 10K_0402_5%

M32

G A TEA20

R 180 1

2 10K_0402_5%

N32

P C H _ T EMP_ALERT# R 181 1

2 10K_0402_5%

M30

G PIO39

R 169 1

2 10K_0402_5%

N30

G PIO48

R 170 1

2 10K_0402_5%

H12

C R _ W A K E#

R 168 1

2 10K_0402_5%

AA23

D G P U _ P W R OK

R 874 1

2 10K_0402_5%

AB45
AB38
AB42

INIT3_3V

AB41

This signal has weak internal
PU, can't pull low

T39
P6

B

T48

P AD

C10
+ 3 V ALW

I B E X PEAK-M_FCBGA1071
<12> C L K _ P CI_FB
<37> C L K _ P CI_EC
<36> C L K _ D E BUG_PORT_0
<31> C L K _ D E BUG_PORT_1

R 158
R 160
R 161
R 162

1
1
1
1

2
2
2
2

I B E X PEAK-M_FCBGA1071
22_0402_5%
R _ C L K _ PCI_FB
22_0402_5%
R _ C L K _ PCI_EC
22_0402_5% R _ C L K _ D EBUG_PORT_0
22_0402_5% R _ C L K _ D EBUG_PORT_1

P C I _GNT0# @ R 163 1

2 1K_0402_5%

P C I _GNT1# @ R 164 1

2 1K_0402_5%

Boot BIOS Strap
+ 3 V ALW
RP8
U S B _ OC#0
W X M I T_OFF#
U S B _ OC#1
U S B _ OC#2

4
3
2
1

5
6
7
8

PCI_GNT0# PCI_GNT1# Boot BIOS
Location
0
0
LPC
0

1

E C _ SMI#

R 157 1

2 10K_0402_5%

P C H _ GPIO15

R 159 1

2 1K_0402_5%

P C H _ GPIO12

R 811 1

2 10K_0402_5%

NV_ALE
Enable Intel Anti-Theft
Technology Κ 8.2K PU to +3VS

P C I E C L KREQ6#

R 812 1

2 10K_0402_5%

P C I E C L KREQ7#

R 813 1

2 10K_0402_5%

Disable Intel Anti-Theft
Technology Κ floating(internal PD)

P C H _ GPIO28

R 814 1

2 10K_0402_5%

G PIO57

R 182 1

2 10K_0402_5%

G PIO35

R 165 2

1 10K_0402_5%

V G A _ PRSNT_L#

R 911 1

2 10K_0402_5%

Intel Anti-Theft Techonlogy

High=Endabled
NV_ALE
Low=Disable(floating)

*
+ 1.8VS

N V _ ALE

Reserved(NAND)

@ R 1 74 1

2 1K_0402_5%

DMI Termination Voltage

C

NV_CLE

SPI

1
R 179 1

*

Weak internal
PU,Do not pull low

2 0_0402_5%

N V _ C LE
+ 3VS

10K_1206_8P4R_5%

@ R 1 84 1

+ 3 V S_NV

DMI termination voltage.
weak internal PU, don't PD

+ 3VS

2 1K_0402_5%

A

1

Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default *
5

4

1
2

IN1

O

1

<6> B U F _ PLT_RST#

IN2

P L T_RST#

5

3

Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

A

Compal Secret Data

S ecurity Classification

S N 7 4 A H C 1 G08DCKR_SC70-5

@ R 1 85
100K_0402_5%

Q 29B

6

Q 29A
2 N7002DW-7-F_SOT363-6

2

A16 swap overide Strap/Top-Block
Swap Override jumper

P

@U2

G

2 1K_0402_5%

5

<12> P E G _ CLKREQ#
P C I _GNT3# @ R 183 1

D G P U _ P W R OK

3

1
5
6
7
8

Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW

4

4
3
2
1

PCI

2 N 7002DW-7-F_SOT363-6

RP9
U S B _ OC#6
U S B _ OC#5
U S B _ OC#4
U S B _ OC#7

0

1

2

10K_1206_8P4R_5%

2

http://laptop-motherboard-schematic.blogspot.com/

Title

Compal Electronics, Inc.
IBEX-M(4/6)-PCI/USB/RSVD

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P

Monday, April 13, 2009

Sheet
1

14

of

49

5

4

+ 3 VS

+ V 1 . 1 A _ INT_VCCSUS
2
0 .1U_0402_16V4Z
C 179
+ 3 VALW

1
B

Y22

U19
2
U20
U22

1

1 / 5BA4/4W

V15
V16

2

0 .1U_0402_16V4Z
C 185

Y16

VCCSATAPLL[1]

0.032A VCCSATAPLL[2]

DCPSST

VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]

VCC3_3[5]
VCC3_3[6]
VCC3_3[7]

VCCVRM[4]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

1

2

1

2

C 197
0 .1U_0402_16V4Z

A

C 196
0 .1U_0402_16V4Z

3 n BA4/4W

V_CPU_IO[2]

CPU

V_CPU_IO[1]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

C 176 1

2 0 .1U_0402_16V4Z

1 / 2BA2/2W

AK3
AK1

AH22
AT20

@ L4

1

+ 1 . 05VS_VCCAPLL_L
@ R 189

2

1

10UH_LB2012T100MR_20%_0805

1

+ 1.05VS

2

VCCRTC

2mA

I B E X PEAK-M_FCBGA1071

6mA

VCCSUSHDA

+ 1.8VS

BJ18
AM23

+ 1.05VS

0_0603_5%

AF22

1

AD19
AF20
AF19
AH20

2

VCCVRM[1]

0.035A

VCCFDIPLL

6mA

VCCIO[1]

1

2
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
0.156A VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

1

2

C 1 48
10U_0805_6.3V6M

C 1 49
0 .1U_0402_16V4Z

1

2 0_0402_5%

+ 1.8VS

1

2 0_0402_5%

+ 3VS

0.085A

AM8
AM9
AP11
AP9

1

+ 1.05VS

B

@ R 190

+ 1 . 0 5 V S_VCCFDIPLL_L
@ L5

1

2

0_0603_5%

+ 1 . 0 5 V S_VCCFDIPLL
1
2
10UH_LB2012T100MR_20%_0805

1

2
+ 1.05VS

+ 1.05VS_L

+ V 1 . 05S_VCCA_A_DPL_L
R 1 92
L6

R 191

1

2

0_0603_5%

1

2

0_0603_5%

1

2

+ 1.05VS

1
R 194
R 195
R 198
R 200

1
1
1
1

2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2

1

2

+

2

1

2

Issued Date

+ 5 V ALW + 3 V ALW
@ R 1 93
0_0603_5%

1
+

2

D5

100_0402_5%

C H 751H-40PT_SOD323-2
I C H _ V 5 R E F _ RUN

I C H _ V 5 R E F_SUS

20 mils

20 mils
1

C 194
1U_0402_6.3V4K_X5R

2

Compal Secret Data
2008/03/13

+ 3VS

R 197

C H 751H-40PT_SOD323-2

1

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

+ 5 VS

D4
R 196
100_0402_5%

+ V 1 . 0 5S_VCCA_B_DPL

10UH_LB2012T100MR_20%_0805

+ 3 V ALW

2

1

+ V 1 . 0 5S_VCCA_B_DPL_L
R 201
L7

1
+ 3 . 3 A _ 1 .5A_VCCPAZSUS

@

+ V 1 . 0 5S_VCCA_A_DPL

10UH_LB2012T100MR_20%_0805

2

1

4

R 671

@ R 672

+ 3VS

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

2

S ecurity Classification

5

C 1 47
0.01U_0402_25V7K

AU16

I B E X PEAK-M_FCBGA1071

AB19
AB20
AB22
AD22
+ P C H _VCC1_1_20
+ P C H _VCC1_1_21
+ P C H _VCC1_1_22
+ P C H _VCC1_1_23

C 160
0 .1U_0402_16V4Z

LVDS
HVCMOS

C 159
10U_0805_6.3V6M

+ 1 . 0 5 V S_VCCFDIPLL

VCC3_3[1]

VCCDMI[2]

+VCCP

AT16

C 167
1 U_0402_6.3V6K

C 1 46
10U_0603_6.3V6M

C 1 45
1U_0402_6.3V6K

VCC CORE

DMI

VCCIO[54]
VCCIO[55]

0.061A

VCCDMI[1]

+ 1.05VS

AD20

L30

AT22

2 @

@

AH19

AA34
Y34
Y35
AA35

AN30
AN31
AN35

C 682 1
2 0 .1U_0402_16V4Z
+ 1.8VS

0_0603_5%

A12

HDA

2

AT18
AU18

RTC

2

1

C 190
0 .1U_0402_16V4Z

1

C 189
0 .1U_0402_16V4Z

2
+ R T C V CC

C 188
4 .7U_0603_6.3V6K

1

2

+ 3VS

AD13

1
DCPSUS

2

AT24
C

+ 3VS

+ 1 . 05VS_VCCAPLL

VCCIO[4]

+VCCP

1 / 2BA2/2W

U35

2

0 .1U_0402_16V4Z
C 182
+ 3VS

VCC3_3[14]

P36

2

VCCIO[3]

VCCIO[9]

1 / 3BA4/4W P18
1

3.208A

2

1

VCCVRM[2]

C 183
10U_0805_6.3V6M

V12

VCC3_3[13]

N36

1

2
+ 1 .8VS

2

+ V C C SST

2

0 .1U_0402_16V4Z
C 177

VCC3_3[12]

M36

1

1

1

1

VCC3_3[11]

1

AD35

1

AF32

VCCIO[2]

VCC3_3[10]

+ 3VS

L38

+ 3VS

AB35

2

AF34
AH34

VCCIO[21]
VCCIO[22]
VCCIO[23]

0.357A

J38

+ 1.8VS

2

2

AH23
AJ35
AH35

VCC3_3[9]

I C H _ V 5 R E F _ RUN

2

2 0_0603_5%

1

2

1

C 175
1U_0402_6.3V6K

1

C 174
1U_0402_6.3V6K

2

C 173
1U_0402_6.3V6K

1

0.073A
VCCADPLLB[1]
VCCADPLLB[2]

VCC3_3[8]

K49

2

VCC3_3[4]

2

1

C 172
0 .1U_0402_16V4Z

BD51
BD53

+ 1.05VS

V5REF

1

VCC3_3[3]

AB34

1

R 7 79 1

C 178
0 .1U_0402_16V4Z

+ V 1 . 0 5S_VCCA_B_DPL

0.072A
VCCADPLLA[1]
VCCADPLLA[2]

1

+ 1.05VS
I C H _ V 5 R E F_SUS

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

1

2
VCC3_3[2]

AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27

AP43
AP45
AT46
AT45

1

BB51
BB53

+ 1.05VS

2

>1mA

@

VCCTX_LVDS[3]
VCCTX_LVDS[4]

AH39

2

+ V 1 . 0 5S_VCCA_A_DPL

0.035A
VCCVRM[3]

2

0.042A
VCCAPLLEXP

2

M U R A TA_BLM18AG601SN1D_0603

1

AU24

F24

VCCIO[24]

2

1

AH38

2

+ 1.8VS

DCPRTC

1

BJ24

PCI E*

V9

V5REF_SUS

10UH_LB2012T100MR_20%_0805

U23
V23

VCCALVDS
VSSA_LVDS

NAND / SPI

+ V C C RTCEXT
0 .1U_0402_16V4Z

2

>1mA

0_0603_5%

2

FDI

C 166 1

VCCIO[56]

1

C 186
2 2 0U_D2_4VM_R15

C

VCCSUS3_3[28]

AK24

@ L3

2

2

AF51

C 191
2 2 0U_B_2.5VM_R15M

VCCME[12]

2

+ 1.05VS_APLL
@ R 188

1

C 187
1U_0402_6.3V6K

VCCME[11]

2

1

C 165
1U_0402_6.3V6K

VCCME[10]

0.030A

0.059A VCCTX_LVDS[2]

C 170
10U_0603_6.3V6M

USB

VCCME[9]

1

AF53

1

1

D

VCCTX_LVDS[1]

+ 3 V ALW

1

2

+ 3VS

+ 1.05VS

C 164
1U_0402_6.3V6K

Y42

VCCME[8]

Clock and Miscellaneous

Y41

VCCME[7]

PCI/GPIO/LPC

Y39

1.998A

SATA

C 153
1U_0402_6.3V6K

2

V42

VCCME[6]

PCI/GPIO/LPC

2

1

V41

C 161
1U_0402_6.3V6K

1

C 163
10U_0805_6.3V6M

2

C 162
10U_0805_6.3V6M

V39

VCCME[5]

VSSA_DAC[2]

AE52

C 1000

AF42

VCCME[4]

VSSA_DAC[1]

AE50

10U_0805_6.3V6M

AF41

VCCME[3]

VCCADAC[2]

C 9 99

AF43

VCCADAC[1]

0.069A

0.01U_0603_16V7K

AD41

VCCME[2]

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]1.524A
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]

C 9 98

2

AD39

VCCME[1]

2

AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31

0.01U_0603_16V7K

1

AD38

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
0.163AVCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

2

2

C 169
1 U_0402_6.3V6K

Y20

0 .1U_0402_16V4Z DCPSUSBYP

+1.05VS

1

0.344A

VCCLAN[2]

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

1

C 168
1 U_0402_6.3V6K

2 C 152

1

VCCLAN[1]

V24
V26
Y24
Y26

C 158
0 .1U_0402_16V4Z

AF24

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

0.052A

VCCACLK[2]

C 181
10U_0805_6.3V6M

AF23

VCCACLK[1]

1

C 1 93
1U_0402_6.3V6K

DG1.1 no M3
support and not
Intel LAN, VCCLAN
Source=>GND

AP53

C 157
0 .1U_0402_16V4Z

AP51

@

1

C 180
1U_0402_6.3V6K

2

+ 1.05VS
C 150
1 U_0402_6.3V6K

@

POWER

U 1J

C 171
0 .1U_0402_16V4Z

2

1

C 1 84
1U_0402_6.3V6K

1

L 45

POWER

U1G

CRT

+ 1.05VS

2

0_0603_5%
10UH_LB2012T100MR_20%_0805

D

1

+ V C C P _ V C CA_CLK

1

C 144
1U_0402_6.3V6K

2

C 143
10U_0805_6.3V6M

1

2

C 192
1 U_0402_6.3V6K

+ 1.05VS
+ V C C P _ V CCA_CLK_L
@ L1
@ R 186

3

2

http://laptop-motherboard-schematic.blogspot.com/

Title

C 1 95
1U_0402_6.3V4K_X5R

2

A

Compal Electronics, Inc.
IBEX-M(5/6)-PWR

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P

Monday, April 13, 2009

Sheet
1

15

of

49

5

4

3

U1I

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42

D

C

B

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

2

1

U 1H

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

AB16
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

D

C

B

I B E X PEAK-M_FCBGA1071

I B E X PEAK-M_FCBGA1071
A

A

Compal Secret Data

S ecurity Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Title

Compal Electronics, Inc.
IBEX-M(6/6)-GND

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P

Monday, April 13, 2009

Sheet
1

16

of

49

5

4

+ V R E F _ D Q_DIMMA

+1.5V

3

2

1

+ 1.5V
4 B A 2 /6W

<8> D D R _ A _D[0..63]

+1.5V
+ V _ D D R _ C P U _REF

<8> D D R _ A _ DM[0..7]

2

D D R _ A _DM0
D D R _ A _D2
D D R _ A _D3
D D R _ A _D8
D D R _ A _D9
D D R _ A _ DQS#1
D D R _ A _ DQS1
D D R _ A _D10
D D R _ A _D11
D D R _ A _D16
D D R _ A _D17
D D R _ A _ DQS#2
D D R _ A _ DQS2
D D R _ A _D18
D D R _ A _D19
D D R _ A _D24
D D R _ A _D25
D D R _ A _DM3
D D R _ A _D26
D D R _ A _D27

1

C O NN@

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

<8> D D R _ A _ DQS[0..7]
D D R _ A _D4
D D R _ A _D5

<8> D D R _ A _MA[0..15]

D D R _ A _ DQS#0
D D R _ A _ DQS0

V _ D D R _ C P U _ REF
0_0402_5%

1

2

R 884

<8> D D R _ A _ DQS#[0..7]

+ V _ D D R _ C P U_REF0

R 205
1K_0402_1%

+ V _ D D R _ C P U _REF

2

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

2

R 898

0_0402_5%
M3 @

1

1

C 1058
2 .2U_0603_6.3V4Z

2
D

C 1057
0.1U_0402_10V6K

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

D D R _ A _D0
D D R _ A _D1

D D R _ A _D6
D D R _ A _D7

D

R 206
1K_0402_1%

D D R _ A _D12
D D R _ A _D13

2

J D I M M1
+ V R E F _ D Q_DIMMA

+ V R E F _ D Q_DIMMA

D D R _ A _DM1
D R A M R ST#

D R A M R ST# <6,18>

D D R _ A _D14
D D R _ A _D15
D D R _ A _D20
D D R _ A _D21
D D R _ A _DM2
D D R _ A _D22
D D R _ A _D23
D D R _ A _D28
D D R _ A _D29

Layout Note:
Pla ce near JP4

D D R _ A _ DQS#3
D D R _ A _ DQS3
D D R _ A _D30
D D R _ A _D31

+1.5V

D D R _ A _ WE#
D D R _ A _ CAS#

<8> D D R _ C S 1 _DIMMA#

D D R _ A_MA13
D D R _ C S 1 _DIMMA#

D D R _ A _D32
D D R _ A _D33
D D R _ A _ DQS#4
D D R _ A _ DQS4
B

D D R _ A _D34
D D R _ A _D35
D D R _ A _D40
D D R _ A _D41
D D R _ A _DM5
D D R _ A _D42
D D R _ A _D43
D D R _ A _D48
D D R _ A _D49
D D R _ A _ DQS#6
D D R _ A _ DQS6
D D R _ A _D50
D D R _ A _D51
D D R _ A _D56
D D R _ A _D57
D D R _ A _DM7

2

1
2

2

1

R 208
10K_0402_5%

1

C 220
0 .1U_0402_16V4Z

+ 3VS
A

C 219
2.2U_0402_6.3V6M

D D R _ A _D58
D D R _ A _D59
1 R 207
2
10K_0402_5%

205

G1

G2

2

1

2

1

2

2

+ C 200
3 3 0 U _D2_2VY_R7M

2

D D R _ A _MA2
D D R _ A _MA0
M _ C L K _DDR1
M _ C L K _DDR#1
D D R _ A _BS1
D D R _ A _ RAS#
D D R _ C S 0 _DIMMA#
M _ ODT0
M _ ODT1

M _ C L K _DDR1 <8>
M _ C L K _DDR#1 <8>
D D R _ A _BS1 <8>
D D R _ A _ RAS# <8>

Layout Note:
Place near JP4.203 & JP4.204

D D R _ C S 0 _DIMMA# <8>
M _ ODT0 <8>
M _ ODT1 <8>

+ V R E F _CA

+ V _ D D R _ C P U _REF
+ 0.75VS

V _ D D R _ M C H _ REF
D D R _ A _D36
D D R _ A _D37

1
1

D D R _ A _DM4

2

D D R _ A _D38
D D R _ A _D39

1

2

R 877

2
0_0402_5%

1

2

1

2

1

2

1

2

1

2

D D R _ A _D44
D D R _ A _D45

B

D D R _ A _ DQS#5
D D R _ A _ DQS5
D D R _ A _D46
D D R _ A _D47
D D R _ A _D52
D D R _ A _D53
D D R _ A _DM6
D D R _ A _D54
D D R _ A _D55
D D R _ A _D60
D D R _ A _D61
D D R _ A _ DQS#7
D D R _ A _ DQS7
D D R _ A _D62
D D R _ A _D63
P M_EXTTS#1_R
S M B _DATA_S3
S M B _CLK_S3

PM_EXTTS#1_R <6,18>
S M B _ DATA_S3 <12,18,19,30>
S M B _CLK_S3 <12,18,19,30>

A

+ 0.75VS
1 / 7 6 B A1/86W

206

DDR3 SO-DIMM A

+ 0.75VS

Compal Secret Data

S ecurity Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1

C 212
0 .1U_0402_16V4Z

2

1

C 211
0 .1U_0402_16V4Z

2

1

C 210
0 .1U_0402_16V4Z

2

1

C 209
0 .1U_0402_16V4Z

2

1

C 208
10U_0603_6.3V6M

2

1

C 207
10U_0603_6.3V6M

2

1

C 206
10U_0603_6.3V6M

2

D D R_A_MA6
D D R _ A _MA4

1

1

C 202
10U_0805_6.3V6M

<8> D D R _ A _ WE#
<8> D D R _ A _ CAS#

1

D DR_A_MA11
D D R _ A _MA7

C 218
1 U_0402_6.3V6K

<8> D D R _ A _BS0

D D R _ A_MA10
D D R _ A _BS0

C

D D R _ A_MA15
D D R _ A_MA14

C 217
1 U_0402_6.3V6K

M _ C L K _DDR0
M _ C L K _DDR#0

D D R _ C K E 1 _DIMMA <8>

C 216
1 U_0402_6.3V6K

D D R _ A _MA3
D D R _ A _MA1
<8> M _ C L K _DDR0
<8> M _ C L K _DDR#0

D D R _ C K E 1 _DIMMA

C 215
1 U_0402_6.3V6K

D D R_A_MA8
D D R _ A _MA5

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

C 205
10U_0603_6.3V6M

D D R _ A_MA12
D D R _ A _MA9

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

C 204
10U_0603_6.3V6M

D D R _ A _BS2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

C 203
10U_0603_6.3V6M

<8> D D R _ A _BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

C 201
10U_0603_6.3V6M

D D R _ C K E 0 _DIMMA

C 214
2.2U_0402_6.3V6M

<8> D D R _ C K E 0 _DIMMA

C 213
0 .1U_0402_16V4Z

C

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

REVERSE
Compal Electronics, Inc.
Title
DDRIII-SODIMM SLOT1
Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P

Monday, April 13, 2009

Sheet
1

17

of

49

5

4

+ 1.5V

3

+ 1.5V

2

<8> D D R _ B _ DQS#[0..7]

4 B A 2 /6W

<8> D D R _ B _ D[0..63]

+ V R E F _ D Q_DIMMB

+ V R E F _ D Q_DIMMB

D D R _ B_MA12
D D R _ B _MA9
D DR_B_MA8
D D R _ B _MA5
D D R _ B _MA3
D D R _ B _MA1
<8> M _ C L K _DDR2
<8> M _ C L K _DDR#2

M _ C L K _DDR2
M _ C L K _DDR#2

<8> D D R _ B _BS0

D D R _ B_MA10
D D R _ B _BS0

<8> D D R _ B _ WE#
<8> D D R _ B _ CAS#

D D R _ B _ WE#
D D R _ B _ CAS#

<8> D D R _ C S 3 _DIMMB#

D D R _ B_MA13
D D R _ C S 3 _DIMMB#

D D R _ B _D32
D D R _ B _D33
D D R _ B _ DQS#4
D D R _ B _ DQS4
B

D D R _ B _D34
D D R _ B _D35
D D R _ B _D40
D D R _ B _D41
D D R _ B _DM5
D D R _ B _D42
D D R _ B _D43
D D R _ B _D48
D D R _ B _D49
D D R _ B _ DQS#6
D D R _ B _ DQS6
D D R _ B _D50
D D R _ B _D51
D D R _ B _D56
D D R _ B _D57
D D R _ B _DM7

1

2

1

2

C 242
0 .1U_0402_16V4Z

+ 3 VS
A

C 241
2.2U_0402_6.3V6M

D D R _ B _D58
D D R _ B _D59
1 R 210
2
10K_0402_5%
R 211

1

2

10K_0402_5%

205

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

G1

G2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

D D R _ B _D28
D D R _ B _D29
D D R _ B _ DQS#3
D D R _ B _ DQS3
D D R _ B _D30
D D R _ B _D31

D D R _ C K E 3 _DIMMB

Layout Note:
Pla ce near JP5

D D R _ C K E 3 _DIMMB <8>

D D R _ B_MA15
D D R _ B_MA14

C

DDR_B_MA11
D D R _ B _MA7
D DR_B_MA6
D D R _ B _MA4

+1.5V

D D R _ B _MA2
D D R _ B _MA0
M _ C L K _DDR3
M _ C L K _DDR#3
D D R _ B _BS1
D D R _ B _ RAS#
D D R _ C S 2 _DIMMB#
M _ ODT2
M _ ODT3

M _ C L K _DDR3 <8>
M _ C L K _DDR#3 <8>

1

D D R _ B _BS1 <8>
D D R _ B _ RAS# <8>

2 @

D D R _ C S 2 _DIMMB# <8>
M _ODT2 <8>
M _ODT3 <8>

1

1

2 @

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

2

1

2

+ V R E F _CA

V _ D D R _ M C H _ REF
D D R _ B _D36
D D R _ B _D37

1

D D R _ B _DM4

2

D D R _ B _D38
D D R _ B _D39

1

2

Layout Note:
Place near JP5.203 & JP5.204
B

+0.75VS

D D R _ B _D44
D D R _ B _D45
D D R _ B _ DQS#5
D D R _ B _ DQS5

1

D D R _ B _D46
D D R _ B _D47

2

D D R _ B _D52
D D R _ B _D53

1

2

1

2

1

2

D D R _ B _DM6
D D R _ B _D54
D D R _ B _D55
D D R _ B _D60
D D R _ B _D61
D D R _ B _ DQS#7
D D R _ B _ DQS7
D D R _ B _D62
D D R _ B _D63
P M_EXTTS#1_R
S M B _DATA_S3
S M B _CLK_S3

P M_EXTTS#1_R <6,17>
S M B _DATA_S3 <12,17,19,30>
S M B _CLK_S3 <12,17,19,30>
+ 0.75VS

A

DDR3 SO-DIMM B
REVERSE

1 / 7 6 B A1/86W

206

+ 0.75VS
C ONN@

Compal Secret Data

S ecurity Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1

C 234
0 .1U_0402_16V4Z

D D R _ B _BS2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

D D R _ B _D22
D D R _ B _D23

C 233
0 .1U_0402_16V4Z

<8> D D R _ B _BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

D D R _ B _DM2

C 232
0 .1U_0402_16V4Z

D D R _ C K E 2 _DIMMB

D D R _ B _D20
D D R _ B _D21

C 231
0 .1U_0402_16V4Z

<8> D D R _ C K E 2 _DIMMB

D R A M R ST# <6,17>

D D R _ B _D14
D D R _ B _D15

C 230
10U_0603_6.3V6M

C

D D R _ B _DM1
D R A M R ST#

C 229
10U_0603_6.3V6M

D D R _ B _D26
D D R _ B _D27

D

D D R _ B _D12
D D R _ B _D13

C 228
10U_0603_6.3V6M

D D R _ B _DM3

0_0402_5%

C 227
10U_0603_6.3V6M

D D R _ B _D24
D D R _ B _D25

2
M 3@

C 240
1 U_0402_6.3V6K

D D R _ B _D18
D D R _ B _D19

1
R 899

D D R _ B _D6
D D R _ B _D7

C 226
10U_0603_6.3V6M

D D R _ B _ DQS#2
D D R _ B _ DQS2

D D R _ B _ DQS#0
D D R _ B _ DQS0

C 239
1 U_0402_6.3V6K

D D R _ B _D16
D D R _ B _D17

+ V _ D D R _ C P U_REF1

2
0_0402_5%

C 225
10U_0603_6.3V6M

D D R _ B _D10
D D R _ B _D11

1

<8> D D R _ B _MA[0..15]

C 238
1 U_0402_6.3V6K

D D R _ B _ DQS#1
D D R _ B _ DQS1

D D R _ B _D4
D D R _ B _D5

C 224
10U_0603_6.3V6M

D D R _ B _D8
D D R _ B _D9

R 885

<8> D D R _ B _ D QS[0..7]

C 237
1 U_0402_6.3V6K

D D R _ B _D2
D D R _ B _D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C 223
10U_0603_6.3V6M

D D R _ B _DM0

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C 1060
2 .2U_0603_6.3V4Z

2

D D R _ B _D0
D D R _ B _D1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C 235
0 .1U_0402_16V4Z

D

1

C 1059
0.1U_0402_10V6K

2

C 221
2.2U_0402_6.3V6M

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+ V _ D D R _ C P U_REF

<8> D D R _ B _ DM[0..7]

J D I MM2
V _ D D R _ M C H _ REF

1

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Title

Compal Electronics, Inc.
DDRIII-SODIMM SLOT2

Size

D o c u m ent Number

Rev
0 .1

Ca lp e lla DI S LA4 743P
D a te:

Monday, April 13, 2009

Sheet
1

18

of

49

5

4

3

2

1

+1.05VS_CK505
+1.05VS_CK505
+3VS_CK505

80mA

CLK_14M_PCH @ C808 1

+3VS_CK505

2 10P_0402_50V8J

U3

<12> CLK_BUF_DOT96
DOT96 <12> CLK_BUF_DOT96#

OK
D

OK

27M

OK
OK

CKSSCD

<24>
<24>

27M_CLK
27M_SSC

<12>

CL K_DMI
CLK_DMI#

DMI<12>

27M_CLK
27M_SSC

CL K_DMI
C LK_DMI#
CL K _BUF_CKSSCD
CL K_BUF_CKSSCD#

<12> CL K _BUF_CKSSCD
<12> CL K_BUF_CKSSCD#

R213 2
R214 2

1
1

33_0402_5% L_CLK_BUF_DOT96
33_0402_5% L_CLK_BUF_DOT96#

@ R216 2
@ R217 2

1
1

33_0402_5% L_27M_CLK
33_0402_5% L_27M_SSC

R221 1
R223 1

2
2

33_0402_5% L _CLK_DMI
33_0402_5% L_CLK_DMI#

R219 1
R220 1

2
2

33_0402_5% L _CLK_BUF_CKSSCD
33_0402_5% L _CLK_BUF_CKSSCD#
CPU_STOP#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

VDD_DOT
VSS_DOT
DOT_96
DOT_96# 96MHz
VDD_27
27MHZ
27MHZ_SS
VSS_27
VSS_SATA
SRC_1/SATA
SRC_1#/SATA# 100MHz
VSS_SRC
SRC_2
SRC_2# 100MHz
VDD_SRC_IO
CPU_STOP#

SMB_CLK_S3
SMB_DATA_S3
R EF_0/CPU_SEL

32
31
30
29
28
27
26
25

SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#

SMB_CLK_S3 <12,17,18,30>
SMB_DATA_S3 <12,17,18,30>
R222 2
1 33_0402_5%

CLK_14M_PCH

CLK_14M_PCH <12>

CLK_XTAL_IN
CLK_XTAL_OUT

14M OK
D

@

24
23
22
21
20
19
18
17

VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC

133MHz

TGND

250mA
CLK_BUF_DOT96
CLK_BUF_DOT96#

R_ CK P WRGD

R226 1
R237 1

2 0_0402_5%
2 0_0402_5% CK P W R GD

L_CLK_BUF_BCLK
L_CLK_BUF_BCLK#

R224 1
R225 1

2 33_0402_5%
2 33_0402_5%

VGATE

<13,46>

CLK_BUF_BCLK <12>
CLK_BUF_BCLK# <12>

BCLK OK

33

SLG8SP585VTR_QFN32_5X5

1

DOT_CLK(96MHz)

1

27MHz

1

27MHz_SS

+3VS_CK505

C259
18P_0402_50V8J

1

2

2

2 14.318MHZ_16PF_7A14300083
C260
18P_0402_50V8J

1

1

1

CPU_1

<46>

CLK_EN#

+3VS_CK505

0(default)

133MHz

133MHz

1

100MHz

100MHz

CPU_STOP#

R234 1

1

CPU_0

D

3

CK P W R GD

PIN 30

S Q30
2N7002_SOT23-3

2

CLK_EN# 2
G

2

2

1

2

1

2

Place close to U51
C

R218
1
2
0_0805_5%

Vendor suggests 22pF

2

+1.05VS_CK505

+ V CCP
R607
10K_0402_5%

2

C

2

CLK_XTAL_OUT
CLK_XTAL_IN
Y3

1

C250
0.1U_0402_16V4Z

1

1

C249
0.1U_0402_16V4Z

1

REF(14.318MHz)

1

C248
0.1U_0402_16V4Z

SRC/SATA(100MHz)

1

C247
0.1U_0402_16V4Z

1

1

2

1

2

C254
0.1U_0402_16V4Z

SRC(100MHz_SS)

2

0_0805_5%

C246
0.1U_0402_16V4Z

2

+3VS_CK505
R212
1

C253
0.1U_0402_16V4Z

133MHz

+3VS

SLG8SP585Κ pin8 is GND (for DELLΕHP)
SLG8SP587Κ pin8 is 48MHz (For ABO or 030)

C245
10U_0805_10V4Z

Number

1

Output

C252
10U_0805_10V4Z

Number of Clock Outputs

Routing the trace at least 10mil

2 10K_0402_5%

CPU_SEL During CK_PEWGD Latch Pin1
+3VS
@
R244 1

2 10K_0402_5%

R247 1

2 10K_0402_5%

R EF_0/CPU_SEL

B

B

A

A

Compal Secret Data

Security Classification
2007/08/28

Issued Date

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title
Size

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.
Clock Generator CK505

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Sheet

Monday, April 13, 2009
1

19

of

49

C

D

E

BLUE
GR EEN
R ED

0.1U_0402_16V4Z
2
C266
J CRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

GR EEN
BLUE
+5VS
C268
0.1U_0402_16V4Z
1
2

R270
4.7K_0402_5%

2

A

3

Y

R274 1

2 0_0603_5%

D_ V S YNC
D_ DD CDATA
1

R272
4.7K_0402_5%

R271
4.7K_0402_5%

@ C269
5P_0402_50V8C

2

1

6

1
3

2

1

I_ C RT_DDC_DATA

1

@ C270
5P_0402_50V8C

2

2

R273
4.7K_0402_5%
2

V S YNC_G_A

4

U6
SN74AHCT1G125GW_SOT353-5

1

1
D_ HS Y NC

1

1

2 0_0603_5%

5
1

3

CRT _ VSYNC

G

<22> CRT _VSYNC

R269 1

2

A

P
OE#

2

DGP U_EDIDSEL#
+3VS

+ CRTVDD

2

5
1
CRT _ HS YNC

DGP U_EDIDSEL#

+ CRTVDD

P
OE#

<22> CRT _ HSYNC

16
17

SUYIN_070546FR015S263ZR
C ONN@

1 10K_0402_5%

U5
SN74AHCT1G125GW_SOT353-5
HS Y N C_G_A
4
Y

G

2

+3VS

UMA@
R901
10K_0402_5%

2

R815 2

+3VS

Q2A
2N7002DW-7-F_SOT363-6
3

D_ DDC CLK

I_ CRT_DDC_DATA <13>

5

C267
0.1U_0402_16V4Z
1
2

1

2

+5VS

Place close to
JCRT1

1

R ED

3

1

1

1 .1A_6VDC_FUSE

D8
DAN217T146_SC59-3

RB491D_SC59-3

W=40mils

2

2

CRT Connector

F1
1

1

D7

3

D9
2

D6

+ CRT VDD

DAN217T146_SC59-3

1

+ RCRT_VCC

2

+5VS

DAN217T146_SC59-3

B

2

A

I_ CRT _DDC_CLK

4

I_ CRT_DDC_CLK <13>

Q2B
2N7002DW-7-F_SOT363-6

1

S G@
R878
4.7K_0402_5%

1

E D IDSEL

2

2 0_0402_5%

2

R900 1
SG@

S G@
R879
4.7K_0402_5%

2

DGP U_EDIDSEL

+3VS_NV

D_ DD CDATA

6

1

S G@

D_ CRT_DDC_DATA <24>

Q11A

2N7002DW-7-F_SOT363-6
3

3

E D IDSEL
5

E DIDSEL <22>

D_ DDC CLK

3
S G@

CRT Termination/EMI Filter
<22>

M _RED

4

D_ CRT _DDC_CLK <24>

Q11B

2N7002DW-7-F_SOT363-6

C_ R ED

L8

C_ GRN

L9

1

2 HLC0603CSCCR11JT_0603

R ED

1

2 HLC0603CSCCR11JT_0603

GR EEN

C_ BLU

L10 1

2 HLC0603CSCCR11JT_0603

BLUE

+3VS

2

@

1

2

1

2

1

2

1

1

3

@

DGP U_EDIDSEL
SG@
Q12B
2N7002DW-7-F_SOT363-6

Q12A
2N7002DW-7-F_SOT363-6

2

5

6

4

<14> DGPU_EDIDSEL#

DGP U_EDIDSEL#

SG@
R902
10K_0402_5%

1

2

C276
10P_0402_50V8J

1

C275
10P_0402_50V8J

@

C274
10P_0402_50V8J

2

C273
22P_0402_50V8J

1

C272
22P_0402_50V8J

R277
150_0402_1%

R276
150_0402_1%
2
1

2

1

M_BLUE
R275
150_0402_1%
2
1

<22>

C271
22P_0402_50V8J

2

<22> M _GREEN

4

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

C

D

Compal Electronics, Inc.
CRT Connector

Size

http://laptop-motherboard-schematic.blogspot.com/
B

4

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Sheet

Monday, April 13, 2009
E

20

of

49

5

D

02/20 Change to 0805 size

0.1U_0402_16V4Z

1

2

2

R278
470_0805_5%

C282

3

S

1

0.1U_0402_16V4Z

2

1

R279
1M_0402_5%

C280
4.7U_0805_10V4Z

1

2
G

1

2
2

R280
2

2

DM IC_DAT <33>
DM IC_CLK <33>
+5VS
LVDS_INV_PWM <22>
BKOFF# <37>

C283
4.7U_0805_10V4Z

1

100K_0402_5%

2N7002DW-7-F_SOT363-6
Q3A

C284
0.047U_0402_16V7K

02/13 Reserve

3

DM IC_DAT
DM I C_CLK
+3V_LOGO
R281
1
LVDS_INV_PWM 100_0805_5%
BKOFF#

Limited Current < 1A
BKOFF#

+USB_CAM
L V DS_EDID_CLK <22>
LVDS_EDID_DATA <22>

<13>

I_ E NAVDD

I_ E NAVDD

5

@ R282
10K_0402_5%

R283
10K_0402_5%

1

C

4

L V DS_EDID_CLK
LVDS_EDID_DATA

C281

2

LVDS_A2- <22>
LVDS_A2+ <22>
LVDS_A1- <22>
LVDS_A1+ <22>
LVDS_A0- <22>
LVDS_A0+ <22>
LVDS_ACLK- <22>
LVDS_ACLK+ <22>

Q3B
2N7002DW-7-F_SOT363-6

+3VS

LVDS_A2LVDS_A2+
LVDS_A1LVDS_A1+
LVDS_A0LVDS_A0+
LVDS_ACLKLVDS_ACLK+

1

USB20_P4
USB20_N4

2
1
2
4
3
4
6
5
6
8
7
8
10
9
10
12
11
12
14
13
14
16
15
16
18
17
18
20
19
20
22
21
22
24
23
24
26
25
26
28
27
28
30
29
30
32
31
32
34
33
34
36
35
36
38
37
38
40
39
40
42
GND GND
ACES_88242-4001
C ONN@

Q13
SI2301BDS-T1-E3_SOT23-3
D

J LVDS1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

+5VALW

+3VS

1

+ L CDVDD
1

+ L CDVDD

+ L CDVDD

6 2

1
2

LVDS CONN & USB Camera + Dig Mic

2

USB20_P4
USB20_N4

C279
680P_0402_50V7K

C278
680P_0402_50V7K

1
2

C277
680P_0402_50V7K

<14>
<14>

2

1

INV PWR_B+

D

1

2

1

+ L CDVDD

3

2

+3VS

4

01/03 Change to 0.047u to meet T1 timing

C

S

S G@
Q33
2N7002_SOT23-3

1

EMI request.

1
SG@
R880
2.2K_0402_5%

D

2
G

<24> D_ E NAVDD
2

2

C286
680P_0402_50V7K

3

1

Must close JLVDS1pin 24Ε
Ε26

+3VS

R285
2.2K_0402_5%
1

1

R284
2.2K_0402_5%
L V DS_EDID_CLK
LVDS_EDID_DATA

DM IC_DAT

2

2

DM I C_CLK
B+

@ C287
220P_0402_25V8J

1

2

1

INVPWR_B+
@
L11

@ C288
220P_0402_25V8J

2

1

2

0_0805_5%

L12
1
2
FBMA-L11-201209-221LMA30T_0805

0308_Reserve L10 and install L11.
B

B

USB Camera

+USB_CAM
+5VS

2

OUT

R286
215K_0603_1%

5

GND

1

2
SHDN

BYP

4
1

3

1
1

G916-390T1UF_SOT23-5

2
R287
100K_0402_1%

2

@

2

2

1

C981
47P_0402_50V8J

IN

C289
10U_0805_6.3V6M

2
R288
0_0402_5%
C290
10U_0805_6.3V6M

1

U7
1

+USB_CAM is +3.9VS, R286:215K; R287:100Kohm

+USB_CAM=1.25(1+R1091/R1093)

A

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title

3

2

Compal Electronics, Inc.
LCD CONN.

Size

http://laptop-motherboard-schematic.blogspot.com/
4

A

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Sheet

Monday, April 13, 2009
1

21

of

49

5

4

LVDS Switch

3

2

1

LVDS I2C switch

+ 3VS

Backlight Enable

52
5
54
51
57

SEL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC
NC
NC
NC
Thermal_GND

1

<24> D _ E D I D _DATA
R 919

2
SG@
Q 35A
2 N 7002DW-7-F_SOT363-6

L V D S _ E D ID_DATA <21>

S G @ Q 34A
2 N7002DW-7-F_SOT363-6

2 0_0402_5%

1

L V D S _ E D ID_DATA

5

2

<13> I G P U _BKLT_EN

4

<13> I _ E D I D_DATA

6

R 790

2

D G P U _ SELECT#

0_0402_5%
SG@

1
6
9
13
16
21
24
28
33
39
44
49
53
55

D G P U _ SELECT# <14>

4

<24> D _ E D I D _CLK
R 920

<13> I _ E D I D_CLK

2 0_0402_5%

1

SG@
R 8 82
4.7K_0402_5%
E N B KL

3 1

SG@
R 883
4.7K_0402_5%

2

S G @ C 1005
4 .7U_0805_10V4Z

<20>

1

1

L V DS_A0+ <21>
L V DS_A0- <21>
L V DS_A1+ <21>
L V DS_A1- <21>
L V DS_A2+ <21>
L V DS_A2- <21>
L V D S _ACLK+ <21>
L V D S_ACLK- <21>

E D I D SEL

3

17

E D I D S EL

ENBKL

D

<37>

6

L V DS_A0+
L V DS_A0L V DS_A1+
L V DS_A1L V DS_A2+
L V DS_A2L V D S _ACLK+
L V D S_ACLK-

3

L V D S _ E D ID_CLK

SG@
Q 37B
2 N7002DW-7-F_SOT363-6

5

<24> D G P U _ BKL_EN
L V D S _ E DID_CLK <21>

SG@
R 886
10K_0402_5%

S G @ Q 34B
2 N7002DW-7-F_SOT363-6

4

0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2

2

2
3
7
8
11
12
14
15
19
20

+ 3 VS

2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

1

1

46
45
41
40
35
34
30
29
25
26

0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1

2

I _ L VDS_A0+
I _ LVDS_A0I _ L VDS_A1+
I _ LVDS_A1I _ L VDS_A2+
I _ LVDS_A2I _ L V DS_ACLK+
I _ L VDS_ACLK-

I _ LVDS_A0+
I _ LVDS_A0I _ LVDS_A1+
I _ LVDS_A1I _ LVDS_A2+
I _ LVDS_A2I _ L V DS_ACLK+
I _ L VDS_ACLK-

48
47
43
42
37
36
32
31
22
23

S G@
Q 35B
2 N 7002DW-7-F_SOT363-6

1

<13>
<13>
<13>
<13>
<13>
<13>
<13>
<13>

D _ L VDS_A0+
D _ L VDS_A0D _ L VDS_A1+
D _ L VDS_A1D _ L VDS_A2+
D _ L VDS_A2D _ L V D S_ACLK+
D _ L V DS_ACLK-

4
10
18
27
38
50
56

5

D

<25> D _ L VDS_A0+
<25> D _ L VDS_A0<25> D _ L VDS_A1+
<25> D _ L VDS_A1<25> D _ L VDS_A2+
<25> D _ L VDS_A2<25> D _ L V DS_ACLK+
<25> D _ L V D S_ACLK-

VCC
VCC
VCC
VCC
VCC
VCC
VCC

S G @ C 1004
0 .1U_0402_16V4Z

U35

I G P U _BKLT_EN

2 UMA@
0_0402_5%

1
R 7 99

E N B KL

UMA ONLY (LVDS)

T S 3 D V 5 2 0ERHUR_QFN56_11X5~D
S G@

C

LVDS PWM switch

2

+ 3VS

1 0_0402_5%

I N V _ P WM <37>

R P 36 4

I _ LVDS_A1I _ LVDS_A1+

R P 37 4

I _ LVDS_A2+
I _ LVDS_A2-

R P 38 3

I _ L VDS_ACLKI _ L V DS_ACLK+

R P 39 4

3
3
4
3

L V DS_A01
L V DS_A0+
2
U M A @ 0_0404_4P2R_5%
L V DS_A11
L V DS_A1+
2
U M A @ 0_0404_4P2R_5%
L V DS_A2+
2
L V DS_A21
U M A @ 0_0404_4P2R_5%
L V D S_ACLK1
L V D S _ACLK+
2
U M A @ 0_0404_4P2R_5%

C

1

2

SG@
R 891
4.7K_0402_5%

S G@
@ R 890 2
R 8 89
4.7K_0402_5%

I _ LVDS_A0I _ LVDS_A0+

6

SG@
Q 36A
2 N7002DW-7-F_SOT363-6

6

1

L V D S _ I NV_PWM <21>

1

3

1

2

<13> D P S T _ PWM

S G@
Q 37A
2 N 7002DW-7-F_SOT363-6

2

D P S T _ PWM

5

<24> D _ I N V _ PWM

4

CRT Switch

U MA@
R 892 2

1 0_0402_5%

L V D S _ I NV_PWM

SG@
Q 36B
2 N7002DW-7-F_SOT363-6

+ 3 VS

2

1 SG@
C 1013
2

0 .1U_0402_16V4Z

2

1 SG@
C 1012

0 .1U_0402_16V4Z

1 SG@
C 1011

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

B

B

1 SG@
C 1014
2

U 43
+ 3VS

1
4
9
19

<24>
<24>
<24>
<24>
<24>

D _RED
D _ G R E EN
D _ B L UE
D_ CRT_ HSYNC
D _ C R T _ V S Y NC

24
22
18
17
14

<13>
<13>
<13>
<13>
<13>

I_RED
I _ G R EEN
I _ B LUE
I _ C R T _ H S Y NC
I _ C R T _ V S YNC

23
21
16
15
13

VDD
VDD
VDD
VDD
A0
B0
C0
D0
E0
A1
B1
C1
D1
E1

SEL
YA
YB
YC
YD
YE
GND
GND
GND
GND

12

D G P U _ SELECT#

2
5
6

M_ RED
M _ G R EEN
M _ B LUE

8
11

C RT_ HSYNC
CRT_ VSYNC

UMA ONLY (CRT)
M_ RED
<20>
M _ G R EEN <20>
M _ B LUE <20>

I_RED
I _ G R EEN
I _ B LUE
I _ C R T _ H S Y NC
I _ C R T _ V S YNC

C R T _ H S Y N C <20>
C R T _ V S Y N C <20>

R 893
R 894
R 895
R 896
R 897

2
2
2
2
2

UMA@
UMA@
UMA@
UMA@
UMA@

1
1
1
1
1

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

M_ RED
M _ G R EEN
M _ B LUE
C RT_ HSYNC
CRT_ VSYNC

3
7
10
20

P I3V512QE_QSOP24
SG@

A

A

Compal Secret Data

S ecurity Classification
Issued Date

2007/09/29

Deciphered Date

2007/09/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Title

Compal Electronics, Inc.
LVDS Switch

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P

Monday, April 13, 2009

Sheet
1

22

of

49

5

V

X

X

R867

V

X

X

9
UMA@
R850 1

2 0_0402_5%

10

1
2
+3VS_LS
@C1052
2.2U_0603_6.3V4Z

UMA@
R853 1
@ R855 1

2 0_0402_5%

11

2 4.7K_0402_5%

12
49

+3VS_LS
@ R859

2 0_0402_5%

1

HPD_SINK

SDA_SOURCE

SDA_SINK

@ R857 1
UMA@
R858 1

SCL_SOURCE

SCL_SINK

ANALOG2

GND

VCC3V

VCC3V

GND
thm_pad

2 4.7K_0402_5%
2 0_0402_5%

OE*

S G@
C375 2

1 0.1U_0402_16V4Z HDM ICLK-

1

<25> HDM I_C_CLK+

S G@
C376 2

1 0.1U_0402_16V4Z HDM ICLK+

4

1

2

4

3

@ R866

1

UMA@
R839 2
UMA@
R841 2

34

UMA@ R843
@ R844
UMA@ R845
@ R846

33
32

1
1
1
1

0_0402_5%
0_0402_5%
4.7K_0402_5%
0_0402_5%

WCM-2012-900T_0805
HDM I_R_CLK+
3

30

H DMI_DETECT

29

HD MIDAT

28

HDM ICLK
@ R851 2

27
26

+3VS_LS

R856 2
UMA@

25

14.7K_0402_5%

R854 1
UMA@

HDM ICLK-

1 0_0402_5%

C

H DMI_DETECT 2
S G@ Q19A
2N7002DW-7-F_SOT363-6

@ R861
1

+3VS_LS

+3VS_LS

@C1054
HDMI_TX_0+

2
68_0402_5%

UMA@
R862
20K_0402_5%
UMA@
R865
2
1 TMDS_B_HPD

0.5P_0402_50V8B

+3VS_LS

1 0.1U_0402_16V4Z HDMI_TX_0+

4

2

2

4

HDMI_TX_1@ R864
@C1056
HDMI_TX_1+
1
2
68_0402_5%
0.5P_0402_50V8B

@C1055

HDMI_R_TX0-

HDMI_TX_2-

@ R863
1
2
68_0402_5%
0.5P_0402_50V8B

2

2 0_0402_5%

1

<13> TMDS_B_HPD#

0_0402_5%
UMA@
R867
7.5K_0402_1%

WCM-2012-900T_0805
HDMI_R_TX0+
3

3

R852
10K_0402_5%
UMA@

+3VS_LS

2 0_0402_5%

2

<25> HDMI_C_TX0+

S G@
C378 2

1

UMA@

+3VS_LS

HDMI_TX_0@ R860
1
2
68_0402_5%
0.5P_0402_50V8B

L29
1 0.1U_0402_16V4Z HDMI_TX_0-

+3VS_LS

31

S IC STHDLS101TQTR QFN 48P HDMI SHIFTER

@C1053

HDM ICLK+

HDMI_TX_2+
<25> HDMI_C_TX0-

+3VS_LS

HDM I_R_CLK-

2

2

1

10U_0805_6.3V6M

1 0_0402_5%

2
2
2
2

1

@ R868

C1051

UMA@
C1050

1 0_0402_5%

0_0402_5%

S G@
C377 2

0.1U_0402_10V6K

1 4.7K_0402_5% +3VS_LS

36
35

L28

<25> HDM I_C_CLK-

0.1U_0402_10V6K

UMA@

0.01U_0402_16V7K
C1049
UMA@

C1048

37
GND

39

38
IN_D1-

IN_D1+

41

40

IN_D2-

VCC3V

42

43
GND

IN_D2+

45

44
IN_D3-

46
VCC3V

IN_D3+

48

47
IN_D4-

HPD_SOURCE

1 4.7K_0402_5% +3VS_LS

@ R835 2

1

8

@ R834 2

1

R862

2

+3VS_LS

2

1uF

2

1

6

4.7K ohm

1uF

1

1

X

0.1uF

2

GND

X

C667

GND

24

R835

ANALOG1(REXT)

OUT_D1-

X
X

<13> HDM ID_CTRLCLK

DDC_EN

OUT_D1+

X

7

<13> HDM ID_CTRLDATA

EQUALIZATION SETTING:
[PC1,PC0]=00,8dB
[PC1,PC0]=01,4dB (Recommanded)
[PC1,PC0]=10,12dB
[PC1,PC0]=11,0dB

4.7K ohm

X

1 4.3K_0402_1%6

GND

23

X
0 ohm

UMA@
R849 2

TMDS_B_HPD

4.7K ohm

X

0 ohm

UMA@
R848
2.2K_0402_5%

VCC3V

22

X

X

5

P C1

FUCNTION2

VCC3V

0 ohm

X

UMA@
R847
2.2K_0402_5%

X

4

OUT_D2-

R834
R841

0 ohm

2
0_0402_5%

FUNCTION3

21

R839

0 ohm

4.7K ohm

FUNCTION4

P C0

FUNCTION1

20

R844

0 ohm

X

1

VCC3V

OUT_D2+

R843

X

X

3

GND

R854

0 ohm

@ R842

GND

19

R851

0 ohm

+3VS_LS

GND

18

4.7K ohm

2

OUT_D3-

X

1

17

X

1
2
0_0402_5%
+3VS_LS

OUT_D3+

R857

@ R836
4.7K_0402_5%
UMA@
R840
1
2
4.7K_0402_5%

@ R838
4.7K_0402_5%

VCC3V

4.7K ohm

16

X

UMA@
R837

UMA@
U47

15

X

R858

+3VS_LS

2 0_0402_5%

X

R855

@ R833
4.7K_0402_5%

+3VS_LS

IN_D4+

@ R576 1

1

1

D

HDM ICLK

OUT_D4-

2.2uF

0 ohm

2

2 0_0402_5%

OUT_D4+

X

<25> HDMICLK_VGA

14

X
0 ohm

X

TMDSD_DATA0 <13>
TMDSD_DATA0# <13>

13

R853

X

1

C1052

0 ohm

2

+3VS_LS

SG@
Q5B
@ R575 1
2N7002DW-7-F_SOT363-6
3

4

<13> TMDSD_CLK#
<13> TMDSD_CLK

1

R849 3.9K ohm 499 ohm 499 ohm

HD MIDAT

6

TMDSD_DATA1 <13>
TMDSD_DATA1# <13>

2

1

1

<25> HDMIDAT_VGA

X

<13> TMDSD_DATA2#
<13> TMDSD_DATA2

1

X

2

X

X

S G@
Q5A
2N7002DW-7-F_SOT363-6

1

X

R842

1

+3VS

+3VS_LS

2

4.7K ohm

R838

R850

C

4.7K ohm

2

D

X

@ R572
2.2K_0402_5%

1

R840 4.7K ohm

@ R571
2.2K_0402_5%

X

+3VS_LS

0_0603_5%

2

4.7K ohm

+3VS_NV

2

X

1

UMA@
R832

0 ohm 4.7K ohm

0 ohm

2

+3VS_NV

2

X

3

5

R836

X

X

2

R837

Parade
8171

1

ST
R833

4

Parade
8101T

@ R869

1

2

@ R870

1

2 0_0402_5%

0_0402_5%
+ 5VS_HDMI

@ R871

1

WCM-2012-900T_0805
HDMI_R_TX1+
3

1

2
2 0_0402_5%

1
L31

<25> HDMI_C_TX2+

S G@
C381 2

1 0.1U_0402_16V4Z HDMI_TX_2+

4

1
4

@ R873

2

2

<24>

4

HDMI_DET
S G@
R924
10K_0402_5%

WCM-2012-900T_0805
HDMI_R_TX2+
3

3
1

HDMI_R_TX2-

2

+5VS_HDMI
B
A

Y
3

1

1

1 0.1U_0402_16V4Z HDMI_TX_2-

0_0402_5%
HDM ICLKHDM ICLK+
HDMI_TX_0HDMI_TX_0+
HDMI_TX_1HDMI_TX_1+
HDMI_TX_2HDMI_TX_2+

H DMI_DETECT

1

DGP U _PWR_EN

DGP U_PWR_EN <14,39,45,47>

U51
NC7SZ08P5X_NL_SC70-5
S G@

@

R579
1
2
10K_0402_1%

1

1

H DMI_DETECT

L32

1

HDM I_R_CLKHDM I_R_CLK+
HDMI_R_TX0HDMI_R_TX0+
HDMI_R_TX1HDMI_R_TX1+
HDMI_R_TX2HDMI_R_TX2+

4

C668
330P_0402_50V7K 2

Q19B
2N7002DW-7-F_SOT363-6
S G@

2

2

3

2

<14> DGP U_HPD_INT#

SG@
R740

R580
100K_0402_1%
2

1

1

1
S G@
R739
2

SG@
R738
2

S G@
R737
2

S G@
R736

1

1

1
SG@
R735
2

S G@
R734
2

2

1

1

5

1
D35
SKS10-04AT_TSMA

18
16
15
19

HD MIDAT
HDM ICLK
2 FBML10160808121LMT_0603

12
10
9
7
6
4
3
1

Compal Secret Data

1

Security Classification
D

S

2007/08/28

Issued Date

S G@ Q31
2N7002_SOT23-3

2
G
3

5

2

1

2

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

CKCK+
D0D0+
D1D1+
D2D2+

CEC
Reserved
GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND

13
14
2
5
8
11
20
21
22
23
17

A

3

2

Compal Electronics, Inc.
HDMI LS & Conn.

Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
4

+5V
SDA
SCL
HP_DET

SUYIN_100042MR019S153ZL
C ONN@

499_0402_1%
499_0402_1%
499_0402_1%
499_0402_1%
499_0402_1%
499_0402_1%
499_0402_1%

+3VS_NV

1

J HDMI1

SG@
R733
499_0402_1%

A

2

2

<25> HDMI_C_TX2-

2

@

5

@ R872
S G@
C382 2

D34
RB411DT146_SOT23-3

HDMI Connector

+3VS

0_0402_5%

B

C667
0.1U_0402_16V4Z

3

22N_0402_16V7K

4

C666
22N_0402_16V7K

4

HDMI_R_TX1-

C665

1 0.1U_0402_16V4Z HDMI_TX_1+

2

2

S G@
C380 2

2

1

<25> HDMI_C_TX1+

1

R577
1
2
1.5K_0402_5%
R578
1
2
1.5K_0402_5%

1

P

1 0.1U_0402_16V4Z HDMI_TX_1-

G

S G@
C379 2

B

+5VS

L30

<25> HDMI_C_TX1-

Da te:

Rev
0.1

LA4743P
Sheet

Monday, April 13, 2009
1

23

of

49

1

2

3

4

5

U8A
P a rt 1 of 5

C 776
C 777
C 778
C 779
C 780
C 781
C 782
C 783
C 784
C 785
C 786
C 787
C 788
C 789
C 790
C 791
C 792
C 793
C 794
C 795
C 796
C 797
C 798
C 799
C 800
C 801
C 802
C 803
C 804
C 805
C 806
C 807

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z
0 .1U_0402_16V4Z

<12> C L K _ P CIE_VGA
<12> C L K _ P CIE_VGA#
R 6 89 1

<14> D G P U _ H O LD_RST#
+ 3 VS_NV

AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26

C LK_PCIE_VGA
C LK_PCIE_VGA#

AB10
AC10

2 200_0402_1%

AF10
AE10

S G @ R 6 91 1

2 2.49K_0402_1%

AG10

S G @ R 6 93 1

2 0_0402_5%

S G @ R 6 94 1

@

PCIE_CRX_GTX_G_P15
PCIE_CRX_GTX_G_N15
P C IE_CRX_GTX_G_P14
P C IE_CRX_GTX_G_N14
P C IE_CRX_GTX_G_P13
P C IE_CRX_GTX_G_N13
P C IE_CRX_GTX_G_P12
P C IE_CRX_GTX_G_N12
P C IE_CRX_GTX_G_P11
P C IE_CRX_GTX_G_N11
P C IE_CRX_GTX_G_P10
P C IE_CRX_GTX_G_N10
P C IE_CRX_GTX_G_P9
P C I E_CRX_GTX_G_N9
PCIE_CRX_GTX_G_P8
PCIE_CRX_GTX_G_N8
PCIE_CRX_GTX_G_P7
PCIE_CRX_GTX_G_N7
PCIE_CRX_GTX_G_P6
PCIE_CRX_GTX_G_N6
PCIE_CRX_GTX_G_P5
PCIE_CRX_GTX_G_N5
PCIE_CRX_GTX_G_P4
PCIE_CRX_GTX_G_N4
PCIE_CRX_GTX_G_P3
PCIE_CRX_GTX_G_N3
PCIE_CRX_GTX_G_P2
PCIE_CRX_GTX_G_N2
PCIE_CRX_GTX_G_P1
PCIE_CRX_GTX_G_N1
PCIE_CRX_GTX_G_P0
PCIE_CRX_GTX_G_N0

2 10K_0402_5%

P EX_RST#

AD9
AE9

GPIO
DACA

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_VREF
DACA_RSET

DACB

SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@
SG@

PCI EXPRESS

P C IE_CRX_GTX_P15
P C IE_CRX_GTX_N15
P C IE_CRX_GTX_P14
P C IE_CRX_GTX_N14
P C IE_CRX_GTX_P13
P C IE_CRX_GTX_N13
P C IE_CRX_GTX_P12
P C IE_CRX_GTX_N12
P C IE_CRX_GTX_P11
P C IE_CRX_GTX_N11
P C IE_CRX_GTX_P10
P C IE_CRX_GTX_N10
P C IE_CRX_GTX_P9
P C I E_CRX_GTX_N9
P C IE_CRX_GTX_P8
P C I E_CRX_GTX_N8
P C IE_CRX_GTX_P7
P C I E_CRX_GTX_N7
P C IE_CRX_GTX_P6
P C I E_CRX_GTX_N6
P C IE_CRX_GTX_P5
P C I E_CRX_GTX_N5
P C IE_CRX_GTX_P4
P C I E_CRX_GTX_N4
P C IE_CRX_GTX_P3
P C I E_CRX_GTX_N3
P C IE_CRX_GTX_P2
P C I E_CRX_GTX_N2
P C IE_CRX_GTX_P1
P C I E_CRX_GTX_N1
P C IE_CRX_GTX_P0
P C I E_CRX_GTX_N0

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

DACB_HSYNC
DACB_VSYNC
DACB_RED
DACB_BLUE
DACB_GREEN
DACB_VREF
DACB_RSET

TEST

<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>

AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA

I2C

B

P C IE_CTX_GRX_P15
P C IE_CTX_GRX_N15
P C IE_CTX_GRX_P14
P C IE_CTX_GRX_N14
P C IE_CTX_GRX_P13
P C IE_CTX_GRX_N13
P C IE_CTX_GRX_P12
P C IE_CTX_GRX_N12
P C IE_CTX_GRX_P11
P C IE_CTX_GRX_N11
P C IE_CTX_GRX_P10
P C IE_CTX_GRX_N10
P C IE_CTX_GRX_P9
P C I E_CTX_GRX_N9
P C IE_CTX_GRX_P8
P C I E_CTX_GRX_N8
P C IE_CTX_GRX_P7
P C I E_CTX_GRX_N7
P C IE_CTX_GRX_P6
P C I E_CTX_GRX_N6
P C IE_CTX_GRX_P5
P C I E_CTX_GRX_N5
P C IE_CTX_GRX_P4
P C I E_CTX_GRX_N4
P C IE_CTX_GRX_P3
P C I E_CTX_GRX_N3
P C IE_CTX_GRX_P2
P C I E_CTX_GRX_N2
P C IE_CTX_GRX_P1
P C I E_CTX_GRX_N1
P C IE_CTX_GRX_P0
P C I E_CTX_GRX_N0

I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA

PEX_REFCLK
PEX_REFCLK_N

PEX_TERMP

XTAL_SSIN
XTAL_OUTBUFF

PEX_RST_N
PEX_CLKREQ_N

N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

H D M I _ DET <23>
D _ I N V _ PWM <22>
D _ E N A V D D <21>
D G P U _ B KL_EN <22>
G P U _ VID0 <47>
G P U _ VID1 <47>
G P U _ VID2
S G @ R 327 1
S G @ R 328 1

THERMAL ALERT
S IN N_GPIO9

XTAL_OUT
XTAL_IN

2 0_0402_5%
2 0_0402_5%

T H E R M#_VGA
T H E R M _SCI#
A

Close to GPU
D _RED

AD2
AD1

S G @ R 297 1

2 150_0402_1%

D _ G R E EN S G @ R 296 1

2 150_0402_1%

D _ B L UE

S G @ R 295 1

2 150_0402_1%

I 2 C B _SCL
I 2 C B _SDA

S G @ R 319 1
S G @ R 320 1

2 2.2K_0402_5%
2 2.2K_0402_5%

H D C P _ S CL S G @ R 686 1
H D C P _ S D A S G @ R 687 1

2 2.2K_0402_5%
2 2.2K_0402_5%

G P U _ VID0
G P U _ VID1

2 10K_0402_5%
2 10K_0402_5%

D _ C R T _ H S Y N C <22>
D _ C R T _ V S Y N C <22>

AE2
AD3
AE3

D _RED
D _ B L UE
D _ G R E EN

AF1
AE1

D A CA_VREF S G @ C 358 1
D A C A _ R S EF S G @ R 294 1

+ 3 V S_NV

D _ R E D <22>
D _ B L UE <22>
D _ G R E E N <22>

2 0 .1U_0402_16V4Z
2 124_0402_1%

U6
U4
T5
R4
T4

@ R 595 1
@ R 187 1

D _ E D I D _CLK S G @ R 808 1
D _ E D I D _DATA
S G @ R 809 1

R6
V6

AF3
AG4
AE4
AF4
AG3

J T A G_TCK
J T A G_TDI
J T A G_TDO
J T AG_TMS
J T A G_TRST@ R 903 1

T64
T65
T66
T67

S G @ R 688 1

AD25

I 2 C B _SCL
I 2 C B _SDA

A2
B1

D _EDID_CLK
D _EDID_DATA

A3
A4

H DCP_SCL
HD CP_SDA

T1
T2

V G A _SM_CLK
V G A _ SM_DA

D11

0_0402_5% 1
0_0402_5% 1

CRT

D _ E D I D _CLK <22>
D _ E D I D _DATA <22>

LVDS

2 R 325 @
2 R 326 @

HDCP

D _ E D I D _CLK
D _ E D I D _DATA

ACTIVE

USAGE

IN

N/A

HPD-C (used for IFPC)

GPIO1

IN

N/A

2nd DVI Hot-plug

GPIO2

OUT

H

P anel Back-Light PWM

GPIO3

OUT

H

P anel Pow er Enable

GPIO4

OUT

H

Panel Back-Light Enable

GPIO5

OUT

N/A

NVVDD VID0

GPIO6

OUT

N/A

NVVDD VID1

GPIO7

OUT

N/A

NVVDD VID2

GPIO8

IN

L

OVERT

GPIO9

OUT

L

T hermal Alert

GPIO10

OUT

N/A

MEM_VREF

GPIO11

OUT

L

SLI SYNCO

GPIO12

IN

N/A

AC Detect

GPIO13

OUT

L

MEM_VID

X TALOUT
@ R 695 2

X TALIN

1 0_0402_5%

2 7 M_CLK <19>

S G @ Y7
2 7MHZ_18PF_X3S027000FI1H-X
X TALIN

SG@
C 810
20P_0402_50V8

I/O

GPIO0

2 7 M _SSC <19>

2 10K_0402_5%

V G A _SM_CLK S G @ R 315 2
V G A _ SM_DA
S G @ R 316 2

1 0_0402_5%
1 0_0402_5%

N10M-GLM-S-A1_BGA533
SG@

C

GPIO

1 10K_0402_5%

2 7 M_SSC
@ R 692 1

D10

D _ C R T _ D D C_CLK <20>
D _ C R T _ D D C_DATA <20>

H D C P _ S CL <25>
H D C P _ S D A <25>

E9
E10

B

2 10K_0402_5%

R1
T3
R2
R3

2 2.2K_0402_5%
2 2.2K_0402_5%

T P C12
T P C12
T P C12
T P C12
2 10K_0402_5%

@ R 690 2

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

CLK

A

<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>

1
2

3
4

<37> T H E R M _SCI#
X TALOUT

1

1

2

2

T H E R M _SCI#

10K_0402_5% 1

T H E R M#_VGA

10K_0402_5% 2

S M B _ E C_CK2_R <12>
S M B _ E C _DA2_R <12>
+ 3 VS_NV
SG@
2 R 696
SG@
1 R 314

SG@
C 8 11
20P_0402_50V8

D

GPIO14

OUT

H

PS Control

GPIO15

IN

N/A

HPD-E (used for IFPE)

GPIO16

OUT

N/A

FAN PWM Control

GPIO17

N/A

GPIO18

N/A

GPIO19

Issued Date

2008/09/15

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

http://laptop-motherboard-schematic.blogspot.com/
2

3

4

IN

D

N/A

HPD-D (used for IFPD)

Compal Electronics, Inc.

Compal Secret Data

S ecurity Classification

C

Title

PEG Interface
Size
D o c u m ent Number
Custom
D a te:

Rev
0 .1

Calpella DIS LA4743P
Sheet

Monday, April 13, 2009
5

24

of

49

1

2

3

4

5

LVDS Interface
U 8C

H D M I C LK_VGA
H D M I D AT_VGA
H D MI_C_TX2+
H D MI_C_TX2H D MI_C_TX1+
H D MI_C_TX1H D MI_C_TX0+
H D MI_C_TX0H D M I _ C_CLK+
H D M I _ C_CLK-

H D MI_C_TX2+
H D MI_C_TX2H D MI_C_TX1+
H D MI_C_TX1H D MI_C_TX0+
H D MI_C_TX0H D M I _ C_CLK+
H D M I _ C_CLK-

G4
G5
P4
N4
M5
M4
L4
K4
H4
J4
D3
D4
F5
F4
E4
D5
C3
C4
B3
B4

B

F7
G6
D6
C6
A6
A7
B6
B7
E6
E7

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

NC

RFU_1
RFU_2
RFU_3
RFU_4
RFU_5

STRAP

LVDS / TMDS

<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

NC
NC
NC

STRAP0
STRAP1
STRAP2

BUFRST_N

GENERAL

AB3
AB2
W1
V1
W3
W2
AA2
AA3
AB1
AA1

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

THERMDN
THERMDP

CEC
SPDIF

ROM_CS_N

SERIAL

A

AC4
AD4
V5
V4
AA5
AA4
W4
Y4
AB4
AB5

D _ L V D S_ACLK+
D _ L V D S_ACLKD _ L VDS_A0+
D _ L VDS_A0D _ L VDS_A1+
D _ L VDS_A1D _ L VDS_A2+
D _ L VDS_A2-

RFU

P a rt 3 of 5
<22>
<22>
<22>
<22>
<22>
<22>
<22>
<22>

ROM_SCLK
ROM_SI
ROM_SO

IFPAB_RSET
IFPC_RSET
IFPD_RSET
IFPE_RSET

C15
D15
J5

T6
W6
Y6
AA6
N3

A

C7

S T R AP0

B9

S T R AP1

A9

S T R AP2

N5

D8

VG A_THERMDC

D9

VG A_THERMDA

N2
F9

S P D I F _ IN

S G@
R 6 69 1

B10

R O M _ CS#

C9

R O M _ SCLK

A10

R O M _SI

C10

R O M _SO

AB6

IFPAB_RSET R 290
SG@
IFPC_RSET R 302
SG@
I F P D _ R SET R 697
SG@
I F P E _ RSET R 698

R5
M6
F8

2 36K_0402_1%

SG@
R 301 1

2 10K_0402_5%

SPDIF
+ 3 V S_NV
B

1

@

2 1K_0402_1%

1

2 1K_0402_1%

1

2 1K_0402_1%

1

2 1K_0402_1%

N10M-GLM-S-A1_BGA533
S G@

Straps
C

HDCP ROM

FB HW Strap for DDR3: (RAM_CFG @ROM_SI) C
- Hynix 64Mx16: 0000 (R344 pull-down 15K)
- Samsung 64Mx16: 0001 (R344 pull-down 20K)

MULTI LEVEL STRAPS
+ 3 VS_NV

1

S T R AP0
S T R AP1
S T R AP2
R O M _SI
R O M _SO
R O M _ SCLK

SG@
C 388
0 .1U_0402_16V4Z

2

+ 3 VS_NV

U10

1
2
3
4

A0
A1
A2
GND

VCC
WP
SCL
SDA

8
7
6
5

1 R 329

2

4.99K_0402_1%
H DCP_SCL
HD CP_SDA

H D C P _ S CL <24>
H D C P _ S D A <24>

H D C P _ S CL

1

A T 2 4 C 1 6BN-SHBY-B
SG@

@

S G@
1 R 3 30
2
45.3K_0402_1%

2

R 313
@
10K_0402_5%

S G @ 1 R 339
2
35K_0402_1%

@

1 R 3 40

S G @ 1 R 342
2
24.9K_0402_1%

@

1 R 3 43

S G @ 1 R 344
2
15K_0402_1%

@

1 R 3 45

S G @ 1 R 346
2
4.99K_0402_1%

@

1 R 3 47

@

1 R 348

2

4.99K_0402_1%

2

4.99K_0402_1%

2

4.99K_0402_1%

2

4.99K_0402_1%

2

4.99K_0402_1%
S G @ 1 R 3 49
2
4.99K_0402_1%

D

D

Compal Secret Data

S ecurity Classification
Issued Date

2008/09/15

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

http://laptop-motherboard-schematic.blogspot.com/
2

3

4

Title

Compal Electronics, Inc.
N10M(2)_ LVDS&DP&HDCP

Size
D o c u m ent Number
C u s t om
D a te:

Rev
0 .1

Ca lp e lla DI S LA4 743P
Sheet

Monday, April 13, 2009
5

25

of

49

3

32~63 CKE

C M D A28

A

+ V D D _MEM

@ R 745
100_0402_5%

1

@ R 750
100_0402_5%

1

@ R 746
100_0402_5%

0~31 CKE

+ V D D _MEM

2

2

+ V D D _MEM

2

0~31 ODT

+ V D D _MEM

5

@ R 7 49
100_0402_5%

1

32~63 ODT
A

4

2

2

1

1

C M D A30

C M D A18

<28> M D A[31..16]

B

<29> M D A[47..32]

<29> M D A[63..48]

C

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FB_VREF
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_DEBUG

N10M-GLM-S-A1_BGA533
SG@

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
C M D A10
C M D A11
C M D A12
C M D A13
C M D A14
C M D A15
C M D A16
C M D A17
C M D A18
C M D A19
C M D A20
C M D A21
C M D A22
C M D A23
C M D A24
C M D A25
C M D A26
C M D A27
C M D A28
C M D A29
C M D A30

C26
B19
D19
D23
T24
AA23
AB27
T26

D Q M A0
D Q M A1
D Q M A2
D Q M A3
D Q M A4
D Q M A5
D Q M A6
D Q M A7

D25
A18
E18
B24
R22
Y24
AA27
R27

D Q S A#0
D Q S A#1
D Q S A#2
D Q S A#3
D Q S A#4
D Q S A#5
D Q S A#6
D Q S A#7

C25
A19
E19
A24
T22
AA24
AA26
T27

D Q S A0
D Q S A1
D Q S A2
D Q S A3
D Q S A4
D Q S A5
D Q S A6
D Q S A7

A16

FB_ VREF

C M D A [30..0] <28,29>

1

1

1

B

D Q M A [3..0] <28>

D Q M A [7..4] <29>

D Q S A #[3..0] <28>

D Q S A #[7..4] <29>

D Q S A [3..0] <28>

D Q S A [7..4] <29>

C

W=15mils

F24
F23

C L KA0 <28>
C L KA0# <28>

N24
N23
M22

SG@
R 751
10K_0402_5%

C L KA1 <29>
C L KA1# <29>
ODT
+ V D D _MEM
ODT

SG@
R12 1

2 10K_0402_5%

1

+ V D D _MEM

F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22
J22
L22

S G@
R 7 47
10K_0402_5%

2

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

SG@
R 752
10K_0402_5%

2

D22
E24
E22
D24
D26
D27
C27
B27
A21
B21
C21
C19
C18
D18
B18
C16
E21
F21
D20
F20
D17
F18
D16
E16
A22
C24
D21
B22
C22
A25
B25
A26
U24
V24
V23
R24
T23
R23
P24
P22
AC24
AB23
AB24
W24
AA22
W23
W22
V22
AA25
W27
W26
W25
AB25
AB26
AD26
AD27
V25
R25
V26
V27
R26
T25
N25
N26

2

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
M D A10
M D A11
M D A12
M D A13
M D A14
M D A15
M D A16
M D A17
M D A18
M D A19
M D A20
M D A21
M D A22
M D A23
M D A24
M D A25
M D A26
M D A27
M D A28
M D A29
M D A30
M D A31
M D A32
M D A33
M D A34
M D A35
M D A36
M D A37
M D A38
M D A39
M D A40
M D A41
M D A42
M D A43
M D A44
M D A45
M D A46
M D A47
M D A48
M D A49
M D A50
M D A51
M D A52
M D A53
M D A54
M D A55
M D A56
M D A57
M D A58
M D A59
M D A60
M D A61
M D A62
M D A63

MEMORY INTERFACE

P a rt 2 of 5

<28> M D A[15..0]

SG@
R 7 48
10K_0402_5%

2

1

CMDA7
U8B

Rt

2

@ R 699
1K_0402_1%

1
2

@ R 701
1K_0402_1%

D

Rb

@

1

2

0 .1U_0402_16V4Z

FB_ VREF

C 813

D

Close to U8

Compal Secret Data

S ecurity Classification
Issued Date

2008/09/15

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

http://laptop-motherboard-schematic.blogspot.com/
2

3

4

Title

Compal Electronics, Inc.
N10M(3)_VGA RAM Interface

Size
D o c u m ent Number
C u s t om
D a te:

Rev
0 .1

Ca lp e lla DI S LA4 743P
Sheet

Monday, April 13, 2009
5

26

of

49

1

2

3

4

5

VGA Pow er sequence: +.3VS->+NVVDD->+VDD_MEM

U 8E

SG@

10U_0805_6.3V6M

POWER

4.7U_0603_6.3V6K

C 829

0.01U_0402_16V7K

S G@
+ P C IE

Layout Note:Please
colse to Ball.

600 mA

SG@

2

SG@

C 857

SG@

2

1

1

2

SG@

10U_0805_6.3V6M

S G@

2

1

C 856

G P U _ P LLVDD

2

1

4.7U_0603_6.3V6K

2
P E X _ PLLDVDD

1

C 855

1

1 U_0603_10V4Z

FB_CAL_PU_GND

S G@
0_0402_5%
0_0402_5%

U2
U5
U11
U12
U13
U14
U15
U16
U17
U23
U26
V9
V19
W11
W14
W17
Y2
Y5
Y23
Y26
AC2
AC5
AC6
AC8
AC11
AC14
AC17
AC20
AC23
AC26
AF2
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
T16
T15
T14
F6

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

FB_CAL_TERM_GND

1

2 R 7 04

W16

1

S G@
2 R 7 06

E14

S G@

GND_SENSE MULTI_STRAP_REF1_GND
GND_SENSE MULTI_STRAP_REF0_GND

A15 S G @ R 742 1

2 40.2_0402_1%

B16 S G @ R 743 1

2 60.4_0402_1%

F11 S G @ R 705 1

2 40.2K_0402_1%

F10 S G @ R 707 1

2 40.2K_0402_1%

R19

+ 3 V S_NV

F B _ P L L AVDD

120mA DACB_VDD

SG@
R 708 1

P E X _SVDD_3V3

AC19
T19

C 8 62

DACA_VDD

AG2

DACA_VDD

W5

D A C B _ V D D S G @ R 7 09 1

2 10K_0402_5%

B15

S G @ R 7 10 1

2 40.2_0402_1%

W15

S G @ R 7 44 1

2 0_0402_5%

E15

S G @ R 7 11 1

2 0_0402_5%

1

SG@ 2

IFPAB_PLLVDD
IFPC_PLLVDD

FB_CAL_PD_VDDQ

IFPD_PLLVDD

VDD_SENSE

IFPE_PLLVDD

VDD_SENSE

B

K5

IFPC_IOVDD
IFPDE_IOVDD

A

N10M-GLM-S-A1_BGA533
SG@

S P _ P LLVDD

L6

P a rt 5 of 5

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

2 0_0402_5%

0 .1U_0402_16V4Z

D7

2

SG@

C 854

I F P E _ P LLVDD

1

1 U_0603_10V4Z

2 10K_0402_5%

C 8 44

N6

1

2

S G@

4.7U_0603_6.3V6K

I F P D _ P L LVDD

C 828

2 10K_0402_5%

0.01U_0402_16V7K

P6

2

SG@

C 853

AD5

IF PC_PLLVDD

2

SG@

1

0 .1U_0402_16V4Z

I FPAB_PLLVDD

FB_DLLAVDD

1

2

SG@

C 8 43

H6

IFPB_IOVDD

1

1 U_0603_10V4Z

J6

I F P D E _ I O VDD

FB_PLLAVDD

C 827

IF P C_IOVDD

FB_PLLAVDD
IFPA_IOVDD

0.01U_0402_16V7K

V2

2

C 852

V3

I F P B _ I OVDD

PLLVDD

SG@

1

0 .1U_0402_16V4Z

2 10K_0402_5%

IF P A_IOVDD

PEX_SVDD_3V3

1

2

SG@

C 8 42

AG9

K6

2

S G@

AG7
AF7
AE7
AD8
AD7
AC9
AF9

C 826

P E X _SVDD_3V3

SG@

150mA

SG@
R76 1
SG@
R79 1

VID_PLLVDD
SP_PLLVDD

150mA
SG@
R71 1

PEX_PLLVDD

2

1

C 8 41

2

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

1

2

SG@

1 U_0603_10V4Z

S G@

1

A12
B12
C12
D12
E12
F12

1

C 8 40

SG@

2

C 861

SG@

1

0 .1U_0402_16V4Z

2

C 860

1

0 .1U_0402_16V4Z

V D D 33
C 859

C 858

2

1 U_0603_10V4Z

1

2 0_0603_5%

1 U_0402_6.3V4Z

B

150mA

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

SG@

0 .1U_0402_16V4Z

+ 3 VS_NV
SG@
R 703 1

B2
B5
B8
B11
B14
B17
B20
B23
B26
E2
E5
E8
E11
E17
E20
E23
E26
H2
H5
J11
J14
J17
K9
K19
L2
L5
L11
L12
L13
L14
L15
L16
L17
M12
M13
M14
M15
M16
P2
P5
P9
P19
P23
P26
T12
T13

+ P C IE

AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7

C 8 39

SG@

1.8A

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

0 .1U_0402_16V4Z

1

2

SG@

SG@

C 824

2

SG@

C 850

2

S G@

1

1 U_0402_6.3V4Z

1

C 838

SG@

C 849

2

SG@

2

1 U_0402_6.3V4Z

C 848

1

1

0.022U_0402_16V7K

S G@

4.7U_0603_6.3V6K

C 847

2

10U_0805_6.3V6M

1

2

C 837

SG@

1

0.022U_0402_16V7K

2

C 836

SG@

1

0.022U_0402_16V7K

2

C 835

SG@

1

0.022U_0402_16V7K

2

C 834

SG@

1

0.022U_0402_16V7K

2

C 833

1

0.022U_0402_16V7K

0.022U_0402_16V7K

2

C 832

C 831

1

0.022U_0402_16V7K

0.022u X 9
0.01u X 3
0.1u X 8
4.7u X 1
1u(0402) X 1
1u(0603) X 1
10u(0805) X 3

3.4A

S G@

0.047U_0402_16V7K

A

C 823

SG@

A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22

0.047U_0402_16V7K

2

SG@

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

C 822

1

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

0.047U_0402_16V7K

2

SG@

C 821

1

0 .1U_0402_16V4Z

C 820

2

S G@

0 .1U_0402_16V4Z

C 819

2

SG@

1

+ V D D _MEM
P a rt 4 of 5

0 .1U_0402_16V4Z

C 818

2

SG@

1

0 .1U_0402_16V4Z

C 817

2

SG@

1

0 .1U_0402_16V4Z

2

SG@

1

0 .1U_0402_16V4Z

1

C 816

0 .1U_0402_16V4Z

C 815

C 814

2

0 .1U_0402_16V4Z

1

U 8D

J9
J10
J12
J13
L9
M9
M11
M17
N9
N11
N12
N13
N14
N15
N16
N17
N19
P11
P12
P13
P14
P15
P16
P17
R9
R11
R12
R13
R14
R15
R16
R17
T9
T11
T17
U9
U19
W9
W10
W12
W13
W18
W19

GND

+NVVDD

11.44A

+ V D D _MEM

+ N V V D D _ S ENSE

to Pow er

N10M-GLM-S-A1_BGA533
SG@

+ P C IE

SG@
L33

10mA
F B _ P L L AVDD

1

2

B LM18PG181SN1D_0603

85mA

2

1

SG@
L44

1

100mA

2

1

2

SG@

SG@

S G@

1

2

C 8 98

2

1

2

SG@

D

SG@

Layout Note:Please
colse to BGA.

1

2

2
1 U_0402_6.3V4Z

SG@

1

C 9 64

2

+ P C IE

SG@
L40

1

1 0 N H_MLG1608B10NJT_5%

1 U_0402_6.3V4Z

SG@

1

C 8 93

SG@

2

0 .1U_0402_16V4Z

C 882

C 881

0 .1U_0402_16V4Z

2

SG@

1 U_0402_6.3V4Z

S G@

1

C 8 97

SG@

2

1 U_0402_6.3V4Z

Layout Note:Please
colse to Ball.

1

C 8 96

2

4.7U_0603_6.3V6M

1

C 8 95

2

1 U_0402_6.3V4Z

SG@

1

C 8 94

2

C 888
470P_0402_50V8J
SG@

Compal Secret Data

S ecurity Classification
Issued Date

SG@

2008/09/15

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

1

110mA
0 .1U_0402_16V4Z

2

SG@

1

C 9 63

SG@

C 887

2

1

0.1U_0402_10V6K

C 901

2

SG@

1

0.1U_0402_10V6K

C 900

S G@

1

4700P_0402_25V7K

C 899

2

SG@

1 U_0402_6.3V4Z

C 958

4.7U_0603_6.3V6K

2

1

2

1

PEX_PLLDVDD

0.1U_0402_10V6K

SG@

1

C 9 05

2

IF P C_IOVDD
0.1U_0402_10V6K

DACA_VDD

1

1U_0603_10V6K

1

C 9 03

SG@

B LM18PG181SN1D_0603

1

2
SG@

1 U_0402_6.3V4Z

150mA

2

C 9 04
4.7U_0603_6.3V6K

120mA

2

SG@
L42

1

B LM18PG181SN1D_0603

SG@ 2

SG@
L41

2
SG@

2

B LM18PG181SN1D_0603

1

C 880

+ P C IE

C 9 02

SG@

1
4.7U_0603_6.3V6K

2

+ P C IE

S G@
L 37

135mA
C 879

SG@

1

1 U_0402_6.3V4Z

2

G P U _ P LLVDD

2

S G@

4.7U_0603_6.3V6K

SG@

C 962

2

1

0.1U_0402_10V6K

S G@

C 961

2

1

0.1U_0402_10V6K

1

C 886

D

1

0.1U_0402_10V6K

C 885

2

SG@

+ 3 VS_NV

1

SG@

B LM18PG181SN1D_0603

1

C 960

SG@

1
4.7U_0603_6.3V6K

SG@

2

100mA

IF PC_PLLVDD
1U_0603_10V6K

C 884

2

4.7U_0603_6.3V6K

C 883

4.7U_0603_6.3V6K

SG@ 2

1

C

Layout Note:Please
colse to BGA.

+ P C IE

S G@
L 46
S P _ P LLVDD
C 1061

2

1

B L M18PG181SN1D_0603

1

2

SG@

4.7U_0603_6.3V6K

70mA

2

1

C 8 91
0.1U_0402_10V6K

2

SG@
S G@
L 38

1

1

C 8 78

C 8 77

C 8 76

1

2
+ 3 VS_NV

IF P A_IOVDD

1

B L M18PG181SN1D_0603
0.1U_0402_10V6K

2

+ 1 .8VS_NV

1U_0603_10V6K

2

@

C 9 59

S G@

1

1

2

I F P B _ I OVDD

0.1U_0402_10V6K

2

@

C 9 52

1

0.1U_0402_10V6K

SG@

C 8 71

2

@

4700P_0402_25V7K

C 8 70

2

1

1U_0603_10V6K

C 8 69

SG@ 2

1

4.7U_0603_6.3V6K

C 8 68

1

4.7U_0603_6.3V6K

B L M18PG181SN1D_0603

I FPAB_PLLVDD

1 U_0402_6.3V4Z

SG@
L34

1

C 867

C 866

+ P C IE

4.7U_0603_6.3V6K

C

http://laptop-motherboard-schematic.blogspot.com/
2

3

4

Title

Compal Electronics, Inc.
N10M(4)_Power/GND

Size
D o c u m ent Number
C u s t om Ca lp e lla DI S
D a te:

Rev
0 .1

LA4 743P
Sheet

Monday, April 13, 2009
5

27

of

49

1

2

VRAM DDR3 chips (512MB)

C M D A19
C M D A25
C M D A22
C M D A24
CMDA0
CMDA2
C M D A21
C M D A16
C M D A23
C M D A20
C M D A17
CMDA9
C M D A14
C M D A26

D Q M A[7..0]

<26,29> D Q M A[7..0]

M D A [63..0]

<26,29> M D A[63..0]

C M D A [30..0]

<26,29> C M D A [30..0]

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

C M D A12
CMDA3
C M D A27

M3
N9
M4

C L KA0
C L KA0#
C M D A18

J8
K8
K10

C M D A30
C M D A29
CMDA1
C M D A10
C M D A11
B

K2
L3
J4
K4
L4

D Q S A2
D Q S A1

F4
C8

D Q M A2
D Q M A1

E8
D4

D Q S A#2
D Q S A#1

L9

2

J2
L2
J10
L10
A1
A11
T1
T11

SG@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D8
C4
C9
C3
A8
A3
B9
A4

MDA8
M D A14
M D A10
M D A12
M D A11
M D A13
MDA9
M D A15

M E M _ V REF1

M9
H2

C M D A19
C M D A25
C M D A22
C M D A24
CMDA0
CMDA2
C M D A21
C M D A16
C M D A23
C M D A20
C M D A17
CMDA9
C M D A14
C M D A26

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

+ V D D _MEM

BA0
BA1
BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE 310mA
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
NC
NC
NC
NC

J8
K8
K10

VREFCA
VREFDQ

ODT/ODT0
CS
RAS
CAS
WE 310mA
DQSL
DQSU

C M D A15

T3

ZQ 1

L9

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A11
T1
T11

100-BALL
S D R A M D DR3
K 4 B 1 G 1646D-HCF8_FBGA100
VRAM@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

J2
L2
J10
L10

S G@

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DML
DMU

G4
B8

E4
F8
F3
F9
H4
H9
G3
H8

MDA5
MDA1
MDA6
MDA2
MDA4
MDA0
MDA7
MDA3

D8
C4
C9
C3
A8
A3
B9
A4

M D A26
M D A30
M D A28
M D A29
M D A27
M D A25
M D A24
M D A31

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

0..31

CMD0

A4

CMD1

RAS#

CMD2

A5

CMD3

BA1

32..63
RAS#
BA1

CMD4

A2

CMD5

A4

CMD6

A3

CMD7

CKE

A

CMD8

+ V D D _MEM

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

E8
D4

D Q S A#0
D Q S A#3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

F4
C8

D Q M A0
D Q M A3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

K2
L3
J4
K4
L4

D Q S A0
D Q S A3

B2
B10
D2
D9
E3
E9
F10
G2
G10

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

C L KA0
C L KA0#
C M D A18

C M D A30
C M D A29
CMDA1
C M D A10
C M D A11

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M3
N9
M4

+ V D D _MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

C M D A12
CMDA3
C M D A27

243_0402_1%

1

ZQ 0

VREFCA
VREFDQ

M D A21
M D A18
M D A23
M D A16
M D A20
M D A19
M D A22
M D A17

R 7 16

2

T3

243_0402_1%

SG@

C M D A15

R 7 15

R 7 14

10K_0402_5%

1

<26,29> C M D A 15

G4
B8

U12

E4
F8
F3
F9
H4
H9
G3
H8

1

<26,29> D Q S A#[7..0]

DATA Bus

2

H2

D Q S A [7..0]
D Q S A#[7..0]

5

Address

U 11
M E M _ V REF0 M9

<26,29> D Q S A[7..0]

4

Hynix : H5TQ1G63BFR-12C-->SA000032400
Sam sung : K4W1G1646E-HC12-->SA000035700

64Mx16 DDR3 700MHz*4==>512MB
Low 32 bit FB

A

3

CS#

CMD9

A11

CMD10

CAS#

CAS#

CMD11

WE#

WE#

CMD12

BA0

BA0

CMD14

A12

A12

CMD15

RST

RST

CMD16

A7

A7

CMD17

A10

A10

CMD18

CKE

CMD19

A0

A0

CMD20

A9

A9

CMD21

A6

A6

CMD22

A2

CMD23

A8

CMD24

A3

CMD25

A1

A1

CMD26

A13

A13

CMD27

BA2

A11

CMD13

B3
D10
G8
K3
K9
N2
N10
R2
R10

+ V D D _MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

A5

B

A8

BA2

CMD28
CMD29

ODT
CS#

CMD30
B2
B10
D2
D9
E3
E9
F10
G2
G10

LOW

HIGH

100-BALL
S D R A M D DR3
K 4 B 1 G 1 646D-HCF8_FBGA100
VRAM@
+ V D D _MEM

C L K A0

1

1

<26>

C L KA0
SG@
R 718
121_0402_1%

M E M _ V REF1

1

C 9 08
0.01U_0402_16V7K

1 SG@

C 907
0.01U_0402_16V7K

2

2

2

SG@
R 722
121_0402_1%

2

1

1

SG@

1 S G@

2

SG@
R 720
1K_0402_1%

2

0.01U_0402_16V7K C 906

M E M _ V REF0
SG@
R 7 21
1K_0402_1%

1

2

2

SG@
R 7 19
1K_0402_1%

C

SG@
R 717
1K_0402_1%

2

+ V D D _MEM

1

C

<26>

C L KA0#

C L KA0#

DDR3 BGA MEMORY

+ V D D _MEM

2

SG@

C 918

SG@

1

1

2

0.1U_0402_16V7K

SG@

2

C 917

S G@

1

0.1U_0402_16V7K

2

C 916

1

0.1U_0402_16V7K

2

C 915

SG@

1

0.1U_0402_16V7K

2

C 914

SG@

1

0.1U_0402_16V7K

2

C 913

SG@

1

0.1U_0402_16V7K

2

C 912

SG@

1

1U_0402_6.3V6K

2

C 911

S G@

1

1U_0402_6.3V6K

2

C 910

1

1U_0402_6.3V6K

2

C 909

SG@

C 928

SG@

2

1

0.1U_0402_16V7K

S G@

C 927

2

1

0.1U_0402_16V7K

C 926

2

1

0.1U_0402_16V7K

SG@

C 925

2

1

0.1U_0402_16V7K

SG@

C 924

2

1

0.1U_0402_16V7K

SG@

C 923

2

1

0.1U_0402_16V7K

SG@

C 922

2

1

1U_0402_6.3V6K

S G@

C 921

2

1

1U_0402_6.3V6K

C 920

SG@

1

1U_0402_6.3V6K

C 919

2

1U_0402_6.3V6K

D

1

1U_0402_6.3V6K

DDR3 BGA MEMORY

+ V D D _MEM

SG@

Compal Secret Data

S ecurity Classification
Issued Date

2008/09/15

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

http://laptop-motherboard-schematic.blogspot.com/
2

D

SG@

3

4

Title

Compal Electronics, Inc.
VRAM DDR3

Size

D o c u m ent Number

Rev
0.1

LA-4901P
D a te:

Sheet

Monday, April 13, 2009
5

28

of

49

1

2

3

VRAM DDR3 chips (512MB)

4

D Q S A [7..0]

<26,28> D Q S A[7..0]

64Mx16 DDR3 700MHz*4==>512MB
High 32 bit FB

D Q S A#[7..0]

<26,28> D Q S A#[7..0]

D Q M A[7..0]

<26,28> D Q M A[7..0]

M D A [63..0]

<26,28> M D A [63..0]
U 13
M E M _ V REF2

M9
H2

C M D A19
C M D A25
CMDA4
CMDA6
CMDA5
C M D A13
C M D A21
C M D A16
C M D A23
C M D A20
C M D A17
CMDA9
C M D A14
C M D A26

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

C M D A12
CMDA3
C M D A27

M3
N9
M4

C L KA1
C L KA1#
CMDA7

J8
K8
K10

C M D A7

<26>

C M D A28

K2
L3
J4
K4
L4

D Q S A4
D Q S A7

F4
C8

D Q M A4
D Q M A7

E8
D4

D Q S A#4
D Q S A#7

G4
B8

C M D A15

T3

ZQ 2

L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M D A39
M D A36
M D A37
M D A34
M D A38
M D A33
M D A35
M D A32

D8
C4
C9
C3
A8
A3
B9
A4

M D A61
M D A60
M D A59
M D A62
M D A58
M D A63
M D A57
M D A56

U 14
M E M _ V REF3

M9
H2

C M D A19
C M D A25
CMDA4
CMDA6
CMDA5
C M D A13
C M D A21
C M D A16
C M D A23
C M D A20
C M D A17
CMDA9
C M D A14
C M D A26

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

C M D A12
CMDA3
C M D A27

M3
N9
M4

C L KA1
C L KA1#
CMDA7

J8
K8
K10

A2
A9
C2
C10
D3
E10
F2
H3
H10

C M D A28
CMDA8
CMDA1
C M D A10
C M D A11

K2
L3
J4
K4
L4

D Q S A5
D Q S A6

F4
C8

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

D Q M A5
D Q M A6

E8
D4

D Q S A#5
D Q S A#6

G4
B8

+ V D D _MEM

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE 310mA
DQSL
DQSU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B3
D10
G8
K3
K9
N2
N10
R2
R10

+ V D D _MEM

1

B

C M D A28
CMDA8
CMDA1
C M D A10
C M D A11

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E4
F8
F3
F9
H4
H9
G3
H8

T3

ZQ 3

L9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E4
F8
F3
F9
H4
H9
G3
H8

M D A41
M D A46
M D A40
M D A45
M D A42
M D A47
M D A44
M D A43

D8
C4
C9
C3
A8
A3
B9
A4

M D A48
M D A53
M D A50
M D A52
M D A51
M D A54
M D A49
M D A55

A

+ V D D _MEM

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE 310mA
DQSL
DQSU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B3
D10
G8
K3
K9
N2
N10
R2
R10

+ V D D _MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

B

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10

J2
L2
J10
L10

R 726
243_0402_1%

A1
A11
T1
T11

S G@

100-BALL
S D R A M D DR3
K 4 B 1 G 1646D-HCF8_FBGA100
VRAM@

1

+ V D D _MEM

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10
+ V D D _MEM

SG@
R 727
121_0402_1%

SG@
R 728
1K_0402_1%

2

S G@
R 729
1K_0402_1%

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

100-BALL
S D R A M D DR3
K 4 B 1 G 1646D-HCF8_FBGA100
VRAM@

C L KA1

C L K A1

1

<26>

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2 0.01U_0402_16V7K

1

1

1

M E M _ V REF2
S G@
R 732
1K_0402_1%

1 SG@

SG@
R 730
1K_0402_1%

SG@
R 731
121_0402_1%

1 SG@

C 930
0.01U_0402_16V7K

2

2

2

C 931
0.01U_0402_16V7K

2

C

M E M _ V REF3

2

S G@
C 9 29 1

2

2

A1
A11
T1
T11

SG@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

J2
L2
J10
L10

R 7 25
243_0402_1%

C

C M D A15

VREFCA
VREFDQ

1

<26>

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

A

C M D A [30..0]

<26,28> C M D A [30..0]

VREFCA
VREFDQ

5

<26>

2

DDR3 BGA MEMORY

+ V D D _MEM

2

SG@

C 9 51

S G@

1

1

2

0.1U_0402_16V7K

2

C 9 50

SG@

1

0.1U_0402_16V7K

2

C 9 49

SG@

1

0.1U_0402_16V7K

2

C 9 48

SG@

1

0.1U_0402_16V7K

2

C 9 47

SG@

1

0.1U_0402_16V7K

2

C 9 46

S G@

1

0.1U_0402_16V7K

2

C 9 45

SG@

1

1U_0402_6.3V6K

SG@

2

C 9 44

SG@

1

1U_0402_6.3V6K

2

C 9 43

1

1U_0402_6.3V6K

2

C 9 42

SG@

1

1U_0402_6.3V6K

2

C 9 41

SG@

1

0.1U_0402_16V7K

S G@

2

C 9 40

SG@

1

DDR3 BGA MEMORY

+ V D D _MEM

0.1U_0402_16V7K

2

C 9 39

1

0.1U_0402_16V7K

2

C 9 38

SG@

1

0.1U_0402_16V7K

2

C 9 37

SG@

1

0.1U_0402_16V7K

2

C 9 36

SG@

1

0.1U_0402_16V7K

2

C 9 35

1

1U_0402_6.3V6K

S G@

C 9 34

2

1U_0402_6.3V6K

C 9 33

SG@

1

1U_0402_6.3V6K

C 9 32

2

1U_0402_6.3V6K

1

C L KA1#

C L K A1#

SG@

D

D

Compal Secret Data

S ecurity Classification
Issued Date

2008/09/15

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

http://laptop-motherboard-schematic.blogspot.com/
2

3

4

Title

Compal Electronics, Inc.
VRAM DDR3

Size

D o c u m ent Number

Rev
0.1

Cartier DIS
D a te:

Sheet

Monday, April 13, 2009
5

29

of

49

5

4

3

2

1

D

D

HDD Connector
J H DD

SATA_RXN0_C <11>
SATA_RXP0_C <11>

+3VS

+3VS_ACL

Near CONN side.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS_ACL_IO

D10

+3VS

2

1

1

R364
0_0603_5%
2

2

1

2

CH751H-40PT_SOD323-2

Pleace near HDD CONN (JP3)

1

2

1

2

1

2

1

2

C

SMB_CLK_S3
U15

VDDIO absolute man
rating is VDD+0.1
1

+3VS_ACL_IO
R366
0_0402_5%
1
2

2
3
4

CD-ROM Connector

5
6

+3VS_ACL

Vdd_IO

0011101b

SDA / SDI / SDO

GND

SDO

Reserved

GND

GND

INT 2

Vdd

INT 1

13

SMB_DATA_S3

12

R367
0_0402_5%
1
2

11

Reserved

GND

SMB_DATA_S3 <12,17,18,19>

10
9
8

A CCEL_INT <14>

CS

J O DD

SMB_CLK_S3 <12,17,18,19>

14

+5VS

SCL / SPC

+5VS

OCTEK_SAT-22EH1G_RV
C ONN@

7

SATA_TXP4
SATA_TXN4
C473 2
C474 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_RXN4_C
SATA_RXP4_C

SATA_RXN4_C <11>
SATA_RXP4_C <11>
+5VS

Near CONN side.
6
5
4
3
2
1

R368 2

+5VS
1

2
SUYIN_127382FR013GX09ZR
C ONN@

1

2

1

2

1

2

1
10K_0402_5%

M ust be placed in the center of the system.

Placea caps. near ODD CONN.

C478
10U_0805_10V4Z

SATA_RXN4
SATA_RXP4

SATA_TXP4 <11>
SATA_TXN4 <11>

C477
10U_0805_10V4Z

DP
V5
V5
MD
GND
GND

LIS302DLTR_LGA14_3x5

13
12
11
10
9
8
7

C476
1U_0603_10V4Z

GND
A+
AGND
BB+
GND

C475
0.1U_0402_16V4Z

B

1

C469
10U_0805_6.3V6M

SATA_RXN0_C
SATA_RXP0_C

C468
0.1U_0402_16V4Z

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

C465
0.1U_0402_16V4Z

GND
GND

SATA_RXN0 C466 2
SATA_RXP0 C467 2

+3VS_ACL

ACCELEROMETER (ST)

SATA_TXP0 <11>
SATA_TXN0 <11>

C464
0.1U_0402_16V4Z

24
23

SATA_TXP0
SATA_TXN0

C463
0.1U_0402_16V4Z

C

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

1
2
3
4
5
6
7

C462
10U_0805_10V4Z

GND
A+
AGND
BB+
GND

B

02/12 Change SM bus to VS

Z ZZ1

PCB-MB

A

A

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title

Size Do c ument Number
Cu s tom C alpella DI S

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.
HDD & CDROM

Da te:

Rev
0.1

LA4743P
Sheet

Monday, April 13, 2009
1

30

of

49

A

B

C516

C517

1

C518
2

2

2

2

2

1

2

0.1U_0402_16V4Z

1

2

C513
0.1U_0402_16V4Z

C515

1

1

2

2

1

+1.5VS

PLT_RST#
<14> CLK_DEBUG_PORT_1
R399 1
R401 1

D

G

2

2

2

C511
4.7U_0805_10V4Z

S

1
2
0_1206_5%

@ Q16
SI2301BDS_SOT23

C510
0.1U_0402_16V4Z

1

+3VS
R410
1

2 0_0402_5%
2 0_0402_5%

P CIE_C_RXN2
PCIE_C_RXP2

+3VS_WLAN

@ R409
1
2
0_0603_5%

3

A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
A37
A39
A41
A43
A45
A47
A49
A51

CL K_PCIE_MCARD2#
CL K_PCIE_MCARD2

<12> CLK_PCIE_WLAN#
<12> CLK_PCIE_WLAN

R389

+3VALW

IC H_PCIE_WAKE#
C H_DATA
CH_ CLK

<35> CH_DATA
<35> CH_ CLK
<12> CL KREQ_WLAN#

0_0805_5%

<12> P CIE_RXN2
<12> PCIE_RXP2
+ 3VS_WWAN

1

2

2 47P_0402_50V8J

J M INIA
R388

C512
0.01U_0402_16V7K

0.1U_0402_16V4Z

1

1
1

E

@ C977 1

+1.5VS_WLAN

C509
0.1U_0402_16V4Z

+3VALW

1

D

Mini Card Solt--WLAN/WWAN

+ 3VS_WWAN
0.01U_0402_16V7K 4.7U_0805_10V4Z

C514
4.7U_0805_10V4Z

+3VALW

C

1

<12>
<12>

+3VS

PCIE_TXN2
PCIE_TXP2

PCIE_TXN2
PCIE_TXP2

0_0805_5%
+3VS_WLAN

<37> W W A N_POWER_OFF

WAKE#
COEX1
COEX2
CLKREQ#
GND
REFCLKREFCLK+
GND
Reserved
Reserved
GND
PERn0
PERp0
GND
GND
PETn0
PETp0
GND
GND
+3.3Vaux
+3.3Vaux
GND
Reserved
Reserved
Reserved
Reserved

A53

+3.3Vaux

GND
+1.5V
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

GND

W_DISABLE#
PERST#
+3.3Vaux

GND
+1.5V
SMB_CLK
SMB_DATA

GND

USB_DUSB_D+

GND
LED_WWAN#
LED_WLAN#
LED_WPAN#
+1.5V

GND

+3.3Vaux

GND

GND

A2

+3VS_WLAN

A6
A8
A10
A12
A14
A16
A20
A22
A24

+1.5VS_WLAN
LPC_FRAME# <11,36,37>
L PC_AD3 <11,36,37>
L PC_AD2 <11,36,37>
L PC_AD1 <11,36,37>
L PC_AD0 <11,36,37>
XMIT_OFF#
PLT_RST#
@ R400 1
R402 1

A28
A30
A32

D13

2
1
CH751H-40_SC76
2 0_0805_5%
+3VALW
2 0_0805_5%
+3VS_WLAN
+1.5VS_WLAN

SMBCLK
SMBDATA

A36
A38

1

XMIT_OFF <14>

USB20_N5 <14>
USB20_P5 <14>

A42
A44
A46
A48

W L_LED# <38>
+1.5VS_WLAN

A52

+3VS_WLAN
2

A54

QUASA_CA0416-092N21
C ONN@

1

@ C978
47P_0402_50V8J
@ C979 1

2 47P_0402_50V8J

J M INIB
IC H_PCIE_WAKE#
C H_DATA
CH_ CLK

B1
B3
B5
B7

<12> CL K REQ_WWAN#

2

@ R406
1
2 UIM_DATA
47K_0402_5%

UIM _PWR
UIM _PWR
UIM_DATA
UI M_CLK
U IM_RST
UIM_VPP

6
5
4
3
2
1

6 G2
5 G1
4
3
2
1

8
7

UI M_CLK
1

C519 @
18P_0402_50V8J

2
UIM _ PWR_R
U IM_DATA_R
UI M_CLK_R
U IM_RST_R
UIM_VPP_R

ACES_87212-06G0
C ONN@

REFCLKREFCLK+

GND

B17
B19

For PR

J SIM

UIM _ PWR_R
U IM_DATA_R
UI M_CLK_R
U IM_RST_R
UIM_VPP_R

WL_LED#
1
P R@ R758

W W _ LED#_R
2
0_0402_5%

XMIT_OFF# 1
P R@ R759

M_WXMIT_OFF#
2
0_0402_5%

R760
R761
R762
R763
R764
R765
R766
R767
R768
R769

1
1
1
1
1

2
2
2
2
2

1
1
1
1
1

2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

<12> PCIE_RXN1
<12> PCIE_RXP1

<12>
<12>

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

P R@
P R@
P R@
P R@
P R@

UIM _PWR
UIM_DATA
UI M_CLK
U IM_RST
UIM_VPP

PA@
PA@
PA@
PA@
PA@

R395 1
1
R397
PCIE_TXN1
PCIE_TXP1
+3VS_WWAN

0_0402_5%
2 P CIE_C_RXN1
2 PCIE_C_RXP1
0_0402_5%

R403
1
1
R404

Reserved
Reserved

GND

B23
B25

PCIE_TXN1
PCIE_TXP1

PERn0
PERp0

GND
GND

B31
B33

0_0603_5%
2
2
0_0603_5%

+3.3Vaux
GND
+1.5V
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
GND
W_DISABLE#
PERST#
+3.3Vaux
GND
+1.5V
SMB_CLK
SMB_DATA
GND
USB_DUSB_D+
GND
LED_WWAN#
LED_WLAN#
LED_WPAN#
+1.5V
GND
+3.3Vaux

GND

B11
B13

<12> CL K_PCIE_WWAN#
<12> CL K _PCIE_WWAN

SIM card Connector

WAKE#
COEX1
COEX1
CLKREQ#

PETn0
PETp0

GND

B37
B39
B41
B43
B45
B47
B49
B51

GND
+3.3Vaux
+3.3Vaux
GND
Reserved
Reserved
Reserved
Reserved

<14> USB20_N9
<14> USB20_P9

EXP_CPPE#

+1.5VS
U19
12
14

+3VS

C523 1

2 0.1U_0402_16V4Z

C524 1

2 0.1U_0402_16V4Z

2
4
17

+3VALW
<6,14,32> PLT_RST#
<37,38,39,48> S Y S ON
<37,39,41,44,45> SUSP#
+3VALW

PLT_RST#

6

S Y SON

20

SUSP#

1

@ R414 1

2 100K_0402_5%

10

EXP_CPPE#

9
18

1.5Vin
1.5Vin

1.5Vout
1.5Vout

3.3Vin
3.3Vin

3.3Vout
3.3Vout

AUX_IN
SYSRST#
SHDN#

AUX_OUT
OC#
PERST#

STBY#

NC

CPPE#

GND

11
13

+1.5VS_PEC

3
5

+3VS_PEC

<13,32> ICH_PCIE_WAKE#

R413 1

0_0402_5%

2

+3V_PEC

PCIE_PME#_R
PERST#

+3VS_PEC

15

+3V_PEC
<12> CLKREQ_EXP#

19
8

SMBCLK
SMBDATA

<12>
SMBCLK
<12> SMBDATA
+1.5VS_PEC

EXP_CPPE#

<12> CLK_PCIE_EXP#
<12> CLK_PCIE_EXP

PERST#

16

<12> PCIE_RXN4
<12> PCIE_RXP4

7

<12> PCIE_TXN4
<12> PCIE_TXP4

CPUSB#

1

RCLKEN

@ C527
330P_0402_50V7K

R5538D001-TR-F_QFN20_4X4~D

2

W W _ LED#_R

2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS_WWAN
1
C980
47P_0402_50V8J
@

Near to Express Card slot.
+3VS_PEC

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

C521
0.1U_0402_16V4Z

C

D

3

1

1

2

2

C522
4.7U_0805_10V4Z

+1.5VS_PEC

C525
0.1U_0402_16V4Z

1

1

2

2

C526
4.7U_0805_10V4Z

+3V_PEC

GND
GND

Title

C528
0.1U_0402_16V4Z

1

1

2

2

C529
4.7U_0805_10V4Z

Compal Electronics, Inc.
WLAN, WWAN, New Card

Size

http://laptop-motherboard-schematic.blogspot.com/
B

W W _LED# <38>

+1.5VS_WLAN

Compal Secret Data

Security Classification

A

27
28

1
WXMIT_OFF# <14>
CH751H-40_SC76
2 0_0805_5%
+3VALW
2 0_0805_5%
+ 3VS_WWAN
+1.5VS_WLAN

USB20_N8 <14>
USB20_P8 <14>

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2

SMBCLK
SMBDATA

SANTA_130801-5_RT
C ONN@

internal pull high to 3.3Vaux-in
EC need setting at Hi-Z & output Low

4

2

M_WXMIT_OFF# D12
PLT_RST#
@ R396 1
R398 1

JEXP

Express Card Power Switch
C520
1
2 0.1U_0402_16V4Z

+3VS_WWAN
+1.5VS_WLAN
UIM _ PWR_R
U IM_DATA_R
UI M_CLK_R
U IM_RST_R
UIM_VPP_R

QUASA_CA0416-092N21
C ONN@

New Card

3

B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
B34
B36
B38
B40
B42
B44
B46
B48
B50
B52

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Sheet

Monday, April 13, 2009
E

31

of

49

4

5

4

3

+ D V D D12
L2

1

LAN Conn.

R 817

1

2

2

1

2

1

2

1

2

1

C 1030
0 .1U_0402_16V4Z

1

1

C 1029
0 .1U_0402_16V4Z

1

2

C 1028
0 .1U_0402_16V4Z

1

2

C 1027
0 .1U_0402_16V4Z

1

2

J R J 45
C 1026
0 .1U_0402_16V4Z

1

2

2

0_0805_5%

R 369
300_0402_5%

2

L A N _ACT#

2

C 480
0 .1U_0402_16V4Z

1

L A N L ED_ACT#

1

1

2

U46

R 819 2
+ V D D33

1 12K_0402_1% 1
2
LAN_X1
3
LAN_X2
4
5
6
Close to Pin8.
+ DVDD
7
+ D V D D12
8
+ V D D33
9
<12> C L K _ P CIE_LAN#
10
1
1
<12> C L K _ P CIE_LAN
11
+ V D D33
12
<12> P C IE_TXP3
13
<12> P C IE_TXN3
2
2
14
C 481 2
1 0.1U_0402_16V7K P C IE_PTX_IRX_N3 15
<12> P C I E_RXN3
C
479
0.1U_0402_16V7K
P
CIE_PTX_IRX_P3
16
2
1
<12> P C I E_RXP3
17
+ D V D D12
18
<6,14,31> P L T_RST#
19
<13,31> I C H _ P C I E _WAKE#
M PD
20
C L K R E Q_LAN#
21
<12> C L K R E Q_LAN#
22
D
4
1
C
H
751H-40PT_SOD323-2
C
R
_
C
D
1
N
1
2
23
<14> C R _ W A K E#
CR_CD0N
24
25
+ V C C _4IN1
26
+ D V D D12
27
2
+ V D D33
28
C R _ L ED#
29
M D IO14
30
1
M D IO13
31
32
C 1035
10U_0805_6.3V6M

LAN_X2

2

3
NC OUT

NC

2

IN

1

1

4

C 1043
27P_0402_50V8J

JMC261

C 1040
0 .1U_0402_16V4Z

LAN_X1

Y4
2 5 MHZ_16PF_X3S025000FG1H-HX

C 1034
0 .1U_0402_16V4Z

C

REXT
VDDX33
XIN
XOUT
GND
LX
FB12
VDDREG
CLKN
CLKP
AVDDH
RXP
RXN
GND
(LQFP
TXN
TXP
AVDDX
RSTN
WAKEN
MPD
CREQN
SMB_SCL/LED2
CR_CD1N
CR_CD0N
VCC3O
VDD
VDDIO
TESTN
SMB_SDA/CR_LEDN
MDIO14
MDIO13
GND

1

64)

NC
NC
NC
NC
NC
AVDD33
GND
VIN_2
VIP_2
AVDD12
VIN_1
VIP_1
GND
VDD
LED1
LED0
MDIO0
MDIO1
MDIO2
VDDIO
MDIO3
MDIO4
MDIO5
GND
MDIO6
MDIO7
VDDIO
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

L A N _MDI3L A N _MDI3+
L A N _MDI2L A N _MDI2+

1

L A N _LINK#

+ V D D33

2

L A N _MDI0L A N _MDI0+

L A N _LINK#
L A N _ACT#
M D IO0
M D IO1
M D IO2
M D IO3
M D IO4
M D IO5

1

14

R J 4 5_MIDI3-

8

R J 4 5_MIDI3+

7

R J 4 5_MIDI1-

6

R J 4 5_MIDI2-

5

R J 4 5_MIDI2+

4

R J 4 5_MIDI1+

3

R J 4 5_MIDI0-

2

R J 4 5_MIDI0+

1

+ 3 V_LAN

11

L A N L E D_LINK#

12

R 3 71
300_0402_5%

L A N _MDI1L A N _MDI1+

Yellow LED+
Yellow LEDSHLD1
PR4DETECT PIN1

16
9

PR4+
PR2-

D

PR3PR3+
PR2+
PR1DETCET PIN2
PR1+
SHLD1

10
15

Green LED+
Green LEDFOX_JM36113-P1122-7F
C ONN@

+ D V D D12

LANGND

1
+ D V D D12

2

1

C 483
0 .1U_0402_16V4Z

2

C 484
4 .7U_0805_10V4Z

10/100 and Giga Transformer Co lay
+ V D D33

R 333 1

2 22_0402_5%

M D I O5_R
C

U17

M D IO6
M D IO7
C 1042

+ V D D33

M D IO8
M D IO9
M D IO10
M D IO11
M D IO12

1

2 0 .1U_0402_16V4Z

C 1044
27P_0402_50V8J

2

2

C 482
0 .1U_0402_16V4Z

+ D V D D12

13

+ 3 V_LAN

J M C261-LGBZ0A_LQFP64_7X7

L A N _MDI0+
L A N _MDI0-

1
2
3

L A N _MDI1+
L A N _MDI1-

4
5
6

L A N _MDI2+
L A N _MDI2-

7
8
9

L A N _MDI3+
L A N _MDI3-

10
11
12

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

24
23
22

C 1041

2

1 1000P_0402_50V7K

21
20
19

C 1039

2

1 1000P_0402_50V7K

18
17
16

C 1085

15
14
13

C 1083

R 8 22 1

2

75_0402_1%

R 8 21 1

2

75_0402_1%

2

75_0402_1%

R J 4 5_MIDI0+
R J 4 5_MIDI0-

R J 4 5_MIDI1+
R J 4 5_MIDI1-

1 1000P_0402_50V7K

2

R 9 23 1

8 111DL@

R J 4 5_MIDI2+
R J 4 5_MIDI2-

1 1000P_0402_50V7K

2

R J 4 5_MIDI3+
R J 4 5_MIDI3-

R 9 22 1

2

75_0402_1%

R J 4 5 _ GND

D

2

2

C 1023
0 .1U_0402_16V4Z

C 1018
10U_0805_6.3V6M

1

C 1019
0 .1U_0402_16V4Z

4 . 7 U H_1008HC-472EJFS-A_5%_1008

C 1022
0 .1U_0402_16V4Z

+ 3 V_LAN

C 1025
10U_0805_6.3V6M

2
C 1021
0 .1U_0402_16V4Z

1

C 1020
0 .1U_0402_16V4Z

+ DVDD

2

+ V D D33

8 111DL@

1
C 1045
1000P_1206_2KV7K

JMC251 Κ SA000039X 00

2

S U P E R W O R L D_SWG150401

JMC261 Κ SA000037N 00

1.For Giga LAN (RTL8111DL):
Mail source: LANKom: LG-2446S-1 (P/N: SP050005L00)
2nd Source: MHPC: NS892406 (P/N: SP050005900)
2.For 10/100M (RTL 8103EL):
Main Source: MHPC NS892404 (P/N: SP050003P00)

D3E support

Card Reader Connector

B

JREAD1

M D I O5_R
M D IO0
M D IO1
M D IO2
M D IO3
CR_CD1N
M D IO4

@

+ V D D33
+ 3VS

2

1

+ V DD33

@ R 823 1

+ 3 V ALW

2 0_0805_5%

D40

R 825
4.7K_0402_5%

R 826
4.7K_0402_5%

R 8 28 1

2 1.2K_0402_5% 2

1

C R _ L ED#

2
@
R 382 1

@

2 0_0402_5%

W hite

40 mils

3

1

+ 3 V_LAN

+ V C C _4IN1

D 39
CR_CD1N

2

CR_CD0N

3

1

Q 15
SI2301BDS-T1-E3_SOT23-3

Issued Date

D A N 2 02U_SC70

C 1047
270P_0402_25V7

Compal Secret Data
2007/08/28

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

1

2

S ecurity Classification

4

X D _ CD

1
2

2

G

7IN1 GND
7IN1 GND

<37> L A N _ P O W E R _OFF

5

+ 5VS

H T - 1 1 0TW_WHITE

D

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

T A I T W _ R 0 1 5 - B 1 0 - LM
CONN@

A

1 0_0402_5%
1 0_0402_5%

1

M D IO6

2

R 925 2
R 927 2

1

2
26
17
15
19
24
22
13

1

@
@

M PD

2

M D I O5_R
M D IO0
M D IO1
M D IO2
M D IO3
M D IO8
M D IO9
M D IO10
M D IO11
M D IO4
CR_CD0N

2 0_0402_5%

S

41
42

7IN1 GND
7IN1 GND

SD-WP-SW

20
14
12
30
29
27
23
18
16
25
1

R 9 26 1

C 485
0 .1U_0402_16V4Z

11
31

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

P L T_RST#

2

34
33
35
40
39
38
37
36

7 IN 1 CONN

+ V C C _4IN1

1

M D IO4
M D IO6
M D IO14
X D _ CD
M D IO13
M D IO12
M D I O5_R
M D IO7

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

21
28

C 1086

32
10
9
8
7
6
5
4

SD-VCC
MS-VCC

0 .1U_0402_16V4Z

M D IO0
M D IO1
M D IO2
M D IO3
M D IO8
M D IO9
M D IO10
M D IO11

XD-VCC

C 1062
10U_0805_6.3V6M

3

+ V C C _4IN1

R 824
100K_0402_5%

B

2

http://laptop-motherboard-schematic.blogspot.com/

Title

R 829 1

2 10K_0402_5%

M D IO4

R 830 1

2 10K_0402_5%

M D IO6

R 831 1

2 1K_0402_5%

M D IO13

A

Compal Electronics, Inc.
USB CardReader&CONN

Size
D o c u m ent Number
C u s t om
Ca lp e lla
D a te:

Rev
0 .1

DI S LA4 743P

Monday, April 13, 2009

Sheet
1

32

of

49

1
2
33_0402_5%

<11> HDA _ SDIN0
<11> HDA _ S DOUT_CODEC
<11> HDA _ S Y NC_CODEC
<11,37> HDA _RST#_CODEC

HDA _ S DI N0_CODEC

8

HDA _ S DOUT_CODEC

5

HDA _ S Y NC _CODEC

10

HDA _RST#_CODEC

11

R679 1
R446 1

<21> DM IC_CLK
<21> DMIC_DAT

@ R910 1

<37> E A P D_CODEC

2 33_0402_5%
2 0_0603_5%

2
4

2 0_0402_5%

46
48

+3VS
2

<37>

R908 1

EC_MUTE#

2 10K_0402_5% 47

SENSE_A
SENSE_B

HDA_BITCLK
HDA_SDI

HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_or_F

HDA_SDO
HDA_SYNC

HP1_PORT_B_L
HP1_PORT_B_R

HDA_RST#

PORT_C_L
PORT_C_R
VREFOUT_C
DMIC_CLK/GPIO1
DMIC0/GPIO2

SPKR_PORT_D_L+
SPKR_PORT_D_L-

DMIC1/GPIO0/SPDIF_OUT_1
SPDIF_OUT_0

SPKR_PORT_D_RSPKR_PORT_D_R+

EAPD

PORT_E_L
PORT_E_R

EC_MUTE#
2
C1069
4.7U_0603_6.3V6M

1

35
36

PORT_F_L
PORT_F_R

CAP-

PC_BEEP
CAP+
MONO_OUT

33
30
26
42
49

2

R442 2
@ C555
1

2

2

+ V REFOUT_INTMIC

31
32

HP_OUTL
HP _OUTR

19
20
24

MIC_EXTL C557 1
MIC_EXTR C558 1

40
41

SPKL+
SPKL-

43
44

SPKRSPKR+

CAP2
VREFFILT

PVSS

V-

DAP

VREG

92HD81B1X5NLGXB1X8_QFN48_7X7~D

1

1
2

2

1

1
2

R435
4.7K_0402_5%

1

M I C_IN_L

+ A V DD_CODEC
R438
R439
R440

2 2.5K_0402_1%
2 39.2K_0402_1%
2 20K_0402_1%

1
1
1

C556

2 2.2U_0603_6.3V4Z MIC_EXT_L
2 2.2U_0603_6.3V4Z MIC_EXT_R

HP_DET# <34>
EXTMIC_DET# <34>

2 1000P_0402_50V7K

1

HP_OUTL <34>
HP _ OUTR <34>

HP Jack

MIC_EXT_L <34>
MIC_EXT_R <34>

Ext MIC

+VREFOUT_EXTMIC
SPKL+
SPKL-

<34>
<34>

SPKRSPKR+

<34>
<34>

Internal SPKR

+ A V DD_CODEC

15
16

R909
10K_0402_5%

17
18

M IC _INL C559 1
M IC_ I NR C560 1

12

M ONO_ INR C561 2

2 2.2U_0603_6.3V4Z
2 2.2U_0603_6.3V4Z

M I C_IN_L
M IC_ IN_R

1 0.1U_0402_16V4Z

M ON O_IN

M IC_IN_L <34>
M IC_ IN_R <34>

Int MIC

R447 2

1 47K_0402_5%

@ R448 2

1 47K_0402_5%

C1070 1

22
21
34
37
2

1

1

2

2

1

2

2 0.1U_0402_16V4Z

25

DVSS
AVSS
AVSS
AVSS

2

SENSEA
1 100K_0402_5%
+ A V DD_CODEC
1000P_0402_50V7K

28
29
23

C1071
4.7U_0603_6.3V6M

7

13
14

R434
4.7K_0402_5%
M IC_ IN_R

2

6

R433
4.7K_0402_5%

2

1U_0603_10V4Z

1

HDA _BITCLK_CODEC
R444

39
45

C546 1

1U_0603_10V4Z

1

2
1
47_0402_5%

<11> HDA _BITCLK_CODEC

PVDD
PVDD

DVDD_IO

R431
2
1
1K_0402_5%

D
EC_BEEP <37>
Q38
2N7002_SOT23-3 S

2
G

SB_SPKR

SB_SPKR <11>

3

3

1

R449
10K_0402_5%

@ R441

AVDD
AVDD

DVDD

1

C1068
10U_0805_10V4Z

@ C554
2
1
33P_0402_50V8K

DVDD_CORE

+ V REFOUT_INTMIC

2

MIC_EXT_L

1

2

9

2

1

2

2

27
38

C1067
1U_0402_6.3V6K

1
1 10U_0805_10V4Z

2

C562
0.1U_0402_16V4Z

C1065

1

C545 1

R432
4.7K_0402_5%
MIC_EXT_R

C1066
0.1U_0402_16V4Z

1
U22

1 0_0805_5%

C1064
1U_0402_6.3V6K

2

R904 2

C564
1U_0603_10V6K

1

E

R430
2
1
0_0402_5%

+5VS

C1063
0.1U_0402_16V4Z

2

1

+ A V DD_CODEC

C563
10U_0805_10V4Z
1
2

2 0_0603_5%

D

+VREFOUT_EXTMIC

C1072
10U_0805_10V4Z

R907 1

C551
0.1U_0402_16V4Z

1

1

+3VS_HDA

C976
0.1U_0402_16V4Z

+3VS

C

+ 3VS_DVDD

R437
BLM18BD601SN1D_0603
2
1

C553
1U_0402_6.3V6K

+3VS

B

2

A

2

1

3

3

MDC 1.5 Conn.
+3VS

JP8

R452 1

HDA _ S Y NC_MDC
2 33_0402_5% HDA _ S DIN1_MDC

GND1
IAC_SDATA_OUT
GND2
IAC_SYNC
IAC_SDATA_IN
IAC_RESET#

RES0
RES1
3.3V
GND3
GND4
IAC_BITCLK

2
4
6
8
10
12

R450 1

2 0_0603_5%
+3VS

HDA_BITCLK_MDC <11>

H10
HOLEA

1

10_0402_5%

@ C568 1

2

10P_0402_25V8K

1

2

2 1000P_0402_50V7K

@ C984 1

2 1000P_0402_50V7K

@ C985 1

2 1000P_0402_50V7K

@ C986 1

2 1000P_0402_50V7K

R754 1

2 0_0603_5%

@

R132 1

2 0_0603_5%

@

R135 1

2 0_0603_5%

@

R139 1

2 0_0603_5%

1

2

GNDA

<34>

13
14
15
16
17
18

ACES_88018-124G

Connector for MDC Rev1.5

1

1

GND
GND
GND
GND
GND
GND

@ R453 2
H9
HOLEA

+3VS
C566
0.1U_0402_16V4Z

<11> HDA _ S Y NC_MDC
<11> HDA _ SDIN1
<11> HDA_RST#_MDC

1
3
5
7
9
11

C565
1000P_0402_50V7K

HDA _ SDOUT_MDC

<11> HDA _ SDOUT_MDC

@ C983 1

GND

C ONN@

GNDA

MDC Standoff
4

4

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

A

Title

Codec_IDT9271B7

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size Do c ument Number
Cu s tom

http://laptop-motherboard-schematic.blogspot.com/
B

C

D

Da te:

Rev
0.1

Calpella DIS LA4743P
Sheet

Monday, April 13, 2009
E

33

of

49

B

C

D

E

1

A

SPEAKER

2

5
6

2
M IC_IN_L

INTMIC IN

1

<33>

GND1
GND2

1

R469
0_0402_5%

E&T_3806-F04N-02R
C ONN@
<33>

C ONN@
JP10
1
2

M IC_ IN_R

3
4
D16
PSOT24C_SOT23-3

1
2
GND
GND
ACES_88231-02001

1

D15
PSOT24C_SOT23-3
1

1
2
3
4

2

2

2

2
2

1

C572
330P_0402_50V7K

1

1

1
2
3
4

3

1

C571
330P_0402_50V7K

SPK_RSPK_R+
SPK_LSPK_L+
C570
330P_0402_50V7K

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

3

2
2
2
2

2

SPKRSPKR+
SPKLSPKL+

1
1
1
1

C569
330P_0402_50V7K

1

<33>
<33>
<33>
<33>

R454
R455
R456
R457

3

D17
PSOT24C_SOT23-3

JSPK1
SPKRSPKR+
SPKLSPKL+

Audio connector
J A UDIO

2

Add JSPK2 for PA
C ONN@
JSPK2
SPK_LSPK_L+

1
2
3
4

<33>
<33>

MIC_EXT_R
MIC_EXT_L

<33>
<33>

HP_OUTL
HP _OUTR

<33> EXTMIC_DET#
<33> HP_DET#

1
2
3
4
5
6
7
8
9
10

MIC_EXT_R
MIC_EXT_L
HP_OUTL
HP _OUTR
EXTMIC_DET#
HP_DET#

1
2
GND
GND

11
12

ACES_88231-02001

1
2
3
4
5
6
7
8
9
10

2

GND1
GND2
ACES_87213-1000G
C ONN@

Consumer IR
1

+5VL

R476
100_0805_5%
3

3

I R1
2

1
2

<37>

CIR_ IN

CIR_ IN

3
4

Vout
VCC
GND
GND
IRM-V536/TR1_3P

C597
4.7U_0805_10V4Z

4

4

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

A

Title

AM P & Audio Jack

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size Do c ument Number
Cu s tom

http://laptop-motherboard-schematic.blogspot.com/
B

C

D

Da te:

Rev
0.1

Calpella DIS LA4743P
Sheet

Monday, April 13, 2009
E

34

of

49

5

4

3

2

Right side USB Power Switch

1

Right side ESATA/USB combination Connector

+5VALW
+ USB_VCCC
+ US B_VCCC

TPS2061IDGNR_MSOP8
2

JESATA

W=100mils

8
7
6
5

1
+
2

1

2

C601
1000P_0402_50V7K

USB_EN#

1

OUT
OUT
OUT
OC#

C600
0.1U_0402_16V4Z

D

GND
IN
IN
EN#

C598
150U_B_6.3VM_R40M

C599
4.7U_0805_10V4Z

U2 4
1
2
3
4

R479 1
R480 1

<14> USB20_N2
<14> USB20_P2

1

2

<11>
<11>

2 10K_0402_5%

1

1
2
3
4

U SB20_N2_R
USB20_P2_R

C602 2
C603 2

1 0.01U_0402_16V7KSATA_RXN2
1 0.01U_0402_16V7KSATA_RXP2

+5VALW

USB

VBUS
DD+
GND

5
6
7
8
9
10
11

SATA_TXP2
SATA_TXN2

SATA_TXP2
SATA_TXN2

<11> SATA_RXN2_C
<11> SATA_RXP2_C

R481

2 0_0402_5%
2 0_0402_5%

D

GND
A+
ESATA
AGND
BB+
GND

12
13
14
15

GND
GND
GND
GND
TYCO_1759576-1
C ONN@

D20
4

+5VALW

Finger printer

USB20_N2

VIN

3

D21
IO1

IO2 GND

USB20_P2

2

4

+5VALW
SATA_TXN2

1

VIN

3

PRTR5V0U2X_SOT143-4

IO1

IO2 GND

2

SATA_TXP2

1

PRTR5V0U2X_SOT143-4

1 0 / 0 8 ESD request

+3VS

C

2

C

1

R483
0_0603_5%

1

+3VS_FP

C ONN@
JFPR
R484 1
R485 1

<14> USB20_N7
<14> USB20_P7

2 0_0402_5%
2 0_0402_5%

U SB20_N7_R
USB20_P7_R

C604
0.1U_0402_16V4Z

1
2
3
4
5
6

1
2
3
4
GND
GND

BT Connector

2

9

D22
4

+5VALW
U SB20_N7_R

3

VIN

IO1

IO2 GND

2

Need change to New version

JBT

P-TWO_161011-04021
USB20_P7_R

1

PRTR5V0U2X_SOT143-4
10

1
2
3
4
5
6
7
8

GND 1
2
3
4
5
6
7
GND 8

+3VAUX_BT
USB20_P6_R
U SB20_N6_R

R487
R488

@ R489 1
@ R490 1

1 0_0402_5%
1 0_0402_5%

2
2

USB20_P6 <14>
USB20_N6 <14>
BT_LED <38>
CH_DATA <31>
CH_ CLK <31>

1K_0402_5%
1K_0402_5%

2
2

ACES_87213-0800G
C ONN@

D2 3
4

+5VALW
U SB20_N6_R

VIN

3

2

IO1

USB20_P6_R

1

IO2 GND

PRTR5V0U2X_SOT143-4

1 0 / 0 8 ESD request
+3VAUX_BT
Q20

SI2301BDS_SOT23
B

R491

USB20_N1
USB20_P1

2

3
1

0.1U_0402_16V4Z

1

1

2

1

R493
100K_0402_5%

C606

2

1

2

0.01U_0402_16V7K

BT_OFF

R494 1

C607

1

C608

2

2

2

0_0603_5%

<14>
11
12

1

D

<14>
<14>

USB_EN#

+3VS

1
2
3
4
5
6
7
8
9
10

G

<37> USB_EN#
<14>
USB20_N0
<14>
USB20_P0

1
2
3
4
5
6
7
8
9
10

S

J USB
+5VALW

C605
1U_0603_10V4Z

B

USB cable connector for Left side

2 10K_0402_5%

C609 1

4.7U_0805_10V4Z

2 0.1U_0402_16V4Z

GND1
GND2
ACES_87213-1000G
C ONN@

A

A

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title
Size

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.
USB, BT, eSATA

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Sheet

Monday, April 13, 2009
1

35

of

49

5

4

3

2

1

SPI ROM => 1M (EC code)
D

D

+3VL

&U25
U25
20mils

C610
0.1U_0402_16V4Z

8
3

FSEL#

<37>

SPI_CLK

<37>

F W R#

SPI_FSEL#
2
10_0402_5%
S PI_CLK_R
2
10_0402_5%
S P I_FWR#
2
10_0402_5%

1
R495
1
R496
1
R497

VSS

4

LPC Debug Port

W

7

2
<37>

VCC

1

MX25L8005M2C-15G SOP 8P

HOLD

1

45@

S

6

Change from +3VL to +3VS. 6/9

C

5

D

Q

2

SPI_SO 1
R498

Removed +3VS. 6/13

F RD#
2
0_0402_5%

F RD#

<37>

W IESON G6179 8P SPI

B+

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P

JP15

SA00000XT00Κ S IC FL 8M MX25L8005M2C-15G SOP 8P (MXIC)

R233

SA00001AW00Κ S IC FL 16M MX25L1605AM2C-15G SOP 8P SPI (MXIC)

S PI_CLK_R 1

SA000021A00Κ S IC FL 32M MX25L3205DM2I-12G SOP 8P (MXIC)

2
10_0402_5%

<14> CLK_DEBUG_PORT_0

C391
1
2

<11,31,37> LPC_FRAME#
<14,37> P CI_RST#

6P_0402_50V8D

SA000031Q00Κ S IC FL 32M AT25DF321-SU SOIC 8P (ATMEL)

<11,31,37>
<11,31,37>
<11,31,37>
<11,31,37>

0919 EMI request
C

L PC_AD0
L PC_AD1
L PC_AD2
L PC_AD3
ON/ OFFBTNLED#

SPI ROM on PCH => 4M (ME code + System BIOS)

Connect pin3 & 23
together and pin 24
to GND in 6/29.

+3VS
+3VS

&U31

V CC1 P WRGD
SPI_CLK_JP18
SPI_CS#_JP18
SPI_SI_JP18
SPI_SO_JP18
SPI_HOLD#_0

1
2 SPI_WP#
3.3K_0402_5%

R659 1

2S PI_HOLD#
3.3K_0402_5%

+3VS

C773
0.1U_0402_16V4Z

1

R661

<11> S PI_CLK_PCH
<11>

SPI_SI

SPI_SB_CS# 1

SPI_WP#

3

S PI_HOLD#

7

2

1

S PI_CLK_PCH 15_0402_5%

6

SPI_SI

5

VCC

45@
VSS

Ground
LPC_PCI_CLK
Ground
LPC_FRAME#
+V3S
LPC_RESET#
+V3S
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
VCC_3VA
PWR_LED#
CAPS_LED#
NUM_LED#
VCC1_PWRGD
SPI_CLK
SPI_CS#
SPI_SI
SPI_SO
SPI_HOLD#
Reserved
Reserved
Reserved

C

ACES_87216-2404_24P
C ONN@

32M AT25DF321-SU SOIC 8P

U31
8
@ R660
1K_0402_5%

<11> SPI_SB_CS#

2

2

R658 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

4

W
HOLD
S
C
D

R662
Q

2

W IESON G6179 8P SPI

SPI_SO_L 1

2

SPI_SO_R

SPI_SO_R <11>

+3VALW

15_0402_5%
R504 1

B

<37,38> ON/OFFBTN_LED#
<37> V CC1 _PWRGD

SPI_CLK

2
0_0402_5%

SPI_CLK_JP18

FSEL#

2
0_0402_5%

SPI_CS#_JP18

2
0_0402_5%

SPI_SI_JP18

2
0_0402_5%

SPI_HOLD#_0

2
0_0402_5%

SPI_SO_JP18

2
0_0402_5%

ON/ OFFBTNLED#

2
0_0402_5%

V CC1 P WRGD

1
R501
DE B UG@
1
R502
DE B UG@
F W R#
1
R503
DE B UG@
HOL D#
2
1
3.3K_0402_5%
R505
DE B UG@
F RD#
1
R506
DE B UG@
ON /OFFBTN_LED#
1
R507
DE B UG@
V CC1 _ PWRGD
1
R508
DE B UG@

B

11/07 Add 0 Ohm for debug port

A

A

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title
Size

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.
BIOS ROM

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Sheet

Monday, April 13, 2009
1

36

of

49

C612

+3VL_EC
BATT_OVP

C616

+3VL

C617
2

+3VL_EC
R511
1

+3VL

2
0_0805_5%

+3VALW
U27

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%

@ C623
1

<14>
GATEA20
<14>
KB_RST#
<11>
S IRQ
<11,31,36> LPC_FRAME#
<11,31,36> L PC_AD3
<11,31,36> L PC_AD2
<11,31,36> L PC_AD1
<11,31,36> L PC_AD0

@ R516
2

1

2
33_0402_5%

15P_0402_50V8J
<14> CLK_PCI_EC

<14,36> P CI_RST#

2
47K_0402_5%

1
0.1U_0402_16V4Z

2

2
C630

<14>
E C_SCI#
<11,33> HDA _RST#_CODEC

+3VS

1

1

1
R523
100K_0402_5%

R526
10K_0402_5%
2

2

R525
10K_0402_5%

L I D_SW#

TP_BTN#

01/03 Change to +3VS

@ R531
10K_0402_5%

@ R533 1

2
0_0402_5%

R532
10K_0402_5%<38,40>
<38,40>
<12>
<12>

+3VL

1

<13>
<13>
<14>
<38>

2

2

SLP_S3#
SLP_S5#
EC_SMI#
L ID_SW#

<13>
E C_ ACIN
<6> FAN_SPEED
<31> W W A N_ POWER_OFF
1
2
R538
4.7K_0402_5%
<39> DIM_LED

1
C645
0.1U_0402_16V4Z

SLP_S3#
SLP_S5#
EC_SMI#
L I D_SW#
ESB_CLK_R
ESB_DAT_R
EC_PME#
E C_ ACIN
FAN_SPEED
W W A N_ POWER_OFF
UTX
L A N _POWER_OFF_R
ON/ OFFBTN#
DI M_LED

C647
15P_0402_50V8J
1
2

C646
0.1U_0402_16V4Z

C RY 2

3
2

MISC
AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

NC

OSC

NC

OSC

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPO

1

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

GPI

XCLK1
XCLK0

V18R

@
R539
20M_0402_5%

4

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

68
70
71
72

FAB_SET
V CTRL
IRE F
AC_SET

83
84
85
86
87
88

EC_MUTE#
USB_EN#
I2 C_INT

EC_BEEP
A C OFF

EC_BEEP <33>
A COFF
<41>

C RY 1

R524

1

C649
15P_0402_50V8J

EC DEBUG port

+ E C_AVCC

L26
0_0603_5%

@ C618 1

2 100P_0402_50V8J

KSO10

@ C619 1

2 100P_0402_50V8J

KSO11

@ C620 1

2 100P_0402_50V8J

KSO14

@ C621 1

2 100P_0402_50V8J

KSO13

@ C622 1

2 100P_0402_50V8J

KSO12

@ C625 1

2 100P_0402_50V8J

KSO3

@ C626 1

2 100P_0402_50V8J

KSO6

@ C627 1

2 100P_0402_50V8J

KSO8

@ C628 1

2 100P_0402_50V8J

KSO7

@ C629 1

2 100P_0402_50V8J

KSO4

@ C631 1

2 100P_0402_50V8J

KSO2

@ C632 1

2 100P_0402_50V8J

KSI0

@ C633 1

2 100P_0402_50V8J

KSO1

@ C634 1

2 100P_0402_50V8J

KSO5

@ C635 1

2 100P_0402_50V8J

KSI3

@ C636 1

2 0_0402_5%

1

2 100P_0402_50V8J

KSI2

@ C637 1

2 100P_0402_50V8J

KSO0

@ C638 1

2 100P_0402_50V8J

KSI5

@ C639 1

2 100P_0402_50V8J

KSI4

@ C640 1

2 100P_0402_50V8J

KSO9

@ C641 1

2 100P_0402_50V8J

KSI6

@ C642 1

2 100P_0402_50V8J

KSI7

@ C643 1

2 100P_0402_50V8J

KSI1

@ C644 1

2 100P_0402_50V8J

ENBKL

2

<38>
<38>

A C_LED# <40>

11/09 don't stuff when use C0

119
120
126
128

R527
R528
R529

1
1
1
R530

F RD#
F W R#
SPI_CLK
FSEL#

33_0402_5%
33_0402_5%
33_0402_5%

1

2 10K_0402_5%
+5VL
C IR_ IN
<34>
V CC1 _ PWRGD <36>
F S TCHG <41>
STD_ADP <41>
CAPS_LED# <38>
BAT_LED# <38>
ON/OFFBTN_LED# <36,38>
S Y S ON
<31,38,39,48>
V R_ ON
<46>

CIR_ IN
V CC1 _ PWRGD
F S TCHG
STD_ADP
CAPS_LED#
BAT_LED#
ON /OFFBTN_LED#
S Y SON
V R _ON
A C_ IN

EC_RSMRST#
100
2
101 R535 1
E C _ON 0_0402_5%
102
WL_BLUE_LED#
103
P M_PWROK_R
104
BKOFF#
105
M _PWROK
106
TP_LED#
107
108
SLP_S4#
ENBKL
E A P D_CODEC
T HERM_SCI#
SUSP#
PWRBTN_OUT#
NM I_DBG#

F RD#
F W R#
SPI_CLK
FSEL#

2
2
2

2

110
112
114
115
116
117
118

2 10K_0402_5%
2 10K_0402_5%
TP_CLK
TP_DATA

97
98
99
109

73
74
89
90
91
92
93
95
121
127

R519 1
R520 1

TP_CLK
TP_DATA

B KOFF# <21>
M _PWROK <13>
TP_LED# <38>

2

PV PWROK sequence issue

JKB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2

+3VL

+3VL

NM I_DBG#

13" INT_KBD
CONN.( TYPE "D"
KB)

PM_PWROK <13>

100_0402_5%

SLP_S4# <13>
ENBKL
<22>
E A P D_CODEC <33>
T HERM_SCI# <24>
SUSP#
<31,39,41,44,45>
PWRBTN_OUT# <13>

C648
4.7U_0603_6.3V6K

A D P_ID

D24
1

2

CH751H-40PT_SOD323-2

R540
10K_0402_5%
D2 5
1

+3VL

2 P C I_SERR#

P CI_SERR# <14>

CH751H-40PT_SOD323-2
R541
150K_0402_5%

1
2

0_0805_5%
R543
1

2

1
C650

L A N _POWER_OFF_R

2
0.1U_0402_16V4Z

L27
1
2
0_0603_5%

A C_ IN

2

D26
1

A CIN

A CIN

<41>

CH751H-40PT_SOD323-2
0_0402_5%
+3VL

+3VL

1

2

1

1

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

ACES_85202-24051
C ONN@

2
2

2
100P_0402_50V8J

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1

R545
4.7K_0402_5%

R544
4.7K_0402_5%
<38> ESB_CLK
<38> ESB_DAT

C651

1
10K_0402_5%

R741

R536
1

1

2

<36>
<36>
<36>
<36>

1
10K_0402_5%
EC_RSMRST# <13>
E C_LID_OUT# <12>
E C_ ON
<42>
WL_BLUE_LED# <38>

124

For C
Revision

+3VL_EC

<6>
<41>
<41>
<41>

EC_MUTE# <33>
USB_EN# <35>
I2 C_INT
<38>

1

2

0.01U_0402_16V7K
E CA G ND
2

BATT_TEMP <40>
BATT_OVP <40>
A DP_I
<41>
A DP _ID
<40>
TP_BTN# <38>

FAN_SET
V CTRL
IRE F
AC_SET

E CA G ND

1

1

KSO15

+5V_TP

KB926QFB0_LQFP128_14X14

32.768KHZ_12.5PF_Q13MC14610002

<32> L A N_POWER_OFF

BATT_TEMP
BATT_OVP
A DP_I
A D P_ID
TP_BTN#

INV_PWM <22>

C624

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
P S2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
S PI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
S M Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

2

03/13 PV2 Add EMI solution

@ R542 2

63
64
65
66
75
76

PWM Output

1

Y6

UTX

I NV_PWM

R534

<38> ON/OFFBTN#

PCI_RST#

77
78
79
80

EC_PME#
EC_PME#

EC_PME#

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

21
23
26
27

2

<14> PCI_PME#

2

1

11/15 Delete PCI_PME#

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

1

+3VALW

2

+3VL

12
13
37
20
38

2
R518
0_0402_5%

J OPEN

2

R522
8.2K_0402_5%
2

1

R521
8.2K_0402_5%

CL K_PCI_EC
PCI_RST#
ECRST#
1

J4

+3VL

PCI_RST#

1

SUSP#

2

S Y SON

1
2
3
4
5
7
8
10

1

R517

1

1

+3VL

GATEA20
KB_RST#
S I RQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

2

2
2
2
2

VCC
VCC
VCC
VCC
VCC
VCC

1
1
1
1

GND
GND
GND
GND
GND

R512
R513
R514
R515

For EMI

11
24
35
94
113

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

+ EC_AVCC

67

C615
2
2
1000P_0402_50V7K

AVCC

C614

1

100P_0402_50V8J

1

AGND

C613

2
2
0.1U_0402_16V4Z

2

1000P_0402_50V7K

69

1

0.1U_0402_16V4Z
1

9
22
33
96
111
125

0.1U_0402_16V4Z
1
1

R546
R547

1
1

2 0_0402_5%
2 0_0402_5%

C652 @
10P_0402_50V8J
ESB_CLK_R
ESB_DAT_R

Compal Secret Data

Security Classification
Issued Date

2007/08/28

Deciphered Date

2006/07/26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
EC KB926/KB Conn.

Size

http://laptop-motherboard-schematic.blogspot.com/

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Monday, April 13, 2009

Sheet

37

of

49

A

B

C

D

E

1

1

9

for debug only

J CAP

JTPSW
3

2

4

+5VS

+3VL
ESB_DAT

@ R570
2

ESB_CLK

33_0402_5%
@ R564
2
1

1

2

2 0_0402_5%
2 0_0402_5%

1
2
3
4
GND
GND

ON/ OFFBTN#

SMT1-05_4P

P-TWO_161011-04021
CONN@

Capacitor Sensor Conn

R557
0_0805_5%

1

C662
2

+5VS

TP_LED#
TP_BTN#

TP_LED# <37>
TP_BTN# <37>

1

+5V_TP
R558 1

2 0_0603_5%

+5V_TP

15P_0402_50V8J
S

D

1

J CSB

2 1.8K_0402_5%

R563

1

2 1K_0402_5%

1

1

2

1
<31,37,39,48> S Y SON

2

D

S

1
2
3
4
5
6

1
2
3
4
GND
GND
@ Q24
2N7002_SOT23-3

C654
0.1U_0402_16V4Z

2

JTP

S Y SON 2
G

P-TWO_161021-10021
C ONN@

@

C772
15P_0402_50V8J

1

Q23 @
SI2301BDS-T1-E3_SOT23-3

2

1

1

R596

@ R560
10K_0402_5%

3

2 FBMA-11-100505-801T 0402
2 FBMA-11-100505-801T 0402

1
2
3
4
5
6
7
8
9
10
GND
GND

G

<36,37> ON/OFFBTN_LED#
<37> ESB_CLK
<37> ESB_DAT
<37>
I2 C_INT
+5VALW
<37>
L ID_SW#
<37> ON/OFFBTN#

1
2
3
4
5
6
7
8
9
10
11
12

2

D32
PSOT24C_SOT23-3
+5VALW

3

ON /OFFBTN_LED#
E NE@ R561 1
E NE@ R562 1

TP_DATA
TP_CLK

T/P Board Conn

15P_0402_50V8J
C660
2
1

33_0402_5%

1
2
3
4
5
6

P-TWO_161011-04021
C ONN@

2

<37,40> SMB_EC_CK1
<37,40> SMB_EC_DA1

1

2

CAPS_LED# <37>

3

10

SW2

1
2
3
4
5
6

6
5

1
2
3
4
GND
GND

ACES_87213-0800G
C ONN@

Cy p r ess@
R597 1
R598 1
Cy p r ess@

T/P Board (Inculde T/P_ON/OFF)

+5VS

@

ON /OFFBTN_LED#

1 GND
2
3
4
5
6
7
8 GND

@

White

AMBER

1
2
3
4
5
6
7
8

Power Button

Caps-Lock Conn

J L ED
+5VALW
+5VS
+3VS
<37>
BAT_LED#
<11> SATA_LED#
<11> HDDHALT_LED#

1

System LED Conn

TP_CLK
TP_DATA

P-TWO_161011-04021
C ONN@

TP_CLK
TP_DATA

@ C658
100P_0402_50V8J

1

1

2

2

<37>
<37>

@ C659
100P_0402_50V8J

C661
2 4.7U_0603_6.3V6K

Mini card LED

3

3

+3VS
1

Keyboard backlight Conn

2

R565
10K_0402_5%

WL_BLUE_LED# <37>

0_0805_5%

1
2
3
4
5
6

Q25
2N7002_SOT23-3

1
2
3
4
GND
GND

<35>

BT_LED

D

S

2
G

R567
100K_0402_5%
2

P-TWO_161011-04021
C ONN@

1

JKBL
2

3

1

1

R566
+5VS_LED

D33
<31> W L_LED#

2

<31> W W _LED#

3

W L_LED

1

PSOT24C_SOT23-3
4

4

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

KBD, ON/OFF, SW, CIR
Size

http://laptop-motherboard-schematic.blogspot.com/
B

C

D

Compal Electronics, Inc.

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Sheet

Monday, April 13, 2009
E

38

of

49

4

3

RUNO N_3VS

2
R584
470_0402_5%

SUSP

Q10A
2N7002DW-7-F_SOT363-6

1

1

C677
4700P_0402_25V7K

2
R U NON

1

2

D

R650
1K_0402_5%

2

5

1
4

Q10B
2N7002DW-7-F_SOT363-6

01/03 Sparate+5VS
and +3VS power
timing

2

2

1

2

2

R U NON

R585
470_0402_5%
SUSP

2

1

C680
10U_0805_10V4Z

2

1

C679
0.1U_0402_16V4Z

1

10U_0805_10V4Z

4

C669
4

2

2

+1.5VS
SI7326DN-T1-E3_PAK1212-8
U30
1
2
5
3
C681
10U_0805_10V4Z

1

+1.5V to +1.5VS Transfer
+1.5V

C673
0.1U_0402_16V4Z

1
2

R581
330K_0402_5%

6

2

2

1

1

+3VS
SI7326DN-T1-E3_PAK1212-8
U2 9
1
2
5
3

3

2

C675
330K_0402_5%

1

C672
10U_0805_10V4Z

1

4

R583

+3VALW

1

D

10U_0805_10V4Z

1

B+

+3VALW to +3VS Transfer
B+

1

SI7326DN-T1-E3_PAK1212-8 +5VS
U2 8
1
2
5
3

C671
0.1U_0402_16V4Z

+5VALW

C674
10U_0805_10V4Z

+5VALW to +5VS Transfer

2

1

5

C676
0.01U_0402_16V7K

1

C770
0.1U_0402_25V4K

2

2

2

SG@
C1078
0.1U_0402_25V4K

DIM LED
+ VCCP

+1.5V

+5VS

+0.75VS

3

Q6A
A

2
1

H1
HOLEA

H2
HOLEA

H3
HOLEA

H4
HOLEA

H5
HOLEA

H6
HOLEA

5

<37>

S USP

DIM_LED

DI M_LED

D IM_LED#
D

S

Q27
2N7002_SOT23-3

2
G

<45>

Q6B

H8
HOLEA

A

5

SUSP#

H11
HOLEA

H12
HOLEA

<31,37,41,44,45>

H13
HOLEA

H14
HOLEA

H15
HOLEA

H16
HOLEA

H17
HOLEA

H18
HOLEA

FM1
1

FM2
1

FM3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

B

C670
0.1U_0402_16V4Z

100K_0402_5%

1

FM4
1

Compal Secret Data

Security Classification
2007/08/28

Issued Date

5

2

2

2
3
SUSP

1

2

2N7002DW-7-F_SOT363-6

1

S Y SON# 2

Q7B

4

2
6
Q7A

2N7002DW-7-F_SOT363-6

2
3
5
4

SUSP

2N7002DW-7-F_SOT363-6

2
6
1

2

470_0402_5%

1
H7
HOLEA

2N7002DW-7-F_SOT363-6
4
3
2

2
6

S Y SON#

<31,37,38,48> S Y SON

SUSP

Q8B

470_0402_5%

R587
2N7002DW-7-F_SOT363-6

R586
100K_0402_5%
<45>

5

2N7002DW-7-F_SOT363-6

2
3
SUSP

Q8A

470_0402_5%

+3VL

1

+3VL

Q9B

4

1

2

470_0402_5%
2N7002DW-7-F_SOT363-6

2
6
SUSP

2N7002DW-7-F_SOT363-6

Q9A

470_0402_5%

R582
10K_0402_5%

G

470_0402_5%

1

1

R593

1

R592

B

3

R591

1

1

1

1

1

1

R590

D

R589

+5VS_LED

Q26

SI2301BDS-T1-E3_SOT23-3
S

R588

2

C

5

Discharge circuit
+1.5VS

1
6

S G@ Q18A
NV VDD_PG

SG@ Q18B
2N7002DW-7-F_SOT363-6

+3VS

2

4
NV VDD_PG#

2

+5VS

C1079
0.1U_0402_16V4Z

C1081
10U_0805_10V4Z

2

SG@

1

1

NV VDD_PG

2

1
SG@

4.64A

2N7002DW-7-F_SOT363-6 R917
470_0402_5%

S G@ Q17B
2N7002DW-7-F_SOT363-6

6

1

5

NV VDD_PG

SG@ Q17A

1

<47>

SG@
R916
1K_0402_5%

1
SG@

+VDD_MEM
SI7326DN-T1-E3_PAK1212-8
U50 S G@
1
2
5
3

3

1
2

S G@

R594
470_0402_5%

C1074
0.1U_0402_16V4Z

4

1

+1.5V

100 mA

NV VDD_PG#

2

SG@
C1077
0.01U_0402_16V7K

2

+1.5V to +1.5VS_NV Transfer

2N7002DW-7-F_SOT363-6

2

1

2
1

4

SG@ Q14B
2N7002DW-7-F_SOT363-6

2

3

SG@ Q14A
DGP U _PWR_EN 2

5

<14,23,45,47> DGP U_PWR_EN

1
6

1

3

SG@
R915
470_0402_5%

1
S G@

4

S G@
2

S G@

SI7326DN-T1-E3_PAK1212-8
U49 S G@
1
2
5
3
1
S G@

C1076
10U_0805_10V4Z

2

2

DGP U _PWR_EN#

S G@

+1.8VS

2

1

2

SG@
C1073
10U_0805_10V4Z

4

1

B+

2N7002DW-7-F_SOT363-6
R913
470_0402_5%

SG@
R912
330K_0402_5%

+1.8VS_NV

400 mA

C1075
0.1U_0402_16V4Z

C

+1.8VS to +1.8VS_NV Transfer

R918
330K_0402_5%

SI7326DN-T1-E3_PAK1212-8 +3VS_NV
U48 S G@
1
2
5
3

1

+3VALW

4

+3VALW to +3VS_NV Transfer
B+

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

DC/DC Interface
Size

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.

Da te:

Do c ument Number

Rev
0.1

C alpella DI S LA 4743P
Sheet

Monday, April 13, 2009
1

39

of

49

A

B

C

D

+3VALW
3

PQ3
T P0610K-T1-E3_SOT23-3
+3VL

connect to KBC pin97

BATT

AC_LED# <37>

1

499K_0402_1% 340K_0402_1%
P R4 1
P R1 1
2
2

RLZ3.6B_LL34
AD P _SIGNAL

1

P R3
10K_0402_5%

J DC

3
PL1
HCB2012KF-121T50_0805

1
2

P C5
1000P_0402_50V7K

1
2

1
P C3
1000P_0402_50V7K

2

P C4
100P_0402_50V8J

2
1

@PJSOT 24C_SOT23-3

2

2

1

P D1

ACES_87302-0441

P C2
100P_0402_50V8J

3

+

P R5
10K_0402_5%

0
-

2

1

1

BATT_OVP <37>

4

PL2
HCB2012KF-121T50_0805

1

2

105K_0402_1%
P R6 1
2

2

1

1

2

AD P IN

0.01U_0402_25V7K
P C6

6
5
4
3
2
1

2

GND
GND
4
3
2
1

2

8

2

VIN

2

2

1

@1000P_0402_50V7K

P

PD4
P R2
10K_0402_5%

G

1

PR8
2K_0402_5%

1

1

2 1

ADP_ID <37>
PC12

+5VALW

1

2

1

2

2

100K_0402_5%

0.01U_0402_25V7K
P C1

1 P R9

P U1A
LM358ADT_SO8

2

VMB
JBATT

GND

P D2

6
3

SUYIN_200275MR006G113ZL

PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C

2
1

GND

1
1

GND

PL4
HCB2012KF-121T50_0805

EC_SMD
EC_SMC

2
3
4
5

2

PC8
1000P_0402_50V7K

2

8

SMD
SMC
B/I
TS

2

BATT+

7

BATT

PL3
HCB2012KF-121T50_0805

1

1

P C9
0.01U_0402_50V4Z

2

P D3

1

CPU

3

3

P R7
604K_0402_1%

+5VS

1

2
3

PJSOT 24C_SOT23-3

1

2

1

1

1

P H1
10K_T H11-3H103FT_0603_1%

P R14
100_0402_5%

2

PJSOT 24C_SOT23-3

2

1

2

P R15
150K_0402_1%

1
3

S

P

6

PR11
150K_0402_1%

+

0
-

G

5

2

PR12
2.49K_0402_1%

2

1

P C10
0.22U_0603_10V7K

+3VL

2

PR16
6.49K_0402_1%

2

1

1

1

1

<41>

1

PQ1
SSM3K7002FU_SC70-3

2

7

G

PU1B

4

+5VALW

D

LM358ADT_SO8

PC11
1000P_0402_50V7K

2

SMB_EC_CK1 <37,38>

<42>

8

PR10
200K_0402_1%

SMB_EC_DA1 <37,38>

1

SMB_EC_DA1

SMB_EC_CK1
BAT _ID

EN0

2

2

PR13
100_0402_5%

2

PR17
1K_0402_5%
BATT_TEMP <37>

4

4

Security Classification
Issued Date

Compal Secret Data
2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

DC Connector/CPU_OTP
Size

http://laptop-motherboard-schematic.blogspot.com/
B

C

Compal Electronics, Inc.

D ate:

D o cument Number

R ev
0.1

Calpella DIS LA4743P
Sheet

Monday, April 13, 2009
D

40

of

49

A

B

C

P4

V IN

D

B+

BATT

PQ102

P2

AO 4 407_SO8
PQ103

25

L X_ CHG

24

R E GN 2

23

D L _ CHG

4

1
2

1

5
6
7
8

3
2

1

PC122
4 .7 U_ 0805_25V6-K

1
2

PC116
4 .7 U_ 0805_25V6-K

PC115
4 .7 U_ 0805_25V6-K

1
3
2
1

2
20

19

21

<40>

1
3

BATT

1

IREF

<37>

2

PR121
200K_0402_1%

PR122
6 8 1 K_0402_1%

2

2

1

PR1 24
1 K_ 0402_5%

V IN

3

PU1 0 2A
L M3 93DG_SO8

4

2

P A C IN

7

O

L M3 93DG_SO8

1

-

2

PR133
1 0 K_0603_0.1%

<37>

PR127
1 0 K_0402_1%
PU1 0 2B

1

8
+

1

1

6

P

1

5

G

PR134
10K_0402_5%

PD103
RL Z4 .3 B_LL34

2

2

2

ACIN

S
F ST CHG#

1
<37>

1 .2 4 VREF

2

2

PQ112
SSM3 K7 0 0 2 FU_SC70-3

G

2

PR1 32
1 0 0 K_0402_5%

1

D

2

PC1 26
0 .0 4 7 U_0402_16V7K

3

2

1

1
1
2

PR1 28
1 0 K_0402_5%

1

C H G EN#

2

PR129
1 0 K_0402_1%

1
2
1

PR130
2 .1 5K_0402_1%

1

8

PC125
0 .1 U_ 0603_25V7K

1

PR1 26
100K_0402_1%
+3VL

P
G
4

1

133K_0402_1%

1

2
1
1VIN_1
2

1
2
1

BAT _ ID

G
S

V IN

O
-

4 7 K_0402_5%
PR119

2

+3VL

2

PR135
1 0 K_ 0603_0.1%

+

BQ 2 4 7 4 0VREF

+3VL

PR131
1 3 3 K_0402_1%

2

2

2

PR1 25
47_1206_5%

3

2

PR1 20

1

V IN

1

DPMDET

CELLS

SRP

BAT

SRN
18

17

15

16

PQ111
SSM3 K7 0 0 2 FU_SC70-3

2

PR123
1M_0402_5%

2

PC118
0 .1 U_ 0 402_10V7K

D

PC123
0 .1 U_ 0 402_10V7K

PD104
1 SS3 55_SOD323-2

1

AO 4 468_SO8
1 U_ 0 6 03_10V6K

1

V IN

3

PC119

PR117
100K_0402_5%

1

1
2

PC1 20
0 .2 2 U_0603_10V7K

Charge Detector

2
PC1 21
1 0 0 P_0402_50V8J

1

ADP_I

PC135
@4 7 0 P_0603_50V8J

PQ110

IADAPT

2

2

PR118
10K_0402_5%

<37>

SRSET

IADAPT

1

1

PR1 16
39K_0402_5%

22

1

PGND

1

LODRV

ISYNSET

2

EXTPWR

4
PR115
100K_0402_1%

2

PC117
1 U_ 0 6 03_10V6K

PR1 41
@4 .7_1206_5%

2 2

14

2

2

1
1 SS3 5 5_SOD323-2

13

BATT

2

2

REGN

PR112
0 .0 15_1206_1%

1

2

1

VADJ

PL102
1 0 U_ L F 9 1 9 AS-100M-P3_4.5A_20%

1

2

PH

2

1

VCT RL

12

2

1 SS3 5 5_SOD323-2
<37>

V A DJ

1

3

PR114
@0_0402_5%

0 .1 U_ 0402_10V7K
D H _ CHG 1

PC114
4 .7 U_ 0805_25V6-K

VDAC

PQ106
DT C1 1 5 EUA_SC70-3

4

PD1 02

PR113
1 4 3 K_0402_1%

S

2

2

1

11

G
PD1 01

2

1
26

1

3
2
1

HIDRV

<37>

PC111

+3VL

D

2

PU1 0 1
BQ 2 4 7 4 0 RHDR_ QFN28_5X5

VREF

27

PQ108
AO N7 4 0 8 L _ DFN8-5

2

PR1 42
0_0402_5%
BST _ CHG
1
2
PR1 39
0_0402_5%
D H_ CHG1
2

ACO F F

1

1
2

BTST

1

28

2

1

10

1

PC110
1 U_ 0 8 05_25V6K

1

1

ACO F F#

2

1 U_ 0 6 03_6.3V6M

SSM3 K7 0 0 2 FU_SC70-3

AGND

2

29

PC113
4 .7 U_ 0805_25V6-K

PVCC

2
5

CHGEN

ACN

TP

1

P A C IN

PQ109

1

V IN

CHG _ B+

1

IADSLP

BQ 2 4 7 40VREF

PC1 12

1
PR1 11
3K_0402_1%

2

PR1 05
1 0 K_0402_5%

2

3

9

S

1

PR1 08
10_1206_5%

1

2

3
ACP

5

4
LPMD

ACDET

7

6
ACSET

LPREF
8

PC1 05
4 .7 U_0805_25V6-K

2
1

2
2

PR103
4 7 K_0402_5%

ACO F F#

2

1

2

1

2

C H G EN#

PR110
0_0402_5%

8
7
6
5

CHG _ B+
PC1 04
4 .7 U_0805_25V6-K

1

1
2

PR1 40
1 0 0 K_0402_5%

2

1
1

PC1 07
@0 .0 1 U_0402_16V7K

PR1 09
<3 1 ,3 7,39,44,45> SUSP#
1 5 0 K_0402_5%

G

2

PC102
1 U_ 0 6 03_6.3V6M

2

ACSET

2

1
2
3

PL101
HCB2 0 1 2KF-121T50_0805

1

PC1 03
4 .7 U_0805_25V6-K

ACDET

PC1 08
0 .1 U_ 0603_25V7K

4

1

AC_ SET

1

D

2

3
1

PR106
2 0 0 K_0402_5%

1

2

PC106
0 .1 U_ 0603_16V7K

3
1

PQ105
DT C1 1 5 EUA_SC70-3

4

2

PC124
0 .1 U_ 0603_25V7K

1

PQ107
SSM3 K7 0 0 2FU_SC70-3

PQ104
DT A1 4 4 EUA_SC70-3

2

3

2

1

0 .0 12_2512_1%
PR104
0_0402_5%

<37>

2

PR107
47K_0402_1%

1

8
7
6
5

2

1

1

1
2
3

4

PR101
4 7 K_0402_5%

2

PC1 01
4 7 P_0402_50V8J

1

PR102

AO 4 409_SO8

1
2
3

A CN

AO 4 433_SO8

8
7
6
5

A CP

PQ101

PR1 36
6 0 .4K_0402_1%
D

3

G

STD_ADP <37>

1

2

V IN_ 1

PQ113
SSM3 K7 0 0 2 FU_SC70-3

2

F ST CHG

S
PU1 0 4

ACDET

2

2

4

2

5

ANODE

NC

3

1 .2 4 VREF

2
1

L MV4 3 1ACM5X_SOT23-5
4

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

http://laptop-motherboard-schematic.blogspot.com/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

CATHODE
NC

2 2 P_ 0 402_50V8J

100K_0402_1%
PR138

1

PC127
PR137
20K_0402_1%

REF

1

4
1

B

C

Title

Compal Electronics, Inc.
Charger

Size

Do cu me n t Number

Rev
0.1

Calpella DIS LA4743P
Da te:

Mo n d a y, Ap ril 13, 2009
D

Sheet

41

of

49

A

B

C

D

E

1

2VREF_51125

1

PR304
20K_0402_1%
2

LG_5V

5

1
2

PC305
10U_1206_25V6M

PC304
1000P_0402_50V7K
2
1

3
2
1

ENTRIP1

4
PU301
TPS51125RGER_QFN24_4X4

1

PQ304
STL8NH3LL

VL

PR311
191K_0402_1%

PR317
1

+5VALWP

2

R_EC_RSMRST# <13>

1
+

PC310
150U_B_6.3VM_R45M

2

PC311
10U_0805_10V6K

0_0402_5%

1

2

1

2

PR316
4.7_1206_5%
2
1

19

PL303
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
5

LX_5V

VCLK
18

VIN

VREG5
17

21
20

2

PC315
680P_0603_50V8J

EN0

GND

PR312
1M_0402_1%
2

DRVL1

16

DRVL2

15

12

LL1

22

PR308
PC308
0_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
U G_5V
1
2

1

<40>

VFB1

LL2

4

24
23

2

1
2
3

AON7406L_DFN8-5

VREF

DRVH1

SKIPSEL

1

VBST1

DRVH2

13

B++

VBST2

EN0

4

PGOOD

PQ302
AON7408L_DFN8-5

3
2
1

9
10
11

LG_3V

1
1
2

150U_B_6.3VM_R45M

2

2

PC309

+

U G_3V

PQ303

PC314
680P_0603_50V8J

1

PR315
4.7_1206_5%

5

+3VALWP

1
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V

BST_3V

VO1

VREG3

14

1
2
3
PL302
4.7UH_SIQB74B-4R7PF_4A_20%
2
1

VO2

8
PR307

PR309
0_0402_5%
1
2

TONSEL

2

P PAD

7

VFB2

ENTRIP2

25

UG1_3V

2

5

1

PC306
10U_0805_6.3V6M

4

PR306
115K_0402_1%
2

1

6

PQ301
AON7408L_DFN8-5

B++

1

2

3

5

1
2

PC303
4.7U_0805_25V6-K

PC301
1000P_0402_50V7K
2
1

PR305
105K_0402_1%
1

E NTRIP1

PR303
20K_0402_1%
1
2

+3VLP

2
PC313
0.1U_0402_25V6
2
1

1

PR302
30.9K_0402_1%
2

2

PL301
HCB2012KF-121T50_0805

1

4

B++

B+

2

E NTRIP2

PR301
13.7K_0402_1%
1

1

PC316
0.1U_0402_25V6
2
1

PC302
0.22U_0603_10V7K

2

1

2

B++

1
2
G

D

3

1

D
PQ305
SSM3K7002FU_SC70-3

PC312
0.1U_0603_25V7K

3

2VREF_51125

E NTRIP2

E NTRIP1

3

S

PQ306
SSM3K7002FU_SC70-3

2
G

3

S

1

1

D

PR313
100K_0402_5%
2

1

+5VALWP

PJP301
2
2

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

1
P AD-OPEN 2x2m

P A D-OPEN 4x4m
PJP303

VL

PQ307
SSM3K7002FU_SC70-3
2
G

+3VL

+3VLP
PJP302

1

+3VALWP

2

+5VL

VL
PJP304

P A D-OPEN 4x4m

2

EC_ON <37>

1
P AD-OPEN 2x2m

1

3

S

2

PR314
100K_0402_5%

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

3.3VALWP/5VALWP
Size Do c ument Number
Cu s tom
C alpella

http://laptop-motherboard-schematic.blogspot.com/
B

C

D

Compal Electronics, Inc.

Da te:

Rev
0.1

DI S LA 4743P
Sheet

Monday, April 13, 2009
E

42

of

49

5

4

3

2

1

2

1
2

1

PC409
0.22U_0402_6.3V6K

VSS_AXG_SENSE

ISUM+
I SUM-

1 3

3
2
1

0_0603_5%

PR411
3.65K_0805_1%

4

PR412
0_0402_5%
PH401

2

PC419
2.2U_0603_6.3V6K

1

PQ402
T PCA8028_PSO8

VID2

C

0.56UH_MMD-10CZ-R56M-M1_19A_20%

2

20

2 + 5VALW

PR408
4.7_1206_5%

1

PR410

1

19

21

2

1

13

14

12
VIN

IMON

10

9

8

11
VDD

ISUM+

BOOT

18 DL_GFX

2 1

2

PR415
PC420
10KB_0603_5%_ERT J1VR103J
2.61K_0402_1%
680P_0603_50V7K

1 PR418

2

11K_0402_1%
PC423
0.1U_0402_16V7K

G F XVR_PWRGD

1

2

PC424
0.033U_0402_16V7K
PR423
3.01K_0402_1%
PR429
82.5_0402_1%

G F XVR_VID_0 <9>
G F XVR_VID_1 <9>
G F XVR_VID_2 <9>
G F XVR_VID_3 <9>
G F XVR_VID_4 <9>
G F XVR_VID_5 <9>
G F XVR_VID_6 <9>
G FXVR_EN <9>
G FXVR_DPRSLPVR <9>

2

PR421
PR422
PR425
PR426
PR427
PR428
PR430
PR431
PR432

PR424
100_0402_1%

1

2

1

B

1

1
1
1
1
1
1
1
1
1

2

PC425
0.01U_0402_16V7K

1

B

2
2
2
2
2
2
2
2
2

2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2

1

GFXVR_CLKEN#

1

2

PR417
8.06K_0402_1%

VID1

1

3

17

22

1

1

2

PR420
@10K_0402_1%

2

2

PR416
17.8K_0402_1%

1

2

PC421
150P_0402_50V8J

1

1

1 2

PR419
@1.91K_0402_1%

PC422
22P_0402_50V8J

2

CLK_EN#

VID3

+VGA_CORE

VID0

28

1
PC417
100P_0402_50V8J

PGOOD

VID4

1

23

2

24

2

VID5

2 1

25

1

VID6

1

VCCP

26

2
2

RBIAS

+VGA_CORE

PL402

4

1

2

LGATE

2 DH_GFX1

16 LX_GFX

2

PR409
47K_0402_1%

VSSP

VW

VR_ON

PC418
1000P_0402_50V7K

COMP

DPRSLPVR

PR414
825K_0402_1%

UGATE
PU401
ISL62881HRZ-T _QFN28_4X4 PHASE

1

4

PR407
0_0603_5%

15 D H_GFX 1

2

C

VSEN
FB

4

1

5

PQ401
AO4474_SO8

2

PC410
0.22U_0603_16V7K

5

6

1

3
2
1

7

PR413
8.66K_0402_1%

RTN

AGND

2

ISUM

PC413
330P_0402_50V7K

PC412
330P_0402_50V7K

27

2

2

PR405
2.2_0603_5%

29

1

PR406
+VGA_CORE 10_0402_5%

2

<9> VCC_AXG_SENSE

1

BST_GFX 1

2

PC411
1000P_0402_50V7K

1

1

<9> VSS_AXG_SENSE

2

2

D

G FXVR_IMON <9>

5
6
7
8

1

2

2

2

PC407
1U_0603_6.3V6M

PR404
10_0402_5%

PR403
22.6K_0402_1%

1 1

1
+ 5VALW 2
1_0603_5%

PC408
0.22U_0603_25V7K

PR402
0_0603_5%
PR401

1

1
2

PC406
0.1U_0402_25V6

1
2

PC403
10U_1206_25V6

1
2

PC402
10U_1206_25V6

1
2

D

PC401
1000P_0402_50V7K

CPU_B+

PC426
180P_0402_50V8J

ISUM+
I SUM-

A

A

Security Classification

Compal Secret Data
2008/10/31

Issued Date

Deciphered Date

2009/10/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title

VCCGFX
Size
D o cument Number
C u s tom Calpella DIS

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.

D ate:

R ev

LA4743P

Monday, April 13, 2009

Sheet
1

43

of

49

5

4

3

2

1

<9> VTT_SELECT
D

1

D

PR520
174K_0402_1%

PR517
0_0402_5%

1
PR501
26.7K_0402_1%

PR518
10_0402_5%
+1.1VTT

1

1

2

1

2

PR505
0_0402_5%

PR503
75K_0402_1%

PR504
29.4K_0402_1%

1

1

2

+1.05VSP

2

B+++

B+
PL502
HCB2012KF-121T50_0805

1

2

0_0402_5%

BST_1.1VTT

9

UG_1.1VTT

10

LX_1.1VTT

11

LG_1.1VTT

12

PR508

VBST2

VBST1

DR VH2

DR VH1

LL2

LL1
DR VL1

22

BST _1.05V

21

UG_1.05V

20

LX_1.05V

19

LG_1.05V

2

1

2

1
2

1
2

1000P_0402_50V7K
PC505

PC521
0.1U_0402_25V6

+1.05VSP

PL501
2.2UH_PCMC063T -2R2MN_8A_20%

1

2

1
PC508

PR516
4.7_1206_5%

18

T PS51124RGER_QFN24_4x4

1 2

4

+

2

2

PC519
680P_0603_50V7K

3
2
1

PR511
12.1K_0402_1%

220U_B2_2.5VM_R25M

1

PGND1

TRIP1

PQ503
FDMC8296_POWER33-8-5

B

2
1

PR512
0_0402_5%

1
1
1

2

2

SUSP#

+ 5VALW

PC515
4.7U_0805_10V6K

1

1
2

PC514
1U_0603_10V6K
PC513
@0.1U_0402_16V7K

PC512
@0.1U_0402_16V7K

2

1
2

PR514
3.3_0402_5%

1

2

2

2

+

<31,37,39,41,45> SUSP#
330U_X_2VM_R6M

PC522

1
330U_X_2VM_R6M

2

UG1_1.05V

PR509
0_0402_5%

PR513
0_0402_5%

1
PC517

1

1

1
2
3

PR510
14.7K_0402_1%

+ VCCP

2

PC507
0.1U_0402_10V7K

PR507
0_0402_5%

2

17

V5IN
16

V5FILT

PGND2
13

4

1

+

2

4

24
23

5

DR VL2

5

2

1
VO1

VFB1

3
GND

5

4

6

EN1

PQ504
T PCA8028_PSO8

1 2

PGOOD1

EN2

15

1

B

PC518
680P_0603_50V7K

2

330U_X_2VM_R6M

2

1

1
PR515
4.7_1206_5%

+

1

2

5

2

1 2

UG1_1.1VTT

PGOOD2

8

TRIP2

PL503
0.47UH_FDV0630-R47M-P3_18A_20%

PR506
0_0402_5%

14

1
2
3

+1.1VTT

PC523

7
PC506
0.1U_0402_10V7K

PQ501
AON7408L_DFN8-5

C

3
2
1

4

P PAD

TONSEL

2

25

VO2

PU501

PC524
@ 0.022U_0402_25V7K

VFB2

1

8
7
6
5
PQ502
AO4474_SO8

1

VT T PWRGOOD
PC503
10U_1206_25V6

<6>
C

1

1

1

2

2

1

0.1U_0402_25V6
PC520

2

1000P_0402_50V7K
PC502

1
2

2

1

PC511
10U_1206_25V6

PC501
4.7U_0805_25V6-K

B+++

2

PR502
10.5K_0402_1%

2

2

2

VT T _SENSE

<9> VTT_SENSE

PJP501
+1.05VSP

1

2

+1.05VS (6A,240mils

,Via NO.= 12)

P AD -OPEN 4x4m

A

A

PJP502
+1.1VTT

1

2

+ VCCP

(14A,240mils ,Via NO.= 28)

P AD -OPEN 4x4m

Security Classification

PJP503

1

2
P AD -OPEN 4x4m

5

Compal Secret Data
2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

1.1VTTP/1.1VSP
Size

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Compal Electronics, Inc.

D ate:

D o cument Number

R ev
0.1

Calpella DIS LA4743P
Monday, April 13, 2009

Sheet
1

44

of

49

5

4

3

2

1

D

D

+1.5V

VIN

VCNTL

GND

NC

VREF

NC

VOUT

NC

6

+5VALW

5

1

2

7
8

2

4

1

3
P R 601
1K_0402_1%

2

1
2

P C 602
@ 1 0U_0805_10V4Z

1
P C 601
1 0U_0805_10V4Z

2

P U 601

1

TP

P C 603
1U_0603_16V6K

9

C

2

+0.75VSP
1

1
S

2
G

P R 603
1K_0402_1%

2

2

1

1
P R 604
0_0402_5%

1

<39> SUSP

D

3

P Q601
S S M 3K7002FU_SC70-3

2

2

P R 602
@ 0_0402_5%

1

1

P C604
0.1U_0402_16V7K

G 2 9 92F1U_SO8

<39> SYSON#

P C 605
10U_0805_6.3V6M

C

2

P C 606
@ 0.1U_0402_16V7K

1

+ 5 VALW

1

6

2

<14,23,39,47> DGPU_PWR_EN

(2A,80mils ,Via NO.= 4)

+ 1.8VS

VOUT

1

1

+1.8VSP

3
2

1

FB
TP

9
P C616
22U_0805_6.3V6M

1

P C 617
0.01U_0402_16V7K

EN

B

P R 608
39.2K_0402_1%

4

1

2
P R 609
0_0402_5%

8

1

1

S U S P#

2

<31,37,39,41,44> SUSP#

GND

VOUT
P A D - O P EN 3x3m

P C613
@47P_0402_50V8J

2

POK

(1.5A,60mils ,Via NO.= 3)

P C615
10U_0805_10V6K

5

1

+ 1 .8VSP

2

VIN

P R 611
15K_0402_1%

P C 614
150P_0402_50V8J

1

2

A PL5915KAI-TRL_SO8

2

P JP602

1

2

P U 602

7

2

P A D - O P EN 3x3m
B

P C 612
22U_0805_6.3V6M

1

1
+ P C IE

A P L5913-KAC-TRL_SO8

2

2

P R 607
15K_0402_1%

P C 618
1U_0603_6.3V6M

6

1

VCNTL

+ 1 . 1V_PCIE

2

2

1

FB

+ 3VS
P JP603

+1.1V_PCIE

4

1

1

P C 611
@ 0.01U_0402_16V7K

+ 5 V ALW

P C 610
10U_0805_10V6K

3

1

(2A,80mils ,Via NO.= 4)

9

2

+ 0.75VS

VOUT

5

2

2
P A D - O P EN 3x3m

GND

1

EN

2

+ 0.75VSP

VIN
VOUT

2
P R 606
0_0402_5%

8

1
P JP601

VIN

2

POK

VCNTL

P U603

7

+ 1.5VS

P C 609
1U_0603_6.3V6M

2

P R 610
12K_0402_1%

A

A

Compal Secret Data

S ecurity Classification
Issued Date

2006/11/23

Deciphered Date

2007/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Title

Compal Electronics, Inc.
0.75VP/1.8VSP/1.1V_PCIE

Size

D o c u m ent Number

Rev
0 .1

Ca lp e lla DI S LA4 743P
D a te:

Monday, April 13, 2009

Sheet
1

45

of

49

4

3

5
6
7
8

PR206 0_0402_5%

2

PR207 0_0402_5%

2

PR2 81

1
1

2

BO O ST _ CPU2

PR208
0_0603_5%

PC210
0 .2 2 U_ 0603_10V7K

2

1

1

2

VGATE

1

2

PR222

0_0402_5%

1

H_ PSI#

1

3

2

+VCC_ CO RE

1

10K_0402_5%

2

PR216
1_0402_5%

VSUM-

1

T PCA8 0 2 8 - H_ SO P-ADVANCE8-5

@ PR221 1 K_ 0402_5%
+ VCCP

<9>

1

2
3
2
1

PR217
1 .9 1 K_0402_1%

2

F

2

5
4

2

1
<13,19>

L G AT E_ CPU2

2

PR2 19
0_0402_5%

CL K_ EN#

2

PC2 11
6 8 0 P_0603_50V7K

1

1

G

4

V 2N
PR2 11
4 .7 _1206_5%

PR212
1 .9 1K_0402_1%

1

CL K_ EN#

1

PL201

LF2
PQ203

<19>

2

0 .3 6 UH_ PCMC1 0 4 T - R36MN1R17_30A_20%

1

P HASE_ CPU2

2 PR290 1
@ 1 K_ 0402_1%
+3VS

PC206
1 0 U_1206_25V6

1

PC205
1 0 U_1206_25V6

2

1

PR213
0_0603_5%

2

UG AT E_ CPU2

PR2 15

<9> H_ DPRSL PVR

H

4

2

2

1K_0402_1% PR2 10 499_0402_1%

+

2

@

PR2 14
3 .6 5K_0603_1%

+VCCP

G

@

+

1

1

2

B+

1

2

1

1

V R_ O N

1

2

1

@

1

2

3
2
1

@

2

1

2

PQ202
AO 4 474_SO8

2

1

PR209 0_0402_5%
<37>

PR284
1
2
1K_0402_1%

H_ VID6

PR283
1
2
1K_0402_1%

H_ VID5

<9>

2

1

PR205 0_0402_5%

PR2185
2
1K_0402_1%

<9>

PR280
1
2
1K_0402_1%

H_ VID4

1

PR204 0_0402_5%
PR2186
2
1K_0402_1%

<9>

PR279
1
2
1K_0402_1%

H_ VID3

2

2

PR2187
2
1K_0402_1%

H_ VID2

<9>

2

1

1

PL202
HCB2 0 1 2KF-121T50_0805
PL205
HCB2 0 1 2KF-121T50_0805

PR203 0_0402_5%

PR2188
2
1K_0402_1%

<9>

1

PR202 0_0402_5%

@

PR2189
2
1K_0402_1%

H_ VID1

@

PR2175
2
1K_0402_1%

H_ VID0

<9>

PR2174
2
1K_0402_1%

<9>

PR278
1
2
1K_0402_1%

PR201 0_0402_5%
H

PR277
1
2
1K_0402_1%

PR276
1
2
1K_0402_1%
@

2

CPU_B+

PC202
1 0 0 U_25V_M

5

+VCCP

PC209
1 0 0 U_25V_M

6

PC204
1 0 0 0 P_0402_50V7K

7

PC203
0 .1 U_0402_25V6

8

IS EN2
VSUM+

F

2

PR2 82

2

1
1 K_ 0402_1%

1

2
PR223 1 4 7 K_0402_1%

2

PC221
2 2 P_ 0 402_50V8J

41

AGND

E

ISL 6 2 8 8 3 HRZ-T_QFN40_5X5

11
12
13
14
15
16
17
18
19
20
3 9 0 P_0402_50V7K

1

2

1

2

0_0402_5%
PR228

PR236
562_0402_1%PC2 24
PR239

VSUM+

2

1

1

2

2

PC2 49

1

1 0 KB_ 0 6 0 3 _ 5 %_ERTJ1VR103J

1
2

PC2 37
1 0 U_1206_25V6

1
10K_0402_5%

PR2 57
1_0402_5%

2

1
PR256

2

1
PR255
3 .6 5K_0603_1%

2
1

+VCC_ CO RE
V 1N

VSUMB

IS EN1
VSUM+

VSUM-

2

2

1

PR2 65

A

Iccmax= 35A
I_TDC=TDB
OCP=TDBA, Intel spec=TDBA
A

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

Title

http://laptop-motherboard-schematic.blogspot.com/
6

5

4

3

Compal Electronics, Inc.
+CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

7

2

100_0402_1%

21

1 2 0 0 P_0402_50V7K

8

1

3

2

1

1

3
2
1
1
PR261
0_0402_5%

PH2 0 2

2

5

1

1

T PCA8 0 2 8 - H_ SO P-ADVANCE8-5

4

4

2

2

LF1
PR253
4 .7 _1206_5%

PQ206

L G AT E_ CPU1

2

1

1

C

0 .3 6 UH_ PCMC1 0 4 T - R36MN1R17_30A_20%

2

2

PR251
2 .6 1K_0402_1%

1

0 .0 4 7 U_0603_16V7K

PC2 43 2

1

0 .2 2 U_0603_10V7K

PC2 42 2

@2 7 0 0P_0402_50V7K

PC241

PR250
82.5_0402_1%
0 .0 1 U_0402_25V7K

1
1

PR260
1 .1 K_0402_1%

PR262
1 1 K_0402_1%

0_0402_5%

4

P HASE_ CPU1

PC2 50
0 .1 U_ 0402_16V7K

1

2

PR2 63
<9> VSSSENSE

2

PC2 47
1 0 0 0 P_0402_50V7K

1

B

2

PC245
3 3 0 P_0402_50V7K

1
PC240
0 .2 2 U_ 0603_10V7K

PL204

PC2 44

0_0402_5%

PC248
3 3 0 P_0402_50V7K

PR252

V C CSENSE

1

>

2

2

1

2
PR2 48
0_0603_5%

2

UG AT E_ CPU1

C

PC2 36
1 0 U_1206_25V6

PQ205
AO 4 474_SO8
PR243
0_0603_5%

1

5
6
7
8
VSSSENSE

2

PR2 46
8 .2 5K_0402_1%

C PU_B+

PC2 35
1 0 0 0P_0402_50V7K

1

1
2

2

+5 VALW

PC246
6 8 0 P_0603_50V7K

1

0 .2 2 U_ 0402_10V4Z

1

2

D

2

2

1_0402_5%

BO O ST_ CPU1

PC232

IS EN1

0 .2 2 U_ 0402_10V4Z
PC233

1

1

<9>

1

PR2 44

IS EN2

IMVP_ IMO N

2

2
PR2 41
4 1 2 K_0402_1%

2

CPU_B+

PC2 34
0 .1 U_0402_25V6

2

2

1

1

0_0402_5%

PC229
0 .2 2 U_0603_25V7K

2

PC227
1 5 0 P_ 0402_50V8J

0_0402_5%

1
PR2 42

3
2
1

D

1

2

PR2 38
2 .4 3 K_0402_1%

1

1

2

2

PC228
1 U_ 0 603_10V6K

1

PC2 25
1 0 P_0402_50V8K

PC230
0 .2 2 U_0603_25V7K

1

PC222
1 0 0 0 P_0402_50V7K

1

2
2

1

PR235
8 .0 6 K_0402_1%

2

PR234 @
2 4 9 K_0402_1%

1

2

+5 VALW

1

E

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

2

PR225 0_0402_5%

1
30
29
28
27
26
25
24
23
22
21

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

1 U_ 0 603_10V6K

2
1
2
3
4
5
6
7
8
9
10

PC212
1 U_ 0 6 03_10V6K

PC223

1

<6> H_ PRO CHO T#

PU2 01

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

68_0402_5%

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

+VCCP

40
39
38
37
36
35
34
33
32
31

PR224

Size

Do cu me n t Number

Rev
0.1

Calpella DIS LA4743P
Da te:
2

Mo n d a y, April 13, 2009

Sheet

46
1

of

49

A

B

C

D

1

1

PR701
0_0402_5%

1

2

1

<14,23,39,45> DGPU_PWR_EN

PL701
HCB1608KF-121T30_0603

2

VGA_B+

14

1

PC707
4.7U_0805_10V6K

1
2

1
2

1
2

+

PR720
4.7_1206_5%

PQ702

2

1

D L _VGA

4
2

T PS51117RGYR_QFN14_3.5x3.5

2

+NVVDDP
1

N VVDD_PG <39>

3
2
1

PC716
680P_0603_50V7K

1

+ 5VALW

2

2

1

2

1

AO4714_SO8

PR713
10_0402_5%

2

PQ713A
2N7002KDW-2N_SOT363-6

PR718

PR711
75K_0402_1%

1

2

6

1
3

2

2

38.3K_0402_1%

1

+ N VVDD_SENSE

2
PR717
10K_0402_1%

GPU_VID1

PC715
0.022U_0402_16V7K

PR719
10K_0402_5%

GPU_VID0

+NVVDD

0

0.9V

0

1

0.85V

0

0

0.8V

1

2

2

2

76.8K_0402_1%

GPU_VID1 <24>

1

1
PR712

1

3

+NVVDDP

+NVVDD_SENSE

2

1

PR714
0_0402_5%

1

3
2
1

PL702
0.82UH_PCMC063T -R82MN_13A_20%

2

2

@1000P_0402_50V7K

D H _VGA_1

PR706
7.15K_0402_1%

9

DRVL

2
PR707
0_0402_5%

1

15
TP

1

PGOOD

PR721
0_0402_5%

2
PC713

1

1

1

10

V5DRV

1

6

PGND

PR708
5.11K_0402_1%

1

LX_VGA

11

TRIP

VFB

D H _ VGA

12

8

1

5

V5FILT

13

PC712
22U_0805_6.3V6M

PC702
1U_0603_10V6K

2

LL

PC711
22U_0805_6.3V6M

1

+VGA_COREP1

DRVH

VOUT

PC709
470U_D2_2VM_R4.5M

4

2

1

0_0402_5%

TON

4

2

3

PC705
2200P_0402_50V7K

2

PC706
0.1U_0402_10V7K

5
6
7
8

2

B+

PQ701
AON7408L_DFN8-5

VBST

2

1

7

PR703

EN_PSV

1
2

GND

2

PR705
255K_0402_1%

2

1
2
5

1+5VALW

PU701

2

PC710
1000P_0402_50V7K

PR702
316_0402_1%

+ N VVDDP

2 1

PR704
0_0402_5%

PC704
4.7U_0805_25V6-K

BST _VGA 1

2

PC703
4.7U_0805_25V6-K

PC708
@0.1U_0402_25V6

+ 5VALW

1

2

PC701
@1000P_0402_50V7K

1

2

1

4

5

GPU_VID0 <24>
1

3

PQ713B
2N7002KDW-2N_SOT363-6
PR715
10K_0402_1%

PC714
0.022U_0402_16V7K

2

2

PR716
10K_0402_5%

4

4

PJP701
+ N VVDDP

1

2

+ N VVDD

(11A,489mils ,Via NO.= 22)
Security Classification

P AD -OPEN 4x4m
PJP702

1

Issued Date

2
P AD -OPEN 4x4m
A

Compal Secret Data
2007/05/29

Deciphered Date

200810/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

http://laptop-motherboard-schematic.blogspot.com/
B

C

Title

Compal Electronics, Inc.
VGA_CORE

Size

D o cument Number

R ev
0.1

Calpella DIS LA4743P
D ate:

Sheet

Monday, April 13, 2009
D

47

of

49

A

B

C

D

1

1

PL902

PR901
0_0402_5%

HCB1608KF-121T30_0603
1.5V_B+

2

2

5

14
VBST

2

1

1

PR907 13.7K_0402_1%

PQ902
FDMC8296_POWER33-8-5

PR909
4.7_1206_5%

PC908
4.7U_0805_10V6K

4

1
3
2
1

2

8

7
+1.5VP

1

PR908

PC913
680P_0603_50V8J

+

2

1

T PS51117RGYR_QFN14_3.5x3.5

1

PC910
330U_B2_2.5VM_R15M

D L_1.5V

+1.5VP

4.7U_0805_6.3V6K

+ 5VALW

9

2

2

10

2

2

1

PC909

DRVL

0_0402_5%

LX_1.5V

11

V5DRV

PL901
2.2UH_PCMC063T -2R2MN_8A_20%

3
2
1

TP

1

15

EN_PSV

PGOOD

12

TRIP

VFB

1
PR905

LL

V5FILT

D H_1.5V_1

1

6

2

1

5
PC907
1U_0603_10V6K

2

13

DRVH

VOUT

2

1
4

D H _1.5V 4

1

3

PQ901
AON7408L_DFN8-5

0.1U_0402_10V7K

2

1

0_0402_5%

TON

PGND

2

2

GND

2
+1.5VP

2

2

B+

5

1+5VALW

PU901
PR904
255K_0402_1%

1
PR906

1

PR902
0_0402_5%

PR903
316_0402_1%
2

2

2

PC904
1000P_0402_50V7K

BST _1.5V
1

PC903
10U_1206_25V6

PC905

+ 5VALW

PC906
0.1U_0402_25V6

PC901
@ 1000P_0402_50V7K

1

1

1

2

2

1,37,38,39> SYSON

1

2

10.2K_0603_0.1%

1

OCP=9.8913(min)
MOSTemperature Factor=1.3 (100C)
PR911
10K_0603_0.1%

3

2

3

PJP901
+1.5VP

1

2

+1.5V

(6A,240mils ,Via NO.= 12)

P AD -OPEN 4x4m

4

4

Security Classification
Issued Date

Compal Secret Data
2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

http://laptop-motherboard-schematic.blogspot.com/
B

C

Title

Compal Electronics, Inc.
1.5VP

Size

D o cument Number

R ev
0.1

Calpella DIS LA4743P
D ate:

Sheet

Monday, April 13, 2009
D

48

of

49

A

B

C

D

E

Version Change List ( P. I. R. List ) for Power Circuit
Item Page#

Title

Date Request
Owner

Issue Description

Rev.

Solution Description

1

1

2

2

3

3

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

Size Do c ument Number
Cu s tom
C alpella

http://laptop-motherboard-schematic.blogspot.com/
B

C

D

Compal Electronics, Inc.
Power Changed-List History-1

Da te:

Rev
0.1

DI S LA 4743P
Sheet

Monday, April 13, 2009
E

49

of

49
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.5
Linearized                      : No
Encryption                      : Standard V5.5 (256-bit)
Warning                         : Incomplete Encrypt specification
EXIF Metadata provided by EXIF.tools

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