IDX80 La 3291
User Manual:
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Page Count: 53
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Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Cover Sheet
153Monday, January 08, 2007
Intel Merom Dual Core LV1.33G&1.5G
/Yonah Single Core ULV 1.06G&1.2G + Calistoga GM + ICH7-M
2007-01-08
REV: X0.5
PecosII Schematics Document
Project Name: PecosII
(IDX80)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PCB Serial Number:
LA-3291
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Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Block Diagram
253Monday, January 08, 2007
page 36
page 32
page 32
HD#[0..63]HA#[3..31] 533/667MHz
FSB
Merom Dual Core LV
/Yonah Single Core ULV
Gigabit Lan
88E8053
Transformer
& RJ45
479 uFCBGA CPU
Embedded Controller
CRT port
Intel Calistoga GM
ICH7-M
652 BGA
Block Diagram
1466 FCBGA
ROM DAUGHTER BOARD
SST39VF080
ENE KB910L
HDD 1.8"
DC-DC VCCP&
CPU_CORE
TPM
SLB9635TT
SDVO
LVDS port
page 24
page 17
page 18
page 34
page 32
page 35
page 25
page 28
page 6, 7, 8
page 9, 10, 11, 12, 13, 14
page 20, 21, 22, 23 page 24
page 33
SMSC
LPC47N217
Channel B
DDR2
Azalia Codec
STAC9220
AMP & HP &
MIC
page 30
page 31
USBPORT0
On M/B
USBPORT 5
USBPORT 6
USBPORT 7
On M/B
USBPORT 1
USBPORT 2
page 37 page 46
page 6
page 5
page 6
Fan Control x1
Digitizer FIR
PCIE BUS
PCI Bus
3.3V 33MHz
DMI x4 1.5V
page 29
USB 2.0 48MHz/480Mb
Azalia 3.3V
PATA100
CPU Thermal Sensor
G781F
Clock Generator
ICS9LPRS325AKLF
Docking
CRT
page 19
CRT CONN.
LVDS CONN.
Hydis
LCD 12.1"
XGA/SXGA+
DVI Controller
CH7307
Channel A
DDR2
1.8V 533/667MHz
Mini Card
WWAN
CardBus
R5C843 3.3V 33MHz
LPC Bus
X Bus
page 18
DVI CONN
Docking
HP&MIC
page 36
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCIE x1
SO-DIMM x 1
4 BANK page 15
SO-DIMM x 1
4 BANK page 16
Mini Card
WLAN
page 24
USBPORT 3 Finger Printer
page 36
USB 2.0
Controller
page 27
Port 0
Port 1
Port 2
USBPORT 4
page 26
SD Socket
page 36
Docking
RJ45
page 26
PCMCIA Slot
page 36
LLANO DOCK
page 36
LLANO DOCK
page 36
LLANO DOCK
page 24
WLAN
Bluetooth
page 27
Travel DOCK
page 36
WWAN page 24
CardBus
page 25
PCIE BUS
express
cardpage 26
page 24
SIM
card
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Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Notes&Revision
353Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Voltage Rails
B+
1.5V switched power rail for PCI-E interface
1.8V switched power rail+1.8VS ON
VIN
+3VS 3.3V switched power rail
3.3V always on power rail
ON
5V always on power rail
2.5V switched power rail for MCH video PLL
ON
+1.5VS
+0.9VS
+VCC_CORE
AC or battery power rail for power circuit
ON
N/A
Power Plane
+VCCP
ON
N/A
12V always on power rail
+1.8V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ONRTC power
ON
+5VS
RTCVCC
+2.5VS
5V switched power rail
ON
+3VALW
ON
ON
S0-S1
0.9V switched power rail for DDRII Vtt
ON
Description
1.05V power rail for Processor I/O and MCH core power
ON
ON
Adapter power supply (19V)
1.8V power rail for DDRII
+5VALW
+12VALW
Core voltage for CPU
OFF
ON*
OFF
ON
OFF
OFF
ON
OFF
ON
ON
OFF
ON ON*
ON ON*
OFF
OFF OFF
OFF
N/A
S3
OFFOFF
N/A
N/A
OFF
N/A
OFF
OFF
OFFOFF
S5
IDSEL #
2 A,BCARD BUS
DEVICE
External PCI Devices
REQ/GNT #
AD20
PIRQ
+VCCP
+3VS
OFFOFF
S1
ON note1
+5VS
+1.5VS
+CPU_CORE
ONONS0
OFF
S3
+12VALW
Power Management table
S5 S4/AC don't exist
ON
State
OFF
ON note1 ON
+5VALW
ON ON
S5 S4/AC
+3VALW
+0.9VS
+2.5VS
+1.8V
OFF
Signal +1.8VS
ON
OFF
Symbol Note
: Question Area Mark.(Wait check)
: means Digital Ground
: means Analog Ground
@: means don't stuff, just reserve
DB@: means jsut stuff when Mini-PCI E Debug card function enable
DVI_7307@: means just stuff when use CH7307 controller
DVI_1362@: means just stuff when use Sil1362 controller
9220@: means just populate when mount 9220 on board;
depopulate when mount 9228 on board
AD21USB controller 0E,F,G
9228@: means just populate when mount 9228 on board;
depopulate when mount 9220 on board
LV@: means just populate when mount Merom/Yonah LV DC CPU on board;
depopulate when mount Yonah ULV SC CPU on board
+3V_LAN 3.3V LAN power rail ON ON*
Buffer@: means just populate when buffer generate V_DDR_MCH_REF;
depopulate when 1.8V divider generate V_DDR_MCH_REF
1.8_divider@: means just populate when 1.8V divider generate V_DDR_MCH_REF;
depopulate when buffer generate V_DDR_MCH_REF
ON*
+3V_LAN
Note1 : +3V_LAN is ON only with AC power available, otherwise it is OFF.
1@: means just populate 0ohm resistors on board;
2@: means just populate MAX9890 & related components on board;
3220@: means populate 0ohm resistors when mount Agilent 3220,unpopulate 0ohm resistors when mount other
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Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Power rail
453Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MAX8770
MAX1908
CHARGER
MAX1538
BATTERY SELECTOR
B+
VS
FSTCHG
BATSELB_A#
ACIN
MAINPWRON
LDO
G965
BRIDGE BATTERY
SUSP#P
RTC BATT
+2.5VSP
+3VS +5VS
+3VALW +5VALW +12VALW
SYSON
SUSP#
DOCK_IN
+1.5VSP
BATT+
A OR B BATTERY
APL5331
+0.9VSP
VCCP_ON#
+VCCP
LDO
XC61CN
+VCCP_OK
SUSP
+1.8VP
+1.8VS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
H_DPRSLPVR
H_DPRSTP#
H_PSI#
VR_ON
VGATE
CLK_ENABLE#
H_PROCHOT#
+VCC_CORE
SUSP
SUSP#
EC_ON#
A OR B BATTERYA OR B BATTERY
RTC_VREF
BATT+
VIN
VSB
POWER SOURCE
CHARGER SOURCE
FSTCHG
IREF
G920AT24U
ADAPTER
DOCK
A BATTERY
B BATTERY
MAX1902 MAX8743 ISL6269
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FSLC
FSLB
CLK_ENABLE#
FSLA
SEL_24M
H_STP_PCI#
CLK_ENABLE#
CLK_14M_SIO SEL_PCI5
H_STP_CPU#
+CK_VDD_48
+CK_VDD_REF
+CK_VDD_48
CLK_PCI_PCM FCTSEL1
ITP_EN
CLKREQB#
CLK_48M_ICH
FCTSEL1
CLKREQA#
ITP_ENCLK_PCI_ICH
SEL_PCI6
DOCTC
DREFCLK
DREFCLK#
DOCTT
+CK_VDD_REF
SEL_PCI6CLK_PCI_SIO
FSLB
FSLCCLK_14M_ICH
CLK_PCI_EC SEL_48M
CLK_PCI_USB
SEL_24M
FSLA
CLK_48M_USB
SEL_48M
ICS_48MHz CLK_48M_SD
CLKREQC#
PCICLK6 CLK_DEBUG_PORT
CLK_PCI_TPMPCICLK5
CLK_CPU_BCLK
CLK_CPU_BCLK#
CK_CPU
CK_CPU#
CLK_MCH_BCLK#CK_MCH#
CLK_CPU_XDP
CLK_CPU_XDP#
CK_ITP
CK_ITP#
CLK_PCIE_WAN#
CLK_PCIE_WAN
CK_SRC9#
CK_SRC9
CLK_PCIE_MINI#
CLK_PCIE_MINI
CK_SRC8#
CK_SRC8
CLK_MCH_3GPLL#
CLK_MCH_3GPLL
CK_SRC4#
CK_SRC4
CLK_PCIE_ICH
CK_SRC3#
CK_SRC3
CLK_PCIE_ICH#
CLK_PCIE_LAN
CLK_PCIE_LAN#CK_SRC2#
CK_SRC2
DREF_SSCLK
DREF_SSCLK#
CK_SRC0
CK_SRC0#
CLK_MCH_BCLKCK_MCH
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK#
CLK_CPU_XDP
CLK_CPU_XDP#
CLK_PCIE_WAN
CLK_PCIE_WAN#
CLK_PCIE_MINI
CLK_PCIE_MINI#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DREF_SSCLK
DREF_SSCLK#
DREFCLK
DREFCLK#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_MCH_BCLK
ICH_SMBDATA
ICH_SMBCLK
SEL_PCI5
+CK_VDD_DP
+CK_VDD_MAIN2
+3VS
+CK_VDD_MAIN1
+3VS
+VCCP
+VCCP
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+VCCP
+3VS
+CK_VDD_MAIN1
+CK_VDD_DP
+3VS
+3VS
+3VS
+3VS
CPU_BSEL0<7>
CPU_BSEL1<7>
CPU_BSEL2<7>
CLK_ENABLE#<46>
MCH_CLKSEL0 <9>
H_STP_PCI# <22>
H_STP_CPU# <22>
CLK_PCI_PCM<25>
CLKREQB# <24>
CLK_PCI_TPM <32>
MCH_CLKSEL1 <9> CLK_14M_SIO<35>
MCH_CLKSEL2 <9>
CLK_48M_ICH<22>
CLKREQA# <24>
CLK_PCI_ICH<20>
CLK_PCI_EC<33>
DREFCLK<9>
DREFCLK#<9>
CLK_PCI_SIO<35>
CLK_14M_ICH<22>
CLK_PCI_USB<27>
CLK_48M_USB<27>
CLK_48M_SD <25>
CLKREQC# <9>
CLK_DEBUG_PORT <24>
CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>
CLK_MCH_BCLK# <9>
CLK_CPU_XDP# <6>
CLK_CPU_XDP <6>
CLK_PCIE_WAN# <24>
CLK_PCIE_WAN <24>
CLK_PCIE_MINI# <24>
CLK_PCIE_MINI <24>
CLK_MCH_3GPLL# <9>
CLK_MCH_3GPLL <9>
CLK_PCIE_ICH# <22>
CLK_PCIE_ICH <22>
CLK_PCIE_LAN# <28>
CLK_PCIE_LAN <28>
DREF_SSCLK# <9>
DREF_SSCLK <9>
CLK_MCH_BCLK <9>
ICH_SMBDATA<6,15,16,22,24>
ICH_SMBCLK<6,15,16,22,24>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Clock Generator
553Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Pin28/29 function select
CLK_Rc
CLK_Rb
CLK_Rf
CLK_Re
100
1
CLKSEL1
0
100
0
0
133
PCI
MHz
33.3
SRC
MHz
CPU
MHz
33.3
CLKSEL2
1
FSLA
Pin5/6 function select
CLKSEL0
ITPEN: 0 SRC10 Pair ,
1 CPU_ITP Pair
166
FSLB
1
FSLC
CLK_Rd
CLK_Rc
Stuff
CLK_Rf
CLK_Re
CLK_Ra
CLK_Ra
CLK_Re
Stuff
FSB Frequency Selet:
533MHz
CLK_Rb
No Stuff
No Stuff
CLK_Rf
CLK_Rd
CLK_Re
CLK_Rc
CLK_Rf
CLK_Rc
CLK_Rd
No Stuff
CLK_Ra
CPU Driven Stuff
CLK_Rb
CLK_Rd
*
667MHz
CLK_Rb
(Default)
CLK_Ra
Pin 43/44,47/48 function select
SEL_PCI5/6: 0 CLKREQ5/6#,
1 PCICLK5/6
FCTSEL1: 0 DOT96/LCD100 *
1 27M/SRC0
Pin45 function select
SEL_24M: 0 Test mode ,
1 24MHz
Pin38 function select
SEL_48M: 0 CLKREQ7 ,
1 48MHz output
R97 49.9_0402_1%
@12
R482
1K_0402_5%
12
R71 0_0402_5%
1 2
R65 0_0402_5%
1 2
R43 0_0402_5%
1 2
R506
300_0402_5%
12
R72 0_0402_5%
1 2
R67 0_0402_5%
1 2
R99 49.9_0402_1%
@12
R22 12_0402_5%
12
R103 49.9_0402_1%
@12
R44 0_0402_5%
1 2
R101 49.9_0402_1%
@12
R502
10K_0402_5%
DB@
12
R105 49.9_0402_1%
@12
R56 0_0402_5%
1 2
R108 49.9_0402_1%
@12
R112 49.9_0402_1%
@12
R45833_0402_5%
12
C385
0.1U_0402_16V4Z
1
2
R66 0_0402_5%
1 2
R504
10K_0402_5%
12
R49333_0402_5%
12
R46933_0402_5%
12
R44933_0402_5%
12
R69 0_0402_5%
1 2
R55 0_0402_5%
1 2
C387
0.1U_0402_16V4Z
1
2
R464
1K_0402_5%
1 2
C393
0.1U_0402_16V4Z
1
2
R498
10K_0402_5%
12
R68 0_0402_5%
1 2
R500
10K_0402_5%
@
12
C391
10U_0805_10V4Z
1
2
Y1
14.31818MHZ_20P_6X1430004201
12
C389
0.1U_0402_16V4Z
1
2
C397 0.1U_0402_16V4Z
1 2
R505
10K_0402_5%
12
R442
8.2K_0402_5%
12
R63 0_0402_5%
1 2
R460
1K_0402_5%
12
C386
0.1U_0402_16V4Z
1
2
R109 49.9_0402_1%
@12
R499
10K_0402_5%
1 2
R113 49.9_0402_1%
@12
R450
1K_0402_5%
12
R21 12_0402_5%
12
C392
0.1U_0402_16V4Z
1
2
R62 0_0402_5%
1 2
L14
FBMA-L11-201209-221LMA30T_0805
1 2
U46
ICS9LPRS325CKLFT_MLF72
VDDSRC
1
VDDSRC
49
VDDSRC
65
VDDPCI
30
VDDPCI
36
VDD48
40
VDDCPU
12
VDDREF
18
USB_48MHz/FSLA
41
FSLB/TEST_MODE/24Mhz
45
X2
19
X1
20
GNDPCI
31
SEL_24M/PCICLK2
32
REF0/FSLC/TEST_SEL
23
SMBDAT
17
SMBCLK
16
ITP_EN/PCICLK_F0
37
GND
9
CPU_STOP# 24
CPUCLKT1LP 11
CPUCLKC1LP 10
CPUCLKT2_ITP/SRCCLKT10LP 6
SEL_48M/PCICLK3
33
PCICLK4/FCTSEL1
34
CPUCLKC0LP 13
CPUCLKT0LP 14
PCI_SRC_STOP# 25
GNDA 8
VDDA 7
GNDPCI
35
CPUCLKC2_ITP/SRCCLKC10LP 5
GNDREF
21
GNDCPU
15
GNDSRC
4
GND48
42
GNDSRC
68
DOTT_96MHz/27MHz_Nonspread
43
DOTC_96MHz/27MHz_spread
44
VTT_PWRGD#/PD
39
SEL_PCI5/REF1
22 SRCCLKT7LP 66
SRCCLKC7LP 67
SRCCLKT8LP 70
SRCCLKC8LP 69
SRCCLKT9LP 3
SRCCLKC9LP 2
SRCCLKC1LP 51
LCD100/96/SRC0_TLP 47
SRCCLKT2LP 52
SRCCLKT4LP 58
SRCCLKT1LP 50
CLKREQ4# 57
SRCCLKC2LP 53
SRCCLKC5LP 61
SRCCLKC4LP 59
SRCCLKT5LP 60
LCD100/96/SRC0_CLP 48
SRCCLKC3LP 56
SRCCLKT3LP 55
SRCCLKT6LP 63
SRCCLKC6LP 64
CLKREQ6# 62
CLKREQ8# 71
CLKREQ9# 72
CLKREQ1# 46
CLKREQ5#/PCICLK6 29
CLKREQ3#/PCICLK5 28
CLKREQ2# 26
CLKREQ7#/48Mhz_1 38
VDDSRC
54
SEL_PCI6/PCICLK1
27
THRM_PAD
73
THRM_PAD
74
THRM_PAD
75
THRM_PAD
76
R466
0_0402_5%
1 2
R51 0_0402_5%
1 2
R463 10K_0402_5%
12
R448 10K_0402_5%
12
R487
8.2K_0402_5%
12
R476 33_0402_5% DB@
12
L15
FBMA-L11-201209-221LMA30T_0805
1 2
C388
10U_0805_10V4Z
1
2
R483 10K_0402_5%
12
C395 22P_0402_50V8J
1 2
R102 49.9_0402_1%
@12
R98 49.9_0402_1%
@12
R439
56_0402_5%
@
12
R100 49.9_0402_1%
@12
R104 49.9_0402_1%
@12
R471
0_0402_5%
@
12
R106 49.9_0402_1%
@12
R495
0_0402_5%
@
12
R110 49.9_0402_1%
@12
R443
1K_0402_5%
1 2
R47433_0402_5%
12
R52 0_0402_5%
1 2
R114 49.9_0402_1%
@12
R447
0_0402_5%
1 2
R46233_0402_5%
12
R47533_0402_5%
12
R501
10K_0402_5%
@
12
L19
FBMA-L11-201209-221LMA30T_0805
1 2
R532
10K_0402_5%
12
C396 22P_0402_50V8J
1 2
R430
1_0805_1%
1 2
R477 33_0402_5%
12
R4890_0402_5% 12
R488
1K_0402_5%
1 2
L4
FBMA-L11-201209-221LMA30T_0805
1 2
R53 0_0402_5%
1 2
C390
0.1U_0402_16V4Z
1
2
C399 0.1U_0402_16V4Z
1 2
R431
2.2_0805_1%
1 2
R503
10K_0402_5%
@
12
R96 49.9_0402_1%
@12
C394
0.1U_0402_16V4Z
1
2
R64 0_0402_5%
1 2
R107 49.9_0402_1%
@12
C415 0.1U_0402_16V4Z
1 2
R486
0_0402_5%
12
R111 49.9_0402_1%
@12
J1
NO SHORT PADS
12
R491
0_0402_5%
1 2
R54 0_0402_5%
1 2
R115 49.9_0402_1%
@12
R459 33_0402_5%
1 2
C384
10U_0805_10V4Z
1
2
R497
10K_0402_5%
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_D#47
H_D#46
H_D#44
H_D#45
H_D#51
H_D#50
H_D#48
H_D#49
H_SMI#
H_STPCLK#
H_D#55
H_D#54
H_D#52
H_D#53
H_D#59
H_D#58
H_D#56
H_D#57
H_D#63
H_D#62
H_D#60
H_D#61
CLK_CPU_BCLK
H_THERMDA
H_THERMTRIP#
H_THERMDC
CLK_CPU_BCLK#
XDP_BPM#3
ICH_SMBDATA
ICH_SMBCLK
XDP_BPM#2
XDP_DBRESET#_R
XDP_BPM#1
XDP_BPM#0
XDP_PRE
XDP_DBRESET#XDP_DBRESET#_R
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_TCK
XDP_TDO
XDP_TRST#
XDP_TMS
XDP_TDI
XDP_TDO
H_RESET#H_RESET#_R
H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDP
CLK_CPU_XDP#
XDP_BPM#4
XDP_BPM#5
XDP_BPM#5
H_IERR#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
XDP_BPM#0
XDP_BPM#2
XDP_BPM#3
XDP_BPM#1
XDP_TCK
XDP_TRST#
TEST1
XDP_TMS
H_CPUSLP#
XDP_TDO
TEST2
XDP_TDI
H_PWRGOOD
XDP_BPM#5
XDP_BPM#4
H_DPWR#
H_D#0
H_D#1
H_D#2
H_D#3
H_D#7
H_D#6
H_D#4
H_D#5
H_D#11
H_D#10
H_D#8
H_D#9
H_DSTBN#2
H_DSTBP#2
H_INTR
H_DSTBN#1
H_DSTBP#1
H_INIT#
H_DSTBP#0
H_DSTBN#0
H_A20M#
H_IGNNE#
H_DSTBN#3
H_FERR#
H_DSTBP#3
H_NMI
H_D#15
H_D#14
H_D#12
H_D#13
H_D#19
H_D#18
H_D#16
H_D#17
H_RS#1
H_A#30
H_A#27
H_A#18
H_A#3
H_A#10
H_BNR#
H_HITM#
H_BR0#
H_LOCK#
H_A#11
XDP_DBRESET#
H_A#21
H_A#17
H_A#26
H_A#13
H_A#9
H_ADS#
H_A#7
H_ADSTB#0
H_A#25
H_DPSLP#
H_A#20
H_A#16
H_A#8
H_A#6
H_A#12
H_HIT#
H_TRDY#
H_A#28
H_A#29
H_ADSTB#1
H_A#23
H_REQ#0
H_RS#0
H_BPRI#
H_DBSY#
H_A#19
H_REQ#2
H_REQ#4
H_A#15
H_A#24
H_A#5
H_DRDY#
H_RS#2
H_A#14
H_D#23
H_D#22
H_D#20
H_D#21
H_A#31
H_REQ#1
H_A#4
H_A#22
H_RESET#
H_REQ#3
H_DPRSTP#
H_D#27
H_D#26
H_D#24
H_D#25
H_D#31
H_D#30
H_D#28
H_D#29
H_D#35
H_D#34
H_D#32
H_D#33
H_D#39
H_D#38
H_D#36
H_D#37
H_D#43
H_D#42
H_D#40
H_D#41
H_DEFER#
H_PROCHOT#
PROCHOT#
THERM#
H_THERMDA
H_THERMDC
SMB_EC_CK2
SMB_EC_DA2
H_PROCHOT#
+VCCP
+3VS
+VCCP +VCCP
+VCCP
+5VS
+5VS
+3VS
+VCCP
+3VS
+3VS
H_A#[3..31]<9> H_D#[0..63] <9>
H_ADS#<9>
H_REQ#[0..4]<9>
H_ADSTB#0<9> H_ADSTB#1<9>
CLK_CPU_BCLK<5> CLK_CPU_BCLK#<5>
H_BNR#<9> H_BPRI#<9> H_BR0#<9> H_DEFER#<9> H_DRDY#<9> H_HIT#<9> H_HITM#<9>
H_LOCK#<9> H_RESET#<9>
H_TRDY#<9>
H_RS#[0..2]<9>
XDP_DBRESET#<22> H_DBSY#<9> H_DPSLP#<21> H_DPRSTP#<21,46> H_DPWR#<9>
H_PWRGOOD<21> H_CPUSLP#<9,21>
H_THERMTRIP#<9,21>
H_DINV#0 <9>
H_DINV#1 <9>
H_DINV#2 <9>
H_DINV#3 <9>
H_DSTBN#[0..3] <9>
H_DSTBP#[0..3] <9>
H_A20M# <21>
H_IGNNE# <21>
H_INIT# <21>
H_INTR <21>
H_NMI <21>
H_STPCLK# <21>
H_SMI# <21>
CLK_CPU_XDP# <5>
CLK_CPU_XDP <5>
FAN_SPEED1<33>
FAN_PWM<33>
PROCHOT# <33>
H_PROCHOT#<46>
SMB_EC_CK2<24,33,36,39>
SMB_EC_DA2<24,33,36,39>
ICH_SMBDATA<5,15,16,22,24>
ICH_SMBCLK<5,15,16,22,24>
H_FERR# <21>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Yonah1/2-GTL/ITP
653Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ITP-XDP Connector
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
This shall place near CPU
Thermal Sensor G781F
In order to for Yonah B-0 silicon to boot,
due to issue in the reset sequence. needed
for processor.
Place U2 near the top and LCD side
for using it's local thermal sensor to
monitor the LCD back side temperature
JP2
SAMTE_BSH-030-01-L-D-A
@
GND0
1
OBSFN_A0
3
OBSFN_A1
5
GND2
7
OBSDATA_A0
9
OBSDATA_A1
11
GND4
13
OBSDATA_A2
15
OBSDATA_A3
17
GND6
19
OBSFN_B0
21
OBSFN_B1
23
GND8
25
OBSDATA_B0
27
OBSDATA_B1
29
GND10
31
OBSDATA_B2
33
OBSDATA_B3
35
GND12
37
PWRGOOD/HOOK0
39
HOOK1
41
VCC_OBS_AB
43
HOOK2
45
HOOK3
47
GND14
49
SDA
51
SCL
53
TCK1
55
TCK0
57
GND16
59
GND1 2
OBSFN_C0 4
OBSFN_C1 6
GND3 8
OBSDATA_C0 10
OBSDATA_C1 12
GND5 14
OBSDATA_C2 16
OBSDATA_C3 18
GND7 20
OBSFN_D0 22
OBSFN_D1 24
GND9 26
OBSDATA_D0 28
OBSDATA_D1 30
GND11 32
OBSDATA_D2 34
OBSDATA_D3 36
GND13 38
ITPCLK/HOOK4 40
ITPCLK#/HOOK5 42
VCC_OBS_CD 44
RESET#/HOOK6 46
DBR#/HOOK7 48
GND15 50
TD0 52
TRST# 54
TDI 56
TMS 58
GND17 60
R522 51_0402_5%
1 2
R511 56_0402_5%
1 2
R513 56_0402_5%
1 2
C
B
E
Q2
2SC2411KT146_SOT23
1
2
3
R525
100_0402_1%
1 2
JP3
MOLEX_53780-0310
1
1
2
2
3
3
R521 1K_0402_5%
@
1 2
C404
10U_0805_10V4Z
1
2
R515
1K_0402_1%
1 2
D1
CH355PT_SOD323
2 1
G
D
S
Q1
FDN359AN_NL_SOT23
2
13
C401 0.1U_0402_16V4Z
12
R507 1K_0402_5%
@
1 2
R518
10K_0402_5%
@
12
R519
56_0402_5%
1 2
U2
G781F_SOP8
VDD1 1
ALERT# 6
THERM# 4
GND 5
D+
2
D-
3
SCLK
8
SDATA
7
R516
200_0402_1%
12
C402
0.1U_0402_16V4Z
1
2
R523 10K_0402_5%
@
1 2
R514
1K_0402_5%
12
R527
56_0402_5%
12
C405
0.1U_0402_16V4Z
1
2
R512 56_0402_5%
1 2
R954
68_0402_5%
12
ADDR GROUP
CONTROL
HOST CLK
MISC
DATA GROUP
THERMAL
DIODE
LEGACY CPU
YONAH-ULV
U8A
YONAH-ULV_FCBGA479~D
A3#
J4
A4#
L4
A5#
M3
A6#
K5
A7#
M1
A8#
N2
A9#
J1
A10#
N3
A11#
P5
A12#
P2
A13#
L1
A14#
P4
A15#
P1
A16#
R1
A17#
Y2
A18#
U5
A19#
R3
A20#
W6
A21#
U4
A22#
Y5
A23#
U2
A24#
R4
A25#
T5
A26#
T3
A27#
W3
A28#
W5
A29#
Y4
A30#
W2
A31#
Y1
REQ0#
K3
REQ1#
H2
REQ2#
K2
REQ3#
J3
REQ4#
L5
ADSTB0#
L2
ADSTB1#
V4
BCLK0
A22
BCLK1
A21
ADS#
H1
BNR#
E2
BPRI#
G5
BR0#
F1
DEFER#
H5
DRDY#
F21
HIT#
G6
HITM#
E4
IERR#
D20
LOCK#
H4
RESET#
B1
RS0#
F3
RS1#
F4
RS2#
G3
TRDY#
G2
BPM0#
AD4
BPM1#
AD3
BPM2#
AD1
BPM3#
AC4
DBR#
C20
DBSY#
E1
DPSLP#
B5
DPWR#
D24
PRDY#
AC2
PREQ#
AC1
PROCHOT#
D21
PWRGOOD
D6
SLP#
D7
TCK
AC5
TDI
AA6
TDO
AB3
TEST1
C26
TEST2
D25
TMS
AB5
TRST#
AB6
THERMDA
A24
THERMDC
A25
THERMTRIP#
C7
D0# E22
D1# F24
D2# E26
D3# H22
D4# F23
D5# G25
D6# E25
D7# E23
D8# K24
D9# G24
D10# J24
D11# J23
D12# H26
D13# F26
D14# K22
D15# H25
D16# N22
D17# K25
D18# P26
D19# R23
D20# L25
D21# L22
D22# L23
D23# M23
D24# P25
D25# P22
D26# P23
D27# T24
D28# R24
D29# L26
D30# T25
D31# N24
D32# AA23
D33# AB24
D34# V24
D35# V26
D36# W25
D37# U23
D38# U25
D39# U22
D40# AB25
D41# W22
D42# Y23
D43# AA26
D44# Y26
D45# Y22
D46# AC26
D47# AA24
D48# AC22
D49# AC23
D50# AB22
D51# AA21
D52# AB21
D53# AC25
D54# AD20
D55# AE22
D56# AF23
D57# AD24
D58# AE21
D59# AD21
D60# AE25
D61# AF25
D62# AF22
D63# AF26
DINV0# J26
DINV1# M26
DINV2# V23
DINV3# AC20
DSTBN0# H23
DSTBN1# M24
DSTBN2# W24
DSTBN3# AD23
DSTBP0# G22
DSTBP1# N25
DSTBP2# Y25
DSTBP3# AE24
A20M# A6
FERR# A5
IGNNE# C4
INIT# B3
LINT0 C6
LINT1 B4
STPCLK# D5
SMI# A3
DPRSTP#
E5
C406 1000P_0402_50V7K
1 2
R509 56_0402_1%
1 2
C403
2200P_0402_50V7K
1
2
R526
1K_0402_5%
12
R524 8.2K_0402_5%
1 2
R510 56_0402_5%
1 2
R508 56_0402_5%
1 2
R517 0_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VSSSENSE
VCCSENSE
COMP2
COMP1
CPU_VID2
COMP3
CPU_VID6
CPU_VID3
CPU_BSEL0
CPU_VID4
CPU_BSEL2
VCCSENSE
CPU_BSEL1
CPU_VID0
VSSSENSE
CPU_VID5
COMP0
H_PSI#
CPU_VID1
+VCCP
+VCC_CORE
+VCCP
V_CPU_GTLREF
V_CPU_GTLREF
+1.5VS
+VCC_CORE
+VCC_CORE
CPU_BSEL0<5>
VCCSENSE<46> VSSSENSE<46>
CPU_BSEL1<5> CPU_BSEL2<5>
H_PSI#<46>
CPU_VID0<46> CPU_VID1<46> CPU_VID2<46> CPU_VID3<46> CPU_VID4<46> CPU_VID5<46> CPU_VID6<46>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Yonah2/2-PWR/GND
753Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Close to CPU pin AD26
within 500mils.
Length match within 25 mils
The trace width 18 mils space
7 mils
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
00
0
1
CPU_BSEL0
1
1
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.
Close to CPU pin
within 500mils.
C407
0.01U_0402_16V7K
1
2
R534
54.9_0402_1%
12
R533
27.4_0402_1%
12
POWER, GROUND
YONAH-ULV
U8C
YONAH-ULV_FCBGA479~D
VCC
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7
VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VSS K1
VSS J2
VSS M2
VSS N1
VSS T1
VSS R2
VSS V2
VSS W1
VSS A26
VSS D26
VSS C25
VSS F25
VSS B24
VSS A23
VSS D23
VSS E24
VSS B21
VSS C22
VSS F22
VSS E21
VSS B19
VSS A19
VSS D19
VSS C19
VSS F19
VSS E19
VSS B16
VSS A16
VSS D16
VSS C16
VSS F16
VSS E16
VSS B13
VSS A14
VSS D13
VSS C14
VSS F13
VSS E14
VSS B11
VSS A11
VSS D11
VSS C11
VSS F11
VSS E11
VSS B8
VSS A8
VSS D8
VSS C8
VSS F8
VSS E8
VSS G26
VSS K26
VSS J25
VSS M25
VSS N26
VSS T26
VSS R25
VSS V25
VSS W26
VSS H24
VSS G23
VSS K23
VSS L24
VSS P24
VSS N23
VSS T23
VSS U24
VSS Y24
VSS W23
VSS H21
VSS J22
VSS M22
VSS L21
VSS P21
VSS R22
VSS V22
VSS U21
VSS Y21
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
F7 VCC
A7
R530
100_0402_1%
1 2
R528
2K_0402_1%
12
R531
100_0402_1%
1 2
R529
1K_0402_1%
12
POWER, GROUNG, RESERVED SIGNALS AND NC
YONAH-ULV
U8B
YONAH-ULV_FCBGA479~D
PSI#
AE6
GTLREF
AD26
VCCSENSE
AF7
VCCA
B26
VCC
AB20
VCC
AA20
VCC
AF20
VCC
AE20
VCC
AB18
VCC
AB17
VCC
AA18
VCC
AA17
VCC
AD18
VCC
AD17
VCC
AC18
VCC
AC17
VCC
AF18
VCC
AF17
RSVD
T22
RSVD
V3
RSVD
B2
RSVD
C3
VSS AB26
VSS AA25
VSS AD25
VSS AE26
VSS AB23
VSS AC24
VSS AF24
VSS AE23
VSS AA22
VSS AD22
VSS AC21
VSS AF21
VSS AB19
VSS AA19
VSS AD19
VSS AC19
VSS AF19
VSS AE19
VSS AB16
VSS AA16
VSS AD16
VSS AC16
VSS AF16
VSS AE16
VSS AB13
VSS AA14
VSS AD13
VSS AC14
VSS AF13
VSS AE14
VSS AB11
VSS AA11
VSS AD11
VSS AC11
VSS AF11
VSS AE11
VSS AB8
VSS AA8
VSS AD8
VSS AC8
VSS AF8
VSS AE8
VSS AA5
VSS AD5
VSS AC6
VSS AF6
VSS AB4
VSS AC3
VSS AF3
VSS AE4
VSS AB1
VSS AA2
VSS AD2
VSS AE1
VSS B6
VSS C5
VSS F5
VSS E6
VSS H6
VSS J5
VSS M5
VSS L6
VSS P6
VSS R5
VSS V5
VSS U6
VSS Y6
VSS A4
VSS D4
VSS E3
VSS H3
VSS G4
VSS K4
VSS L3
VSS P3
VSS N4
VSS T4
VSS U3
VSS Y3
VSS W4
VSS D1
VSS C2
VSS F2
VSS G1
RSVD
B25
VSSSENSE
AE7
VCCP
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
T6
VCCP
R6
VCCP
K21
VCCP
J21
VCCP
M21
VCCP
N21
VCCP
T21
VCCP
R21
VCCP
V21
VCCP
W21
VCCP
V6
VCCP
G21
VID0
AD6
VID1
AF5
VID2
AE5
VID3
AF4
VID4
AE3
VID5
AF2
VID6
AE2
BSEL0
B22
BSEL1
B23
BSEL2
C21
COMP0
R26
COMP1
U26
COMP2
U1
COMP3
V1
RSVD
C23
RSVD
C24
RSVD
AA1
RSVD
AA4
RSVD
AB2
RSVD
AA3
RSVD
M4
RSVD
N5
RSVD
T2
RSVD
D2
RSVD
F6
RSVD
D3
RSVD
C1
RSVD
AF1
RSVD
D22
VCC
E7
R536
54.9_0402_1%
12
C408
10U_0805_10V4Z
1
2
R535
27.4_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCP
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Yonah bypass
853Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Place these inside
socket cavity on L8
(North side
Secondary)
ESR <= 1.5m ohm
Capacitor > 1980uF
Mid Frequence Decoupling
Place these capacitors on L8
(North side,Secondary Layer)
North Side SecondarySouth Side Secondary
Place these capacitors on L8
(South side,Secondary Layer)
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(South side,Secondary Layer)
C423
22U_0805_6.3V6M
LV@
1
2
C437
22U_0805_6.3V6M
@
1
2
C452
0.1U_0402_10V6K
1
2
C409
22U_0805_6.3V6M
1
2
C425
22U_0805_6.3V6M
@
1
2
C424
22U_0805_6.3V6M
LV@
1
2
+
C441
330U_D2E_2.5VM_R9
LV@ 1
2
C410
22U_0805_6.3V6M
1
2
C433
22U_0805_6.3V6M
LV@
1
2
C438
22U_0805_6.3V6M
@
1
2
C418
22U_0805_6.3V6M
@
1
2
C453
0.1U_0402_10V6K
1
2
C426
22U_0805_6.3V6M
@
1
2
C439
22U_0805_6.3V6M
LV@
1
2
C411
22U_0805_6.3V6M
LV@
1
2
+
C443
330U_D2E_2.5VM_R9
1
2
C444
22U_0805_6.3V6M
@
1
2
C412
22U_0805_6.3V6M
LV@
1
2
C440
22U_0805_6.3V6M
LV@
1
2
C449
0.1U_0402_10V6K
1
2
C427
22U_0805_6.3V6M
@
1
2
C419
22U_0805_6.3V6M
1
2
+
C442
330U_D2E_2.5VM_R9
LV@
1
2
C413
22U_0805_6.3V6M
LV@
1
2
+
C446
330U_D2E_2.5VM_R9
1
2
C445
22U_0805_6.3V6M
@
1
2
C450
0.1U_0402_10V6K
1
2
C420
22U_0805_6.3V6M
1
2
C431
22U_0805_6.3V6M
@
1
2
C414
22U_0805_6.3V6M
LV@
1
2
C429
22U_0805_6.3V6M
1
2
C428
22U_0805_6.3V6M
@
1
2
C421
22U_0805_6.3V6M
LV@
1
2
C458
22U_0805_6.3V6M
@
1
2
C451
0.1U_0402_10V6K
1
2
C448
0.1U_0402_10V6K
1
2
C435
22U_0805_6.3V6M
1
2
C430
22U_0805_6.3V6M
1
2
C432
22U_0805_6.3V6M
@
1
2
C422
22U_0805_6.3V6M
LV@
1
2
C434
22U_0805_6.3V6M
LV@
1
2
C436
22U_0805_6.3V6M
1
2
+
C447
330U_D2E_2.5VM_R9
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG8
CFG10
CFG14
CFG15
CFG17
CFG3
CFG4
CFG9
PM_EXTTS#1
PLTRST_R#
EC_EXTTS#0
M_OCDOCMP1
M_OCDOCMP0
M_OCDOCMP0
M_OCDOCMP1
CFG11
CFG6
CFG7
CFG5
CFG12
CFG13
CFG18
CFG16
CFG19
PWROK
H_VREF
M_ODT0
EC_EXTTS#0
M_ODT1
M_ODT2
MCH_CLKSEL0
DDR_CS1_DIMMA#
DMI_RXP3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DMI_RXN2
DMI_RXP2
DMI_TXP2
DMI_TXP3
DMI_TXN3
DMI_RXN3
DMI_TXN2
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
CLK_MCH_3GPLL
CLK_MCH_3GPLL#M_CLK_DDR0
M_CLK_DDR3
M_CLK_DDR2
M_CLK_DDR1
DMI_RXP1 CFG20
DMI_RXP0
DMI_RXN0
DMI_RXN1
DREFCLK#
DMI_TXP0
DMI_TXP1
DREFCLK
SMRCOMPP
SMRCOMPN
DMI_TXN0
DREF_SSCLK#
DMI_TXN1
DREF_SSCLK
MCH_CLKSEL1
MCH_CLKSEL2
DDR_CS0_DIMMA#
PM_BMBUSY#
H_THERMTRIP#
CLKREQC#
PM_EXTTS#1
V_DDR_MCH_REF
M_ODT3
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
H_RS#2
H_D#50
H_D#45
H_D#11
H_ADS#
H_DSTBP#0
H_DSTBN#1
CLK_MCH_BCLK
H_ADSTB#0
H_A#14
H_A#8
H_D#47
H_D#12
H_TRDY#
H_REQ#4
H_A#27
H_A#11
H_D#39
H_D#26
H_D#24
H_D#6
H_D#0
H_SWNG0
H_DRDY#
H_A#28
H_A#24
H_A#21
H_SWNG1
H_D#57
H_D#43
H_D#18
H_HIT#
H_A#19
H_D#52
H_D#21
H_D#15
H_DSTBP#3
H_REQ#0
H_A#17
H_A#3
H_D#46
H_D#38
H_HITM#
H_DINV#1
H_A#25
H_A#6
H_D#58
H_D#30
H_D#17
H_D#5
H_DEFER#
H_DINV#3
H_ADSTB#1
H_A#31
H_A#29
H_XSCOMP
H_D#61
H_D#33
H_D#29
H_D#20
H_DINV#2
H_A#22
H_D#51
H_D#48
H_D#40
H_D#19
H_D#8
H_D#4
H_VREF
H_RS#0
H_A#26
H_A#7
H_D#53
H_CPUSLP#
H_DBSY#
H_BR0#
H_DSTBN#2
H_DINV#0
H_A#23
H_A#12
H_A#5
H_D#60
H_D#44
H_D#25
H_D#16
H_BPRI#
H_DSTBN#3
H_REQ#1
H_A#13
H_D#59
H_D#41
H_D#37
H_D#28
H_D#27
H_D#23
H_D#9
H_D#1
H_RESET#
H_A#20
H_A#15
H_D#54
H_D#42
H_D#36
H_D#14
H_D#3
H_RS#1
H_A#9
H_A#4
H_D#56
H_D#55
H_D#34
H_D#13
H_SWNG1
H_LOCK#
H_DSTBP#2
H_DSTBP#1
H_DSTBN#0
H_REQ#3
H_D#63
H_D#22
H_D#10
H_BNR#
H_REQ#2
H_A#16
H_SWNG0
H_YSCOMP
H_YRCOMP
H_XRCOMP
H_D#35
H_D#31
H_D#7
H_DPWR#
CLK_MCH_BCLK#
H_A#30
H_A#18
H_A#10
H_D#62
H_D#49
H_D#32
H_D#2
VREF
VREF
V_DDR_MCH_REF
V_DDR_MCH_REF
+VCCP
+VCCP+VCCP
+VCCP
+3VS
+1.8V
+1.8V
+5VALW
+1.8V
H_D#[0..63]<6> H_A#[3..31] <6>
H_REQ#[0..4] <6>
H_DSTBN#[0..3] <6>
H_DSTBP#[0..3] <6>
H_RS#[0..2] <6>
DMI_TXN0<22> DMI_TXN1<22> DMI_TXN2<22> DMI_TXN3<22>
DMI_TXP0<22> DMI_TXP1<22> DMI_TXP2<22> DMI_TXP3<22>
DMI_RXN0<22> DMI_RXN1<22> DMI_RXN2<22> DMI_RXN3<22>
DMI_RXP0<22> DMI_RXP1<22> DMI_RXP2<22> DMI_RXP3<22>
M_CLK_DDR0<15> M_CLK_DDR1<15> M_CLK_DDR2<16> M_CLK_DDR3<16>
M_CLK_DDR#0<15> M_CLK_DDR#1<15> M_CLK_DDR#2<16> M_CLK_DDR#3<16>
DDR_CS0_DIMMA#<15> DDR_CS1_DIMMA#<15>
PM_BMBUSY#<22>
H_DPRSLPVR<22,46> H_THERMTRIP#<6,21>
CLKREQC# <5>
CLK_MCH_3GPLL# <5>
CLK_MCH_3GPLL <5>
CFG20 <13>
CFG19 <13>
CFG18 <13>
CFG16 <13>
CFG13 <13>
CFG12 <13>
CFG9 <13>
CFG7 <13>
CFG5 <13>
MCH_CLKSEL2 <5>
MCH_CLKSEL1 <5>
MCH_CLKSEL0 <5>
EC_EXTTS#0<15,16,33>
DREFCLK# <5>
DREFCLK <5>
DREF_SSCLK# <5>
DREF_SSCLK <5>
PWROK<22,33,34>
MCH_ICH_SYNC#<20>
V_DDR_MCH_REF<15,16>
M_ODT0<15> M_ODT1<15> M_ODT2<16> M_ODT3<16>
DDR_CKE0_DIMMA<15> DDR_CKE1_DIMMA<15>
PLT_RST#<18,20,22,24,28,32,33,35>
DDR_CKE2_DIMMB<16> DDR_CKE3_DIMMB<16>
DDR_CS2_DIMMB#<16> DDR_CS3_DIMMB#<16>
H_LOCK# <6>
H_BPRI# <6>
H_DINV#3 <6>
H_DPWR# <6>
CLK_MCH_BCLK <5>
H_HIT# <6>
H_DINV#2 <6>
H_BNR# <6>
H_DINV#0 <6>
H_TRDY# <6>
H_HITM# <6>
H_ADSTB#1 <6>
H_CPUSLP# <6,21>
H_ADS# <6>
H_DEFER# <6>
H_BR0# <6>
H_DBSY# <6>
H_ADSTB#0 <6>
H_DINV#1 <6>
H_RESET# <6>
CLK_MCH_BCLK# <5>
H_DRDY# <6>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Calistoga1/6-GTL/DMIDDRMUX
953Monday, January 08, 2007
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.
Stuff R546 & R547 for A1 Calistoga
Description at page13.
Layout Note:
Route as short
as possible
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
Use +1.8V divide voltage for V_DDR_MCH_REF, R545/R548 use 100_0402_1%
Use buffer to generate V_DDR_MCH_REF, R545/R548 use 1K_0402_1%
T6
PAD T5
PAD
T4
PAD
C455
0.1U_0402_16V4Z
1
2
DMI
DDR MUXING
CFG
PM
CLKNC
RESERVED
U3B
CALISTOGA_FCBGA1466~D
DMIRXN0
AE35
DMIRXN1
AF39
DMIRXN2
AG35
DMIRXN3
AH39
DMIRXP0
AC35
DMIRXP1
AE39
DMIRXP2
AF35
DMIRXP3
AG39
DMITXN0
AE37
DMITXN1
AF41
DMITXN2
AG37
DMITXN3
AH41
DMITXP0
AC37
DMITXP1
AE41
DMITXP2
AF37
DMITXP3
AG41
SM_CK0
AY35
SM_CK1
AR1
SM_CK2
AW7
SM_CK3
AW40
SM_CK0#
AW35
SM_CK1#
AT1
SM_CK2#
AY7
SM_CK3#
AY40
SM_OCDCOMP0
AL20
SM_OCDCOMP1
AF10
SM_ODT0
BA13
SM_ODT1
BA12
SM_ODT2
AY20
SM_ODT3
AU21
SM_RCOMPN
AV9
SM_RCOMPP
AT9
SM_VREF0
AK1
SM_VREF1
AK41
SM_CKE0
AU20
SM_CKE1
AT20
SM_CKE2
BA29
SM_CKE3
AY29
SM_CS0#
AW13
SM_CS1#
AW12
SM_CS2#
AY21
SM_CS3#
AW21
CFG16 G18
CFG1 K18
CFG2 J18
CFG3 F18
CFG4 E15
CFG5 F15
CFG6 E18
CFG7 D19
CFG8 D16
CFG9 G16
CFG10 E16
CFG11 D15
CFG12 G15
CFG13 K15
CFG14 C15
CFG15 H16
CFG0 K16
CFG17 H15
CFG18 J25
CFG19 K27
CFG20 J26
G_CLKP AG33
G_CLKN AF33
D_REF_CLKN A27
D_REF_CLKP A26
D_REF_SSCLKN C40
D_REF_SSCLKP D41
NC0 A3
NC1 A39
NC2 A4
NC3 A40
NC4 AW1
NC5 AW41
NC6 AY1
NC7 BA1
NC8 BA2
NC9 BA3
NC10 BA39
NC11 BA40
NC12 BA41
NC13 C1
NC14 AY41
NC15 B2
NC16 B41
NC17 C41
NC18 D1
PM_BMBUSY#
G28
PM_EXTTS0#
F25
PM_EXTTS1#
H26
PM_THERMTRIP#
G6
PWROK
AH33
RSTIN#
AH34
RESERVED1 T32
RESERVED2 R32
RESERVED3 F3
RESERVED4 F7
RESERVED5 AG11
RESERVED6 AF11
RESERVED7 H7
RESERVED8 J19
RESERVED9 A41
RESERVED10 A34
RESERVED11 D28
RESERVED12 D27
RESERVED13 A35
ICH_SYNC#
K28
CLK_REQ# H32
U1
G2992F1U_SO8
Buffer@
VOUT
4
NC 5
GND
2
VREF
3
VIN
1VCNTL 6
NC 7
NC 8
TP 9
R537 80.6_0402_1%
1 2
C680
1U_0603_10V4Z
Buffer@
1
2
HOST
U3A
CALISTOGA_FCBGA1466~D
HD0#
F1
HD1#
J1
HD2#
H1
HD3#
J6
HD4#
H3
HD5#
K2
HD6#
G1
HD7#
G2
HD8#
K9
HD9#
K1
HD10#
K7
HD11#
J8
HD12#
H4
HD13#
J3
HD14#
K11
HD15#
G4
HD16#
T10
HD17#
W11
HD18#
T3
HD19#
U7
HD20#
U9
HD21#
U11
HD22#
T11
HD23#
W9
HD24#
T1
HD25#
T8
HD26#
T4
HD27#
W7
HD28#
U5
HD29#
T9
HD30#
W6
HD31#
T5
HD32#
AB7
HD33#
AA9
HD34#
W4
HD35#
W3
HD36#
Y3
HD37#
Y7
HD38#
W5
HD39#
Y10
HD40#
AB8
HD41#
W2
HD42#
AA4
HD43#
AA7
HD44#
AA2
HD45#
AA6
HD46#
AA10
HD47#
Y8
HD48#
AA1
HD49#
AB4
HD50#
AC9
HD51#
AB11
HD52#
AC11
HD53#
AB3
HD54#
AC2
HD55#
AD1
HD56#
AD9
HD57#
AC1
HD58#
AD7
HD59#
AC6
HD60#
AB5
HD61#
AD10
HD62#
AD4
HD63#
AC8
HVREF1
K13
HXRCOMP
E1
HXSCOMP
E2
HYRCOMP
Y1
HYSCOMP
U1
HXSWING
E4
HYSWING
W1
HA3# H9
HA4# C9
HA5# E11
HA6# G11
HA7# F11
HA8# G12
HA9# F9
HA10# H11
HA11# J12
HA12# G14
HA13# D9
HA14# J14
HA15# H13
HA16# J15
HA17# F14
HA18# D12
HA19# A11
HA20# C11
HA21# A12
HA22# A13
HA23# E13
HA24# G13
HA25# F12
HA26# B12
HA27# B14
HA28# C12
HA29# A14
HA30# C14
HA31# D14
HREQ#0 D8
HREQ#1 G8
HREQ#2 B8
HREQ#3 F8
HREQ#4 A8
HADSTB#0 B9
HADSTB#1 C13
HRS0# B4
HRS1# E6
HRS2# D6
HCLKN AG1
HCLKP AG2
HDINV#0 J7
HDINV#1 W8
HDINV#2 U3
HDINV#3 AB10
HDSTBN#0 K4
HDSTBN#1 T7
HDSTBN#2 Y5
HDSTBN#3 AC4
HDSTBP#0 K3
HDSTBP#1 T6
HDSTBP#2 AA5
HDSTBP#3 AC5
HCPURST# B7
HADS# E8
HTRDY# E7
HDPWR# J9
HDRDY# H8
HDEFER# C3
HHITM# D4
HHIT# D3
HLOCK# B3
HBREQ0# C7
HBNR# C6
HBPRI# F6
HDBSY# A7
HCPUSLP# E3
HVREF0
J13
T3
PAD
R546
40.2_0402_1% @ 12
R556
200_0402_1%
12
R539
54.9_0402_1%
12
R446
0_0805_5%
1.8_divider@
1 2
R549
221_0603_1%
12
R542 100_0402_1%
12
T9
PAD
R545
1K_0402_1%
12
R553
10K_0402_5%@12
T8
PAD
R555
100_0402_1%
12
C456
0.1U_0402_16V4Z
1
2
R551
100_0402_1%
12
T1
PAD
C457
0.1U_0402_16V4Z
1
2
R540
54.9_0402_1%
12
R541 0_0402_5%
1 2
T2
PAD
R547
40.2_0402_1% @ 12
R538 80.6_0402_1%
1 2
R550
221_0603_1%
12
R554
100_0402_1%
12
T7
PAD
R548
1K_0402_1%
12
R552
10K_0402_5%
12
C454
0.1U_0402_16V4Z
1
2
C932
10U_1206_6.3V7K
Buffer@ 1
2
R543
24.9_0402_1%
12
R544
24.9_0402_1%
12
C931
10U_1206_6.3V7K
Buffer@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_D43
DDR_A_D27
DDR_A_D2
DDR_A_D32
DDR_A_D15
DDR_A_D11
DDR_A_D41
DDR_A_D26
DDR_A_D6
DDR_A_D49
DDR_A_D47
DDR_A_D58
DDR_A_D42
DDR_A_D1
DDR_A_D46
DDR_A_D23
DDR_A_D40
DDR_A_D36
DDR_A_D5
DDR_A_D48
DDR_A_D14
DDR_A_D20
DDR_A_D24
DDR_A_D54
DDR_A_D63
DDR_A_D10
DDR_A_D8
DDR_A_D57
DDR_A_D16
DDR_A_D9
DDR_A_D18
DDR_A_D39
DDR_A_D37
DDR_A_D30
DDR_A_D4
DDR_A_D45
DDR_A_D7
DDR_A_D60
DDR_A_D13
DDR_A_D62
DDR_A_D19
DDR_A_D53
DDR_A_D51
DDR_A_D17
DDR_A_D3
DDR_A_D52
DDR_A_D12
DDR_A_D38
DDR_A_D29
DDR_A_D44
DDR_A_D50
DDR_A_D61
DDR_A_D59
DDR_A_D0
DDR_A_D55
SA_RCVENIN#
DDR_A_DM1
DDR_A_DM6
SA_RCVENOUT#
DDR_A_DM0
DDR_A_DM4
DDR_A_DM3
DDR_A_DM7
DDR_A_DM5
DDR_A_DM2
DDR_A_BS#1
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_D22
DDR_A_D21
DDR_A_MA7
DDR_A_MA5
DDR_A_MA4
DDR_A_MA6
DDR_A_MA8
DDR_A_MA10
DDR_A_MA9
DDR_A_MA11
DDR_A_MA12
DDR_A_D25
DDR_A_D35
DDR_A_D28
DDR_A_D33
DDR_A_D34
DDR_A_D31
DDR_A_D56
DDR_A_DQS#0
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS0
DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#
DDR_B_DM3
DDR_B_DM0
DDR_B_DM6
DDR_B_DM1
DDR_B_DM5
DDR_B_DM7
DDR_B_DM4
DDR_B_DM2
DDR_B_DQS#7
DDR_B_DQS#6
DDR_B_DQS1
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS7
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS#0
DDR_B_MA0
DDR_B_MA7
DDR_B_MA2
DDR_B_MA5
DDR_B_MA3
DDR_B_MA9
DDR_B_MA4
DDR_B_MA6
DDR_B_MA8
DDR_B_MA12
DDR_B_MA1
DDR_B_DQS#1
DDR_B_MA11
DDR_B_MA10
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_D0
DDR_B_D1
DDR_B_D3
DDR_B_D2
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D11
DDR_B_D15
DDR_B_D8
DDR_B_D9
DDR_B_D12
DDR_B_D14
DDR_B_D13
DDR_B_D10
DDR_B_D23
DDR_B_D19
DDR_B_D18
DDR_B_D22
DDR_B_D17
DDR_B_D16
DDR_B_D21
DDR_B_D30
DDR_B_D27
DDR_B_D25
DDR_B_D28
DDR_B_D31
DDR_B_D20
DDR_B_D29
DDR_B_D26
DDR_B_D24
DDR_B_D35
DDR_B_D39
DDR_B_D38
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D46
DDR_B_D44
DDR_B_D37
DDR_B_D47
DDR_B_D36
DDR_B_D45
DDR_B_D42
DDR_B_D43
DDR_B_D40
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D54
DDR_B_D41
DDR_B_D55
DDR_B_D53
DDR_B_D57
DDR_B_D48
DDR_B_D62
DDR_B_D60
DDR_B_D61
DDR_B_D58
DDR_B_D63
DDR_B_D59
DDR_B_D52
DDR_B_D56
SB_RCVENIN#
DDR_A_BS#0
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
DDR_B_BS#1
DDR_B_BS#0
SB_RCVENOUT#
DDR_A_BS#2
DDR_A_MA13
DDR_B_BS#2
DDR_B_MA13
DDR_A_BS#0<15> DDR_A_BS#1<15>
DDR_A_DM[0..7]<15>
DDR_A_DQS[0..7]<15>
DDR_A_DQS#[0..7]<15>
DDR_A_MA[0..13]<15>
DDR_A_WE#<15>
DDR_A_CAS#<15> DDR_A_RAS#<15>
DDR_B_BS#0<16> DDR_B_BS#1<16>
DDR_A_D[0..63] <15>
DDR_B_DM[0..7]<16>
DDR_B_DQS[0..7]<16>
DDR_B_DQS#[0..7]<16>
DDR_B_MA[0..13]<16>
DDR_B_WE#<16>
DDR_B_CAS#<16> DDR_B_RAS#<16>
DDR_B_D[0..63] <16>
DDR_A_BS#2<15> DDR_B_BS#2<16>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Calistoga2/6-DDRA&B
10 53Monday, January 08, 2007
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Route to a via next to ball Route to a via next to ball
T12 PAD
T10 PAD T11 PAD
T13 PAD
DDR SYS MEMORY A
U3D
CALISTOGA_FCBGA1466~D
SA_DQ0 AJ35
SA_DQ1 AJ34
SA_DQ2 AM31
SA_DQ3 AM33
SA_DQ4 AJ36
SA_DQ5 AK35
SA_DQ6 AJ32
SA_DQ7 AH31
SA_DQ8 AN35
SA_DQ9 AP33
SA_DQ10 AR31
SA_DQ11 AP31
SA_DQ12 AN38
SA_DQ13 AM36
SA_DQ14 AM34
SA_DQ15 AN33
SA_DQ16 AK26
SA_DQ17 AL27
SA_DQ18 AM26
SA_DQ19 AN24
SA_DQ20 AK28
SA_DQ21 AL28
SA_DQ22 AM24
SA_DQ23 AP26
SA_DQ24 AP23
SA_DQ25 AL22
SA_DQ26 AP21
SA_DQ27 AN20
SA_DQ28 AL23
SA_DQ29 AP24
SA_DQ30 AP20
SA_DQ31 AT21
SA_DQ32 AR12
SA_DQ33 AR14
SA_DQ34 AP13
SA_DQ35 AP12
SA_DQ36 AT13
SA_DQ37 AT12
SA_DQ38 AL14
SA_DQ39 AL12
SA_DQ40 AK9
SA_DQ41 AN7
SA_DQ42 AK8
SA_DQ43 AK7
SA_DQ44 AP9
SA_DQ45 AN9
SA_DQ46 AT5
SA_DQ47 AL5
SA_DQ48 AY2
SA_DQ49 AW2
SA_DQ50 AP1
SA_DQ51 AN2
SA_DQ52 AV2
SA_DQ53 AT3
SA_DQ54 AN1
SA_DQ55 AL2
SA_DQ56 AG7
SA_DQ57 AF9
SA_DQ58 AG4
SA_DQ59 AF6
SA_DQ60 AG9
SA_DQ61 AH6
SA_DQ62 AF4
SA_DQ63 AF8
SA_BS0
AU12
SA_BS1
AV14
SA_BS2
BA20
SA_CAS#
AY13
SA_RAS#
AW14
SA_WE#
AY14
SA_RCVENIN#
AK23
SA_RCVENOUT#
AK24
SA_DM0
AJ33
SA_DM1
AM35
SA_DM2
AL26
SA_DM3
AN22
SA_DM4
AM14
SA_DM5
AL9
SA_DM6
AR3
SA_DM7
AH4
SA_DQS0
AK33
SA_DQS1
AT33
SA_DQS2
AN28
SA_DQS3
AM22
SA_DQS4
AN12
SA_DQS5
AN8
SA_DQS6
AP3
SA_DQS7
AG5
SA_DQS0#
AK32
SA_DQS1#
AU33
SA_DQS2#
AN27
SA_DQS3#
AM21
SA_DQS4#
AM12
SA_DQS5#
AL8
SA_DQS6#
AN3
SA_DQS7#
AH5
SA_MA0
AY16
SA_MA1
AU14
SA_MA2
AW16
SA_MA3
BA16
SA_MA4
BA17
SA_MA5
AU16
SA_MA6
AV17
SA_MA7
AU17
SA_MA8
AW17
SA_MA9
AT16
SA_MA10
AU13
SA_MA11
AT17
SA_MA12
AV20
SA_MA13
AV12
DDR SYS MEMORY B
U3E
CALISTOGA_FCBGA1466~D
SB_DQ0 AK39
SB_DQ1 AJ37
SB_DQ2 AP39
SB_DQ3 AR41
SB_DQ4 AJ38
SB_DQ5 AK38
SB_DQ6 AN41
SB_DQ7 AP41
SB_DQ8 AT40
SB_DQ9 AV41
SB_DQ10 AU38
SB_DQ11 AV38
SB_DQ12 AP38
SB_DQ13 AR40
SB_DQ14 AW38
SB_DQ15 AY38
SB_DQ16 BA38
SB_DQ17 AV36
SB_DQ18 AR36
SB_DQ19 AP36
SB_DQ20 BA36
SB_DQ21 AU36
SB_DQ22 AP35
SB_DQ23 AP34
SB_DQ24 AY33
SB_DQ25 BA33
SB_DQ26 AT31
SB_DQ27 AU29
SB_DQ28 AU31
SB_DQ29 AW31
SB_DQ30 AV29
SB_DQ31 AW29
SB_DQ32 AM19
SB_DQ33 AL19
SB_DQ34 AP14
SB_DQ35 AN14
SB_DQ36 AN17
SB_DQ37 AM16
SB_DQ38 AP15
SB_DQ39 AL15
SB_DQ40 AJ11
SB_DQ41 AH10
SB_DQ42 AJ9
SB_DQ43 AN10
SB_DQ44 AK13
SB_DQ45 AH11
SB_DQ46 AK10
SB_DQ47 AJ8
SB_DQ48 BA10
SB_DQ49 AW10
SB_DQ50 BA4
SB_DQ51 AW4
SB_DQ52 AY10
SB_DQ53 AY9
SB_DQ54 AW5
SB_DQ55 AY5
SB_DQ56 AV4
SB_DQ57 AR5
SB_DQ58 AK4
SB_DQ59 AK3
SB_DQ60 AT4
SB_DQ61 AK5
SB_DQ62 AJ5
SB_DQ63 AJ3
SB_BS0
AT24
SB_BS1
AV23
SB_BS2
AY28
SB_CAS#
AR24
SB_RAS#
AU23
SB_WE#
AR27
SB_RCVENIN#
AK16
SB_RCVENOUT#
AK18
SB_DM0
AK36
SB_DM1
AR38
SB_DM2
AT36
SB_DM3
BA31
SB_DM4
AL17
SB_DM5
AH8
SB_DM6
BA5
SB_DM7
AN4
SB_DQS0
AM39
SB_DQS1
AT39
SB_DQS2
AU35
SB_DQS3
AR29
SB_DQS4
AR16
SB_DQS5
AR10
SB_DQS6
AR7
SB_DQS7
AN5
SB_DQS0#
AM40
SB_DQS1#
AU39
SB_DQS2#
AT35
SB_DQS3#
AP29
SB_DQS4#
AP16
SB_DQS5#
AT10
SB_DQS6#
AT7
SB_DQS7#
AP5
SB_MA0
AY23
SB_MA1
AW24
SB_MA2
AY24
SB_MA3
AR28
SB_MA4
AT27
SB_MA5
AT28
SB_MA6
AU27
SB_MA7
AV28
SB_MA8
AV27
SB_MA9
AW27
SB_MA10
AV24
SB_MA11
BA27
SB_MA12
AY27
SB_MA13
AR23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEGCOMP
SDVOB_INT+
SDVOB_INT-
SDVO_R-
SDVO_CLK-
SDVO_B-
SDVO_G-
SDVO_R+
SDVO_B+
SDVO_G+
SDVO_CLK+
LVDSCLKA-
LVDSA_D1+
LVDSA_D2+
LVDSA_D0+
LVDSA_D2-
LVDSA_D1-
LVDSA_D0-
LCD_I2C_DAT
LIBG
ENVDD
LVDD_EN
GM_PWM
SDVO_SDAT
SDVO_SCLK
3VDDCDA
3VDDCCL
LVDSCLKA+
LVDSB_D1+
LVDSB_D0+
LVDSB_D0-
LVDSB_D2+
LVDSB_D1-
LVDSB_D2-
LVDSCLKB+
LVDSCLKB-
LCD_I2C_CLK
LCTLA_CLK
LCTLB_DATA
ENABLT
LCTLA_CLK
LCTLB_DATA
LCD_I2C_CLK
LCD_I2C_DAT
+1.5VS_PCIE
+1.5VS
+3VS
3VDDCDA<19>
SDVO_SDAT<18>
LVDSA_D0+<17>
SDVO_SCLK<18>
LVDSA_D1+<17> LVDSA_D2+<17>
LVDSA_D0-<17> LVDSA_D1-<17> LVDSA_D2-<17>
LVDSB_D0+<17> LVDSB_D1+<17> LVDSB_D2+<17>
LVDSB_D0-<17> LVDSB_D1-<17> LVDSB_D2-<17>
LVDSCLKA+<17> LVDSCLKA-<17> LVDSCLKB+<17> LVDSCLKB-<17>
GM_PWM<17>
CRT_VSYNC<19> CRT_HSYNC<19> CRT_B<19>
CRT_G<19>
CRT_R<19>
SDVOB_R+ <18>
SDVOB_G+ <18>
SDVOB_B+ <18>
SDVOB_CLK+ <18>
SDVOB_R- <18>
SDVOB_G- <18>
SDVOB_B- <18>
SDVOB_CLK- <18>
SDVOB_INT+ <18>
SDVOB_INT- <18>
ENVDD<17>
LCD_I2C_CLK<17> LCD_I2C_DAT<17>
3VDDCCL<19>
ENABLT<17,33>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Calistoga3/6-VGA/LVDS
11 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PEGCOMP trace width
and spacing is 18/25 mils.
R565 change to 226ohm
required by Motion
R562 150_0402_5%
12
R586 10K_0402_5%
1 2
R564 150_0402_5%
12
R561 39_0402_5%
12
R565 226_0402_1%
1 2
R37 10K_0402_5%
1 2
C466
0.1U_0402_16V4Z
1 2
C463 0.1U_0402_16V4Z
1 2
C464 0.1U_0402_16V4Z
1 2
LVDS TV CRT
PCI-EXPRESS GRAPHICS
U3C
CALISTOGA_FCBGA1466~D
SDVOCTRL_CLK
H28 SDVOCTRL_DATA
H27
LA_DATA0
B37
LA_DATA1
B34
LA_DATA2
A36
LVREFH
C33
LVREFL
C32
TVDAC_A
A16
TVDAC_B
C18
TVDAC_C
A19
TV_IREF
J20
TV_IRTNA
B16
TV_IRTNB
B18
TV_IRTNC
B19
DDCCLK
C26
DDCDATA
C25
LA_DATA#0
C37
LA_DATA#1
B35
LA_DATA#2
A37
LB_DATA0
F30
LB_DATA1
D29
LB_DATA2
F28
LB_DATA#0
G30
LB_DATA#1
D30
LB_DATA#2
F29
LA_CLK
A32
LA_CLK#
A33
LB_CLK
E26
LB_CLK#
E27
LBKLT_CTL
D32
LBKLT_EN
J30
LCTLA_CLK
H30
LCTLB_DATA
H29
LDDC_CLK
G26
LDDC_DATA
G25
LVDD_EN
F32
LIBG
B38
LVBG
C35
VSYNC
H23
HSYNC
G23
BLUE
E23
BLUE#
D23
GREEN
C22
GREEN#
B22
RED
A21
RED#
B21
CRT_IREF
J22
EXP_COMPI D40
EXP_COMPO D38
EXP_RXN0 F34
EXP_RXN1 G38
EXP_RXN2 H34
EXP_RXN3 J38
EXP_RXN4 L34
EXP_RXN5 M38
EXP_RXN6 N34
EXP_RXN7 P38
EXP_RXN8 R34
EXP_RXN9 T38
EXP_RXN10 V34
EXP_RXN11 W38
EXP_RXN12 Y34
EXP_RXN13 AA38
EXP_RXN14 AB34
EXP_RXN15 AC38
EXP_RXP0 D34
EXP_RXP1 F38
EXP_RXP2 G34
EXP_RXP3 H38
EXP_RXP4 J34
EXP_RXP5 L38
EXP_RXP6 M34
EXP_RXP7 N38
EXP_RXP8 P34
EXP_RXP9 R38
EXP_RXP10 T34
EXP_RXP11 V38
EXP_RXP12 W34
EXP_RXP13 Y38
EXP_RXP14 AA34
EXP_RXP15 AB38
EXP_TXN0 F36
EXP_TXN1 G40
EXP_TXN2 H36
EXP_TXN3 J40
EXP_TXN4 L36
EXP_TXN5 M40
EXP_TXN6 N36
EXP_TXN7 P40
EXP_TXN8 R36
EXP_TXN9 T40
EXP_TXN10 V36
EXP_TXN11 W40
EXP_TXN12 Y36
EXP_TXN13 AA40
EXP_TXN14 AB36
EXP_TXN15 AC40
EXP_TXP0 D36
EXP_TXP1 F40
EXP_TXP2 G36
EXP_TXP3 H40
EXP_TXP4 J36
EXP_TXP5 L40
EXP_TXP6 M36
EXP_TXP7 N40
EXP_TXP8 P36
EXP_TXP9 R40
EXP_TXP10 T36
EXP_TXP11 V40
EXP_TXP12 W36
EXP_TXP13 Y40
EXP_TXP14 AA36
EXP_TXP15 AB40
TV_DCONSEL1
J29
TV_DCONSEL0
K30
R585 10K_0402_5%
1 2 C460 0.1U_0402_16V4Z
1 2
R559 1.5K_0402_1%
1 2
R42 10K_0402_5%
1 2
C461
0.1U_0402_16V4Z
1 2
R563 150_0402_5%
12
R557
24.9_0402_1%
1 2
R558 0_0402_5%
12
R560 39_0402_5%
12
C467 0.1U_0402_16V4Z
1 2
C465
0.1U_0402_16V4Z
1 2
C462 0.1U_0402_16V4Z
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MCH_D2
MCH_A6
MCH_AB1
3GRLL_R
+1.5VS
+1.5VS_PCIE
+1.5VS
+3VS
+1.5VS_MPLL
+1.5VS
+1.5VS_3GPLL
+1.5VS
+VCCP
+2.5VS
+2.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS_DPLLA
+1.5VS_DPLLB +1.5VS_MPLL
+1.5VS_HPLL
+1.5VS
+1.5VS_3GPLL +1.5VS
+1.5VS
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+2.5VS
+2.5VS
+2.5VS
+1.5VS
+1.5VS
+2.5VS
+2.5VS
+VCCP
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Calistoga4/6-PWR
12 53Monday, January 08, 2007
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
W=40 mils
close pin G41
Should be placed near GMCH
close pin B30
C485
2.2U_0805_16V4Z
1
2
L6
MBK1608301YZF_0603
1 2
C490
0.1U_0402_16V4Z
1
2
L8
MBK1608301YZF_0603
1 2
C481
0.1U_0402_16V4Z
1
2
C468
0.1U_0402_16V4Z
1
2
C494
10U_0805_6.3V6M
1
2
C475
10U_1206_6.3V6M
1
2
C470
10U_0805_6.3V6M
1
2
C474
0.1U_0402_16V4Z
1
2
C482
0.1U_0402_16V4Z
1
2
+
C499
470U_D2_2.5VM
1
2
C498
0.47U_0603_10V7K
1
2
D17
CH751H-40PT_SOD323
21
+
C477
330U_D2E_2.5VM_R9
1
2
C487
10U_0805_6.3V6M
1
2
C471
10U_0805_6.3V6M
1
2
+
C500
470U_D2_2.5VM
1
2
C480
0.1U_0402_16V4Z
1
2
C484
4.7U_0805_10V4Z
1
2
L5
MBK1608301YZF_0603
1 2
C497
0.22U_0603_10V7K
1
2
C504
0.1U_0402_16V4Z
1
2
C491
22U_0805_6.3V6M
1
2
L3
BLM18PG181SN1D_0603
1 2
C479
0.022U_0402_16V7K
1
2
C476
0.1U_0402_16V4Z
1
2
C473
0.1U_0402_16V4Z
1
2
C483
0.01U_0402_16V7K
1
2
C503
0.1U_0402_16V4Z
1
2
C496
0.1U_0402_16V4Z
1
2
P O W E R
U3H
CALISTOGA_FCBGA1466~D
VCC_SYNC H22
VCCTX_LVDS0 B30
VCCTX_LVDS1 C30
VCC3G0 AB41
VCC3G1 AJ41
VCC3G2 L41
VCC3G3 N41
VCC3G4 R41
VCC3G5 V41
VCC3G6 Y41
VCCA_3GBG G41
VSSA_3GBG H41
VCCA_3GPLL AC33
VCCTX_LVDS2 A30
VCCA_LVDS A38
VSSA_LVDS B39
VCCA_MPLL AF2
VCCA_TVBG H20
VSSA_TVBG G20
VCCA_TVDACA0 E19
VCCA_TVDACA1 F19
VCCA_TVDACB0 C20
VCCA_TVDACB1 D20
VCCA_TVDACC0 E20
VCCA_TVDACC1 F20
VCCAUX1 AF31
VCCAUX2 AE31
VCCAUX3 AC31
VCCAUX4 AL30
VCCAUX5 AK30
VCCAUX6 AJ30
VCCAUX7 AH30
VCCAUX8 AG30
VCCAUX9 AF30
VCCAUX10 AE30
VCCAUX11 AD30
VCCAUX12 AC30
VCCAUX13 AG29
VCCAUX14 AF29
VCCAUX15 AE29
VCCAUX16 AD29
VCCAUX17 AC29
VCCAUX18 AG28
VCCAUX19 AF28
VCCAUX20 AE28
VTT0
AC14
VTT1
AB14
VTT2
W14
VTT3
V14
VTT4
T14
VTT5
R14
VTT6
P14
VTT7
N14
VTT8
M14
VTT9
L14
VTT10
AD13
VTT11
AC13
VTT12
AB13
VTT13
AA13
VTT14
Y13
VTT15
W13
VTT16
V13
VTT17
U13
VTT18
T13
VTT19
R13
VTT20
N13
VTT21
M13
VTT22
L13
VTT23
AB12
VTT24
AA12
VTT25
Y12
VTT26
W12
VTT27
V12
VTT28
U12
VTT29
T12
VTT30
R12
VTT31
P12
VTT32
N12
VTT33
M12
VTT34
L12
VTT35
R11
VTT36
P11
VTT37
N11
VTT38
M11
VTT39
R10
VTT40
P10
VTT41
N10
VTT42
M10
VTT43
P9
VTT44
N9
VTT45
M9
VTT46
R8
VTT47
P8
VTT48
N8
VTT49
M8
VTT50
P7
VTT51
N7
VTT52
M7
VTT53
R6
VTT54
P6
VTT55
M6
VTT56
A6
VTT57
R5
VTT59
N5
VTT60
M5
VTT61
P4
VTT62
N4
VTT63
M4
VTT64
R3
VTT65
P3
VTT66
N3
VTT67
M3
VTT68
R2
VTT69
P2
VTT70
M2
VTT71
D2
VTT72
AB1
VTT73
R1
VTT74
P1
VTT75
N1
VTT76
M1
VCCA_CRTDAC0 E21
VCCA_CRTDAC1 F21
VSSA_CRTDAC2 G21
VCCA_DPLLA B26
VCCA_DPLLB C39
VCCA_HPLL AF1
VCCD_HMPLL0 AH1
VCCD_HMPLL1 AH2
VCCD_LVDS0 A28
VCCD_LVDS1 B28
VCCD_LVDS2 C28
VCCD_TVDAC D21
VCCDQ_TVDAC H19
VCCHV0 A23
VCCHV1 B23
VCCHV2 B25
VCCAUX21 AH22
VCCAUX22 AJ21
VCCAUX23 AH21
VCCAUX24 AJ20
VCCAUX25 AH20
VCCAUX26 AH19
VCCAUX27 P19
VCCAUX28 P16
VCCAUX29 AH15
VCCAUX30 P15
VCCAUX31 AH14
VCCAUX32
AG14
VCCAUX33
AF14
VCCAUX34
AE14
VCCAUX35
Y14
VCCAUX36
AF13
VCCAUX37
AE13
VCCAUX38
AF12
VCCAUX39
AE12
VCCAUX40
AD12
VCCAUX0 AK31
VTT58
P5
C495
0.22U_0603_10V7K
1
2
C502
0.1U_0402_16V4Z
1
2
C501
22U_0805_6.3V6M
1
2
R566
0.5_0805_1%
1 2
+
C469
220U_D2_4VM
1
2
L1
BLM21PG600SN1D_0805
1 2 L2
BLM18PG600SN1D_0603
12
C493
0.1U_0402_16V4Z
1
2
C472
4.7U_0805_10V4Z
1
2
C486
0.1U_0402_16V4Z
1
2
L7
MBK1608301YZF_0603
1 2
C492
0.47U_0603_10V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCSM_LF2
VCCSM_LF1
VCCSM_LF5
VCCSM_LF4
+VCCP
+1.5VS
+VCCP
+1.8V
+VCCP
+1.8V
+3VS
+1.8V
CFG5<9>
CFG7<9>
CFG9<9>
CFG12<9>
CFG13<9>
CFG16<9>
CFG18<9> CFG19<9> CFG20<9>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Calistoga5/6-PWR/GND
13 53Monday, January 08, 2007
CFG[11,10] Reserved
CFG[13:12]
1 = PCIE/SDVO are operating
simu.
CFG7
CFG19
(Default)
CFG20
0 = DMI x 2
CFG18
CFG[19:18] have internal pull down
*
Strap Pin Table
*
10 = All Z Mode Enabled
0 = Reserved
(Default)
1 = Normal Operation
CFG5
SDVO_CTRLDATA
*
1 = DMI Lane Reversal Enable
(Default)
*
1 = Dynamic ODT Enabled (Default)
*
(Default)
00 = Reserved
1 = 1.5V
*
*
1 = DMI x 4
CFG[3:17] have internal pull up
0 = No SDVO Device Present
(Default)
*
*
(Default)
(Default)
0 = Normal Operation
(Default)
0 = Only PCIE or SDVO is
operational.
0 = Dynamic ODT Disabled
(PCIE/SDVO select)
01 = XOR Mode Enabled
001 = 533MT/s FSB
CFG16
0 = 1.05V
011 = 667MT/s FSB
0 = Lane Reversal Enable
CFG9
1 = SDVO Device Present
CFG[2:0]
1 = Mobile Yonah CPU
11 = Normal Operation
Place near pin BA15
Place near pin BA23
Place near pin AT41 & AM41
Place near pin AV1 & AJ1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
no caps required by the
Rev1.501 check list
C535
0.47U_0603_10V7K
1
2
R570 2.2K_0402_5%
@
1 2
C517
0.1U_0402_16V4Z
1
2
R568 2.2K_0402_5%
@
1 2
C531
10U_0805_6.3V6M
1
2
+
C524
220U_D2_4VM
1
2
C509
0.47U_0603_10V7K
1
2
R567 2.2K_0402_5%
@
1 2
+
C525
330U_D2E_2.5VM_R9
1
2
C514
0.1U_0402_16V4Z
1
2
R573 1K_0402_5%
@
1 2
R574 1K_0402_5%
@
1 2
C526
0.47U_0603_10V7K
1
2
+
C533
330U_D2E_2.5VM_R9
1
2
R571 2.2K_0402_5%
@
1 2
R569 2.2K_0402_5%
@
1 2
C536
0.47U_0603_10V7K
1
2
C519
10U_0805_6.3V6M
1
2
C513
0.22U_0603_10V7K
1
2
C511
0.22U_0603_10V7K
1
2
P O W E R
U3F
CALISTOGA_FCBGA1466~D
VCC_NCTF1
AC27
VCC_NCTF2
AB27
VCC_NCTF3
AA27
VCC_NCTF4
Y27
VCC_NCTF5
W27
VCC_NCTF6
V27
VCC_NCTF7
U27
VCCAUX_NCTF52 Y15
VCC_NCTF9
R27
VCC_NCTF10
AD26
VCC_NCTF11
AC26
VCC_NCTF12
AB26
VCC_NCTF13
AA26
VCC_NCTF14
Y26
VCC_NCTF15
W26
VCC_NCTF16
V26
VCC_NCTF17
U26
VCC_NCTF18
T26
VCC_NCTF19
R26
VCC_NCTF20
AD25
VCC_NCTF21
AC25
VCC_NCTF22
AB25
VCC_NCTF23
AA25
VCC_NCTF24
Y25
VCC_NCTF25
W25
VCCAUX_NCTF53 W15
VCC_NCTF27
U25
VCC_NCTF28
T25
VCC_NCTF29
R25
VCC_NCTF30
AD24
VCC_NCTF31
AC24
VCC_NCTF32
AB24
VCC_NCTF33
AA24
VCC_NCTF34
Y24
VCC_NCTF35
W24
VCC_NCTF36
V24
VCCAUX_NCTF54 V15
VCC_NCTF38
T24
VCC_NCTF39
R24
VCC_NCTF40
AD23
VCC_NCTF41
V23
VCC_NCTF42
U23
VCC_NCTF43
T23
VCC_NCTF44
R23
VCC_NCTF45
AD22
VCC_NCTF46
V22
VCC_NCTF47
U22
VCC_NCTF48
T22
VCC_NCTF49
R22
VCC_NCTF50
AD21
VCC_NCTF51
V21
VCC_NCTF52
U21
VCC_NCTF53
T21
VCC_NCTF54
R21
VCC_NCTF55
AD20
VCC_NCTF56
V20
VCC_NCTF57
U20
VCC_NCTF58
T20
VCCAUX_NCTF55 U15
VCC_NCTF60
AD19
VCC_NCTF61
V19
VCC_NCTF62
U19
VCC_NCTF63
T19
VCC_NCTF64
AD18
VCC_NCTF65
AC18
VCC_NCTF66
AB18
VCC_NCTF67
AA18
VCC_NCTF68
Y18
VCC_NCTF69
W18
VCC_NCTF70
V18
VCC_NCTF71
U18
VCC_NCTF72
T18
VCC_NCTF0
AD27 VCCAUX_NCTF0 AG27
VCCAUX_NCTF1 AF27
VCCAUX_NCTF2 AG26
VCCAUX_NCTF3 AF26
VCCAUX_NCTF4 AG25
VCCAUX_NCTF5 AF25
VCCAUX_NCTF6 AG24
VCCAUX_NCTF7 AF24
VCCAUX_NCTF8 AG23
VCCAUX_NCTF9 AF23
VCCAUX_NCTF10 AG22
VCCAUX_NCTF11 AF22
VCCAUX_NCTF12 AG21
VCCAUX_NCTF13 AF21
VCCAUX_NCTF14 AG20
VCCAUX_NCTF15 AF20
VCCAUX_NCTF16 AG19
VCCAUX_NCTF17 AF19
VCCAUX_NCTF18 R19
VCCAUX_NCTF19 AG18
VCCAUX_NCTF20 AF18
VCCAUX_NCTF21 R18
VCCAUX_NCTF22 AG17
VCCAUX_NCTF23 AF17
VCCAUX_NCTF24 AE17
VCCAUX_NCTF25 AD17
VCCAUX_NCTF26 AB17
VCCAUX_NCTF27 AA17
VCCAUX_NCTF28 W17
VCCAUX_NCTF29 V17
VCCAUX_NCTF30 T17
VCCAUX_NCTF31 R17
VCCAUX_NCTF32 AG16
VCCAUX_NCTF33 AF16
VCCAUX_NCTF34 AE16
VCCAUX_NCTF35 AD16
VCCAUX_NCTF36 AC16
VCCAUX_NCTF37 AB16
VCCAUX_NCTF38 AA16
VCCAUX_NCTF39 Y16
VCCAUX_NCTF40 W16
VCCAUX_NCTF41 V16
VCCAUX_NCTF42 U16
VCCAUX_NCTF43 T16
VCCAUX_NCTF44 R16
VCCAUX_NCTF45 AG15
VCCAUX_NCTF46 AF15
VCCAUX_NCTF47 AE15
VCCAUX_NCTF48 AD15
VCCAUX_NCTF49 AC15
VCCAUX_NCTF50 AB15
VSS_NCTF0 AE27
VCCAUX_NCTF51 AA15
VSS_NCTF1 AE26
VCC_NCTF59
R20
VCCAUX_NCTF56 T15
VSS_NCTF2 AE25
VSS_NCTF3 AE24
VSS_NCTF4 AE23
VSS_NCTF5 AE22
VSS_NCTF6 AE21
VSS_NCTF7 AE20
VSS_NCTF8 AE19
VSS_NCTF9 AE18
VSS_NCTF10 AC17
VSS_NCTF11 Y17
VSS_NCTF12 U17
VCC_NCTF26
V25
VCCAUX_NCTF57 R15
VCC_NCTF37
U24
VCC_NCTF8
T27
VCC100
M19
VCC101
L19
VCC102
N18
VCC103
M18
VCC104
L18
VCC105
P17
VCC106
N17
VCC107
M17
VCC108
N16
VCC109
M16
VCC110
L16
VCC_SM100 AR6
VCC_SM101 AP6
VCC_SM102 AN6
VCC_SM103 AL6
VCC_SM104 AK6
VCC_SM105 AJ6
VCC_SM106 AV1
VCC_SM107 AJ1
+
C527
330U_D2E_2.5VM_R9
@
1
2
C512
0.22U_0603_10V7K
1
2
R575 1K_0402_5%
@
1 2
C515
0.1U_0402_16V4Z
1
2
C510
0.47U_0603_10V7K
1
2
P O W E R
U3G
CALISTOGA_FCBGA1466~D
VCC0
AA33
VCC1
W33
VCC2
P33
VCC3
N33
VCC4
L33
VCC5
J33
VCC6
AA32
VCC7
Y32
VCC8
W32
VCC9
V32
VCC10
P32
VCC11
N32
VCC12
M32
VCC13
L32
VCC14
J32
VCC15
AA31
VCC16
W31
VCC17
V31
VCC18
T31
VCC19
R31
VCC20
P31
VCC21
N31
VCC22
M31
VCC23
AA30
VCC24
Y30
VCC25
W30
VCC26
V30
VCC27
U30
VCC28
T30
VCC29
R30
VCC30
P30
VCC31
N30
VCC32
M30
VCC33
L30
VCC34
AA29
VCC35
Y29
VCC36
W29
VCC37
V29
VCC38
U29
VCC39
R29
VCC40
P29
VCC41
M29
VCC42
L29
VCC43
AB28
VCC44
AA28
VCC45
Y28
VCC_SM5 AY34
VCC_SM6 AW34
VCC_SM7 AV34
VCC_SM8 AU34
VCC_SM9 AT34
VCC_SM10 AR34
VCC_SM11 BA30
VCC_SM12 AY30
VCC_SM13 AW30
VCC_SM14 AV30
VCC_SM15 AU30
VCC_SM16 AT30
VCC_SM17 AR30
VCC_SM18 AP30
VCC_SM19 AN30
VCC_SM20 AM30
VCC_SM21 AM29
VCC_SM22 AL29
VCC_SM23 AK29
VCC_SM24 AJ29
VCC_SM25 AH29
VCC_SM26 AJ28
VCC_SM27 AH28
VCC_SM28 AJ27
VCC_SM29 AH27
VCC_SM30 BA26
VCC_SM31 AY26
VCC_SM32 AW26
VCC_SM33 AV26
VCC_SM34 AU26
VCC_SM35 AT26
VCC_SM36 AR26
VCC_SM37 AJ26
VCC_SM38 AH26
VCC_SM39 AJ25
VCC_SM40 AH25
VCC_SM41 AJ24
VCC_SM42 AH24
VCC_SM43 BA23
VCC_SM44 AJ23
VCC_SM45 BA22
VCC_SM46 AY22
VCC_SM47 AW22
VCC_SM48 AV22
VCC_SM49 AU22
VCC_SM50 AT22
VCC_SM51 AR22
VCC_SM52 AP22
VCC_SM53 AK22
VCC_SM54 AJ22
VCC_SM55 AK21
VCC_SM56 AK20
VCC_SM57 BA19
VCC_SM58 AY19
VCC_SM59 AW19
VCC_SM60 AV19
VCC_SM61 AU19
VCC_SM62 AT19
VCC_SM63 AR19
VCC_SM64 AP19
VCC_SM65 AK19
VCC_SM66 AJ19
VCC_SM67 AJ18
VCC_SM68 AJ17
VCC_SM69 AH17
VCC_SM70 AJ16
VCC_SM71 AH16
VCC_SM72 BA15
VCC_SM3 AU40
VCC_SM4 BA34
VCC_SM73 AY15
VCC_SM74 AW15
VCC_SM75 AV15
VCC_SM76 AU15
VCC_SM77 AT15
VCC_SM78 AR15
VCC_SM79 AJ15
VCC_SM80 AJ14
VCC_SM81 AJ13
VCC_SM82 AH13
VCC_SM83 AK12
VCC_SM84 AJ12
VCC_SM85 AH12
VCC_SM86 AG12
VCC_SM87 AK11
VCC_SM88 BA8
VCC_SM89 AY8
VCC_SM90 AW8
VCC_SM91 AV8
VCC_SM92 AT8
VCC_SM93 AR8
VCC_SM94 AP8
VCC_SM95 BA6
VCC_SM96 AY6
VCC_SM97 AW6
VCC_SM98 AV6
VCC_SM99 AT6
VCC_SM1 AT41
VCC_SM0 AU41
VCC_SM2 AM41
VCC46
V28
VCC47
U28
VCC48
T28
VCC49
R28
VCC50
P28
VCC51
N28
VCC52
M28
VCC53
L28
VCC54
P27
VCC55
N27
VCC56
M27
VCC57
L27
VCC58
P26
VCC59
N26
VCC60
L26
VCC61
N25
VCC62
M25
VCC63
L25
VCC64
P24
VCC65
N24
VCC66
M24
VCC67
AB23
VCC68
AA23
VCC69
Y23
VCC70
P23
VCC71
N23
VCC72
M23
VCC73
L23
VCC74
AC22
VCC75
AB22
VCC76
Y22
VCC77
W22
VCC78
P22
VCC79
N22
VCC80
M22
VCC81
L22
VCC82
AC21
VCC83
AA21
VCC84
W21
VCC85
N21
VCC86
M21
VCC87
L21
VCC88
AC20
VCC89
AB20
VCC90
Y20
VCC91
W20
VCC92
P20
VCC93
N20
VCC94
M20
VCC95
L20
VCC96
AB19
VCC97
AA19
VCC98
Y19
VCC99
N19
C534
0.47U_0603_10V7K
1
2
C532
10U_0805_6.3V6M
1
2
C520
1U_0603_10V4Z
1
2
C516
0.1U_0402_16V4Z
1
2
C518
10U_0805_6.3V6M
1
2
R572 2.2K_0402_5%
@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Calistoga6/6-GND
14 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
P O W E R
U3I
CALISTOGA_FCBGA1466~D
VSS0
AC41
VSS1
AA41
VSS2
W41
VSS3
T41
VSS4
P41
VSS5
M41
VSS6
J41
VSS7
F41
VSS8
AV40
VSS9
AP40
VSS10
AN40
VSS11
AK40
VSS13
AH40
VSS14
AG40
VSS15
AF40
VSS16
AE40
VSS17
B40
VSS18
AY39
VSS19
AW39
VSS21
AR39
VSS22
AN39
VSS24
AC39
VSS25
AB39
VSS26
AA39
VSS27
Y39
VSS28
W39
VSS29
V39
VSS30
T39
VSS31
R39
VSS32
P39
VSS33
N39
VSS34
M39
VSS35
L39
VSS36
J39
VSS37
H39
VSS20
AV39
VSS23
AJ39
VSS12
AJ40
VSS38
G39
VSS40
D39
VSS41
AT38
VSS42
AM38
VSS43
AH38
VSS44
AG38
VSS45
AF38
VSS46
AE38
VSS47
C38
VSS48
AK37
VSS49
AH37
VSS50
AB37
VSS51
AA37
VSS52
Y37
VSS53
W37
VSS54
V37
VSS55
T37
VSS56
R37
VSS57
P37
VSS58
N37
VSS59
M37
VSS60
L37
VSS61
J37
VSS62
H37
VSS63
G37
VSS64
F37
VSS65
D37
VSS66
AY36
VSS67
AW36
VSS68
AN36
VSS69
AH36
VSS70
AG36
VSS71
AF36
VSS72
AE36
VSS73
AC36
VSS74
C36
VSS75
B36
VSS76
BA35
VSS77
AV35
VSS78
AR35
VSS79
AH35
VSS80
AB35
VSS81
AA35
VSS82
Y35
VSS83
W35
VSS84
V35
VSS85
T35
VSS86
R35
VSS87
P35
VSS88
N35
VSS89
M35
VSS90
L35
VSS91
J35
VSS92
H35
VSS93
G35
VSS94
F35
VSS95
D35
VSS96
AN34
VSS97
AK34
VSS98
AG34
VSS99
AF34
VSS39
F39
VSS100 AE34
VSS101 AC34
VSS102 C34
VSS103 AW33
VSS104 AV33
VSS105 AR33
VSS106 AE33
VSS107 AB33
VSS108 Y33
VSS109 V33
VSS110 T33
VSS111 R33
VSS112 M33
VSS113 H33
VSS114 G33
VSS115 F33
VSS116 D33
VSS117 B33
VSS118 AH32
VSS119 AG32
VSS120 AF32
VSS121 AE32
VSS122 AC32
VSS123 AB32
VSS124 G32
VSS125 B32
VSS126 AY31
VSS127 AV31
VSS128 AN31
VSS129 AJ31
VSS130 AG31
VSS131 AB31
VSS132 Y31
VSS133 AB30
VSS134 E30
VSS135 AT29
VSS136 AN29
VSS137 AB29
VSS138 T29
VSS139 N29
VSS140 K29
VSS141 G29
VSS142 E29
VSS143 C29
VSS144 B29
VSS145 A29
VSS146 BA28
VSS147 AW28
VSS148 AU28
VSS149 AP28
VSS150 AM28
VSS151 AD28
VSS152 AC28
VSS153 W28
VSS154 J28
VSS155 E28
VSS156 AP27
VSS157 AM27
VSS158 AK27
VSS159 J27
VSS160 G27
VSS161 F27
VSS162 C27
VSS163 B27
VSS164 AN26
VSS165 M26
VSS166 K26
VSS167 F26
VSS168 D26
VSS169 AK25
VSS170 P25
VSS171 K25
VSS172 H25
VSS173 E25
VSS174 D25
VSS175 A25
VSS176 BA24
VSS177 AU24
VSS178 AL24
VSS179 AW23
VSS180 AT23
VSS181 AN23
VSS182 AM23
VSS183 AH23
VSS184 AC23
VSS185 W23
VSS186 K23
VSS187 J23
VSS188 F23
VSS189 C23
VSS190 AA22
VSS191 K22
VSS192 G22
VSS193 F22
VSS194 E22
VSS195 D22
VSS196 A22
VSS197 BA21
VSS198 AV21
VSS199 AR21
P O W E R
U3J
CALISTOGA_FCBGA1466~D
VSS200
AN21
VSS201
AL21
VSS202
AB21
VSS203
Y21
VSS204
P21
VSS205
K21
VSS206
J21
VSS207
H21
VSS208
C21
VSS209
AW20
VSS210
AR20
VSS211
AM20
VSS212
AA20
VSS213
K20
VSS214
B20
VSS215
A20
VSS216
AN19
VSS217
AC19
VSS218
W19
VSS219
K19
VSS220
G19
VSS221
C19
VSS222
AH18
VSS223
P18
VSS224
H18
VSS225
D18
VSS226
A18
VSS227
AY17
VSS228
AR17
VSS229
AP17
VSS230
AM17
VSS231
AK17
VSS232
AV16
VSS233
AN16
VSS234
AL16
VSS235
J16
VSS236
F16
VSS237
C16
VSS238
AN15
VSS239
AM15
VSS240
AK15
VSS241
N15
VSS242
M15
VSS243
L15
VSS244
B15
VSS245
A15
VSS246
BA14
VSS247
AT14
VSS248
AK14
VSS249
AD14
VSS250
AA14
VSS251
U14
VSS252
K14
VSS253
H14
VSS254
E14
VSS255
AV13
VSS256
AR13
VSS257
AN13
VSS258
AM13
VSS259
AL13
VSS260
AG13
VSS261
P13
VSS262
F13
VSS266
AC12
VSS267
K12
VSS268
H12
VSS269
E12
VSS270
AD11
VSS271
AA11
VSS272
Y11
VSS273
J11
VSS274
D11
VSS275
B11
VSS276
AV10
VSS277
AP10
VSS278
AL10
VSS279
AJ10
VSS265
D13
VSS264
B13
VSS263
AY12
VSS285 AW9
VSS286 AR9
VSS287 AH9
VSS288 AB9
VSS289 Y9
VSS290 R9
VSS292 G9
VSS291 E9
VSS293 A9
VSS294 AG8
VSS295 AD8
VSS296 AA8
VSS297 U8
VSS298 K8
VSS299 C8
VSS300 BA7
VSS301 AV7
VSS302 AP7
VSS303 AL7
VSS304 AJ7
VSS305 AH7
VSS306 AF7
VSS307 AC7
VSS308 R7
VSS309 G7
VSS310 D7
VSS311 AG6
VSS312 AD6
VSS313 AB6
VSS314 Y6
VSS317 K6
VSS318 H6
VSS319 B6
VSS320 AV5
VSS321 AF5
VSS322 AD5
VSS323 AY4
VSS324 AR4
VSS325 AP4
VSS326 AL4
VSS327 AJ4
VSS328 Y4
VSS329 U4
VSS330 R4
VSS331 J4
VSS332 F4
VSS333 C4
VSS334 AY3
VSS335 AW3
VSS336 AV3
VSS337 AL3
VSS341 AD3
VSS345 AT2
VSS346 AR2
VSS347 AP2
VSS348 AK2
VSS351 AB2
VSS352 Y2
VSS353 U2
VSS354 T2
VSS355 N2
VSS356 J2
VSS357 H2
VSS359 C2
VSS360 AL1
VSS358 F2
VSS349 AJ2
VSS350 AD2
VSS344 G3
VSS343 AA3
VSS342 AC3
VSS340 AF3
VSS338 AH3
VSS280 AG10
VSS281 AC10
VSS282 W10
VSS283 U10
VSS284 BA9
VSS315 U6
VSS316 N6
VSS339 AG3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D11
DDR_A_D39
DDR_A_D35
DDR_A_D59
DDR_A_D58
DDR_A_D10
DDR_A_D63
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D42
DDR_A_D43
DDR_A_D60
DDR_A_D57
DDR_A_D25
DDR_A_D24
DDR_A_D47
DDR_A_D46
DDR_A_D56
DDR_A_D61
DDR_A_D50
DDR_A_D13
DDR_A_D51
DDR_A_D12
DDR_A_D55
DDR_A_D22
DDR_A_D19
DDR_A_D0
DDR_A_D4
DDR_A_D23
DDR_A_D18
DDR_A_D14
DDR_A_D52
V_DDR_MCH_REF
DDR_A_MA11
DDR_A_D53
DDR_CKE1_DIMMA
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR0
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
ICH_SMBCLK
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3
DDR_A_MA9 DDR_A_MA7
DDR_A_MA12
DDR_A_MA5
DDR_A_WE#
DDR_A_D8
DDR_A_D3
DDR_A_D2
DDR_A_D17
DDR_A_D21
DDR_A_D30
DDR_A_D27
DDR_A_D7
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DM3
DDR_A_DM1
DDR_A_DM2
DDR_A_DM0
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS7
ICH_SMBDATA
DDR_CKE0_DIMMA
DDR_A_MA8
DDR_CS1_DIMMA#
DDR_A_MA11
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_CAS#
DDR_A_D15
DDR_A_D20
DDR_A_D9
DDR_A_D16
DDR_A_D28
DDR_A_D26
DDR_A_D31
DDR_A_D33
DDR_A_D36
DDR_A_D37
DDR_A_D29
DDR_A_D32
DDR_A_D49
DDR_A_D48
DDR_A_D54
DDR_A_DM6
DDR_A_DM4
DDR_A_DM5
DDR_A_DM7
DDR_A_MA13
DDR_A_DQS5
DDR_A_BS#0
DDR_A_BS#2
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_MA0
DDR_A_MA4
DDR_A_BS#1
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA6
DDR_A_MA2
DDR_A_D1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT1
M_ODT0
DDR_A_MA13
DDR_A_MA7
M_ODT0
DDR_A_D5
DDR_A_D6
DDR_A_D41
DDR_A_D45 DDR_A_D40
DDR_A_D44
DDR_A_BS#1
DDR_A_RAS#
EC_EXTTS#0
M_ODT1
DDR_CS1_DIMMA#
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA10
DDR_A_BS#0
DDR_A_MA3
DDR_A_MA1
DDR_A_MA8
DDR_A_MA5
DDR_A_MA12
DDR_A_MA9
DDR_CKE0_DIMMA
DDR_A_BS#2
+1.8V
+0.9VS
+3VS
+1.8V
+1.8V
+0.9VS
+1.8V
DDR_A_CAS#<10>
DDR_CS1_DIMMA#<9>
V_DDR_MCH_REF <9,16>
M_CLK_DDR0 <9>
M_ODT1<9>
M_CLK_DDR#0 <9>
DDR_CKE1_DIMMA <9>
DDR_A_BS#1 <10>
DDR_A_RAS# <10>
ICH_SMBDATA<5,6,16,22,24>
DDR_CS0_DIMMA# <9>
M_ODT0 <9>
M_CLK_DDR1 <9>
M_CLK_DDR#1 <9>
DDR_A_DQS#[0..7]<10>
DDR_A_D[0..63]<10>
EC_EXTTS#0 <9,16,33>
DDR_A_DM[0..7]<10>
DDR_A_DQS[0..7]<10>
DDR_A_MA[0..13]<10>
DDR_CKE0_DIMMA<9>
DDR_A_BS#2<10>
DDR_A_BS#0<10> DDR_A_WE#<10>
ICH_SMBCLK<5,6,16,22,24>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
DDRII SO-DIMM A
15 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Layout Note:
Place these resistor
closely JP4,all
trace length Max=1.5"
Layout Note:
Place near JP4
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
REVERSE
SO-DIMM A
Add C611, C612 follow Motion's request
C611
0.1U_0402_16V4Z
1
2
C560
0.1U_0402_16V4Z
1
2
RP1
56_0404_4P2R_5%
1 4
2 3
RP9
56_0404_4P2R_5%
1 4
2 3
RP3
56_0404_4P2R_5%
1 4
2 3
C542
2.2U_0805_16V4Z
1
2
C538
0.1U_0402_16V4Z
1
2
C546
0.1U_0402_16V4Z
1
2
C551
0.1U_0402_16V4Z
1
2
C540
2.2U_0805_16V4Z
1
2
C612
0.1U_0402_16V4Z
1
2
RP4 56_0404_4P2R_5%
14 23
C555
0.1U_0402_16V4Z
1
2
RP11
56_0404_4P2R_5%
1 4
2 3
RP8 56_0404_4P2R_5%
14 23
C559
0.1U_0402_16V4Z
1
2
C548
0.1U_0402_16V4Z
1
2
RP13 56_0404_4P2R_5%
14 23
C550
0.1U_0402_16V4Z
1
2
RP10 56_0404_4P2R_5%
14 23
C539
2.2U_0805_16V4Z
1
2
C544
0.1U_0402_16V4Z
1
2
C547
0.1U_0402_16V4Z
1
2
C554
0.1U_0402_16V4Z
1
2
C558
0.1U_0402_16V4Z
1
2
C537
2.2U_0805_16V4Z
1
2
RP5
56_0404_4P2R_5%
1 4
2 3
C561
0.1U_0402_16V4Z
1
2
+
C528
220U_D2_4VM
@
1
2
RP12 56_0404_4P2R_5%
14 23
C543
2.2U_0805_16V4Z
1
2
JP4
FOX_ASOA426-M2R-TR
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD
199
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SAO 198
SA1 200
C549
0.1U_0402_16V4Z
1
2
RP6 56_0404_4P2R_5%
14 23
R577
10K_0402_5%
12
C541
2.2U_0805_16V4Z
1
2
C553
0.1U_0402_16V4Z
1
2
R579 0_0402_5%@1 2
C557
0.1U_0402_16V4Z
1
2
R578
10K_0402_5%
12
C545
0.1U_0402_16V4Z
1
2
RP7
56_0404_4P2R_5%
1 4
2 3
C552
0.1U_0402_16V4Z
1
2
C556
0.1U_0402_16V4Z
1
2
RP2 56_0404_4P2R_5%
14 23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_CS3_DIMMB#
DDR_B_D27
DDR_CS3_DIMMB#
DDR_B_WE#
DDR_B_D29
DDR_B_D25
DDR_B_D24
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_D28
DDR_B_D26
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_MA9
DDR_B_MA5
DDR_B_MA12
DDR_B_MA8
M_ODT3
M_ODT2
DDR_B_D19
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS#4
DDR_B_MA3
DDR_B_MA10
DDR_B_MA1
DDR_B_DQS#6
DDR_B_MA9
DDR_B_D8
DDR_B_WE#
DDR_B_MA5
DDR_B_MA12
V_DDR_MCH_REF
DDR_B_D5
DDR_B_D9
DDR_B_D7
DDR_B_D3
DDR_B_D0
DDR_B_D10
DDR_B_D23
DDR_B_D40
DDR_B_D11
DDR_B_D22
DDR_B_D37
DDR_B_D35
DDR_B_D36
DDR_B_D34
DDR_B_D60
DDR_B_D47
DDR_B_DQS4
DDR_B_BS#2
DDR_B_DM3
DDR_B_D59
DDR_B_D61
DDR_B_DQS#0
DDR_B_D41
DDR_B_DQS2
DDR_B_DM7
DDR_B_BS#0
DDR_B_D48
DDR_B_D42
DDR_B_DQS0
DDR_B_MA8
DDR_B_DM5
DDR_B_DQS1
DDR_B_DQS6
DDR_B_DQS#1
DDR_B_CAS#
DDR_B_D58
DDR_B_D53
DDR_B_D20 DDR_B_D16DDR_B_D21 DDR_B_D18
DDR_B_MA11
DDR_B_MA2
DDR_B_D6
DDR_B_MA6
DDR_B_MA4
DDR_B_MA0
DDR_B_D1
DDR_B_D2
DDR_B_D4
DDR_B_RAS#
DDR_B_BS#1
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D15
DDR_B_D33
DDR_B_D32
DDR_B_D45
DDR_B_D46
DDR_B_D44
DDR_B_D43
DDR_B_D49
DDR_B_D57
DDR_B_D52
DDR_B_D63
DDR_B_D56
DDR_B_D62
DDR_B_D54
DDR_B_D55
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DM4
DDR_B_DM6
DDR_B_MA7
DDR_B_DQS#7
DDR_B_DQS#5
DDR_B_DM1
DDR_B_DQS5
DDR_B_DQS7
DDR_B_MA13
DDR_B_DM2
DDR_CKE3_DIMMB
DDR_B_MA6
DDR_B_D50
DDR_B_D51
DDR_B_D39
DDR_B_D38
DDR_B_DM0
DDR_CKE3_DIMMB
ICH_SMBCLK
DDR_CS2_DIMMB#
ICH_SMBDATA
DDR_CKE2_DIMMB
DDR_B_D31
DDR_B_D30
DDR_B_MA1
DDR_B_BS#0
DDR_B_CAS#
DDR_B_MA3
DDR_B_MA10
EC_EXTTS#0
M_ODT3
DDR_B_BS#2
DDR_CKE2_DIMMB
DDR_B_MA7
DDR_B_MA11
DDR_B_MA2
DDR_B_MA4
DDR_B_BS#1
DDR_B_MA0
DDR_CS2_DIMMB#
DDR_B_RAS#
DDR_B_MA13
M_ODT2
+1.8V
+3VS
+3VS
+1.8V
+0.9VS
+1.8V
+0.9VS
DDR_B_DQS#[0..7]<10>
DDR_B_D[0..63]<10>
DDR_B_DM[0..7]<10>
DDR_B_DQS[0..7]<10>
DDR_B_MA[0..13]<10>
DDR_CKE2_DIMMB<9>
DDR_B_BS#2<10>
DDR_B_BS#0<10> DDR_B_WE#<10>
DDR_B_CAS#<10>
DDR_CS3_DIMMB#<9>
M_ODT3<9>
M_CLK_DDR3 <9>
M_CLK_DDR#3 <9>
DDR_CKE3_DIMMB <9>
DDR_B_BS#1 <10>
DDR_B_RAS# <10>
DDR_CS2_DIMMB# <9>
ICH_SMBCLK<5,6,15,22,24>
ICH_SMBDATA<5,6,15,22,24>
M_ODT2 <9>
M_CLK_DDR2 <9>
M_CLK_DDR#2 <9>
V_DDR_MCH_REF <9,15>
EC_EXTTS#0 <9,15,33>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
DDRII SO-DIMM B
16 53Monday, January 08, 2007
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SO-DIMM B
STANDARD
Layout Note:
Place near JP5
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"
Add C619, C625 follow Motion's request
RP25
56_0404_4P2R_5%
1 4
2 3
RP19 56_0404_4P2R_5%
14 23
C582
0.1U_0402_16V4Z
1
2
C619
0.1U_0402_16V4Z
1
2
RP16
56_0404_4P2R_5%
1 4
2 3
C578
0.1U_0402_16V4Z
1
2
C570
0.1U_0402_16V4Z
1
2
RP26 56_0404_4P2R_5%
14 23
C585
0.1U_0402_16V4Z
1
2
R580
10K_0402_5%
1 2
C625
0.1U_0402_16V4Z
1
2
C573
0.1U_0402_16V4Z
1
2
C574
0.1U_0402_16V4Z
1
2
C569
0.1U_0402_16V4Z
1
2
C581
0.1U_0402_16V4Z
1
2
C566
2.2U_0805_16V4Z
1
2
C563
0.1U_0402_16V4Z
1
2
RP28
56_0404_4P2R_5%
14 23
C564
2.2U_0805_16V4Z
1
2
C571
0.1U_0402_16V4Z
1
2
C577
0.1U_0402_16V4Z
1
2
RP18
56_0404_4P2R_5%
1 4
2 3
RP21 56_0404_4P2R_5%
14 23
C584
0.1U_0402_16V4Z
1
2
RP17 56_0404_4P2R_5%
14 23
RP23
56_0404_4P2R_5%
1 4
2 3
C580
0.1U_0402_16V4Z
1
2
C567
2.2U_0805_16V4Z
1
2
C572
0.1U_0402_16V4Z
1
2
RP24 56_0404_4P2R_5%
14 23
C562
2.2U_0805_16V4Z
1
2
C576
0.1U_0402_16V4Z
1
2
JP5
QTC_C111A-040SP31
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD
199
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SAO 198
SA1 200
R634 0_0402_5%@1 2
C565
2.2U_0805_16V4Z
1
2
C583
0.1U_0402_16V4Z
1
2
R581
10K_0402_5%
12
RP20
56_0404_4P2R_5%
1 4
2 3
RP14
56_0404_4P2R_5%
1 4
2 3
C579
0.1U_0402_16V4Z
1
2
C568
2.2U_0805_16V4Z
1
2
RP15 56_0404_4P2R_5%
14 23
C586
0.1U_0402_16V4Z
1
2
C575
0.1U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LVDSCLKA+
LVDSCLKB-
LVDSCLKB+
LVDSB_D0-
LVDSB_D0+
LVDSB_D1-
LVDSB_D1+
LVDSB_D2-
LVDSB_D2+
PDCT
LCD_I2C_CLK
LVDSA_D1-
LVDSA_D1+
LVDSA_D2-
LVDSA_D2+
DISPOFF#
LVDSCLKA-
LVDSA_D0-
LVDSA_D0+
LCD_I2C_DAT
ID0
PID0
PID1
ID0ID1
ENVDD
PWM_CTL
CHARGE_LED# BATT_LED# PWR_LED#
PID1
ID1
PID0
GM_PWM
INVT_PWM
LED_PWM
LED_PWM_R
+LCDVDD+
B+
+3VS
Invert_B+
Invert_B+
+3VS
+3VS
+12VALW +LCDVDD
+LCDVDD
+3VS
+3VS
+12VALW
+5VALW +5VALW +5VALW
+3VS
+5VALW
+LCDVDD
DIGISUSP<33> RXDB#<35> TXDB<35>
CTSB#<35> DTRB#<35>
PDCT<33>
LVDSA_D2+<11> LVDSA_D2-<11>
LVDSA_D1+<11> LVDSA_D1-<11>
LVDSA_D0+<11> LVDSA_D0-<11>
INVT_PWM<33>
DAC_BRIG<33>
LCD_I2C_DAT<11> LCD_I2C_CLK<11>
GM_PWM<11>
DIGI_RST#<33>
LVDSB_D0+<11>
LVDSB_D1+<11>
LVDSB_D2+<11>
LVDSB_D0-<11>
LVDSB_D1-<11>
LVDSB_D2-<11>
LVDSCLKA+<11> LVDSCLKA-<11>
LVDSCLKB+<11> LVDSCLKB-<11>
ENABLT<11,33>
BKOFF#<33>
ENVDD<11>
ID1<22> ID0 <22>
CHARGE_LED#<33> BATT_LED#<33> PWR_LED#<33>
PID1<22> PID0 <22>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
LCD Conn&Inverter /LED dimming control
17 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LCD CONN.
600mA
Reserved for EMI
Close to JP6
BATTERY CHARGE BATTERY FULL POWER ON
0
1
0ID0 config
0
1Digitizer
Reserve
0
1
ID1
N-Trig
1TouchPanel 0
1
0PID0 config
0
1
Toshiba SXGA+
Hydis XGA
0
1
PID1
Hydis SXGA+
1
Toshiba XGA
Reserved for EMI
R640
100K_0402_5%
@
12
R590
4.7K_0402_5%
@
12
R635
100K_0402_5%
12
G
D
S
Q66
AO3413_SOT23
2
1 3
C610 0.1U_0402_16V4Z
1 2
R587
150K_0402_5%
12
G
D
S
Q5
2N7002_SOT23
2
13
R593
10K_0402_5%
12
G
D
S
Q64
AO3413_SOT23
2
1 3
R642 0_0402_5%
1 2
R591 0_0402_5%@
1 2
D15
HT-170Y-DT_0805
21
D19
HT-170NB-DTP/C_BLUE_0805
21
R716
100K_0402_5%
@
12
C591
0.01U_0603_50V4Z
1
2
R712 0_0402_5%
@
1 2
R582
100K_0402_5%
12
R641
10K_0402_5%
12
J3
NO SHORT 2x2m
2 1
R364
120_0402_5%
1 2
R717
10K_0402_5%
12
G
D
S
Q65
AO3413_SOT23
2
1 3
G
D
S
Q4
2N7002_SOT23
2
13
C589
0.1U_0402_16V4Z
1
2
R583
470_0402_5%
12
R636 100K_0402_5%
1 2
D16
HT-170NB-DTP/C_BLUE_0805
21
R262 0_0603_5%
1 2
G
D
S
Q16
2N7002_SOT23
2
13
D45
PSOT24C-LF_T7_SOT23-3
2
3
1
C587
10U_0805_10V4Z
1
2
R633
100K_0402_5%
@
12
J2
NO SHORT 2x2m
2 1
C590
0.01U_0402_16V7K
1
2
R330
10K_0402_5%
1 2
C588
0.1U_0402_16V4Z
1
2
C592
0.1U_0603_25V7K
1
2
R263 0_0603_5%
1 2
G
D
S
Q3
AO3402_SOT23
2
13
R588
100K_0402_5%@
12
R924
22K_0402_5%
12
22K
22K
Q6
DTC124EKAT146_SOT23
2
13
C681
10U_0805_10V4Z
1
2
U19
TC7SH08FUF_SSOP5
B
1
A
2Y4
P5
G
3
JP7
MOLEX_53780-0790
1
2
3
4
5
6
7
R291
0_0603_5%
12
R317
220_0402_5%
1 2
R6
510_0402_5%
12
R290
0_0603_5%
12
R315
220_0402_5%
1 2
R589
10K_0402_5%
12
JP6
IPEX_20143-040E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
R331
10K_0402_5%
1 2
R592 0_0402_5%
1 2
R584
100K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AS
DVI_DVDD_1.8V
DVI_DVDD_2.5VDVI_V10
DVI_V7
DVI_CLK+
DVI_TX1+
DVI_TX0-
DVI_TX0+
DVI_CLK-
DVI_TX2+
DVI_TX2-
DVI_V2
DVI_AVDD_3V
DVI_DVDD_2.5V
DVI_DVDD_1.8V
DVI_V3 DVI_DVDD_1.8V
I2C_ADD
DVI_DVDD_2.5V DVI_V5 DVI_DVDD_2.5V
DVI_DETECT
DVI_CLK+
DVI_CLK-
DVI_TX2+
DVI_TX1+
DVI_TX2-
DVI_TX0+
DVI_TX1-
DVI_TX0-
SDVO_SDAT
SDVO_SCLK
DVI_DDC_CLK
1362_SDA_DDC
1362_SCL_DDC
DVI_DDC_DAT1362_SDA_DDC
DVI_DVDD_1.8V
SDVO_SCLK
DVI_AVDD_3V
SDVO_SDAT
DVI_DDC_DAT
DVI_V6
DVI_V1 DVI_DVDD_1.8V
DVI_V9 DVI_DVDD_2.5V
DVI_AVDD_3V
DVI_V8
DVI_DDC_CLK1362_SCL_DDC
DVI_V4
AS
DVI_DETECT
DVI_CLK+
DVI_CLK-
DVI_TX2+
DVI_TX1+
DVI_TX2-
DVI_TX0+
DVI_TX1-
DVI_TX0-
DVI_DDC_CLK
DVI_DDC_DAT
DVI_AVDD_3V
DVI_AVDD_3V
DVI_AVDD_3V
DVI_TX1-
DVI_TX0-
DVI_TX0+
DVI_TX1-
DVI_TX1+
DVI_TX2-
DVI_TX2+
DVI_CLK-
DVI_CLK+
DVI_DDC_CLK
DVI_DDC_DAT DVI_DETECT
DVI_DETECT
DVI_DETECT#
+2.5VS
+3VS
+2.5VS
+1.8VS
+5VS +5VS
+2.5VS
+5VS
+5VS
+3VS
+5VS +5VS
+5VS +5VS
+5VS +5VS
SDVOB_INT+<11> SDVOB_INT-<11>
SDVOB_R+<11> SDVOB_R-<11>
SDVOB_G+<11> SDVOB_G-<11>
SDVOB_CLK+<11> SDVOB_CLK-<11>
SDVOB_B+<11> SDVOB_B-<11>
PLT_RST#<9,20,22,24,28,32,33,35>
SDVO_SDAT <11>
SDVO_SCLK <11>
DVI_DETECT# <20>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
DVI CONN
18 53Monday, January 08, 2007
Note:
Install DVI-Ra 1K_0402_5% for SiI1362
Install DVI-Ra 0_0402_5% for CH7307
DVI-Ra
W=20 mils
Note: Address = 0x70
Install DVI-Rb 0_0402_5% for SiI1362
DVI-Rb
Note: Address = 0x72
Install DVI-Rb 10K_0402_5% for CH7307
DVI CONTROLLER
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R597 0_0402_5%DVI_1362@
1 2
R610
300_0402_5%DVI_1362@
1 2
G
D
S
Q11
2N7002_SOT23
2
13
R617 0_0402_5%DVI_1362@
1 2
L11
0_0603_5%DVI_1362@
1 2
R605
300_0402_1%@
1 2
R613 0_0402_5%DVI_7307@
1 2
R620
0_0402_5%
DVI_1362@
1 2
R601 0_0402_5%DVI_1362@
1 2
R630 0_0402_5%
DVI_1362@
1 2
R602 0_0402_5%DVI_7307@
1 2
C605
0.1U_0402_16V4Z
DVI_1362@
1
2
C597
0.1U_0402_16V4Z
@
1
2
R598 0_0402_5%DVI_7307@
1 2
R599 0_0402_5%DVI_1362@
1 2
R604
300_0402_1%@
1 2
D41
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
R594
300_0402_1%@
1 2
C608
150P_0402_50V8J
1
2
C604
0.1U_0402_16V4Z
@
1
2
C595
10U_0805_10V4Z
DVI_1362@
1
2
R595
300_0402_1%@
12
R623
1K_0402_5%DVI_1362@
1 2
R632
0_0402_5%
DVI_7307@
12
R631
1K_0402_5%
DVI_1362@
12
C600
10U_0805_10V4Z
DVI_7307@
1
2
R619
0_0402_5%
DVI_1362@
1 2
R612 2.7K_0402_5%
1 2
C594
0.1U_0402_16V4Z
DVI_1362@
1
2
C599
0.1U_0402_16V4ZDVI_7307@
1
2
R628
0_0402_5%
DVI_1362@
12
C603
0.1U_0402_16V4Z
@
1
2
R596 0_0402_5%DVI_7307@
1 2
R622
10K_0402_5%
@
12
R627
1K_0402_5%@
12
R282 10K_0402_5%
12
D43
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
R615 0_0402_5%DVI_1362@
1 2
R618
10K_0402_5%
DVI_7307@
12
L9
0_0603_5%DVI_1362@
1 2
L10
0_0603_5%DVI_7307@
1 2
JP8
JAE_DD2R040HP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R616
1.2K_0402_5%
DVI_7307@
12
D40
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
R606 0_0402_5%DVI_7307@
1 2
C607
10U_0805_10V4Z
DVI_1362@
1
2
C602 0.1U_0402_16V4Z
1 2
R626 0_0402_5%DVI_1362@
1 2
C596
0.1U_0402_16V4Z
@
1
2C598
0.1U_0402_16V4ZDVI_7307@
1
2
C593
0.1U_0402_16V4Z
DVI_1362@
1
2
R611 0_0402_5%DVI_7307@
1 2
R629 0_0402_5%
DVI_1362@
1 2
U4
CH7307C-DEF_LQFP48
HPDET 29
ATPG
27
SDVOB_INT+
32
SDVOB_INT-
33
NC
35
SC_PROM 9
SD_PROM 8
SPD 5
SPC 4
SDVOB_R+
37
SDVOB_R-
38
SDVOB_G+
40
SDVOB_G-
41
SDVOB_B+
43
SDVOB_B-
44
SDVOB_CLK+
46
SDVOB_CLK-
47
AS
3
RESET#
2
SCEN
26
VSWING
25
SC_DDC 11
SD_DDC 10
NC
34
DVDD 12
DVDD 28
AVDD_PLL 1
TVDD 15
TVDD 21
AVDD 36
AVDD 42
AVDD 48
DGND
7
DGND
30
AGND
31
AGND
39
AGND
45
TGND
18
TGND
24
AGND_PLL
6
TLC# 13
TLC 14
TDC0# 16
TDC0 17
TDC1# 19
TDC1 20
TDC2# 22
TDC2 23
ThermmaoGND
49
D42
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
C601 0.1U_0402_16V4Z
1 2
R621
10K_0402_5%
DVI_7307@
12
R625
16K_0402_5%
12
R603 0_0402_5%DVI_1362@
1 2
D39
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
R607 0_0402_5%DVI_1362@
1 2
R614 2.7K_0402_5%
1 2
R609 0_0402_5%DVI_1362@
1 2
R600 0_0402_5%DVI_7307@
1 2
R624
16K_0402_5%
12
C606
0.1U_0402_16V4Z
DVI_1362@
1
2
R608 0_0402_5%DVI_7307@
1 2
D44
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CRT_B_MB
CRT_G_MB
CRT_R_MB
CRT_R
CRT_G
CRT_B
CRT_R_MB
CRT_G_MB
CRT_B_MB
CRT_R_DOCK
CRT_G_DOCK
CRT_B_DOCK
CRTR
CRTG
CRTB
CRTR
CRTG
HSYNC
CRTB
VSYNC
M_SEN#
3VDDCCL_R
DOCKEN_VGA
CRT_HSYNC
CRT_HSYNC_DOCK
CRT_VSYNC_DOCK
CRT_VSYNC
CRT_HSYNCMB
CRT_HSYNCDOCK
CRT_VSYNCMB
CRT_VSYNCDOCK
3VDDCDA_R3VDDCDA
3VDDCCL
HSYNC
VSYNC
+5VS
+3VS
CRTVCC
+3VS
+2.5VS
+5VS
+5VS
+3VS
+5VS
+5VS
+5VS
+5VS
CRT_R_DOCK <36>
CRT_G_DOCK <36>
CRT_B_DOCK <36>
DOCKEN_VGA <33,34>
CRT_R<11> CRT_G<11> CRT_B<11>
M_SEN#<22,36>
CRT_HSYNC<11>
CRT_HSYNC_DOCK <36>
CRT_VSYNC<11>
CRT_VSYNC_DOCK <36>
3VDDCDA_R<36>
3VDDCDA<11>
3VDDCCL_R<36>
3VDDCCL<11>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
CRT CONN
19 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DOCKEN 0: TO MB
1: TO DOCK
To DOCK
C343
100P_0402_50V8J
1
2
R147
1K_0402_5%
1 2
L13
FBMA-L11-201209-170LMT
1 2
D34
DAN217_SC59
@
2
3
1
C609
0.1U_0402_16V4Z
1
2
C633
0.1U_0402_16V4Z
1
2
R146
1K_0402_5%
1 2
D31
DAN217_SC59
@
2
3
1
D35
DAN217_SC59
@
2
3
1
C614
6P_0402_50V8K
1
2
JP12
ALLTO_C10510-115A5-L_15P
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
R1159
39_0402_5%
12
R145
1K_0402_5%
1 2
R143
2.2K_0402_5%
1 2
R1154
39_0402_5%
12
F1
1.1A 6V UL/CSA/TUV
21
U6
PI5V330QE_QSOP16
S1A 2
S2A 3
S1B 5
S2B 6
S1C 11
S2C 10
S1D 14
S2D 13
DA
4
DB
7
DC
9
DD
12
GND
8
EN 15
IN 1
VCC
16
C617
6P_0402_50V8K
1
2
R1155
39_0402_5%
12
R371
10K_0402_5%
1 2
C618
6P_0402_50V8K
1
2
R141
2.2K_0402_5%
1 2
R372
10K_0402_5%
1 2
C615
6P_0402_50V8K
1
2
C671
0.1U_0402_16V4Z
1
2
C613
6P_0402_50V8K
1
2
R637
133_0402_1%
G
D
S
Q8
BSS138W-7-F_SOT323~D
2
13
U5
74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
U7
74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
C620
0.1U_0402_16V4Z
1
2
G
D
S
Q49
BSS138W-7-F_SOT323~D
2
13
R1158
39_0402_5%
12
D29
RB491D_SOT23
2 1
R638
133_0402_1%
R144
2.2K_0402_5%
1 2
D3
DAN217_SC59
@
2
3
1
R142
2.2K_0402_5%
1 2
C672
0.1U_0402_16V4Z
1
2
R639
133_0402_1%
L12
FBMA-L11-201209-170LMT
1 2
L16
FBMA-L11-201209-170LMT
1 2
U51
74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
R148
1K_0402_5%
1 2
C616
6P_0402_50V8K
1
2
C677
0.1U_0402_16V4Z
1
2
D4
DAN217_SC59
@
2
3
1
U52
74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI_REQ2#
PCI_PIRQD#
PCI_AD0
PCI_REQ4#
PCI_AD1
CLK_PCI_ICH
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD7
PCI_AD6
PCI_AD8
PCI_AD9
PCI_AD11
PCI_AD10
PCI_AD14
PCI_AD15
PCI_AD13
PCI_AD12
PCI_AD16
PCI_AD17
PCI_AD19
PCI_AD18
PCI_AD22
PCI_AD23
PCI_AD21
PCI_AD20
PCI_AD25
PCI_AD24
PCI_AD28
PCI_AD29
PCI_AD31
PCI_AD30
PCI_AD26
PCI_AD27
PCI_GNT2#
PCI_REQ3#
PCI_SERR#
PLT_RST#
PCI_PLTRST#
PCI_PIRQH#
PCI_PIRQG#
PCI_PIRQF#
PCI_PIRQE#PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#
PCI_PME#
PCI_REQ3#
PCI_PLTRST#
PCI_IRDY#
PCI_PLOCK#
PCI_SERR#
PCI_PERR#
PCI_PIRQC#
PCI_PIRQA#
PCI_PCIRST# PCI_RST#
PCI_PIRQB#
PCI_REQ1#
PCI_REQ4#
PCI_REQ2#
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#3
PCI_C/BE#2
CLK_PCI_ICH
PCI_DEVSEL#
PCI_FRAME#
PCI_TRDY#
PCI_PERR#
PCI_STOP#
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_PLOCK#
PCI_REQ0#
PCI_PIRQH#
PCI_PIRQG#
PCI_PIRQF#
PCI_PIRQE#
PCI_REQ0#
PCI_REQ1#
DVI_DETECT#
DVI_DETECT#
PCI_GNT0#
+3VS
+3VS
+3VS
+3VS
PCI_AD[0..31]<25,27>
MCH_ICH_SYNC# <9>
PCI_PME# <34>
CLK_PCI_ICH <5>
PCI_FRAME# <25,27>
PCI_TRDY# <25,27>
PCI_STOP# <25,27>
PCI_SERR# <25,27>
PCI_PERR# <25,27>
PCI_DEVSEL# <25,27>
PCI_PAR <25,27>
PCI_IRDY# <25,27>
PCI_C/BE#3 <25,27>
PCI_C/BE#2 <25,27>
PCI_C/BE#1 <25,27>
PCI_C/BE#0 <25,27>
PCI_REQ2# <25>
PCI_GNT2# <25>
PLT_RST# <9,18,22,24,28,32,33,35>
PCI_RST# <25,27>
PCI_PIRQA#<25>
PCI_REQ0# <27>
PCI_GNT0# <27>
PCI_PIRQE# <27>
PCI_PIRQF# <27>
PCI_PIRQG# <27>PCI_PIRQC#<25>
DVI_DETECT# <18>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
ICH7M1/4-PCI Interface
20 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Place closely pin A9
R651 8.2K_0402_5%
1 2
R664 8.2K_0402_5%
1 2
R669
10_0402_5%@
1 2
R644 8.2K_0402_5%
1 2
R654 8.2K_0402_5%
1 2
R645 8.2K_0402_5%
1 2
U11
TC7SH08FUF_SSOP5
@
B
1
A
2Y4
P5
G
3
R652 8.2K_0402_5%
1 2
R665 8.2K_0402_5%
1 2
R655
0_0402_5%
12
R646 8.2K_0402_5%
1 2
R653 8.2K_0402_5%
1 2
R666 8.2K_0402_5%
1 2
R647 8.2K_0402_5%
1 2
R667 8.2K_0402_5%
1 2
R659 8.2K_0402_5%
1 2
R648 8.2K_0402_5%
1 2
R662
0_0402_5%
12
R657 8.2K_0402_5%
1 2
R656 8.2K_0402_5%
1 2
R660 8.2K_0402_5%
1 2
R649 8.2K_0402_5%
1 2
C621
8.2P_0402_50V8D@
1
2
R658 8.2K_0402_5%
1 2
R650 8.2K_0402_5%
1 2
R663 8.2K_0402_5%
1 2
R661 8.2K_0402_5%
1 2
U10
TC7SH08FUF_SSOP5
@
B
1
A
2Y4
P5
G
3
Interrupt I/F
PCI
MISC
U9B
ICH7_BGA652~D
FRAME# F16
GPIO17 / GNT5# D8
TRDY# F14
STOP# F15
GPIO2 / PIRQE# G8
GPIO3 / PIRQF# F7
GPIO4 / PIRQG# F8
GPIO5 / PIRQH# G7
C/BE0# B15
C/BE1# C12
C/BE2# D12
C/BE3# C15
IRDY# A7
PAR E10
PCIRST# B18
DEVSEL# A12
PERR# C9
PLOCK# E11
SERR# B10
PIRQC#
C5
RSVD[4]
AH4
PIRQA#
A3
RSVD[5]
AD9
RSVD[2]
AD5
RSVD[3]
AG4
PIRQB#
B4
PIRQD#
B5
RSVD[1]
AE5
REQ0# D7
GNT0# E7
REQ1# C16
GNT1# D16
REQ2# C17
GNT2# D17
REQ3# E13
GNT3# F13
REQ4# / GPIO22 A13
GNT4# / GPIO48 A14
GPIO1 / REQ5# C8
AD0
E18
AD1
C18
AD2
A16
AD3
F18
AD4
E16
AD5
A18
AD6
E17
AD7
A17
AD8
A15
AD9
C14
AD10
E14
AD11
D14
AD12
B12
AD13
C13
AD14
G15
AD15
G13
AD16
E12
AD17
C11
AD18
D11
AD19
A11
AD20
A10
AD21
F11
AD22
F10
AD23
E9
AD24
D9
AD25
B9
AD26
A8
AD27
A6
AD28
C7
AD29
B6
AD30
E6
AD31
D6
RSVD[6] AE9
RSVD[7] AG8
RSVD[8] AH8
RSVD[9] F21
MCH_SYNC# AH20
PLTRST# C26
PCICLK A9
PME# B19
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_INTVRMEN
ICH_INTVRMEN
ACZ_BCLK
ICH_RTCX1
ICH_RTCRST#
PDD14
PDD11
PDD12
PDD10
PDD13
PDD15
PDD5
PDD4
PDD7
PDD8
PDD6
PDD9
PDDACK#
PDD3
PDIOW#
PDD1
PDD0
PDD2
ACZ_RST# H_SMI#
H_IGNNE#
H_NMI
LPC_AD1
LPC_AD2
LPC_AD3
H_PWRGOOD
THRMTRIP_ICH#
PDA0
SM_INTRUDER#
DPRSLP#
ICH_AZ_CODEC_SDIN0
H_CPUSLP_R#
ICH_RTCX2
KBRST#
GATEA20
H_FERR#
ACZ_SDOUT
BATT1.2
LPC_AD0
LPC_DRQ#0
LPC_FRAME#
PDD[0..15]
PDIORDY
IDEIRQ
PDIOR# PDDREQ
PDCS1#
PDCS3#
PDA1
PDA2
H_INIT#
H_INTR
H_DPSLP#
H_A20M#
ACZ_SYNC
H_STPCLK#
+VCCP
+3VS
+RTCVCC
+RTCVCC
+VCCP
+RTCVCC
+3VS
+3VS
CHGRTC
BATT1.1
+RTCVCC
LPC_AD0 <24,32,33,35>
LPC_AD1 <24,32,33,35>
LPC_AD2 <24,32,33,35>
LPC_AD3 <24,32,33,35>
LPC_DRQ#0 <35>
LPC_FRAME# <24,32,33,35>
PDIORDY<24> IDEIRQ<24> PDDACK#<24> PDIOW#<24> PDIOR#<24>
PDCS1# <24>
PDCS3# <24>
PDDREQ <24>
PDD[0..15] <24>
PDA1 <24>
PDA2 <24>
PDA0 <24>
H_NMI <6>
H_SMI# <6>
H_INIT# <6>
H_INTR <6>
KBRST# <33>
H_IGNNE# <6>
H_PWRGOOD <6>
H_DPRSTP# <6,46>
H_DPSLP# <6>
H_A20M# <6>
GATEA20 <33>
H_STPCLK# <6>
H_THERMTRIP# <6,9>
H_FERR# <6>
ICH_AZ_CODEC_RST#<30>
ICH_AZ_CODEC_SDIN0<30>
ICH_AZ_CODEC_SDOUT<30>
ICH_AZ_CODEC_BITCLK<30>
ICH_AZ_CODEC_SYNC<30>
H_CPUSLP# <6,9>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
ICH7M2/4-RTC/LPC/IDE/Azalia
21 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R683 must be placed close to U9.AF26
within 2" and R681 must be placed close
to R683 within 2".
W=20mils
+-
Pull high to enable the
internal Vccsus1_5
suspend regulator. pull
low to disable it--ICH_INTVRMEN
R681
56_0402_5%
12
R687
0_0402_5%@
12
R674 0_0402_5%
12
Y2
32.768KHZ_12.5PF_1TJS125BJ4A421P
OUT 4
IN 1
NC
3
NC
2
R68033_0402_5%
1 2
R675 56_0402_5%
12
R689
4.7K_0402_5%
12
R670
10M_0402_5%
12
R672
1M_0402_5%
1 2
D8
BAS40-04_SOT23
1
2
3
R686
332K_0402_1%
12
R671
20K_0402_5%
1 2
R683
24.9_0402_1%
1 2
C623 18P_0402_50V8J
12
R68433_0402_5%
1 2
R688
8.2K_0402_5%
12
RTC LAN SATA
AC-97/AZALIA
LPCCPU
IDE
U9A
ICH7_BGA652~D
RTXC1
AB1
RTCX2
AB2
RTCRST#
AA3
INTVRMEN
W4
INTRUDER#
Y5
EE_CS
W1
EE_SHCLK
Y1
EE_DOUT
Y2
EE_DIN
W3
LAN_CLK
V3
LAN_RSTSYNC
U3
LAN_RXD0
U5
LAN_RXD1
V4
LAN_RXD2
T5
LAN_TXD0
U7
LAN_TXD1
V6
LAN_TXD2
V7
ACZ_BCLK
U1
ACZ_SYNC
R6
ACZ_RST#
R5
ACZ_SDIN0
T2
ACZ_SDIN1
T3
ACZ_SDIN2
T1
ACZ_SDOUT
T4
SATALED#
AF18
SATA0RXN
AF3
SATA0RXP
AE3
SATA0TXN
AG2
SATA0TXP
AH2
SATA2RXN
AF7
SATA2RXP
AE7
SATA2TXN
AG6
SATA2TXP
AH6
SATA_CLKN
AF1
SATA_CLKP
AE1
SATARBIASN
AH10
SATARBIASP
AG10
IORDY
AG16
IDEIRQ
AH16
DDACK#
AF16
DIOW#
AH15
DIOR#
AF15
LAD0 AA6
LAD1 AB5
LAD2 AC4
LAD3 Y6
LDRQ0# AC3
LDRQ1# / GPIO23 AA5
LFRAME# AB3
A20GATE AE22
A20M# AH28
CPUSLP# AG27
TP1 / DPRSTP# AF24
TP2 / DPSLP# AH25
FERR# AG26
GPIO49 / CPUPWRGD AG24
IGNNE# AG22
INIT3_3V# AG21
INIT# AF22
INTR AF25
RCIN# AG23
SMI# AF23
NMI AH24
STPCLK# AH22
THERMTRIP# AF26
DA0 AH17
DA1 AE17
DA2 AF17
DCS1# AE16
DCS3# AD16
DD0 AB15
DD1 AE14
DD2 AG13
DD3 AF13
DD4 AD14
DD5 AC13
DD6 AD12
DD7 AC12
DD8 AE12
DD9 AF12
DD10 AB13
DD11 AC14
DD12 AF14
DD13 AH13
DD14 AH14
DD15 AC15
DDREQ AE15
R690
511_0603_1%
1 2
C622 18P_0402_50V8J
12
R682 0_0402_5%
12
R67733_0402_5%
1 2
C626
0.1U_0402_16V4Z
1
2
R67933_0402_5%
1 2
R676 0_0402_5%
@
12
CMOS_CLR1
NO SHORT PADS
1 2
R678 10K_0402_5%
12
R691
100_0603_1%
1 2
BATT1
RTCBATT
1 2
R673 10K_0402_5%
12
C624
1U_0603_10V4Z
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_SPKR
LINKALERT#
USB_OC#3
SUS_STAT#
USB_OC#6
USB_OC#7
PCIE_C_TXP2
PCIE_C_TXN2
USB_OC#4
USB_OC#7
EC_SCI#
USBP7-
USBP7+
USBP6-
USBP6+
USBP0-
USBP0+
USBP1+
USBP2-
USBP2+
USBP3-
USBP3+
USBP5-
USBP5+
USB_OC#5
USB_OC#5
EC_RSMRST#
USB_OC#6
ICH_SMLINK1
ICH_SMLINK0
LINKALERT#
XDP_DBRESET#
PM_CLKRUN#
USBRBIAS
DMI_IRCOMP
ICH_RI#
H_STP_PCI#
PM_CLKRUN#
DMI_TXN2
DMI_TXN3
DMI_TXP2
DMI_RXN2
USB_OC#4
USB_OC#0
USB_OC#1
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_RXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_RXP0
DMI_TXP3
DMI_RXN3
DMI_RXP3
DMI_RXP2
PLT_RST#
SB_THERM#
SIRQ
CLK_PCIE_ICH
CLK_PCIE_ICH#
USB_OC#2
CLK_48M_ICH
CLK_14M_ICH
EC_PBTNOUT#
USB_OC#3
ICH_SUSCLK
XDP_DBRESET#
USB_OC#1
USB_OC#2
USBP1-
USB_OC#0
PM_BMBUSY#
H_STP_CPU#
PCIE_RXP2
PCIE_RXN2
CLK_48M_ICH CLK_14M_ICH
SLP_S3#
SLP_S4#
SLP_S5#
H_DPRSLPVR
EC_FLASH#
IDERST_HD#
SIRQ
EC_SCI#
VGATE_INTEL
PM_BATLOW#
PWROK
PCIE_C_TXP1
PCIE_C_TXN1
PCIE_RXP1
PCIE_RXN1
ICH_PCIE_WAKE#
EC_SMI#
EC_SWI#
M_SEN#
SB_THERM#
ICH_SMB_CLK
ICH_SMB_DATA
ICH_SMB_DATA
ICH_SMB_CLKICH_SMBCLK
ICH_SMBDATA
PCIE_C_TXP3
PCIE_C_TXN3
PCIE_RXP3
PCIE_RXN3
USBP4-
USBP4+
USB_SMI#
ID0
PID0
ID1
PID1
+3VALW
+3VALW
+3VS
+1.5VS
+3VALW
+3VALW +3VALW
+3VALW
+3VS
+3VALW
+3V_LAN
+3VS
+3VS
USB_OC#0<32> USB_OC#1<32>
SUS_STAT#<32,35> XDP_DBRESET#<6>
PM_BMBUSY#<9>
H_STP_PCI#<5> H_STP_CPU#<5>
PM_CLKRUN#<25,27,32,33,35>
PCIE_RXN2<24> PCIE_RXP2<24> PCIE_TXN2<24> PCIE_TXP2<24>
CLK_14M_ICH <5>
CLK_48M_ICH <5>
SLP_S3# <33>
SLP_S4# <33>
H_DPRSLPVR <9,46>
EC_PBTNOUT# <33>
EC_RSMRST# <27,33>
PM_BATLOW# <33>
DMI_RXN0 <9>
DMI_RXP0 <9>
DMI_TXN0 <9>
DMI_TXP0 <9>
DMI_RXN1 <9>
DMI_RXP1 <9>
DMI_TXN1 <9>
DMI_TXP1 <9>
DMI_RXN2 <9>
DMI_RXP2 <9>
DMI_TXN2 <9>
DMI_TXP2 <9>
DMI_RXN3 <9>
DMI_RXP3 <9>
DMI_TXN3 <9>
DMI_TXP3 <9>
CLK_PCIE_ICH# <5>
CLK_PCIE_ICH <5>
USBP0+ <32>
USBP1- <32>
USBP1+ <32>
USBP2- <24>
USBP2+ <24>
USBP3+ <36>
USBP5- <36>
USBP5+ <36>
USBP6- <36>
USBP6+ <36>
USBP7- <36>
USBP7+ <36>
PLT_RST# <9,18,20,24,28,32,33,35>
EC_SCI#<33>
EC_FLASH#<34>
IDERST_HD#<24>
EC_THRM#<33> SIRQ<25,32,33,35>
VGATE_INTEL<33,46>
ICH_SPKR<30>
SLP_S5# <33>
PWROK <9,33,34>
PCIE_RXN1<28> PCIE_RXP1<28> PCIE_TXN1<28> PCIE_TXP1<28>
LAN_WAKE#<28>
PCIE_WAKE#<24>
EC_SMI# <33>
EC_SWI# <33>
M_SEN#<19,36>
ICH_SMBCLK<5,6,15,16,24>
ICH_SMBDATA<5,6,15,16,24>
PCIE_RXN3<24> PCIE_RXP3<24> PCIE_TXN3<24> PCIE_TXP3<24>
USBP4+ <36>
USB_OC#6<34> USB_OC#7<34>
USB_OC#4<34>
USBP0- <32>
USBP3- <36>
USBP4- <36>
USB_SMI#<27>
ID0<17>
PID0 <17>
ID1<17>
PID1 <17>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
ICH7M3/4-USB/DMI/PCIE/PM/GP
22 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Need update symbol
Within 500 mils
Within 500 mils
if the susclk duty cycle is
beyond the 30-70% range, it
indicate a poor oscillation signal
This is only supported USBRBIAS value for the Intel
82801GM and is required to properly configure the
USB interface drive strength.
R692
10_0402_5%
@
12
G
D
S
Q9
2N7002_SOT23
2
13
R709 10K_0402_5%
1 2
R715 24.9_0402_1%
1 2
R711 10K_0402_5%
1 2
R697
10K_0402_5%
1 2
C630
0.1U_0402_16V4Z 12
R743 8.2K_0402_5%
1 2
SATA
POWER MGT
SYS
SMB
GPIO
Clocks
GPIO
GPIO
U9C
ICH7_BGA652~D
RI#
A28
SPKR
A19
SYS_RST#
A22 SUS_STAT#
A27
GPIO0 / BM_BUSY#
AB18
GPIO26
A21
GPIO27
B21
GPIO28
E23
GPIO32 / CLKRUN#
AG18
GPIO33 / AZ_DOCK_EN#
AC19
GPIO34 / AZ_DOCK_RST#
U2
VRMPWRGD
AD22
GPIO11 / SMBALERT#
B23
SUSCLK C20
SLP_S3# B24
SLP_S4# D23
SLP_S5# F22
PWROK AA4
GPIO16 / DPRSLPVR AC22
TP0 / BATLOW# C21
PWRBTN# C23
LAN_RST# C19
RSMRST# Y4
GPIO21 / SATA0GP AF19
GPIO19 / SATA1GP AH18
GPIO36 / SATA2GP AH19
GPIO37 / SATA3GP AE19
CLK14 AC1
CLK48 B2
GPIO9 E20
GPIO10 A20
GPIO12 F19
GPIO13 E19
GPIO14 R4
GPIO15 E22
GPIO24 R3
GPIO25 D20
GPIO35 / SATAREQ# AD21
GPIO38 AD20
GPIO39 AE20
SMBCLK
C22
SMBDATA
B22
LINKALERT#
A26
SMLINK0
B25
SMLINK1
A25
GPIO18 / STPPCI#
AC20
GPIO20 / STPCPU#
AF21
WAKE#
F20
SERIRQ
AH21
THRM#
AF20
GPIO6
AC21
GPIO7
AC18
GPIO8
E21
R719 22.6_0402_1%
1 2
R701
8.2K_0402_5%
1 2
C670
0.1U_0402_16V4Z 12
R708 10K_0402_5%
1 2
R710 8.2K_0402_5%
1 2
RP27
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R733 8.2K_0402_5%
1 2
R706 8.2K_0402_5%
1 2
R1345
0_0402_5%
1 2
R71310K_0402_5%
1 2
PCI-EXPRESS
DIRECT MEDIA INTERFACE
USB
SPI
U9D
ICH7_BGA652~D
SPI_CLK
R2
SPI_CS#
P6
SPI_ARB
P1
SPI_MOSI
P5
SPI_MISO
P2
DMI0RXN V26
DMI0RXP V25
DMI0TXN U28
DMI0TXP U27
DMI1RXN Y26
DMI1RXP Y25
DMI1TXN W28
DMI1TXP W27
DMI2RXN AB26
DMI2RXP AB25
DMI2TXN AA28
DMI2TXP AA27
DMI3RXN AD25
DMI3RXP AD24
DMI3TXN AC28
DMI3TXP AC27
DMI_CLKN AE28
DMI_CLKP AE27
DMI_ZCOMP C25
DMI_IRCOMP D25
PERn1
F26
PERp1
F25
PETn1
E28
PETp1
E27
PERn2
H26
PERp2
H25
PETn2
G28
PETp2
G27
PERn3
K26
PERp3
K25
PETn3
J28
PETp3
J27
PERn4
M26
PERp4
M25
PETn4
L28
PETp4
L27
PERn5
P26
PERp5
P25
PETn5
N28
PETp5
N27
PERn6
T25
PERp6
T24
PETn6
R28
PETp6
R27
OC0#
D3
OC1#
C4
OC2#
D5
OC3#
D4
OC4#
E5
OC5# / GPIO29
C3
OC6# / GPIO30
A2
OC7# / GPIO31
B3
USBP0N F1
USBP0P F2
USBP1N G4
USBP1P G3
USBP2N H1
USBP2P H2
USBP3N J4
USBP3P J3
USBP4N K1
USBP4P K2
USBP5N L4
USBP5P L5
USBP6N M1
USBP6P M2
USBP7N N4
USBP7P N3
USBRBIAS# D2
USBRBIAS D1
RP29
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R704 10K_0402_5%
1 2
C629
0.1U_0402_16V4Z 12
T15 PAD
C628
4.7P_0402_50V8C
@
1
2
R714 10K_0402_5%
1 2
R694
2.2K_0402_5%
12
D10 RB751V_SOD323
21
R702
2.2K_0402_5%
12
C627
4.7P_0402_50V8C
@
1
2
R695
2.2K_0402_5%
12
R576
1K_0402_5%
12
C631
0.1U_0402_16V4Z 12
G
D
S
Q71
BSS138_NL_SOT23-3
2
13
R693
10_0402_5%
@
12
R705
8.2K_0402_5%
12
R745 8.2K_0402_5%
1 2
C632
0.1U_0402_16V4Z 12
R703
2.2K_0402_5%
12
R742 8.2K_0402_5%
1 2
G
D
S
Q10
2N7002_SOT23
2
13
R696
10K_0402_5%
1 2
C661
0.1U_0402_16V4Z 12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_V5REF_RUN
ICH_V5REF_SUS
ICH_K7
ICH_C28
ICH_G20
+1.5VS_DMIPLL
ICH_V5REF_RUN
ICH_V5REF_SUS
ICH_AA2
ICH_Y7
+3VALW
+VCCP
+3VS
+1.5VS
+RTCVCC
+3VALW
+1.5VS
+1.5VS
+3VS+5VS
+3VALW+5VALW
+3VS
+1.5VS
+1.5VS
+3VS
+3VS
+3VALW
+3VALW
+1.5VS
+VCCP
+1.5VS_DMIPLL+1.5VS_DMIPLLR
+3VS
+1.5VS
+1.5VS
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.3
ICH7M4/4-PWR/GND
23 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Place closely pin AG28 within 100mlis.
Place closely pin
D28,T28,AD28.
Place closely pin AG5.
Place closely pin AG9.
CRB use 270uF
R723
0.5_0805_1%
1 2
C660
0.1U_0402_16V4Z
1
2
C657
0.1U_0402_16V4Z
1
2
C656
0.1U_0402_16V4Z
1
2
C663
0.1U_0402_16V4Z
1 2
C668
0.1U_0402_16V4Z
1
2
C644
0.1U_0402_16V4Z
1 2
R722
10_0402_5%
12
C655
0.1U_0402_16V4Z
1
2
L18
BLM18AG601SN1D_0603
1 2
C638
0.1U_0402_16V4Z
1
2
D11
CH751H-40PT_SOD323
21
L17
BLM21PG600SN1D_0805
1 2
C641
0.1U_0402_16V4Z
1
2
R721
100_0402_5%
12
C658
10U_0805_10V4Z
1
2
C653
0.1U_0402_16V4Z
1
2
C652
0.1U_0402_16V4Z
1
2
C649
0.1U_0402_16V4Z
1
2
C648
0.1U_0402_16V4Z
1
2
C642
0.1U_0402_16V4Z
1
2
C659
0.01U_0402_16V7K
1
2
C662
0.1U_0402_16V4Z
1
2
C665
0.1U_0402_16V4Z
1
2
T17PAD
C635
1U_0603_10V4Z
1
2
C645
0.1U_0402_16V4Z
1
2
C650
0.1U_0402_16V4Z
1
2
U9E
ICH7_BGA652~D
VSS[0]
A4
VSS[1]
A23
VSS[2]
B1
VSS[3]
B8
VSS[4]
B11
VSS[5]
B14
VSS[6]
B17
VSS[7]
B20
VSS[8]
B26
VSS[9]
B28
VSS[10]
C2
VSS[11]
C6
VSS[12]
C27
VSS[13]
D10
VSS[14]
D13
VSS[15]
D18
VSS[16]
D21
VSS[17]
D24
VSS[18]
E1
VSS[19]
E2
VSS[21]
E4
VSS[22]
E8
VSS[23]
E15
VSS[24]
F3
VSS[25]
F4
VSS[26]
F5
VSS[27]
F12
VSS[28]
F27
VSS[29]
F28
VSS[30]
G1
VSS[31]
G2
VSS[32]
G5
VSS[33]
G6
VSS[34]
G9
VSS[35]
G14
VSS[36]
G18
VSS[37]
G21
VSS[38]
G24
VSS[39]
G25
VSS[40]
G26
VSS[41]
H3
VSS[42]
H4
VSS[43]
H5
VSS[44]
H24
VSS[45]
H27
VSS[46]
H28
VSS[47]
J1
VSS[48]
J2
VSS[49]
J5
VSS[50]
J24
VSS[51]
J25
VSS[52]
J26
VSS[53]
K24
VSS[54]
K27
VSS[55]
K28
VSS[56]
L13
VSS[57]
L15
VSS[58]
L24
VSS[59]
L25
VSS[60]
L26
VSS[61]
M3
VSS[62]
M4
VSS[63]
M5
VSS[64]
M12
VSS[65]
M13
VSS[66]
M14
VSS[67]
M15
VSS[68]
M16
VSS[69]
M17
VSS[70]
M24
VSS[71]
M27
VSS[72]
M28
VSS[73]
N1
VSS[74]
N2
VSS[75]
N5
VSS[76]
N6
VSS[77]
N11
VSS[78]
N12
VSS[79]
N13
VSS[80]
N14
VSS[81]
N15
VSS[82]
N16
VSS[83]
N17
VSS[84]
N18
VSS[85]
N24
VSS[86]
N25
VSS[87]
N26
VSS[88]
P3
VSS[89]
P4
VSS[90]
P12
VSS[91]
P13
VSS[92]
P14
VSS[93]
P15
VSS[94]
P16
VSS[95]
P17
VSS[96]
P24
VSS[97]
P27
VSS[98] P28
VSS[99] R1
VSS[100] R11
VSS[101] R12
VSS[102] R13
VSS[103] R14
VSS[104] R15
VSS[105] R16
VSS[106] R17
VSS[107] R18
VSS[108] T6
VSS[109] T12
VSS[110] T13
VSS[111] T14
VSS[112] T15
VSS[113] T16
VSS[114] T17
VSS[115] U4
VSS[116] U12
VSS[117] U13
VSS[118] U14
VSS[119] U15
VSS[120] U16
VSS[121] U17
VSS[122] U24
VSS[123] U25
VSS[124] U26
VSS[125] V2
VSS[126] V13
VSS[127] V15
VSS[128] V24
VSS[129] V27
VSS[130] V28
VSS[131] W6
VSS[132] W24
VSS[133] W25
VSS[134] W26
VSS[135] Y3
VSS[136] Y24
VSS[137] Y27
VSS[138] Y28
VSS[139] AA1
VSS[140] AA24
VSS[141] AA25
VSS[142] AA26
VSS[143] AB4
VSS[144] AB6
VSS[145] AB11
VSS[146] AB14
VSS[147] AB16
VSS[148] AB19
VSS[149] AB21
VSS[150] AB24
VSS[151] AB27
VSS[152] AB28
VSS[153] AC2
VSS[154] AC5
VSS[155] AC9
VSS[156] AC11
VSS[157] AD1
VSS[158] AD3
VSS[159] AD4
VSS[160] AD7
VSS[161] AD8
VSS[162] AD11
VSS[163] AD15
VSS[164] AD19
VSS[165] AD23
VSS[166] AE2
VSS[167] AE4
VSS[168] AE8
VSS[169] AE11
VSS[170] AE13
VSS[171] AE18
VSS[172] AE21
VSS[173] AE24
VSS[174] AE25
VSS[175] AF2
VSS[176] AF4
VSS[177] AF8
VSS[178] AF11
VSS[179] AF27
VSS[180] AF28
VSS[181] AG1
VSS[182] AG3
VSS[183] AG7
VSS[184] AG11
VSS[185] AG14
VSS[186] AG17
VSS[187] AG20
VSS[188] AG25
VSS[189] AH1
VSS[190] AH3
VSS[191] AH7
VSS[192] AH12
VSS[193] AH23
VSS[194] AH27
C636
0.1U_0402_16V4Z
1
2
D12
CH751H-40PT_SOD323
21
T16PAD
C667
0.1U_0402_16V4Z
1
2
U9F
ICH7_BGA652~D
V5REF[1]
G10
V5REF[2]
AD17
V5REF_Sus
F6
Vcc1_5_B[1]
AA22
Vcc1_5_B[2]
AA23
Vcc1_5_B[3]
AB22
Vcc1_5_B[4]
AB23
Vcc1_5_B[5]
AC23
Vcc1_5_B[6]
AC24
Vcc1_5_B[7]
AC25
Vcc1_5_B[8]
AC26
Vcc1_5_B[9]
AD26
Vcc1_5_B[10]
AD27
Vcc1_5_B[11]
AD28
Vcc1_5_B[12]
D26
Vcc1_5_B[13]
D27
Vcc1_5_B[14]
D28
Vcc1_5_B[15]
E24
Vcc1_5_B[16]
E25
Vcc1_5_B[17]
E26
Vcc1_5_B[18]
F23
Vcc1_5_B[19]
F24
Vcc1_5_B[20]
G22
Vcc1_5_B[21]
G23
Vcc1_5_B[22]
H22
Vcc1_5_B[23]
H23
Vcc1_5_B[24]
J22
Vcc1_5_B[25]
J23
Vcc1_5_B[26]
K22
Vcc1_5_B[27]
K23
Vcc1_5_B[28]
L22
Vcc1_5_B[29]
L23
Vcc1_5_B[30]
M22
Vcc1_5_B[31]
M23
Vcc1_5_B[32]
N22
Vcc1_5_B[33]
N23
Vcc1_5_B[34]
P22
Vcc1_5_B[35]
P23
Vcc1_5_B[36]
R22
Vcc1_5_B[37]
R23
Vcc1_5_B[38]
R24
Vcc1_5_B[39]
R25
Vcc1_5_B[41]
T22
Vcc1_5_B[42]
T23
Vcc1_5_B[43]
T26
Vcc1_5_B[44]
T27
Vcc1_5_B[45]
T28
Vcc1_5_B[46]
U22
Vcc1_5_B[47]
U23
Vcc1_5_B[48]
V22
Vcc1_5_B[49]
V23
Vcc1_5_B[50]
W22
Vcc1_5_B[52]
Y22
Vcc1_5_B[53]
Y23
Vcc1_5_B[51]
W23
Vcc1_5_B[40]
R26
Vcc3_3[1]
B27
VccDMIPLL
AG28
VccSATAPLL
AD2
Vcc3_3[2]
AH11
Vcc1_05[1] L11
Vcc1_05[2] L12
Vcc1_05[3] L14
Vcc1_05[4] L16
Vcc1_05[6] L18
Vcc1_05[5] L17
Vcc1_05[7] M11
Vcc1_05[8] M18
Vcc1_05[9] P11
Vcc1_05[10] P18
Vcc1_05[11] T11
Vcc1_05[12] T18
Vcc1_05[13] U11
Vcc1_05[14] U18
Vcc1_05[15] V11
Vcc1_05[16] V12
Vcc1_05[17] V14
Vcc1_05[18] V16
Vcc1_05[19] V17
Vcc1_05[20] V18
Vcc3_3 / VccHDA U6
VccSus3_3/VccSusHDA R7
V_CPU_IO[1] AE23
V_CPU_IO[2] AE26
V_CPU_IO[3] AH26
Vcc3_3[3] AA7
Vcc3_3[4] AB12
Vcc3_3[5] AB20
Vcc3_3[6] AC16
Vcc3_3[7] AD13
Vcc3_3[8] AD18
Vcc3_3[9] AG12
Vcc3_3[10] AG15
Vcc3_3[11] AG19
Vcc3_3[12] A5
Vcc3_3[14] B16
Vcc3_3[15] B7
Vcc3_3[16] C10
Vcc3_3[13] B13
Vcc3_3[17] D15
Vcc3_3[18] F9
Vcc3_3[19] G11
Vcc3_3[20] G12
VccRTC W5
VccSus3_3[1] P7
VccSus3_3[2] A24
VccSus3_3[4] D19
VccSus3_3[5] D22
VccSus3_3[6] G19
VccSus3_3[3] C24
VccSus3_3[7] K3
VccSus3_3[8] K4
VccSus3_3[9] K5
VccSus3_3[10] K6
VccSus3_3[11] L1
Vcc1_5_A[19] AB17
Vcc1_5_A[20] AC17
Vcc1_5_A[21] T7
Vcc1_5_A[22] F17
Vcc1_5_A[23] G17
Vcc1_5_A[24] AB8
Vcc1_5_A[25] AC8
VccSus1_05[1] K7
Vcc1_5_A[1]
AB7
Vcc1_5_A[2]
AC6
Vcc1_5_A[3]
AC7
Vcc1_5_A[4]
AD6
Vcc1_5_A[5]
AE6
Vcc1_5_A[6]
AF5
Vcc1_5_A[7]
AF6
Vcc1_5_A[8]
AG5
Vcc1_5_A[9]
AH5
Vcc1_5_A[10]
AB10
Vcc1_5_A[11]
AB9
Vcc1_5_A[12]
AC10
Vcc1_5_A[13]
AD10
Vcc1_5_A[14]
AE10
Vcc1_5_A[15]
AF10
Vcc1_5_A[16]
AF9
Vcc1_5_A[17]
AG9
Vcc1_5_A[18]
AH9
VccSus3_3[19]
E3
VccUSBPLL
C1
VccSus1_05/VccLAN1_05[1]
AA2
VccSus1_05/VccLAN1_05[2]
Y7
VccSus3_3/VccLAN3_3[1]
V5
VccSus3_3/VccLAN3_3[2]
V1
VccSus3_3/VccLAN3_3[3]
W2
VccSus3_3/VccLAN3_3[4]
W7
Vcc3_3[21] G16
VccSus3_3[12] L2
VccSus3_3[13] L3
VccSus3_3[14] L6
VccSus3_3[15] L7
VccSus3_3[16] M6
VccSus3_3[17] M7
VccSus3_3[18] N7
VccSus1_05[2] C28
VccSus1_05[3] G20
Vcc1_5_A[26] A1
Vcc1_5_A[27] H6
Vcc1_5_A[28] H7
Vcc1_5_A[29] J6
Vcc1_5_A[30] J7
T19 PAD
C664
1U_0603_10V4Z
1
2
C651
0.1U_0402_16V4Z
1
2
T18PAD
C654
0.1U_0402_16V4Z
1
2
C666
0.1U_0402_16V4Z
1
2
C647
0.1U_0402_16V4Z
1
2
C643
0.1U_0402_16V4Z
1 2
T20 PAD
C639
0.1U_0402_16V4Z
1
2
+
C637
220U_D2_4VM
1
2
+
C634
330U_D2E_2.5VM_R9
1
2
C646
4.7U_0805_10V4Z
1 2
C640
0.1U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PIDERST#
PDDREQ
PDD6
PDD14
PDD15
PIDERST# PDD7
PDD1
PDD0
PDD8
PDD5
PDD4
PDD3
PDD2
PDD12
PDD13
PDD11
PDD10
PDD9
PDDREQ
PDIOR# IDEIRQ
PDDACK#
PDIOW#
PDCS1#
PDA1
PDA0 PDA2PDCS3#
PCSEL
PDD[0..15]
PDIORDY
EC_CK1
EC_DA1
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_DA1
SCLKSMB_EC_CK1
SMB_EC_CK2
SMB_EC_DA2
EC_CK2
EC_DA2
UIM_DATA
UIM_VPP
UIM_CLK
UIM_PWR
WWANOFF#
USBP2+
PCIE_C_RXP3
CLK_PCIE_WAN
CLK_PCIE_WAN#
USBP2-
PCIE_C_RXN3
PCIE_RXP3
PCIE_RXN3
CLKREQA#
PCIE_TXN3
PCIE_TXP3
PCIE_WAKE#
UIM_RST
UIM_DATA UIM_CLK
UIM_RST
BT_ACTIVE
NEC_USBP1-
CLK_PCIE_MINI#
CLK_PCIE_MINI
PCIE_C_RXP2
PCIE_C_RXN2PCIE_RXN2
PCIE_RXP2
CLKREQB#
PCIE_TXN2
PCIE_TXP2
PCIE_WAKE#
WL_SW#
NEC_USBP1+
UIM_RST
UIM_VPP
UIM_CLK
UIM_DATA
UIM_PWR
WLAN_ACTIVE
UIM_VPP
UIM_VCC
DB_LPC_AD3
DB_LPC_AD0
DB_LPC_AD2
DB_LPC_FRAME#
DB_LPC_RST#
DB_LPC_AD1
DB_LPC_AD3
DB_LPC_AD0
DB_LPC_FRAME#
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_RST#
CLK_DEBUG_PORT
WL_SW#
SDA
SMB_EC_DA1
SMB_EC_CK1
F_FALL G_DA2 SMB_EC_DA2
SMB_EC_CK2
MOTION G_CK2
WLANOFF#
CLK_DEBUG_PORT
+3VS
+3VS
+3VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+5VS
+3VS
+1.5VS +3VS
+3VS
+3VS+1.5VS
+3VS
+3VS
+3V_LAN
+3V_LAN
+5VALW
+3VS
+3VS
+3VS
+3VS
+3VS
PLT_RST#<9,18,20,22,28,32,33,35>
PDIOR#<21> PDA0<21> PDCS3#<21> PDA1<21>
PDIOW# <21>
PDDREQ <21>
PDDACK# <21>
PDCS1# <21>
PDA2 <21>
PDIORDY <21>
IDEIRQ <21>
PDD[0..15]<21>
SMB_EC_CK1<33,34,39>
SMB_EC_DA1<33,34,39>
SMB_EC_CK2<6,33,36,39>
SMB_EC_DA2<6,33,36,39>
WWANOFF# <33>
CLKREQA#<5>
PCIE_RXN3<22>
CLK_PCIE_WAN#<5> CLK_PCIE_WAN<5>
ICH_SMBCLK <5,6,15,16,22>
PCIE_RXP3<22>
PCIE_TXN3<22> PCIE_TXP3<22>
PLT_RST# <9,18,20,22,28,32,33,35>
ICH_SMBDATA <5,6,15,16,22>
PCIE_WAKE#<22>
CLKREQB#<5>
CLK_PCIE_MINI<5> CLK_PCIE_MINI#<5>
PCIE_RXN2<22> PCIE_RXP2<22>
ICH_SMBCLK <5,6,15,16,22>
PCIE_TXP2<22> PCIE_TXN2<22>
PLT_RST# <9,18,20,22,28,32,33,35>
ICH_SMBDATA <5,6,15,16,22>
PCIE_WAKE#<22>
WL_SW#<33>
BT_ACTIVE<27> WLAN_ACTIVE<27>
LPC_FRAME#<21,32,33,35> LPC_AD0<21,32,33,35> LPC_AD1<21,32,33,35> LPC_AD2<21,32,33,35> LPC_AD3<21,32,33,35>
PLT_RST#<9,18,20,22,28,32,33,35>
CLK_DEBUG_PORT<5>
NEC_USBP1- <27>
NEC_USBP1+ <27>
USBP2- <22>
USBP2+ <22>
IDERST_HD#<22>
WLANOFF# <33>
MOTION<33> F_FALL<33>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
MINI Card Slot/PIDE&Thermal sensor
24 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
500mA
Place caps. near HDD
CONN.
Layout Note: +VPHDD trace
width 60 mil
SM BUS Addr. 1001 001
Thermal Sensor for inverter
Thermal Sensor for CPU, Place near the CPU
SM BUS Addr. 1001 110
SM BUS Addr. 1001 001
SM BUS Addr. 1001 010
Thermal Sensor for SO-DIMM
Mini-Express Card---WWAN
Mini-Express Card ---WLAN
Wireless SW
Symbol update
Place C37 close to JP28
add these for Port 80H debug card
Thermal Sensor for charger
SM BUS Addr. 1001 010
SM BUS Addr. 0011 000
G
D
S
Q61
2N7002_SOT23
2
13
JP10
SUYIN_127212FA040G200ZX
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
G
D
S
Q22
2N7002_SOT23
2
1 3
R785 0_0402_5%
1 2
C877
0.1U_0402_16V4Z
1 2
D5
DAN217_SC59
2
31
R913
10K_0402_5%
1 2
G
D
S
Q57
2N7002_SOT23
2
1 3
C673 33P_0402_50V8J
12
R959
10K_0402_5%
1 2
R966
33_0402_5%
@
12
R728 0_0402_5%
1 2
C749 0.1U_0402_16V4Z
@12
R957 10K_0402_5%
12
R752 10K_0402_5%
@
1 2
D2
NUP4301MR6T1G_TSOP6
CH1
1
Vn
2
CH2
3CH3 4
Vp 5
CH4 6
C669
0.1U_0402_16V4Z
12
G
D
S
Q56
2N7002_SOT23
2
1 3
G
D
S
Q20
2N7002_SOT23
2
1 3
G
D
S
Q69
2N7002_SOT23
2
13
R727 470_0402_5%
1 2
R777 0_0402_5%DB@
1 2
R783 0_0402_5%
DB@
1 2
C878
0.1U_0402_16V4Z
1 2
R955
10K_0402_5%
1 2
U35
TC74A1-5.0VCT_SOT23-5
VDD 3
GND 2
SCLK
4
SDA
5
NC 1
R902
10K_0402_5%
1 2
YAMAI_FMS006Z-2101-0
JP9
VCC(C1)
1
GND(C5)
2
RST(C2)
3
VPP(C6)
4
CLK(C3)
5
I/O(C7)
6
SW1
7
SW2
8
GND1
9
GND2
10
R729
5.6K_0402_5%@
12
U14
MCP9803T-M/MSG_MSOP8
VDD 8
A0 7
A1 6
A2 5
SDA
1
SCLK
2
ALERT
3
GND
4
JP28
FOX_AS0B226-S52N-7F~N
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
GND1
53
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
GND2 54
R781 0_0402_5%DB@
1 2
U56
KXP84-2050_DFN14
Output X
5
Output Z
6
Output Y
7RESET 8
CS# 9
MOTION
3IO VDD 13
SCL/SCLK 12
SDA/SDO 11
ADDR0/SDI 10
FF
4
GND
1NC 14
VDD
2
Thermal_Pad 15
C683
0.1U_0402_16V4Z
1
2
R726
0_0402_5%@
1 2
R774 0_0402_5%
1 2
R786 0_0402_5%
1 2
G
D
S
Q54
2N7002_SOT23
2
1 3
C674
1000P_0402_50V7K
1
2
C682 4.7U_0805_10V4Z
12
U36
TC74A2-5.0VCT_SOT23-5
VDD 3
GND 2
SCLK
4
SDA
5
NC 1
R725
4.7K_0402_5%
12
R778 0_0402_5%
DB@
1 2
C675
10U_0805_10V4Z
1
2
C676
0.1U_0402_16V4Z
1
2
C687 10U_0805_10V4Z
1 2
C684
0.1U_0402_16V4Z
1
2
R956 10K_0402_5%
12
R720
8.2K_0402_5%
1 2
U55
TC74A2-5.0VCT_SOT23-5
VDD 3
GND 2
SCLK
4
SDA
5
NC 1
G
D
S
Q55
2N7002_SOT23
2
1 3
D38
PSOT24C-LF_T7_SOT23-3
2
3
1
R779 0_0402_5%
DB@
1 2
R730
4.7K_0402_5%
12
C927
0.1U_0402_16V4Z
1 2
R968 10K_0402_5%
12
JP14
MOLEX_53780-0290
1
1
2
2
R903
10K_0402_5%
1 2
C685
0.1U_0402_16V4Z
1
2
R773 0_0402_5%
1 2
R782 0_0402_5%
DB@
1 2
C924
0.1U_0402_16V4Z
1 2
U54
TC74A1-5.0VCT_SOT23-5
VDD 3
GND 2
SCLK
4
SDA
5
NC 1
R958
10K_0402_5%
1 2
U12
TC7SH08FUF_SSOP5
B
1
A
2Y4
P5
G
3
C933
22P_0402_50V8J
@1
2
+
C37
330U_D3L_6.3VM_R25M
1
2
JP13
FOX_AS0B226-S52N-7F~N
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
GND1
53
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
GND2 54
C686
0.1U_0402_16V4Z
1
2
C928
0.1U_0402_16V4Z
1 2
R724 22_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCM_PME#
PCM_SPK#
CLK_PCI_PCM
PCI_AD25
PCI_AD31
PCI_AD29
PCI_AD30
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD23
PCI_AD24
PCI_AD21
PCI_AD16
PCI_AD22
PCI_AD20
PCI_AD14
PCI_AD19
PCI_AD18
PCI_AD11
PCI_AD6
PCI_AD9
PCI_AD12
PCI_AD13
PCI_AD15
PCI_AD8
PCI_AD4
PCI_AD5
PCI_AD2
PCI_AD10
PCI_AD17
PCI_AD7
PCI_AD3
PCI_AD1
PCI_AD0
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
PCI_C/BE#3
S1_A8
S1_CE1#
S1_A12
S1_REG#
PCI_PERR#
PCI_IRDY#
PCI_TRDY#
PCI_FRAME#
CB_IDSEL
PCI_RST#
PCI_DEVSEL#
PCI_STOP#
PCI_SERR#
PCI_REQ2#
PCI_GNT2#
PCI_PAR
S1_A21
S1_A20
S1_A22
S1_A15
S1_A23
S1_A19
S1_A[0..25]
S1_D[0..15]
S1_RDY#
S1_WP
S1_A16
S1_BVD1
S1_D14
S1_D2
S1_A18
S1_BVD2
S1_CD1#
S1_VS2
S1_VS1
S1_CD2#
S1_INPACK#
S1_WE#
S1_A14
S1_WAIT#
S1_A13
S1_OE#
S1_CE2#
S1_D3
S1_D12
S1_D4
S1_D13
S1_D5
S1_A11
S1_D7
GBRST#
S1_D11
S1_D6
S1_A25
S1_A24
S1_A17
S1_A10
S1_D15
S1_IORD#
S1_A6
S1_A4
S1_A3
S1_A7
S1_A9
S1_A1
S1_D1
S1_A2
S1_D0
S1_A5
S1_D8
S1_IOWR#
S1_D10
S1_A0
S1_D9
S1_RST SD_WP#
SD_DET#
VCC5EN#
EXT_48M
VPPEN0
VPPEN1
NEC_USBP0+
SD_PWREN
VCC3EN#
SD_DAT2
SD_DAT3
SD_DAT1
SD_DAT0
SD_CLK_RSD_CLK
MDIO10
MDIO11
MDIO12
MDIO08 SD_CMD
NEC_USBP0-
CLK_48M_SD
MDIO13
GBRST#
CLK_PCI_PCM CLK_PCI_PCM_R
PCM_CLK_EN#
CLK_PCI_PCM_R
CLK_PCI_PCM CLK_PCI_PCM_R
PCM_CLK_EN#
PCI_AD20_R PCI_AD20CB_IDSEL
S1_CD1#
SD_DET# CARD_INSERT#
+3V_R5C843
+3V_R5C843
+3V_R5C843
+3V_R5C843
+3VS +3V_R5C843
+3V_R5C843
+3V_R5C843
+3V_R5C843
+3VS
+5VS
+3VS
PM_CLKRUN#<22,27,32,33,35>
S1_BVD1 <26>
S1_RDY# <26>
S1_BVD2 <26>
S1_RST <26>
PCI_AD[0..31]<20,27>
S1_WE# <26>
S1_INPACK# <26>
S1_WAIT# <26>
SIRQ<22,32,33,35>
PCI_PIRQA#<20>
PCI_PIRQC#<20>
HWSPND#<33>
PCI_C/BE#1<20,27> PCI_C/BE#2<20,27> PCI_C/BE#3<20,27>
PCI_C/BE#0<20,27>
S1_REG# <26>
S1_CE1# <26>
PCI_GNT2#<20> PCI_REQ2#<20>
PCI_TRDY#<20,27> PCI_IRDY#<20,27> PCI_STOP#<20,27> PCI_DEVSEL#<20,27>
PCI_PERR#<20,27>
PCI_PAR<20,27>
PCI_RST#<20,27>
PCI_FRAME#<20,27>
PCI_SERR#<20,27>
S1_D[0..15] <26>
S1_A[0..25] <26>
S1_IORD# <26>
S1_CE2# <26>
S1_OE# <26>
S1_IOWR# <26>
S1_WP <26>
PCM_PME#<34>
S1_CD1# <26>
PCM_SPK#<30>
S1_CD2# <26>
S1_VS2 <26>
S1_VS1 <26>
VCC5EN#<26>
VPPEN1<26>
SD_DET# <26>
SD_WP# <26>
VPPEN0<26>
CLK_48M_SD <5>
VCC3EN#<26>
SD_PWREN <26>
SD_CMD <26>
SD_DAT2 <26>
SD_DAT0 <26>
SD_DAT3 <26>
SD_DAT1 <26>
SD_CLK_R <26>
NEC_USBP0+<27> NEC_USBP0-<27>
CLK_PCI_PCM<5>
PCM_CLK_EN#<33>
CARD_INSERT# <33>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
CARDBUS_R5C843
25 53Monday, January 08, 2007
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Pull down UDIO4 to
disable MS function
Layout notice:
apply shield GND
for CLK_PCI_PCM to
reduce external noise.
USB signals, impedance 90 ohm
Layout notice: apply Shield GND
for L19 signal S1_A16
C71,C188, C208 close to
JP33 cardbus connector
G
D
S
Q67
SI1303DL-T1-E3_SOT323-3~D @
2
1 3
C15
0.1U_0402_16V7K
1
2
C505
0.47U_0603_10V7K
1
2
U48
SN74CBTD1G125_SC70-5
OE#
1
A
2
GND
3B4
VCC 5
R744
10_0402_5%
@
12
R479 33_0402_5%
12
R26
100K_0402_5%
12
C188
270P_0402_50V7K
@
1
2
C2
0.01U_0402_25V4Z
1
2
R24
100K_0402_5%
12
C361 100P_0402_50V8J
1 2
C18
0.01U_0402_25V4Z
1
2
C9
10U_0805_6.3V4Z
@
1
2
C4
10U_0805_6.3V4Z
1
2
C208
270P_0402_50V7K
@
1
2
R30 33_0402_5%
12
C24
0.01U_0402_25V4Z
1
2
R60 0_0402_5%@
1 2
R45 10K_0402_5%
1 2
R445 0_0805_5%
1 2
C17
0.01U_0402_25V4Z
1
2
C506
0.47U_0603_10V7K
1
2
C362 100P_0402_50V8J
1 2
C14
0.01U_0402_25V4Z
1
2
R29 100K_0402_5%@
1 2
C23
0.01U_0402_25V4Z
1
2
C3
0.01U_0402_25V4Z
1
2
C25
0.01U_0402_25V4Z
1
2
R848 100_0402_1%
1 2
R5C843
U15B
R5C843-CSP208P_CSP208~D
CPS
D11
TPAP1
B10
TPAP0
B12
TPAN0
A12
TPBP0
B13
TPBN0
A13
TPBIAS0
D12
XO
B16 XI
A16
TPAN1
A10
TPBP1
B11
TPBN1
A11
VREF
D13
REXT
B14
MDIO00 B1
MDIO01 A2
MDIO02 A3
MDIO03 B3
MDIO04 B4
MDIO05 A5
MDIO06 B5
MDIO07 D5
MDIO08 A6
MDIO09 B6
MDIO10 D6
MDIO11 E6
MDIO12 A7
MDIO13 B7
MDIO14 D7
MDIO15 E7
MDIO16 A8
MDIO17 B8
MDIO18 D8
MDIO19 E8
FIL0
A14
TPBIAS1
D10
USBDP
V14
USBDM
W14
VPPEN0
V13
VPPEN1
W13
VCC5EN#
R13
VCC3EN#
T13
REGEN#
R7
R46 10K_0402_5%
1 2
C706
15P_0402_50V8J
@
1
2
R699
10_0402_5%
@
12
R32 0_0402_5%@
1 2
C359 100P_0402_50V8J
1 2
U49
TC7SH08FUF_SSOP5
B
1
A
2Y4
P5
G
3
R36
10K_0402_5%
1 2
C1
0.01U_0402_25V4Z
1
2
R480 33_0402_5%
12
C6
0.01U_0402_25V4Z
1
2
R451 0_0402_5%
1 2
R5C843
U15A
R5C843-CSP208P_CSP208~D
AD31
M2
AD30
M1
AD29
N5
AD28
N4
AD27
N2
AD26
N1
AD25
P5
AD24
P4
AD23
R4
AD22
R2
AD21
R1
AD20
T2
AD19
T1
AD18
U2
AD17
U1
AD16
V1
AD15
T7
AD14
V7
AD13
W7
AD12
R8
AD11
T8
AD10
V8
AD9
W8
AD8
R9
AD7
V9
AD6
W9
AD5
T11
AD4
V11
AD3
W11
AD2
T12
AD1
V12
AD0
W12
PAR
V6
DEVSEL#
T5
FRAME#
V3
GNT#
M5
IDSEL
P1
IRDY#
V4
PERR#
W5
REQ#
M4
SERR#
T6
STOP#
V5
TRDY#
W4
CCLK/CADR16 L19
CCLKRUN#/WP(IOIS16#) A18
CRST#/RESET H19
RESERVED/CDATA2 C19
RESERVED/CDATA14 W18
RESERVED/CADR18 N16
CAD31/CDATA10 B19
CAD30/CDATA9 C18
CAD29/CDATA1 D19
CAD28/CDATA8 D18
CAD27/CDATA0 E19
CAD26/CADR0 E16
CAD25/CADR1 F18
CAD24/CADR2 F15
CAD23/CADR3 G18
CAD22/CADR4 G15
CAD21/CADR5 H18
CAD20/CADR6 H15
CAD19/CADR25 J18
CAD18/CADR7 J16
CAD17/CADR24 J15
CAD16/CADR17 P16
CAD15/IOWR# P19
CAD14/CADR9 R19
CAD13/IORD# P18
CAD12/CADR11 R18
CAD11/OE# T19
CAD10/CE2# T18
CAD9/CADR10 U19
CAD8/CDATA15 U18
CAD7/CDATA7 W17
CAD6/CDATA13 V17
CAD5/CDATA6 W16
CAD4/CDATA12 V16
CAD3/CDATA5 W15
CAD2/CDATA11 V15
CAD1/CDATA4 T15
CAD0/CDATA3 R14
CC/BE3#/REG# F16
CC/BE2#/CADR12 K18
CC/BE1#/CADR8 P15
CC/BE0#/CE1# V19
CPAR/CADR13 N15
CAUDIO/BVD2(SPKR#/LED) F19
RESERVED/CADR19 N19
CCD1#/CD1# T14
CCD2#/CD2# D15
CDEVSEL#/CADR21 L18
CFRAME#/CADR23 K16
CGNT#/WE# M15
CINT#/RDY(IREQ#) M18
CIRDY#/CADR15 K15
CREQ#/INPACK# G19
CSTOP#/CADR20 M16
CSTSCHG/BVD1(STSCHG#/RI#) E18
CTRDY#/CADR22 L16
CVS1/VS1# R16
CVS2/VS2# H16
PCICLK
K1
PCIRST#
L4
GBRST#
G2
CPERR#/CADR14 N18
CSERR#/WAIT# G16
HWSPND#
F2
CLKRUN#
L5
INTA#
J2
C/BE3#
P2
C/BE2#
W2
C/BE1#
W6
C/BE0#
T9
INTB#
K4
INTC#
K2
UDIO0/SERIRQ#
J4
UDIO1
H1
UDIO2
H2
UDIO3
H4
UDIO4
H5
UDIO5
G1
RI_OUT#/PME#
G4
SPKROUT
F1
TEST
F4
R34 0_0402_5%
1 2
R478 33_0402_5%
12
R33 10K_0402_5%
1 2
R31 0_0402_5%
1 2
C30
0.01U_0402_25V4Z1
2
R28 0_0402_5%
1 2
R50
100K_0402_5%
12
C13
0.01U_0402_25V4Z
1
2
C5
0.01U_0402_25V4Z
1
2
R5C843
U15C
R5C843-CSP208P_CSP208~D
VCC_3V1
F5
VCC_3V2
G5
VCC_3V3
J19
VCC_3V4
K19
VCC_PCI3V1
W3
VCC_PCI3V2
R11
VCC_PCI3V3
R12
VCC_MD3V
A4
VCC_RIN1
R6
VCC_RIN2
E13
VCC_ROUT1
L1
AGND1
A9
AGND2
B9
AGND3
D9
VCC_ROUT2
E14
AVCC_PHY1
E10
AVCC_PHY2
E11
AVCC_PHY3
A17
GND1
J1
GND2
J5
GND3
K5
GND4
E9
GND5
R10
GND6
T10
GND7
V10
GND8
W10
GND9
L15
GND10
M19
NC1 L2
NC2 C1
NC3 D1
NC4 E1
NC5 C2
NC6 D2
NC7 E2
NC8 E4
NC9 E12
AVCC_PHY4
B17
AGND4
D14
AGND5
A15
AGND6
B15
R27 100K_0402_5%
1 2
C679
4.7P_0402_50V8C
@
1
2
C7
0.01U_0402_25V4Z
1
2
C363 100P_0402_50V8J
1 2
C27
1U_0402_6.3V6K
1
2
R472 33_0402_5%
12
C8
10U_0805_6.3V4Z
1
2
C360 100P_0402_50V8J
1 2
C71
0.01U_0402_25V4Z
1 2
R473 33_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP S1_CD2#
S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD1
S1_BVD2
S1_D8
S1_D9
S1_D10
S1_A[0..25]
S1_D[0..15]
SD_CLK_R
VCC3EN#
VCC5EN#
+S1_VPP
+S1_VCC +S1_VPP
+S1_VCC
+SD_VCC
+3V_R5C843 +SD_VCC
+S1_VCC
+S1_VPP
+5VS
+3VS
S1_A[0..25]<25>
S1_WP<25>
S1_RDY#<25> S1_WE#<25>
S1_D[0..15]<25>
S1_CE1#<25>
S1_OE#<25>
S1_CD1# <25>
S1_VS1 <25>
S1_CE2# <25>
S1_IORD# <25>
S1_IOWR# <25>
S1_VS2 <25>
S1_RST <25>
S1_WAIT# <25>
S1_INPACK# <25>
S1_BVD2 <25>
S1_REG# <25>
S1_BVD1 <25>
S1_CD2# <25>
SD_DET#<25>
SD_WP#<25>
SD_DAT2<25>
SD_DAT3<25> SD_CMD<25>
SD_DAT0<25> SD_DAT1<25>
SD_CLK_R<25>
SD_PWREN<25>
VCC5EN#<25>
VCC3EN#<25>
VPPEN0<25> VPPEN1<25>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
PCMCIA Slot/SD
26 53Monday, January 08, 2007
CARDBUS SOCKET
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Close to SD socket
SD SOCKET
Closer to JP32
C11
10U_0805_6.3V4Z
1
2
C36
0.1U_0402_16V7K
1
2
C35
1U_0402_6.3V6K
1
2
Q15
AAT4250IGV-T1_SOT23-5
IN
5
ON/OFF#
4
OUT 1
GND 2
N.C 3
C12
0.01U_0402_25V4Z
1
2
JP32
MOLEX_67600-0001
SD1
1
SD2
2
Vss1
3
Vdd
4
SDCLK
5
Vss2
6
SD3
7
SD4
8
SD5
9
MMC_DET#
10 Wr_Pt_Vss 11
Vss3 12
Vss4 13
Wr_Pt 14
JP33
FCI_62597-00B_RB
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35 35
36 36
37 37
38 38
39 39
40 40
41 41
42 42
43 43
44 44
45 45
46 46
47 47
48 48
49 49
50 50
51 51
52 52
53 53
54 54
55 55
56 56
57 57
58 58
59 59
60 60
61 61
62 62
63 63
64 64
65 65
66 66
67 67
68 68
C41 0.1U_0402_16V7K
1
2U26
R5531V002-E2-FA_SSOP16
VCC3IN
11
VCC5IN
13
VCC5IN
15
NC
6
EN1
4
EN0
3
VCC3_EN
2
VCC5_EN
1
VCCOUT 14
VCCOUT 12
VCCOUT 9
VPPOUT 8
NC 10
NC 7
FLG 5
GND 16
R643
150K_0402_5%
12
C40
0.1U_0402_16V7K
1
2
C38 0.1U_0402_16V7K
1
2
C371
10P_0402_50V8J
1
2
C10
0.01U_0402_25V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BT_ACTIVE
NEC_USBP2-
WLAN_ACTIVE
NEC_USBP2+
PCI_C/BE#0
PCI_AD4
PCI_PAR
PCI_AD3
PCI_FRAME#
PCI_AD2
NEC_USBP1-_R
PCI_AD1
USB_IDSEL
NEC_USBP1+_R
PCI_AD0
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
AVSS
NEC_USBP2-_R
PCI_REQ0#
PCI_PIRQE#
PCI_GNT0#
PCI_PERR#
PCI_SERR#
NEC_USBP2+_R
PCI_PIRQF#
PCI_PIRQG#
CLK_PCI_USB_R
VBBRST#
USB_PME#
NEC_USBP3-_R
NEC_USBP3+_R
VCCRST#
NEC_USBP4-_R
NEC_USBP4-
NEC_USBP4+_R
PCI_AD31
NEC_USB_OC#0
PCI_AD30
NEC_USB_OC#1
PCI_AD29
NEC_USB_OC#2
PCI_AD28
USB_SMI#
NEC_USB_OC#3
PCI_AD27
PCI_RST#
NEC_USB_OC#4
PCI_AD26
AVSS
PCI_AD25
PCI_AD24
PCI_AD23
CLK_PCI_USB
PCI_AD22
PCI_C/BE#3
PCI_AD21
PCI_AD20
PM_CLKRUN#
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
NEC_USBP0-_R
PCI_AD15
PCI_AD14
PCI_AD13
NEC_USBP0-
PCI_AD12
NEC_USBP0+_R
PCI_AD11
EC_RSMRST#
PCI_AD10
PCI_AD9
PCI_AD8
PCI_RST#
PCI_AD7
PCI_C/BE#2
PCI_AD6
PCI_C/BE#1
PCI_AD5
AVSS
NEC_USBP0+
NEC_USBP0-
NEC_USBP1+
NEC_USBP1-
NEC_USBP2-
NEC_USBP2+
NEC_USBP3-
NEC_USBP3+
CLK_48M_USB_R
NEC_USBP3+
NEC_USBP2-
NEC_USBP3-
NEC_USBP1+
NEC_USBP1-
NEC_USBP0+
CLK_48M_USB
USB_CLK_EN#
CLK_PCI_USB CLK_PCI_USB_R
USB_CLK_EN#
PCI_AD21_RUSB_IDSEL
CLK_PCI_USB CLK_PCI_USB_R
PCI_AD21
NEC_USBP4-
NEC_USB_OC#0
NEC_USB_OC#3
NEC_USB_OC#4
NEC_USB_OC#2
NEC_USBP4+
NEC_USB_OC#1
NEC_USBP4+
USB_CLK_EN#
CLK_48M_USB CLK_48M_USB_R
CLK_48M_USB CLK_48M_USB_R
NEC_USBP2+
+3VS
USB_AVDD
+3V_NECUSB USB_AVDD
USB_AVDD
+3V_NECUSB
+3V_NECUSB
+3V_NECUSB
+3V_NECUSB
+3VS
+5VS
+5VS
+3VS
+3V_NECUSB
BTDIS#<33>
PCI_C/BE#1<20,25> PCI_C/BE#0<20,25>
PCI_PAR<20,25> PCI_FRAME#<20,25>
PCI_STOP#<20,25>
PCI_IRDY#<20,25> PCI_TRDY#<20,25>
PCI_DEVSEL#<20,25>
PCI_SERR#<20,25> PCI_PERR#<20,25> PCI_GNT0#<20> PCI_REQ0#<20>
PCI_PIRQE#<20> PCI_PIRQF#<20> PCI_PIRQG#<20>
USB_PME#<34>
PCI_RST#<20,25>
PCI_AD[0..31]<20,25>
PM_CLKRUN#<22,25,32,33,35>
EC_RSMRST#<22,33>
PCI_C/BE#3<20,25>
USB_SMI#<22>
PCI_C/BE#2<20,25>
WLAN_ACTIVE<24>
BT_ACTIVE<24>
NEC_USBP1- <24>
NEC_USBP1+ <24>
NEC_USBP0- <25>
NEC_USBP0+ <25>
USB_CLK_EN#<33>
CLK_PCI_USB<5>
USB_CLK_EN#<33>
CLK_48M_USB<5>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
BT&USB CONTROLLER
27 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BT MODULE CONN
Bluetooth Cable
Mini Card Pin3
Mini Card Pin5
WLAN_ACTIVE JP27.4
BT_ACTIVE JP27.1
R343 1.5K_0402_5%
12
R310 36_0603_1%@
1 2
R308 36_0603_1%@
1 2
R320 0_0402_5%
1 2
R314 0_0402_5%
1 2
R341 1.5K_0402_5%
12
G
D
S
Q68
SI1303DL-T1-E3_SOT323-3~D @
2
1 3
C357
0.1U_0402_16V4Z
1
2
RP54
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R342 1.5K_0402_5%
12
C79
10U_0805_6.3V4Z
1
2
R74 0_0402_5%
@
1 2
R321 0_0402_5%@
1 2
C78
10U_0805_6.3V4Z
1
2
R304 36_0603_1%
1 2
R311 36_0603_1%@
1 2
R312 0_0402_5%
@
1 2
R309 36_0603_1%@
1 2
R345 1.5K_0402_5%
12
C350
0.1U_0402_16V4Z
@
1
2
R306 36_0603_1%
1 2
C358
0.1U_0402_16V4Z
1
2
R322
15K_0402_5%
1 2
C742
0.1U_0402_16V4Z
1 2
R305 36_0603_1%
1 2
C355
0.1U_0402_16V4Z
1
2
R260
0_0603_5%
1 2
C80
10U_0805_6.3V4Z
1
2
R318 36_0603_1%
1 2
R748
10_0402_5%
@
12
U53
SN74CBTD1G125_SC70-5
OE#
1
A
2
GND
3B4
VCC 5
R307 36_0603_1%
1 2
C77
10U_0805_6.3V4Z
1
2
R698
10_0402_5%
@
12
C354
0.1U_0402_16V4Z
1
2
R856
100_0402_1%
12
C349
0.1U_0402_16V4Z
@
1
2
R340 1.5K_0402_5%
12
C72
10U_0805_6.3V4Z
@1
2
R826
0_0805_5%
1 2
R344 1.5K_0402_5%
12
R324
10K_0402_5%
1 2
USB 2.0 CONTROLLER
uPD720101F1-EA8
FBGA144
U27
uPD720101F1-EA8-A_FBGA144
VDD P2
NTEST1 M8
VDD D7
TEST L8
XT1/SCLK L9
XT2 P8
LEGC
L7
VDD P3
VSS
B1
VCCRST#
C9
SMI#
L6
N.C.
P6
N.C
M6
PME#
D9
PCLK
A8
VBBRST#
B8
VDD P12
VSS
N1
VDD_PCI H3
INTA#
C7
INTB#
B7
INTC#
A7
GNT0#
D6 REQ0#
C6
AD31
A6
AD30
B6
VSS
P10
AD29
C5
AD28
A5
AD27
C4
AD26
B5
AD25
A4
AD24
B4
CBE3#
C3
IDSEL
B3
VDD A13
VSS
N14
VSS
D8
AD23
C1
SMC M7
AD22
C2
AD21
D2
AD20
D1
AD19
D3
VDD A12
AD18
E1
AD17
E3
AD16
F2
CBE2#
F1
FRAME#
F3
IRDY#
F4
TRDY#
G1
DEVSEL#
G2
VDD_PCI M4
STOP#
G3
PERR#
H2
SERR#
H1
PAR
J4
CBE1#
J3
VSS
H14
AD15
J1
AD14
J2
AD13
K3
VDD A3
AD12
K1
AD11
L3
AD10
K2
AD9
L1
AD8
L2
CBE0#
M2
AD7
M1
AD6
N3
VSS
B14
VSS
D12
VDD E2
AD5
M3
AD4
N4
AD3
P4
AD2
N5
AD1
P5
AD0
M5
CRUN#
N6
VDD_PCI C8
SRDTA N9
SRCLK M9
SRMOD P9
OCI1 B12
PPON1 C12
OCI5 B9
OCI2 B11
OCI4 A10
AMC P7
OCI3 B10
VDD N8
VSS
A2
PPON2 A11
PPON3 C11
PPON4 C10
TEB N7
PPON5 A9
NANDTEST M10
VSS
B2
RSDM5 E13
DM5 D14
VDD G12
DP5 C13
RSDP5 C14
VSS
N13
VDD L13
VSS
B13
VSS
M11
RSDM1 M14
DM1 M13
VDD J13
DP1 L14
RSDP1 K13
VSS
L12
RSDM2 K14
DM2 K12
VDD H13
DP2 J14
RSDP2 J12
VSS
H12
VDD F13
VSS
N2
AVDD N10
AVSS
P13
AVDD N12
AVSS(R) N11
RREF P11
AVSS
M12
VSS
G4
RSDM3 H11
DM3 G11
DP3 G13
RSDP3 G14
VSS
J11
RSDM4 F12
DM4 F14
VDD D13
DP4 E12
RSDP4 E14
VSS
F11
VDD H4
R261
0_0603_5%
1 2
U50
SN74CBTD1G125_SC70-5
OE#
1
A
2
GND
3B4
VCC 5
R452 0_0402_5%
1 2
R73 0_0402_5%
@
1 2
C353
0.1U_0402_16V4Z
1
2
R319 36_0603_1%
1 2
C356
0.1U_0402_16V4Z
1
2
R75 0_0402_5%@
1 2
RP55
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R346 1.5K_0402_5%
12
C352
0.1U_0402_16V4Z
1
2
C351
0.1U_0402_16V4Z
@
1
2
R313
0_0402_5%
@
1 2
R323
15K_0402_5%
1 2
C678
4.7P_0402_50V8C
@
1
2
RP30
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
C707
15P_0402_50V8J
@
1
2
JP15
MOLEX_53780-0890
1
2
3
4
5
6
7
8
JP29
ACES_85201-0405
@
1
2
3
4
R329
9.1K_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LAN_EN#
LAN_CTRL25
CLK_PCIE_LAN
LAN_WAKE#
VPD_DATA
MAR_RSET
PLT_RST#
CLK_PCIE_LAN#
XTALOXTALI
LAN_ACT#
XTALO
XTALI
LAN_CTRL25
MAR_DISABLE
LAN_MDI1-
LAN_MDI1+
LAN_MDI0-
LAN_MDI0+
VPD_CLK
LAN_MDI3-
LAN_MDI3+
LAN_MDI2-
LAN_MDI2+
PCIE_MAR_T+
PCIE_MAR_T-
LAN_LINK#
LAN_CTRL12
MAR_VAUX
MAR_VMAIN
VPD_CLK
PCIE_RXP1
LAN_CTRL12
PCIE_RXN1
PCIE_TXN1
PCIE_TXP1
VPD_DATA
LAN_WAKE#
+12VALW
+3V_LAN
+3VALW
+3VALW
+3V_LAN
+3V_LAN
+2.5V_LAN
+3V_LAN
+3V_LAN
+1.2V_LAN
+1.2V_LAN
+2.5V_LAN
+2.5V_LAN
+1.2V_LAN
+3V_LAN
+3V_LAN
+3V_LAN
+LAN_AVDDL
+LAN_AVDD
+LAN_AVDDL +LAN_AVDD
LAN_EN#<33>
PCIE_TXP1<22>
PCIE_RXP1<22>
PLT_RST#<9,18,20,22,24,32,33,35>
CLK_PCIE_LAN#<5> CLK_PCIE_LAN<5>
LAN_MDI1+<29> LAN_MDI1-<29>
LAN_MDI3-<29>
LAN_MDI2+<29> LAN_MDI2-<29>
LAN_MDI0+<29> LAN_MDI0-<29>
LAN_MDI3+<29>
LAN_LINK# <29>
PCIE_RXN1<22> LAN_ACT# <29>
PCIE_TXN1<22>
LAN_WAKE#<22>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
88E8053
28 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Note: Place Bypass Cap. with every power pin ACAP.
40 mil
40mil
40mil
TRACE TO IC IS 25MIL
PLACE PNP TO CHIP ACAP
CTRL25 PIN TRACE IS
25MIL
PLACE PNP TO CHIP ACAP
CTRL12 PIN TRACE IS
25MIL
9 Vias to Ground at least.
C73
0.1U_0402_16V4Z
1
2
C55
0.1U_0402_16V4Z
1
2
R77 0_0402_5%
1 2
Y8
25MHZ_20PF_6X25000017
1 2
C53
0.1U_0402_16V4Z
1
2
R79 0_0402_5%@1 2
C57
0.1U_0402_16V4Z
1
2
C75
0.1U_0402_16V4Z
1
2
C750
0.01U_0402_16V7K
1
2
U20
AT24C16AN-10SU-2.7_SO8~N
A0 1
A1 2
SDA
5SCL
6
VCC
8
A2 3
GND 4
WP
7
C58
0.1U_0402_16V4Z
1
2
S
G
D
Q52 SI3456BDV-T1-E3_TSOP6
3
6
245
1
R35
4.7K_0402_5%
12
R39 10K_0402_5%
1 2
R40
4.7K_0402_5%
12
R78 0_0402_5%
@1 2
R47
4.7K_0402_5%
12
C74
0.1U_0402_16V4Z
1
2C49
0.1U_0402_16V4Z
1
2
R81 4.75K_0402_1%
1 2
R794
10K_0402_5%
12
C56 0.1U_0402_16V4Z
1 2
C48
4.7U_0805_10V4Z
1
2
C69
18P_0402_50V8J
1
2
PJP25
PAD-SHORT 2x2m
2 1
C60
0.1U_0402_16V4Z
1
2
C51
0.1U_0402_16V4Z
1
2
C54
0.1U_0402_16V4Z
1
2
PCI-E LED
CLOCK
FLASH
MEMORY
EEPROM
TEST
Media
Analog
POWER
&
GROUND
U13
88E8053-NNC1C000_QFN64
TX_P
49
TX_N
50
RX_P
54
RX_N
53
WAKEn
6
REFCLKP
55
REFCLKN
56
PERSTn
5
MDIP0
17
MDIN0
18
MDIP1
20
MDIN1
21
MDIP2
26
MDIN2
27
MDIP3
30
MDIN3
31
VPD_CLK
38
VPD_DATA
41
SPI_DO
34
SPI_DI
35
SPI_CLK
37
SPI_CS
36
XTALI
15
XTALO
14
LOM_DISABLEn
10
VAUX_AVLBL
12
SWITCH_VCC
11
VMAIN_AVLBL
47
SWITCH_VAUX
9
HSDACP
24
HSDACN
25
RSET
16
CTRL25
4
CTRL12
3
LED_ACTn 59
LED_LINK10/100n 60
LED_LINK1000n 62
LED_LINKn 63
TESTMODE 46
TSTPT 29
VDD25 64
AVDDL 19
AVDDL 22
AVDDL 28
AVDDL 32
AVDDL 51
AVDDL 52
AVDDL 57
AVDD 23
VDDO_TTL 1
VDDO_TTL 8
VDDO_TTL 40
VDDO_TTL 45
VDDO_TTL 61
VDD 2
VDD 7
VDD 13
VDD 33
VDD 39
VDD 44
VDD 48
VDD 58
SMCLK/NC 42
SMDATA/NC 43
EPAD 65
R288
0_0603_5%
12
R793
10K_0402_5%
12
C63
0.1U_0402_16V4Z
1
2
C70
18P_0402_50V8J
1
2
C46 0.1U_0402_16V4Z
1 2
C64
0.1U_0402_16V4Z
1
2
C62
0.1U_0402_16V4Z
1
2
G
D
S
Q51
2N7002_SOT23
2
13
C65
0.1U_0402_16V4Z
1
2
C61
0.1U_0402_16V4Z
1
2
R41
4.7K_0402_5%
12
C52
0.1U_0402_16V4Z
1
2
C66
0.1U_0402_16V4Z
1
2
C50
4.7U_0805_10V4Z
1
2
TP1 PAD
Q53
BCP69_SOT223
1
2
43
C67
0.1U_0402_16V4Z
1
2
C47 0.1U_0402_16V4Z
1 2
C59
0.1U_0402_16V4Z
1
2
Q50
BCP69_SOT223
1
2
43
R38
4.7K_0402_5%
12
R289
0_0603_5%
12
C68
0.1U_0402_16V4Z
1
2
R76 0_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RJ45_MDI0-
RJ45_MDI0+
RJ45_MDI1+
RJ45_MDI2-
RJ45_MDI1-
RJ45_MDI3+
RJ45_MDI3-
RJ45_MDI2+
RJ45_MDI1+
RJ45_MDI3-
RJ45_MDI0-
RJ45_MDI2+
SW_LAN_TX+
SW_LAN_RX+
SW_LAN_TX-
SW_LAN_RX3+
SW_LAN_TX2+
SW_LAN_TX2-
RJ45_MDI1-SW_LAN_RX-
RJ45_MDI0+
RJ45_MDI2-
RJ45_MDI3+
SW_LAN_RX3-
LAN_MDI0+
LAN_MDI0-
LAN_MDI1+
LAN_MDI1-
LAN_MDI2+
LAN_MDI2-
LAN_MDI3+
LAN_MDI3-
LAN_SW_VCC
SW_LAN_RX3+
SW_LAN_RX3-
SW_LAN_RX-
DOCK_LAN_TX-
DOCK_LAN_RX+
DOCK_LAN_TX+
DOCK_LAN_TX2+
DOCK_LAN_RX3+
DOCK_LAN_RX3-
DOCK_LAN_TX2-
LAN_MDI0+R
LAN_MDI1+R
SW_LAN_TX2+
SW_LAN_TX2-
SW_LAN_RX+
SW_LAN_TX+
SW_LAN_TX-
LAN_MDI3+R DOCK_LAN_RX-
DOCK_LAN_ACT#
DOCK_LAN_LINK#
LAN_MDI0+
LAN_MDI1+
LAN_MDI3+
DOCKEN
LAN_MDI0-
LAN_MDI1-
LAN_MDI2+R
LAN_MDI2+
LAN_MDI2-
LAN_MDI3-
LAN_MDI0-R
LAN_MDI1-R
LAN_MDI2-R
LAN_MDI3-R
LAN_MDI0- LAN_MDI0-R
LAN_MDI0+RLAN_MDI0+
LAN_MDI1-RLAN_MDI1-
LAN_MDI1+RLAN_MDI1+
LAN_MDI2- LAN_MDI2-R
LAN_MDI2+ LAN_MDI2+R
LAN_MDI3- LAN_MDI3-R
LAN_MDI3+ LAN_MDI3+R
+2.5V_LAN
+3V_LAN
LAN_MDI0+<28>
LAN_MDI1+<28>
LAN_MDI3+<28>
DOCKEN<33>
LAN_LINK#<28>
LAN_ACT#<28>
DOCK_LAN_TX- <36>
DOCK_LAN_TX+ <36>
DOCK_LAN_RX- <36>
DOCK_LAN_RX+ <36>
DOCK_LAN_TX2- <36>
DOCK_LAN_TX2+ <36>
DOCK_LAN_RX3- <36>
DOCK_LAN_RX3+ <36>
DOCK_LAN_ACT# <36>
DOCK_LAN_LINK# <36>
LAN_MDI2+<28>
LAN_MDI0-<28>
LAN_MDI1-<28>
LAN_MDI2-<28>
LAN_MDI3-<28>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Magnetics & RJ45
29 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Close to Chip side
FROM NIC
DOCKEN 1: TO DOCK
0: TO RJ45
LAN ANALOG
SWITCH
TO
RJ45
TO
DOCK
Layout Notice : Place ckoke as
close PI3L500 as possible
R819
0_0603_5%
@
1 2
R810 75_0402_1%
1 2
C779
0.1U_0603_16V7K
1
2
R825
0_0603_5%
@
1 2
R806 49.9_0402_1%
12
C784 0.01U_0402_16V7K
1 2
L24
WCM-2012-900T_4P~D
1
1
4
433
22
T21
BOTH_GST5009-V LF
TCT1
1
TD1+
2
TD1-
3
TCT2
4
TD2+
5
TD2-
6MX2- 19
MX2+ 20
MCT2 21
MX1- 22
MX1+ 23
MCT1 24
TCT3
7
TD3+
8
TD3-
9
TCT4
10
TD4+
11
TD4-
12
MCT3 18
MX3+ 17
MX3- 16
MCT4 15
MX4+ 14
MX4- 13
R820
0_0603_5%
@
1 2
R803 49.9_0402_1%
12
R801 49.9_0402_1%
12
C786
1000P_1206_2KV7K
1
2
C781
0.01U_0402_16V7K
12
R821
0_0603_5%
@
1 2
R813 75_0402_1%
1 2
R807 49.9_0402_1%
12 L22
WCM-2012-900T_4P~D
1
1
4
433
22
C777
0.01U_0402_16V7K
12
C776
0.01U_0402_16V7K
12
R811 75_0402_1%
1 2
R804 49.9_0402_1%
12
JP16
ALLTOP_C10068-10804
PR1-
2
PR1+
1
PR2+
3
PR3+
4
PR3-
5
PR2-
6
PR4+
7
PR4-
8
SHLD2
10
SHLD1
9
R809
0_0603_5%
12
L25
WCM-2012-900T_4P~D
1
1
4
433
22
R822
0_0603_5%
@
1 2
C783 0.01U_0402_16V7K
1 2
C271
0.001U_0402_50V7M
1 2
C782 0.01U_0402_16V7K
1 2
L26
BLM18AG601SN1D_0603 @ 1 2
R800
0_0805_5%
1 2
U24
PI3L500ZFE_TQFN56
SEL
17
A0
2
A1
3
A2
7
A3
8
A4
11
A5
12
A6
14
0B1 48
0B2 46
1B1 47
1B2 45
2B1 43
2B2 41
3B1 42
3B2 40
4B1 37
4B2 35
5B1 36
5B2 34
6B1 32
6B2 30
7B1 31
7B2 29
A7
15
LED0
19
LED1
20
LED2
54
0LED1 22
0LED2 25
1LED1 23
1LED2 26
2LED1 52
2LED2 51
NC
5
VDD0 4
VDD1 10
VDD2 18
VDD3 27
VDD4 38
VDD5 50
VDD6 56
GND0
1
GND1
6
GND2
9
GND3
13
GND4
16
GND5
21
GND6
24
GND7
28
GND8
33
GND9
39
GND10
44
GND11
49
GND12
53
GND13
55
R818
0_0603_5%
@
1 2
C785 0.01U_0402_16V7K
1 2
R823
0_0603_5%
@
1 2
L23
WCM-2012-900T_4P~D
1
1
4
433
22
R805 49.9_0402_1%
12
C778
0.047U_0402_16V7K
@
1
2
C780
0.01U_0402_16V7K
12
R812 75_0402_1%
1 2
R802 49.9_0402_1%
12
R808 49.9_0402_1%
12
R824
0_0603_5%
@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SENSE_B
MB_HP_R1
INT_MIC3
DOCK_HP_PLUG#
INT_SPK_L
PC_BEEP
HP_OUT_L
SDATA_IN
MB_MIC_L
INT_MIC2
SENSE_B
SENSE_A
ICH_AZ_CODEC_RST#
INT_SPK_R
HP_OUT_R
ICH_AZ_CODEC_BITCLK MB_MIC_R
CAP2
PC_BEEP
VDDA
INT_MIC1
ICH_AZ_CODEC_SDOUT
SENSE_A
AFILT1
AFILT2
MB_HP_L1
INT_MIC3
ICH_AZ_CODEC_SYNC
MB_HP_R1
MB_HP_L1 MB_HP_L
MB_HP_R
ShutDown#
MB_HP_PLUG#
ShutDown#
VDDA
VDDC
VDDA
+3VS
VDDA
VDDA
+5VALW
VDDA
VDDC
VDDA
VDDA
MIC_SEL<33>
VrefOut_B <31>
INT_MIC1 <36>
INT_MIC3 <31>
BEEP#<33>
PCM_SPK#<25>
ICH_SPKR<22>
DOCK_MIC <36>
HP_PLUG#<31,36>
DIS_INTMIC<36>
INT_MIC3 <31>
INT_MIC2 <36>
ICH_AZ_CODEC_BITCLK<21>
INT_SPK_L <31>
INT_SPK_R <31>
GNDA<31,36>
MB_HP_PLUG# <31>
MIC_SENSE <31>
HP_OUT_L <36>
HP_OUT_R <36>
MB_MIC_L <31>
MB_MIC_R <31>
ICH_AZ_CODEC_SDOUT<21> ICH_AZ_CODEC_SYNC<21> ICH_AZ_CODEC_RST#<21>
ICH_AZ_CODEC_SDIN0<21>
MB_HP_L <31>
MB_HP_R <31>
SUSP#<33,37,39>
ShutDown# <33>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Azalia Codec STAC9220
30 53Monday, January 08, 2007
GPIO pin
Port E for INT_MIC1
and INT_MIC3
For DOCK MIC
For DOCK HP
Port C for DOCK/B ext mic
R59 POP DE_POP
Port A for MB HP
STAC9220
R58,C799 DE_POP POP
Analog ground
Digital ground
Place decoupling
caps as close to
Codec as possible.
Item
MIC_SEL
H (Portrait)
L (Landscape)
INT_MIC1 INT_MIC2 INT_MIC3
ENABLE ENABLE
ENABLE ENABLE
DISABLE
DISABLE
NOTE: Place pull-up
resistors close to
CODEC Pin25
MB_HP_PLUG#
(PIN 23/24)
DIS_INTMIC DOCK_MIC
H
LENABLE
DISABLE ENABLE
DISABLE
INT_SPK_L PIN16
H
L
ENABLE
DISABLE
INT_SPK_R PIN17
INT_MIC1
INT_MIC3
INT_MIC2 (PIN 46) (PIN 14) (PIN 20) (PIN 15,18) MIC2
OO
O
MIC3MIC1
STAC9228
POP DE_POP
CD input pins for
INT_MIC2 and INT_MIC3
Port F for internal speaker
Io= 200mA
Vo= 4.65V ~ 4.85V
w=30mil
w=40mil
Port D for DOCK/B HP
Port B for MB ext mic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
For MB HP
Place bypass capacitor
close to CODEC Pin26
For MB EXT MIC
C26,C32
(EAPD function)
R61 DE_POP POP
C793 1U_0603_10V4Z
1 2
R961
10K_0603_1%
R963
39.2K_0603_1%
G
D
S
Q60
2N7002_SOT23
2
13
C39
1U_0603_16V6K
2@
1
2
G
D
S
Q58
2N7002_SOT23
2
13
C788
0.1U_0402_16V4Z
1
2
G
D
S
Q59
2N7002_SOT23
2
13
R23
0_0603_5%
1@
1 2
R16 0_0603_5%
1 2
R815
100K_0402_5%
@
12
C799
0.1U_0402_16V4Z
9228@
1
2
C791
0.1U_0402_16V4Z
1
2
C31
10U_0805_6.3V6M
1
2
R58
0_0402_5%
9228@
D18
1SS355_SOD323
@
12
R18 0_0603_5%
1 2
C33
10U_0805_6.3V6M
1
2
C19
0.1U_0402_16V4Z
1
2
C800
0.1U_0402_16V4Z
@
1
2R25
0_0603_5%
1@
1 2
R816 2K_0402_5%
12
C32
820P_0603_50V7K
9220@
1
2
R746
22_0402_5%
@
1 2
C790
0.1U_0402_16V4Z
1
2
R49
100K_0402_5%
1 2
U47
MAX9890AEBL+T_UCSP9
2@
VCC C2
SHDN#
C1
INL
B1 OUTL A1
GND
A2 OUTR A3
INR
B3
CEXT C3
NC B2
C26
820P_0603_50V7K
9220@
1
2
C794 1U_0603_10V4Z
1 2
U18
TPS793475DBVR_SOT23-5
VIN
1
EN
3
VOUT 5
GND 2
BYPASS 4
R57
100K_0402_5%
2@
1 2
C798
0.1U_0402_16V4Z
2@
1
2
STAC9220
U22
STAC9220X5TAEA6XR_LQFP48~D
AVDD1
25
AVDD2
38
DVDD_CORE1
1
DVDD_CORE3
9
BIT_CLK
6
SDATA_IN
8
SDATA_OUT
5
SYNC
10
RESET#
11
CAP2
33
VREF_FILT
27
AFILT1
30
AFILT2
31
VOLUME_DOWN
3
VOLUME_UP
2
GPIO0
45
GPIO1
46
GPIO2
44
GPIO3/SPDIFIN/EAPD
47
SPDIF_OUT
48
PLL_CAP
43
NC
40
SENSE_A 13
SENSE_B 34
PORT_A_L_HP 39
PORT_A_R_HP 41
PORT_B_L 21
PORT_B_R 22
PORT_C_L 23
PORT_C_R 24
PORT_D_L_HP 35
PORT_D_R_HP 36
PORT_E_L 14
PORT_E_R 15
PORT_F_L_HP 16
PORT_F_R_HP 17
VREFOUT_A 37
VREFOUT_B 28
VREFOUT_C 29
VREFOUT_D 32
CD_L 18
CD_G 19
CD_R 20
PC_BEEP 12
AVSS1 26
AVSS3 42
DVSS2
4
DVSS3
7
C21
0.33U_0603_16V4Z
R19
5.11K_0402_1%~D
C16
1U_0603_16V6K
1
2
C789
4.7U_0805_10V4Z
1
2
C416
22U_0805_6.3V6M
@
1
2
G
D
S
Q62
2N7002_SOT23
@
2
13
R817 2K_0402_5%
12
R747
33_0402_5%
1 2
C795
0.1U_0402_16V4Z
1
2
R962
20K_0603_1%
C787
4.7U_0805_10V4Z
1
2
C34
10U_0805_6.3V6M
1
2
C797
0.1U_0402_16V4Z
1
2
C20
0.1U_0402_16V4Z
1
2
R59
0_0402_5%
9220@
R48
0_0402_5%
R814 2K_0402_5%
12
R960
5.11K_0402_1%~D
R61
0_0402_5%
9228@
L21
MBK1608301YZF_0603
1 2
C796 1U_0603_10V4Z
1 2
C792
0.1U_0402_16V4Z
1
2
R20
5.11K_0402_1%~D
R17 0_0603_5%
1 2
C22
27P_0402_50V8J
@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PORTB_1L
INTSPK_L-
INTSPK_L+
INTSPK_R+
INTSPK_R-
MB_HP_PLUG#
MIC_SENSE
PORTA_2L
PORTA_1R
PORTA_1L
PORTA_2R
INTSPK_L+
GAIN1
BYPASS
INTSPK_L-
GAIN0
INTSPK_R+
INTSPK_R-
GAIN1
GAIN0
INT_MIC_3
MB_MIC_L
PORTB_2R
PORTB_2L
PORTB_1RMB_MIC_R
VrefOut_B
PORTA_3RMB_HP_R
PORTA_3LMB_HP_L
INTMIC3
+5VS
VDDA
+5VS
+5VAMP
VDDA
+5VS
VDDA
MIC_SENSE<30>
INT_SPK_R<30>
MB_MIC_R<30>
MB_MIC_L<30>
INT_SPK_L<30>
MUTE#<33>
INT_MIC3<30>
GNDA<30,36>
MB_HP_R<30>
MB_HP_L<30>
MB_HP_PLUG#<30>
VrefOut_B<30>
HP_PLUG#<30,36>
MB_HP_PLUG#<30>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
AMP & Audio JACK
31 53Monday, January 08, 2007
Speaker
MB HP
MB ext MIC
PORT A
Internal MIC3
Gain Setting
6dB0
GAIN0 GAIN1
15.6dB
21.6dB
0
W=30mils
AV(inv)
90K ohm
45K ohm
0
INPUT
Compal P/N: SCVL080C000
10dB
25K ohm
1
IMPEDANCE
*
1
11
0
70K ohm
DVT2 swap pin
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PORT B
R845
20K_0402_5%
12
JP18
MOLEX_53780-0290
1
12
2
L51
BLM18AG601SN1D_0603
1 2
C831
0.1U_0402_16V4Z
1
2
U16
TPA6017A2PWPRG4_TSSOP20~N
GND4
1GND3
11 GND2
13 GND1
20
VDD 16
PVDD1 15
RIN-
17
BYPASS 10
NC 12
LOUT- 8
LOUT+ 4
ROUT- 14
ROUT+ 18
RIN+
7
LIN-
5
LIN+
9
GAIN0 2
GAIN1 3
PVDD2 6
SHUTDOWN
19
R829
10K_0402_5%
12
C42
2.2U_0805_25V6K
1 2
R700
4.99_0402_1%
1 2
R831
4.7K_0402_5%
1 2
JP19
ACES_85201-0405
1
2
3
4
R827
10K_0402_5%
@
12
C45
2.2U_0805_25V6K
1 2
R707
4.99_0402_1%
1 2
R847
20K_0402_5%
@
12
L42
BK1608HM601-T_0603
1 2
L36
FBMA-L11-160808-700LMT
1 2
R840
4.02K_0603_1%
1 2
C822
0.1U_0402_16V4Z
1 2
C828
10U_0805_10V4Z
1
2
R844
20K_0402_5%
12
C835
0.01U_0402_25V4Z
1
2
C818
10U_0805_10V4Z
1
2
L47
BK1608HM601-T_0603
1 2
R841
4.02K_0603_1%
1 2
C836
0.01U_0402_25V4Z
1
2
R2
100K_0402_5%
12
R1
100K_0402_5%@
12
C830
4.7U_0805_10V4Z
1
2
R846
20K_0402_5%
@
12
C833
220P_0402_50V7K
1
2
+
C827
220U_D2_4VM
1 2
C817
0.1U_0402_16V4Z
1
2
C816
0.1U_0402_16V4Z
1
2
C834
220P_0402_50V7K
1
2
D33
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
L35
BLM21PG221SN1D_0805
1 2
R5
4.02K_0603_1%
1 2
C821
0.47U_0603_16V4Z
1 2
+
C826
220U_D2_4VM
1 2
D32
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
C824
0.1U_0402_16V4Z
1 2
C815 0.22U_0603_10V7K
12
R828
10K_0402_5%
12
JP17
MOLEX_53780-0290
1
1
2
2
L48
BLM18AG601SN1D_0603
1 2
U31
TC7SH08FUF_SSOP5
B
1
A
2Y4
P5
G
3
U30
TC7SH08FUF_SSOP5
B
1
A
2Y4
P5
G
3
R830
10K_0402_5%
@
12
C819
0.1U_0402_16V4Z
1
2
JP21
SUYIN_010030FR006G100ZL
1
2
3
4
5
6
C823
0.47U_0603_16V4Z
1 2
JP20
SUYIN_010030FR006G100ZL
1
2
3
4
5
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPCPD#
USBP0- USB20_P0_RUSBP0+
TPM_LPCPD#
SUS_STAT# LPCPD#
CLK_PCI_TPM
TPM_XTALO
USB_OC#0
USB_OC#1
LPC_AD1
LPC_AD3
TPM_XTALO
CLK_PCI_TPM
TPM_XTALI
LPC_AD2
TPM_XTALI
PM_CLKRUN#
LPC_FRAME#
SIRQ
LPC_AD0
PLT_RST#
BADDR
USB20_N0_R
USB20_P1_R
USBP1-
USBP1+ USB20_N1_R
+3VS
+3VS +3VALW
USB_0S USB_1S
+5VALW
+3VS
USB_0S USB_0
USB_1S USB_1
CLK_PCI_TPM<5>
USBP0-<22> USBP0+<22>
TPM_LPCPD#<33>
SUS_STAT#<22,35>
USB_OC#0 <22>
USB_OC#1 <22>
PM_CLKRUN#<22,25,27,33,35>
LPC_AD0<21,24,33,35> LPC_AD1<21,24,33,35> LPC_AD2<21,24,33,35> LPC_AD3<21,24,33,35> LPC_FRAME#<21,24,33,35> PLT_RST#<9,18,20,22,24,28,33,35>
SIRQ<22,25,33,35>
USBP1-<22> USBP1+<22>
WAKE_PWR_EN# <33,36>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
TPM/USB Port x2
32 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
*1 = 04Eh(Default)
0 = 02Eh
TPM
USB Port 0
USB Port 1
USB Over Current
Base I/O Address
W=40mils
1A
W=40mils
W=40mils
Required by Motion
for ESD protect
R952
10M_0402_5%
12
C853
0.1U_0402_16V4Z
1
2
C839
0.001U_0402_50V7M
1
2
R858 4.7K_0402_5%
1 2
R14 47_0402_5%
1 2
R15 47_0402_5%
1 2
C332
3.3P_0402_50V8J@
1
2
C691
0.1U_0402_16V4Z
1
2
C842
0.001U_0402_50V7M
1
2
SLB 9635 TT 1.2
U17
SLB 9635 TT 1.2_TSSOP28
NC 1
GPIO2 2
NC 3
GND
4
VSB 5
GPIO 6
PP
7
TEST1 8
TESTB1/BADD 9
VDD 10
GND
11
NC 12
XTALI/32K IN
13
XTALO
14
CLKRUN#
15
LRESET#
16
LAD3
17
GND
18 VDD 19
LAD2
20
LCLK
21
LFRAME#
22
LAD1
23
VDD 24
GND
25
LAD0
26
SERIRQ
27 LPCPD#
28 R854 0_0603_5%
12
R852 0_0603_5%
1 2
R855
0_0402_5%
@
1 2
D27
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
C857
22P_0402_50V8J
@1
2
C329
3.3P_0402_50V8J
@
1
2
C925 18P_0402_50V8J
1 2
C690
4.7U_0805_10V4Z
1
2C28
0.1U_0402_16V4Z
1
2
R850 0_0603_5%
1 2
R849 0_0603_5%
1 2
C926 18P_0402_50V8J
1 2
Y7
32.768KHZ_12.5PF_1TJS125BJ4A421P
OUT
4
IN
1
NC 3
NC 2
R860 4.7K_0402_5%@
1 2
+
C841
150U_D2_6.3VM
1
2
C856
0.1U_0402_16V4Z
1
2
R859
33_0402_5%
@
12
+
C837
150U_D2_6.3VM
1
2
D28
PRTR5V0U2X_SOT143-4
GND 1
IO1 2
IO2
3
VIN
4
L49
FBMA-L11-451616-800LMA10T
1 2
R951
0_0402_5%
12
JP23
SUYIN_020173MR004S583ZL
VCC
1
D-
2
D+
3
GND
4
56
JP22
SUYIN_020173MR004S583ZL
VCC
1
D-
2
D+
3
GND
4
56
R851 0_0603_5%
1 2
U32
TC7SH08FUF_SSOP5
B
1
A
2Y4
P5
G
3
T22
PAD
C855
0.1U_0402_16V4Z
1
2
C929
0.1U_0402_16V4Z
1 2
L50
FBMA-L11-451616-800LMA10T
1 2
C838
0.1U_0402_16V4Z
1
2
C330
3.3P_0402_50V8J@
1
2
T23
PAD
C854
0.1U_0402_16V4Z
1
2
U29
TPS2062DR_SO8~D
GND
1
IN
2
EN1#
3
EN2#
4
OC1# 8
OUT1 7
OUT2 6
OC2# 5
C29
0.1U_0402_16V4Z
1
2
C840
0.1U_0402_16V4Z
1
2
R953
0_0402_5% @
12
C331
3.3P_0402_50V8J
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
WAKE_PWR_EN#
KBRST#
CRY2
BDID0
BDID2
PROCHOT#
BDID1
DOCKEN_VGA
EC_TXD
ADB1
EC_SCI#
ADB0
SMB_EC_DA1
ADB2
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2
KBA0
ADB3
ADB5
ADB4
KBA4
KBA2
KBA3
KBA1
KBA10
KBA5
KBA6
KBA8
KBA9
KBA13
KBA7
CRY2
KBA14
KBA11
KBA12
KBA18
KBA16
ADB6
EC_SMI#
CRY1
SUSP#
BATT_OVP
LPC_FRAME#
PWR_LED#
EC_THRM#
SYSON
ACIN
VR_ON
ON/OFF
CHARGE_LED#
EC_PBTNOUT#
LPC_AD0
WLANOFF#
LPC_AD2
FSEL#
FWR#
CLK_PCI_EC
LPC_AD1
LPC_AD3
ROTA90#
FRD#
ECAGND
FAN_PWM
BATT_TEMP1
IREF
DAC_BRIG
SLP_S5#
PLT_RST#
EC_ON
BATT_LED#
ROTA90#
KSI3
KSI0
KSI1
KSI2
MUTE#
DS_DOCKED_ID
VGATE_INTEL
VCCP_ON#
PWROK
BKOFF#
EC_RSMRST#
KBA17
KBA15
FSTCHG
ADB[0..7]
EC_SWI#
KBA[0..19]
KBA19
ADB7
SLP_S4# FPR_PWRON#
CLK_PCI_EC
SASBTN#
DIGI_RST#
PWR_GD
BATT_TEMP2
PME#
ECRST#
TPM_LPCPD#
LAN_EN#
WL_SW#
BTDIS#
WL_SW#
F_FALL
KSI5
KSI4
KSI6
KSI7
DOCKEN
BDID2
BDID1
EC_EXTTS#0
BDID0
EC_TXD
ECAGND
PM_CLKRUN#
BATT_TEMP1
ECAGNDDS_DOCKED_ID
DS_DOCKED_ID
ECAGND
BATT_OVP ECAGND
DIGISUSP
SMB_EC_DA2
SMB_EC_CK2
SMB_EC_CK1
SMB_EC_DA1
BATSELB_A#
FAN_SPEED1
PDCT
CRY1
BATT_TEMP2 ECAGND
FSEL#
FRD#
SASBTN#
GATEA20
SIRQ
PDCT
TPM_LPCPD#
KSI_USER#
KSI_USER#
ENABLT
BEEP#
PM_BATLOW#_RPM_BATLOW#
HWSPND#
CHGSEL
ACOFF
EC_TXD
MIC_SEL
WWANOFF#
PCM_CLK_EN#
PCM_CLK_EN#
CARD_INSERT#
USB_CLK_EN#
USB_CLK_EN#
SLP_S4#_R
SLP_S3# SLP_S3#_R
SLP_S5#_R
EC_PBTNOUT#_R
EC_RSMRST#_R
MOTION
INVT_PWM
ShutDown#_L ShutDown#
+3VALW
+3VALW
EC_AVCC
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
EC_AVCC+3VALW
+5VALW
+3VALW
+3VALW
+5VALW
+3VS
+3VS
BEEP# <30>
SIRQ<22,25,32,35>
ADB[0..7] <34>
KBA[0..19] <34>
PWROK <9,22,34>
FRD# <34>
FWR# <34>
EC_ON <34>
FSEL# <34>
EC_THRM# <22>
WLANOFF# <24>
FSTCHG <40,41>
VR_ON <37,46>
VGATE_INTEL <22,46>
ROTA90# <36>
PROCHOT# <6>
ACIN <40,42>
ON/OFF <34>
DOCKEN_VGA <19,34>
LPC_AD3<21,24,32,35> LPC_AD2<21,24,32,35> LPC_AD1<21,24,32,35> LPC_AD0<21,24,32,35>
KSI_USER#<36>
SASBTN#<36>
WAKE_PWR_EN#<32,36>
PWR_GD<38>
BATT_TEMP2 <39>
PME#<34>
LAN_EN# <28>
BTDIS#<27>
WL_SW#<24>
SLP_S4#<22>
DOCKEN <29>
DIGISUSP<17>
EC_EXTTS#0<9,15,16>
EC_SCI#<22>
GATEA20<21> KBRST#<21>
LPC_FRAME#<21,24,32,35>
BATSELB_A# <41>PLT_RST#<9,18,20,22,24,28,32,35>
FAN_SPEED1 <6>
CLK_PCI_EC<5>
KSI0<36> KSI1<36> KSI2<36> KSI3<36>
TPM_LPCPD# <32>
SMB_EC_DA2<6,24,36,39> SMB_EC_CK2<6,24,36,39> SMB_EC_DA1<24,34,39> SMB_EC_CK1<24,34,39>
PWR_LED#<17>
CHARGE_LED#<17> BATT_LED#<17> MUTE#<31>
KSI4<36> KSI5<36> KSI6<36> KSI7<36>
SYSON<37,45>
EC_RSMRST#<22,27> BKOFF#<17>
VCCP_ON#<43>
EC_SMI#<22> EC_SWI#<22>
SUSP#<30,37,39>
EC_PBTNOUT#<22>
SLP_S5#<22>
PDCT <17>
BATT_TEMP1 <39>
DS_DOCKED_ID <36>
BATT_OVP <41>
DAC_BRIG <17>
IREF <40>
FAN_PWM <6>
PM_CLKRUN#<22,25,27,32,35>
DIGI_RST#<17>
FPR_PWRON#<36>
ENABLT <11,17>
PM_BATLOW#<22>
HWSPND#<25>
CHGSEL<40>
ACOFF <40>
MIC_SEL <30>
WWANOFF# <24>
PCM_CLK_EN# <25>
CARD_INSERT#<25>
USB_CLK_EN# <27>
SLP_S3#<22>
MOTION<24>
F_FALL<24>
INVT_PWM <17>
ShutDown# <30>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
ENE KB910
33 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BDID2 BDID1 BDID0 Version
000
00
00
0
10
11
0
0
01
0
0
10
101
0.1
0.2
0.3
Rework
0.4
0.4
0.5
1.0
0
DVT1
Phase
EVT1
EVT2
Rework
DVT2
Reserve
DVT2
SSBTN:User button as,
ALT+CTL+Delete
PVT
MP
1
1
1
11
0Reserve
Reserve
C338
0.1U_0402_16V4Z
1
2
C345
15P_0402_50V8J
@
1
2
R297
10K_0402_5%
12
R391
10K_0402_5%
12
R86 0_0402_5%
1 2
R332
10K_0402_5%
12
L43
FBMA-L11-160808-601LMT_200mA_10%
12
R325
10K_0402_5%
12
C336 0.01U_0402_16V7K
1 2
R327
10K_0402_5%
@
12
R326
10K_0402_5%
@
12
R285
0_0603_5%
12
R87 0_0402_5%@
1 2
C344
0.1U_0402_16V4Z
1
2
R2794.7K_0402_5% 12
L44
FBMA-L11-160808-601LMT_200mA_10%
1 2
R82 0_0402_5%
1 2
R380
10K_0402_5%
12
R267
1K_0402_5%
1 2
R293
10K_0402_5%
12
RP22
10K_0804_8P4R_5%
18 27 36 45
R333
10K_0402_5%
12
R281
33_0402_5%
@
1 2
TP3
PAD
R83 0_0402_5%
1 2
C335 0.01U_0402_16V7K
1 2
R276
47K_0402_5%
1 2
Host
PS2 interface
DA output or GPO
SM BUS
PWR
FAN/PWM
INTERFACE
key Matrix
scan
AD INtput or GPI
Address
BUS
Data
BUS
U33
KB910LQF A1_LQFP144~N
LPC AD0/LAD0
12 LPC AD1/LAD1
10 LPC AD2/LAD2
9LPC AD3/LAD3
6
PM_CLKRUN#/ CLKRUN#
44
LPC_FRAME# / LFRAME#
5SERIRQ
3
CLK_PCI_EC/PCICLK
14
BATT LOW LED#/ E51MR0
101
VCC/ EC VCC 11
VCC / EC VCC 26
VCC 127
VCC 141
EC_AVCC / AVCC 75
KSI0/GPIO30
63
KSI1/GPIO31
64
KSI2/GPI032
65
KSI3/GPIO33
66
KSI4/GPIO34
67
KSI5/GPI035
68
KSI6/GPIO36
69
KSI7/GPIO37
70
KSO0/GPIO20
47
KSO1/GPIO21
48
KSO2/GPIO22
49
KSO3/GPIO23
50
KSO4/GPIO24
51
KSO5/GPIO25
52
KSO6/GPIO26
53
KSO7/GPIO27
54
KSO8/GPIO28
55
KSO9/GPIO29
56
KSO10/GPIO2A
57
KSO11/GPIO2B
58
KSO12/GPIO2C
59
KSO13/GPIO2D
60
KSO14/GPIO2E
61
KSO15/GPIO2F
62
KBRST#/GPIO01/KBRST#
2
PM SLP S3#/GPIO04
8BKOFF#/GPIO03
7
PM SLP S05#/ GPIO07
17
PSCLK1 91
PSDAT1 92
PSCLK2 93
PSDAT2 94
PSCLK3 95
PSDAT3 96
LID SW#/ GPIO0A
20
SUSP#/GPIO0B
21
XCLKO
140
XCLKI
138
BATTEMP/AD0/GPIO38 71
BATT OVP/AD1/GPIO39 72
ADP_I/AD2/GPIO3A 73
AD BID0/AD3/GPIO3B 74
DAC_BRIG/DA0/GPIO3D 76
EN DFAN1/DA1/GPIO3D 78
IREF2/DA2 79
EN DFAN2/DA3/ GPIO3F 80
INVT_PWM/GPIO0F/PWM1 25
BEEP#/GPIO10/PWM2 27
GPIO57/GPIO57 137
EC SMC1/GPIO44/SCL1
85
GPIO58/GPIO58 142
GPIO59/GPIO59 143
EC SMC2/GPIO46/SCL2
87 EC SMD2/ GPIO47/SDA2
88
FAN SPEED1/GPIO14/FANFB1 32
FSEL#/SELMEM# 144
FAN SPEED2/GPIO15/FANFB2 33
GND
13
GND
28
GND
39
GND
103
EC RST#/ ECRST#
42
AC IN/ GPIO1C 43
PCMRST#/GPIO1E 45
WL OFF#/GPIO1F 46
PBTN_OUT#/GPIO0C
22
ONOFF/GPIO18 36
FRD#/RD# 135
FWR#/WR# 136
BATT CHGI LED#/ E51CS#
99
CAPS LED#/ E51TMR1
100
EC ON/ GPIO1B 41
ACOFF/GPIO18/PWM4 31
ARROW LED#/ E51 INT0
102
OUT BEEP/GPIO12/PWM3 30
ADB0/D0 125
ADB1/D1 126
ADB2/D2 128
ADB3/ D3 130
ADB4/D4 131
KBA0/A0 111
KBA1/A1 112
KBA2/A2 113
KBA3/A3 114
KBA4/A4 115
KBA13/A13 124
KBA12/A12 123
KBA5/A5 116
KBA6/A6 117
KBA7/A7 118
KBA11/A11 122
KBA10/A10 121
KBA14/A14 110
KBA15/A15 109
KBA16/A16 108
KBA17/A17 107
KBA18/A18 106
KBA19/A19 98
KBA8/A8 119
KBA9/A9 120
GA20/ GPIO00/GA20
1
VCC / EC VCC 37
VCC / EC VCC 105
AGND
77
GND
129 GND
139
PCIRST#
15
EC URXD/KSO16/GPIO48
89
EC UTXD/KSO17/GPIO49
90
ADB5/D5 132
ADB6/D6 133
ADB7/D7 134
EC_RSMRST#/ GPIO02
4
EC LID OUT#/GPIO06
16
EC SMI#/GPIO08
18
EC SWI#/GPIO09
19
EC PME#/GPIO0D
23
ECTHERM#/GPIO11 29
SYSON/GPIO56/ E51 INT1
104
ALI/MH#/GPIO40 81
FSTCHG/GPIO41 82
VR ON/ GPIO42 83
SELIO2#/ GPIO43 84
EC SMD1/GPIO44/SDA1
86
SELIO#/ GPIO50 97
PWRLED#/ GPIO19
38
PCM_SPK#/EMAIL_LED#/ GPIO16
34
SB_SPKR/PWR_SUSP_LED#/ GPIO17
35
NUMLED#/ GPIO1A
40
EC SCI#/SCI#/GPIO0E
24
R2804.7K_0402_5% 12
C340
1000P_0402_50V7K
1
2
R2774.7K_0402_5% 12
R295
10K_0402_5%
12
C334 0.01U_0402_16V7K
1 2
C339
0.1U_0402_16V4Z
1
2
R157
1K_0402_5%
1 2
R84 0_0402_5%
1 2
R298
10K_0402_5%
@
12
C337
0.1U_0402_16V4Z
1
2
JP24
ACES_85201-0405
@
1
2
3
4
R2784.7K_0402_5% 12
R270 4.7K_0402_5%
1 2
C347
10P_0402_50V8J
12
R299
10K_0402_5%
12
R85 0_0402_5%
1 2
C346
10P_0402_50V8J
12
R286
20M_0603_5%@
12
Y3
32.768K +-10PPM Q13MC20610009
OUT 4
IN 1
NC
3
NC
2
C341
0.1U_0402_16V4Z
1
2
C342
1000P_0402_50V7K
1
2
C348 0.01U_0402_16V7K
1 2
R70
1K_0402_5%
@
1 2
R88
0_0402_5%
2@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EC_ON#
EC_ON ECON
ON/OFFBTN# ON/OFF
EC_FLASH# EC_FLASH_T#
PWROK
PCIPME#
FWE#
FWR#
ADB2
KBA1
ADB7
ADB0
ADB6
ADB1
KBA10
FRD#
ADB5
KBA2
KBA3
FSEL#
ADB4
ADB3
KBA0
KBA6
KBA12
KBA8
FWE#
KBA19
ADB[0..7]
KBA[0..19]
KBA4
KBA18
KBA5
KBA13
KBA7
KBA17
KBA16
KBA15
KBA11
KBA14
KBA9
BIOS_RST#
DOCKEN_VGA
DOCK_USB_OC#3
KBA12
KBA16
KBA13
KBA11
KBA14
KBA15
KBA8
KBA9
FWE#
BIOS_RST#
KBA18
KBA7
KBA2
KBA6
KBA3
KBA5
KBA4
KBA1 KBA0
FSEL#
FRD#
ADB7
ADB0
ADB2
ADB1
ADB6
ADB3
ADB4
ADB5
KBA10
KBA19
KBA17
ON/OFFBTN#
USB_OC#6
USB_OC#4
DOCK_USB_OC#2
DOCKEN_VGA#
USB_OC#7
DOCK_USB_OC#4
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
EC_ON<33>
ON/OFF <33>
EC_ON# <44>
PWROK<9,22,33>
EC_FLASH#<22>
PCI_PME# <20>PME#<33>
FWR#<33>
SMB_EC_DA1<24,33,39> SMB_EC_CK1<24,33,39>
DOCKEN_VGA<19,33>
DOCK_USB_OC#3<36>
DOCK_USB_OC#2<36>
DOCK_USB_OC#4<36>
USB_OC#6 <22>
USB_OC#4 <22>
FRD#<33> FSEL#<33>
ADB[0..7]<33>
KBA[0..19]<33>
USB_OC#7 <22>
USB_PME#<27>
PCM_PME#<25>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
EC Extend I/O&BIOS
34 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V
Power BTN
EC I2C Bus Address:
NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#
24C164: 1011xxx R/W#
24C16: 1010xxx R/W#
BIOS/B Conn
C875
0.1U_0402_16V4Z
1 2
C883
0.1U_0402_16V4Z
1
2
D23
DAN202U_SC70
2
3
1
R905
100K_0402_5%
1 2
R900 100_0402_5%
1 2
D36
PSOT24C-LF_T7_SOT23-3
2
3
1
R897 100_0402_5%
1 2
R909
10K_0402_5%
1 2
C876
1000P_0402_50V7K
1
2
C881
0.1U_0402_16V4Z
1
2
SW1
HSS111_4P
1 2
U37
TC7SH32FU_SSOP5
I0
2
I1
1O4
G
3P5
C882
10U_0805_10V4Z
1
2
JP25
ACES_88072-4071_40P
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
R907
10K_0402_5%
1 2
R906 0_0402_5%@1 2
R899
0_0402_5%
1 2
R912
10K_0402_5%
1 2
G
D
S
Q21
2N7002_SOT23
2
13
R901
22K_0402_5%
12
U38A TC74LCX32FTF_TSSOP14
A
1
B
2O3
P14
G
7
U39
SST39VF080-70-4C-EIE_TSOP40~N
@
A0
21
A1
20
A2
19
A3
18
A4
17
A5
16
A6
15
A7
14
A8
8
A9
7
A10
36
A11
6
A12
5
A13
4
A14
3
A15
2
A16
1
A18
13
CE#
22
OE#
24
D0 25
D1 26
D2 27
D3 28
D4 32
D5 33
D6 34
D7 35
GND1 39
A17
40
WE#
9
VCC1 30
VCC0 31
GND0 23
A19
37
NC0 29
NC1 38
NC 11
RP# 10
READY/BUSY# 12
R895
10K_0402_5%
@
12
D24
RLZ20A TE-11_LL34
12
R894
100K_0402_5%
12
C880
0.1U_0402_16V4Z
1
2
R910
10K_0402_5%
1 2
U38B TC74LCX32FTF_TSSOP14
A
4
B
5O6
P14
G
7
C879
0.1U_0402_16V4Z
1
2
U38C TC74LCX32FTF_TSSOP14
A
9
B
10 O8
P14
G
7
R921 100_0402_5%
1 2
22K
22K
Q19
DTC124EKAT146_SOT23
2
13
G
D
S
Q23
2N7002_SOT23
2
13
R908
10K_0402_5%
1 2
R896
100K_0402_5%
12
U38D TC74LCX32FTF_TSSOP14
A
12
B
13 O11
P14
G
7
R904
22K_0402_5%
1 2
U34
AT24C16AN-10SU-2.7_SO8~N
A0 1
A1 2
SDA
5SCL
6
VCC
8
A2 3
GND 4
WP
7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPC_FRAME#
LPC_AD0
LPC_AD2
LPC_AD1
LPC_AD3
LPC_DRQ#0
PM_CLKRUN#
SIRQ
CLK_14M_SIO
CLK_PCI_SIO
PLT_RST# PLT_RST_R#
RXDB#
TXDB
LPC47N217_SYSOPT
CLK_PCI_SIOCLK_14M_SIO IRTXOUT
IRMODE
IRRX
DTRB#
CTSB#
+IR_3VS
IRTXOUT
IRRX IRMODE
CLK_14M_SIO
CLK_PCI_SIO
LPC_AD0
PLT_RST#
LPC_AD3
LPC_FRAME#
LPC_AD2
LPC_DRQ#0
LPC_AD1
SIRQ
SUS_STAT#
IRRX
+3VS
+3VALW
+3VS
+3VS
+IR_ANODE
+3VS
+5VS
+3VS
+3VS
LPC_AD0<21,24,32,33> LPC_AD1<21,24,32,33> LPC_AD2<21,24,32,33> LPC_AD3<21,24,32,33>
CLK_14M_SIO<5>
CLK_PCI_SIO<5>
SUS_STAT#<22,32>
PLT_RST#<9,18,20,22,24,28,32,33>
LPC_FRAME#<21,24,32,33> LPC_DRQ#0<21>
SIRQ<22,25,32,33>
TXDB <17>
RXDB# <17>
DTRB# <17>
CTSB# <17>
PM_CLKRUN#<22,25,27,32,33>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
SMSC LPC47N217/FIR
35 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Strap pin Pin # Description
BADDR 33 BASE Address Selection
"0": 2E~2F (Default)
"1": 4E~4F
(60mil)
(60mil)
(30mil)
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT
PCB Footprint : TFDU6101E
FIR
FOR LPC SIO DEBUG PORT
Place the debug port under MINI card
R920
47_1206_5%
12
C888
4.7U_0805_10V4Z
1
2
R294 0_0603_5%
3220@ 12
R967
10K_0402_5%
@
1 2
C886
0.1U_0402_16V4Z
1
2
C507
0.47U_0603_10V7K
@
1
2
C892
10U_0805_10V4Z
@
1
2
R916
33_0402_5%
@
12
R3
4.7_1206_5%
1 2
R283
47K_0402_5%
@
1 2
JP26
ACES_85201-2005@
11
22
33
44
55
66
77
88
99
10 10
11 11
12 12
13 13
14 14
16 16
17 17
18 18
15 15
20 20
19 19
C889
22P_0402_50V8J
@1
2
R969
10K_0402_5%
@
1 2
C893
10U_0805_10V4Z
1
2
C885
0.1U_0402_16V4Z
1
2
R915
33_0402_5%
@
12
U41
HSDL-3220_8P
IRED_C
2
GND
8MODE 7
SD/MODE 5
IRED_A 1
RXD
4
VCC
6
TXD 3
C890
22P_0402_50V8J
@1
2
R914 22_0402_5%
1 2
R918
4.7_0603_5%
@
1 2
C894
0.1U_0402_16V4Z
1
2
POWER
CLOCK
GPIO
LPC I/F
SERIAL I/F
FIR
PARALLEL I/F
U40
LPC47N217-JV_STQFP64
LAD0
10
LAD1
12
LAD2
13
LAD3
14
LFRAME#
15
LDRQ#
16
PCI_RESET#
17
LPCPD#
18
CLKRUN#
19
PCI_CLK
20
SER_IRQ
21
IO_PME#
6
RXD1 62
TXD1 63
DSR1# 64
RTS1# 1
CTS1# 2
DTR1# 3
RI1# 4
DCD1# 5
IRRX2 37
IRTX2 38
IRMODE/IRRX3 39
INIT# 41
SLCTIN# 42
PD0 44
PD1 46
PD2 47
PD3 48
PD4 49
PD5 50
PD6 51
PD7 53
SLCT 55
PE 56
BUSY 57
ACK# 58
ERROR# 59
ALF# 60
STROBE# 61
GPIO40
23
GPIO41
24
GPIO42
25
GPIO43
27
GPIO44
28
GPIO45
29
GPIO46
30
GPIO47
31
GPIO10
32
GPIO11/SYSOPT
33
GPIO12/IO_SMI#
34
GPIO13/IRQIN1
35
GPIO14/IRQIN2
36
GPIO23
40
CLK14
9
VTR 7
VCC 26
VCC 54
VSS
8
VSS
22
VSS
43
VSS
52 VCC 45
VCC 11
R917
4.7K_0402_5%
12
C891
22U_1206_10V4Z
1
2
C887
1000P_0402_50V7K
1
2
R919 4.7_0603_5%
@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KSI3
KSI4
KSI2
KSI5
KSI0
KSI1
KSI7
KSI6
KSI_USER#
VDDA
GNDA
INT_MIC2 INTMIC2
HP_PLUG# D_HP_OUT_L
D_HP_OUT_R
HP_OUT_L
HP_OUT_R
DOCK_LAN_TX-
DOCK_LAN_RX+
DOCK_LAN_RX-
DOCK_LAN_RX3+
DOCK_LAN_TX+
DOCK_LAN_RX3-
DOCK_LAN_TX2-
DOCK_LAN_TX2+ DOCKC_IN
USBP6-
USBP6+
USBP7+
USBP4-
USBP4+
USBP5+
USBP5-
DOCK_LAN_LINK#
DOCK_LAN_ACT#
DOCK_USB_OC#2
DOCK_USB_OC#4
DOCK_USB_OC#3
USBP7- GNDA
DS_DOCKED_ID
DIS_INTMIC
CRT_VSYNC_DOCK
CRT_HSYNC_DOCK
CRT_R_DOCKCRT_R_DOCKC
CRT_G_DOCKCRT_G_DOCKC
CRT_B_DOCK
3VDDCDA_R
3VDDCCL_R
M_SEN#
D_DOCK_MIC DOCK_MIC
DIS_INTMIC
ROTA90#
CRT_B_DOCKC
WAKE_PWR_EN#
SMB_EC_CK2
SMB_EC_DA2
INTMIC1
GNDA
USBP3-
SASBTN#
GNDA
USBP3+
SMB_EC_DA2_ALS
SMB_EC_CK2_ALS
+5V_DOCK
+3VS
DOCK_IN
+5V_DOCK
+3VALW
+2.5V_LAN
VDDA
+5VALW +5V_DOCK
+5VALW
+3VS
+3VS
+3VS
+3VS
VDDA
+3VS
INT_MIC2<30>
KSI0<33> KSI1<33> KSI2<33> KSI3<33> KSI4<33> KSI5<33> KSI6<33> KSI7<33> KSI_USER#<33>
HP_PLUG#<30,31>
HP_OUT_R<30> HP_OUT_L<30>
DOCK_LAN_TX+<29> DOCK_LAN_TX-<29>
DOCK_LAN_RX+<29> DOCK_LAN_RX-<29>
DOCK_LAN_RX3+<29> DOCK_LAN_RX3-<29>
DOCK_LAN_TX2+<29> DOCK_LAN_TX2-<29>
DOCK_LAN_LINK#<29> DOCK_LAN_ACT#<29>
DOCK_USB_OC#2<34> DOCK_USB_OC#3<34> DOCK_USB_OC#4<34>
GNDA <30,31>
DS_DOCKED_ID<33>
DIS_INTMIC <30>
CRT_HSYNC_DOCK <19>
CRT_VSYNC_DOCK <19>
CRT_R_DOCK <19>
CRT_G_DOCK <19>
CRT_B_DOCK <19>
3VDDCCL_R <19>
3VDDCDA_R <19>
M_SEN# <19,22>
DOCK_MIC <30>
ROTA90# <33>
WAKE_PWR_EN#<32,33>
USBP4-<22> USBP4+<22>
USBP6+<22> USBP6-<22>
USBP7+<22> USBP7-<22>
USBP3-<22> USBP3+<22>
FPR_PWRON#<33>
SASBTN#<33>
USBP5+<22> USBP5-<22>
INT_MIC1<30>
GNDA<30,31>
SMB_EC_DA2<6,24,33,39>
SMB_EC_CK2<6,24,33,39>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Docking Conn /FingerPrinter /Button board Conn
36 53Monday, January 08, 2007
To BTN Board
ALS/MIC & Finger Print combine CONN
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DOCKING BD.
19vdc_2.25A
Need to update the Symbol
Reserved for EMI
To support wake up from Docking.
L45
FBM-11-160808-700T_0603
1 2
R300 0_0603_5%
1 2
L46
FBM-11-160808-700T_0603
1 2
C930
0.47U_0603_16V7K
1
2
C896
4.7U_0603_6.3V6M
@
1
2
R964
330K_0402_5%
1 2
R731
4.7K_0402_5%
12
R301 0_0603_5%
1 2
C899
0.1U_0402_16V4Z
1
2
C902
0.1U_0402_16V4Z
1
2
R922 0_0402_5%
12
C897
0.1U_0402_10V6K
1
2
G
D
S
Q70
2N7002_SOT23
2
1 3
D37
PSOT24C-LF_T7_SOT23-3
2
3
1
C900
0.1U_0402_16V4Z
1
2
C904
0.22U_0603_10V7K
1 2
R965 22K_0402_5%
1 2
JP34
ACES_85201-1205
1
2
3
4
5
6
7
8
9
10
11
12
G
D
S
Q72
2N7002_SOT23
2
1 3
R292 0_0603_5%
1 2
R732
4.7K_0402_5%
12
L20
HCB4532KF-800T90_1812
12
R302 0_0603_5%
1 2
C898
0.1U_0805_25V7M
1
2
R296 0_0603_5%
1 2
C901
0.1U_0402_16V4Z
1
2
G
D
S
Q25
AO3413_SOT23
2
13
C895
0.22U_0603_10V7K
1 2
R923
5.1K_0402_5%
1 2
C903
0.1U_0805_25V7M
1
2
G
D
S
Q63
AO3413_SOT23
2
13
R303 0_0603_5%
12
JP30
ACES_87151-2205
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
JP27
ACES_88363-08001
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41 41
42 42
43 43
44 44
45 45
46 46
47 47
48 48
49 49
50 50
51 51
52 52
53 53
54 54
55 55
56 56
57 57
58 58
59 59
60 60
61 61
62 62
63 63
64 64
65 65
66 66
67 67
68 68
69 69
70 70
71 71
72 72
73 73
74 74
75 75
76 76
77 77
78 78
79 79
80 80
R970
22K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VR_ON#
VR_ON
VR_ON#
SYSON
SUSP
SYSON#
SUSP
SUSP
SUSP
SUSP SUSP SUSP SUSP
SUSP
SUSP
SYSON#
SUSP
VR_ON#
+5VALW
+5VALW
+5VS+5VALW
+3VALW +3VS
+3VALW
+VCC_CORE +VCCP
+1.8V +1.8VS
+12VALW
+12VALW
+12VALW
+5VS +3VS +2.5VS +1.8VS +1.5VS +0.9VS
+1.8V
+5VALW
SUSP<43>
SUSP#<30,33,39>
SUSP#P <43,45>
VR_ON<33,46>
SYSON<33,45>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
DC-DC interface
37 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+1.8V to +1.8VS Transfer
+5VALW to +5VS Transfer
+3VALW to +3VS Transfer
C908
10U_1206_6.3V7K
1
2
G
D
S
Q30
2N7002_SOT23
@
2
13
G
D
S
Q38
2N7002_SOT23
2
13
G
D
S
Q29
2N7002_SOT23
@
2
13
R940
100K_0402_5%
12
C914
0.1U_0402_16V4Z
1
2
C905
10U_0805_10V4Z
1
2
C906
0.1U_0402_16V4Z
1
2
R932
470_0402_5%
@
12
R933
330_0402_5%@
12
R926
470_0402_5%
@
12
G
D
S
Q35
2N7002_SOT23
@
2
13
G
D
S
Q41
2N7002_SOT23
@
2
13
R938 47K_0402_5%
1 2
C920
0.1U_0402_16V4Z
1
2
G
D
S
Q40
2N7002_SOT23
2
13
G
D
S
Q42
2N7002_SOT23
2
13
G
D
S
Q37
2N7002_SOT23
2
13
G
D
S
Q34
2N7002_SOT23
@
2
13
C918
10U_1206_6.3V7K
1
2
+
C907
100U_D2_6.3VM
1
2
C909
0.1U_0402_16V4Z
1
2
C916
10U_0805_10V4Z
1
2
R935
10K_0402_5%
12
C911
0.1U_0402_16V4Z
1
2
R929
470_0402_5%
@
12
U44
AO4468_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C915
0.1U_0402_16V4Z
1
2
G
D
S
Q32
2N7002_SOT23
@
2
13
U43
AO4468_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
G
D
S
Q28
2N7002_SOT23
@
2
13
G
D
S
Q33
2N7002_SOT23
2
13
R927
470_0402_5%
@
12
G
D
S
Q27
2N7002_SOT23
2
13
G
D
S
Q36
2N7002_SOT23
@
2
13
G
D
S
Q39
2N7002_SOT23
2
13
R930
470_0402_5%
@
12
R937 56K_0402_5%
1 2
R936
10K_0402_5%
12
+
C917
100U_D2_6.3VM
1
2
C913
10U_1206_6.3V7K
1
2
R934
330_0402_5%
@
12
R928
470_0402_5%
@
12
R939
100K_0402_5%@
1 2
C910
10U_0805_10V4Z
1
2
U42
AO4468_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
G
D
S
Q31
2N7002_SOT23
@
2
13
C919
0.1U_0402_16V4Z
1
2
+
C912
100U_D2_6.3VM
1
2
R925
470_0402_5%
12
R931 100K_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR_GD
+1.5VS +2.5VS+2.5VS
+5VS
+3VS
+3VS+3VS
+1.8VS +3VALW +3VALW
+3VALW
+3VALW
VCCP_POK<43>
PWR_GD <33>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
POWER OK CKT
38 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R950
330_0402_5%
1 2
CF13
1
C922
0.1U_0402_16V4Z
1
2
H51
HOLEE
1
CF11
1
FD6
1
FD3
1
R944
47K_0402_5%
1 2
H21
HOLEA
1
U45B
74LVC14APW_TSSOP14
O4
I
3
P14
G
7
CF14
1
J6
NO SHORT 2x2m
2 1
CLIP1
Antenna_CLIP
1
H20
HOLEA
1
H13
HOLEB
1
H8
HOLEA
1
H25
HOLEC
1
U45A
74LVC14APW_TSSOP14
O2
I
1
P14
G
7
H14
HOLEA
1
H22
HOLED
1
CF6
1
H11
HOLEB
1
R943
330_0402_5%
1 2
CF1
1
H1
HOLEE
1
CF8
1
H2
HOLEA
1
R942
330_0402_5%
1 2
H7
HOLEB
1
R941
1K_0402_5%
1 2
FD2
1
Q43
MMBT3904_NL_SOT23
2
3 1
CF9
1
H3
HOLED
1
R946
180K_0402_5%
12
H12
HOLEA
1
R947
560K_0402_5%
12
H29
HOLEE
1
H10
HOLED
1
CF2
1
D25
RB751V_SOD323
21
R948
10K_0402_5%
1 2
CF10
1
Q48
MMBT3904_NL_SOT23
2
3 1
R949
330_0402_5%
1 2
H18
HOLEA
1
C921
0.1U_0402_16V4Z
1
2
H19
HOLED
1
H9
HOLEA
1
H27
HOLEA
1
CF5
1
U45C
74LVC14APW_TSSOP14
O6
I
5
P14
G
7
CF4
1
Q47
MMBT3904_NL_SOT23
2
3 1
U45D
74LVC14APW_TSSOP14
O8
I
9
P14
G
7
CF7
1
FD5
1
H4
HOLEA
1
H5
HOLEA
1
G
D
S
Q46
2N7002_SOT23
2
13
FD4
1
H17
HOLEA
1
H15
HOLEB
1
C923
0.1U_0402_16V4Z
1
2
FD1
1
Q44
MMBT3904_NL_SOT23
2
3 1
R945
10K_0402_5%
12
H16
HOLEA
1
H6
HOLEA
1
G
D
S
Q45
2N7002_SOT23
2
13
CF12
1
H26
HOLEA
1
CF3
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BATT_TEMP1
BATT_A+
BATT_TEMP2
BATT_B+
P1
SUSP#
SPOK
P1
BATT_A+
BATT_A
+3VALW
BATT_B+
BATT_B
+3VALW
+12VALW
VSB
B+
VIN
DOCK_IN
PACIN
SPOK<42>
SUSP#<30,33,37>
BATT_TEMP2 <33>
SMB_EC_DA2 <6,24,33,36>
SMB_EC_CK2 <6,24,33,36>
BATT_TEMP1 <33>
SMB_EC_DA1 <24,33,34>
SMB_EC_CK1 <24,33,34>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
PWR-Vin/bridge Batt/RTC
39 53Monday, January 08, 2007
SMART
Battery:
1.BAT+
2.ID
3.B/I
4.TS
5.SMD
6.SMC
7.GND
PJP1 battery connector
SMART
Battery:
1.BAT+
2.ID
3.B/I
4.TS
5.SMD
6.SMC
7.GND
PJP2 battery connector
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PR11
43.2K_0402_1%
12
PR13
57.6K_0402_1%
1 2
PD26
B540C_SMC
2 1
PJPC1
MOLEX_53780-0290
1
2
PC9
0.1U_0603_25V7K
1 2
PR21
100K_0402_5%
12
PD27
B540C_SMC
2 1
PJP2
SUYIN_250263MR007G107ZL
1
2
3
4
5
6
7
PR1
10_1206_5%
12
PQ5
DTC115EUA_SC70
2
13
PR6
100_0402_5%
1 2
PR34
3.4K_0402_1%
1 2
E
B
C
PQ1
2SA1037AK_SC59
2
31
PL1
FBMA-L18-453215-900LMA90T_1812
1 2
PL2
FBMA-L18-453215-900LMA90T_1812
1 2
PC1
0.01U_0402_25V7K
12
PC6
560P_0402_50V7K
12
PH1
100K_0603_1%_TH11-4H104FT
12
PR20
100_0402_5%
1 2
PR15
100K_0402_5%
1 2
PR3
1K_0402_5%
12
PL3
FBMA-L18-453215-900LMA90T_1812
1 2
PR12
40.2K_0402_1%
12
PR17
6.49K_0402_1%
1 2
PC4
12P_0402_50V8J
12
PR4
6.49K_0402_1%
1 2
PJP1
SUYIN_250263MR007G110ZR
11
22
33
44
55
66
77
PD3
1SS355TE-17_SOD323-2
1 2
PR10
3.92K_0402_1%
1 2
PC8
1000P_0402_50V7K
12
PD2
DAN217_SC59
2
31
G
D
S
PQ4
IRLML5103_SOT23
2
13
G
D
S
PQ7
RHU002N06_SOT323
2
13
PC3
560P_0402_50V7K
12
PD4
RB160L-40_SOD106
12
PR9
442_0402_1%
1 2
PD1
RLZ24B_LL34
12
PR2
1K_0402_5%
1 2
G
D
S
PQ3
RHU002N06_SOT323
2
13
PR18 100_0402_5%
1 2
PC2
1000P_0402_50V7K
12
PQ6
DTC115EUA_SC70
2
13
PC5
12P_0402_50V8J
12
PR5 100_0402_5%
1 2
PC7
0.01U_0402_25V7K
12
PR19
10K_0402_5%
12
PR16
1K_0402_5%
12
1
2
G
G3
PJPD1
SINGA_2DC-S028B200
1
2
5
43
PR7
22.1K_0402_1%
1 2
PR8
22.1K_0402_1%
1 2
PR14
1K_0402_5%
1 2
C
B
E
PQ2
2SC2412K_SC59
1
2
3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCTL
LX
PACIN
ACOFF#
ACOFF#
ICTL
VCTL
ICTL
CSIP
DLO
PACIN
BATT+
CCI
REF_MAX1908 DHI
BST
1908LDO
+12VALW
VIN
P2
1908LDO
BATT+
MAX1908-CCS
P3
1908LDO
B+
1908LDO
VIN
VIN
VIN
PACIN
PACIN
CHGSEL<33>
ACON<44>
ACOFF
<33>
FSTCHG<33,41>
ACIN<33,42>
IREF <33>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
PWR-Changer MAX1908ETI
40 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
4S CC-CV MODE : 17.4V for 2800mAH Battery
Charge voltage
Iadp=0~2.38A(45.23W)
Charger
CC-CV
Pulse charge.
Charge mode
1908LDO.
Change voltage.VCTL
PR163=160K
PR163=0,PR164=@
Note.
17.0V
16.8V
2.0769V PR164=100K
Vin Detector(Detector Point:pin10 of PU1)
typ.
H-->L V 16.98V V
L-->H V 17.85V V
4S CC-CV MODE : 16.8V for 2600mAH,2400mAH Battery
PR43
0_0402_5%
1 2
PR33
100K_0402_1%
12
PR41
100K_0402_1%
12
PC22
4.7U_1206_25V6K
12
PR186 0_0402_5%
12
PC20
4.7U_1206_25V6K
12
PR163
84.5K_0402_1%
12
PQ17
DTC115EUA_SC70
2
13
PR262
100K_0402_1%
12
PR45
10K_0402_5%
1 2
PC25
1U_0805_25V4Z
1 2
PC16
0.1U_0603_25V7K
12
PR37
100K_0402_1%
12
47K
47K
PQ11
DTA144EUA_SC70
2
1 3
PR155
10K_0402_1%
1 2
PR35
0_0402_5%
12
PC17
1U_0603_10V6K
12
PR39
10K_0402_1%
1 2
PQ10
AO4407_SO8
3 6
5
7
8
2
4
1
PL5
16UH_D104C-919AS-160M_3.7A_20%
1 2
PR42
158K_0603_1% @
12
PQ9
AO4407_SO8
3 6
5
7
8
2
4
1
PR38
22K_0402_5%
1 2
PC24
1U_0603_10V6K
1 2
PR24
200K_0402_1%
12
PC26
0.001U_0402_50V7M
12
PD29
RLZ4.3B_LL34
12
PC14
0.1U_0603_25V7K@
12
PC12
10U_1206_25V6M
1
2
PC28
0.1U_0402_16V7K
12
G
D
S
PQ16
RHU002N06_SOT323
2
13
PL4
FBMA-L18-453215-900LMA90T_1812
1 2
PC11
10U_1206_25V6M
1
2
PR23
47K_0402_5%
12
G
D
S
PQ49
RHU002N06_SOT323
2
13
PR28
0_0402_5%
12
PR44
100K_0402_5%
1 2
PC29
0.1U_0402_16V7K
12
PC10
10U_1206_25V6M
1
2
PQ8
AO4407_SO8
36
5
7
82
4
1
PC18
0.1U_0402_16V7K
12
PQ12
DTC115EUA_SC70
2
13
PR31
9.31K_0402_1%
12
AO4916_SO8
PQ15
D2 2
G2
8
G1 3
D1/S2/K
5
D2 1
D1/S2/K
7
S1/A 4
D1/S2/K
6
PQ51
DTC115EUA_SC70
2
13
PR32
15K_0402_1%
1 2
PD7
1SS355_SOD323
12
PC15
0.1U_0603_25V7K
12
10K
10K
PQ13
DTC114EKA_SC59
2
13
PR26
10K_0402_5%
1 2
PD5
RLZ22B_LL34@
12
PR47
681K_0402_1%
1 2
PR184
100K_0402_1%
12
PR30
0.015_2512_1%
1
3
4
2
PC23
0.01U_0402_16V7K
12
PR40
10K_0402_5%
12
PR46
150K_0402_1%
12
G
D
S
PQ14
RHU002N06_SOT323
2
13
PR27
150K_0402_5%
12
PR22
0.01_2512_1%
1
3
4
2
PR36
33_1206_5%
12
PC19
0.1U_0603_25V7K
1 2
PD6
1SS355_SOD323 @
1 2
PR164
100K_0402_1%
12
PD10
1SS355_SOD323
1 2
PR48
20K_0402_1%
12
PR29
215K_0402_1%
12
PR25
47K_0402_5%
1 2
PC21
4.7U_1206_25V6K
12
PU1
MAX1908ETI+T_QFN28
CCI
6
VCTL
15
ICTL
13
CLS
3
REF
4
CELLS
17
REFIN
12
ACIN
10
ACOK#
11
SHDN#
8
IINP
28
DCIN
1
CCS
5
CCV
7
ICHG
9
BATT 16
CSSP 27
PGND
20
DLOV 22
CSSN 26
LDO 2
BST 24
DHI 25
DLO 21
CSIP 19
LX 23
CSIN 18
GND
14
TP 29
PC13
0.1U_0603_25V7K@
12
PC27
0.001U_0402_50V7M
12
PD8
1SS355_SOD323
1 2
PD9
1SS355_SOD323
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1538VDD
1538VDD
1538VCC
BATT+
VS
BATT+
VS
BATT_B BATT_A
PACIN VL
RTCVREF
1908LDO
PACIN
VIN
VS
BATSELB_A# <33>
FSTCHG <33,40>
BATT_OVP<33>
BATT_UVM <44>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
PWR-Batt Select & OVP
41 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
OVP voltage :
LI-4S :17.8V----BATT-OVP=1.9758V(4.2V CELL)
BATT-OVP=0.111*BATT+
LI-4S :18V-----BATT-OVP=1.998V(4.35V CELL)
PC35
0.01U_0402_25V7Z
12
PR101
2K_0402_5%
1 2
FDS4935_SO8
PQ18
G2 2
D2
8
S1 3
D1
5
S2 1
D2
7
G1 4
D1
6
FDS4935_SO8
PQ19
G2
2D2 8
S1
3
D1 5
S2
1
D2 7
G1
4D1 6
PR57
100K_0402_5%
1 2
PR51
100K_0402_1%
1 2
PR60
845K_0603_1%
12
PR54
0_0402_5%
1 2
PD31
1SS355TE-17_SOD323-2
1 2
PU3A
LM358DT_SO8
+3
-2
0
1
P8
G
4
PR56
100K_0402_5%
1 2
PC30
1U_0805_25V4Z
12
PR49
309K_0402_1%
1 2
PC120
0.01U_0402_16V7K
12
PC122
0.01U_0402_16V7K
12
PR52
0_0402_5%@
1 2
G
D
S
PQ25
RHU002N06_SOT323
2
13
PC32
1U_0603_10V6K
12
PR58
66.5K_0402_1%
NA
12
PR160
10K_0402_1%
12
PC31
1U_0805_25V4Z
12
PR55
100K_0402_5%
1 2
PR53
0_0402_5%
1 2
PR165
10K_0402_1%
1 2
PR91
3K_0402_5%
1 2
PR166
10K_0402_1%
1 2
G
D
S
PQ26
RHU002N06_SOT323
2
13
PU3B
LM358DT_SO8
+5
-6
0
7
P8
G
4
PR61
300K_0603_0.1%
12
PR62
143K_0402_1%
12
PC121
0.1U_0402_16V7K
12
PR93
2K_0402_5%
1 2
PC36
0.01U_0402_25V7Z
12
PR59
100K_0402_1%
1 2
PU2
MAX1538ETI+T_QFN28
MINVA
1
ADPBLK
14
CHGIN
17
REVBLK
13
ADPPWR
12
ADPIN
11
EXTLD
16
DISB
23
CHGA
19
CHGB
20
BATB
22
AIRDET 10
NC2 21
BATA
25
DISA
24
NC1 15
ACDET 9
RELRN 4
DISBAT
18
BATSEL 3
GND
27
BATSUP 26
OUT1 7
OUT0 6
VDD 28
OUT2 8
CHRG 5
MINVB
2
TP
29
PR167
0_0402_5%
1 2
PD30
1SS355TE-17_SOD323-2
1 2
PC33
0.047U_0603_50V7K
@
1 2
PU7A
LM393DG_SO8
+
3
-
2O1
P8
G
4
PC34
0.047U_0603_50V7K
@
1 2
PR92
3K_0402_5%
1 2
PR50
412K_0603_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FLYBACKSNB
VDD_MAX1902
BST51
DH3
LX3
DL3
DL5
BST31
FB5
ACIN
FB3
DH5
BST5
LX5
VS
B+++
B+++
VS
+3VALWP
B+
2.5VREF
+12VALWP
VL
+5VALWP
SPOK <39>
MAINPWRON <44>
ACIN<33,40>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
PWR-+3.3V/5V/12V
42 53Monday, January 08, 2007
Change from 2.2U to 10U for S3 noise issue
OCP Min.= 80mV/1.27K*(2.8K+1.27K)/37=6.929A
Current limit Threshold Min.=80 mV Mx.=120mV.
+3VALWP Choke DCR = 37m .
L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56)
RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3)
OCP Max.=120mV/1.27K*(2.8K+1.27K)/37=10.394A
OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A
Current limit Threshold Min.=80 mV Mx.=120mV.
+5VALWP Choke DCR = 40m .
OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A
+3.3V/+5V/+12V
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PR193
2.7K_1206_5%
@
12
PR122
0_0402_5%
12
PD12
CHP202UPT_SOT323-3
2
3
1
PD15
SKUL30-02AT_SMA
2 1
PR69
1M_0402_1%
1 2
PR74
698_0402_1%
12
PL8
4.7UH_PCMC063T-4R7MN_5.5A_20%
1 2
PR63
22_1206_5%@
12
PR70
2M_0402_1%
12
PR75
300K_0402_5% @
12
PR76
3.57K_0402_1%
1 2
+
PC53
150U_D2E_6.3VM_R18
1
2
PC54
1000P_0402_50V7K
12
AO4916_SO8
PQ20
D2
2G2 8
G1
3
D1/S2/K 5
D2
1
D1/S2/K 7
S1/A
4D1/S2/K 6
PU4
MAX1902EAI+T_SSOP28
LX3
26
DL3
24
BST3
25
DH3
27
CSH3
1
CSL3
2
FB3
3
SKIP#
10
GND
8
12OUT 4
VDD 5
BST5 18
DH5 16
LX5 17
DL5 19
PGND 20
CSH5 14
CSL5 13
FB5 12
SEQ 15
REF 9
SYNC 6
RESET# 11
SHDN#
23
TIME/ON5
7
RUN/ON3
28
VL 21
V+ 22
PR81
10K_0402_1%
12
PC47
47P_0402_50V8J
12
PD16
SKS10-04AT_TSMA
2 1
PC44
2200P_0402_50V7K
@
12
PL7
9UH_SDT-1204P-9R0-120 GP_4.5A_20%
1 4
3 2
PC40
0.1U_0603_25V7K
1 2
PR71
1.54K_0402_1%
12
PR79
10K_0402_1%
1 2
PC52
100P_0402_25V8K
12
PD13
1SS355TE-17_SOD323-2
1 2
PC37
10U_1206_25VAK
1 2
PR78
10.2K_0402_1%
12
PC43
4.7U_0805_6.3V6K
12
PR67
2.8K_0402_1%
1 2
PD11
EC11FS2_SOD106
12
PC58
2.2U_0805_10V6K
12
PC48
4.7U_1206_25V6K
12
PC50
0.47U_0603_16V7K
12
PC39
0.1U_0603_25V7K
1 2
PR185
10_1206_5%
12
PC42
10U_1206_25V6M
12
PR77
0_0402_5%
1 2
PC57
100P_0402_25V8K
12
PC59
1U_0805_25V4Z
@
12
PC45
10U_1206_25V6M
12
PR73
10K_0402_5%
1 2
AO4916_SO8
PQ21
D2 2
G2
8
G1 3
D1/S2/K
5
D2 1
D1/S2/K
7
S1/A 4
D1/S2/K
6
PC38
470P_0805_100V7K@
1 2
PR64
0_0402_5%
12
PR72
619_0402_1%
1 2
PC51
0.47U_0603_16V7K
12
PR168
47K_0402_5%@
12
PL6
FBMA-L18-453215-900LMA90T_1812
1 2
PR66
0_0402_5%
1 2
PC46
0.1U_0603_25V7K
12
PC49
47P_0402_50V8J
12
G
D
S
PQ40
RHU002N06_SOT323@
2
13
+
PC56
150U_D2E_6.3VM_R18
1
2
PR68
1.27K_0402_1%
12
PC55
4.7U_0805_6.3V6K
12
PC41
2200P_0402_50V7K@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BOOT_6269
6269_VCC
6269_VCC
PHASE_6269
UG_6269
LG_6269
ISEN_6269
EN_2.5VSP
6269_VCC
B+
+VCCPP
+5VS
+1.8V
+0.9VSP
+3VALW
+VCCPP
+1.5VS
+12VALW
+12VALWP
+1.8VP
+0.9VSP
+1.5VSP
+VCCP
+0.9VS
+2.5VSP
+5VALW
+1.8V
+3VALW+3VALWP
+2.5VS
+5VALWP
+2.5VSP
+3VALW
+VCCPP
VCCP_ON#<33>
SUSP<37>
SUSP#P<37,45>
VCCP_POK <38>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
+0.9VSP&VCCP&+2.5
43 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+2.5VSP
PU14
XC61CN0902MR
VSS
3
PWDOUT 2
VDDIN
1
PR270
6.49K_0402_1%
1 2
PC61
10U_1206_6.3V7K
12
PJP5
3MM
21
PQ52
SI4800BDY-T1-E3_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PC189
0.22U_0603_16V7K@
12
PC62
0.1U_0603_25V7K
12
PJP10
3MM
21
PJP4
3MM
21
PC64
22U_1206_10V6M
12
PQ53
SI4810BDY-T1-E3_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PR274
2K_0402_1%
12
PC186
2.2U_0603_6.3V6K
1 2
PC60
1U_0603_10V6K
12
PR84
0_0402_5%
1 2
PC119
22U_1206_6.3V6M
12
PJP8
3MM
21
PU16
ISL6269CRZ-T_QFN16
FCCM
3
EN
4
BOOT 13
PVCC 12
VIN
1
VCC
2
PGOOD 16
PHASE 15
UG 14
LG 11
PGND 10
VO
8
COMP
5
FB
6
FSET
7
ISEN 9
GND 17
PC63
22U_1206_10V6M@
12
PR271
49.9K_0402_1%
12
PR273
1.5K_0402_1%
1 2
PC192
6800P_0402_25V7K
12
PJP7
3MM
21
PR156
11K_0402_1%
12
PR83
1K_0402_1%
12
PL22
FBMA-L11-322513-201LMA40T_1210
1 2
PR264
1K_0402_1%
1 2
PC184
10U_1206_25VAK
12
PR265
0_0603_5%
1 2
PJP3
2MM
21
PC118
4.7U_0805_6.3V6K
12
PR267
4.7_0603_5%
1 2
PU5
APL5331KAC-TRL_SO8
VOUT
4
NC 5
GND
2
VREF
3
VIN
1VCNTL 6
NC 7
NC 8
TP 9
PC185 0.1U_0603_25V7K
1 2
PR269
0_0402_5%
1 2
PR80
0_0402_5%
1 2
PR272
57.6K_0402_1%
12
PR82
1K_0402_1%
12
PC187
2.2U_0603_6.3V6K
12
PR268
0_0402_5%
1 2
PR266
4.7_0603_5%
@
12
PJP6
3MM
21
PU12
G965-18ADJP1UF_SO8
ADJ 4
GND
5
VIN
2VO 3
EN
1
GND 8
GND 7
GND
6
PC88
1000P_0402_50V7K
12
PC67
1000P_0402_50V7K@
12
PL23
2.2UH_SSC-10030D3-2R2_7A_20%
12
3
PC190
0.01U_0402_25V7K
12
+
PC188
330U_D2E_2.5VM
1
2
PC191
22P_0402_50V8J
12
G
D
S
PQ23
RHU002N06_SOT323
2
13
PJP9
3MM
21
PR157
10K_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAINPWRON
CHGRTCP
TM_REF1
VS
VL VL
VL
VS
RTCVREF
VIN
BATT_A
1538VCC
BATT_B
CHGRTC
VSB
VS
VL
VL
B+
VIN
+5VALW
BATT_B
PACIN
VS
B+
VL
VL
VL
VL
ACON<40>
MAINPWRON<42>
BATT_UVM<41>
EC_ON#<34>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
RTC Batt&OTP&Pre-charge
44 53Monday, January 08, 2007
H-->L 14.556V 14.807V 15.372V
Precharge detector
Min. typ. Max.
Precharge detector
Min. typ. Max.
ACIN
L-->H 15.276V 15.836V 16.411V
BATT ONLY
L-->H 6.008V 6.124V 6.243V
H-->L 5.044V 5.096V 5.205V
PH2 under CPU botten side :
CPU thermal protection at 80 degree C
Recovery at 44(45) degree C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PD17
RLS4148_LLDS2
12
G
D
S
PQ35
RHU002N06_SOT323
2
13
PC73
0.022U_0402_16V7K
1 2
PD28
RB751V-40TE17_SOD323-2
12
PR97
16.9K_0402_1%
1 2
PC146
1000P_0402_50V7K
12
PR96
2.15K_0402_1%
12
PR87
470K_0402_1%
12
PU9
G920AT24U_SOT89
IN
2
GND
1
OUT 3
PR108
22K_0402_5%
1 2
PR208
47K_0402_5%
1 2
PR210
66.5K_0402_1%
1 2
PR206
140K_0402_1%
12
PR65
100K_0402_5%
12
PR106
100K_0402_5%
1 2
PU13B
LM393DG_SO8
+5
-6
O
7
P8
G
4
PR192
2M_0402_1%
12
PD33
RB715F_SOT323
2
31
PD21
RLS4148_LLDS2
12
PR203
1.5K_1206_5%
1 2
PR204
10K_0402_5%
12
PR102
33_1206_5%
12
PC86
1U_0805_25V4Z
12
PR201
1.5K_1206_5%
1 2
PD32
RLS4148_LLDS2
12
PC85
0.22U_1206_25V7K
12
PU13A
LM393DG_SO8
+3
-2
O
1
P8
G
4
PQ43
DTC115EUA_SC70
2
13
PR88
47K_0402_1%
12
PR207
634K_0603_1%
12
PR109
560_0402_5%
1 2
PR99
150K_0402_1%
12
PC71
0.1U_0603_25V7K
12
PC69
1000P_0402_50V7K
12
PR89
287K_0402_1%
12
PR98
150K_0402_1%
12
PH2
10KB_0603_1%_TH11-3H103FT
12
PR95
47K_0402_1%
1 2
PQ27
TP0610K-T1-E3_SOT23
2
13
PR90
499K_0402_1%
12
G
D
S
PQ24
RHU002N06_SOT323
2
13
PC147
0.1U_0603_25V7K
12
PC78
0.022U_0402_16V7K
1 2
PR86
470K_0402_1%
12
PR94
47K_0402_1%
1 2
PR104
200_0805_5%
12
PR200
1.5K_1206_5%
1 2
PC87
4.7U_0805_6.3V6K
12
PC83
0.1U_0603_25V7K
12
PR209
34K_0402_1%
12
PU7B
LM393DG_SO8
+
5
-
6O7
P8
G
4
PR205
412K_0603_1%
PC75
0.1U_0603_25V7K
12
PC76
1000P_0402_50V7K
12
PC79
100P_0402_50V8J
12
PD19
RLS4148_LLDS2
12
PR202
1.5K_1206_5%
1 2
PR110
560_0402_5%
1 2
G
D
S
PQ22
RHU002N06_SOT323
2
13
PC77
1U_0603_10V6K
12
PD20
RLS4148_LLDS2
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DL1_1.8VP
DH2_1.5VSP
DL2_1.5VSP
LX1_1.8VP
LX2_1.5VSP
BST1_1.8VP
REF_MAX8743
BST2_1.5VSP
FB2_1.5VSP
DH1_1.8VP
VCC_MAX8743
ILIM2_1.5VSP
ILIM1_1.8VP
+5VALW
+1.5VSP
1845_B+
B+
+1.8VP
SYSON<33,37>
SUSP#P <37,43>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
+1.5VSP & +1.8VP
45 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PC152
4.7U_1206_25V6K
12
PR215
10K_0402_1%
12
PD34
DAP202U_SOT323
2
31
PR216
0_0402_5%
12
PC155
0.1U_0603_25V7K
12
PR211
0_0402_5%
1 2
PC149
4.7U_1206_25V6K
12
PC154
1U_0805_25V4Z
12
PR219
15K_0402_1%
12
PR213
0_0402_5%
1 2
PC161
0.01U_0402_25V7K@
12
PU10
MAX8743EEI+T_QSOP28~N
OUT2 15
BST2 19
FB2 14
CS2 16
VDD 21
UVP 9
SKIP
6
V+ 4
GND
23
ON1
11
DH1
26
LX1
27
ILIM2 13
DL1
24
VCC 22
PGOOD 7
FB1
2ON2 12
ILIM1 3
OVP
8
REF
10
LX2 17
DL2 20
TON 5
CS1
28
BST1
25
DH2 18
OUT1
1
PC100
4.7U_0805_6.3V6K
12
PR221
100K_0402_1%
12
PR212
20_0603_5%
1 2
PR214
5.1K_0402_1%
12
+
PC159
150U_D2E_6.3VM_R18
1
2
PR217
0_0402_5%
1 2
PC158
4.7U_0805_6.3V6K
@
12
PL18
4.7UH_MPL73-4R7_5.5A_20%
1 2
PC153
0.1U_0603_25V7K
12
AO4916_SO8
PQ45
D2 2
G2
8
G1 3
D1/S2/K
5
D2 1
D1/S2/K
7
S1/A 4
D1/S2/K
6
PC150
2200P_0402_50V7K
@
12
PC160
4.7U_0805_6.3V6K
@
12
PL19
4.7UH_MPL73-4R7_5.5A_20%
1 2
PR220
100K_0402_1%
12
PC162
0.22U_0603_10V7K
12
PC148
2200P_0402_50V7K
@
12
PC156
0.1U_0603_25V7K
12
+
PC157
150U_D2E_6.3VM_R18
1
2
PR218
33K_0402_1%
12
PC151
4.7U_1206_25V6K
12
AO4916_SO8
PQ44
D2
2G2 8
G1
3
D1/S2/K 5
D2
1
D1/S2/K 7
S1/A
4D1/S2/K 6
PJP11
3MM
21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
POUT
DH1_CPU
SHDN#
D4_CPU
PWRGD_CPU
CLKEN#
D3_CPU
D5_CPU
REF_CPU
D6_CPU
D0_CPU
D2_CPU
D1_CPU
CCI_CPU
CSN2_CPU
CSP1_CPU
DPRSTP#
FB_CPU
CSN1_CPU
DL1_CPU
BSTM1_CPUBST1_CPU
VSSSENSE
LX1_CPU
VCC_CPU
VRHOT
PSI#
DPRSLPVR
VDD_CPU
CPU_VCC_SENSE
DL1_CPU
PWRGD_CPU
CLK_ENABLE#
+5VS
CPU_B+
+5VS
B+
+3VS
+VCC_CORE
+3VS
VCCSENSE
<7>
VGATE_INTEL<22,33>
CLK_ENABLE#<5>
H_PROCHOT#<6>
VSSSENSE<7>
CPU_VID0<7>
VR_ON<33,37>
CPU_VID1<7>
CPU_VID2<7>
CPU_VID5<7>
CPU_VID4<7>
CPU_VID3<7>
CPU_VID6<7>
H_DPRSLPVR<9,22>
H_DPRSTP#<6,21>
H_PSI#<7>
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
PWR-CPU-CORE
46 53Monday, January 08, 2007
For windows idle mode noise issue
NTC
NTC
NTC
Tsw=Cton(Rton+6.5k) Cton=16.26pf
f=1/Tsw=1/Cton(Rton+6.5K)
=1/16.26pf(200k+6.5k)=297.824khz
Rton=PR224
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PR261,PQ54 will be populated
when MAX8870 Rev0.2 is used.
For ULV CPU, PR247 value 8.87K, P/N:SD034887180
For LV CPU, PR247 value 3.65K, P/N: SD034365180
PR249
0_0402_5%
1 2
PC167
0.1U_0603_25V7K
12
PC166
10U_1206_25VAK
12
PR247 3.65K_0402_1%
1 2
PH5
10KB_0603_1%_TH11-3H103FT
1 2
PR257 0_0402_5%@
1 2
PC177
4700P_0402_25V7K
1 2
PR251
3K_0603_1%@
1 2
PR246
2K_0402_1%
1 2
PR255
10K_0402_5%@
1 2
PC165
10U_1206_25VAK
12
PC173470P_0402_50V7K
12
PR228 0_0402_5%
12
PR233
7.68K_0402_1%
1 2
PC179
1000P_0402_50V7K
1 2
PR260 0_0402_5%
1 2
PR222
0_1206_5%
12
PR243 0_0402_5%
1 2
PR227
0_0402_5%
1 2
PQ47
IRF7832PBF_SO8
S
1
S
3G
4
D8
D7
D6
D5
S
2
PR232 0_0402_5%
12
PR254
0_0402_5%
1 2
PR235 0_0402_5%
1 2
PC174 0.22U_0603_16V7K
1 2
PC170
2.2U_0603_6.3V6K
1 2
PC171
0.22U_0603_16V7K
1 2
PC168
2200P_0402_50V7K
12
PR250
3K_0603_1%@
1 2
G
D
S
PQ54
RHU002N06_SOT323@
2
13
PR237
3.48K_0402_1%
1 2
PC164
10U_1206_25VAK
12
PC169
2.2U_0603_6.3V6K
1 2
PR241 0_0402_5%
1 2
PR252
0_0402_5%
1 2
PR244 1K_0402_1%@
1 2
PR230 0_0402_5%
12
PC172
680P_0402_50V7-K
@
12
PR239 499_0402_1%
1 2
PR238 71.5K_0402_1%
12
+
PC182
47U_25V_M
1
2
PH4
100K_0603_1%_TH11-4H104FT
@
1 2
PR245
2K_0402_1%
1 2
PR236
10_0402_5%
12
PR225
13K_0402_1%
1 2
PR253
20K_0402_1%
1 2
PR229 0_0402_5%
12
PR261
2K_0402_1%@
1 2
PR231
4.7_1206_5%
@
12
PR259
10_0402_5%
12
+
PC181
47U_25V_M
1
2
PR234 0_0402_5%
12
PC178
470P_0402_50V8J
1 2
PR2420_0402_5%
12
PC180
0.1U_0402_16V7K
1 2
PR256
100_0402_5%
1 2
PL21
P_0.36H_ETQP4LR36WFC_24A_20%
12
PR226 0_0402_5%
12
PC163
0.01U_0402_25V7Z
12
PQ46
SI7840DP-T1-E3_SO8
3 5
2
4
1
PR248 100_0402_5%
1 2
PR224
200K_0402_5%
12
PC176 1000P_0402_50V7K@
1 2
PQ48
IRF7832PBF_SO8
S
1
S
3G
4
D8
D7
D6
D5
S
2
PR240 0_0402_5%
1 2
PU15
MAX8770GTL+_TQFN40
FB 12
CSP2 14
GND 18
CCV
9
CCI 10
REF
11
CSP1 17
CSN2 15
CSN1 16
CLKEN
1
BST2 20
GNDS 13
DPRSTP
40
D2
33
D1
32
D0
31 BST1 30
Vcc
19
TIME
7
THRM
6
VRHOT
5
POUT
4
PSI
3
PWRGD
2
TON 8
PGND2 23
VDD 25
DL2 24
DL1 26
DH2 21
PGND1 27
D6
37
D4
35
D5
36
D3
34
LX2 22
LX1 28
DH1 29
DPRSLPVR
39
SHDN
38
TP
41
PC175 0.22U_0603_16V7K
1 2
+
PC183
15U_D2_25VM_R90
1
2
PL20
FBMA-L11-322513-201LMA40T_1210
12
PR223
10_0402_5%
12
PR258
10K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Power up Sequence
47 53Monday, January 08, 2007
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Hardware PIR list
48 53Monday, January 08, 2007
HW P.I.R LIST
P18
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Change item Change reason Date Revision
1. ADD 100K ohm pull-down resistor on ENVDD Follow Intel suggestions 9/05/05 X0.1
Page#
2. ADD one more Panel ID, PID0 to support more panel Reqired by Mothion P18 9/05/05 X0.1
3. Add R791, Del R877 Use LED signal from Minicard to control RF LED directly, Reqired by Mothion P28, P34 9/28/05 X0.1
4. Add R46,R31,R32,JP32 and Q12, Del JP31 Support SD card function and cancel the Smart card function P25, P26 1/11/06 X0.1
5. Change the net of R22 pin 2 from CLK_48M_SC to CLK_48M_SD Support SD card function and cancel the Smart card function P5 1/12/06 X0.1
6. Add R37,R42 to pull high LCTLA_CLK & LCTLB_DATA Follow Intel Rev 1.601 design check list P11 1/12/06
7. Add U19, C610, Delete D26,D30 and populate R636 Follow Intel Rev 1.601 design check list to pull down ENABLT P17 1/12/06
8. Delete R668,R732 No need these pull high resistor for setting the Boot BIOS destination P20 1/12/06
X0.1
X0.1
X0.1
9.Add an unpopulated resistor R676 Reserved for the future. P21
10. Unpopulate R895 Use the internal pull high of ICH7 P34
11. Swap the USB port 3 and port 4 to the docking connector JP27 Follow Motion's request P36
1/12/06
1/12/06
1/12/06 X0.1
X0.1
X0.1
12. Add R48 and C800 Tune regulator power sequence to insure AVDD rail should come up after the DVDD rail P30 1/14/06 X0.1
13. C26,C32,R59,R60 only populate for 9220;
R59,C798,R58,C799,R61populate for 9204 For 9220 and 9204 co-layout P30 1/14/06 X0.1
14. change C826/827 from 47uF to 220 uF Follow Sigmatel suggestions P31 1/14/06 X0.1
15. Depopulate C846/C847 Follow Sigmatel suggestions P31 1/14/06 X0.1
16. Change cardbus signals SPKROUT and HWSPND# pull
high power to +3V_R5C843 from +3VALW Follow FAE check list request P25 1/16/06 X0.1
17. Add JP31,U19 and related components; delete JP32,Q12
and relatied components Follow Motion change: add SC, delete SD P26 1/17/06 X0.1
18. Add layout notice for CCLK/CARD16 Follow FAE check list request P25 1/19/06 X0.1
19. Add C71 Follow FAE check list request P25 1/19/06 X0.1
20. Pull cardbus signals TPBP0/TPBN0/TPBP1/TPBN1 to ground Follow FAE check list request P25 1/19/06 X0.1
21. Remove U28 and add R1/Q12 Follow motion request: shutdown amplifier to save power in S3 state P31 1/24/06 X0.1
22. Signal mute# change into mute Match Item 21 request P31,P33 1/24/06 X0.1
23. Delete R879, R880 and cancel the net of DDR_ID0, DDR_ID1 Delete the unused DDR_ID0 and DDR_ID1 P33 2/13/06 X0.1
24. JP1 and Add U8 Update the package of CPU from uFCPGA to uFCBGA P33 2/13/06 X0.1
25. Delete U21, ADD U27 Change the USB HUB to USB controlller P27 2/21/06 X0.1
26. Delete U1, Add U46 Change the clock Gen to compal part P5 2/21/06 X0.1
27. Move the net ACOFF from U33 pin31 to U33 pin80
Add the net LED_PWM Use the PMW signals from EC to contol the brighness of LED P33,P36 2/21/06
28. Delete tlhe R953 Follow Intel USA suggestions
X0.1
3/01/06
P22 X0.1
29. Delete tlhe R951, R853 Follow Motion's request P32 3/02/06
30.update the Docking connector's symbol Change the Docking con from 100 pins to 80pins P36 3/02/06
X0.1
X0.1
31.Del U23 and relative components, add U47 and relative components Change the Smart card controller from O2 to Omnikey P26 3/03/06 X0.1
Remove the Smart card function X0.1
3/07/0632.Del U27&JP31 and relative components P26
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Hardware PIR list
49 53Monday, January 08, 2007
HW P.I.R LIST
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Change item Change reason Date Revision
X0.1
Page#
P26 3/07/06
33.Add Q15, JP32 and relative components Follow Motion's request add SD card feature
34.Del LED_PWM, Add PWM_CTL to Q14 pin 2 Follow Motion's solution for LED dimming control P17 3/09/06 X0.1
35. Add the location for R775,R777,R778,R782,R781,R783 and R476 Reserve the locations for Port 80H debug card when debugging P24, P5 3/09/06 X0.1
36. Reassign the pin net of Docking Put the anlog power and analog GND together to get get better placement and return loop. P36 3/13/06 X0.1
37. Add CF13,CF14 and Del H23, H24,H28,CL2,CL3 3/13/06 X0.1P38
New PCB and new feature requirement
38. Add the locations for C431,C432,C425,C426,C427
C458,C437,C438C444,C445 Reserve the locations for 10uF caps in case of world wide shortage of 22uF caps P8 3/13/06 X0.1
39. Change the net of R747.2 from ICH_AZ_CODEC_SDIN0
to SDATA_IN Correct the net error P30 3/15/06 X0.1
40. Add C271 Connect GND and LAN shield P29 3/15/06 X0.1
41. change +0.9V to +0.9VS for VTT of DDR Power net error P16 3/21/06 X0.1
42.Populate R918 follow Vishay's suggestion 3/21/06
P35 X0.1
43.Delete Q12, add U31 and unpopulate R1, change MUTE to MUTE# to avoid the current leakage when MUTE ative and no Headphone plugging in S0 P31 3/22/06 X0.1
44.Add R73, R74 For debug use only P27 3/24/06 X0.1
45. Update JP24 symbol Use small footprint for layout space saving P33 3/24/06 X0.1
46.ADD D34,D35,D36,D37,D38,D39,D40,D41,D42,D43,D44 Add the location of ESD protection Diode for HSYNC, VSYNC, ON/OFFBTN#, WL_SW# and DVI signal lines. P19,P34,P36,
P24,P18 3/30/06 X0.1
47.Delete R772 remove the dual pull-up resistors for WL_SW# P24 3/31/06 X0.1
48.Delete Q7, Add D45 update symbol P17 4/07/06 X0.1
49.Add R472,R473,R478,R479,C359,C360,C361,C362 Add these components for signal quality of SD. P25 4/10/06 X0.1
50.Add R951, R953, R964, R965, C930 and Q63 To support usb wake up from docking and wake up function can be selected by user. P32,P36 5/12/06 X0.2
X0.25/12/06
P24
51.Delete R775 ;pin10,pin12,pin14,pin16 of JP13 net swap Delete the useless power and change error the LPC nets for port 80H debug card
52.Add R2 To pull high HP_PLUG# to give it a stable status. P31 5/12/06 X0.2
53.Add R480, C363 To reduce the SD_CMD's overshoot and undershoot P25 5/15/06 X0.2
54.Add C611, C612,C619,C625 Follow Motion's request P15,P16 5/15/06 X0.2
55.Add H51, JP12,JP22,JP23 Add a hole to fix HDD FPC, symbols of VGA connentor and usb connectors update for ME requirement P38,P19,P32 5/24/06 X0.2
56.Add C633,C671,C672,C677 Follow motion's request P49,P17 5/24/06 X0.2
57.unpopulate R73 To solve the issue of system hangup when enable NEC controller P49,P27 5/26/06 X0.2
58.reasssign the docking usb ports to ICH7 To support DOS mode for all docking ports P22,P36 5/26/06 X0.2
59.Delete Q62,Q13,R776,R780,R791,R924 Remove LEDs for HDD,B/T and WWAN,WLAN P17,P27,P24 5/26/06 X0.2
60.Add D6,D9,D13,R4,R7,R8 Support the LEDs change to M/B P17 5/29/06 X0.2
61.Add two nets of WLAN_SW_EN, WWAN_SW_EN on U33,JP30 Follow SED request for supprting antenna's switching P33,P36 5/29/06 X0.2
62.Change nets of JP6.24, JP6.36 from GND to +3vs, add R263,R262 follow motion's request of reserving 4 power wires for N-trig P17 6/01/06 X0.2
63.Change Q52, from AO3402 to SI3456,
JP13&JP28 pin24 from+3VALW to +3V_LAN To support WOWLAN & WOL in AC only mode P28,P24 6/06/06 X0.2
X0.2
6/06/06
64.Change +3VALW of U27 to +3VS,Del R315, change USB_SMI#
from U9.E21 to U9.AC18, populate R346,R320, unpopulate R312,R321 For more power saving and extendeing the life of bridge batter in S3 mode P27,P22
65.Swap the nets of U46.16&U46.17 modify the wrongly connected SMbus of clock Gen, to solve the issue of C3 hang up P5 6/06/06 X0.2
66.Add R641, R633, change the net of PID1 to ID0 add ID0, ID1 two hw strap pins to identify the N-Trig Wacom or TouchKo P17,P22 6/07/06 X0.2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Hardware PIR list
50 53Monday, January 08, 2007
HW P.I.R LIST
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Change item Change reason Date Revision
X0.3
Page#
P17 7/17/06
67.Change R8 from 150ohm to 2.2K Solve LED no light issue
68.Swap cardbus controller U15B pinV14/W14 net names Solve new card can not be detected issue P25 7/17/06 X0.3
69.Change H26/H27 size from 110 to 165 Solve standoff too big & hole too small to dock-MB/B can not fix well issue P38 7/17/06 X0.3
70.Add PID and ID table; change LCD connector symbol Be beneficial to look at schematic; connect NC pin for EMI providing P17 7/17/06 X0.3
71.Delete H50 No use P38 7/17/06 X0.3
72.Change block diagram Follow Motion requirement P2 7/27/06 X0.3
73.Add R3, unpopulate R918/R919 Solving Irda communication information occur error issue P35 7/31/06 X0.3
74.Populate R17/R18 Follow EMI requirement P30 7/31/06 X0.3
75.Change R11 to L21 Follow EMI requirement P30 7/31/06 X0.3
76.Change U42/U43/U44 from AO4422 to AO4468 AO4422 will EOL, AO4468 will substitute it P37 7/31/06 X0.3
77.Add new JP34, delete old JP29/JP34 Solving DFX issue P36 7/31/06 X0.3
78. Add mark LV@ on +VCC_CORE 12*22U & 2*330U
decoupling capacitors For Motion requirement P8 7/31/06 X0.3
79. Add unpopulate R698/C678 Following Motion requirement for providing EMI P27 8/1/06 X0.3
80. Add unpopulate R699/C679 Following Motion requirement for providing EMI P25 8/1/06 X0.3
81. Add series resistors R700/R707 Following Sigmatel requirement P31 8/1/06 X0.3
82. Change C835/C836 from 220pF to 0.01U Following Sigmatel requirement P31 8/1/06 X0.3
83. Change L27/L28/L29/L30/L31/L32/L33/L34 to L22/L23/L24/L25
co-layout with R818/R819/R820/R821/R822/R823/R824/R825 Follow EMI requirement P29 8/1/06 X0.3
84. Add unpopulate JP29 on side of NEC controller For Motion requirement P27 X0.3
85.Change H18 size from C276D110 to C197D110 For ME change requirement P38
8/2/06
8/2/06 X0.3
86. Add C74/C75 Following Motion requirement P28 8/2/06 X0.3
87. Delete R57,R69,C798 Co-layout Trinity and delete co-layout Colorado with STAC9220 P30 8/4/06 X0.3
88. Add U1/C680/C931/C932/R446 Adding buffer to generate V_DDR_MCH_REF to solve SODIM sometime can not boot issue P9 8/7/06 X0.3
89. Change R81 from 4.87K to 4.75K Following Marvell requirement to optimize LAN chip usage P28 8/14/06 X0.3
90. Change C69/C70 from 27pF to 18pF Following Marvell requirement to optimize LAN chip usage P28 8/14/06 X0.3
91. Change transformer T21 from GST5009-LF to GST5009-V Following Marvell requirement to optimize LAN chip usage P29 8/14/06 X0.3
92. Change U16/U31 power supply from +5VALW to +5VS Save power in S3 state and reduce speakers output noise P31 8/14/06 X0.3
93.Add R23/R25/U47/C39/C798/R57/Q62 footprint on board Reserve for reduce headphone pop niose P30 8/16/06 X0.3
94. Delete Q61, R685, R668, Q14, D6, D9, D13, R7, R8, R4.
Add R924, Q16, R712, R642, R6, Q64, R364, D15, R331, Q66,
R317, D19, R330, Q65, R315, D16.
As Motion requirement. Add LED brightness control function. P17 9/29/06 X0.4
95. Change J2, J3 size, change J6 to Jump type. Follow factory DFX requirement. P17 9/29/06 X0.4
96. Add C681, R717, R716.
Change JP6.40 from GND to PID1.
Add signal PID1 to ICH7.AE20. Follow Motion requirement. Add one pin to support panel ID. P17 9/29/06 X0.4
97. Add R718, Q11.
Add signal DVI_DETECT# to ICH7. AD21.
P22
Follow Motion requirement. Add DVI plug detect function to ICH. P18
P22 9/29/06 X0.4
98. Change R34 from un-mounted to mounted.
Add U48, R60, R451, Q67, U49. Follow Motion requirement. Add power saving function for Ricoh controller. P25 9/29/06 X0.4
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D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Hardware PIR list
51 53Monday, January 08, 2007
HW P.I.R LIST
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Change item Change reason Date RevisionPage#
P27
99. Add R826, R452, Q68, U50, R75, U53.
Change U27 power supply from +3VS to +3V_NECUSB. Follow Motion requirement. Add power saving function for NEC controller.
100. Delete R287.
Add R87, R82, R86, R83, R84, R85. For debug. P33
9/29/06 X0.4
101. Add R333, R332.
Add signal PCM_CLK_EN#, USB_CLK_EN#, Card_Insert#. P33
9/29/06 X0.4
9/29/06 X0.4
Follow Motion requirement. Add power saving function for NEC controller and Ricoh controller.
102. Add location CLIP1 For deal with antenna routing conveniently P38 10/16/06 X0.4
P35 10/17/06 X0.4
P24 10/17/06 X0.4
103. Add R294 FIR part change
104. Add U56, C686, C685, C684, C683, R725,
R730, R720, R968, C687, Q61, Q69, U57.
Add signal G_SENSOR to EC. Add G-Sensor function
105. Swap EC U33 pin35 and pin80 Solve +5V_DOCK turn on/off condition validity P36 11/01/06 X0.4
106. Delete EC U33 pin62 project _ID net name No use P33 11/01/06 X0.4
107. Delete U57,change U33 pin62/pin90 net name Follow vender review result to change P24, P33 11/01/06 X0.4
108. Delete EC U33 pin91/pin92 net name No use P33 11/01/06 X0.4
109. JP30 pin4 and pin6 pull down to ground No use P36 11/01/06 X0.4
110. Buletooth USBP2+/- change into NEC_USBP2+/-;
JP28 NEC_USBP2+/- change into USBP2+/-
Swap WWAN and BT, ensure WWAN to be used under DOS mode P24, P27 11/01/06 X0.4
111.Change U33 pin46 net name from RFOFF# to WLANOFF#
Change U33 pin92 net name from WWAN_SW_EN to WWANOFF#
Change JP13 net name from RFOFF# to WLANOFF#
Change JP28 net name from RFOFF# to WWANOFF#
Separate WLAN and WWAN on/off control signal P24, P33 11/01/06 X0.4
112. H9 connect to digital ground from analog ground Antenna pass through H9 area, provide signal being interfere P38 11/01/06 X0.4
113. Add C416 Delay shutdown ramp up time to solve headphone pop-noise P30 11/01/06 X0.4
114. Add unpopulate C507 For HSDL-3220 FIR reserve capacitor P35 11/01/06 X0.4
115. Delete R328,R316, project_ID related table No use P33 11/01/06 X0.4
116. R327/R326 populate, R267/r157 unpopulate Correct BDID configuration P33 11/01/06 X0.4
117. Add unpopulate R966/C933 Add AC ternimation for EMI providing P24 11/01/06 X0.4
118. Change BIOS/B connector from E&T_1009-E40L-00R
to ACES_88072-4071_40P Solving BIOS/B connect stably with MB P34 11/06/06 X0.4
Solving USB connector stability when inserting USB device P32 11/06/06 X0.4
120. JP19,
change Pin1 to GNDA;
change Pin2 to INTMIC3;
change Pin3 to GNDA;
119. Change USB connector from SUYIN_020173MR004S500ZL
to SUYIN_020173MR004S583ZL
Solve the MIC(3rd) noise issue; P36 11/08/06 X0.4
121. JP34;
Move Pin11 --> Pin9
Move Pin10 --> Pin11
Move Pin9 --> Pin10
Solve the MIC(Mic2) 'click' noise issue; P31 11/08/06 X0.4
122. Change H26/H27 size form C276D165 to C276D173 Solve the docking CRT signal instability issue P38 11/14/06 X0.4
123. Add unpopulate R283/R967 and R969 Follow SMSC schematics review P35 11/14/06 X0.4
124. Change L42/L47 from BLM18AG601SND1 to BK1608HM601-T Follow IDT AP test feedback result P31 12/27/06 X0.5
125. Swap EC U33 pin27 and pin30 Solving fan noise, pin30 PWM can not be programming to 30KHz P33 12/27/06 X0.5
126. Delete R718, delete U9 pinAD21 net to NC the pin ,
change net PCI_REQ5# into DVI_DETECT# Solving DVI can be automatically detected by system when inserting P18, P20,P22 12/28/06 X0.5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Hardware PIR list
52 53Monday, January 08, 2007
HW P.I.R LIST
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Change item Change reason Date RevisionPage#
P33127. Redefine BID For reviewing 12/28/06 X0.5
128. Add Q70, Q72, R731, R732 Providing ALS/B leak current to +3VS P36 12/29/06 X0.5
129. Re-assign MB ALS/B connector JP34 pin Solving the 1st array mic noise issue P36 12/29/06 X0.5
130. unpopulate Q62/C416, add R88, when use MAX9890,
use U33 pin91 control shutdown pin with R88 Reduce HP pop noise P33,P30 12/29/06 X0.5
131. Change PCIE 0.1u capacitor C631/C632/C629/C630/C661/C670
part number Solving PCIE capacitor temperature characteristic unstable issue P22 12/29/06 X0.5
132. Change FIR module U41 to agielent HSDL-3220 Use agielent FIR module to solve FIR transmition and receive fail issue P35 12/29/06 X0.5
133. Change JP30 pin19 GND to GNDA Solving 2nd array mic noise issue P36 12/29/06 X0.5
134. Change R965 form 100 to 22K; change C930 from 0.1U to 0.47U
and re-connect; change R964 from 100K to 330K; add R970 Solving vibration issue when S3 wake up only battery supply power P36 12/29/06 X0.5
135. change JP34 pin assignment Avoid record noise in internal MIC1 P36 01/08/07 X0.5
136. delete signal "Blanco_USB_OC#" Avoid ESD fail on this pin P34 01/08/07 X0.5
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D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Power PIR list
53 53Monday, January 08, 2007
2. Add PQ51,PQ49,PR262, change PR163 from 0 to
84.5K,change PR164 from 0 to 100K. Add switch function to support Sanyo 4.35 cell battery.
Change item
P40 03/03/06 X0.1
3. Del MAX8578 circuit(PU6,PQ41,PL17,PL16...),add ISL6269 solution
for VCCP(PU16,PQ52,PQ53,PL22,PL23...). Improve VCCP supply current from 4A to 7A. X0.1
03/03/06
P43
POWER P.I.R LIST
P40
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Change reason Date Revision
1. Change PR39 from 1K_0402_1% to 10K_0402_1%. For MAX1908 issue. 01/14/06
Page#
X0.1
4. Remove PC88 from PU14.3 to PU14.1 Connection error P43 03/24/06 X0.1
5. Delete PC88,PU14 Use ISL6269 PGOOD as VCCP_POK. P43 03/30/06 X0.1
6. ADD PC88,PU14 ,PR264 Use PU14 produce VCCP_POK.
6. ADD PR34,change PR10 form 7.32K to 3.92K Providing PR10 being destroied only one resistor as load, one resistor divide into two resistors to reduce resistor fail risk P39 10/16/06 X0.4
