IDX80 La 3291

User Manual:

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4

3

2

1

Project Name: PecosII
(IDX80)
D

D

PCB Serial Number:
LA-3291

PecosII Schematics Document
C

C

Intel Merom Dual Core LV1.33G&1.5G
/Yonah Single Core ULV 1.06G&1.2G + Calistoga GM + ICH7-M

2007-01-08

B

B

REV: X0.5

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Cover Sheet
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
1
1

Rev
X 0.5
of

53

5

4

DC-DC
page 37

3

2

Block Diagram

VCCP&
CPU_CORE

Clock Generator
CPU Thermal Sensor
ICS9LPRS325AKLF
G781F
page 6
page 5

Merom Dual Core LV
/Yonah Single Core ULV

page 46

D

1

Fan Control x1
page 6

D

479 uFCBGA CPU
CRT port

Docking
CRTpage 36

page 6, 7, 8

FSB
HA#[3..31]

HD#[0..63]

533/667MHz

CRT CONN.

Intel Calistoga GM

page 19

DVI CONN
page 18

Hydis
LCD 12.1"
XGA/SXGA+

C

SDVO

DVI Controller
CH7307 page 18

SO-DIMM x 1
4 BANK

1.8V 533/667MHz

page 15

USBPORT0

1466 FCBGA

DDR2 Channel B

LVDS port

LVDS CONN.

DDR2 Channel A

page 17

SO-DIMM x 1
4 BANK

page 9, 10, 11, 12, 13, 14

page 16

USBPORT 2
USBPORT 3
USBPORT 4

DMI x4 1.5V

USBPORT 5
USBPORT 6

SIM
card page

24

Mini Card
WWAN
page 24

PCIE BUS

Mini Card
WLANpage 24

PCIE BUS

ICH7-M
652 BGA

PCIE x1
3.3V 33MHz PCI Bus

USB 2.0

48MHz/480Mb

Azalia

3.3V

PATA100
page 20, 21, 22, 23

page 32
C

page 24

Finger Printer

page 36

LLANO DOCK
page

36

Travel DOCKpage

36

LLANO DOCK
page

36

LLANO DOCKpage

36

Azalia Codec
STAC9220page 30

LPC Bus 3.3V 33MHz
Docking
HP&MIC

Port 2
page 27

page 24

Bluetooth

WLAN

page 25

page 36

CardBus

page 29

Port 1

Port 0

Transformer
& RJ45

WWAN

page 32

page 24

page 25

page 27

page 28

Docking
RJ45

CardBus
R5C843

USB 2.0
Controller

USBPORT 7

On M/B

HDD 1.8"

B

Gigabit Lan
88E8053

On M/B

USBPORT 1

B

AMP & HP &
MIC
page 31

page 36

PCMCIA Slot
page 26
SD Socket
page 26

express
card page

page 32

page 35

SMSC
LPC47N217

Embedded Controller

ENE KB910L

TPM
SLB9635TT

page 33
26

X Bus

A

ROM DAUGHTER BOARD
A

SST39VF080

Digitizer

FIR

page 34

Compal Electronics, Inc.(KunShan)

Title

Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
2
1

Rev
X 0.5
of

53

5

4

External PCI Devices
DEVICE

IDSEL #

3

2

1

Power Management table

REQ/GNT #

PIRQ

CARD BUS

AD20

2

A,B

USB controller

AD21

0

E,F,G

+12VALW
Signal

+1.8V

+5VS

+5VALW

+3VS

+3VALW

+1.8VS

+3V_LAN

+2.5VS
+1.5VS

D

+0.9VS

State

D

+VCCP
+CPU_CORE
ON

S0

ON

ON

S1

ON

ON

ON

S3

ON note1

ON

OFF

S5 S4/AC

ON note1

OFF

OFF

S5 S4/AC don't exist

OFF

OFF

OFF

Note1 : +3V_LAN is ON only with AC power available, otherwise it is OFF.

Symbol Note

Voltage Rails
: means Digital Ground

Power Plane

C

: means Analog Ground

: Question Area Mark.(Wait check)

@: means don't stuff, just reserve

S0-S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit

N/A

N/A

N/A

+VCC_CORE

Core voltage for CPU

ON

OFF

OFF

+VCCP

1.05V power rail for Processor I/O and MCH core power

ON

OFF

OFF

+0.9VS

0.9V switched power rail for DDRII Vtt

ON

OFF

OFF

+1.5VS

1.5V switched power rail for PCI-E interface

ON

OFF

OFF

+1.8V

1.8V power rail for DDRII

ON

ON

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V switched power rail for MCH video PLL

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

DVI_7307@: means just stuff when use CH7307 controller

+5VALW

5V always on power rail

ON

ON

ON*

DVI_1362@: means just stuff when use Sil1362 controller

+5VS

5V switched power rail

ON

OFF

OFF
ON*

DB@: means jsut stuff when Mini-PCI E Debug card function enable

B

Description

9220@: means just populate when mount 9220 on board;
depopulate when mount 9228 on board
9228@: means just populate when mount 9228 on board;
depopulate when mount 9220 on board

+12VALW

12V always on power rail

ON

ON

RTCVCC

RTC power

ON

ON

ON

+3V_LAN

3.3V LAN power rail

ON

ON*

ON*

C

B

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

LV@: means just populate when mount Merom/Yonah LV DC CPU on board;
depopulate when mount Yonah ULV SC CPU on board
Buffer@: means just populate when buffer generate V_DDR_MCH_REF;
depopulate when 1.8V divider generate V_DDR_MCH_REF
1.8_divider@: means just populate when 1.8V divider generate V_DDR_MCH_REF;
depopulate when buffer generate V_DDR_MCH_REF
1@: means just populate 0ohm resistors on board;
2@: means just populate MAX9890 & related components on board;
3220@: means populate 0ohm resistors when mount Agilent 3220,unpopulate 0ohm resistors when mount other

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Notes&Revision
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
3
1

Rev
X 0.5
of

53

5

4

3

2

1

B+
ADAPTER
VS

ACIN
MAINPWRON

D

DOCK

SYSON
SUSP#

MAX1902

DOCK_IN

+3VALW

VCCP_ON#
MAX8743

+5VALW +12VALW

ISL6269

D

+1.8VP
+1.5VSP
+VCCP

LDO
G965

SUSP#P

SUSP

APL5331

LDO
XC61CN

EC_ON#
SUSP

A OR B BATTERY

C

A OR B BATTERY

+2.5VSP

+1.8VS

A BATTERY

SUSP#

+3VS

+0.9VSP
+VCCP_OK

C

+5VS

MAX1908
CHARGER

FSTCHG
IREF

BRIDGE BATTERY

H_DPRSLPVR
H_DPRSTP#
H_PSI#

B BATTERY

BATT+

A OR B BATTERY

VR_ON

VID0
VID1
VID2
VID3

MAX8770

VID4

VGATE
B

MAX1538

VID6

H_PROCHOT#

FSTCHG

B

VID5

CLK_ENABLE#

BATSELB_A#

BATTERY SELECTOR
RTC_VREF

VSB

POWER SOURCE

+VCC_CORE

BATT+
RTC BATT

G920AT24U

VIN

CHARGER SOURCE

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Power rail
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
4
1

Rev
X 0.5
of

53

5

4

3

FSLB

FSLA

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

1
2
+3VS
FBMA-L11-201209-221LMA30T_0805 1

0

0

1

133

100

33.3

2

C386

0.1U_0402_16V4Z

1

C387

0.1U_0402_16V4Z

1

2

+CK_VDD_MAIN2

33.3

L15

R430

1
2
+3VS
FBMA-L11-201209-221LMA30T_0805 1

FSB Frequency Selet:

1
1

C388

1

C389

C390

D

533MHz

CLK_Ra CLK_Rb CLK_Rc

No Stuff

CLK_Rd CLK_Re CLK_Rf

Stuff

CLK_Rd CLK_Re CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

2

10U_0805_10V4Z

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

Stuff

CLK_Rd CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

VDDSRC
VDDSRC
VDDSRC
VDDSRC

CLK_48M_USB
CLK_48M_ICH

2
1

<33> CLK_PCI_EC

VDDA

7

GNDA

8

<27> CLK_PCI_USB

1
R466
0_0402_5%

<35> CLK_PCI_SIO

2

MCH_CLKSEL1 <9>

1
12_0402_5%
FSLA
1
12_0402_5%
FSLB
FSLC
1
R449
FCTSEL1

2
2
2
2

R464

2

CLK_14M_SIO
2
33_0402_5%

<35> CLK_14M_SIO

1K_0402_5%

DREFCLK

<9> DREFCLK

1

CPU_BSEL1

1

CLK_Rb

<9> DREFCLK#

@ R471

2

0_0402_5%

<20> CLK_PCI_ICH

CLK_Re

B

CPU_STOP#

24

H_STP_CPU#

H_STP_CPU# <22>

CK_CPU

1
R43
CK_CPU#
1
R44

2 CLK_CPU_BCLK
0_0402_5%
2 CLK_CPU_BCLK#
0_0402_5%

CK_MCH

1
R51
CK_MCH#
1
R52

2 CLK_MCH_BCLK
0_0402_5%
2 CLK_MCH_BCLK#
0_0402_5%

CK_ITP

2 CLK_CPU_XDP
0_0402_5%
2 CLK_CPU_XDP#
0_0402_5%

CPUCLKT1LP

11

CPUCLKC1LP

10

CPUCLKT0LP

14

CPUCLKC0LP

13

X1
X2
CPUCLKT2_ITP/SRCCLKT10LP

6

CPUCLKC2_ITP/SRCCLKC10LP

5

USB_48MHz/FSLA

45

FSLB/TEST_MODE/24Mhz

23

H_STP_PCI#

SRCCLKT9LP

3

SRCCLKC9LP

2

REF0/FSLC/TEST_SEL
PCICLK4/FCTSEL1

CLKREQ9#

72

SEL_48M/PCICLK3

SRCCLKT8LP

70

CK_SRC8

32

SEL_24M/PCICLK2

SRCCLKC8LP

69

CK_SRC8#

27

SEL_PCI6/PCICLK1

CLKREQ8#

71

CLKREQB#

SEL_PCI5
1
R462

22

SRCCLKT7LP

66

SEL_PCI5/REF1
SRCCLKC7LP

67

DOCTT

43

DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1

38

DOCTC

44

DOTC_96MHz/27MHz_spread

63

ITP_EN
1
R458

37

ITP_EN/PCICLK_F0

2
0_0402_5%
DREFCLK#
2
0_0402_5%

1
R486
1
R489

CLK_PCI_ICH
2
33_0402_5%

39

VTT_PWRGD#/PD

SRCCLKT6LP
SRCCLKC6LP

64

CLKREQ6#

62

SRCCLKT5LP

60

SRCCLKC5LP

61

1
R491
0_0402_5%

2

MCH_CLKSEL2 <9>

R488
1K_0402_5%

2

ICH_SMBDATA

<6,15,16,22,24> ICH_SMBDATA

17
4

CLK_Rc

@ R495

Pin 43/44,47/48 function select

Pin28/29 function select
+3VS

CLK_Rf

+3VS

+3VS
1

SRCCLKT4LP
SRCCLKC4LP

59

CLKREQ4#

57

1
R64
CK_SRC4#
1
R65
CLKREQC#

SRCCLKT3LP

55

CK_SRC3

SRCCLKC3LP

56

GNDCPU

CLKREQ3#/PCICLK5

28

21

GNDREF

SRCCLKT2LP

52

31

GNDPCI

SRCCLKC2LP

53

35

GNDPCI

CLKREQ2#

26

42

GND48

SRCCLKT1LP

50

68

GNDSRC

SRCCLKC1LP

51

CLKREQ1#

46

LCD100/96/SRC0_TLP

47

LCD100/96/SRC0_CLP

48

2
2

10K_0402_5%

CLK_CPU_XDP# <6>

CLK_PCIE_WAN <24>

R506
300_0402_5%

2

<24>

CLK_48M_SD

1 2

0 DOT96/LCD100
1 27M/SRC0

+3VS

CLK_48M_SD <25>

33_0402_5%

R532
10K_0402_5%

SEL_48M

DB@ 33_0402_5%
CLK_DEBUG_PORT
1
CLK_DEBUG_PORT <24>
2 CLK_MCH_3GPLL
0_0402_5%
2 CLK_MCH_3GPLL#
0_0402_5%
R483 2

1
R66
CK_SRC3#
1
R67
PCICLK5
2
R477
CK_SRC2
1
R68
CK_SRC2# 1
R69

CLK_MCH_3GPLL <9>

SEL_48M:
CLK_MCH_3GPLL# <9>

CLKREQC#
<9>
10K_0402_5%
1
+3VS
2 CLK_PCIE_ICH
CLK_PCIE_ICH <22>
0_0402_5%
2 CLK_PCIE_ICH#
CLK_PCIE_ICH# <22>
0_0402_5%
1 CLK_PCI_TPM
33_0402_5%
2 CLK_PCIE_LAN
0_0402_5%
2 CLK_PCIE_LAN#
0_0402_5%

B

R501
10K_0402_5%
@

Pin5/6 function select

CLK_PCI_TPM <32>

0 CLKREQ7 ,
1 48MHz output

Pin45 function select

+3VS

CLK_PCIE_LAN <28>

SEL_24M

R505
10K_0402_5%

CLK_PCIE_LAN# <28>

SEL_PCI5
73
74
75
76

THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD

CK_SRC0

1
R71
CK_SRC0# 1
R72

DREF_SSCLK
2
0_0402_5%
DREF_SSCLK#
2
0_0402_5%

R499
10K_0402_5%

ITP_EN
R500
10K_0402_5%
@

DREF_SSCLK

<9>

A

DREF_SSCLK# <9>

ITPEN:

*

C

Pin38 function select

+3VS

SEL_PCI5/6: 0 CLKREQ5/6#,
1 PCICLK5/6

0 SRC10 Pair ,
1 CPU_ITP Pair

SEL_24M:

0 Test mode ,
1 24MHz

Compal Electronics, Inc.(KunShan)

J1
NO SHORT PADS

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

CLK_PCIE_MINI# <24>

ICS9LPRS325CKLFT_MLF72

FCTSEL1:

CLK_PCIE_WAN

CLK_PCIE_MINI <24>

2

2

R504

1

CLK_ENABLE#

SEL_PCI6

CLK_CPU_XDP <6>

Clock Generator

2

A

FCTSEL1

1

R503
10K_0402_5%
@

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

1

R498
10K_0402_5%
2

1
R497
10K_0402_5%
@

1

+3VS

R502
10K_0402_5%
DB@

1
R459

CK_SRC4

15

1

2

0_0402_5%

GNDSRC

10K_0402_5%
1

ICS_48MHz

R476
PCICLK6 2

SMBDAT

CLK_MCH_BCLK <9>
CLK_MCH_BCLK# <9>

CLKREQB#

29

SMBCLK

CLK_CPU_BCLK# <6>

2 CLK_PCIE_MINI
0_0402_5%
2 CLK_PCIE_MINI#
0_0402_5%

R463
2

58

2

16

CLK_CPU_BCLK <6>

2 CLK_PCIE_WAN#
CLK_PCIE_WAN# <24>
1 0_0402_5%
+3VS
10K_0402_5%
CLKREQA#
<24>

1
R62
1
R63

CLKREQ5#/PCICLK6

GND

1
CPU_BSEL2

ICH_SMBCLK

<6,15,16,22,24> ICH_SMBCLK

CK_SRC9#
1
R562
R448

33

1

<7>

1

2
R100
CLK_CPU_XDP# 2
R101

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

2
R102
CLK_PCIE_WAN# 2
R103
CLK_PCIE_MINI 2
R104
CLK_PCIE_MINI# 2
R105
CLK_MCH_3GPLL 2
R107
CLK_MCH_3GPLL#2
R106
DREF_SSCLK
2
R109
DREF_SSCLK#
2
R108
DREFCLK
2
R111
DREFCLK#
2
R110
CLK_PCIE_ICH
2
R113
CLK_PCIE_ICH# 2
R112
CLK_PCIE_LAN
2
R115
CLK_PCIE_LAN# 2
R114

<22>

0_0402_5%
2 CLK_PCIE_WAN

CLKREQA#

34

9
R482
1K_0402_5%

1
R53
CK_ITP#
1
R54
R55
CK_SRC9
1

1
R474
SEL_48M
1
R469
SEL_24M
1
R475
SEL_PCI6
1
R493

CLK_ENABLE#

<46> CLK_ENABLE#

FSLC

CLK_CPU_XDP

D

2
0.1U_0402_16V4Z

H_STP_PCI#

VDD48

41

1
C415

25

+VCCP

R487
8.2K_0402_5%
2
1

1
@ 49.9_0402_1%
1
@ 49.9_0402_1%

+3VS

PCI_SRC_STOP#

VDDREF

2

FSLB
<7>

2
R22
2
R21

CLK_PCI_PCM
33_0402_5%
CLK_PCI_EC
33_0402_5%
CLK_PCI_USB
33_0402_5%
CLK_PCI_SIO
33_0402_5%

<25> CLK_PCI_PCM

R460
1K_0402_5%

VDDCPU

20

CLK_14M_ICH
2
33_0402_5%

<22> CLK_14M_ICH

+VCCP

12

19

<22> CLK_48M_ICH

R450
1K_0402_5%

1

22P_0402_50V8J
2
<27> CLK_48M_USB

CLK_Ra

2
R96
CLK_CPU_BCLK# 2
R97
CLK_MCH_BCLK 2
R98
CLK_MCH_BCLK# 2
R99

1

2

R443
1K_0402_5%

2

14.31818MHZ_20P_6X1430004201
Y1

VDDPCI
VDDPCI

2

C396
1

C399

30
36

2 +CK_VDD_REF 18
0.1U_0402_16V4Z
2 +CK_VDD_48 40
0.1U_0402_16V4Z

1

2

2

1
R447
0_0402_5%

CLK_Rd
MCH_CLKSEL0 <9>

C397

22P_0402_50V8J
1

1
CPU_BSEL0

2

1

<7>

C395
1

C394
0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805
1
49
54
65

@
R439
56_0402_5%
2

2

CLK_CPU_BCLK

1

+CK_VDD_DP

+VCCP

1

1

C393
0.1U_0402_16V4Z

+CK_VDD_REF

+CK_VDD_MAIN1

C

2

L4

CLK_Re

R442
8.2K_0402_5%
FSLA 2
1

1

C392
0.1U_0402_16V4Z

1_0805_1%
1
2 +CK_VDD_48
R431
2.2_0805_1%

U46

667MHz

2

1

*(Default)

Stuff

10U_0805_10V4Z

2

CPU Driven

2

1

C391

0.1U_0402_16V4Z

2

100

2

1
2
+3VS
FBMA-L11-201209-221LMA30T_0805 1

2

1

166

10U_0805_10V4Z

2

C385

1

1

+CK_VDD_DP

L19
1

C384

2

1

1

2

L14

FSLC

0

2

+CK_VDD_MAIN1

4

3

2

Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
5
1

Rev
X 0.5
of

53

4

K3
H2
K2
J3
L5

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

L2
V4

ADSTB0#
ADSTB1#

C

H_ADSTB#0
H_ADSTB#1

<5> CLK_CPU_BCLK
<5> CLK_CPU_BCLK#

<9>
<9>
<9>

R519
+VCCP

1

2

56_0402_5%

<9>
<9>
<9>

H_ADS#
H_BNR#
<9> H_BPRI#
H_BR0#
<9> H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
<9> H_LOCK#
<9> H_RESET#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

F3
F4
G3
G2

<9> H_RS#[0..2]

<9> H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
<22> XDP_DBRESET#
<9>
H_DBSY#
<21> H_DPSLP#
<21,46> H_DPRSTP#
<9> H_DPWR#

B

<46> H_PROCHOT#

2
2

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

@ 1K_0402_5%
51_0402_5%

In order to for Yonah B-0 silicon to boot,
due to issue in the reset sequence. needed
for processor.
<9,21> H_THERMTRIP#

BCLK0
BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

H_THERMDA
H_THERMDC
H_THERMTRIP#

DATA GROUP

HOST CLK

CONTROL

RS0#
RS1#
RS2#
TRDY#

AD4
AD3
AD1
AC4

BPM0#
BPM1#
BPM2#
BPM3#

XDP_DBRESET# C20
H_DBSY#
E1
H_DPSLP#
B5
H_DPRSTP#
E5
H_DPWR#
D24
XDP_BPM#4 AC2
XDP_BPM#5 AC1
H_PROCHOT# D21

<21> H_PWRGOOD
<9,21> H_CPUSLP#

R521 1
R522 1

A22
A21

ADDR GROUP

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6

MISC

THERMAL
DIODE

DINV0#
DINV1#
DINV2#
DINV3#

J26
M26
V23
AC20

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

H23
M24
W24
AD23
G22
N25
Y25
AE24

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

A6
A5
C4
B3
C6
B4

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

STPCLK#
SMI#

D5
A3

H_STPCLK#
H_SMI#

LEGACY CPU

THERMDA
THERMDC
THERMTRIP#

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+3VS
R507
XDP_DBRESET#_R

ITP-XDP Connector
JP2
XDP_BPM#5
XDP_BPM#4
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0

R514
H_PWRGOOD 2
1H_PWRGOOD_R
1K_0402_5%
+VCCP
2
1
C401 0.1U_0402_16V4Z
<5,15,16,22,24> ICH_SMBDATA
<5,15,16,22,24> ICH_SMBCLK

ICH_SMBDATA
ICH_SMBCLK
XDP_TCK

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

1

+VCCP

@

This shall place near CPU
R508 1
56_0402_5%
2

XDP_TDI

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

@ 1K_0402_5%
2

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

56_0402_1%

XDP_TMS

R509

1

2

XDP_TDO

R510 1

2

56_0402_5%

XDP_BPM#5

R511 1

2

56_0402_5%

XDP_TRST#

R512 1

2

56_0402_5%

XDP_TCK

R513 1

2

56_0402_5%

D

CLK_CPU_XDP
CLK_CPU_XDP#

CLK_CPU_XDP <5>
CLK_CPU_XDP# <5>
1K_0402_1%
+VCCP
H_RESET#_R
1 R515
2 H_RESET#
XDP_DBRESET#_R 2
1 XDP_DBRESET#
R516
XDP_TDO
200_0402_1%
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
1 R517
2 0_0402_5%

SAMTE_BSH-030-01-L-D-A

C

Thermal Sensor G781F
+3VS

1

C403

C402

R518
10K_0402_5%
@

0.1U_0402_16V4Z

H_THERMDA

2

1
U2

2200P_0402_50V7K

<24,33,36,39> SMB_EC_CK2
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

<9>
<9>
<9>
<9>

H_DSTBN#[0..3]

2

D+

VDD1

H_THERMDC

3

D-

ALERT#

6

SMB_EC_CK2

8

SCLK

THERM#

4

7

SDATA

GND

5

2

<24,33,36,39> SMB_EC_DA2

SMB_EC_DA2

1

THERM#

G781F_SOP8

Place U2 near the top and LCD side
for using it's local thermal sensor to
monitor the LCD back side temperature

<9>

H_DSTBP#[0..3] <9>

B
+5VS

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

A24
A25
C7

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

1

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

YONAH-ULV

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

<21>
<21>
<21>
<21>
<21>
<21>

H_STPCLK#
H_SMI#

<21>
<21>

+5VS

1
R523

2
@10K_0402_5%

1
C404
10U_0805_10V4Z
2
D1

1 C405
0.1U_0402_16V4Z
2

CH355PT_SOD323

JP3
1
2
3

<33> FAN_SPEED1
1
C406

YONAH-ULV_FCBGA479~D

1
R524
FAN_PWM

+3VS
<33>

2
1000P_0402_50V7K

1
2
3

MOLEX_53780-0310
2
8.2K_0402_5%

R525
1

2

D

S

Q1
FDN359AN_NL_SOT23

2
G

100_0402_1%

+3VS

1

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

1

3

J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1

2

<9>

1

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
<9> H_REQ#[0..4]

H_ADSTB#0
H_ADSTB#1

H_D#[0..63]

2

D

<9>
<9>

3

U8A

2

5
<9> H_A#[3..31]

1

+VCCP

A

A

1

R526
1K_0402_5%

1

2

R527
56_0402_5%

PROCHOT#

PROCHOT#

<33>

1

R954
2

C

3

E
H_PROCHOT#

Compal Electronics, Inc.(KunShan)

Q2
2SC2411KT146_SOT23

2
B

2

68_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Yonah1/2-GTL/ITP
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
6

Rev
X 0.5
of

53

4

3

+VCCP

R530
100_0402_1%
1
2

2

V_CPU_GTLREF

+VCC_CORE

D

VCCSENSE

1

R531
100_0402_1%
1
2

+1.5VS

C407
0.01U_0402_16V7K

R529
1K_0402_1%

VSSSENSE

2

R528
2K_0402_1%

Close to CPU pin AD26
within 500mils.

1

2

C408
10U_0805_10V4Z

1

Length match within 25 mils
The trace width 18 mils space
<46> VCCSENSE
7 mils
<46> VSSSENSE

+VCC_CORE

VCCSENSE
VSSSENSE

B26

VCCA

K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

H_PSI#

AE6

PSI#

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD6
AF5
AE5
AF4
AE3
AF2
AE2

VID0
VID1
VID2
VID3
VID4
VID5
VID6

2

Close to CPU pin
within 500mils.

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

133

0

0

1

H_PSI#
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD26

V_CPU_GTLREF
C

166

0

1

1

<5> CPU_BSEL0
<5> CPU_BSEL1
<5> CPU_BSEL2

R536
54.9_0402_1%
2
1

R535
27.4_0402_1%
2
1

R534
54.9_0402_1%
2
1

GTLREF

B22
B23
C21

BSEL0
BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

R26
U26
U1
V1

COMP0
COMP1
COMP2
COMP3

E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25

B

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

YONAH-ULV

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

+VCC_CORE

R533
27.4_0402_1%
2
1

U8C

AF7
AE7

1

<46>
<46>
<46>
<46>
<46>
<46>
<46>

1

U8B
VCCSENSE
VSSSENSE

+VCCP

<46>

2

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUNG, RESERVED SIGNALS AND NC

5

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7

YONAH-ULV_FCBGA479~D

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH-ULV

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

D

C

B

YONAH-ULV_FCBGA479~D

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Yonah2/2-PWR/GND
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
7
1

Rev
X 0.5
of

53

5

4

3

2

1

+VCC_CORE

D

1
Place these capacitors on L8
(North side,Secondary Layer)

2

1
C409
22U_0805_6.3V6M

1
C410
22U_0805_6.3V6M

2

2

LV@
C411
22U_0805_6.3V6M

1

2

1

LV@
C412
22U_0805_6.3V6M

2

LV@
C413
22U_0805_6.3V6M

1 LV@
C414
22U_0805_6.3V6M
2

1

1

1

2

D

1
C418
@ 22U_0805_6.3V6M
2

C431
@ 22U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(South side,Secondary Layer)

2

1
C419
22U_0805_6.3V6M

1
C420
22U_0805_6.3V6M

2

2

LV@
C421
22U_0805_6.3V6M

1

2

1

LV@
C422
22U_0805_6.3V6M

2

LV@
C423
22U_0805_6.3V6M

2

LV@
C424
22U_0805_6.3V6M

2

1
C428
@ 22U_0805_6.3V6M

2

C432
@ 22U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

2

1
C429
22U_0805_6.3V6M

2

1
C430
22U_0805_6.3V6M

2

LV@
C433
22U_0805_6.3V6M

1

1 LV@
C434
22U_0805_6.3V6M

2

2

1
C425
@ 22U_0805_6.3V6M

2

1
C426
@ 22U_0805_6.3V6M
2

1
C427
@ 22U_0805_6.3V6M

2

C458
@ 22U_0805_6.3V6M

Mid Frequence Decoupling

C

C

+VCC_CORE

1
Place these capacitors on L8
(South side,Secondary Layer)

2

1
C435
22U_0805_6.3V6M
2

1
C436
22U_0805_6.3V6M

2

LV@
C439
22U_0805_6.3V6M

1

2

1

1

LV@
C440
22U_0805_6.3V6M

2

C437
@ 22U_0805_6.3V6M

2

1
C438
@ 22U_0805_6.3V6M

2

1
C444
@ 22U_0805_6.3V6M
2

C445
@ 22U_0805_6.3V6M

+VCC_CORE
330U_D2E_2.5VM_R9

South Side Secondary

North Side Secondary
1

LV@

C442

330U_D2E_2.5VM_R9

1

1

+

C443

2

+

C446

LV@
C441

2

2

B

+

1
+

ESR <= 1.5m ohm
Capacitor > 1980uF

2

B

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

+VCCP

1
@ C447
330U_D2E_2.5VM_R9

1

1

1

1

1

1

+
2

2

C448
0.1U_0402_10V6K

C449
0.1U_0402_10V6K

2

2

C450
0.1U_0402_10V6K

2

C451
0.1U_0402_10V6K

2

C452
0.1U_0402_10V6K

2

Place these inside
socket cavity on L8
(North side
C453
0.1U_0402_10V6K Secondary)

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Yonah bypass
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
8
1

Rev
X 0.5
of

53

HADSTB#0
HADSTB#1

B9
C13

H_ADSTB#0
H_ADSTB#1

HCLKN
HCLKP

AG1
AG2

CLK_MCH_BCLK#
CLK_MCH_BCLK

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

K4
T7
Y5
AC4
K3
T6
AA5
AC5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

J7
W8
U3
AB10

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

HRS0#
HRS1#
HRS2#

B4
E6
D6

H_RS#0
H_RS#1
H_RS#2

H_ADSTB#0
H_ADSTB#1

<6>
<6>

CLK_MCH_BCLK# <5>
CLK_MCH_BCLK <5>
H_DSTBN#[0..3] <6>

H_DSTBP#[0..3] <6>

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RS#[0..2]

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6,21>

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

AE35
AF39
AG35
AH39

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

<22>
<22>
<22>
<22>

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AC35
AE39
AF35
AG39

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

<22>
<22>
<22>
<22>

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AE37
AF41
AG37
AH41

DMITXN0
DMITXN1
DMITXN2
DMITXN3

<22>
<22>
<22>
<22>

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

AC37
AE41
AF37
AG41

DMITXP0
DMITXP1
DMITXP2
DMITXP3

AY35
AR1
AW7
AW40

SM_CK0
SM_CK1
SM_CK2
SM_CK3

<15>
<15>
<16>
<16>

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

AW35
AT1
AY7
AY40

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

AU20
AT20
BA29
AY29

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

AW13
AW12
AY21
AW21

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

M_OCDOCMP0
M_OCDOCMP1

AL20
AF10

SM_OCDCOMP0
SM_OCDCOMP1

BA13
BA12
AY20
AU21

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

<15>
<15>
<16>
<16>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

<15>
<15>
<16>
<16>
R537
1
1
R538

2
2

M_ODT0
M_ODT1
M_ODT2
M_ODT3
80.6_0402_1%

V_DDR_MCH_REF
PM_BMBUSY#
<22> PM_BMBUSY#
EC_EXTTS#0
<15,16,33> EC_EXTTS#0
PM_EXTTS#1
R541
0_0402_5%
1
2
<22,46> H_DPRSLPVR
H_THERMTRIP#
<6,21> H_THERMTRIP#
PWROK
<22,33,34> PWROK
PLTRST_R#
2
1
<18,20,22,24,28,32,33,35> PLT_RST#
R542
100_0402_1%

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#
ICH_SYNC#

1

1

1
R545
1K_0402_1%
VREF
1
C454
0.1U_0402_16V4Z
2

221_0603_1%

R550
2

H_SWNG0

D_REF_SSCLKN
D_REF_SSCLKP

C40
D41

DREF_SSCLK#
DREF_SSCLK

CLK_REQ#

H32

CLKREQC#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

<5>
<5>
<5>
<13>
<13>
<13>
D

<13>
<13>
<13>
<13>
<13>
<13>

CLK_MCH_3GPLL <5>
CLK_MCH_3GPLL# <5>
DREFCLK#
DREFCLK

<5>
<5>

DREF_SSCLK# <5>
DREF_SSCLK <5>
CLKREQC#

<5>

C

B

U1

Buffer@
1
C932
10U_1206_6.3V7K
M_OCDOCMP0
M_OCDOCMP1

VREF

1

VIN

2
3
4

2

VCNTL

6

GND

NC

5

VREF

NC

7

VOUT

NC

8

TP

9

+5VALW
2

1

Buffer@
C680
1U_0603_10V4Z

G2992F1U_SO8
Buffer@
V_DDR_MCH_REF
1

R547
@ 40.2_0402_1%
2
1

+VCCP

D_REF_CLKN
D_REF_CLKP

DREFCLK#
DREFCLK

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
T1
T2
CFG5
T3
CFG7
T4
CFG9
T5
T6
CFG12
CFG13
T7
T8
CFG16
T9
CFG18
CFG19
CFG20

+1.8V

R546
@ 40.2_0402_1%
2
1

V_DDR_MCH_REF
1
2
0_0805_5%
1.8_divider@

AG33 CLK_MCH_3GPLL
AF33 CLK_MCH_3GPLL#

Layout Note:
Route as short
as possible

<6>

<15,16> V_DDR_MCH_REF

221_0603_1%

2

R549

100_0402_1%

G28
F25
H26
G6
AH33
AH34

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
PAD
CFG4
PAD
CFG5
CFG6
PAD
CFG7
CFG8
PAD
CFG9
CFG10
PAD
CFG11
PAD
CFG12
CFG13
CFG14
PAD
CFG15
PAD
CFG16
CFG17
PAD
CFG18
CFG19
CFG20

2

C931
10U_1206_6.3V7K
Buffer@

+3VS
H_SWNG1

1

2

0.1U_0402_16V4Z
C456

1
R555

100_0402_1%

2

2

1

0.1U_0402_16V4Z
C455

1

100_0402_1%

2

R554

1

2

0.1U_0402_16V4Z

H_VREF

C457

200_0402_1%

1
R551
2

SM_VREF0
SM_VREF1

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

A27
A26

SM_RCOMPN
SM_RCOMPP

AK1
AK41

CALISTOGA_FCBGA1466~D

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

R446

+VCCP

1

AV9
AT9

K28

<20> MCH_ICH_SYNC#

+VCCP

R556

SMRCOMPN
SMRCOMPP

80.6_0402_1%

+1.8V

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

2

M_ODT0
M_ODT1
M_ODT2
M_ODT3

CLK

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

<15>
<15>
<16>
<16>

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

CALISTOGA_FCBGA1466~D

A

CFG

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

<15>
<15>
<16>
<16>

+1.8V

<6>
<6>
<6>
<6>

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

<22>
<22>
<22>
<22>

NC

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

R544
24.9_0402_1%
2
1

R543
24.9_0402_1%
2
1

HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

H_REQ#[0..4] <6>

D8
G8
B8
F8
A8

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

Description at page13.

U3B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

2

R540
54.9_0402_1%
2
1

R539
54.9_0402_1%
2
1

J13
H_VREF
K13
H_XRCOMP E1
H_XSCOMP E2
H_YRCOMP Y1
H_YSCOMP U1
H_SWNG0
E4
H_SWNG1 W1

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

PM

H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

DDR MUXING

+VCCP

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

1

DMI

C

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

2

H_A#[3..31] <6>

U3A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

D

B

3

2
1
R548
1K_0402_1%

H_D#[0..63]

HOST

<6>

4

RESERVED

5

Stuff R546 & R547 for A1 Calistoga

R552
1
10K_0402_5%

EC_EXTTS#0

2

PM_EXTTS#1

R553
2
1
@10K_0402_5%

A

Use +1.8V divide voltage for V_DDR_MCH_REF, R545/R548 use 100_0402_1%
Use buffer to generate V_DDR_MCH_REF, R545/R548 use 1K_0402_1%

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Calistoga1/6-GTL/DMIDDRMUX
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
9
1

Rev
X 0.5
of

53

5

4

3

2

1

D

D

<15> DDR_A_DQS[0..7]

C

<15> DDR_A_DQS#[0..7]

<15> DDR_A_MA[0..13]

B

<15> DDR_A_CAS#
<15> DDR_A_RAS#
<15> DDR_A_WE#
T10 PAD
T12 PAD

AU12
AV14
BA20

SA_BS0
SA_BS1
SA_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AY13
AW14
AY14
AK23
AK24

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

U3E

Route to a via next to ball

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63]

<15>
<16> DDR_B_BS#0
<16> DDR_B_BS#1
<16> DDR_B_BS#2
<16> DDR_B_DM[0..7]

<16> DDR_B_DQS[0..7]

<16> DDR_B_DQS#[0..7]

<16> DDR_B_MA[0..13]

<16> DDR_B_CAS#
<16> DDR_B_RAS#
<16> DDR_B_WE#
T11 PAD
T13 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

AT24
AV23
AY28

SB_BS0
SB_BS1
SB_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

AR24
AU23
AR27
AK16
AK18

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

DDR SYS MEMORY B

<15> DDR_A_DM[0..7]

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR SYS MEMORY A

U3D
<15> DDR_A_BS#0
<15> DDR_A_BS#1
<15> DDR_A_BS#2

Route to a via next to ball

CALISTOGA_FCBGA1466~D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D[0..63]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

<16>

C

B

CALISTOGA_FCBGA1466~D

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Calistoga2/6-DDRA&B
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
10
1

Rev
X 0.5
of

53

5

4

3

D

<17> LVDSA_D0<17> LVDSA_D1<17> LVDSA_D2-

<17> LVDSB_D0<17> LVDSB_D1<17> LVDSB_D2<17>
<17>
<17>
<17>

+3VS

1
R37

2 LCTLA_CLK
10K_0402_5%

1
R42

2 LCTLB_DATA
10K_0402_5%

1
R586

2 LCD_I2C_CLK
10K_0402_5%

1
R585

2 LCD_I2C_DAT
10K_0402_5%

LVDSCLKA+
LVDSCLKALVDSCLKB+
LVDSCLKB-

<17> GM_PWM
<17,33> ENABLT

<17>

ENVDD

<17> LCD_I2C_CLK
<17> LCD_I2C_DAT
ENVDD 2
R5581
R559

H27
H28

SDVOCTRL_DATA
SDVOCTRL_CLK

LVDSA_D0+
LVDSA_D1+
LVDSA_D2+

B37
B34
A36

LA_DATA0
LA_DATA1
LA_DATA2

LVDSA_D0LVDSA_D1LVDSA_D2-

C37
B35
A37

LA_DATA#0
LA_DATA#1
LA_DATA#2

LVDSB_D0+
LVDSB_D1+
LVDSB_D2+

F30
D29
F28

LB_DATA0
LB_DATA1
LB_DATA2

LVDSB_D0LVDSB_D1LVDSB_D2-

G30
D30
F29

LB_DATA#0
LB_DATA#1
LB_DATA#2

LVDSCLKA+
LVDSCLKALVDSCLKB+
LVDSCLKB-

A32
A33
E26
E27

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

GM_PWM
ENABLT
LCTLA_CLK
LCTLB_DATA
LCD_I2C_CLK
LCD_I2C_DAT
LVDD_EN
1
0_0402_5%
LIBG
2
1.5K_0402_1%

D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

A16
C18
A19

TVDAC_A
TVDAC_B
TVDAC_C

+1.5VS

B

<19>

CRT_G

<19>

CRT_R

R560 2
R561 2
2
R562
2
R563
2
R564

39_0402_5%
39_0402_5%

1
1

1
150_0402_5%
1
150_0402_5%
1
150_0402_5%
1
R565

2

TV_IRTNA
TV_IRTNB
TV_IRTNC

J29
K30

TV_DCONSEL1
TV_DCONSEL0

C26
C25

DDCCLK
DDCDATA

H23
G23
E23
D23
C22
B22
A21
B21

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

J22

CRT_IREF

CRT

<19> CRT_VSYNC
<19> CRT_HSYNC
<19>
CRT_B

3VDDCCL
3VDDCDA

TV_IREF

TV

<19> 3VDDCCL
<19>
3VDDCDA

J20
B16
B18
B19

EXP_COMPI
EXP_COMPO

LVDS

<17> LVDSB_D0+
<17> LVDSB_D1+
<17> LVDSB_D2+

SDVO_SDAT
SDVO_SCLK

226_0402_1%

PCI-EXPRESS GRAPHICS

<17> LVDSA_D0+
<17> LVDSA_D1+
<17> LVDSA_D2+

C

PEGCOMP trace width
and spacing is 18/25 mils.

U3C
<18> SDVO_SDAT
<18> SDVO_SCLK

2

D40
D38

PEGCOMP

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

SDVO_RSDVO_GSDVO_BSDVO_CLK-

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

SDVO_R+
SDVO_G+
SDVO_B+
SDVO_CLK+

SDVOB_INT-

R557
+1.5VS_PCIE
24.9_0402_1%
1
2

SDVOB_INT-

SDVOB_INT+

1

D

<18>

SDVOB_INT+ <18>

C

C460
1

0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
2
C461
1
2
C462 0.1U_0402_16V4Z
1
2
C463 0.1U_0402_16V4Z

SDVOB_RSDVOB_GSDVOB_BSDVOB_CLK-

<18>
<18>
<18>
<18>

C464 0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
C465
1
2
C466
1
2
C467 0.1U_0402_16V4Z

SDVOB_R+
SDVOB_G+
SDVOB_B+
SDVOB_CLK+

<18>
<18>
<18>
<18>

B

CALISTOGA_FCBGA1466~D

R565 change to 226ohm
required by Motion

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Calistoga3/6-VGA/LVDS
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
11
1

Rev
X 0.5
of

53

5

4

10U_0805_6.3V6M

220U_D2_4VM

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

B26
C39
AF1

VCCA_LVDS
VSSA_LVDS

A38
B39

VCCA_MPLL

AF2

VCCA_TVBG
VSSA_TVBG

H20
G20

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

E19
F19
C20
D20
E20
F20

+1.5VS

VCCD_HMPLL0
VCCD_HMPLL1

AH1
AH2

+1.5VS

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

A28
B28
C28

VCCD_TVDAC
VCCDQ_TVDAC

D21
H19

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

C482

1

1

2

2

1

1

2

2

D

+2.5VS

close pin B30

BLM18PG181SN1D_0603
D17
1

2 +VCCP
+2.5VS

CH751H-40PT_SOD323

2

1

+2.5VS
C483
0.01U_0402_16V7K

2

+1.5VS

close pin G41

C

+1.5VS

+1.5VS

A23
B23
B25
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

2

2

1

+3VS
1

1

2

2

1

1

2

2

C487
10U_0805_6.3V6M

C494
10U_0805_6.3V6M

L7
+1.5VS

+1.5VS

+1.5VS

1

2

1
+
2

L8
+1.5VS

1

2

1

2

+1.5VS

+
2

1

2

L6

+1.5VS_DPLLB

MBK1608301YZF_0603
1
2

1

CALISTOGA_FCBGA1466~D

L5
+1.5VS_HPLL
MBK1608301YZF_0603

+1.5VS_DPLLA

MBK1608301YZF_0603
1
2

C490
0.1U_0402_16V4Z

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

2

1

2

2

1

C491
22U_0805_6.3V6M

VCCHV0
VCCHV1
VCCHV2

2

+1.5VS_MPLL

1

1

0.1U_0402_16V4Z

P O W E R

1
C480
0.1U_0402_16V4Z

E21
F21
G21

1

+2.5VS
0.1U_0402_16V4Z

2

R566
L2
+1.5VS
BLM18PG600SN1D_0603
0.5_0805_1%
1
2 3GRLL_R2
1

C473

2

L3
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

+1.5VS_3GPLL

C472
4.7U_0805_10V4Z

+1.5VS

C476
0.1U_0402_16V4Z

2

C481
0.1U_0402_16V4Z

+1.5VS_3GPLL
+2.5VS

1 C471

C475
10U_1206_6.3V6M

2

1 C470

C474
0.1U_0402_16V4Z

+ C469

C479
0.022U_0402_16V7K

VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

1

1

2
B

+1.5VS_MPLL

MBK1608301YZF_0603
1
2

1

2

1

2

C502
0.1U_0402_16V4Z

+1.5VS

AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12

AC33
G41
H41

W=40 mils

1

BLM21PG600SN1D_0805

22U_0805_6.3V6M

2

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

L1
10U_0805_6.3V6M

C501

1

C498
0.47U_0603_10V7K
MCH_AB1

2

MCH_D2

AB41
AJ41
L41
N41
R41
V41
Y41

placed near GMCH

+1.5VS_PCIE

C503
0.1U_0402_16V4Z

1
C497
0.22U_0603_10V7K

B

C495
0.22U_0603_10V7K

2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

2

C504
0.1U_0402_16V4Z

1

C492
0.47U_0603_10V7K

MCH_A6

1

+2.5VS
C468Should be
0.1U_0402_16V4Z

C499
470U_D2_2.5VM

C

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

1

+2.5VS

C500

2

H22
B30
C30
A30

470U_D2_2.5VM

2

1

VCC_SYNC

C486
0.1U_0402_16V4Z

1

C485
2.2U_0805_16V4Z

2

4.7U_0805_10V4Z

C484

330U_D2E_2.5VM_R9

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

C493
0.1U_0402_16V4Z

+

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

C496
0.1U_0402_16V4Z

1
C477

2

U3H

+VCCP

D

3

1

2

A

A

Compal Electronics, Inc.(KunShan)

Title

Calistoga4/6-PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
12
1

Rev
X 0.5
of

53

5

4

3

2

1

Strap Pin Table
CFG[3:17] have internal pull up

10U_0805_6.3V6M
C

220U_D2_4VM

330U_D2E_2.5VM_R9

C533

1
C524
+

1
C525
+

2

2

1
+

B

2
330U_D2E_2.5VM_R9

+VCCP
+1.8V

CALISTOGA_FCBGA1466~D

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AR6
AP6
AN6
AL6
AK6
AJ6
AV1 VCCSM_LF2
AJ1 VCCSM_LF1

1

2

C536
0.47U_0603_10V7K

VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110

C535
0.47U_0603_10V7K

M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16

1

2

Place near pin AV1 & AJ1

1

2

C510
0.47U_0603_10V7K

1

2

= 667MT/s FSB
= 533MT/s FSB

CFG5

0 = DMI x 2
1 = DMI x 4 *(Default)

CFG7

0 = Reserved
1 = Mobile Yonah CPU *(Default)

CFG9

0 = Lane Reversal Enable
1 = Normal Operation
(Default)

*

CFG[11,10]
00
01
10
11

CFG[13:12]
+1.8V

2

1

2

1

2

1
C517

1

2

=
=
=
=

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation *(Default)

CFG16

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled *(Default)

CFG18

0 = 1.05V
1 = 1.5V

CFG19

0 = Normal Operation * (Default)
1 = DMI Lane Reversal Enable

*(Default)

0 = No SDVO Device Present
(Default)

SDVO_CTRLDATA

1 = SDVO Device Present

*

0 = Only PCIE or SDVO is
operational. *(Default)
1 = PCIE/SDVO are operating
simu.

CFG20
(PCIE/SDVO select)

C

1

2

Place near pin BA23

C531

D

Reserved

Place near pin AT41 & AM41

C516

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

C509
0.47U_0603_10V7K

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

011
001

CFG[2:0]

0.1U_0402_16V4Z

2

VCCSM_LF4
VCCSM_LF5

0.1U_0402_16V4Z

2

P O W E R

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

0.1U_0402_16V4Z

2

1

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

C515

C519 1

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

0.1U_0402_16V4Z

C518 1

C520
1U_0603_10V4Z

10U_0805_6.3V6M

AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19

C514

no caps required by the
Rev1.501 check list

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

C526
0.47U_0603_10V7K

2

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

CFG[19:18] have internal pull down

+1.8V

U3G

1

C532

1

C527

<9>

CFG5

<9>

CFG7

<9>

CFG9

<9>

CFG12

<9>

CFG13

<9>

CFG16

1
+

R567

1

2 @

2.2K_0402_5%

R568

1

2 @

2.2K_0402_5%

R569

1

2 @

2.2K_0402_5%

R570

1

2 @

2.2K_0402_5%

R571

1

2 @

2.2K_0402_5%

R572

1

2 @

2.2K_0402_5%

2
2
2
10U_0805_6.3V6M
@ 330U_D2E_2.5VM_R9
10U_0805_6.3V6M
B

+3VS

C534

2

1

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

P O W E R

2

1

C513
0.22U_0603_10V7K

1

C512
0.22U_0603_10V7K

C511
0.22U_0603_10V7K

D

AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18

+VCCP

+1.5VS

0.47U_0603_10V7K

U3F

+VCCP

<9>
<9>
<9>

1

CFG18
CFG19
CFG20

R573
R574
R575

1
1
1

2 @1K_0402_5%
2 @1K_0402_5%
2 @1K_0402_5%

2

Place near pin BA15

CALISTOGA_FCBGA1466~D

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Calistoga5/6-PWR/GND
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
13
1

Rev
X 0.5
of

53

5

4

3

2

U3I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34

D

C

B

A

1

U3J

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10

VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

D

C

B

CALISTOGA_FCBGA1466~D

A

CALISTOGA_FCBGA1466~D

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Calistoga6/6-GND
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
14
1

Rev
X 0.5
of

53

5

4

3

2

+1.8V

1

+1.8V
V_DDR_MCH_REF

<10> DDR_A_DQS#[0..7]

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

Add C611, C612 follow Motion's request

+1.8V

2

2

+

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_D21
DDR_A_D17

1
1
C612

2

1
C611

C547

2

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z
C546

2

1

0.1U_0402_16V4Z
C545

C544

2

1

0.1U_0402_16V4Z

C543

2

1

0.1U_0402_16V4Z

C542

2

1

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

C541

2

2.2U_0805_16V4Z

2

1

C540

2.2U_0805_16V4Z

C539

2.2U_0805_16V4Z

1

+1.8V

DDR_A_DQS#2
DDR_A_DQS2

C528

DDR_A_D22
DDR_A_D19

2@220U_D2_4VM

DDR_A_D25
DDR_A_D24
DDR_A_DM3
DDR_A_D27
DDR_A_D30

C

DDR_CKE0_DIMMA

<9> DDR_CKE0_DIMMA

DDR_A_BS#2

<10> DDR_A_BS#2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

<10> DDR_A_BS#0
<10> DDR_A_WE#

+0.9VS

DDR_A_CAS#
DDR_CS1_DIMMA#

<10> DDR_A_CAS#
<9> DDR_CS1_DIMMA#

2

1

2

<9>

M_ODT1

1

DDR_A_D34
DDR_A_D38

2

DDR_A_DQS#4
DDR_A_DQS4

C560

C559

C558

C557

C556

C555

C554

C553

C552

C551

C550

C549

C548

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

M_ODT1

DDR_A_D39
DDR_A_D35
DDR_A_D45
DDR_A_D41

B

DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D52
DDR_A_D53
+0.9VS
RP1
DDR_A_MA8
DDR_A_MA5

RP2
1
2

RP3

4
3

56_0404_4P2R_5% RP4
1
4
4
2
3
3

56_0404_4P2R_5%
1 DDR_A_MA7
2 DDR_A_MA6

RP5 56_0404_4P2R_5% RP6
DDR_A_RAS#
1
4
4
DDR_CS0_DIMMA# 2
3
3

56_0404_4P2R_5%
1 DDR_A_MA12
2 DDR_A_MA9

DDR_A_MA3
DDR_A_MA1

RP7
DDR_A_MA10
DDR_A_BS#0

1
2

56_0404_4P2R_5% RP8
4
4
3
3

1
2

56_0404_4P2R_5% RP10 56_0404_4P2R_5%
4
4
1 DDR_A_MA0
3
3
2 DDR_A_BS#1

RP9
A

4
3

56_0404_4P2R_5%
1 DDR_CKE0_DIMMA
2 DDR_A_BS#2

DDR_A_WE#
DDR_A_CAS#

Layout Note:
Place these resistor
closely JP4,all
trace length Max=1.5"

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D51
DDR_A_D55
DDR_A_D56
DDR_A_D61
DDR_A_DM7
DDR_A_D58
DDR_A_D59

56_0404_4P2R_5%
1 DDR_A_MA4
2 DDR_A_MA2

ICH_SMBDATA
ICH_SMBCLK

<5,6,16,22,24> ICH_SMBDATA
<5,6,16,22,24> ICH_SMBCLK

+3VS
1
C561

RP11 56_0404_4P2R_5% RP12 56_0404_4P2R_5%
M_ODT1
2
3
4
1 M_ODT0
DDR_CS1_DIMMA# 1
4
3
2 DDR_A_MA13

0.1U_0402_16V4Z

2

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

FOX_ASOA426-M2R-TR

SO-DIMM A
REVERSE

DDR_A_DM0
DDR_A_D5
DDR_A_D6

1

2

1

2

D

DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 <9>
M_CLK_DDR#0 <9>

DDR_A_D9
DDR_A_D15

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D20
DDR_A_D16
@ R579
1
DDR_A_DM2

20_0402_5% EC_EXTTS#0

EC_EXTTS#0

<9,16,33>

DDR_A_D18
DDR_A_D23
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D31
DDR_CKE1_DIMMA

C

DDR_CKE1_DIMMA <9>

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_BS#1 <10>
DDR_A_RAS# <10>
DDR_CS0_DIMMA# <9>
M_ODT0

<9>

DDR_A_D36
DDR_A_D33
DDR_A_DM4
DDR_A_D37
DDR_A_D32
DDR_A_D40
DDR_A_D44

B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D46
DDR_A_D48
DDR_A_D49
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <9>
M_CLK_DDR#1 <9>

DDR_A_DM6
DDR_A_D50
DDR_A_D54
DDR_A_D60
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

R578
10K_0402_5%
2
1

DDR_A_D8
DDR_A_D14

Layout Note:
Place near JP4

DDR_A_D7
DDR_A_D1

R577
10K_0402_5%
2
1

DDR_A_D2
DDR_A_D3

D

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

<9,16>

C538

DDR_A_DQS#0
DDR_A_DQS0

<10> DDR_A_MA[0..13]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

V_DDR_MCH_REF

C537

DDR_A_D0
DDR_A_D4

<10> DDR_A_DQS[0..7]

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

0.1U_0402_16V4Z

<10> DDR_A_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_16V4Z

JP4

<10> DDR_A_D[0..63]

56_0404_4P2R_5% RP13 56_0404_4P2R_5%
4
1 DDR_CKE1_DIMMA
3
2 DDR_A_MA11

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

DDRII SO-DIMM A
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
15
1

Rev
X 0.5
of

53

5

4

3

2

+1.8V

<10> DDR_B_DQS#[0..7]
<10> DDR_B_D[0..63]

V_DDR_MCH_REF

Layout Note:
Place near JP5

DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1

Add C619, C625 follow Motion's request

DDR_B_D10
DDR_B_D11

+1.8V

2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D21
DDR_B_D20

1
C625

C619

2

1

0.1U_0402_16V4Z

C572

2

1

0.1U_0402_16V4Z

C571

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C570

2

0.1U_0402_16V4Z

2

1
C569

C568

2

1

0.1U_0402_16V4Z

C567

2

1

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

C566

2

2.2U_0805_16V4Z

C565

2.2U_0805_16V4Z

C564

2.2U_0805_16V4Z

2

1

DDR_B_DQS#2
DDR_B_DQS2

2

DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31

C

<9> DDR_CKE2_DIMMB

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

<10> DDR_B_BS#2

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9VS

2

1

2

<10> DDR_B_CAS#
<9> DDR_CS3_DIMMB#
1

<9>

M_ODT3

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D37
DDR_B_D36

2
C585

C584

C583

C582

C581

C580

C579

C578

C577

C576

C575

C574

C573

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

<10> DDR_B_BS#0
<10> DDR_B_WE#

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D34
DDR_B_D40
DDR_B_D41

B

DDR_B_DM5
DDR_B_D42
DDR_B_D47

+0.9VS

DDR_B_MA1
DDR_B_MA3

RP14
1
2

DDR_B_BS#0
DDR_B_MA10

RP16 56_0404_4P2R_5% RP17 56_0404_4P2R_5%
DDR_B_MA11
1
4
4
1
DDR_CKE3_DIMMB
2
3
3
2

DDR_B_BS#1
DDR_B_MA0

RP18 56_0404_4P2R_5% RP19 56_0404_4P2R_5%
DDR_B_MA5
1
4
4
1
DDR_B_MA8
2
3
3
2

4
3

4
3

RP15 56_0404_4P2R_5%
DDR_B_MA9
1
DDR_B_MA12
2

DDR_B_D48
DDR_B_D53

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D60
DDR_B_D61
DDR_B_DM7
DDR_B_D58
DDR_B_D59

RP20 56_0404_4P2R_5% RP21 56_0404_4P2R_5%
DDR_CS2_DIMMB# 1
DDR_B_MA6
4
4
1
DDR_B_RAS#
DDR_B_MA7
2
3
3
2

<5,6,15,22,24> ICH_SMBDATA
<5,6,15,22,24> ICH_SMBCLK

+3VS

DDR_B_CAS#
DDR_B_WE#

56_0404_4P2R_5% RP28
4
3

1
2

1
C586
0.1U_0402_16V4Z

2

DDR_B_D6
DDR_B_D2

1

2

1

<9,15>

2

D

DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 <9>
M_CLK_DDR#3 <9>

DDR_B_D14
DDR_B_D15

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_D16
DDR_B_D18
@ R634
1
DDR_B_DM2

20_0402_5% EC_EXTTS#0

EC_EXTTS#0

<9,15,33>

DDR_B_D17
DDR_B_D19
DDR_B_D26
DDR_B_D28
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
C

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB <9>

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13

DDR_B_BS#1 <10>
DDR_B_RAS# <10>
DDR_CS2_DIMMB# <9>
M_ODT2

<9>

DDR_B_D33
DDR_B_D32
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

B

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D43
DDR_B_D46
DDR_B_D49
DDR_B_D52
M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2 <9>
M_CLK_DDR#2 <9>

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

QTC_C111A-040SP31

SO-DIMM B
STANDARD

DDR_B_BS#2
DDR_CKE2_DIMMB

R580
1
2
10K_0402_5%

+3VS
A

Compal Electronics, Inc.(KunShan)

56_0404_4P2R_5%

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

V_DDR_MCH_REF

R581

A

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_B_DM0

10K_0402_5%

RP23 56_0404_4P2R_5% RP24 56_0404_4P2R_5%
DDR_B_MA2
1
4
4
1
DDR_B_MA4
2
3
3
2
RP25
56_0404_4P2R_5% RP26 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
DDR_B_MA13
3
4
1
M_ODT3
M_ODT2
1
4
3
2

ICH_SMBDATA
ICH_SMBCLK

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_B_D4
DDR_B_D1

1

DDR_B_D7
DDR_B_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

2

DDR_B_DQS#0
DDR_B_DQS0
D

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C563

DDR_B_D0
DDR_B_D5

<10> DDR_B_MA[0..13]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

C562

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<10> DDR_B_DQS[0..7]

2.2U_0805_16V4Z

JP5

0.1U_0402_16V4Z

<10> DDR_B_DM[0..7]

1

1

+1.8V

4

3

2

DDRII SO-DIMM B
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
16
1

Rev
X 0.5
of

53

5

4

3

+12VALW

Q3
AO3402_SOT23

1

R582
100K_0402_5%

D

S

3

1

+LCDVDD

2

2

R290
2
1
0_0603_5%

C589
0.1U_0402_16V4Z

2 Q4
G 2N7002_SOT23

D

1

Q5

2
G

D

LCD CONN.

2

3
1

3

S
2
2N7002_SOT23

10U_0805_10V4Z

R587
150K_0402_5%

C590

S

2

1

1

1

D

C588
C587
0.1U_0402_16V4Z
2
2
10U_0805_10V4Z

C681
Reserved for EMI

D

+LCDVDD+
1
1

1

2

2
2

600mA

1

R584
100K_0402_5%

G

R583
470_0402_5%

1

+3VS

+LCDVDD

1

+12VALW

1

+LCDVDD

2

JP6
PID1

0.01U_0402_16V7K
ENVDD

2

22K

Q6

22K

R262 1
R263 1

DTC124EKAT146_SOT23
J2
2

2

R635
100K_0402_5%

3

<33> DIGISUSP
<35> RXDB#
<35> TXDB

1

NO SHORT 2x2m

<35> CTSB#
<35> DTRB#

J3

+3VS

<11> LVDSCLKB+
<11> LVDSCLKB-

LCD_I2C_CLK
LCD_I2C_DAT
ID0
PID0
PDCT
ID1
LVDSCLKB+
LVDSCLKB-

<11> LVDSB_D2+
<11> LVDSB_D2-

LVDSB_D2+
LVDSB_D2-

<11> LVDSB_D1+
<11> LVDSB_D1-

LVDSB_D1+
LVDSB_D1-

<11> LVDSB_D0+
<11> LVDSB_D0-

LVDSB_D0+
LVDSB_D0-

<11> LVDSCLKA+
<11> LVDSCLKA-

LVDSCLKA+
LVDSCLKA-

2

1

<11> LCD_I2C_CLK
<11> LCD_I2C_DAT

NO SHORT 2x2m

<33> PDCT

PID0

PID0

<22>
<22>

ID1

ID0

ID0

<22>

R633
@100K_0402_5%

R588
@100K_0402_5%

LVDSA_D2+
LVDSA_D2-

<11> LVDSA_D2+
<11> LVDSA_D2-

2

Close to JP6

LVDSA_D1+
LVDSA_D1-

<11> LVDSA_D1+
<11> LVDSA_D1-

1

+5VALW

2

2

2

ID1

1

R640
@100K_0402_5%

R716
@100K_0402_5%

2

2
1

PID1

2

2
PID1

R589
10K_0402_5%

10K_0402_5%

10K_0402_5%

1

<22>

R641

R593

10K_0402_5%

1

R717
C

1

1

1

+3VS

1

2

ID1 ID0 config
Reserve
0
0
N-Trig
0
1
1
0 TouchPanel
Digitizer
1
1

D
Q16

2
G

LVDSA_D0+
LVDSA_D0-

<11> LVDSA_D0+
<11> LVDSA_D0-

R924
22K_0402_5%

LED_PWM

1
R712

GM_PWM
2
@ 0_0402_5%

1
R642

INVT_PWM
2
0_0402_5%

C

46
45
44
43
42
41

IPEX_20143-040E

PID1 PID0 config
0
0 Toshiba SXGA+
0
Toshiba XGA
1
Hydis SXGA+
1
0
1
1
Hydis XGA

3

S
2N7002_SOT23

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2 0_0603_5%
2 0_0603_5%

1

ENVDD

1

<11>

<33> DIGI_RST#
+3VS

B

+3VS

B

1

LED_PWM_R

+3VS

<33>

BKOFF#

B

2

A

2

0.1U_0402_16V4Z

Invert_B+

B+
R291
1
0_0603_5%

1

1
C591

Reserved for EMI

U19
Y

3

1

1

1

D
1

2

AO3413_SOT23
Q65

1

P

5

C610
1

G

3

2
3

2
3

S

G
D

1

2

AO3413_SOT23
Q66

D

1

S

R330
10K_0402_5%

G

2

S

R331
10K_0402_5%

2

AO3413_SOT23
Q64

G

R6
510_0402_5%

<11,33> ENABLT

R590
@ 4.7K_0402_5%

2

100K_0402_5%
2

2

+5VALW

+5VALW

+5VALW

R636
1

2
4

2

0.01U_0603_50V4Z

TC7SH08FUF_SSOP5
JP7
Invert_B+
DISPOFF#
2
2
0_0402_5%

<33>

DAC_BRIG

D45
1

MOLEX_53780-0790

PSOT24C-LF_T7_SOT23-3

2

2

2

A

1

1

1

GM_PWM

HT-170NB-DTP/C_BLUE_0805

HT-170Y-DT_0805

<33> BATT_LED#

<11>

D16

D19
HT-170NB-DTP/C_BLUE_0805

CHARGE_LED#

2
@ 0_0402_5%

1
R592

POWER ON

D15

<33> CHARGE_LED#

1
R591

1

1

BATTERY FULL

A

INVT_PWM

1
2
3
4
5
6
7

PWM_CTL
3

2

2

2
1

BATTERY CHARGE

<33>
R315
220_0402_5%

R317
220_0402_5%

R364
120_0402_5%

C592
0.1U_0603_25V7K

BATT_LED#

<33> PWR_LED#

PWR_LED#

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

LCD Conn&Inverter /LED dimming control
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
17
1

Rev
X 0.5
of

53

5

4

3

2

1

DVI CONTROLLER
D

D

L9
DVI_DVDD_1.8V

DVI_DVDD_2.5V

R600 1
R601 1

2DVI_7307@ 0_0402_5% DVI_V5
2DVI_1362@ 0_0402_5%

DVI_TX0+
1

DVI_CLK+
R594
@ 300_0402_1%

DVI_V2
DVI_V10

R598 1
R599 1

DVI_V9

2 DVI_7307@ 0_0402_5%
2 DVI_1362@ 0_0402_5%

R602 1
R603 1

2 DVI_7307@ 0_0402_5%
2 DVI_1362@ 0_0402_5%

DVI_DVDD_2.5V
DVI_DVDD_1.8V

1

1

C596
@ 0.1U_0402_16V4Z

DVI_CLK-2

DVI_DVDD_2.5V
DVI_AVDD_3V

12
28
1
15
21
36
42
48

AS
RESET#
VSWING

27
26

ATPG
SCEN

49
2

2

2
1

+2.5VS

0_0402_5%
DVI_1362@
R619

1

1

R622
10K_0402_5%

2

1

R618
10K_0402_5%
DVI_7307@

SC_PROM
SD_PROM

9
8

SPD
SPC

5
4

R621
10K_0402_5%
DVI_7307@

+3VS

DVI_AVDD_3V

1

1 C606

1

1

2

2

2

2

+3VS

DVI_1362@ 0_0603_5%
C607
10U_0805_10V4Z
DVI_1362@

C

DVI_1362@
0.1U_0402_16V4Z

DVI_DETECT
DVI_V6 R606 1
R607 1
DVI_V1 R608 1
R609 1
1362_SDA_DDC
1362_SCL_DDC
R611 1
R613 1
R615 1
R617 1

2
2
2
2

DVI_7307@ 0_0402_5%
DVI_1362@ 0_0402_5%
DVI_7307@ 0_0402_5%
DVI_1362@ 0_0402_5%

2
2
2
2

DVI_7307@ 0_0402_5%
DVI_7307@ 0_0402_5%
DVI_1362@ 0_0402_5%
DVI_1362@ 0_0402_5%

DVI_DDC_CLK
DVI_AVDD_3V
DVI_DDC_DAT
DVI_DVDD_1.8V
SDVO_SDAT
SDVO_SCLK

+2.5VS

SDVO_SDAT
SDVO_SCLK

SDVO_SDAT
SDVO_SCLK

<11>
<11>

R612 1
R614 1

2 2.7K_0402_5%
2 2.7K_0402_5%

+5VS

+5VS

R623

R624
16K_0402_5%

R625
16K_0402_5%

2
2
1362_SDA_DDC

2 DVI_DVDD_1.8V
DVI_1362@ 0_0402_5%

DVI_DDC_DAT
2
0_0402_5%
DVI_1362@

1
R629

1362_SCL_DDC 1
R630

DVI_DDC_CLK
2
0_0402_5%
DVI_1362@

2

B

I2C_ADD

1

W=20 mils

+5VS

1

1
2

Note:
Install DVI-Ra 1K_0402_5% for SiI1362
Install DVI-Ra 0_0402_5% for CH7307

2

R632
0_0402_5%
DVI_7307@

2

Note: Address = 0x70
Install DVI-Rb 0_0402_5% for SiI1362
Note: Address = 0x72
Install DVI-Rb 10K_0402_5% for CH7307

DVI_V3 1
R626

R631
1K_0402_5%
DVI_1362@

DVI-Ra

L11
1

CH7307C-DEF_LQFP48

DVI_V4 1

R627
@1K_0402_5%

R628
0_0402_5%
DVI_1362@

+2.5VS

DVI_1362@ 1K_0402_5%

1

2
AS

DVI-Rb

2
DVI_TX2-

C608
150P_0402_50V8J

@

B

C604
@ 0.1U_0402_16V4Z

1

DVI_1362@
R620
0_0402_5%

2

DVI_AVDD_3V
C605
0.1U_0402_16V4Z
DVI_1362@

2

2

1

DVI_V8
DVI_V7

R616
1.2K_0402_5%
DVI_7307@

11
10

34
35

DVI_1362@ 300_0402_5%

29

2

1

1

3
2
25

AS

R610
<9,20,22,24,28,32,33,35> PLT_RST#
2

HPDET
SC_DDC
SD_DDC

2
DVI_TX1-

C599

1

2

SDVOB_CLK+
SDVOB_CLK-

C603
@ 0.1U_0402_16V4Z

+1.8VS

DVI_7307@ 0_0603_5%
1
C600
10U_0805_10V4Z
DVI_7307@
2

DVI_7307@ 0.1U_0402_16V4Z

R605
@ 300_0402_1%
1

2

DVI_1362@ 0_0603_5%
C595
10U_0805_10V4Z
DVI_1362@

1

46
47

1

2

1

C598

2

2

SDVOB_B+
SDVOB_B-

<11> SDVOB_CLK+
<11> SDVOB_CLK-

NC
NC

43
44

DGND
DGND
AGND
AGND
AGND
TGND
TGND
AGND_PLL

<11> SDVOB_B+
<11> SDVOB_B-

ThermmaoGND

SDVOB_G+
SDVOB_G-

7
30
31
39
45
18
24
6

1

40
41

R604
@ 300_0402_1%

DVI_CLKDVI_CLK+
DVI_TX0DVI_TX0+
DVI_TX1DVI_TX1+
DVI_TX2DVI_TX2+

2DVI_1362@2

DVI_DVDD_2.5V

DVI_TX2+

1

DVI_AVDD_3V

TLC#
TLC
TDC0#
TDC0
TDC1#
TDC1
TDC2#
TDC2

SDVOB_R+
SDVOB_R-

<11> SDVOB_G+
<11> SDVOB_G-

2

C

SDVOB_INT+
SDVOB_INT-

13
14
16
17
19
20
22
23

1

0.1U_0402_16V4Z
32
2
33
2
C602
0.1U_0402_16V4Z
37
<11> SDVOB_R+
38
<11> SDVOB_R1
1

1

L10
C597
@ 0.1U_0402_16V4Z

2
DVI_TX0-

DVI_TX1+

DVDD
DVDD
AVDD_PLL
TVDD
TVDD
AVDD
AVDD
AVDD

C601

<11> SDVOB_INT+
<11> SDVOB_INT-

C594 1

0.1U_0402_16V4Z

DVI_7307@ 0.1U_0402_16V4Z
U4

1

R595
@ 300_0402_1%
2

2DVI_7307@ 0_0402_5%
2DVI_1362@ 0_0402_5%

1

R596 1
R597 1

2

DVI_AVDD_3V
DVI_DVDD_2.5V
DVI_DVDD_1.8V

C593
0.1U_0402_16V4Z
DVI_1362@

1

+5VS
D39
4

DVI_TX0- 3

D40
IO1

2

IO2 GND

1

VIN

DVI_TX0+

4
DVI_TX1- 3

PRTR5V0U2X_SOT143-4

D41

DVI_TX2- 3

2

IO2 GND

1

DVI_TX2+

4
DVI_CLK- 3

1

DVI_TX0-

DVI_TX0+
IO1

2

IO2 GND

1

VIN

DVI_CLK+
DVI_TX1-

PRTR5V0U2X_SOT143-4
DVI_TX1+

+5VS

+5VS

Q11
3

JP8

DVI_DETECT# <20>

D

S

DVI_TX1+

D42
IO1

VIN

PRTR5V0U2X_SOT143-4

2
G

1

+5VS

4

DVI_DETECT

2

PRTR5V0U2X_SOT143-4

+5VS

DVI_DETECT#

IO1

IO2 GND

VIN

D43

2N7002_SOT23

4

A

D44
IO1

2

DVI_DDC_CLK
3 IO2 GND

1

VIN

PRTR5V0U2X_SOT143-4

DVI_DDC_DAT

4

VIN

IO1

2

3

IO2 GND

1

DVI_DETECT

DVI_TX2-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

DVI_TX2+

DVI_CLK+

DVI_CLK-

DVI_DDC_DAT
DVI_DDC_CLK
2
R282

JAE_DD2R040HP2

+5VS

+5VS
1 DVI_DETECT
10K_0402_5%
A

PRTR5V0U2X_SOT143-4

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

DVI CONN
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
18
1

Rev
X 0.5
of

53

5

4

3

2

1

+2.5VS

CRTVCC
F1

D29

1.1A 6V UL/CSA/TUV
1

1

R637

1

1 R639

R638
C613

1

C614

1
C615

2

2

<11>

CRTB

2

2

1
C616
6P_0402_50V8K

2

3VDDCDA

2

1

1
C617
6P_0402_50V8K

2

1

D

R371

JP12
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

3VDDCDA_R
CRTG
HSYNC
CRTB

Q8
BSS138W-7-F_SOT323~D

C618
6P_0402_50V8K

R144

VSYNC

G

2

L16

M_SEN#
CRTR

<22,36> M_SEN#

3

D

1

3VDDCDA

S

CRT_B_MB

L13

2

CRT_G_MB

2

CRTG

R142
2.2K_0402_5%
1

2

R141
2.2K_0402_5%
1

CRTR

G

2

2

1

1

L12

R143

2

10K_0402_5%

1

0.1U_0402_16V4Z

1

2.2K_0402_5%

CRT_R_MB

RB491D_SOT23
C609

2.2K_0402_5%

FBMA-L11-201209-170LMT@DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59
FBMA-L11-201209-170LMT
FBMA-L11-201209-170LMT

D

1

2

2

1

+5VS

2

2

1

1

+3VS

D31

2

D4

2

3

2

3

2

3

+3VS
D3

3VDDCCL

3VDDCCL_R

1

S

<11> 3VDDCCL

3

D

133_0402_1% 6P_0402_50V8K
133_0402_1% 6P_0402_50V8K
133_0402_1% 6P_0402_50V8K

1
Q49
BSS138W-7-F_SOT323~D
2

16
17

ALLTO_C10510-115A5-L_15P
C343
100P_0402_50V8J

<36> 3VDDCDA_R

To DOCK
<36> 3VDDCCL_R
C

C

+5VS

2

3

+5VS

1

+5VS

R145

C633
2

1
C671

2
0.1U_0402_16V4Z

@ DAN217_SC59
1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

D34

C677

C672
2

2
2
0.1U_0402_16V4Z

CRT_HSYNC

2

A

G

<11> CRT_HSYNC

P
OE#

5
1

1K_0402_5%

1

1

R1154
2
1HSYNC
39_0402_5%

4CRT_HSYNCMB
Y U51

3

74AHCT1G125GW_SOT353-5
R146
1

+3VS

2

G

A

3

B

+5VS
CRT_HSYNCDOCK
Y U54

R1155
2
1CRT_HSYNC_DOCK
39_0402_5%

74AHCT1G125GW_SOT353-5

CRT_HSYNC_DOCK

<36>
C620

+5VS

0.1U_0402_16V4Z

DOCKEN

1

1: TO DOCK

R372
10K_0402_5%

0: TO MB

2

3

16

D35
<11>
<11>
<11>

R147
2

@ DAN217_SC59
1

1

CRT_R
CRT_G
CRT_B

4
7
9
12

CRT_VSYNC

2

A

3

G

<11> CRT_VSYNC

P
OE#

5
1

1K_0402_5%

CRT_R
CRT_G
CRT_B

8
4CRT_VSYNCMB
Y U52

B

2
U6

+5VS

2

2

1

P
OE#

5
1

1K_0402_5%

R1158

2
1VSYNC
39_0402_5%

VCC
DA
DB
DC
DD
GND

EN
IN

15
1

S1A
S2A
S1B
S2B
S1C
S2C
S1D
S2D

2
3
5
6
11
10
14
13

DOCKEN_VGA
CRT_R_MB
CRT_R_DOCK
CRT_G_MB
CRT_G_DOCK
CRT_B_MB
CRT_B_DOCK

DOCKEN_VGA <33,34>
CRT_R_DOCK <36>
CRT_G_DOCK <36>
CRT_B_DOCK <36>

PI5V330QE_QSOP16

74AHCT1G125GW_SOT353-5
R148
1

2

A

G

2

P
OE#

5
1

1K_0402_5%

3

A

CRT_VSYNCDOCK
Y U74

R1159
2
1CRT_VSYNC_DOCK
39_0402_5%

CRT_VSYNC_DOCK

<36>

74AHCT1G125GW_SOT353-5

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

CRT CONN
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
19
1

Rev
X 0.5
of

53

5

4

3

2

1

+3VS

2 8.2K_0402_5%

PCI_PLOCK#

R649 1

2 8.2K_0402_5%

PCI_IRDY#

R650 1

2 8.2K_0402_5%

PCI_SERR#

R651 1

2 8.2K_0402_5%

PCI_PERR#

R652 1

2 8.2K_0402_5%

PCI_REQ4#

R653 1

2 8.2K_0402_5%

PCI_REQ3#

R654 1

2 8.2K_0402_5%

DVI_DETECT#

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

+3VS

C

R656 1

2 8.2K_0402_5%

PCI_PIRQA#

R657 1

2 8.2K_0402_5%

PCI_PIRQB#

R658 1

2 8.2K_0402_5%

PCI_PIRQC#

R659 1

2 8.2K_0402_5%

PCI_PIRQD#

R660 1

2 8.2K_0402_5%

PCI_PIRQE#

R661 1

2 8.2K_0402_5%

PCI_PIRQF#

<25> PCI_PIRQA#

R663 1

2 8.2K_0402_5%

PCI_PIRQG#

<25> PCI_PIRQC#

R664 1

2 8.2K_0402_5%

PCI_PIRQH#

R665 1

2 8.2K_0402_5%

PCI_REQ0#

R666 1

2 8.2K_0402_5%

PCI_REQ1#

R667 1

2 8.2K_0402_5%

PCI_REQ2#

D

U9B

<25,27> PCI_AD[0..31]

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ0#
PCI_GNT0#

<27>
<27>

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ2#
PCI_GNT2#

<25>
<25>

C/BE0#
C/BE1#
C/BE2#
C/BE3#

B15
C12
D12
C15

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLTRST#
PCICLK
PME#

C26
A9
B19

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI

Interrupt

A3
B4
C5
B5

PIRQA#
PIRQB#
PIRQC#
PIRQD#

AE5
AD5
AG4
AH4
AD9

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

I/F

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#

G8
F7
F8
G7

PCI_REQ4#
DVI_DETECT#

+3VS
DVI_DETECT# <18>
5

PCI_FRAME#

R648 1

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

AE9
AG8
AH8
F21
AH20

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

<25,27>
<25,27>
<25,27>
<25,27>

PCI_PCIRST#

PCI_IRDY# <25,27>
PCI_PAR <25,27>

2

B

2

A

CLK_PCI_ICH
PCI_PME#

Y

R655
0_0402_5%
1

PCI_DEVSEL# <25,27>
PCI_PERR# <25,27>
PCI_SERR# <25,27>
PCI_STOP# <25,27>
PCI_TRDY# <25,27>
PCI_FRAME# <25,27>

PCI_RST#

4

PCI_RST#

<25,27>

PLT_RST#

<9,18,22,24,28,32,33,35>

TC7SH08FUF_SSOP5
@

+3VS

PCI_PLTRST#

U11

1

B

2

A

Y

<5>
<34>

PLT_RST#

4

C

TC7SH08FUF_SSOP5
@

R662
0_0402_5%
2
1

PCI_PIRQE# <27>
PCI_PIRQF# <27>
PCI_PIRQG# <27>

MCH_ICH_SYNC#

U10

1

P

2 8.2K_0402_5%

G

PCI_TRDY#

R647 1

3

2 8.2K_0402_5%

5

PCI_STOP#

R646 1

P

PCI_DEVSEL#

2 8.2K_0402_5%

G

2 8.2K_0402_5%

R645 1

3

D

R644 1

<9>

Place closely pin A9

ICH7_BGA652~D

2

CLK_PCI_ICH

1

R669
@10_0402_5%

C621
@ 8.2P_0402_50V8D

1

2

B

B

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

ICH7M1/4-PCI Interface
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
20
1

Rev
X 0.5
of

53

5

4

C622
2

18P_0402_50V8J

Y2

R670
10M_0402_5%

1

1

2

R671 1

RTXC1
RTCX2

ICH_RTCRST# AA3

2
20K_0402_5%

CMOS_CLR1
1
2

AB1
AB2

ICH_RTCX2

+RTCVCC

1

2

AA6
AB5
AC4
Y6

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LDRQ0#
LDRQ1# / GPIO23

AC3
AA5

LPC_DRQ#0

LFRAME#

AB3

LPC_FRAME#

A20GATE
A20M#

AE22
AH28

GATEA20
H_A20M#

RTCRST#

ICH_INTVRMENW4
SM_INTRUDER#Y5

R672

LAD0
LAD1
LAD2
LAD3

INTVRMEN
INTRUDER#

1M_0402_5%

NO SHORT PADS

W1
Y1
Y2
W3

<30> ICH_AZ_CODEC_BITCLK

33_0402_5% 1

2 R679

<30> ICH_AZ_CODEC_SYNC
<30> ICH_AZ_CODEC_RST#

33_0402_5% 1

2 R680

ACZ_RST#

GPIO49 / CPUPWRGD

AG24

H_PWRGOOD

H_PWRGOOD <6>

IGNNE#
INIT3_3V#
INIT#
INTR

AG22
AG21
AF22
AF25

H_IGNNE#

H_IGNNE#

<6>

H_INIT#
H_INTR

H_INIT#
H_INTR

<6>
<6>

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_RST#

T2
T3
T1

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

ICH_AZ_CODEC_SDIN0

<30> ICH_AZ_CODEC_SDIN0
C

<30> ICH_AZ_CODEC_SDOUT

FERR#

AG26

U7
V6
V7

R5

33_0402_5% 1

2 R684

ACZ_SDOUT

T4

ACZ_SDOUT
SATALED#

AF3
AE3
AG2
AH2

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

R686
332K_0402_1%

AF7
AE7
AG6
AH6

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

ICH_INTVRMEN

AF1
AE1

SATA_CLKN
SATA_CLKP

2

1

+RTCVCC

R687

1

1

1

+3VS
R688
8.2K_0402_5%

B

Pull high to enable the
internal Vccsus1_5
suspend regulator. pull
low to disable it--ICH_INTVRMEN

PDIORDY
IDEIRQ

2

2
<24>
<24>

AH10
AG10

SATARBIASN
SATARBIASP

AG16
AH16
AF16
AH15
AF15

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

R689
4.7K_0402_5%

2

@ 0_0402_5%

PDIORDY
IDEIRQ

<24>
<24>
<24>

PDDACK#
PDIOW#
PDIOR#

PDDACK#
PDIOW#
PDIOR#

1 0_0402_5%
1 56_0402_5%
H_FERR#
<6>

RCIN#

KBRST#

SMI#
NMI

AF23
AH24

H_SMI#
H_NMI

STPCLK#

AH22

THERMTRIP#

AF26

R682 2
1
0_0402_5%
THRMTRIP_ICH#

KBRST#

<33>

H_SMI#
H_NMI

<6>
<6>

H_STPCLK#
R683
1

<6,9>
<6,46>
<6>

+3VS +VCCP

H_STPCLK#

DA0
DA1
DA2

AH17
AE17
AF17

PDA0
PDA1
PDA2

PDA0
PDA1
PDA2

<24>
<24>
<24>

DCS1#
DCS3#

AE16
AD16

PDCS1#
PDCS3#

PDCS1#
PDCS3#

<24>
<24>

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

DDREQ

AE15

PDDREQ

PDD[0..15]

PDDREQ

R681
56_0402_5%
<6>

2

24.9_0402_1%

IDE

H_CPUSLP#
H_DPRSTP#
H_DPSLP#
+VCCP

1 10K_0402_5%

R678 2

AG23

SATA

AF18

GATEA20
<33>
H_A20M#
<6>
2
1 @ 0_0402_5%

H_CPUSLP_R#
R676
DPRSLP# R674 2
H_DPSLP#
R675 2
H_FERR#

LAN_RXD0
LAN_RXD1
LAN_RXD2

ACZ_BCLK
ACZ_SYNC

LPC_FRAME# <24,32,33,35>
1 R673 10K_0402_5%
+3VS

2

AF24
AH25

U5
V4
T5

D

LPC_DRQ#0 <35>

AG27

LAN_RSTSYNC

AC-97/AZALIA

1

<24,32,33,35>
<24,32,33,35>
<24,32,33,35>
<24,32,33,35>

CPUSLP#

LAN_CLK

U1
R6

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

TP1 / DPRSTP#
TP2 / DPSLP#

V3
U3

2 R677
ACZ_BCLK
ACZ_SYNC

33_0402_5%

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN

C624
1U_0603_10V4Z
1
2

CPU

+RTCVCC

U9A

18P_0402_50V8J

RTC

C623
2

1

IN

NC
OUT 4
32.768KHZ_12.5PF_1TJS125BJ4A421P

2

NC

3

D

1

ICH_RTCX1

LPC

2

2

1

1

3

C

H_THERMTRIP# <6,9>

R683 must be placed close to U9.AF26
within 2" and R681 must be placed close
to R683 within 2".

PDD[0..15]

<24>

<24>
B

ICH7_BGA652~D

CHGRTC
D8
R690
1

R691
1
2

1

BATT1.1

2

+RTCVCC

2

100_0603_1%

3
BAS40-04_SOT23

BATT1.2

1

2

W=20mils

+

BATT1

1

2

511_0603_1%
RTCBATT

C626
0.1U_0402_16V4Z

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

ICH7M2/4-RTC/LPC/IDE/Azalia
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
21
1

Rev
X 0.5
of

53

5

4

3

2

1

+3VS

CLK_48M_ICH

CLK_14M_ICH

1

+3VS

SPKR
SUS_STAT#
SYS_RST#

PM_BMBUSY#

<9> PM_BMBUSY#
+3VS

EC_SCI#

<33> EC_SCI#

10K_0402_5%
R709 1
2 SIRQ

<34> EC_FLASH#
+3VALW
<24> IDERST_HD#

AC20
AF21

R576
1K_0402_5%
2
D

S

3

1

A21

GPIO26

B21
E23

GPIO27
GPIO28

ID0
ID1

ID0
ID1

AG18

GPIO32 / CLKRUN#

AC19
U2

GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#

ICH_PCIE_WAKE# F20
SIRQ
AH21
AF20
1
2 SB_THERM#
D10 RB751V_SOD323
VGATE_INTEL
AD22
<33,46> VGATE_INTEL

<25,32,33,35> SIRQ
<33> EC_THRM#

G

Q71
BSS138_NL_SOT23-3
+3V_LAN

2

<28> LAN_WAKE#

<17>
<17>

GPIO18 / STPPCI#
GPIO20 / STPCPU#

IDERST_HD#
PM_CLKRUN#

<25,27,32,33,35> PM_CLKRUN#

+3VALW

R711

1

2
0_0402_5%

<19,36> M_SEN#
<27> USB_SMI#

M_SEN#
USB_SMI#

AC21
AC18
E21

10K_0402_5%
1
2 LINKALERT#

WAKE#
SERIRQ
THRM#
VRMPWRGD

GPIO

GPIO6
GPIO7
GPIO8

AC1
B2

CLK_14M_ICH
CLK_48M_ICH

SUSCLK

C20

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

B24
D23
F22

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

2
2
2
2

T15 PAD

AA4 PWROK

1
R704

H_DPRSLPVR

TP0 / BATLOW#

C21

PM_BATLOW#

PWRBTN#

C23

EC_PBTNOUT#

LAN_RST#

C19

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39

Y4

2
1
C627
@ 4.7P_0402_50V8C

2

D

C628
@ 4.7P_0402_50V8C

if the susclk duty cycle is
beyond the 30-70% range, it
indicate a poor oscillation signal

SLP_S3#
<33>
SLP_S4#
<33>
SLP_S5#
<33>
PWROK
<9,33,34>
2
10K_0402_5%
H_DPRSLPVR <9,46>
PM_BATLOW# <33>
R705

EC_PBTNOUT# <33>
2

PLT_RST#

PLT_RST#

EC_RSMRST#
EC_RSMRST#
R708
10K_0402_5%
1
2

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

2

CLK_14M_ICH <5>
CLK_48M_ICH <5>

AC22

GPIO16 / DPRSLPVR

1

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

1

+3VALW

<9,18,20,24,28,32,33,35> 8.2K_0402_5%
<27,33>

C

EC_SWI#
EC_SMI#

PID0
PID1

EC_SWI#
EC_SMI#

<33>
<33>

PID0
PID1

<17>
<17>

ICH7_BGA652~D

10K_0402_5%
R713 1
2 XDP_DBRESET#

Need update symbol
U9D

EC_SCI#
F26
F25
E28
E27

PERn1
PERp1
PETn1
PETp1

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

1 C629
1 C630

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

H26
H25
G28
G27

PERn2
PERp2
PETn2
PETp2

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

1 C661
1 C670

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

K26
K25
J28
J27

PERn3
PERp3
PETn3
PETp3

M26
M25
L28
L27

PERn4
PERp4
PETn4
PETp4

P26
P25
N28
N27

PERn5
PERp5
PETn5
PETp5

T25
T24
R28
R27

PERn6
PERp6
PETn6
PETp6

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

<24>
<24>
<24>
<24>

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

<24>
<24>
<24>
<24>

PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3

B

<34> USB_OC#4
<34> USB_OC#6
<34> USB_OC#7

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

SPI_CLK
SPI_CS#
SPI_ARB

P5
P2

SPI_MOSI
SPI_MISO

D3
C4
D5
D4
E5
C3
A2
B3

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

A

ICH7_BGA652~D

SPI

<32> USB_OC#0
<32> USB_OC#1

R2
P6
P1

PCI-EXPRESS

1 C631
1 C632

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

<28>
<28>
<28>
<28>

USB

DIRECT MEDIA INTERFACE

10K_0402_5%
R714 1
2

CLK14
CLK48

RSMRST#

R1345
<24> PCIE_WAKE#

R733 1
R742 1
R743 1
R745 1

GPIO11 / SMBALERT#

EC_FLASH#

1

8.2K_0402_5%
R710 1
2 PM_CLKRUN#

C

H_STP_PCI#
H_STP_CPU#

<5> H_STP_PCI#
<5> H_STP_CPU#

B23

GPIO0 / BM_BUSY#

GPIO

8.2K_0402_5%
R706 1
2 SB_THERM#

AB18

SYS

R701
ICH_RI#
1
2
8.2K_0402_5%
ICH_SPKR
<30> ICH_SPKR
SUS_STAT#
<32,35> SUS_STAT#
XDP_DBRESET#
<6> XDP_DBRESET#

R693
10_0402_5%
@

2

RI#

A19
A27
A22

+3VALW

AF19
AH18
AH19
AE19

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

Clocks

A28

2

G

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

SATA
GPIO

U9C
C22
B22
A26
B25
A25

POWER MGT

2
1

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

SMB

G

2

+3VS

2.2K_0402_5%

ICH_SMB_CLK
1
Q10
2N7002_SOT23

3

R692
10_0402_5%
@

1
R695

D

S

ICH_SMBCLK

1

2

2

R694
R697
2.2K_0402_5%
10K_0402_5%

D

<5,6,15,16,24> ICH_SMBCLK

S

ICH_SMBDATA

<5,6,15,16,24> ICH_SMBDATA

2

2

1

R703
2.2K_0402_5%
R696
2N7002_SOT23
10K_0402_5%
Q9
ICH_SMB_DATA
3
1

2

1
R702
2.2K_0402_5%

D

1

+3VALW
1

+3VALW

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V26
V25
U28
U27

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y26
Y25
W28
W27

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA28
AA27

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD25
AD24
AC28
AC27

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_CLKN
DMI_CLKP

AE28
AE27

CLK_PCIE_ICH#
CLK_PCIE_ICH

C25
D25

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+

USBRBIAS#
USBRBIAS

D2
D1

USBRBIAS

DMI_ZCOMP
DMI_IRCOMP

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

<9>
<9>
<9>
<9>

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

<9>
<9>
<9>
<9>

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

<9>
<9>
<9>
<9>

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

<9>
<9>
<9>
<9>

B

CLK_PCIE_ICH# <5>
CLK_PCIE_ICH <5>
R715
1

24.9_0402_1%
2
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+

R719
1

Within 500 mils
+1.5VS
<32>
<32>
<32>
<32>
<24>
<24>
<36>
<36>
<36>
<36>
<36>
<36>
<36>
<36>
<36>
<36>

RP27
USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

4
3
2
1

5
6
7
8

+3VALW

10K_0804_8P4R_5%
RP29
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

4
3
2
1

5
6
7
8

10K_0804_8P4R_5%

22.6_0402_1%
2

Within 500 mils

A

This is only supported USBRBIAS value for the Intel
82801GM and is required to properly configure the
USB interface drive strength.

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

ICH7M3/4-USB/DMI/PCIE/PM/GP
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
22
1

Rev
X 0.5
of

53

5

4

3

2

1

+VCCP
U9F

2

R721
100_0402_5%

+ C637

C638 1

C639 1

C640 1

2

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Place closely pin
D28,T28,AD28.

D11

1

2

CH751H-40PT_SOD323
ICH_V5REF_RUN
1

C642

2 0.1U_0402_16V4Z

C

2

1

+5VALW +3VALW

R722
10_0402_5%

D12

1

2

CH751H-40PT_SOD323

1

ICH_V5REF_SUS
C650
+3VS

2 0.1U_0402_16V4Z

C651
0.1U_0402_16V4Z

1

2

Place closely pin AG28 within 100mlis.
2

0.5_0805_1%

+1.5VS_DMIPLL

L18
1
2
BLM18AG601SN1D_0603

C658
10U_0805_10V4Z

R723
1

B

1

2

C659
0.01U_0402_16V7K

+1.5VS_DMIPLLR

+1.5VS

B27
+1.5VS_DMIPLL

1

+1.5VS

2

C660
0.1U_0402_16V4Z

1

2

Place closely pin AG5.

+1.5VS

1

2

+3VALW
C665
0.1U_0402_16V4Z

C662
0.1U_0402_16V4Z

+3VS

1
C664
1U_0603_10V4Z

2

Place closely pin AG9.

1
+1.5VS
2

+1.5VS

C667
0.1U_0402_16V4Z

1
T19
T20

PAD
PAD

ICH_AA2
ICH_Y7

VccDMIPLL

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

V5
V1
W2
W7

+3VALW
C668

1

Vcc3_3 / VccHDA

U6

VccSus3_3/VccSusHDA

R7

Vcc3_3[1]

AG28

AA2
Y7

2

Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

AE23
AE26
AH26

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

VccRTC

W5

VccSus3_3[1]

P7

VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

A24
C24
D19
D22
G19

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

1

C635

2

AB17
AC17

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

T7
F17
G17

Vcc1_5_A[24]
Vcc1_5_A[25]

AB8
AC8

330U_D2E_2.5VM_R9

2

+3VS
+3VALW

1

+VCCP
C643
1

C641

2 0.1U_0402_16V4Z

2

0.1U_0402_16V4Z
1
2
C644
0.1U_0402_16V4Z

+3VS
1

C645
1

2

2 0.1U_0402_16V4Z
C646
4.7U_0805_10V4Z

1

2

1

2

1

2

+3VS

+RTCVCC
1

C652

+3VALW

1

C653

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

1

1

C656

2

1

2

+3VALW
C657

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

+1.5VS

C663
1

2

0.1U_0402_16V4Z

VccSus1_05[1]

ICH_K7

VccSus1_05[2]
VccSus1_05[3]

C28
G20

ICH_C28
ICH_G20

A1
H6
H7
J6
J7

2

C634

CRB use 270uF

K7

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

+

1U_0603_10V4Z

1

Vcc1_5_A[19]
Vcc1_5_A[20]

1

C636

C655
0.1U_0402_16V4Z

+3VS

1

V5REF_Sus

1

C654
0.1U_0402_16V4Z

+5VS
1

BLM21PG600SN1D_0805

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

V5REF[2]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C649
0.1U_0402_16V4Z

2
220U_D2_4VM

1

+1.5VS

F6

0.1U_0402_16V4Z

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

C648
0.1U_0402_16V4Z

ICH_V5REF_SUS

L17

V5REF[1]

C647
0.1U_0402_16V4Z

G10
AD17

D

U9E
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27

0.1U_0402_16V4Z

ICH_V5REF_RUN

PAD

T16

PAD
PAD

T17
T18

+1.5VS
1

C666

2 0.1U_0402_16V4Z

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

D

C

B

ICH7_BGA652~D

ICH7_BGA652~D

A

A

0.1U_0402_16V4Z

2

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

ICH7M4/4-PWR/GND
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
23
1

Rev
X 0.3
of

53

5

4

3

2

Q61

+3VS

<21>
D

S

1

2

2

1 10K_0402_5% +3VS

R968 2

KXP84-2050_DFN14

0.1U_0402_16V4Z

2

C683

0.1U_0402_16V4Z

C684

0.1U_0402_16V4Z

C685

0.1U_0402_16V4Z

C686

2

1

3

2N7002_SOT23
PDD0
PDD4
PDD2
PDD1

2

2
10U_0805_10V4Z

SMB_EC_DA2

1

+3VS

2

1

22_0402_5%
1
2
PDD7
2
@10K_0402_5% PDD5
PDD6
PDD3
PDD15
PDD9

Q69
G_CK2
G_DA2

1
C687

R724

PIDERST#
R7521

R720
8.2K_0402_5%

SM BUS Addr. 0011 000

<21>
<21>
<21>
<21>

1

1

+3VS

G

D

GND
VDD
MOTION
FF
Output X
Output Z
Output Y

R730
4.7K_0402_5%

D

MOTION
F_FALL

<33> MOTION
<33> F_FALL

15
14
13
12
11
10
9
8

Thermal_Pad
NC
IO VDD
SCL/SCLK
SDA/SDO
ADDR0/SDI
CS#
RESET

Place caps. near
CONN.

HDD

2N7002_SOT23

S

1
2
3
4
5
6
7

PDD[0..15]

SMB_EC_CK2

1

G

U56

+3VS

2

R725
2
1
4.7K_0402_5%
2
1

3

1

PDD[0..15]

PDIOR#
PDA0
PDCS3#
PDA1

PDIOR#
PDA0
PDCS3#
PDA1

+3VS

JP10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Layout Note: +VPHDD trace
width 60 mil

+3VS

PDD10
PDD11
PDD12

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

500mA

PDDREQ
PDIOW#
PDD8

PDDREQ
PDIOW#

1

<21>
<21>

1
C674

2
PDDACK#
PDD13
PDCS1#
PDD14

PDDACK#

<21>

PDCS1#

<21>

PDIORDY
IDEIRQ
PDA2

<21>
<21>
<21>

1
C675
10U_0805_10V4Z

2

2

C676
0.1U_0402_16V4Z
D

1000P_0402_50V7K
R729

PDIORDY
IDEIRQ
PDA2
PCSEL

1
R727

2
2
C673

2
470_0402_5%

PDDREQ
1
@ 5.6K_0402_5%

1
33P_0402_50V8J

SUYIN_127212FA040G200ZX
+5VS

VDD
GND
NC

Q55
S

1

C

2

<22> IDERST_HD#

2

A

2
G

+5VALW

1

SCLK
SDA

VDD
GND
NC

3
2
1

53

+5VS

1

1

SDA

VDD

8

2

SCLK

A0

7

3

ALERT

A1

GND

A2

SCLK

3
2N7002_SOT23

2

2
G
+5VS

Thermal Sensor for CPU, Place near the CPU

D2
UIM_VPP

UIM_DATA

1

C682
2

2

2

R903
10K_0402_5%

+5VS
1

1

1

2

4
5

D

S

Q20
2N7002_SOT23

SCLK
SDA

CH1 CH4

6

2

Vn

Vp

5

3

CH2 CH3

4

UIM_RST

3
2
1

VDD
GND
NC

2
G
S

D

<22>
<22>

+3VS

2

2
1 UIM_VCC
@ C749 0.1U_0402_16V4Z
UIM_RST
UIM_VPP
UIM_CLK
D5
UIM_DATA
3
1UIM_PWR
2
DAN217_SC59

4
5
EC_DA2

SCLK
SDA

C878
1

3
2
1

VDD
GND
NC

2
0.1U_0402_16V4Z

C37
330U_D3L_6.3VM_R25M

WL_SW#

1
2

1
2

Place C37 close to JP28

MOLEX_53780-0290

1
2
3
4
5
6
7
8
9
10

PCIE_WAKE#
WLAN_ACTIVE
BT_ACTIVE
CLKREQB#

<5> CLK_PCIE_MINI#
<5> CLK_PCIE_MINI

VCC(C1)
GND(C5)
RST(C2)
VPP(C6)
CLK(C3)
I/O(C7)
SW1
SW2

CLK_PCIE_MINI#
CLK_PCIE_MINI

DB_LPC_RST#
CLK_DEBUG_PORT
<5> CLK_DEBUG_PORT
R773
0_0402_5%
PCIE_RXN2 1
2 PCIE_C_RXN2
<22> PCIE_RXN2
PCIE_RXP2 1
2 PCIE_C_RXP2
<22> PCIE_RXP2
R774
0_0402_5%
<22> PCIE_TXN2
<22> PCIE_TXP2

PCIE_TXN2
PCIE_TXP2

GND1
GND2

<21,32,33,35> LPC_FRAME#
<21,32,33,35> LPC_AD0
<21,32,33,35> LPC_AD1
<21,32,33,35> LPC_AD2
<21,32,33,35> LPC_AD3
<9,18,20,22,28,32,33,35> PLT_RST#

R777 1
R778 1
R779 1
R781 1
R782 1
R783 1

2 DB@ 0_0402_5%DB_LPC_FRAME#
2 DB@ 0_0402_5% DB_LPC_AD0
2 DB@ 0_0402_5% DB_LPC_AD1
2 DB@ 0_0402_5% DB_LPC_AD2
2 DB@ 0_0402_5% DB_LPC_AD3
2 DB@ 0_0402_5% DB_LPC_RST#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0
WLANOFF#

WLANOFF#
PLT_RST#
+3V_LAN

<33>
<9,18,20,22,28,32,33,35>

ICH_SMBCLK <5,6,15,16,22>
ICH_SMBDATA <5,6,15,16,22>
NEC_USBP1NEC_USBP1+

NEC_USBP1- <27>
NEC_USBP1+ <27>

A

FOX_AS0B226-S52N-7F~N

add these for Port 80H debug card

Compal Electronics, Inc.(KunShan)

2
G

TC74A2-5.0VCT_SOT23-5

+1.5VS +3VS

JP13
PCIE_WAKE#
WLAN_ACTIVE
BT_ACTIVE
CLKREQB#

YAMAI_FMS006Z-2101-0

+5VS

+3VS

B

UIM_CLK

4.7U_0805_10V4Z
1

0.1U_0402_16V4Z

U36

Q22
2N7002_SOT23
3

USBP2USBP2+

Mini-Express Card ---WLAN

SM BUS Addr. 1001 001

SMB_EC_DA2 1

USBP2USBP2+

+3VS

1

TC74A1-5.0VCT_SOT23-5

EC_CK2

+5VS

<6,33,36,39> SMB_EC_DA2

C877

U35

22P_0402_50V8J

WL_SW#

NUP4301MR6T1G_TSOP6

2

R902
10K_0402_5%

A

C

ICH_SMBCLK <5,6,15,16,22>
ICH_SMBDATA <5,6,15,16,22>

JP14
<33>

D38
PSOT24C-LF_T7_SOT23-3

JP9

3

<33>
<9,18,20,22,28,32,33,35>

2

WL_SW#

Symbol update

+5VS

1

WWANOFF#
PLT_RST#
+3V_LAN

Wireless SW

<22>
<27>
<27>
<5>

@ R966
33_0402_5%

<6,33,36,39> SMB_EC_CK2

54

WWANOFF#

+

Thermal Sensor for charger

0.1U_0402_16V4Z
2
0_0402_5%
1
+5VS
10K_0402_5%
1
10K_0402_5%

1
R728
6
2
R957
5
2
R956

SM BUS Addr. 1001 110

SMB_EC_CK2

GND1

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

1

SM BUS Addr. 1001 010

MCP9803T-M/MSG_MSOP8

1

GND2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

FOX_AS0B226-S52N-7F~N

CLK_DEBUG_PORT

@ C933

2

0.1U_0402_16V4Z

3

1

1

2N7002_SOT23

S

D

SMB_EC_CK1

C928

U14
SDA

3

2
G

+5VS

4
B

4
5

C924

1

TC74A2-5.0VCT_SOT23-5

R958
10K_0402_5%

S

D

SMB_EC_CK1
SMB_EC_DA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2

2

+5VS

R959
10K_0402_5%
Q56

Q57

PCIE_TXN3
PCIE_TXP3
+3VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1

S

D
2
G

2N7002_SOT23
U55

1

0_0402_5%
2 PCIE_C_RXN3
2 PCIE_C_RXP3
0_0402_5%

EC_DA1

3

+5VS

SMB_EC_DA1

R786
PCIE_RXN3 1
PCIE_RXP3 1
R785
<22> PCIE_TXN3
<22> PCIE_TXP3

+5VS

SMB_EC_DA1 1

CLK_PCIE_WAN#
CLK_PCIE_WAN

2

Q54

<22> PCIE_RXN3
<22> PCIE_RXP3

2
@ 0_0402_5%

Thermal Sensor for inverter

CLKREQA#

<5> CLKREQA#
<5> CLK_PCIE_WAN#
<5> CLK_PCIE_WAN

TC7SH08FUF_SSOP5

R726

SM BUS Addr. 1001 001
1

<33,34,39> SMB_EC_DA1

PIDERST#

4

Y

C927

PCIE_WAKE#

U12

TC74A1-5.0VCT_SOT23-5

3EC_CK1
2N7002_SOT23

D

SMB_EC_CK1

3
2
1

B

3

SCLK
SDA

1

P

5
1
4
5

<22> PCIE_WAKE#

0.1U_0402_16V4Z

0.1U_0402_16V4Z

G

2

2

+5VS

U54

1

1

10K_0402_5%

+1.5VS +3VS

JP28

1

R913

R955
10K_0402_5%

<33,34,39> SMB_EC_CK1

2

PLT_RST#

Mini-Express Card---WWAN

+3VS

C669
<9,18,20,22,28,32,33,35>

Title
+5VS

Thermal Sensor for SO-DIMM
5

MINI Card Slot/PIDE&Thermal sensor

SM BUS Addr. 1001 010

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
24
1

Rev
X 0.5
of

53

4

1
2
1
2

S1_A13

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
CB_IDSEL

V3
W4
V4
V5
T5
P1

FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL

CFRAME#/CADR23
CTRDY#/CADR22
CIRDY#/CADR15
CSTOP#/CADR20
CDEVSEL#/CADR21
RESERVED/CADR19
CPERR#/CADR14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/CADR16

K16
L16
K15
M16
L18
N19
N18
G16
G19
M15
E18
A18
L19

S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16

PCI_PERR#
PCI_SERR#

W5
T6

PERR#
SERR#

PCI_REQ2#
PCI_GNT2#

M4
M5

REQ#
GNT#

K1
L4
G2
L5

PCICLK
PCIRST#
GBRST#
CLKRUN#

CINT#/RDY(IREQ#)

M18

S1_RDY#

CRST#/RESET

H19

CAUDIO/BVD2(SPKR#/LED)

F19

1
2
0.01U_0402_25V4Z C71
S1_BVD2
S1_BVD2

CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#

T14
D15
R16
H16

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2

RESERVED/CDATA14
RESERVED/CDATA2
RESERVED/CADR18

W18
C19
N16

S1_D14
S1_D2
S1_A18

C15 1
2

C14

1

2

C25

1

2

C

<20,27> PCI_PERR#
<20,27> PCI_SERR#

<20> PCI_REQ2#
<20> PCI_GNT2#

CLK_PCI_PCM_R
PCI_RST#
GBRST#
2
0_0402_5%
2
@ 100K_0402_5%

<20,27> PCI_RST#
1
R28
1
R29

<22,27,32,33,35> PM_CLKRUN#

J2
K4
K2

1
1

R45

Pull down UDIO4 to
disable MS function

PCM_PME#
PCM_SPK#
1
R34

<34> PCM_PME#
<30> PCM_SPK#
<33> HWSPND#

G4
F1
F2
F4

2
0_0402_5%

UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

<26>

S1_RST

<26>
<26>

C71,C188, C208 close to
JP33 cardbus connector

<26>
@ 2
<26>

1

S1_CD1# <26>
S1_CD2# <26>
2

@
C208

R46

+3V_R5C843

1

RI_OUT#/PME#
SPKROUT
HWSPND#
TEST
R5C843-CSP208P_CSP208~D

+3V_R5C843

1
R33
1

0.01U_0402_25V4Z1

2
10K_0402_5%
2
100K_0402_5%

C30

2

10K_0402_5%
<27> NEC_USBP0+
<27> NEC_USBP0R36

1

R27

2
0_0402_5%

<26>
<26>

VPPEN0
VPPEN1

3

<26>
<26>

VCC5EN#
VCC3EN#

3

A

OE#

5

B

4

2

VCC_MD3V
VCC_RIN1
VCC_RIN2

L1
E14

VCC_ROUT1
VCC_ROUT2

E10
E11
A17
B17

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

A9
B9
D9
D14
A15
B15

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6

J1
J5
K5
E9
R10
T10
V10
W10
L15
M19

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10

D

C

CPS

A16
B16
A14

XI
XO
FIL0

B12
A12

TPAP0
TPAN0

B13
A13

TPBP0
TPBN0

B10
A10

TPAP1
TPAN1

B11
A11

TPBP1
TPBN1

D12
D10

TPBIAS0
TPBIAS1

D13
B14

VREF
REXT

R5C843

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8

SD_DET#

SD_DET#

<26>

SD_WP#
SD_PWREN

SD_WP#
SD_PWREN

<26>
<26>

0_0402_5%
2
@2 0_0402_5%
SD_CMD
1
SD_CLK_R
33_0402_5%
1
SD_DAT0
33_0402_5%
1
SD_DAT1
33_0402_5%
1
SD_DAT2
33_0402_5%
1
SD_DAT3
33_0402_5%
1
33_0402_5%

R311
EXT_48M R321
MDIO08
2
SD_CLK R4802
MDIO10 R30 2
MDIO11 R4722
MDIO12 R4732
MDIO13 R4782
R479

1
C359
1
C360
1
C361
1
C362
1
C363

CLK_48M_SD <5>
SD_CMD
SD_CLK_R
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3

<26>
<26>
<26>
<26>
<26>
<26>
B

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

USBDP
USBDM
VPPEN0
VPPEN1

R13
T13

VCC5EN#
VCC3EN#

R7

REGEN#

CLK_48M_SD

R5C843-CSP208P_CSP208~D
R24
100K_0402_5%

R699
10_0402_5%
@

2

PCM_CLK_EN#

1

+3VS

GND
S1_CD1#

1
2

B
A

U49
Y

3

SD_DET#

2
4

CARD_INSERT#

C679
@ 4.7P_0402_50V8C

A

CARD_INSERT# <33>

TC7SH08FUF_SSOP5

2 CLK_PCI_PCM_R
@ 0_0402_5%

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

A4
R6
E13

CLK_PCI_PCM_R

SN74CBTD1G125_SC70-5

CLK_PCI_PCM 1
R60

1

R5C843

L2
C1
D1
E1
C2
D2
E2
E4
E12

2

VCC

A

5

1

CLK_PCI_PCM 2

D11

VCC5EN#
VCC3EN#

R50
100K_0402_5%

2 PCI_AD20
100_0402_1%

P

PCM_CLK_EN#

1
R848

G

<5> CLK_PCI_PCM

PCI_AD20_R

2
G

U48
<33> PCM_CLK_EN#

@

2

V13
W13

1

1

1

VCC_PCI3V1
VCC_PCI3V2
VCC_PCI3V3

2

S

D

CB_IDSEL

SI1303DL-T1-E3_SOT323-3~D

2

NEC_USBP0+ V14
NEC_USBP0- W14

Q67
+5VS

C24 1

VPPEN0
VPPEN1

1

1
R451

2

+3V_R5C843

W3
R11
R12

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

+3V_R5C843

270P_0402_50V7K

<22,32,33,35> SIRQ
B

2

VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4

U15B

S1_RDY#

S1_VS1
S1_VS2

C17

F5
G5
J19
K19

R5C843-CSP208P_CSP208~D

Layout notice: apply Shield GND
for L19 signal S1_A16

C188

J4
H1
H2
10K_0402_5%
H4
2
H5
2
10K_0402_5%G1

INTA#
INTB#
INTC#

S1_RST

<26>
<26>
<26>
<26>
<26>

270P_0402_50V7K

<20> PCI_PIRQA#
<20> PCI_PIRQC#

S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP

2

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

C13 1

0.01U_0402_25V4Z

<20,27>
<20,27>
<20,27>
<20,27>
<20,27>

2

2

1

0.01U_0402_25V4Z

N15

<26>

1
C18

2

0.01U_0402_25V4Z

CPAR/CADR13

PAR

2

S1_CE1#

2

C1

0.01U_0402_25V4Z

PCI_PAR

1

<26>

C2

1

+3V_R5C843

@ C9

S1_REG#

2

2

C3

1

0.01U_0402_25V4Z

S1_REG#
S1_A12
S1_A8
S1_CE1#

<26>
<26>

2

1

C23

1

0.01U_0402_25V4Z

F16
K18
P15
V19

<26>

S1_OE#
S1_CE2#

2

1
C5

0.01U_0402_25V4Z

<20,27> PCI_PAR

V6

CC/BE3#/REG#
CC/BE2#/CADR12
CC/BE1#/CADR8
CC/BE0#/CE1#

C/BE3#
C/BE2#
C/BE1#
C/BE0#

S1_IORD#

2

1
C6

0.01U_0402_25V4Z

P2
W2
W6
T9

<26>

1
C7

0.01U_0402_25V4Z

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

1
C8

USB signals, impedance 90 ohm

0.01U_0402_25V4Z

<20,27>
<20,27>
<20,27>
<20,27>

2
+3V_R5C843

0.1U_0402_16V7K

2

C27
1U_0402_6.3V6K

C4

10U_0805_6.3V4Z

GBRST#
1

1

S1_IOWR#

2
0_0805_5%
U15C

S1_D[0..15] <26>

0.01U_0402_25V4Z

R26
100K_0402_5%

R5C843

+3V_R5C843

S1_A[0..25] <26>

S1_D[0..15]

0.01U_0402_25V4Z

+3VS

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

10U_0805_6.3V4Z

2

C706
15P_0402_50V8J
@

B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14

0.01U_0402_25V4Z

1

S1_A[0..25]

CAD31/CDATA10
CAD30/CDATA9
CAD29/CDATA1
CAD28/CDATA8
CAD27/CDATA0
CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6
CAD19/CADR25
CAD18/CADR7
CAD17/CADR24
CAD16/CADR17
CAD15/IOWR#
CAD14/CADR9
CAD13/IORD#
CAD12/CADR11
CAD11/OE#
CAD10/CE2#
CAD9/CADR10
CAD8/CDATA15
CAD7/CDATA7
CAD6/CDATA13
CAD5/CDATA6
CAD4/CDATA12
CAD3/CDATA5
CAD2/CDATA11
CAD1/CDATA4
CAD0/CDATA3

10U_0805_6.3V4Z

R744
10_0402_5%
@

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

+3V_R5C843
1
R445

1

U15A
PCI_AD31
M2
PCI_AD30
M1
PCI_AD29
N5
PCI_AD28
N4
PCI_AD27
N2
PCI_AD26
N1
PCI_AD25
P5
PCI_AD24
P4
PCI_AD23
R4
PCI_AD22
R2
PCI_AD21
R1
PCI_AD20
T2
PCI_AD19
T1
PCI_AD18
U2
PCI_AD17
U1
PCI_AD16
V1
PCI_AD15
T7
PCI_AD14
V7
PCI_AD13 W7
PCI_AD12
R8
PCI_AD11
T8
PCI_AD10
V8
PCI_AD9
W8
PCI_AD8
R9
PCI_AD7
V9
PCI_AD6
W9
PCI_AD5
T11
PCI_AD4
V11
PCI_AD3 W11
PCI_AD2
T12
PCI_AD1
V12
PCI_AD0 W12

1

+3VS

<20,27> PCI_AD[0..31]

CLK_PCI_PCM

D

2

C505
0.47U_0603_10V7K

Layout notice:
apply shield GND
for CLK_PCI_PCM to
reduce external noise.

3

C506
0.47U_0603_10V7K

5

4

3

2

CARDBUS_R5C843
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
25
1

Rev
X 0.5
of

53

5

4

3

2

1

CARDBUS SOCKET
<25>

D

<25>

S1_A[0..25]

S1_A[0..25]

D

S1_D[0..15]

S1_D[0..15]

JP33

<25>

S1_CE1#

<25>

S1_OE#

<25>
<25>

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#

S1_WE#
S1_RDY#
+S1_VCC
+S1_VPP

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP

C

<25>

S1_WP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

SD SOCKET

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_CD1#

<25>

S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#

<25>
<25>
<25>
<25>

+SD_VCC
JP32
<25>
<25>
<25>

S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

C371
10P_0402_50V8J
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1

<25>
<25>
<25>
<25>
<25>
<25>
<25>

S1_CD2#

<25>

9

SD5

SD_DAT3
SD_CMD

1
2
3
4
5
6
7
8

SD1
SD2
Vss1
Vdd
SDCLK
Vss2
SD3
SD4

SD_CLK_R

<25> SD_CLK_R

+S1_VCC
+S1_VPP

SD_DAT2

1

<25>
<25>

SD_DAT0
SD_DAT1

10

<25> SD_DET#
2

Wr_Pt
Vss4
Vss3

14
13
12

MMC_DET# Wr_Pt_Vss

11

MOLEX_67600-0001

Close to SD socket
<25>

SD_WP#

C

FCI_62597-00B_RB

+3VS

2

4
3

EN1
EN0

NC
NC

10
7

VCC3EN#

2

VCC3_EN

FLG

5

VCC5EN#

1

VCC5_EN

GND

16

1
C38

0.1U_0402_16V7K
2

<25>
<25>

VPPEN1
VPPEN0

<25>

VCC3EN#

<25>

VCC5EN#

C10
0.01U_0402_25V4Z
2
+S1_VPP

C11
10U_0805_6.3V4Z
2

<25> SD_PWREN

4

ON/OFF#

AAT4250IGV-T1_SOT23-5

8
1

1
C36

C12

2
0.1U_0402_16V7K

0.01U_0402_25V4Z

1

B

OUT
GND
N.C

1

C35
1U_0402_6.3V6K

14
12
9

6

VCC3IN VCCOUT
VCCOUT
VCC5IN VCCOUT
VCC5IN
VPPOUT
NC

13
15

IN

2

Closer to JP32

2

C40 1 R643
0.1U_0402_16V7K

11

1

1

U26

1
2
3

2

150K_0402_5%

+5VS

0.1U_0402_16V7K

Q15
5

2

1
C41

+SD_VCC

+3V_R5C843

+S1_VCC

B

R5531V002-E2-FA_SSOP16

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

PCMCIA Slot/SD
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
26
1

Rev
X 0.5
of

53

5

4

3

2

1

+3V_NECUSB
RP54
+3VS

2

A6
B6
C5
A5
C4
B5
A4
B4
C1
C2
D2
D1
D3
E1
E3
F2
J1
J2
K3
K1
L3
K2
L1
L2
M1
N3
M3
N4
P4
N5
P5
M5

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

C3
F1
J3
M2

CBE3#
CBE2#
CBE1#
CBE0#

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
USB_IDSEL
PCI_DEVSEL#
PCI_REQ0#
PCI_GNT0#
PCI_PERR#
PCI_SERR#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
CLK_PCI_USB_R
VBBRST#
USB_PME#

J4
F3
F4
G1
G3
B3
G2
C6
D6
H2
H1
C7
B7
A7
A8
B8
D9

PAR
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
REQ0#
GNT0#
PERR#
SERR#
INTA#
INTB#
INTC#
PCLK
VBBRST#
PME#

L6
L7

SMI#
LEGC

5
6
7
8

10K_0804_8P4R_5%
+5VS
+3V_NECUSB
C

U50
USB_CLK_EN#

<33> USB_CLK_EN#
<5> CLK_PCI_USB

CLK_PCI_USB

1

OE#

2

A

3

GND

VCC

5

B

4

NEC_USB_OC#4

R324
1
2
10K_0402_5%

CLK_PCI_USB_R

SN74CBTD1G125_SC70-5

CLK_PCI_USB

1
R75

2 CLK_PCI_USB_R
@ 0_0402_5%
+5VS

U53
USB_CLK_EN#

<33> USB_CLK_EN#
<5> CLK_48M_USB

1

CLK_48M_USB 2
3

OE#

VCC

5

B

4

A

CLK_48M_USB_R

GND

SN74CBTD1G125_SC70-5

B

CLK_48M_USB 1
R74 @

2 CLK_48M_USB_R
0_0402_5%
<22,33> EC_RSMRST#

EC_RSMRST# 1
R321
PCI_RST#

BT MODULE CONN

1
R320

<22> USB_SMI#

+3VS

<20,25>
<20,25>
<20,25>
<20,25>

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

<20,25>
<20,25>
<20,25>
<20,25>
<20,25>

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#

<20,25>
<20>
<20>
<20,25>
<20,25>
<20>
<20>
<20>

PCI_DEVSEL#
PCI_REQ0#
PCI_GNT0#
PCI_PERR#
PCI_SERR#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#

2
@ 0_0402_5%

<34> USB_PME#

USB_SMI#

+3V_NECUSB

2

0.1U_0402_16V4Z
JP15
<24> BT_ACTIVE
<24> WLAN_ACTIVE
<33> BTDIS#

BT_ACTIVE
NEC_USBP2+
NEC_USBP2WLAN_ACTIVE

1
2
3
4
5
6
7
8

<20,25> PCI_RST#

<22,25,32,33,35> PM_CLKRUN#

MOLEX_53780-0890

PCI_RST#

PM_CLKRUN#

R344
2
R345
2

1.5K_0402_5%
1
1.5K_0402_5%
1

R342
2
2
R343

1.5K_0402_5%
1
1
1.5K_0402_5%

R346
2
1
R312

1.5K_0402_5%
1
2
@ 0_0402_5%

1
R314

1

C80

2
AVSS

N10
N12

H3
M4
C8

P2
P3
P12
A13
A12
A3
E2
N8
L13
J13
H13
F13
D13
G12
H4
D7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

AVDD
AVDD

RSDM2
DM2
DP2
RSDP2

K14
K12
J14
J12

NEC_USBP1-_R R304 1
NEC_USBP1NEC_USBP1+
NEC_USBP1+_RR305 1

2 36_0603_1%

RSDM3
DM3
DP3
RSDP3

H11
G11
G13
G14

NEC_USBP2-_R R306 1
NEC_USBP2NEC_USBP2+
NEC_USBP2+_RR307 1

2 36_0603_1%

P6
M6
VCCRST#

C9

N6

L9
P8

2 36_0603_1%
NEC_USBP0- <25>
NEC_USBP0+ <25>

2 36_0603_1%

NEC_USBP1- <24>
NEC_USBP1+ <24>

2 36_0603_1%

C

2 36_0603_1%

+3VS
@ ACES_85201-0405

USB 2.0 CONTROLLER
uPD720101F1-EA8
FBGA144

RSDM4
DM4
DP4
RSDP4

F12
F14
E12
E14

NEC_USBP3-_R R308 1
NEC_USBP3NEC_USBP3+
NEC_USBP3+_RR309 1

2@36_0603_1%

RSDM5
DM5
DP5
RSDP5

E13
D14
C13
C14

NEC_USBP4-_R R310 1
NEC_USBP4NEC_USBP4+
NEC_USBP4+_RR311 1

2 @ 36_0603_1%

1
2
3
4
JP29

2@36_0603_1%

2@ 36_0603_1%

USB_AVDD
2

RREF
AVSS(R)

P11
N11

OCI1
OCI2
OCI3
OCI4
OCI5

B12
B11
B10
A10
B9

PPON1
PPON2
PPON3
PPON4
PPON5

C12
A11
C11
C10
A9

NTEST1
SMC
AMC
TEB
TEST
NANDTEST

C351
@ 0.1U_0402_16V4Z

R329
1
2
9.1K_0402_1%
C349
@ 0.1U_0402_16V4Z
1
AVSS
1
2

NEC_USB_OC#0
NEC_USB_OC#1
NEC_USB_OC#2
NEC_USB_OC#3
NEC_USB_OC#4

B

M8
M7
P7
N7
L8
M10
+3V_NECUSB

N.C.
N.C
SRCLK
SRDTA
SRMOD

VCCRST#

CRUN#

2
0_0402_5%

M9
N9
P9

R341
2
2

1.5K_0402_5%
1
1

R340

1.5K_0402_5%

uPD720101F1-EA8-A_FBGA144
A

2

A

RSDM1
DM1
DP1
RSDP1

CLK_48M_USB_R
1
2
R73
@0_0402_5%
NEC_USBP0-_R
R318 1
M14
M13 NEC_USBP0L14 NEC_USBP0+
K13 NEC_USBP0+_RR319 1

XT1/SCLK
XT2

2
0_0402_5%

C742
1

VDD_PCI
VDD_PCI
VDD_PCI

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

RP30
4
3
2
1

2

C79

C350
@ 0.1U_0402_16V4Z
U27

+3V_NECUSB

NEC_USB_OC#0
NEC_USB_OC#1
NEC_USB_OC#2
NEC_USB_OC#3

USB_CLK_EN#

1

1

AVSS
AVSS

@
2
G

SI1303DL-T1-E3_SOT323-3~D

R856
2
1 PCI_AD21
100_0402_1%

1

P13
M12

3

<20,25> PCI_AD[0..31]

2

B1
N1
P10
N14
H14
B14
A2
B2
N2
N13
B13
M11
L12
H12
D12
G4
J11
F11
D8

1

R261
1
2
0_0603_5%

1

C358

2

C72

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1
2
PCI_AD21_R

S

D

USB_IDSEL

1

10U_0805_6.3V4Z

R322
1
2
15K_0402_5%
R323
NEC_USBP4+ 1
2
15K_0402_5%
NEC_USBP4-

Q68

2

2
C357

D

@

2
0_0402_5%

2

2

C78

USB_AVDD

+3V_NECUSB

15K_1206_8P4R_5%

1
R452

1

1

10U_0805_6.3V4Z

C707
15P_0402_50V8J
@

1

C355

C77

10U_0805_6.3V4Z

2

1

C354

1

0.1U_0402_16V4Z

2

C678
@ 4.7P_0402_50V8C

1

C353

2

0.1U_0402_16V4Z

1

1

C352

2

10U_0805_6.3V4Z

8
7
6
5

1

C356

2

10U_0805_6.3V4Z

R748
10_0402_5%
@

2

0.1U_0402_16V4Z

RP55
1
2
3
4

1
2
0_0603_5%
2

R698
10_0402_5%
@
NEC_USBP3+
NEC_USBP3NEC_USBP2+
NEC_USBP2-

2

0.1U_0402_16V4Z

15K_1206_8P4R_5%

D

1

0_0805_5%

CLK_PCI_USB
1

CLK_48M_USB

0.1U_0402_16V4Z

8
7
6
5

0.1U_0402_16V4Z

1
2
3
4

R260

0.1U_0402_16V4Z

NEC_USBP1+
NEC_USBP1NEC_USBP0+
NEC_USBP0-

USB_AVDD

R826

AVSS

R313
0_0402_5%
@
1

Bluetooth Cable
Mini Card Pin5

BT_ACTIVE JP27.1

Mini Card Pin3

WLAN_ACTIVE JP27.4

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

BT&USB CONTROLLER
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
27
1

Rev
X 0.5
of

53

5

4

3

2

1

+3V_LAN

U13

+3V_LAN

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

1

VPD_CLK
VPD_DATA

2

R47
4.7K_0402_5%

<22> LAN_WAKE#

LAN_WAKE#
XTALI
XTALO
R39 1
R76 1
@R78 1
R77 1
@R79 1

+3V_LAN

2 10K_0402_5%
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

1
R81

MAR_DISABLE
MAR_VAUX
MAR_VMAIN

MAR_RSET
LAN_CTRL25
LAN_CTRL12

2
4.75K_0402_1%

TESTMODE
TSTPT

46
29

VDD25

64

AVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL

19
22
28
32
51
52
57

TEST
POWER
&

Media

GROUND

38
41

VPD_CLK
VPD_DATA

34
35
37
36

SPI_DO
SPI_DI
SPI_CLK
SPI_CS

15
14

XTALI
XTALO

10
12
11
47
9
24
25
16
4
3

LOM_DISABLEn
VAUX_AVLBL
SWITCH_VCC
VMAIN_AVLBL
SWITCH_VAUX
HSDACP
HSDACN
Analog
RSET
CTRL25
CTRL12

AVDD

23

VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL

1
8
40
45
61

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

2
7
13
33
39
44
48
58

EPAD

65

SMCLK/NC
SMDATA/NC

42
43

EEPROM
FLASH
MEMORY
CLOCK

LAN_ACT#

LAN_ACT#

<29>

LAN_LINK#

LAN_LINK#

<29>

R38
4.7K_0402_5%

PLACE PNP TO CHIP ACAP
CTRL12 PIN TRACE IS
25MIL

3

17
18
20
21
26
27
30
31

59
60
62
63

1

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

PCI-E

LED_ACTn
LED_LINK10/100n
LED_LINK1000n
LED_LINKn

TP1

PAD
2
+LAN_AVDDL

LAN_CTRL12

+2.5V_LAN

Q50
D

1

C60

BCP69_SOT223
2
4

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

LED

1 0.1U_0402_16V4Z
C48
4.7U_0805_10V4Z

1

1

2

2

+3V_LAN
+3V_LAN

40 mil

+1.2V_LAN

PLACE PNP TO CHIP ACAP
CTRL25 PIN TRACE IS
25MIL

R35
4.7K_0402_5%
LAN_CTRL25

Q53
1
BCP69_SOT223

40mil
C50
4.7U_0805_10V4Z

88E8053-NNC1C000_QFN64

1

1

2

2

Y8
C56

25MHZ_20PF_6X25000017

1

2

R41

1

C69
18P_0402_50V8J

4.7K_0402_5%
VPD_CLK
VPD_DATA

2

C70
18P_0402_50V8J

0.1U_0402_16V4Z
2

1

1

1

2

C

C51
0.1U_0402_16V4Z

+3V_LAN

XTALO

2

2

+2.5V_LAN

9 Vias to Ground at least.

+3V_LAN

1

C73
0.1U_0402_16V4Z

+LAN_AVDD

C

XTALI

40mil +1.2V_LAN

3

<29>
<29>
<29>
<29>
<29>
<29>
<29>
<29>

TX_P
TX_N
RX_P
RX_N
WAKEn
REFCLKP
REFCLKN
PERSTn

2
4

D

49
50
54
53
6
55
56
5

2

<5> CLK_PCIE_LAN
<5> CLK_PCIE_LAN#
<9,18,20,22,24,32,33,35> PLT_RST#

C46 0.1U_0402_16V4Z
PCIE_RXP1 1
PCIE_MAR_T+
2
PCIE_RXN1
1
2 PCIE_MAR_TPCIE_TXP1 C47
0.1U_0402_16V4Z
PCIE_TXN1
LAN_WAKE#
CLK_PCIE_LAN
CLK_PCIE_LAN#
PLT_RST#

1

PCIE_RXP1
PCIE_RXN1
PCIE_TXP1
PCIE_TXN1

2

<22>
<22>
<22>
<22>

R40
4.7K_0402_5%
8 VCC
7 WP
6 SCL
5 SDA

U20
A0
A1
A2
GND

1

1
2
3
4

2

1
C75
0.1U_0402_16V4Z

2

C52
0.1U_0402_16V4Z

1

1

2

C53
0.1U_0402_16V4Z
2

C54
0.1U_0402_16V4Z
2

1

C55
0.1U_0402_16V4Z

AT24C16AN-10SU-2.7_SO8~N

TRACE TO IC IS 25MIL
+LAN_AVDDL

2
B

2

2

2

1

C74
C61
0.1U_0402_16V4Z
1 0.1U_0402_16V4Z

C59
1 0.1U_0402_16V4Z

+3VALW

2

2

R288
1
0_0603_5%

2

+LAN_AVDD

R289
1
0_0603_5%

B

2

2

C62
1 0.1U_0402_16V4Z

+2.5V_LAN

C57
0.1U_0402_16V4Z

1

+3V_LAN

1

C58
0.1U_0402_16V4Z

1

C49
0.1U_0402_16V4Z

+1.2V_LAN

PJP25
2

1

PAD-SHORT 2x2m
D

+12VALW

Q52
2

R793

S

2
4

2
C63

2
C64

1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z

SI3456BDV-T1-E3_TSOP6

G

1

6
5
2
1

R794
10K_0402_5%

2
C65

1 0.1U_0402_16V4Z

2
C66

2
C67

C68

1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z

1 0.1U_0402_16V4Z

3

1

+3VALW

1

2

10K_0402_5%

<33>

LAN_EN#

LAN_EN#

Note: Place Bypass Cap. with every power pin ACAP.

D
Q51

2
G
3

A

S

1

2

C750
0.01U_0402_16V7K

A

2N7002_SOT23

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

88E8053
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
28
1

Rev
X 0.5
of

53

5

4

3

Close to Chip side
1
C776

2
0.01U_0402_16V7K

1
C777

2
0.01U_0402_16V7K

2
0.01U_0402_16V7K

1
C780

1
C781

1
49.9_0402_1%
1
49.9_0402_1%
1
49.9_0402_1%
1
49.9_0402_1%
1
49.9_0402_1%
1
49.9_0402_1%
1
49.9_0402_1%
1
49.9_0402_1%

1

LAN_MDI0+

2
D

0_0805_5%

LAN_MDI0LAN_MDI1+

C778
@ 0.047U_0402_16V7K

LAN_MDI1LAN_MDI2+
LAN_MDI0-

<28> LAN_MDI0-

LAN_MDI2LAN_MDI3+

LAN_MDI0+

<28> LAN_MDI0+

LAN_MDI3-

LAN_MDI1-

<28> LAN_MDI1-

LAN ANALOG
SWITCH

LAN_SW_VCC

L26 1
2
@BLM18AG601SN1D_0603 1

+3V_LAN

1
C779

2

0.1U_0603_16V7K

WCM-2012-900T_4P~D
1 1
2 2
L22

U24

2

LAN_MDI0-R

4

4
3 3
1WCM-2012-900T_4P~D
1
2 2

2

<28> LAN_MDI1+

LAN_MDI2-

<28> LAN_MDI2-

LAN_MDI2+

<28> LAN_MDI2+

LAN_MDI3-

<28> LAN_MDI3-

LAN_MDI3+

<28> LAN_MDI3+

DOCKEN

C

LAN_MDI1+
LAN_MDI2LAN_MDI2+
LAN_MDI3-

4

4
3 3
WCM-2012-900T_4P~D
1 1
2 2
L25
4

4

3

3

3

A1

2B1
3B1

LAN_MDI1-R

7

A2

4B1
5B1

37
36

SW_LAN_TX2SW_LAN_TX2+

LAN_MDI1+R

8

A3

6B1
7B1

32
31

SW_LAN_RX3SW_LAN_RX3+

LAN_MDI2-R

11

A4

LAN_MDI2+R

12

A5

0LED1
1LED1
2LED1

22
23
52

LAN_MDI3-R

14

A6

0B2
1B2

46
45

DOCK_LAN_TXDOCK_LAN_TX+

LAN_MDI3+R

15

A7

2B2
3B2

41
40

DOCK_LAN_RXDOCK_LAN_RX+

17

SEL

4B2
5B2

35
34

DOCK_LAN_TX2DOCK_LAN_TX2+

19
20
54

LED0
LED1
LED2

6B2
7B2

30
29

DOCK_LAN_RX3DOCK_LAN_RX3+

0LED2
1LED2
2LED2

25
26
51

DOCK_LAN_ACT#

DOCKEN

DOCKEN

0: TO RJ45

<28> LAN_ACT#

Layout Notice : Place ckoke as
close PI3L500 as possible

LAN_MDI0-R

<28> LAN_LINK#

LAN_MDI0+R
5
LAN_MDI1-R

@ R821
1
2
0_0603_5%
R822
1@
2
0_0603_5%
@ R823
1
2
0_0603_5%
@ R824
1
2
0_0603_5%

SW_LAN_RXSW_LAN_RX+

LAN_MDI0+R

TO
RJ45

DOCK_LAN_TX- <36>
DOCK_LAN_TX+ <36>
DOCK_LAN_RX- <36>
DOCK_LAN_RX+ <36>

TO
DOCK

DOCK_LAN_TX2- <36>
DOCK_LAN_TX2+ <36>

C

DOCK_LAN_RX3- <36>
DOCK_LAN_RX3+ <36>
DOCK_LAN_ACT# <36>

DOCK_LAN_LINK#

DOCK_LAN_LINK# <36>

NC

LAN_MDI1+R

PI3L500ZFE_TQFN56

FROM NIC
LAN_MDI2-R
LAN_MDI2+R
LAN_MDI3-R

@
1 R825 2
0_0603_5%

LAN_MDI3+R
+2.5V_LAN

1

LAN_MDI3+

4
3
WCM-2012-900T_4P~D
1 1
2 2
L24

SW_LAN_TXSW_LAN_TX+

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

LAN_MDI1-

<33>

3

48
47

1
6
9
13
16
21
24
28
33
39
44
49
53
55

LAN_MDI0LAN_MDI0+

@ R818
1
2
0_0603_5%
@ R819
1
2
0_0603_5%
@ R820
1
2
0_0603_5%

1: TO DOCK

4

0B1
1B1

A0

43
42

L23
LAN_MDI1+

56
50
38
27
18
10
4

2
0.01U_0402_16V7K

1

R800
2
R801
2
R802
2
R803
2
R804
2
R805
2
R806
2
R807
2
R808

VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0

D

2

R809
0_0603_5%

B

T21

2

B

SW_LAN_TX+
SW_LAN_TX-

C782

SW_LAN_RX+
SW_LAN_RX-

C783

SW_LAN_TX2+
SW_LAN_TX2-

C784

SW_LAN_RX3+
SW_LAN_RX3-

C785

1

1

1

1

2

2

2

2

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

1
2
3

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

24
23
22

RJ45_MDI0+
RJ45_MDI0-

4
5
6

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MDI1+
RJ45_MDI1-

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MDI2+
RJ45_MDI2-

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

RJ45_MDI3+
RJ45_MDI3-

1
R810
1
R811
1
R812
1
R813

JP16

2
75_0402_1%
2
75_0402_1%
2
75_0402_1%
2
75_0402_1%
2
C786
1000P_1206_2KV7K

BOTH_GST5009-V LF

1

9

SHLD1

RJ45_MDI3-

8

PR4-

RJ45_MDI3+

7

PR4+

RJ45_MDI1-

6

PR2-

RJ45_MDI2-

5

PR3-

RJ45_MDI2+

4

PR3+

RJ45_MDI1+

3

PR2+

RJ45_MDI0-

2

PR1-

RJ45_MDI0+

1

PR1+

10

SHLD2
ALLTOP_C10068-10804

C271
0.001U_0402_50V7M
1
2
A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Magnetics & RJ45
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
29
1

Rev
X 0.5
of

53

5

4

3

2

1

VDDA

2
C788

100K_0402_5%

0.1U_0402_16V4Z

@

MB_HP_PLUG# 2
G
2N7002_SOT23

CAP2

1

GPIO pin
<33>

MIC_SEL
VDDC

3
2

0_0402_5%

1

AFILT2

45
46
44
47
48
43

9228@ R58
0_0402_5% 40
1

B

BIT_CLK
SDATA_IN
SDATA_OUT
SYNC
RESET#

MB_HP_L

<31>

NOTE: Place pull-up
resistors close to
CODEC Pin25

1

2

C2
A1
A3
C3
B2

SENSE_B

1

PORT_B_L
PORT_B_R

21
22

MB_MIC_L
MB_MIC_R

PORT_C_L
PORT_C_R

23
24

C21

PORT_D_L_HP
PORT_D_R_HP

35
36

HP_OUT_L
HP_OUT_R

HP_OUT_L
HP_OUT_R
INT_MIC1
INT_MIC3

INT_SPK_L
INT_SPK_R

2

SENSE_A
VDDA

R49

2@

100K_0402_5%

Port A for MB HP

CAP2
VREF_FILT
AFILT1
AFILT2

9228@ C799
0.1U_0402_16V4Z

2

4
7

PORT_E_L
PORT_E_R

14
15

PORT_F_L_HP
PORT_F_R_HP

16
17

INT_SPK_L
INT_SPK_R

VREFOUT_A

37

GPIO0
GPIO1
GPIO2
GPIO3/SPDIFIN/EAPD

VREFOUT_B

28

VREFOUT_C

29

VREFOUT_D

32

CD_L

18

CD_G

19

SPDIF_OUT
PLL_CAP
NC

Q58

<31,36> HP_PLUG#

DOCK/B ext mic

INT_MIC3

20

INT_MIC2

PC_BEEP

12

PC_BEEP

AVSS1
AVSS3

26
42

<36>
Port
<36> D

D

DOCK_HP_PLUG#

For DOCK HP

for MB ext mic

DOCK_MIC Port
<36>
C for

VrefOut_B

CD_R

DVSS2
DVSS3

<31>
Port
<31>B

0.33U_0603_16V4Z

INT_MIC1
INT_MIC3

VOLUME_DOWN
VOLUME_UP

MB_MIC_L
MB_MIC_R

Q59

2
G
2N7002_SOT23

D

2
G
2N7002_SOT23

For DOCK MIC

Q60

2
G
2N7002_SOT23

<36> DIS_INTMIC
S

D

S

1

1

2

2

C20
0.1U_0402_16V4Z

MB_HP_L1
MB_HP_R1

R20
5.11K_0402_1%~D

C19
0.1U_0402_16V4Z

39
41

R19
5.11K_0402_1%~D

R963
39.2K_0603_1%

PORT_A_L_HP
PORT_A_R_HP

STAC9220

2

9228@R61

2

9220@R59 0_0402_5%

9220@ C32
820P_0603_50V7K

9220@ C26
820P_0603_50V7K

2

10U_0805_6.3V6M

C33

10U_0805_6.3V6M

C31
2

1

6
8
5
10
11

33
27
30
31

AFILT1
1

MB_HP_L
VDDA

1
ICH_AZ_CODEC_BITCLK
SDATA_IN
1
2
33_0402_5% ICH_AZ_CODEC_SDOUT
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_RST#
R747

ICH_AZ_CODEC_BITCLK
ICH_AZ_CODEC_SDIN0
ICH_AZ_CODEC_SDOUT
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_RST#

DVDD_CORE1
DVDD_CORE3

<31>

Place bypass capacitor
close to CODEC Pin26

MB_HP_PLUG# <31>
For

MB HP
C

S
MIC_SENSE For
<31>MB

EXT MIC

for DOCK/B HP

<36>E for INT_MIC1
Port
<31>
and
INT_MIC3
<31>

Port
<31> F for internal speaker

<31>

VDDA
INT_MIC3

<31>

CD input pins for
INT_MIC2 and INT_MIC3
INT_MIC2

1

<21>
<21>
<21>
<21>
<21>

SENSE_A
SENSE_B

SENSE_A
SENSE_B

D

R962
20K_0603_1%

1
9

R746 @
1
2
27P_0402_50V8J 22_0402_5%

MB_HP_R

MAX9890AEBL+T_UCSP9

13
34

AVDD1
AVDD2

MB_HP_R

2@

U47 2@
SHDN# VCC
INL
OUTL
INR
OUTR
GND
CEXT
NC

U22

25
38

C22 @

C

2

ShutDown#

C1
B1
B3
A2

Analog ground

R815 @
100K_0402_5%

<36>
<33>

BEEP#

2
R814

1
1
2K_0402_5%C796

2
1U_0603_10V4Z

<25>

PCM_SPK#

2
R816

1
1
2
2K_0402_5% C793 1U_0603_10V4Z

<22>

ICH_SPKR

2
R817

1
1
2
2K_0402_5% C794 1U_0603_10V4Z

2

2

2

1

Digital ground

PC_BEEP

B

1

2

1

<33>

C416 @
22U_0805_6.3V6M

R961
10K_0603_1%

Place decoupling
caps as close to
Codec as possible.

1

C797
0.1U_0402_16V4Z

C16
1U_0603_16V6K

1
2
MBK1608301YZF_0603

1

2
0_0603_5%

VDDA

2

2
0_0603_5%
2
0_0603_5%
2
0_0603_5%

VDDA

1@
1 R25

MB_HP_L1

2

S

ShutDown#

1

1

MB_HP_R1

C792
0.1U_0402_16V4Z

VDDC

L21

1@
R23
0_0603_5%
1
2

GNDA

C34
10U_0805_6.3V6M

+3VS

<31,36>

1

C800
0.1U_0402_16V4Z

@

ShutDown#
D

3

R48
0_0402_5%
<33,37,39> SUSP#

Q62

R960
5.11K_0402_1%~D

TPS793475DBVR_SOT23-5

2

1

2

4.7U_0805_10V4Z
2
0.1U_0402_16V4Z

3

2

GND

D

C791

1 1

1

R57

3

4

BYPASS
EN

1
R16
1
R17
1
R18

2@

2

3

0.1U_0402_16V4Z

1

1

2

C790

1 C787

3

2

1

5

VOUT
VIN

C798
0.1U_0402_16V4Z

1
C789
4.7U_0805_10V4Z

1

VDDA

w=40mil

VDDA

Io= 200mA
Vo= 4.65V ~ 4.85V
w=30mil

U18

C39
1U_0603_16V6K

+5VALW

@ D18
1SS355_SOD323

STAC9220X5TAEA6XR_LQFP48~D

1

0.1U_0402_16V4Z

2

2

C795

Item

STAC9228

STAC9220

C26,C32

POP

DE_POP

R58,C799

DE_POP

POP

R59

POP

R61

DE_POP

DE_POP

DIS_INTMIC

INT_MIC1
INT_MIC2
INT_MIC3

DOCK_MIC
(PIN 23/24)

MB_HP_PLUG#
(EAPD function)

INT_SPK_L
INT_SPK_R

PIN16
PIN17

MIC_SEL

INT_MIC1

INT_MIC2

INT_MIC3

(PIN 46)

(PIN 14)

(PIN 20)

(PIN 15,18)

H

DISABLE

ENABLE

H

ENABLE

L (Landscape)

ENABLE

DISABLE

ENABLE

L

ENABLE

DISABLE

L

DISABLE

H (Portrait)

DISABLE

ENABLE

ENABLE

POP

MIC2 O

O MIC1

MIC3 O

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Azalia Codec STAC9220
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
30
1

Rev
X 0.5
of

53

5

+5VS

4

Gain Setting

GAIN0

GAIN1

AV(inv)

3

2

1

INPUT
IMPEDANCE

R831
1

1

1

VDDA
R827
10K_0402_5%
@

R828
10K_0402_5%

0

6dB

90K ohm

2

4.7K_0402_5%

Compal P/N: SCVL080C000

*

0

1

10dB

70K ohm

1

0

15.6dB

45K ohm

1

1

21.6dB

25K ohm

Internal MIC3
D

2

2

D

GAIN0

0

ACES_85201-0405
1

1

GAIN1
R829
10K_0402_5%

2

<30> INT_MIC3

INT_MIC_3

1

1
2
L36
FBMA-L11-160808-700LMT

C815 0.22U_0603_10V7K

R830
10K_0402_5%

<30,36>

2

2

@

1
2
3
4
JP19

INTMIC3

GNDA

DVT2 swap pin

L35
1

2

+5VS

BLM21PG221SN1D_0805

+5VAMP

MB HP
PORT A

W=30mils
C816

1

1

1

C817

1

C818

C819

C

GAIN1

GAIN1

ROUT+

18

INTSPK_R+

ROUT-

14

INTSPK_R-

LOUT+

4

INTSPK_L+

LOUT-

8

INTSPK_L-

RIN-

<30>

MB_HP_L

MB_HP_L

R700
4.99_0402_1%
1
2
R707
4.99_0402_1%
1
2

1

PORTA_3L

1

C827

1

INT_SPK_L

5

2

LIN-

1

R845
20K_0402_5%

2

LIN+

C824
<30>

PORTA_2L
2
220U_D2_4VM

2

9
2 C823
0.47U_0603_16V4Z

PORTA_2R
2
220U_D2_4VM

R844
20K_0402_5%

0.1U_0402_16V4Z
1

L42
BK1608HM601-T_0603
1
2
L47
BK1608HM601-T_0603
1
2

C826
PORTA_3R

<30> MB_HP_PLUG#
PORTA_1R

MB_HP_PLUG#

4
3
2
1

PORTA_1L

1

2

C835
0.01U_0402_25V4Z

17

2

3

MB_HP_R

C836
0.01U_0402_25V4Z

C822
1

<30> INT_SPK_R

GAIN0

GAIN0

<30> MB_HP_R

2

RIN+

2

6
5

1

7
2 C821
0.47U_0603_16V4Z

1

C

JP20

0.1U_0402_16V4Z

1

2

+

2

10U_0805_10V4Z

+

2

U16

16
15
6

2

0.1U_0402_16V4Z

VDD
PVDD1
PVDD2

0.1U_0402_16V4Z

SUYIN_010030FR006G100ZL

0.1U_0402_16V4Z
VDDA

0.1U_0402_16V4Z

<30>

VrefOut_B

VrefOut_B

1

2

4.02K_0603_1%
4.7U_0805_10V4Z

TC7SH08FUF_SSOP5

MUTE#

2
R841

MB_MIC_R

MB_MIC_R

<30>

MB_MIC_L

MB_MIC_L

Speaker

A

D33

4

VIN

IO1

2

3

IO2 GND

1

PRTR5V0U2X_SOT143-4

1
2

@ R846

@ R847

20K_0402_5%

MOLEX_53780-0290
JP18
2 2
1 1

1

20K_0402_5%
2
2

INTSPK_LINTSPK_L+
D32

1
2

L48
BLM18AG601SN1D_0603
1
2
L51
BLM18AG601SN1D_0603
1
2

2PORTB_2R
2.2U_0805_25V6K
C42
1
2PORTB_2L
2.2U_0805_25V6K
1

1

JP17

6
5

4.02K_0603_1%
1

1

C45
<30>

JP21

R840

4.02K_0603_1%

INTSPK_R+
INTSPK_R-

B

PORT B

1

<30> MIC_SENSE
PORTB_1R

MIC_SENSE

PORTB_1L

1

2

4
3
2
1

C833
220P_0402_50V7K

2

R5

2

GND1
GND2
GND3
GND4

2
TPA6017A2PWPRG4_TSSOP20~N

C831

C834
220P_0402_50V7K

<33>

3

TC7SH08FUF_SSOP5

4

MB ext MIC

1
C830

2

Y

BYPASS

1

1

A

10

2

B

2

U31

20
13
11
1

1

12

SHUTDOWN

P

Y
A

4

NC
BYPASS

G

B

2

P

5

1
2

R1
@ 100K_0402_5%

U30

3

<30> MB_HP_PLUG#

1

G

<30,36> HP_PLUG#

5

R2
100K_0402_5%
2

B

19

C828
10U_0805_10V4Z

1

VDDA

SUYIN_010030FR006G100ZL

MOLEX_53780-0290

4

VIN

IO1

2

3

IO2 GND

1

A

PRTR5V0U2X_SOT143-4

+5VS

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

AMP & Audio JACK
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
31
1

Rev
X 0.5
of

53

4

3

USB_0S USB_1S

USB_0
L49
1
2 W=40mils
FBMA-L11-451616-800LMA10T
1
1
+ C837
C838
C839
150U_D2_6.3VM
0.1U_0402_16V4Z
2
2

+5VALW

1A

USB Port 0
D27

2

1

U29

1

1
2
3
4

1
C690

2
4.7U_0805_10V4Z

C691

GND
IN
EN1#
EN2#

8
7
6
5

OC1#
OUT1
OUT2
OC2#

TPS2062DR_SO8~D

2

R951

2
47_0402_5%

USB_OC#0

1
R14

2
47_0402_5% 1

USB_OC#1
1

<22>

R953
@ 0_0402_5%

2
1
D

USB_OC#1

<22>

0.001U_0402_50V7M

<22>
<22>

C28

0.1U_0402_16V4Z 2

WAKE_PWR_EN# <33,36>

IO1

IO2 GND

JP22

C29

1

VIN

3

PRTR5V0U2X_SOT143-4
USB_OC#0

USBP01
USBP0+ R849 1
R850

USBP0USBP0+

2 0.1U_0402_16V4Z

0_0402_5%

1
2
3
4

USB20_N0_R
USB20_P0_R

2
2 0_0603_5%
0_0603_5%
1

1

VCC
DD+
GND

Required by Motion
for ESD protect

SUYIN_020173MR004S583ZL

C330

C329

1

2

1
R15

4

5

0.1U_0402_16V4Z
W=40mils

1

USB_0S

USB Over Current

D

2

6

5

2
@ 3.3P_0402_50V8J

2
@ 3.3P_0402_50V8J

2

USB Port 1
USB_1S

USB_1
L50

1
2 W=40mils
FBMA-L11-451616-800LMA10T
1
C840
0.1U_0402_16V4Z

<21,24,33,35>
<21,24,33,35>
<21,24,33,35>
<21,24,33,35>
<21,24,33,35>
<9,18,20,22,24,28,33,35>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#

<22,25,33,35> SIRQ
<5> CLK_PCI_TPM
<22,25,27,33,35> PM_CLKRUN#

PM_CLKRUN#

26
23
20
17
22
16
28
27
21
15
7

GPIO
GPIO2

1

2
2 0_0603_5%
0_0603_5%
1

USB20_N1_R
USB20_P1_R
1

5

1
2
3
4

VCC
DD+
GND

C

6

USBP11
USBP1+ R851 1
R852

SUYIN_020173MR004S583ZL

C332

C331

C853
0.1U_0402_16V4Z

2
@ 3.3P_0402_50V8J

2
@ 3.3P_0402_50V8J

PAD

6
2

PAD
R854
2

SLB 9635 TT 1.2
CLKRUN#

2

TEST1
TESTB1/BADD

R860
1

8
9

BADDR 1
R858

T23
T22
0_0603_5%
1
@ 4.7K_0402_5%
2

Base I/O Address
0 = 02Eh
*1 = 04Eh(Default)

2

+3VS
4.7K_0402_5%

PP
NC
NC
NC

TPM_XTALO

14

XTALO

TPM_XTALI

13

XTALI/32K IN

3
12
1

R855 @
0_0402_5%
1
2

2

0.1U_0402_16V4Z

1

B

TPM_LPCPD#

2

A

CLK_PCI_TPM

TPM_XTALI

1
C925

1
2

R952
10M_0402_5%

A

C857

22P_0402_50V8J

1

2

@

TPM_XTALO

2

4

LPCPD#

TC7SH08FUF_SSOP5

2
18P_0402_50V8J

32.768KHZ_12.5PF_1TJS125BJ4A421P

1

@ R859
33_0402_5%

U32
Y

3

<33> TPM_LPCPD#

SUS_STAT#

P

<22,35> SUS_STAT#

G

5

1

25
18
11
4

SLB 9635 TT 1.2_TSSOP28

B

C929+3VS

GND
GND
GND
GND

B

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK

IO1

IO2 GND

5

U17
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#
LPCPD#
SIRQ
CLK_PCI_TPM

2

VIN

3

VSB

2

USBP1USBP1+

1

24
19
10

2

1

1

4

JP23
<22>
<22>

C856

VDD
VDD
VDD

1

C842
150U_D2_6.3VM

0.001U_0402_50V7M

+3VALW

0.1U_0402_16V4Z

2

C855
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

C854

2

D28

2

+ C841

PRTR5V0U2X_SOT143-4

TPM
+3VS

C

2

1

1

IN

NC

2

4

OUT

NC

3

Y7
1
C926

A

2
18P_0402_50V8J

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

TPM/USB Port x2
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
32
1

Rev
X 0.5
of

53

5

4

3

2

1

C346

1
C339

2

2

BATT_OVP

1
C341

2

1000P_0402_50V7K

1
C335

DS_DOCKED_ID

C342
2

DS_DOCKED_ID

1000P_0402_50V7K

1
C336
1
R270

1

C348

1
C340

R286
@ 20M_0603_5%

C347

<32,36> WAKE_PWR_EN#
<17> PWR_LED#
<36> KSI_USER#
<17> CHARGE_LED#
<17> BATT_LED#
<31> MUTE#
<24> WL_SW#
<37,45> SYSON

+3VALW

<22,27> EC_RSMRST#

1

<22> SLP_S3#
<22> SLP_S5#

R391

EC_RSMRST# 1
R86
SLP_S3#
1
R83
SLP_S5#
1
R84

2
0_0402_5%
2
0_0402_5%
2
0_0402_5%

2

EC_TXD
<22> EC_PBTNOUT#

EC_PBTNOUT# 1

2
0_0402_5%

R85

<43> VCCP_ON#

<22>
<22>
<27>
<30,37,39>

10K_0402_5%
TP3
PAD

<17> BKOFF#

EC_SMI#
EC_SWI#
BTDIS#
SUSP#

<34> PME#

140
138

75
EC_AVCC / AVCC

1

PCM_SPK#/EMAIL_LED#/ GPIO16
SB_SPKR/PWR_SUSP_LED#/ GPIO17
PWRLED#/ GPIO19
NUMLED#/ GPIO1A
BATT CHGI LED#/ E51CS#
BATT LOW LED#/ E51MR0
CAPS LED#/ E51TMR1
ARROW LED#/ E51 INT0
SYSON/GPIO56/ E51 INT1
EC_RSMRST#/ GPIO02
BKOFF#/GPIO03
PM SLP S3#/GPIO04
EC LID OUT#/GPIO06
PM SLP S05#/ GPIO07
EC SMI#/GPIO08
EC SWI#/GPIO09
LID SW#/ GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC PME#/GPIO0D

XCLKO
XCLKI

84
97
135
136
144

SM BUS

EC ON/ GPIO1B
AC IN/ GPIO1C
ECTHERM#/GPIO11
ONOFF/GPIO18
PCMRST#/GPIO1E
WL OFF#/GPIO1F

139
129
103
13
28
39

CRY1
CRY2

SELIO2#/ GPIO43
SELIO#/ GPIO50
FRD#/RD#
FWR#/WR#
FSEL#/SELMEM#

Address
BUS

ALI/MH#/GPIO40
FSTCHG/GPIO41
VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

PWROK
PROCHOT#
FRD#
FWR#
FSEL#

41
43
29
36
45
46

EC_ON
ACIN
EC_THRM#
ON/OFF
DOCKEN
WLANOFF#

81
82
83
137
142
143

DOCKEN_VGA
FSTCHG
VR_ON
ENABLT
VGATE_INTEL
ROTA90#

PWROK
PROCHOT#
FRD#
FWR#
FSEL#

<9,22,34>
<6>
<34>
<34>
<34>

EC_ON
ACIN
EC_THRM#
ON/OFF
DOCKEN
WLANOFF#

<34>
<40,42>
<22>
<34>
<29>
<24>

1

2

2

2

1

1
<34>

2

4
7
8
16
17
18
19
20
21
22
23

Data
BUS

ADB[0..7]

R157

2

EC_RSMRST#_R
BKOFF#
SLP_S3#_R
VCCP_ON#
SLP_S5#_R
EC_SMI#
EC_SWI#
BTDIS#
SUSP#
EC_PBTNOUT#_R
PME#

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

1

34
35
38
40
99
101
100
102
104

ADB0/D0
ADB1/D1
ADB2/D2
ADB3/ D3
ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7
KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

@
R326

@ R327

2

EC_TXD
WAKE_PWR_EN#
PWR_LED#
KSI_USER#
CHARGE_LED#
BATT_LED#
MUTE#
WL_SW#
SYSON

EC SMD2/ GPIO47/SDA2
EC SMC2/GPIO46/SCL2
EC SMD1/GPIO44/SDA1
EC SMC1/GPIO44/SCL1

91
92
93
94
95
96

2

88
87
86
85

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

+3VALW
PCM_CLK_EN#

R325

C

BDID0
BDID1

KBA[0..19] <34>

BDID2
+3VALW
@
R267
R299
10K_0402_5%

R70
1K_0402_5%

+5VALW

JP24

B

SMB_EC_DA2
SMB_EC_CK2
SMB_EC_DA1
SMB_EC_CK1

PS2 interface

0_0402_5%
1
2ShutDown#
ShutDown#
<30>
ShutDown#_L
2@R88
WWANOFF#
WWANOFF# <24>
PCM_CLK_EN#
PCM_CLK_EN# <25>
LAN_EN#
LAN_EN#
<28>
TPM_LPCPD#
TPM_LPCPD# <32>
USB_CLK_EN#
USB_CLK_EN# <27> ADB[0..7]
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
KBA[0..19]
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

USB_CLK_EN#

10K_0402_5%

1K_0402_5%

<6,24,36,39>
<6,24,36,39>
<24,34,39>
<24,34,39>

@ ACES_85201-0405

SMB_EC_DA2
SMB_EC_CK2
SMB_EC_DA1
SMB_EC_CK1

key Matrix
scan
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
EC URXD/KSO16/GPIO48
EC UTXD/KSO17/GPIO49

@ R298
10K_0402_5%

R332
INVT_PWM <17>
FAN_PWM <6>
BEEP#
<30>
ACOFF
<40>
FAN_SPEED1 <6>
PDCT
<17>

1

1
2

FPR_PWRON#
CHGSEL

<24> F_FALL
<25> CARD_INSERT#
<24> MOTION

SSBTN:User button as,
ALT+CTL+Delete

EC_TXD

INVT_PWM
FAN_PWM
BEEP#
ACOFF
FAN_SPEED1
PDCT

PDCT

10K_0402_5%

HWSPND#
EC_EXTTS#0
PWR_GD
DIGI_RST#
SASBTN#
DIGISUSP

SASBTN#

1
2
3
4

25
27
30
31
32
33

D

10K_0402_5%

1K_0402_5%

<22> PM_BATLOW#
<22> SLP_S4#

R87 @
PM_BATLOW# 1
SLP_S4#
1
R82

HWSPND#
EC_EXTTS#0
PWR_GD
DIGI_RST#
SASBTN#
DIGISUSP
PM_BATLOW#_R
SLP_S4#_R
FPR_PWRON#
CHGSEL
BDID0
BDID1
BDID2
F_FALL
CARD_INSERT#
MOTION

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
89
90

INVT_PWM/GPIO0F/PWM1
BEEP#/GPIO10/PWM2
OUT BEEP/GPIO12/PWM3
ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

+3VS

10K_0402_5%

R297
10K_0402_5%

<25>
<9,15,16>
<38>
<17>
<36>
0_0402_5%
<17>
2
2
0_0402_5% <36>
<40>

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

CRY2

R333
DAC_BRIG <17>
BATSELB_A# <41>
IREF
<40>
MIC_SEL
<30>

10K_0402_5%

C

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPI032
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPI035
KSI6/GPIO36
KSI7/GPIO37

DAC_BRIG
BATSELB_A#
IREF
MIC_SEL

1

1
C345
15P_0402_50V8J
@

+3VALW

63
64
65
66
67
68
69
70

76
78
79
80

R285
1
0_0603_5%

+3VS

FAN/PWM
<36>
<36>
<36>
<36>
<36>
<36>
<36>
<36>

2

1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

DAC_BRIG/DA0/GPIO3D
EN DFAN1/DA1/GPIO3D
IREF2/DA2
EN DFAN2/DA3/ GPIO3F
DA output or GPO

BATT_TEMP1 <39>
BATT_OVP <41>
DS_DOCKED_ID <36>
BATT_TEMP2 <39>

2

2
R281
33_0402_5%
@

<22> EC_SCI#
<22,25,27,32,35> PM_CLKRUN#

71
72
73
74

BATTEMP/AD0/GPIO38
BATT OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD BID0/AD3/GPIO3B
AD INtput or GPI

PWR

2

1

1
47K_0402_5%
C344
0.1U_0402_16V4Z
2

CLK_PCI_EC

GA20/ GPIO00/GA20
KBRST#/GPIO01/KBRST#
SERIRQ
LPC_FRAME# / LFRAME#
LPC AD3/LAD3
LPC AD2/LAD2
Host
LPC AD1/LAD1 INTERFACE
LPC AD0/LAD0
CLK_PCI_EC/PCICLK
PCIRST#
EC RST#/ ECRST#
EC SCI#/SCI#/GPIO0E
PM_CLKRUN#/ CLKRUN#

AGND

2

1
2
3
5
6
9
10
12
14
15
42
24
44

BATT_TEMP1
BATT_OVP
DS_DOCKED_ID
BATT_TEMP2

77

R276
1

GATEA20
KBRST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PLT_RST#

1

10P_0402_50V8J

GND
GND
GND
GND
GND
GND

+3VALW

<21>
<21>
<22,25,32,35>
<21,24,32,35>
<21,24,32,35>
<21,24,32,35>
<21,24,32,35>
<21,24,32,35>
<5>
<9,18,20,22,24,28,32,35>

GATEA20
KBRST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
PM_CLKRUN#

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC

U33

11
26
37
105
127
141

2
D

1

1

C338
0.1U_0402_16V4Z
2

CRY1

2

1

1
2
1 ECAGND
FBMA-L11-160808-601LMT_200mA_10%

2

2

L43

2

1

1

EC_AVCC

C337
0.1U_0402_16V4Z

BATT_TEMP2

EC_AVCC

0.1U_0402_16V4Z

ECAGND
2
1
0.01U_0402_16V7K
ECAGND
10P_0402_50V8J
0.01U_0402_16V7K
ECAGND
2
3 NC
OUT 4
0.01U_0402_16V7K
ECAGND
2
2 NC
IN 1
0.01U_0402_16V7K
2
32.768K +-10PPM Q13MC20610009
Y3
4.7K_0402_5%

1
C334

0.1U_0402_16V4Z

2

BATT_TEMP1
+3VALW
FBMA-L11-160808-601LMT_200mA_10%
1
2
+3VALW
L44
2

TPM_LPCPD#

BDID2 BDID1 BDID0 Version Phase
0

DOCKEN_VGA <19,34>
FSTCHG
<40,41>
VR_ON
<37,46>
ENABLT
<11,17>
VGATE_INTEL <22,46>
ROTA90#
<36>

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

1

1

0.1

EVT1

0.2

EVT2

B

0.3 DVT1
Rework Rework
DVT2
0.4
Reserve

0.4

DVT2
PVT

1

0

0

0.5

1

0

1

1.0

1

1

0

Reserve

1

1

1

Reserve

KB910LQF A1_LQFP144~N

ECAGND

MP

+3VALW
+3VALW

R293
10K_0402_5%

10K_0402_5%

1
2
3
4

FSEL#
FRD#

+3VALW

R295

2

10K_0804_8P4R_5%

10K_0402_5%
2

2

A

1

1
R380
A

RP22
8
7
6
5

1

+3VALW

WL_SW#

KSI_USER#
+5VALW

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
5

Compal Electronics, Inc.(KunShan)

ROTA90#
2
2
2
2

1
1
1
1

R277
R278
R279
R280
4

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

ENE KB910
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
33
1

Rev
X 0.5
of

53

5

4

3

2

1

NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#
+3VALW
+3VALW

C875

Power BTN

1

ON/OFFBTN#

2

HSS111_4P

3

ON/OFF

2

EC_ON#

1

+3VALW

2
0.1U_0402_16V4Z

2

SW1
1

ON/OFF

<33>

EC_ON#

<44>

EC_ON

1000P_0402_50V7K
2
2

A0
A1
A2
GND

1
2

1
2
3
4

1
R897

2
100_0402_5%

<25> PCM_PME#

1
R900

2
100_0402_5%

<27> USB_PME#

1
R921

2
100_0402_5%

<33>

PME#

PCIPME# 1

2

PCI_PME#

<20>

D

0_0402_5%

D24

1 C876

EC I2C Bus Address:
24C164: 1011xxx R/W#
24C16: 1010xxx R/W#

RLZ20A TE-11_LL34
2

1

Q19

VCC
WP
SCL
SDA

AT24C16AN-10SU-2.7_SO8~N

1
EC_ON

R904
22K_0402_5%
1
2ECON

R899

U34
8
7
6
5

<24,33,39> SMB_EC_CK1
<24,33,39> SMB_EC_DA1

DAN202U_SC70

1
<33>

2

R901
22K_0402_5%

@

R894
100K_0402_5%

D23
D

R895
10K_0402_5%

+3VALW

2

R896
100K_0402_5%

1

1

+3VALW

22K

3

22K
DTC124EKAT146_SOT23
WHEN R=33K,Vbe=0.8V
WHEN R=0,Vbe=1.35V
+3VALW

PWROK

+3VALW
R905
100K_0402_5%
5

1

EC_FLASH_T#

1

I1

O
3

1

I0

D

S
2N7002_SOT23

<33>

FWR#

FWR#

U37

2

P

EC_FLASH# 3

<22> EC_FLASH#

G

1

Q21

G

D36
PSOT24C-LF_T7_SOT23-3

2

2

3

<9,22,33> PWROK

C

2

ON/OFFBTN#

4

FWE#
C

TC7SH32FU_SSOP5

1
@ R906

2
0_0402_5%

+3VALW
R907

DOCK_USB_OC#4

1

A

TC74LCX32FTF_TSSOP14

P

<36> DOCK_USB_OC#4

14

2
U38A

O

2

3 USB_OC#4
1

7

B

G

10K_0402_5%
1

2

+3VALW

<33>
USB_OC#4

<33>

C879
0.1U_0402_16V4Z
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

1

5

B

14

TC74LCX32FTF_TSSOP14

P

A

O

D

7

S

+3VALW

6 USB_OC#6
1

2

2
G
10K_0402_5% R910
1
DOCK_USB_OC#3

<22>

9

TC74LCX32FTF_TSSOP14
O

B

8 USB_OC#7
1

7

10

A

14

2
U38C

<36> DOCK_USB_OC#3

USB_OC#6

C880
0.1U_0402_16V4Z

P

2N7002_SOT23
Q23

G

DOCKEN_VGA

DOCKEN_VGA#

4

1
<19,33> DOCKEN_VGA

DOCK_USB_OC#2

3

B

2
U38B

<36> DOCK_USB_OC#2

G

2
R909
10K_0402_5%

2

USB_OC#7

<22>
<33>
<33>

C883
0.1U_0402_16V4Z

A

13

B

14

FSEL#
FRD#

FSEL#
FRD#
FWE#

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

22
24
9

CE#
OE#
WE#

1

1

C882
10U_0805_10V4Z

C881
VCC0
VCC1

31
30

D0
D1
D2
D3
D4
D5
D6
D7

25
26
27
28
32
33
34
35

RP#
NC
READY/BUSY#
NC0
NC1

10
11
12
29
38

GND0
GND1

23
39

2
2
0.1U_0402_16V4Z
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

+3VALW

B

R912
1

BIOS/B Conn

2
10K_0402_5%

JP25

BIOS_RST#

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
BIOS_RST#
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

TC74LCX32FTF_TSSOP14

P

U38D

KBA[0..19]

SST39VF080-70-4C-EIE_TSOP40~N
@

+3VALW

12

KBA[0..19]

U39

+3VALW
10K_0402_5%
R908
1

+3VALW

ADB[0..7]

ADB[0..7]

<22>

11

7

G

O

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

KBA17
KBA19
KBA10
ADB7
ADB6
ADB5
ADB4
+3VALW
ADB3
ADB2
ADB1
ADB0
FRD#
FSEL#
KBA0

ACES_88072-4071_40P

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

EC Extend I/O&BIOS
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
34
1

Rev
X 0.5
of

53

5

4

3

2

1

D

D

+3VS

2

1000P_0402_50V7K

2

4.7U_0805_10V4Z

<9,18,20,22,24,28,32,33>
CLK_14M_SIO

PLT_RST#

U40

1
<21,24,32,33>
<21,24,32,33>
<21,24,32,33>
<21,24,32,33>

2

<21,24,32,33> LPC_FRAME#
<21> LPC_DRQ#0
22_0402_5%
PLT_RST# R914 1
2
<22,32> SUS_STAT#

CLK_PCI_SIO

<22,25,27,32,33> PM_CLKRUN#
<5> CLK_PCI_SIO
<22,25,32,33> SIRQ

1

1

C

@ R915
33_0402_5%

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

@ R916
33_0402_5%

22P_0402_50V8J

LAD0
LAD1
LAD2
LAD3

LPC_FRAME#
LPC_DRQ#0

15
16

LFRAME#
LDRQ#

PLT_RST_R#
SUS_STAT#

17
18

PCI_RESET#
LPCPD#

PM_CLKRUN#
CLK_PCI_SIO
SIRQ

19
20
21
6

CLKRUN#
PCI_CLK
SER_IRQ
IO_PME#

@ C890

1

22P_0402_50V8J
2

2

1

LPC47N217_SYSOPT
R917
4.7K_0402_5%

BADDR

Pin #
33

Description

2

Strap pin

9

CLK14

2

2
@ C889

10
12
13
14

CLK_14M_SIO

<5> CLK_14M_SIO
1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

BASE Address Selection
"0": 2E~2F (Default)
"1": 4E~4F

RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#

62
63
64
1
2
3
4
5

RXDB#
TXDB

IRRX2
IRTX2
IRMODE/IRRX3

37
38
39

IRRX
IRTXOUT
IRMODE

INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

VTR
VCC
VCC
VCC
VCC

7
11
26
45
54

SERIAL I/F

0.1U_0402_16V4Z

C888

FIR

CLOCK

23
24
25
27
28
29
30
31
32
33
34
35
36
40

GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23

8
22
43
52

VSS
VSS
VSS
VSS

PARALLEL I/F

2

1

C887

LPC I/F

0.1U_0402_16V4Z

C886 1

GPIO

C885 1

POWER

CTSB#
DTRB#

RXDB#
TXDB

<17>
<17>

CTSB#
DTRB#

<17>
<17>

C

FOR LPC SIO DEBUG PORT
+5VS
+3VS

JP26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+3VALW

+3VS

LPC47N217-JV_STQFP64

CLK_14M_SIO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PLT_RST#
CLK_PCI_SIO
SIRQ

@ ACES_85201-2005

Place the debug port under MINI card
B

B

2

+3VS

FIR

1

R283
47K_0402_5%
@

@ R918
4.7_0603_5%
1
2

+3VS
(60mil)

2

IRRX

R967
10K_0402_5%
@

R3
4.7_1206_5%
1
2

+IR_ANODE

1
1

1

C891
22U_1206_10V4Z

2
4.7_0603_5%

(60mil)

@ R919

2

1
C892
@10U_0805_10V4Z
2

1
47_1206_5%

C893
10U_0805_10V4Z

1

+IR_3VS
1 (30mil)
C894
0.1U_0402_16V4Z

2

2

IRED_C
RXD
VCC
GND

IRED_A
TXD
SD/MODE
MODE

1
3
5
7

IRTXOUT
IRMODE
1

HSDL-3220_8P
PCB Footprint : TFDU6101E
2
1
R294 3220@ 0_0603_5%

R969
10K_0402_5%
@
1

2

2
4
6
8

C507
0.47U_0603_10V7K

IRRX

R920

2

U41
+3VS

2 @

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

SMSC LPC47N217/FIR
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
35
1

Rev
X 0.5
of

53

5

4

ALS/MIC & Finger Print

3

2

1

combine CONN

+3VS

R731
2
1
4.7K_0402_5%

Q72
1

DOCKING BD.

SMB_EC_DA2_ALS

S

D

SMB_EC_DA2

<6,24,33,39> SMB_EC_DA2

D

R732
2
1
4.7K_0402_5%

D

3

19vdc_2.25A

2
G

2N7002_SOT23

SMB_EC_CK2_ALS

S

D

SMB_EC_CK2

1

3

2
G

2N7002_SOT23

+3VS
L45

C895
1

<30> INT_MIC1

2

1

0.22U_0603_10V7K

ACES_85201-1205

+3VS
2

INTMIC1

12
11
10
9
8
7
6
5
4
3
2
1
JP34

FBM-11-160808-700T_0603
VDDA

Q25
1

AO3413_SOT23
2

G

C

<33> FPR_PWRON#

<30,31>

D

S

3

+3VS

C896
@

4.7U_0603_6.3V6M

2

1

1

2 0.1U_0402_10V6K

C897

<33>
<22>
<22>

GNDA
SASBTN#
USBP3+
USBP3-

GNDA
USBP3+
USBP3-

<29> DOCK_LAN_TX2<29> DOCK_LAN_TX2+

DOCK_LAN_TX2DOCK_LAN_TX2+

<29> DOCK_LAN_RX3<29> DOCK_LAN_RX3+

DOCK_LAN_RX3DOCK_LAN_RX3+

<29> DOCK_LAN_TX<29> DOCK_LAN_TX+

DOCK_LAN_TXDOCK_LAN_TX+

<29> DOCK_LAN_RX<29> DOCK_LAN_RX+

DOCK_LAN_RXDOCK_LAN_RX+

<29> DOCK_LAN_ACT#
<29> DOCK_LAN_LINK#
USBP4+
USBP4-

<22>
<22>

USBP6+
USBP6-

USBP6+
USBP6-

<22>
<22>

USBP7+
USBP7-

USBP7+
USBP7-

USBP5+
USBP5-

<34> DOCK_USB_OC#2
<34> DOCK_USB_OC#3
<34> DOCK_USB_OC#4

2

3

<30,31> HP_PLUG#
<30> HP_OUT_L
<30> HP_OUT_R
<33> DS_DOCKED_ID

USBP5+
USBP5DOCK_USB_OC#2
DOCK_USB_OC#3
DOCK_USB_OC#4

0_0603_5%
HP_PLUG#
HP_OUT_L R302
1
2
HP_OUT_R
1
2
R301
0_0603_5%
DS_DOCKED_ID

D_HP_OUT_L
D_HP_OUT_R

1

D37
PSOT24C-LF_T7_SOT23-3

USBP4+
USBP4-

<22>
<22>

<22>
<22>

SASBTN#

DOCK_LAN_ACT#
DOCK_LAN_LINK#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

HCB4532KF-800T90_1812

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

DOCKC_IN

2

1
2

L20

2
C903

C898
1
0.1U_0805_25V7M
+5V_DOCK

1
0.1U_0805_25V7M

DIS_INTMIC
2

Q70
<6,24,33,39> SMB_EC_CK2

DOCK_IN

JP27

5.1K_0402_5%
R923
+2.5V_LAN

1

+3VS

C

+3VALW
VDDA

GNDA

GNDA

<30,31>

D_DOCK_MIC 2
R303 2
R922

DOCK_MIC
1
DOCK_MIC
DIS_INTMIC
1 0_0603_5%
DIS_INTMIC
0_0402_5%
ROTA90#
ROTA90#
<33>
M_SEN#
M_SEN#
<19,22>
3VDDCDA_R
3VDDCDA_R <19>
3VDDCCL_R
Reserved for EMI 3VDDCCL_R <19>
CRT_B_DOCKC
1
2 CRT_B_DOCK
CRT_B_DOCK
R292
0_0603_5%
CRT_G_DOCKC
1
2 CRT_G_DOCK
CRT_G_DOCK
R296
0_0603_5%
CRT_R_DOCKC
1
2 CRT_R_DOCK
CRT_R_DOCK
R300
0_0603_5%
CRT_VSYNC_DOCK
CRT_VSYNC_DOCK <19>
CRT_HSYNC_DOCK
CRT_HSYNC_DOCK <19>

<30>
<30>

<19>
<19>
<19>

ACES_88363-08001

Need to update the Symbol

To BTN Board

B

+5V_DOCK
B

+5VALW
JP30

L46
2
1
2
FBM-11-160808-700T_0603
0.22U_0603_10V7K

INT_MIC2

1

GNDA
INTMIC2
GNDA
VDDA

<32,33> WAKE_PWR_EN#

WAKE_PWR_EN# 1
R965

2
22K_0402_5%

2 0.1U_0402_16V4Z

2

2

1
R970
22K_0402_5%
+3VS

2

1

2

0.47U_0603_16V7K

2

C930

R964
330K_0402_5%

0.1U_0402_16V4Z

1

G

INT_MIC2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSI_USER#

3
1

1
C900

Q63
AO3413_SOT23
D

C904

<30>

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSI_USER#

C899 1

+5V_DOCK

+5VALW

S

<33>
<33>
<33>
<33>
<33>
<33>
<33>
<33>
<33>

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

1

C901 1

C902
0.1U_0402_16V4Z

2 0.1U_0402_16V4Z

2

To support wake up from Docking.

ACES_87151-2205

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Docking Conn /FingerPrinter /Button board Conn
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
36
1

Rev
X 0.5
of

53

2

1

1

1

2
1

2
1

2
1

2

3

D

D Q32
2 SUSP
G 2N7002_SOT23
@

S

+VCC_CORE

+VCCP

1

1

+1.8V

2
+12VALW
100K_0402_1%

2 SUSP
G 2N7002_SOT23
@

S

2 SUSP
G 2N7002_SOT23

C909
2 0.1U_0402_16V4Z

R933
@ 330_0402_5%

1

3

S

D Q34

3

S

R934
@ 330_0402_5%

VR_ON#

2 SYSON#
G 2N7002_SOT23
@

2

R932
470_0402_5%
@

D Q33

D

S

2
G

Q35
2N7002_SOT23
@

1

1
R931
1

VR_ON#

D

2
G
3

2

D Q31
2 SUSP
G 2N7002_SOT23
@

2

C907
100U_D2_6.3VM

AO4468_SO8
C908
10U_1206_6.3V7K

2

S

R930
470_0402_5%
@

1

C905
C906
10U_0805_10V4Z
2
2 0.1U_0402_16V4Z

1

+

1
2
3
4

1

1

S
S
S
G

1

1

1

D
D
D
D

S

3

U42
8
7
6
5

S

3

S

D Q30
2 SUSP
G 2N7002_SOT23
@

+0.9VS

R929
470_0402_5%
@

3

+1.8VS

D Q29
2 SUSP
G 2N7002_SOT23
@

2

+1.8V

D Q28
2 SUSP
G 2N7002_SOT23

+1.5VS

R928
470_0402_5%
@

3

D Q27

+1.8V to +1.8VS Transfer

R927
470_0402_5%
@

1

1

2

R926
470_0402_5%
@
2

R925
470_0402_5%

D

+1.8VS

1

+2.5VS

1

+3VS

1

+5VS

1

3

3

1

4

3

5

S

Q36
2N7002_SOT23
@

C

C

+3VALW to +3VS Transfer
+5VALW

+3VS

1
R937
1

2

1

2

AO4468_SO8
C913
10U_1206_6.3V7K

2

2
+12VALW
56K_0402_5%

<43>

SYSON#

D Q37

SUSP

SUSP

C914

2 SUSP
G 2N7002_SOT23

<33,45> SYSON

S

SYSON 2
G

Q38
2N7002_SOT23
3

3

2 0.1U_0402_16V4Z

D

1

C912
100U_D2_6.3VM

R935
10K_0402_5%

R936
10K_0402_5%

D

3

+

C910
C911
10U_0805_10V4Z
2
2 0.1U_0402_16V4Z

2

1

S
S
S
G

+5VALW

1

1

1

D
D
D
D

1
1
2
3
4

1

U43
8
7
6
5

1

+3VALW

S

Q39
2N7002_SOT23

2
G

<30,33,39> SUSP#

S

B

B

+5VALW to +5VS Transfer
+5VS
U44

2

2

1

C916
C915
10U_0805_10V4Z
2 0.1U_0402_16V4Z
2

+3VALW
+5VALW

AO4468_SO8
C918
10U_1206_6.3V7K

2

1
C917
100U_D2_6.3VM

1
2
3
4

1
R938
1

2
+12VALW
47K_0402_5%

R939
@100K_0402_5%

D Q40
C919

2 SUSP
G 2N7002_SOT23

R940
100K_0402_5%

VR_ON#

S

3

2 0.1U_0402_16V4Z

1

+

1
S
S
S
G

1

1

D
D
D
D

2

8
7
6
5

1

+5VALW

VR_ON

2
G
3

<33,46> VR_ON

S

1
Q41
2N7002_SOT23
@

SUSP

D
Q42

2
G

<43,45>

1
C920

3

1

SUSP#P
D

S 2N7002_SOT23

2 0.1U_0402_16V4Z

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

DC-DC interface
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
37
1

Rev
X 0.5
of

53

5

4

1

7

Q43
MMBT3904_NL_SOT23

14
1

U45B

D

D25

P

R944
2

O

3

2

47K_0402_5%
74LVC14APW_TSSOP14

I

1

O

4

1

2

RB751V_SOD323
74LVC14APW_TSSOP14
+3VS

C921

3

1

2

U45A

I
G

1

G

1

1

1

1

+3VALW

7

R943
330_0402_5%

330_0402_5%

Q44
MMBT3904_NL_SOT23

2 0.1U_0402_16V4Z
1

3

2

2

2

R942

1K_0402_5%

+3VALW

14

R941
D

+3VS

2

2

+3VS

P

+1.8VS

3

+5VS

R945
10K_0402_5%

+3VALW

1

2

1
J6

C922
R946

2

2 0.1U_0402_16V4Z

180K_0402_5%
1

D

3

14

U45C

S

P

2

I

6

O

1

G

5

7

1

R947

1

PWR_GD

PWR_GD

<33>

NO SHORT 2x2m

Q45
2N7002_SOT23

2
G

74LVC14APW_TSSOP14

C923

560K_0402_5%

2 0.1U_0402_16V4Z

C

2

C

8

O

1
Q47
MMBT3904_NL_SOT23

D

S

7

74LVC14APW_TSSOP14

Q46
2N7002_SOT23

2
G

3

1

1

I
G

9
2

U45D

3

14

2

+3VALW

1

R950
330_0402_5%
1

R949
330_0402_5%
1

R948
10K_0402_5%

+2.5VS

2

2

+2.5VS

P

+1.5VS

Q48
MMBT3904_NL_SOT23

2
3

<43> VCCP_POK

CF12
1

CLIP1

B

1

CF10
1

CF8

CF9
1

CF4
1

CF5
1

CF2
1

CF6
1

CF7
1

1

CF11
1

CF3

CF1

B

1

Antenna_CLIP
FD2
1

FD6
1

FD5
1

FD4
1

1

H9
HOLEA

CF13
1

H1
HOLEE

H29
HOLEE

H51
HOLEE

H15
HOLEB

H13
HOLEB

1
H12
HOLEA

H14
HOLEA

H8
HOLEA

H6
HOLEA

1

H11
HOLEB

H16
HOLEA

1

1

1

H7
HOLEB

H21
HOLEA

1

H5
HOLEA

H20
HOLEA

1

H4
HOLEA

H17
HOLEA

1

1

H26
HOLEA

1

1
H2
HOLEA

H27
HOLEA

1

1

H18
HOLEA

CF14

1

1

H25
HOLEC

FD3
1

1

1

FD1
1

H3
HOLED

H22
HOLED

H10
HOLED

H19
HOLED

1

1

1

1

1

1

1

1

1

1

A

1

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

POWER OK CKT
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Monday, January 08, 2007
Sheet 38
1

Rev
X 0.5
of

53

5

4

3

DOCK_IN
D

P1

PJPD1

PL1
FBMA-L18-453215-900LMA90T_1812
1
2

P1

1

1

BATT_A
BATT_A+

VIN

PL2
FBMA-L18-453215-900LMA90T_1812
1
2

B540C_SMC
PD27
2
1

D

BATT_A+

2

1 2

2

PR1
10_1206_5%

PC2
1000P_0402_50V7K
PC1
0.01U_0402_25V7K

PJP1
1
2
3
4
5
6
7

SMART
Battery:
1.BAT+
2.ID
3.B/I
4.TS
5.SMD
6.SMC
7.GND

+12VALW

1

3

1

2

1
2

VSB

1

1

PR19
10K_0402_5%

SPOK

2

SMART
Battery:
1.BAT+
2.ID
3.B/I
4.TS
5.SMD
6.SMC
7.GND

1K_0402_5%
PR16
2
1

1
2
3
4
5
6
7

1
1

PR18 100_0402_5%
1
2

SUYIN_250263MR007G107ZL

B

PR17
6.49K_0402_1%
2
2

+3VALW
SMB_EC_DA2

<6,24,33,36>

SMB_EC_CK2

<6,24,33,36>

PR20
100_0402_5%

1

PQ6
DTC115EUA_SC70
2
PACIN
G

2

D

3

SUSP#

S

PQ7
RHU002N06_SOT323

3

<30,33,37> SUSP#

3

1

SPOK

PQ5
DTC115EUA_SC70

100K_0402_5%
PR21
2
1

<33>

PR14
1K_0402_5%

PJP2

PJP2 battery connector

1

BATT_TEMP2

B+

PR15
100K_0402_5%

2

2 BATT_TEMP2

1
2

G

2

1

PC7
0.01U_0402_25V7K

1

1
D

1

PD4
RB160L-40_SOD106

1
2

S

2

IRLML5103_SOT23

1000P_0402_50V7K
PC8

2

PD3
1SS355TE-17_SOD323-2

D
PJPC1

BATT_B+

1

3
2

1
1

PL3
FBMA-L18-453215-900LMA90T_1812
1
2

PQ4

MOLEX_53780-0290

<42>

<24,33,34>

C

E

B

PC9
0.1U_0603_25V7K

SMB_EC_CK1

BATT_B+

S

PD2
DAN217_SC59

<24,33,34>

PR6
100_0402_5%

PR10
3.92K_0402_1%

PQ2
2SC2412K_SC59

2
B
PR13
57.6K_0402_1%

RHU002N06_SOT323
PQ3
2
G

100_0402_5%
1
2

BATT_B

1
C

3

1
3

SUYIN_250263MR007G110ZR

+3VALW
SMB_EC_DA1

2

1

PR12
40.2K_0402_1%
2
1

2

PR5

PR4
6.49K_0402_1%
2
2

PR34
3.4K_0402_1%

PQ1
2SA1037AK_SC59
C

2

1

1
1

2

3 1

E

2
B

2

1K_0402_5%
2
1

PR9
442_0402_1%

1

PR8
22.1K_0402_1%
1

PR7
22.1K_0402_1%

PH1
100K_0603_1%_TH11-4H104FT

<33>

2

2

2

C

PR3
1
2
3
4
5
6
7

BATT_TEMP1

PR2
1K_0402_5%

RLZ24B_LL34

PJP1 battery connector

PR11
43.2K_0402_1%
2
1

2 BATT_TEMP1

1

PD1

2

12P_0402_50V8J
PC5
2
1

SINGA_2DC-S028B200

12P_0402_50V8J
PC4
2
1

3

3

560P_0402_50V7K
PC6
2
1

1

2

2

G
G

560P_0402_50V7K
PC3
2
1

4
5

1

1

1

B540C_SMC
PD26
2
1

2

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

PWR-Vin/bridge Batt/RTC
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
39
1

Rev
X 0.5
of

53

5

4

3

2

1

Charger
Iadp=0~2.38A(45.23W)
P2

1

4

2

3
1

1

2
PC14
@ 0.1U_0603_25V7K

1

0_0402_5%
PR35

2

1

1

@ 158K_0603_1%

2
PQ17
DTC115EUA_SC70

BST

24

BST

DLOV

22

IINP
CCV

2

CSIP
CSIN
BATT

19
18
16

2
PR186

1
0_0402_5%

20

14

5

MAX1908-CCS

1

4

2

3

PC19
0.1U_0603_25V7K

0.015_2512_1%

PD9
1SS355_SOD323
2

ACOFF

C

1
PR36
33_1206_5%

1908LDO

CCI

PL5

PC22
4.7U_1206_25V6K

DLO

DLO

PC21
4.7U_1206_25V6K
2
1

23
21

1

LX

LX

LDO

BATT+

PR30

2

28
7

1

3
16UH_D104C-919AS-160M_3.7A_20%
1
2

PC24
1U_0603_10V6K

MAX1908ETI+T_QFN28

PC25
1U_0805_25V4Z

CSIP

PC27
0.001U_0402_50V7M

B

BATT+

PR43
0_0402_5%
1
2

3

2

2

B

PQ13
DTC114EKA_SC59

PQ15
DHI

1

0.1U_0402_16V7K
PC28
2
1
1

1
2

PR41
100K_0402_1%

1

PACIN

PR42

ACOK#
SHDN#
ACIN
ICHG

2

PD8
1SS355_SOD323

1

2
PR40
10K_0402_5%

PD29
RLZ4.3B_LL34

11
8
10
9

PR39
10K_0402_1%
0.001U_0402_50V7M
PC26
6
2
1

ACIN

1

PACIN
PR155
10K_0402_1%
1
2

VCTL
ICTL

CCI

1908LDO

ACON

15
13

1

10K

PC20
4.7U_1206_25V6K
2
1

1

25

<33>

2
2
1
2

DHI

1
2
3
4

REFIN

PGND

1
2

1

PR38
22K_0402_5%
1
2

26

G2
D2
D1/S2/K
D2
D1/S2/K
G1
D1/S2/K S1/A

CLS

GND

VCTL
ICTL

PR32
15K_0402_1%

CSSN

8
7
6
5

2

12

1

PR31
9.31K_0402_1%

29

REF

CCS

2

PC23
0.01U_0402_16V7K

S

2
G
1SS355_SOD323
PD10
1
2

1908LDO

TP
CELLS

2

1

D

3

RHU002N06_SOT323

PC18
0.1U_0402_16V7K
2
1

PR33
100K_0402_1%
2
1

3

27

1

17

REF_MAX1908 4

2
CSSP

1

215K_0402_1%
PR29
2
1

PD6
@1SS355_SOD323

2

PR28
0_0402_5%
2
1

10K

AO4916_SO8

DCIN

2

PQ14
RHU002N06_SOT323

<33,42>

PD5
@ RLZ22B_LL34

2

1

PU1
1

2

PC16
0.1U_0603_25V7K

1

1

2

2

PR27
150K_0402_5%

PQ16

VIN

2

2

VIN
PC17
1U_0603_10V6K

ACOFF#

PR25
47K_0402_5%
2

1

ACOFF#

S

C

D

2

PR26
10K_0402_5%

1

3

2

8
7
6
5

PD7

PQ12
DTC115EUA_SC70

3

2
G

<44>

2

1

1SS355_SOD323

D

PACIN

1

1
2
3

1

2

@ 0.1U_0603_25V7K

2

PC13

1

1

2

2

0.1U_0603_25V7K
PC15
2
1

1

1

47K

1

4
1

3

47K
2

PR24
200K_0402_1%

4

PR23
47K_0402_5%
2
1

0.01_2512_1%
DTA144EUA_SC70
PQ11

PQ10
AO4407_SO8

PL4
FBMA-L18-453215-900LMA90T_1812
1
2

PR22

8
7
6
5

4

P3

1
2
3

PC12
10U_1206_25V6M

1
2
3

PC11
10U_1206_25V6M

VIN
D

B+

PQ9
AO4407_SO8

8
7
6
5

PC10
10U_1206_25V6M

PQ8
AO4407_SO8

VIN
<33>

1

Charge voltage

PC29
0.1U_0402_16V7K

4S CC-CV MODE : 17.4V for 2800mAH Battery
4S CC-CV MODE : 16.8V for 2600mAH,2400mAH Battery

1

1

IREF

2

1

PR44
100K_0402_5%

PR45
10K_0402_5%
1
2

2

<33,41> FSTCHG

PR46
150K_0402_1%

2

1

1908LDO

PR262

ICTL

PACIN

1

2

1

2

CHGSEL

PR164
100K_0402_1%

Change voltage.

Note.

1908LDO.

16.8V

PR163=0,PR164=@

2.0769V

17.0V

PR163=160K
PR164=100K

Vin Detector(Detector Point:pin10 of PU1)
typ.
L-->H
V 17.85V
V
H-->L
V 16.98V
V

A

Compal Electronics, Inc.(KunShan)

2

3

VCTL

CC-CV
Pulse charge.

VCTL
PQ51
DTC115EUA_SC70

Charge mode

2

RHU002N06_SOT323
S

A

<33>

PR48
20K_0402_1%

PR163
84.5K_0402_1%

D
2

1

PQ49
2
G

3

2

1
PR184
100K_0402_1%

PR47
681K_0402_1%
1
2

1

100K_0402_1%

2

+12VALW

1

PR37
100K_0402_1%

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

PWR-Changer MAX1908ETI
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
40
1

Rev
X 0.5
of

53

5

4

PACIN

3

2

1

2

1

VL
VS

1

2

ADPPWR

13

REVBLK

ADPBLK

18
17

DISBAT
CHGIN

19

CHGA

2
9

10

OUT2
OUT1
OUT0

2

FSTCHG

<33,40>

BATSELB_A#

<33>

PR53
0_0402_5%

8
7
6
C

20

CHGB

23

DISB

BATSUP

26

24

DISA

21
15

22

NC2
NC1

BATB

25

BATA

VDD

28

29

TP

PR55
100K_0402_5%
1
2

MINVB

1

27

1538VDD

PR56
100K_0402_5%
1
2
PR57
100K_0402_5%
1
2

2

MINVA

1538VCC

2

4
3
2
1
G1
S1
G2
S2

2

PR54
0_0402_5%

2
PR59
100K_0402_1%
NA

OVP voltage :
LI-4S :17.8V----BATT-OVP=1.9758V(4.2V CELL)
LI-4S :18V-----BATT-OVP=1.998V(4.35V CELL)
BATT-OVP=0.111*BATT+

1

PR58
66.5K_0402_1%

1

D1
D1
D2
D2

2

1908LDO

1
1

B

BATT+

VS

2
1
2

1
2

1

1

P
G

-

LM358DT_SO8

2

2

PR62
143K_0402_1%

PC36
0.01U_0402_25V7Z

PQ26
A

2
G

BATT_UVM

<44>

S

3

3

LM358DT_SO8

PU3A
3

+

0
4

8
P
4
1

2
G
S

RHU002N06_SOT323

1

RHU002N06_SOT323

1

D

D
PQ25

6

BATT_OVP

PR61
300K_0603_0.1%

2

2
BATT_A

1
BATT_B

-

<33>

PR101
2K_0402_5%

1

PR93
2K_0402_5%

A

PU3B
5

+

0
G

7

8

2

VS

PR91
3K_0402_5%
1
2

PR60
845K_0603_1%
PC35
0.01U_0402_25V7Z

PC34
0.047U_0603_50V7K
@

1

2

1
2
3
4

PR92
3K_0402_5%
1
2

PC33
0.047U_0603_50V7K
@
1
2

PQ19
FDS4935_SO8

S2
G2
S1
G1

D2
D2
D1
D1

8
7
6
5

1

5
6
7
8

B

2

PR52
@ 0_0402_5%
1

1538VDD

PQ18
FDS4935_SO8

PR167
0_0402_5%
1

PC31
1U_0805_25V4Z
2
1

14

C

5
3
4

EXTLD

GND

BATT+

CHRG
BATSEL
RELRN

1

16

ACDET

12

AIRDET

1

1U_0805_25V4Z
PC30

PU2
MAX1538ETI+T_QFN28
11 ADPIN

2

VIN

PC120
0.01U_0402_16V7K

2

1

1SS355TE-17_SOD323-2

1U_0603_10V6K

1

PD31

PR160
10K_0402_1%

PC32

PACIN

1

1

PC122
0.01U_0402_16V7K

2

PR49
309K_0402_1%

PR166
10K_0402_1%

2

LM393DG_SO8

D

1

2

G

1

1

PR51
100K_0402_1%

O

PD30
1SS355TE-17_SOD323-2

-

1

+

2

4

2

2

1

1

RTCVREF

2

PC121
0.1U_0402_16V7K

2

3
D

PR165
10K_0402_1%
PU7A

P

2

8

PR50
412K_0603_1%

Compal Electronics, Inc.(KunShan)

Title

PWR-Batt Select & OVP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
41
1

Rev
X 0.5
of

53

5

4

3

2

1

+3.3V/+5V/+12V
Change from 2.2U to 10U for S3 noise issue

+3VALWP Choke DCR = 37m .
Current limit Threshold Min.=80 mV Mx.=120mV.
OCP Min.= 80mV/1.27K*(2.8K+1.27K)/37=6.929A
OCP Max.=120mV/1.27K*(2.8K+1.27K)/37=10.394A

1
PD11
EC11FS2_SOD106

2
PC38
@ 470P_0805_100V7K

D

2

2

D

1

1

B+

PC37
10U_1206_25VAK
2

PL6
PC39
0.1U_0603_25V7K

1

BST31

2

2

BST51

1

FLYBACK

PR63
@ 22_1206_5%

PL7

2

SNB
1

4

FBMA-L18-453215-900LMA90T_1812

PC40
0.1U_0603_25V7K
3

2

PQ20

1

28

RUN/ON3

2

1

1
2

PC45
10U_1206_25V6M

PC44
2200P_0402_50V7K

1
2

2
PR66

2

1
3

1

1

4
5
18
16
17
19
20
14
13
12
15
9
6
11

VDD_MAX1902
BST5

PR70
2M_0402_1%

DH5
LX5
2

DL5
2

2.5VREF

FB5

1

PR71
1.54K_0402_1%

1

12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RESET#

PC51
0.47U_0603_16V7K

PR74
698_0402_1%

2

PR77
0_0402_5%
MAX1902EAI+T_SSOP28

2

PC55
4.7U_0805_6.3V6K

+5VALWP
B

1

2

1

GND

2

TIME/ON5

PQ40
@ RHU002N06_SOT323

21

22

7

C

PC47
47P_0402_50V8J

1

CSH3
CSL3
FB3
SKIP#
SHDN#

S

@

2

1
2
3
10
23

VL

LX3
DL3

D

2
G

0_0402_5%

1

PC48
4.7U_1206_25V6K

1
2

26
24

V+

DH3

8

PR75
@300K_0402_5%

BST3

27

1

PR73
10K_0402_5%

25

G2
D2
D1/S2/K
D2
D1/S2/K
G1
D1/S2/K S1/A
AO4916_SO8

ACIN

1
2
1

1

2

2

1
2

ACIN

PC52
100P_0402_25V8K

PR76
3.57K_0402_1%
1
2

1
PD15
SKUL30-02AT_SMA

<39>

1

PD16
SKS10-04AT_TSMA

2
2

2

1
+

PC57
100P_0402_25V8K

PC56
150U_D2E_6.3VM_R18

1

SPOK

PR78
10.2K_0402_1%
2
1

PR79
10K_0402_1%

PR122
0_0402_5%
MAINPWRON

<44>
1

2

1

VS

1

PC54
1000P_0402_50V7K

2

2

PC43

1
2
3
4

2

150U_D2E_6.3VM_R18

+

+12VALWP

PC46
0.1U_0603_25V7K

PU4
0.47U_0603_16V7K
PC50
2
1
PR72
619_0402_1%
1

<33,40>

PC53 1

2

PR68
1.27K_0402_1%

FB3

+3VALWP

B

1

PR67
2.8K_0402_1%

2

2
PR69
1M_0402_1%
2

PC49
47P_0402_50V8J
1
2

1

2
1

PL8

4.7UH_PCMC063T-4R7MN_5.5A_20%

1

DL3

8
7
6
5

4.7U_0805_6.3V6K

PR185
10_1206_5%

DH3

LX3

C

PQ21

2.7K_1206_5%
@ PR193
2
1

2

PR64
0_0402_5%

2

B+++
VS VL

2

1

1
PC42
10U_1206_25V6M

2

PC41
2200P_0402_50V7K

@

2

1

AO4916_SO8

2

8
7
6
5

1 1

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

PD13
1SS355TE-17_SOD323-2

1
2
3
4

PD12
CHP202UPT_SOT323-3

3

1

9UH_SDT-1204P-9R0-120 GP_4.5A_20%

B+++

1

2

PC59
@1U_0805_25V4Z

+5VALWP Choke DCR = 40m .
Current limit Threshold Min.=80 mV Mx.=120mV.
OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A
OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A

2

2

PR168
@ 47K_0402_5%

2

1

1

1

PR81
10K_0402_1%
PC58
2.2U_0805_10V6K

A

A

RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3)
L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56)

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

PWR-+3.3V/5V/12V
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
42
1

Rev
X 0.5
of

53

3

2

1

+2.5VSP

PU12
VO

3

EN_2.5VSP 1

EN

ADJ

4

+1.8V

+2.5VSP
1

VIN

PR156
11K_0402_1%

1

5

GND

GND

7

6

GND

GND

8

G965-18ADJP1UF_SO8

PU5
VIN

2

GND

VCNTL

6

NC

5

+3VALW

PR157
10K_0402_1%

3

VREF

NC

7

4

VOUT

NC

8

TP

9

<37,45>

1

PR80
0_0402_5%
2
1

SUSP#P

1

0.1U_0603_25V7K
PC62
2
1

APL5331KAC-TRL_SO8

2

PR83
1K_0402_1%

PU14
XC61CN0902MR

1

VDDIN

2

VCCP_POK

<38>
PJP3
2MM

3

1
PC88
1000P_0402_50V7K

PWDOUT
VSS

+VCCPP

PC64
22U_1206_10V6M

2

2

1

PC63
@ 22U_1206_10V6M

S

2

2
G

PR84
0_0402_5%

1

1
2

D
PQ23
RHU002N06_SOT323

3

1

SUSP

PC67
1000P_0402_50V7K

@

+0.9VSP
<37>

D

2

PR82
1K_0402_1%

PC60
1U_0603_10V6K

2

1
PC61
10U_1206_6.3V7K

2

1

1

2

2

1

D

PC119
22U_1206_6.3V6M

2
2

PC118
4.7U_0805_6.3V6K

2

1

+3VALW

2

4

1

5

+12VALWP

1

C

2

+12VALW

C

PJP4
3MM

PR264
1K_0402_1%
2

1

2

+1.8VP

1

2

LG

2

+2.5VS

5
6
7
8
D
D
D
D
G
S
S
S

PC186
1
2

12

PQ52

6269_VCC

SI4800BDY-T1-E3_SO8

10

ISEN

9

+2.5VSP

PL23
1

1

B

+VCCPP
1

PQ53
SI4810BDY-T1-E3_SO8

+
2

PJP8
3MM

PC188
330U_D2E_2.5VM
+VCCPP

1

2

+VCCP

4
3
2
1

VO

PR270
ISEN_6269
1
2
6.49K_0402_1%

G
S
S
S

D
D
D
D

3

PGND

PJP7
3MM

2.2UH_SSC-10030D3-2R2_7A_20%

LG_6269

11

8

7

2

5

PC189
@ 0.22U_0603_16V7K

FSET

EN
COMP

4

+1.8V

3MM

2

ISL6269CRZ-T_QFN16

FCCM

2

PJP6

@PR266
4.7_0603_5%
PR267
4.7_0603_5%
1
2

PU16
3

+3VALW

PC185 0.1U_0603_25V7K

5
6
7
8

PR268
0_0402_5%
1
2

VCC

FB

2

PC187
2.2U_0603_6.3V6K

2

2

PJP5
3MM

4
3
2
1

BOOT

UG

PVCC

6

1

B

1

1

+5VALW

1

13

14

15

PGOOD

PHASE

2
6269_VCC

PR269
0_0402_5%
1
2

+3VALWP

2

+5VS
BOOT_6269

16

17
GND
VIN

1

0_0603_5%

2.2U_0603_6.3V6K

VCCP_ON#

1

UG_6269
PR265

1

<33>

+5VALWP

PHASE_6269
6269_VCC

1

2

1

PL22
FBMA-L11-322513-201LMA40T_1210
1
2

PC184
10U_1206_25VAK

B+

2

+0.9VS

2

PC190
0.01U_0402_25V7K
PJP10
3MM
1

+1.5VSP

PR273
1.5K_0402_1%
1
2

2

+1.5VS

A

1

A

PC192
6800P_0402_25V7K

2

1

1

1

2

PR271
49.9K_0402_1%

PR272
57.6K_0402_1%
2
1

PC191
22P_0402_50V8J
2
1

1

PJP9
3MM
+0.9VSP

2

PR274
2K_0402_1%

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

+0.9VSP&VCCP&+2.5
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
43
1

Rev
X 0.5
of

53

5

4

3

2

1

VL
VL

1

VL

4
2

1

VIN
2

2

2

1

1

OUT

3

1

1

1

GND
1
2

PC86
1U_0805_25V4Z

2

PR109
560_0402_5%

1

2

CHGRTC

3

2

2
1

1
1

VL

PACIN

PR209
34K_0402_1%

PQ43
DTC115EUA_SC70

PR210
66.5K_0402_1%

BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 5.044V 5.096V 5.205V
L-->H 6.008V 6.124V 6.243V

2

+5VALW

3

RTCVREF

PU9
G920AT24U_SOT89

S

1

2

IN

B

RHU002N06_SOT323
PQ35
PR208
2
1
2
G
47K_0402_5%

2

Precharge detector
Min.
typ.
Max.
H-->L 14.556V 14.807V 15.372V
L-->H 15.276V 15.836V 16.411V

PR108
22K_0402_5%

2

PC146
1000P_0402_50V7K

2

2
1

D

ACIN
1

PR207
634K_0603_1%

2

1

PR206
140K_0402_1%
PC69
1000P_0402_50V7K

1

3

-

1

1
2
+

O

LM393DG_SO8

PC147
0.1U_0603_25V7K

P
1

PR205
412K_0603_1%

2

PC85
0.22U_1206_25V7K

2

1

PR106
100K_0402_5%

3
PD33
RB715F_SOT323

PC83
0.1U_0603_25V7K

1

2

2

B

ACON

2

1

PR104
200_0805_5%

<40>

G

VS

4

1

1

1

3

2

2

1

B+

1

PU13A
<42> MAINPWRON

8

PQ27
TP0610K-T1-E3_SOT23
2

1538VCC

PR204
10K_0402_5%
PR102
33_1206_5%

2

1 1
1

RLS4148_LLDS2

2

2

2

PR192
2M_0402_1%
1

VS
PD20
RLS4148_LLDS2

PD21
2

A

B+

PR203
1.5K_1206_5%
1
2

PC71
0.1U_0603_25V7K

1

RLS4148_LLDS2

CHGRTCP

P

8

1

1

2

EC_ON#

1

1
2

1

2

1
2

2

VIN

PD19

<34>

PR90
499K_0402_1%

C

PR202
1.5K_1206_5%
1
2

PD32

VL

2

VL

PR201
1.5K_1206_5%
1
2

PD28

BATT_B

6

PR200
1.5K_1206_5%
1
2

VL

PR98
150K_0402_1%

RB751V-40TE17_SOD323-2

BATT_A

-

LM393DG_SO8

PR99
150K_0402_1%

2

5

G

1
3

0.022U_0402_16V7K
PR87
470K_0402_1%

RLS4148_LLDS2

VSB

+

O

PR89
287K_0402_1%

PC79
100P_0402_50V8J

1
2

2

1

1

7

2

PU13B
LM393DG_SO8

1

1U_0603_10V6K
PC77

MAINPWRON

7

O

1

2

-

2
G
S

BATT_B
D

PC78

RHU002N06_SOT323

PD17
RLS4148_LLDS2

P

6

PC73
0.022U_0402_16V7K

+

D

1

1
2
8
5

2

2

1

10KB_0603_1%_TH11-3H103FT
PH2

1000P_0402_50V7K
PC76
2
1

PU7B

G

2

TM_REF1

C

PC75
0.1U_0603_25V7K

1

2

PR95
47K_0402_1%

VS

PQ24

2
G
S

PR96
2.15K_0402_1%

1

D

VL

VS

PR97
16.9K_0402_1%

RHU002N06_SOT323

3

VL

PR86
470K_0402_1%

PR88
47K_0402_1%

1
2
<41> BATT_UVM

PR94
47K_0402_1%
1
2

PQ22

2

D

PR65
100K_0402_5%

4

PH2 under CPU botten side :
CPU thermal protection at 80 degree C
Recovery at 44(45) degree C

PR110
560_0402_5%

PC87
4.7U_0805_6.3V6K

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

RTC Batt&OTP&Pre-charge
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
44
1

Rev
X 0.5
of

53

5

4

3

2

1

D

D

1845_B+
PJP11
3MM

2

LX1
DL1

28
1

CS1
OUT1

2

FB1

11

ON1

21

BST2
DH2
LX2
DL2
CS2

19
18
17
20
16

OUT2
FB2
ON2

15
14
12

1

LX2_1.5VSP

BST2_1.5VSP

1

VDD

PC152
4.7U_1206_25V6K

1
2

PC151
4.7U_1206_25V6K

2

+1.5VSP

2

9

DH1

27
24

1

PR213
UVP

BST1

2

4.7UH_MPL73-4R7_5.5A_20%

DH2_1.5VSP
DL2_1.5VSP

PR214 @
5.1K_0402_1%

1
+
2

PC159
150U_D2E_6.3VM_R18

LX1_1.8VP
DL1_1.8VP

@

26

22

4

PU10
25
DH1_1.8VP

VCC

1

2

2

V+

1

2

PL19
PC156
0.1U_0603_25V7K
1

FB2_1.5VSP
1

2

2

+

PC158
4.7U_0805_6.3V6K

1

PC157
150U_D2E_6.3VM_R18

1

AO4916_SO8
0_0402_5%
1
2

+1.8VP

4.7U_0805_6.3V6K
PC160
2
1

PC155

PR212
20_0603_5%
1
2
VCC_MAX8743

BST1_1.8VP

C

@

1
2
3
4

G2
D2
D1/S2/K
D2
D1/S2/K
G1
D1/S2/K S1/A

2

0.1U_0603_25V7K
PC153

2
PR211
0_0402_5%

1

1

8
7
6
5

1U_0805_25V4Z
PC154

1

PL18
4.7UH_MPL73-4R7_5.5A_20%

1
PQ45

AO4916_SO8
0.1U_0603_25V7K

2

3

8
7
6
5

2

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

PC150
2200P_0402_50V7K

1
PD34
DAP202U_SOT323

PQ44
1
2
3
4

2

1

@

C

B+

2

+5VALW

PC100
4.7U_0805_6.3V6K

1
2

PC149
4.7U_1206_25V6K

PC148
2200P_0402_50V7K
2
1

1

2

1
15K_0402_1%

ILIM1_1.8VP

1

REF_MAX8743
PC162
0.22U_0603_10V7K

2

SUSP#P

<37,43>

2

1

2

PR218
33K_0402_1%
2
1
PR219
2
1

PR215
10K_0402_1%

ILIM2_1.5VSP

B

PR217
0_0402_5%

PR221
100K_0402_1%

REF

13
3

ILIM2
ILIM1

PR220
100K_0402_1%
2
1

MAX8743EEI+T_QSOP28~N

10

GND

SKIP
6

@

PC161
0.01U_0402_25V7K

23

PR216
0_0402_5%

B

7
5

PGOOD
TON
OVP

1

8

2

1

SYSON

2

<33,37>

A

A

Compal Electronics, Inc.(KunShan)

Title

+1.5VSP & +1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
45
1

Rev
X 0.5
of

53

5

4

3

2

1

+5VS

CPU_B+

PL20
FBMA-L11-322513-201LMA40T_1210

PR222

CPU_VID3

2

1

D3_CPU

34

D3

DL1

26

DL1_CPU

<7>

CPU_VID4

2

1

D4_CPU

35

D4

PGND1

27

PR234 0_0402_5%

<7>

CPU_VID5

2

1

D5_CPU

36

D5

GND

18

PR235 0_0402_5%

<7>

CPU_VID6

1

2

D6_CPU

37

D6

CSP1

17

FB_CPU

11
2 REF_CPU

REF

CCI

10

CCI_CPU

DPRSLPVR

DH2

21

1

2 DPRSLPVR PC175

<6,21> H_DPRSTP#

1

2 DPRSTP#

40

BST2

20

1

2

PSI#

3

PSI

LX2

22

2

PWRGD

DL2

24

1

CLKEN

<7>

H_PSI#

0.22U_0603_16V7K 39

2

CSP2

VRHOT

CSN2

15

4

POUT

GNDS

13

+5VS

PR244
1

@ 1K_0402_1%
2

PR247
1

3.65K_0402_1%
2

PC176

CLKEN#
MAX8770GTL+_TQFN40
SHDN#

2

PR254
0_0402_5%

1

2
PR251
3K_0603_1%
1

PC182
47U_25V_M

PC181
47U_25V_M

PC168
2200P_0402_50V7K
2
1

PC167
0.1U_0603_25V7K
2
1

PC166
10U_1206_25VAK
2
1

PC165
10U_1206_25VAK
2
1

2
100_0402_5%

PC177
4700P_0402_25V7K

2

PC178
470P_0402_50V8J
B

VSSSENSE

POUT
PC180
0.1U_0402_16V7K

PR259
10_0402_5%

For ULV CPU, PR247 value 8.87K, P/N:SD034887180
For LV CPU, PR247 value 3.65K, P/N: SD034365180

1

PR261
@ 2K_0402_1%

1

2

2

+3VS

2

1

1

PR258
10K_0402_5%

1
@

PR248

C

PR260 0_0402_5%
1
2

VSSSENSE
1

<7>
2

0_0402_5%
1
2

VRHOT

1

PR257
@

2

PR256
100_0402_5%

B

<6> H_PROCHOT#

2

PR253
20K_0402_1%

2

PR255
@ 10K_0402_5%

1
NTC PR250
@ 3K_0603_1%

1

PWRGD_CPU

0.22U_0603_16V7K

@ 1000P_0402_50V7K
CPU_VCC_SENSE
1
2
1

2

CSN2_CPU

1000P_0402_50V7K

2
0_0402_5%
PR252
1
2
1

SHDN

PC174

PR243 0_0402_5%
1
2

TP

1

1
<5> CLK_ENABLE#

1

23

5

2

<22,33> VGATE_INTEL

PR246
2K_0402_1%

PR245
2K_0402_1%

PR249
0_0402_5%

PGND2

14

38

10KB_0603_1%_TH11-3H103FT
1
2

@

2

+3VS

DPRSTP

NTC PH5
3.48K_0402_1%
PR237
2
1
2

1

1

<9,22> H_DPRSLPVR

2

0_0402_5%

CSN1_CPU

12

1

0_0402_5%

PR241

16

FB

41

499_0402_1%

PR240

CSN1

CCV

PC179

PR239

TIME

9

1

@

2

71.5K_0402_1%
7
1

CSP1_CPU

<7>

<7>

PR232 0_0402_5%

+VCC_CORE

PL21
P_0.36H_ETQP4LR36WFC_24A_20%
2
1

VCCSENSE

PR230 0_0402_5%

+
2

PR242

LX1_CPU

2

1

0_0402_5%

28

1

LX1

+

10_0402_5%

D2

1

D

For windows idle mode noise issue

PR236

33

7.68K_0402_1%
PR233
1
2

D2_CPU

1

1

680P_0402_50V7-K

2

PR231

DH1_CPU

CPU_VID2

2

29

<7>

1

DH1

PR229 0_0402_5%

2

D1

PC172

32

3
2
1

D1_CPU

5
6
7
8

1

D
D
D
D

2

B+

4

G
S
S
S

CPU_VID1

0.22U_0603_16V7K

1

PC171
BSTM1_CPU 1
2

PQ48
IRF7832PBF_SO8

<7>

2

DL1_CPU 4
3
2
1

BST1

PR228 0_0402_5%

1

5
6
7
8

D0

30

PC173 2

2

2

PR227

31

1

5
0_0402_5%

D0_CPU

D
D
D
D

BST1_CPU

1

G
S
S
S

8

2

4
3
2
1

TON

CPU_VID0

PR238 2

PC164
10U_1206_25VAK
2
1

1

THRM

<7>

470P_0402_50V7K

2

200K_0402_5%
2 PR224 1

VDD

PQ47
IRF7832PBF_SO8

6

+

SI7840DP-T1-E3_SO8
25

Vcc

PR226 0_0402_5%

C

<33,37> VR_ON

1

1
VCC_CPU
19

1

PQ46

PU15

1

NTC
@ PH4
100K_0603_1%_TH11-4H104FT
1
2

VDD_CPU

2
2

PR225
13K_0402_1%

2

2

PC169
PC170
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K

2
PC183
15U_D2_25VM_R90

0_1206_5%
PR223
10_0402_5%

4.7_1206_5%

D

1
PC163
0.01U_0402_25V7Z

1

2

1

D

3

CLK_ENABLE#

PQ54
PWRGD_CPU 2
G

S

@ RHU002N06_SOT323

PR261,PQ54 will be populated
when MAX8870 Rev0.2 is used.
A

Tsw=Cton(Rton+6.5k)
Cton=16.26pf
f=1/Tsw=1/Cton(Rton+6.5K)
=1/16.26pf(200k+6.5k)=297.824khz
Rton=PR224

A

Compal Electronics, Inc.(KunShan)

Title

PWR-CPU-CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
46
1

Rev
X 0.5
of

53

5

4

3

2

1

D

D

C

C

B

B

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Power up Sequence
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
47
1

Rev
X 0.5
of

53

5

4

3

2

1

HW P.I.R LIST
Change reason

Change item
1. ADD 100K ohm pull-down resistor on ENVDD
D

C

Page#
P18

Follow Intel suggestions

Date
9/05/05

Revision
X0.1

2. ADD one more Panel ID, PID0 to support more panel

Reqired by Mothion

P18

9/05/05

X0.1

3. Add R791, Del R877

Use LED signal from Minicard to control RF LED directly, Reqired by Mothion

P28, P34

9/28/05

X0.1

4. Add R46,R31,R32,JP32 and Q12, Del JP31

Support SD card function and cancel the Smart card function

P25, P26

1/11/06

X0.1

5. Change the net of R22 pin 2 from CLK_48M_SC to CLK_48M_SD

Support SD card function and cancel the Smart card function

P5

1/12/06

X0.1

6. Add R37,R42 to pull high LCTLA_CLK & LCTLB_DATA

Follow Intel Rev 1.601 design check list

P11

1/12/06

X0.1

7. Add U19, C610, Delete D26,D30 and populate R636

Follow Intel Rev 1.601 design check list to pull down ENABLT

P17

1/12/06

X0.1

8. Delete R668,R732

No need these pull high resistor for setting the Boot BIOS destination

P20

1/12/06

X0.1

9.Add an unpopulated resistor R676

Reserved for the future.

P21

1/12/06

X0.1

10. Unpopulate R895

Use the internal pull high of ICH7

P34

1/12/06

X0.1

11. Swap the USB port 3 and port 4 to the docking connector JP27

Follow Motion's request

P36

1/12/06

X0.1

12. Add R48 and C800

Tune regulator power sequence to insure AVDD rail should come up after the DVDD rail

P30

1/14/06

X0.1

13. C26,C32,R59,R60 only populate for 9220;
R59,C798,R58,C799,R61populate for 9204

For 9220 and 9204 co-layout

P30

1/14/06

X0.1

14. change C826/827 from 47uF to 220 uF

Follow Sigmatel suggestions

P31

1/14/06

X0.1

15. Depopulate C846/C847

Follow Sigmatel suggestions

P31

1/14/06

X0.1

16. Change cardbus signals SPKROUT and HWSPND# pull
high power to +3V_R5C843 from +3VALW

Follow FAE check list request

P25

1/16/06

X0.1

17. Add JP31,U19 and related components; delete JP32,Q12
and relatied components

Follow Motion change: add SC, delete SD

P26

1/17/06

X0.1

18. Add layout notice for CCLK/CARD16

Follow FAE check list request

P25

1/19/06

X0.1

19. Add C71

Follow FAE check list request

P25

1/19/06

X0.1

20. Pull cardbus signals TPBP0/TPBN0/TPBP1/TPBN1 to ground

Follow FAE check list request

P25

1/19/06

X0.1

21. Remove U28 and add R1/Q12

Follow motion request: shutdown amplifier to save power in S3 state

P31

1/24/06

X0.1

22. Signal mute# change into mute

Match Item 21 request

P31,P33

1/24/06

X0.1

23. Delete R879, R880 and cancel the net of DDR_ID0, DDR_ID1

Delete the unused DDR_ID0 and DDR_ID1

P33

2/13/06

X0.1

24. JP1 and Add U8

Update the package of CPU from uFCPGA to uFCBGA

P33

2/13/06

X0.1

25. Delete U21, ADD U27

Change the USB HUB to USB controlller

P27

2/21/06

X0.1

26. Delete U1, Add U46

Change the clock Gen to compal part

P5

2/21/06

X0.1

27. Move the net ACOFF from U33 pin31 to U33 pin80
Add the net LED_PWM

Use the PMW signals from EC to contol the brighness of LED

P33,P36

2/21/06

X0.1

28. Delete tlhe R953

Follow Intel USA suggestions

P22

3/01/06

X0.1

29. Delete tlhe R951, R853

Follow Motion's request

P32

3/02/06

X0.1

30.update the Docking connector's symbol

Change the Docking con from 100 pins to 80pins

P36

3/02/06

X0.1

31.Del U23 and relative components, add U47 and relative components

Change the Smart card controller from O2 to Omnikey

P26

3/03/06

X0.1

32.Del U27&JP31 and relative components

Remove the Smart card function

P26

3/07/06

X0.1

D

C

B

B

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Hardware PIR list
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
48
1

Rev
X 0.5
of

53

5

4

3

2

1

HW P.I.R LIST
Change reason

Change item

Page#

Date

Revision

3/07/06

X0.1

33.Add Q15, JP32 and relative components

Follow Motion's request add SD card feature

P26

34.Del LED_PWM, Add PWM_CTL to Q14 pin 2

Follow Motion's solution for LED dimming control

P17

3/09/06

X0.1

35. Add the location for R775,R777,R778,R782,R781,R783 and R476

Reserve the locations for Port 80H debug card when debugging

P24, P5

3/09/06

X0.1

36. Reassign the pin net of Docking

Put the anlog power and analog GND together to get get better placement and return loop.

P36

3/13/06

X0.1

37. Add CF13,CF14 and Del H23, H24,H28,CL2,CL3

New PCB and new feature requirement

P38

3/13/06

X0.1

38. Add the locations for C431,C432,C425,C426,C427
C458,C437,C438C444,C445
39. Change the net of R747.2 from ICH_AZ_CODEC_SDIN0
to SDATA_IN

Reserve the locations for 10uF caps in case of world wide shortage of 22uF caps

P8

3/13/06

X0.1

Correct the net error

P30

3/15/06

X0.1

40. Add C271

Connect GND and LAN shield

P29

3/15/06

X0.1

41. change +0.9V to +0.9VS for VTT of DDR

Power net error

P16

3/21/06

X0.1

42.Populate R918

follow Vishay's suggestion

P35

3/21/06

X0.1

43.Delete Q12, add U31 and unpopulate R1, change MUTE to MUTE#

to avoid the current leakage when MUTE ative and no Headphone plugging in S0

P31

3/22/06

X0.1

44.Add R73, R74

For debug use only

P27

3/24/06

X0.1

45. Update JP24 symbol

Use small footprint for layout space saving

P33

3/24/06

X0.1

46.ADD D34,D35,D36,D37,D38,D39,D40,D41,D42,D43,D44

Add the location of ESD protection Diode for HSYNC, VSYNC, ON/OFFBTN#, WL_SW# and DVI signal lines.

3/30/06

X0.1

47.Delete R772

remove the dual pull-up resistors for WL_SW#

P24

3/31/06

X0.1

48.Delete Q7, Add D45

update symbol

P17

4/07/06

X0.1

49.Add R472,R473,R478,R479,C359,C360,C361,C362

Add these components for signal quality of SD.

P25

4/10/06

X0.1

50.Add R951, R953, R964, R965, C930 and Q63

To support usb wake up from docking and wake up function can be selected by user.

P32,P36

5/12/06

X0.2

51.Delete R775 ;pin10,pin12,pin14,pin16 of JP13 net swap

Delete the useless power and change error the LPC nets for port 80H debug card

P24

5/12/06

X0.2

52.Add R2

To pull high HP_PLUG# to give it a stable status.

P31

5/12/06

X0.2

53.Add R480, C363

To reduce the SD_CMD's overshoot and undershoot

P25

5/15/06

X0.2

54.Add C611, C612,C619,C625

Follow Motion's request

P15,P16

5/15/06

X0.2

55.Add H51, JP12,JP22,JP23

Add a hole to fix HDD FPC, symbols of VGA connentor and usb connectors update for ME requirement

P38,P19,P32

5/24/06

X0.2

D

D

C

B

C

P19,P34,P36,
P24,P18

56.Add C633,C671,C672,C677

Follow motion's request

P49,P17

5/24/06

X0.2

57.unpopulate R73

To solve the issue of system hangup when enable NEC controller

P49,P27

5/26/06

X0.2

58.reasssign the docking usb ports to ICH7

To support DOS mode for all docking ports

P22,P36

5/26/06

X0.2

59.Delete Q62,Q13,R776,R780,R791,R924

Remove LEDs for HDD,B/T and WWAN,WLAN

P17,P27,P24

5/26/06

X0.2

60.Add D6,D9,D13,R4,R7,R8

Support the LEDs change to M/B

P17

5/29/06

X0.2

61.Add two nets of WLAN_SW_EN, WWAN_SW_EN on U33,JP30

Follow SED request for supprting antenna's switching

P33,P36

5/29/06

X0.2

62.Change nets of JP6.24, JP6.36 from GND to +3vs, add R263,R262

follow motion's request of reserving 4 power wires for N-trig

P17

6/01/06

X0.2

To support WOWLAN & WOL in AC only mode

P28,P24

6/06/06

X0.2

For more power saving and extendeing the life of bridge batter in S3 mode

P27,P22

63.Change Q52, from AO3402 to SI3456,
JP13&JP28 pin24 from+3VALW to +3V_LAN
64.Change +3VALW of U27 to +3VS,Del R315, change USB_SMI#
from U9.E21 to U9.AC18, populate R346,R320, unpopulate R312,R321
A

65.Swap the nets of U46.16&U46.17

modify the wrongly connected SMbus of clock Gen, to solve the issue of C3 hang up

66.Add R641, R633, change the net of PID1 to ID0

add ID0, ID1 two hw strap pins to identify the N-Trig Wacom or TouchKo

P5
P17,P22

6/06/06

X0.2

6/06/06

X0.2

6/07/06

X0.2

B

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Hardware PIR list
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
49
1

Rev
X 0.5
of

53

5

4

3

2

1

HW P.I.R LIST
Change reason

Date

Revision

67.Change R8 from 150ohm to 2.2K

Change item
Solve LED no light issue

Page#
P17

7/17/06

X0.3

68.Swap cardbus controller U15B pinV14/W14 net names

Solve new card can not be detected issue

P25

7/17/06

X0.3

69.Change H26/H27 size from 110 to 165

Solve standoff too big & hole too small to dock-MB/B can not fix well issue

P38

7/17/06

X0.3

70.Add PID and ID table; change LCD connector symbol

Be beneficial to look at schematic; connect NC pin for EMI providing

D

D

No use

P38

7/17/06

72.Change block diagram

Follow Motion requirement

P2

7/27/06

X0.3

73.Add R3, unpopulate R918/R919

Solving Irda communication information occur error issue

P35

74.Populate R17/R18

Follow EMI requirement

P30

7/31/06

X0.3

75.Change R11 to L21

Follow EMI requirement

P30

7/31/06

X0.3

AO4422 will EOL, AO4468 will substitute it

P37

7/31/06

Solving DFX issue

X0.3

X0.3

P36

7/31/06

X0.3

78. Add mark LV@ on +VCC_CORE 12*22U & 2*330U
decoupling capacitors

For Motion requirement

P8

7/31/06

X0.3

79. Add unpopulate R698/C678

Following Motion requirement for providing EMI

P27

8/1/06

X0.3

80. Add unpopulate R699/C679

Following Motion requirement for providing EMI

P25

8/1/06

X0.3

81. Add series resistors R700/R707

Following Sigmatel requirement

P31

8/1/06

X0.3

82. Change C835/C836 from 220pF to 0.01U

Following Sigmatel requirement

P31

8/1/06

X0.3

C

83. Change L27/L28/L29/L30/L31/L32/L33/L34 to L22/L23/L24/L25
co-layout with R818/R819/R820/R821/R822/R823/R824/R825

P29

Follow EMI requirement

84. Add unpopulate JP29 on side of NEC controller

A

X0.3

7/31/06

77.Add new JP34, delete old JP29/JP34

B

X0.3

7/17/06

71.Delete H50

76.Change U42/U43/U44 from AO4422 to AO4468

C

P17

For Motion requirement

8/1/06

X0.3

P27

8/2/06

X0.3
X0.3

85.Change H18 size from C276D110 to C197D110

For ME change requirement

P38

8/2/06

86. Add C74/C75

Following Motion requirement

P28

8/2/06

X0.3

87. Delete R57,R69,C798

Co-layout Trinity and delete co-layout Colorado with STAC9220

P30

8/4/06

X0.3

88. Add U1/C680/C931/C932/R446

Adding buffer to generate V_DDR_MCH_REF to solve SODIM sometime can not boot issue

P9

89. Change R81 from 4.87K to 4.75K

Following Marvell requirement to optimize LAN chip usage

P28

90. Change C69/C70 from 27pF to 18pF

Following Marvell requirement to optimize LAN chip usage

P28

91. Change transformer T21 from GST5009-LF to GST5009-V

Following Marvell requirement to optimize LAN chip usage

P29

8/14/06

X0.3

8/7/06

X0.3

8/14/06
8/14/06

X0.3

92. Change U16/U31 power supply from +5VALW to +5VS

Save power in S3 state and reduce speakers output noise

P31

8/14/06

X0.3

93.Add R23/R25/U47/C39/C798/R57/Q62 footprint on board

Reserve for reduce headphone pop niose

P30

8/16/06

X0.3

94. Delete Q61, R685, R668, Q14, D6, D9, D13, R7, R8, R4.
Add R924, Q16, R712, R642, R6, Q64, R364, D15, R331, Q66,
R317, D19, R330, Q65, R315, D16.

As Motion requirement. Add LED brightness control function.

P17

9/29/06

X0.4

95. Change J2, J3 size, change J6 to Jump type.

Follow factory DFX requirement.

P17

9/29/06

X0.4

96. Add C681, R717, R716.
Change JP6.40 from GND to PID1.
Add signal PID1 to ICH7.AE20.

Follow Motion requirement. Add one pin to support panel ID.

P17
P22

9/29/06

X0.4

97. Add R718, Q11.
Add signal DVI_DETECT# to ICH7. AD21.

Follow Motion requirement. Add DVI plug detect function to ICH.

P18
P22

98. Change R34 from un-mounted to mounted.
Add U48, R60, R451, Q67, U49.

Follow Motion requirement. Add power saving function for Ricoh controller.

P25

9/29/06

B

X0.3

X0.4

9/29/06

A

X0.4

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Hardware PIR list
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
50
1

Rev
X 0.5
of

53

5

4

3

2

1

HW P.I.R LIST
Change reason

Change item

D

100. Delete R287.
Add R87, R82, R86, R83, R84, R85.

For debug.

P27

9/29/06

X0.4

P33

9/29/06

X0.4

P33

9/29/06

X0.4

102. Add location CLIP1

For deal with antenna routing conveniently

P38

10/16/06

X0.4

103. Add R294

FIR part change

P35

10/17/06

X0.4

104. Add U56, C686, C685, C684, C683, R725,
R730, R720, R968, C687, Q61, Q69, U57.
Add signal G_SENSOR to EC.

Add G-Sensor function

P24

10/17/06

X0.4

Solve +5V_DOCK turn on/off condition validity
No use

P36

11/01/06

X0.4

P33

11/01/06

X0.4

107. Delete U57,change U33 pin62/pin90 net name

Follow vender review result to change

P24, P33

11/01/06

X0.4

108. Delete EC U33 pin91/pin92 net name

No use

P33

11/01/06

X0.4

109. JP30 pin4 and pin6 pull down to ground

No use

P36

11/01/06

X0.4

111.Change U33 pin46 net name from RFOFF# to WLANOFF#
Change U33 pin92 net name from WWAN_SW_EN to WWANOFF#
Change JP13 net name from RFOFF# to WLANOFF#
Change JP28 net name from RFOFF# to WWANOFF#

Swap WWAN and BT, ensure WWAN to be used under DOS mode

Separate WLAN and WWAN on/off control signal

112. H9 connect to digital ground from analog ground

Antenna pass through H9 area, provide signal being interfere

113. Add C416

Delay shutdown ramp up time to solve headphone pop-noise

114. Add unpopulate C507

For HSDL-3220 FIR reserve capacitor

P24, P27

11/01/06

P24, P33

11/01/06

P38

11/01/06

P30

11/01/06

P35
P33

11/01/06
11/01/06

X0.4
X0.4

X0.4
X0.4
X0.4
X0.4

115. Delete R328,R316, project_ID related table

No use

116. R327/R326 populate, R267/r157 unpopulate

Correct BDID configuration

P33

11/01/06

X0.4

117. Add unpopulate R966/C933

Add AC ternimation for EMI providing

P24

11/01/06

X0.4

Solving BIOS/B connect stably with MB

P34

118. Change BIOS/B connector from E&T_1009-E40L-00R
to ACES_88072-4071_40P
119. Change USB connector from SUYIN_020173MR004S500ZL
to SUYIN_020173MR004S583ZL
120. JP19,
change Pin1 to GNDA;
change Pin2 to INTMIC3;
change Pin3 to GNDA;
121. JP34;
Move Pin11 --> Pin9
Move Pin10 --> Pin11
Move Pin9 --> Pin10
122. Change H26/H27 size form C276D165 to C276D173

D

C

110. Buletooth USBP2+/- change into NEC_USBP2+/-;
JP28 NEC_USBP2+/- change into USBP2+/-

11/06/06

P32

11/06/06

X0.4

Solve the MIC(3rd) noise issue;

P36

11/08/06

X0.4

Solve the MIC(Mic2) 'click' noise issue;

P31

11/08/06

X0.4

Solve the docking CRT signal instability issue

P38

11/14/06

X0.4

P35

11/14/06

X0.4

P31
P33

12/27/06

X0.5

Follow SMSC schematics review

124. Change L42/L47 from BLM18AG601SND1 to BK1608HM601-T

Follow IDT AP test feedback result

125. Swap EC U33 pin27 and pin30

Solving fan noise, pin30 PWM can not be programming to 30KHz

126. Delete R718, delete U9 pinAD21 net to NC the pin ,
change net PCI_REQ5# into DVI_DETECT#

Solving DVI can be automatically detected by system when inserting

P18, P20,P22

B

X0.4

Solving USB connector stability when inserting USB device

123. Add unpopulate R283/R967 and R969

A

Revision

Follow Motion requirement. Add power saving function for NEC controller and Ricoh controller.

106. Delete EC U33 pin62 project _ID net name

B

Date

101. Add R333, R332.
Add signal PCM_CLK_EN#, USB_CLK_EN#, Card_Insert#.

105. Swap EC U33 pin35 and pin80

C

Page#

Follow Motion requirement. Add power saving function for NEC controller.

99. Add R826, R452, Q68, U50, R75, U53.
Change U27 power supply from +3VS to +3V_NECUSB.

12/27/06

X0.5

12/28/06

X0.5

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Hardware PIR list
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
51
1

Rev
X 0.5
of

53

5

4

3

2

1

HW P.I.R LIST
Change reason

Change item

D

Date

Revision

127. Redefine BID

For reviewing

P33

12/28/06

X0.5

128. Add Q70, Q72, R731, R732

Providing ALS/B leak current to +3VS

P36

12/29/06

X0.5

P36

12/29/06

X0.5

P33,P30

12/29/06

X0.5

129. Re-assign MB ALS/B connector JP34 pin

Solving the 1st array mic noise issue

130. unpopulate Q62/C416, add R88, when use MAX9890,
use U33 pin91 control shutdown pin with R88

Reduce HP pop noise

131. Change PCIE 0.1u capacitor C631/C632/C629/C630/C661/C670
part number

Solving PCIE capacitor temperature characteristic unstable issue

Page#

P22

D

X0.5

12/29/06

132. Change FIR module U41 to agielent HSDL-3220

Use agielent FIR module to solve FIR transmition and receive fail issue

P35

12/29/06

X0.5

133. Change JP30 pin19 GND to GNDA

Solving 2nd array mic noise issue

P36

12/29/06

X0.5

134. Change R965 form 100 to 22K; change C930 from 0.1U to 0.47U
and re-connect; change R964 from 100K to 330K; add R970

Solving vibration issue when S3 wake up only battery supply power

P36

12/29/06

X0.5

135. change JP34 pin assignment

Avoid record noise in internal MIC1

P36

01/08/07

X0.5

136. delete signal "Blanco_USB_OC#"

Avoid ESD fail on this pin

P34

01/08/07

X0.5

C

C

B

B

A

A

Compal Electronics, Inc.(KunShan)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Hardware PIR list
Size
Custom
Date:

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
52
1

Rev
X 0.5
of

53

5

4

3

2

1

POWER P.I.R LIST
Change reason

Change item
1. Change PR39 from 1K_0402_1% to 10K_0402_1%.

D

2. Add PQ51,PQ49,PR262, change PR163 from 0 to
84.5K,change PR164 from 0 to 100K.
3. Del MAX8578 circuit(PU6,PQ41,PL17,PL16...),add ISL6269 solution
for VCCP(PU16,PQ52,PQ53,PL22,PL23...).
4. Remove PC88 from PU14.3 to PU14.1
5. Delete PC88,PU14

Page#

Date

Revision

For MAX1908 issue.

P40

01/14/06

X0.1

Add switch function to support Sanyo 4.35 cell battery.

P40

03/03/06

X0.1

Improve VCCP supply current from 4A to 7A.

P43

03/03/06

X0.1

Connection error

P43

03/24/06

X0.1

Use ISL6269 PGOOD as VCCP_POK.

P43

03/30/06

X0.1

6. ADD PC88,PU14 ,PR264

Use PU14 produce VCCP_POK.

6. ADD PR34,change PR10 form 7.32K to 3.92K

Providing PR10 being destroied only one resistor as load, one resistor divide into two resistors to reduce resistor fail risk

P39

10/16/06

D

X0.4

C

C

B

B

A

A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Power PIR list
Size
Custom
Date:

5

4

3

2

Document Number

PecosII-IDX80-LA3291
Sheet
Monday, January 08, 2007
53
1

Rev
X 0.5
of

53



---

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File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : Yes
Create Date                     : 2007:01:11 14:36:05+08:00
Modify Date                     : 2007:01:11 14:36:05+08:00
Page Count                      : 53
Creation Date                   : 2007:01:11 06:36:05Z
Mod Date                        : 2007:01:11 06:36:05Z
Producer                        : Acrobat Distiller 5.0 (Windows)
Metadata Date                   : 2007:01:11 06:36:05Z

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