Intel® 64 And IA 32 Architectures Software Developer’s Manual, Volume 3B: System Programming Guide, Part 2 Intel 2018 11 [Intel Manual Vol.3B
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- Chapter 14 Power and Thermal Management
- 14.1 Enhanced Intel Speedstep® Technology
- 14.2 P-State Hardware Coordination
- 14.3 System Software Considerations and Opportunistic processor Performance operation
- 14.4 Hardware-Controlled Performance States (HWP)
- 14.4.1 HWP Programming Interfaces
- 14.4.2 Enabling HWP
- 14.4.3 HWP Performance Range and Dynamic Capabilities
- 14.4.4 Managing HWP
- 14.4.5 HWP Feedback
- 14.4.6 HWP Notifications
- 14.4.7 Idle Logical Processor Impact on Core Frequency
- 14.4.8 Fast Write of Uncore MSR (Model Specific Feature)
- 14.4.9 Fast_IA32_HWP_REQUEST CPUID
- 14.4.10 Recommendations for OS use of HWP Controls
- 14.5 Hardware Duty Cycling (HDC)
- 14.6 MWAIT Extensions for Advanced Power Management
- 14.7 Thermal Monitoring and Protection
- 14.8 Package Level Thermal Management
- 14.9 Platform Specific Power Management Support
- Chapter 15 Machine-Check Architecture
- 15.1 Machine-Check Architecture
- 15.2 Compatibility with Pentium Processor
- 15.3 Machine-Check MSRs
- 15.4 Enhanced Cache Error reporting
- 15.5 Corrected Machine Check Error Interrupt
- 15.6 Recovery of Uncorrected Recoverable (UCR) Errors
- 15.7 Machine-Check Availability
- 15.8 Machine-Check Initialization
- 15.9 Interpreting the MCA Error Codes
- 15.10 Guidelines for Writing Machine-Check Software
- Chapter 16 Interpreting Machine-Check Error Codes
- 16.1 Incremental Decoding Information: Processor Family 06H Machine Error Codes For Machine Check
- 16.2 Incremental Decoding Information: Intel Core 2 Processor Family Machine Error Codes For Machine Check
- 16.3 Incremental Decoding Information: Processor Family with CPUID DisplayFamily_DisplayModel Signature 06_1AH, Machine Error Codes For Machine Check
- 16.4 Incremental Decoding Information: Processor Family with CPUID DisplayFamily_DisplayModel Signature 06_2DH, Machine Error Codes For Machine Check
- 16.5 Incremental Decoding Information: Processor Family with CPUID DisplayFamily_DisplayModel Signature 06_3EH, Machine Error Codes For Machine Check
- 16.6 Incremental Decoding Information: Processor Family with CPUID DisplayFamily_DisplayModel Signature 06_3FH, Machine Error Codes For Machine Check
- 16.7 Incremental Decoding Information: Processor Family with CPUID DisplayFamily_DisplayModel Signature 06_56H, Machine Error Codes For Machine Check
- 16.8 Incremental Decoding Information: Processor Family with CPUID DisplayFamily_DisplayModel Signature 06_4FH, Machine Error Codes For Machine Check
- 16.9 Incremental Decoding Information: Processor Family with CPUID DisplayFamily_DisplayModel Signature 06_55H, Machine Error Codes For Machine Check
- 16.10 Incremental Decoding Information: Processor Family with CPUID DisplayFamily_DisplayModel Signature 06_5FH, Machine Error Codes For Machine Check
- 16.11 Incremental Decoding Information: Processor Family 0FH Machine Error Codes For Machine Check
- Chapter 17 Debug, Branch Profile, TSC, and Intel® Resource Director Technology (Intel® RDT) Features
- 17.1 Overview of Debug Support Facilities
- 17.2 Debug Registers
- 17.3 Debug Exceptions
- 17.4 Last Branch, Interrupt, and Exception Recording Overview
- 17.4.1 IA32_DEBUGCTL MSR
- 17.4.2 Monitoring Branches, Exceptions, and Interrupts
- 17.4.3 Single-Stepping on Branches
- 17.4.4 Branch Trace Messages
- 17.4.5 Branch Trace Store (BTS)
- 17.4.6 CPL-Qualified Branch Trace Mechanism
- 17.4.7 Freezing LBR and Performance Counters on PMI
- 17.4.8 LBR Stack
- 17.4.9 BTS and DS Save Area
- 17.5 Last Branch, Interrupt, and Exception Recording (Intel® Core™ 2 Duo and Intel® Atom™ Processors)
- 17.6 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Microarchitecture
- 17.7 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus Microarchitecture
- 17.8 Last Branch, Interrupt and Exception Recording for Intel® Xeon Phi™ Processor 7200/5200/3200
- 17.9 Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Nehalem
- 17.10 Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Sandy Bridge
- 17.11 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Haswell Microarchitecture
- 17.12 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture
- 17.13 Last Branch, Interrupt, and Exception Recording (Processors based on Intel NetBurst® Microarchitecture)
- 17.14 Last Branch, Interrupt, and Exception Recording (Intel® Core™ Solo and Intel® Core™ Duo Processors)
- 17.15 Last Branch, Interrupt, and Exception Recording (Pentium M Processors)
- 17.16 Last Branch, Interrupt, and Exception Recording (P6 Family Processors)
- 17.17 Time-Stamp Counter
- 17.18 Intel® Resource Director Technology (Intel® RDT) Monitoring Features
- 17.18.1 Overview of Cache Monitoring Technology and Memory Bandwidth Monitoring
- 17.18.2 Enabling Monitoring: Usage Flow
- 17.18.3 Enumeration and Detecting Support of Cache Monitoring Technology and Memory Bandwidth Monitoring
- 17.18.4 Monitoring Resource Type and Capability Enumeration
- 17.18.5 Feature-Specific Enumeration
- 17.18.6 Monitoring Resource RMID Association
- 17.18.7 Monitoring Resource Selection and Reporting Infrastructure
- 17.18.8 Monitoring Programming Considerations
- 17.19 Intel® Resource Director Technology (Intel® RDT) Allocation Features
- 17.19.1 Introduction to Cache Allocation Technology (CAT)
- 17.19.2 Cache Allocation Technology Architecture
- 17.19.3 Code and Data Prioritization (CDP) Technology
- 17.19.4 Enabling Cache Allocation Technology Usage Flow
- 17.19.4.1 Enumeration and Detection Support of Cache Allocation Technology
- 17.19.4.2 Cache Allocation Technology: Resource Type and Capability Enumeration
- 17.19.4.3 Cache Allocation Technology: Cache Mask Configuration
- 17.19.4.4 Class of Service to Cache Mask Association: Common Across Allocation Features
- 17.19.5 Code and Data Prioritization (CDP): Enumerating and Enabling L3 CDP Technology
- 17.19.6 Code and Data Prioritization (CDP): Enumerating and Enabling L2 CDP Technology
- 17.19.6.1 Mapping Between L2 CDP Masks and L2 CAT Masks
- 17.19.6.2 Common L2 and L3 CDP Programming Considerations
- 17.19.6.3 Cache Allocation Technology Dynamic Configuration
- 17.19.6.4 Cache Allocation Technology Operation With Power Saving Features
- 17.19.6.5 Cache Allocation Technology Operation with Other Operating Modes
- 17.19.6.6 Associating Threads with CAT/CDP Classes of Service
- 17.19.7 Introduction to Memory Bandwidth Allocation
- Chapter 18 Performance Monitoring
- 18.1 Performance Monitoring Overview
- 18.2 Architectural Performance Monitoring
- 18.3 Performance Monitoring (Intel® Core™ Processors and Intel® Xeon® Processors)
- 18.3.1 Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name Nehalem
- 18.3.2 Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name Westmere
- 18.3.3 Intel® Xeon® Processor E7 Family Performance Monitoring Facility
- 18.3.4 Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name Sandy Bridge
- 18.3.4.1 Global Counter Control Facilities In Intel® Microarchitecture Code Name Sandy Bridge
- 18.3.4.2 Counter Coalescence
- 18.3.4.3 Full Width Writes to Performance Counters
- 18.3.4.4 PEBS Support in Intel® Microarchitecture Code Name Sandy Bridge
- 18.3.4.5 Off-core Response Performance Monitoring
- 18.3.4.6 Uncore Performance Monitoring Facilities In Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series
- 18.3.4.7 Intel® Xeon® Processor E5 Family Performance Monitoring Facility
- 18.3.4.8 Intel® Xeon® Processor E5 Family Uncore Performance Monitoring Facility
- 18.3.5 3rd Generation Intel® Core™ Processor Performance Monitoring Facility
- 18.3.6 4th Generation Intel® Core™ Processor Performance Monitoring Facility
- 18.3.6.1 Processor Event Based Sampling (PEBS) Facility
- 18.3.6.2 PEBS Data Format
- 18.3.6.3 PEBS Data Address Profiling
- 18.3.6.4 Off-core Response Performance Monitoring
- 18.3.6.5 Performance Monitoring and Intel® TSX
- 18.3.6.6 Uncore Performance Monitoring Facilities in the 4th Generation Intel® Core™ Processors
- 18.3.6.7 Intel® Xeon® Processor E5 v3 Family Uncore Performance Monitoring Facility
- 18.3.7 5th Generation Intel® Core™ Processor and Intel® Core™ M Processor Performance Monitoring Facility
- 18.3.8 6th Generation, 7th Generation and 8th Generation Intel® Core™ Processor Performance Monitoring Facility
- 18.4 Performance monitoring (Intel® Xeon™ Phi Processors)
- 18.5 Performance Monitoring (Intel® Atom™ Processors)
- 18.6 Performance Monitoring (Legacy Intel Processors)
- 18.6.1 Performance Monitoring (Intel® Core™ Solo and Intel® Core™ Duo Processors)
- 18.6.2 Performance Monitoring (Processors Based on Intel® Core™ Microarchitecture)
- 18.6.3 Performance Monitoring (Processors Based on Intel NetBurst® Microarchitecture)
- 18.6.3.1 ESCR MSRs
- 18.6.3.2 Performance Counters
- 18.6.3.3 CCCR MSRs
- 18.6.3.4 Debug Store (DS) Mechanism
- 18.6.3.5 Programming the Performance Counters for Non-Retirement Events
- 18.6.3.6 At-Retirement Counting
- 18.6.3.7 Tagging Mechanism for Replay_event
- 18.6.3.8 Processor Event-Based Sampling (PEBS)
- 18.6.3.9 Operating System Implications
- 18.6.4 Performance Monitoring and Intel Hyper-Threading Technology in Processors Based on Intel NetBurst® Microarchitecture
- 18.6.5 Performance Monitoring and Dual-Core Technology
- 18.6.6 Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache
- 18.6.7 Performance Monitoring on L3 and Caching Bus Controller Sub-Systems
- 18.6.8 Performance Monitoring (P6 Family Processor)
- 18.6.9 Performance Monitoring (Pentium Processors)
- 18.7 Counting Clocks
- 18.7.1 Non-Halted Reference Clockticks
- 18.7.2 Cycle Counting and Opportunistic Processor Operation
- 18.7.3 Determining the Processor Base Frequency
- 18.7.3.1 For Intel® Processors Based on Microarchitecture Code Name Sandy Bridge, Ivy Bridge, Haswell and Broadwell
- 18.7.3.2 For Intel® Processors Based on Microarchitecture Code Name Nehalem
- 18.7.3.3 For Intel® Atom™ Processors Based on the Silvermont Microarchitecture (Including Intel Processors Based on Airmont Microarchitecture)
- 18.7.3.4 For Intel® Core™ 2 Processor Family and for Intel® Xeon® Processors Based on Intel Core Microarchitecture
- 18.8 IA32_PERF_CAPABILITIES MSR Enumeration
- Chapter 19 Performance Monitoring Events
- 19.1 Architectural Performance Monitoring Events
- 19.2 Performance Monitoring Events for Intel® Xeon® Processor Scalable Family
- 19.3 Performance Monitoring Events for 6th Generation, 7th Generation and 8th Generation Intel® Core™ Processors
- 19.4 Performance Monitoring Events for Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series and Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
- 19.5 Performance Monitoring Events for the Intel® Core™ M and 5th Generation Intel® Core™ Processors
- 19.6 Performance Monitoring Events for the 4th Generation Intel® Core™ ProcessorS
- 19.7 Performance Monitoring Events for 3rd Generation Intel® Core™ ProcessorS
- 19.8 Performance Monitoring Events for 2nd Generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series
- 19.9 Performance Monitoring Events for Intel® Core™ i7 Processor Family and Intel® Xeon® Processor Family
- 19.10 Performance Monitoring Events for processors based on Intel® microarchitecture Code Name Westmere
- 19.11 Performance Monitoring Events for Intel® Xeon® Processor 5200, 5400 Series and Intel® Core™2 Extreme Processors QX 9000 Series
- 19.12 Performance Monitoring Events for Intel® Xeon® Processor 3000, 3200, 5100, 5300 Series and Intel® Core™2 Duo ProcessorS
- 19.13 Performance Monitoring Events for Processors Based on the Goldmont Plus Microarchitecture
- 19.14 Performance Monitoring Events for Processors Based on the Goldmont Microarchitecture
- 19.15 Performance Monitoring Events for Processors Based on the Silvermont Microarchitecture
- 19.16 Performance Monitoring Events for 45 nm and 32 nm Intel® Atom™ Processors
- 19.17 Performance Monitoring Events for Intel® Core™ Solo and Intel® Core™ Duo Processors
- 19.18 Pentium® 4 and Intel® Xeon® Processor Performance Monitoring Events
- 19.19 Performance Monitoring Events for Intel® Pentium® M Processors
- 19.20 P6 Family Processor Performance Monitoring Events
- 19.21 Pentium Processor Performance Monitoring Events
- Chapter 20 8086 Emulation
- 20.1 Real-Address Mode
- 20.2 Virtual-8086 Mode
- 20.3 Interrupt and Exception Handling in Virtual-8086 Mode
- 20.4 Protected-Mode Virtual Interrupts
- Chapter 21 Mixing 16-Bit and 32-Bit Code
- Chapter 22 Architecture Compatibility
- 22.1 Processor Families and Categories
- 22.2 Reserved Bits
- 22.3 Enabling New Functions and Modes
- 22.4 Detecting the Presence of New Features Through Software
- 22.5 Intel MMX Technology
- 22.6 Streaming SIMD Extensions (SSE)
- 22.7 Streaming SIMD Extensions 2 (SSE2)
- 22.8 Streaming SIMD Extensions 3 (SSE3)
- 22.9 Additional Streaming SIMD Extensions
- 22.10 Intel Hyper-Threading Technology
- 22.11 Multi-Core Technology
- 22.12 Specific Features of Dual-Core Processor
- 22.13 New Instructions In the Pentium and Later IA-32 Processors
- 22.14 Obsolete Instructions
- 22.15 Undefined Opcodes
- 22.16 New Flags in the EFLAGS Register
- 22.17 Stack Operations and User Software
- 22.18 x87 FPU
- 22.18.1 Control Register CR0 Flags
- 22.18.2 x87 FPU Status Word
- 22.18.3 x87 FPU Control Word
- 22.18.4 x87 FPU Tag Word
- 22.18.5 Data Types
- 22.18.6 Floating-Point Exceptions
- 22.18.6.1 Denormal Operand Exception (#D)
- 22.18.6.2 Numeric Overflow Exception (#O)
- 22.18.6.3 Numeric Underflow Exception (#U)
- 22.18.6.4 Exception Precedence
- 22.18.6.5 CS and EIP For FPU Exceptions
- 22.18.6.6 FPU Error Signals
- 22.18.6.7 Assertion of the FERR# Pin
- 22.18.6.8 Invalid Operation Exception On Denormals
- 22.18.6.9 Alignment Check Exceptions (#AC)
- 22.18.6.10 Segment Not Present Exception During FLDENV
- 22.18.6.11 Device Not Available Exception (#NM)
- 22.18.6.12 Coprocessor Segment Overrun Exception
- 22.18.6.13 General Protection Exception (#GP)
- 22.18.6.14 Floating-Point Error Exception (#MF)
- 22.18.7 Changes to Floating-Point Instructions
- 22.18.7.1 FDIV, FPREM, and FSQRT Instructions
- 22.18.7.2 FSCALE Instruction
- 22.18.7.3 FPREM1 Instruction
- 22.18.7.4 FPREM Instruction
- 22.18.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions
- 22.18.7.6 FPTAN Instruction
- 22.18.7.7 Stack Overflow
- 22.18.7.8 FSIN, FCOS, and FSINCOS Instructions
- 22.18.7.9 FPATAN Instruction
- 22.18.7.10 F2XM1 Instruction
- 22.18.7.11 FLD Instruction
- 22.18.7.12 FXTRACT Instruction
- 22.18.7.13 Load Constant Instructions
- 22.18.7.14 FXAM Instruction
- 22.18.7.15 FSAVE and FSTENV Instructions
- 22.18.8 Transcendental Instructions
- 22.18.9 Obsolete Instructions and Undefined Opcodes
- 22.18.10 WAIT/FWAIT Prefix Differences
- 22.18.11 Operands Split Across Segments and/or Pages
- 22.18.12 FPU Instruction Synchronization
- 22.19 Serializing Instructions
- 22.20 FPU and Math Coprocessor Initialization
- 22.21 Control Registers
- 22.22 Memory Management Facilities
- 22.23 Debug Facilities
- 22.24 Recognition of Breakpoints
- 22.25 Exceptions and/or Exception Conditions
- 22.26 Interrupts
- 22.27 Advanced Programmable Interrupt Controller (APIC)
- 22.28 Task Switching and TSs
- 22.29 Cache Management
- 22.30 Paging
- 22.31 Stack Operations and Supervisor Software
- 22.32 Mixing 16- and 32-Bit Segments
- 22.33 Segment and Address Wraparound
- 22.34 Store Buffers and Memory Ordering
- 22.35 Bus Locking
- 22.36 Bus Hold
- 22.37 Model-Specific Extensions to the IA-32
- 22.38 Two Ways to Run Intel 286 Processor Tasks
- 22.39 Initial State of Pentium, Pentium Pro and Pentium 4 Processors