Kinetis KL25: 48MHz Cortex M0+ 32 128KB Flash 80 Pin KL25Z Reference Manual

User Manual:

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Chapter 1: About This Document
- Overview
  - Purpose
  - Audience
- Conventions
Chapter 2: Introduction
- Overview
- Kinetis L Series
- KL25 Sub-Family Introduction
- Module functional categories
- Orderable part numbers
Chapter 3: Chip Configuration
- Introduction
- Module to Module Interconnects
  - Module to Module Interconnects
  - Analog reference options
- Core Modules
- System Modules
- Clock Modules
  - MCG Configuration
    - MCG FLL modes
  - OSC Configuration
    - OSC modes of operation with MCG and RTC
- Memories and Memory Interfaces
- Analog
- Timers
- Communication interfaces
- Human-machine interfaces (HMI)
  - GPIO Configuration
  - TSI Configuration
    - TSI Instantiation Information
    - TSI Interrupts
Chapter 4: Memory Map
- Introduction
- System memory map
- Flash Memory Map
  - Alternate Non-Volatile IRC User Trim Description
- SRAM memory map
- Bit Manipulation Engine
- Peripheral bridge (AIPS-Lite) memory map
- Private Peripheral Bus (PPB) memory map
Chapter 5: Clock Distribution
- Introduction
- Programming model
- High-Level device clocking diagram
- Clock definitions
  - Device clock summary
- Internal clocking requirements
  - Clock divider values after reset
  - VLPR mode clocking
- Clock Gating
- Module clocks
Chapter 6: Reset and Boot
- Introduction
- Reset
- Boot
Chapter 7: Power Management
- Introduction
- Clocking Modes
- Power modes
- Entering and exiting power modes
- Module Operation in Low Power Modes
Chapter 8: Security
- Introduction
- Flash Security
- Security Interactions with other Modules
  - Security Interactions with Debug
Chapter 9: Debug
- Introduction
- Debug Port Pin Descriptions
- SWD status and control registers
  - MDM-AP Control Register
  - MDM-AP Status Register
- Debug Resets
- Micro Trace Buffer (MTB)
- Debug in Low Power Modes
- Debug & Security
Chapter 10: Signal Multiplexing and Signal Descriptions
- Introduction
- Signal Multiplexing Integration
- Pinout
  - KL25 Signal Multiplexing and Pin Assignments
  - KL25 Pinouts
- Module Signal Description Tables
Chapter 11: Port control and interrupts (PORT)
- Introduction
- Overview
  - Features
  - Modes of operation
- External signal description
- Detailed signal description
- Memory map and register definition
  - PORTx
- Functional description
Chapter 12: System integration module (SIM)
- Introduction
  - Features
- Memory map and register definition
  - SIM
- Functional description
Chapter 13: System Mode Controller (SMC)
- Introduction
- Modes of operation
- Memory map and register descriptions
  - SMC
- Functional description
Chapter 14: Power Management Controller (PMC)
- Introduction
- Features
- Low-voltage detect (LVD) system
- I/O retention
- Memory map and register descriptions
  - PMC
Chapter 15: Low-Leakage Wakeup Unit (LLWU)
- Introduction
- LLWU signal descriptions
- Memory map/register definition
  - LLWU
- Functional description
Chapter 16: Reset Control Module (RCM)
- Introduction
- Reset memory map and register descriptions
  - RCM
Chapter 17: Bit Manipulation Engine (BME)
- Introduction
- External Signal Description
- Memory Map and Register Definition
- Functional Description
- Application Information
Chapter 18: Miscellaneous Control Module (MCM)
- Introduction
  - Features
- Memory map/register descriptions
  - MCM
Chapter 19: Micro Trace Buffer (MTB)
- Introduction
- External Signal Description
- Memory Map and Register Definition
Chapter 20: Crossbar Switch Lite (AXBS-Lite)
- Introduction
  - Features
- Memory Map / Register Definition
- Functional Description
  - General operation
  - Arbitration
- Initialization/application information
Chapter 21: Peripheral Bridge (AIPS-Lite)
- Introduction
  - Features
  - General operation
- Functional description
  - Access support
Chapter 22: Direct Memory Access Multiplexer (DMAMUX)
- Introduction
- External signal description
- Memory map/register definition
  - DMAMUXx
    - DMAMUXx_CHCFGn
- Functional description
- Initialization/application information
  - Reset
  - Enabling and configuring sources
Chapter 23: DMA Controller Module
- Introduction
  - Overview
  - Features
- DMA Transfer Overview
- Memory Map and Registers
  - DMA
- Functional Description
Chapter 24: Multipurpose Clock Generator (MCG)
- Introduction
  - Features
  - Modes of Operation
- External Signal Description
- Memory Map/Register Definition
  - MCG
- Functional Description
- Initialization / Application information
Chapter 25: Oscillator (OSC)
- Introduction
- Features and Modes
- Block Diagram
- OSC Signal Descriptions
- External Crystal / Resonator Connections
- External Clock Connections
- Memory Map/Register Definitions
- Functional Description
- Reset
- Low Power Modes Operation
- Interrupts
Chapter 26: Flash Memory Controller (FMC)
- Introduction
  - Overview
  - Features
- Modes of operation
- External signal description
- Memory map and register descriptions
- Functional description
Chapter 27: Flash Memory Module (FTFA)
- Introduction
- External Signal Description
- Memory Map and Registers
- Functional Description
Chapter 28: Analog-to-Digital Converter (ADC)
- Introduction
  - Features
  - Block diagram
- ADC Signal Descriptions
- Register definition
  - ADCx
- Functional description
- Initialization information
  - ADC module initialization example
    - Initialization sequence
    - Pseudo-code example
- Application information
  - External pins and routing
  - Sources of error
Chapter 29: Comparator (CMP)
- Introduction
- CMP features
- 6-bit DAC key features
- ANMUX key features
- CMP, DAC and ANMUX diagram
- CMP block diagram
- Memory map/register definitions
  - CMPx
- Functional description
- CMP interrupts
- DMA support
- CMP Asyncrhonous DMA support
- Digital-to-analog converter
- DAC functional description
  - Voltage reference source select
- DAC resets
- DAC clocks
- DAC interrupts
- CMP Trigger Mode
Chapter 30: 12-bit Digital-to-Analog Converter (DAC)
- Introduction
- Features
- Block diagram
- Memory map/register definition
  - DACx
- Functional description
Chapter 31: Timer/PWM Module (TPM)
- Introduction
- TPM Signal Descriptions
  - TPM_EXTCLK — TPM External Clock
  - TPM_CHn — TPM Channel (n) I/O Pin
- Memory Map and Register Definition
  - TPMx
- Functional Description
Chapter 32: Periodic Interrupt Timer (PIT)
- Introduction
  - Block diagram
  - Features
- Signal description
- Memory map/register description
  - PIT
- Functional description
- Initialization and application information
- Example configuration for chained timers
- Example configuration for the lifetime timer
Chapter 33: Low-Power Timer (LPTMR)
- Introduction
  - Features
  - Modes of operation
- LPTMR signal descriptions
  - Detailed signal descriptions
- Memory map and register definition
  - LPTMRx
- Functional description
Chapter 34: Real Time Clock (RTC)
- Introduction
- Register definition
  - RTC
- Functional description
Chapter 35: Universal Serial Bus OTG Controller (USBOTG)
- Introduction
- Functional description
  - Data Structures
- Programmers interface
- Memory map/Register definitions
  - USBx
- OTG and Host mode operation
- Host Mode Operation Examples
- On-The-Go operation
  - OTG dual role A device operation
  - OTG dual role B device operation
Chapter 36: USB Voltage Regulator
- Introduction
- USB Voltage Regulator Module Signal Descriptions
Chapter 37: Serial Peripheral Interface (SPI)
- Introduction
- External Signal Description
- Memory Map and Register Descriptions
  - SPI0
- Functional Description
- Initialization/Application Information
  - Initialization Sequence
  - Pseudo-Code Example
Chapter 38: Inter-Integrated Circuit (I2C)
- Introduction
- I2C signal descriptions
- Memory map and register descriptions
  - I2Cx
- Functional description
- Initialization/application information
Chapter 39: Universal Asynchronous Receiver/Transmitter (UART0)
- Introduction
- Register definition
  - UARTx
- Functional description
Chapter 40: Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
- Introduction
- Register definition
  - UARTx
- Functional description
Chapter 41: General-Purpose Input/Output (GPIO)
- Introduction
- Memory map and register definition
  - GPIOx
- FGPIO memory map and register definition
  - FGPIOx
- Functional description
Chapter 42: Touch Sensing Input (TSI)
- Introduction
- External signal description
  - TSI[15:0]
- Register definition
  - TSIx
- Functional description
Revision History of this Document
- Appendix A Revision History of this Document

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