Kinetis KL25: 48MHz Cortex M0+ 32 128KB Flash 80 Pin KL25Z Reference Manual
User Manual:
Open the PDF directly: View PDF
Page Count: 807 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- Chapter 1: About This Document
- Chapter 2: Introduction
- Chapter 3: Chip Configuration
- Introduction
- Module to Module Interconnects
- Core Modules
- System Modules
- SIM Configuration
- System Mode Controller (SMC) Configuration
- PMC Configuration
- Low-Leakage Wake-up Unit (LLWU) Configuration
- MCM Configuration
- Crossbar-Light Switch Configuration
- Peripheral Bridge Configuration
- DMA request multiplexer configuration
- DMA Controller Configuration
- Computer Operating Properly (COP) Watchdog Configuration
- Clock Modules
- Memories and Memory Interfaces
- Analog
- Timers
- Communication interfaces
- Human-machine interfaces (HMI)
- Chapter 4: Memory Map
- Chapter 5: Clock Distribution
- Chapter 6: Reset and Boot
- Introduction
- Reset
- Power-on reset (POR)
- System reset sources
- External pin reset (RESET)
- Low-voltage detect (LVD)
- Computer operating properly (COP) watchdog timer
- Low leakage wakeup (LLWU)
- Multipurpose clock generator loss-of-clock (LOC)
- MCG loss-of-lock (LOL) reset
- Stop mode acknowledge error (SACKERR)
- Software reset (SW)
- Lockup reset (LOCKUP)
- MDM-AP system reset request
- MCU Resets
- Reset Pin
- Debug resets
- Boot
- Chapter 7: Power Management
- Chapter 8: Security
- Chapter 9: Debug
- Chapter 10: Signal Multiplexing and Signal Descriptions
- Chapter 11: Port control and interrupts (PORT)
- Chapter 12: System integration module (SIM)
- Chapter 13: System Mode Controller (SMC)
- Chapter 14: Power Management Controller (PMC)
- Chapter 15: Low-Leakage Wakeup Unit (LLWU)
- Chapter 16: Reset Control Module (RCM)
- Chapter 17: Bit Manipulation Engine (BME)
- Chapter 18: Miscellaneous Control Module (MCM)
- Chapter 19: Micro Trace Buffer (MTB)
- Chapter 20: Crossbar Switch Lite (AXBS-Lite)
- Chapter 21: Peripheral Bridge (AIPS-Lite)
- Chapter 22: Direct Memory Access Multiplexer (DMAMUX)
- Chapter 23: DMA Controller Module
- Chapter 24: Multipurpose Clock Generator (MCG)
- Chapter 25: Oscillator (OSC)
- Chapter 26: Flash Memory Controller (FMC)
- Chapter 27: Flash Memory Module (FTFA)
- Introduction
- External Signal Description
- Memory Map and Registers
- Functional Description
- Flash Protection
- Interrupts
- Flash Operation in Low-Power Modes
- Functional Modes of Operation
- Flash Reads and Ignored Writes
- Read While Write (RWW)
- Flash Program and Erase
- Flash Command Operations
- Margin Read Commands
- Flash Command Description
- Security
- Reset Sequence
- Chapter 28: Analog-to-Digital Converter (ADC)
- Introduction
- ADC Signal Descriptions
- Register definition
- Functional description
- Initialization information
- Application information
- Chapter 29: Comparator (CMP)
- Introduction
- CMP features
- 6-bit DAC key features
- ANMUX key features
- CMP, DAC and ANMUX diagram
- CMP block diagram
- Memory map/register definitions
- Functional description
- CMP interrupts
- DMA support
- CMP Asyncrhonous DMA support
- Digital-to-analog converter
- DAC functional description
- DAC resets
- DAC clocks
- DAC interrupts
- CMP Trigger Mode
- Chapter 30: 12-bit Digital-to-Analog Converter (DAC)
- Chapter 31: Timer/PWM Module (TPM)
- Chapter 32: Periodic Interrupt Timer (PIT)
- Chapter 33: Low-Power Timer (LPTMR)
- Chapter 34: Real Time Clock (RTC)
- Chapter 35: Universal Serial Bus OTG Controller (USBOTG)
- Introduction
- Functional description
- Programmers interface
- Memory map/Register definitions
- USBx
- USBx_PERID
- USBx_IDCOMP
- USBx_REV
- USBx_ADDINFO
- USBx_OTGISTAT
- USBx_OTGICR
- USBx_OTGSTAT
- USBx_OTGCTL
- USBx_ISTAT
- USBx_INTEN
- USBx_ERRSTAT
- USBx_ERREN
- USBx_STAT
- USBx_CTL
- USBx_ADDR
- USBx_BDTPAGE1
- USBx_FRMNUML
- USBx_FRMNUMH
- USBx_TOKEN
- USBx_SOFTHLD
- USBx_BDTPAGE2
- USBx_BDTPAGE3
- USBx_ENDPTn
- USBx_USBCTRL
- USBx_OBSERVE
- USBx_CONTROL
- USBx_USBTRC0
- USBx_USBFRMADJUST
- USBx
- OTG and Host mode operation
- Host Mode Operation Examples
- On-The-Go operation
- Chapter 36: USB Voltage Regulator
- Chapter 37: Serial Peripheral Interface (SPI)
- Chapter 38: Inter-Integrated Circuit (I2C)
- Chapter 39: Universal Asynchronous Receiver/Transmitter (UART0)
- Chapter 40: Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
- Chapter 41: General-Purpose Input/Output (GPIO)
- Chapter 42: Touch Sensing Input (TSI)
- Introduction
- External signal description
- Register definition
- Functional description
- Revision History of this Document