LA 4051P
User Manual:
Open the PDF directly: View PDF 
.
Page Count: 63
| Download | |
| Open PDF In Browser | View PDF |
A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : JAL21/22
PCB NO : LA-4051P (DAA00000R1L)
BOM P/N : 43153431L01 (Avia TPM)
43153431L02 (Avia Non TPM)
43153431L11(DSC TPM)
43153431L12 (DSC Non TPM)
1
M09 Avia / Maybach DIS
uFCPGA Mobile Penryn
Intel Cantiga PM + ICH9M
2
2
2008-06-16
REV : 1.0 (A00)
@ : Nopop Component
3
3
1@ : for Avia / JAL22 (NB9P) Component
2@ : for MayDSC / JAL21 (NB9M) Component
3@ : Disable TPM
4@ : Enable TPM
Fix Function Field
4
4
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number
DAA00000R1L
Description
Compal Electronics, Inc.
PCB 03P LA-4051P REV1 M/B
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
A
B
C
D
Title
Cover Sheet
Size
Document Number
Date:
Monday, June 16, 2008
Rev
1.0
LA-4051P
Sheet
E
1
of
63
A
B
Block Diagram
Compal confidential
Model : JAL21/22
FAN
C
Pentium-M
Penryn -4MB (Socket P)
+1.5V_RUN
uFCPGA CPU
Thermal
GUARDIAN III
EMC4002
+FAN1_VOUT
page 18
+3.3V_M
E
Clock Generator
CK505
SLG8LP554
CPU ITP Port
+1.05V_VCCP
page 18
+VCC_CORE
1
D
+1.05V_VCCP
+3.3V_M
page 7
page6
page 7,8,9
478pin
CRT CONN
+5V_RUN
1
page 20
Video Switch
TS3DV520
VGA
H_A#(3..35)
VGA
NV G98
+3.3V_RUN page 20
+3.3V_RUN
PCIE-E 16X
page 16,17
+1.5V_RUN
page 51,52,53,54,55,56
DPC
+1.8V_MEM
+1.8V_MEM 667/800 MHz
1329pin BGA
+1.8V_MEM
page 19
+0.9V_DDR_VTT
Memory BUS (DDR2)
Cantiga
+GPU_CORE
on M/B Board
+LCDVDD
+INV_PWR_SRC
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
INTEL
+1.1V_GFX_PCIE
LVDS
DDRII-DIMM X2
FSB 1066 MHz
+FBVDDQ
+3.3V_RUN
LVDS CONN
+5V_ALW
H_D#(0..63)
System Bus
+1.05V_VCCP
Trough LVDS Cable
USB Port
Camera
USB[11]
+3.3V_RUN
Repeater
DMI
page 21
PCI BUS
2
CardBus
R5C847
page 35
+3.3V_RUN
DAI
SNIFFER
IEEE1394
page 31
SD CONN
+3.3V_RUN_CARD
page 31
SATA3
USB[7]
Through CABLE to SD Board
+RTC_CELL
USB[0,1] RIGHT SIDE
On IO/B
676pin BGA
+3.3V_ALW_ICH
Intel Boazman
82567LM
S-ATA(4)
PCIE2
Mini Card 3
WPAN/BT/Robson
SIM card
+3.3V_RUN
+1.5V_RUN page 34
USB[4]
+1V_LAN_M
SATA0
E-Module
page 29
LPC BUS
+5V_HDD
Azalia Codec
92HD71B
page 26
AMP & INT.
Speaker
+3.3V_RUN
+VDDA
page 27
+5V_RUN
TPM 1.2 USB[10]
Dig. MIC
32Mbit
page 19
MEC5035
+RTC_CELL
+3.3V_ALW
DAI
SSM2602
page 38
73S8009CN
3V/5V
page 44
+3.3V_RUN page 27
MDC
+3.3V_RUN
page 36
1.5V/1.05V
page 41
page 45
+3.3V_SUS
LED
USBH
GPUCORE / 1.1V
3
On IO/B
Trough LVDS Cable
W25X32VSSIG
SMSC KBC
RJ45
page 33
page 28
+3.3V_LAN
page 24
+3.3V_RUN
+2.5V_AVDD_5880
+1.2V_AVDD_5880
page 36
page 43
+3.3V_RUN
SPI
USH I/F
BCM5880
page 36
S-HDD
+5V_MOD
page 26
+3.3V_RUN
33MHz
page 34
USB[5]
RFID
DC IN
BATT IN
LPC BUS
Mini Card 1
WWAN
+3.3V_WLAN
+1.5V_RUN page 34
USB[6]
+3.3V_LAN
page 30
+1.8V_LAN_M
page 22,23,24,25
PCIE1
Mini Card 2
WLAN
+3.3V_RUN
+1.5V_RUN page 34
LAN Switch
P13L500
+3.3V_ALW
SATA1
PCIE3
page 33
Azalia I/F
+3.3V_RUN
2
USB Ports X2
+5V_ALW
GLCI/LCI
+1.05V_VCCP
PCI Express BUS
DOCK LPC BUS
48MHz
+1.5V_RUN
Through CABLE to IO Board
USB[8,9]
3
+5V_RUN
SATA4
Charger USB Port X1
+5V_ALW
page 33
INTEL
ICH9-M
+5V_ALW
page 31,32
E-SATA
USB Port1 X1
USB[2,3] LEFT SIDE
DP CONN
+3.3V_RUN
page 21
+DOCK_PWR_BAR
SATA4
+1.5V_RUN
100MHz
IDSEL:AD17
(GNT#1,REQ#1)
(PIRQD#,PIRQB#,PIRQC#)
DOCKING
PORT
+LOM_VCT
+3.3VRUN 33MHz
page 19
page 10,11,12,13,14,15
DPB
TS2DP512
+5V_RUN
+5V_RUN
+1.05V_M
DP Switch
page 42
Smart Card
page 33
SMBus
DOCKING
HeadPhone &
MIC Jack
+3.3V_RUN page 33
BC
On IO/B
page 36
4
4
Selector
1.8V/0.9V
page 40
page 46
CHARGER
Biometric
+3.3V_RUN page 33
ECE1077
+3.3V_ALW
RJ11
Touch Pad
page 39
BC BUS
VCORE (IMVP-6)
page 48
page 47
http://hobi-elektronika.net
A
Trough Cable
B
Int.KBD &
Stick page
39
SMSC SIO
ECE5028
DELL CONFIDENTIAL/PROPRIETARY
DOCK LPC BUS
Compal Electronics, Inc.
Title
Block Diagram
+3.3V_ALW
page 37
Stick
Through Cable
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
C
D
Sheet
E
2
of
63
5
4
3
2
POWER STATES
USB PORT#
Signal
State
D
C
1
S0 (Full ON) / M0
SLP
S3#
SLP
S4#
SLP
S5#
S4
STATE#
SLP
M#
ALWAYS
PLANE
HIGH
HIGH
HIGH
HIGH
HIGH
ON
M
PLANE
SUS
PLANE
RUN
PLANE
ON
ON
ON
CLOCKS
DESTINATION
0
JUSB1 (Ext Right Side Top)
ON
1
JUSB1 (Ext Right Side Bottom)
JESA1 (Ext Left Side Bottom)
S3 (Suspend to RAM) / M1
LOW
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
OFF
ON
2
S4 (Suspend to DISK) / M1
LOW
HIGH
HIGH
LOW
HIGH
ON
ON
ON
OFF
ON
3
JESA1 (Ext Left Side TOP)
S5 (SOFT OFF) / M1
LOW
HIGH
LOW
LOW
HIGH
ON
ON
ON
OFF
ON
4
WLAN
S3 (Suspend to RAM) / M-OFF
LOW
HIGH
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
5
WWAN
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
LOW
ON
OFF
OFF
OFF
OFF
6
WPAN
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
7
Card Bus/Express card
8
DOCKING
9
DOCKING
10
USH->BIO
11
Camera
ICH9-M
PM TABLE
power
plane
+15V_ALW
+3.3V_SUS
+5V_RUN
+3.3V_M
+5V_ALW
+1.8V_MEM
+3.3V_RUN
+1.05V_M +1.05V_M
+3.3V_ALW_ICH
+2.5V_RUN
+3.3V_RTC_LDO
+1.5V_RUN
+3.3V_M
(M-OFF)
D
C
+0.9V_DDR_VTT
+GPU_CORE
+VCC_CORE
PCI EXPRESS
+1.05V_VCCP
State
+FBVDDQ
+1.1V_GFX_PCIE
B
DESTINATION
Lane 1
MINI CARD-1 WWAN
S0
ON
ON
ON
ON
ON
Lane 2
MINI CARD-2 WLAN
S3
ON
ON
OFF
ON
OFF
Lane 3
MINI CARD-3 BT/UWB
S5 S4/AC
ON
OFF
OFF
ON
OFF
Lane 4
EXPRESS CARD
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
Lane 5
None
Lane 6
10/100/1G LAN
B
PCI TABLE
PCI DEVICE
IDSEL
REQ#/GNT#
PIRQ
R5C847
AD17
REQ#1 / GNT#1
PIRQ[B..D]
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Index and Config.
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
3
of
63
5
4
RUN_ON
3
SI3457
( Q17 )
2
1
+INV_PWR_SRC
ADAPTER
D
GFX_CORE_CNTRL
D
MAX17007
(PU13)
+GPU_COREP
+PWR_SRC
BATTERY
CHARGER
ISL6260
(PU7)
SN0608098
(PU3)
TPS51116
(PU4)
SN0608098
(PU2)
ALWON
C
C
+VCC_CORE
+1.8V_MEM
+1.05V_M
STS11NF30L
(Q116)
RUN_ON
MODC_EN
HDDC_EN
SI3456BDV
(Q29)
MAX9789A
(U22)
+5V_HDD
+5V_MOD
+VDDA
1.05V_RUN_ON
+5V_ALW
GFX_CORE_PWRGD
+5V_RUN
B
SI3456BDV
(Q32)
SI4336DY
(Q61)
+3.3V_LAN
+3.3V_RUN
SI4336DY
(Q67)
M_ON
STS11NF30L
SI3456BDV
SI3456BDV
(Q60)
(Q54)
(Q66)
+3.3V_SUS
+3.3V_ALW_ICH
+3.3V_M
B
EMC4002
LDO Out
(U3)
BCP69
(Q45)
+FBVDDQ
ICH_ALW_ON
SUS_ON
+1.5V_RUN
STS11NF30L
(Q44)
RUN_ON
STS11NF30L
(Q55)
3.3V_RUN_ON
1.5V_RUN_ON
M_ON
+0.9V_DDR_VTT
REGCTL_PNP18
+15V_ALW
ENAB_3VLAN
SN0608098
(PU2)
0.9V_DDR_VTT_ON
ALW_ON
DDR_ON
IMVP_VR_ON
+3.3V_ALW
+1.05V_VCCP
+1.8V_LAN_M
A
+1.8V_RUN
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Power Rail
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
4
of
63
5
4
3
+3.3V_ALW_ICH
2.2K
G16
ICH_SMBCLK
A13
ICH_SMBDATA
2
1
2.2K
2.2K
2N7002
+3.3V_M
2.2K
MEM_SCLK
197
MEM_SDATA
195
DIMMA
SMBUS Address [TBD]
DIMMB
SMBUS Address [TBD]
2N7002
10K
ICH9-M
197
D
+3.3V_ALW_ICH
10K
C17
AMT_SMBCLK
B18
AMT_SMBDAT
195
D
2.2K
93
2A
94
+5V_ALW
2.2K
2A
6
DOCK_SMB_CLK
5
DOCK_SMB_DAT
1A
6
5
DOCKING
SMBUS Address [TBD]
1A
2.2K
+3.3V_ALW
2.2K
8
LCD_SMBCLK
6
7
LCD_SMDATA
5
1B
C
1B
INVERTER
(JLVDS)
C
SMBUS Address [TBD]
2.2K
+3.3V_ALW
2.2K
SIO
1C
112
PBAT_SMBCLK
1C
111
PBAT_SMBDAT
100 ohm
100 ohm
3
4
BATTERY
CONN
SMBUS Address [TBD]
2.2K
2.2K
+3.3V_SUS
10
1D
9
2N7002
1D
EXP_SMBCLK
7
EXP_SMBDATA
8
Express card
SMBUS Address [TBD]
2N7002
100
2.2K
1E
99
2.2K
1E
B
1F
1F
98
97
CARD_SMBCLK
2N7002
CARD_SMBDAT
WLAN_SMBCLK
30
WLAN_SMBDATA
32
2N7002
2.2K
96
2N7002
95
2N7002
1H
32
2.2K
B
WLAN
SMBUS Address [TBD]
2.2K
MEC 5035
1G
+3.3V_WLAN
+3.3V_RUN
MINI_SMBCLK
30
MINI_SMBDATA
32
BT/UWB
SMBUS Address [TBD]
30
WWAN
SMBUS Address [TBD]
2.2K
2.2K
12
CKG_SMBDAT
13
CKG_SMBCLK
1H
+3.3V_ALW
2.2K
2N7002
1H
2N7002
+3.3V_M
CLK_SDATA
17
CLK_SCLK
16 CLK GEN
SMBUS Address [TBD]
9
A
106
10
105
Dedicated JTAG
Charger
1J
A
2N7002
1J
SMBUS Address [TBD]
USH
2N7002
SMBUS Address [TBD]
2.2K
DAI
SMBUS Address [TBD]
103
1K
102
1K
Dedicated JTAG
2.2K
Compal Electronics, Inc.
+3.3V_RUN
Title
SMBUS TOPOLOGY
http://hobi-elektronika.net
5
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
4
3
2
Sheet
1
5
of
63
4
3
+3.3V_M
2
0
266
100
33.3
0
0
1
133
100
33.3
0
1
0
200
100
33.3
0
1
1
166
100
33.3
2
1
2
2
0
1
@
2
1
R10
1
2
SATA_CLKREQ#
MINI3CLK_REQ#
EXPCLK_REQ#
1
2
X1
14.31818MHz_20P_1BX14318CC1A~D
2
1
C16
33P_0402_50V8J~D
1
R12
1
R14
2 +CK_VDD_REF
0_0603_5%~D
2 +CK_VDD_48
0_0603_5%~D
1
49
54
65
VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC
30
36
VDD_PCI
VDD_PCI
12
VDD_CPU
18
VDD_REF
40
VDD_48
0
333
100
33.3
1
0
1
100
100
33.3
1
1
0
400
100
33.3
VDD_A
7
SLG8LP554VTR VSS_A
8
C17
33P_0402_50V8J~D
2
1
CLK_XTAL_OUT
19
XTAL_OUT
<24> CLK_ICH_48M
<8,10> CPU_MCH_BSEL0
<8,10> CPU_MCH_BSEL1
1 39_0402_5%~D
2 2.2K_0402_5%~D
2 0_0402_5%~D
FSA
41
USB_48MHz/FSLA
45
FSL_B/TEST_MODE
<8,10> CPU_MCH_BSEL2
CPU_MCH_BSEL2
R24
2 10K_0402_5%~D
FSC
<37> CLK_PCI_5028
1
<36> CLK_PCI_TPM
<31> CLK_PCI_PCM
<35> CLK_PCI_DOCK
<38> CLK_PCI_5035
1
<24> CLK_ICH_14M
<37> CLK_SIO_14M
<51> CLK_NV_27M
2
<51> CLK_NVSS_27M
<22> CLK_PCI_ICH
B
1
1
2
0_0402_5%~D
FSB
23
R26
2
1 39_0402_5%~D
PCI_SIO
34
PCICLK4/FCT_SEL
CLK_PCI_TPM
R29
2
1 39_0402_5%~D
PCI_TPM
33
PCICLK3
CLK_PCI_PCM
CLK_PCI_DOCK
CLK_PCI_5035
R30
R27
R32
2
1
2
1 22_0402_5%~D
2 22_0402_5%~D
1 39_0402_5%~D
PCI_DOCK
PCI_EC
32
PCICLK2/TME
27
PCICLK1
CLK_ICH_14M
CLK_SIO_14M
R33
R35
1
1
2 22_0402_5%~D
2 22_0402_5%~D
CLKREF
CLK_NV_27M
R37
2
1 33_0402_5%~D
CLK_NV
43
DOT_96/27M
CLK_NVSS_27M
R38
1
2 33_0402_5%~D
CLK_NVSS
44
DOT_96#/27M_SS
CLK_PCI_ICH
R41
2
1 33_0402_5%~D
PCI_ICH
37
22
39
9
TME
PCI_DOCK
*
PIN 32
0
overclocking enabled
1
overclocling disabled
CLK_SCLK
+3.3V_RUN
16
CLK_SDATA
R46
10K_0402_5%~D
ITP_EN
PCI_ICH
*
Pin 5/6 as SRC_10
1
Pin 5/6 as CPU_ITP
2
1
1
R54
10K_0402_5%~D
2
R50
10K_0402_5%~D
FCTSEL1
@
*
PIN43
PIN44
PIN47
PIN48
0=UMA
DOT96T
DOT96C
96/100M_T
96/100M_C
1=DIS
27M_out
27M SSout
SRCT0
SRCC0
H_STP_PCI#
24
H_STP_CPU#
CPU_1
11
MCH_BCLK
CPU_1#
10
MCH_BCLK#
CPU_0
14
CPU_BCLK
CPU_0#
13
CPU_BCLK#
CPU_ITP/SRC_10
6
CPU_ITP
CPU_ITP#/SRC_10#
5
CPU_ITP#
SRC_9
3
PCIE_MINI1
SRC_9#
2
PCIE_MINI1#
CLKREQ_9#
72
MINI1CLK_REQ#
SRC_8
70
PCIE_MINI2
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
D
SRC_8#
69
PCIE_MINI2#
71
MINI2CLK_REQ#
SRC_7
66
PCIE_ICH
SRC_7#
67
PCIE_ICH#
CLKREQ_7#
38
REF_1
SRC_6
63
PCIE_MINI3
SRC_6#
64
PCIE_MINI3#
CLKREQ_6#
62
MINI3CLK_REQ#
SRC_5
60
PCIE_VGA
PCIE_VGA#
PCICLK_F0/ITP_EN
CKPWRGD/PD#
SRC_5#
61
CLKREQ_5#
29
NC
SRC_4
58
PCIE_EXP
SRC_4#
59
PCIE_EXP#
CLKREQ_4#
57
EXPCLK_REQ#
SRC_3
55
MCH_3GPLL
56
SMBCLK
SMBDAT
VSS_SRC
SRC_3#
15
VSS_CPU
CLKREQ_3#
28
21
VSS_REF
SRC_2
52
31
VSS_PCI
SRC_2#
53
35
VSS_PCI
CLKREQ_2#
26
42
VSS_48
68
VSS_SRC
73
THRM_PAD
LCD_CLK#/SRC_0#
CLK_CPU_BCLK
2
33_0402_5%~D
CLK_CPU_BCLK#
2
33_0402_5%~D
@
@
CLK_MCH_BCLK# <10>
C
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP
2
33_0402_5%~D
CLK_CPU_ITP#
2
33_0402_5%~D
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
1
R23
1
R25
CLK_PCIE_MINI1
2
33_0402_5%~D
CLK_PCIE_MINI1#
2
33_0402_5%~D
1
R28
1
R31
CLK_PCIE_MINI2
2
33_0402_5%~D
CLK_PCIE_MINI2#
2
33_0402_5%~D
1
R34
1
R36
CLK_PCIE_ICH
2
33_0402_5%~D
CLK_PCIE_ICH#
2
33_0402_5%~D
1
R39
1
R40
CLK_PCIE_MINI3
2
33_0402_5%~D
CLK_PCIE_MINI3#
2
33_0402_5%~D
1
R42
1
R44
CLK_PCIE_VGA
2
33_0402_5%~D
CLK_PCIE_VGA#
2
33_0402_5%~D
1
R408
1
R415
CLK_PCIE_EXP
2
33_0402_5%~D
CLK_PCIE_EXP#
2
33_0402_5%~D
CLK_PCIE_MINI1 <34>
CLK_PCIE_MINI1# <34>
MINI1CLK_REQ# <34>
CLK_PCIE_MINI2 <34>
CLK_PCIE_MINI2# <34>
MINI2CLK_REQ# <34>
CLK_PCIE_ICH
CLK_PCIE_ICH#
<24>
<24>
CLK_PCIE_MINI3 <34>
CLK_PCIE_MINI3# <34>
B
MINI3CLK_REQ# <34>
CLK_PCIE_VGA <51>
CLK_PCIE_VGA# <51>
CLK_PCIE_EXP <32>
CLK_PCIE_EXP# <32>
EXPCLK_REQ# <32>
CLK_PCIE_SATA# <23>
PCIE_SATA#
48
1
R15
1
R16
CLK_MCH_BCLK <10>
CLK_PCIE_SATA
2
33_0402_5%~D
CLK_PCIE_SATA#
2
33_0402_5%~D
2
475_0402_1%~D
PCIE_SATA
51
47
CLK_MCH_BCLK
2
33_0402_5%~D
CLK_MCH_BCLK#
2
33_0402_5%~D
CLK_MCH_3GPLL# <10>
50
46
H_STP_CPU# <24>
1
R11
1
R13
CLK_MCH_3GPLL
2
33_0402_5%~D
CLK_MCH_3GPLL#
2
33_0402_5%~D
CLK_3GPLLREQ#
2
475_0402_1%~D
SRC_1/SATA
CLKREQ_1#
2
1
R45
MCH_3GPLL#
1
R47
CLK_3GPLLREQ#_R 1
R48
SRC_1#/SATA#
LCD_CLK/SRC_0
1
H_STP_PCI# <24>
1
R18
1
R21
CLKREQ_8#
4
PIN 37
0
+3.3V_RUN
PCI_SIO
17
25
REF_0/FSL_C/TEST_SEL
CLK_PCI_5028
CLK_PWRGD
<24> CLK_PWRGD
R43
10K_0402_5%~D
2
+3.3V_RUN
2
1
FSA
@ R55
@R55
10K_0402_5%~D
1
R17
PCI_STP#
CPU_STP#
XTAL_IN
R19 2
R22 1
R1038 1
@ R51
@R51
10K_0402_5%~D
A
20
CLK_ICH_48M
CPU_MCH_BSEL0
CPU_MCH_BSEL1
+3.3V_M
2
CLK_XTAL_IN
Place crystal within
500 mils of CK505
1
R4
1
R5
1
R6
1
R7
1
R8
1
R356
+CK_VDD_A
2
2.2_0603_5%~D
2
0
MINI1CLK_REQ#
CLK_3GPLLREQ#
C
1
+3.3V_RUN
U1
1
5
0
2
C15
0.047U_0402_16V4Z~D
PCI
MHz
1
C14
4.7U_0603_6.3V4Z~D
SRC
MHz
2
C7
0.1U_0402_16V4Z~D
*
CPU
MHz
1
C6
0.1U_0402_16V4Z~D
FSA
2
2
C5
0.1U_0402_16V4Z~D
FSB
1
1
C10
0.1U_0402_16V4Z~D
FSC
CLKSEL2 CLKSEL1 CLKSEL0
2
2
C13
0.047U_0402_16V7K~D
2
1
@
1
+CK_VDD_REF
C12
0.047U_0402_16V4Z~D
1
C11
4.7U_0603_6.3V4Z~D
1
2
@R9
@R9
0_0402_5%~D
2
C4
0.1U_0402_16V4Z~D
+CK_VDD_48
1
C9
0.1U_0402_16V4Z~D
<27,38,48> CKG_SMBCLK
CLK_SCLK
2
C8
10U_0805_10V4Z~D
3
Q1B
2N7002DW-T/R7_SOT363-6~D
4
1
MINI2CLK_REQ#
1
2
@ L2
@L2
BLM21PG600SN1D_0805~D
+3.3V_M
D
+CK_VDD_MAIN2
2
C3
0.1U_0402_16V4Z~D
CLK_SDATA
Q1A
2N7002DW-T/R7_SOT363-6~D
1
+CK_VDD_MAIN
1
C2
10U_0805_10V4Z~D
2
1
2
+CK_VDD_MAIN
R851
0_0805_5%~D
1
1
C1
0.1U_0402_16V4Z~D
6
<27,38,48> CKG_SMBDAT
R2
2.2K_0402_5%~D
1
2
@ R3
@R3
0_0402_5%~D
R1
2.2K_0402_5%~D
1
+3.3V_M
L1
BK2125HS601-T 0805 ~D
2
1
5
1
R49
1
R52
SATA_CLKREQ#_R
1
R53
CLK_MCH_3GPLL <10>
CLK_3GPLLREQ# <10>
CLK_PCIE_SATA <23>
SATA_CLKREQ# <24>
A
DELL CONFIDENTIAL/PROPRIETARY
SLG8LP554VTR_QFN72_10X10~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
0=UMA
1=Disc. GRFX down
http://hobi-elektronika.net
5
4
3
2
Title
Clock Generator
Size
Document Number
Date:
Friday, June 13, 2008
Rev
1.0
LA-4051P
Sheet
1
6
of
63
5
4
3
2
1
+1.05V_VCCP
Place near JITP
H_STPCLK#
H_INTR
H_NMI
H_SMI#
H_A20M#
H_FERR#
H_IGNNE#
A6
A5
C4
A20M#
FERR#
IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
ITP_BPM2#1
ITP_BPM2#0
M4
N5
T2
V3
B2
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
ITP_BPM2#2
+V_CPU_GTLREF_2
1@ R984
51_0402_5%~D
1
2
+1.05V_VCCP
LOCK#
H4
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
HIT#
HITM#
G6
E4
H_HIT#
H_HITM#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
CONTROL
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
H_BR0# <10>
2
R56
H_INIT# <23>
1
+1.05V_VCCP
56_0402_5%~D
H_LOCK# <10>
H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>
H_RESET#
H_HIT# <10>
H_HITM# <10>
R1015 1
@
2
0_0402_5%~D
BPM#0
ITP_BPM#1
R1016 1
@
2
0_0402_5%~D
BPM#1
ITP_BPM#2
R1017 1
@
2
0_0402_5%~D
BPM#2
ITP_BPM#3
R1018 1
@
2
0_0402_5%~D
BPM#3
ITP_BPM#4
R1019 1
@
2
0_0402_5%~D
BPM#4
ITP_BPM#5
R1020 1
@
2
1
2
R57 @ 124_0402_5%~D
0_0402_5%~D
BPM#5
<6> CLK_CPU_ITP
<6> CLK_CPU_ITP#
1
2
R989 @ 22.6_0402_1%~D
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TCK
+1.05V_VCCP
Depop R57 & R989
for Enhance ESD on dock issue
ITP_TRST#
ITP_TMS
ITP_TDI
29
@
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
JCPU1D
MOLEX_52435-2891_28P~D
R59
56_0402_5%~D
ITP_DBRESET# <24>
EC_CPU_PROCHOT#
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
D21
A24
B25
C7
H_THERMDA
2
H_THERMDA <18>
@ C18
100P_0402_50V8K~D
BCLK[0]
BCLK[1]
A22
A21
width / Spacing = 10 / 10 mil
1
H_THERMDC
H_THERMDC <18>
H_THERMTRIP#
H CLK
H_THERMTRIP# <18>
CLK_CPU_BCLK
CLK_CPU_BCLK#
QUAD_REF_CTRL
CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>
@
ITP_BPM#0
+1.05V_VCCP
ITP_BPM#1
@
TYCO_1-1674770-2_Penryn~D
R973
H_RESET#
51_0402_1%~D
1
R61
2 H_THERMTRIP#
56_0402_5%~D
+1.05V_VCCP
R785
51_0402_5%~D
1
2 ITP_BPM#5
B
ITP_DBRESET#
ITP_BPM#0
ITP_TDO
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND6
IERR#
INIT#
H_IERR#
H_INIT#
H_DEFER# <10>
H_DRDY# <10>
H_DBSY# <10>
JITP1
ESD Team
Command
Unstuff
GND7
H_BR0#
D20
B3
THERMAL
ICH
<23> H_A20M#
<23> H_FERR#
<23> H_IGNNE#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
ADDR GROUP_1
<10> H_ADSTB#1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
F1
BR0#
2
+1.05V_VCCP
30
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H_DEFER#
H_DRDY#
H_DBSY#
2
1
1
K3
H2
K2
J3
L1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
C
<23>
<23>
<23>
<23>
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H5
F21
E1
H_ADS# <10>
H_BNR# <10>
H_BPRI# <10>
2
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADS#
H_BNR#
H_BPRI#
DEFER#
DRDY#
DBSY#
XDP/ITP SIGNALS
<10>
<10>
<10>
<10>
<10>
H1
E2
G5
ADS#
BNR#
BPRI#
RESERVED
<10> H_ADSTB#0
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
ADDR GROUP_0
D
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
C20
0.1U_0402_16V4Z~D
JCPU1A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
C19
0.1U_0402_16V4Z~D
1
<10> H_A#[3..35]
ITP_BPM#2
ITP_BPM#3
R976
@
0_0402_5%~D
1
2 ITP_BPM2#0
@ R978
@
0_0402_5%~D
1
2 ITP_BPM2#1
@ R980
@
0_0402_5%~D
1
2 ITP_BPM2#2
@ R982
@
0_0402_5%~D
1
2 ITP_BPM2#3
QC:
ES1: POP ALL
ES2: POP 0 ohm ONLY
DC: DEPOP ALL
+1.05V_VCCP
R977
51_0402_1%~D
R979
51_0402_1%~D
R981
51_0402_1%~D
R983
51_0402_1%~D
Depop ALL for
Enhance ESD on dock issue
+3.3V_ALW_ICH
Place close to CPU within 200 mil
Pin D22
Dual Core: 0 V
Quad Core: 2/3 VTT
1
R60
ITP_DBRESET#
2
10K_0402_5%~D
Place close to JITP within 1ns = 5000 mil
+1.05V_VCCP
+1.05V_VCCP
+3.3V_RUN
1
+1.05V_VCCP
1
1@ R942
1K_0402_1%~D
+1.05V_VCCP
1@ R943
100K_0402_5%~D
R66
649_0402_5%~D
1
2
ITP_TMS
1
1@
R946
10K_0402_5%~D
C
3
50 ohm, 0.5 inch (max)
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
D
C
ITP_BPM2#3
B
TYCO_1-1674770-2_Penryn~D
ITP_TRST#
Place close to CPU within 200ps = 1000 mil
ITP_TCK
2
27_0402_5%
Place close to JITP within 200ps = 1000 mil
1@
E
Q14
2
2
B
MMST3904-7-F_SOT323-3~D
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
2
3
Layout close CPU PIN D22
ITP_TDO
R64
39_0402_5%~D
1
2
1
R67
R945
10K_0402_5%~D
1@
2
G
S
A
R62
51_0402_5%~D
1
2
2
1@ Q129
BSS138_SOT23~D
ITP_TDI
1
D
2
1@ R944
1.74K_0402_1%~D
1
1
2
+V_CPU_GTLREF_2
R65
150_0402_5%~D
1
2
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
1
QUAD_REF_CTRL
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Quad Core support circuit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Penryn Processor(1/2)
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
7
of
63
5
4
3
2
1
+VCC_CORE
+VCC_CORE
JCPU1C
D
<10> H_D#[0..63]
JCPU1B
TYCO_1-1674770-2_Penryn~D
1
2
1
H_DPRSTP# <10,23,47>
H_DPSLP# <23>
H_DPWR# <10>
H_PWRGOOD <23>
H_CPUSLP# <10>
H_PSI# <47>
2
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
1
E5
B5
D24
D6
D7
AE6
2
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
1
COMP0
COMP1
COMP2
COMP3
2
DATA GRP 2
R26
U26
AA1
Y1
R71
24.9_0402_1%~D
COMP[0]
COMP[1]
COMP[2]
COMP[3]
MISC
H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DINV#3 <10>
R70
49.9_0402_1%~D
2 0_0402_5%~D
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
R69
24.9_0402_1%~D
<6,10> CPU_MCH_BSEL1
R1040 1
PAD~D T153
AD26
C23
D25
C24
AF26
AF1
A26
C3
BSEL0 B22
BSEL1 B23
C21
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DINV#2 <10>
R68
49.9_0402_1%~D
<6,10> CPU_MCH_BSEL0
PAD~D T138
PAD~D T4
R1039 1
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
2 0_0402_5%~D
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DATA GRP 3
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA[01]
VCCA[02]
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
AF7
VCCSENSE
VSSSENSE
AE7
VSSSENSE
D
+1.05V_VCCP
1
+
2
C
CRB was 270uF
VID0
VID1
VID2
VID3
VID4
VID5
VID6
<47>
<47>
<47>
<47>
<47>
<47>
<47>
1
2
1
2
C23
10U_0805_10V4Z~D
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
C22
0.01U_0402_16V7K~D
+V_CPU_GTLREF
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
C21
220U_D2_4VY_R15M~D
<10> H_DSTBN#1
<10> H_DSTBP#1
<10> H_DINV#1
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 1
C
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP 0
<10> H_DSTBN#0
<10> H_DSTBP#0
<10> H_DINV#0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
+1.5V_RUN
VCCSENSE <47>
VSSSENSE <47>
TYCO_1-1674770-2_Penryn~D
<6,10> CPU_MCH_BSEL2
R1041 1
20_0402_5%~D BSEL2
Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 25 ohm. COMP1,
COMP3 should be 50 ohm.
(Quad Core design)
B
TEST1
TEST2
BCLK
533
133
166
BSEL2
0
0
BSEL1
BSEL0
0
1
1
R75
VCCSENSE
2
100_0402_1%~D
1
@R833
@
R833
1
R76
VSSSENSE
2
100_0402_1%~D
Reserve for testing
only
2
27.4_0402_1%~D
+1.05V_VCCP
1
1
+VCC_CORE
Dual Core Should follow Quad Core value
Avia should support Quad / Dual Core CPU
Route VCCSENSE and VSSSENSE trace at
27.4 ohms, 7 mils spacing and the placement should be within 1 inch (max)
R77
1K_0402_1%~D
+V_CPU_GTLREF
800
200
0
1
0
1067
266
0
0
0
1
2
667
Place R75 and R76 near CPU
TEST3
TEST5
For the purpose of testability, route these signals
through a ground referenced Z0 = 50ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
FSB
B
1
2
1
1
@R73
@
R73
1K_0402_5%~D
@R72
@
R72
1K_0402_5%~D
2
PAD~D T154
PAD~D T3
Length match within 25 mils, Z0=27.4 ohm
A
A
2
R78
2K_0402_1%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Layout close CPU PIN AD26
50 ohm, 0.5 inch (max)
http://hobi-elektronika.net
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Penryn Processor(2/2)
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
8
of
63
5
4
3
2
1
+VCC_CORE
D
Place these inside 1
socket cavity on L8
(North side
Secondary)
2
1
C24
10U_0805_4VAM~D
2
1
C25
10U_0805_4VAM~D
2
1
C26
10U_0805_4VAM~D
2
1
C27
10U_0805_4VAM~D
C28
10U_0805_4VAM~D
2
1
1
2
C29
10U_0805_4VAM~D
2
1
C30
10U_0805_4VAM~D
2
1
C31
10U_0805_4VAM~D
2
1
C32
10U_0805_4VAM~D
2
C33
10U_0805_4VAM~D
D
+VCC_CORE
Place these inside 1
socket cavity on L8
(Sorth side
Secondary)
2
1
C34
10U_0805_4VAM~D
2
1
C35
10U_0805_4VAM~D
2
1
C36
10U_0805_4VAM~D
2
1
C37
10U_0805_4VAM~D
C38
10U_0805_4VAM~D
2
1
1
2
C39
10U_0805_4VAM~D
2
1
C40
10U_0805_4VAM~D
2
1
C41
10U_0805_4VAM~D
2
1
C42
10U_0805_4VAM~D
2
C43
10U_0805_4VAM~D
+VCC_CORE
Place these inside 1
socket cavity on L8
(North side
Primary)
2
1
C44
10U_0805_4VAM~D
2
1
C45
10U_0805_4VAM~D
2
1
C46
10U_0805_4VAM~D
2
1
C47
10U_0805_4VAM~D
1
C48
10U_0805_4VAM~D
2
2
C49
10U_0805_4VAM~D
+VCC_CORE
C
Place these inside 1
socket cavity on L8
(Sorth side
Primary)
2
1
C50
10U_0805_4VAM~D
2
1
C51
10U_0805_4VAM~D
2
1
C52
10U_0805_4VAM~D
2
1
C53
10U_0805_4VAM~D
10uF 0805 X6S -> 85 degree C
1
C54
10U_0805_4VAM~D
2
2
C55
10U_0805_4VAM~D
C
High Frequence Decoupling
Near VCORE regulator.
+VCC_CORE
+
2
1
+
2
1
+
2
1
+
2
C57
270U_D_2VM_R4.5M~D
Board Bottom Side
1
C60
270U_D_2VM_R4.5M~D
2
@
1@ C59
270U_D_2VM_R4.5M~D
+
C56
270U_D_2VM_R4.5M~D
2
1
@
C61
270U_D_2VM_R4.5M~D
+
C58
270U_D_2VM_R4.5M~D
1
ESR <= 1.5m ohm
Capacitor > 1320uF
Board Top Side
B
B
+1.05V_VCCP
1
2
1
C62
0.1U_0402_10V7K~D
2
1
C63
0.1U_0402_10V7K~D
2
1
C64
0.1U_0402_10V7K~D
2
1
C65
0.1U_0402_10V7K~D
1
C66
0.1U_0402_10V7K~D
2
2
C67
0.1U_0402_10V7K~D
Place these inside
socket cavity on L8
(North side
Secondary)
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
CPU Bypass
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
9
of
63
5
4
3
2
1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
<8>
<8>
<8>
<8>
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
<8>
<8>
<8>
<8>
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_RS#0
H_RS#1
H_RS#2
+H_VREF
H_ADS# <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
H_DPWR# <8>
H_DRDY# <7>
H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>
H_TRDY# <7>
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
1
2
1
1
2
M_ODT0
M_ODT1
M_ODT2
M_ODT3
BD17
AY17
BF15
AY13
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SMRCOMP
SMRCOMP#
BG22
BH21
SM_RCOMP
SM_RCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
BF28
BH28
SM_RCOMP_VOH
SM_RCOMP_VOL
+V_DDR_MCH_REF
SM_PWROK
499_0402_1%~D
TP_SM_DRAMRST#
AV42
AR36
BF17
BC36
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
B38
A38
E41
F41
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
F43
E43
PEG_CLK
PEG_CLK#
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
AE41
AE37
AE47
AH39
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
AE40
AE38
AE48
AH40
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
AE35
AE43
AE46
AH42
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
AD35
AE44
AF46
AH43
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
T25
T26
T27
T28
T29
PAD~D T30
1
2
<24> CL_CLK0
<24> CL_DATA0
<24,38> ICH_CL_PWROK
<24> CL_RST0#
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VR_ON
CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF
PAD~D T31
<12> DDPC_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
<6> CLK_3GPLLREQ#
<24> MCH_ICH_SYNC#
B33
B32
G33
F33
E33
C34
AH37
AH36
AN36
AJ35
AH34
C
3
1
2 2
B
R104
E
330_0402_5%~D
Q4
MMST3904-7-F_SOT323-3~D
1
1 2
R101
54.9_0402_1%~D
MCH_TSATN# 2
1
R103
0_0402_5%~D
4
T32
T33
T34
T35
T36
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
TP_MCH_RSVD1
TP_MCH_RSVD2
TP_MCH_RSVD3
TP_MCH_RSVD4
TP_MCH_RSVD5
TP_MCH_RSVD6
TP_MCH_RSVD7
TP_MCH_RSVD8
TP_MCH_RSVD9
ME_JTAG_TCK @ R804 1
ME_JTAG_TDI @ R805 1
ME_JTAG_TDO @ R806 1
ME_JTAG_TMS @ R807 1
TP_RSV14
@ R1088 1
T172PAD~D
T173PAD~D
T174PAD~D
T175PAD~D
T176PAD~D
T177PAD~D
T178PAD~D
T179PAD~D
RSVD15
RSVD16
RSVD17
B31
B2
M1
TP_MCH_RSVD15
TP_MCH_RSVD16
TP_MCH_RSVD17
T6
T7
T8
PAD~D
PAD~D
PAD~D
RSVD20
AY21
TP_MCH_RSVD20
T9
PAD~D
RSVD22
RSVD23
RSVD24
RSVD25
BG23
BF23
BH18
BF18
TP_MCH_RSVD22
TP_MCH_RSVD23
TP_MCH_RSVD24
TP_MCH_RSVD25
T10 PAD~D
T11 PAD~D
T12 PAD~D
T182PAD~D
2
2
2
2
2
T5 PAD~D
T123PAD~D
T124PAD~D
T125PAD~D
T126PAD~D
+1.05V_VCCP
100_0402_5%~D
100_0402_5%~D
100_0402_5%~D
100_0402_5%~D
51K_0402_1%~D
D
Reserve 100ohm and Test
point for ME JTAG debug
C
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
CLK_3GPLLREQ#
MCH_ICH_SYNC#
N28
M28
G36
E36
K36
H36
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
MCH_TSATN#
B12
TSATN#
ICH_AZ_MCH_BITCLK
ICH_AZ_MCH_RST#
ICH_AZ_MCH_SDIN2
ICH_AZ_MCH_SDOUT
ICH_AZ_MCH_SYNC
B28
B30
B29
C29
A28
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
R29
B7
N33
P32
AT40
AT11
T20
R32
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T14 PAD~D
T15 PAD~D
CFG5 <12>
CFG6 <12>
CFG7 <12>
T16 PAD~D
CFG9 <12>
T17 PAD~D
T18 PAD~D
T19 PAD~D
T20 PAD~D
T21 PAD~D
T22 PAD~D
CFG16 <12>
T23 PAD~D
T24 PAD~D
CFG19 <12>
CFG20 <12>
CFG5
CFG6
CFG7
CFG9
CFG16
CFG19
CFG20
PM_SYNC#
H_DPRSTP#
PM_SYNC# <24>
H_DPRSTP# <8,23,47>
PM_EXTTS#
ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR
PM_EXTTS# <18>
ICH_PWRGD <24,41>
B
THERMTRIP_MCH# <18>
DPRSLPVR <24,47>
+3.3V_RUN
PM_EXTTS#
2
R85
1
10K_0402_5%~D
SM_PWROK
2
R86
1
0_0402_5%~D
Use for DDR3 signls,
if support DDR2 need
connect to GND
CANTIGA ES_FCBGA1329~D
A
PLTRST1#_R
MCH_TSATN_EC <37>
C
THERMTRIP_MCH#
2
R100
1
R102
1
100_0402_5%~D
2
56_0402_5%~D
PLTRST1# <22,32,51>
+1.05V_VCCP
DELL CONFIDENTIAL/PROPRIETARY
2
B
E
Compal Electronics, Inc.
3
1
1
2
+1.05V_VCCP
1
2
1
2
2
1
2
2
1
http://hobi-elektronika.net
5
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
+3.3V_RUN
2
1
2
1
for Quad Core
<24>
<24>
<24>
<24>
R99
1K_0402_5%~D
1@ 75_0402_1%~D
Option Part
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
R98
1K_0402_5%~D
1
R97
1K_0402_1%~D
C76
2.2U_0603_6.3V6K~D
2
2
SMRCOMP_VOL
C75
0.01U_0402_16V7K~D
2
<24>
<24>
<24>
<24>
BA17
AY16
AV16
AR13
NC
R87
499_0402_1%~D
1
C74
0.1U_0402_16V7K~D
2
2@ R95
100_0402_1%~D
A
@ C73
0.1U_0402_16V7K~D
R94
2K_0402_1%~D
1
C72
2.2U_0603_6.3V6K~D
H_SWNG
1
2
C71
0.01U_0402_16V7K~D
+H_VREF
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
SMRCOMP_VOH
1
R93
3.01K_0402_1%~D
<24>
<24>
<24>
<24>
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
R88
1K_0402_1%~D
R91
221_0402_1%~D
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
+1.05V_M
<7>
<7>
<7>
<7>
<7>
+1.8V_MEM
R90
1K_0402_1%~D
<24>
<24>
<24>
<24>
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
<8>
<8>
<8>
<8>
H_AVREF
H_DVREF
+1.05V_VCCP
2
T13
BC28
AY28
AY36
BB36
GRAPHICS VID
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
CANTIGA ES_FCBGA1329~D
+1.05V_VCCP
PAD~D
<6> CLK_MCH_3GPLL
<6> CLK_MCH_3GPLL#
C70
0.1U_0402_16V4Z~D
A11
B11
1
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
ME
H_CPURST#
H_CPUSLP#
2
R81
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
HDA
C12
E11
2
1
R83
1K_0402_1%~D
H_RESET#
H_CPUSLP#
<7> H_RESET#
<8> H_CPUSLP#
1
1
24.9_0402_1%~D
<16>
<16>
<17>
<17>
AR24
AR21
AU24
AV20
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
CLK
J8
L3
Y13
Y1
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DMI
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
<16>
<16>
<17>
<17>
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
MISC
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
+V_DDR_MCH_REF
2
H_SWING
H_RCOMP
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
SMRCOMP
1
80.6_0402_1%~D
SMRCOMP#
1
80.6_0402_1%~D
2
R79
2
R80
2
2
C5
E3
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
<16>
<16>
<17>
<17>
+1.8V_MEM
1
H_SWNG
+H_RCOMP
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
AP24
AT21
AV24
AU20
PM
2@ R82
1
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
<16>
<16>
<17>
<17>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
CFG
1@ 16.9_0402_1%~D
Option Part
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
RSVD
for Quad Core
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
C69
0.1U_0402_16V4Z~D
C
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C68
0.1U_0402_16V4Z~D
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
HOST
<8> H_D#[0..63]
D
B
H_A#[3..35] <7>
U2A
<16>
<16>
<17>
<17>
DDR CLK/ CONTROL/COMPENSATION
U2B
Q3
MMST3904-7-F_SOT323-3~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL")
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CONTAINS CONFIDENTIAL
THIS DOCUMENT MAY NOT
OF DELL. IN ADDITION,
DISCLOSED TO ANY THIRD
Title
Cantiga(1 of 6)
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
2
Sheet
1
10
of
63
5
4
3
2
1
D
D
DDR_A_D[0..63]
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
BB20
BD20
AY20
SA_RAS#
SA_CAS#
SA_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
<16> DDR_A_MA[0..14]
MEMORY
SYSTEM
<16> DDR_A_DQS#[0..7]
DDR
<16> DDR_A_DQS[0..7]
C
A
<16> DDR_A_DM[0..7]
B
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
<16>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D[0..63]
U2E
<17> DDR_B_BS0
<17> DDR_B_BS1
<17> DDR_B_BS2
<17> DDR_B_RAS#
<17> DDR_B_CAS#
<17> DDR_B_WE#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
BC16
BB17
BB33
SB_BS_0
SB_BS_1
SB_BS_2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
AU17
BG16
BF14
SB_RAS#
SB_CAS#
SB_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
<17> DDR_B_DM[0..7]
<17> DDR_B_DQS[0..7]
<17> DDR_B_DQS#[0..7]
<17> DDR_B_MA[0..14]
CANTIGA ES_FCBGA1329~D
B
SA_BS_0
SA_BS_1
SA_BS_2
MEMORY
BD21
BG18
AT25
SYSTEM
<16> DDR_A_RAS#
<16> DDR_A_CAS#
<16> DDR_A_WE#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR
U2D
<16> DDR_A_BS0
<16> DDR_A_BS1
<16> DDR_A_BS2
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
<17>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C
B
CANTIGA ES_FCBGA1329~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
Cantiga(2 of 6)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
11
of
63
5
4
3
2
Strap Pin Table
1
+VCC_PEG
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
M29
C44
B43
E37
E38
C41
C40
B37
A37
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
H47
E46
G40
A40
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
H48
D45
F40
B40
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
TVA_DAC
TVB_DAC
TVC_DAC
H24
TV_RTN
C31
E32
TV_DCONSEL_0
TV_DCONSEL_1
E28
G28
G29
H32
J32
J29
E29
L29
B
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
VGA
J28
TV
F25
H25
K25
LVDS
C
M33
K33
J33
PEG_COMPI
PEG_COMPO
GRAPHICS
D
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
PCI-EXPRESS
L32
G32
M32
T37
T36
DMI X2 Select
CFG6
iTPM Host
Interface
Low = iTPM enable
CFG7
Management
Engine Crypto
Strap
Low = TLS cipher suite with no confidentiality
CFG9
PCI Express
Graphic Lane
CFG16
FSB Dynamic
ODT
Low=Dynamic ODT Disable
DMI Lane
Reversal
Low=Normal (default)
PEGCOMP
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
PEG_MRX_GTX_N0
PEG_MRX_GTX_N1
PEG_MRX_GTX_N2
PEG_MRX_GTX_N3
PEG_MRX_GTX_N4
PEG_MRX_GTX_N5
PEG_MRX_GTX_N6
PEG_MRX_GTX_N7
PEG_MRX_GTX_N8
PEG_MRX_GTX_N9
PEG_MRX_GTX_N10
PEG_MRX_GTX_N11
PEG_MRX_GTX_N12
PEG_MRX_GTX_N13
PEG_MRX_GTX_N14
PEG_MRX_GTX_N15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PEG_MRX_GTX_P0
PEG_MRX_GTX_P1
PEG_MRX_GTX_P2
PEG_MRX_GTX_P3
PEG_MRX_GTX_P4
PEG_MRX_GTX_P5
PEG_MRX_GTX_P6
PEG_MRX_GTX_P7
PEG_MRX_GTX_P8
PEG_MRX_GTX_P9
PEG_MRX_GTX_P10
PEG_MRX_GTX_P11
PEG_MRX_GTX_P12
PEG_MRX_GTX_P13
PEG_MRX_GTX_P14
PEG_MRX_GTX_P15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_N15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_P15
Low = DMI x 2
CFG5
R105
49.9_0402_1%~D
2
U2C
1
PEG_MRX_GTX_N[0..15] <51>
CFG19
High = DMI x 4 (Default)
High = iTPM disable(Defult)
High = Normal Operation(Default)
High=Dynamic ODT Enable(default)
High=Lane Reversed
Low=Only digital display port (SDVO/DP/iHDMI) or
PCIe is operational (default)
High = Digital display port (SDVO/DP/iHDMI) and
PCIe are operating simultaneously via the PEG
port
Digital Display
CFG20 Port
Concurrent
Operation
PEG_MRX_GTX_P[0..15] <51>
SDVO_CRTL_DATA
Low=No SDVO Device Present
(default)
High=SDVO Device Present
Low=DisplayPort disabled (default)
DDPC_CTRLDATA
PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_N[0..15]
CANTIGA ES_FCBGA1329~D
D
High = TLS cipher suite with
confidentiality(Default)
Low = Reverse Lane
High=DisplayPort device present
C
PEG_MTX_GRX_P[0..15] <51>
PEG_MTX_GRX_N[0..15] <51>
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0
C77
2
1 0.1U_0402_10V7K~D
C78 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1
C79
2
1 0.1U_0402_10V7K~D
C80 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2
C81
2
1 0.1U_0402_10V7K~D
C82 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3
C83
2
1 0.1U_0402_10V7K~D
C84 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_N4
C85
2
1 0.1U_0402_10V7K~D
C86 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5
C87
2
1 0.1U_0402_10V7K~D
C88 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6
C89
2
1 0.1U_0402_10V7K~D
C90 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7
C91
2
1 0.1U_0402_10V7K~D
C92 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8
C93
1
2 0.1U_0402_10V7K~D
C94 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9
C95
1
2 0.1U_0402_10V7K~D
C96 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_C_P10 C97
PEG_MTX_GRX_C_N10
1
2 0.1U_0402_10V7K~D
C98 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_C_P11 C99
PEG_MTX_GRX_C_N11
1
2 0.1U_0402_10V7K~D
C100 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_C_P12 C101 1
PEG_MTX_GRX_C_N12
2 0.1U_0402_10V7K~D
C102 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_C_P13 C103 1
PEG_MTX_GRX_C_N13
2 0.1U_0402_10V7K~D
C104 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_C_P14 C105 1
PEG_MTX_GRX_C_N14
2 0.1U_0402_10V7K~D
C106 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_C_P15 C107 1
PEG_MTX_GRX_C_N15
2 0.1U_0402_10V7K~D
C108 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
<10> CFG5
@ R106 1
2 2.21K_0402_1%~D
<10> CFG6
@ R107 1
2 2.21K_0402_1%~D
<10> CFG7
@ R108 1
2 2.21K_0402_1%~D
<10> CFG9
@ R109 1
2 2.21K_0402_1%~D
<10> CFG16
@ R110 1
2 2.21K_0402_1%~D
B
CFG[5:16] have internal pullup
+3.3V_RUN
<10> CFG19
@ R111 1
2 4.02K_0402_1%~D
<10> CFG20
@ R112 1
2 4.02K_0402_1%~D
<10> DDPC_CTRLDATA
@ R113 1
2 4.02K_0402_1%~D
CFG[19:20] have internal pulldown
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
Cantiga(3 of 6)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
12
of
63
5
4
3
2
1
+1.05V_VCCP
U2H
CRB 270uF
2
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
A SM
+1.05V_M_PEGPLL
1
2
1
2
1
2
1
2
0_0805_5%~D
1
+
2
TV
SM CK
HDA
D TV/CRT
C
1
2
1
2
1
2
2
0_1210_5%~D
+1.05V_M_HPLL
24mA Max.
B24
A24
2
+1.5V_RUN
VCC_HDA
A32
VCCD_TVDAC
M25
VCCD_QDAC
L28
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
+1.05V_M
L4
2
1
BLM18AG121SN1D_0603~D
1
2
+1.05V_M_MPLL
139.2mA Max.
1
2
+1.05V_M
2
B
+1.05V_M
+1.05V_M_PEGPLL
1
2
+1.5V_RUN
L49
BLM18PG181SN1_0603~D
2
1
12mil
AA47
M38
L37
C133
22U_0805_6.3VAM~D
C998
0.1U_0402_16V4Z~D
+1.5V_RUN_QDAC
AF1
2
1
L5
LQH32CNR15M33L_1210~D
R120
0_0603_5%~D
1
2
1
2
LVDS
DMI
VCCA_TV_DAC_1
VCCA_TV_DAC_2
1
1_0402_5%~D
2
1
2
1
C138
0.01U_0402_25V7K~D
VTTLF
C118
10U_0805_4VAM~D
2
1
R117
+1.05V_M
1
R119
C140
0.1U_0402_16V4Z~D
VTTLF1
VTTLF2
VTTLF3
A CK
AXF
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
+1.05V_M_PEGPLL
L3
BLM21PG221SN1D_0805~D
1
2
+1.05V_M
R116
+1.05V_M_A_SM
D
Follow ERB,CRB option
to select +1.05V_M or
+1.05V_VCCP
+1.5V_RUN
+3.3V_RUN
+1.05V_M
C117
0.1U_0402_16V4Z~D
+1.05V_VCCP
2
AA48
CANTIGA ES_FCBGA1329~D
+1.8V_MEM
1
2
+VCC_DMI
2
1
1
+VCC_PEG
PJP22
PAD-OPEN1x1m
1
+1.05V_M
2
@ L6
LBC2518T91NM_1210~D
+
@ C145
220U_D2_4VY_R15M~D
2
+1.8V_SM_CK
C147
10U_0805_4VAM~D
2
1
R121
1_0603_5%~D
L7
LQM21FN1R0N00 _0805~D
Rdc=0.1~0.2,rated
current=220mA(MAX)
1
1
2
2
1
2
C146
0.1U_0402_16V4Z~D
A
VCCA_PEG_PLL
C141
0.1U_0402_16V4Z~D
2
2
2 0_0402_5%~D
0_0402_5%~D
C139
0.1U_0402_16V4Z~D
AH48
AF48
AH47
AG47
C144
0.47U_0402_10V4Z~D
C143
0.47U_0402_10V4Z~D
2
1
1
R778 1
@R779
@
R779
1
1
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
V48
U48
V47
U47
U46
C137
0.1U_0402_16V4Z~D
C142
0.47U_0402_10V4Z~D
2
1
+VCCA_PEG_BG
AD48
2
C132
0.1U_0402_16V4Z~D
VCC_HV_1
VCC_HV_2
VCC_HV_3
GMCH_VTTLF1 A8
GMCH_VTTLF2 L1
GMCH_VTTLF3AB2
1
VCCA_PEG_BG
2
1
@ R115
0_1210_5%~D
+1.05V_M
C119
0.1U_0402_16V4Z~D
VCC_TX_LVDS
+VCC_DMI
2
J47
2
1
1
2
R114
0_1210_5%~D
C131
4.7U_0603_6.3V6M~D
K47
+VCC_PEG
1
VSSA_LVDS
1
C130
0.1U_0402_16V4Z~D
C136
0.1U_0402_16V4Z~D
2
B
VCCA_LVDS
C120
100U_D2E_6.3VM_R15M~D
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
+3.3V_RUN_HVC35
B35
A35
0_0603_5%~D
+1.05V_M_MPLL
J48
@C129
@
C129
2.2U_0603_6.3V6K~D
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
BF21
BH20
BG20
BF20
R1065
1
+1.05V_M_HPLL
C123
22U_0805_6.3V6M~D
B22
B21
A21
+3.3V_RUN
2
AD1
AE1
+1.05V_M_SM_CK
+1.8V_SM_CK
1
VCCA_HPLL
VCCA_MPLL
C128
22U_0805_6.3V6M~D
2
2
C127
0.1U_0402_16V4Z~D
2
1
L48
+
C122
4.7U_0603_6.3V6M~D
1
C126
1U_0603_10V4Z~D
2
R118
0_1210_5%~D
@ C125
10U_0805_4VAM~D
1+VCC_AXF
F47
VCCA_DPLLB
1
C121
1U_0603_10V4Z~D
+1.05V_M
VCCA_DPLLA
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
POWER
C
VCCA_DAC_BG
VSSA_DAC_BG
A25
B25
1
CRT
PLL
VTT
A LVDS
2
A PEG
2
1
C116
2.2U_0603_10V7K~D
2
1
C115
4.7U_0603_6.3V6M~D
C114
4.7U_0603_6.3V6M~D
1
B27
A26
C113
22U_0805_6.3V6M~D
D
2
+VCC_PEG
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
C112
4.7U_0603_6.3V6M~D
2
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
C111
220U_D2_4VY_R15M~D
+
1
C110
0.47U_0402_10V4Z~D
C109
220U_D2_4VY_R15M~D
1
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
Cantiga(4 of 6)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
13
of
63
4
3
2
2
VCC_35
+1.05V_M
VCC NCTF
1
2
Layout Note:
Inside GMCH cavity.R123
0_0402_5%~D
Layout Note:
Place on the edge
Layout Note:
Place close to GMCH
B
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
T37
T38
VCC_AXG_SENSE
VSS_AXG_SENSE
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
1
2
A
1
2
1
2
1
2
1
2
1
2
1
2
C163
1U_0402_6.3V4Z~D
PAD~D
PAD~D
AV44
BA37
AM40
AV21
AY5
AM10
BB13
C162
1U_0402_6.3V4Z~D
VCC_AXG_SENSE
VSS_AXG_SENSE
CANTIGA ES_FCBGA1329~D
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
C161
0.47U_0402_10V4Z~D
AJ14
AH14
B
C160
0.22U_0402_10V4Z~D
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
C
C159
0.22U_0402_10V4Z~D
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
D
C158
0.1U_0402_10V7K~D
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
C157
0.1U_0402_10V7K~D
BA36
BB24
BD16
BB21
AW16
AW13
AT13
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC SM LF
2
1
C156
0.1U_0402_10V7K~D
1
C155
0.22U_0402_10V4Z~D
C
2
POWER
T32
Layout Note:
Place close to GMCH
2
1
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC GFX NCTF
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
2
1
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
VCC SM
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
+
VCC CORE
2
1
POWER
2
1
C154
0.22U_0402_10V4Z~D
2
1
C153
22U_0805_6.3VAM~D
+
C152
220U_D2_4VY_R15M~D
1
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
1
C151
22U_0805_6.3V6M~D
CRB 270uF
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
C150
22U_0805_6.3V6M~D
2
D
C148
330U_D2_2.5VY_R15M
U2F
C149
0.1U_0402_10V7K~D
+1.05V_M
1
U2G
+1.8V_MEM
VCC GFX
5
DELL CONFIDENTIAL/PROPRIETARY
CANTIGA ES_FCBGA1329~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
Cantiga(5 of 6)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
14
of
63
A
5
4
3
2
1
U2I
U2J
B
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
BA16
VSS_235
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS
VSS NCTF
C
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS SCB
D
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
NC
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS_351
VSS_352
VSS_353
VSS_354
U24
U28
U25
U29
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
BH48
BH1
A48
C1
A3
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
D
C
B
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
CANTIGA ES_FCBGA1329~D
A
A
CANTIGA ES_FCBGA1329~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
Cantiga(6 of 6)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
15
of
63
5
4
3
2
1
+1.8V_MEM
+1.8V_MEM
<11> DDR_A_DQS#[0..7]
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
D
DDR_A_D8
DDR_A_D9
+1.8V_MEM
DDR_A_DQS#1
DDR_A_DQS1
2
1
DDR_A_D10
DDR_A_D11
C170
C169
1
2.2U_0603_6.3V6K~D
2
2.2U_0603_6.3V6K~D
2
1
C168
C167
1
2.2U_0603_6.3V6K~D
C166
2
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
DDR_A_D16
DDR_A_D17
2
1
DDR_A_D18
DDR_A_D19
C174
0.1U_0402_16V4Z~D
1
C173
C172
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C171
0.1U_0402_16V4Z~D
2
1
DDR_A_D24
DDR_A_D25
2
DDR_A_DM3
DDR_A_D26
DDR_A_D27
C
<10> DDR_CKE0_DIMMA
<11> DDR_A_BS2
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<11> DDR_A_BS0
<11> DDR_A_WE#
<11> DDR_A_CAS#
<10> DDR_CS1_DIMMA#
+0.9V_DDR_VTT
<10> M_ODT1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D32
DDR_A_D33
2
1
2
DDR_A_DQS#4
DDR_A_DQS4
1
DDR_A_D34
DDR_A_D35
2
C188
C187
C186
C185
C184
C183
C182
C181
C180
C179
C178
C177
C176
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
C175
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
B
2
1
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
+0.9V_DDR_VTT
RN1
DDR_A_MA3
1
DDR_A_MA1
2
56_0404_4P2R_5%~D
RN4
4
3
RN6
4
3
4
3
4
3
4
3
DDR_A_DM7
1 DDR_A_MA5
2 DDR_A_MA9
56_0404_4P2R_5%~D
DDR_A_D58
DDR_A_D59
1 DDR_A_MA2
2 DDR_A_MA4
56_0404_4P2R_5%~D
<17,24> MEM_SDATA
<17,24> MEM_SCLK
+3.3V_M
DDR_CKE1_DIMMA 2
1
R130
56_0402_5%~D
4
3
RN11
RN13
RN12
DDR_CKE0_DIMMA 2
DDR_A_BS2
1
56_0404_4P2R_5%~D
1 DDR_A_MA13
2 M_ODT0
56_0404_4P2R_5%~D
3
4
4
3
1 DDR_A_MA11
2 DDR_A_MA14
56_0404_4P2R_5%~D
Layout Note:
Place these resistor
closely JDIMMA,all
trace length
Max=1.3"
http://hobi-elektronika.net
5
4
1
2
1
2
C190
2.2U_0603_6.3V6K~D
4
3
1 DDR_A_BS1
2 DDR_A_MA0
56_0404_4P2R_5%~D
C189
4
3
MEM_SDATA
MEM_SCLK
0.1U_0402_16V4Z~D
A
DDR_A_D56
DDR_A_D57
RN10
RN9
DDR_CS1_DIMMA# 1
M_ODT1
2
56_0404_4P2R_5%~D
DDR_A_D50
DDR_A_D51
Layout Note:
Place these resistor
closely JDIMMA,all
trace length<750 mil
RN8
RN7
DDR_A_CAS#
1
DDR_A_WE#
2
56_0404_4P2R_5%~D
1 DDR_A_MA6
2 DDR_A_MA7
56_0404_4P2R_5%~D
4
3
RN5
DDR_CS0_DIMMA# 1
DDR_A_RAS#
2
56_0404_4P2R_5%~D
1 DDR_A_MA12
2 DDR_A_MA8
56_0404_4P2R_5%~D
4
3
RN3
DDR_A_BS0
1
DDR_A_MA10
2
56_0404_4P2R_5%~D
DDR_A_DQS#6
DDR_A_DQS6
RN2
4
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
1
2
1
2
D
DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_A_D14
DDR_A_D15
2
DDR_A_DQS#2
DDR_A_DQS2
1
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C165
<11> DDR_A_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C164
DDR_A_D0
DDR_A_D1
Layout Note:
Place near JDIMMA
<11> DDR_A_DQS[0..7]
0.1U_0402_16V4Z~D
JDIMMA
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
<11> DDR_A_DM[0..7]
1
2.2U_0603_6.3V6K~D
<11> DDR_A_D[0..63]
1
+V_DDR_MCH_REF
+V_DDR_MCH_REF
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
G1
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
G2
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
C
DDR_CKE1_DIMMA <10>
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_BS1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0 <10>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R128 1
R129 1
2 10K_0402_5%~D
2 10K_0402_5%~D
A
FOX_AS0A426-N4RN-7F~D
DIMMA
REVERSE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
DDRII-SODIMM SLOT1
Size
Document Number
Date:
Wednesday, June 11, 2008
Rev
1.0
LA-4051P
Sheet
1
16
of
63
5
4
3
2
+1.8V_MEM
<11> DDR_B_DQS#[0..7]
DDR_B_D8
DDR_B_D9
1
DDR_B_DQS#1
DDR_B_DQS1
C197
2
2.2U_0603_6.3V6K~D
2
1
C196
2.2U_0603_6.3V6K~D
1
C195
C194
2
2.2U_0603_6.3V6K~D
C193
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2
1
DDR_B_D10
DDR_B_D11
2
2
1
DDR_B_DQS#2
DDR_B_DQS2
C201
C200
2
1
0.1U_0402_16V4Z~D
C199
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
C198
0.1U_0402_16V4Z~D
1
DDR_B_D18
DDR_B_D19
2
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
<10> DDR_CKE2_DIMMB
C
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_B_BS2
<11> DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
<11> DDR_B_BS0
<11> DDR_B_WE#
+0.9V_DDR_VTT
DDR_B_CAS#
DDR_CS3_DIMMB#
<11> DDR_B_CAS#
<10> DDR_CS3_DIMMB#
2
1
2
M_ODT3
1
DDR_B_D32
DDR_B_D33
2
DDR_B_DQS#4
DDR_B_DQS4
C214
C213
C212
C211
C210
C209
C208
C207
C206
C205
C204
C203
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
C202
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
<10> M_ODT3
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
B
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
+0.9V_DDR_VTT
DDR_B_MA3
1
DDR_B_MA1
2
56_0404_4P2R_5%~D
4
3
4
3
RN19
4
3
4
3
4
3
4
3
DDR_CKE3_DIMMB 2
1
R133
56_0402_5%~D
4
3
DDR_B_MA5
1
DDR_B_MA8
2
56_0404_4P2R_5%~D
DDR_B_D56
DDR_B_D57
Layout Note:
Place these resistor
closely JDIMMB,all
trace length<750 mil
DDR_B_DM7
DDR_B_D58
DDR_B_D59
RN21
RN20
DDR_B_MA7
1
DDR_B_MA6
2
56_0404_4P2R_5%~D
RN26
RN25
DDR_CS3_DIMMB# 2
M_ODT3
1
M_ODT2
1
DDR_B_MA13
2
56_0404_4P2R_5%~D
3
4
4
3
DDR_B_MA9
1
DDR_CKE2_DIMMB
2
56_0404_4P2R_5%~D
56_0404_4P2R_5%~D
Layout Note:
Place these resistor
closely JDIMMB,all
trace length
Max=1.3"
http://hobi-elektronika.net
5
4
1
2
1
2
2
1
2
DDR_B_D12
DDR_B_D13
D
DDR_B_DM1
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 <10>
M_CLK_DDR#2 <10>
DDR_B_D14
DDR_B_D15
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB <10>
C
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>
M_ODT2
DDR_B_MA13
M_ODT2 <10>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
B
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
FOX_AS0A426-N8RN-7F_RV
C216
RN24
C215
DDR_B_MA4
1
DDR_B_MA2
2
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
A
0.1U_0402_16V4Z~D
RN23
RN22
MEM_SDATA
MEM_SCLK
<16,24> MEM_SDATA
<16,24> MEM_SCLK
+3.3V_M
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
1
DIMMB
REVERSE
+3.3V_M
2
1
R131
10K_0402_5%~D
R132
4
3
DDR_B_WE#
1
DDR_B_CAS#
2
56_0404_4P2R_5%~D
DDR_B_MA14
1
DDR_B_MA11
2
56_0404_4P2R_5%~D
4
3
4
3
DDR_B_RAS#
1
DDR_CS2_DIMMB# 2
56_0404_4P2R_5%~D
DDR_B_D50
DDR_B_D51
RN17
RN18
DDR_B_MA0
1
DDR_B_BS1
2
56_0404_4P2R_5%~D
DDR_B_MA12
1
DDR_B_BS2
2
56_0404_4P2R_5%~D
4
3
RN16
DDR_B_BS0
1
DDR_B_MA10
2
56_0404_4P2R_5%~D
DDR_B_DQS#6
DDR_B_DQS6
RN15
RN14
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
DDR_B_D6
DDR_B_D7
10K_0402_5%~D
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
DDR_B_D16
DDR_B_D17
DDR_B_DM0
1
+1.8V_MEM
DDR_B_D4
DDR_B_D5
A
2
DDR_B_D2
DDR_B_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C192
DDR_B_DQS#0
DDR_B_DQS0
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
0.1U_0402_16V4Z~D
<11> DDR_B_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C191
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DDR_B_D0
DDR_B_D1
<11> DDR_B_DQS[0..7]
1
2.2U_0603_6.3V6K~D
JDIMMB
Layout Note:
Place near JDIMMB
<11> DDR_B_DM[0..7]
1
+V_DDR_MCH_REF
+V_DDR_MCH_REF
<11> DDR_B_D[0..63]
D
1
+1.8V_MEM
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
DDRII-SODIMM SLOT2
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
17
of
63
5
4
3
2
1
+3.3V_M
1
Discrete
VGA_THERMDP
VGA_THERMDP <51>
1
1
THERMATRIP1#
C217
470P_0402_50V7K~D
1
C218
0.1U_0402_16V4Z~D
T186PAD~D
PWR_MON <47>
ISL88731_ICM <48>Diode
circuit at DP4/DN4 is used for skin
temp sensor (placed optimally between CPU,
MCH and MEM).
Place C221 close to the
Guardian pins as possible.
@R1005
@
R1005
270K_0402_1%
1
<38> BC_DAT_EMC4002
C
1
2
2
B
C221
E
<38> BC_CLK_EMC4002
2
2200P_0402_50V7K~D
1
Place under CPU
C224
2200P_0402_50V7K~D
1
10
11
<7> H_THERMDA
1
C225
470P_0402_50V7K~D
<7> H_THERMDC
Place C225 close to U3
REM_DIODE1_P
REM_DIODE1_N
2
2
+RTC_CELL
1
C229
0.1U_0402_16V4Z~D
2
<38,41> 3.3V_M_PWRGD
<41> ICH_PWRGD#
1
R146 1
R148
1
DP4/DN8
DN4/DP8
DP2
DN2
DP5/DN9
DN5/DP9
47
46
41
40
DP3/DN7
DN3/DP7
42
2
R150
3
1
4.7K_0402_5%~D
LDO_POK
ADDR_MODE/XEN
LDO_SET
33
VDD_5V
VDD_5V
9
VDD_3V
7
8
FAN_OUT
FAN_OUT
15
14
VDDH/VDD_5V2
VDDH/VDD_5V2
32
31
VDDL/VDD_3V2
28
LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2
29
30
TACH2/GPIO4
PWM2/GPIO1
16
13
TACH1/GPIO3
CLK_IN/GPIO2
EC_32KHZ_OUT
5
1
For Remote1
mode
SMBUS
Address
POWER_SW# 4
2.5V_RUN_PWRGD
<37,41>
B
+3V_LDOIN
+1.8V_RUN
2
R985
1
2
1
0_0402_5%~D
1
2
1
2
2
1
R152
0.82_1210_1%~D
LDO_SET
U70
74AHC1G08GW_SOT353-5~D
1
POWER_SW_IN# <38>
IN2
2
DOCK_PWR_SW# <38>
3
E
Q11
MMST3904-7-F_SOT323-3~D
C240
0.1U_0402_16V4Z~D
2
2N3904
2F(r/w)
2N3904
2E(r/w)
18K
Thermistor
2F(r/w)
>= 33K
Thermistor
2E(r/w)
3
<= 4.7K +/- 5%
10K
1
@
R144
@
R143
2
1
2
1
Ra
Rb
Voltage margining circuit
for LDO output. Adjustable
from 1.2 to 2.5V.
Ra=((LDO_OUT/1.11)-1)*Rb.
2
*
THERMATRIP3#
C
THERM_B3 2
B
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
0_0402_5%~D
<51> THERMTRIP_VGA#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
+1.8V_RUN
PM_EXTTS# <10>
IN1
O
G
Pull-up Resistor
on ADDR_MODE/XEN
P
0.1U_0402_16V4Z~D
R155
8.2K_0402_5%~D
1
2
1
1
2
R157
2.2K_0402_5%~D
R156
8.2K_0402_5%~D
1
At maximum load current of 600mA,the the
voltage drop across the should be keep
in the range of 0.5V to 1V
+3.3V_SUS
C1014
+3.3V_M
+3.3V_RUN
2
1
+3.3V_M
10K_0402_5%~D
THERM_STP# <44>
2
+RTC_CELL
47K_0402_1%~D
LDO_SET
2
+RTC_CELL
A
R149 10K_0402_5%~D
2
1
1
49
<38> EC_32KHZ_OUT
+FAN1_VOUT
FAN1_TACH_FB
VSET
34
2
R145
1
@R147
@
R147
10K_0402_5%~D
1
C233
0.1U_0402_16V4Z~D
2
19
+3.3V_M
ACAV_IN <38,48>
R1034 @
2
LDO_SHDN#
2
BC_INT#_EMC4002 <38>
C239
0.1U_0402_16V4Z~D
2
1
1
10K_0402_5%~D
POWER_SW#
C238
10U_0805_10V4Z~D
2
1
THERMTRIP1#
THERMTRIP2#
THERMTRIP3#
12
26
27
20
25
R140
10KB_0603_1%_TSM1A103F34D3R~D
C226
0.1U_0402_16V4Z~D
C232
10U_0805_10V4Z~D
6
5
C237
10U_0805_10V4Z~D
1
ATF_INT#/BC-LINK_IRQ#
POWER_SW#
ACAVAIL_CLR
THERMTRIP_SIO/PWM1/GPIO5
SYS_SHDN#
VCC_PWRGD
3V_PWROK#
RTC_PWR3V
2
1
1
2
2
R141
VCC
1
+3.3V_RUN
+3.3V_RUN
C236
0.1U_0402_16V4Z~D
2
C235
10U_0805_10V4Z~D
1
Rset=953,Tp=88degree
C234
0.1U_0402_16V4Z~D
2
2
C231
0.1U_0402_16V4Z~D
+3VSUS_THRM
+5V_RUN
R151
953_0402_1%~D
DP6/VREF_T2
DN6/VIN2
VSS
1
VGA_THERMDP
VGA_THERMDN
DP1/VREF_T
DN1/THERM
18
2
2 1K_0402_5%~D 17
1K_0402_5%~D
THERMATRIP1#
22
THERMATRIP2#
23
THERMATRIP3#
24
B
REM_DIODE4_P
REM_DIODE4_N
38
37
4
VSET
39
48
45
44
43
21
C230
1U_0603_10V4Z~D
1
VIN1
VCP1
VCP2
36
35
+3VSUS_THRM
2
R142
0_0603_5%~D
1
2
R139
1.2K_0402_1%~D
2
1
+3.3V_M
C
SMDATA/BC-LINK_DATA
SMBCLK/BC-LINK_CLK
1
Place C224,C225 close to the Guardian pins as possible
@C222
@C222
100P_0402_50V8K~D
THERMISTOR OPTION:
Single-ended routing to thermistor is permissible
(ground return). Place R139 and C226 near EMC4002
U3
EMC4002
Place C223 close to the Q8 as possible
2
Place C222 close to Q7 as
possible.
2
3
1
C
2
2
B
Q8
MMST3904-7-F_SOT323-3~D
E
1
1
C
2
@C223
@
C223
100P_0402_50V8K~D
2
R153
3.16K_0402_1%~D
<10> THERMTRIP_MCH#
R154
5.1K_0402_1%~D
C220
0.1U_0402_16V4Z~D
3
1 R992
2
4.7K_0402_5%~D
Q9
ISL88731_ICM_R
1
D38
MMST3904-7-F_SOT323-3~D
2
PWR_MON_GFX
3
3
1
1
C219
2
1
THERMATRIP2#
5
6
MOLEX_53398-0471~D
1
+1.05V_VCCP
R138
C
2.2K_0402_5%~D
1
2
2
B
E
Q6
MMST3904-7-F_SOT323-3~D
2
1
2
3 G1
4 G2
2
2
R137
8.2K_0402_5%~D
1
RB751S40T1_SOD523-2~D
1
1
D2
RB751S40T1_SOD523-2~D
1
2
3
4
+FAN1_VOUT
FAN1_TACH_FB
D
VGA_THERMDN <51>
Place Capacitor close to Guardian Chip
JFAN1
<22> FAN1_DET#
+3.3V_M
22U_0805_6.3VAM~D
<7> H_THERMTRIP#
2
Q7
MMST3904-7-F_SOT323-3~D
2
VGA_THERMDN
R136
10K_0402_5%~D
2
3
1
B
D
E
+1.05V_VCCP
R135
C
2.2K_0402_5%~D
1
2
2
B
E
Q5
MMST3904-7-F_SOT323-3~D
+3.3V_M
C
2
R134
8.2K_0402_5%~D
4
3
2
Title
FAN & Thermal Sensor
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
18
of
63
A
5
4
3
2
JLVDS1
+15V_ALW
4
2
I
G
2
BAT54CW_SOT323~D
1
2
@ R164
0_0402_5%~D
+3.3V_RUN
3
1
2
1
2
2
3
1
2
1
1
LDDC_DATA_GPU <51>
LDDC_CLK_GPU <51>
LVDS_CBL_DET# <22>
1
2
C241
0.1U_0402_16V4Z~D
D
Q15
DDTC124EUA-7-F_SOT323-3~D
CAM_MIC_CBL_DET# <22>
DMIC_CLK <27>
+3.3V_RUN
DMIC0 <27>
D48
SD05.TCT_SOD323-2~D
2
1
@
Pin28 3.3VRUN is for Mic PWR
@
C
2
R165
10K_0402_5%~D
D56
SD05.TCT_SOD323-2~D
2
1
@
1
LCD_SMBCLK <38>
+3.3V_RUN
LCD_SMBDAT <38>
+INV_PWR_SRC
D47
SD05.TCT_SOD323-2~D
2
1
+CAMERA_VDD
1
2
C246
0.1U_0603_50V4Z~D
2
0_0402_5%~D
Dual layout for Q17
6
5
2
1
+INV_PWR_SRC
4
Q18
2N7002W-7-F_SOT323-3~D
3
2
GND IO2
3
IO1
4
VIN
USBP11_D-
S
D
2
1
100K_0402_5%~D
B
2
G
@ U50
1
C247
0.1U_0603_50V4Z~D
PWR_SRC_ON
PWR_SRC_ON
USBP11_D+
SI3457DV : P CHANNAL
<28,37,40,41> RUN_ON
FDS4435: P CHANNAL
+CAMERA_VDD
PRTR5V0U2X_SOT143-4~D
<24> USBP11-
0.1U_0402_25V4K~D
2
2
3
+5V_RUN
4
2
1
C1027
Q133
2N7002W-7-F_SOT323-3~D
1
2
1
3
2
1
R169
0_0603_5%~D
Close to JLVD1.6,7,8
2
+INV_PWR_SRC
1
R167
100K_0402_5%~D
1
R168
C1026
0.1U_0402_16V4Z~D
R994
100K_0402_5%~D
S
+3.3V_RUN
Q17
SI3457DV-T1_TSOP6~D
G
1
2
D
@
2
1
R170
0_0603_5%~D
1
+PWR_SRC
40mil
8
7
6
5
1
2
3
G
Close to JLVD1.28
+CMOS_VDD_R
+15V_ALW
2
G
2
40mil
C248
1000P_0402_50V7K~D
1
1
C244
0.1U_0402_16V4Z~D
D
S
2
C250
10U_1206_16V4Z~D
C249
0.1U_0402_16V4Z~D
1
+LCDVDD
@Q16
@
Q16
FDS4435_NL_SO8~D
+PWR_SRC
Overlap on Q16 for pop option
1
+3.3V_RUN
C243
0.1U_0402_16V4Z~D
PMV45EN_SOT23-3~D
Q132
C245
0.1U_0402_16V4Z~D
2
2
D
PNL_BKLT_CBL_DET# <22>
BREATH_BLUE_LED_LCD <42>
BATT_YELLOW_LED_LCD <42>
BATT_BLUE_LED_LCD <42>
BREATH_BLUE_LED_LCD
BATT_YELLOW_LED_LCD
BATT_BLUE_LED_LCD
BIA_PWM_GPU <51>
+5V_ALW
1
LCD_TST <37>
+LCDVDD
S
1
@ R166
LCD_TST
3
<37> CCD_OFF
3
PCB 03P LA-4051P REV0 M/B
<51> ENVDD_GPU
DMIC0
+CAMERA_VDD
Webcam PWR CTRL
<37> LCD_VCC_TEST_EN
Description
DAA00000R0L
2
2
O
LVDS CABLE
Part Number
Q12
1
SI3456DV-T1-E3_TSOP6~D
3
@
LCD_A0+_GPU <51>
LCD_A0-_GPU <51>
LCD_SMBCLK
LCD_SMBDAT
5
1
D3
LCD_A1+_GPU <51>
LCD_A1-_GPU <51>
1
B
6 2
LCD_A2+_GPU <51>
LCD_A2-_GPU <51>
2
R158
100K_0402_5%~D
C242
0.1U_0402_25V4Z~D
Q13A
2N7002DW-T/R7_SOT363-6~D
6
5
2
1
4
@R163
@
R163
100K_0402_5%~D
Place near to JLVDS1
LCD_ACLK+_GPU <51>
LCD_ACLK-_GPU <51>
JAE_FI-DP58SB-VF88L
1
LDDC_CLK_GPU
2
2.2K_0402_5%~D
LDDC_DATA_GPU
2
2.2K_0402_5%~D
1
R159
1
R160
LCD_B0+_GPU <51>
LCD_B0-_GPU <51>
USBP11_DUSBP11_D+
+15V_ALW
G
1
+3.3V_RUN
LCD_B1+_GPU <51>
LCD_B1-_GPU <51>
CAM_MIC_CBL_DET#
DMIC_CLK
+3.3V_RUN
S
+LCDVDD
LCD_B2+_GPU <51>
LCD_B2-_GPU <51>
LDDC_DATA_GPU
LDDC_CLK_GPU
LVDS_CBL_DET#
+LCDVDD
D
LCD_BCLK+_GPU <51>
LCD_BCLK-_GPU <51>
Q13B
2N7002DW-T/R7_SOT363-6~D
Even_ClkIN+
Even_ClkINVSS
Even_Rin2+
Even_Rin2VSS
Even_Rin1+
Even_Rin1VSS
Even_Rin0+
Even_Rin0VSS
Odd_ClkIN+
Odd_ClkINVSS
Odd_Rin2+
Odd_Rin2VSS
Odd_Rin1+
Odd_Rin1VSS
Odd_Rin0+
Odd_Rin0VSS
DATA EEDID
CLK EEDID
VSS
VEEDID
Diag_Loop_CAM
MIC_CLK
3.3V
MIC_SIG
5V
USBUSB+
GND
CONNTST
SMB_CLK
SMB_DATA
INV_SRC
INV_SRC
INV_SRC
INV_SRC
VBLVBLVBLVBLINV_PWM
+5V_ALW
TEST
VDD
VDD
VDD
CONNTST
PWR_LED
BATT2_LED
BATT1_LED
VSS
R162
100K_0402_5%~D
C
LCD Power
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MGND1
MGND2
MGND3
MGND4
MGND5
MGND6
MGND7
MGND8
MGND9
MGND10
MGND11
MGND12
R161
470_0402_5%~D
D
59
60
61
62
63
64
65
66
67
68
69
70
1
<24> USBP11+
USBP11-
1
USBP11+
4
@ L59
DLW21SN121SQ2L_4P~D
1
2 2
4
3
3
1
R457
2
0_0402_5%~D
1
R513
2
0_0402_5%~D
USBP11_DUSBP11_D+
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
LVDS Conn
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
19
of
63
1
2
@
+3.3V_RUN
2
2
2
+5V_RUN_CRT 1
2
3
2
1
1
1
1
3
2
1
C253
10P_0402_50V8J~D
@
1
C252
10P_0402_50V8J~D
@
2
C251
10P_0402_50V8J~D
2
1
C996
22P_0402_50V8J~D
2
1
C518
22P_0402_50V8J~D
2
1
C390
22P_0402_50V8J~D
2
1
C257
10P_0402_50V8J~D
1
C256
10P_0402_50V8J~D
2
C255
10P_0402_50V8J~D
X01 Remove TV Function
1
2
BLUE_CRT_L
1
2
L61
BLM18BB470SN1D_0603~D
1
2
L62
BLM18BB470SN1D_0603~D
1
2
L63
BLM18BB470SN1D_0603~D
1
GREEN_CRT_L
2
0_0603_5%~D
3
2
2
0_0603_5%~D
1
R843
R174
150_0402_1%~D
2
1
1
R841
BLUE_CRT
R173
150_0402_1%~D
2
1
GREEN_CRT
R172
150_0402_1%~D
2
1
RED_CRT_L
+CRT_VCC
R
1
2
1
2
1
2
2
52
5
54
51
@R176
@
R176
1K_0402_5%~D
NC
NC
NC
NC
To Dock Conn.
B
16
17
SUYIN_070546FR015S558ZR
HSYNC_CRT
1
R177
VSYNC_CRT
1
R178
L11
BLM18AG121SN1D_0603~D
2 HSYNC_L2 1
2
0_0402_5%~D
L12
BLM18AG121SN1D_0603~D
2 VSYNC_L2 1
2
0_0402_5%~D
C258
2
0.1U_0402_16V4Z~D
+3.3V_RUN
2
1
2
1
2
1
2
1
2
1
2
@
C268
22P_0402_50V8J~D
2
1
C267
22P_0402_50V8J~D
2
1
C266
0.1U_0402_16V4Z~D
2
1
C265
0.1U_0402_16V4Z~D
2
1
C264
0.1U_0402_16V4Z~D
1
TS3DV520ERHUR_QFN56_11X5~D
C263
0.1U_0402_16V4Z~D
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
1
DAT_DDC2_DOCK <35>
CLK_DDC2_DOCK <35>
VSYNC_DOCK <35>
HSYNC_DOCK <35>
RED_DOCK <35>
GREEN_DOCK <35>
BLUE_DOCK <35>
C262
0.1U_0402_16V4Z~D
1
6
9
13
16
21
24
28
33
39
44
49
53
55
DAT_DDC2_DOCK
CLK_DDC2_DOCK
VSYNC_DOCK
HSYNC_DOCK
RED_DOCK
GREEN_DOCK
BLUE_DOCK
C261
0.1U_0402_16V4Z~D
SEL
46
45
41
40
35
34
30
29
25
26
JVGA_HS
B
+CRT_VCC
JVGA_VS
M_ID2#
DAT_DDC2_CRT
CLK_DDC2_CRT
C260
0.1U_0402_16V4Z~D
17
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
To MB CRT Conn.
C259
10U_0805_10V4Z~D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
DAT_DDC2_CRT
CLK_DDC2_CRT
VSYNC_BUF
HSYNC_BUF
RED_CRT
GREEN_CRT
BLUE_CRT
@R175
@
R175
1K_0402_5%~D
CRT_SWITCH
0: MB
1: Docking (APR/ EPR)
2
3
7
8
11
12
14
15
19
20
G
48
47
43
42
37
36
32
31
22
23
R793
2.2K_0402_5%~D
CRT_SWITCH
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R794
2.2K_0402_5%~D
<37> CRT_SWITCH
4
10
18
27
38
50
56
1
U4
<51> GPU_DAT_DDC
<51> GPU_CLK_DDC
<51> CRT_VSYNC_GPU
<51> CRT_HSYNC_GPU
<51> CRT_RED_GPU
<51> CRT_GRN_GPU
<51> CRT_BLU_GPU
2
+5V_RUN_SYNC
B
GPU_DAT_DDC
GPU_CLK_DDC
1
C254
0.01U_0402_16V7K~D
2
0_0603_5%~D
R171
0_1206_5%~D
1
R830
@F2
@
F2
5A_125V_R451005.MRL~D
RED_CRT
+5V_RUN
@
D8
SDM10U45-7_SOD523-2~D
+3.3V_RUN
@
D7
DA204U_SOT323-3~D
@
D6
DA204U_SOT323-3~D
D5
DA204U_SOT323-3~D
1
2
@
2
+5V_RUN
1
D9
SDM10U45-7_SOD523-2~D
+5V_RUN_SYNC
P
HSYNC_BUF
A
3
G
2
A
Y
4
HSYNC_CRT
U5
SN74AHCT1G125GW_SC70-5~D
A
2
A
3
G
1
C270
0.1U_0402_16V4Z~D
VSYNC_BUF
5
2
P
1
2
1K_0402_5%~D
1
5
1
R179
OE#
2
OE#
1
C269
0.1U_0402_16V4Z~D
Y
4
VSYNC_CRT
U6
SN74AHCT1G125GW_SC70-5~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
2
Title
CRT/Video switch
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
1
Sheet
20
of
63
2
DPB_CA_DET#
A
2 DPB_CA_DET
DPC_CA_DET#
+3.3V_RUN
4
Y
5
SN74CBTD3306CPWR_TSSOP8~D
+3.3V_RUN
U7
NC7SZ04P5X_NL_SC70-5~D
2
A
DPC_CA_DET
2
1
2
2
2
1
D10
+3.3V_RUN_R 1
B0540WS-7_SOD323-2~D
2
1
2
1
1
F1
1206L150PR~D
1
2
R1087
10K_0402_5%~D
1
2
C276
0.1U_0402_16V4Z~D
8
3
6
4
@
+VDISPLAY_VCC
1
DPC_CA_DET <35,51>
2
1
2
C482
10U_0805_10V6K~D
Y
U8
NC7SZ04P5X_NL_SC70-5~D
U78
1A
VCC
2A
1B
1OE#
2B
2OE# GND
C275
0.01U_0402_16V7K~D
4
B
<51> DVI_C_DAT_DDC
5
SN74CBTD3306CPWR_TSSOP8~D
R1085
10K_0402_5%~D
1
2
+3.3V_RUN
+5V_RUN
C1074
0.1U_0402_16V4Z~D
1
2
2
5
1
7
R764
33_0402_5%~D
1
2
+3.3V_RUN
NC
1
2
P
1
R92
33_0402_5%~D
1
2
<51> DVI_C_CLK_DDC
G
<51> DVI_B_DAT_DDC
C277
0.1U_0402_16V4Z~D
8
3
6
4
DPC_DOCK_AUX_SW <35>
DPC_DOCK_AUX#SW <35>
SN74CBTD3306CPWR_TSSOP8~D
R1086
10K_0402_5%~D
1
2
+3.3V_RUN
3
R89
33_0402_5%~D
1
2
1A
VCC
2A
1B
1OE#
2B
2OE# GND
DPC_DOCK_AUX_SW
DPC_DOCK_AUX#_SW
1
U76
2
5
1
7
8
3
6
4
R184
0_1206_5%~D
R74
33_0402_5%~D
1
2
<51> DVI_B_CLK_DDC
C274
0.1U_0402_10V7K~D
1A
VCC
2A
1B
1OE#
2B
2OE# GND
P
+5V_RUN
C1073
0.1U_0402_16V4Z~D
1
2
U77
2
5
1
7
1
NC
SN74CBTD3306CPWR_TSSOP8~D
R1084
10K_0402_5%~D
1
2
+3.3V_RUN
2
<51> DPC_DOCK_AUX#
G
<51> DPC_DOCK_AUX
DPB_AUX_SW
DPB_AUX#SW
+3.3V_RUN
@
3
1
2
1
8
3
6
4
1K_0402_5%~D
2 R1101 1
2
1
R1102
1K_0402_5%~D
C273
0.1U_0402_10V7K~D
1A
VCC
2A
1B
1OE#
2B
2OE# GND
@
2 R1099 1
2
1
R1100
1K_0402_5%~D
@
1K_0402_5%~D
U75
2
5
1
7
1
C272
0.1U_0402_10V7K~D
2
1
Display port Connector
@
R1035
0_1206_5%~D
2
@
@
R183
100K_0402_5%~D
<51> DPB_AUX
@
+5V_RUN
C1065
0.1U_0402_16V4Z~D
1
2
R182
100K_0402_5%~D
C271
0.1U_0402_10V7K~D
2
1
+3.3V_RUN
SW for eDOCK side
R181
100K_0402_5%~D
C1064
0.1U_0402_16V4Z~D
1
2
R180
100K_0402_5%~D
+5V_RUN
2
+3.3V_RUN
SW for MB side
<51> DPB_AUX#
1
B
JDP1
DPB_MB_HPD
DPB_MB_AUX#
DPB_MB_AUX
DPB_MB_P14
DPB_MB_CA_DET
DPB_MB_LANE3#_C
<51> DPB_MB_P14
DPB_AUX_SW
R1006
2@
DPB_AUX#SW
2
R1007 @
DPC_DOCK_AUX_SW 2
R1008 @
DPC_DOCK_AUX#SW 2
R1009 @
U9
<51> DPB_LANE_P0_C
<51> DPB_LANE_N0_C
3
4
ML_IN 0(p)
ML_IN 0(n)
ML_A 0(p)
ML_A 0(n)
56
55
DPB_MB_LANE0
DPB_MB_LANE0#
<51> DPB_LANE_P1_C
<51> DPB_LANE_N1_C
6
7
ML_IN 1(p)
ML_IN 1(n)
ML_A 1(p)
ML_A 1(n)
53
52
DPB_MB_LANE1
DPB_MB_LANE1#
<51> DPB_LANE_P2_C
<51> DPB_LANE_N2_C
9
10
ML_IN 2(p)
ML_IN 2(n)
ML_A 2(p)
ML_A 2(n)
50
49
<51> DPB_LANE_P3_C
<51> DPB_LANE_N3_C
12
13
ML_IN 3(p)
ML_IN 3(n)
ML_A 3(p)
ML_A 3(n)
AUX_A (p)
AUX_A (n)
DPB_AUX_SW
DPB_AUX#SW
<35> DPB_DOCK_HPD
<35> DPB_DOCK_CA_DET
+3.3V_RUN_LP
30
LP
DP_PRIORITY
29
Priority
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_MB_LANE1_C
DPB_MB_LANE1#_C
DPB_MB_LANE2
DPB_MB_LANE2#
C282
C283
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_MB_LANE2_C
DPB_MB_LANE2#_C
47
46
DPB_MB_LANE3
DPB_MB_LANE3#
C284
C285
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_MB_LANE3_C
DPB_MB_LANE3#_C
45
43
DPB_MB_AUX
DPB_MB_AUX#
25
24
DPB_DOCK_LANE0
DPB_DOCK_LANE0#
C286
C287
ML_B 1(p)
ML_B 1(n)
22
21
DPB_DOCK_LANE1
DPB_DOCK_LANE1#
ML_B 2(p)
ML_B 2(n)
19
18
ML_B 3(p)
ML_B 3(n)
R185
R186
R187
R188
DPC_CA_DET
1M_0402_5%~D
DPB_MB_CA_DET
1M_0402_5%~D
2 DPB_MB_HPD
100K_0402_5%~D
2 DPB_DOCK_CA_DET
1M_0402_5%~D
2 DPB_DOCK_HPD
100K_0402_5%~D
1
2
@
1
@
1
1
2
1
DPB_MB_LANE0_C
C288
C289
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_DOCK_LANE1_C <35>
DPB_DOCK_LANE1#_C <35>
DPB_DOCK_LANE2
DPB_DOCK_LANE2#
C290
C291
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_DOCK_LANE2_C <35>
DPB_DOCK_LANE2#_C <35>
16
15
DPB_DOCK_LANE3
DPB_DOCK_LANE3#
C292
C293
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_DOCK_LANE3_C <35>
DPB_DOCK_LANE3#_C <35>
AUX_B (p)
AUX_B (n)
28
26
DPB_DOCK_AUX
DPB_DOCK_AUX#
HPD
37
DPB_HPD
39
DPB_CA_DET
CAD
DPB_DOCK_LANE0_C <35>
DPB_DOCK_LANE0#_C <35>
DPB_MB_LANE0_C
1
10 DPB_MB_LANE0_C
DPB_MB_LANE0#_C
2
9
DPB_MB_LANE0#_C
DPB_MB_LANE1_C
4
7
DPB_MB_LANE1_C
DPB_MB_LANE1#_C
5
6
DPB_MB_LANE1#_C
3
8
RCLAMP0524P.TCT~D
D12 @
DPB_HPD <51>
DPB_CA_DET <51>
+3.3V_RUN
38
VDD*1
+5V_RUN
2
8
14
17
23
34
48
54
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
5
11
20
27
31
42
44
51
Thermal GND
57
2
R895
2
@R896
@
R896
2
@R897
@
R897
2
@R898
@
R898
2
@R899
@
R899
2
@R900
@
R900
DPB_MB_LANE2_C
1
10 DPB_MB_LANE2_C
DPB_MB_LANE2#_C
2
9
DPB_MB_LANE2#_C
DPB_MB_LANE3_C
4
7
DPB_MB_LANE3_C
DPB_MB_LANE3#_C
5
6
DPB_MB_LANE3#_C
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
DPB_MB_AUX
2
@ R209
2
R278
DPB_DOCK_AUX 2
@ R336
DPB_DOCK_AUX# 2
@ R337
DPC_DOCK_AUX 2
@ R419
DPC_DOCK_AUX# 2
@ R647
3
8
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
DPB_MB_AUX#
RCLAMP0524P.TCT~D
D13 @
DPB_MB_AUX#
1
10 DPB_MB_AUX#
DPB_MB_AUX
2
9
DPB_MB_AUX
DPB_MB_HPD
4
7
DPB_MB_HPD
DPB_MB_CA_DET
5
6
DPB_MB_CA_DET
Pads for interoperability,
remove in X01 if not needed.
8
RCLAMP0524P.TCT~D
Standard operational mode for device
Low power Mode
Device is forced into a low power mode
causing the output s to go to a high-Z
state, all other inputs are ignore
1
1 R911
2
0_0402_5%~D
2
0_0402_5%~D
DPB_MB_HPD
1 R968
5
@
1
IN1
2
IN2
C1018 0.1U_0402_16V4Z~D
P
<37> DP_MB_EN
O
G
<35,37> DOCK_DET#
2
DP_MB_HPD_EN
4
74AHC1G08GW_SOT353-5~D
3
2
Normal Mode
Low
Place close to JDP1 connector
+3.3V_RUN
1
Hi
http://hobi-elektronika.net
2
A
3
TS2DP512_QFN56_8X8~D
Description
21
22
23
24
GND
GND
GND
GND
MOLEX_105019-0001
DPB_DOCK_AUX <35>
DPB_DOCK_AUX# <35>
DPVadj
DP_PWR
RTN
HP_DET
AUX_CHGND
AUX_CH+
GND
CA_DET
LANE3LANE3_shield
LANE3+
LANE2LANE2_shield
LANE2+
LANE1LANE1_shield
LANE1+
LANE0LANE0_shield
LANE0+
D11 @
U66
LP
DPB_MB_LANE1_C
DPB_MB_LANE0#_C
Its for Enhance ESD on dock issue.
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
R191
100K_0402_5%~D
State
DPB_MB_LANE2_C
DPB_MB_LANE1#_C
0.033U_0402_16V7K~D
DPB_HPD
Pin30 Level
DPB_MB_LANE3_C
DPB_MB_LANE2#_C
2
1
C984
2
2
ML_B 0(p)
ML_B 0(n)
1M_0402_5%~D
2
2
CAD_A
CAD_B
C280
C281
2
1
1
2
1
C950
0.1U_0402_10V7K~D
2
1
C941
1000P_0402_50V7K~D
1
C940
0.01U_0402_16V7K~D
2
C939
0.1U_0402_10V7K~D
2
C938
0.1U_0402_10V7K~D
C937
1U_0603_10V4Z~D
2
1
HPD_A
HPD_B
DPB_MB_LANE0_C
DPB_MB_LANE0#_C
R993
+3.3V_RUN
1
41
33
1
A
1
40
32
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
R1001
+3.3V_RUN
R193
3.48K_0402_1%~D
+5V_RUN
DPB_MB_CA_DET
DPB_DOCK_CA_DET
R190
100K_0402_5%~D
2
<37> DP_PRIORITY
DP_MB_HPD_EN
DPB_DOCK_HPD
AUX (p)
AUX (n)
2
2
1
1
R189
100K_0402_5%~D
2
+3.3V_RUN
36
35
C278
C279
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Display port
Size
Document Number
Date:
Friday, June 13, 2008
Rev
1.0
LA-4051P
1
Sheet
21
of
63
5
4
3
2
1
+3.3V_RUN
2 8.2K_0402_5%~D PCI_TRDY#
R197 1
2 8.2K_0402_5%~D PCI_FRAME#
R198 1
2 8.2K_0402_5%~D PCI_PLOCK#
R199 1
2 8.2K_0402_5%~D PCI_IRDY#
R200 1
2 8.2K_0402_5%~D PCI_SERR#
R201 1
2 8.2K_0402_5%~D PCI_PERR#
+3.3V_RUN
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI
F1
G4
B6
A7
F13
F12
E6
F6
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
D8
B4
D6
A5
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
C14
D4
R2
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PCI_REQ1# <31>
PCI_GNT1# <31>
PCIE_MCARD2_DET# <34>
T183PAD~D
PCIE_MCARD3_DET# <34>
GNT2#/GPIO53
GNT3#/GPIO55
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
+3.3V_ALW_ICH
C294
0.1U_0402_16V4Z~D
<31>
<31>
<31>
<31>
PCI_PCIRST#
PCI_IRDY# <31>
PCI_PAR <31>
1
IN1
2
IN2
PCI_DEVSEL# <31>
PCI_PERR# <31>
OUT
PCI_SERR# <31>
PCI_STOP# <31>
PCI_TRDY# <31>
PCI_FRAME# <31>
2 8.2K_0402_5%~D PCI_PIRQB#
R204 1
2 8.2K_0402_5%~D PCI_PIRQC#
R205 1
2 8.2K_0402_5%~D PCI_PIRQD#
R207 1
2 8.2K_0402_5%~D PCI_REQ0#
R208 1
2 8.2K_0402_5%~D PCI_REQ1#
R702 1
2 100K_0402_5%~D FAN1_DET#
R755 1
2 100K_0402_5%~D LVDS_CBL_DET#
R212 1
2 100K_0402_5%~D CAM_MIC_CBL_DET#
10
IN1
R817 1
2 100K_0402_5%~D PNL_BKLT_CBL_DET#
9
IN2
IN1
5
IN2
P
4
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
H4
K6
F2
G2
LVDS_CBL_DET#
PNL_BKLT_CBL_DET#
CAM_MIC_CBL_DET#
FAN1_DET#
LVDS_CBL_DET# <19>
PNL_BKLT_CBL_DET# <19>
CAM_MIC_CBL_DET# <19>
FAN1_DET# <18>
PLTRST1#
6
PLTRST1# <10,32,51>
G
OUT
C
U11B
74VHC08MTCX_NL_TSSOP14~D
7
PCI_PLTRST#
+3.3V_ALW_ICH
14
J5
E1
J6
C4
CLK_PCI_ICH <6>
ICH_PME# <37>
ICH9M REV 1.0
P
<31> PCI_PIRQB#
<31> PCI_PIRQC#
<31> PCI_PIRQD#
14
2 8.2K_0402_5%~D PCI_PIRQA#
R203 1
Interrupt I/F
PCI_RST# <31>
+3.3V_ALW_ICH
R202 1
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_RST#
3
U11A
74VHC08MTCX_NL_TSSOP14~D
OUT
PLTRST2#
8
PLTRST2# <37,38>
U11C
74VHC08MTCX_NL_TSSOP14~D
7
C
D
U10B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
14
R196 1
<31> PCI_AD[0..31]
P
2 8.2K_0402_5%~D PCI_STOP#
G
2 8.2K_0402_5%~D PCI_DEVSEL#
R195 1
7
R194 1
G
D
14
+3.3V_ALW_ICH
IN1
12
IN2
P
13
7
PCI_GNT0#
<24> ICH_SPI_CS1#
PLTRST3# <34,36>
U11D
74VHC08MTCX_NL_TSSOP14~D
ICH_SPI_CS1#
1
1
GNT3#/GPIO55
B
1
B
11 PLTRST3#
G
OUT
@ R214
@R214
1K_0402_5%~D
2
2
R213
1K_0402_5%~D
2
@ R215
1K_0402_5%~D
Place closely pin U10.D4
2
CLK_PCI_ICH
Boot BIOS Strap
A16 away override strap.
PCI_GNT0#
*
SPI_CS1#
Boot BIOS Location
0
1
SPI
1
0
PCI
1
1
LPC
CLK_ICH_TERM 1
PCI_GNT3#
@ R216
@R216
10_0402_5%~D
Low = A16 swap override enabled.
High = Default.
1
2
@ C295
@C295
8.2P_0402_50V8J~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
ICH9-M(1/4)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
22
of
63
3
2
1
+RTC_CELL
+RTC_CELL
1
4
1
5
2
R218
332K_0402_1%~D
LAN100_SLP
2
ICH_INTVRMEN
2
2
R217
332K_0402_1%~D
@ R219
@R219
0_0402_5%~D
ICH9M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
C296
2
1
1
2
2
1
A25
F20
C22
RTCRST#
SRTCRST#
INTRUDER#
ICH_INTVRMEN
LAN100_SLP
B22
A22
INTVRMEN
LAN100_SLP
E25
GLAN_CLK
<29> LAN_CLK
C13
LAN_RSTSYNC
LAN_RX0
LAN_RX1
LAN_RX2
F14
G13
D14
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TX0
LAN_TX1
LAN_TX2
D13
D12
E13
LAN_TXD0
LAN_TXD1
LAN_TXD2
GLAN_DOCK#
B10
GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
<29> LAN_RSTSYNC
C
ME_CLR1
1
C298
@SHORT PADS~D
2
1U_0603_10V4Z~D
<29> LAN_RX0
<29> LAN_RX1
<29> LAN_RX2
CMOS_CLR1 @SHORT PADS~D
1
2
C299
1U_0603_10V4Z~D
<29> LAN_TX0
<29> LAN_TX1
<29> LAN_TX2
Close to U55
1
R234
1
R235
1
R239
1
R241
<27> ICH_AZ_CODEC_SDOUT
<27> ICH_AZ_CODEC_SYNC
<27> ICH_AZ_CODEC_RST#
<27> ICH_AZ_CODEC_BITCLK
1
C302
27P_0402_50V8J~D
2 ICH_AZ_SDOUT
33_0402_5%~D
2 ICH_AZ_SYNC
33_0402_5%~D
2 ICH_AZ_RST#
33_0402_5%~D
2 ICH_AZ_BITCLK
33_0402_5%~D
<33> ICH_AZ_MDC_BITCLK
<33> ICH_AZ_MDC_SYNC
<33> ICH_AZ_MDC_RST#
<27> ICH_AZ_CODEC_SDIN0
<33> ICH_AZ_MDC_SDIN1
<51> ICH_AZ_GPU_SDIN2
1
2
+1.5V_RUN_PCIE_ICH
R232
2
1
C300
R236 33_0402_5%~D
24.9_0402_1%~D
ICH_AZ_BITCLK
27P_0402_50V8J~D
1
2
ICH_AZ_SYNC
1
2
R238
33_0402_5%~D
ICH_AZ_RST#
1
2
R240
33_0402_5%~D
ICH_AZ_CODEC_SDIN0
ICH_AZ_MDC_SDIN1
ICH_AZ_GPU_SDIN2
2
1
R242
<33> ICH_AZ_MDC_SDOUT
<51> ICH_AZ_GPU_SDOUT
@
<51> ICH_AZ_GPU_SYNC
@
<51> ICH_AZ_GPU_RST#
B
@
<51> ICH_AZ_GPU_BITCLK
1 @
C309
27P_0402_50V8J~D
1
R243
1
R244
1
R245
1
R246
2 ICH_AZ_SDOUT
33_0402_5%~D
2 ICH_AZ_SYNC
33_0402_5%~D
2 ICH_AZ_RST#
33_0402_5%~D
2 ICH_AZ_BITCLK
33_0402_5%~D
@
<37> ME_FWP
T46 PAD~D
SATA_ACT#_R
<42> SATA_ACT#_R
<26> PSATA_IRX_DTX_N0_C
<26> PSATA_IRX_DTX_P0_C
<26> PSATA_ITX_DRX_N0
<26> PSATA_ITX_DRX_P0
<26> SATA_ODD_IRX_DTX_N1_C
<26> SATA_ODD_IRX_DTX_P1_C
<26> SATA_ODD_ITX_DRX_N1
<26> SATA_ODD_ITX_DRX_P1
2
ICH_AZ_SDOUT
2
33_0402_5%~D
ME_FWP
RTC_BAT_DET#
2
C307 2
C308
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
2
C310 2
C311
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
AE7
HDA_RST#
AF4
AG4
AH3
AE5
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AG5
HDA_SDOUT
AG7
AE8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
AH16
AF17
AG17
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AH13
AJ13
SATA_ODD_ITX_DRX_N1_C AG14
SATA_ODD_ITX_DRX_P1_C AF14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C
K5
K4
L6
K2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
FWH4/LFRAME#
K3
LPC_LFRAME#
LDRQ0#
LDRQ1#/GPIO23
J3
J1
LPC_LDRQ0#
LPC_LDRQ1#
A20GATE
A20M#
N7
AJ27
SIO_A20GATE
H_A20M#
DPRSTP#
DPSLP#
AJ25
AE23
FERR#
AJ26
H_DPRSTP#
H_DPSLP#
R229
2
1
56_0402_5%~D
H_PWRGOOD
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
<36,37,38>
+3.3V_RUN
<36,37,38>
<36,37,38>
<36,37,38>
<36,37,38>
SIO_RCIN#
LPC_LFRAME# <36,37,38>
LPC_LDRQ0# <37>
LPC_LDRQ1# <37>
SIO_A20GATE <38>
H_A20M# <7>
SIO_A20GATE
+1.05V_VCCP
1
ICH_RTCRST#
SRTCRST#
INTRUDER#
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
2
2
RTCX1
RTCX2
@R228
@
R228
56_0402_1%~D
1
2 20K_0402_5%~D
2 20K_0402_5%~D
2 1M_0402_5%~D
LPC_LAD[0..3]
U10A
C23
C24
ICH_RTCX2
@R227
@
R227
56_0402_1%~D
1
R224 1
R225 1
R226 1
R223
0_0402_5%~D
1
2
2
R230
2
R231
1
10K_0402_5%~D
1
10K_0402_5%~D
2
R233
1
56_0402_5%~D
+1.05V_VCCP
H_FERR#
H_DPRSTP# <8,10,47>
H_DPSLP# <8>
C
H_FERR# <7>
CPUPWRGD
AD22
IGNNE#
AF25
H_IGNNE#
INIT#
INTR
RCIN#
AE22
AG25
L3
H_INIT#
H_INTR
SIO_RCIN#
NMI
SMI#
AF23
AF24
H_NMI
H_SMI#
STPCLK#
AH27
H_STPCLK#
THRMTRIP#
AG26
THRMTRIP_ICH#
TP12
AG27
ICH_TP12
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
H_PWRGOOD <8>
H_IGNNE# <7>
H_INIT# <7>
H_INTR <7>
SIO_RCIN# <38>
+1.05V_VCCP
1
+RTC_CELL
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
H_NMI <7>
H_SMI# <7>
R237
56_0402_5%~D
H_STPCLK# <7>
2
Keep ME RTC Registers
1
1
Open
2
2
Clear ME RTC Registers
ICH_LAN100_SLP
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
RTC
LPC
32.768KHZ_12.5PF_1TJE125DP1~D
C297
4P_0402_50V8B~D
ME_CLR1 TPM setting
Shunt
ICH_INTVRMEN
R222
10M_0402_5%~D
LAN / GLAN
CPU
Keep CMOS
Y1
IHDA
Open
CIS
ICH9M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)
ICH_RTCX1
1
SATA
2
4P_0402_50V8B~D
Clear CMOS
2
CMOS setting
2
Shunt
1
CMOS_CLR1
D
Package
9.6X4.06 mm
1 GLAN_DOCK#
10K_0402_5%~D
2
R221
1
1
+3.3V_ALW_ICH
D
@ R220
0_0402_5%~D
1
2
C301
0.1U_0402_16V4Z~D
T41PAD~D
ESATA_ITX_DRX_N4_C
2
ESATA_ITX_DRX_P4_C C303 2
C304
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
AH9
AJ9
AE10
AF10
SATA_ITX_DRX_N3_C
SATA_ITX_DRX_P3_C
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
SATA_CLKN
SATA_CLKP
AH18
AJ18
CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS#
SATARBIAS
AJ7
AH7
2
R247
2
C305 2
C306
ESATA_IRX_DTX_N4_C <33>
ESATA_IRX_DTX_P4_C <33>
ESATA_ITX_DRX_N4 <33>
ESATA_ITX_DRX_P4 <33>
SATA_SBRX_DTX_N3_C <35>
SATA_SBRX_DTX_P3_C <35>
SATA_SBTX_C_DRX_N3 <35>
SATA_SBTX_C_DRX_P3 <35>
B
CLK_PCIE_SATA# <6>
CLK_PCIE_SATA <6>
1
24.9_0402_1%~D
Within 500 mils
ICH9M REV 1.0
HDA SDOUT
0
0
RSVD
0
1
Enter XOR Chain
1
0
Normal Operation (Default)
1
1
Set PCIE port config bit 1
10K_0402_5%~D
@ R248
1K_0402_5%~D
R84
ICH_AZ_SYNC
ICH_AZ_SDOUT
Description
2
ICH RSVD_TP3
1
+3.3V_RUN
XOR Chain Entrance Strap
ICH_AZ_SDOUT
2
2
@
1
1
R96 @
10K_0402_5%~D
1
ICH_RSVD_TP3 <24>
2
@ R249
1K_0402_5%~D
For WLAN detection issue
Pin AH4 , AG5 has weak internal PD
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
ICH9-M(2/4)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Friday, June 13, 2008
Sheet
1
23
of
63
5
4
3
2
1
+3.3V_ALW_ICH
+3.3V_RUN
+3.3V_RUN
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
L29
L28
M27
M26
PERN2
PERP2
PETN2
PETP2
C322 1
C323 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PCIE_IRX_MCARDTX_N3 J29
PCIE_IRX_MCARDTX_P3 J28
PCIE_ITX_MCARDRX_N3 K27
PCIE_ITX_MCARDRX_P3 K26
PERN3
PERP3
PETN3
PETP3
C803 1
C804 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4
PCIE_ITX_EXPRX_P4
PCIE_IRX_MCARDTX_N3
PCIE_IRX_MCARDTX_P3
PCIE_ITX_MCARDRX_N3_C
PCIE_ITX_MCARDRX_P3_C
<29>
<29>
<29>
<29>
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4_C
PCIE_ITX_EXPRX_P4_C
PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6_C
PCIE_ITX_GLANRX_P6_C
C326 1
C327 1
SLP_M#
B16
SIO_SLP_M#
CL_CLK0
CL_CLK1
F24
B19
CL_CLK0 <10>
ICH_CL_CLK1 <34>
CL_DATA0
CL_DATA1
F22
C19
CL_DATA0 <10>
ICH_CL_DATA1 <34>
CL_VREF0
CL_VREF1
C25
A19
+CL_VREF0_ICH
+CL_VREF1_ICH
CL_RST0#
CL_RST1#
F21
D18
CL_RST0#
ICH_CL_RST1#
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
A16
C18
C11
C20
ME_SUS_PWR_ACK
AC_PRESENT
ME_WOL_EN
CLK_PWRGD <6>
CLK_ICH_14M
2
ICH_LAN_RST#
<22> ICH_SPI_CS1#
1
1
0.1U_0402_16V4Z~D
R299
3.3K_0402_5%~D
<33> USB_OC0_1#
8
7
6
5
R301
33_0402_5%~D
SPI_CLK_R1 1
2 ICH_EC_SPI_CLK
SPI_DO_R1 1
2 ICH_EC_SPI_DO
R302
33_0402_5%~D
2
VCC
HOLD#
SCLK
SI
R1042 1
<33> USB_OC2#
<33> ESATA_USB_OC#
E29
E28
F27
F26
PERN5
PERP5
PETN5
PETP5
PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6
PCIE_ITX_GLANRX_P6
C29
C28
D27
D26
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
ICH_EC_SPI_CLK
ICH_SPI_CS0#_R
ICH_SPI_CS1#_R
D23
D24
F23
ICH_EC_SPI_DO
ICH_EC_SPI_DIN
D25
E23
1
1
2
1
R303
22.6_0402_1%~D
0.1U_0402_16V4Z~D
@ R375
3.3K_0402_5%~D
8
7
6
5
http://hobi-elektronika.net
W25X16VSSIG_SO8~D
AG2
AG1
Within 500 mils
PCIE_MCARD1_DET# <34>
ME_SUS_PWR_ACK <38>
AC_PRESENT <38>
ME_WOL_EN <38>
2
@ C312
4.7P_0402_50V8C~D
C
Place closely pin U10.AF3
CLK_ICH_48M
1
+3.3V_ALW_ICH
R285
10_0402_5%~D
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V27
V26
U29
U28
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB27
AB26
AA29
AA28
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
T26
T25
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#
USB
AF29
AF28
DMI_IRCOMP
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
<10>
<10>
<10>
<10>
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
TPM_ID:
H: Enable
L: Disable
C318
8.2P_0402_50V8D~D
2
TPM_ID
R304
100K_0402_5%~D
+3.3V_WLAN
3@
+CL_VREF1_ICH
1
Within 500 mils
1
R292
2
24.9_0402_1%~D
+1.5V_RUN_PCIE_ICH
----->Right Side Top
----->Right Side Bottom
----->Left Side Top
----->Left Side Bottom
----->WLAN
----->WWAN
ICH_SMBDATA 6
----->WPAN
----->EXP Card
+3.3V_M
----->DOCK
----->DOCK
ICH_SMBCLK 3
----->BIO
----->Camera
USBP0- <33>
USBP0+ <33>
USBP1- <33>
USBP1+ <33>
USBP2- <33>
USBP2+ <33>
USBP3- <33>
USBP3+ <33>
USBP4- <34>
USBP4+ <34>
USBP5- <34>
USBP5+ <34>
USBP6- <34>
USBP6+ <34>
USBP7- <32>
USBP7+ <32>
USBP8- <35>
USBP8+ <35>
USBP9- <35>
USBP9+ <35>
USBP10- <36>
USBP10+ <36>
USBP11- <19>
USBP11+ <19>
1
R273
100K_0402_5%~D
4@
2
+3.3V_M
1
+3.3V_M
+CL_VREF0_ICH
1
2
B
MEM_SDATA
MEM_SDATA <16,17>
Q27A
2N7002DW-T/R7_SOT363-6~D
MEM_SCLK
4
Q27B
2N7002DW-T/R7_SOT363-6~D
MEM_SCLK <16,17>
A
DELL CONFIDENTIAL/PROPRIETARY
ICH9M REV 1.0
Compal Electronics, Inc.
2
VCC
HOLD#
SCLK
SI
USBRBIAS
1
2
PERN4
PERP4
PETN4
PETP4
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
@ R279
10_0402_5%~D
+3.3V_RUN
G29
G28
H27
H26
USB_OC0_1#
2 0_0402_5%~D
USB_OC2#
ESATA_USB_OC#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#
USB_OC10#
USB_OC11#
1
2
@
CL_RST0# <10>
ICH_CL_RST1# <34>
1
2
@ R284
10K_0402_5%~D
Place closely pin U10.H1
+3.3V_ALW_ICH
<10,38>
SIO_SLP_M# <38>
2
ICH_CL_PWROK
1
SATA
GPIO
Clocks
ICH_CL_PWROK
R297
2.2K_0402_5%~D
2
R6
R296
2.2K_0402_5%~D
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
R294
33_0402_5%~D
ICH_SPI_CS0#
1
2
1
2
33_0402_5%~D
R295
C328
1
2
@ U13
2
CLPWROK
ICH_RSMRST# <38>
1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
@ R377
3.3K_0402_5%~D
5
CLK_PWRGD
2
C320 1
C321 1
W25X32VSSIG_SO8~D
@
SPI_WP#_SEL 1 R1044 2
0_0402_5%~D
R5
R287
3.24K_0402_1%~D
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
U12
CS#
SO
WP#
GND
CK_PWRGD
ICH_LAN_RST# <38>
1
<34>
<34>
<34>
<34>
Flash ROM
1
2
3
4
ICH_RSMRST#
2
PERN1
PERP1
PETN1
PETP1
+3.3V_LAN
2SPI_DIN_R2
ICH_LAN_RST#
D22
R290
453_0402_1%~D
N29
N28
P27
P26
@ C484
1
2
ICH_SPI_CS1#
ICH_SPI_DIN_R 1
D20
RSMRST#
1
+3.3V_ALW_ICH
8.2K_0402_5%~D
SIO_PWRBTN# <38>
1
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1
R298
3.3K_0402_5%~D
@ R329
33_0402_5%~D
LAN_RST#
2
R275
2
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
200 MIL SO8
SPI_WP#_SEL <37>
SIO_PWRBTN#
C325
0.1U_0402_16V4Z~D
10/100/1G LAN --->
R1043
1
2
0_0402_5%~D
ICH_BATLOW#
R286
3.24K_0402_1%~D
C317 1
C319 1
Express card--->
A
B13
R3
1
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
<34>
<34>
<34>
<34>
10K_1206_8P4R_5%~D
USB_OC9#
1
2
R288
10K_0402_5%~D
USB_OC10#
1
2
R291
10K_0402_5%~D
USB_OC8#
1
2
R293
10K_0402_5%~D
CS#
SO
WP#
GND
BATLOW#
PWRBTN#
2
<34>
<34>
<34>
<34>
<32>
<32>
<32>
<32>
1
2
3
4
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
2
100K_0402_5%~D
2
100K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
100K_0402_5%~D
2
10K_1206_8P4R_5%~D
RP2
USB_OC6#
5
4
USB_OC5#
6
3
USB_OC7#
7
2
USB_OC11#
8
1
ICH_SPI_CS0#
ICH_EC_SPI_DIN 1
2SPI_DIN_R1
R300
33_0402_5%~D
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
DPRSLPVR <10,47>
R289
453_0402_1%~D
BT/UWB--->
+3.3V_LAN
SMB
TP11
ICH_CL_PWROK 1
R250
DPRSLPVR
1
@ R253
ICH_PWRGD
1
R257
ICH_RSMRST# 1
R260
ME_WOL_EN
1
R263
1
B
4
3
2
1
DPRSLPVR
<10,41>
U10D
MiniWLAN (Mini Card 2)--->
USB_OC0_1#
USB_OC2#
ESATA_USB_OC#
USB_OC4#
VRMPWRGD
A20
M7
AJ24
B21
AH20
AJ20
AJ21
M2
DPRSLPVR/GPIO16
T130 PAD~D
ICH_PWRGD
ICH9M REV 1.0
MiniWWAN (Mini Card 1)--->
+3.3V_ALW_ICH
RP1
5
6
7
8
2 ITP_DBRESET#
100K_0402_5%~D
1
@R811
@
R811
D21
SPKR
MCH_ICH_SYNC#
ICH_RSVD_TP3
ICH_TP8
ICH_TP9
ICH_TP10
ICH_PWRGD
2
Option to " Disable "
clkrun. Pulling it
down
will keep the clks
running.
<27> SPKR
<10> MCH_ICH_SYNC#
<23> ICH_RSVD_TP3
PAD~D T50
PAD~D T51
PAD~D T52
ICH_GPIO26
G20
D
1
2
@ R283
10_0402_5%~D
2
WAKE#
SERIRQ
THRM#
ICH_TP11
AG19
AH21
AG21
SIO_EXT_SMI#
A21
C12
CONTACTLESS_DET#
C21
AE18
K1
ICH_GPIO20
AF8
AJ22
SD_DET#
A9
IO_LOOP
D19
SATA_CLKREQ#
L1
AE19
WPAN_RADIO_DIS_MINI# AG22
HDD_DET#
AF21
ICH_GPIO49
AH24
A8
C10
PWROK
HDD_DET#
2
1
2
1
CLKRUN#
2
@
CLKRUN#
IMVP_PWRGD
SIO_EXT_SCI#
TPM_ID
S4_STATE#/GPIO26
T44 PAD~D
SIO_SLP_S3# <37>
SIO_SLP_S4# <38>
SIO_SLP_S5# <38>
R276
10K_0402_5%~D
2
High = No Reboot
1
C316
4700P_0402_25V7K~D
SPKR
1
@ C315
47P_0402_50V8J~D
1
Low = Default
@ C313
47P_0402_50V8J~D
No Reboot Strap
R282
8.2K_0402_5%~D
STP_PCI#
STP_CPU#
2
100K_0402_5%~D
1
100K_0402_5%~D
2
100K_0402_5%~D
1
<34> USB_MCARD2_DET#
A14
E19
E20
M5
AJ23
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
1
R836
2
R760
1
R759
ODD_DET#
C324
0.1U_0402_16V4Z~D
1
R280
1
R281
<34> USB_MCARD1_DET#
+3.3V_RUN
SMBALERT#/GPIO11
H_STP_PCI#
H_STP_CPU#
ICH_PCIE_WAKE#
IRQ_SERIRQ_ICH
RSV_THRM#
C16
E16
G17
PMSYNC#/GPIO0
A17
L4
P1
SLP_S3#
SLP_S4#
SLP_S5#
1394_DET#
CLK_ICH_14M <6>
CLK_ICH_48M <6>
R271
10K_0402_5%~D
2 ICH_EC_SPI_DO
1K_0402_5%~D
1
@ R270
C
2
0_0402_5%~D
<38> SIO_EXT_SMI#
<29> LAN_DISABLE#
<36> CONTACTLESS_DET#
PAD~D T39
2
0_0402_5%~D
PAD~D T132
2
0_0402_5%~D
<31> SD_DET#
<33> IO_LOOP
<6> SATA_CLKREQ#
<26,38> ODD_DET#
PAD~D T48
<26> HDD_DET#
PAD~D T185
SUS_STAT#/LPCPD#
SYS_RESET#
SMB_ALERT#
CLKRUN#
SUSCLK
ICH_SUSCLK
1
1
R277
<37> SIO_EXT_WAKE#
M6
CLK_ICH_14M
CLK_ICH_48M
1
+3.3V_LAN
R4
G19
PM_SYNC#
H1
AF3
CLK14
CLK48
+3.3V_RUN
2
<38> SIO_EXT_SCI#
RI#
SPEAKER_DET# <28>
USB_MCARD3_DET# <34>
1394_DET# <31>
2
PAD~D T45
F19
SUS_STAT#/LPCPD#
ITP_DBRESET#
SPEAKER_DET#
USB_MCARD3_DET#
1394_DET#
5
2
R1028
Stuff = Enable
ICH_RI#
2
8.2K_0402_5%~D
AH23
AF19
AE21
AD20
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SYS GPIO
Power MGT
@
No stuff = Disable
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
MISC
GPIO
Controller Link
iTPM function
R270
G16
A13
E17
C17
B18
PCI-Express
2 SIO_EXT_SCI#
10K_0402_5%~D
1
R272
ICH_SMBCLK
ICH_SMBDATA
ICH_GPIO60
AMT_SMBCLK
AMT_SMBDAT
Direct Media Interface
2 SPEAKER_DET#
100K_0402_5%~D
1
R834
1
R256
U10C
SPI
D
2 ICH_SMBCLK
2.2K_0402_5%~D
2 ICH_SMBDATA
2.2K_0402_5%~D
2 ICH_CL_RST1#
10K_0402_5%~D
2 AMT_SMBCLK
<38> AMT_SMBCLK
10K_0402_5%~D
<38> AMT_SMBDAT
2 AMT_SMBDAT
10K_0402_5%~D
2 ICH_RI#
10K_0402_5%~D
PAD~D T184
2 ICH_PCIE_WAKE#
<7> ITP_DBRESET#
10K_0402_5%~D
1 ME_SUS_PWR_ACK
<10> PM_SYNC#
10K_0402_5%~D
2 SIO_EXT_SMI#
10K_0402_5%~D
2 ICH_GPIO60
<6> H_STP_PCI#
10K_0402_5%~D
<6> H_STP_CPU#
2 SMB_ALERT#
10K_0402_5%~D
<31,37,38> CLKRUN#
2 IO_LOOP
100K_0402_5%~D
<37> ICH_PCIE_WAKE#
2 CONTACTLESS_DET#<31,36,37,38> IRQ_SERIRQ
1
2
100K_0402_5%~D
R122
33_0402_5%~D
LAN_DISABLE#
1
<37,41,47> IMVP_PWRGD
10K_0402_5%~D
1
R252
1
R255
1
@R259
@
R259
1
R262
1
R265
1
R267
1
R268
2
R269
1
R274
1
R787
1
R192
1
R835
1
R963
2 IMVP_PWRGD
2.2K_0402_5%~D
2 MCH_ICH_SYNC#
10K_0402_5%~D
2 RSV_THRM#
8.2K_0402_5%~D
1 IRQ_SERIRQ
10K_0402_5%~D
2 SPKR
1K_0402_5%~D
1
@ R251
1
@ R254
1
R258
2
R261
1
@ R264
@ R380
33_0402_5%~D
SPI_CLK_R2 1
2
SPI_DO_R2
1
2
ICH_EC_SPI_DIN 1
@ R382
ICH_EC_SPI_CLK
ICH_EC_SPI_DO
@ 33_0402_5%~D
R381
2 ICH_SPI_DIN_R
0_0402_5%~D
Follow Daisy Chain and Star
Topology. Place close to U10
pinE23 within 500mils
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
ICH9-M(3/4)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Friday, June 13, 2008
Sheet
1
24
of
63
5
4
3
2
1
2
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
AJ5
VCCUSBPLL
AA7
AB6
AB7
AC6
AC7
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
A10
A11
VCCLAN1_05[1]
VCCLAN1_05[2]
A12
B12
VCCLAN3_3[1]
VCCLAN3_3[2]
A27
VCCGLANPLL
D28
D29
E26
E27
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
A26
VCCGLAN3_3
VCC3_3[1]
AG29
VCC3_3[2]
AJ6
VCC3_3[7]
AC10
+3.3V_RUN
1
VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]
AD19
AF20
AG24
AC20
C349
0.1U_0402_16V4Z~D
1
2
2
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
B9
F9
G3
G6
J2
J7
K7
CORE
VCCHDA
AJ4
VCCSUSHDA
AJ3
VCCSUS1_05[1]
VCCSUS1_05[2]
AC8
F17
VCCSUS1_5[1]
AD8
VCCSUS1_5[2]
F18
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
A18
D16
D17
E22
VCCSUS3_3[5]
AF1
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
VCCCL1_05
G22
VCCCL1_5
G23
VCCCL3_3[1]
VCCCL3_3[2]
A24
B24
2
+3.3V_RUN
1
2
+3.3V/1.5V_RUN_HDA
+3.3V_RUN
1
2
1
2
1
2
TP_VCCSUS1.05_INT_ICH1
T53
TP_VCCSUS1.05_INT_ICH2
VCCSUS1_5_ICH_1
T91
VCCSUS1_5_ICH_2
T122 PAD~D
2
1
2
+3.3V/1.5V_RUN_HDA
+3.3V_RUN
1
1
2
2
1
+3.3V_RUN
R314
0_0603_5%~D
2
1
+1.5V_RUN
@ R315
0_0603_5%~D
Choice to support GMCH
C352
0.1U_0402_16V4Z~D
+3.3V_ALW_ICH
PAD~D
2
1
C357
0.1U_0402_16V4Z~D
+3.3V_ALW_ICH
VCCSUS1_5_ICH_2
1
+3.3V_ALW_ICH
2
1
2
VCCCL1_05_ICH 1
C366
VCCCL1_5
1
2
1
2
C360
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
+3.3V_LAN
1
2
1
2
C369
0.1U_0402_16V4Z~D
2
+3.3V_RUN
AC12
AC13
AC14
AB23
AC23
C355
0.1U_0402_16V4Z~D
2
1
VCC1_5_A[21]
VCC1_5_A[22]
V_CPU_IO[1]
V_CPU_IO[2]
1
C368
1U_0603_10V4Z~D
2
1
C373
4.7U_0603_6.3V6M~D
1
C372
2.2U_0603_6.3V6K~D
A
C371
10U_0805_4VAM~D
L17
1UH_20%_0805~D
VCC1_5_A[20]
G10
G9
+VCC_DMI_ICH
+1.05V_VCCP
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
VSS_NCTF[1]
VSS_NCTF[2]
VSS_NCTF[3]
VSS_NCTF[4]
VSS_NCTF[5]
VSS_NCTF[6]
VSS_NCTF[7]
VSS_NCTF[8]
VSS_NCTF[9]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
D
C
B
ICH9M REV 1.0
GLAN POWER
+1.5V_RUN
2
VCC1_5_A[18]
VCC1_5_A[19]
AC21
+VCCDMIPLL
2
1
R312
1_0603_1%~D
5ohm@100MHz
1
2
+1.05V_VCCP
L15
BLM18PG181SN1_0603~D
C354
0.1U_0402_16V4Z~D
+VCCGLANPLL
1
VCC1_5_A[17]
R29
W23
Y23
2
+1.5V_RUN
+VCCDMIPLL_R
C363
0.1U_0402_16V4Z~D
+1.5V_RUN
AC9
AC18
AC19
2
C353
0.1U_0402_16V4Z~D
VCCLAN1.05_INT_ICH
1
2
C370
0.1U_0402_16V4Z~D
VCC1_5_A[9]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
USB CORE
2
C367
0.1U_0402_16V4Z~D
1
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
1
VCC_DMI[1]
VCC_DMI[2]
C362
0.022U_0402_16V7K~D
2
+3.3V_LAN
C365
0.1U_0402_16V4Z~D
1
2
C364
0.1U_0402_16V4Z~D
1
VCC1_5_A[1]
VCC1_5_A[2]
VCC1_5_A[3]
VCC1_5_A[4]
VCC1_5_A[5]
VCC1_5_A[6]
VCC1_5_A[7]
VCC1_5_A[8]
L14
BLM18PG181SN1_0603~D
1
2
VCCDMIPLL
C361
0.022U_0402_16V7K~D
B
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
ATX
2
C359
1U_0603_10V4Z~D
1
VCCSATAPLL
ARX
2
C358
1U_0603_10V4Z~D
1
AJ19
1
MMBD4148-7-F_SOT23-3~D
C346
0.1U_0402_16V4Z~D
2
1
C351
1U_0603_10V4Z~D
C350
10U_0805_4VAM~D
1
2
2
C347
0.1U_0402_16V4Z~D
C
1
1
C348
0.1U_0402_16V4Z~D
+1.5V_RUN_SATAPLL
L16
10UH_LB2012T100MR_20%_0805~D
1
2
VCCA3GP
+1.5V_RUN
2
C345
0.1U_0402_16V4Z~D
C342
1U_0603_10V6K~D
1
2
10_0805_5%~D
C344
4.7U_0603_6.3V6M~D
2
VCCP_CORE
ICH_V5REF_SUS
1
VCC1_5_B[1]
VCC1_5_B[2]
VCC1_5_B[3]
VCC1_5_B[4]
VCC1_5_B[5]
VCC1_5_B[6]
VCC1_5_B[7]
VCC1_5_B[8]
VCC1_5_B[9]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
C343
4.7U_0603_6.3V6M~D
1
D16
RB751S40T1_SOD523-2~D
2
R313
100_0402_5%~D
V5REF_SUS
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
PCI
1
2
1
2
2
V5REF
VCCPSUS
1
VCC1_05[1]
VCC1_05[2]
VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]
VCC1_05[7]
VCC1_05[8]
VCC1_05[9]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
+1.05V_VCCP_D 1
3
C341
10U_0805_4VAM~D
2
AE1
VCCPUSB
1
A6
ICH_V5REF_SUS
VCCRTC
C334
0.1U_0402_16V4Z~D
2
R310
1
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C340
0.01U_0402_16V7K~D
2
+3.3V_ALW_ICH
1
ICH_V5REF_RUN
C339
2.2U_0603_6.3V6K~D
+
1
+1.05V_VCCP
C338
22U_0805_6.3V6M~D
1
C337
22U_0805_6.3V6M~D
C336
220U_D2_4VY_R15M~D
C335
1U_0603_10V6K~D
+1.5V_RUN
2
U10F
A23
+1.5V_RUN_PCIE_ICH
L13
+1.5V_RUN_PCIE_ICH
1
2
BLM21PG600SN1D_0805~D
D
+5V_ALW
2
+1.5V_RUN
ICH_V5REF_RUN
1
2
2
U10E
+1.05V_VCCP
D14
C333
0.1U_0402_16V4Z~D
D15
RB751S40T1_SOD523-2~D
1
C332
0.1U_0402_16V4Z~D
2
R311
100_0402_5%~D
1
C331
0.1U_0402_16V4Z~D
+3.3V_RUN
C330
1U_0603_10V4Z~D
+5V_RUN
1
2
+RTC_CELL
A
ICH9M REV 1.0
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL")
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
CONTAINS CONFIDENTIAL
THIS DOCUMENT MAY NOT
OF DELL. IN ADDITION,
DISCLOSED TO ANY THIRD
Title
ICH8(4/4)
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
2
Sheet
1
25
of
63
5
4
3
2
1
D
D
+5VMOD Source
+15V_ALW
GND1
GND2
14
15
2
<37> MODC_EN
1
TYCO_1759920-3
R319
100K_0402_5%~D
Pleace near ODD CONN
Main SATA +5V Default
2
R323
100K_0402_5%~D
2
Main SATA +5V Default
4
1
2
5
6
4
1
1
2
5
6
2
2
@ PAD-OPEN 4x4m
Open
B
+5V_HDD Source
+3.3V_ALW
1
2
5
6
2
1
1
3
4
1
+5V_RUN
PJP25
1
2
2
<37> HDDC_EN
FOX_LD2122H-S4SL6_RV
Pleace near HDD CONN
2
1
23
24
+5V_HDD
R322
100K_0402_5%~D
GND1
GND2
S
C383
10U_0805_10V4Z~D
5
D Q32
SI3456BDV-T1-E3_TSOP6~D
G
3
C382
0.1U_0603_50V4Z~D
2
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
HDD_EN_5V
Q34B
2N7002DW-T/R7_SOT363-6
2
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
R320
100K_0402_5%~D
R321
100K_0402_5%~D
Q34A
2N7002DW-T/R7_SOT363-6
1
HDD_DET#
+5V_HDD
@ C388
0.1U_0402_10V7K~D
2
<24> HDD_DET#
@ C387
0.1U_0402_16V4Z~D
2
1
@ C386
10U_0805_10V4Z~D
2
1
C385
0.1U_0402_16V4Z~D
1
C384
1000P_0402_50V7K~D
B
+3.3V_HDD
+3.3V_HDD
+3.3V_ALW2
2
close SATA connector
+5V_HDD
PSATA_IRX_DTX_N0
PSATA_IRX_DTX_P0
6
1 0.01U_0402_16V7K~D
1 0.01U_0402_16V7K~D
2
@ PAD-OPEN 4x4m
+5V_ALW
GND
RX+
RXGND
TXTX+
GND
1
C380 2
C381 2
1
2
+15V_ALW
1
<23> PSATA_IRX_DTX_N0_C
<23> PSATA_IRX_DTX_P0_C
1
2
3
4
5
6
7
+5V_RUN
P2
1
HDD PWR
JSATA2
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0
+5V_MOD
C
For HDD
<23> PSATA_ITX_DRX_P0
<23> PSATA_ITX_DRX_N0
2
4
C
1
1
2
3
2
6
5
S
R318
100K_0402_5%~D
DP
+5V
+5V
MD
GND
GND
Q31A
2N7002DW-T/R7_SOT363-6
8
9
10
11
12
13
3
C379
10U_0805_10V4Z~D
close SATA connector
D Q29
SI3456BDV-T1-E3_TSOP6~D
G
2 MOD_EN
1
<23> SATA_ODD_IRX_DTX_P1_C
1 SATA_ODD_IRX_DTX_N1
0.01U_0402_16V7K~D
1 SATA_ODD_IRX_DTX_P1
0.01U_0402_16V7K~D
ODD_DET#
<24,38> ODD_DET#
+5V_MOD
2
C374
2
C375
R316
100K_0402_5%~D
R317
100K_0402_5%~D
C378
0.1U_0603_50V4Z~D
2
<23> SATA_ODD_IRX_DTX_N1_C
GND
RX+
RXGND
TXTX+
GND
Q31B
2N7002DW-T/R7_SOT363-6
1
C377
0.1U_0402_16V4Z~D
2
C376
1000P_0402_50V7K~D
1
1
2
3
4
5
6
7
1
JSATA1
SATA_ODD_ITX_DRX_P1
SATA_ODD_ITX_DRX_N1
<23> SATA_ODD_ITX_DRX_P1
<23> SATA_ODD_ITX_DRX_N1
2
+3.3V_ALW2
+5V_MOD
+5V_ALW
1
For ODD
D @ Q131
SI3456BDV-T1-E3_TSOP6~D
G
3
1
1
@ R974
100K_0402_5%~D
2
+3.3V_RUN
PJP42
@ C1020
10U_0805_10V4Z~D
1
+3.3V_HDD
2
4
S
2
@ PAD-OPEN 4x4m
Short
+3.3V_HDD Source
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
ODD/HDD CONNECTOR
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
26
of
63
2
1
XTALO_12MHZ
+3.3V_RUN
1
DCVDD
AVDD
HPVDD
DBVDD
DVSS
AVSS
HPVSS
4
19
15
AGND
24
LLINEIN
LOUT
ROUT
16
17
AUD_DOCK_MIC_IN_L_C
AUD_DOCK_MIC_IN_R_C
23
RLINEIN
C481 1000P_0402_50V7K~DDAI_SMBCLK
DAI_SMBDATA
28
27
SCLK
SDIN
LHPOUT
RHPOUT
13
14
NC_LHPOUT
NC_RHPOUT
XTALI_12MHZ
XTALO_12MHZ
1
2
MCLK/XTI
XTO/ POR
CLKOUT
6
I2S_12MHZ
BCLK
HDA_SDI_CODEC
5
HDA_SDO
DMIC1/VOL_DN/GPIO2
AUD_DOCK_MIC_IN_L
AUD_DOCK_MIC_IN_R
C409
16
17
30
NC
NC
NC
18
19
20
AUD_DOCK_HP_OUT_L
AUD_DOCK_HP_OUT_R
47
SPDIF_OUT_0_1/EAPD/GPIO0
<51> SPDIF_OUT
48
SPDIF_OUT_0
2
2
2
0.22U_0805_16V7K
2
2
200_0402_5%~D
AUD_DOCK_MIC_IN_L_C
AUD_DOCK_MIC_IN_R_C
200_0402_5%~D
DAI_SMBCLK
200_0402_5%~D
2 AUD_DOCK_HP_L_R
2 AUD_DOCK_HP_R_R
R342
200_0402_5%~D
Place close to U16
1
1
AGND
92HD71B7A5NLGXB3X8_QFN48_7x7~D
@ R344
47_0402_5%~D
1
2
Layout Skill
AGND short to GND
2
1
2
U17
16
1A
1Y#
3
I2S_LRCLK
4
2A
2Y#
5
DAI_LRCK# <35>
6
3A
3Y#
7
DAI_DO# <35>
@ SPEAKER SET
DAA00000R0L
Description
PCB 03P LA-4051P REV0 M/B
<37> EN_I2S_NB_CODEC
2
1
R345
1K_0402_5%~D
5Y#
11
14
6A
1
15
OE1#
OE2#
+3.3V_RUN
6Y#
13
GND
8
DAI_12MHZ# <35>
I2S_DI#
+3.3V_RUN
1
R354
100K_0402_5%~D
U18
A
2
D20
DA204U_SOT323-3~D
@
1
2
4
G
Y
3
1
@
1
4
A
+3.3V_RUN
2
2
2
+3.3V_RUN
3
2
2
1
2
2
Y
U19
A
74LVC1G14GV_SOT753-5~D
@
2
DAI_DI <35>
74LVC1G14GV_SOT753-5~D
@
<33>
<37> DOCK_HP_DET
2
5
1
Q40A
2N7002DW-T/R7_SOT363-6~D
4
4
1
AUD_MIC_SWITCH
6
1
1
1
2
2
6
3
1
1
2
5
Q38B
2N7002DW-T/R7_SOT363-6~D
5A
@
2
Q38A
2N7002DW-T/R7_SOT363-6~D
1
C420
1000P_0402_50V7K~D
R355
100K_0402_5%~D
R352
39.2K_0402_1%~D
+3.3V_RUN
R351
20K_0402_1%~D
<28,33,37> AUD_HP_NB_SENSE
12
C419
0.1U_0402_16V7K~D
AUD_SENSE_B
+3.3V_RUN
R353
100K_0402_5%~D
2
C417
1000P_0402_50V7K~D
R349
20K_0402_1%~D
R348
39.2K_0402_1%~D
R350
100K_0402_5%~D
1
+VDDA
R347
5.11K_0402_1%~D
2
1
C418
0.1U_0402_16V7K~D
AUD_SENSE_A
+3.3V_RUN
4Y#
1
5
Place closely to Pin 34
R346
5.11K_0402_1%~D
2
1
Place closely to Pin 13.
4A
9
CD74HC366M96_SO16~D
+VDDA
A
10
DAI_BCLK# <35>
2
Part Number
VCC
2
3
2
CKG_SMBDAT <6,38,48>
I2S_BCLK
I2S_12MHZ
@C416
@C416
0.1U_0402_10V7K~D
3
Q36B
2N7002DW-T/R7_SOT363-6~D
+3.3V_RUN
I2S_DO
1
CKG_SMBCLK <6,38,48>
1
1
2
4
+3.3V_RUN
1U_0603_10V6K~D
C414
26
42
AVSS
AVSS
Thermal PAD GND
AUD_PC_BEEP
CAP2
VREFFILT
6
Q36A
2N7002DW-T/R7_SOT363-6~D
@ D55
DA204U_SOT323-3~D
33
27
1
@ D19
DA204U_SOT323-3~D
CAP2
VREFFILT
DVSS
49
ICH_AZ_CODEC_SDOUT
MONO_OUT
+3.3V_RUN
@ D18
DA204U_SOT323-3~D
7
12
32
2
@ D17
DA204U_SOT323-3~D
Close to U16 pin5
GPIO5
GPIO6
SPDIF_OUT_1/GPIO7
PC_BEEP
C413
0.1U_0402_16V7K~D
43
44
45
10U_0805_10V6K~D
C415
@C412
@
C412
10P_0402_50V8J~D
T61PAD~D
AGND
C406
4.7U_0603_6.3V6M~D
AGND
For next version I2S.
will disconnect SMBUS
and PU.
Need check the PU
value.
AGND
2
B
SSM2602_LFCSP28_5X5~D
1
DAI_SMBDATA
1
<28> AUD_EAPD
R1092
0.22U_0805_16V7K
R340
1 AUD_DOCK_HP_L_C 1
1 AUD_DOCK_HP_R_C 1
C411
1
PORT_F_L
PORT_F_R
GPIO3
R1091
1
1
2
@ R343
10_0402_5%~D
1U_0805_16V7K~D
1 DOCK_MIC_IN_L_C
1 DOCK_MIC_IN_R_C
1U_0805_16V7K~D
2
2
C410
ICH_AZ_CODEC_BITCLK
29
5
14
15
31
1
PORT_E_L
PORT_E_R
GPIO4/VREFOUT_E
C408
DMIC0/VOL_UP/GPIO1
Thermal Pad
NC
P
4
I2S_LRCLK
NC_ADCLRC
G
<19> DMIC0
C485
150P_0402_50V8J~D
1000P_0402_50V7K~D
C329
AUD_LINE_OUT_L <28>
AUD_LINE_OUT_R <28>
DMIC_CLK
VMID
+3.3V_RUN
C124/C329
close to U16
AGND
2
CSB
20
3
Close to U16 pin6
PORT_D_L
PORT_D_R
1
Select I2C (low)& SPI
(high)interface
26
3
2
46
2
1
35
36
92HD71B
L75
BLM18BB221SN1D_0603~D
1
2 DMIC_CLK_R
<19> DMIC_CLK
23
24
29
9
11
R335
2.2K_0402_5%~D
EMC Solution
PORT_C_L
PORT_C_R
VREFOUT_C
AUD_EXT_MIC_L <33>
AUD_EXT_MIC_R <33>
+VREFOUT
C124
1000P_0402_50V7K~D
AGND
1
2
2
HDA_RST#
10M_0402_5%~D
HDA_SYNC
11
2
10
<23> ICH_AZ_CODEC_RST#
Close to U16 pin3
@
2
R330
10K_0402_5%~D
1
R334
2.2K_0402_5%~D
C407
0.1U_0402_10V7K~D
<23> ICH_AZ_CODEC_SYNC
I2S_DI#
I2S_DO
DACLRC
ADCLRC
2
8
MODE
I2S_BCLK
8
10
3
ICH_AC_SDIN0_R
2
33_0402_5%~D
ICH_AZ_CODEC_SDOUT
25
7
DACDAT
ADCDAT
1
+3.3V_RUN
R331
10K_0402_5%~D
AUD_HP_OUT_L <28>
AUD_HP_OUT_R <28>
10M_0402_5%~D
R309
1
2
<23> ICH_AZ_CODEC_SDOUT
MICIN
MICBIAS
2
1
AUD_SENSE_A
AUD_SENSE_B
R308
1
R332
<23> ICH_AZ_CODEC_SDIN0
+3.3V_RUN
22
21
3
HDA_BITCLK
NC_MICIN
NC_MICBIAS
2
6
PAD~D T59
PAD~D T60
1
PORT_B_L
PORT_B_R
VREFOUT_B
21
22
28
R1077
10K_0402_5%~D
@
T56 PAD~D
T57 PAD~D
2
39
41
37
C392/C481
close to U15
3
PORT_A_L
PORT_A_R
NC
+3.3V_RUN
AUD_DOCK_HP_R_R
2
2
13
34
1
R333
10K_0402_5%~D
ICH_AZ_CODEC_BITCLK
<23> ICH_AZ_CODEC_BITCLK
2
SENSE_A
SENSE_B
AGND
SSM2602
3
18
12
5
R1077 Reserve for SSM2603
1
Close to U16 pin1 & pin9
1
25
38
AVDD
AVDD
2
U15
1
DVDD_CORE
DVDD_CORE
NC/OTP
DVDD_IO
2
1
SSM2602 change new version
1
5
1
9
40
3
2
1
1
2
U16
C401
0.1U_0402_10V7K~D
2
1
+3.3V_RUN
@ C400
10U_0805_10V6K~D
2
1
C399
0.1U_0402_10V7K~D
1
C405
0.1U_0402_10V7K~D
C404
1U_0603_10V6K~D
2
@ C403
10U_0805_10V6K~D
C402
1000P_0402_50V7K~D
2
B
1
1
C392 1000P_0402_50V7K~D
AGND
AUD_DOCK_HP_L_R
1
2
+3.3V_RUN
1
2
2
2
+VDDA
2
+3.3V_RUN_I2S_AVDD
AGND
2
AGND
2
1
1
1
R328
10K_0402_5%~D
@
@
NC
P
1
2
2
C393
0.1U_0402_16V7K~D
47UH_CBMF1608T470K_10%~D
1
C483
0.1U_0402_16V7K~D
1
C391
4.7U_0603_6.3V4Z~D
2
C396
0.1U_0402_16V7K~D
TRACE>15 mil
1
2
+3.3V_RUN_I2S_AVDD
L72
C395
4.7U_0603_6.3V4Z~D
AUD_PC_BEEP
2
C398
0.1U_0402_16V7K~D
<38> BEEP
1
2
499K_0402_1%~D
2
499K_0402_1%~D
+3.3V_RUN
C995
27P_0402_50V8J~D
<24> SPKR
2
1
0.1U_0402_16V4Z~D R327
2
1
0.1U_0402_16V4Z~D R828
C994
27P_0402_50V8J~D
1
C389
1
C394
L18
BLM18EG601SN1D_2P~D
+3.3V_RUN_I2S_VDD
1
XTALI_12MHZ
2
12MHZ_18PF_1Y712000CE1J~D
1
1
2
2
2
0_0402_5%~D
Y5
1
1
R786
1
R762
DOCK_MIC_DET <37>
Q40B
2N7002DW-T/R7_SOT363-6~D
2
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
2
Azalia (HD) Codec
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
1
Sheet
27
of
63
5
4
3
2
1
+5V_SPK_AMP
5
C421
1
2
1
A
0.1U_0402_10V7K~D
4
Y
B
@R357
@
R357
1
P
2
G
AUD_NB_MUTE
AUD_HP_NB_SENSE
2
Speaker Connector
0_0402_5%~D
U20
74AHCT1G08GW_SOT353-5~D
JSPK1
15 mils trace
3
<27,33,37> AUD_HP_NB_SENSE
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
D
<24> SPEAKER_DET#
5
0.1U_0402_10V7K~D
AUD_HP_EN
4
Place Close to Audio Chip
8
18
SPVDD
SPVDD
30
INT_SPK_L1
2
SPKR_RIN+
LOUT-
7
INT_SPK_L2
ROUT+
20
INT_SPK_R1
ROUT-
19
INT_SPK_R2
HP_OUTL
16
HP_SPK_L1
HP_OUTR
15
HP_SPK_R1
GAIN0
31
AUD_GAIN1
GAIN1
32
AUD_GAIN2
2
1K_0402_5%~D
HP_INR_C
26
HP_INR
2
2
2
1
2
1
2
7
8
GND
GND
D
MOLEX_53780-0670~D
24
BYPASS
HP_INL
Gain Setting
+5V_SPK_AMP
CPVDD
1
R368
29
1
R362 0_0402_5%~D
1
2
1
2
C443
0.033U_0402_16V7K~D
2
SPKR_RIN-
SET
1
1
CPGND
2
2
RUN_ON
REG_OUT
2
C1N
11
SGND
SPGND
SPGND
TP
12
28
5
21
33
C1N
HPVSS
CPVSS
C1P
14
13
1
10
4
@
2
1
1
RUN_ON <19,37,40,41>
2
1
C448
1U_0603_10V6K~D
2
C1P
TPA6040A4RHBR_QFN32_5X5~D
R367
100K_0402_5%~D
@
+CPVSS
2
1
8mil
AUD_AMP_MUTE#
C450
2
1U_0603_10V6K~D
0_0402_5%~D
R365
100K_0402_5%~D
See Note 2
@
SPKR_LIN-
2
HPVDD
9
1
2
AUD_GAIN2
C447
1U_0603_10V6K~D
R363
1M_0402_1%~D
2
1
17
AUD_GAIN1
1
REG_EN
2
25
See Note 1
HP_SPK_R1 <33>
2
AUD_AMP_MUTE#
C449
0.033U_0402_16V7K~D
1
HP_EN
R366
0_0402_5%~D
1
22
R361
100K_0402_5%~D
/SPKR_EN
AUD_HP_EN
HP_SPK_L1 <33>
@ R360
100K_0402_5%~D
23
C446
1U_0603_10V6K~D
1
AUD_SPK_ENABLE#
C445
1U_0603_10V6K~D
C444
10U_0805_10V6K~D
+5V_SPK_AMP
2
2
1U_0603_10V6K~D
@ R359
100K_0402_5%~D
2
1
C438
R358
100K_0402_5%~D
2
1
@C442
@
C442
47P_0402_50V8J~D
1
@C441
@
C441
47P_0402_50V8J~D
2
@C440
@
C440
47P_0402_50V8J~D
1
1
C
+5V_SPK_AMP
2
6
27
2
1
LOUT+
HP_INL_C
1
6
SPKR_LIN+
2
1K_0402_5%~D
@C439
@
C439
47P_0402_50V8J~D
1
2
1
C436
R818
10U_1206_25VAK~D
1
2
1
C437
R827
10U_1206_25VAK~D
+5V_SPK_AMP
AUD_SPK_ENABLE#
VDD
3
2
2
R364
100K_0402_5%~D
3
SPKR_INR_C
1
1
1
2
3
4
5
6
0 .033U_0805_50V7K~D
1
B
SPKR_INL_C
1
C433
10U_0805_10V6K~D
<27> AUD_HP_OUT_R
0 .033U_0805_50V7K~D
2
2
C432
1U_0603_10V6K~D
C
1
U22
1
C431
10U_0805_10V6K~D
<27> AUD_HP_OUT_L
2
2
C430
1U_0603_10V6K~D
1
<27> AUD_LINE_OUT_R
1
1
C429
0.1U_0402_10V7K~D
2
C435
2
C428
1U_0603_10V6K~D
2
C427
1U_0603_10V6K~D
C434
1
1
W=40mils
+5V_SPK_AMP
74AHCT1G08GW_SOT353-5~D
U21
1
<27> AUD_LINE_OUT_L
Place Close to Audio Chip
G
Y
B
+5V_SPK_AMP
P
A
@ C426
100P_0402_50V8J~D
1
@ C425
100P_0402_50V8J~D
2
@ C424
100P_0402_50V8J~D
AUD_EAPD
<27> AUD_EAPD
L19
BLM21PG600SN1D_0805~D
1
2
+5V_RUN
@ C423
100P_0402_50V8J~D
+5V_SPK_AMP
C422
1
2
1
2
3
4
5
6
+VDDA
MINIMAM 150 mA
See Note 1
GAIN1
GAIN2
AV(inv)
INPUT
IMPEDANCE
B
0
0
6dB
82K ohm
0
1
10dB
66K ohm
1
0
15.6dB
45K ohm
1
1
21.6dB
26K ohm
See Note 2
2
<27> AUD_EAPD
*
See Note 2
1
Q42A
2N7002DW-T/R7_SOT363-6~D
3
See Note 2
R362
5
<37> AUD_NB_MUTE
*
@
R366
C443
C449
R367
@
R368
@
4
Q42B
2N7002DW-T/R7_SOT363-6~D
TPA6040
@
9789A
@
@
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
AMP and PHONE JACK
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
28
of
63
5
4
3
2
1
D
D
16
17
LAN_TX3LAN_TX3+
VDDO_33_3
VDDO_33_46
AVDD_33_28
3
46
28
DVDD_10_5
DVDD_10_8
DVDD_10_33
DVDD_10_38
5
8
33
38
+1V_LAN_M
AVDD_18_11
AVDD_18_14
AVDD_18_19
AVDD_18_18
AVDD_18_24
AVDD_18_25
AVDD_18_41
AVDD_18_54
AVDD_18_32
AVDD_18_30
11
14
19
18
24
25
41
54
32
30
+1.8V_LAN_M
CTRL18
CTRL10
29
31
RESERVED_NC
51
GND_PAD
57
2
1
1
2
1
2
1
2
1
1
2
1
2
+1.8V_LAN_M
T155
T156
T157
T158
T159
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
1
2
+1V_LAN_M
1
2
1
VOUT = 1.204 (1+R1/R2),
where R1 = R960 + R961, R2 = R962
+LOM_VCT
+3.3V_LAN
Q101
2
VIN
GND
EN
VOUT
5
ADJ
4
TPS73601
2
MMBT3906WT1G_SC70-3~D
R959
10K_0402_5%~D
DOCKED
2
1
2
R961
39.2K_0402_1%~D
1
2
<30,37> DOCKED
1
R960
4.64K_0402_1%
Q103
C1011
4.7U_0603_6.3V4Z~D
Follow 82567 schematic
chiplist that VCC_1.0 for
external use 10uF XR5 *2 and
0.1uF *2
for internal use 4.7uF X5R *2
and 0.1uF *3
C1010
4.7U_0603_6.3V4Z~D
1
1
2
3
C1012
0.1U_0402_16V4Z~D
C1025
0.1U_0402_16V4Z~D
1
2
C1024
0.1U_0402_16V4Z~D
2
2
C479
0.1U_0402_16V4Z~D
2
1
C478
4.7U_0805_10V4Z~D
1
C477
4.7U_0805_10V4Z~D
MA use internal 1V,NOT external solutions.
82567LM:
B0 version: 1.05V
A1 version: 1V
B
1
JTAG_TDO_LAN
JTAG_TDI_LAN
JTAG_TMS_LAN
JTAG_TCK_LAN
JTAG_TRST_LAN
2
35
40
39
7
6
2
2
Q45
BCP69_SOT223~D
C476
27P_0402_50V8J~D
Need to ensure
crystal at least
300uW max power
drive-level
2
1
C473
470P_0402_50V7K~D
REGCTL_PNP18
82567LM_QFN56~D
2
1
Trace=12mil
1
C472
470P_0402_50V7K~D
1
C475
27P_0402_50V8J~D
XTAL2
XTAL1
XTALI
2
Y2
25MHZ_18PF_1BX25000CK1D~D
TEST_EN
1
C471
4.7U_0603_6.3V4Z~D
2
B
XTALO
2
0_0402_5%~D
LAN_DISABLE_N
REGCTL_PNP18
C470
0.1U_0402_16V4Z~D
37
1
C474
10U_0805_10V4Z~D
1
DIS_REG10
36
2
10K_0402_5%~D
XTALO
9
XTALI
10
<37> LAN_DISABLE#_R
1
R379
34
2
1
R374
5.1K_0402_5%~D
C469
0.1U_0402_16V4Z~D
<24> LAN_DISABLE#
1K_0402_5%~D
1
2
@ R1004
0_0402_5%~D
1
R378
1
2
+1.8V_LAN_M
Trace=12mil
C468
0.1U_0402_16V4Z~D
1
IEEE_TEST_P
IEEE_TEST_N
1
2
+3.3V_LAN_R
C467
10U_0805_10V4Z~D
2
12
13
1
2
C
C466
10U_0805_10V4Z~D
R376
LAN_TEST_P
LAN_TEST_N
2
0_0402_5%~D
1
2
+3.3V_LAN
C465
0.1U_0402_16V4Z~D
1
@ R373
RSET
1
<40> ENAB_3VLAN
3
15
1
4.99K_0402_1%~D
2
R372
LED_0
LED_1
LED_2
JTAG_TRST
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
4
2
1
<30> LOM_ACTLED_YEL#
<30> LOM_SPD100LED_ORG#
<30> LOM_SPD10LED_GRN#
2
2
1
C
2
1
1
JRXD_0
JRXD_1
JRXD_2
1
+3.3V_LAN
Q44
STS11NF30L_SO8~D
1
2
3
1
47
48
49
+3.3V_LAN
8
7
6
5
2
<23> LAN_RX0
<23> LAN_RX1
<23> LAN_RX2
1
LAN_TX3- <30>
LAN_TX3+ <30>
2
3
JTXD_0
JTXD_1
JTXD_2
C464
4.7U_0603_6.3V4Z~D
42
43
44
C463
0.1U_0402_16V4Z~D
<23> LAN_TX0
<23> LAN_TX1
<23> LAN_TX2
2
LAN_TX2- <30>
LAN_TX2+ <30>
2
4
JKCLK
JRSTSYNC
4
MDI_N_3
MDI_P_3
2 LAN_CLK_R 45
33_0402_5%~D 50
1
LAN_TX1- <30>
LAN_TX1+ <30>
1
MDI_N_2
MDI_P_2
LAN_TX2LAN_TX2+
R371
2_1210_5%~D
LAN_TX1LAN_TX1+
20
21
2
22
23
C459
0.1U_0402_16V4Z~D
MDI_N_1
MDI_P_1
C458
0.1U_0402_16V4Z~D
GLAN_RXP
GLAN_RXN
C457
4.7U_0603_6.3V4Z~D
55
56
+3.3V_ALW
LAN_TX0- <30>
LAN_TX0+ <30>
C456
4.7U_0603_6.3V4Z~D
LAN_TX0LAN_TX0+
C455
10U_0805_10V4Z~D
26
27
1
R369
MDI_N_0
MDI_P_0
C454
0.1U_0402_16V4Z~D
<23> LAN_CLK
<23> LAN_RSTSYNC
GLAN_TXP
GLAN_TXN
C453
4.7U_0603_6.3V4Z~D
<24> PCIE_ITX_GLANRX_P6_C
<24> PCIE_ITX_GLANRX_N6_C
52
53
R370
1 PCIE_IRX_GLANTX_N6_C
0.1U_0402_10V7K~D
2_1210_5%~D
2
C452
2
<24> PCIE_IRX_GLANTX_N6
Layout Notice : Place as close
chip as possible.
U23
B
1 PCIE_IRX_GLANTX_P6_C
0.1U_0402_10V7K~D
E
2
C451
C
<24> PCIE_IRX_GLANTX_P6
R962
36.5K_0402_1%~D
A
2
A
Intel proposal add external LDO for RJ45:
MB:2.5V,
DELL CONFIDENTIAL/PROPRIETARY
Dock:2.65V
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
LAN-82567LM
Size
Document Number
Date:
Friday, June 06, 2008
Rev
1.0
LA-4051P
Sheet
1
29
of
63
5
4
3
2
1
D
D
+3.3V_LAN
LAN ANALOG
SWITCH
56
50
38
27
18
10
4
1
U25
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
1
2
C462
0.1U_0402_16V4Z~D
2
C461
0.1U_0402_16V4Z~D
1
C460
0.1U_0402_16V4Z~D
2
<29> LAN_TX0<29> LAN_TX0+
<29> LAN_TX1<29> LAN_TX1+
<29> LAN_TX2<29> LAN_TX2+
C
<29> LAN_TX3<29> LAN_TX3+
<29,37> DOCKED
LAN_TX0LAN_TX0-R
1
2
L20
22NH_0603CS-360EJTS_5%_0603~D
LAN_TX0+ 1
LAN_TX0+R
2
L21
22NH_0603CS-360EJTS_5%_0603~D
2
3
0B1
1B1
48
47
SW_LAN_TX0SW_LAN_TX0+
A1
2B1
3B1
43
42
SW_LAN_TX1SW_LAN_TX1+
A2
4B1
5B1
37
36
SW_LAN_TX2SW_LAN_TX2+
SW_LAN_TX3SW_LAN_TX3+
A0
LAN_TX1LAN_TX1-R
1
2
L22
22NH_0603CS-360EJTS_5%_0603~D
LAN_TX1+ 1
LAN_TX1+R
2
L23
22NH_0603CS-360EJTS_5%_0603~D
7
8
A3
6B1
7B1
32
31
LAN_TX2LAN_TX2-R
1
2
L24
22NH_0603CS-360EJTS_5%_0603~D
LAN_TX2+ 1
LAN_TX2+R
2
L25
22NH_0603CS-360EJTS_5%_0603~D
11
A4
12
A5
0LED1
1LED1
2LED1
22
23
52
LAN_ACTLED_YEL_R#
LED_10_GRN_R#
LED_100_ORG_R#
LAN_TX3LAN_TX3-R
1
2
L26
22NH_0603CS-360EJTS_5%_0603~D
LAN_TX3+ 1
LAN_TX3+R
2
L27
22NH_0603CS-360EJTS_5%_0603~D
14
A6
0B2
1B2
46
45
DOCK_LOM_TRD0DOCK_LOM_TRD0+
15
A7
2B2
3B2
41
40
DOCK_LOM_TRD1DOCK_LOM_TRD1+
DOCKED
17
SEL
4B2
5B2
35
34
DOCK_LOM_TRD2DOCK_LOM_TRD2+
19
20
54
LED0
LED1
LED2
6B2
7B2
30
29
DOCK_LOM_TRD3DOCK_LOM_TRD3+
0LED2
1LED2
2LED2
25
26
51
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_SPD100LED_ORG#
Layout Notice : Place bead as
close PI3L500 as possible
<29> LOM_ACTLED_YEL#
<29> LOM_SPD10LED_GRN#
<29> LOM_SPD100LED_ORG#
5
NC
SW_LAN_TX1- <33>
SW_LAN_TX1+ <33>
SW_LAN_TX2- <33>
SW_LAN_TX2+ <33>
SW_LAN_TX3- <33>
SW_LAN_TX3+ <33>
LAN_ACTLED_YEL_R# <33>
LED_10_GRN_R# <33>
LED_100_ORG_R# <33>
C
DOCK_LOM_TRD0- <35>
DOCK_LOM_TRD0+ <35>
DOCK_LOM_TRD1- <35>
DOCK_LOM_TRD1+ <35>
DOCK_LOM_TRD2- <35>
DOCK_LOM_TRD2+ <35>
DOCK_LOM_TRD3- <35>
DOCK_LOM_TRD3+ <35>
DOCK_LOM_ACTLED_YEL# <35>
DOCK_LOM_SPD10LED_GRN# <35>
DOCK_LOM_SPD100LED_ORG# <35>
PAD_GND
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
57
SW_LAN_TX0- <33>
SW_LAN_TX0+ <33>
PI3L500-AZFEX_TQFN56~D
FROM NIC
DOCKED
TO
DOCK
1
6
9
13
16
21
24
28
33
39
44
49
53
55
1: TO DOCK
0: TO RJ45
+3.3V_LAN
1
2
2
2
@R394
@
R394
10K_0402_5%~D
@R393
@
R393
10K_0402_5%~D
@R392
@
R392
10K_0402_5%~D
1
B
1
B
LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
LAN TRANSFOMER
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
30
of
63
5
4
3
2
1
U26A
CBS_SPK
1
W14
V14
close to U26
F4
R7
TPAP0
TPAN0
TPBP0
TPBN0
TPBIAS0
CPS
VREF
REXT
XI
XO
FIL0
USB TEST
R417
10K_0402_1%~D
1
C513
0.01U_0402_16V7K~D
2
2
B
B12
A12
B13
A13
D12
D11
D13
B14
A16
B16
A14
1394 I/F
TPAP0
TPAN0
TPBP0
TPBN0
TPBIAS0
CPS
CBVREF
CBREXT
R5C847XI
R5C847XO
INT &
AUDIO
UDIO3
UDIO4
USBDM
USBDP
TEST1
TEST2
CD1#/CCD1#
CD2#/CCD2#
VS1#/CVS1
VS2#/CVS2
T14
D15
R16
H16
CBS_CCD1#
CBS_CCD2#
CBS_CVS1
CBS_CVS2
CDATA14
CDATA2
CADR18
VPPEN0
VPPEN1
VCC5EN#
VCC3EN#
W18
C19
N16
V13
W13
R13
T13
CBS_DATA14
CBS_DATA2
CBS_DATA18
VPPEN0
VPPEN1
VCC5EN#
VCC3EN#
B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8
SDCD#/MMCCD#
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
1
2
1
2
1
1
2
2
2
Z3008
2
1
2
1
C494
270P_0402_50V7K~D
<24> 1394_DET#
<37> PWR_BTN_BD_DET#
<42> SNIFFER_BLUE
<42> SNIFFER_YELLOW
<38> SNIFFER_PWR_SW#
<37> WIRELESS_ON#/OFF
<37,38> INSTANT_ON_SW#
<38,39> POWER_SW#_MB
<42>
BREATH_BLUE_LED_IO
R407
<37,42> LID_CL#
5.1K_0402_1%~D
+3.3V_ALW
R401
56.2_0402_1%~D
1
Close to U26
CBS_CC/BE3# <32>
CBS_CC/BE2# <32>
CBS_CC/BE1# <32>
CBS_CC/BE0# <32>
CBS_CPAR <32>
CBS_CFRAME# <32>
CBS_CTRDY# <32>
CBS_CIRDY# <32>
CBS_CSTOP# <32>
CBS_CDEVSEL# <32>
CBS_CBLOCK# <32>
CBS_CPERR# <32>
CBS_CSERR# <32>
CBS_CREQ# <32>
CBS_CGNT# <32>
CBS_CSTSCHNG <32>
CBS_CCLKRUN# <32>
CBS_CAUDIO <32>
must have clean layout
TYCO_2-1734820-0_20P-T
1
+3.3V_RUN
CBS_CCLK <32>
CBS_DATA14 <32>
CBS_DATA2 <32>
CBS_DATA18 <32>
2
CBS_CCD1#
1
2
CBS_CCD2#
2
C1038
270P_0402_50V7K~D
VCC3IN
13
15
VCC5IN
VCC5IN
VPPEN0
VPPEN1
3
4
EN0
EN1
VCC3EN#
VCC5EN#
2
1
VCC3_EN
VCC5_EN
1
1
5
16
C1039
270P_0402_50V7K~D
FLG
GND
NC
NC
NC
R416/C397
close to R5C847
2
C397
33P_0402_50V8J~D
For MMC PLUS
+3.3V_RUN_CARD
EN
OUT
GND
OC#
1
2
3
TPS2051BDBVR_SOT23-5~D
2
1
Close to JP5 pin5
1
2
2
IN
4
1
1
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
G1
G2
A
TYCO_1-1775737-6
Close to JP5 pin5
R5C847XI
2
DELL CONFIDENTIAL/PROPRIETARY
X3
24.576MHz_16P_1BG24576CKIA~D
1
1
PCI_CBS_TERM 2
4.7P_0402_50V8C~D
C517
5
MMCDAT5
SDCMD/MMCCMD
MMCDAT4
SDDAT3/MMCDAT3
SDDAT2/MMCDAT2
R413
150K_0402_5%~D
5
CARD_PWR
C506
1U_0603_10V4Z~D
http://hobi-elektronika.net
JSD1
SD_DET#
SDWP#
SDCD#/MMCCD#
SDDAT1/MMCDAT1
SDDAT0/MMCDAT0
MMCDAT7
MMCDAT6
<24> SD_DET#
2
22P_0402_50V8J~D
C515
2
1
1
R784
100K_0402_5%~D
1
C505
0.01U_0402_16V7K~D
C516
1U_0603_10V4Z~D
2
7
6
10
2
2
+3.3V_ALW_ICH
1
0_0402_5%~D
2 SDCLK/MMC_CLK_R
27_0402_5%
1
2
1
C514
27P_0402_50V8J~D
2
1
B
MDIO07
2
SDCMD/MMCCMD R414
SDCLK/MMCCLK
1
SDDAT0/MMCDAT0 R416
SDDAT1/MMCDAT1
SDDAT2/MMCDAT2
SDDAT3/MMCDAT3
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
C509
0.1U_0402_16V4Z~D
R420
100K_0402_5%~D
R418
10_0402_5%~D
2
1
2
2 100K_0402_5%~D
100K_0402_5%~D
CBUS_GRST#
1
+CBS_VPP
8
SDCLK/MMC_CLK_R
1
R411 1
@R412
@
R412
2
R5531V002-E2-FA_SSOP16~D
U28
A
1
2
SDWP#
CARD_PWR
+3.3V_RUN
VPPEN0
SDCLK/MMCCLK
9
14
12
1
+3.3V_RUN_CARD
+3.3V_RUN
VCCOUT
VCCOUT
VCCOUT
VPPOUT
R5C847-CSP208Q_CSP208~D
CLK_PCI_PCM
+CBS_VCC
U27
11
+5V_RUN
1
CBS_CRST# <32>
1
2
@ C501
0.01U_0402_16V7K~D
CBS_CCD1# <32>
CBS_CCD2# <32>
CBS_CVS1 <32>
CBS_CVS2 <32>
GND1
GND2
C
2
R410
22_0402_5%~D
CBS_CINT# <32>
21
22
2
INTA#
INTB#
INTC#
UDIO0/SRIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
RI_OUT#/PME#
SPKROUT#
R403
56.2_0402_1%~D
D
@ C497
10U_0805_10V4Z~D
J2
K4
K2
J4
H1
H2
H4
H5
G1
G4
F1
<22> PCI_PIRQD#
<22> PCI_PIRQB#
<22> PCI_PIRQC#
<24,36,37,38> IRQ_SERIRQ
TPBP0
TPBN0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C496
0.1U_0402_16V4Z~D
GBRST#
PCIRST#
PCICLK
CLKRUN#
HWSPND#
JS1394
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
@ C500
0.01U_0402_16V7K~D
G2
L4
K1
L5
F2
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CPAR
CBS_CFRAME#
CBS_CTRDY#
CBS_CIRDY#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CBLOCK#
CBS_CPERR#
CBS_CSERR#
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CCLK_R
CBS_CINT#
CBS_CRST#
CBS_CAUDIO
2
C499
0.1U_0402_16V4Z~D
CBUS_GRST#
PCI_RST#
CLK_PCI_PCM
CLKRUN#
CB_HWSPND#
<22> PCI_RST#
<6> CLK_PCI_PCM
<24,37,38> CLKRUN#
<37> CB_HWSPND#
F16
K18
P15
V19
N15
K16
L16
K15
M16
L18
N19
N18
G16
G19
M15
E18
A18
L19
M18
H19
F19
2
1
C498
1U_0402_6.3V6K~D
REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
REG#/CCBE3#
CADR12/CCBE2#
CADR8/CCBE1#
CE1#/CCBE0#
CADR13/CPAR
CADR23/CFRAME#
CADR22/CTRDY#
CADR15/CIRDY#
CADR20/CSTOP#
CADR21/CDEVSEL#
CADR19
CADR14/CPERR#
WAIT#/CSERR#
INPACK#/CREQ#
WE#/CGNT#
BVD1/CSTSCHG
WP/CCLKRUN#
CADR16/CCLK
READY/CINT#
RESET/CRST#
BVD2/CAUDIO
TPAP0
TPAN0
1
C495
1U_0402_6.3V6K~D
M4
M5
V3
V4
W4
T5
V5
W5
T6
RST&
CLK
PAR
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IDSEL
CBS_CAD13
TPBIAS0
1
C
V6
T9
W6
W2
P2
P1
CBS_CAD15
CBS_CAD31 <32>
CBS_CAD30 <32>
CBS_CAD29 <32>
CBS_CAD28 <32>
CBS_CAD27 <32>
CBS_CAD26 <32>
CBS_CAD25 <32>
CBS_CAD24 <32>
CBS_CAD23 <32>
CBS_CAD22 <32>
CBS_CAD21 <32>
CBS_CAD20 <32>
CBS_CAD19 <32>
CBS_CAD18 <32>
CBS_CAD17 <32>
CBS_CAD16 <32>
CBS_CAD15 <32>
CBS_CAD14 <32>
CBS_CAD13 <32>
CBS_CAD12 <32>
CBS_CAD11 <32>
CBS_CAD10 <32>
CBS_CAD9 <32>
CBS_CAD8 <32>
CBS_CAD7 <32>
CBS_CAD6 <32>
CBS_CAD5 <32>
CBS_CAD4 <32>
CBS_CAD3 <32>
CBS_CAD2 <32>
CBS_CAD1 <32>
CBS_CAD0 <32>
C685
0.1U_0402_16V4Z~D
PCI_AD17
PCI_PAR
<22> PCI_PAR
PCI_C_BE0#
<22> PCI_C_BE0#
PCI_C_BE1#
<22> PCI_C_BE1#
PCI_C_BE2#
<22> PCI_C_BE2#
PCI_C_BE3#
<22> PCI_C_BE3#
CBS_IDSEL
1
2
R409
100_0402_5%~D
PCI_REQ1#
<22> PCI_REQ1#
PCI_GNT1#
<22> PCI_GNT1#
PCI_FRAME#
<22> PCI_FRAME#
PCI_IRDY#
<22> PCI_IRDY#
PCI_TRDY#
<22> PCI_TRDY#
PCI_DEVSEL#
<22> PCI_DEVSEL#
PCI_STOP#
<22> PCI_STOP#
PCI_PERR#
<22> PCI_PERR#
PCI_SERR#
<22> PCI_SERR#
Media Card I/F
CPS
2
0_0402_5%~D
UDIO4
2
10K_0402_5%~D
PCI I/F
1
R404
1
R406
B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14
C493
0.33U_0603_10V7K~D
+3.3V_RUN_PHY
CDATA10/CAD31
CDATA9/CAD30
CDATA1/CAD29
CDATA8/CAD28
CDATA0/CAD27
CADR0/CAD26
CADR1/CAD25
CADR2/CAD24
CADR3/CAD23
CADR4/CAD22
CADR5/CAD21
CADR6/CAD20
CADR25/CAD19
CADR7/CAD18
CADR24/CAD17
CADR17/CAD16
IOWR#/CAD15
CADR9/CAD14
IORD#/CAD13
CADR11/CAD12
OE#/CAD11
CE2#/CAD10
CADR10/CAD9
CDATA15/CAD8
CDATA7/CAD7
CDATA13/CAD6
CDATA6/CAD5
CDATA12/CAD4
CDATA5/CAD3
CDATA11/CAD2
CDATA4/CAD1
CDATA3/CAD0
C492
0.01U_0402_16V7K~D
D
CB_HWSPND#
2
10K_0402_5%~D
CBS_SPK
2
100K_0402_5%~D
UDIO3
2
10K_0402_5%~D
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
R399
56.2_0402_1%~D
1
R400
1
R402
1
R405
W12
V12
T12
W11
V11
T11
W9
V9
R9
W8
V8
T8
R8
W7
V7
T7
V1
U1
U2
T1
T2
R1
R2
R4
P4
P5
N1
N2
N4
N5
M1
M2
R398
56.2_0402_1%~D
+3.3V_RUN
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
16 bit PC card I/F
R5C847-CSP208Q
<22> PCI_AD[0..31]
2
R421
R5C847XO
1
0_0402_5%~D
Close to Pin A16,B16
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
CardBus Controller(R5C847)
Size
3
2
Rev
1.0
LA-4051P
Date:
4
Document Number
Thursday, June 05, 2008
Sheet
1
31
of
63
5
4
3
2
1
+3.3V_RUN
C528
1000P_0402_50V7K~D
C527
1000P_0402_50V7K~D
2
+1.5V_CARD
D
+1.5V_RUN
DIGITAL
GND
ANALOG
GND
3.3Vin
3.3Vin
3.3Vout
3.3Vout
3
5
@
1
R657
1
R683
1
R684
1
R790
2
100K_0402_5%~D
2
0_0402_5%~D
2
100K_0402_5%~D
2
100K_0402_5%~D
6
AUX_IN
SHDN#
PERST#
EXPRCRD_STBY_R#
1
STBY#
NC
EXPRCRD_PWREN#
10
CPPE#
GND
CPUSB#
9
18
<37> EXPRCRD_PWREN#
+3.3V_CARDAUX
19
OC#
20
1
2
15
AUX_OUT
SYSRST#
2
8
1
16
2
7
1
2
1
2
C788
10U_0805_6.3V6M~D
2
4
2
C781
0.1U_0402_16V4Z~D
11
13
C356
0.1U_0402_16V4Z~D
1.5Vout
1.5Vout
+3.3V_CARD
1
2
C1041
10U_0805_10V4Z~D
@
<37> EXPRCRD_STDBY#
A10
A11
B10
B11
C1
D1
E12
NC
NC
NC
NC
NC
NC
NC
PLTRST1#
<10,22,51> PLTRST1#
@
NC
1.5Vin
1.5Vin
1
C1040
10U_0805_10V4Z~D
+3.3V_SUS
2
U52
12
14
C801
0.1U_0402_16V4Z~D
NC
NC
NC
NC
NC
NC
NC
2
17
A9
B9
D9
D14
A15
B15
AGND
AGND
AGND
AGND
AGND
AGND
2
1
C314
0.1U_0402_16V4Z~D
D10
E1
C2
D2
E2
L2
E4
C
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
2
1
C997
0.1U_0402_16V4Z~D
E10
E11
A17
B17
1
J1
J5
K5
E9
R10
T10
V10
W10
L15
M19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
C999
0.1U_0402_16V4Z~D
+3.3V_RUN
C135
0.1U_0402_16V4Z~D
+3.3V_RUN_PHY
VCC_3V
VCC_3V
VCC_3V
VCC_3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_RIN
VCC_RIN
VCC_ROUT
VCC_ROUT
VCC_MD3V
C134
0.1U_0402_16V4Z~D
R5C847-CSP208Q
F5
G5
J19
K19
W3
R11
R12
R6
E13
L1
E14
A4
ANALOG
POWER
2
2
1
1
DIGITAL
POWER
2
1
2
1
+3.3V_SUS
C540
0.01U_0402_16V7K~D
2
1
C539
0.47U_0402_16V4Z~D
2
1
C538
0.01U_0402_16V7K~D
2
1
C537
0.47U_0402_16V4Z~D
2
1
C536
0.1U_0402_10V7K~D
1
C535
0.01U_0402_16V7K~D
2
C534
0.01U_0402_16V7K~D
C533
10U_0805_10V4Z~D
2
1
2
1
U26B
+3.3V_RUN
1
1
C526
0.1U_0402_16V4Z~D
2
+3.3V_RUN_PHY
C525
0.1U_0402_16V4Z~D
2
1
C524
10U_0805_10V4Z~D
1
2
C776
0.01U_0402_16V7K~D
2
1
C530
0.01U_0402_16V7K~D
2
1
C523
0.01U_0402_16V7K~D
2
1
C529
0.01U_0402_16V7K~D
2
1
2
C532
0.01U_0402_16V7K~D
1
C531
10U_0805_10V4Z~D
+3.3V_RUN
2
1
C522
0.01U_0402_16V7K~D
2
D
1
C521
0.01U_0402_16V7K~D
1
C520
0.01U_0402_16V7K~D
2
C519
10U_0805_10V4Z~D
1
+3.3V_RUN L28
BLM21A601SPT_0805~D
1
2
CPUSB#
RCLKEN
CARD_RESET#
R5538_QFN20~D
C
Express Card
R5C847-CSP208Q_CSP208~D
+1.5V_CARD: Max. 650mA, Average 500mA
+3.3V_CARD: Max. 1300mA, Average 1000mA
<31> CBS_CAD[0..31]
+3.3V_ALW
<31> CBS_CC/BE1#
<31> CBS_CPAR
<31> CBS_CPERR#
<31> CBS_CGNT#
<31> CBS_CINT#
+CBS_VCC
+CBS_VPP
<31> CBS_CCLK
<31> CBS_CIRDY#
<31> CBS_CC/BE2#
B
GND7
GND8
71
72
CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_DATA14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13
CBS_CAD15
CBS_CAD16
CBS_DATA18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#
CBS_CCD1# <31>
+1.5V_CARD
CBS_DATA14 <31>
1
@
1
R791
2
0_0402_5%~D
CBS_CVS1 <31>
2
CBS_DATA18 <31>
CBS_CBLOCK# <31>
CBS_CSTOP# <31>
CBS_CDEVSEL# <31>
+CBS_VCC
+CBS_VPP
CBS_CTRDY# <31>
CBS_CFRAME# <31>
1
@ R792
1 1
<24> USBP7-
2
0_0402_5%~D
2 2
<24> USBP7+
4
L64
3
USBP7_DUSBP7_D+
3
EXP_SMBCLK
EXP_SMBDATA
DLW21SN900SQ2_0805~D
<34,37> PCIE_WAKE#
+3.3V_CARDAUX
CBS_CVS2 <31>
CBS_CRST# <31>
CBS_CSERR# <31>
CBS_CREQ# <31>
CBS_CC/BE3# <31>
CBS_CAUDIO <31>
CBS_CSTSCHNG <31>
1
2
+3.3V_CARD
<6> EXPCLK_REQ# EXPRCRD_PWREN#
1
CBS_CCD2# <31>
+3.3V_SUS
PCMCIA CAGE
Description
+CBS_VPP
PCB 03P LA-4051P REV0 M/B
Part Number
DAA00000R0L
Description
PCB 03P LA-4051P REV0 M/B
2
1
2
@
SD CABLE
Part Number
DAA00000R0L
Description
Close to JCBUS1 Pin18/52
2
1
2
Close to JCBUS1 pin51,17
PCB 03P LA-4051P REV0 M/B
http://hobi-elektronika.net
5
1
C543
10U_0805_10V4Z~D
EXPRESS CAGE
C542
0.01U_0402_16V7K~D
@
C541
0.01U_0402_16V7K~D
1
<34,38> CARD_SMBDAT
+CBS_VCC
C769
0.1U_0402_10V7K~D
DAA00000R0L
1
2
Part Number
A
6
1
1
2
MOLEX_48315-0012_RT
<6> CLK_PCIE_EXP#
<6> CLK_PCIE_EXP
<24> PCIE_IRX_EXPTX_N4
<24> PCIE_IRX_EXPTX_P4
<24> PCIE_ITX_EXPRX_N4_C
<24> PCIE_ITX_EXPRX_P4_C
EXP_SMBDATA
Q112A
2N7002DW-T/R7_SOT363-6
+3.3V_SUS
5
@
PCB 03P LA-4051P REV0 M/B
R127
2.2K_0402_5%~D
DAA00000R0L
Description
R126
2.2K_0402_5%~D
Part Number
<34,38> CARD_SMBCLK
3
Q112B
2N7002DW-T/R7_SOT363-6
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND1
GND2
GND3
GND4
USBDUSBD+
CPUSB#
RESERVE1
RESERVE2
SMBCLK
SMBDATA
+1.5V_1
+1.5V_2
WAKE#
+3.3VAUX
PERST#
+3.3V_1
+3.3V_2
+3.3V_3
CLKREQ#
CPPE#
NC
REFCLKREFCLK+
GND5
GND6
GND7
GND8
PERN0
PERP0
GND9
GND10
GND11
GND12
PETN0
PETP0
GND13
GND14
GND15
GND16
41
42
GND17
GND18
B
A
HRS_FH28-40S-0.5SH(05)
EXP_SMBCLK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
CardBus/SD card Socket
Size
3
2
Document Number
Rev
1.0
LA-4051P
Date:
4
PCIE_WAKE#
CARD_RESET#
2
IO FPC
JEXP1
<37> EXPRCRD_DET#
CPUSB#
4
2
@
R947
100K_0402_5%~D
1
GND5
GND6
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
C790
0.1U_0402_16V4Z~D
69
70
GND3
CCD1#
CAD2
CAD4
CAD6
CB_D14
CAD8
CAD10
CVS1
CAD13
CAD15
CAD16
CB_D18
CBLOCK#
CSTOP#
CDEVSEL#
VCC
VPP2
CTRDY#
CFRAME#
CAD17
CAD19
CVS2
CRST#
CSERR#
CREQ#
CCBE3#
CAUDIO
CSTSCHG
CAD28
CAD30
CAD31
CCD2#
GND4
C789
0.1U_0402_16V4Z~D
<31> CBS_DATA2
<31> CBS_CCLKRUN#
CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27
CBS_CAD29
CBS_DATA2
CBS_CCLKRUN#
GND1
CAD0
CAD1
CAD3
CAD5
CAD7
CCBE0#
CAD9
CAD11
CAD12
CAD14
CCBE1#
CPAR
CPERR#
CGNT#
CINT#
VCC
VPP1
CCLK
CIRDY#
CCBE2#
CAD18
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
CB_D2
CCLKRUN#
GND2
C802
0.1U_0402_16V4Z~D
<31> CBS_CC/BE0#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
2
JCBUS1
CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#
Wednesday, June 11, 2008
Sheet
1
32
of
63
5
4
3
2
1
+5V_ESATA
1
+
U29
1
2
3
4
+5V_ALW_FUSE
<37> ESATA_USB_PWR_EN#
GND
IN
EN1#
EN2#
OC1#
OUT1
OUT2
OC2#
ESATA_USB_OC#
8
7
6
5
ESATA_USB_OC# <24>
2
TPS2062ADR_SO8~D
1
2
JESA1
USBP3_DUSBP3_D+
1
2
3
4
USBP2_DUSBP2_D+
5
6
7
8
+5V_CHGUSB
C548
0.1U_0402_16V4Z~D
1
+
C588
+5V_CHGUSB
1
2
2
SATA_ITX_DRX_P4_C
SATA_ITX_DRX_N4_C
SATA_IRX_DTX_N4_C
U53
1
2
3
4
+5V_ALW_FUSE
<37> USB_POWERSHARE_PWR_EN#
C549
GND
IN
EN1#
EN2#
OC1#
OUT1
OUT2
OC2#
8
7
6
5
USB_OC2#
SATA_IRX_DTX_P4_C
USB_OC2# <24>
C550
2
C1021
1U_0402_6.3V6K~D
2
1
R987 @ 0_0402_5%~D
2
1
<38> EN_CELL_CHARGER_DET#
<37> CELL_CHARGER_DET#
TPS2062ADR_SO8~D
1SATA_IRX_DTX_N4
4700P_0402_25V7K~D
1SATA_IRX_DTX_P4
4700P_0402_25V7K~D
2
+1.8V_RUN
D67
1 RB751S40T1_SOD523-2~D
2
R1037
+3.3V_ALW2
100K_0402_5%~D
1
2
A_VCC
A_DA_D+
A_GND
B_VCC
B_DB_D+
B_GND
modify pin18,19 drill
150U_D_6.3VM_R15M~D
2
C547
10U_1206_16V4Z~D
2
C546
0.1U_0402_16V4Z~D
1
D
PJP26
PAD-OPEN 4x4m
2
1
C545
0.1U_0402_16V4Z~D
1
+5V_ESATA
+5V_ALW
USB PORT#
C544
150U_D_6.3VM_R15M~D
@ FUSE1
L0603
1
2
USB
9
10
11
12
13
14
15
GND
A+
ESATA
AGND
BB+
GND
16
17
DET1
DET2
18
19
20
21
G1
G2
G3
G4
R1047
R1048
R1051
R1052
C
@
@
2
2
2
2
34
13
SEL0_A
SEL0_B
33
14
SEL1_A
SEL1_B
1
1
2 0_0402_5%~D
2 0_0402_5%~D
32
15
SEL2_A
SEL2_B
1
1
2 0_0402_5%~D
2 0_0402_5%~D
31
16
SEL3_A
SEL3_B
1
1
EN_A
EN_B
19
IREF
2 0_0402_5%~D
2 0_0402_5%~D
11
12
AO+
AO-
27
26
BIBI+
21
22
2
2
SATA_ITX_DRX_P4
2
2
C1052
SATA_ITX_DRX_N4
2
SATA_IRX_DTX_N4_C C488
SATA_IRX_DTX_P4_C
2
2
1
17
18
@
@
R1070
R1071
1
1
2 0_0402_5%~D
2 0_0402_5%~D
SD_A
SD_B
36
35
@
@
R1072
R1073
1
1
2 0_0402_5%~D
2 0_0402_5%~D
USBP2_D+_SW
4
2
JESA1 (Ext Left Side Bottom)
3
JESA1 (Ext Left Side TOP)
4
WLAN
5
WWAN
6
WPAN
7
Express card
8
DOCKING
9
DOCKING
1 R1046 2
470_0402_5%~D
SATA_ITX_DRX_N4
10
USH->BIO
11
Camera
GND
GND
GND
GND
AGND
25
20
9
4
24
PAD
37
<36> FP_USBD+
1
<36> FP_USBD-
4
4
Equalizer Selection
SEL0_ [A:B] SEL1_ [A:B]
no equalization
0
0
0
1
[0:2.5dB] @ 1.6 GHz
USBP2_D-
1
0
[2.5:4.5dB] @ 1.6 GHz
USBP2_D+
1
1
[4.5:6.5dB] @ 1.6 GHz
1
2
FP_USB_D-
3
3
2
0_0402_5%~D
2
0_0402_5%~D
Fingerprint CONN.
+5V_RUN
Compliance Channel
FP_USB_D+
3
3
1
2
3
4
5
6
1
2
3
4
5
6
GND
GND
7
8
<36> FP_RESET#
2
0_0402_5%~D
+3.3V_RUN
+5V_BIO
FP_USB_DFP_USB_D+
BIO_RESET#
1
2
@ R910
0_0603_5%~D
2
0_0402_5%~D
SEL2_ [A:B]
B
@ L31
DLW21SN121SQ2L_4P~D
1 1
2 2
USBP3+
<24> USBP3+
4
4
3
1x
1
1.2x
Place close to
JBIO1.1
2
0_0402_5%~D
1
R427
2
0_0402_5%~D
<24> USBP2+
1
2
C623
0.1U_0402_16V4Z~D
+5V_ALW
<24> IO_LOOP
R1074
1
2 0_0402_5%~D
R1075
1
2 0_0402_5%~D
UPEK --> 5V
AUTHENTEC -->3.3V
FP FPC
Part Number
DAA00000R0L
Description
PCB 03P LA-4051P REV0 M/B
+3.3V_SUS
U54 @
DETECT_GND
8
VCC
NC
7
6
HSD-
D-
5
HSD+
D+
3
GND
4
2
AUD_EXT_MIC_L <27>
AUD_EXT_MIC_R <27>
+VREFOUT
AUD_MIC_SWITCH <27>
LAN_ACTLED_YEL_R# <30>
LED_10_GRN_R# <30>
LED_100_ORG_R# <30>
+3.3V_SUS
+LOM_VCT
USB_SIDE_EN# <37>
USB_OC0_1# <24>
ICH_AZ_MDC_BITCLK
<23>
1
OE#
1
@ U30
1
USBP2_D-_SW
USBP2_D+
2
USBP2_D+_SW
GND IO2
3
IO1
4
VIN
USBP2_D2
+5V_CHGUSB
PRTR5V0U2X_SOT143-4~D
@ U55
TS3USB31RSER_QFN8_1P5X1P5~D
USBP3_D+
Change Layout Placement to Close SB
1
GND IO2
3
2
IO1
4
VIN
USBP3_D-
+LOM_VCT
Place close
to JIO1.35
+5V_ALW
R326
10K_0402_5%~D
HP_SPK_L1 <28>
HP_SPK_R1 <28>
1
2
ICH_AZ_MDC_RST1#
@ RJ11 CABLE
3
Q35
Part Number
Description
2N7002W-7-F_SOT323-3~D
R325
DAA00000R0L PCB 03P LA-4051P REV0 M/B
100K_0402_5%~D
@
MDC FPC
Part Number
DAA00000R0L
TYCO_1759898-1
Place close
to JIO1.36
+3.3V_LAN
2
0_0402_5%~D
1
<23> ICH_AZ_MDC_RST#
ICH_AZ_MDC_SDOUT <23>
ICH_AZ_MDC_SYNC <23>
ICH_AZ_MDC_SDIN1 <23>
AUD_HP_NB_SENSE <27,28,37>
2
+VREFOUT
PRTR5V0U2X_SOT143-4~D
Place ESD diodes as close as USB connector.
1
@ R324
1
+5V_ESATA
1
ICH_AZ_MDC_RST1#
Place close
to JIO1.13
Description
1
2
A
Place close
to JIO1.30
PCB 03P LA-4051P REV0 M/B
DELL CONFIDENTIAL/PROPRIETARY
<37> MDC_RST_DIS#
Compal Electronics, Inc.
Title
update pad
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
USB 2.0 PORT
Size
4
3
2
Document Number
Rev
1.0
LA-4051P
Date:
5
B
+3.3V_SUS
1
<24> USBP1+
<24> USBP1-
+3.3V_RUN
PRTR5V0U2X_SOT143-4~D
2
<24> USBP0+
<24> USBP0A
FP_USB_D+
C634
0.1U_0402_16V4Z~D
+3.3V_LAN
4
VIN
C768
0.1U_0402_16V4Z~D
<30> SW_LAN_TX0<30> SW_LAN_TX0+
3
IO1
C712
0.1U_0402_16V4Z~D
<30> SW_LAN_TX1+
<30> SW_LAN_TX1-
GND IO2
2
C711
0.1U_0402_16V4Z~D
<30> SW_LAN_TX2<30> SW_LAN_TX2+
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
pop U51 per 02/22 email (ESD team)
JIO1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
-3.5dB
@
Left side USB Port
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
0dB
1
FP_USB_D-
USBP3_D+
3
1
R426
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
0
1
2
R1002
0_0402_5%~D
USBP3_D-
<24> USBP2-
<30> SW_LAN_TX3+
<30> SW_LAN_TX3-
*
De-emphasis
2
<24> USBP3-
0
2
BIO_RESET#
S
USBP3-
SEL3_ [A:B]
Swing
1
+5V_RUN
U51
Output De-emphasis Adjustment
D
1
R424
Output Swing Control
2
G
1
R425
+3.3V_RUN
JBIO1
TYCO_1734242-6
4
D
C
@ L29
DLW21SN121SQ2L_4P~D
1
2 2
1
R422
1
R423
*
@ L30
DLW21SN121SQ2L_4P~D
1
2 2
JUSB1 (Ext Right Side Bottom)
SATA_ITX_DRX_P4
PI2EQX3201BZFE_TQFN36_6X5~D
USBP2_D-_SW
1
SATA_ITX_DRX_P4_C
1
4700P_0402_25V7K~D
SATA_ITX_DRX_N4_C
1
4700P_0402_25V7K~D
OUT+
OUT-
CLKIN+
CLKIN-
2
JUSB1 (Ext Right Side Top)
C770
0.1U_0402_16V4Z~D
1
1
30
29
2 470_0402_5%~D
1
6
10
23
28
5
1
0
C1015
0.1U_0402_16V4Z~D
R1068
R1069
2 5.1K_0402_1%~D
2 5.1K_0402_1%~D
VDD
VDD
VDD
VDD
VDD
AVDD
1
C510
0.1U_0402_16V4Z~D
BO+
BO-
C508
0.1U_0402_16V4Z~D
AI+
AI-
7
8
R1055
R1056
R305 1
@
+1.8V_RUN
1
2
3
R1053
R1054
R306
R307
+1.8V_RUN
C504
1
1
1
1
2 ESATA_IRX_DTX_P4
0.01U_0402_16V7K~D
2 ESATA_IRX_DTX_N4
0.01U_0402_16V7K~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
1
C507
0.1U_0402_16V4Z~D
C491
<23> ESATA_IRX_DTX_N4_C
1
1
C489
0.1U_0402_16V4Z~D
<23> ESATA_ITX_DRX_P4
<23> ESATA_ITX_DRX_N4
<23> ESATA_IRX_DTX_P4_C
1
C490
0.1U_0402_16V4Z~D
1
U72
C1054
10U_1206_16V4Z~D
TYCO_1759562-1
DESTINATION
Friday, June 13, 2008
Sheet
1
33
of
63
5
4
3
2
1
+3.3V_WLAN
R437
100K_0402_5%~D
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
<24> PCIE_ITX_WANRX_N1_C
<24> PCIE_ITX_WANRX_P1_C
PCIE_MCARD2_DET#
<22> PCIE_MCARD2_DET#
C
54
2
GND2
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
WWAN_RADIO_DIS#
PLTRST3# <22,36>
USBP5_DUSBP5_D+
USB_MCARD2_DET#
LED_WWAN_OUT#
1
USB_MCARD2_DET# <24>
LED_WWAN_OUT# <42>
@ C552
33P_0402_50V8J~D
For WIMAX LED debug
2
<24> ICH_CL_CLK1
<24> ICH_CL_DATA1
<24> ICH_CL_RST1#
+3.3V_RUN
1
100K_0402_5%~D
2
100K_0402_5%~D
+1.5V_RUN
PCIE_MCARD1_DET#
<24> PCIE_MCARD1_DET#
1
R448
2
0_0402_5%~D
+3.3V_WLAN
2
1
2
6
2
5
UIM_VPP
UIM_DATA
UIM_CLK
+3.3Vaux
+1.5V
1000
+-9%
330
+-9%
500
+-5%
2
+
2
2
3
1
2
375
SRV05-4.TCT_SOT23-6~D
2
1
2
PCIE_WAKE#
2 0_0402_5%~D
2 0_0402_5%~D
MINI3CLK_REQ#
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
R454 1
R455 1
<6> MINI3CLK_REQ#
CLK_PCIE_MINI3#
CLK_PCIE_MINI3
<6> CLK_PCIE_MINI3#
<6> CLK_PCIE_MINI3
HOST_DEBUG_RX
MSCLK
PCIE_IRX_MCARDTX_N3
PCIE_IRX_MCARDTX_P3
<24> PCIE_IRX_MCARDTX_N3
<24> PCIE_IRX_MCARDTX_P3
Normal
PCIE_ITX_MCARDRX_N3_C
PCIE_ITX_MCARDRX_P3_C
<24> PCIE_ITX_MCARDRX_N3_C
<24> PCIE_ITX_MCARDRX_P3_C
PCIE_MCARD3_DET#
<22> PCIE_MCARD3_DET#
250 (Wake enable)
5 (Not wake enable)
+3.3V_RUN
+1.5V_RUN
NA
2
2
1
R438
2
100K_0402_5%~D
USB_MCARD1_DET#
@
1
R741
2PCIE_MCARD1_DET#
0_0402_5%~D
1
WLAN_RADIO_DIS#_R
2
1 PLTRST3#
R444
0_0402_5%~D
WLAN_SMBCLK
WLAN_SMBDATA
USBP4_DUSBP4_D+
USB_MCARD1_DET#
WIMAX LED
LED_WLAN_OUT#
1
2 LED_WPAN_OUT#
@ R446
0_0402_5%~D
USB_MCARD1_DET# <24>
C
LED_WLAN_OUT# <42>
LED_WPAN_OUT# <42>
WLAN Noise
USB_MCARD1_DET#
1
C553
4700P_0402_25V7K~D
1
4
<24> USBP4-
@ L33
DLW21SN121SQ2L_4P~D
1
2 2
4
3
1
R452
1
R453
USBP4_D+
USBP4_D-
3
2
0_0402_5%~D
2
0_0402_5%~D
@
USB_MCARD3_DET# 1
R742
2 PCIE_MCARD3_DET#
0_0402_5%~D
WPAN Noise
USB_MCARD3_DET#
+3.3V_RUN
JMINI3
1
750
250
54
USB_MCARD1_DET#
UIM_DATA
4
Aux Power
Normal
GND2
2
100K_0402_5%~D
+3.3V_RUN
<24> USBP4+
WPAN Card
C577
33P_0402_50V8J~D
1
Primary Power
Peak
2
1
+SIM_PWR
C576
33P_0402_50V8J~D
+3.3V
Voltage
Tolerance
2
1
GND1
1
R439
UIM_VPP
<38> HOST_DEBUG_RX
<38> MSCLK
PWR
Rail
1
C562
4.7U_0603_6.3V4Z~D
2
1
C561
0.1U_0402_16V4Z~D
2
1
53
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2007/11/3 Remove Latch2
1
C575
33P_0402_50V8J~D
GND
VPP
I/O
NC
GND
GND
MOLEX_475531001
2
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
PCIE_MCARD1_DET#
+1.5V_RUN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
R458
2
100K_0402_5%~D
+3.3V_RUN
2
1
2
C585
4.7U_0603_6.3V4Z~D
2
1
C584
0.1U_0402_16V4Z~D
2
1
C583
0.1U_0402_16V4Z~D
2
1
C582
0.047U_0402_16V4Z~D
2
1
C581
0.047U_0402_16V4Z~D
2
1
@C580
@
C580
0.1U_0402_16V4Z~D
1
C579
0.047U_0402_16V4Z~D
2
C578
0.047U_0402_16V4Z~D
1
A
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
B
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
TYCO_1775861-1~D
+1.5V_RUN
2
1
C572
4700P_0402_25V7K~D
2
C571 4700P_0402_25V7K~D
HOST_DEBUG_TX
2
R456
HOST_DEBUG_TX <38>
WPAN_RADIO_DIS#
1 PLTRST3#
0_0402_5%~D
MINI_SMBCLK
MINI_SMBDATA
USBP6_DUSBP6_D+
USB_MCARD3_DET#
MSDATA
1
R459
<37>
+3.3V_RUN
R266
100K_0402_5%~D
USB_MCARD3_DET# <24>
MSDATA <38>
LED_WPAN_OUT#
2
0_0402_5%~D
1
<24> USBP6-
4
<24> USBP6+
@ L34
DLW21SN121SQ2L_4P~D
1
2 2
4
1
R460
1
R461
3
USBP6_DUSBP6_D+
3
A
2
0_0402_5%~D
2
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
D
+3.3V_ALW_ICH
2
+3.3V_RUN
5
6
7
8
9
10
C574
33P_0402_50V8J~D
2
C573
1U_0603_10V4Z~D
1
VCC
RST
CLK
NC
1
USBP5_D+
C560
0.1U_0402_16V4Z~D
JSIM1
UIM_RESET
UIM_CLK
3
2
0_0402_5%~D
2
0_0402_5%~D
USBP5_D-
1
CARD_SMBDAT <32,38>
TYCO_1775861-1~D
U31
+SIM_PWR
1
2
3
4
4
1
R450
1
R451
3
C559
0.047U_0402_16V4Z~D
<24> USBP5+
4
C558
0.047U_0402_16V4Z~D
2
<24> USBP5-
@ L32
@L32
DLW21SN121SQ2L_4P~D
1 1
2 2
CARD_SMBDAT
3
+3.3V_WLAN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
C554
330U_D2E_6.3VM_R25~D
USB_MCARD2_DET# 2
R447
PCIE_MCARD2_DET# 1
R449
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
<24> PCIE_ITX_WLANRX_N2_C
<24> PCIE_ITX_WLANRX_P2_C
COEX2_WLAN_ACTIVE
WIMAX LED
2
0_0402_5%~D
1
R840
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
<24> PCIE_IRX_WLANTX_N2
<24> PCIE_IRX_WLANTX_P2
MINI_SMBCLK
MINI_SMBDATA
@C557
@
C557
0.1U_0402_16V4Z~D
+
5
<37>
C556
0.047U_0402_16V4Z~D
2
1
2
1
D
S
G
3
<6> CLK_PCIE_MINI2#
<6> CLK_PCIE_MINI2
WWAN_RADIO_DIS#
1
2 PLTRST3#
R442
0_0402_5%~D
UIM_RESET
B
R440
R441
<6> MINI2CLK_REQ#
C555
0.047U_0402_16V4Z~D
2
1
C563
330U_D2E_6.3VM_R25~D
2
1
C568
33P_0402_50V8J~D
2
1
C567
22U_0805_6.3VAM~D
2
1
C566
33P_0402_50V8J~D
1
C565
0.047U_0402_16V4Z~D
C564
0.047U_0402_16V4Z~D
2
C570
0.047U_0402_16V4Z~D
1
4
Mini WLAN
+3.3V_WLAN
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
+1.5V_RUN
+SIM_PWR
CARD_SMBCLK <32,38>
Q49B
2N7002DW-T/R7_SOT363-6~D
PCIE_WAKE#
1
2 0_0402_5%~D
1
2 0_0402_5%~D
+3.3V_RUN
C569
33P_0402_50V8J~D
2
GND1
WLAN_SMBDATA
JMINI2
TYCO_1775861-1~D
+1.5V_RUN
1
53
2
CARD_SMBCLK
2
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
<24> PCIE_IRX_WANTX_N1
<24> PCIE_IRX_WANTX_P1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
@
6
Q49A
2N7002DW-T/R7_SOT363-6~D
1
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
<6> CLK_PCIE_MINI1#
<6> CLK_PCIE_MINI1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
1
@
MINI1CLK_REQ#
<6> MINI1CLK_REQ#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
1
+3.3V_RUN
JMINI1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
+3.3V_RUN
PCIE_WAKE#
<32,37> PCIE_WAKE#
2
<38> AUX_EN_WOWL
2 PCIE_MCARD2_DET#
0_0402_5%~D
1
@
USB_MCARD2_DET# 1
R740
Mini WWAN
@
1
5
Q48B
2N7002DW-T/R7_SOT363-6~D
6
Q53A
2N7002DW-T/R7_SOT363-6~D
2
1
2
5
CARD_SMBDAT
3
4
1
4
R436
200K_0402_5%~D
MINI_SMBDATA
WLAN_SMBCLK
R435
470K_0402_5%~D
D
Q47
SI3456BDV-T1-E3_TSOP6~D
C551
4700P_0402_25V7K~D
3
1
2
CARD_SMBCLK
6
Q48A
2N7002DW-T/R7_SOT363-6~D
4
Q53B
2N7002DW-T/R7_SOT363-6~D
1
2
2
D21
RB751S40T1_SOD523-2~D
+3.3V_WLAN
6
5
2
1
R434
2.2K_0402_5%~D
<37> WLAN_RADIO_DIS#
+3.3V_ALW
WLAN_RADIO_DIS#_R
2
R433
2.2K_0402_5%~D
2
+15V_ALW
2
0_0402_5%~D
1
R432
100K_0402_5%~D
1
@R428
@
R428
R431
100K_0402_5%~D
R430
2.2K_0402_5%~D
R429
2.2K_0402_5%~D
MINI_SMBCLK
1
+3.3V_RUN
3
2
Title
Mini Card
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
34
of
63
2
1
JDOCK1
DOCK_DET_1
<30> DOCK_LOM_SPD10LED_GRN#
<21> DPB_DOCK_CA_DET
D23 @
DPB_DOCK_LANE0_C
10 DPB_DOCK_LANE0_C
1
DPB_DOCK_LANE0#_C 2
DPB_DOCK_LANE1_C
9
DPB_DOCK_LANE0#_C
4
7
DPB_DOCK_LANE1_C
DPB_DOCK_LANE1#_C 5
6
DPB_DOCK_LANE1#_C
3
D25 @
DPB_DOCK_LANE2_C
1
DPB_DOCK_LANE2#_C 2
B
DPB_DOCK_LANE3_C
DPB_DOCK_LANE0_C
DPB_DOCK_LANE0#_C
<21> DPB_DOCK_LANE0_C
<21> DPB_DOCK_LANE0#_C
DPB_DOCK_LANE1_C
DPB_DOCK_LANE1#_C
<21> DPB_DOCK_LANE1_C
<21> DPB_DOCK_LANE1#_C
DPB_DOCK_LANE2_C
DPB_DOCK_LANE2#_C
<21> DPB_DOCK_LANE2_C
<21> DPB_DOCK_LANE2#_C
DPB_DOCK_LANE3_C
DPB_DOCK_LANE3#_C
<21> DPB_DOCK_LANE3_C
<21> DPB_DOCK_LANE3#_C
8
RCLAMP0524P.TCT~D
DPB_DOCK_CA_DET
DPB_DOCK_AUX
<21> DPB_DOCK_AUX
DPB_DOCK_AUX#
<21> DPB_DOCK_AUX# R1095
DPB_DOCK_HPD 1
2DOCKB_HPD
<21> DPB_DOCK_HPD
DPB_DOCK_LANE2_C
0_0402_5%~D
10
+NBDOCK_DC_IN_SS
9
DPB_DOCK_LANE2#_C
4
7
DPB_DOCK_LANE3_C
DPB_DOCK_LANE3#_C 5
6
DPB_DOCK_LANE3#_C
BLUE_DOCK
<20> BLUE_DOCK
RED_DOCK
<20> RED_DOCK
3
RCLAMP0524P.TCT~D
<20> HSYNC_DOCK
<20> VSYNC_DOCK
D27 @
DPB_DOCK_AUX#
<38> CLK_MSE
<38> DAT_MSE
10 DPB_DOCK_AUX#
1
GREEN_DOCK
<20> GREEN_DOCK
8
DPB_DOCK_AUX
2
9
DPB_DOCK_AUX
DPB_DOCK_HPD
4
7
DPB_DOCK_HPD
DPB_DOCK_CA_DET
5
6
DPB_DOCK_CA_DET
<27> DAI_BCLK#
<27> DAI_LRCK#
<27> DAI_DI
<27> DAI_DO#
3
<27> DAI_12MHZ#
8
RCLAMP0524P.TCT~D
<37> D_LAD0
<37> D_LAD1
Place close to JP1 connector
<37> D_LAD2
<37> D_LAD3
<37> D_LFRAME#
<37> D_CLKRUN#
<37> D_SERIRQ
<37> D_DLDRQ1#
<6> CLK_PCI_DOCK
<38> DOCK_SMB_CLK
<38> DOCK_SMB_DAT
<38,43> DOCK_SMB_ALERT#
<43> DOCK_PSID
<38> DOCK_PWR_BTN#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
146
147
148
GND1
PWR1
PWR1
PWR1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
PWR2
PWR2
PWR2
GND2
149
150
151
152
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
159
160
161
162
163
164
DOCK_AC_OFF
DOCK_AC_OFF <37,49>
DOCK_LOM_SPD100LED_ORG# <30>
DPC_CA_DET <21,51>
DPC_CA_DET
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
D22 @
DPC_LANE_P0_C <51>
DPC_LANE_N0_C <51>
DPC_LANE_P1_C <51>
DPC_LANE_N1_C <51>
DPC_LANE_P0_C
1
10 DPC_LANE_P0_C
DPC_LANE_N0_C
2
9
DPC_LANE_N0_C
DPC_LANE_P1_C
4
7
DPC_LANE_P1_C
DPC_LANE_N1_C
5
6
DPC_LANE_N1_C
DPC_LANE_P2_C <51>
DPC_LANE_N2_C <51>
3
DPC_LANE_P3_C <51>
DPC_LANE_N3_C <51>
RCLAMP0524P.TCT~D
DPC_DOCK_AUX_SW
DPC_DOCK_AUX_SW <21>
DPC_DOCK_AUX#SW
DPC_DOCK_AUX#SW <21>
R1096
DOCKC_HPD 1
DPC_DOCK_HPD
2
0_0402_5%~D
ACAV_DOCK_SRC# <49>
8
D24 @
DPC_DOCK_HPD
<51>
DAT_DDC2_DOCK <20>
CLK_DDC2_DOCK <20>
SATA_SBRX_DTX_P3
2
SATA_SBRX_DTX_N3 C586 2
C587
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
DPC_LANE_P2_C
1
10 DPC_LANE_P2_C
DPC_LANE_N2_C
2
9
DPC_LANE_N2_C
DPC_LANE_P3_C
4
7
DPC_LANE_P3_C
DPC_LANE_N3_C
5
6
DPC_LANE_N3_C
SATA_SBRX_DTX_P3_C <23>
SATA_SBRX_DTX_N3_C <23>
B
3
8
SATA_SBTX_C_DRX_P3 <23>
SATA_SBTX_C_DRX_N3 <23>
RCLAMP0524P.TCT~D
USBP8+ <24>
USBP8- <24>
D26 @
USBP9+ <24>
USBP9- <24>
CLK_KBD <38>
DAT_KBD <38>
DPC_DOCK_AUX_SW
1
10 DPC_DOCK_AUX_SW
DPC_DOCK_AUX#SW
2
9
DPC_DOCK_AUX#SW
DPC_DOCK_HPD
4
7
DPC_DOCK_HPD
DPC_CA_DET
5
6
DPC_CA_DET
3
8
RCLAMP0524P.TCT~D
BREATH_LED# <38,42>
DOCK_LOM_ACTLED_YEL# <30>
Place close to JP1 connector
DOCK_LOM_TRD0+ <30>
DOCK_LOM_TRD0- <30>
DOCK_LOM_TRD1+ <30>
DOCK_LOM_TRD1- <30>
TR0/1CT
TR2/3CT
+LOM_VCT
+3.3V_ALW
DOCK_LOM_TRD2+ <30>
DOCK_LOM_TRD2- <30>
DOCK_LOM_TRD3+ <30>
DOCK_LOM_TRD3- <30>
DOCK_DCIN_IS+ <48>
DOCK_DCIN_IS- <48>
2
R1033
1
100K_0402_5%~D
@ 2
R124
1
100K_0402_5%~D
+RTC_CELL
DOCK_DET#
D70
RB751S40T1_SOD523-2~D
1
2
DOCK_DET# <21,37>
DOCK_POR_RST# <38>
DOCK_DET_D#
DPC_DOCK_HPD
CLK_PCI_DOCK
@ R462
10_0402_5%~D
2
2
2
1
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
R1057
1K_0402_5%~D
@
2
2
3
1
153
154
155
156
157
158
C1016
0.1U_0603_50V4Z~D
D65
SM24.TCT_SOT23-3
2
C1017
0.1U_0603_50V4Z~D
1
1
R796
100K_0402_5%~D
+DOCK_PWR_BAR
+DOCK_PWR_BAR
1
1
<37,43,49> SLICE_BAT_PRES#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
1
2
@C590
@C590
4.7P_0402_50V8C~D
JAE_WD2F144WB1
A
A
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
2
DOCKING CONN
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
1
Sheet
35
of
63
2
RDIF
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
1
2
RFREADER_TXN1_PI
2
JCS1
RFTAG_VRXN
RFTAG_VRXP
1
R496
1
R497
2
4.12K_0402_1%~D
2
4.12K_0402_1%~D
1
C640
1
C642
2
1U_1206_100V4Z~D
2
1U_1206_100V4Z~D
ANT_RFTAG_VRXN_R
ANT_RFTAG_VRXP_R
RFREADER_TXP1_PI
C589
4.7P_0402_50V8C~D
2
1
1
2
3
4
5
6
1
2
3
4
5 G1
6 G2
A
7
8
TYCO_1-1775784-0_6P-T
+3.3V_RUN
1
2
3K_0402_1%~D
1U_0603_10V6K~D
1
2
1
2
3
L74
2RFREADER_TXP1
1
@
2
C643
R498
1
1
@
<24> CONTACTLESS_DET#
RFREADER_RXP
2
1
1
D29
1
1U_0603_10V6K~D
2
1
3
+3.3V_RUN
L73
2RFREADER_TXN1 1
2
2
2
1
2
2
D28
C639
2
1
1
BAS40-04_SOT23-3~D
2
1
1
1
BAS40-04_SOT23-3~D
1
2
2
2
2
C619
1U_0402_6.3V6K~D
2
1
C931
4.7U_0603_6.3V6M~D
PCI_TPM_TERM 2
2
C618
1U_0402_6.3V6K~D
@
2
1
C934
4.7U_0603_6.3V6M~D
1
1
C930
4.7U_0603_6.3V6M~D
2
1
2
C617
1U_0402_6.3V6K~D
1
1
2
C875
1U_0402_6.3V6K~D
1
1
2
C616
1U_0402_6.3V6K~D
1
1
C607
1U_0402_6.3V6K~D
@
2
C606
1U_0402_6.3V6K~D
1
1
+2.5V_AVDD_5880
C638
1U_0402_6.3V6K~D
2
4.7K_0402_5%~D
2
100K_0402_5%~D
2
100NH_LLQ1608-FR10G_2%~D
2
BCM5880_GPIO15
1
C637
1U_0402_6.3V6K~D
1
@R341
@
R341
1
@R1027
@
R1027
2
2
C636
1U_0402_6.3V6K~D
SC_DET
1
C635
1U_0402_6.3V6K~D
BCM5880_GPIO15
2
+3.3V_RUN
BLM18BB100SN1D_0603~D
2
1 +RFID_AVDD3P3
L38
C632
0.1U_0402_16V4Z~D
8
7
6
5
1
+1.2V_AVDD_5880
BLM18BB100SN1D_0603~D
2
1 +RFID_AVDD1P2
L37
2
SPI_RXD
M45PE16-VMP6TP_SO8~D
TYCO_1-1734821-0_10P-T
300_0402_5%~D
Q
VSS
VCC
W#
1
3K_0402_1%~D
+3.3V_RUN
1
2
+3.3V_RUN
2
100NH_LLQ1608-FR10G_2%~D
1
CLK_PCI_TPM
2
D
C
RESET#
S#
1
R494
U34
1
2
3
4
2
48MHz
SC_C4 & SC_C8 is for 90 ohm
RFREADER_RXN
1
SPI_TXD
SPI_CLK
SPI_RST
SPI_CS
24MHZ 27.12MHz
2
Pull-downs
for 5880 Rev
A0, and
pull-ups for
Rev B0
C631
1U_0402_6.3V6K~D
10
9
8
7
6
5
4
3
2
1
RVD
+1.2V_AVDD_5880
1
C630
3.3U_0603_10V4Z~D
10
9
8
7
6
5
4
3
2
1
AD[16:15]
C1059
68P_0402_50V8J~D
GND
GND
REF CLK
C647
150P_0402_50V8J~D
2
12
11
RVD
C1058
68P_0402_50V8J~D
1
SMC_ADD18
SMC_ADD17
USBH_OC0#
USBH_OC1#
C629
0.1U_0402_16V4Z~D
2
USB
C628
1U_0402_6.3V6K~D
100K_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
SPI
C641
150P_0402_50V8J~D
1
73S8009CN
SC_DET
SC_IO
SC_C4
SC_C8
SC_CLK
SC_RST
00
C627
1U_0603_10V4Z~D
2
1
2
2
2
2
JSC1
SC_IO
SC_C8
SC_DET
1 R210
17
28
31
33
2
L69
TER_USBH_N1
TER_USBH_P1
2
R773 1
R491 1
R493 1
R492 1
R772
When using the 73S8009C,no-stuff R768,R769,R490
When using the 73S8009CN,stuff R768,R769,R490
SC_RST
SC_CLK
SC_C4
+3.3V_RUN
GND
GND
GND
Therm_GND
1
2
1
10UH_LQH32CN100K53L_10%~D
+LIN
11
SMC
SSMC
R744
10_0402_5%~D
2
23
25
14
22
21
20
16
18
4.7U_0603_6.3V6M~D
C644
1U_0603_10V4Z~D
1
C611
0.47U_0402_6.3V6K
C958
10U_0805_10V4Z~D
A
DM
DP
PRES
I/O
AUX1
AUX2
CLK
RST
1
8009_VDDMON
10
AD[18:17]
+2.5V_AVDD_5880
BLM18BB100SN1D_0603~D
2
1 +RFID_AVDD2P5
L36
2
C898
27P_0402_50V8J~D
+SC_VCC
ON/OFF
CLKIN
RDY
OFF_ACK
OFF_REQ
CS
SC_USB#
CMDVCC5#
CMDVCC3#
RSTIN
OFF#
TEST1
TEST2
I/OUC
AUX1UC
AUX2UC
C621
C633
27P_0402_50V8J~D
BCM5880_IO
AUX1UC
AUX2UC
24
7
8
9
11
12
13
4
5
6
32
10
30
1
2
3
19
26
29
15
27
01
Boot SRC
C625
1U_0402_6.3V6K~D
2
1
R771
1K_0402_5%~D
PAD~D T139
PAD~D T63
PAD~D T64
8009_VDDMON
GPIO16_TER_TRIS
@
1
2 SC_USB#
5880_GPIO26
R490 1
2 47K_0402_1%~D
5880_GPIO25
R766 1
2 47K_0402_1%~D
BCM5880_SCRST R767 2
1 47K_0402_1%~D
BCM5880_SCDET R770
10K_0402_5%~D
VCC
VPC
VDD
VP
LIN
2 BBCLK
1K_0402_5%~D
2 LPC_EN_R
4.7K_0402_5%~D
2 JTAG_RST#_USH
1K_0402_5%~D
2 SMC_ADD15
4.7K_0402_5%~D
1
R473
1
3@ R489
1
R737
1
R479
POR_EXTR
U33
GPIO14_TER_ON/OFF
BCM5880_SCCLK
VDDO_33
VDDO_33
VDDO_33
2
C615
1U_0402_6.3V6K~D
2
@ R972
4.7K_0402_5%~D
2 LPD#
4.7K_0402_5%~D
2 OVSTB
4.7K_0402_5%~D
2 TAMPER_N
4.7K_0402_5%~D
2 RST_N
4.7K_0402_5%~D
2 SMC_ADD16
4.7K_0402_5%~D
1 SC_USB#
10K_0402_5%~D
2LPC_EN_R
3K_0402_5%~D
2 FP_RESET#
4.7K_0402_5%~D
C626
0.1U_0402_16V4Z~D
1
1
VESD
L9
L10
L11
BCM5880KFBG_FBGA225~D
Function
C624
1U_0402_6.3V6K~D
+SC_VCC
1
2
SBOOT
VDD_BB
VDD_BB
L8
+3.3V_RUN
1
2
B
C614
1U_0402_6.3V6K~D
1
2
V3P3_TAMPER_N
C613
1U_0402_6.3V6K~D
2
V3P3_PWRGOOD
1
2
BCM5880KFBG_FBGA225~D
1
R474
1
R484
1
R736
1
R810
1
R478
2
R850
1
4@ R1058
1
R63
R476
5.1M_0402_5%~D
R488
3.3M_0402_5%~D
2
C609
12P_0402_50V8J~D
C706
10U_0805_6.3V6M~D
1
C620
0.1U_0402_16V4Z~D
27.12MHZ_12PF_1N227120CC0B~D
C608
12P_0402_50V8J~D
V3P3_BBLCLK
2
+3.3V_RUN
+3.3V_RUN
R485
H14
+3.3V_RUN
1
2
R339
4.7K_0402_5%~D
4.7K_0402_5%~D
+3.3V_RUN
VDDO_33SC
VDDO_33SC
VDDO_SC
C605
1U_0402_6.3V6K~D
XO
L13
M14
K13
Place
close
to
pinA14
C14
G11
G6
G7
G8
H10
H11
H6
H7
H8
H9
J10
J12
J6
J7
J8
J9
K10
K12
L12
M13
F8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C602
1U_0402_6.3V6K~D
GND
4
VDDO_33CORE
VDDO_33CORE
VDDO_33CORE
+VDD_BBL H12
J13
@
+3.3V_RUN
+3.3V_RUN
VDDO_LPC
VDDO_LPC
K5
L5
L6
AVSS_LDO12
AVSS_ldo25
AVSS_ldo25
AVSS_AUX
AVSS_REF
AVSS_PLL
C612
1U_0402_6.3V6K~D
3
C1019
0.1U_0402_16V4Z~D
2
GND
OUT
C920
0.1U_0402_16V4Z~D
1
IN
1
SWV
680P_0402_50V7-K~D
K8
L7
H15
1
0_0402_5%~D
TAMPER_N H13
2
R471
+3.3V_RUN
VDDO_SMC
VDDO_SMC
VDDO_SMC
C601
1U_0402_6.3V6K~D
2
1
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTN
JTCE
@ R482
4.7K_0402_5%~D
1
REF_XIN
RST_N
RSTOUT_N
BBCLK
R820
4.7K_0402_5%~D
Y3
XI
2
R487
0_0402_5%~D
BCM5880KFBG_FBGA225~D
2
C8
D7
A5
E9
G10
F10
A10
A9
B8
E8
VDDO_VAR
VDDO_VAR
R845
4.7K_0402_5%~D
1
K2
J1
K1
J3
M1
K3
P12
J2
L1
1
C594
P10
R11
N10
R12
P11
M9
HF_RFIDTAG_AVSS
HF_RFIDTAG_AVSS
HF_RFIDTAG_DVSS
HF_RX_ADC_AVSS1
HF_RX_ADC_AVSS2
HF_RX_AVSS
HF_RX_AVSS
HF_TX_AVSS
HF_TX_AVSS
HF_TX_AVSS
E6
F6
G5
H5
J5
R844
4.7K_0402_5%~D
2
10M_0402_5%~D
2
C936
1U_0402_6.3V6K~D
1
R486
2
C935
1U_0402_6.3V6K~D
2 REF_XOUT
0_0402_5%~D
SMC_ADV_N
SMC_BLS_N_0
SMC_BLS_N_1
SMC_CRE
SMC_CS_N_0
SMC_CS_N_1
SMC_IO_3V
SMC_OE_N
SMC_WE_N
JTAG_CLK_USH
JTAG_TDI_USH
JTAG_TDO_USH
JTAG_TMS_USH
JTAG_RST#_USH
JTCE_USH
T72
T73
T74
T75
T76
T77
CLKOUT
CLKOUT_EN
R819
4.7K_0402_5%~D
+SC_PWR
1
R481
GPIO_25/SC_SEL5V
GPIO_26/SC_SEL18V
SC_CINRUSH
SC_CLK
SC_VCC
SC_RST
SC_IO
SC_FCB
SC_FCB_ENB
SC_DET
SC_PWR
SC_PWR
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
N8
R8
RFREADER_RXN
RFREADER_RXP
RFREADER_TXN1
RFREADER_TXP1
@R475
@
R475
4.7K_0402_5%~D
BCM5880_SCVCC
BCM5880_SCRST
BCM5880_IO
AUX1UC
AUX2UC
BCM5880_SCDET
PAD~DT142
P8
R7
N15
L14
L15
K15
K14
J14
J15
M10
M15
N14
A1
B2
R991
RST_N
0_0402_5%~D
SPI_RST 1
2 SPI_RST_R
+RFID_AVDD3P3
1
2
C595
0.01U_0402_25V7K~D
RFTAG_VRXN
RFTAG_VRXP
2
BCM5880_SCCLK
AUXCLK_XTALIN
AUXCLK_XTALOUT
+3.3V_RUN
1
USBH_DN1
USBH_UP1
USBH_OC_1
AUX_XIN
D15
AUX_XOUT E14
T70
T71
CLK
N13
P13
R15
PAD~D
PAD~D
JTAG
2 22_0402_5%~D USBH_N1
2 22_0402_5%~D USBH_P1
USBH_OC1#
@ C600
680P_0402_50V7-K~D
5880_GPIO25
5880_GPIO26
1
2
REFCLK_XTALIN
REFCLK_XTALOUT
1
R768 1
R769 1
FP_RESET# <33>
REF_XIN
F15
REF_XOUT F14
1
TER_USBH_N1
TER_USBH_P1
T68
T69
2
USBH_DN0
USBH_UP0
USBH_OC_0
PAD~D
PAD~D
2
USBH_OC0#
UART LPC
SPI
N11
N12
M11
T66
SMC_ADD15
SMC_ADD16
SMC_ADD17
SMC_ADD18
OVSTB/ZEROB
SCANACCMODE
SECURE_BOOT
SWV/ERROR,OSC1,OSC2,SPL
TESTMODE/TST_SEC_BOOT
IDDQ_EN/CM3_MODE
B6
A6
C7
B7
E7
B10
C10
A11
A12
C11
B11
C9
B9
+RFID_AVDD1P2
C595 close to Pin A6
C933
4.7U_0603_6.3V6M~D
FP_USBDFP_USBD+
PAD~D
OVSTB
N9
SCANMOD M8
SBOOT
P9
SWV
M12
TSTMOD
R9
IDQ_EN
R10
HF_RFIDTAG_AVSS
HF_RFIDTAG_VREF
HF_RFIDTAG_VRX_N
HF_RFIDTAG_VRX_P
HF_RFIDTAG_VTX
HF_RX_TEST0
HF_RX_TEST1
HF_RX_TEST2
HF_RX_TEST3
HF_RX_N
HF_RX_P
HF_TX_N
HF_TX_P
+RFID_AVDD2P5
C877
1U_0402_6.3V6K~D
USBD_DN
USBD_UP
GPIO_27/USBD_ATATCH
PLL_VDD_1P2I
PLL_AVDD_1P2O
PLL_VSS
PLL_VDD_1P2I
PLL_VSS
NC
A7
F7
C6
E10
F9
G9
D8
A8
D9
C873
1U_0402_6.3V6K~D
R13
R14
P14
B
<33> FP_USBD<33> FP_USBD+
SMC_DATA_0
SMC_DATA_1
SMC_DATA_2
SMC_DATA_3
SMC_DATA_4
SMC_DATA_5
SMC_DATA_6
SMC_DATA_7
SMC_DATA_8
SMC_DATA_9
SMC_DATA_10
SMC_DATA_11
SMC_DATA_12
SMC_DATA_13
SMC_DATA_14
SMC_DATA_15
SPI
BootStrap
2 0_0402_5%~D USBP10-_R
2 0_0402_5%~D USBP10+_R
2 1.5K_0402_5%~D
R2
P3
R1
P2
R3
M4
N2
N3
P1
M3
M2
L4
N1
L3
L2
K4
Smard Card
R468 1
R469 1
R470 1
GPIO_14
GPIO_15
GPIO_16
2
B14
B15
D12
D13
E12
A15
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_DVDD1P2
HF_RX_ADC_AVDD1P2
HF_RX_AVDD1P2
HF_RX_AVDD2P5
HF_TX_AVDD1P2
HF_TX_AVDD2P5
HF_TX_AVDD3P3
C932
4.7U_0603_6.3V6M~D
GPIO14_TER_ON/OFF C4
BCM5880_GPIO15
A2
GPIO16_TER_TRIS
D4
2
1
BCM5880
POR_AVSS
POR_EXTR
POR_INT12
POR_MONITOR
C599
1U_0402_6.3V6K~D
GPIO_6/SSP_CLK
GPIO_7/SSP_FSS
GPIO_8/SSP_RXD
GPIO_9/SSP_TXD
1
F12
POR_EXTR G13
G15
G14
C598
1U_0402_6.3V6K~D
C5
B3
D5
A3
+1.2V_PLL_5880
1
2
C591
680P_0402_50V7-K~D
R4
M5
1
2
R463 1
D10
2 2.2K_0402_5%~D
R465
4.7K_0402_5%~D
A14
G12
+2.5V_AVDD_5880
B13
A13
1
+3.3V_RUN
B12
E11
+1.2V_AVDD_5880
E13
2
F13
+1.2V_PLL_5880
D14
P15 +OTP_PWR 2
1
+3.3V_RUN
R467
0_0603_5%~D
F11
2
1
+SC_PWR
R829
0_0603_5%~D
C12
D11
C15
+1.2V_VDDC_5880
E15
CORE_CINRUSH
CORE_PWRDN
ALDO_PWRDN
AVDD33_LDO25
AVDD_2P5I
AVDD_2P5O
AVDD25_ldo12
AVDD25_ldo12
AVDD_1P2O
AVDD_1P2I_AUX
AVDD_1P2I_REF
AVDD25_PLL
OTP_PWR
C597
1U_0402_6.3V6K~D
GPIO_0/UART_RX
GPIO_1/UART_TX
GPIO_2/UART_CTS
GPIO_3/UART_RTS
H1
J4
H2
H3
G1
H4
F2
G4
G2
G3
E2
F4
F1
F3
D2
E3
D1
E1
C2
D3
C1
E4
B1
C3
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
C596
1U_0402_6.3V6K~D
B5
B4
D6
A4
SMC_ADD_0
SMC_ADD_1
SMC_ADD_2
SMC_ADD_3
SMC_ADD_4
SMC_ADD_5
SMC_ADD_6
SMC_ADD_7
SMC_ADD_8
SMC_ADD_9
SMC_ADD_10
SMC_ADD_11
SMC_ADD_12
SMC_ADD_13
SMC_ADD_14
SMC_ADD_15/REFCLK_FREQ_0
SMC_ADD_16/REFCLK_FREQ_1
SMC_ADD_17/BOOT_SRC_0
SMC_ADD_18/BOOT_SR_1
SMC_ADD_19
SMC_ADD_20
SMC_ADD_21
SMC_ADD_22
SMC_ADD_23
@
BCM5880
C13
E5
F5
J11
K11
K6
K7
K9
N4
P4
@
UART_TX/GPIO1
LCLK
LPCEN
GPIO_17/LRESET_N
GPIO_18/LFRAME_N
GPIO_19/LSERIRQ
GPIO_20/LAD[0]
GPIO_21/LAD[1]
GPIO_22/LAD[2]
GPIO_23/LAD[3]
GPIO_24/LPCPD_N
C593
1U_0603_10V4Z~D
UART_RX/GPIO0
@ R58
0_0402_5%~D
1
2
BCM5880
M7
R6
N5
P5
M6
R5
N6
N7
P6
P7
U32C
U32B
C592
1U_0603_10V4Z~D
SPI_CLK
SPI_CS
SPI_RXD
SPI_TXD
1.5K_0402_5%~D
<24> USBP10<24> USBP10+
1
+1.2V_VDDC_5880
U32A
D71 RB751S40T1_SOD523-2~D
1
2
CLK_PCI_TPM
LPC_EN_R
@ 1R464
20_0402_5%~D
<37> SP_TPM_LPC_EN
R1050
10_0402_5%~D
2 PLTRST3#_USH
<22,34> PLTRST3#
LPC_LFRAME#
<23,37,38> LPC_LFRAME#
IRQ_SERIRQ_R
1
2
<24,31,37,38> IRQ_SERIRQ
LPC_LAD0
R842
0_0402_5%~D
<23,37,38> LPC_LAD0
LPC_LAD1
<23,37,38> LPC_LAD1
LPC_LAD2
<23,37,38> LPC_LAD2
LPC_LAD3
<23,37,38> LPC_LAD3
LPD#
1
2
<37> SP_TPM_LPC_EN
@ R466
0_0402_5%~D
UART_RX/GPIO0
UART_TX/GPIO1
R849
UART_CTS
PAD~D T171
SC_DET
SC_DET_R
2
1
1
<6> CLK_PCI_TPM
4@
DELL CONFIDENTIAL/PROPRIETARY
TPM Disable: Depop D71, R1058, Pop R489
@
SMART CARD CAGE
Part Number
DAA00000R0L
Compal Electronics, Inc.
Description
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PCB 03P LA-4051P REV0 M/B
http://hobi-elektronika.net
2
1
USH I/F
Size
Document Number
Date:
Friday, June 13, 2008
Rev
1.0
LA-4051P
Sheet
36
of
63
5
4
3
2
1
+3.3V_ALW
1
2
+3.3V_RUN
U35
ESATA_USB_PWR_EN#
2
100K_0402_5%~D
GPIOE[0]/RXD
GPIOE[1]/TXD
GPIOE[2]/RTS#
GPIOE[3]/DSR#
GPIOE[4]/CTS#
GPIOE[5]/DTR#
GPIOE[6]/RI#
GPIOE[7]/DCD#
LCD_TST
PSID_DISABLE#
PANEL_BKEN_GPU
DOCKED
DOCK_DET#
AUD_NB_MUTE
CELL_CHARGER_DET#
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#
65
66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82
GPIOB[0]/INIT#
GPIOB[1]/SLCTIN#
GPIOC[2]/SCLT
GPIOC[3]/PE
GPIOC[4]/BUSY
GPIOC[5]/ACK#
GPIOC[6]/ERROR#
GPIOC[7]/ALF#
GPIOD[0]/STROBE#
GPIOC[1]/PD7
GPIOC[0]/PD6
GPIOB[7]/PD5
GPIOB[6]/PD4
GPIOB[5]/PD3
GPIOB[4]/PD2
GPIOB[3]/PD1
GPIOB[2]/PD0
LID_CL_SIO#
1.05V_RUN_ON
61
62
GPIOD[1]
GPIOD[2]
GFX_CORE_ON
INSTANT_ON_SW_D#
HDDC_EN
MODC_EN
63
28
29
30
31
GPIOD[3]/VBUS_DET
GPIOD[4]/OCS1_N
GPIOD[5]/OCS2_N
GPIOD[6]/OCS3_N
GPIOD[7]/OCS4_N
SLICE_BAT_PRES#
PWR_BTN_BD_DET#
32
33
GPIOH[6]
GPIOH[7]
SYS_LED_MASK#
GFX_OPEN_GL_EN
R526 1
2 0_0402_5%~D
ICH_PME#
ICH_PCIE_WAKE#
WLAN_RADIO_DIS#
88
89
90
91
92
93
94
95
<32> EXPRCRD_DET#
BIOS_RECOVERY
PAD~D T161
C
USB_SIDE_EN#
EN_I2S_NB_CODEC
CB_HWSPND#
EN_DOCK_PWR_BAR
ADAPT_OC
<33> USB_SIDE_EN#
<27> EN_I2S_NB_CODEC
<31> CB_HWSPND#
<49> EN_DOCK_PWR_BAR
<48> ADAPT_OC
<19> LCD_TST
<43> PSID_DISABLE#
<51> PANEL_BKEN_GPU
<29,30> DOCKED
<21,35> DOCK_DET#
<28> AUD_NB_MUTE
<33> CELL_CHARGER_DET#
<19> LCD_VCC_TEST_EN
<19> CCD_OFF
<27,28,33> AUD_HP_NB_SENSE
<33> ESATA_USB_PWR_EN#
D4
1
<31,38> INSTANT_ON_SW#
<40> 1.05V_RUN_ON
@
<50> GFX_CORE_ON
2
<26> HDDC_EN
<26> MODC_EN
RB751S40T1_SOD523-2~D
1
R1029
2
0_0402_5%~D
<35,43,49> SLICE_BAT_PRES#
<31> PWR_BTN_BD_DET#
<29> LAN_DISABLE#_R
<42> CAP_LED#
<42> SYS_LED_MASK#
PAD~D T162
<24> SIO_EXT_WAKE#
<22> ICH_PME#
<24> ICH_PCIE_WAKE#
<34> WLAN_RADIO_DIS#
B
BID2 BID1 BID0 REV
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
X00
X01
X02
X03
X04
A00
WWAN_RADIO_DIS#
<34> WWAN_RADIO_DIS#
VGA_IDENTIFY
CHIPSET_ID1
R528
10K_0402_5%~D
2
1
CHIPSET_ID0
BID2
BID1
BID0
SYSOPT1/GPIOH[2]
SYSOPT0/GPIOH[3]
109
110
111
112
GPIOF[7]
GPIOF[6]
GPIOF[5]
GPIOF[4]
2
1
2
1
2
1
2
1
2
1
@R533
@
R533
10K_0402_5%~D
@R532
@
R532
10K_0402_5%~D
BID0
R531
10K_0402_5%~D
R530
10K_0402_5%~D
R529
10K_0402_5%~D
A
1
@R534
@
R534
1
R535
1
@R536
@
R536
1
R537
1
R538
BID1
BID2
CHIPSET_ID0
CHIPSET_ID1
GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)
GPIOI[2](VDD18)
CAP_LDO
GPIOJ[0](RBIAS)
GPIO
TEST_PIN
TEST
CLK
IRTX
IRRX
115
116
117
118
GPIOF[3]/IRMODE/IRRX3B
GPIOF[2]/IRTX2
GPIOF[1]/IRRX2
GPIOF[0]/IRMODE/IRRX3A
1.8V_RUN_ON
9
10
13
12
15
16
19
18
21
22
SNIFFER_BLUE#
SNIFFER_YELLOW#
DOCK_HP_DET
CRT_SWITCH
ME_FWP
NB_AC_OFF
125
124
120
86
127
RUN_ON
1.5V_RUN_ON
1
2
R509
0_0402_5%~D
0.9V_DDR_VTT_ON
+CAP_LDO 8mil
DP_MB_EN
2
1
R514
1K_0402_5%~D
DOCK_AC_OFF_EC
35
GPIOI[7](ATEST)
GPIOI[4](XTAL1/CLKIN)
GPIOI[3](XTAL2)
123
122
3.3V_RUN_ON
54
52
49
47
42
41
56
37
46
44
39
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5028
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLKI (14.318 MHz)
64
CLK_SIO_14M
VSS
96
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
55
53
50
48
43
38
45
40
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
LPC
DLPC
1
T81 PAD~D
SNIFFER_BLUE# <42>
2
SNIFFER_YELLOW# <42>
DOCK_HP_DET <27>
CRT_SWITCH <20>
ME_FWP <23>
NB_AC_OFF <43,48,49>
DP_PRIORITY <21>
2.5V_RUN_PWRGD <18,41>
RUN_ON <19,28,40,41>
1.5V_RUN_ON <45>
VGA_IDENTIFY
IN1
2
IN2
O
2
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
D_CLKRUN#
2
R510
2
R511
2
R512
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
2
R515
2
R516
2
R518
3.3V_RUN_ON
2
R519
0.9V_DDR_VTT_ON 2
R520
PBATT_OFF
2
R521
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
GFX_CORE_ON
2
100K_0402_5%~D
D_SERIRQ
D_DLDRQ1#
C1031
DP_MB_EN <21>
0.1U_0402_16V4Z~D
1
2
+3.3V_ALW
1
1
R522
SNIFFER_BLUE#
2
@R507
@
R507
SNIFFER_YELLOW# 2
@R508
@
R508
TP_DET#
2
R756
INSTANT_ON_SW_D# 2
R20 @
+3.3V_RUN
IMVP_VR_ON <47>
IMVP_PWRGD <24,41,47>
0.9V_DDR_VTT_ON <46>
U71
74AHC1G08GW_SOT353-5~D
RUN_ON
D72
1.5V_RUN_ON
RB751S40T1_SOD523-2~D
1.05V_RUN_ON
2
1
DOCK_AC_OFF <35,49>
4
1
2
@ R1066
0_0402_5%~D
SIO_SLP_S3# <24>
3.3V_RUN_ON <40>
LPC_LAD[0..3]
<23,36,38>
1
R523
C
+3.3V_RUN
LPC_LFRAME# <23,36,38>
PLTRST2# <22,38>
CLK_PCI_5028 <6>
CLKRUN# <24,31,38>
LPC_LDRQ0# <23>
LPC_LDRQ1# <23>
IRQ_SERIRQ <24,31,36,38>
CLK_PCI_5028
R648
10K_0402_5%~D
ME_FWP
CLK_SIO_14M <6>
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
CLK_SIO_14M
R527
10_0402_5%~D
@R506
@
R506
10_0402_5%~D
@ R649
10K_0402_5%~D
D_LAD0 <35>
D_LAD1 <35>
D_LAD2 <35>
D_LAD3 <35>
D_LFRAME# <35>
D_CLKRUN# <35>
D_DLDRQ1# <35>
D_SERIRQ <35>
1
C656
4.7P_0402_50V8C~D
2
1
@C654
@
C654
4.7P_0402_50V8C~D
2
B
+3.3V_ALW
R524
1M_0402_5%~D
RUNPWROK
7
OUT65
105
GPIOJ[4](VSS)
VSS
GPIOK[7](VSS)
VSS
VSS
VSS
VSS
VSS
GPIOJ[1](VSS)
11
17
23
36
51
72
87
121
128
RUNPWROK <38,41,47,50>
SP_TPM_LPC_EN <36>
LID_CL_SIO#
R525
10_0402_5%~D
2
1
LID_CL#
LID_CL# <31,42>
1
GPIO_PSID_SELECT <43>
1
2
2
C657
4.7U_0603_6.3V4Z~D
C655
0.047U_0402_16V4Z~D
SPI_WP#_SEL <24>
TP_DET#
CHIPSET_ID1
DOCK_MIC_DET <27>
MCH_TSATN_EC <10>
<38,48> ACAV_IN_NB
PWRGD
113
114
119
126
ECE5028-NU_VTQFP128_14X14~D
TP_DET# <39>
CHIPSET_ID0
A
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
0
0
Roush-I Foose-I
0
1
Roush-A
1
0
SmFF
1
1
Nike
http://hobi-elektronika.net
5
GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)
GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)
GPIOK[1](USBDN2)
GPIOK[3](USBDP3)
GPIOK[2](USBDN3)
GPIOK[5](USBDP4)
GPIOK[6](USBDN4)
USB
GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]
106
107
+3.3V_ALW
@
VCC1
VCC1
VCC1
VCC1
EXPRCRD_DET#
1
2
3
4
5
84
83
6
GPIOI[1](VCC1)
1
1
R988
GPIOH[0]
GPIOH[1]
GPIOH[4]
GPIOH[5]
BC_INT#
BC_DAT
BC_CLK
<31> WIRELESS_ON#/OFF
<34> WPAN_RADIO_DIS#
<32> EXPRCRD_PWREN#
<32> EXPRCRD_STDBY#
<38> BC_INT#_ECE5028
<38> BC_DAT_ECE5028
<38> BC_CLK_ECE5028
ECE5028-NU
(ECE5018)
DOCK_MIC_DET
2
2USB_POWERSHARE_PWR_EN#
100K_0402_5%~D
24
25
26
27
58
59
60
PCIE_WAKE#
USB_POWERSHARE_PWR_EN#
+3.3V_ALW
8
14
20
1
1
R504
WIRELESS_ON#/OFF
WPAN_RADIO_DIS#
EXPRCRD_PWREN#
EXPRCRD_STDBY#
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
DCIN_CBL_DET#
PBATT_OFF
+3.3V_ALW
VCC1(VDDA33)
GPIOJ[7](VDDA33)
GPIOK[4](VDDA33)
2
USB_SIDE_EN#
2
100K_0402_5%~D
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
2
1
R502
97
98
99
100
101
102
103
104
1
+3.3V_ALW2
PBAT_PRES#
C653
0.1U_0402_16V4Z~D
<43> PBAT_PRES#
<42> SCRL_LED#
<42> NUM_LED#
<43> DCIN_CBL_DET#
<49> PBATT_OFF
<33> MDC_RST_DIS#
<32,34> PCIE_WAKE#
<33> USB_POWERSHARE_PWR_EN#
C651
0.1U_0402_16V4Z~D
2
D
WIRELESS_ON#/OFF
2
100K_0402_5%~D
2 SP_TPM_LPC_EN
10K_0402_5%~D
PWR_BTN_BD_DET#
2
100K_0402_5%~D
1
R754
2
1
C650
0.1U_0402_16V4Z~D
2
1
R913
1
R788
2
1
C649
0.1U_0402_10V7K~D
1
@
2
C652
0.1U_0402_16V4Z~D
1
@
1
34
57
85
108
D
1
C648
0.1U_0402_16V4Z~D
2
CELL_CHARGER_DET#
2
100K_0402_5%~D
+3.3V_ALW
R1067
33K_0402_5%~D
2
1
1
R951
LCD_TST
2
100K_0402_5%~D
PANEL_BKEN_GPU
2
100K_0402_5%~D
5
1
R909
DCIN_CBL_DET#
2
100K_0402_5%~D
1
R816
1
R505
P
SLICE_BAT_PRES#
2
4.7K_0402_5%~D
SYS_LED_MASK#
2
10K_0402_5%~D
G
1
R503
1
R1014
3
PCIE_WAKE#
2
10K_0402_5%~D
1
R501
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
ECE5028
Size
Document Number
Date:
Friday, June 13, 2008
Rev
1.0
LA-4051P
Sheet
1
37
of
63
5
4
3
2
1
1
+RTC_CELL
R539
100K_0402_5%~D
<18> POWER_SW_IN#
AGND
<18> EC_32KHZ_OUT
125
1+5035_AGND
15mil
Place closely pin 58
1
CLK_PCI_5035
R588
10_0402_5%~D
1
2
C675
22P_0402_50V8J~D
2
A
2
C674
22P_0402_50V8J~D
3
1
L39
BLM18AG121SN1D_0603~D
2
C673
4.7P_0402_50V8C~D
2
1
2
DOCK_PWR_SW#
1
R554
1
2
2
@ C669
1U_0402_6.3V6K~D
2
1K_0402_5%~D
+RTC_CELL
+3.3V_ALW
D68
2
EN_CELL_CHARGER_DET#
HOST_DEBUG_TX <34>
HOST_DEBUG_RX <34>
RESET_OUT# <41>
MSDATA <34>
MSCLK <34>
SIO_A20GATE <23>
PS_ID <43>
Bat2
BAT1_LED# <42>
Bat1
BAT2_LED# <42>
RC_ID
= Amber LED
= Blue LED
1
20mA drive pins
5
6
7
8
12
13
93
94
95
96
97
98
99
100
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
CKG_SMBDAT
CKG_SMBCLK
M_ON
ICH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
SIO_SLP_M# <24>
DOCK_SMB_ALERT# <35,43>
ME_WOL_EN <24>
ME_SUS_PWR_ACK <24>
1.8V_SUS_PWRGD <46>
ICH_CL_PWROK <10,24>
3.3V_LAN_PWRGD <41>
1.05V_M_PWRGD <45>
ALW_PWRGD_3V_5V <44>
SUSPWROK <41>
SIO_SLP_S5# <24>
BEEP <27>
AUX_ON <40>
ODD_DET# <24,26>
3.3V_M_PWRGD <18,41>
AUX_EN_WOWL <34>
SIO_SLP_S4# <24>
M_ON <40,45>
ICH_RSMRST# <24>
AC_PRESENT <24>
SIO_PWRBTN# <24>
INSTANT_ON_SW#
DOCK_SMB_DAT
DOCK_SMB_CLK
2
1
R975
2
R560 @
1
R562
1
R971
@
1
RB751S40T1_SOD523-2~D
2
200K_0402_5%~D
1
100K_0402_5%~D
2
100K_0402_5%~D
2
100K_0402_5%~D
+3.3V_ALW
1
R1030
2
R565
2
R567
2
100K_0402_5%~D
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
2
R569
2
R570
2
R571
2
R572
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
R573
2
10K_0402_5%~D
+5V_RUN
C
CLK_KBD
+3.3V_ALW
DAT_KBD
CLK_MSE
2
SIO_SLP_M#
DOCK_SMB_ALERT#
ME_WOL_EN
ME_SUS_PWR_ACK
1.8V_SUS_PWRGD
ICH_CL_PWROK
3.3V_LAN_PWRGD
1.05V_M_PWRGD
ALW_PWRGD_3V_5V
SUSPWROK
SIO_SLP_S5#
BEEP
AUX_ON
ODD_DET#
SNIFFER_PWR_SW#
SNIFFER/INSTANT_SW#
R578
10K_0402_5%~D
DAT_MSE
1
2
3
14
15
16
17
18
28
29
30
31
32
33
34
73
84
89
90
91
108
109
INSTANT_ON_SW#
R211
1K_0402_5%~D
1
HOST_DEBUG_TX
HOST_DEBUG_RX
RESET_OUT#
MSDATA
MSCLK
SIO_A20GATE
PS_ID
BAT1_LED#
BAT2_LED#
FWP#
DOCK_PWR_BTN# <35>
C670
1U_0603_10V4Z~D
AC_PRESENT
FWP#
@ R586
10K_0402_5%~D
+3.3V_ALW
2
1
1
1
2
Y4
32.768K_12.5P_1TJS125DJ4A420P~D
MEC5035_XTAL2
4
1
8mil
MEC5035_XTAL1
1
2
1
+RTC_CELL
2
SNIFFER/INSTANT_SW#
ALWON
EN_CELL_CHARGER_DET#
POWER_SW_IN#
ACAV_IN
DOCK_PWR_SW#
ALWON <44>
EN_CELL_CHARGER_DET#
2
INSTANT_ON_SW#
O
C978
1
1
B
2
5
1
IN2
P
IN1
SNIFFER_PWR_SW#
G
118
119
120
126
127
128
1
1
2
@
C827 0.1U_0402_16V4Z~D
SNIFFER_PWR_SW#
<31>
EC_JTAG_RST_PAD1
INSTANT_ON_SW# <31,37>
@SHORT PADS~D
<33>
3
BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#
@
4
2
2
CARD_SMBDAT <32,34>
CARD_SMBCLK <32,34>
1
0.1U_0402_16V7K~D
1
@
R585
CARD_SMBDAT
CARD_SMBCLK
JTAG_RST#
2
ACAV_IN_NB
R579
10K_0402_5%~D
DOCK_SMB_DAT <35>
DOCK_SMB_CLK <35>
LCD_SMBDAT <19>
LCD_SMBCLK <19>
CKG_SMBDAT <6,27,48>
CKG_SMBCLK <6,27,48>
AMT_SMBDAT <24>
AMT_SMBCLK <24>
ACAV_IN_NB <37,48>
100_0402_1%~D
121
XTAL1
XTAL2
GPIO160/32KHZ_OUT
ACES_85204-06001~D
32 KHz
Clock
Same as Laguna
21
44
65
83
116
104
4
52
MASTER CLOCK
122
124
117
thermal GND
MEC5035_XTAL1
1
0_0402_5%~D
DDR_ON <46>
RUNPWROK <37,41,47,50>
ICH_LAN_RST# <24>
U62
74AHC1G08GW_SOT353-5~D
VSS_RO
MEC5035_XTAL2
2
R587
RC_ID
DDR_ON
RUNPWROK
DELL PWR SW INF
129
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
GPIO011/nSMI
GPIO061/LPCPD#
LDRQ#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/nEC_SCI
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[7]
VSS[8]
2
1
1
1
2
2
1
1
2
2
R583
10K_0402_5%~D
1
2
3
4
5
6
R584
10K_0402_5%~D
R582
10K_0402_5%~D
G1
G2
1
2
3
4
5
6
R581
10K_0402_5%~D
@ JTAG1
7
8
R580
49.9_0402_1%~D
B
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
HOST INTERFACE
11
54
55
56
57
58
59
60
61
62
63
64
66
R550
100K_0402_5%~D
<18> DOCK_PWR_SW#
19
27
49
50
67
68
69
70
71
72
81
82
92
110
114
115
123
SMBUS INTERFACE
VR_CAP[1]
<24,31,36,37> IRQ_SERIRQ
<22,37> PLTRST2#
<6> CLK_PCI_5035
<23,36,37> LPC_LFRAME#
<23,36,37> LPC_LAD0
<23,36,37> LPC_LAD1
<23,36,37> LPC_LAD2
<23,36,37> LPC_LAD3
<24,31,37> CLKRUN#
<24> SIO_EXT_SCI#
+3.3V_ALW
SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC5035
IRQ_SERIRQ
PLTRST2#
CLK_PCI_5035
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
GPIO022/BCM_B_CLK/V_CLK
GPIO023/BCM_B_DAT/V_DATA
GPIO024/BCM_B_INT#/V_FRAME
GPIO042/BCM_C_INT#
GPIO043/BCM_C_DAT
GPIO044/BCM_C_CLK
GPIO045/LSBCM_D_INT#
GPIO046/LSBCM_D_DAT
GPIO047/LSBCM_D_CLK
GPIO121/BCM_A_INT#
GPIO122/BCM_A_DAT
GPIO123/BCM_A_CLK
22
<24> SIO_EXT_SMI#
<23> SIO_RCIN#
23
24
25
35
36
37
38
39
40
85
86
87
+5035_VSS 101
15mil
HOST_DEBUG_RX
2
0_0402_5%~D
Molex_53261
BC_INT#_ECE1077
BC_DAT_ECE1077
BC_CLK_ECE1077
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
BC-LINK
26
51
74
88
113
20
53
1
2
1
2
1
2
R576
10K_0402_5%~D
R575
10K_0402_5%~D
R574
100K_0402_5%~D
MSDATA
MSCLK
1
R577
<39> BC_INT#_ECE1077
<39> BC_DAT_ECE1077
<39> BC_CLK_ECE1077
<37> BC_INT#_ECE5028
<37> BC_DAT_ECE5028
<37> BC_CLK_ECE5028
GPIO050/FAN_TACH1
GPIO051/FAN_TACH2
GPIO052/FAN_TACH3
GPIO053/PWM0
GPIO054/PWM1
GPIO055/PWM2
GPIO056/PWM3
+VR_CAP
BC_CLK_EMC4002
BC_DAT_EMC4002
BC_INT#_EMC4002
D
2
GPIO001
GPIO002
GPIO014/GPTP-IN7
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO020
GPIO26/GPTP-IN1
GPIO27/GPTP-OUT1
GPIO30/GPTP-IN2
GPIO31/GPTP-OUT2
GPIO032/GPTP-IN3
GPIO040/GPTP-OUT3
GPIO041
GPIO107
GPIO120
GPIO124/GPTP-OUT5
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
C671
4.7U_0603_6.3V4Z~D
BREATH_LED#
ICH_ALW_ON
Remove ECE1088 (2007/10/29)
JDEG1
5 5
4 4
3 3
2 2
1 1
GPIO145/I2C1K_DATA/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#
FAN PWM & TACH
41
42
43
45
46
47
48
2
POWER_SW#_MB <31,39>
+RTC_CELL
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
VBAT
<18> BC_CLK_EMC4002
<18> BC_DAT_EMC4002
<18> BC_INT#_EMC4002
DOCK_POR_RST#
SUS_ON
2
1
2
1K_0402_5%~D
C659
1U_0603_10V4Z~D
C480
4700P_0402_25V7K~D
<35,42> BREATH_LED#
<40> ICH_ALW_ON
<39> KYBRD_BKLT_PWM
+3.3V_ALW
@
GPIO021/RC_ID
GPIO025/UART_CLK
VCC_PRWGD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO102/ECGP_SOUT
GPIO103/ECGP_SIN
GPIO104/UART_TX
GPIO105/UART_RX
GPIO106/nRESET_OUT
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
GENERAL PURPOSE I/O
<35> DOCK_POR_RST#
<40,41> SUS_ON
2
1
C668
0.1U_0402_16V4Z~D
C
102
103
105
106
107
2
1
C667
0.1U_0402_16V4Z~D
M_ON
1
1M_0402_5%~D
AUX_ON
2
2.7K_0402_5%~D
DDR_ON
2
100K_0402_5%~D
SUS_ON
2
100K_0402_5%~D
ICH_ALW_ON
2
100K_0402_5%~D
C1055
DOCK_POR_RST#
1
1
2
1M_0402_5%~D
0.1U_0402_16V4Z~D
2
R561
1
R563
1
R564
1
R566
1
R568
2
R1059
GPIO007/I2C1D_DATA/PS2_CLK0B
GPIO010/I2C1D_CLK/PS2_DAT0B
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B
GPIO155/I2C1C_CLK/PS2_DAT1B
JTAG INTERFACE
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
2
1
C666
0.1U_0402_16V4Z~D
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
2
1
C665
0.1U_0402_16V4Z~D
<39> CLK_TP_SIO
<39> DAT_TP_SIO
<35> CLK_KBD
<35> DAT_KBD
<35> CLK_MSE
<35> DAT_MSE
<43> PBAT_SMBDAT
<43> PBAT_SMBCLK
2
1
MISC INTERFACE
PS/2 INTERFACE
9
10
75
76
77
78
79
80
111
112
1
C664
0.1U_0402_16V4Z~D
2
U36
1 HOST_DEBUG_TX
10K_0402_5%~D
2
R1032
1
C663
10U_0805_10V4Z~D
2
C660
0.1U_0402_16V4Z~D
1
R541
1
2
+RTC_CELL_VBAT
1
C662
0.1U_0402_16V4Z~D
1
2
R544
0_0402_5%~D
2
@ C658
1U_0402_6.3V6K~D
POWER_SW_IN#
+3.3V_ALW
+RTC_CELL
C661
0.1U_0402_16V4Z~D
2 CKG_SMBDAT
2.2K_0402_5%~D
2 CKG_SMBCLK
2.2K_0402_5%~D
2 BC_DAT_ECE5028
100K_0402_5%~D
1 BC_DAT_EMC4002
100K_0402_5%~D
1 BC_DAT_ECE1077
100K_0402_5%~D
1 DOCK_SMB_ALERT#
10K_0402_5%~D
2 LCD_SMBCLK
2.2K_0402_5%~D
2 LCD_SMBDAT
2.2K_0402_5%~D
2 PBAT_SMBDAT
2.2K_0402_5%~D
2 PBAT_SMBCLK
2.2K_0402_5%~D
1 LPC_LDRQ#_MEC5035
100K_0402_5%~D
2 CARD_SMBDAT
2.2K_0402_5%~D
2 CARD_SMBCLK
2.2K_0402_5%~D
1
R540
1
R542
1
R543
2
R545
2
R546
2
R547
1
R548
1
R549
1
R551
1
R552
2
@ R837
1
R838
1
R839
D
1
2
+3.3V_ALW
ACAV_IN <18,48>
2
R1031
1=JTAG interface Reset disabled
0=Reset JTAG interface
1
0_0402_5%~D
MEC5035_XVTQFP128_14X14~D
1
2
L40
BLM18AG121SN1D_0603~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
EMC5035
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
38
of
63
5
4
3
2
1
2
1
2
1
1
2
2
1
1
@
2
@
2
R595
4.7K_0402_5%~D
@
@
DAT_TP_SIO
2
1
2
CLK_TP_SIO <38>
C683
10P_0402_50V8J~D
1
D
DAT_TP_SIO <38>
CLK_TP_SIO
C682
10P_0402_50V8J~D
2
R594
4.7K_0402_5%~D
2
C680
10P_0402_50V8J~D
Place close to JTP1 connector
1
+5V_RUN
R1094
TP_CLK
1
R1093
L41
1
2
BLM18AG601SN1D_0603~D
1
2
L42
BLM18AG601SN1D_0603~D
TP_DATA
C681
10P_0402_50V8J~D
D54
SD05.TCT_SOD323-2~D
D53
SD05.TCT_SOD323-2~D
D
4.7K_0402_5%~D
4.7K_0402_5%~D
TP_CLK
TP_DATA
1
+5V_ALW
C
C
Power Switch for debug
JTP1
+5V_RUN
+5V_ALW
+3.3V_RUN
TP_DET#
17
18
G1
G2
B
+5V_RUN
1
2
+3.3V_RUN
1
2
POWER_SW#_MB
1
1
2
2
1
@ C684
100P_0402_50V8J~D
Close to JTP1
2
PWR_SW1
@SHORT PADS~D
Place on Top
+3.3V_ALW
1
2
TYCO_1-1775737-6
<31,38> POWER_SW#_MB
C771
0.1U_0402_16V4Z~D
<38> KYBRD_BKLT_PWM
<37> TP_DET#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C679
0.1U_0402_16V4Z~D
TP_CLK
TP_DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C678
0.1U_0402_16V4Z~D
<38> BC_DAT_ECE1077
<38> BC_CLK_ECE1077
<38> BC_INT#_ECE1077
+3.3V_ALW
1
1
2
2
B
PWR_SW2
@SHORT PADS~D
Place on Bottom
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Touch PAD/Int KB/LID
Size
http://hobi-elektronika.net
4
3
Rev
1.0
LA-4051P
Date:
5
Document Number
2
Thursday, June 05, 2008
Sheet
1
39
of
63
A
5
4
3
2
1
+5VRUN Source
4
6
Q57A
2N7002DW-T/R7_SOT363-6~D
2
3
5
1
C688
3300P_0402_50V7K~D
2
Q56A
2N7002DW-T/R7_SOT363-6~D
2
<19,28,37,41> RUN_ON
4
6
1
2
3
RUN_ON_3V#
C692
4700P_0402_25V7K~D
5
Q64A
2N7002DW-T/R7_SOT363-6~D
2
R607
20K_0402_5%~D
1
2
4
2
C693
470P_0402_50V7K~D
C
1
1
3
1
S
D
2
G
S
S
R614
20K_0402_5%~D
1
2
4
S
1
2
1
1
2
D
RUN_ON_3V# 2
G
D
3
S
1
1
2
1
1
2
S
D
2
G
3
S
D
2
G
3
D
2
G
1
1
2
1
RUN_ON_5V#
3
D
2
G
3
1
2
1
1
2
S
ALW_ON_3.3V#
3
1
1
2
3
4
1
C695
10U_0805_10V4Z~D
1
1
2
3
2
2
D
2
G
+1.05V_VCCP
@ Q80
@ R626
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
SUS_ON_3.3V#
+3.3V_RUN
Q79
2N7002W-7-F_SOT323-3~D
C698
4700P_0402_25V7K~D
+0.9V_DDR_VTT
R625
39_0402_5%~D
6
C697
470P_0402_50V7K~D
B
@ Q78
@ R624
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
2
@ R621
470K_0402_5%~D
@ Q77
@ R623
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
1
+1.5V_RUN
@ Q76
@ R622
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
1
2
2
2
<37> 1.05V_RUN_ON
@ Q82
2N7002W-7-F_SOT323-3~D
@R628
@
R628
1K_0402_5%~D
@ R629
200K_0402_5%~D
Q74A
2N7002DW-T/R7_SOT363-6~D
2
1
Q70B
2N7002DW-T/R7_SOT363-6~D
1
+3.3V_ALW_ICH
@ Q81
2N7002W-7-F_SOT323-3~D
@R627
@
R627
1K_0402_5%~D
1
+3.3V_SUS
ENAB_3VLAN <29>
5
3
Q70A
2N7002DW-T/R7_SOT363-6~D
+5V_RUN
Q74B
2N7002DW-T/R7_SOT363-6~D
N21917830
5
+1.05V_VCCP
Discharge Circuit
R619
100K_0402_5%~D
R620
100K_0402_5%~D
2
1
RUN_ON_1.05V#
+15V_ALW
+3.3V_ALW2
1
2
3
1
2
@ D31
RB751V_SOD323-2~D
1
2
R618
0_0402_5%~D
2
1
2
1
1
D
2
G
R617
100K_0402_5%~D
4
2
Q68A
2N7002DW-7-F_SOT363-6~D
M_ON_3.3V#
C696
4700P_0402_25V7K~D
R613
100K_0402_5%~D
6
4
6
1
8
7
6
5
+3.3V_M
3
1
1
+1.05V_M
2
3
2
2
3
G
1
NTMS4107NR2G_SO8~D
Q67
+1.05V_M
1
D
S
4
M_ENABLE
+15V_ALW
Discharge Circuit
@ Q71
2N7002W-7-F_SOT323-3~D
@R615
@
R615
75_0603_5%~D
2
+3.3V_ALW2
@ Q72
2N7002W-7-F_SOT323-3~D
@R616
@
R616
1K_0402_5%~D
6
5
2
1
Q68B
2N7002DW-7-F_SOT363-6~D
M_ON_3.3V# 5
+3.3V_M
R612
20K_0402_5%~D
1
Q66
SI3456BDV-T1-E3_TSOP6~D
C694
10U_0805_10V4Z~D
2
+3.3V_ALW
R610
100K_0402_5%~D
1
+15V_ALW
R611
100K_0402_5%~D
A
2
1
+1.05V_VCCP Source
+3.3VM Source
+3.3V_ALW2
<38> AUX_ON
1
Q64B
2N7002DW-T/R7_SOT363-6~D
+3.3V_RUN
2
<37> 3.3V_RUN_ON
2
1
2
3
1
2
@ D30
RB751V_SOD323-2~D
1
2
R609
0_0402_5%~D
2
1
1
8
7
6
5
2
1
R608
100K_0402_5%~D
4
5
Q62A
2N7002DW-T/R7_SOT363-6~D
NTMS4107NR2G_SO8~D
Q61
+3.3V_ALW
R606
100K_0402_5%~D
6
4
3
2
Q62B
2N7002DW-T/R7_SOT363-6~D
SUS_ON_3.3V#
C
2
2
1
2
1
SUS_ENABLE
1
R605
20K_0402_5%~D
C690
10U_0805_10V4Z~D
R604
100K_0402_5%~D
+15V_ALW
+3.3V_SUS
C691
10U_0805_10V4Z~D
+3.3V_ALW2
Q60
STS11NF30L_SO8~D
8
1
7
2
6
3
5
R603
100K_0402_5%~D
+3.3V_ALW2
<38,45> M_ON
1
1
1
+3.3V_ALW
B
D
+3.3V_RUN Source
+3.3V_SUS Source
+15V_ALW
<38,41> SUS_ON
R600
20K_0402_5%~D
2
2
1
Q56B
2N7002DW-T/R7_SOT363-6~D
RUN_ON_5V#
2
<38> ICH_ALW_ON
2
6
1
5
R601
20K_0402_5%~D
2
+5V_RUN
1
RUN_ENABLE
4
Q57B
2N7002DW-T/R7_SOT363-6~D
ALW_ON_3.3V#
1
2
G
3
2
2
3
ALW_ENABLE
Q55
STS11NF30L_SO8~D
1
2
3
C689
2200P_0402_50V7K~D
R602
100K_0402_5%~D
2
4
C687
10U_0805_10V4Z~D
1
R599
100K_0402_5%~D
S
1
6
5
2
1
R597
100K_0402_5%~D
8
7
6
5
4
1
Q54
+3.3V_ALW_ICH
SI3456BDV-T1-E3_TSOP6~D
R598
100K_0402_5%~D
+5V_ALW
C686
10U_0805_10V4Z~D
+3.3V_ALW2
+15V_ALW
1
+3.3V_ALW
D
+15V_ALW
D
+3.3V_ALW2
+3.3V_ALW_ICH Source
DC/DC Interface
S
RUN_ON_1.05V# 2
G
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
POWER CONTROL
Size
Document Number
Date:
Tuesday, June 10, 2008
Rev
1.0
LA-4051P
Sheet
1
40
of
63
3
2
Q84
MMST3904-7-F_SOT323-3~D
1
A
8
P
P
8
+3.3V_ALW
Y
7
6
A
U39A
74LVC3G14DC_VSSOP8~D
+3.3V_ALW
2
Y
U39B
74LVC3G14DC_VSSOP8~D
1
C700
0.1U_0402_16V4Z~D
2
14
D
1
1
2
R636
0_0402_5%~D
<19,28,37,40> RUN_ON
2
14
3
E
U40A
74VHC08MTCX_NL_TSSOP14~D
IN1
OUT 3
IN2
+3.3V_ALW
P
1
C
C699
0.1U_0402_16V4Z~D
2
G
2
R635
4.7K_0402_5%~D
1
2
2
B
C703
2200P_0402_50V7K~D
2
1
1
7
3
2
1
1
1
2
B
2
R634
200K_0402_5%~D
C702
0.1U_0402_16V4Z~D
E
1
D32
RB751V_SOD323-2~D
1
Q83
MMBT3906WT1G_SC70-3~D
C
2
D
R633
10K_0402_5%~D
1
2
1
G
+5V_RUN
+3.3V_ALW
4
<50> 1.1V_GFX_PWRGD
2
+5V_ALW
1
0_0402_5%~D
1
0_0402_5%~D
1
0_0402_5%~D
1
0_0402_5%~D
R632
C701
100K_0402_5%~D 0.1U_0402_16V4Z~D
<45> 1.5V_RUN_PWRGD
<50,54> GFX_CORE_PWRGD
2 @
R630
2
R631
2
R808
2 @
R809
1
+3.3V_SUS
<18,37> 2.5V_RUN_PWRGD
G
4
4
5
E
2
R639
4.7K_0402_5%~D
1
2
2
B
U40B
74VHC08MTCX_NL_TSSOP14~D
RUNPWROK
6
RUNPWROK <37,38,47,50>
G
IN2
C
+3.3V_ALW
Q86
MMST3904-7-F_SOT323-3~D
14
C705
2200P_0402_50V7K~D
2
1
1
E
3
IN1
IN2
+3.3V_ALW
P
10
3.3V_5V_SUS_PWRGD 9
OUT
G
<38,40> SUS_ON
+3.3V_ALW
8
SUSPWROK <38>
U40C
74VHC08MTCX_NL_TSSOP14~D
7
1
2
R638
200K_0402_5%~D
C704
0.1U_0402_16V4Z~D
2
1
2
R637
1 10K_0402_5%~D
5
Q85
MMBT3906WT1G_SC70-3~D
B
1
OUT
C
2
D33
RB751V_SOD323-2~D
1
IN1
7
3
+3.3V_RUN
P
4
+3.3V_ALW
+3.3V_SUS
3
8
+3.3V_M
P
Y
G
A
5
1
3
4
U39C
74LVC3G14DC_VSSOP8~D
R640
100K_0402_5%~D
2
+3.3V_ALW
IN1
RESET_OUT#
12
IN2
1
13
11
OUT
ICH_PWRGD
S
H7
@H_3P0
H8
@H_3P0
1
1
1
1
1
1
1
<18>
ICH_PWRGD
H9
H10
H11
H22
H12
@H_3P0 @H_3P0 @H_3P0 @H_2P2 @H_3P0
<10,24>
1
H6
@H_3P0
1
H5
@H_3P0
1
H4
@H_3P0
1
H3
@H_3P0
1
H2
@H_3P0
1
IO board
H1
@H_3P0
ICH_PWRGD#
Q87
2N7002W-7-F_SOT323-3~D
2
G
U40D
74VHC08MTCX_NL_TSSOP14~D
7
<38> RESET_OUT#
IMVP_PWRGD
3
14
ICH_PWRGD#
D
P
<24,37,47> IMVP_PWRGD
G
1
2
2
1
1
B
1
C
2
E
C
Q88
MMBT3906WT1G_SC70-3~D
D35
RB751V_SOD323-2~D
2
1
R643
200K_0402_5%~D
2
C707
0.1U_0402_16V4Z~D
R641
10K_0402_5%~D
1
2
2
C708
2200P_0402_50V7K~D
1
R642
200K_0402_5%~D
D34
RB751V_SOD323-2~D
2
1
C
+3.3V_ALW
+3.3V_ALW
+3.3V_M
2
2
eDOCK x 2
3
8
P
2
CPU x 4
1
2
1
1
A
Y
G
2
C709
0.1U_0402_16V4Z~D
D37
RB751V_SOD323-2~D
4
1
1
1
1
1
1
1
1
1
1
1
R646
200K_0402_5%~D
1
@
B
Q89
MMBT3906WT1G_SC70-3~D
1
H25
H_5P0
1
H21
H_3P75
1
H24
H_6P1
B
H15
H14
@H_5P3 @H_5P3
E
H20
@H_3P9
R644
10K_0402_5%~D
1
2
2
C710
2200P_0402_50V7K~D
H19
@H_4P0
R645
200K_0402_5%~D
H16
H17
H23
H18
@H_4P2 @H_3P8 @H_4P2 @H_4P2
D36
RB751V_SOD323-2~D
2
1
C
B
+3.3V_ALW
A
1
3
8
P
1
2
1
FIDUCIAL MARK~D
GND
FD4
2
1
D41
RB751V_SOD323-2~D
6
A
Y
G
2
4
FIDUCIAL MARK~D
FD3
1
1
1
FIDUCIAL MARK~D
2
1
C714
0.1U_0402_16V4Z~D
B
1
CLIP2
EMI_CLIP
2
C
1
1
FD2
E
FD1
C713
0.1U_0402_16V4Z~D
1
2
Q91
MMBT3906WT1G_SC70-3~D
R653
200K_0402_5%~D
GND
Fiducial Mark
C715
2200P_0402_50V7K~D
CLIP1
EMI_CLIP
R652
200K_0402_5%~D
EMI CLIP
R651
10K_0402_5%~D
1
2
2
3.3V_M_PWRGD <18,38>
+3.3V_ALW
+3.3V_LAN
D40
RB751V_SOD323-2~D
2
1
7
U41A
74LVC3G14DC_VSSOP8~D
2
3.3V_LAN_PWRGD <38>
U41B
74LVC3G14DC_VSSOP8~D
A
FIDUCIAL MARK~D
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Power Good
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
41
of
63
3
2
3
1
6
2
+5V_ALW
Q140A
LED 2.3mA
2
ON MB
2 BATT_BLUE_LED
1K_0402_5%~D
1
R665
2
2N7002W-7-F_SOT323-3~D
2
BREATH_BLUE_LED_LCD <19>
2N7002DW-7-F_SOT363-6~D
Q142A
2N7002DW-7-F_SOT363-6~D
LED 2.3mA
1
6
2
1
SYS_LED_MASK#
+3.3V_ALW
1
3
YEL
LTST-C155TBJSKT_Blue/YEL~D
MASK_BASE_LEDS#
2
G
+5V_ALW
Q148
DDTA114EUA-7-F_SOT323-3~D
2BREATH_BLUE_LED_LCD
1K_0402_5%~D
3
S
4
Q141A
1
R1000
Q153
1
1
U68
NC7SZ04P5X_NL_SC70-5~D
D
D46
BLUE
1
R999
100K_0402_5%~D
4
Y
D
A
1
1
5
P
2
<38> BAT2_LED#
BAT2_LED
2
LED 19mA
3
SYS_LED_MASK#
+3.3V_ALW
6
2
Q146
DDTA114EUA-7-F_SOT323-3~D
2N7002DW-7-F_SOT363-6~D
BREATH_BLUE_LED_IO <31>
2
1
BREATH LED
3
1
6
4
1 R997
2BREATH_BLUE_LED_IO
100_0402_5%~D
1
100K_0402_5%~D
BATTERY LED
R996
+5V_ALW
100K_0402_5%~D
NC
Q144B
2N7002DW-T/R7_SOT363-6~D
1
+5V_ALW
G
1
3
2
5
BREATH_LED
3
+5V_ALW
R998
1
+3.3V_ALW
2
2
Q147
4
Y
U42
3
MASK_BASE_LEDS#
Q144A
2N7002DW-T/R7_SOT363-6~D
G
A
NC7SZ04P5X_NL_SC70-5~D
4
2
3
2N7002DW-T/R7_SOT363-6~D
Q145B
5
6
1
5
P
NC
2
<35,38> BREATH_LED#
D
1
2
2N7002DW-T/R7_SOT363-6~D
Q145A
+3.3V_ALW
3
2
100K_0402_5%~D
Q143
R995
1
+3.3V_ALW
DDTA114EUA-7-F_SOT323-3~D
4
+5V_ALW
DDTA114EUA-7-F_SOT323-3~D
5
R906
100K_0402_5%~D
+3.3V_WLAN
1
1
2
2N7002DW-7-F_SOT363-6~D
Q142B
2N7002DW-7-F_SOT363-6~D
3
2
5
4
Q150
LED 2.3mA
3
5
SYS_LED_MASK#
1
2
Q151B
DDTA114EUA-7-F_SOT323-3~D
Q141B
Q115
DDTA114EUA-7-F_SOT323-3~D
1
C
+3.3V_ALW
1
WWAN LED solution for Blue LED
3
+3.3V_RUN
BATT_YELLOW_LED
2
150_0402_5%~D
1
R1003
3
2
D45
LTST-C191TBKT-5A BLU_0603~D
+5V_RUN
R905
100K_0402_5%~D
4
U69
NC7SZ04P5X_NL_SC70-5~D
1
G
2 WLAN_LED
1K_0402_5%~D
1
R663
Y
DDTA114EUA-7-F_SOT323-3~D
4
2
SDM10U45-7_SOD523-2~D
MASK_BASE_LEDS#
ON LCD
1
R903
2
1K_0402_5%~D
BATT_BLUE_LED_LCD <19>
1
R904
2
150_0402_5%~D
BATT_YELLOW_LED_LCD <19>
1
2N7002DW-7-F_SOT363-6~D
2
R206
100K_0402_5%~D
A
3
D66
C
2
5
4
P
<38> BAT1_LED#
1
6
1
1
1
5
2
Q151A
2N7002DW-7-F_SOT363-6~D
<34> LED_WLAN_OUT#
BAT1_LED
LED 2.3mA
+3.3V_ALW
Q140B
NC
1
Q97
DDTA114EUA-7-F_SOT323-3~D
2
Q149
2
3
+3.3V_ALW
2
R662
100K_0402_5%~D
3
2N7002DW-7-F_SOT363-6~D
WLAN LED solution for Blue LED
3
2
+3.3V_ALW
+5V_RUN
4
3
2 WWAN_LED
1K_0402_5%~D
1
R125
5
<34> LED_WWAN_OUT#
2
1
D61
LTST-C191TBKT-5A BLU_0603~D
+5V_RUN
MASK_BASE_LEDS#
LED 2.3mA
3
KEYBOARD STATUS LED
1
Q94
DDTA114EUA-7-F_SOT323-3~D
+5V_ALW
2
R660
10K_0402_5%~D
2
6
0_0402_5%~D
Q120
DDTA114EUA-7-F_SOT323-3~D
3
2
MASK_BASE_LEDS#
2
<37> CAP_LED#
WPAN_LED
2
2
1
1K_0402_5%~D
LTST-C191TBKT-5A BLU_0603~D
1
R661
Q154
2N7002W-7-F_SOT323-3~D
1
R556
+3.3V_ALW
1
<37> SCRL_LED#
2
Q121
DDTA114EUA-7-F_SOT323-3~D
3
3
SNIFFER LED
R_CAP_LED#
2
1K_0402_5%~D
2
1
R596
1
1
D57
LTST-C191TBKT-5A BLU_0603~D
R_NUM_LED#
2
1K_0402_5%~D
2
Q122
DDTA114EUA-7-F_SOT323-3~D
2
D
2
<37> NUM_LED#
1
D58
LTST-C191TBKT-5A BLU_0603~D
1
@
1
Q100
DDTA114EUA-7-F_SOT323-3~D
1
R655
1
R667 @
SNIFFER_YELLOW
2
220_0402_5%~D
SNIFFER_YELLOW
R_SCRL_LED#
2
1K_0402_5%~D
2
B
3
MASK_BASE_LEDS# 2
G
1
LED 2.3mA
S
D43
B
<37> SNIFFER_YELLOW#
R1036
1
1
2
1
<34> LED_WPAN_OUT#
3
WPAN LED solution for Blue LED
Q152A
2N7002DW-7-F_SOT363-6~D
@
+3.3V_RUN
1
D59
LTST-C191TBKT-5A BLU_0603~D
<31>
LED 2.3mA ALL
3
+5V_ALW
+3.3V_ALW
Q102
DDTA114EUA-7-F_SOT323-3~D
5
2
LID_CL#
1
IN1
SYS_LED_MASK#
2
IN2
P
<31,37> LID_CL#
O
3
1
<37> SYS_LED_MASK#
SNIFFER_BLUE
2
1K_0402_5%~D
1
R668
SNIFFER_BLUE <31>
4
MASK_BASE_LEDS#
G
<37> SNIFFER_BLUE#
U14
74AHC1G08GW_SOT353-5~D
BIOS GPIO Table for LED Control
SYS_LED_MASK#
+3.3V_RUN
+5V_RUN
HDD LED solution for Blue LED
1
A
Q92
DDTA114EUA-7-F_SOT323-3~D
2
Q152B
Low
X
MASK BASE MB LEDs (Lid Closed)
High
Low
Do Not Mask LEDs (Lid Opened)
High
High
A
2
2N7002DW-7-F_SOT363-6~D
4
3
Compal Electronics, Inc.
LED 2.3mA
5
1
<23> SATA_ACT#_R
MASK ALL LED (SNIFFER FUNCTION)
3
R654
10K_0402_5%~D
LID_CL#
1
R659
MASK_BASE_LEDS#
http://hobi-elektronika.net
5
2SATA_LED
1K_0402_5%~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
D42
LTST-C191TBKT-5A BLU_0603~D
4
3
2
Title
LED
Size
Document Number
Date:
Tuesday, June 10, 2008
Rev
1.0
LA-4051P
Sheet
1
42
of
63
5
4
3
2
1
+COINCELL
1
COIN RTC Battery
PR1
1K_0402_5%~D
JRTC1
1
2
3
2
+COINCELL
Z4012
+3.3V_RTC_LDO
D
1
2 G1
3 G2
4
5
MOLEX_53398-0371~D
D
3
2
+3.3V_ALW
+RTC_CELL
1
PD1
BAT54CW_SOT323~D
DA204U_SOT323~D @
PD5
DA204U_SOT323~D
PJP1
PC2
0.1U_0603_25V7K~D
2
1
1
FOX_BP02093-P5652-7F~D
9
8
7
6
5
4
3
2
1
PR3
100_0402_5%~D
1
2
Z4304
Z4305
Z4306
PR4
100_0402_5%~D
1
2
PR5
100_0402_5%~D
1
2
PBAT_SMBCLK <38>
PBAT_SMBDAT <38>
PR6 @
100_0402_5%~D
1
2
PBAT_ALARM#
PBATT+
Move to power schematic @ RTC BATTERY
PAD-OPEN 4x4m
Part Number
Description
DAA00000R0L
PCB 03P LA-4051P REV0 M/B
PBAT_PRES# <37>
PBATT1
PQ69
FDN338P_SOT23-3~D
1
2
1
3
DOCK_SMB_ALERT#
<35,38>
2
2
PD32
RB751V-40_SOD323~D
C
3
GND
GND
9
8
7
6
5
4
3
2
1
2
1
PC3
2200P_0402_50V7K~D
2
1
11
10
PC1
1U_0603_10V6K~D
27.4
2
PD3
PD4
DA204U_SOT323~D
@
+3.3V_ALW
PR2
10K_0402_1%~D
2
1
@
1
PD2
DA204U_SOT323~D
1
@
1
Primary Battery Connector
1
PL1
FBMA-L18-453215-900LMA90T_1812~D
1
2
1
2
3
2
3
2
3
2
3
ESD Diodes
C
PR8
2.2K_0402_5%~D
1
2
2
3
1
1
4
PS_ID <38>
<37>
2
3
@
B
1
2
3
PD8
DA204U_SOT323~D
1
1
COM
GPIO_PSID_SELECT
PR13
1
2
PSID_DISABLE#
<37>
10K_0402_5%~D
1
2
PC9
10U_1206_25V6M~D
PR15
4.7K_0805_5%~D
2
1
PC8
0.1U_0603_25V7K~D
2
1
PR18
22K_0402_5%~D
2
1
PC7
0.1U_0603_25V7K~D
2
1
PC6
0.1U_0603_25V7K~D
2
1
4
1
PR14
2
1M_0402_5%~D
+DC_IN_SS
A
1
1
PR342
100K_0402_5%~D
1
2
D
S
1
2
G
NB_AC_OFF
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
http://hobi-elektronika.net
CONN SET 03N DCJACK-MB
WDMD-DCJAL201-DF
5
4
DELL CONFIDENTIAL/PROPRIETARY
<37,48,49>
PC12
0.1U_0603_25V7K~D
2
5
3
PQ5
RHU002N06_SOT323
Description
PQ4A
IMD2AT-108_SC74-6~D
<49> NB_AC_OFF_BJT
6
PC11
0.1U_0603_25V7K~D
2
1
@ DC-IN cable
DC301003B0L
+5V_ALW
@
MOLEX_87437-0763
Part Number
+5V_ALW
@
DC_IN+ Source
4
PR17
1M_0402_5%~D
2
1
3
PC4
0.022U_0805_50V7K
1
2
PQ4B
IMD2AT-108_SC74-6~D
2
@
PL4
FBMJ4516HS720NT_1806~D
1
2
V+
8
7
6
5
+DC_IN
2
1
PR16
0_0402_5%~D
+DCIN_JACK
PC5
0.1U_0603_25V7K~D
2
1
-DCIN_JACK
PD9
VZ0603M260APT_0603
PC10
0.1U_0603_25V7K~D
2
1
A
NC
6
5
TS5A63157DCKR_SC70-6~D
E
PR12
15K_0402_1%~D
1
2
1
1
2
3
@
2
PQ3
FDS6679AZ_SO8~D
+DC_IN
PL3
FBMJ4516HS720NT_1806~D
1
2
1
2
3
4
5
6
7
3
GND
IN
<37>
@
1
2
3
4
5
6
7
NB_PSID_TS5A63157
NO
1
DCIN_CBL_DET#
2
PC254
0.47U_0402_6.3V6K
PR221
0_0402_5%~D
1
2
PJPDC1
2
+5V_ALW
PQ2
MMST3904-7-F_SOT323~D
2
B
PU1
1
<35> DOCK_PSID
1
@
PQ1
FDV301N_SOT23~D
C
@
PD7
SM24_SOT23
2
3
PD17
DA204U_SOT323~D
B
3
2
G
PR10
100K_0402_1%~D
1
2
3
2
1
+3.3V_ALW
PR9
33_0402_5%~D
1
2
+3.3V_ALW
PR11
10K_0402_1%~D
D
PL2
BLM18BD102SN1D_0603~D
2
1
NB_PSID
1
PR7
1
2
0_0402_5%~D
S
@
PD6
DA204U_SOT323~D
+5V_ALW
2
PC257
1500P_0402_7K~D
<35,37,49> SLICE_BAT_PRES#
3
2
+DCIN
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4041P
Sheet
1
43
of
63
5
4
3
2
1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
+DC1_PWR_SRC
D
D
PJP2
1
+PWR_SRC
2
3
2
1
PC35
220U_V_6.3VM_R25M~D
PR31
0_0402_5%~D
2
1
PR35
0_0402_5%~D
2
1
1
NC
5
6
7
8
+3.3V_ALW_LGATE
1
PR212
4.7_1206_5%~D
PR33
2.2_0402_1%~D
+3.3V_ALW_BOOT1
2
PQ9
FDS6676AS_NL_SO8~D
4
3
2
1
1
SN0608098_QFN32_5X5~D
+3.3V_ALWP
PL6
3.0UH_HMP1362-3R0-R_17A_20%~D
2
GNDA_3V5V
C
G
1
+
2
PC169
220U_V_6.3VM_R25M~D
GNDA_3V5V
2 PR29 0_0402_5%~D
1
POK2
2
1 EN_3V_5V
+3.3V_ALW_UGATE PR210 0_0402_5%~D
+3.3V_ALW_PHASE
+5V_ALW_LGATE
PC22
10U_1206_25V6M~D
2
1
2
1
PC21
10U_1206_25V6M~D
2
1
PC20
10U_1206_25V6M~D
5
6
7
8
D
D
D
D
4
PQ7
FDS8880_NL_SO8~D
S
S
S
32
31
30
29
28
27
26
25
PC31
0.1U_0603_25V7K~D
LDOREFIN
LDO
VIN
VREF3
EN_LDO
V5FILT
TONSEL
VREF2
@
PR27
187K_0402_1%~D
1
2
GNDA_3V5V
PR32
2.2_0402_1%~D
1
2 +5V_ALW_BOOT
1
PC34
0.1U_0402_10V7K~D
2
1
1
2
@ PR26
0_0402_5%~D
REFIN2
TRIP2
VOUT2
SKIPSEL
PGOOD2
EN2
DRVH2
LL2
PC19
0.1U_0805_50V7K
2
1
PC26
1U_0603_10V6K~D
2
1
EN_3V_5V
8
7
6
5
4
3
2
1
PAD
EN_3V_5V
PC30
0.1U_0603_25V7K~D
2
1
8
7
6
5
1
2
3
33
1
2
3
1
FDS6676AS_NL_SO8~D
4
PR211
4.7_1206_5%~D
NC
PR34
0_0603_5%~D
1
2
@
PQ8
VSW
VOUT1
VFB1
TRIP1
PGOOD1
EN1
DRVH1
LL1
3.3 Volt +/-5%
Thermal Design Current: 7.39A
Peak current: 10.56A
OCP min: 13A
PR25
@ PR24
0_0603_5%~D
2
S
S
S
PR28
GNDA_3V5V 150K_0402_1%~D
PR209
1
2
ALW_PWRGD_3V_5V
0_0402_5%~D
2
1
+5V_ALW_UGATE
+5V_ALW_PHASE
9
10
11
12
13
14
15
16
0_0402_5%~D
2
@
1
PC198
1000P_0603_25V7K~D
2
2
1
PR30
0_0603_5%~D
1
2
PC33
0.1U_0402_10V7K~D
2
1
PC32
330U_D3L_6.3VM_R25~D
2
PU2
+5V_ALWP
GNDA_3V5V
2
VBST1
DRVL1
V5DRV
SECFB
GND
PGND
DRVL2
VBST2
4
GNDA_3V5V
PL5
3.0UH_HMP1362-3R0-R_17A_20%~D
2
PC27
0.1U_0603_25V7K~D
1
2
17
18
19
20
21
22
23
24
8
7
6
5
D
D
D
D
PQ6
FDS8880_NL_SO8~D
+5V_ALWP
+
@ PR23
0_0402_5%~D
1
2
PC29
0.1U_0402_10V7K~D
2
1
PC23
4.7U_0805_6.3V6K
2
1
PC25
1U_0603_10V6K~D
2
1
PC24
1U_0603_25V7K~D
2
1
PR22
@ 0_0402_5%~D
1
2
1
G
1
PR21
10_0603_5%~D
2
1
PAD-OPEN1x1m
+3.3V_ALW2
PC28
0.1U_0402_10V7K~D
2
1
C
2
@
GNDA_3V5V
5 Volt +/-5%
Thermal Design Current:6.62A
Peck current: 9.46A
OCP min: 11.3A
+5V_VCC1
PC18
2200P_0402_50V7K~D
2
1
PJP3
1
+5V_ALW2
PC199
1000P_0603_25V7K~D
2
2
1
PR20
0_0805_5%
1
2
PR19
0_0805_5%
1
2
PC17
10U_1206_25V6M~D
2
1
PC16
10U_1206_25V6M~D
2
1
PC15
10U_1206_25V6M~D
2
1
PC13
2200P_0402_50V7K~D
2
1
Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
H_MOSFET FDS8880
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
Inductor 4.7U_HMU1356-4R7-R_10A(DELTA)
PC14
0.1U_0805_50V7K
2
1
PAD-OPEN 4x4m
VOUT1=5V
L=4.7uF
Fsw=400KHz
D=0.265
Output Ripple Current=1.97A
Output Ripple Voltage=1.97A*25mOhm=49.37mV)
Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A
1
+
2
@
GNDA_3V5V
GNDA_3V5V
PC39
0.1U_0603_25V7K~D
1 1
2
2
2
+3.3V_ALW
PAD-OPEN1x1m
GNDA_3V5V
PD12
BAT54CW_SOT323~D
3
1
+15V_ALWP
(100mA,20mils ,Via NO.=1)
2
PJP6
+5V_ALWP
1
2
+5V_ALW
ALW_PWRGD_3V_5V
<38>
PR42
200K_0402_1%~D
2
1
PC40
0.1U_0603_25V7K~D
2
1
2
PAD-OPEN1x1m
PJP34
2
ALW_PWRGD_3V_5V
PJP5
PAD-OPEN 4x4m
Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
H_MOSFET FDS8880
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
Inductor 3.0U_HMP1362-3R0-R_17A(DELTA)
PR41
0_0402_5%~D
2
1
PR39
0_0402_5%~D
2
1
+15V_ALW
1
3
BAT54SW-7-F_SOT323-3~D
B
PR43
39.2K_0402_1%~D
1
2
<18> THERM_STP#
@
POK2
PD11
PR40
200K_0402_5%
1
2
<38> ALWON
PR38
2K_0402_5%~D
2
1
VOUT2=3.3V
L=3.0uF
Fsw=500KHz
D=0.176
Output Ripple Current=1.84A
Output Ripple Voltage=1.84A*25mOhm=46.05mV
Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A
+3.3V_ALW
PR37
200K_0402_1%~D
1
2
PD10
BAT54SW-7-F_SOT323-3~D
1
PR36
200K_0402_1%~D
1
2
3
PJP4
PC37
4.7U_0603_6.3V6K~D
2
1
B
PC36
0.1U_0603_25V7K~D
1 1
2
2
1
PC38
0.1U_0603_25V7K~D
2
1
+5V_ALWP
+5V_ALW2
GNDA_3V5V
PAD-OPEN 4x4m
A
A
GNDA_3V5V
PJP7
+3.3V_ALWP
1
2
+3.3V_ALW
PAD-OPEN 4x4m
DELL CONFIDENTIAL/PROPRIETARY
PJP35
1
Compal Electronics, Inc.
2
Title
PAD-OPEN 4x4m
DC/DC +3V/ +5V
http://hobi-elektronika.net
5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
3
2
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4041P
Sheet
1
44
of
63
5
4
3
2
1
+1.5V_RUN / +1.05V_M/ +3.3V_RTC_LDO
+DC2_PWR_SRC
PJP8
1
+PWR_SRC
2
PC47
2200P_0402_50V7K~D
2
1
PC46
0.1U_0603_25V7K~D
2
1
2
1
PC45
10U_1206_25V6M~D
2
1
1.05 Volt +/-5%
Thermal Design Current: 7.89A
Peack current: 11.27A
OCP min: 13.8A
D
D
D
D
5
6
7
8
3
2
1
S
S
S
G
+1.05V_MP
PL7
1.4UH_HMP1340-1R4_15A_20%~D
1
2
1
+
2
@
PC57
0.1U_0402_10V7K~D
1
2
+
PC56
10U_1206_6.3V7K
2
1
1
PC54
330U_D2E_2.5VM_R9
PR214
4.7_1206_5%~D
5
3
2
1
PQ13
FDMS8670S_MLP8~D
4
C
1
3
2
REFIN2_1_05
@
1
2
PR52
130K_0402_1%~D
GNDA_1P5V_1P05V
PR54 2 0_0402_5%~D
1
GNDA_1P5V_1P05V
1.05V_M_PWRGD
EN2
1.05V_UGATE
1.05V_PHASE
PC201
1000P_0603_50V7K~D
2
2
1
1
PQ10
FDS6298_SO8~D
PC53
330U_D2E_2.5VM_R9
2
PR47
0_0402_5%~D
2
VBST1
DRVL1
V5DRV
SECFB
GND
PGND
DRVL2
VBST2
PAD
1.5V_LGATE
4
GNDA_1P5V_1P05V
PC61
0.1U_0603_25V7K~D
1
2
32
31
30
29
28
27
26
25
17
18
19
20
21
22
23
24
33
2
1
PC60
0.1U_0603_25V7K~D
8
7
6
5
D
D
D
D
S
S
S
GNDA_1P5V_1P05V
PR57
2.2_0402_1%~D
1
2
@
1
GNDA_1P5V_1P05V
1
@ PR51
0_0402_5%~D
8
7
6
5
4
3
2
1
PU3
GNDA_1P5V_1P05V
9 VSW
REFIN2
10 VOUT1
TRIP2
PR53
11 VFB1
VOUT2
12 TRIP1
1
2
SKIPSEL
1.5V_RUN_PWRGD
130K_0402_1%~D
13 PGOOD1
PGOOD2
EN1
14
GNDA_1P5V_1P05V
EN2
1.5V_UGATE 15 EN1
DRVH2
1.5V_PHASE 16 DRVH1
LL1 SN0608098_QFN32_5X5~D LL2
4
2
PC52
0.1U_0402_10V7K~D
1
PR50
@ 0_0603_5%~D
LDOREFIN
LDO
VIN
VREF3
EN_LDO
V5FILT
TONSEL
VREF2
PR48
0_0402_5%~D
1
2
PR49
@ 0_0402_5%~D
1
2
2
@
1
2
3
PQ12
SI4812BDY-T1-E3_SO8~D
G
PR46
0_0402_5%~D
PC49
0.1U_0603_25V7K~D
REF 1
2
GNDA_1P5V_1P05V
PC63
1U_0603_10V6K~D
2
1
1
GNDA_1P5V_1P05V
1
2
3
1
PR213
4.7_1206_5%~D
PC200
1000P_0603_50V7K~D
2
2
1
PR55
0_0603_5%~D
1
2
@
PR56
0_0603_5%~D
1
2
@
PC59
0.1U_0402_10V7K~D
1
2
+
2
PC58
10U_1206_6.3V7K
2
1
1
PC55
330U_D2E_2.5VM_R9
PL8
3.3UH_FDVE0640-3R3M_7A_20%~D
2
1
4
PC51
0.1U_0402_10V7K~D
+1.5V_RUN_P
2
C
8
7
6
5
PQ11
SI4800BDY-T1_SO8~D
1
1.5 Volt +/-5%
Thermal Design Current: 2.63A
Peak current: 3.76A
OCP min: 4.3A
+3.3V_RTC_LDO
PC50
1U_0402_6.3V6K~D
2
1
2
+5V_VCC2
PC44
10U_1206_25V6M~D
PC48
PR45
1U_0603_25V7K~D 0_0805_5%~D
1
2
1
2
PR44
0_0805_5%~D
1
2
PC43
2200P_0402_50V7K~D
2
1
PC42
0.1U_0603_25V7K~D
2
1
D
PAD-OPEN 4x4m
PC41
10U_1206_25V6M~D
2
1
D
PR58
2.2_0402_1%~D
1
2
GNDA_1P5V_1P05V
1.05V_LGATE
GNDA_1P5V_1P05V
B
+5V_ALW
VOUT1=1.5V
L=3.3uF
Fsw=200KHz
D=0.081
Output Ripple Current=2.15A
Output Ripple Voltage=2.15A*15mOhm=32.27mV
Input Ripple Current=TDC*(D*(1-D))^0.5=0.97A
1.05V_M_PWRGD
1.05V_M_PWRGD <38>
1.5V_RUN_PWRGD
1.5V_RUN_PWRGD
B
VOUT2=1.05V
L=0.88uF
Fsw=300KHz
D=0.057
Output Ripple Current=3.88A
Output Ripple Voltage=3.88A*4.5mOhm=17.44mV
Input Ripple Current=TDC*(D*(1-D))^0.5=2.53A
+5V_VCC2
PC62
4.7U_0603_6.3V6K~D
2
1
@
Component select
Input CAP 10uF_1206_25V
Output Cap 220U_D2_4VM_R15(NEC_PSLV0G227M)
H_MOSFET SI4800BDY
L_MOSFET SI4810BDY(16/20mOhm@4.5V, 6A)
Inductor 3.3U_MPL73-3R3_6A(DELTA)
PR61
100K_0402_1%~D
1
2
PR60
100K_0402_1%~D
2
1
+3.3V_SUS +3.3V_ALW
@ PR59
10_0603_5%~D
2
1
Component select
Input CAP 10uF_1206_25V*2
Output Cap 330U_D2E_2.5VM_R9*2(Sanyo2R5TPE330M9)
H_MOSFET SI4682DY
L_MOSFET SI4362DY(4.2/5.5mOhm@4.5V, 15A)
Inductor 0.88U_MPC1040LR88_17A(NEC_TOKIN)
<41>
PJP9
PR207
0_0402_5%~D
2
1
EN1
PJP11
+1.5V_RUN_P
A
1
2
+1.5V_RUN
+3.3V_ALW
PAD-OPEN 4x4m
@PR62
@
PR62
100K_0402_1%~D
2
1
PR208
PR63
0_0402_5%~D 0_0402_5%~D
EN2 2
1
1
2
1
1.5V_RUN_ON <37>
2
2
PAD-OPEN 4x4m
PJP10
PJP12
1
1
+1.05V_MP
PAD-OPEN1x1m
2
+1.05V_M
A
PAD-OPEN 4x4m
GNDA_1P5V_1P05V
M_ON <38,40>
DELL CONFIDENTIAL/PROPRIETARY
OK to Short if CAD
System can Support
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
http://hobi-elektronika.net
5
4
3
2
+1.5V_RUN / +1.05V_VCCP
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4041P
Sheet
1
45
of
63
5
4
3
PL17
MURATA_BLM18SG221TN1E_0603~D
1
2
2
1
+1.8VSUSP/ +0.9V_DDR_VTT
DDR2 Termination
+DDR_PWR_SRC
PJP13
PAD-OPEN 4x4m
1
2
2
1
2
D
PC67
2200P_0402_50V7K~D
2
1
PC65
10U_1206_25V6M~D
PC64
10U_1206_25V6M~D
1
PC66
0.1U_0603_25V7K~D
2
1
+PWR_SRC
D
1
+1.8V_SUSP
23
1
19
DRVL
VTTSNS
2
18
PGND_D
GND
3
PC69
10U_0805_6.3V6M~D
S
S
S
24
1
2
3
3
VTT
2+1.8VSUSP_L
16
CS
14
V5FILT
13
PGOOD
11
S5
MODE
4
5
COMP
6
VDDQSNS
8
GNDA_DDR
VDDQSET
9
Design current 0.7A for +0.9V_DDR_VTTP
Peak current 1A for +0.9V_DDR_VTTP
0_0402_5%~D
PR69 @
0_0402_5%~D
2
PC74
0.033U_0603_16V6K~D
@
1
C
GNDA_DDR
+5V_ALW
1
2
TPS51116RGE_QFN24_4X4~D
PC170
0.1U_0402_10V7K~D
CS_GND
TP
25
PR67
+V_DDR_MCH_REF
1
2
PC75
GNDA_DDR
15
0_0402_5%~D
PR71
5.1_0402_1%~D
2
1
17
S3
V5IN
10
2
+1.8V_SUSP
PR65
0_0402_5%~D
VTTREF
PR70
1
1U_0603_10V6K~D
2
1
2
GNDA_DDR
1
2
3
<38> 1.8V_SUS_PWRGD
<37> 0.9V_DDR_VTT_ON
2
+0.9V_DDR_VTTP
1
2
1
7.32K_0402_1%~D
PR68
200K_0402_1%~D
<38> DDR_ON
1
PR66
2
4
2
1
2
5
FDMS8670S_MLP8~D
PQ15
+3.3V_ALW
1
1
TPS51116_DRVL
PR215
4.7_1206_5%~D
1
2
+
2
PC73
0.1U_0402_10V7K~D
+
2
1
PC72
330U_D2_2.5VY_R15M
1
PC71
330U_D2_2.5VY_R15M
C
PC202
1000P_0603_50V7K~D
2
2
1
1
PL9
1.4UH_HMP1362-1R4_25A_20%~D
1
2
VTTGND
1
LL
2
DRVH
20
VLDOIN
1
VBST
21
PC171
10U_0805_6.3V6M~D
22
2.2_0603_1%~D
TPS51116_DRVH
PC70
10U_0805_6.3V6M~D
1
4
PC203
1U_0402_6.3V6K~D
NC
2
7
PU4
NC
@
PC68
PR64
0.22U_0603_10V7K~D
1
2
2
12
2
D
D
D
D
PQ14
FDS6298_SO8~D
G
+1.8V_SUSP
1
8
7
6
5
1.8 Volt +/-5%
Thermal Design Current: 9.11A
Peck current: 13.01A
OCP min: 14.02A
PD13
RB751V-40_SOD323~D
+5V_ALW
@
PC76
1U_0603_10V6K~D
GNDA_DDR
+5V_ALW
GNDA_DDR
B
B
PJP14
@ PR205
@ PR206
27.4K_0402_1%~D
17.4K_0603_1%~D
1
2
1
2
GNDA_DDR
2
1
2
PAD-OPEN1x1m
GNDA_DDR
1
PR174
0_0402_5%~D
PJP15
PAD-OPEN 4x4m
1
2
+5V_ALW
PJP16
PAD-OPEN 4x4m
1
2
+1.8V_SUSP
+1.8V_MEM
PJP17
+0.9V_DDR_VTTP
2
1
+0.9V_DDR_VTT
PAD-OPEN 2x2m~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL")
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
CONTAINS CONFIDENTIAL
THIS DOCUMENT MAY NOT
OF DELL. IN ADDITION,
DISCLOSED TO ANY THIRD
Title
1.8VSUSP/0.9VDDR
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4041P
Sheet
1
46
of
63
7
6
5
4
3
2
PC84
100U_25V_M~D
PC83
100U_25V_M~D
PC82
100U_25V_M~D
1
2
1
2
1
2
GNDA_VCORE
6
1
2
PC97
10U_1206_25V6M~D
2
1
1
2
1
PC108
10U_1206_25V6M~D
2
1
4
2
3
PR125
10K_0402_1%~D
1
2
1
22.1K_0402_1%~D
2@ PR131
2
1
2
PR103
+VCC_CORE
2
1
1@ PC119
0.22U_0603_10V7K~D
2
1
1@ PR126
7.68K_0805_1%~D
2@ PC124
0.1U_0402_10V7K~D
C
PR120
10_0402_1%~D
B
2
G
1
2
PR119
G
S
2
4.7_0805_1%~D
EP
ISL6208CRZ-T_QFN8P_3X3~D
1@
PWR_MON <18>
1
PR108
4.7_0805_1%~D
PQ20
SI7686DP-T1-E3_SO8~D
2
4
LGATE
1@ PQ55
FDMS8670S_MLP-8~D
PC118
680P_0603_50V7K~D
2
2
1
GND
VO
PL13
0.36UH_FDUE1040DR36M_34.9A_20%~D
PHASE3
3
3
UGATE3
D
PWM PHASE
7
S
8
PC114
680P_0603_50V7K~D
2
1
1
5
FCCM UGATE
2
3
2
1
PR114
PC113
2.2_0603_1%~D 0.22U_0603_10V7K~D
1 2
1
1
2
PQ21
6
BOOT
FDMS8670S_MLP-8~D
VCC
9
VSUM
1@ PR127
0_0402_5%~D
VO
DELL CONFIDENTIAL/PROPRIETARY
A
Compal Electronics, Inc.
Maybach DIS
change PR123 to 10_ohm
change PC122 to PR320 10_ohm
http://hobi-elektronika.net
PC96
10U_1206_25V6M~D
PC94
2200P_0402_50V7K~D
2
1
1
PR90
4.7_0805_1%~D
PC93
0.1U_0603_25V7K~D
2
1
1
GNDA_VCORE
PU8
5
LGATE3
2
2
1
2@ PC126
1000P_0402_50V7K~D
1
2
2@ PC125
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
2
4
3
2@ PR117
17.8K_0402_1%~D
2
1
1
1
2
1@ PR111
2.43K_0402_1%~D
2
1
2
2
1@ PR123
1K_0402_1%~D
2
1
1@ PH3
2
1
1
2@ PR323
33K_0402_5%~D
1
2
1@ PR124
15K_0402_1%~D
VO
6.8KB_0603_5%_ERTJ1VR682J~D
1@ PC112
0.01U_0402_25V7K~D
1
2
2
1@ PC116
.047U_0402_16V7K~D
16
VO
DFB
15
14
GND
1
VSUM
1@ PR112
4.53K_0402_1%~D
2
1
1@ PC115
0.33U_0603_10V7K
VW
D
COMP
PC109
1U_0603_10V6K~D
7
OCSET
+5V_ALW
GNDA_VCORE
1@ PR107
20K_0402_1%~D
2
1
VSUM 17
1@
ISL6260CCRZ_QFN40~D
VSUM
1@
FB
1@ PR101
7.68K_0805_1%~D
+CPU_PWR_SRC
2@ PR106
226K_0402_1%~D
2
1
D
1
10
PR97
10_0402_1%~D
1@ PC103
0.22U_0603_10V7K~D
2
1
PR100
10K_0402_1%~D
1
2
2
G
+VCC_CORE
1
3
G
2
2
1
21
2
1
3
2
VDIFF
330P_0402_50V7K~D
1
7
PC81
10U_1206_25V6M~D
2
1
PC80
10U_1206_25V6M~D
PC79
2200P_0402_50V7K~D
2
1
2
PR75
4.7_0805_1%~D
3
1
ISEN3
LGATE2
4
2@ PR275
0_0402_5%~D
CSN2 2
1
RTN
11
1@ PC122
2
1
2
1
PR129
6.34K_0402_1%~D
8
D
2
25
EP
ISL6208CRZ-T_QFN8P_3X3~D
1@
PR95
PWM3
9
PL12
0.36UH_FDUE1040DR36M_34.9A_20%~D
PHASE2
PC110
2200P_0402_50V7K~D
2
1
13
2@ PC123
1@ PC121
2
1
VO
E
2@ PR276
0_0402_5%~D
CSN3 2
1
VSEN
CSN3
1@
PR121
162K_0402_1%~D
1000P_0402_50V7K~D
GNDA_VCORE
VSUM
PC107
0.1U_0603_25V7K~D
2
1
VR_ON
12
1@ PR122
12.1K_0402_1%~D
2
1
1
F
PR81
0_0402_5%~D
PC106
10U_1206_25V6M~D
2
1
35
GNDA_VCORE
1@ PC127
1@ PR130
0.01U_0402_16V7K~D
2K_0402_1%~D
2
1
0_0402_5%~D
2
2
S
1
4
LGATE
PC100
680P_0603_50V7K~D
2
1
GND
UGATE2
PC102
680P_0603_50V7K~D
2
2
1
3
PQ18
SI7686DP-T1-E3_SO8~D
PWM PHASE
7
1@ PQ54
FDMS8670S_MLP-8~D
1
8
3
BOOT
FCCM UGATE
2
D
VCC
6
S
5
PR91
PC99
2.2_0603_1%~D 0.22U_0603_10V7K~D
2
1
1
2
1
24
2
PC120
180P_0402_50V8J~D
1
2
1@ PR80
7.68K_0805_1%~D
2
CLK_EN#
1@ PC111
1@ PR116
0_0603_5%~D
1000P_0402_50V7K~D 2
1
1.18K_0402_1%~D
1
2
1@ PC117
680P_0402_50V7-K~D
22
FCCM
1
1
PR118
0_0402_5%~D
+VCC_CORE
1@ PC89
0.22U_0603_10V7K~D
2
1
PR78
10K_0402_1%~D
1
2
4.7_0805_1%~D
38
8
2
PR76
10_0402_1%~D
1
4
PU6
S
PMON
PR115
2
B
PQ17
5
PWM2
26
1
PSI#
2
PR110
2
1
0_0402_5%~D
2
FDMS8670S_MLP-8~D
40
23
ISEN2
1
41
1
G
3
2
1
DPRSLPVR
9
PC105 1000P_0402_50V7K~D
2
1
1@ PR113
2
1
232_0402_1%~D
2
PQ19
DPRSTP#
36
C
GNDA_VCORE
G
1
1
0_0402_5%~D
1
PC104 1000P_0402_50V7K~D
2
1
<8> VSSSENSE
2
1
2
CLK_ENABLE#
1
2@ PR109
2
1
4.99K_0402_1%
3
LGATE1
1
37
@ PR105 0_0402_5%~D
2@ PH2
10KB_0603_1%_ERTJ1VG103FA~D
1
1@ PQ53
FDMS8670S_MLP-8~D
PC91
680P_0603_50V7K~D
2
2
1
2
FDMS8670S_MLP-8~D
VID0
VID1
VID2
VID3
VID4
VID5
VID6
ISEN1
2
PR96
2
1
499_0402_1%~D
<37> IMVP_VR_ON
2
PR72
PC78
4.7_0805_1%~D
0.1U_0603_25V7K~D
2
1
1
3
2@ PR322
33K_0402_5%~D
2 PR87
1
0_0402_5%~D
2 PR89
1
0_0402_5%~D
2 PR93
1
0_0402_5%~D
2 PR94
1
0_0402_5%~D
2
1
0_0402_5%~D
1@ PR99
2
1
10K_0402_5%~D
@
2@ PR102 PAD~D T2
0_0402_5%~D
1@ PC101
1U_0603_10V6K~D
2
1
PR104
GNDA_VCORE
2
<8> VCCSENSE
2
1
<37,38,41,50> RUNPWROK
PC87
680P_0603_50V7K~D
2
1
4
D
28
29
30
31
32
33
34
1
SOFT
27
2
6
PWM1
CSN2
PR98
3
2
1
PQ16
SI7686DP-T1-E3_SO8~D
PHASE1
4
S
2
7
GND
PC95
1U_0603_10V6K~D
NTC
39
18
RBIAS
5
DROOP
2 PR86
1
0_0402_5%~D
2 PR88
1
0_0402_5%~D
2 PR92
1
0_0402_5%~D
<8> H_PSI#
2@ PR128
2
1
PWM PHASE
3
PU7
VID0
VID1
VID2
VID3
VID4
VID5
VID6
<10,24> DPRSLPVR
A
2
EP
H
PAD-OPEN 4x4m
PL11
0.36UH_FDUE1040DR36M_34.9A_20%~D
2
@ 100K_0603_5%_ERTJ1VV104J~D
<8,10,23> H_DPRSTP#
D
VIN
VDD
VR_TT#
3
3V3
19
20
4
GNDA_VCORE
<18> PWR_MON
8
1
PH11
2
FCCM UGATE
<24,37,41>
PGOOD
IMVP6_PROCHOT#
@
T1
6
ISL6208CRZ-T_QFN8P_3X3~D
1@
2
+
2
+5V_ALW
PAD~D
PC98
0.015u_0402_16V7K~D
2
1
1
9
2
+
+PWR_SRC
PJP18
1
1
G
BOOT
LGATE
+
1
Iccmax=44A
I_TDC=35A
OCP=65A, Intel spec=50A
VCC
UGATE1
1
+CPU_PWR_SRC
2
2
GNDA_VCORE
@ PC92
2200P_0402_50V7K~D
2
1
<8>
<8>
<8>
<8>
<8>
<8>
<8>
2@ PR321
33K_0402_5%~D
1
1
0.01U_0402_25V7K~D
1@ PC88
2
1
IMVP_PWRGD
VSS
@ PR84
0_0402_5%~D
2
1
PL10
FBMJ4516HS720NT_1806~D
1
2
5
PR79
1.91K_0603_1%~D
2@ PR85
13K_0402_1%
PR82
147K_0402_1%~D
2
1
1
430 ohm
0 ohm
1uF
0.45uH
+3.3V_RUN
GNDA_VCORE
PR74
PC86
2.2_0603_1%~D 0.22U_0603_10V7K~D
2
1
1
2
PU5
+5V_ALW
4
D
PR73 1@
10_0603_5%~D
10K ohm
10 ohm
0.22uF
0.36uH
F
E
PC85
1U_0603_10V6K~D
2
1
2
+5V_ALW
PR83
0_0603_5%~D
1
Maybach DIS
PC98
470pF
PR115
6.04K ohm
PR118
71.5K ohm
PC120
0.47uF
PR129
825 ohm
PR78,PR100,PR125
PR76,PR97,PR120
PC89,PC103,PC119
PL11,PL12,PL13
+CPU_PWR_SRC
PC90
PR77
1U_0603_10V6K~D 10_0603_5%~D
2
1
1
2
G
AVIA
PC98
0.15uF
PR115
0 ohm
PR118
0 ohm
PC120
180pF
PR129
6.34K ohm
PR78,PR100,PR125
PR76,PR97,PR120
PC89,PC103,PC119
PL11,PL12,PL13
5
PU7
AVIA ISL6260C
Maybach DIS MAX8786
PC77
0.1U_0603_25V7K~D
2
1
+CPU_PWR_SRC
1
H
1
0_0402_5%~D
8
PU5 PU6 PU8
AVIA ISL6208
Maybach DIS MAX8791
5
Title
+VCORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4041P
2
47
Sheet
1
of
63
5
4
3
NC
16
12
GND
29
TP
PC130
0.1U_0603_25V7K~D
2
1
1
PR339
100K_0402_5%~D
1
1 PR157
2
+VCHGR
0_0402_5%~D
4
G
3
2
1
BQ24745RHDR_QFN28_5X5~D
@
PJP20
1
2
2
3
PC160
PC161
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
1
2
1
2
1
VFB
15
@
PR156 @
1.8K_1206_5%~D
17
2
CSON
@
1
CE
D
S
PQ30
RHU002N06_SOT323
19
18
PC159
2200P_0402_50V7K~D
2
1
PGND
CSOP
+VCHGR
PR153
0.01_1206_1%~D
4
PC158
10U_1206_25V6M~D
2
1
VREF
7
D
D
D
D
3
S
S
S
PC154
0.1U_0402_10V7K~D
2
1
PR154
1
2
10K_0402_5%~D
PL14
5.6U_HMU1356-5R6_8.8A_20%~D
2
1+VCHGR_L 1
+VCHGR_B
PC157
10U_1206_25V6M~D
2
1
2
ISL88731_VREF
PC153
1U_0603_10V6K~D
2
1
@
@ PC144
220P_0402_50V7K~D
CHG_LGATE
PC141
10U_1206_25V6M~D
2
1
20
PC156
10U_1206_25V6M~D
2
1
LGATE
PC140
10U_1206_25V6M~D
2
1
EAO
PC155
0.1U_0603_25V7K~D
2
1
4
PC139
0.1U_0603_25V7K~D
2
1
PHASE
PC142
2200P_0402_50V7K~D
2
1
EAI
PR158
0_0402_5%~D
1
FBO
5
4
3
B
1
1
2
PC145
PR151
2200P_0402_50V7K~D 7.5K_0402_5%~D
PC148
120P_0402_50VNPO~D
1
2
@ PC150
0.01U_0402_25V7K~D
2
1
@
PC149
220P_0402_50V8J~D
2
1
PR155
16.2K_0402_1%~D
2
1
<18> ISL88731_ICM
2
@ PC152
PC147
0.01U_0402_25V7K~D56P_0402_50VNPO~D
2
1
1
2
<6,27,38> CKG_SMBDAT
PR150
200K_0402_5%~D
PC151
0.01U_0402_25V7K~D
2
1
PR152
4.7K_0402_5%~D
2
1
GNDA_CHG
<6,27,38> CKG_SMBCLK
2
4
CHG_UGATE
PR149
1
0_0603_5%~D
2
C
2
24
23
PC138
1U_0603_10V6K~D
1
2
PQ28
SI4800BDY-T1_SO8~D
UGATE
VICM
6
21 ISL88731_VDDP
@ PR148
33_0603_1%~D
PR216
4.7_1206_5%~D
VDDP
NC
PR144
2.2_0603_1%~D
2
1
1
25
2
1
2
2
28
27
BOOT
5
6
7
8
SDA
26
3
2
1
9
ICOUT
PC204
1000P_0603_50V7K~D
2
2
1
SCL
<35>
SW_GND <50>
PQ27
SI4800BDY-T1_SO8~D
VDDSMB
10
DOCK_DCIN_IS-
PQ29
SI4812BDY-T1-E3_SO8~D
ACOK
11
6
5
6
7
8
13
8
CSSP
ACIN
5
PR338
100K_0402_5%~D
2
1
@ PC134
1U_0603_10V6K~D
1
2
GNDA_CHG
Throttle_ICOUT
CSSN
1
DCIN
2
14
ISL88731_ICM
1
PU9
22
<35>
PC146
3300PF_0402_50V7K~D
2
1
5
3
6
2
7
1
8
1
2
0_0402_5%~D
PR340
100K_0402_5%~D
1
2
1
2
PC133
0.1U_0603_25V7K~D
1
2
PR140
0_0402_5%~D
1
Throttle_ICREF
GNDA_CHG
PC128
2200P_0402_50V7K~D
2
1
PQ23
NTR4502PT1G_SOT23-3~D
1
3
1
PQ25
NTR4502PT1G_SOT23-3~D
PQ26
RHU002N06_SOT323
1
3
PC132
0.1U_0603_25V7K~D
1
2
GNDA_CHG
PC143
0.1U_0402_10V7K~D
3
2
1
PC129
TBD_0603_25V7K~D
PR133
33K_0402_5%~D
2
1
PR137
10K_0402_5%~D
2
1
1
2
2
DOCK_DCIN_IS+
D
PQ70A
NTGD4161PT1G_TSOP6~D
PD14
RB751V_SOD323~D
2
1
+3.3V_ALW
4
PC137
0.1U_0603_25V7K~D
2
1
0.01U_0402_25V7K~D
PQ70B
NTGD4161PT1G_TSOP6~D
1
@ PR147
15.8K_0402_1%~D
2
1
<18,38> ACAV_IN
3
2
@ PR138
10K_0402_5%~D
ICREF
2
PC131
0.047uF_0603_25V7K~D
1
2
1
1
PR143
10K_0402_5%~D
2
1
@ PR142
10K_0402_1%~D
2
1
S
2
G
PR146
1
GNDA_CHG
PQ66
RHU002N06_SOT323
3
2
1
PC136
2
D
PC135
1U_0805_25V6K~D
2
1
PR145
49.9K_0402_1%~D
1
2
2
2
1
2
2
D
309K_0402_1%
C
ISL88731_VREF
3
G
ISL88731_VDDP
PR141
3
4
2
S
+SDC_IN
1
1
G
S
2
G
@
CHAGER_SRC
PL16
FBMJ4516HS720NT_1806~D
1
2
D
<50> ACAV_DOCK_SRC
+PWR_SRC
PR132
0.01_1206_1%~D
S
PR307
200K_0402_1%~D
2
1
S
D
3
S
PQ44
RHU002N06_SOT323
PR139
33K_0402_5%~D
1
PQ24
RHU002N06_SOT323
D
2
G
PR135
24k_0402_1%~D
2
1
D
2
G
3
1
NB_AC_OFF#
+DC_IN
PR136
160K_0402_1%~D
4
PR134
10K_0402_5%~D
2
1
NB_AC_OFF <37,43,50>
1
1
+SDC_IN
PQ22
SI4835BDY-T1-E3_SO8~D
8
1
7
2
6
3
5
D
2
PD30 RB081L-20_SOD106~D
1
2
+DC_IN_SS
3
2
G
GNDA_CHG
PAD-OPEN1x1m
@
GNDA_CHG
PD35
GNDA_CHG
NB_AC_OFF# 2
1
2
1 Throttle_ICOUT
@ PR219
200K_0402_1%~D
PR160
100K_0402_5%~D
1
2
1
@
TI
@
Maxim
@
@
@
@
@
@
@
ADAPT_OC <37>
D
S
PQ31
RHU002N06_SOT323
PC144 PR157 PC160 PC161
1K_0402_5%~D
2
G
3
G
PR163
100K_0402_1%~D
2
1
4
1
GNDA_CHG
PC145 PR151 PR154 PC154 PC132 PC133 PR138 PC134 PR148
@
TI
0
100
Maxim
@
@
A
DELL CONFIDENTIAL/PROPRIETARY
GNDA_CHG
Compal Electronics, Inc.
Title
Maybach DIS
PR162=51.1K, PR165=16.9K, PR167=499.
AVIA
http://hobi-elektronika.net
PR162=32.4K, PR165=19.1K, PR167=523.
5
+5V_ALW
GNDA_CHG GNDA_CHG
GNDA_CHG
RB751S40T1_SOD523-2~D
+3.3V_ALW
@ PR166
2
1
ACAV_IN_NB <37,38>
PU10B
LM393DR_SO8~D
IN+
PC163
10P_0402_50V8J~D
2
1
PR335
1
2
0_0402_5%~D
3
GNDA_CHG
PU10A
LM393DR_SO8~D
O 1
PC168
0.01U_0402_25V7K~D
2
1
7
IN-
PC167
100P_0402_50V8J
2
1
O
IN-
4
PR332
42.2K_0402_1%~D
2
1
6
IN+
2
P
T43
PR159
1M_0402_1%~D
1
2
8
PAD~D@
8
2
+5V_ALW
@ PR164
26.7K_0402_1%
1
2
Maximum charging current is 6.24A
PC166
100P_0402_50V8J
2
1
1
PR334
1M_0402_5%~D
2
PR161
1
2
8.45K_0402_5%~D
ACAV_IN
+5V_ALW
PR220
0_0402_5%~D
2
1
@ PR218
200K_0402_1%~D
@
ISL88731_ICM
PR341
100K_0402_5%~D
PR333
47K_0402_1%~D
2
1
1
5
PC255
100P_0402_50V8J
2
1
PR331
232K_0402_1%~D
2
1
PR336
21.5K_0402_1%~D
2
1
PC256
100P_0402_50V8J~D
2
1
@
+3.3V_ALW
+DC_IN ISL88731_VREF
A
@
@
PR162
32.4K_0402_1%~D
2
1
10K
@
PR167
PR165
523_0402_1%~D 19.1K_0402_1%~D
2
1
2
1
PC164
0.01U_0402_25V7K~D
2
1
0.1u
@
PC162
0.1U_0402_10V7K~D
2
1
4.7K
P
365K
220p
G
Maxim
@
GNDA_CHG
2
Throttle_ICREF
PR155 PC149 PR152 PC150 PR150 PC148 PC151 PC147 PC152
ISL88731_VREF
309K
TI
PC165
100P_0402_50V8J
2
1
PR141
GNDA_CHG
GNDA_CHG
4
GNDA_CHG
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Charger
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
0.2
LA-4041P
Sheet
1
48
of
54
5
4
3
2
1
PD16
2 PDS1040S-13_POWERDI5-3
1
3
PQ34
FDS6679AZ_SO8~D
1
PQ36
RHU002N06_SOT323
1
PQ35A
D
IMD2AT-108_SC74-6~D
2
G
2
1
PR274
22K_0402_5%~D
2
1
3
PR273
22K_0402_5%~D
SW_GND <48>
PQ67
RHU002N06_SOT323
3
1
ACAV_DOCK_SRC <48>
EN_DOCK_PWR_BAR
<37>
3
S
+5V_ALW
S
D
EN_DOCK_PWR_BAR#
5
6
1
2
PR200
47K_0402_1%~D
1
PR198
22K_0402_5%~D
1
2
4
2
PR197
240K_0402_5%~D
3
2
2
2
1
2
PR201
22K_0402_5%~D
NB_AC_OFF_BJT <43>
D
PQ52
RHU002N06_SOT323
2
PQ71B G
3
S
2N7002DW-T/R7_SOT363-6~D
C
PQ71A
2
5
1
2N7002DW-T/R7_SOT363-6~D
4
S
2
G
C
S
S
6
1
D
3
2
1
+3.3V_ALW2
D
2
G
D
PQ50
RHU002N06_SOT323
PQ51
RHU002N06_SOT323
3
RHU002N06_SOT323
2
G
<35,38> ACAV_DOCK_SRC#
PQ35B
IMD2AT-108_SC74-6~D
NB_AC_OFF <37,43,48>
D
2
G
3
1
2
1
2
1
PQ37
PR300
100K_0402_5%~D
1
2
PR299
100K_0402_5%~D
+3.3V_ALW2
PR271
100K_0402_5%~D
1
PR199
100K_0402_5%~D
1
D
PR354
330K_0402_5%~D
1
2
3
4
PR272
100K_0402_5%~D
+3.3V_ALW
8
7
6
5
1
1
+3.3V_ALW
PC192
0.47U_0805_25V7K~D
2
1
+DOCK_PWR_BAR
PD31
PDS5100H-13_POWERDI5-3
2
PR361
330K_0402_5%~D
1
5
PR326
240K_0402_5%~D
1
2
6
PC194
0.1U_0603_25V7K~D
2
1
PC193
2200P_0402_50V7K~D
2
1
PD20
2
B
1
RB751V-40_SOD323~D
1
3
1
PQ75B
2N7002DW-T/R7_SOT363-6~D
PR203
33K_0402_5%~D
1
2
1
2
PQ75A
2N7002DW-T/R7_SOT363-6~D
PR328
47K_0402_5%~D
2
1
2
PQ72A
NTGD4161PT1G_TSOP6~D
+DOCK_PWR_BAR
D
PQ43
RHU002N06_SOT323
3
1
1
4
5
2
G
D
PQ77
S
3
S
RHU002N06_SOT323
PD33
RB751S40T1_SOD523-2~D
2
1
+PWR_SRC
RB715F_SC70-3~D
2
<35,37,43> SLICE_BAT_PRES#
1
3
PC262
PR363
1U_0603_25V6-K~D 1K_1206_5%
3
2
PD34
RB751S40T1_SOD523-2~D
4
PD18
1
2
3
2
+DC_IN_SS
4
PR327
47K_0402_5%~D
1
2
PR356
0_0402_5%~D
2
6 1
1
+3.3V_ALW2
+NBDOCK_DC_IN_SS
PQ72B
NTGD4161PT1G_TSOP6~D
1
PR325
240K_0402_5%~D
1
2
2
2
2
PC263
1U_0603_25V6-K~D
1
1
3
2 4
+DC_IN_SS
1
2N7002DW-T/R7_SOT363-6~D
PQ40A
2N7002DW-T/R7_SOT363-6~D
1
PQ40B
1
2N7002DW-7-F_SOT363-6~D
PD19
RB751V-40_SOD323~D
4
PR202
620K_0402_5%~D
2
6
1
PR223
390K_0402_5%~D
PR222
390K_0402_5%~D
2
2
1
1
2
PR352
47K_0402_1%~D
1
2
6
PR353
100K_0402_5%~D
3
4
5
PBATT_PSRC
D
2N7002DW-7-F_SOT363-6~D
PQ76B
<37> PBATT_OFF
PQ39
FDS6679AZ_SO8~D
8
7
6
5
G
5
<37> PBATT_OFF
2
2
S
PQ76A
PR204
33_0402_5%~D
2
1
1
3
D
2
1
8
7
6
5
G
+3.3V_ALW
B
1
2
3
S
1
2
4
+VCHGR
PBATT+
1
2
3
PR351
240K_0402_5%~D
8
7
6
5
FDS6679AZ_SO8~D
PQ38
PR329
100K_0402_5%~D
SI4835BDY-T1-E3_SO8~D
PQ41
PR355
2 2
1 EN_DOCK_PWR_BAR#
G
0_0402_5%~D
DOCK_AC_OFF <35>
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Selector
Size
Document Number
Date:
Friday, June 06, 2008
Rev
1.0
LA-4041P
Sheet
1
49
of
63
5
4
3
2
1
2
PC216
1U_0603_6.3V6M~D
PR277
2
+5V_ALW
1
1
10_0603_5%
PC217
2.2U_0603_10V6K~D
2
1
PR279
2 200K_0402_1%~D
1
15
PR168
PC221
2.2_0603_1%~D
1
2 2
1
DH1
13
0.22U_0603_10V7K~D
UG_VGA1
LX1
14
PHASE_VGA1
DL1
17
LG_VGA1
1
REF
BST2
21
DH2
23
LX2
22
DL2
19
CSH2
26
CSL2
27
DIS_FB2
0
0
1
1
0
PC220
PC172
0.1U_0603_25V7K~D
2
1
PC218
PC173
0.1U_0603_25V7K~D
2
1
1
1@
1@
2
1
1
3
1@ PR291
3.01K_0402_1%
2
4
1@ PR301
4.7_0805_1%
1@ PQ65
FDMS8670S_MLP8~D
PC241
680P_0402_50V7K~D
1
2
2
1
5
LG_VGA2
3
2
1
1@ PQ64
FDMS8670S_MLP8~D
5
4
4
1
2
1@ PR292
6.04K_0402_1%~D
1
2
1@ PR293
0_0402_5%
1@ PR308
0_0402_5%
2
1
B
1
2
PR295
10_0402_1%~D
+5V_ALW
1
1@
PJP36
1
GNDA_GPU
12
11
N.C.
N.C.
13
N.C.
14
15
N.C.
N.C.
VOUTL6935TR_VFQFPN20_4X4~D VIN
8
ADJ
7
PR304
2
1
0_0402_5%
2
1
18
<37,38,41,47>
+GPU_CORE
1
2
2
1
2
2
@ JUMP_43X79
6
2
1
2
PR298
10K_0402_1%~D
PJP40
PC238
10U_0805_6.3V6M~D
1
1
A
2
2
@ JUMP_43X79
PJP41
1.1V_GFX_PWRGD
<41>
+1.1V_GFX_PCIEP
1
1
2
2
@ JUMP_43X79
+1.1V_GFX_PCIE
Title
http://hobi-elektronika.net
5
2
PJP39
+3.3V_ALW
VBIAS
2
@ JUMP_43X79
PC237
10U_0805_6.3V6M~D
1
PGOOD
N.C.
RUNPWROK
1
5
4
SS
N.C.
20
GND
1
EN
3
19
2
GLM3
PR288 change to 7.15K
PR290 change to 10K
PR289 change to 13.7K
9
N.C.
12K_0402_1%~D
0
10
VIN
PAD
1
1
GPU_VID_0
VIN
VOUT
2
2
VOUT
1
PJP38
1
17
1
1
GLM3
A
2
@ JUMP_43X79
+GPU_COREP
16
21
PR317
1.16V
default
PC239
0.1U_0805_25VX7R~D
2
AVIA
0.89V
PR297
10K_0402_1%~D
1
+1.1V_GFX_PCIEP
0
PC236
10U_0805_6.3V6M~D
PU14
PC235
10U_0805_6.3V6M~D
2
2
1
1
2
PJP37
1.05V
default
GLM2
GPU_VID_0
1
@ JUMP_43X79
1
0.89V
2
1@
+1.5V_RUN
AVIA
C
+
3
2
1
S
S
S
2
2 1
2
+GPU_COREP
1
VGA_B+
PAD-OPEN1x1m
GPU_VID_1
+
1@ PL20
0.56UH_MPC1040LR56_23A_+-20%~D
3
2
1
DIS_FB2
PJP21
2
1
1
2@ PR309
0_0402_5%
2
1
GND_T
29
2
GNDA_GPU
1.09V 1.17V
default
1@ PC234
1000P_0402_50V7K~D
LG_VGA2
MAX17007ETI+_TQFN28_4X4~D
2@ PR314
0_0402_5%
2
1
1
1@
+
G
GNDA_GPU
GNDA_GPU
GPU_VID_0
28
FB2
<41,54> GFX_CORE_PWRGD
0.9V
5
6
7
8
D
D
D
D
1
2
1@ PC233
0.22U_0402_6.3V6K
GNDA_GPU
+3.3V_ALW
PR294
100K_0402_5%~D
Maybach
4
PHASE_VGA2
2
GNDA_GPU
PGOOD2
2
2
1
PR313
10K_0402_1%~D
PGOOD1
24
2@
GNDA_GPU
12
1
S
1@ PQ62
FDS6298_SO8~D
1@
UG_VGA2
1
1
D
2
G
<51> GPU_VID_1
B
REFIN1
2
GNDA_GPU
1
2
1
PR312
10K_0402_1%~D
GNDA_GPU
8
PR290
11K_0402_1%~D
2@ PR306
340K_0402_1%~D
3
3
S
RHU002N06_SOT323
2@ PQ68
1
D
2
G
<51> GPU_VID_0
RHU002N06_SOT323
PQ63
2
1
@ PR311
10K_0402_1%~D
2
1
PR310
10K_0402_1%~D
@
PR287
1
2
GNDA_GPU
10_0402_1%~D
1
PR169 2.2_0603_1%~D
2 2
1@ PC229
0.22U_0603_10V7K~D
PR288
10K_0402_1%~D
PR289
31.6K_0402_1%~D
2
1
1
1
PC240
470U_X_2VY_R9M~D
9
2
PR286
0_0402_5%
PC227
470U_X_2VY_R9M~D
CSL1
1
PC226
470U_X_2VY_R9M~D
EN2
1.15V / 1.2V
thermal design current 25A
peak current 30A
PC232
PC228
0.22U_0402_6.3V6K
2
1
GNDA_GPU
+3.3V_ALW
25
2
PC231
GNDA_GPU
PC225
1000P_0402_50V7K~D
1
21
2
GNDA_GPU
1
PR285
6.04K_0402_1%~D
10U_1206_25VAK
1
2
10
PC230
20
CSH1
2
PR283
3.01K_0402_1%
1
PGND
4
3
2
1
EN1
LG_VGA1
3
2
1
11
1
Maybach DIS
PR288 41.2K
PR289 107K
PR290 57.6K
PC224
0.22U_0402_6.3V6K
4
1
3
10U_1206_25VAK
1
2
PR284 @
0_0402_5%
<37> GFX_CORE_ON
4
2
2
SKIP
10U_1206_25VAK
1
2
5
PC174
0.1U_0603_25V7K~D
2
1
470p_0402_50V
PL19
0.56UH_MPC1040LR56_23A_+-20%~D
PR282
4.7_0805_1%
ILIM2
G
PC175
0.1U_0603_25V7K~D
2
1
3
1
4
PC223
680P_0402_50V7K~D
2
2
1
BST1
PQ59
FDS6298_SO8~D
PQ61
FDMS8670S_MLP8~D
ILIM1
PC219
10U_1206_25VAK
1
2
7
10U_1206_25VAK
1
2
TON2
5
@ PR296
200K_0402_1%~D
2
1
18
PR278
2 200K_0402_1%~D
1
S
S
S
@ PR280
0_0402_5%
1
6
3
2
1
2
2
PR281
0_0402_5%
VDD
GNDA_GPU
+GPU_COREP 2
TON1
GND
5
16
1@ PC222
2
C
1
4
2
PR303
0_0402_5%
+5V_ALW
AVIA
PR288 10K
PR289 31.6K
PR290 11K
VCC
1
PQ60
FDMS8670S_MLP8~D
G
2
@ PR302
0_0402_5%
D
PL18
FBMA-L18-453215-900LMA90T_1812~D
2
1
+PWR_SRC
VGA_B+
5
6
7
8
D
1
D
D
D
D
3
1
RHU002N06_SOT323
@PQ73
S
2
PU13
10U_1206_25VAK
1
2
GNDA_GPU
D
Size
C
Date:
4
3
2
Document Number
<Doc>
Rev
1.0
Sheet
Friday, June 13, 2008
1
50
of
63
5
4
U56A
2
C729
1 C728 PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
PEG_MRX_GTX_P7
0.1U_0402_10V7K~D
PEG_MRX_GTX_N7 0.1U_0402_10V7K~D
2
1
2
C731
1 C730 PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
PEG_MRX_GTX_P8
0.1U_0402_10V7K~D
PEG_MRX_GTX_N8 0.1U_0402_10V7K~D
2
1
2
C734
1 C733 PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
PEG_MRX_GTX_P9
0.1U_0402_10V7K~D
PEG_MRX_GTX_N9 0.1U_0402_10V7K~D
2
1
2
C736
1 C735 PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
PEG_MRX_GTX_P10
0.1U_0402_10V7K~D
PEG_MRX_GTX_N10 0.1U_0402_10V7K~D
2
1
2
C739
1 C738 PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEG_MRX_GTX_P11
0.1U_0402_10V7K~D
PEG_MRX_GTX_N11 0.1U_0402_10V7K~D
2
1
2
C741
1 C740 PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
PEG_MRX_GTX_P12
0.1U_0402_10V7K~D
PEG_MRX_GTX_N12 0.1U_0402_10V7K~D
2
1
2
C743
1 C742 PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_P13
0.1U_0402_10V7K~D
PEG_MRX_GTX_N13 0.1U_0402_10V7K~D
2
1
2
C746
1 C745 PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_P14
0.1U_0402_10V7K~D
PEG_MRX_GTX_N14 0.1U_0402_10V7K~D
2
1
2
C749
1 C747 PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
1 C752 PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15
2
C754
<6> CLK_PCIE_VGA
<6> CLK_PCIE_VGA#
R681 1
R856 1
<10,22,32> PLTRST1#
1
2
R682 @ 10K_0402_5%~D
2
2
AL17
AM17
AM18
AM19
AL19
AK19
AL20
AM20
AM21
AM22
AL22
AK22
AL23
AM23
AM24
AM25
AL25
AK25
AL26
AM26
AM27
AM28
AL28
AK28
AK29
AL29
AM29
AM30
AM31
AM32
AN32
AP32
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
CLK_PCIE_VGA
CLK_PCIE_VGA#
AR16
AR17
AR13
AM16
AG21
AG19
AG20
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
PEX_RST_N
PEX_TERMP
PEX_RFU1
PEX_RFU2
0_0402_5%~D
PEX_TERMP
2.49K_0402_1%~D
10K_0402_5%~D
1
2
R957
B
<6> CLK_NVSS_27M
1
R686
2
0_0402_5%~D
1
2
R958 @ 10K_0402_5%~D
AM13
AL13
AM15
AL14
AM14
AK13
AK12
DACB_RED
DACB_BLUE
DACB_GREEN
DACB_RSET
DACB_CSYNC
DACB_VREF
AA4
Y4
AB4
AB6
AB5
AC5
DACC_HSYNC
DACC_VSYNC
DACC_RED
DACC_BLUE
DACC_GREEN
DACC_RSET
DACC_VREF
AM1
AM2
AK4
AJ4
AL4
AH7
AK6
D1
XTAL_OUTBUFF
D2
XTAL_SSIN
2
PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_RSET
DACA_VREF
T119PAD~D
10K_0402_5%~D
1
2
R952
+3.3V_RUN
CRT_HSYNC_GPU
CRT_VSYNC_GPU
CRT_RED_GPU
CRT_BLU_GPU
CRT_GRN_GPU
DACA_RSET
1
DACA_VREF
R677
CRT_HSYNC_GPU <20>
CRT_VSYNC_GPU <20>
CRT_RED_GPU <20>
CRT_BLU_GPU <20>
CRT_GRN_GPU <20>
2
124_0402_1%~D 1
2
C732
0.1U_0402_10V7K~D
1
2
R691
150_0402_1%~D
1
2
R692
150_0402_1%~D
1
2
R693
150_0402_1%~D
CRT_RED_GPU
CRT_GRN_GPU
CRT_BLU_GPU
GPU_GPIO16
DPB_CA_DET
1
2
0_0402_5%~D
R1011
GPU_GPIO18 1
2
0_0402_5%~D
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE
AP14
AN14
AN16
AR14
AP16
AP35
JTAG_TCK_GPU
T83 PAD~D
JTAG_TDI_GPU
T84 PAD~D
JTAG_TDO_GPU
T85 PAD~D
JTAG_TMS_GPU
T86 PAD~D
JTAG_RST#GPU
T87 PAD~D
2
1
R680
10K_0402_5%~D
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
AJ17
AJ18
CLK
XTAL_IN
B1
XTAL_OUT
B2
1
R696
2
@ R672
1
1
1
1
1
DPB_GPU_P14
DPC_CA_DET
<21,35>
<---CRT
DVI_C_CLK_DDC <21>
DVI_C_DAT_DDC <21>
LDDC_CLK_GPU <19>
LDDC_DATA_GPU <19>
DVI_B_CLK_DDC <21>
DVI_B_DAT_DDC <21>
<---DVI C
<---LVDS
R1021
<---DVI B
2
+3.3V_RUN
100K_0402_5%~D
I2CE_SDA R1013 1
2 2.2K_0402_5%~D
@
2 2.2K_0402_5%~D
I2CS_SCL R1024 1
2 2.2K_0402_5%~D
I2CS_SDA R708 1
2 2.2K_0402_5%~D
CLK_NV_27M <6>
@
@
STRAP0
STRAP1
STRAP2
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU
+3.3V_RUN
1
GPU_DAT_DDC
GPU_DAT_DDC
CLOSE TO GPU
2
R919
1
R926
HDCP_WP
MIOA_CTL3
MIOA_DE
MIOA_HSYNC
MIOA_VSYNC
N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14
N5
MIOA_VREF
AE1
V4
W4
R928
2K_0402_1%~D
1
2
5@ R927
45.3K_0402_1%~D
1
2
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT_N
MIOB_CTL3
MIOB_DE
MIOB_HSYNC
MIOB_VSYNC
Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6
W5
W7
V7
MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8
MIOB_D9
MIOB_D10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14
MIOB_D15/(STRAP0)
MIOB_D16/(STRAP1)
MIOB_D17/(STRAP2)
AF1
MIOB_VREF
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
AP4
AN4
AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4
IFPCD_RSET
AK7
IFPE_AUX
IFPE_AUX_N
IFPE_DPL0_TXD2
IFPE_DPL0_TXD2_N
IFPE_DPL1_TXD1
IFPE_DPL1_TXD1_N
IFPE_DPL2_TXD0
IFPE_DPL2_TXD0_N
IFPE_DPL3_TXC
IFPE_DPL3_TXC_N
AE4
AD4
AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5
IFPF_AUX
IFPF_AUX_N
AF3
AF2
IFPF_DPL0_TXD2
IFPF_DPL0_TXD2_N
IFPF_DPL1_TXD1
IFPF_DPL1_TXD1_N
IFPF_DPL2_TXD0
IFPF_DPL2_TXD0_N
IFPF_DPL3_TXC
IFPF_DPL3_TXC_N
AL2
AL3
AJ3
AJ2
AJ1
AH1
AH2
AH3
D4
D3
C4
C3
SPDIF
A5
BUFRST_N
A4
PGOOD_OUT
C5
STRAP_REF_MIOB
STRAP_REF_3V3
M9
N9
THERMDN
THERMDP
B4
B5
RFU_0
RFU_1
RFU_2
RFU_3
RFU_4
RFU_5
RFU_6
RFU_7
RFU_8
RFU_9
RFU_10
RFU_11
RFU_12
RFU_13
RFU_14
RFU_15
RFU_16
RFU_17
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC
1
2.2K_0402_5%~D
2
10K_0402_5%~D
+3.3V_RUN
C1005
1
2
Part Number
Description
<27> SPDIF_OUT
SA00002B81L
S IC NB9M-NS-B-U2(H) BGA 969P
2
1K_0402_1%~D
DPC_DOCK_AUX <21>
DPC_DOCK_AUX# <21>
DPC_LANE_P0
DPC_LANE_N0
DPC_LANE_P1
DPC_LANE_N1
DPC_LANE_P2
DPC_LANE_N2
DPC_LANE_P3
DPC_LANE_N3
C
1
2
R721
1K_0402_1%~D
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU
SPDIF_OUT_GPU
R1022 1
R1023 1
AD29
AE29
AG29
AH29
G11
G12
G14
G15
G24
G25
G27
G28
J25
J26
L29
M29
P29
R29
E35
E7
F7
H32
M7
P6
P7
R7
U7
V6
2 40.2K_0402_1%~D
2 40.2K_0402_1%~D
VGA_THERMDN <18>
1
2
@ C744
100P_0402_50V8K~D
VGA_THERMDP <18>
all GDDR3
B
ROM_SI_GPU
R927
Q:16x32
10K_1%
H:16x32
15K_1%
S:16x32
20K_1%
Q:32x32
30K_1%
H:32x32
35K_1%
S:32x32
45.3K_1%
A0
A1
A2
GND
SPDIF_OUT_GPU
R939
R1025
depop
R923 R936
15K depop
20K
depop
4
NB9P-GLM2
15K
A
NB9M-NS
NB9P-GLM3(45W)
Compal Electronics, Inc.
1
2
R893
0_0402_5%~D
1
2
R894
0_0402_5%~D
190-00001-0001-T03 AT88SC0808C_SO8~D
VCC
WP
SCL
SDA
2
R922
24.9K
Avia
Maybach
depop
DSC
Avia(45W) 15K
C1032
1
2
0.01U_0402_16V7K~D
@
4.99K_0402_1%~D
U65
8
7
6
5
1
@ D63
DA204U_SOT323-3~D
1
2
3
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
NVG98 PCIE,GPIO,CLK,LVDS
Size
3
2
Document Number
Rev
1.0
LA-4051P
Date:
http://hobi-elektronika.net
AL1
ROM_SCLK
ROM_SI
ROM_SO
ROM_CS_N
1
R720
+3.3V_RUN
2@ U561 GPU NB9M-NS-BH
0.1U_0402_10V7K~D
5
IFPEF_RSET
D
NB9P-GLM2_BGA969~D
Stuff R929 for
standard I2C ROM.
Stuff R932 for
crypto ROM
@
HDCP_WP
HDCP_CLK
HDCP_DAT
@
<20>
+3.3V_RUN
HDCP_DAT
A
MIOA_CLKIN
MIOA_CLKOUT
MIOA_CLKOUT_N
P5
N2
N3
L3
A2
AB7
AD6
AF6
AG6
AJ5
AK15
AL7
D35
2
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
@
1
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
@
2@ R936
15K_0402_1%
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
@ R932
10K_0402_5%~D
<20>
3
1
1
1
1
1
1
1
1
GPU_CLK_DDC
R935
4.99K_0402_1%~D
1
2
2
2
2
2
2
2
2
2
GPU_CLK_DDC
1
C759
C760
C761
C762
C763
C764
C765
C766
<21>
<21>
<21>
<21>
<21>
<21>
<21>
<21>
2
DPC_LANE_P0
DPC_LANE_N0
DPC_LANE_P1
DPC_LANE_N1
DPC_LANE_P2
DPC_LANE_N2
DPC_LANE_P3
DPC_LANE_N3
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
R934
10K_0402_1%~D
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
R933
4.99K_0402_1%~D
1
2
1
1
1
1
1
1
1
1
HDA_BCLK
HDA_SYNC
HDA_SDI
HDA_SDO
HDA_RST_N
IFPD_AUX
IFPD_AUX_N
IFPD_DPL0_TXD2
IFPD_DPL0_TXD2_N
IFPD_DPL1_TXD1
IFPD_DPL1_TXD1_N
IFPD_DPL2_TXD0
IFPD_DPL2_TXD0_N
IFPD_DPL3_TXC
IFPD_DPL3_TXC_N
DPB_AUX <21>
DPB_AUX# <21>
DPB_LANE_P0
DPB_LANE_N0
DPB_LANE_P1
DPB_LANE_N1
DPB_LANE_P2
DPB_LANE_N2
DPB_LANE_P3
DPB_LANE_N3
2
2
2
2
2
2
2
2
2
2
C748
C750
C751
C753
C755
C756
C757
C758
R938
4.99K_0402_1%~D
DPB_LANE_P0
DPB_LANE_N0
DPB_LANE_P1
DPB_LANE_N1
DPB_LANE_P2
DPB_LANE_N2
DPB_LANE_P3
DPB_LANE_N3
2
1
2
1
1
R929
2.2K_0402_5%~D
IFPAB_RSET
N4
R4
T4
W3
Y5
W1
W2
+3.3V_RUN
2
200_0402_1%~D
HDCP_CLK
1
@
I2CE_SCL R709 1
NB9P-GLM2_BGA969~D
R695
2.2K_0402_5%~D
1
AJ11
1K_0402_5%~D
0_0402_5%~D
D7
0_0402_5%~D
A7
33_0402_5%~D
C7
0_0402_5%~D
B7
0_0402_5%~D
D6
R855
1
2
DPB_MB_P14 <21>
@
10K_0402_5%~D
@
R892
100K_0402_5%~D
+3.3V_RUN
R694
2.2K_0402_5%~D
2
2
2
2
2
1
2
R937
10K_0402_5%~D
DPB_CA_DET <21>
DPC_CA_DET
GPU_CLK_DDC
GPU_DAT_DDC
DVI_C_CLK_DDC
DVI_C_DAT_DDC
LDDC_CLK_GPU
LDDC_DATA_GPU
DVI_B_CLK_DDC
DVI_B_DAT_DDC
I2CE_SCL
I2CE_SDA
HDCP_CLK
HDCP_DAT
I2CS_SCL
I2CS_SDA
@ R673
@ R674
@ R675
@ R676
@ R678
ICH_AZ_GPU_BITCLK
ICH_AZ_GPU_SYNC
ICH_AZ_GPU_SDIN2
ICH_AZ_GPU_SDOUT
ICH_AZ_GPU_RST#
R1010
G1
G4
G3
G2
E3
E4
F4
G5
D5
E5
F6
G6
E2
E1
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA
<23>
<23>
<23>
<23>
<23>
AP2
AN3
AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2
GENERAL
PEG_MRX_GTX_P6
0.1U_0402_10V7K~D
PEG_MRX_GTX_N6 0.1U_0402_10V7K~D
2
1
C983
0.033U_0402_16V7K~D
IFPC_AUX
IFPC_AUX_N
IFPC_DPL0_TXD2
IFPC_DPL0_TXD2_N
IFPC_DPL1_TXD1
IFPC_DPL1_TXD1_N
IFPC_DPL2_TXD0
IFPC_DPL2_TXD0_N
IFPC_DPL3_TXC
IFPC_DPL3_TXC_N
RUF
1 C726 PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
<35>
1
Part 4 of 6
LVDS
2
C727
2
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
HDA
PEG_MRX_GTX_P5
0.1U_0402_10V7K~D
PEG_MRX_GTX_N5 0.1U_0402_10V7K~D
2
1
DPB_GPU_P14
GPU_GPIO18
HDMI_DET1
LCD_BCLK+_GPU
LCD_BCLK-_GPU
LCD_B0+_GPU
LCD_B0-_GPU
LCD_B1+_GPU
LCD_B1-_GPU
LCD_B2+_GPU
LCD_B2-_GPU
AM11
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11
AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11
MXM/DVI/DP
1 C724 PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
LCD_BCLK+_GPU
LCD_BCLK-_GPU
LCD_B0+_GPU
LCD_B0-_GPU
LCD_B1+_GPU
LCD_B1-_GPU
LCD_B2+_GPU
LCD_B2-_GPU
R930
4.99K_0402_1%~D
1
2
2
C725
1
PEG_MRX_GTX_P4
0.1U_0402_10V7K~D
PEG_MRX_GTX_N4 0.1U_0402_10V7K~D
2
1
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
2
1 C722 PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
LCD_ACLK+_GPU
LCD_ACLK-_GPU
LCD_A0+_GPU
LCD_A0-_GPU
LCD_A1+_GPU
LCD_A1-_GPU
LCD_A2+_GPU
LCD_A2-_GPU
THERMTRIP_VGA# <18>
2 0_0402_5%~D
GPIO10_REF_SW <55,56>
2
1
@ C982
0.1U_0402_10V7K~D
1
2
R890
10K_0402_5%~D
DPC_DOCK_HPD
DPC_DOCK_HPD
GPU_GPIO16
R931
20K_0402_1%~D
1
2
2
C723
2 0_0402_5%~D
1 R889
1@ R923
15K_0402_1%
1
2
PEG_MRX_GTX_P3
0.1U_0402_10V7K~D
PEG_MRX_GTX_N3 0.1U_0402_10V7K~D
2
1
1 R670
1@ R922
24.9K_0402_1%~D
1
2
1 C720 PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
1@ U56D
<19> LCD_ACLK+_GPU
<19> LCD_ACLK-_GPU
R860
<19> LCD_A0+_GPU
10K_0402_5%~D <19> LCD_A0-_GPU
<19> LCD_A1+_GPU
<19> LCD_A1-_GPU
<19> LCD_A2+_GPU
<19> LCD_A2-_GPU
1
2
C721
DPB_HPD <21>
BIA_PWM_GPU <19>
ENVDD_GPU <19>
PANEL_BKEN_GPU <37>
GPU_VID_0 <50>
GPU_VID_1 <50>
BIA_PWM_GPU
ENVDD_GPU
PANEL_BKEN_GPU
R921
4.99K_0402_1%~D
1
2
1 C718 PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_P2
0.1U_0402_10V7K~D
PEG_MRX_GTX_N2 0.1U_0402_10V7K~D
2
1
K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
R920
45.3K_0402_1%~D
1
2
1 C716 PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
2
C719
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SWAP_RDY_A/GPIO22
STEREO/GPIO23
DVO / GPIO
2
C717
PEG_MRX_GTX_P1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N1 0.1U_0402_10V7K~D
2
1
Part 1 of 6
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
DACs
PEG_MRX_GTX_P0
0.1U_0402_10V7K~D
PEG_MRX_GTX_N0 0.1U_0402_10V7K~D
2
1
AP17
AN17
AN19
AP19
AR19
AR20
AP20
AN20
AN22
AP22
AR22
AR23
AP23
AN23
AN25
AP25
AR25
AR26
AP26
AN26
AN28
AP28
AR28
AR29
AP29
AN29
AN31
AP31
AR31
AR32
AR34
AP34
I2C
PEG_MRX_GTX_N[0..15]
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
TEST
<12> PEG_MRX_GTX_N[0..15]
ENVDD_GPU
PEG_MRX_GTX_P[0..15]
PCI EXPRESS
<12> PEG_MRX_GTX_P[0..15]
PEG_MRX_GTX_P15
0.1U_0402_10V7K~D
PEG_MRX_GTX_N15 0.1U_0402_10V7K~D
2
1
1
MULTIUSE INPUT OUTPUT
1@
PEG_MTX_GRX_N[0..15]
<12> PEG_MTX_GRX_N[0..15]
C
2
2@ R1025
20K_0402_1%~D
1
2
<12> PEG_MTX_GRX_P[0..15]
D
3
PEG_MTX_GRX_P[0..15]
Friday, June 13, 2008
Sheet
1
51
of
63
5
4
3
2
0..31
FBAD[0..63] <55>
DQMA#[0..7]
DQSA_WP[0..7]
DQSA_RN[0..7]
DQSA_RN[0..7]
D
FBA_CMD[0..27]
FBA_CMD[0..27]
<55>
<55>
A5
V32
W31
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
SNN_FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
P30
P32
J30
H34
AF32
AF35
AL32
AL34
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
N32
L35
H31
G35
AD32
AC34
AJ31
AJ35
DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
DQSA_RN4
DQSA_RN5
DQSA_RN6
DQSA_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
N31
L34
J32
H35
AE31
AC33
AJ32
AJ34
DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
DQSA_WP4
DQSA_WP5
DQSA_WP6
DQSA_WP7
J27
FBA_VREF
FBCD[0..63]
NB9P-GLM2_BGA969~D
T115
T149
T151
A4
FBA_CMD6
A3
FBA_CMD7
CS1#
CS1#
FBA_CMD8
CS0#
CS0#
FBA_CMD9
A11
A11
FBA_CMD10
CAS#
CAS#
FBA_CMD11
WE#
WE#
FBA_CMD12
BA0
BA0
A5
A12
A12
RST/ODT
FBA_CMD15
RST/ODT
FBA_CMD16
A7
FBA_CMD17
A10
A10
FBA_CMD18
CKE
CKE
FBA_CMD19
A0
A0
FBA_CMD20
A9
A9
FBA_CMD21
A6
A6
FBA_CMD22
A2
FBA_CMD23
A8
FBA_CMD24
A3
FBA_CMD25
A1
A1
FBA_CMD26
A13
A13
FBA_CMD27
BA2
BA2
A7
A8
+FBVDDQ
10K_0402_5%~D
1
2
1
+FBVDDQ
CLKA0 <55> @
CLKA0# <55>
CLKA1 <55>
CLKA1# <55>
2
FBA_CMD5
T88
1
2
@
R700
1K_0402_1%~D
T32
T31
AC31
AC30
T30
BA1
A2
FBA_CMD14
15mil , TLC less than 500mil
CLKA0
CLKA0#
CLKA1
CLKA1#
R701
1
FBCD[0..63]
DQMC#[0..7]
FBA_CMD4
FBA_CMD13
R699
1K_0402_1%~D
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_DEBUG
T147
0.01U_0402_16V7K~D
C775
FB_VREF
BA1
FBA_CMD3
2
B
FBA_CMD2
RAS#
@
FBA_CMD28
RFU0
RFU0
FBA_CMD29
RFU1
RFU1
FBA_CMD30
RFU2
RFU2
<56>
DQMC#[0..7] <56>
DQSC_RN[0..7]
<55>
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
MEMORY
INTERFACE 1
C
Part 2 of 6
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
RAS#
DQSC_WP[0..7]
1@ U56B
R30
R32
P31
N30
L31
M32
M30
L30
P33
P34
N35
P35
N34
L33
L32
N33
K31
K30
G30
K32
G32
H30
F30
G31
H33
K35
K33
G34
K34
E33
E34
G33
AG30
AH31
AG32
AF31
AF30
AD30
AC32
AE30
AE32
AF33
AF34
AE35
AE33
AE34
AC35
AB32
AN33
AK32
AL33
AM33
AL31
AK30
AJ30
AH30
AM35
AH33
AH35
AH32
AH34
AM34
AL35
AJ33
FBA_CMD1
32..63
DQMA#[0..7] <55>
DQSA_WP[0..7]
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
A4
FBC_CMD[0..27]
DQSC_WP[0..7]
<56>
DQSC_RN[0..7]
<56>
FBC_CMD[0..27]
D
<56>
1@ U56C
FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63
D11
E11
F10
D8
F8
F9
E8
F12
B11
C13
A11
B8
A8
C8
C11
C10
D12
E13
F17
F15
F16
E16
F14
F13
D13
A13
B13
A14
C16
A17
B16
D16
D24
D26
E25
F25
F27
E28
F28
D29
A25
B25
D25
C26
C28
B28
A28
A29
E29
F29
D30
E31
C33
D33
F32
E32
B29
C29
B31
C31
B32
C32
B34
B35
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
Part 3 of 6
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
C17
B19
D18
F21
A23
D21
B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
B20
A20
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
SNN_FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
F11
D10
D15
A16
D27
D28
D34
A34
DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
D9
B10
E14
B14
F26
A26
D31
A31
DQSC_RN0
DQSC_RN1
DQSC_RN2
DQSC_RN3
DQSC_RN4
DQSC_RN5
DQSC_RN6
DQSC_RN7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
E10
A10
D14
C14
E26
B26
D32
A32
DQSC_WP0
DQSC_WP1
DQSC_WP2
DQSC_WP3
DQSC_WP4
DQSC_WP5
DQSC_WP6
DQSC_WP7
FBC_CLK0
FBC_CLK0_N
FBC_CLK1
FBC_CLK1_N
FBC_DEBUG
E17
D17
D23
E23
G19
MEMORY
INTERFACE 2
FBAD[0..63]
FBA_CMD0
1
CLKC0
CLKC0#
CLKC1
CLKC1#
R857
1
T148
C
T140
T141
T150
T152
B
CLKC0 <56>
CLKC0# <56>
CLKC1 <56>
CLKC1# <56>
2
+FBVDDQ
1@ 10K_0402_5%~D
NB9P-GLM2_BGA969~D
FBA_RST#
FBA_RST#
FBA_CMD15
1
R697
2
10K_0402_5%~D
1
R698
2
10K_0402_5%~D
FBC_CMD15 1
1@ R858
2
FBA_CKE10K_0402_5%~D
FBA_CKE
FBA_CMD18
FBC_CMD18 1
2
1@ R812
10K_0402_5%~D
Pull-down for
initialization
Pull-down for initialization
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
NVG98 Memory Interface
Size
Date:
4
3
2
Document Number
Rev
1.0
LA-4051P
Thursday, June 05, 2008
Sheet
1
52
of
63
4
3
+GPU_CORE
1@
2
1
+1.1V_GFX_PCIE
U56E
Place near Balls
2
2
1
L65
10UH_CB2012T100MR_20%_0805~D
C787
4.7U_0603_6.3V4Z~D
C604
22U_0805_6.3V6M~D
1
2
1.8V for G84 & G9X
2
2
1
2
1
2
+FBVDDQ
L47
1
2
2
BLM15AG121SN1D_2P~D
B
BLM18PG600SN1_0603~D
+IFPC_IOVDD
1
2
2
C866
C879
C880
1
2
4700P_0402_25V7K~D
1
C
20mil
470P_0402_50V7K~D
2
2
C859
4.7U_0603_6.3V6M~D
2
C842
0.1U_0402_10V7K~D
2
1
C841
0.1U_0402_10V7K~D
2
1
1
C1029
470P_0402_50V7K~D
2
1
1
2
1
2
C856
4700P_0402_25V7K~D
2
1
2
2
C837
4700P_0402_25V7K~D
2
1
2
1
C820
1U_0402_6.3V6K~D
2
1
2
1
C836
4700P_0402_25V7K~D
2
1
2
1
C819
4.7U_0603_6.3V4Z~D
2
1
2
1
C835
4700P_0402_25V7K~D
2
1
2
1
C818
1U_0402_6.3V6K~D
1
1
+1.1V_GFX_PCIE
L67
+IFPAB_IOVDD
+IFPC_IOVDD
+IFPE_IOVDD
L71
+IFPEF_PLLVDD
2
1
2
1
1
2
+FBVDDQ
2
BLM15AG121SN1D_2P~D
C1008
4.7U_0603_6.3V6M~D
1
+GPU_PLLVDD
C1007
4700P_0402_25V7K~D
+IFPAB_PLLVDD
+IFPCD_PLLVDD
+IFPEF_PLLVDD
C1006
470P_0402_50V7K~D
AE9
AD9
AF9
1
2
1
1
C855
470P_0402_50V7K~D
1
2
2
+IFPAB_PLLVDD
+FBVDDQ
1
1
+FBVDDQ
L48
BLM18AG121SN1D_0603~D
1
2
IFPAB_PLLVDD = 160 mA
Place near GPU
1
2
C864
4.7U_0603_6.3V6M~D
2
1
C861
4700P_0402_25V7K~D
2
1
2
C860
470P_0402_50V7K~D
C1028
4700P_0402_25V7K~D
1
C959
22U_0805_6.3V6M~D
2
+PEX_PLLVDD
1
Place near GPU
IFPAB_IOVDD = 100mA
C799
4.7U_0603_6.3V4Z~D
2
1
C1035
1U_0402_6.3V6K~D
POWER
C876
0.1U_0402_10V7K~D
2
1
C786
1U_0603_10V4Z~D
1
NB9P-GLM2_BGA969~D
A
IFPEF_PLLVDD = 160 mA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL")
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
2
Place near Balls
1
C840
0.1U_0402_10V7K~D
2
PLLVDD
VID_PLLVDD
SP_PLLVDD
2
1
C834
4700P_0402_25V7K~D
2
1
2
BLM15AG121SN1D_2P~D
VDD_SENSE
10 mil
C850
0.1U_0402_10V7K~D
2
1
C849
1U_0402_6.3V6K~D
2
1
C848
0.1U_0402_10V7K~D
1
C847
0.1U_0402_10V7K~D
2
C1037
4.7U_0603_6.3V6M~D
1
1
AD20
2
1
C817
1U_0402_6.3V6K~D
+GPU_PLLVDD
A
+1.1V_GFX_PCIE
AG9
AG10
AJ8
AK8
AE7
AD7
AK9
AJ9
AJ6
2
1
C839
0.1U_0402_10V7K~D
L45
GPU_PLLVDD = 140 mA
IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD
IFPE_IOVDD
IFPF_IOVDD
IFPAB_PLLVDD
IFPCD_PLLVDD
IFPEF_PLLVDD
2
+1.1V_GFX_PCIE
C833
4700P_0402_25V7K~D
2
1
C838
0.022U_0402_16V7K~D
2
1
2
BLM15AG121SN1D_2P~D
C862
4.7U_0603_6.3V6M~D
1
C863
4700P_0402_25V7K~D
2
C865
470P_0402_50V7K~D
1
1
+1.1V_GFX_PCIE
+IFPAB_IOVDD
C832
4700P_0402_25V7K~D
L66
+IFPCD_PLLVDD
2
Place near Balls
1
C1036
1U_0402_6.3V6K~D
IFPCD_PLLVDD = 160 mA
+FBVDDQ
B18
E21
G8
G9
G17
G18
G22
H29
J14
J15
J16
J17
J20
J21
J22
J23
J24
J29
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
2
1
PEX_IOVDDQ = 1600mA
C831
4700P_0402_25V7K~D
2
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
2
1
Place near GPU
C814
4700P_0402_25V7K~D
2
AG14
2
1
Place near Balls
C830
4700P_0402_25V7K~D
1
2
L70
BLM18PG600SN1_0603~D
C1004
4.7U_0603_6.3V6M~D
1
C1001
2
4700P_0402_25V7K~D
1
C1000
470P_0402_50V7K~D
B
1
PEX_PLLVDD
2
C813
4700P_0402_25V7K~D
+1.1V_GFX_PCIE
20mil
+IFPE_IOVDD
2
C816
0.1U_0402_10V7K~D
2
AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16
1
C815
0.1U_0402_10V7K~D
2
1
1
+1.1V_GFX_PCIE
C798
1U_0402_6.3V6K~D
1
C1030
0.1U_0402_10V7K~D
2
C854
470P_0402_50V7K~D
1
C853
4700P_0402_25V7K~D
2
C852
4.7U_0603_6.3V6M~D
1
MIOA_VDD pull-down 10K.
No use! 200711/26
C800
.47U_0402_6.3V6-K~D
+DACA_VDD
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24
1
C796
.47U_0402_6.3V6-K~D
Delete TV Fucntion
2007/11/20
L46
1
2
BLM15AG121SN1D_2P~D
AK16
AK17
AK21
AK24
AK27
C797
0.1U_0402_10V7K~D
DACA VDD= 53mA
+3.3V_RUN
2
BLM15AG121SN1D_2P~D
PEX_IOVDD = 500mA
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
C795
0.1U_0402_10V7K~D
Close J9~J13
C
2
2
1
1
PEX_PLLVDD = 100mA
+PEX_PLLVDD
+3.3V_RUN
C782
4.7U_0603_6.3V4Z~D
2
+3.3V_MIO
2
1
D
MIOA/B = 20mA
+FBVDDQ
1 R990
2
0_0402_5%~D
1
2
1
10 mil
C1034
.47U_0402_6.3V6-K~D
2
1
R902 2
10K_0402_5%~D
C780
1U_0402_6.3V6K~D
2
1
C929
4.7U_0603_6.3V4Z~D
2
1
C928
4.7U_0603_6.3V4Z~D
2
1
C927
4.7U_0603_6.3V4Z~D
1
C845
0.1U_0402_10V7K~D
C844
0.1U_0402_10V7K~D
1
C843
1U_0805_10V7K~D
2
1
C779
0.1U_0402_10V7K~D
Place near BGA
+3.3V_RUN
P9
R9
T9
U9
U5
AA9
AB9
W9
Y9
AA7
2
1
C785
0.01U_0402_16V7K~D
2
MIOA_VDDQ_0
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_CAL_PD_VDDQ
MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_CAL_PD_VDDQ
R1012
+DACA_VDD
10K_0402_5%~D
AJ12
+DACB_VDD
AC6
1
2
AG7 +DACC_VDD 1
2
10K_0402_5%~D
R722
AG27
+FB_DLLAVDD
AF27
J19
R706
J18
44.2_0402_1%~D
FB_CAL_PD_VDDQ
K27
1
2
1
C784
0.1U_0402_10V7K~D
2
1
FB_CAL_PD_VDDQ
+FB_DLLAVDD
R706
45.3 ohm (8X GPU)
TBD
(9X GPU)
C1023
0.1U_0402_10V7K~D
2
1
C808
0.47U_0402_10V4Z~D
2
1
C807
0.47U_0402_10V4Z~D
2
1
C806
0.47U_0402_10V4Z~D
2
1
C826
0.47U_0402_10V4Z~D
2
1
C825
0.47U_0402_10V4Z~D
2
1
C824
0.47U_0402_10V4Z~D
2
1
C823
0.47U_0402_10V4Z~D
1
C822
0.47U_0402_10V4Z~D
C926
0.47U_0402_10V4Z~D
2
C925
0.47U_0402_10V4Z~D
1
FB_DLLAVDD
FB_PLLAVDD
FBAC_DLLAVDD
FBAC_PLLAVDD
+3.3V_RUN
C1033
4.7U_0603_6.3V4Z~D
D
DACA_VDD
DACB_VDD
DACC_VDD
L68
J9
J10
J11
J12
J13
C888
1U_0402_6.3V6K~D
2
Part 5 of 6
VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
C874
0.1U_0402_10V7K~D
2
1
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110
C851
0.1U_0402_10V7K~D
2
1
C809
0.1U_0402_10V7K~D
2
1
C793
0.1U_0402_10V7K~D
2
1
C821
0.1U_0402_10V7K~D
2
1
C792
0.1U_0402_10V7K~D
2
1
C791
0.1U_0402_10V7K~D
2
1
C794
0.1U_0402_10V7K~D
2
1
C805
0.1U_0402_10V7K~D
1
C812
0.1U_0402_10V7K~D
C811
0.1U_0402_10V7K~D
2
C810
0.1U_0402_10V7K~D
1
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19
P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
4.7U_0603_6.3V6M~D
5
4
3
CONTAINS CONFIDENTIAL
THIS DOCUMENT MAY NOT
OF DELL. IN ADDITION,
DISCLOSED TO ANY THIRD
Title
NVG98 POWER
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
2
Sheet
1
53
of
63
5
4
3
2
1
1@ U56F
D
C
B
+FBVDDQ Source
+15V_ALW
4
1
2
3
R815
100K_0402_5%~D
Q117B
2N7002DW-7-F_SOT363-6~D
5
1
4
6
FBVDDQ_EN
2
1
2
@ C897
@C897
4700P_0402_25V7K~D
1
<41,50> GFX_CORE_PWRGD
2
Q117A
2N7002DW-7-F_SOT363-6~D
+FBVDDQ
R814
20K_0402_5%~D
Q116
STS11NF30L_SO8~D
1
2
3
C889
10U_0805_10V4Z~D
2
+3.3V_ALW2
8
7
6
5
1
R813
100K_0402_5%~D
2
1
+1.8V_MEM
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
Part 6 of 6
GND
B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F5
F31
F34
J2
J5
J31
J34
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V2
V5
V9
V12
V14
V16
V18
V20
V22
V24
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
RFU_GND_0
RFU_GND_1
GND_SENSE
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33
AK14
K9
AD19
FB_CAL_PU_GND
FB_CAL_TERM_GND
L27
M27
MIOA_CAL_PU_GND
MIOB_CAL_PU_GND
T5
AA6
D
C
B
FB_CAL_PU_GND
FB_CAL_TERM_GND
MIOA_CAL_PU_GND
MIOB_CAL_PU_GND
R703 1
R859 1
2 30.9_0402_1%
2 40.2_0402_1%~D
2
@ R1026 2
@ R861
1
1 49.9_0402_1%~D
49.9_0402_1%~D
NB9P-GLM2_BGA969~D
A
A
R860/R861 ; depop for G84
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
NVG98 GND
Size
Date:
4
3
2
Document Number
Rev
1.0
LA-4051P
Thursday, June 05, 2008
Sheet
1
54
of
63
4
3
2
32Mx32 GDDR3
1
32Mx32 GDDR3
FBAD[0..63]
FBAD[0..63] <52>
ZQ1
2
R862
243_0402_1%~D
DQSA_RN3
DQSA_RN2
DQSA_RN1
DQSA_RN0
+FBVDDQ
ZQ
MF
RDQS0
RDQS1
RDQS2
RDQS3
A2
A11
F1
F12
M1
M12
V2
V11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V4
V9
H10
SEN
RESET
BA2
J1
J12
VSSA
VSSA
VDDA
VDDA
K1
K12
H1
H12
VREF
VREF
FBA_CMD27
FBA_CMD8
FBA_CMD18
FBA_CMD10
FBA_CMD14
FBA_CMD11
CLKA1
CLKA1#
H3
F4
H9
F9
J3
H4
J11
J10
RAS#
CAS#
WE#
CS0#
A12/CS1#
CKE
CK
CK#
U58 is Mirror
+FBVDDQ
<52> CLKA1
<52> CLKA1#
1
2
+FBVDDQ
R863
243_0402_1%~D
ZQ2
A4
A9
DQSA_RN7
DQSA_RN6
DQSA_RN5
DQSA_RN4
D3
D10
P10
P3
RDQS0
RDQS1
RDQS2
RDQS3
A2
A11
F1
F12
M1
M12
V2
V11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V4
V9
H10
SEN
RESET
BA2
J1
J12
VSSA
VSSA
+FBVDDQ
FBA_CMD15
FBA_CMD1
+FBVDDQ
ZQ
MF
A3
A10
G1
G12
L1
L12
V3
V10
1
2
2N7002W-7-F_SOT323-3~D
1
2
1
Q119
2
+FBVDDQ
B
R865
511_0402_1%~D
12 mil
2
2
1
2
2
2
2
FBA_VREF_4
1
2
2
FBA_VREF_5
1
S
R868
1.18K_0402_1%~D
C903
0.1U_0402_10V7K~D
3
D
2
G
909_0402_1%~D
1
2
GPIO10_REF_SW <51,56>
for NB8P value
C907
0.01U_0402_16V7K~D
1
1
C902
0.1U_0402_10V7K~D
2
2
C906
0.01U_0402_16V7K~D
1
1
C901
0.1U_0402_10V7K~D
2
2
C905
0.01U_0402_16V7K~D
1
1
C884
0.1U_0402_10V7K~D
2
2
C904
0.01U_0402_16V7K~D
1
1
C883
0.1U_0402_10V7K~D
2
2
C887
0.01U_0402_16V7K~D
1
C886
0.01U_0402_16V7K~D
2
C885
0.01U_0402_16V7K~D
1
2
1
C882
0.1U_0402_10V7K~D
2
1
C881
4.7U_0603_6.3V6M~D
2
1
C900
4.7U_0603_6.3V6M~D
2
1
C899
4.7U_0603_6.3V6M~D
1
2
C912
0.1U_0402_10V7K~D
2
2
1
C916
0.01U_0402_16V7K~D
1
1
C893
0.1U_0402_10V7K~D
2
2
C915
0.01U_0402_16V7K~D
2
1
1
C892
0.1U_0402_10V7K~D
1
2
C914
0.01U_0402_16V7K~D
2
2
1
C891
0.1U_0402_10V7K~D
2
1
1
C913
0.01U_0402_16V7K~D
2
1
2
C896
0.01U_0402_16V7K~D
2
1
2
C895
0.01U_0402_16V7K~D
1
R870
1.18K_0402_1%~D
A
FBA_VREF_2
C919
0.01U_0402_16V7K~D
2
909_0402_1%~D
C894
0.01U_0402_16V7K~D
R738
511_0402_1%~D
12 mil
R869
1
2
1
C911
0.1U_0402_10V7K~D
2
1
C910
0.1U_0402_10V7K~D
+FBVDDQ
1
C890
4.7U_0603_6.3V6M~D
S
1
1
R832
1.18K_0402_1%~D
Place below decoupling caps close U58
Place below decoupling caps close U57
C909
4.7U_0603_6.3V6M~D
2
+FBVDDQ
C908
4.7U_0603_6.3V6M~D
D
FBA_VREF_3
2
909_0402_1%~D
1
+FBVDDQ
12 mil
C918
0.01U_0402_16V7K~D
1
R887
1.18K_0402_1%~D
2
G
R831
1
R867
C872
0.01U_0402_16V7K~D
909_0402_1%~D
R864
511_0402_1%~D
12 mil
FBA_VREF_1
2
K1
K12
+FBVDDQ
A3
A10
G1
G12
L1
L12
V3
V10
1
2
R866
VDDA
VDDA
243 ohm for NB8P
475 ohm for NB9X
Place close to U58
+FBVDDQ
K4J10324QD-BC12_FBGA136~D
R734
511_0402_1%~D
1
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
R824
475_0402_1%~D
CLKA1#
C
K4J10324QD-BC12_FBGA136~D
B
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CLKA1
2
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
FBA_VREF_3
FBA_VREF_4
D
C917
0.01U_0402_16V7K~D
FBA_CMD15
FBA_CMD27
A4
A9
D3
D10
P10
P3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
WDQS0
WDQS1
WDQS2
WDQS3
<52>
1
RAS#
CAS#
WE#
CS0#
A12/CS1#
CKE
CK
CK#
D2
D11
P11
P2
FBAD56
FBAD62
FBAD63
FBAD59
FBAD61
FBAD57
FBAD58
FBAD60
FBAD48
FBAD49
FBAD51
FBAD50
FBAD52
FBAD53
FBAD54
FBAD55
FBAD42
FBAD41
FBAD40
FBAD47
FBAD45
FBAD46
FBAD43
FBAD44
FBAD33
FBAD34
FBAD35
FBAD32
FBAD38
FBAD39
FBAD37
FBAD36
2
H3
F4
H9
F9
J3
H4
J11
J10
DQSA_WP7
DQSA_WP6
DQSA_WP5
DQSA_WP4
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
1
FBA_CMD1
FBA_CMD10
FBA_CMD11
FBA_CMD8
FBA_CMD14
FBA_CMD18
CLKA0
CLKA0#
FBA_CMD3
FBA_CMD12
DQMA#7
DQMA#6
DQMA#5
DQMA#4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
FBA_CMD[0..27]
2
VREF
VREF
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H1
H12
BA2
T144
CS0#
CKE
CAS#
A4
A5
A6
A9
A0
A1
A2
A11
A10
A3
A8
A7
WE#
BA1
BA0
RAS#
--> NV/CS1#
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
A12
BA0
BA1
DM0
DM1
DM2
DM3
<52>
1
1
FBA_VREF_1
FBA_VREF_2
Mirror U58
RAS# -->
CAS# -->
WE
-->
CS0# -->
A0
-->
A1
-->
A2
-->
A3
-->
A4
-->
A5
-->
A6
-->
A7
-->
A8
-->
A9
-->
A10 -->
A11 -->
CKE -->
BA0 -->
BA1 -->
BA2 -->
NC/CS1#
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
J2
G4
G9
E3
E10
N10
N3
<52>
DQSA_RN[0..7]
1
<52> CLKA0
<52> CLKA0#
WDQS0
WDQS1
WDQS2
WDQS3
FBA_CMD5
FBA_CMD13
FBA_CMD21
FBA_CMD20
FBA_CMD19
FBA_CMD25
FBA_CMD4
FBA_CMD9
FBA_CMD17
FBA_CMD6
FBA_CMD23
FBA_CMD16
Q118
C
D2
D11
P11
P2
FBAD31
FBAD30
FBAD27
FBAD29
FBAD24
FBAD28
FBAD26
FBAD25
FBAD22
FBAD20
FBAD23
FBAD18
FBAD21
FBAD16
FBAD19
FBAD17
FBAD9
FBAD8
FBAD14
FBAD11
FBAD15
FBAD13
FBAD10
FBAD12
FBAD5
FBAD7
FBAD4
FBAD6
FBAD3
FBAD1
FBAD2
FBAD0
FBA_VREF_6
243 ohm for NB8P
475 ohm for NB9X
Place close to U57
DQSA_WP3
DQSA_WP2
DQSA_WP1
DQSA_WP0
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
1
1
R750
475_0402_1%~D
CLKA0#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQSA_WP[0..7]
DQMA#[0..7] <52>
FBA_CMD[0..27]
3
2
CLKA0
FBA_CMD12
FBA_CMD3
DQMA#3
DQMA#2
DQMA#1
DQMA#0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
A12
BA0
BA1
DM0
DM1
DM2
DM3
DQMA#[0..7]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T143
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
J2
G4
G9
E3
E10
N10
N3
U58
2N7002W-7-F_SOT323-3~D
5@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
FBA_CMD19
FBA_CMD25
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
FBA_CMD21
FBA_CMD16
FBA_CMD23
FBA_CMD20
FBA_CMD17
FBA_CMD9
DQSA_RN[0..7]
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
U57
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
5@
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
DQSA_WP[0..7]
1
5
A
GPIO10_REF_SW <51,56>
DELL CONFIDENTIAL/PROPRIETARY
for NB8P value
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
NVG94 External GDDR3-A
Size
Date:
4
3
2
Document Number
Rev
1.0
LA-4051P
Thursday, June 05, 2008
Sheet
1
55
of
63
4
3
2
32Mx32 GDDR3
5@
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
ZQ3
2
A4
A9
1@ R873
243_0402_1%~D
DQSC_RN1
DQSC_RN0
DQSC_RN3
DQSC_RN2
+FBVDDQ
+FBVDDQ
2
2
SEN
RESET
BA2
J1
J12
VSSA
VSSA
VDDA
VDDA
K1
K12
C
+FBVDDQ
A3
A10
G1
G12
L1
L12
V3
V10
2
1@2
1@
1
2
1
2
12 mil
FBC_VREF_3
2
909_0402_1%~D
1
1@
R877
1.18K_0402_1%~D
D
S
1@
2
G
2
1@
1
1@2
1@
+FBVDDQ
B
1@
R881
511_0402_1%~D
FBC_VREF_4
12 mil
2
R882
909_0402_1%~D
1@ R883
1.18K_0402_1%~D
C973
0.1U_0402_10V7K~D
1
R876
1
1
2
1@
GPIO10_REF_SW <51,55>
C977
0.01U_0402_16V7K~D
2
1@
1
1
C954
0.1U_0402_10V7K~D
2
1@
1
1@2
C976
0.01U_0402_16V7K~D
2
1@
1
1@2
1
C972
0.1U_0402_10V7K~D
2
1@
1
1@2
1
C975
0.01U_0402_16V7K~D
1@
1
1@2
1
C974
0.01U_0402_16V7K~D
1@
1@2
1
C971
0.1U_0402_10V7K~D
1@2
1
C953
0.1U_0402_10V7K~D
1@ 2
1
C957
0.01U_0402_16V7K~D
2
1
C956
0.01U_0402_16V7K~D
2
1@ 1
2
1@
R875
511_0402_1%~D
1@
Place below decoupling caps close U60
C955
0.01U_0402_16V7K~D
2
1@ 1
2
1@1
C968
0.01U_0402_16V7K~D
2
1@ 1
2
1@1
C967
0.01U_0402_16V7K~D
1@ 1
2
C966
0.01U_0402_16V7K~D
2
2
C965
0.01U_0402_16V7K~D
2
1@ 1
C948
0.01U_0402_16V7K~D
A
1@ 1
C947
0.01U_0402_16V7K~D
2
C946
0.01U_0402_16V7K~D
1@ 1
GPIO10_REF_SW <51,55>
2
1@1
C952
0.1U_0402_10V7K~D
2
2
1@1
C951
4.7U_0603_6.3V6M~D
1
V4
V9
H10
+FBVDDQ
1
C970
4.7U_0603_6.3V6M~D
2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ZQ
MF
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
+FBVDDQ
C969
4.7U_0603_6.3V6M~D
2
A2
A11
F1
F12
M1
M12
V2
V11
FBC_CMD15
FBC_CMD1
C964
0.1U_0402_10V7K~D
Q125
RDQS0
RDQS1
RDQS2
RDQS3
+FBVDDQ
C963
0.1U_0402_10V7K~D
1@ R886
1.18K_0402_1%~D
1@
2
1@1
C962
0.1U_0402_10V7K~D
1
2
1@1
C945
0.1U_0402_10V7K~D
2
FBC_VREF_2
1@1
C944
0.1U_0402_10V7K~D
12 mil
1@1
C943
0.1U_0402_10V7K~D
1@1
C942
4.7U_0603_6.3V6M~D
1@
C924
0.01U_0402_16V7K~D
1
D3
D10
P10
P3
+FBVDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
+FBVDDQ
R884
511_0402_1%~D
909_0402_1%~D
A4
A9
DQSC_RN7
DQSC_RN6
DQSC_RN5
DQSC_RN4
2
1@ R874
243_0402_1%~D
Place below decoupling caps close U59
1@
R885
ZQ4
K4J10324QD-BC12_FBGA136~D
1@
+FBVDDQ
<52> CLKC1
<52> CLKC1#
K1
K12
VDDA
VDDA
VSSA
VSSA
C961
4.7U_0603_6.3V6M~D
S
SEN
RESET
BA2
J1
J12
C960
4.7U_0603_6.3V6M~D
3
2
G
2N7002W-7-F_SOT323-3~D
1@
V4
V9
H10
RAS#
CAS#
WE#
CS0#
A12/CS1#
CKE
CK
CK#
243 ohm for NB8P
475 ohm for NB9X
Place close to U60
C923
0.01U_0402_16V7K~D
D
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
H3
F4
H9
F9
J3
H4
J11
J10
U60 is Mirror
+FBVDDQ
1
FBC_CMD27
FBC_CMD8
FBC_CMD18
FBC_CMD10
FBC_CMD14
FBC_CMD11
CLKC1
CLKC1#
R872
475_0402_1%~D
CLKC1#
1
1
FBC_VREF_5
1
1@R880
1.18K_0402_1%~D
1
B
A2
A11
F1
F12
M1
M12
V2
V11
12 mil
FBC_VREF_1
2
909_0402_1%~D
RDQS0
RDQS1
RDQS2
RDQS3
C922
0.01U_0402_16V7K~D
1
2
R879
1
1@
1@
R878
511_0402_1%~D
D3
D10
P10
P3
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
VREF
VREF
1@
C921
0.01U_0402_16V7K~D
FBC_CMD15
FBC_CMD27
ZQ
MF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
H12
D
<52>
CLKC1
2
RAS#
CAS#
WE#
CS0#
A12/CS1#
CKE
CK
CK#
FBC_VREF_3
FBC_VREF_4
FBC_CMD[0..27]
1
H3
F4
H9
F9
J3
H4
J11
J10
WDQS0
WDQS1
WDQS2
WDQS3
<52>
DQMC#[0..7] <52>
FBC_CMD[0..27]
1
FBC_CMD1
FBC_CMD10
FBC_CMD11
FBC_CMD8
FBC_CMD14
FBC_CMD18
CLKC0
CLKC0#
D2
D11
P11
P2
DQMC#[0..7]
2
VREF
VREF
DQSC_WP7
DQSC_WP6
DQSC_WP5
DQSC_WP4
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
<52>
DQSC_RN[0..7]
1
H1
H12
FBC_CMD3
FBC_CMD12
DQMC#7
DQMC#6
DQMC#5
DQMC#4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
FBCD62
FBCD61
FBCD63
FBCD60
FBCD58
FBCD59
FBCD57
FBCD56
FBCD55
FBCD54
FBCD52
FBCD53
FBCD50
FBCD51
FBCD48
FBCD49
FBCD47
FBCD41
FBCD46
FBCD40
FBCD42
FBCD45
FBCD44
FBCD43
FBCD38
FBCD39
FBCD36
FBCD37
FBCD34
FBCD35
FBCD32
FBCD33
2
FBC_VREF_1
FBC_VREF_2
BA2
CS0#
CKE
T146
CAS#
A4
A5
A6
A9
A0
A1
A2
A11
A10
A3
A8
A7
WE#
BA1
BA0
RAS#
--> NV/CS1#
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
A12
BA0
BA1
DM0
DM1
DM2
DM3
1
WDQS0
WDQS1
WDQS2
WDQS3
RAS# -->
CAS# -->
WE
-->
CS0# -->
A0
-->
A1
-->
A2
-->
A3
-->
A4
-->
A5
-->
A6
-->
A7
-->
A8
-->
A9
-->
A10 -->
A11 -->
CKE -->
BA0 -->
BA1 -->
BA2 -->
NC/CS1#
DQSC_RN[0..7]
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
J2
G4
G9
E3
E10
N10
N3
<52>
DQSC_WP[0..7]
2
1
D2
D11
P11
P2
Mirror U60
FBCD[0..63]
2
<52> CLKC0
<52> CLKC0#
C
DQSC_WP1
DQSC_WP0
DQSC_WP3
DQSC_WP2
FBC_CMD5
FBC_CMD13
FBC_CMD21
FBC_CMD20
FBC_CMD19
FBC_CMD25
FBC_CMD4
FBC_CMD9
FBC_CMD17
FBC_CMD6
FBC_CMD23
FBC_CMD16
Q124
243 ohm for NB8P
475 ohm for NB9X
Place close to U59
FBC_CMD12
FBC_CMD3
DQMC#1
DQMC#0
DQMC#3
DQMC#2
FBCD13
FBCD12
FBCD15
FBCD11
FBCD10
FBCD8
FBCD14
FBCD9
FBCD6
FBCD2
FBCD5
FBCD3
FBCD4
FBCD1
FBCD7
FBCD0
FBCD25
FBCD26
FBCD27
FBCD24
FBCD29
FBCD28
FBCD31
FBCD30
FBCD16
FBCD17
FBCD22
FBCD23
FBCD19
FBCD18
FBCD21
FBCD20
FBC_VREF_6
1
CLKC0#
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
1
T145
R871
475_0402_1%~D
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
3
1@
FBCD[0..63]
DQSC_WP[0..7]
A3
A10
G1
G12
L1
L12
V3
V10
2
CLKC0
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
A12
BA0
BA1
DM0
DM1
DM2
DM3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
J2
G4
G9
E3
E10
N10
N3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBC_CMD19
FBC_CMD25
FBC_CMD22
FBC_CMD24
FBC_CMD0
FBC_CMD2
FBC_CMD21
FBC_CMD16
FBC_CMD23
FBC_CMD20
FBC_CMD17
FBC_CMD9
U60
K4J10324QD-BC12_FBGA136~D
2N7002W-7-F_SOT323-3~D
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
U59
32Mx32 GDDR3
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
5@
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
5
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
Title
NVG94 External GDDR3-B
Size
Date:
4
3
2
Document Number
Rev
1.0
LA-4051P
Thursday, June 05, 2008
Sheet
1
56
of
63
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Date
Request
Owner
Issue Description
Solution Description
Rev.
1
37
ECE5028
2007/10/09
Compal
change BID pop option to X01: SCH165393
R534 (depop) ;
2
33
USB2.0
2007/10/25
Compal
Charger USB Fail: SCH165395
Need to swap the connection for USB_CHARGER_PWR_EN# & ESATA_USB_PWR_EN#
X01
3
13
Cantiga
2007/10/25
Compal
modify JUMPER ref. name
Modify ref name from P1 to PJP22
X01
4
51
NV98
2007/10/25
Compal
VRAM strap pin pop option
depop R922,R923,R933,R934 and pop R920,R921,R935,R936 to match 16Mx32 (Samsung)
51
NV98
20
CRT SW
2007/10/25
Compal
5
C
Title
No more TV out function supported on
Edock-LIO:SCH165398
R529 ( pop )
X01
D
X01
Delete TV signals & Circuit, and remove R669, R762, R763
X01
6
6
Clock
2007/11/1
Compal
Clock 27M R37 Resistor Error:SCH165399
7
7
Quad Core
2007/11/5
Compal
Support Quad Core CPU
R37 change value to 33ohm
X01
8
21
DP
2007/11/5
Compal
Support DP compoments
(1) Support DP, all components stuff
X01
9
21
DP
2007/11/5
Compal
DPB_HPD# Voltage Level
Remove R1006 pull down 7.5K (UMA need the resistor), becasue Descrite level is 3.3V
X01
10
21
DP
2007/11/5
Compal
DOCK_DET# Double Pull Up
Remove R799 for Double Pull Up
X01
11
21
DP
2007/11/5
Compal
DP Spec for AUX/# need pull down 100k
add DPB_MB_AUX/# --> R895/R896
(1) Quad Core Support, stuff R941, R984, R945, R946, R943, R942, R944, Q14, Q129
X01
(2) Quad Core ITP Support, stuff R976, R977, R978, R979, R980, R981, R982, R983
C
X01
add DPB_DOCK_AUX/# --> R897/R898
add DPC_DOCK_AUX/# --> R899/R900 (no-stuff)
12
22
SB
2007/11/5
Compal
13
23
SB
2007/11/5
Compal
SB Remove RTC Detect Funcion
14
23
SB
51
GPU
2007/11/5
Compal
Support HDCP Audio:SCH165403
24
SB
2007/11/5
Compal
SB GPIO Change:SCH165431
15
MDC Reset Change Control By ECE5028 to 5V Level:SCH165401
SB U10 PinF6 change Name to GNT3#/GPIO55 only
X01
Remove R375, R961, R960, Q130 and Add T46 on U10 pinAE8
X01
SB Stuff 3rd HD Audio to GPU R243, R244, R245, R246
X01
GPU Stuff R673, R674, R676, R678 0ohm, R675 33ohm
37
(1) Sniffer detect Remove From SB to ECE5028 GPIOH7, U10 pinAE8 add T39, pull up resistor
R754 change to page37
(2)R266 USB_MCARD3_DET# move to page34
(3)SB U10 pinC12 net named to "LAN_PHY_PWR_CNTRL"
X01
16
28
Audio
2007/11/5
Compal
Audio Test Result:SCH165433
C437/C436 change from 1uF_1206 to 2.2uF_1206
X01
17
31
37
PWR Board
2007/11/5
Compal
Power Board Detect pin
JS1394 pin9 change name to "PWR_BTN_BD_DET#",
and connect to page 37 ECE5028 pin33 GPIOH7
X01
LOM
2007/11/5
Compal
LOM Disable pin name changed:SCH165431
LOM Disable pin name changed to "LAN_PHY_PWR_CNTRL"
and connect to page 37 ECE5028 pin88 GPIOG0
ESATA
2007/11/5
Compal
ESATA Enable pin name Change:SCH165431
ESATA Enable pin name U29 Changed to "ESATA_USB_PWR_EN#"
and connector to ECE5028 pin82 GPIOB2
X01
X01
18
B
19
20
29
37
33
37
33
37
name Changed:SCH165431
X01
B
USB
2007/11/5
Compal
Charger USB Port pin name Change:SCH165431
Chatger USB U53 Enable pin name changed to "USB_POWERSHARE_PWR_EN#"
and connector to ECE5028 pin104 GPIOA7
21
33
USB
2007/11/5
Compal
Charger USB Port Switch Eye Diagram Fail:SCH165434
U54 Change to TI Part TS3USB1RSER
X01
22
33
MDC
2007/12/5
Compal
MDC DIS pin Voltage to +3.3V too Low:SCH165431
23
34
WLAN
2007/11/5
Compal
New ME Drawing Remove Latch 2
R326 pull up to +5V_ALW and connrection changed from SB to ECE5028 pin102
GPIOA5 (2007/12/5 update to pull up +5V_ALW)
Remove JLAT2
X01
X01
X01
24
34
Nimi-card
2007/11/5
Compal
Correct Nimi-Card Detect
stuff R438, R458, R449
25
35
Dock-ESD
2007/11/5
Compal
Support Dock ESD
ESD Part D65, D66 stuff
X01
26
36
USH
2007/11/5
Compal
Smartcard Detect Cancel:SCH165435
Smartcard SC_DET pin remove module port to EC
X01
27
36
USH
2007/11/5
Compal
X01
36
USH
2007/11/5
Compal
Correct Smartcard Buffer 73S8009CN Power Bead
Current Value:SCH165435
Contactless Connector Changed:SCH165435
L69 change part >400mA of Murata LQH32CN100K53L
28
JCS1 change connector to TYCO_1-1775784-0_6P-T. But still wait contactless spec to update
X01
29
37
ECE5028
2007/11/5
Compal
ECE5028 change GPIO Define:SCH165431
(1)pin102 no need of PNL_LED_MASK#, change to MDC_RST_DIS#
(3)pin70 GPIOC5 no need of ADAPT_TRIP_SET, NC
(4)updte CHIP_ID message, current set to (0,0)
A
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Changed-List History 1
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
57
of
63
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
30
38
MEC5035
2007/11/05
Compal
MEC5035 pin19 add RC_ID:SCH165437
add R211/C480
X01
31
38
MEC5035
2007/11/05
Compal
MEC5035 SUSPWROK change Define:SCH165437
SUSPWROK change from pin19 to pin30
X01
Compal
MEC5035 no need DEBUG_ENABLE#, support from
KOST_DEBUG_RX:SCH165437
(1)JDEG1 pin 2 change to HOST_DEBUG_RX, Double pull up --> remove R553.
32
38
MEC5035
2007/11/05
X01
(2)DEBUG_ENABLE# no need, remove R959
33
38
MEC5035
2007/11/05
Compal
No Need EC SPI Rom Function:SCH165439
D
(1)Remove R591, R589, R590, R592, R593, C672, U37
X01
(2)MEC5035 pin 67, 68, 69 : NC
34
38
MEC5035
2007/11/05
Compal
No Need ECE1088:SCH165440
(1)MEC5035 pin35, 37 : NC
39
35
39
38
ECE1088
2007/11/05
Compal
TouchPad Change Define:SCH165443
36
41
Screw
2007/11/05
Compal
ME Changed Screw Size
37
42
LED
2007/11/05
Compal
LED Circuit Changed:SCH165444
(1)TouchPad Connector Change pin define for pin 14/15/16 to GND/KYBD_BLJT_PWR/TP_DET#
(1)Dock: H14/H15 --> H_5P3
(2)GPU : H19 --> 4P0, H20 --> 3P9, H21 --> 3P3
(3)H23 --> 4P0
(4)H22 --> 2P2
X01
(1)Add U14 AND Gate for Base LED Mark with LID_CL#
X01
(2) Refer Page 42 for LED circuit changed
C
38
37
MEC5028
2007/11/19
Compal
ALWON oscillation on Battery only
with RTC battery:SCH165445
39
24,33,36
USH/BIO
2007/11/19
Compal
USH add Reset# to BIO Module:SCH165061
40
29
2007/11/19
Compal
Intel LOM PHY 82576LM change to B0 version:SCH165446
BIO_DET# Function Delete, add R63 pull-up for FP_RESET#. And link to USH pin C3. And
add R1002 for UPEK module
Intel LOM PHY 82576LM change to B0 version
X01
X01
LOM
Cause the ECE5028 no power, add D4/R20 to separate
X01
X01
41
10~15
NB
2007/11/19
Compal
Intel NB Cantiga change to B0:SCH165447
Intel NB Cantiga change to B0
42
21,35,51
DP
2007/11/19
Compal
DP Port Cable Detect change to "H" Detect:SCH165448
Delete R783/Q10, and net name change to DPB_HPD
Delete R795/Q114, and net name change to DPC_DOCK_HPD
X01
43
21
DP
2007/11/19
Compal
DP Port delete no use parts
Delete R895~R900, R209, R278, R336, R337, R419, R647 --> Dell want keep those parts
X01
21
DP
2007/11/19
Compal
DP Port delete function:SCH165448
DP Port delete function work, DPC_DOCK_AUX_SW/DPC_DOCK_AUX#SW add R1008/R1009 100k to GND
DP Port delete function work, DPB_AUX_SW/DPB_AUX#SW add R1006/R1007 100k to GND, but depop
U9 pin 1 R193 change to 3.48K_1%, and depop R180/R181/R896. pop R276/R336/R337
X01
45
35
DOCK
2007/11/19
Compal
Dock connect rename:SCH165449
Dock connect rename to JDOCK1
X01
46
35
DOCK
2007/11/20
Compal
Dock connect ESD Diode:SCH165449
add D65 SM24C.TCT_SOD23 ESD Diode on +DOCK_PWR_BAR
X01
47
18
Thermal
2007/11/20
Compal
No need for PWR_MON_GFX for DSC platform:SCH165450
un-stuff R1005
X01
48
20
CRT/ESD
2007/11/20
Compal
No stuff CRT ESD Diode D5, D6, D7:SCH165453
No stuff CRT ESD Diode D5, D6, D7
X01
49
55,56
GDDR
2007/11/20
Compal
50
51
GPU
2007/11/20
Compal
Compal
44
51
12,13,20
NB/GPU
51, 53
2007/11/20
Chnage to NB9P, CLK Shunt Resistors Change Value:SCH165454
R750, R824, R871, R872 change to 475ohm_1%
X01
need to add two series resistors for CA_DET:SCH165454
add R1010, R1011 0hm, un-stuff
X01
TV Function Remove from M09 Platform:SCH165454
NB: page12 U2 pinC31/E32 --> NC
X01
NB: page13 U2 pinM25 to GND, pinL28 to +1.5V_RUN after a Bead (L49)
SW: page20 U4 7B1/8B1/9B1, 7B2/8B2/9B2 --> NC and remove R669/R762/R763
GPU: page51, delete R679, C737. U56 pinAA4/Y4/AB4/AB6/AC5 NC
GPU: page53, delete DACB: C867,C868, C869, C1031,L49, and add R1012 10K pull dowm DACB at pinAC6
52
51
GPU
2007/11/20
Compal
Nvidia FAE suggest for I2C E channel pull up:SCH165454
53
51
GPU
2007/11/20
Compal
54
35
DOCK
2007/11/20
Compal
Nvidia GPU set threes different power level: 1.17V,
1.09V, 0.9V:SCH165454
DOCK pin out to support Battery Slice:SCH165449
55
30
LOM
2007/11/20
Compal
56
57
A
X01
(2)KYBD_BLJT_PWR connect to MEC5035 pin47
C
B
X01
(2)remove ECE1088: U38, C676, C677, R747, R650, R826
18
29, 33, 35
58
30
59
33
Remove termination resistors capacitors
resistors:SCH165456
and LED serial
U56 GPU pinD5/E5 I2CE_SCL/SDA add R709/R1013 10K pull up, but depop
X01
U56 GPIO5 --> GPU_VID_0
X01
GPIO6 --> GPU_VID_1
JDOCK1 pin41 add net : +NBDOCK_DC_IN_SS
X01
Remove MDI termination R384~R391, C488~C491, R395, R396, R397 move to IO Board
X01
EMC4002
2007/11/21
Compal
EMC4002, Power SW pin separate :SCH165450
Add AND Gate: U70 and C1014, R143/R144 depop
X01
LOM
2007/11/21
Compal
Intel LOM LDO for +2.65V/+2.5V:SCH165456
page29: Add LDO Q101/Q103, R959~R962, C1010~C1012
page33: IO connector pin36 change to +LOM_VCT
page35: Dock pin116/118 change to +LOM_VCT
X01
2007/11/21
Compal
X01
Compal
Change MDI bus Bead Value at L20 ~ L27 from 36nH
to 22nH:SCH165456
USB SW Vendor Suggest Change Design:SCH165434
Change MDI bus Bead Value at L20 ~ L27 from 36nH to 22nH, will improving the IEEE
2007/11/21
USB Port Two Connection Changed for Port2: SB --> Switch--> Choke -->
Connector, and Switch Chip close to SB
X01
LOM SW
USB Port 2
60
21
2007/11/21
Compal
61
53
GPU Power
DP
2007/11/21
Compal
62
53
GPU Power
2007/11/21
Compal
Proper Compoments Derating
Change from Nvidia NB8P to NB9P, remove some
parts:SCH165457
pop for NB9P on +IFPE_IOVDD/ +IFPEF_PLLVDD:SCH165457
D10 change change to B0540WS-7_SOD323-2
X01
For +IFPC_IOVDD remove Q127, R940, Q128, PJP43
X01
+IFPE_IOVDD: L70, C1000, C1001, C1004
+IFPEF_PLLVDD: L71, C1006, C1007, C1008
X01
B
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Changed-List History -2
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
58
of
63
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
63
38
MEC5035
2007/11/21
Compal
64
37
MEC5028
2007/11/21
Compal
Issue Description
Solution Description
Change Netname following Power Circuit Changed:SCH165437
D
"ACAV_IN_DOCK" to " ACAV_DOCK_SRC"
"ACAV_IN_DOCK#" to " ACAV_DOCK_SRC#"
"ACAV_IN_MB/DOCK" to " ACAV_IN"
Remove U64, C846, add U71, C1031
X01
1) Add 100k no pop pull-ups to +3.3V_ALW2 on:
- USB_SIDE_EN#
- ESATA_USB_PWR_EN#
- USB_POWERSHARE_PWR_EN#
2) No stuff R502, R923, R929.
65
37
MEC5028
2007/11/21
Compal
Change PU/PD on SYS_LED_MASK#:SCH165431
add R1014 100k PD
X01
36
USH
2007/11/21
Compal
Remove unnecessary parts on contact less:SCH165435
Remove R495, R499
X01
67
51
GPU
2007/11/21
Compal
Need to depop R855/R892 to pass HDMI spec:SCH165454
depop R855/R892
X01
69
27, 36
24, 29, 37
Crystal
2007/11/21
Compal
Y3 Y5 is not PSL parts:SCH165458
Update Y3, Y5 to PSL parts
X01
Crystal
2007/11/22
Compal
LAN_PHY_DISABLE# Change net name same with Roush:SCH165431
Change net name to LAN_DISABLE# for SB GPIO12 to PHY, and pass a 0ohm resistor
for "LAN_DISABLE#_R" to ECE5028 GPIOG0
X01
X01
70
7
CPU Quad Core
2007/11/22
Compal
Bom Separate for Avia and Maybach DSC for CPU:SCH165460
71
19
Camera VDD
2007/11/22
Compal
72
31
PCMCIA
2007/11/22
Compal
73
31
PCMCIA
2007/11/22
Compal
74
33
BIO
2007/11/22
Compal
75
35
Docking
2007/11/22
Compal
76
36
Contact Less
2007/11/22
Compal
Contact Less Connector Changed:SCH165435
JCS1 Contact Less Connector Changed to Tyco_1-1775784-0
X01
77
27
I2C Codec
2007/11/27
Compal
Reduce one components R329 for I2C Codec fixed:SCH165467
We use I2C codec, no more for SPI Audio Codec, R329 can remove
X01
78
36
USH
2007/11/27
Compal
use B0 USH BCM5880 Chip, resistors setting changed:SCH165435
R845/R844 pop, delete R847/R846
X01
79
24
SPI/ICH9
2007/11/27
Compal
no more for 2nd SPI Rom, save board space:SCH165469
delete components: R307/R308/R309/R295/R305/R304/R306/C329/U13
X01
80
7
ITP
2007/11/29
Compal
ESD suggest add 0-ohm resistors on ITP bus:SCH165507
Add R1015~R1020 on ITP BPM#0~BPM#5, and depop first. Then we need hand
soldering when we want use ITP
remove D1/R122
X01
81
13
82
37, 36
82
51, 52, 53,
54
Camera net name update:SCH165461
Change the R976~ R983, R984, R941~R946 Q129, Q14 to 1@, then Avia Bom
Stuff. MaybachDSC un-stuff
Camera net name update to "+CAMERA_VDD"
X01
Change SD Card Power Switch for PSL:SCH165463
U28 chnage to TI TPS2051BDBVR_SOT23-5
X01
JSD1 connector changed from FPC type to Cable type:SCH165464
JSD1 change to 16pin cable type connector, same with touchpad connector
X01
BIO connector change to another part:SCH165464
JBIO1 change to "TYCO_1734242-6_6P-T"
X01
Docking Connector Change Layout Symbol:SCH165449
JDOCK1 change to JAE_WD2F144WB1
X01
NB
2007/12/03
Intel
USH
2007/12/04
Broadcom
Broadcom Review Result
SCH165564, Intel provide remove D1/R122
Graphic
2007/12/04
Nvidia
Nvidia Review result
(1)
(4)
(6)
(7)
(8)
(4) R699, R700, C755 no stuff
B
(2) PEX_IOVDD add C1034
C
X01
R788 SP_TPM_LPC_EN pull up pop
(2) R490 depop
(3) C591 depop
remove R472 resistor 10ohm
(5) pop R829, depop R467 for B0 version
depop R849, due to Broadcom no need detect SC_DET
R476 Change to 5.1M, R488 change to 3.3M to reduce power consumption
depop C594
(9) add R1027 47K pull down
(1) PEX_IOVDDQ add C1035 1uF
D
X01
66
68
C
DF174483: [SSI2]The LCD/LED will keep had power
with USB device when unplug AC & Battery.
Rev.
X01
X01
(3) remove C778
(5) FBVDDQ C820 to 1u and add one C1036 (1u)
(6) +FBVDDQ all 0.022u to 4700p, done
(7) +FB_DLLAVDD add C1033 4.7u
(8) +GPU_PLLVDD
(9) +GPU_PLLVDD
C850 change to 0.1u
B
add C1037 4.7u
(10) strap pin define change,
STRAP0: Not stuff R933; Stuff R920 with 45.3K 1%.
STRAP1: Not Stuff R921; Stuff R934 with 10K 1%
STRAP2: NB9M-NS : Not stuff R935, Stuff R922 with 20K 1%
STRAP2: NB9P-GLM2 : Not stuff R935, Stuff R922 with 25K 1%
ROM_CLK_GPU: NB9M-NS : Not stuff R923, stuff R936 with 15K 1%
ROM_SI_GPU:
Qimonda 16Mx32 : Not stuff R931, Stuff R927 with 10K 1%.
Hynix 16Mx32
: Not stuff R931, Stuff R927 with 15K 1%
Samsung 16Mx32 : Not stuff R931, stuff R927 with 20K 1%
Qimonda 32Mx32 : Not stuff R931, Stuff R927 with 30K 1%.
Hynix 32Mx32
: Not stuff R931, Stuff R927 with 35K 1%
Samsung 32Mx32 : Not stuff R931, stuff R927 with 45.3K 1%
ROM_SO_GPU: Not stuff R928, Stuff R930 with 4.99K 1%
(11) Add R1022 40.2K 1% on STRAP_REF_MIOB
(13) C982 Remove
(12) Add R1023 40.2K 1% on STRAP_REF_3V3.
(14)Add pull down resiter on MIOA_CAL_PU_GND R1026 and not stuff
(15)Add 10K pull down on MIOB_CLKIN R1021
(16) I2CE_SCL/SDA:
(17) I2CS_SCL/SDA:
A
Change R709 and R1013 to pull up +3.3V_RUN
Add 10K pull up on I2CS_SCL.
A
(18) R696 pop
82
28
Audio
2007/12/05
IDT
IDT Audio Reference changed
X01
R818. R827 change to 1K_0402
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History-3
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
Sheet
1
59
of
63
2
1
Version Change List ( P. I. R. List )
Item Page#
83
32
Title
CardBus/Express
Date
2007/12/6
Request
Owner
Ricoh
Issue Description
Solution Description
Ricoh review result
Rev.
X01
(1) CBS_CCD1#/CBS_CCD2# add C1038/C1039 270pF pull down
(2) U52 +1.5V_CARD add C1041, +3.3V_CARDAUX ADD C1040 10uF_0805
(3) R657, R684, R790 depop, because chip internal have been pull up
84
85
B
86
87
88
A
24
LOM
2007/12/10
Intel
2007/12/10
Dell
SB/VGA
2007/12/10
Codec
37, 38
23, 51
27
18,21,37,38
EC
EMC4002 , DP
5028, 5035, LED
DP
Per Intel message, no use GPIO12 to control
LAN_DISABLE#, then reserve to pull up
add R1028 pull up +3.3V_ALW_ICH, depop
X01
INSTANT_ON_SW# design change (WI165505)
INSTANT_ON_SW# change design to add R1029, R1030, R1031,
then depop R560, D4, C827, R20
X01
Compal
HDMI Over Audio source changed, because it will imapct S3
resume. HDMI source change from SPDIF
Depop R673, R674, R675, R676, R678, R243, R244, R245, R246.
X01
2007/12/12
Compal
IDT codec review result to change C408 ~ C411
Value from 1uF to 2.2uF
X01
2007/12/13
Compal
The VCC tied to logic gate VCC isnt correct.
Change U70,U66,U71,U62,U14 from 74AHCT to 74AHC part. (VCC pin spec = 3.3V)
X01
89
35
2007/12/17
Dell
SCH166257: DOCK_DET# add pull 100K
add R1033 100K, and depop R124
X02
90
38
DOCK/5035
2007/12/17
Dell
TASK166259: update GPIO Map
signal ACAV_DOCK_SRC# can be removed from the 5035
X02
91
29
LOM PHY
2007/12/17
Dell
De-pop R1004
X02
92
42
LED
2007/12/17
Compal
SCH166263: De-pop R1004 for control LAN PHY enable from
BIOS setting
SCH165444: add D66 for +5V_RUN back drive issues
add D66 between Q151 and Q97
X02
93
18
+2.5V LDO
2007/12/17
Compal
SCH166267: Disable EMC4002 LDO for +2.5V_RUN
add R1034 10K pull low, and de-pop R149, C238, C239
X02
94
19
DP
2007/12/17
Compal
SCH166272: De-populate D10 with a 0ohm Resistor
95
42
LED
2007/12/17
DELL
SCH166275:Mask signals for NUM/SCRL/CAPS LEDs
D10 footprinter can't stuff for 0805 or 1210, reserve a 1210 resistor
footprint first: R1035
Add Q154/R1036 to control NUM/SCRL/CAPS LED on/off, R1036 de-pop
X02
96
33, 38
97
6, 8, 24
98
USB
X02
2007/12/17
DELL
SCH166278:Update cell charger detect circuit
add D67/D68 R1037, del R986, update C1021 to 1uF
X02
CLOKC, CPU, ICH
2007/12/17
DELL
SCH166282: intel NOA tets points comliance
add R1038~R1042 on PT2
X02
33
eSATA
2007/12/17
Compal
SCH166284:eSATA add Repeater Chip
X02
99
37
5035
2007/12/17
Compal
SCH166316:PT2 change to X02 BID
eSATA repeater for ICH to eSATA trace over 5inch issues, addU72, C1042~C1045,
R1043~R1048, Q155 . U72 change to PI2EQX3201BZFE
PT2 change the BID for X02: R530, R534 pop. R535, R529 de-pop
100
35
Dock
2007/12/21
Compal
SCH166435 : Hot Docking then Docking side Apdater Protect
add D70 and R1057 on docking connector, and add C1055, R1059.
MEC5035 pin41 change to "DOCK_POR_RST#" to dock pin140
X02
101
9
CPU Bulk Caps
2008/2/4
Power
SCH166160 : CPU Bulk change to 270u_4.5mohm to support QC CPU
C56~C61 change to 270U_D_2VM_R4.5M~D, C58, C61 depop
X03
102
21
DP
2008/2/13
Dell
SCH168227 : DP Circuit Separate to Two Path for DP and DVI
Add C1056, C1057, R1060~R1063, Q155, Q156, U73, U74
X03
103
24, 36
SB (TPM), USH
2008/2/13
Dell
SCH168228 : Disable TPM Strape pin on SB GPIO6
Add R304 (3@) pull low when disable TPM Strap, and depop R273. And USH Depop
D71, R1058 (4@) Pop R489 (3@)
X03
104
27
Audio
2008/2/13
IDT
Depop R328, and R327/R828 change to 499K
X03
105
35
Dock
2008/2/13
Power
SCH168229 : Reduce distortion, hissing, noise, and “pops”
when changing PC BEEP volume
SCH168230 : Prevent System as Docking Always
Depop R1057
X03
106
13
NB
2008/2/13
Compal
SCH168231 : Debug +3.3V_Run backdrive issues
Reserve R1065 and stuff
X03
107
37
ECE5028
2008/2/13
Power
SCH168232 : Power Battery Slice Issues
Add D72/R1067, and reserve R1066
X03
108
33
eSATA
2008/2/13
Pericom
R1068~R1069 pop, and R1070~R1073 depop. And pop R1046 470ohm for SATA Eye
X03
109
36
USH
2008/2/13
Dell
SCH168233 : Vendor Suggest Reserve Some Resistors on ESATA
Repeater Chip
SCH168234 : USH USB Signals Damping Resistor Value
R468/ R469 change to 0ohm
X03
110
33
USB Switch
2008/2/13
Dell
SCH168235 : USB Switch Add Resistore Reserve
Add R1074, R1075, depop
X03
111
42
LED
2008/2/13
Compal
SCH168236 : Follow Roush Test Result for LED Current Spec
Change to 1K: R663, R125, R661, R1000, R668, R659, R556, R596, R655, R903, R665
Change to 82ohm: R997
X03
112
18
EMC4002
2008/2/13
SMSC
Proper ESATA Power Consumption on EMC4002
R152
X03
113
6
Clock
2008/2/13
Dell
SCH168237 : For
+3.3V LDO
SCH168238 : For
Proper Ferrite Bead Power Rating
L1 change to BK2125HS601 500mA
114
36
USH
2008/2/13
Broadcom
SCH168239 : For
USH Support Low Power
Pop R849
X03
115
10
NB
2008/2/13
Intel
SCH168045 : Reserve for Intel Debug
add R1088, Depop
X03
116
37
ECE5028
2008/2/13
Compal
SCH168043 : X03 Board ID Updated
Pop R529 and Depop R534
X03
117
27
Audio
2008/2/15
ADI
SCH168240 : ADI Suggest
(1) L18 change to BLM18EG601SN1D for wider high frequency coverage
(2) U15 pin 12/18 combine together and add L72(BLM18EG601SN1D)
(3) C391, C395, C406 change to 4.7uF_0603 (IDT suggest 10uF_0805
better, but the package is too big)
(4)C392 remove
X03
118
27 36
Audio USH
2008/2/15 IDT Broadcom
119
24 36
SB USH
2008/2/15
Compal
http://hobi-elektronika.net
2
Chip Version changed
TPM Disable to Common Resistors
Location with UMA, R1064 --> R304,
R483 --> R489
B
X02
Change to 0.82_1210
A
X03
(1) U32 USH change to C0 version
(2) U16 IDT Audio change to 92HD71B7A5NLGXB3X8_QFN48
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Changed-List History 4
Size
Document Number
Date:
Thursday, June 05, 2008
Rev
1.0
LA-4051P
1
Sheet
60
of
63
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
120
7
ITP
2008/2/18
Intel
Change Some ITP Resistors Value
ITP Resistors: R67 --> 27, R64 --> 39 , R66 -> 649, R65 --> 150, R57 --> 124
X03
121
33
eSATA
2008/2/18
Compal
SCH168046: Follow eSATA EA Result, Add the Parallel Resistor
R1046 pop 470ohm
X03
(1) ADI SSM2602 add AGND net, include Audio Codec 92HD71
(2) Audio Precision spec for SNR and THD+N update, then C436/C437 change to 10uF
X03
(1) R1060 / R1061 / R1062 / R1063 change to 10K
(2) R897/R336/R898/R337/R1008/R1009 Depopulate
(3) R193 to 5.11K
(4) R1001 change to 1M
X03
(1)
(2)
(3)
(4)
(5)
(6)
X03
122
27, 28
Audio
2008/2/20
ADI/Dell
123
21
DP
2008/2/20
Dell
SCH168466 : ADI Suggest to Update Separate AGND and Audio
Precision Spec Update
SCH168467 : More DP Components Changed
124
27
Codec
2008/2/22
ADI/Dell
SCH168468 : update codec circuit for noise problem
B
C401, change to 0.1uF
add C124,C329,R308,R309,C392,C481
delete C397
C408/C409 change to 0.22uF
C410/C411 change to 0.068uF
R340/R342 change to 100 ohm
B
125
36
USH5880
2008/2/22
Compal
SCH168469 : add PI circuit for EMI issue
Add L73/L74/C1059/C1058
126
18
EMC4002
2008/2/25
Compal
SCH168531 : chnge R153 value to meet the formula of Ra
R153 change to 3.16K
X03
X03
127
33
USB2.0
2008/2/29
Compal
SCH168774 : To pop U51 per ESD testing result
pop U51
X03
128
23,29,36
ICH,USH,LAN
2008/2/29
Compal
SCH168777 : X'tal EA result to change some Caps value
C296/C297 from 15pF to 10pF;C475/C476 from 27pF to 12pF;C609/C608 from 22pF to 12pF
X03
129
8
CPU
2008/3/3
Dell
SCH168828 : QC BU issue
Pin AA7 of the CPU has to be NC and we connect it to +VCC_CORE
X03
130
27
Codec
2008/3/3
SCH168836 : Follow Roush to add R1091/R1092 for Audio noise
add R1091/R1092 (100 ohm)
X03
131
39
TP/KB/LID
2008/3/3
SCH168838 : M09 S3 backdrive issue
Touch pad vendor use 5VALW for SMBUS,to add R1093,Ro1094, and depop R594/R595
X03
132
23
ICH
2008/3/3
Compal
SCH168843 : 24MHz noise issue (EMI feedback)
pop C300,C302,C309
X03
133
7
CPU
2008/4/28
Compal
SCH170946 : change R944 from 2K to 1.74K
R944 from 2K to 1.74K
X04
134
7
CPU
2008/4/28
Compal
POP R785 to support Quad Core circuit
POP R785 (51 ohm)
X04
135
10
MCH
2008/4/28
Compal
SCH170947 : R82 & R95 value for Quad core , Dual Core
R82 for Avia is 16.9 ohm ; R82 for DSC is 24.9 ohm
136
21,51
GPU,DP
2008/4/28
Compal
SCH170948 : ESD requirement
C984 & C983 from 0.1uF to 0.033uF
X04
137
24
ICH
2008/4/28
Compal
SCH170949 : Depop 2nd SPI ROM
Depop R329,R1044,R377,U13,R375,C484,R380,R381,R382
X04
138
27
Codec
2008/4/28
Compal
SCH170950 : DMIC_CLK EMI issue
We pop C485 and change R338 to L75(POP)
X04
139
27
Codec
2008/4/28
Compal
SCH170952 : Bypass double inverter of DAI_DI
140
35
eDOCK
2008/4/28
Compal
SCH170955 : Follow Roush to add R1095, R1096
follow Roush to bypass U18,U19. so we depop U18,U19,C418,C419, and add R762(0 ohm)
to bypass it.
add R1095,R1096
X04
141
37
ECE5028
2008/4/28
Compal
SCH170956 : change BID
depop R529, add R534 ;
X04
142
40
PWR CTRL
2008/4/28
Compal
SCH170957 : add discharge circuit
143
18
EMC4002
2008/5/7
Compal
144
42
LED
2008/5/7
145
23
ICH
146
40
147
37
148
7,18
CPU,EMC4002
2008/5/29
149
7,37
CPU,ECE5028
2008/5/29
150
24,38
ICH,MEC5035
151
29
Compal/IDT
Dell
X04
R95 for Avia is 75 ohm ; R95 for DSC is 100 ohm
A
depop R530, add R535 ; add R531, depop R536
add R625(39 ohm), Q79
X04
SCH171232 : FAN speed couldnt be detected issue
add D38
X04
Compal
SCH171235 : SNIFFER LED only support blue color led
depop Q100,R667
X04
2008/5/8
Compal
SCH171330 : WLAN detection issue
Follow Roush to add R84,R96 PD 10K ohm
X04
PWR CTRL
2008/5/27
Compal
SCH172015 : Follow Roush to change C688 value
From 4700pF to 3300pF
A00
ECE5028
2008/5/27
Compal
SCH172018 : BID to A00(1.0)
pop R529, depop R534
A00
SCH172109 : to disconnect the Quad Core 2nd thermal sensor
delete the traces, H_THERMDA1 / H_THERMDC1, and delete C227, C228
A00
Compal
SCH172115 : to modify the Quad Core detect circuit
(1)
(2)
(3)
(4)
2008/6/2
DELL
SCH172198 : re-route ODD_DET#
add a connection to MEC5035 pin34 also.
A00
2008/6/6
DELL
SCH172398 : LOM IEEE test result from Intel
C475 & C476 from 12PF to 27PF to pass LOM IEEE test
A00
A00
82567LM
Intel/DELL
of 3.3VRUN
X04
disconnect ECE5028 pin3, pin4. make it NC.
delete R941, and CPU pin F8 connect to R945 pin2, the net name is QUAD_REF_CTRL
R945 change to 10K, and R945 pin 1 change PU to +1.05V_VCCP
R943 pin 1 change PU to +3.3V_RUN
152
42
LED
2008/6/6
Compal
SCH172400 : Breath LED current issue
R997 from 82 ohm to 100 ohm for current limited
153
24
ICH
2008/6/6
Compal
SCH172402 : SAWTOOTH waveform on SERIRQ issue
Add R122(33 ohm)
154
36
USH5880
2008/6/13
BRCM
BRCM feedback for PI circuit
C1058/C1059 from 5% to 1% ;
A00
A
A00
C641/C647 from 5% to 1%
A00
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
2
Changed-List History 4
Size
Document Number
Date:
Friday, June 13, 2008
Rev
1.0
LA-4051P
1
Sheet
61
of
63
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
1
43
Title
Date
+DC_IN
11/24
43
43
48
leverage
Roush
DCIN_CBL_DET# damage ECE5028
Add ESD diedo PD17 DA204U_SOT323 at DCIN_CBL_DET#
Series PR221 1K_0402_5% between PJPDC1, PIN1 and DCIN_CBL_DET#
Parallel PC254 0.47uF_0402_6.3V on DCIN_CBL_DET#
Roush component and rework changes
for Dcoking test
PC4 change form 0.47uF_0805_25V to 0.1uF_0805_25V
PR14 change form 240K_0402_5% to 1M_0402_5%
PR17 change form 47K_0402_1% to 220K_0402_5%
PR18 change form 47K_0402_1% to 22K_0402_5%
PR342 change form 0_0402_1% to 100K_0402_5%
NB DC blocking MOSFET won't turn off
when Dock AC insert.
Add PQ44 RHU002N06 control NB DC blocking MOSFET.
Control singal is NB_AC_OFF
Series PR284 200K_0402_1% between PQ44 PIN1 and ACAV_IN
Add PD30 B540C parallel PQ34
leverage
Roush
Charger of ISL88731 will turn off
When ACIN is no power
Add LM393 to replace ISL88731 ACOK function(PU11B)
leverage
Roush
+PWR_SRC exist on Docking connector
through the DOCK_DCIN_IS+ and -
Add PQ70 NTGD4161PT1G series DOCK_DCIN_IS+ and Add PQ71 RHU002N06 to control PQ70 on/off
leverage
Roush
A global signal name change
for all notebooks
From "ACAV_IN_DOCK" to "ACAV_DOCK_SRC"
From "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#"
11/24
leverage
Roush
SCH165050: Validate EMC4002 VIN1/VCP1/VCP2
for UMA & Discrete for PT1 SMT
Depop UL circuit.
11/24
leverage
Roush
PBATT DC blocking MOSFET won't turn off
when Docking AC insert.
It will cause Battery or adapter protect.
Add PD18 RB715F_SOT323, PD20 and PD19 RB751V_SOD323, PR329 100K_0402_5%
PR328 and PR327 47K_0402_5%, PR326 and PR325 240K_0402_5%
PQ75 2N7002DW-7-F_SOT363-6, PQ72 NTG6161PT1G_TSOP6
Extra net name add +NBDOCK_DC_IN_SS from Docking connector
+DC_IN
+DC_IN
48
Charger
11/24
C
6
48
49
Charger
Selector
7
48
49
Charger
Selector
8
48
Charger
9
49
leverage
Roush
Charger
11/24
5
Selector
Rev.
Add PQ69 NTR4502PT1G, and PD32 RB751_SOD323
Connect to DOCK_SMB_ALERT# and SLICE_BAT_PRES#
11/24
4
Solution Description
Battery slice need detect
NB battery is insert or not.
11/24
3
Issue Description
leverage
Roush
D
2
Request
Owner
11/24
11/24
leverage
Roush
D
C
B
B
10
43
+DCIN
11
52
Graphic
12
48
49
Selector
charger
13
47
Vcore
11/24
EE /
SCH165224
follow HW change
To delete the RTC detection circuit
11/24
Compal
support Maybach DIS and AVIA
Add PR308 and PR309 to switch 1 phase or 2 phase.
11/30
Dell
12/17
Intersil
for slice function implement
change charger output to FB pin15 net name from PBATT+ to +VCHGR
Add PQ41 PQ70 PR351 PR352 PR353 between +VCHGR and PBATT+
transent to meet Intel IMVP6+
change PR116 from 1.69K to 1.18K,PC111 from 680p to 1000pF,
PR113 from 332 to 232,PR121 from 82.5K to 162k,
PC117 from 1500p to 680pF,PC120 from 220p to 180pF,
PR122 from 14.7K to 12.1K,PR107 from 11.5K to 20k,
PR130 from 1K to 2k,PC116 from 0.033u to 0.047u,
PC112 from 0.033u to 0.01uF
A
14
47
Vcore
12/17
Maxim
fix voltage too low when no load
A
change PR78,PR100,PR120 from 2K to 430 ohm
Change PC89,PC103,PC119 from 0.22u to 1uF
Title
<Title>
http://hobi-elektronika.net
5
Size
C
Date:
4
3
2
Document Number
<Doc>
Rev
1.0
Sheet
Thursday, June 05, 2008
1
62
of
63
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
15
43
Title
+DCIN
Date
12/17
Request
Owner
Dell
D
16
49
selector
17
49
Selector
18
47
+Vcore
12/24
02/19
02/19
Dell
Merle
DELL
A
Solution Description
change DCIN connector for ESD issue of
"DCIN_CBL_DET#"
AC adaptor crowbar when docking
Fix BITS CR196131 and CR196130
Dell /
Maxim
Reduce Ring-backwithin 20mV when change
bulk caps from 4*220uF to 3*270uF
(Maybach DIS)
D
Add PR354 330K ohm
Add PR355: 0 ohm
Add PQ77 RHU002N06
Add PR363 1K_1206 and PC262 1U_0603_25V from +NBDOCK_DC_IN_SS to ground
Add PD35 RB751S40T1_SOD523-2 from NB_AC_OFF# to ACAV_IN_NB
PR129 change from
909 ohm to 825 ohm
change PR123 to 10_ohm
change PC122 to PR320 10_ohm
47
+Vcore
02/19
Maxim
Fix Jitter issue
20
50
Graphic
02/19
Maxim
MAX17007 cold boot issue back up circuit
if IC versin change can not catch ST
schedule
Add PQ73 RHU002N06
Add PR296
Delete non-use circuit
delete +DC_IN_SS to PR217 and PR217.
C
21
48
Charger
03/06
Compal
22
49
Selector
03/06
Compal
23
47
+Vcore
03/11
Maxim
For driver IC power down issue
Add PR321 PR322 PR323 from IC pin 2 to GND
24
50
Graphic
03/18
Compal
hardware delete NET
delete NET 1.1V_RUN_ON
delete PR305
25
50
Graphic
4/23
EMI soultion
change PR168 to 2.2ohm
26
50
Graphic
4/23
Compal
4/23
Maxim
27
50
Graphic
28
47
Vcore
29
48
Charger
30
50
Graphic PWR
31
43
DC-IN
32
49
33
48
Charger
5/21
34
50
Graphic PWR
6/10
Selector
Compal
Change PQ40 from IMD2AT to 2N7002DW
change PR202 from240K_ohm ot 620k_ohm
change PR204 from 47K_ohm to 33_ohm
add PR222 390K_ohm and PR223 390K_ohm
add PD34 RB751S40T1
For slice battery hot docking issue
hardware change control mode
MAX17007 version change
un-pop PQ73 RHU002N06
un-pop PR296
JAL21 Driver IC power down issue
need change resistor value
change PR321 PR322 PR323 to 33K
5/23
Dell
For Dell M09 platform
Change PR135 to 24K PC256 to 100p
5/23
Nvidia
support GLM3
PR288 change to 7.15K, PR290 change to 10K, PR289 change to 13.7K
6/3
6/4
Compal
Glitch issue on SLICE_BAT_PRES#
Compal
Reserve a pull high resistor between
+3.3V_ALW2 and SLICE_BAT_PRES#
Merle
DELL
Compal
Add PC257:SE074152K8L(S CER CAP 1500P 50V +-10% X7R 0402)
between pin2 of PQ69 and GND.
Reduce delay time between NB adapter removal
and ACAV_IN_NB de-assert from 1.6mS to~400uS.
change PL18 to PSL
B
un-pop PR310 pop PR312 (un-pop PR311 pop PR313 for JAL21)
Maxim
4/23
Rev.
from Molex_87437_0663 to MOLEX_87437-0763
19
C
B
Issue Description
Add un-pop PR330:SD02847018L(S RES 1/16W 4.7K +-5% 0402)
between +3.3V_ALW2 and PQ40B.5.
change PC256 from .1uF to 100pF.
change PR135 from 100K to 24K.
A
change PL18 from SM01001821L (Tai tech) to SM01002078L (KC)
Title
<Title>
http://hobi-elektronika.net
5
Size
C
Date:
4
3
2
Document Number
<Doc>
Rev
0.4
Sheet
Friday, June 13, 2008
1
63
of
63
</pre><hr>Source Exif Data: <br /><pre>File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.5
Linearized : No
Encryption : Standard V5.5 (256-bit)
Warning : Incomplete Encrypt specification
</pre>
<small>EXIF Metadata provided by <a href="https://exif.tools/">EXIF.tools</a></small>
<div id="ezoic-pub-ad-placeholder-110">
<script async src="//pagead2.googlesyndication.com/pagead/js/adsbygoogle.js"></script>
<!-- usermanual link ad -->
<ins class="adsbygoogle"
style="display:block"
data-ad-client="ca-pub-0545639743190253"
data-ad-slot="6172135303"
data-ad-format="link"></ins>
<script>
(adsbygoogle = window.adsbygoogle || []).push({});
</script>
</div>
</div>
<div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> <div class="visualClear"></div>
</div>
</div>
<div id="mw-navigation">
<h2>Navigation menu</h2>
<div id="mw-head">
<div id="p-personal" role="navigation" class="" aria-labelledby="p-personal-label">
<!-- <div id="p-search" role="search">
<form action="https://usermanual.wiki/search.php" id="searchform">
<div id="simpleSearch">
<input type="search" name="search" placeholder="Search UserManual.wiki" title="Search UserManual.wiki [ctrl-option-f]" accesskey="f" id="searchInput" tabindex="1" autocomplete="off"><input type="hidden" value="Special:Search" name="title"><input type="submit" name="go" value="Go" title="Find a User Manual" id="searchButton" class="searchButton"> </div>
</form>
</div>-->
<ul>
<li id="pt-mycontris"><a href="https://usermanual.wiki/upload" title="Upload User Manual" accesskey="y">Upload a User Manual</a></li>
</ul>
</div>
<div id="left-navigation">
<div id="p-namespaces" role="navigation" class="vectorTabs" aria-labelledby="p-namespaces-label">
<h3 id="p-namespaces-label">Versions of this User Manual:</h3>
<ul>
<li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Document/LA4051P.1870654589" title="User Manual Wiki" accesskey="c">Wiki Guide</a></span></li> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Document/LA4051P.1870654589/html" title="HTML" accesskey="c">HTML</a></span></li> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Document/LA4051P.1870654589/amp" title="Mobile AMP" accesskey="c">Mobile</a></span></li> <li id="ca-nstab-main" class="selected" ><span><a href="https://usermanual.wiki/Document/LA4051P.1870654589/help" title="Discussion / FAQ / Help" accesskey="c">Download & Help</a></span></li>
</ul>
</div>
</div>
<div id="right-navigation">
<div id="p-views" role="navigation" class="vectorTabs" aria-labelledby="p-views-label">
<h3 id="p-views-label">Views</h3>
<ul>
<li id="ca-view"><span><a href="#">User Manual</a></span></li>
<li class="selected" id="ca-edit"><span><a href="https://usermanual.wiki/Document/LA4051P.1870654589/help" title="Ask a question" accesskey="e">Discussion / Help</a></span></li>
</ul>
</div>
</div>
</div>
<div id="mw-panel">
<div id="p-logo" role="banner"><a class="mw-wiki-logo" href="https://usermanual.wiki/Main_Page" title="Visit the main page"></a></div>
<div class="portal" role="navigation" id="p-navigation" aria-labelledby="p-navigation-label">
<h3 id="p-navigation-label">Navigation</h3>
</div>
<div class="portal" role="navigation" id="p-tb" aria-labelledby="p-tb-label">
</div>
</div>
</div>
<div id="footer" role="contentinfo">
<ul id="footer-info">
<li id="footer-info-lastmod">© 2026 UserManual.wiki</li>
</ul>
<ul id="footer-places">
<li id="footer-places-privacy"><a href="https://usermanual.wiki/ContactUs" title="UserManual.wiki:Contact Us">Contact Us</a></li>
<li id="footer-places-about"><a href="https://usermanual.wiki/DMCA" title="UserManual.wiki:DMCA">DMCA</a></li>
</ul>
<ul id="footer-icons" class="noprint">
<li id="footer-poweredbyico">
</li>
</ul>
</div>
</div></body></html>
<script src="/cdn-cgi/scripts/7d0fa10a/cloudflare-static/rocket-loader.min.js" data-cf-settings="a890a2062f5e5d61528e03b1-|49" defer></script>