UM10462 LPC11U3x/2x/1x User Manual LPC11U3X
User Manual:
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- Chapter 1: LPC11U3x/2x/1x Introductory information
- Chapter 2: LPC11U3x/2x/1x Memory mapping
- Chapter 3: LPC11U3x/2x/1x System control block
- 3.1 How to read this chapter
- 3.2 Introduction
- 3.3 Pin description
- 3.4 Clocking and power control
- 3.5 Register description
- 3.5.1 System memory remap register
- 3.5.2 Peripheral reset control register
- 3.5.3 System PLL control register
- 3.5.4 System PLL status register
- 3.5.5 USB PLL control register
- 3.5.6 USB PLL status register
- 3.5.7 System oscillator control register
- 3.5.8 Watchdog oscillator control register
- 3.5.9 Internal resonant crystal control register
- 3.5.10 System reset status register
- 3.5.11 System PLL clock source select register
- 3.5.12 System PLL clock source update register
- 3.5.13 USB PLL clock source select register
- 3.5.14 USB PLL clock source update enable register
- 3.5.15 Main clock source select register
- 3.5.16 Main clock source update enable register
- 3.5.17 System clock divider register
- 3.5.18 System clock control register
- 3.5.19 SSP0 clock divider register
- 3.5.20 USART clock divider register
- 3.5.21 SSP1 clock divider register
- 3.5.22 USB clock source select register
- 3.5.23 USB clock source update enable register
- 3.5.24 USB clock divider register
- 3.5.25 CLKOUT clock source select register
- 3.5.26 CLKOUT clock source update enable register
- 3.5.27 CLKOUT clock divider register
- 3.5.28 POR captured PIO status register 0
- 3.5.29 POR captured PIO status register 1
- 3.5.30 BOD control register
- 3.5.31 System tick counter calibration register
- 3.5.32 IRQ latency register
- 3.5.33 NMI source selection register
- 3.5.34 Pin interrupt select registers
- 3.5.35 USB clock control register
- 3.5.36 USB clock status register
- 3.5.37 Interrupt wake-up enable register 0
- 3.5.38 Interrupt wake-up enable register 1
- 3.5.39 Deep-sleep mode configuration register
- 3.5.40 Wake-up configuration register
- 3.5.41 Power configuration register
- 3.5.42 Device ID register
- 3.5.43 Flash memory access
- 3.6 Reset
- 3.7 Start-up behavior
- 3.8 Brown-out detection
- 3.9 Power management
- 3.10 System PLL/USB PLL functional description
- Post divider
- Feedback divider
- Changing the divider values
- Chapter 4: LPC11U3x/2x/1x Power Management Unit (PMU)
- Chapter 5: LPC11U3x/2x/1x Power profiles
- 5.1 How to read this chapter
- 5.2 Features
- 5.3 Basic configuration
- 5.4 General description
- 5.5 Definitions
- 5.6 Clocking routine
- 5.6.1 set_pll
- 5.6.1.1 Param0: system PLL input frequency and Param1: expected system clock
- 5.6.1.2 Param2: mode
- 5.6.1.3 Param3: system PLL lock time-out
- 5.6.1.4 Code examples
- 5.6.1.4.1 Invalid frequency (device maximum clock rate exceeded)
- 5.6.1.4.2 Invalid frequency selection (system clock divider restrictions)
- 5.6.1.4.3 Exact solution cannot be found (PLL)
- 5.6.1.4.4 System clock less than or equal to the expected value
- 5.6.1.4.5 System clock greater than or equal to the expected value
- 5.6.1.4.6 System clock approximately equal to the expected value
- 5.6.1 set_pll
- 5.7 Power routine
- Chapter 6: LPC11U3x/2x/1x NVIC
- 6.1 How to read this chapter
- 6.2 Introduction
- 6.3 Features
- 6.4 Interrupt sources
- 6.5 Register description
- 6.5.1 Interrupt Set Enable Register 0 register
- 6.5.2 Interrupt clear enable register 0
- 6.5.3 Interrupt Set Pending Register 0 register
- 6.5.4 Interrupt Clear Pending Register 0 register
- 6.5.5 Interrupt Active Bit Register 0
- 6.5.6 Interrupt Priority Register 0
- 6.5.7 Interrupt Priority Register 1
- 6.5.8 Interrupt Priority Register 2
- 6.5.9 Interrupt Priority Register 3
- 6.5.10 Interrupt Priority Register 4
- 6.5.11 Interrupt Priority Register 5
- 6.5.12 Interrupt Priority Register 6
- 6.5.13 Interrupt Priority Register 7
- Chapter 7: LPC11U3x/2x/1x I/O configuration
- 7.1 How to read this chapter
- 7.2 Introduction
- 7.3 General description
- 7.4 Register description
- 7.4.1 I/O configuration registers
- 7.4.1.1 RESET_PIO0_0 register
- 7.4.1.2 PIO0_1 register
- 7.4.1.3 PIO0_2 register
- 7.4.1.4 PIO0_3 register
- 7.4.1.5 PIO0_4 register
- 7.4.1.6 PIO0_5 register
- 7.4.1.7 PIO0_6 register
- 7.4.1.8 PIO0_7 register
- 7.4.1.9 PIO0_8 register
- 7.4.1.10 PIO0_9 register
- 7.4.1.11 SWCLK_PIO0_10 register
- 7.4.1.12 TDI_PIO0_11 register
- 7.4.1.13 TMS_PIO0_12 register
- 7.4.1.14 PIO0_13 register
- 7.4.1.15 TRST_PIO0_14 register
- 7.4.1.16 SWDIO_PIO0_15 register
- 7.4.1.17 PIO0_16 register
- 7.4.1.18 PIO0_17 register
- 7.4.1.19 PIO0_18 register
- 7.4.1.20 PIO0_19 register
- 7.4.1.21 PIO0_20 register
- 7.4.1.22 PIO0_21 register
- 7.4.1.23 PIO0_22 register
- 7.4.1.24 PIO0_23 register
- 7.4.1.25 PIO1_0 register
- 7.4.1.26 PIO1_1 register
- 7.4.1.27 PIO1_2 register
- 7.4.1.28 PIO1_3 register
- 7.4.1.29 PIO1_4 register
- 7.4.1.30 PIO1_5 register
- 7.4.1.31 PIO1_6 register
- 7.4.1.32 PIO1_7 register
- 7.4.1.33 PIO1_8 register
- 7.4.1.34 PIO1_9 register
- 7.4.1.35 PIO1_10 register
- 7.4.1.36 PIO1_11 register
- 7.4.1.37 PIO1_12 register
- 7.4.1.38 PIO1_13 register
- 7.4.1.39 PIO1_14 register
- 7.4.1.40 PIO1_15 register
- 7.4.1.41 PIO1_16 register
- 7.4.1.42 PIO1_17 register
- 7.4.1.43 PIO1_18 register
- 7.4.1.44 PIO1_19 register
- 7.4.1.45 PIO1_20 register
- 7.4.1.46 PIO1_21 register
- 7.4.1.47 PIO1_22 register
- 7.4.1.48 PIO1_23 register
- 7.4.1.49 PIO1_24 register
- 7.4.1.50 PIO1_25 register
- 7.4.1.51 PIO1_26 register
- 7.4.1.52 PIO1_27 register
- 7.4.1.53 PIO1_28 register
- 7.4.1.54 PIO1_29 register
- 7.4.1.55 PIO1_31 register
- 7.4.1 I/O configuration registers
- Chapter 8: LPC11U3x/2x/1x Pin configuration
- Chapter 9: LPC11U3x/2x/1x GPIO
- 9.1 How to read this chapter
- 9.2 Basic configuration
- 9.3 Features
- 9.4 Introduction
- 9.5 Register description
- 9.5.1 GPIO pin interrupts register description
- 9.5.1.1 Pin interrupt mode register
- 9.5.1.2 Pin interrupt level (rising edge) interrupt enable register
- 9.5.1.3 Pin interrupt level (rising edge) interrupt set register
- 9.5.1.4 Pin interrupt level (rising edge interrupt) clear register
- 9.5.1.5 Pin interrupt active level (falling edge) interrupt enable register
- 9.5.1.6 Pin interrupt active level (falling edge) interrupt set register
- 9.5.1.7 Pin interrupt active level (falling edge interrupt) clear register
- 9.5.1.8 Pin interrupt rising edge register
- 9.5.1.9 Pin interrupt falling edge register
- 9.5.1.10 Pin interrupt status register
- 9.5.2 GPIO GROUP0/GROUP1 interrupt register description
- 9.5.3 GPIO port register description
- 9.5.3.1 GPIO port byte pin registers
- 9.5.3.2 GPIO port word pin registers
- 9.5.3.3 GPIO port direction registers
- 9.5.3.4 GPIO port mask registers
- 9.5.3.5 GPIO port pin registers
- 9.5.3.6 GPIO masked port pin registers
- 9.5.3.7 GPIO port set registers
- 9.5.3.8 GPIO port clear registers
- 9.5.3.9 GPIO port toggle registers
- 9.5.1 GPIO pin interrupts register description
- 9.6 Functional description
- Chapter 10: LPC11U3x/2x/1x USB on-chip drivers
- 10.1 How to read this chapter
- 10.2 Introduction
- 10.3 USB driver functions
- 10.4 Calling the USB device driver
- 10.5 USB API
- 10.5.1 __WORD_BYTE
- 10.5.2 _BM_T
- 10.5.3 _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR
- 10.5.4 _CDC_CALL_MANAGEMENT_DESCRIPTOR
- 10.5.5 _CDC_HEADER_DESCRIPTOR
- 10.5.6 _CDC_LINE_CODING
- 10.5.7 _CDC_UNION_1SLAVE_DESCRIPTOR
- 10.5.8 _CDC_UNION_DESCRIPTOR
- 10.5.9 _DFU_STATUS
- 10.5.10 _HID_DESCRIPTOR
- 10.5.11 _HID_DESCRIPTOR::_HID_DESCRIPTOR_LIST
- 10.5.12 _HID_REPORT_T
- 10.5.13 _MSC_CBW
- 10.5.14 _MSC_CSW
- 10.5.15 _REQUEST_TYPE
- 10.5.16 _USB_COMMON_DESCRIPTOR
- 10.5.17 _USB_CORE_DESCS_T
- 10.5.18 _USB_DEVICE_QUALIFIER_DESCRIPTOR
- 10.5.19 _USB_DFU_FUNC_DESCRIPTOR
- 10.5.20 _USB_INTERFACE_DESCRIPTOR
- 10.5.21 _USB_OTHER_SPEED_CONFIGURATION
- 10.5.22 _USB_SETUP_PACKET
- 10.5.23 _USB_STRING_DESCRIPTOR
- 10.5.24 _WB_T
- 10.5.25 USBD_API
- 10.5.26 USBD_API_INIT_PARAM
- 10.5.27 USBD_CDC_API
- 10.5.28 USBD_CDC_INIT_PARAM
- 10.5.29 USBD_CORE_API
- 10.5.30 USBD_DFU_API
- 10.5.31 USBD_DFU_INIT_PARAM
- 10.5.32 USBD_HID_API
- 10.5.33 USBD_HID_INIT_PARAM
- 10.5.34 USBD_HW_API
- 10.5.35 USBD_MSC_API
- 10.5.36 USBD_MSC_INIT_PARAM
- Chapter 11: LPC11U3x/2x/1x USB2.0 device controller
- 11.1 How to read this chapter
- 11.2 Basic configuration
- 11.3 Features
- 11.4 General description
- 11.5 Pin description
- 11.6 Register description
- 11.6.1 USB Device Command/Status register (DEVCMDSTAT)
- 11.6.2 USB Info register (INFO)
- 11.6.3 USB EP Command/Status List start address (EPLISTSTART)
- 11.6.4 USB Data buffer start address (DATABUFSTART)
- 11.6.5 USB Link Power Management register (LPM)
- 11.6.6 USB Endpoint skip (EPSKIP)
- 11.6.7 USB Endpoint Buffer in use (EPINUSE)
- 11.6.8 USB Endpoint Buffer Configuration (EPBUFCFG)
- 11.6.9 USB interrupt status register (INTSTAT)
- 11.6.10 USB interrupt enable register (INTEN)
- 11.6.11 USB set interrupt status register (INTSETSTAT)
- 11.6.12 USB interrupt routing register (INTROUTING)
- 11.6.13 USB Endpoint toggle (EPTOGGLE)
- 11.7 Functional description
- Chapter 12: LPC11U3x/2x/1x USART
- 12.1 How to read this chapter
- 12.2 Basic configuration
- 12.3 Features
- 12.4 Pin description
- 12.5 Register description
- 12.5.1 USART Receiver Buffer Register (when DLAB = 0, Read Only)
- 12.5.2 USART Transmitter Holding Register (when DLAB = 0, Write Only)
- 12.5.3 USART Divisor Latch LSB and MSB Registers (when DLAB = 1)
- 12.5.4 USART Interrupt Enable Register (when DLAB = 0)
- 12.5.5 USART Interrupt Identification Register (Read Only)
- 12.5.6 USART FIFO Control Register (Write Only)
- 12.5.7 USART Line Control Register
- 12.5.8 USART Modem Control Register
- 12.5.9 USART Line Status Register (Read-Only)
- 12.5.10 USART Modem Status Register
- 12.5.11 USART Scratch Pad Register
- 12.5.12 USART Auto-baud Control Register
- 12.5.13 IrDA Control Register
- 12.5.14 USART Fractional Divider Register
- 12.5.15 USART Oversampling Register
- 12.5.16 USART Transmit Enable Register
- 12.5.17 UART Half-duplex enable register
- 12.5.18 Smart Card Interface Control register
- 12.5.19 USART RS485 Control register
- 12.5.20 USART RS-485 Address Match register
- 12.5.21 USART RS-485 Delay value register
- 12.5.22 USART Synchronous mode control register
- 12.6 Functional description
- RS-485/EIA-485 Normal Multidrop Mode
- RS-485/EIA-485 Auto Address Detection (AAD) mode
- RS-485/EIA-485 Auto Direction Control
- RS485/EIA-485 driver delay time
- RS485/EIA-485 output inversion
- 12.7 Architecture
- Chapter 13: LPC11U3x/2x/1x SSP/SPI
- 13.1 How to read this chapter
- 13.2 Basic configuration
- 13.3 Features
- 13.4 General description
- 13.5 Pin description
- 13.6 Register description
- 13.6.1 SSP/SPI Control Register 0
- 13.6.2 SSP/SPI Control Register 1
- 13.6.3 SSP/SPI Data Register
- 13.6.4 SSP/SPI Status Register
- 13.6.5 SSP/SPI Clock Prescale Register
- 13.6.6 SSP/SPI Interrupt Mask Set/Clear Register
- 13.6.7 SSP/SPI Raw Interrupt Status Register
- 13.6.8 SSP/SPI Masked Interrupt Status Register
- 13.6.9 SSP/SPI Interrupt Clear Register
- 13.7 Functional description
- Chapter 14: LPC11U3x/2x/1x I2C-bus controller
- 14.1 How to read this chapter
- 14.2 Basic configuration
- 14.3 Features
- 14.4 Applications
- 14.5 General description
- 14.6 Pin description
- 14.7 Register description
- 14.7.1 I2C Control Set register (CONSET)
- 14.7.2 I2C Status register (STAT)
- 14.7.3 I2C Data register (DAT)
- 14.7.4 I2C Slave Address register 0 (ADR0)
- 14.7.5 I2C SCL HIGH and LOW duty cycle registers (SCLH and SCLL)
- 14.7.6 I2C Control Clear register (CONCLR)
- 14.7.7 I2C Monitor mode control register (MMCTRL)
- 14.7.8 I2C Slave Address registers (ADR[1, 2, 3])
- 14.7.9 I2C Data buffer register (DATA_BUFFER)
- 14.7.10 I2C Mask registers (MASK[0, 1, 2, 3])
- 14.8 Functional description
- 14.8.1 Input filters and output stages
- 14.8.2 Address Registers, ADR0 to ADR3
- 14.8.3 Address mask registers, MASK0 to MASK3
- 14.8.4 Comparator
- 14.8.5 Shift register, DAT
- 14.8.6 Arbitration and synchronization logic
- 14.8.7 Serial clock generator
- 14.8.8 Timing and control
- 14.8.9 Control register, CONSET and CONCLR
- 14.8.10 Status decoder and status register
- 14.9 I2C operating modes
- 14.10 Details of I2C operating modes
- 14.10.1 Master Transmitter mode
- 14.10.2 Master Receiver mode
- 14.10.3 Slave Receiver mode
- 14.10.4 Slave Transmitter mode
- 14.10.5 Miscellaneous states
- 14.10.6 Some special cases
- 14.10.7 I2C state service routines
- 14.10.8 Initialization
- 14.10.9 I2C interrupt service
- 14.10.10 The state service routines
- 14.10.11 Adapting state services to an application
- 14.11 Software example
- Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1
- 15.1 How to read this chapter
- 15.2 Basic configuration
- 15.3 Features
- 15.4 Applications
- 15.5 General description
- 15.6 Pin description
- 15.7 Register description
- 15.7.1 Interrupt Register
- 15.7.2 Timer Control Register
- 15.7.3 Timer Counter
- 15.7.4 Prescale Register
- 15.7.5 Prescale Counter register
- 15.7.6 Match Control Register
- 15.7.7 Match Registers
- 15.7.8 Capture Control Register
- 15.7.9 Capture Registers
- 15.7.10 External Match Register
- 15.7.11 Count Control Register
- 15.7.12 PWM Control register
- 15.7.13 Rules for single edge controlled PWM outputs
- 15.8 Example timer operation
- 15.9 Architecture
- Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
- 16.1 How to read this chapter
- 16.2 Basic configuration
- 16.3 Features
- 16.4 Applications
- 16.5 General description
- 16.6 Pin description
- 16.7 Register description
- 16.7.1 Interrupt Register
- 16.7.2 Timer Control Register
- 16.7.3 Timer Counter registers
- 16.7.4 Prescale Register
- 16.7.5 Prescale Counter Register
- 16.7.6 Match Control Register
- 16.7.7 Match Registers
- 16.7.8 Capture Control Register
- 16.7.9 Capture Registers
- 16.7.10 External Match Register
- 16.7.11 Count Control Register
- 16.7.12 PWM Control Register
- 16.7.13 Rules for single edge controlled PWM outputs
- 16.8 Example timer operation
- 16.9 Architecture
- Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT)
- Chapter 18: LPC11U3x/2x/1x System tick timer
- Chapter 19: LPC11U3x/2x/1x ADC
- Chapter 20: LPC11U3x/2x/1x Flash programming firmware
- 20.1 How to read this chapter
- 20.2 Bootloader
- 20.3 Features
- 20.4 Description
- 20.5 Memory map after any reset
- 20.6 Flash content protection mechanism
- 20.7 Criterion for Valid User Code
- 20.8 ISP/IAP communication protocol
- 20.9 USB communication protocol
- 20.10 Boot process flowchart
- 20.11 Sector numbers
- 20.12 Code Read Protection (CRP)
- 20.13 ISP commands
- 20.13.1 Unlock <Unlock code>
- 20.13.2 Set Baud Rate <Baud Rate> <stop bit>
- 20.13.3 Echo <setting>
- 20.13.4 Write to RAM <start address> <number of bytes>
- 20.13.5 Read Memory <address> <no. of bytes>
- 20.13.6 Prepare sector(s) for write operation <start sector number> <end sector number>
- 20.13.7 Copy RAM to flash <Flash address> <RAM address> <no of bytes>
- 20.13.8 Go <address> <mode>
- 20.13.9 Erase sector(s) <start sector number> <end sector number>
- 20.13.10 Blank check sector(s) <sector number> <end sector number>
- 20.13.11 Read Part Identification number
- 20.13.12 Read Boot code version number
- 20.13.13 Compare <address1> <address2> <no of bytes>
- 20.13.14 ReadUID
- 20.13.15 ISP Return Codes
- 20.14 IAP commands
- 20.14.1 Prepare sector(s) for write operation
- 20.14.2 Copy RAM to flash
- 20.14.3 Erase Sector(s)
- 20.14.4 Blank check sector(s)
- 20.14.5 Read Part Identification number
- 20.14.6 Read Boot code version number
- 20.14.7 Compare <address1> <address2> <no of bytes>
- 20.14.8 Reinvoke ISP
- 20.14.9 ReadUID
- 20.14.10 Erase page
- 20.14.11 Write EEPROM
- 20.14.12 Read EEPROM
- 20.14.13 IAP Status codes
- 20.15 Debug notes
- 20.16 Register description
- 20.16.1 EEPROM BIST start address register
- 20.16.2 EEPROM BIST stop address register
- 20.16.3 EEPROM signature register
- 20.16.4 Flash controller registers
- 20.16.4.1 Flash memory access register
- 20.16.4.2 Flash signature generation
- 20.16.4.3 Signature generation address and control registers
- 20.16.4.4 Signature generation result registers
- 20.16.4.5 Flash module status register
- 20.16.4.6 Flash module status clear register
- 20.16.4.7 Algorithm and procedure for signature generation
- Signature generation
- Content verification
- Chapter 21: LPC11U3x/2x/1x Serial Wire Debugger (SWD)
- Chapter 22: LPC11U3x/2x/1x Integer division routines
- Chapter 23: LPC11U3x/2x/1x I/O Handler
- Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
- 24.1 Introduction
- 24.2 About the Cortex-M0 processor and core peripherals
- 24.3 Processor
- 24.4 Instruction set
- 24.4.1 Instruction set summary
- 24.4.2 Intrinsic functions
- 24.4.3 About the instruction descriptions
- 24.4.4 Memory access instructions
- 24.4.5 General data processing instructions
- 24.4.6 Branch and control instructions
- 24.4.7 Miscellaneous instructions
- 24.5 Peripherals
- 24.5.1 About the ARM Cortex-M0
- 24.5.2 Nested Vectored Interrupt Controller
- 24.5.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
- 24.5.2.2 Interrupt Set-enable Register
- 24.5.2.3 Interrupt Clear-enable Register
- 24.5.2.4 Interrupt Set-pending Register
- 24.5.2.5 Interrupt Clear-pending Register
- 24.5.2.6 Interrupt Priority Registers
- 24.5.2.7 Level-sensitive and pulse interrupts
- 24.5.2.8 NVIC usage hints and tips
- 24.5.3 System Control Block
- 24.5.3.1 The CMSIS mapping of the Cortex-M0 SCB registers
- 24.5.3.2 CPUID Register
- 24.5.3.3 Interrupt Control and State Register
- 24.5.3.4 Application Interrupt and Reset Control Register
- 24.5.3.5 System Control Register
- 24.5.3.6 Configuration and Control Register
- 24.5.3.7 System Handler Priority Registers
- 24.5.3.8 SCB usage hints and tips
- 24.5.4 System timer, SysTick
- 24.6 Cortex-M0 instruction summary
- Chapter 25: Supplementary information