UM10211 LPC23XX User Manual

User Manual:

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Chapter 1: LPC23xx Introductory information
- 1.1 Introduction
- 1.2 How to read this manual
- 1.3 Features
- 1.4 Applications
- 1.5 Ordering information and options
- 1.6 Architectural overview
- 1.7 ARM7TDMI-S processor
- 1.8 On-chip flash memory system
- 1.9 On-chip Static RAM
- 1.10 Block diagram
Chapter 2: LPC23XX Memory addressing
- 2.1 Memory map and peripheral addressing
- 2.2 Memory maps
- 2.3 APB peripheral addresses
- 2.4 LPC2300 memory re-mapping and boot ROM
  - 2.4.1 Memory map concepts and operating modes
  - 2.4.2 Memory re-mapping
- 2.5 Memory mapping control
  - 2.5.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)
  - 2.5.2 Memory mapping control usage notes
- 2.6 Prefetch abort and data abort exceptions
Chapter 3: LPC23XX System control block
- 3.1 Introduction
- 3.2 Pin description
- 3.3 Register description
- 3.4 Reset
  - 3.4.1 Reset Source Identification Register (RSIR - 0xE01F C180)
- 3.5 Brown-out detection
- 3.6 External interrupt inputs
- 3.7 Other system controls and status flags
  - 3.7.1 AHB Configuration
    - 3.7.1.1 AHB Arbiter Configuration register 1 (AHBCFG1 - 0xE01F C188)
      - 3.7.1.1.1 Examples of AHB1 settings
    - 3.7.1.2 AHB Arbiter Configuration register 2 (AHBCFG2 - 0xE01F C18C)
      - 3.7.1.2.1 Examples of AHB2 settings
  - 3.7.2 System Controls and Status register (SCS - 0xE01F C1A0)
- 3.8 Code security vs. debugging
Chapter 4: LPC23XX Clocking and power control
- 4.1 How to read this chapter
- 4.2 Introduction
- 4.3 Register description
- 4.4 Oscillators
- 4.5 Clock source selection multiplexer
  - 4.5.1 Clock Source Select register (CLKSRCSEL - 0xE01F C10C)
- 4.6 PLL (Phase Locked Loop)
- 4.7 Clock dividers
- 4.8 Power control
- 4.9 Wakeup timer
Chapter 5: LPC23XX External Memory Controller (EMC)
- 5.1 How to read this chapter
- 5.2 Basic configuration
- 5.3 Introduction
- 5.4 Features
- 5.5 Functional overview
- 5.6 EMC functional description
- 5.7 AHB Slave register interface
- 5.8 Memory bank select
- 5.9 Reset
- 5.10 Pin description
- 5.11 Register description
- 5.12 External memory interface
Chapter 6: LPC23XX Vectored Interrupt Controller (VIC)
- 6.1 How to read this chapter
- 6.2 Features
- 6.3 Description
- 6.4 Register description
- 6.5 VIC registers
- 6.6 Interrupt sources
Chapter 7: LPC23XX Memory Acceleration Module (MAM)
- 7.1 Introduction
- 7.2 Operation
- 7.3 Memory Acceleration Module blocks
- 7.4 Memory Accelerator Module Operating modes
- 7.5 MAM configuration
- 7.6 Register description
- 7.7 MAM Control Register (MAMCR - 0xE01F C000)
- 7.8 MAM Timing Register (MAMTIM - 0xE01F C004)
- 7.9 MAM usage notes
Chapter 8: LPC23XX Pin configuration
- 8.1 Overview
- 8.2 LPC2361/62 100-pin packages
- 8.3 LPC2364/65/66/67/68 100-pin packages
- 8.4 LPC2377/78 144-pin package
- 8.5 LPC2387 100-pin package
- 8.6 LPC2388 144-pin package
Chapter 9: LPC23XX Pin connect block
- 9.1 How to read this chapter
- 9.2 Description
- 9.3 Pin function select register values
- 9.4 Pin mode select register values
- 9.5 Register description
- Pin control module register reset values
Chapter 10: LPC23XX General Purpose Input/Output ports (GPIO)
- 10.1 Basic configuration
- 10.2 Features
  - 10.2.1 Digital I/O ports
  - 10.2.2 Interrupt generating digital ports
- 10.3 Applications
- 10.4 Pin description
- 10.5 Register description
- 10.6 GPIO usage notes
Chapter 11: LPC23XX Ethernet
- 11.1 How to read this chapter
- 11.2 Basic configuration
- 11.3 Introduction
- 11.4 Features
- 11.5 Architecture and operation
- 11.6 DMA engine functions
- 11.7 Overview of DMA operation
- 11.8 Ethernet Packet
- 11.9 Overview
  - 11.9.1 Partitioning
  - 11.9.2 Example PHY Devices
- 11.10 Pin description
- 11.11 Registers and software interface
  - 11.11.1 Register map
- 11.12 Ethernet MAC register definitions
  - 11.12.1 MAC Configuration Register 1 (MAC1 - 0xFFE0 0000)
  - 11.12.2 MAC Configuration Register 2 (MAC2 - 0xFFE0 0004)
  - 11.12.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0xFFE0 0008)
  - 11.12.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0xFFE0 000C)
  - 11.12.5 Collision Window / Retry Register (CLRT - 0xFFE0 0010)
  - 11.12.6 Maximum Frame Register (MAXF - 0xFFE0 0014)
  - 11.12.7 PHY Support Register (SUPP - 0xFFE0 0018)
  - 11.12.8 Test Register (TEST - 0xFFE0 001C)
  - 11.12.9 MII Mgmt Configuration Register (MCFG - 0xFFE0 0020)
  - 11.12.10 MII Mgmt Command Register (MCMD - 0xFFE0 0024)
  - 11.12.11 MII Mgmt Address Register (MADR - 0xFFE0 0028)
  - 11.12.12 MII Mgmt Write Data Register (MWTD - 0xFFE0 002C)
  - 11.12.13 MII Mgmt Read Data Register (MRDD - 0xFFE0 0030)
  - 11.12.14 MII Mgmt Indicators Register (MIND - 0xFFE0 0034)
  - 11.12.15 Station Address 0 Register (SA0 - 0xFFE0 0040)
  - 11.12.16 Station Address 1 Register (SA1 - 0xFFE0 0044)
  - 11.12.17 Station Address 2 Register (SA2 - 0xFFE0 0048)
- 11.13 Control register definitions
  - 11.13.1 Command Register (Command - 0xFFE0 0100)
  - 11.13.2 Status Register (Status - 0xFFE0 0104)
  - 11.13.3 Receive Descriptor Base Address Register (RxDescriptor - 0xFFE0 0108)
  - 11.13.4 Receive Status Base Address Register (RxStatus - 0xFFE0 010C)
  - 11.13.5 Receive Number of Descriptors Register (RxDescriptor - 0xFFE0 0110)
  - 11.13.6 Receive Produce Index Register (RxProduceIndex - 0xFFE0 0114)
  - 11.13.7 Receive Consume Index Register (RxConsumeIndex - 0xFFE0 0118)
  - 11.13.8 Transmit Descriptor Base Address Register (TxDescriptor - 0xFFE0 011C)
  - 11.13.9 Transmit Status Base Address Register (TxStatus - 0xFFE0 0120)
  - 11.13.10 Transmit Number of Descriptors Register (TxDescriptorNumber - 0xFFE0 0124)
  - 11.13.11 Transmit Produce Index Register (TxProduceIndex - 0xFFE0 0128)
  - 11.13.12 Transmit Consume Index Register (TxConsumeIndex - 0xFFE0 012C)
  - 11.13.13 Transmit Status Vector 0 Register (TSV0 - 0xFFE0 0158)
  - 11.13.14 Transmit Status Vector 1 Register (TSV1 - 0xFFE0 015C)
  - 11.13.15 Receive Status Vector Register (RSV - 0xFFE0 0160)
  - 11.13.16 Flow Control Counter Register (FlowControlCounter - 0xFFE0 0170)
  - 11.13.17 Flow Control Status Register (FlowControlStatus - 0xFFE0 0174)
- 11.14 Receive filter register definitions
  - 11.14.1 Receive Filter Control Register (RxFilterCtrl - 0xFFE0 0200)
  - 11.14.2 Receive Filter WoL Status Register (RxFilterWoLStatus - 0xFFE0 0204)
  - 11.14.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0xFFE0 0208)
  - 11.14.4 Hash Filter Table LSBs Register (HashFilterL - 0xFFE0 0210)
  - 11.14.5 Hash Filter Table MSBs Register (HashFilterH - 0xFFE0 0214)
- 11.15 Module control register definitions
  - 11.15.1 Interrupt Status Register (IntStatus - 0xFFE0 0FE0)
  - 11.15.2 Interrupt Enable Register (IntEnable - 0xFFE0 0FE4)
  - 11.15.3 Interrupt Clear Register (IntClear - 0xFFE0 0FE8)
  - 11.15.4 Interrupt Set Register (IntSet - 0xFFE0 0FEC)
  - 11.15.5 Power Down Register (PowerDown - 0xFFE0 0FF4)
- 11.16 Descriptor and status formats
  - 11.16.1 Receive descriptors and statuses
  - 11.16.2 Transmit descriptors and statuses
- 11.17 Ethernet block functional description
  - 11.17.1 Overview
  - 11.17.2 AHB interface
- 11.18 Interrupts
  - 11.18.1 Direct Memory Access (DMA)
  - 11.18.2 Initialization
  - 11.18.3 Transmit process
  - 11.18.4 Receive process
  - 11.18.5 Transmission retry
  - 11.18.6 Status hash CRC calculations
  - 11.18.7 Duplex modes
  - 11.18.8 IEE 802.3/Clause 31 flow control
  - 11.18.9 Half-Duplex mode backpressure
  - 11.18.10 Receive filtering
  - 11.18.11 Power management
  - 11.18.12 Wake-up on LAN
  - 11.18.13 Enabling and disabling receive and transmit
  - 11.18.14 Transmission padding and CRC
  - 11.18.15 Huge frames and frame length checking
  - 11.18.16 Statistics counters
  - 11.18.17 MAC status vectors
  - 11.18.18 Reset
  - 11.18.19 Ethernet errors
- 11.19 AHB bandwidth
  - 11.19.1 DMA access
  - 11.19.2 Types of CPU access
  - 11.19.3 Overall bandwidth
- 11.20 CRC calculation
Chapter 12: LPC23XX CAN controllers CAN1/2
- 12.1 How to read this chapter
- 12.2 Basic configuration
- 12.3 Introduction
- 12.4 Features
  - 12.4.1 General CAN features
  - 12.4.2 CAN controller features
  - 12.4.3 Acceptance filter features
- 12.5 Pin description
- 12.6 CAN controller architecture
  - 12.6.1 APB interface block (AIB)
  - 12.6.2 Interface management logic (IML)
  - 12.6.3 Transmit Buffers (TXB)
  - 12.6.4 Receive Buffer (RXB)
  - 12.6.5 Error Management Logic (EML)
  - 12.6.6 Bit Timing Logic (BTL)
  - 12.6.7 Bit Stream Processor (BSP)
  - 12.6.8 CAN controller self-tests
- Global self test
- Local self test
- 12.7 Memory map of the CAN block
- 12.8 CAN controller registers
  - 12.8.1 Mode Register (CAN1MOD - 0xE004 4000, CAN2MOD - 0xE004 8000)
  - 12.8.2 Command Register (CAN1CMR - 0xE004 x004, CAN2CMR - 0xE004 8004)
  - 12.8.3 Global Status Register (CAN1GSR - 0xE004 x008, CAN2GSR - 0xE004 8008)
- RX error counter
- TX error counter
  - 12.8.4 Interrupt and Capture Register (CAN1ICR - 0xE004 400C, CAN2ICR - 0xE004 800C)
  - 12.8.5 Interrupt Enable Register (CAN1IER - 0xE004 4010, CAN2IER - 0xE004 8010)
  - 12.8.6 Bus Timing Register (CAN1BTR - 0xE004 4014, CAN2BTR - 0xE004 8014)
- Baud rate prescaler
- Synchronization jump width
- Time segment 1 and time segment 2
  - 12.8.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL - 0xE004 8018)
  - 12.8.8 Status Register (CAN1SR - 0xE004 401C, CAN2SR - 0xE004 801C)
  - 12.8.9 Receive Frame Status Register (CAN1RFS - 0xE004 4020, CAN2RFS - 0xE004 8020)
    - 12.8.9.1 ID index field
  - 12.8.10 Receive Identifier Register (CAN1RID - 0xE004 4024, CAN2RID - 0xE004 8024)
  - 12.8.11 Receive Data Register A (CAN1RDA - 0xE004 4028, CAN2RDA - 0xE004 8028)
  - 12.8.12 Receive Data Register B (CAN1RDB - 0xE004 402C, CAN2RDB - 0xE004 802C)
  - 12.8.13 Transmit Frame Information Register (CAN1TFI[1/2/3] - 0xE004 40[30/ 40/50], CAN2TFI[1/2/3] - 0xE004 80[30/40/50])
- Automatic transmit priority detection
- Tx DLC
  - 12.8.14 Transmit Identifier Register (CAN1TID[1/2/3] - 0xE004 40[34/44/54], CAN2TID[1/2/3] - 0xE004 80[34/44/54])
  - 12.8.15 Transmit Data Register A (CAN1TDA[1/2/3] - 0xE004 40[38/48/58], CAN2TDA[1/2/3] - 0xE004 80[38/48/58])
  - 12.8.16 Transmit Data Register B (CAN1TDB[1/2/3] - 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0xE004 80[3C/4C/5C])
  - 12.8.17 CAN Sleep Clear register (CANSLEEPCLR - 0x400F C110)
  - 12.8.18 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114)
- 12.9 CAN controller operation
  - 12.9.1 Error handling
  - 12.9.2 Sleep mode
  - 12.9.3 Interrupts
  - 12.9.4 Transmit priority
- 12.10 Centralized CAN registers
  - 12.10.1 Central Transmit Status Register (CANTxSR - 0xE004 0000)
  - 12.10.2 Central Receive Status Register (CANRxSR - 0xE004 0004)
  - 12.10.3 Central Miscellaneous Status Register (CANMSR - 0xE004 0008)
- 12.11 Global acceptance filter
- 12.12 Acceptance filter modes
  - 12.12.1 Acceptance filter Off mode
  - 12.12.2 Acceptance filter Bypass mode
  - 12.12.3 Acceptance filter Operating mode
  - 12.12.4 FullCAN mode
- 12.13 Sections of the ID look-up table RAM
- 12.14 ID look-up table RAM
- 12.15 Acceptance filter registers
  - 12.15.1 Acceptance Filter Mode Register (AFMR - 0xE003 C000)
  - 12.15.2 Section configuration registers
  - 12.15.3 Standard Frame Individual Start Address Register (SFF_sa - 0xE003 C004)
  - 12.15.4 Standard Frame Group Start Address Register (SFF_GRP_sa - 0xE003 C008)
  - 12.15.5 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C)
  - 12.15.6 Extended Frame Group Start Address Register (EFF_GRP_sa - 0xE003 C010)
  - 12.15.7 End of AF Tables Register (ENDofTable - 0xE003 C014)
  - 12.15.8 Status registers
  - 12.15.9 LUT Error Address Register (LUTerrAd - 0xE003 C018)
  - 12.15.10 LUT Error Register (LUTerr - 0xE003 C01C)
  - 12.15.11 Global FullCANInterrupt Enable register (FCANIE - 0xE003 C020)
  - 12.15.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0xE003 C024 and FCANIC1 - 0xE003 C028)
- 12.16 Configuration and search algorithm
  - 12.16.1 Acceptance filter search algorithm
- 12.17 FullCAN mode
  - 12.17.1 FullCAN message layout
  - 12.17.2 FullCAN interrupts
  - 12.17.3 Set and clear mechanism of the FullCAN interrupt
- 12.18 Examples of acceptance filter tables and ID index values
  - 12.18.1 Example 1: only one section is used
  - 12.18.2 Example 2: all sections are used
  - 12.18.3 Example 3: more than one but not all sections are used
  - 12.18.4 Configuration example 4
  - 12.18.5 Configuration example 5
  - 12.18.6 Configuration example 6
- Explicit standard frame format identifier section (11-bit CAN ID):
- Group of standard frame format identifier section (11-bit CAN ID):
- Explicit extended frame format identifier section (29-bit CAN ID, Figure 60)
- Group of extended frame format identifier section (29-bit CAN ID, Figure 60)
  - 12.18.7 Configuration example 7
- FullCAN explicit standard frame format identifier section (11-bit CAN ID)
- Explicit standard frame format identifier section (11-bit CAN ID)
- FullCAN message object data section
  - 12.18.8 Look-up table programming guidelines
Chapter 13: LPC23XX USB device controller
- 13.1 How to read this chapter
- 13.2 Basic configuration
- 13.3 Introduction
- 13.4 Features
- 13.5 Fixed endpoint configuration
- 13.6 Functional description
  - 13.6.1 Analog transceiver
  - 13.6.2 Serial Interface Engine (SIE)
  - 13.6.3 Endpoint RAM (EP_RAM)
  - 13.6.4 EP_RAM access control
  - 13.6.5 DMA engine and bus master interface
  - 13.6.6 Register interface
  - 13.6.7 SoftConnect
  - 13.6.8 GoodLink
- 13.7 Operational overview
- 13.8 Pin description
  - 13.8.1 LPC2378 usage note
  - 13.8.2 LPC2388 usage note
- 13.9 Clocking and power management
  - 13.9.1 Power requirements
  - 13.9.2 Clocks
  - 13.9.3 Power management support
  - 13.9.4 Remote wake-up
- 13.10 Register description
  - 13.10.1 Port select register
    - 13.10.1.1 USB Port Select register (USBPortSel - 0xFFE0 C110 – LPC2378 only)
  - 13.10.2 Clock control registers
    - 13.10.2.1 USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4)
    - 13.10.2.2 USB Clock Status register (USBClkSt - 0xFFE0 CFF8)
  - 13.10.3 Device interrupt registers
  - 13.10.4 Endpoint interrupt registers
  - 13.10.5 Endpoint realization registers
  - 13.10.6 USB transfer registers
  - 13.10.7 SIE command code registers
    - 13.10.7.1 USB Command Code register (USBCmdCode - 0xFFE0 C210)
    - 13.10.7.2 USB Command Data register (USBCmdData - 0xFFE0 C214)
  - 13.10.8 DMA registers
- 13.11 Interrupt handling
- Slave mode
- DMA mode
- 13.12 Serial interface engine command description
  - 13.12.1 Set Address (Command: 0xD0, Data: write 1 byte)
  - 13.12.2 Configure Device (Command: 0xD8, Data: write 1 byte)
  - 13.12.3 Set Mode (Command: 0xF3, Data: write 1 byte)
  - 13.12.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes)
  - 13.12.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)
  - 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte)
  - 13.12.7 Get Device Status (Command: 0xFE, Data: read 1 byte)
  - 13.12.8 Get Error Code (Command: 0xFF, Data: read 1 byte)
  - 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte)
  - 13.12.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))
  - 13.12.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte)
  - 13.12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional))
  - 13.12.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))
  - 13.12.14 Validate Buffer (Command: 0xFA, Data: none)
- 13.13 USB device controller initialization
- 13.14 Slave mode operation
  - 13.14.1 Interrupt generation
  - 13.14.2 Data transfer for OUT endpoints
  - 13.14.3 Data transfer for IN endpoints
- 13.15 DMA operation
  - 13.15.1 Transfer terminology
  - 13.15.2 USB device communication area
  - 13.15.3 Triggering the DMA engine
  - 13.15.4 The DMA descriptor
  - 13.15.5 Non-isochronous endpoint operation
  - 13.15.6 Isochronous endpoint operation
- OUT endpoints
- IN endpoints
  - 13.15.6.4 DMA descriptor completion
  - 13.15.6.5 Isochronous OUT Endpoint Operation Example
  - 13.15.7 Auto Length Transfer Extraction (ATLE) mode operation
- OUT transfers in ATLE mode
- IN transfers in ATLE mode
  - 13.15.7.1 Setting up the DMA transfer
  - 13.15.7.2 Finding the DMA Descriptor
  - 13.15.7.3 Transferring the Data
- OUT endpoints
- IN endpoints
  - 13.15.7.4 Ending the packet transfer
- OUT endpoints
- IN endpoints
- 13.16 Double buffered endpoint operation
  - 13.16.1 Bulk endpoints
  - 13.16.2 Isochronous endpoints
Chapter 14: LPC23XX USB Host controller
- 14.1 How to read this chapter
- 14.2 Basic configuration
- 14.3 Introduction
  - 14.3.1 Features
  - 14.3.2 Architecture
- 14.4 Interfaces
  - 14.4.1 Pin description
  - 14.4.2 Software interface
Chapter 15: LPC23XX USB OTG controller
- 15.1 How to read this chapter
- 15.2 Basic configuration
- 15.3 Introduction
- 15.4 Features
- 15.5 Architecture
- 15.6 Modes of operation
- 15.7 Pin configuration
- 15.8 Register description
- 15.9 HNP support
  - 15.9.1 B-device: peripheral to host switching
- Remove D+ pull-up
- Add D+ pull-up
  - 15.9.2 A-device: host to peripheral HNP switching
- Set BDIS_ACON_EN in external OTG transceiver
- Clear BDIS_ACON_EN in external OTG transceiver
- Discharge VBUS
- Load and enable OTG timer
- Stop OTG timer
- Suspend host on port 1
- 15.10 Clocking and power management
  - 15.10.1 Device clock request signals
    - 15.10.1.1 Host clock request signals
  - 15.10.2 Power-down mode support
- 15.11 USB OTG controller initialization
Chapter 16: LPC23XX UART0/2/3
- 16.1 Basic configuration
- 16.2 Features
- 16.3 Pin description
- 16.4 Register description
- 16.5 Architecture
Chapter 17: LPC23XX UART1
- 17.1 Basic configuration
- 17.2 Features
- 17.3 Pin description
- 17.4 Register description
- 17.5 Architecture
Chapter 18: LPC23XX SPI
- 18.1 Basic configuration
- 18.2 Features
- 18.3 Introduction
- 18.4 SPI data transfers
- 18.5 SPI peripheral details
- 18.6 Pin description
- 18.7 Register description
- 18.8 Architecture
Chapter 19: LPC23XX SSP0/1 interfaces
- 19.1 Basic configuration
- 19.2 Features
- 19.3 Description
- 19.4 Pin descriptions
- 19.5 Bus description
- 19.6 Register Description
Chapter 20: LPC23XX SD/MMC interface
- 20.1 How to read this chapter
- 20.2 Basic configuration
- 20.3 Introduction
- 20.4 Features
- 20.5 SD/MMC card interface pin description
- 20.6 Functional overview
- 20.7 Register description
Chapter 21: LPC23XX I2C-bus interfaces I2C0/1/2
- 21.1 Basic configuration
- 21.2 Features
- 21.3 Applications
- 21.4 Description
- 21.5 Pin description
- 21.6 I2C operating modes
- 21.7 I2C implementation and operation
- 21.8 Register description
- 21.9 Details of I2C operating modes
- 21.10 Software example
Chapter 22: LPC23XX I2S interface
- 22.1 Basic configuration
- 22.2 Features
- 22.3 Description
- 22.4 Pin descriptions
- 22.5 Register description
- 22.6 I2S transmit and receive interfaces
- 22.7 FIFO controller
Chapter 23: LPC23XX Timer0/1/2/3
- 23.1 Basic configuration
- 23.2 Features
- 23.3 Applications
- 23.4 Description
- 23.5 Pin description
  - 23.5.1 Multiple CAP and MAT pins
- 23.6 Register description
- 23.7 Example timer operation
- 23.8 Architecture
Chapter 24: LPC23XX Pulse Width Modulator (PWM)
- 24.1 Basic configuration
- 24.2 Features
- 24.3 Description
- 24.4 Sample waveform with rules for single and double edge control
  - 24.4.1 Rules for Single Edge Controlled PWM Outputs
  - 24.4.2 Rules for Double Edge Controlled PWM Outputs
- 24.5 Pin description
- 24.6 PWM base addresses
- 24.7 Register description
Chapter 25: LPC23XX WatchDog Timer (WDT)
- 25.1 Features
- 25.2 Introduction
- 25.3 Description
- 25.4 Register description
- 25.5 Block diagram
Chapter 26: LPC23XX Real Time Clock (RTC) and battery RAM
- 26.1 How to read this chapter
- 26.2 Basic configuration
- 26.3 Features
- 26.4 Description
- 26.5 Architecture
- 26.6 Pin description
- 26.7 Register description
- 26.8 RTC usage notes
  - 26.8.1 Alarm output
- 26.9 Battery RAM
- 26.10 RTC external 32 kHz oscillator component selection
Chapter 27: LPC23XX Analog-to-Digital Converter (ADC)
- 27.1 How to read this chapter
- 27.2 Basic configuration
- 27.3 Features
- 27.4 Description
- 27.5 Pin description
- 27.6 Register description
- 27.7 Operation
Chapter 28: LPC23XX Digital-to Analog Converter (DAC)
- 28.1 Basic configuration
- 28.2 Features
- 28.3 Pin description
- 28.4 Register description (DACR - 0xE006 C000)
- 28.5 Operation
Chapter 29: LPC23XX Flash memory programming firmware
- 29.1 Introduction
- 29.2 Features
- 29.3 Description
  - 29.3.1 Memory map after any reset
    - 29.3.1.1 Criterion for Valid User Code
  - 29.3.2 Communication protocol
- 29.4 Boot process flowchart
- 29.5 Sector numbers
- 29.6 Code Read Protection (CRP)
- 29.7 ISP commands
- 29.8 IAP commands
- 29.9 JTAG flash programming interface
Chapter 30: LPC23XX General Purpose DMA (GPDMA) controller
- 30.1 Basic configuration
- 30.2 Introduction
- 30.3 Features of the GPDMA
- 30.4 Functional overview
- 30.5 Programmer’s model
- 30.6 About the programmer’s model
- 30.7 Programming the GPDMA
- 30.8 Summary of GPDMA registers
- 30.9 Register descriptions
- 30.10 Channel registers
- 30.11 Address generation
- 30.12 Scatter/Gather
- 30.13 Interrupt requests
  - 30.13.1 Hardware interrupt sequence flow
  - 30.13.2 Interrupt polling sequence flow
- 30.14 GPDMA data flow
- 30.15 Flow control
Chapter 31: LPC23XX EmbeddedTrace Module (ETM)
- 31.1 Features
- 31.2 Applications
- 31.3 Description
  - 31.3.1 ETM configuration
- 31.4 Pin description
- 31.5 Register description
- 31.6 Reset state of multiplexed pins
- 31.7 Block diagram
Chapter 32: LPC23XX EmbeddedICE logic
- 32.1 Features
- 32.2 Applications
- 32.3 Description
- 32.4 Pin description
- 32.5 JTAG usage notes
- 32.6 Register description
- 32.7 Block diagram
Chapter 33: LPC23XX RealMonitor
- 33.1 Features
- 33.2 Applications
- 33.3 Description
  - 33.3.1 RealMonitor Components
    - 33.3.1.1 RMHost
    - 33.3.1.2 RMTarget
  - 33.3.2 How RealMonitor Works
- 33.4 How to Enable RealMonitor
- 33.5 RealMonitor Build Options
Chapter 34: Supplementary information
- 34.1 Abbreviations
- 34.2 Legal information
- 34.3 Tables
- 34.4 Figures
- 34.5 Contents

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