M6800 Microprocessor Applications Manual 1975

M6800_Microprocessor_Applications_Manual_1975 M6800_Microprocessor_Applications_Manual_1975

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MOTOROLA
SelJ'1iconductor Products Inc_

M6800
MICROPROCESSOR
APPLICATION MANUAL
Circuit diagrams external to Motorola products are included as a means of illustrating typical Microprocessor
applications; consequently, complete information sufficient for construction purposes is not necessarily given. The
information in this manual has been carefully checked and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of Motorola Inc. or others.
Motorola reserves the right to change specifications without notice.

EXORciser MIKBUG and EXbug are trademarks of Motorola Inc.

First Edition
Second Printing
MOTOROLA INC., 1975
"All Rights Reserved"

Printed in U.S.A.

TABLE OF CONTENTS
CHAPTER 1
Introduction to the MC6800 Microprocessor ................................. 1-1
1
1-1
System Organization .................................................... 1-1
1-1.1
MC6800 Family Elements ................................................ 1-3
1-1.1.1
Memory on The Bus .................................................... 1-3
1-1.1.2
I/O on the Bus ......................................................... 1-5
1-1.2
Typical System Configuration ............................................. 1-7
1-1.2.1
Memory Allocation ..................................................... 1-7
1-1.2.2
Hardware Requirements .................................................. 1-7
1-2
1-2.1
1-2.2
1-2.3
1-2.3.1
1-2.3.2
1-2.3.3
1-2.3.4
1-2.3.5
1-2.3.6

Source Statements and Addressing Modes ................................... 1-10
Source Statements ...................................................... 1-11
Labels ................................................................ 1-11
Addressing Modes ............ .......................................... 1-12
Inherent (Includes "Accumulator Addressing " Mode) ......................... 1-12
Immediate Addressing Mode .............................................. 1-13
Direct and Extended Addressing Modes ..................................... 1-13
Relative Addressing Mode ................................................ 1-14
Indexed Addressing Mode ................................................ 1-16
Mode Selection ......................................................... 1-16

1-3
1-3.1
1-3.2
1-3.3
1-3.3.1
1-3.3.2
1-3.3.3
1-3.3.4
1-3.4
1-3.4.1
1-3.4.2

Instruction Set ......................................................... 1-20
Condition Code Register Operations ........................................ 1-20
Number Systems ....................................................... 1-21
Accumulator and Memory Operations ...................................... 1-24
Arithmetic Operations .............................................. .; .... 1-24
Logic Operations ....................................................... 1-26
Data Test Operations .................................................... 1-26
Data Handling Operations ................................................ 1-26
Program Control Operations .............................................. 1-26
Index Register/Stack Pointer Operations ..................................... 1-26
Jump and Branch Operations .............................................. 1-33

CHAPTER 2
2
Programming Techniques ................................................ 2-1
2-1
Arithmetic Operation .................................................... 2-1
2-1.1
Number Systems ....................................................... 2-1
2-1.2
The Condition Code Register ............................................. 2-2
2-1.3
Overflow .............................................................. 2-2
2-1.4
The Arithmetic Instructions ............................................... 2-4
2-1.4.1
Use of Arithmetic Instructions .......................... ".................. 2-4
2-1.5
Addition and Subtraction Routines ......................................... 2-8
iii

TABLE OF CONTENTS (Continued)
2-1.6
2-1.7

Multiplication .......................................................... 2-12
Division .............................................................. 2-18

2-2

Counting and Delay Measurement/Generation ................................ 2-26

2-3
2-3.1

Evaluating Peripheral Control Routines ...................................... 2-30
Service Requests and Programs as Waveforms on a Timing Diagram Notation Used .......................................................... 2-30
Development of Equations and Inequalities Used to Test Successful
System Operation ....................................................... 2-32
Floppy Disk Data Transfer Routine ........................................ 2-34
Cassette Data Transfer Routine ............................................ 2-35
Utilization of MPU Processing Time ....................................... 2-36
Program Model for Two Prioritized Service Requests .......................... 2-38
Requirements That Must Be Satisfied When an MPU Services Multiple SR's ...... 2-39
Serial Data Transfer and Dynamic Refresh Processing ......................... 2-41
Increasing MPU Processing Efficiency with the Flip-Flop Model for Two
"Equal Period SR's" .................................................... 2-42

2-3.2
2-3.3
2-3.4
2-3.5
2-3.6
2-3.7
2-3.8
2-3.9
2-4

Use of the Index Register ................................................ 2-44

CHAPTER 3
3
Input/Output Techniques ................................................. 3-1
3-1
Introduction ........................................................... 3-1
3-2
3-2.1
3-2.2
3-2.3
3-2.4

MC6800 Interrupt Sequences ............................................. 3-2
Interrupt Request (IRQ) .................................................. 3-2
Non Maskable Interrupt (NMI) ............................................ 3-4
Reset (RES) ............................................................ 3-4
Software Interrupt (SWI) ................................................. 3-6

3-3

Interrupt Prioritizing ..................................................... 3-7

3-4
3-4.1
3-4.1.1
3-4.1.2
3-4.1.3
3-4.1.4
3-4.2
3-4.2.1
3-4.2.2
3-4.2.3
3-4.2.4
3-4.3

Program Controlled Data Transfers ......................................... 3-8
MC6820 Peripheral Interface Adapter ...................................... 3-8
Input/Output Configuration ............................................... 3-8
Internal Organization .................................................... 3-9
Addressing and Initialization ............................................. 3-16
System Considerations ....................................... ,' ........... 3-20
MC6850 Asynchronous Communications Interface Adapter ..................... 3-21
Input/Output Configuration .............................................. .3-21
Internal Organization .................................................... 3-22
Addressing and Initialization .............................................. 3-25
System Considerations .................................................. .3-26
MC6860 Low Speed Modem ............................................ .3-28

TABLE OF CONTENTS (Continued)
3-4.3.1
3-4.3.2
3-4.3.3
3-5

Input/Output Configuration ............................................... 3-29
Internal Organization .................................................... 3-33
Handshake and Control .................................................. 3-34
Direct Memory Access .................................................. 3-38

CHAPTER
4
4-1
4-1.1
4-1.1.2
4-1.2
4-1.3
4-1.4
4-1.5

4
M6800 Family Hardware Characteristics ................................... .4-1
Clock Circuitry for the MC6800 .......................................... .4-1
Clock Requirements and Circuitry ........................................ .4-1
Clock Module .......................................................... 4-6
Halting the MC6800 and Single Instruction Execution ........................ .4-13
MC6800 Reset and Interrupt Controls ..................................... .4-13
Three-State Control Line Operation ....................................... .4-19
M6800 Family Interface and Enabling Considerations ........................ .4-19

4-2

M6800 System Hardware Techniques ...................................... .4-24
4-2.1
Interrupt Priority Circuitry ............................................... .4-24
4-2.1.1
8-Level Prioritizing .................................................... .4-24
4-2.1.2
13-Level Prioritizing ................................................... .4-27
4-2.2
Direct Memory Access (DMA) ........................................... .4-31
4-2.2.1
DMA Transfers by Halting Processor ...................................... .4-32
4-2.2.2
DMA Transfers by Cycle Stealing ........................................ .4-35
4-2.2.3
Multiplexed DMA!MPU Operation ...................................... ,.. .4-38
4-2.2.4
Summary of DMA Techniques ........................................... .4-42
4-2.3
Automatic Reset and Single Cycle Execution Circuitry ........................ .4-42
4-2.4
Interval Timer .......................................................... 4-46
4-2.5
Memory System Design .................................................. 4-48
4-2.5.1
Interfacing the MC6800 with Slow and Dynamic Memories ................... .4-48
4-2.5.2
2KX8 RAM Memory Design Example ..................................... .4-62
4-2.5.3
8KX8 Non-Volatile RAM Design Example ................................. .4-69
4-2.5.4
Design Considerations When Using Non-Family Memories with the MC6800 ..... .4-88
CHAPTERS
5
5-1
5-1.1
5-1.1.1
5-1.1.2
5-1.2
5-1.2.1
5-1.2.2
5-1.2.3
5-1.2.4

Peripheral Control Techniques ............................................ 5-1
Data Input Devices ...................................................... 5-1
Keyboards for Manual Entry of Data ....................................... 5-1
Decoded Keyboard for a POS Terminal ..................................... 5-1
Non Encoded Keyboard .................................................. 5-6
Scanning Wand for Capturing Data From Printed Symbols ..................... 5-12
Universal Product Code (UPC) Symbol ..................................... 5-12
Hardware Requirements .................................................. 5-16
Data Recovery Technique ................................................ 5-18
Wand!MPU Interface .................................................... 5-18
v

TABLE OF CONTENTS (Continued)
5-1.2.5

Data Recovery Control Program ........................................... 5-22

5-2
5-2.1
5-2.1.1
5-2.1.2
5-2.1.3
5-2.1.4
5-2.2

Data Output Devices .................................................... 5-34
Printer Control ................................ "......................... 5-34
SEIKO AN-I0IF Operating Characteristics .................................. 5-42
Printer Hardware/Software Tradeoffs ....................................... 5-43
Printer I/O Configuration ................................................. 5-43
Printer Control Program .................................................. 5-44
Burroughs Self-Scan Display Control ....................................... 5-57

5-3
5-3.1
5-3.1.1
5-3.1.2
5-3.1.3
5-3.1.4
5-3.2
5-3.2.1
5-3.2.2

Data Interchange Devices ................................................ 5-57
Introduction to Data Communications ...................................... 5-57
TTY to ACIA Hardware ................................................. 5-57
TTY to ACIA Software .................................................. 5-63
ACIA to Modem Hardware ............................................... 5-71
ACIA to Modem Software ............................................... 5-71
Tape Cassette System ................................................... 5-73
Hardware Description ................................................... 5-74
Software Description .................................................... 5-88

5-4
5-4.1
5-4.2
5-4.3
5-4.4
5-4.5
5-4.5
5-4.6.1
5-4.6.2
5-4.6.3
5-4.6.4
5-4.7
5-4.7.1
5-4.7.2
5-4.7.3
5-4.7.4
5-4.8
5-4.9

Floppy Disk ............................................................ 5-113
Introduction ........................................................... 5-113
Overall Considerations ................................................... 5-114
System Hardware/Software Interface ....................................... 5-119
Disk Program Routine Linking Control ..................................... 5-128
Seek and Restore Operations .............................................. 5-129
Read Operation ......................................................... 5-143
The Read Operation Interface ............................................. 5-144
Data Recovery ......................................................... 5-147
Read Data Logic ....................................................... 5-153
Read Operation Program Routine .......................................... 5-156
Write Operation ........................................................ 5-163
The Write Operation Interface ............................................. 5-167
Formatter Write Logic ................................................... 5-171
Formatter Error Detect Logic ............................................. 5-174
Write Operation Program Routine .......................................... 5-175
Special Operations - UPC Lookup ........................................ 5-181
Integrated Read/Write Logic .............................................. 5-198

5-4.A
5-4.B
5-4.C
5-4.0
5-4.E

SA900/901 Diskette Storage Drive ......................................... 5-203
Orbis Model 74 Diskette Drive ............................................ 5-219
Cal Comp 140 Diskette Drive ............................................. 5-228
Recording Formats ...................................................... 5-239
Floppy Disk Program Listings ............................................. 5-246
vi

TABLE OF CONTENTS (Continued)
CHAPTER 6
6
System Design Techniques ............................................... 6-1
6-1
Introduction ........................ ................................... 6-1
6-2

Transaction Terminal Definition ........................................... 6-2

6-3
6-3.1
6-3.2
6-3.3
6-3.4

Hardware/Software Tradeoffs ............................................. 6-6
Memory Reference I/O vs DMA I/O ....................................... 6-6
Software vs Hardware Peripheral Service Prioritizing .......................... 6-7
Software vs Hardware Timer .............................................. 6-7
Display With or Without Memory ......................................... 6-8

6-4
6-4.1
6-4.2
6-4.2.1
6-4.2.2
6-4.2.3
6-4.2.4
6-4.3

Transaction Terminal Hardware and Software' ................................ 6-10
Hardware Configuration .................................................. 6-10
Transaction Terminal Software Development ................................. 6-21
Software Background Preparation .......................................... 6-21
Development of Macro Flow Diagram ...................................... 6-48
Technique of Executive Program Organization ............................... 6-50
Description of Macro Flow Diagram ....................................... 6-57
Interrupt Control ........................................................ 6-90

CHAPTER 7
7
System Development Tasks ............................................... 7-1
7-1
Assembly of the Control Program .......................................... 7-2
7-1.1
M6800 Cross-Assembler Syntax ........................................... 7-2
7-1.1.1
Line Numbers .......................................................... 7-13
7-1.1.2
Fields of the Source Statement ............................................ 7-13
7-1.1.3
Labels ................................................................ 7-13
7-1.1.4
Operands .............................................................. 7-13
7-1.1.5
Comments ............................................................. 7-14
7-1.2
Accessing a Timeshare Service ............................................ 7-14
7-1.3
Entering a Source Program ............................................... 7-15
7-1.4
Assembling a Source Program ............................................ 7-18
7-1.5
Simulation ............................................................. 7-21
7-1.5.1
Simulator Commands .................................................... 7-21
7-1.5.2
Operating the Simulator .................................................. 7-29
7-1.5.3
Macro Commands ...................................................... 7-30
7-1.5.4
Sample Simulated Program ............................................... 7-34
7-1.5.5
Simulation Results ...................................................... 7-39
7-1.6
HELP ................................................................ 7-40
7-1.7
Build Virtual Machine ................................................... 7-50
7-2
7-2.1

The EXORciser ........................................................ 7-69
Hardware Components ................................................... 7-71
vii

TABLE OF CONTENTS (Continued)
7-2.1.1
7-2.2
7-2.2.1
7-2.2.2
7-2.3
7-2.4
7-2.4.1
7-2.4.2
7-2.4.3

Hardware Specifications ................................................. 7-71
Software Components ................................................... 7 -74
EXORciser Control ..................................................... 7-74
MAID ........ , ........................................................ 7-74
Memory Utilization ..................................................... 7-75
Hardware Operations and Controls ......................................... 7-78
Combined Hardware/Software ............................................. 7-78
ABORT Button Circuit .................................................. 7-79
REST AR T Button Circuit ................................................ 7-79
VMA Inhibit Decoder ................................................... 7-79
Asynchronous Communications Interface .................................... 7-80
Scope SYNC .......................................................... 7 -80

7-2.4.4
7-2.4.5
7-2.4.6
7-2.5
7-2.5.1
7-2.5.2
7-2.5.3

Interrupts .............................................................. 7-80
NMI ................................................................. 7-80
RESET ............................................................... 7-81
SWI .................................................................. 7-81

7-2.5.4
7-2.6

Hardware Interrupt ...................................................... 7-81
Test Signals ........................................................... 7 -82

7-3

Evaluation Module ...................................................... 7-88

APPENDIX A: Questions and Answers
1.

Systems Operation ...................................................... A-l

2.
3.
4.

Control ............................................................... A-5
Interrupt Operation ...................................................... A-9
Programming .,' ........................................................ A-15

viii

LIST OF FIGURES
CHAPTER
1-1.1
1-1.1.1-1
1-1.1.1-2
1-1.1.2-1
1-1.1.2-2
1-1.1.2-3
1-1.1.2-4
1-1.1.2-5
1-1.1.2-6
1-1.2-1

1
MC6800 Bus and Control Signals
MCM6810 RAM Functional Block Diagram
MCM6830 ROM Functional Block· Diagram

1-2.1
1-2.3.1-1
1-2.3.1-2
1-2.3.2-1
1-2.3.3-1
1-2.3.4-1
1-2.3.4-2
1-2.3.5-1
1-2.3.6-1

Programmable Registers
Accumulator Addressing
Inherent Addressing
Immediate Addressing Mode
Direct Addressing Mode
Relative Addressing Mode
Extended Addressing Mode

1-3.1
1-3.1-1
1-3.1-2
1-3.3.1-1
1-3.3.2-1
1-3.3.3-1
1-3.3.4-1
1-3.4.1-1
1-3.4.1-2
1-3.4.1-3
1-3.4.2-1
1-3.4.2-2
1-3.4.2-3
1-3.4.2-4
1-3.4.2-5
1-3.4.2-6
1-3.4.2-7
1-3.4.2-8
1-3.4.2-9

MC6800 Instruction Set
Condition Code Register Bit Definition
Condition Code Register Instructions
Arithmetic Instructions
Logic Instructions
Data Test Instructions
Data Handling Instructions
Index Register and Stack Pointer Instructions
Stack Operation, Push Instruction
Stack Operation, Pull Instruction

MPU Parallel I/O Interface
MPU/PIA Interface
PIA Registers
MPU Serial I/O Interface
MPU/ACIA Interface
ACIA Registers
MPU Minimum System

Indexed Addressing Mode
Addressing Mode Summary

Jump and Branch Instructions
Program Flow for Jump and Branch Instructions
Program Flow for BSR
Program Flow for JSR (Extended)
Program Flow for JSR (Indexed)
Program Flow for RTS
Program Flow for Interrupts
Program Flow for RTI
Conditional Branch Instructions

LIST OF FIGURES (Continued)
CHAPTER
2-1.5-1
2-1.6-1
2-1.6-2
2-1.6-3
2-1.6-4
2-1.6-5
2-1.6-6
2-1. 7-1
2-1.7-2

2
Decimal Subtract Assembly Listing
Multiplication Using Booth's Algorithm
Flow.Chart for Booth's Algorithm
Assembly Listing for Booth's Algorithm
Simulation of Booth's Algorithm
XKMULT Flow Chart
XKMULT Assembly Listing
XKDIVD Flow Chart
XKDIVD Assembly Listing

2-3.1-1
2-3.1-2
2-3.1-3
2-3.1-4
2-3.4-1
2-3.4-2
2-3.6-1
2-3.7-1
2-3.7-2
2-3.7-3
2-3.8-1
2-3.8-2
2-3.9-1

Peripheral Service Request (SR) and Data Transfer Program Waveforms and Notation
Flow Chart for a Typical Data Transfer Program for a Single Service Request
Data Transfer Program Indicating Method Used to Calculate Program Parameters
Relationship of Peripheral Data Stream to Program Timing
Flow Chart for Serial Data Transfer
Cassette Bit Serial Data Transfer Program
Program Model for Two Prioritized Time Dependent Service Requests
Timing Constraints for Successful System Operation for Prioritized Multiple Service Requests
Timing Diagram Showing Requirements of Equation 14 for Two SR's
Timing Diagram Showing Requirements of Equation 15 for Two SR's
Serial Data Transfer and Dynamic Display Refresh Routine
Serial Data Display SR Parameters and System Requirement Test
Flip-Flop Model for Two "Equal" Period SR's

CHAPTER
3-2.1-1
3-2.1-3
3-2.2-1
3-2.3-1
3-2.4-1

3
Hardware Interrupt Request Sequence
Interrupt Vectors, Permanent Memory Assignments
Non-Maskable Interrupt Sequence
Reset Interrupt Sequence
Software Interrupt Sequence

3-3-1

Hardware Interrupt Prioritizing -

3-4.1.1-1
3-4.1.2-1
3-4.1.2-2
3-4.1.2-3
3-4.1.2-4
3-4.1.2-5
3-4.1.3-1
3-4.1.3-2
3-4.1.3-3

MC6820 PIA VO Diagram
MC6820 PIA - Block Diagram
PIA Output Circuit Configurations
PIA Control Register Format
Read Timing Characteristics
Write Timing Characteristics
PIA Register Addressing
Family Addressing
Typical VO Configuration

Block Diagram

LIST OF FIGURES (Continued)
3-4.2.1-1
3-4.2.2-1
3-4.2.2-2
3-4.2.2-3
3-4.2.3-1
3-4.2.4-1
3-4.3.1-1
3-4.3.1-2
3-4.3.2-1
3-4.3.3-1
3-4.3.3-2
3-4.3.3-3
3-4.3.3-4

MC6850 ACIA I/O Diagram
ACIA Block Diagram
ACIA Status Register Format·
ACIA Control Register Format
ACIA Register Addressing
Asynchronous Data Format
Typical MC6860 System Configuration
I/O Configuration for MC6860 Modem
MC6860 Modem Block Diagram
Answer Mode
Automatic Disconnect - Long or Short Space
Originate Mode
Initiate Disconnect

CHAPTER
4-1.1-1
4-1.1-2
4-1.1-3
4-1.1-4
4-1.1-5
4-1.1-6
4-1.2-1
4-1.3-1
4-1.3-2a
4-1.3-2b
4-1.3-3
4-1.3-4
4-1.3-5
4-1.3-6
4-1..4-1
4-1.5-1
4-1.5.2

4
MPU Clock Waveform Specifications
MPQ6842 Clock Buffer
MPU Clock Circuit
Clock Circuit Waveforms
Monostable Clock Generator
Monostable Clock Circuit Waveforms
Halt and Single Cycle Execution
~ESET Timing
Interrupt Timing
Wait Instruction Timing
Interrupt Signal Format
Interrupt Enabling
Interrupt Not Properly Enabled
Alternate Enable Generation
Three State Control Timing
Buffered M6800 System
M6800 Bus Expansion Example

4-2.1-1
4-2.1.1-1
4-2.1.1-2
4-2.1.1-3
4-2.1.2-1
4-2.1.2-2
4-2.1.2-3
4-2.2.1-1

8-Level Priority Interrupt Configuration Block Diagram
8-Level Hardware Prioritized Interrupt Logic
Prioritizing Interrupt Circuitry Relative Timing
Interrupt Vector Memory Allocation
13-Level Hardware Prioritized Interrupt Logic
13-Level Priority Circuitry Truth Table
Interrupt Vector Memory Allocation
DMA Transfers by Halting Processor
xi

LIST OF FIGURES (Continued)
4-2.2.1-2
4-2.2.2-1
4-2.2.2-2
4-2.2.3-1
4-2.2.3-2
4-2.2.3-3
4-2.3-1
4-2.3-2
4-2.3-3
4-2.4-1
4-2.4-2
4-2.5.1-1/
4-2.5.1-2
4-2.5.1-3
4-2.5.1-4
4-2.5.1-5
4-2.5.1-6
4-2.5.1-7
4-2.5.1-8
4-2.5.1-9
4-2.5.1-10
4-2.5.1-11
4-2.5.1-12
4-2.5.2-1
4-2.5.2-2
4-2.5.2-3
4-2.5.2-4
4-2.5.2-5
4-2.5.3-1
4-2.5.3-2a
4-2.5.3-2b
4-2.5.3-2c
4-2.5.3-3
4-2.5.3-4
4-2.5.3-5
4-2.5.3-5
4-2.5.3-7
4-2.5.3-8
4-2.5.3-9

Timing of DMA Transfers by Halting the MPU
Block Diagram of DMA Transfers by Cycle Stealing
Timing of DMA Transfers by Cycle Stealing
Multiplexed DMA/MPU Operation
Timing of Multiplexed DMA/MPU Operation
Timing of Multiplexed DMA/MPU Operation Using MCM6605 4K RAM
Automatic Reset and HALT Synchronization
Single Instruction Timing
~ingle

Cycle Instruction Execution
Interval Timer
Timer Software Examples
MPU Clock Waveform Specifications
Read Data From Memories or Peripherals
Write Data to Memories or Peripherals
Read Cycle with 1.0ILS Memory
Write Cycle with 1.0ILS Memory
Effect of Memory Ready on Clock Signals
General MPU to Memory Interface
Dynamic Memory Interface
M6800 Clock Circuitry with Interface for Slow and Dynamic Memory
MPU Clock Circuitry Waveforms
MPU Clock Circuitry Waveforms
Monostable Clock Generator with Memory Ready
2KX8 Memory System Block Diagram
2KX8 Memory System Schematic Diagram
MPU/2KX8 Memory Read Cycle
MPU/2KX8 Memory Write Cycle
2KX8 Memory System with Memory Ready
MCM6605 4K RAM Block Diagram
Read Cycle Timing (Minimum Cycle)
Write and Refresh Cycle Timing (Minimum Cycle)
Read-Modify-Write Timing (Minimum Cycle)
Non- Volatile Memory System Block Diagram
EXORciser/4K Memory System Timing Diagram
Memory Timing in Standby Mode
Address Buffers and Decoding Logic
Data Buffers and Memory Array
Refresh Control Logic
Refresh Timing

xii

LIST OF FIGURES (Continued)
4-2.5.3-10

Power Fail Logic and Chip Enable Driver

4-2.5.3-11
4-2.5.3-12
4-2.5.3-13
4-2.5.3-14
4-2.5.3-15

Power Up/Down Synchronization
Memory System Breadboard
Alternate Read and Write Memory Accesses
Memory PC Board Array
Power Line Ripple

CHAPTER
5-1.1.1-1
5-1.1.1-2
5-1.1.1-3
5-1.1.1-4
5-1.1.1-5
5-1.1.2-1
5-1.1.2-2
5-1.1.2-3
5-1.1.2-4
5-1.1.2-5
5-1.1.2-6
5-1.1.2-7
5-1.1.2-8
5-1.1.2-9
5-1.2.1-1
5-1.2.1-2
5-1.2.1-3
5-1.2.1-4
5-1.2.1-5
5-1.2.2-1

5-1.2.3-1
5-1.2.3-2
5-1.2.3-3
5-1.2.4-1
5-1.2.5-1
5-1.2.5-2
5-1.2.5-3
5-1.2.5-4
5-1.2.5-5
5-1.2.5-6
5-1.2.5-7
5-1.2.5-8

POS Keyboard Configuration
Keyboard Coding/PIA Interface
Keyboard/PIA Hardware Interface
Flow Chart for Keyboard Service Routine
Keyboard Service Assembly Listing
Keyboard/PIA Interface
Keyboard Control Flow Chart
Keyboard Control Assembly Listing
Initial PIA I/O Configuration
Result of Key Closure
Contents of Accumulator A
I/O Conditions Reversed
Generation of Output Word
Lookup Table
UPC Symbol from Box of Kleenex Tissues
UPC Standard Symbol
UPC Character Structure
Nominal Dimensions of Printed UPC Symbol
Encoding for UPC Characters
UPC Wand Signal Conditioning Circuitry
Dimensions for Standard Symbol Characters
UPC Symbol Printing Tolerances
Worst Case Printing Tolerances
Transaction Terminal Flow Diagram
Flow Chart for XKIWND Initialization Routine
XKIWND Assembly Listing
Flow Chart for YKWAND Routine
YKWAND Assembly Listing
Flow Chart for WSORT Routine
WSOR T Assembly Listing
Flow Chart for WCNVRT UPC to BCD Conversion Routine
WCNVRT Assembly Listing

xiii

LIST OF FIGURES (Continued)
5-1.2.5-9
5-1.2.5-10
5-1.2.5-11
5-1.2.5-12
5-1.2.5-13

XKWAND Table and Buffer Memory Locations
Flow Chart for WERCHK ERROR Check
WERCHK Assembly Listing
Flow Chart for WBCDPK Packing Routine
WBCDPK Assembly Listing

5-2.1.1-1
5-2.1.1-2
5-2.1.1-3
5-2.1.3-1
5-2.1.4-1
5-2.1.4-2
5-2.1.4-3
5-2.1.4-4
5-2.1.4-5
5-2.1.4-6
5-2.1.4-7(a)
5-2.1.4-7(b)
5-2.1.4-8
5-2.1.4-9
5-2.2-1
5-2.2-2
5-3.1-1
5-3.1-2
5.3.1.1-1
5-3.1.2-1
5-3.1.2-2
5-3.1.3-1
5-3.2.1-1
5-3.2.1-2
5-3.2.1-3
5-3.2.1-4
5-3.2.1-5
5-3.2.1-6
5-3.2.1-7
5-3.2.1-8
5-3.2.1-9
5-3.2.1-10
5-3.2.1-11
5-3.2.1-12
5-3.2.1-13

SEIKO AN-101F Printing Mechanism
Timing Signal Generation
Timing Signals
SEIKO Printer Circuit Requirements
Print Cycle Timing: "MICROPROCESSOR"
Initialization
Printer Enable
Reset Service
Printer/MPU Relative Activity
Print Service
PKSCAN Flow Chart
PKSCAN Assembly Listing
Roll Left Operation on PIA Registers
Printer Column/Text Buffer Relationship
Burroughs Self-Scan Display Characteristics
PIA/Burroughs Display Interface
Paper Tape Format
TTY/ACIA and Modem/ACIA Systems
MPU to TTY Interface
Flow Chart for Comm. Program
Data Comm. Assembly Listing
MPU to Remote Site
800 BPI Recording Format
PIA, Tape Drive and Read/Write Control Electronics Interface
Read/Write Circuitry
Write Operation Timing and Format Conversion
Read Operation Timing
EOT/BOT Circuitry with Hardware Safety Feature
Phase Locked Loop Data Recovery
Read Data Recovery Timing (After Preamble, with Loop in Lock)
Cassette Serial Read/Write and Control Logic
Read Operation Sequence Timing
Write Operation Sequence Timing
Start, Stop, and Interblock Gaps Derived From the Tape Velocity Profile
Load Point
xiv

LIST OF FIGURES (Continued)
5-3.2.2-1
5-3.2.2-2
5-3.2.2-3
5-3.2.2-4
5-3.2.2-5

System Integration of Rewind to Load Point
Move to Load Point Flow Chart
Move to Load Point Assembly Listing
System Integration of Write Routine
Flow Chart of Write Routine

5~3.2.2-6

Write Routine Assembly Listing
Flow Chart of Read Routine

5-3.2.2-7
5-3.2.2-8
5-4.1-1
5-4.1-2
5-4.2-1
5-4.2-2
5-4.2-3
5-4.2-4
5-4.3-2
5-4.3-1
5-4.5-1
5-4.5-2
5-4.5-3
5-4.5-4
5-4.6.1-1
5-4.6.1-2
5-4.6.1-3
5-4.6.2-1
5-4.6.2-2
5-4.6.2-4
5-4.6.2-5
5-4.6.2-6
5-4.6.3-1
5-4.6.3-2
5-4.6.4-2
5-4.6.4-3
5-4.7.1-1
5-4.7.1-2
5-4.7.2-1
5-4.7.2-3
5-4.7.3-1
5-4.7.4-2
5-4.8-1
5-4.8-2

Read Routine Assembly Listing
M6800/Floppy Disk Subsystem
Floppy Disk System
Example of a Serial Task System
Multiple MPU System
Radial Interface
Daisy Chain Interface
Byte Ready/Request Interface
Floppy Disk Functional Interface
Typical Host/Floppy Disk Program Interaction
Seek/Restore Interface
'FKSKIN' Flow
'FKSEEK' Flow
Read Operation Interface
Read Clock Logic
Error Detect Logic
Floppy Disk IBM 3740 Format Data and Clock Recovery
Data and Clock Recovery Timing
VCM Frequency Faster Than Data Rate
PLL Response - Worst Case Capture Time
MC4024 Voltage vs Frequency for Floppy Disk Data Recovery
Read Data Logic (Read Shift Register, Read Buffer, Bit Counter and CRC Check)
Start Read Timing
Read Routine Flow Chart
System Integration of Floppy Disk Routines
Write Operation Interface
Write Control Signal Sequence
Floppy Disk Write Logic
Append CRC Timing
Error Detect Logic
Write Flow
UPC Track Format
UPC Lookup Program Integration
xv

LIST OF FIGURES (Continued)
5-4.8-4
5-4.9-1
5-4.9-2
5-4.9-3
5-4.A-2
5-4.A-3
5-4.A-4
5-4.A-5
5-4.A-6A
5-4.A-6B
5-4.A-7
5-4.A-8
5-4.A-9
5-4.A-10
5-4.A-11
5-4.A-12
5-4.A-13
5-4.A-14
5-4.A-15
5-4.A-15
5-4.A-17
5-4.B-1
5-4.B-3
5-4.B-4
5-4.B-5

UPC Search Program Flow Chart
Combined Read/Write Data Logic
Combined Read/Write Clock Logic
Error Detect Logic
Loading SA900/901
SA900 Functional Diagram, One Sector Hole
SA901 Functional Diagram, 32 Sector Holes
Head Load and Carriage Assembly
SA100 Diskette and Cartridge Layout
SAlOl Diskette and Cartridge Layout
Standard Interface Lines, SA 900/901
Index Timing, SA 900/901
Index/Sector Timing, SA 900/901
Data Line Driver/Receiver Combination, SA 900/901
Control Signal Driver/Receiver, SA 900/901
Sector Recording Format, SA 901
Track Access Timing, SA 900/901
Read Initiate Timing, SA 900/901
Read Signal Timing, SA 900/901
Write Initiate Timing, SA 900/901
File Inop Circuit, SA 900/901
Orbis Model 74 Functional Block Diagram
Power Up Sequence, Orbis Model 74
Read/Write Sequence, Orbis Model 74
Interface Drive & Receiver, Orbis Model 74

5-4.C-1
5-4.C-8
5-4.C-9
5-4.C-10
5-4.C-11
5-4.C-12
5-4.C-13
5-4.D-1
5-4.D-2
5-4.D-4
5-4.D-3
5-4.D-5
5-4.D-6
5-4.D-7
5-4.D-8

Floppy Disk Cartridge, Cal Comp 140
The CDS 140, Cal Comp 140
Driver Mechanism, Cal Comp 140
Centering Cone and Driver Hub, Cal Comp 140
Positioning Mechanism, Cal Comp 140
Model 140 Functional Block Diagram, Cal Comp 140
Tunnel Erase, Cal Comp 140
Data Pattern
Bit Cell
Data Bytes
Byte·
Track Format
Index Recording Format
Sector Recording Format
Index Address Mark

xvi

LIST OF FIGURES (Continued)
5-4.D-9
5-4.D-10
5-4.D-11

ID Address Mark
Data Address Mark
Deleted Data Address Mark

CHAPTER 6
Conventional Design Cycle
6-1-1
6-1-2
MPU -Based Design Cycle
6-2-1

POS Keyboard Configuration

6-4.1-1

Transaction Terminal Block Diagram

6-4.1-2
6-4.1-3
6-4.1-4
6-4.1-5
6-4.1-6
6-4.1-7
6-4.1-8
6-4.1-9
6-4.2.1-1
6-4.2.2-1
6-4.2.3-1
6-4.2.4-1
6-4.2.4-2
6-4.2.4-3
6-4.2.4-4
6-4.2.4-5
6-4.2.4-6
6-4.2.4-7
6-4.2.4-8
6-4.2.4-9
6-4.2.4-10
6-4.2.4-11
6-4.2.4-12
6-4.3-1
6-4.3-2

Control Circuitry Configuration
I/O Control Card Schematic Diagram
MPU /Control Card Schematic
MIKBUG™ PIA and TTY /RS-232 Circuitry

CHAPTER
7-1
7-1.3-1
7-1.3-2
7-1.4-1

7
System Development: Like an Iceberg
Entering the Source Program "AAA"
Listing of the Source Program "AAA"
Fields of Assembly Listing

Transaction Terminal Memory Map
Transaction Terminal Address Decoding Chart
Bus Extender Enable/Disable
MC8T26, Partial Schematic
Flow for Key Entry Data
Transaction Terminal Flow Diagram
XLABEL Assembly Listing
System Initialization Assembly Listing
Software Poll for Service Assembly Listing
Keyboard PIA Hardware Interface
Keyboard Coding/PIA Interface
Keyboard Decode Assembly Listing
XKSAFE General Flow Diagram
XKSAFE Initialization Section Flow Chart
XKSAFE Entry Point Flow Charts
XKSAFE Main Processing Flow Chart
XKSAFE Defining Section
XKSAFE Service Routine Flow Charts
Flag Reference Summary
Interrupt Control Flow Chart
Interrupt Poll Assembly Listing

xvii

LIST OF FIGURES (Continued)
7-1.4-2
7-1.5.4-1

Assembly Listing for Sample Program "AAA"
Simulation of "AAA"

7-2
7-2-1
7-2-2
7-2.3-1
7-2.6-1

Procedure for Designing and Verifying a System Using the M6800 Microcomputer

7-3-1
7-3-2
7-3-3

Motorola Evaluation Module

Motorola EXORciser
Typical EXORciser System Block Diagram
Memory Map and Addressing
EXORciser Backplane Connections for All Boards
Evaluation Module Block Diagram
Evaluation Module Memory Map

xviii

LIST OF TABLES
CHAPTER
2-1.2-1
2-1.3-1
2-1.3-2
2-1.4-1
2-1.4-2
2-1.4.1-1
2-1.4.1-2

2
Condition Code Register
Overflow for Addition
Overflow for Subtraction
Arithmetic Instructions
Effect of DMA instruction
Truth Table for" Add with Carry"
Truth Table for "Subtract with Borrow"

CHAPTER 4
Performance of Circuit in Figure 4-1.1.1-3
4-1.1-1
Performance of Circuit in Figure 4-1. 1. 1-6
4-1.1-2
4-2.1.1-1
4-2.1.1-2
4-2.2.1-1
4-2.2.4-1
4-2.4-1
4-2.5.3-1
4-2.5.3-2
4-2.5.3-3
4-2.5-4-1

8 Level Priority Circuitry Truth Table
PROM Code for Priority Encoder
Address Assignment
Summary of DMA Techniques
Interval Timer Programming Chart
8KX8 Non-Volatile Memory System Power Requirements
Standby Mode Current Allocation
Battery Characteristics
MPU Family Interface Chart

CHAPTER
5-4.4-1
5-4.4-2
5-4.4-3
5-4.5-5
5-4.5-6
5-4.5-7
5-4.6.4-1
5-4.7.4-1
5-4.8-3
5-4.C-2
5-4.C-3
5-4.C-4
5-4.C-5
5-4.C-6
5-4.C-7

5
'FUDELT' RAM Location
'FVABOR' RAM Location
'FVSTAT' RAM Location
Seek/Restore Preparation Routine
Interrupt Driven Seek/Restore Routine
Seek Examples
Floppy Disk Read Routine
Floppy Disk Write Data Routine
UPC Search Routine
Physical Characteristics, Cal Comp 140
Power Requirements, Cal Comp 140
Operating Environment, Cal Comp 140
Specifications, Cal Comp 140
140'Disk Drive Output Signals, Cal Comp 140
Interface Logic Levels, Cal Comp 140
xix

LIST OF TABLES (Continued)
CHAPTER
6-4.2.1-1
6-4.2.1-2
6-4.2.1-3

6
Transaction Terminal Keyboard/Wand Entry
Transaction Terminal Keyboard Buffers
Transaction Terminal Keyboard Flags

CHAPTER
7-1-1
7-1.1-1
7-1.1-2
7-1.4-1
7-1.5.5-1
7-1.6-1
7-1.6-2
7-1.6-3
7-1.7-1

7
Alphabetic Listing of Instruction Mnemonics
Assembler Directives
ASCn Code
Assembler Error Messages
Typical Simulator Errors
HELP Error Messages
HELP Listing of Simulator and B VM Commands
HELP Messages
B VM Machine File and Output Memory Commands

7-2.2.2-1

MAID Control Commands

7-3-1

Evaluation Module Specifications

CHAPTER 1
1.

INTRODUCTION TO THE MC6800 MICROPROCESSOR

Motorola has elected to provide a microprocessor family of parts headed by the MC6800
Microprocessing Unit (MPU). The MC6800 MPU is an eight-bit parallel microprocessor with addressing
capability of up to 65,536 words. It is TTL compatible requiring only a single five-volt supply and no external
TTL devices for bus interface in small systems.
In support of the MPU are several memory and I/O interface devices. To date, the family consists of
a 128 X 8 RAM (MCM6810), a 1024 X 8 ROM (MCM6830), a parallel I/O interface (MC6820 PIA), and an
asynchronous serial I/O interface (MC6850 ACIA). In keeping with the family concept, each operates on a
single five-volt power supply and is compatible with the system bus signals. The family of parts is not a chip set
in the sense that the MPU operation is dependent upon other family elements; the MC6800 is a self-contained
microprocessor capable of operating with virtually any MOS or standard TTL device. The significant point is
that the other family members merely add additional capability and/or flexibility. They provide excellent tools
in configuring a full microprocessor operating system.

1-1

SYSTEM ORGANIZATION

Before describing the individual parts in any detail, an explanation of the MPU bus and control
structure will serve to demonstrate how a system is brought together. Figure 1-1-1 is organized to show the
processor's inputs and outputs in four functional categories; data, address, control, and supervisory.
The width and drive capability of the Data Bus has become a standard means of measuring
microprocessors. The MC6800 has an 8-bit bidirectional bus to facilitate data flow throughout the system. The
MPU Data Bus will drive up to 130 pf and one standard TTL load. As a result of the load characteristics of the
RAM, ROM, ACIA, and PIA, the MPU can drive from 7 to 10 family devices without buffering.
Using the family I/O interface devices allows the 16-bit Address Bus to assume additional
responsibility in the M6800 system. Not only does the Address Bus specify memory, but it becomes a tool to
specify I/O devices. By means of its connections to the Data Bus, Control Bus, and selected address lines, the
I/O interface is allocated an area of memory. As a result, the user may converse with I/O using any of the
memory reference instructions, selecting the desired peripheral with a memory address.
In addition to the Data and Address Bus, a Control Bus is provided for the memory and
interface devices. The Control Bus consists of a heterogeneous mix of signals to regulate system operation. Following is a brief review of the designated Control Bus signals shown in Figure 1-1-1. ¢2 is one
phase of the system clock applied to the MPU. It is applied to the enable or chip select inputs of the
family parts to insure that the devices are enabled only when the address bus and VMA are stable. Reset
is used to reset and start the MPU from a power down condition. It is also routed to the Reset inputs
of the PIAs for use during power on initialization. Interrupt Request is generated by the PIA, ACIA, or
user defined hardware to notify the MPU of a request for service.

1-1

Read/Write (R/W) and Valid Memory Address (VMA) are MPU outputs characterizing the Data
Bus and Address Bus, respectively. R/W designates whether the MPU is in a Read or Write mode for each
cycle. VMA indicates to memory and I/O that the MPU is performing a read or write operation in a given cycle.
This signal is applied to the enable or chip select inputs of each family device in order to disable data transfer
when VMA is low.
The last set of signals in Figure 1-1-1, the MPU Supervisory, is used for timing and control of the
MC6800 itself. Note that three of the Supervisory signals are shared with the control bus and affect the memory
and I/O devices as well.

cp1

is one of the two clock phases to the MPU. Non-Maskable Interrupt (NMI) is similar to the

interrupt request input mentioned earlier, except that NMI will always be serviced regardless of the state of a
programmable interrupt mask contained within the processor. Data Bus Enable (DBE) is the three-state control
signal for the MPU data bus. Normally, this signal will be ¢2, derived from the clock. Three-State Control
(TSC) affects the address bus and the R/W line in the same manner that DBE controls the data bus. This signal
can be used, for example, to accomplish a direct memory access by putting the Address Bus and the R/W line in
the high impedance state. The last supervisory input is the Halt signal. When Halt is low, the MPU will stop
processing. In the Halt mode, all three-state signals will be in a high impedance state (address, data and R/W),
VMA will be low, and Bus Available will be high.
The Bus Available supervisory output from the MPU is normally in an inactive low state. It is
brought high by the occurrence of the Halt input low or by execution of a WAIT instruction. In either case, the
MPU stops program execution and sets Bus Available high, indicating that all the three-state buffers are in the
high impedance state. If the MPU has stopped as a result of the Hal t signal, Bus Available will remain high until
the Halt input is again taken high. If the MPU has stopped as a result of the WAIT instruction, it is waiting for an
interrupt and Bus Available will remain active until a non-maskable interrupt or interrupt request occurs. Bus
Available may be used to signal external hardware that the MPU is off the bus for multiprocessor or direct
memory access applications.
+5 V

GND

BUS AVAILABLE

DATA
BUS

HArT
THREE·STATE CONTROL
DATA BUS ENABLE

ADDRESS
BUS

MC6800

NON·MASKABLE INT.
RESET

1
VALID MEM.
ADDRESS

---------------.INT.REQ
~------------~-2

- - - - - - - - - - - - - - . RESET

TO/FROM
6800 CONTROL
CIRCUITS

TO/FROM
MEMORY AND
PERIPHERALS

FIGURE 1-1-1. MC6800 Bus and Control Signals

1-2

CONTROL
BUS

1-1.1

M6800 FAMILY ELEMENTS
With the MC6800 as the focal point, a variety of memory and I/O devices may be tied onto the bus

network. The busses will provide TTL compatible voltage levels (VOH = 2.4 volts, VOL = 0.4 volts) while
dri ving capacitive loads up to 130 picofarads with current loads of up to 1.6 rna sink current and 100 /-La source
current.
1-1.1.1

Memory On The Bus

Memory is connected in a straightforward fashion by tieing directly to the MC6800 busses.
Motorola currently provides two byte oriented memory devices as part of the microprocessor family: The 128 X
8 RAM (MCM681 0) and the 1024 X 8 ROM (MCM6830). Block diagrams of the RAM and ROM are shown
in Figures 1-1.1.1-1 and 1-1.1.1-2, respectively. Notice that the data lines have three-state buffers permitting
the memory data signals to wire-OR directly onto the system data bus. Address decoding is minimized by
providing multiple enable (E) inputs. The enable inputs, when active, select the specified device as defined by
the address inputs. For a small to medium size system, no additional address decoding is necessary. The
memories operate from a single 5V power supply and are TTL compatible. Static operation eliminates the need
for clocks or refresh.

MEMORY
MATRIX
128 X 8

(8) DATA BUS

............
R/W_-----..t

MEMORY CONTROL

E ----4.--"
E-----I
Ee__---l
E"e__---I

FIGURE 1-1.1.1-1. MCM6810 RAM Functional Block Diagram
E*"----,
*DEFINED BY USER

E*..-----.
E* __- - - I

(I)

a..
~

~
w
a:
0
0

<
~

ADDRESS
DECODER

•
•
•
•
•
•
•
•

MEMORY
MATRIX

THREE-STATE
OUTPUT
BUFFERS

DATA BUS

FIGURE 1-1.1.1-2. MCM6830 ROM Functional Block Diagram

1-3

MPU

Control

(8)~} Peripheral
(8)~

r=====~L

_____.t=~==~

FIGURE 1-1.1.2-1. MPU Parallel I/O Interface

Data
Control

MPU

ADDRESS
DO
Dl

~----------------~~ D2

~----------------~~~ D3
D4
D5
D6
D7

FIGURE 1-1.1.2-2. MPU/PIA Interface

CSO
CSl
CS2
RSO
RSl

PIA

Eill'L

IROA
IR08
RESET

DATA ADDRESS
CONTROL

"A" CONTROL
"A" DATA
DIRECTION
DATA

"A" DATA
REGISTER

CAl
CA2
PAO-PA7

ADDRESS
"8" CONTROL
CONTROL
"8" DATA
DIRECTION
"8" DATA
REGISTER

FIGURE 1-1.1.2-3. PIA Registers

C81
C82

P80-P87

MPU

'L- --

iI.

...
~

"--

FIGURE 1-1.1.2-4. MPU Serial I/O Interface

,....-

..,1.-

",I-

DATA

, ....

CONTROL

ADDRESS

1-4

TRANSMIT DATA
RECEIVE DATA
ACIA

'"I/O CONTROL
I/"

PERIPHERAL
OR MODEM

1-1.1.2

I/O On The Bus

The family VO devices are also tied directly to the bus network. In the M6800 architecture, VO is
configured to respond to MPU instructions in the same fashion as memory. This is accomplished by tapping off
the MPU busses such that VO has a "memory" address that the MPU references. Two devices available for
interfacing the microprocessor with the outside world are the MC6820, Peripheral Interface Adapter (PIA), for
parallel interface, and the MC6850, Asynchronous Communication Interface Adapter (ACIA), for serial
interface. Both are designed to tie directly to the MPU busses and transfer signals between peripherals and the
MPU under program control.
Interfacing the MPU to a variety of VO devices is straightforward with the Peripheral Interface
Adapter (PIA). It is a programmable general purpose parallel interface device designed to interface the MPU to
peripherals through two 8-bit bidirectional peripheral data busses and four control lines as shown in Figure
1-1.1.2-1.
The MPU/PIA interface consists of three elements: 8 data lines, 5 address lines, and 5 control lines
(see Figure 1-1.1.2-2). The data lines are bidirectional common to the MPU data bus. The PIA taps off 5 bits
from the 16-bit MPU address bus. These 5 inputs are ~tilized to select the PIA (CSO, CSl, CS2) as well as
registers within the PIA (RSO and RS 1).
The PIA uses all of the signals on the MPU Control Bus. The R!W input ties directly to the MPU
R!W output to control direction of data flow. The PIA has two independent Interrupt Request outputs that may
be wire-ORed together and tied to the IRQ line of the Control Bus or applied separately to prioritizing circuitry.
The Reset input may be tied directly to the MPU control bus to initialize the PIA to an all zero condition when
required. Finally, the Enable input is the timing signal to be supplied to the PIA. This input is typically the cf>2
clock.
The PIA is programmable in the sense that the MPU can Read and/or Write into its internal registers.
There are a total of six 8-bit registers in the PIA. They are separated into an A and B side, each side containing a
Control Register, Data Direction Register, and an Output Data Register (Figure 1-1. 1.2-3). To define operation
of the PIA control lines, an 8-bit word is loaded into the Control Register. Likewise, to define the
PINperipheral data lines to be inputs or outputs, an 8-bit word is loaded into the Data Direction Register.
Finally, data being transferred to peripherals may be saved in the PIA Output Data Register.
Motorola has also made available a serial interface device to accommodate asynchronous data
transfer. The MC6850 Asynchronous Communications Interface Adapter (ACIA) is a general purpose
programmable interface for use between the MPU and asynchronous I/O as shown in Figure 1-1.1.2-4. The
ACIA ties into the MPU Address, Data, and Control Busses enabling the MPU to handle the serial VO using
memory reference instructions.

1-5

The MPU/ACIA interface consists of three elements (see Figure 1-1.1.2-5): 8 data lines, 4 address
lines, and 3 control lines. The data lines are bidirectional common to the MPU data bus. Four of the sixteen
MPU address signals are used to select a particular ACIA (CSO, CS1, CS2), and to select registers within the
ACIA (RS).
The control signals from the bus are Read/Write (R/W) and Enable (E). The R/W input is common to
the MPU control bus R/W signal and the E input in a typical application is the cf>2 clock.
The internal structure of the ACIA is centered around four registers (Figure 1-1.1.2-6): Control,
Status, Transmit Data, and Receive Data. The ACIA is programmed by storing an 8-bit word into the write only
Control Register. This register controls the function of the receiver, transmitter, interrupt enables, and the

MPU

CSO
CS1

ACIA

R/W
IRQ
E
DATA
ADDRESS
CONTROL

FIGURE 1-1.1.2-5. MPU/ACIA Interface

DATA

ADDRESS

TRANSMIT DATA

RECEIVE DATA

CONTROL
CONTROL

STATUS

TRANSMIT DATA
RECEIVE DATA
CLEAR-TO-SEND
DATA CARRIER DETECT
REQUEST-TO-SEND

FIGURE 1-1.1.2-6. ACIA Registers

1-6

modem control signals. ACIA status and error conditions are monitored by reading the 8-bit Satus Register.
The ACIA also has independent transmit and receive data buffers to save data and perform serial/parallel
transformation.
1-1.2

TYPICAL SYSTEM CONFIGURATION

With the preceding material as background, the family devices and bus structure can be combined in
a system configuration. Figure 1-1.2-1 shows a system controlled by the MC6800 containing one each RAM,
ROM, PIA, and ACIA. With the exception of suitable peripherals, this block diagram represents all of the
hardware required for a fully operational MPU system. The family of parts represents 5 devices, clock circuitry
can be designed with 2 devices, and start-up can be accomplished with one device l . Therefore, a functional
system can be configured with as few as eight devices and have both parallel and serial I/O capability.
The configuration of Figure 1-1.2-1 represents typical interconnections regardless of the size of the
system. The data bus is shared fully between all devices in the system. The control bus is shared by all devices,
with each tapping off signals as required. The I/O devices wire-OR all interrupt request signals to the MPU IRQ
input. The PIA has two interrupts and the ACIA, one. VMA and cp2 are both required inputs to the family
devices and are, therefore, applied to the inputs as shown in Figure 1-1.2-1. 2 guarantees that all busses are
stable and VMA designates a valid memory cycle whenever a memory or I/O device is enabled.
1-1.2.1

Memory Allocation

The Address Bus lends itself to very flexible memory allocation. Different combinations of signals
may be tapped off the Address Bus to define where in "memory" each device is located. The chip select signals
(CSO, CS 1, CS2) of the PIA/ ACIA and the enable inputs of the RAM/ROM are used to select specific
devices. In Figure 1-1.2-1, for example, A2, A 14, and A 15, are used to enable the PIA for MPU data
transfer. The least significant address bits (AD, AI) are then utilized to select a memory word or I/O
register within the selected device. Therefore, a given address will specify the device, and a location
within the device.
Table 1-1.2.1-1 shows the "memory map" of the example system. This map represents the area in
memory where each device is located, including I/O. For example, address bits A14 and A15 are both tied to
the E inputs of the RAM. Therefore, whenever both of these address signals are low, the RAM will be
conversing with the MPU on the data bus. It should be noted that without address decoding, the devices will be
allocated a block of memory because the "don't care" address bits may be either logical "0" or" 1", thereby
widening the devices apparent address band. Having defined the memory map, the user may then determine the
address of registers in a specific I/O device. Table 1-1.2.1-2 shows the corresponding register addresses for
each ACIA and PIA register. Notice that bit 2 of the control registers (CRAb2 and CRBb2) and R!W areused to
assist the address signals to select PIA and ACIA registers, respectively.
1-1.2.2

Hardware Requirements

The final point to consider is that the example configuration represents a minimum system. To
expand the system, the user need only make further use of the bus network. If, for example, an additional PIA is
required, A4, A14, and A15 may be tied to CSO, CS1, and CS2, respectively. This procedure could be
continued to add multiple memory and I/O devices without address decoding.
lSee Chapter 4 for typical clock and start-up circuits.

1-7

START·

1/>2
CLOCK

1/>1

MPU

VMA.1/>2

VMA

DBO-DB7

AO-A9
ROM
-....;..;...;..;......--1 E
-~~---LE~

______________

DBO-DB7

AO-AS
RAM

E
E
E
E
RSO
RS1

DBO-DB7

CSO
CS1
CS2

PIA

~'---y----J
PARALLEL I/O (DATA AND CONTROL)
_ _...;A..;,;O;...,-t RS
DBO-DB7
ACIA

IRQ

SERIAL I/O (DATA AND CONTROL)

FIGURE 1-1.2-1. MPU Minimum System

1-8

The MC6800 microprocessor complemented by its family of parts was designed with ease of use in
mind. Interfacing peripherals to the microprocessor with PIAs and ACIAs eases the burden of hardware design
and minimizes software requirements by distributing intelligence to these interfaces. Power supply
requirements are uncomplicated: one five-volt supply throughout the family. Neither decode nor buffering
circuitry is required in systems containing less than 7 to 10 family devices. As the system grows, the design may
require buffers to prevent overloading or address decoders to more precisely define memory blocks. Be that as
it may, the rules don't change and bussing continues to be straightforward.

15
0
1
0
0

ADDRESS
10 9 8 7

6 5 4 3 2 1 0
X X X X X X X
X X X X X X X X X X
1 X X

0
1
1
1

1
X = Variable address
. = Don't care

DEVICE

MEMORY MAP

RAM
ROM
PIA

0000-007F HEX
COoo-C3FF HEX
4004-4007 HEX

ACIA
4008-4009 HEX
o = Logical zero
1 = Logical one

TABLE 1-1.2.1-1

ADDRESS(HEX)

I/O REGISTER

(4004-4007)

RSI

4004
4004

0
0

4005

0
1

4006
4006
4007
(4008-4009)

1
1

(PIA)

RSO
0
0

Data direction register A (CRAb2 =0)
Peripheral interface register A (CRAb2 = 1)
Control register A
Data direction register B (CRBb2 = 0)

1
0
0
1

Peripheral interface register B (CRBb2 = 1)
Control register B
(ACIA)

4008
4008

RS
0
0

4009

Transmit data register (write only)

4009

Receiver data register (read only)

Control register (write only)
Status register (read only)

TABLE

1-1.2~1-2

1-9

1-2

SOURCE STATEMENTS AND ADDRESSING MODES

A hardware configuration similar to that described in the preceding Section provides the nucleus for
a system based on the M6800 Microprocessor Family. Three additional elements are required to complete a
typical system design: (1) the actual peripheral equipment that is dictated by the system specification; (2) any
auxiliary electronics required to control the peripherals; (3) the' 'intelligence" that enables the MPU to perform
the required control and data processing functions.
In an MPU based design, "intelligence" refers to the control program, a sequence of instructions
that will guide the MPU through the various operations it must perform. During development, the designer uses
the MC6800's predefined instruction set to prepare a control program that will satisfy the system requirements.
The program, usually called "software" at this point, is then stored in ROM memory that can be accessed by
the MPU during operation, thus becoming the system's intelligence. Once in ROM, the program is often called
"firmware", however, it is common to find the terms software and firmware used interchangeably in this
context.
Definition of suitable peripheral interfaces is discussed in detail in Chapter 5. The remainder of this
Chapter provides the background information necessary for generation of the control program. Source
statement format and the MPU's addressing modes are introduced in this section. The instruction set is
described in Section 1-3.
The MPU operates on 8-bit binary numbers presented to it via the Data Bus. A given number (byte)
may represent either data or an instruction to be executed, depending on where it is encountered in the control
program. The M6800 has 72 unique instructions, however, it recognizes and takes action on 197 of the 256
possibilities that can occur using an 8-bit word length. This larger number of instructions results from the fact
that many of the executive instructions have more than one addressing mode.
These addressing modes refer to the manner in which the program causes the MPU to obtain its
instructions and data. The programmer must have a method for addressing the MPU's internal registers and all
of the external memory locations. The complete executive instruction set and the applicable addressing modes
are summarized in Figure 1-3-1, however, the addressing modes will be described in greater detail prior to
introducing the instruction set later in this chapter. A programming model of the MC6800 is shown in Figure
1-2-1. The programmable registers consist of: two 8-bit Accumulators; a 6-bit Condition Code Register; a
Program Counter, a Stack Pointer, and an Index Register, each 16 bits long.
0

ACCUMULATOR A

ACCA

ACCUMULATOR B

ACCB
15

0
INDEX REGISTER

PROGRAM COUNTER

STACK POINTER

SP
5

IHlllNlzlvlcl

CONDITION CODES REGISTER

FIGURE 1-2-1. Programming Model of MC6800

1-10

1-2.1

SOURCE STATEMENTS

While programs can be written in the MPU's language, that is, binary numbers, there is no easy way
for the programmer to remember the particular word that corresponds to a given operation. For this reason,
instructions are assigned a three letter mnemonic symbol that suggests the definition of the instruction. The
program is written as a series of source statements using this symbolic language and then translated into
machine language. The translation can be done manually using an alphabetic listing of the symbolic instruction
set such as that shown in Appendix AI. More often, the translation is accomplished by means of a special
computer program referred to as a cross-assembler. The cross-assembler and other "software" design aids
available to the user are described in Chapter 7.
During assembly, each source statement or executive instruction is converted to from one to three
bytes of operating code (opcode), depending on the addressing mode used. The term" executive instruction" is
used here to distinguish between statements that generate machine code and "assembly directives" that are
useful in controlling and documenting the source program but generate no code. The Assembly Directives are
described in Section 7-1. 1.
Each statement in the source program prepared by the user may have from one to four fields: a label,
a mnemonic operator (instruction), an operand, and a comment. The four fields are illustrated in the following
typical source statement:

Label
BEGIN 1

Operator
TST

Operand
DATA1B

Comment
TEST CONTENTS OF DATA1B

(This instruction causes the MPU to test the contents of the memory location labeled DATA1B and set the
Condition Code Register bits accordingly.)
Each source statement must have at least the mnemonic operator field. An operand mayor may not
be required, depending on the nature of the instruction. The comment field is optional, at the programmer's
convenience, for describing and documenting the program.

1-2.2

LABELS

Labels and their use are described in greater detail in Chapter 7. In general, they may correspond to
either a numerical value or a memory location. This use of symbolic references to memory permits
programming without using specific numerical memory addresses. For instance, the operand label "DM1B"
in the example may be anywhere in memory. Labels are required for source statements that are the destination
of jump and branch instructions. In the example, "BEGIN1" identifies the statement as the destination of a
branch or jump instruction located elsewhere in the control program. That instruction will, in turn, have
"BEGIN1" as its operand.
Labels may be up to six characters long and use any alphanumeric combination of the character set
shown in Appendix A2 with the restriction that the first character be alphabetic. Three single character labels,
A, B, and X, are reserved for referring to accumulator A, accumulator B , and the Index Register, respectively.

1-11

1-2.3

ADDRESSING MODES

1-2.3.1

Inherent (Includes "Accumulator Addressing" Mode)
The successive fields in a statement are normally separated by one or more spaces. An exception to

this rule occurs for instructions that use dual addressing in the operand field and for instructions that must
distinguish between the two accumulators. In these cases, A and B are "operands" but the space between them
and the operator may be omitted. This is commonly done, resulting in apparent four character mnemonics for
those instructions.
The addition instruction, ADD, provides an example of dual addressing in the operand field:

Operator

Operand

Comment

ADDA

MEM12

ADD CONTENTS OF MEM12 TO ACCA

ADDB

MEM12

ADDCONTENTSOFMEM12TOACCB

The example used earlier for the test instruction, TST, also applies to the accumulators and uses the
"accumulator addressing mode" to designate which of the two accumulators is being tested:
Operator

Comment

TSTB

TEST CONTENTS OF ACCB

TSTA

TEST CONTENTS OF ACCA

A number of the instructions either alone or together with an accumulator operand contain all of the
address information that is required, that is, the address is "inherent" in the instruction itself. For instance, the
instruction ABA causes the MPU to add the contents of accumulators A and B together and place the result in
accumulator A. The instruction INCB, another example of "accumulator addressing" , causes the contents of
accumulator B to be increased by one. Similarly, INX, increment the Index Register, causes the contents of the
Index Register to be increased by one.
Program flow for instructions of this type is illustrated in Figures 1-2.3.1-1 and 1-2.3.1-2. In these
figures, the general case is shown on the left and a specific example is shown on the right. Numerical examples
are in decimal notation. Instructions of this type require only one byte of opcode.
MPU

MPU

INDEX
ACCB

1199_2001

115_161
RAM

RAM

PROGRAM
MEMORY

PC = 5000

............- - - - /
PC

t-----t

GENERAL FLOW
GENERAL FLOW

PC = 5001 ............_ - - - 1

EXAMPLE

FIGURE 1-2.3.1-2. Accumulator Addressing

FIGURE 1-2.3.1-1. Inherent Addressing

1-12

MPU

ACCA
25
RAM

ADDR t - - - -.....

= 100

PC t - - - - - f

PC + 1

1 - - - -....
1-----4

ADDR = 0 ~255
GENERAL FLOW

EXAMPLE

t----..;.--i

PROGRAM
MEMORY

GENERAL FLOW

ADDR

= 5004

5005

t - - - -.....
1 - - - - - 1 .......

EXAMPLE

FIGURE 1-2.3.3-1. Direct Addressing Mode

FIGURE 1-2.3.2-1. Immediate Addressing Mode

1-2.3.2 Immediate Addressing Mode
In the Immediate addressing mode, the operand is the value that is tobe operated on. For instance,
the instruction

Operator
LDAA

Comment
LOAD 25 INTO ACCA

Operand
#25

causes the MPU to "immediately load accumulator A with the value 25; no further address reference is
required. The Immediate mode is selected by preceding the operand value with the" #" symbol. Program flow
for this addressing mode is illustrated in Figure 1-2.3.2-1.
The operand format allows either properly defined symbols or numerical values. Except for the instructions
CPX, LDX, and LDS, the operand may be any value in the range 0 to 255. Since Compare Index Register
(CPX) , Load Index Register (LDX) , and Load Stack Pointer (LDS), require 16-bitvalues, the immediate mode
for these three instructions require two-byte operands. In the Immediate addressing mode, the" address" of the
operand is effectively the memory location immediately following the instruction itself.
1-2.3.3

Direct and Extended Addressing Modes

In the Direct and Extended modes of addressing, the operand field of the source statement is the
address of the value that is to be operated on. The Direct and Extended modes differ only in the range of
memory locations to which they can direct the MPU. Direct addressing generates a single 8-bit operand and,
hence, can address only memory locations 0 through 255; a two byte operand is generated for Extended
addressing, enabling the MPU to reach the remaining memory locations, 256 through 65535. An example of
Direct addressing and its effect on program flow is illustrated in Figure 1-2.3.3-1.
The MPU, after encountering the opcode for the instruction LDAA (Direct) at memory location
5004 (Program Counter = 5094), looks in the next location, 5005, for the address of the operand. It then sets

1-13

the program counter equal to the value found there (100 in the example) and fetches the operand, in this case a
value to be loaded into accumulator A, from that location. For instructions requiring a two-byte operand such as
LDX (load the Index Register), the operand bytes would be retrieved from locations 100 and 101.
Extended addressing, Figure 1-2.3.3-2, is similar except that a two-byte address is obtained from
locations 5007 and 5008 after the LDAB (Extended) opcode shows up in location 5006. Extended addressing
can be thought of as the "standard" addressing mode, that is, it is a method of reaching anyplace in memory.
Direct addressing, since only one address byte is required, provides a faster method of processing data and
generates fewer bytes of control code. In most applications, the direct addressing range, memory locations
0-255, are reserved for RAM. They are used for data buffering and temporary storage of system variables, the
area in which faster addressing is of most value.
MPU

MPU

ADDR = 3001---:';;'_-1'

FiGURE 1-2.3-3-2. Extended Addressing Mode
PROGRAM
MEMORY

PC = 5006
PC

~---I

5009
ADDR;;;' 256

EXAMPLE

GENERAL FLOW

1- 2.3.4

Relative Addressing Mode

In both the Direct and Extended modes, the address obtained by the MPU is an absolute numerical
address. The Relative addressing mode, implemented for the MPU's branch instructions, specifies a memory
location relative to the Program Counter's current location. Branch instructions generate two bytes of machine
code, one for the instruction opcode and one for the "relative" address (see Figure 1-2.3.4-1). Since it is
desirable to be able to branch in either direction, the 8-bit address byte is interpreted as a signed 7 -bit value; the
8th bit of the operand is treated as a sign bit, "0" = plus and" 1" = minus. The remaining seven bits represent
the numerical value. This results in a relative addressing range of ± 127 with respect to the location of the
branch instruction itself. However, the branch range is computed with respect to the next instruction that would
be executed if the branch conditions are not satisfied. Since two bytes are generated, the next instruction is
located at PC

+ 2.

If D is defined as the address of the branch destination, the range is then:

(PC
or

+ 2) - 127

=:::; D =:::; (PC

PC -

+ 2) + 127

125 =:::; D =:::; PC

that is, the destination of the branch instruction must be within -125 to

+ 129

+ 129 memory locations of the branch

instruction itself. For transferring control beyond this range, the unconditional jump (JMP) ,jump to subroutine
(JSR), and return from subroutine (RTS) are used.

1-14

In Figure 1-2.3.4-1, when the MPU encounters the opcode for BEQ (Branch if result of last
instruction was zero), it tests the Zero bit in the Condition Code Register. If that bit is "0", indicating a
non-zero result, the MPU continues execution with the next instruction (in location 5010 in Figure 1-2.3.4-1).
If the previous result was zero, the branch condition is satisfied and the MPU adds the offset, 15 in this case, to
PC

2 and branches to location 5025 for the next instruction.
The branch instructions allow the programmer to efficiently direct the MPU to one point or another
in the control program depending on the outcome of test results. Since the control program is normally in
read-only memory and cannot be changed, the relative address used in execution of branch instructions is a
constant numerical value.

MPU

RAM

Program
Memory

(PC + 2)

(PC

5008

5010

Next Instr.

5025

Next Instr.
1--------1

Next Instr.

+ 2) + (Offset)

FIGURE 1-2.3.4-1. Relative Addressing Mode

1-15

1-2.3.5

Indexed Addressing Mode
With Indexed addressing, the numerical address is variable and depends on the current contents of

the Index Register. A source statement such as

Operator

Operand
X

STAA

Comment
PUT A IN INDEXED LOCATION

causes the MPU to store the contents of accumulator A in the memory location specified by the contents of the
Index Register (recall that the label "X" is reserved to designate the Index Register). Since there are
instructions for manipulating X during program execution (LDX, INX, DEX, etc.), the Indexed addressing
mode provides a dynamic "on the fly" way to modify program activity.
The operand field can also contain a numerical value that will be automatically added to X during
execution. This format is illustrated in Figure 1-2.3.5-1.
When the MPU encounters the LDAB (Indexed) opcode in location 5006, it looks in the next
memory location for the value to be added to X (5 in the example) and calculates the required address by adding
5 to the present Index Register value of 400. In the operand format, the offset may be represented by a
label or a numerical value in the range 0-255 as in the example. In the earlier example, STAA X, the operand is
equivalent to O,X, that is, the 0 may be omitted when the desired address is equal to X.

1-2.3.6

Mode Selection
Selection of the desired addressing mode is made by the user as the source statements are written.

Translation into appropriate opcode then depends on the method used. If manual translation is used, the
addressing mode is inherent in the opcode. For example, the Immediate, Direct, Indexed, and Extended modes
may all be used with the ADD instruction. The proper mode is determined by selecting (hexidecimal notation)
8B, 9B, AB, or BB, respectively (see Figure 1-3-1).
The source statement format includes adequate information for the selection if an assembler
program is used to generate the opcode. For instance, the Immediate mode is selected by the Assembler
whenever it encounters the "#" symbol in the operand field. Similarly, an "X" in the operand field causes the
Indexed mode to be selected. Only the Relative mode applies to the branch instructions, therefore, the
mnemonic instruction itself is enough for the Assembler to determine addressing mode.
MPU

MPU

ACCS

nn
Tr\Jl5'E"X

U2[]

ADDR = INDX I-----I~
+ OFFSET t--....o...;.;.~....

ADDR = 405

PROGRAM
MEMORY

1-----1

1--""";';'--1"'"
PROGRAM
MEMORY

PC = 5006

OFFSET';;; 255
GENERAL FLOW

t-----I

EXAMPLE

FIGURE 1-2.3.5-1. Indexed Addressing Mode

1-16

For the instructions that use both Direct and Extended modes, the Assembler selects the Direct mode
if the operand value is in the range 0-255 and Extended otherwise. There are a number of instructions for which
the Extended mode is valid but the Direct is not. For these instructions, the Assembler automatically selects the
Extended mode even if the operand is in the 0-255 range. The addressing modes are summarized in Figure

1-2.3.6-1.
Direct:

Example: SUBB Z
Addr. Range = 0-255

Instruction

n +1

Z = Oprnd Address

n+2

Next Instr.

Immediate:
Example: LOAA #K
(K = One-Byte Oprnd)

n + 1
n+2

Instruction

= Operand

Next Inst.

•

OR
(K = Two-Byte Oprnd)
(CPX, LOX, and LOS)

•
•
(K = One-Byte Oprnd)

K = Operand
OR

(K = Two-Byte Oprnd)

KH = Operand

Z + 1

KL = Operand

Relative:

If Z
If Z

~>""'255,

Example: BNE

Assembler Select Direct Mode
255, Extended Mode is selected

n + 1

= Operand

n+2

= Operand

n+3

Next Instr.

Instruction

n+1

(K = Signed 7-Bit Value)

Instruction

n + 2

±K = Brnch Offset
Next Instr.

•
•
•

Addr. Range:
-125 to +129
Relative to n.

Extended:
Example: CMPA Z
Addr. Range:

256-65535

FO Instruction
(n + 2) ±K

n + 1

ZH = Oprnd Address

n+2

ZL = Oprnd Address

n+3

Next Instr.

•
•
•
(K

= One-Byte

Oprnd)

If Brnch Tst False,

Indexed:

= Operand

Next Instr.

= Two-Byte

Oprnd)

= Operand

Z + 1

= Operand

Instruction

= Offset

Example: AODA Z, X

n + 1

Addr. Range:
0-255 Relative to
I ndex Register, X

n+2

Next Instr.

(Z = 8-Bit Unsigned
Value)

X+Z

FIGURE 1-2.3.6-1. Addressing Mode Summary

1-17

If Brnch Tst True.

•
•
•

OR
(K

= Operand

ADDRESSING MODES
BOOLEAN/ARITHMETIC OPERATION

ACCUMULATOR AND MEMORY
OPERATIONS
Add

IMMED

DIRECT

INDEX

EXTND

MNEMONIC

""'

AOOA

AOOB

IN HER

A + M->A

B+M->B

""'

(All register I,bels

refer to contents)

Z V C

t
t
t
t
t

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

t
t
t
t
t

•
•
•
•

Add Acmltrs

ABA

Add with Carry

AOCA

AOCB

B+M+C->B

A.M->A

ANDB

2
2

B·M->B

BITA

BITB

2
2

2
2
2
2

ANOA

2
2

A·M
B.M

00 ->M

And
Bit Test
Clear

CLR
CLRA
CLRB

Compare

CMPA

CMPB

Compare Acmltrs

CBA

Complement, l's

COM

Complement, 2's
(Negate)

Decimal Adjust, A
Decrement

Exclusive OR
Increment

A+B->A
A+M+C->A

00 ->A

00 ->B
B-M

COMA

A->A

COMB

B->B

NEGA

00 - A->A

NEGB

00 - B->B

DAA

UI:CA

A - i ->A

DECB

2
2

B-1->B

NEG

DEC

A-B

M->M

00 -M->M

Converts Binary Add. of BCD Characters
into BCD Format
M -l->M

EORA

AEIlM->A

EORB

BEIlM->B

M+l->M

INC
INCA

A+1->A

INCB

Load Acmltr

LDAA

B +l->B
M ->A

C6
8A

2
2

06
9A

3
3

2
2

E6
AA

5
5

2
2

F6
BA

M ->B

Dr, I nelusive

LDAB
ORAA

A+M->A

ORAB

B+M ->B

Push Data
Pull Data
Rotate Left

PSHA

A -> MSp, SP-l ->SP

PSHB

B ->MSp, SP-1->SP

PULA

SP + 1 ->SP, MSp -> A

PULB

SP + 1 ->SP, MSp -> B

RORA

~l Co

RORB

ROL

ROLA
ROLB
Rotate Right

Shift Left, Arithmetic

ROR

ASL

ASLB

Shift Right, Logic.

Store Acmltr.
Subtract

ASR

COc

ASRA

MJ
A 0

ASRB

LSR

LSRA

LSRB

STAA

A->M

STAB

B->M

•

A-M->A

B-M->B
A-B->A

SBA

Subtr. with Carry

SBCA

A-M-C->A

SBCB

B-M-C->B

Test, Zero or Minus

A->B

B->A

TSTA

A-OO

, TSTB

B -00

TST

M - 00

FIGURE 1-3-1 MC6800 Instruction Set

1-18

•

->
0->111111111 -> 0
c
b7
bo

TBA

1 I III I I I -> 0
bo
c

TAB

• •

•
•
•
•
•

Subract Acmltrs.

Transfer Acmltrs

...•

•
•
•
•

IIII(III~
<-

SUBB

0 <- I I I I I I I I 1<- 0
c
b]
bo

SUBA

IIIIIIIII~
<-

•
• •
• •
• •

•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •

ASLA
Shift Right, Arithmetic

•
•
•
•
•
•
•
•
•
•
•
•
•
•

A-M

COND CODE REG

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•

• •
• •

• •
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•

t
t
t
t
t
~
t
t t
t t
t t

R
R
R

S R

t
t
t
t
t

t t t
t t t
t t t
t R S
t R S
t t R S
t teD ®
t teD ®
t teD ®
t t t@
t @.
t + 0·
t t @.
t t R •
t

t
t
t
t

·
t

•

t
t
t
t

t
t
t
t
t
t
t

®•
®•
®•

•
•
•
•

t
t
t
t
t
t
t
t
t
t
t
t

R
R
R

t
t
t
t
t
t
t
t
t
t
t
t

R
R
R
R

t®
t®
t ®
t ®
t®
t®
t®
t@
t@
t@
t@
t@
t@
t@
t@
t R
t R
t t
t t
t t
t t
t t
t R
t R
t R
t R
t R

•
•
•

•
•
•
•
•
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t

•
•
t
t
t
t
t

•

R
R

INDEX REGISTER AND STACK
POINTER OPERATIONS MNEMONIC
Compare Index Reg
Decrement Index Reg
Decrement Stack Pntr
Increment Index Reg
Increment Stack Pntr
Load Index Reg
Load Stack Pntr
Store Index Reg
Store Stack Pntr
Indx Reg -+Stack Pntr
Stack Pntr -+ Indx Reg

CPX
DEX
DES
INX
INS
LOX
LOS
STX
STS
TXS
TSX

IMMED
OP
BC

CE
8E

DIRECT

3
3

DE
9E
OF
9F

MNEMONIC

BRA

20
24
25
27
2C
2E
22
2F

Branch Always
Branch If Carry Clear
Branch If Carry Set
Branch If = Zero
Branch If ;;. Zero
Branch If > Zero
Branch If Higher
Branch If .;;; Zero
Branch If Lower Or Same

BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BVC
BVS
BPL
BSR
JMP

Branch If < Zero
Branch If Minus
Branch If Not Equal Zero
Branch If Overflow Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutine
No Operation
Return From Interrupt
Return From Subroutine
Software Interrupt
Wait for Interrupt

CLC
CLI
CLV

OC
OE
OA

SEC
SEI
SEV
TAP

00
OF
OB
06
07

TPA

LEGEND:
Operation Code (Hexadecimal);
Number of MPU Cycles;
Number of Program Bytes;
+F
+
Arithmetic Plus;
Arithmetic Minus;
Boolean AND;
MSp Contents of memory location
pointed to be Stack Pointer;

23
20
2B
26
28
29
2A
80

4
4
5
5

2
2
2
2

EE
AE
EF
AF

Boolean Inclusive OR;
Boolean Exclusive 0 R;
Complement of M;
Transfer Into;
Bit = Zero;

EXTNO

INHER

2
2
2
2

6
6
7
7

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8

FE
BE
FF
BF

09
34
08
31

4
4
4
4

1
1
1
1

4
4

2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1

1
1

INHER

BRANCH TEST

C+ Z = 1
N $V = 1
N= 1
Z=O
V=0
V= 1
N=O

N Z V C

• •

0 t @.

7E
BD

2
2

3
9

3
3

} S.. S"';', 0 ..,,01,",

5
12

1
1
1
1

2
10

Advances Prog. Cntr. Only

2 1

• • • t
• • • •
• • • t
• • • •
• • ®t
• • ®t
• • ®t
• • ®t
• • • •
• • • •

• •

• •
• •
• •
R •
R
R
R

•
•
•

• •
• •

2 1

Z V C

•
•
•
•
•
•
•
•

• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •

•
•
•

•
•
•
•

• •
• •

•
•
•
•

• •

• •
• •
•. •
• •
• •
• •
• •
• •
• •
• •
• •
• •

--@--

} S...

,,,,,1 0,,,,,;,",

TJTIT
•

S ••••

• @ ••••

CONDITION CODE REGISTER NOTES:
(Bit set if test is true and cleared otherwise)
(Bit V) Test: Result = 10000000?
R
@ (Bit C) Test: Result = OOOOOOOO?
R
@ (Bit C) Test: Decimal value of most significant BCD Character greater than nine?
R
(Not cleared if previously set.)
S
(Bit
V)
@
Test:
Operand = 10000000 prior to execution?
S
® (Bit V) Test: Operand = 01111111 prior to execution?
S
- - - @ - - ® (Bit V) Test: Set equal to result of N $ C after shift has occurred.
0) (Bit N) Test: Sign bit of most significant (MS) byte of result = I?
®8 Bit V Test: 2's com lement overflow from subtraction of LS b tes?
® (Bit N) Test: Result less than zero? (Bit 15 = 1)
® (All) Load Condition Code Register from Stack. (See Special Operations)
V
l->C
1 -> I
l->V
A -> CCR

·1·I·r·'·I·

CCR -> A

Half-carry from bit 3;
Interrupt mask
Negative (sign bit)
Zero (byte)

•

O->C
0-+1

Byte = Zero;

M-+XH' (M + 1) -+XL
M-+SPH, (M+ 1) -+SPL
XH -+M, XL -+(M + 1)
SPH -+M, SPL -+(M + 1)
X-l-+SP
SP + 1 -+ X

None
C=O
C= 1
Z=1
N $V = 0
Z+ (N $V) = 0
C+ Z = 0
Z+(N$V)=l

BOOLEAN
OPERATION

H
I

•

(XH/XL) - (M/M + 1)
X-l-+X
SP -1 -+SP
X+l-+X
SP + 1 -+SP

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

EXTND
it

01
3B
39
3F
3E

::;:

N
Z
V
C
R

BOOLEAN/ARITHMETIC OPERATION

3
3
3
3

5
5
6
6

INDEX
OP

6E
AD

INHER

MNEMONIC

+
$

JSR
NOP
RTI
RTS
SWI
WAI

CONDITIONS CODE REGISTER

Set Overflow
Acmltr A -->CCR
CC R -> Acmltr A

RELATIVE

OPERATIONS

Clear Carry
Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask

35
30

JUMP AND BRANCH

OPERATIONS

INDEX

Overflow, 2's complement
Carry from bit 7
Reset Always
Set Always.
Test and set if true, cleared otherwise
Not Affected

CCR Condition Code Register
Least Significant
LS
Most Significant
MS

FIGURE 1-3-1 (continued)

1-19

(All)

Set according to the contents of Accumulator A.

1-3

INSTRUCTION SET
The MC6800 instructions are described in detail in the M6800 Programming Manual. This Section

will provide a brief introduction and discuss their use in developing MC6800 control programs.
The instruction set is shown in summary form in Figure 1-3-1. Microprocessor instructions are often
divided into three general classifications: (1) memory reference, so called because they operate on specific
memory locations; (2) operating instructions that function without needing a memory reference; (3) I/O
instructions for transferring data between the microprocessor and peripheral devices.
In many instances, the MC6800 performs the same operation on both its internal accumulators and
the external memory locations. In addition, the M6800 interfaces adapters (PIA and ACIA) allow the MPU to
treat peripheral devices exactly like other memory locations, hence, no I/O instructions as such are required.
Because of these features, other classifications are more suitable for introducing the MC6800's instruction set:
(1) Accumulator and memory operations; (2) Program control operations; (3) Condition Code Register
operations.
1-3.1

CONDITION CODE REGISTER OPERATIONS
The Condition Code Register (CCR), also called the Program Status Byte, will be described first

since it is affected by many of the other instructions as well as the specific operations shown in Figure 1-3.1-2.
The CCR is a 6-bit register within the MPU that is useful in controlling program flow during system operation.
The bits are defined in Figure 1-3.1-1.
The instructions shown in Figure 1-3.1-2 are available to the user for direct manipulation of the
CCR. In addition, the MPU automatically sets or clears the appropriate status bits as many of the other
instructions are executed. The effect of those instructions on the condition code register will be indicated as
they are introduced and is also included in the Instruction Set Summary of Figure 1-3-1.
b5

IHlllNlzlvlcl

Half-carry; set whenever a carry from b3 to b4 of the result is generated
by ADD, ABA, ADC; cleared if no b3 to b4 carry; not affected by other
instructions.
Interrupt Mask; set by hardware or software interrupt or SEI instruction;
cleared by Cli instruction. (Normally not used in arithmetic operations.)
Restored to a zero as a result of an RT1 instruction if 1m stored on the
stacked is low.

N = Negative; set if high order bit (b7) of result is set; cleared otherwise.
Z

Zero; set if result

= 0; cleared otherwise.

v = Overlow; set if there was arithmetic overflow as a result of the operation;
cleared otherwise.
C = Carry; set if there was a carry from the most significant bit (b7) of the
result; cleared otherwise.
FIGURE 1-3.1-1. Condition Code Register Bit Definition

1-20

CONOITIONS CODE REGISTER
OPERATIONS

MNEMONIC

BOOLEAN
OPERATION

Clear Carry

CLC

O~C

Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask

CLI
CLV
SEC
SEI

O~I

Set Overflow
Acmltr A ~ CCR

SEV
TAP

l~V
A~CCR

CCR

TPA

CCR

Acmltr A

R = Reset
S =Set
• = Not affected
CD (A LL)

-- - -- -- -- -- -- -- -- - -- - -- -- - -8
R

O~V
l~C

1 ~I

-I-I-I-l-t-

Set according to the contents of Accumulator A.

FIGURE 1-3.1-2. Condition Code Register Instructions

1-3.2

NUMBER SYSTEMS

Effective use of many of the instructions depends on the interpretation given to numerical data, that
is, what number system is being used? For example, the ALU always performs standard binary addition of two
eight bit numbers using the 2's complement number system to represent both positive and negative numbers.
However, the MPU instruction set and hardware flags permit arithmetic operation using any of four different
representations for the numbers:
(1) Each byte can be interpreted as a signed 2's complement number in the range -128 to + 127:
26

b6
0

0
1

(-128 in 2's complement)
(-1 in 2's complement)

(0 in 2's complement)

0
1

1
1

(+ 1 in 2's complement)
(+ 127 in 2's complement)

b7
1
1

1-21

(2) Each byte can be interpreted as a signed binary number in the range -127 to + 127:
26

b3
1

(-127 in signed binary)

(-1 in signed binary)

(0 in signed binary)

(+ 1 in signed binary)
(+ 127 in signed binary)

(3) Each byte can be interpreted as an unsigned binary number in the range 0 to 255:
27 2 6 2 5 24 2 3 22 21 2 0

(0 in unsigned binary)

(255 in unsigned binary)

(4) Each byte can be thought of as containing two 4-bit binary coded decimal (BCD) numbers. With
this interpretation, each byte can represent numbers in the range 0 to 99:

2°

b3
0

b4
0

(BCD 0)

(BCD 27)

(BCD 99)

The two's complement representation for positive numbers is obtained simply by adding a zero (sign
bit) as the next higher significant bit position:
27

(binary 127)

(+ 127 in 2's complement representation)

(binary 1)

( + 1 in 2's complement representation)

1-22

When the negative of a number is required for an arithmetic operation, it is formed by first
complementing each bit position of the positive representation and then adding one.
64

(+ 127 in 2's complement representation)

000

(l's complement)
(add one)
(-127 in 2's complement representation)

1
1

o
1

0
1

(0 in 2's complement representation)
(l's complement)
(add one)
("0" is same in either notation)

o
1

0
1

(+ 1 in 2's complement representation)
(l's complement)
(add one)
(-1 in 2's complement representation)

1
1

Note that while + 127 is the largest positive two's complement number that can be formed with 8
digits, the largest negative two's complement number is 10000000 or -128. Hence, with this number system,
an eight bit byte can represent integers on the real number line between -128 and + 127 and a7 can be regarded
as a sign bit; if a7 is zero the number is positive, if a7 is one the number is negative:
10000000
11111111
00000000
00000001
01111111
1'1"
I
I
I
rc
I
I~------~~~--------+--------------~--------------~------~?/~--------~
-128
-1
0
+1
+127
Since much of the literature on arithmetic operations presents the information in terms of signed
binary numbers, the difference between 2's complement and signed binary notation is of interest. Signed binary
number notation also uses the most significant digit as a sign bit (0 for positive, 1 for negative). The remaining
bits represent the magnitude as a binary number.
32

111

(-127 in signed binary)

100
000

o
o
o

0
0
0

o
o
o

1
1

( - 1 in signed binary)
(0 in signed binary)
(+ 1 in signed binary)
( + 127 in signed binary)

000
011

An 8-bit byte in this notation represents integers on the real number line between -127 and + 127:
11111111
10000001
00000000
00000001
01111111
1~______~rtl~~________~I~____________~I______________+I______~«~__----~I
-127
))
-1
0
+1
II
+127

1-23

Comparing this to the 2 's complement representation, the positive numbers are identical and the negative
numbers are reversed, i.e., -127 in 2's complement is -1 in signed binary and vice versa. In normal
programming of the MPU, the difference causes no particular problem since numerical data is automatically
converted to the correct format during assembly of the program source statements. However, if during system
operation, incoming data is in signed binary format, the program should provide for conversion. This is easily
done by first complementing each bit of the signed binary number except the sign bit and then adding one:
±

a7
1

a4
1

a3
1

a5
1

al
1

ao
1

(-127 in signed binary)

(1's complement except for sign bit)

(add 1)

(-127 in 2's complement)

The MPU instruction set provides for a simple conversion routine. For example, the following
program steps can be used:
TSTA

Test sign bit, a7, and set N if a7 = 1

BPL NEXT

NEGA

Go to NEXT if N = 0
Form 2's complement of A

40
50

ORAA % 10000000

Restore sign bit

STAA DATAl

Store data in DATAl

CONVRT

This routine assumes that the signed binary data is stored in accumulator A (ACCA). The program tests the sign
bit and if the number is negative (N= 1) performs the required conversion. The contents of ACCA and the N bit
of the Condition Code Register would be as follows after each step of a typical conversion:
Instr

TSTA

BPL NEXT

NEGA

(2's complement of ACCA)

ORAA #% 10000000

(-113 in 2's complement)

(-113 in signed binary)

Note that the sign bit status, N, is updated as the NEG and ORA instructions are executed. This is typical for
many of the instructions; the Condition Code Register is automatically updated as the instruction is executed.
1-3.3

ACCUMULATOR AND MEMORY OPERATIONS
For familiarization purposes, the Accumulator and Memory operations can be further subdivided

into four categories: (1) Arithmetic Operations; (2) Logic Operations; (3) Data Testing; and (4) Data Handling.
1-3.3.1

Arithmetic Operations
The Arithmetic Instructions and their effect on the CCR are shown in Figure 1-3.3. 1-1. The use of

these instructions in performing arithmetic operations is discussed in Section 2-1.

1-24

CONDo CODE REG.
ACCUMULATOR AND MEMORY
OPERATIONS
Add

MNEMONIC
ADDA
ADDB

Add Acmltrs
Add with Carry

A+M---+A
B + M---+B

ADCB

A+ B---+A
A+M+C---+A
B+M+C---+B

Complement, 2's
(Negate)

NEG
NEGA
NEGB

00 - M---+M
00 - A---+A
00 - B ---+ B

Decimal Adjust, A

DAA

Subtract

SUBA
SUBB

Subract Acmltrs.
Subtr. with Carry

ABA
ADCA

BOOLEAN/ARITHMETIC OPERATION
(All register labels
refer to contents)

Converts Binary Add. of BCD Characters
into BCD Format*
A-M---+A
B - M---+B

SBA
SBCA

A-M-C---+A

SBCB

B-M-C---+B

A-B---+A

N Z V

i
i
i
i

i
i
i

•
•
•
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
i
i
i
i
i

i
i
i
i

i
i
i

t t
t t t
t CD ®
t CD ®
t 0 ®
t t t @

t
t
t
t

t t t t
i

t.
i
i

i
i
i
i

*Used after ABA, ADC, and ADD in BCD arithmetic operation; each 8-bit byte regarded as containing two 4-bit
BCD numbers. DAA adds 0110 to lower half-byte if least significant number >1001 or if preceding instruction
caused a Half-carry. Adds 0110 to upper half-byte if most significant number >1001 or if preceding instruction
caused a Carry. Also adds 0110 to upper half-byte if least significant number >1001 and most significant number =9.
(Bit set if test is true and cleared otherwise)
(Bit V) Test: Result = 10000000?
@ (Bit C) Test: Result = OOOOOOOO?

(Bit C) Test: Decimal value of most significant BCD Character greater than nine?
(Not cleared if previously set.)

FIGURE 1-3.3.1-1. Arithmetic Instructions

1-25

1-3.3.2

Logic Operations

The Logic Instructions and their effect on the CCR are shown in Figure 1-3.3.2-1. Note that the
Complement (COM) instruction applies to memory locations as well as both accumulators.
1-3.3.3

Data Test Operations

The Data Test instructions are shown in Figure 1-3.3.3-1. Bit Test (BIT) is useful for updating the
CCR as if the AND function was executed but does not change the contents of the accumulator. The Test (TST)
instruction also operates directly on memory and updates the CCR as if a comparison (CMP) to zero had been
executed.
1-3.3.4

Data Handling Operations

The Data Handling instructions are summarized in Figure 1-3.3.4-1. Note that the Clear (CLR),
Decrement (DEC), Increment (INC), and Shift/Rotate instructions all operate directly on memory and update
the CCR accordingly.

1-3.4

PROGRAM CONTROL OPERATIONS

Program Control operation can be subdivided into two categories: (1) Index Register/Stack Pointer
instructions; (2) Jump and Branch operations.
1-3.4.1

Index Register/Stack Pointer Operations

The instructions for direct operation'on the MPU's Index Register and Stack Pointer are summarized
in Figure 1-3.4.1-1 Decrement (DEX, DES), increment (lNX, INS), load (LDX, LDS), and store (STX, STS)
instructions are provided for both. The Compare instruction, CPX, can be used to compare the Index Register
to a 16-bit value and update the Condition Code Register accordingly.
The TSX instruction causes the Index Register to be loaded with the address of the last data byte put
onto the "stack". The TXS instruction loads the Stack Pointer with a value equal to one less than the current
contents of the Index Register. This causes the next byte to be pulled from the "stack" to come from the
location indicated by the Index Register. The utility of these two instructions can be clarified by describing the
"stack" concept relative to the M6800 system.
The "stack" can be thought of as a sequential list of data stored in the MPU's read/write memory.
The Stack Pointer contains a 16-bit memory address that is used to access the list from one end on a
last-in-first-out (LIFO) basis in contrast to the random access mode used by ~~t! I\t!J>U's other a~~ressin~ lllod~s.
The M6800 instruction set and interrupt structure allow extensive use of the stack concept for
efficient handling of data movement, subroutines and interrupts. The instructions can be used to establish one
---

or more" stacks" anywhere in read/write memory. Stack length is limited only by the amount of memory that is
made available.

1-26

ACCUMULATOR AND MEMORY
OPERATIONS
And
Complement, l's

Exclusive OR
Or, Inclusive

MNEMONIC
ANDA
ANDB
COM
COMA
COMB
EORA

BOOLEAN ARITHME TI C OPERAT 10 N
(All register labels
refer to contents)
A _M-')oA
B - M-')oB
M~M

B ~B
AEBM~A

A+M-')oA
B+M-')oB

N Z V

t
t
t
t
t
t
t
t
t

•
•

• •
• •
• •

•
•
•
•
•
•

A~A

BEBM-')oB

EORB
ORA
ORB

CONO. CODE REG.

•
•
•
•
•
•

t
t
t
t
t
t
t
t
t

R
R
R S
R S
R S
R
R
R
R

•
•
•
•

FIGURE 1-3.3.2-1_ Logic Instructions

ACCUMULATOR AND MEMORY
OPERATIONS
Bit Test
Compare
Compare Acmltrs
Test, Zero or Minus

MNEMONIC
BITA
BITB
CMPA
CMPB
CBA
TST
TSTA
TST8

BOOLEAN I ARITHMETIC OPERATION
(All register labels
refer to contents)

CONDo CODE REG.
4

N Z V

t
t
t
t
t
t
t
t

•

•
•
•
•
•
• •
• •
• •

•
•
•
•
•

A-M
B-M
A-M
B-M
A-B
M - 00
A-DO
B - 00

FIGURE 1-3.3.3-1. Data Test Instructions

1-27

t
t
t
t
t
t
t
t

R
R

t
t
t
R

•
t
t
t

R R
R R

BOO LEAN I ARITHME TIC OP ERATION
(All register labels

ACCUMULATOR AND MEMORY
OPERATIONS

MNEMONIC

Clear

Decrement

Increment

CLRA

CLRB

DEC

M -1

DECA

A-1~A

DECB

B -1~B

INC

M +1~M

INCA

A+1~A

INCB

B +l~B

Load Acmltr

LDAA

M~A
M~B

Push Data

LDAB
PSHA

A ~ MSp, SP-1

~SP

PSHB

B ~MSp, SP-1

~SP

PULA

SP+ 1 ~SP,

MSp~A

PULB

SP + 1 ~SP,

MSp~B

Pull Data
Rotate Left

ROL
ROLA

:1
:1 ~
:1
C

ROLB
Rotate Right

ROR
RORA
RORB

Shift Left, Arithmetic

ASL
ASLA
ASLB

Shift Right, Arithmetic

Shift Right, Logic.

ASR

ASRB

LSRA

Store Acmltr.
Transfer Acmltrs

STAB
TAB

A~B

TBA

B~A

(Bit V) Test: Operand

®
®

(Bit V) Test: Operand

C211111111

LSRB
STAA

11111111

+D +- 111111111+-0
C
b7
bo

ASRA
LSR

+- I I I I I I I I I : J
b7
+bo

D
C

O~IIIIIIIII
b7

D
C

A~M

B~M

= 10000000 prior to execution?
= 01111111 prior to execution?

(Bit V) Test: Set equal to result of N E9 C after shift has occurred.

FIGURE 1-3.3.4-1. Data Handling Instructions

1-28

H I

refer to contents)

CLR

CONDo CODE REG.

•
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2 1

N Z V

S R

t
t
t
t
t
t
t
t

t @
t @
t @
t ®
t ®
t ®
t R
t R

•
•

•
•
•
•

t
t
t
t
t
t
t
t
t
t
t
t

R
R
R

t
t
t
t

•
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•
•
•
•
• •
• •
• •
• •

t ® t
t ® t
t ® t
t ® t
t ® t
t ® t
t ® t
t ® t
t ® t
t ® t
t ® t
t ® t
t @ t
t ® t
t ® t
t R
t R
t R
t R

•
•
•
•

INDEX REGISTER AND STACK
POINTER OPERATIONS

MNEMONIC

BOOLEAN/ARITHMETIC OPERATION

Compare Index Reg

CPX

Decrement Index Reg

DEX

X-1~X

(XH/Xd - (M/M + 1)

Decrement Stack Pntr

DES

SP - 1 ~SP

I ncrement I ndex Reg

INX

X + 1 ~X

I ncrement Stack Pntr

INS

SP + 1 ~SP

Load Index Reg

LOX

M ~XH' (M + 1) ~XL

Load Stack Pntr

LOS

M ~SPH' (M + 1) ~SPL

Store I ndex Reg

STX

XH ~M, XL ~(M + 1)

Store Stack Pntr

STS

SPH ~M, SPL ~(M + 1)

Indx Reg

~Stack

Pntr

TXS

X - 1 ~SP

Stack Pntr ~ Indx Reg

TSX

SP + 1 ~ X

(Bit N) Test: Sign bit of most significant (MS) byte of result = 11

®
®

(Bit V) Test: 2's complement overflow from subtraction of LS bytes?
(Bit N) Test: Result less than zero? (Bit 15 = 1)

FIGURE 1-3.4.1-1. Index Register and Stack Pointer Instructions

1-29

•
•
•
•
•
•
•
•
•
•
•

•
• • •
• • • •
• t • •
• • • •
® t R •
® t R •
® t R •
® t R •
• • • •
• • • •
CD

t
t

Operation of the Stack Pointer with the Push and Pull instructions is illustrated in Figures 1-3.4.1-2
& 1-3.4.1-3. The Push instruction (PSHA) causes the contents of the indicated accumulator (A in this example)
to be stored in memory at the location indicated by the Stack Pointer. The Stack Pointer is automatically
decremented by one following the storage operation and is "pointing" to the next empty stack location. The

MPU

ACCA

m -2

m -2
m -1
SP

----l.~

m +2

New Data

m +1
Previously
Stacked
Data

SP ---.. m -

Previously
Stacked
Data

m++21

m+3

PC~

PSHA
PC

(a) Before PSHA

Next I nstr.

(b) After PSHA

FIGURE 1-3.4.1-2. Stack Operation, Push Instruction

1-30

MPU

ACCA

m -2

m -1

SP~m

Previously
Stacked
Data

f ::~

1
m

SP ~ m

Previously
Stacked
Data

1A
3C

m +2

D5
EC

PC~

PULA
PC

(a) Before PULA

Next Instr.

(b) After PULA

FIGURE 1-3.4.1-3. Stack Operation, Pull Instruction

1-31

JUMP AND BRANCH
OPERATIONS

MNEMONIC

BRANCH TEST

Branch Always
Branch If Carry Clear

BRA

None

BCC

Branch If Carry Set
Branch If = Zero

BCS
BEQ

C=O
C= 1
Z= 1
NEBV=O

Branch If

Zero

BGE

Branch If > Zero
Branch If Higher

BGT
BHI

Z + (N EB V) = 0

BLE

C+ Z = 0
Z + (N EB V)

Branch If Lower Or Same
Branch If < Zero

BLS
BlT

C+ Z = 1
NEBV=l

Branch If Minus

BMI

N= 1

Branch If Not Equal Zero

BNE

Z=O

Branch If Overflow Clear

BVC

Branch If Overflow Set

BVS

V=O
V=1
N=O

Branch !f

Zero

Branch If Plus

BPL

Branch To Subroutine
Jump

BSR
JMP

Jump To Subroutine

JSR

No Operation

NOP

Return From Interrupt

RTI

Return From Subroutine
Software Interru pt

RTS
SWI

Wait for Interrupt

WAI

} See Special Operations
Advances Prog. Cntr. Only

N Z V

•
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•
•

• •
• •

.. ..

--(2)--

} See special Operations

(AiD

Load Condition Code Register from Stack. (See Special Operations)

(Bit I)

Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is
required to exit the wait state.

FIGURE 1-3.4.2-1. Jump and Branch Instructions

1-32

• • • • • •
• S • • • •
•®• • • •

Pull instruction (PULA or PULB) causes the last byte stacked to be loaded into the appropriate accumulator.
The Stack Pointer is automatically incremented by one just prior to the data transfer so that it will point to the
last byte stacked rather than the next empty location. Note that the Pl.:JLL instruction does not "remove" the
data from memory; in the example, 1A is still in location (m+ 1) following execution of PULA. A subsequent
PUSH instruction would overwrite that location with the new "pushed" data.
Execution of the Branch to Subroutine (BSR) and Jump to Subroutine (JSR) instructions cause a
return address to be saved on the stack as shown in Figures 1-3.4.2-3 through 1-3.4.2-5. The stack is
decremented after each byte of the return address is pushed onto the stack. For both of these instructions, the
return address is the memory location following the bytes of code that correspond to the BSR and JSR
instruction. The code required for BSR or JSR may be either two or three bytes, depending on whether the JSR
is in the indexed (two bytes) or the extended (three bytes) addressing mode. Before it is stacked, the Program
Counter is automatically incremented the correct number of times to be pointing at the location of the next
instruction. The Return from Subroutine instruction, RTS, causes the return address to be retrieved and loaded
into the Program Counter as shown in Figure 1-3.4.2-6.
There are several operations that cause the status of the MPU to be saved on the stack. The Software
Interrupt (SWI) and Wait for Interrupt (WAI) instructions as well as the maskable (IRQ) and non-maskable
(NMI) hardware interrupts all cause the MPU's internal registers (except for the Stack Pointer itself) to be
stacked as shown in Figure 1-3.4.2-7. MPU status is restored by the Return from Interrupt, RTI, as shown in
Figure 1-3.4.2-8.
1-3.4.2

Jump and Branch Operations
The Jump and Branch instructions are summarized in Figure 1-3.4.2-1. These instructions are used

to control the transfer of operation from one point to another in the control program.
The No Operation instruction, NOP, while included here, is ajump operation in a very limited sense.
Its only effect is to increment the Program Counter by one. It is useful during program development as a
"stand-in" for some other instruction that is to be determined during debug. It is also used for equalizing the
execution time through alternate paths in a control program.
Execution of the Jump Instruction, JMP, and Branch Always, BRA, effects program flow as shown
in Figure 1-3.4.2-2. When the MPU encounters the Jump (Indexed) instruction, it adds the offset to the value
in the Index Register and uses the result as the address of the next instruction to be executed. In the extended
addressing mode, the address of the next instruction to be executed is fetched from the two locations
immediately following the JMP instruction. The Branch Always (BRA) instruction is similar to the JMP
(extended) instruction except that the relative addressing mode applies and the branch is limited to the range
within -125 or + 127 bytes of the branch instruction itself (see Section 1-2.3.4 for a description of the
addressing modes). The opcode for the BRA instruction requires one less byte than JMP (extended) but takes
one more cycle to execute.
The effect on program flow for the Jump to Subroutine (JSR) and Branch to Subroutine (BSR) is
shown in Figures 1-3.4.2-3 through 1-3.4.2-5. Note that the Program Counter is properly incremented to be
pointing at the correct return address before it is stacked. Operation of the Branch to Subroutine and Jump to
Subroutine (extended) instruction is similar except for the range. The BSR instruction requires less opcode than
JSR (2 bytes versus 3 bytes) and also executes one cycle faster than JSR. The Return from Subroutine, RTS, is
used at the end of a subroutine to return to the main program as indicated in Figure 1-3.4.2-6.
The effect of executing the Software Interrupt, SWI, and the Wait for Interrupt, WAI, and their

1-33

INDXD

Main Program
6E = JMP
K:::: Offset

PC
n
n+1

..•

EXTND

Main Program
PC
n
7E = JMP
n+1 KH = Next Address
n+2 KL = Next Address

••
.

X+K

Next Instruction

Main Program
n
n+ 1
(n + 2) ±K

21>= BRA
K = Offset*

Next Instruction
*K = Signed 7-bit value

(a) Jump

(b) Branch

FIGURE 1-3.4.2-2. Program Flow for Jump and Branch Instructions

---

-------

m-2

m -1

m -1
SP~

m +1

PC~

n+1
n+2

m +1

+ 2)H

+ 2)L
7E

BSR
n

±K = Offset"

+ 1

n+2

Next Main Instr.

.. K = Signed 7-Bit Value

PC-+-(n

+ 2)

±K

BSR
±K = Offset
Next Main Instr .

1st Subr. Instr.

(b) After Execution

(a) Before Execution

FIGURE 1-3.4.2-3. Program Flow for BSR

1-34

-----

m-2

----

m -3
SP--m - 2

(n + 3)H

m -1

SP--"m

(n + 3)L

m+ 1

m +2

L---PC~n

JSR

= BD

JSR

n + 1

= Subr.

Addr.

n + 1

= Subr.

Addr.

n+2

= Subr.

Addr.

n+2

= Subr.

Addr.

n+3

Next Main Instr.

n+3

Next Main Instr.

(a) Before Execution

1st Subr. Instr.

(S formed from
SH and SL)

(b) After Execution

FIGURE 1-3.4.2-4. Program Flow for JSR (Extended)

---

m -2

sp~m-2

m-1

m -1

+ 2)H

+ 2)L

---+- m
7E

m +1

PC--n

JSR

n + 1

= AD

JSR = AD
n + 1

= Offset'

n+2

Next Main Instr.

n+2

•K

= 8·Bit

7E
7A
~

Unsigned Value

PC--x' + K

= Offset

Next Main Instr.

1st Subr. Instr.

'Contents of Index Register
(b) After Execution

(a) Before Execution

FIGURE 1-3.4.2-5. Program Flow for JSR (Indexed)

1-35

m-2

SP~m-2

m -1
m

m +1

+ 3)H

+ 3)L

m -1

SP----" m

7E
7A~

-----

_ __

JSR = BD

SH = Subr. Addr.

n+2

SL = Subr. Addr.

PC~n+3

Next Main Instr.

JSR = BO

n + 1

SH = Subr. Addr.

n+2

SL = Subr. Addr.

n+3

Next Main Instr.

-Last Subr. I nstr.

Last Subr. Instr.

RTS

(a) Before Execution

(b) After Execution

FIGURE 1-3.4.2-6. Program Flow for RTS

1-36

Software Interrupt
Main Program
n
n+ 1

3F =SWI
Next Main Instr.

Wait For
Interrupt
Main Program
3E = WAI
Next Main Instr.

Hardware Interrupt or
Non-Maskable Interrupt (NM I)
Main Program

YES

Continue Main Prog_
n+1

Next Main Instr .

Stack
SP

m -7

-7

m -6

m -5
m -4
m -3
m -2
m -1
m

SWI

Condition Code
Acmltr. B
Acmltr. A
Index Register (XH)
Index Register (XL)
PC(n + 1)H
PC(n + 1)L

HDWR
INT

WAI

NMI

FFFA
FFFB

NMI

FFFC
FFFD

FFF8
FFF9

Interrupt Memory Assignment 1
FFF8
FFF9
FFFA
FFFB
FFFC
FFFD
FFFE
FFFF

Constant, Hdware
Constant, Hdware
Software
Software
Non-Maskable Int.
Non-Maskable Int_
Restart
Restart

MS
LS
MS
LS
MS

....--J"'.....

L..-.-V

LS
MS
LS

First Instr.
Addr. Formed
By Fetching
2-Bytes From
Per. Mem_
Assign_

NOTE: MS = Most Significant Address Byte;
LS = Least Significant Address Byte;

load Interrupt
Vector Into
Program Counter

1st Interrupt Instr.

FIGURE 1-3.4.2-7. Program Flow for Interrupts

1-37

relationship to the hardware interrupts is shown in Figure 1-3.4.2-7. SWI causes the MPU contents to be
stacked and then fetches the starting address of the interrupt routine from the memory locations that respond to
the addresses FFFA and FFFB. Note that as in the case of the subroutine instructions, the Program Counter is
incremented to point at the correct return address before being stacked. The Return from Interrupt instruction,
RTI, (Figure 1-3.4.2-8) is used at the end of an interrupt routine to restore control to the main program. The
SWI instruction is useful for inserting break points in the control program, that is, it can be used to stop
operation and put the MPU registers in memory where they can be examined. The WAI instruction is used to
decrease the time required to service a hardware interrupt; it stacks the MPU contents and then waits for the
interrupt to occur, effectively removing the stacking time from a hardware interrupt sequence.

SP ___ m-7

m -7

m -6

CCR

m-6

CCR

m -5

ACCB

m - 5

ACCB

m -4

ACCA

m -4

ACCA

m -3

XH (Index Reg)

m -3

m -2

XL (Index Reg)

m -2

m -1

PC(n+1)H

m -1

PCH

PC(n+1 )l

PCl

sp-.-.

n +1

PC-

n + 1

PC~

(b) After Execution

(a) Before Execution

FIGURE 1-3.4.2-8. Program Flow for RTI

1-38

BMI
BPL

N= 1
N=

BEQ
BNE

Z=1
Z=

BVC :
BVS :

V=
V= 1

BCC
BCS

C=
C=1

BHI
BLS

C+Z=
C+Z=1

BLT
BGE

NEBV= 1
NEBV= ;

BLE
BGT

Z + (N EBV) = 1
Z+ (NEBV) =

FIGURE 1-3.4.2-9. Conditional Branch Instructions

The conditional branch instructions, Figure 1-3.4.2-9, consist of seven pairs of complementary
instructions. They are used to test the results of the preceding operation and either continue with the next
instruction in sequence (test fails) or cause a branch to another point in the program (test succe~ds).
Four of the pairs are used for simple tests of status bits N, Z, V, and C:
(1) Branch On Minus (BMI) and Branch On Plus (BPL) tests the sign bit, N, to determine if the
previous result was negative or positive, respectively.
(2) Branch On Equal (BEQ) and Branch On Not Equal (BNE) are used to test the zero status bit, Z,
to determine whether or not the result of the previous operation was equal to zero. These two
instructions are useful following a Compare (CMP) instruction to test for equality between an
accumulator and the operand. They are also used following the Bit Test (BIT) to determine
whether or not the same bit positions are set in an accumulator and the operand.
(3) Branch On Overflow Clear (BVC) and Branch On Overflow Set (BVS) tests the state of the V
bit to determine if the previous operation caused an arithmetic overflow.
(4) Branch On Carry Clear (BCC) and Branch On Carry Set (BCS) tests the state of the C bit to
determine if the previous operation caused a carry to occur. BCC and BCS are useful for testing
relative magnitude when the values being tested are regarded as unsigned binary numbers, that
is, the values are in the range 00 (lowest) to FF (highest). BCC following a comparison (CMP)
will cause a branch if the (unsigned) value in the accumulator is higher than or the same as the
value of the operand. Conversely, BCS will cause a branch if the accumulator value is lower
than the operand.
The fifth complementary pair, Branch On Higher (BHI) and Branch On Lower or Same (BLS) are in
a sense complements to BCC and BCS. BHI tests for both C and Z = 0; if used following a CMP, it will cause a
branch if the value in the accumulator is higher than the operand. Conversely, BLS will cause a branch if the
unsigned binary value in the accumulator is lower than Of the same as the operand.
The remaining two pairs are useful in testing results of operations in which the values are regarded as
signed two's complement numbers. This differs from the unsigned binary case in the following sense: In
unsigned, the orientation is higher or lower; in signed two's complement, the comparison is between larger or
smaller where the range of values is between -128 and + 127 (see Section 1-3.2 for a review of number
systems).
Branch On Less Than Zero (BLT) and Branch On Greater Than Or Equal Zero (BGE) test the status
bits for NEB V = 1 and NEB V = 0, respectively. BLT will always cause a branch following an operation in

1-39

which two negative numbers were added. In addition, it will cause a branch following a CMP in which the value
in the accumulator was negative and the operand was positive. BLT will never cause a branch following a CMP
in which the accumulator value was positive and the operand negative. BGE, the complement to BLT, will
cause a branch following operations in which two positive values were added or in which the result was zero.
The last pair, Branch On Less Than Or Equal Zero (BLE) and Branch On Greater Than Zero (BGT)
test the status bits for Z

+ (N EB V) =

1 and Z

+ (N EB V) = 0, respectively. The action ofBLE is identical to

that for BLTexcept that a branch will also occur if the result of the previous result was zero. Conversely, BGTis
similar to BGE except that no branch will occur following a zero result.

1-40

CHAPTER 2
2.

PROGRAMMING TECHNIQUES

The objective of this Chapter is to present examples of programs and techniques that have been
found useful in developing control programs for the MC6800 MPU. Much of the material in subsequent
Chapters also covers programming methods. I/O techniques are discussed in Chapter 3. Chapter 5 is devoted to
peripheral programming; Chapter 6 discusses system integration programming techniques. In this Chapter, the
emphasis is on three programming areas: (1) arithmetic processing; (2) counter and delay operations; (3) use of
the indexed addressing mode. In addition, Section 2-3 presents techniques for determining if a given program is
usable and/or efficient for a particular application.

2-1

ARITHMETIC OPERATION

2-1. 1

NUMBER SYSTEMS

The ALU always performs standard binary addition of two eight bit numbers with the numbers
represented in 2's complement format. However, the MPU instruction set and hardware flags permit arithmetic
operation using any of four different representations for the numbers:
(1) Each byte can be interpreted as a signed 2's complement number in the range -127 to
±

b7
1

b6
0
1
0
0
1

b5
0
1
0
0
1

b4
0
1
0
0
1

b3
0
1
0
0
1

b2
0
1
0
0
1

b1
0
1
0
0
1

bo
1
1
0
1
1

1
0
0
0

+ 127:

(-127 in 2's complement representation)
(-1 in 2's complement representation)
(0 in 2's complement representation)
(+ 1 in 2's complement representation)
(+ 127 in 2's complement representation)

(2) Each byte can be interpreted as an unsigned binary number in the range 0 to 255:
27

b7
0
1

b6
0
1

b5
0
1

b4
0
1

b3
0
1

b2
0
1

b1
0
1

bo
0
1

(0 in unsigned binary)
(255 in unsigned binary)

(3) Each byte contains one 4-bit BCD number in the 4 LSBITS, the 4 MS bits are zeros. This is

referred to as unpacked BCD and can represent numbers in the range of 0-9:
27

b7
0
0
0

b6
0
0
0

b5
0
0
0

b4
0
0
0,

b3
0
0
1

b2
0
1
0

b1
0
0
0

bo
0
1
1

Always must be 0
2-1

(BCD 0)
(BCD 5)
(BCD 9)

(4) Each byte can be thought of as containing tw04-bit binary coded decimal (BCD) numbers. With
this interpretation, each byte can represent numbers in the range 0 to 99:
23
b7
0
0
1

b6
0

bs
0

20
b4
0

0
0

1
0

0
1

b3
0
0
1

b2
0

b1
0

1
0

20
bo
0
1
1

(BCD 00)
(BCD 27)
(BCD 99)

Each of these number systems will be illustrated with programming examples after the condition
code flags and instruction set have been introduced in more detail.

THE CONDITION CODE REGISTER

2-1.2

During operation, the MPU sets (or clears) flags in a Condition Code Register as indicated in Table
2-1.2-1:
bs
H

I I I N I z I V I C I Condition Code Register

H = Half-carry; set whenever a carry from b3 to b4 of the result is generated; cleared otherwise.
I = !nterrupt Mask; set by hardware interrupt or SEI instruction; cleared by CLI instruction. (Normally not
used in arithmetic operations).
N = Negative; set if high order bit (b7) of result is set; cleared otherwise.
Z = Zero; set if result = 0; cleared otherwise.
V = 0 Verflow; set if there was arithmetic overflow as a result of the operation; cleared otherwise.
C =

~arry;

set if there was a carry from the most significant bit (b7) of the result; cleared otherwise.

TABLE 2-1.2-1: Condition Code Register
2-1.3

OVERFLOW

The description of most of the condition code bits is straight forward. However, overflow requires
clarification. Arithmetic overflow is an indication that the last operation resulted in a number beyond the ± 127
range of an 8-bit byte. Overflow can be determined by examining the sign bits of the operands and the result as
indicated in Table 2-1.2-1 where the results for addition of A + B is shown.
Row
1
2
3
4

5
6
7
8

a7
0
0

b7
0
0

r7
0
1

0
0
1
1
1
1

1
1

0
1
0
1
0
1

0
0
1
1

0
1
0
0
0
0
1
0

+ B)

= R

TABLE 2-1.3-1: Overflow for Addition
2-2

If the sign bits of the operands, a7 and b7, are different (rows 3 through 6 of the Table) no overflow can occur

and the V flag is clear after the operation. If the operand sign bits are alike and the result exceeds the byte
capacity, the sign bit of the result (r7) will change and the overflow bit will be set. This is illustrated in the
following example. The example follows actual ALU operation in that the starting number A is initially in the
accumulator but is replaced by the result of the current operation.

6
0
0

5
1
0

7
0
1

1
1

1
0

3
0
0

1
1

0
0
1

1
0
0

1
1
1

0
1

0
1
0

1
1
0

7
1
1
0

6
0
1
1

5
0
1

4
1

3
1

2
1

1
0

0
0

0
1

0
0

A = +54;
B = -121; (negative numbers are in 2's complement
notation)
Ro= A + B = -67; (signs of A & B different; no
overflow)
Ro= -67;
B = -33;
Rl = Ro + B = - 100; (Signs alike but byte capacity
not exceeded; no. overflow)

Rl= -100;
B = -32;
R2= + 124 (Signs of Rl & B alike and sign of result
occurred)

Here the capacity of the register has been exceeded and the result is + 124 rather than -132. Overflow is said to
have occurred.
In subtraction operations, the possibility of overflow exists whenever the operands differ in sign.
Overflow conditions For A - B are illustrated in Table 2-1.3-2.
Row
1
2

a7
0

b7
0
0

r7
0
1

1
1

0
1

0
0

0
1

3
4

0
0
0

5
6

1
1

0
0

0
1

0
0

7
8

1
1

0
1

1
0

(A - B) = R

TABLE 2-1.3-2: Overflow for Subtraction
Note that Table 2-1.3-2 is identical to the addition table except that b7has been replaced by b7. This is explained
by the fact that the ALU performs subtraction by adding the negative of the subtrahend B to the minuend A.
Hence, the ALU first forms the 2's complement of B and then adds. The subtraction table with b7 negated then

2-3

reflects the sign bits of two numbers that are to be added. If a7 and b7 are alike, overflow will occur if the byte
capacity is exceeded.
2-1.4

THE ARITHMETIC INSTRUCTIONS
Table 2-1.4-1 summarizes the instructions used primarily for arithmetic operations. The effect of

each operation on memory and the MPU' s Accumulators is shown along with how the result of each operation
effects the Condition Code Register.
The carry bit is used as a carry for addition and as a borrow for subtraction and is added to the
Accumulators with the Add With Carry Instructions and subtracted from the Accumulators in the Subtract With
Carry instructions.
The Decimal Adjust instruction, DAA, is used in BCD addition to adjust the binary results of the
ALU. Used following the operations, ABA, ADD, and ADC on BCD operands, DAA will adjust the contents
of the accumulator and the C bit to represent the correct BCD Sum.
Table 2-1.4-2 shows the details of the DAA instruction and how it affects and is effected by the
Condition Code Register bits.

Use of Arithmetic Instructions

2-1.4.1

Typical use of the arithmetic instructions is illustrated in the following examples:
The ABA instruction adds the contents of ACCB to the contents of ACCA:
ACCA

10101010

($AA)

ACCB
ACCA
CARRY

11001100
01110110
1

($CC)
($76) with a carry.

The ADCA instruction adds the operand data and the carry bit to ACCA:
b7

ACCA
OPERAND DATA

1
1

0
1

1
0

0
0

1
1

0
1

$AA

CARRY
ACCA

0
1

1
1

$77 with carry

CARRY

In both of these examples, the 2's complement overflow bit, V, will be set as shown in Table
2-1.4.1-1.

2-4

CONDo CODE REG.

ADDRESSING MODES

OPERATIONS

MNEMONIC

ADDA
ADDB
ABA
ADCA
ADCB
COM
COMA
COMB
NEG
NEGA
NEGB

8B
CB

2
2

3
3

2
2

89
C9

2
2

99
09

3
3

2
2

A9
E9
63

Add
Add Acmltrs
Add with Carry
Complement, 1's

Complement, 2's
( Negate

DAA

Rotate Left

ROL
ROLA
ROLB

ROR
RORA
RORB
ASL
ASLA
ASLB
ASR
ASRA

Shift Left, Arithmetic

Shift Right, Arithmetic

Shift Right, Logic,

2
2

BB
FB

4
4

3
3

2
2
2

B9
F9
73

3
3
3

ASRB
LSR
LSRA
LSRB

5
7

4
6

2
2

AO
EO

5
5

2
2

BO
FO

4
4

3
3

82
C2

2
2

92
02

3
3

2
2

A2
E2

2
2

B2
F2

4
4

3
3

LEGEND:
Operation Code (Hexadecimal);
OP
Number of MPU Cycles;
Number of Program Bytes;
#
Arithmetic Plus;
+
Arithmetic Minus;
Boolean AND;
MSp Contents of memory location
pointed to be Stack Pointer;

Byte = Zero;

H
I

Half·carry from bit 3;

Ell

1
1

40
50

2
2

1
1

C
R
S

•

A+M--+A
B+M--+B
A+B--+A
A+M+C--+A
B+M+C--+B
M--+M
A--+A
B--+B
00 - M--+M
00 - A--+A
00 - B --+ B
Converts Binary Add, of BCD Characters
into BCD Format

2
2

1
1

:1 CO

46
56

2
2

1
1

:l
B

48
58

2
2

1
1

:I
A

44
54

2
2

1
1

BOOLEAN/ARITHMETIC OPERATION
(All register labels
refer to contents)

49
59

3
3

Boolean Inclusive OR;
Boolean Exclusive OR;
Complement of M;
Transfer Into;
Bit = Zero;

2
2

90
DO

43
53

2
2

N
Z

2
2

80
CO

Subract Acmltrs.
Subtr. with Carry

SUBA
SUBB
SBA
SBCA
SBCB

Subtract

Decimal Adjust, A

Rotate Right

INHER

EXTND

INDEX

DIRECT

IMMED

ACCUMULATOR AND MEMORY

"}
;}
B

<- [UIIIlIJ:J
b7
A
B-M-C-->B

N Z V

t
t
t
t
t

•
•

t
t

•

t
t

t
t
t
t
t

•
•

t t
t

t
t
t
t
t

t
t
t
t
t
t

t
t R S
t R S
t R S
tQ) 0
teD 0
teD 0

• •
• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •

t t ® t
t t ® t
t t ® t
t t ® t
t t ® t
t t ® t
t t® t
t t ® t
t t® t
t t® t
t t® t
t t® t
R t® t
R t® t
R t® t
t t t t
t t t t
t t t t
t

t t

• •

t t

• •

t @

t
t

CONDITION CODE REGISTER NOTES:
(Bit set if test is true and cleared otherwise)

Interrupt mask
Negative (sign bit)
Zero (byte)
Overflow, 2's complement
Carry from bit 7
Reset Always
Set Always
Test and set if true, cleared otherwise

@
@

(Bit V) Test: Result = 10000000?
(Bit C) Test: Result = OOOOOOOO?
(Bit C) Test: Decimal value of most significant BCD Character greater than nine?
(Not cleared if previously set.)

(Bit V) Test: Set equal to result of N Ell Cafter shift has occurred.

Not Affected

CCR Condition Code Register
Least Significant
LS
MS Most Significant

TABLE 2-1.4-1. Arithmetic Instructions

2-5

Operation: Adds hexadecimal numbers 00, 06, 60, or 66 to ACCA, and may also set the carry
bit, as indicated in the following table:
State of
C-Bit
Before DAA
(Col. 1)

Upper
Half-Byte
(Bits 4-7)
(Col. 2)

Initial
Half-Carry
H-Bit
(Col. 3)

Lower
Half-Byte
(Bits 0-3)
(Col. 4)

Number Added
to ACCA
by DAA
(Col. 5)

State of
C-Bit
After DAA
(Col. 6)

0
0
0

0-9
0-8
0-9

0
0

0-9
A-F
0-3

00
06
06

0
0
0

A-F
9-F
A-F

0
0

0-9
A-F
0-3

60
66
66

0-2
0-2
0-3

0
0

0-9
A-F
0-3

60
66
66

NOTE: Columns (1) to (4) of the above table represent all possible cases which can result from
any of the operations ABA, ADD, or ADC, with initial carry either set or clear, applied
to two binary-coded-decimal operands. The table shows hexadecimal values.
Effect on Condition Code Register:
H Not affected.
I Not affected.
N Set if most significantbit of the result is set; cleared otherwise.
Z Set if all bits of the result are cleared; cleared otherwise.
V Not defined.
C Set or reset according to the same rule as if the DAA and an immediately preceding ABA,
ADD, or ADC were replaced by a hypothetical binary-coded-decimal addition.

TABLE 2-1.4-2. Effect of DAA Instruction

2-6

2's complement

b7
ACC

b7
OPERAND (OR ACCB)

overflow

carry

b7
ACC

after

before

1
0
0
0
0
1
0

0
0
1

1
1
0
1
0
0
1

0
0

0
1
1

0
1
1
1

0
1
1
1
1

0
0
1
1

TABLE 2-1.4.1-1 Truth Table for "Add with Carry"

The SUBA instruction subtracts the operand data from ACCA:
b7

ACCA

$65

OPERAND DATA

1
1

0
0

ACCA
BORROW

0
1

$87
$DE with a borrow

The SBCA instruction subtracts the operand and the borrow (carry) it from ACCA.

ACCA
OPERAND DATA

$BC

1
1

$7B

1
0
0

C=l
$40 no borrow

BORROW (carry)
0

BORROW

The 2's complement overflow and carry bits are set in accordance with Table 2-1.4.1-2 as a result of
a subtraction operation.

2-7

2's
complement

carry

b7
ACCA

overflow

after

b7
ACCA
before

0
0

0
1

0
1
1
0

1
1

0
1
0

0
0
0

1
0
1

0
1
1

0
0

b7
OPERAND
0
0
1
1

before

0
0

1
1
0
0
0
1
1
1
1
0
TABLE 2-1.4.1-2: Truth Table for "Subtract with Borrow"

2-1.5

ADDITION AND SUBTRACTION ROUTINES

Most MPU based systems will require that the arithmetic instruction set be combined into more
complex routines that operate on numbers larger than one byte. If more than one number system is used,
routines must be written for each, or conversion routines to some common base must be used. In many cases,
however, it is more efficient to write a specialized routine for each system requirement, i.e., hexadecimal
(HEX) versus unpacked BCD multiplication, etc. In this section, several algorithms will be discussed with
specific examples showing their implementation with the MC6800 instruction set.
The basic arithmetic operations are binary addition and subtraction:
ALPHA + BETA
LDAA
ADDA
STAA

= GAMMA

ALPHA - BETA

= GAMMA

ALPHA
BETA

LDAA
SUBA

ALPHA
BETA

GAMMA

STAA

GAMMA

These operations are so short that they are usually programmed in line with the main flow. Addition
of single packed BCD bytes requires only one more instruction. The DAA instruction is used immediately after
the ADD, ADC, or ABA instructions to adjust the binary generated in accumulator A (ACCA) to the correct
BCD value:

Carry
X
X
0

LDAA

ALPHA

ADDA
DAA

BETA

STAA

GAMMA

ACCA
67
+79
146

01100111
carry 0111 1001
o 11100000

1 0100 0110

= ACCA
=

MEMORY

= ACCA
= ACCA

binary result
after DAA; the carry bit will also be set
because of the BCD carry.

2-8

Since no similar instruction is available for BCD subtraction, 10's complement arithmetic may be
used to generate the difference. The follow routine performs a BCD subtraction of two digit BCD numbers:
LDAA
SUBA
SEC
ADCA
DAA
STAA

#$99
BETA
ALPHA
GAMMA

(99-BETA) = ACCA
carry = 1
ACCA + ALPHA + C = ACCA
DECIMAL ADJUST (-100)
ALPHA-BETA = GAMMA

The routine implements the algorithm defined by the following equations.
ALPHA - BETA = GAMMA
ALPHA + (99-BETA) -99 = GAMMA
ALPHA + (99-BETA+1) -100 = GAMMA

9's COMPLEMENT OF BETA
10's COMPLEMENT OF BETA

One is added to the 9's complement of the subtrahend by setting the carry bit to find the 10's complement of
BETA which is then added to the minuend ALPHA and saved in ACCA. The DAA instruction adjusts the result
in ACCA to the proper BCD values before storing the difference in GAMMA. Since 100 has been added (99 +
1) to the subtrahend by finding the 10's complement, 100 must also be subtracted. This is accomplished by the
DAA instruction since the resulting carry is discarded.
Multiple precision operations mean that the data and results require more than one byte of memory.
The simplest multiple precision routines are addition and subtraction of 16 bit binary or 2's complement
numbers. This is often called double precision since 2 consecutive bytes are required to store 16 binary bits of
information. The following routines illustrate these functions:
LDAA
LDAB
ADDA
ADCB
STAA
STAB

ALPHA +1
ALPHA
BETA +1
BETA
GAMMA +1
GAMMA

ADD LS BYTES
ADD MS BYTES WITH CARRY FROM LS BYTES

LDAA

ALPHA +1
ALPHA
BETA +1
BETA
GAMMA +1
GAMMA

SUBTRACT LS BYTES
SUBTRACT MS BYTES WITH BORROW FROM LS BYTES

LDAB
SUBA
SBCB
STAA
STAB

Four digit BCD addition can be accomplished in a similar fashion with the use of the DAA
instruction. The following routine has been expanded to a 2N digit addition where N is the max number of
packed BCD bytes used:

2-9

START
LOOP

CLC
LDX
LDAA
ADCA
DAA
STAA
DEX
BNE

#N
ALPHA ,X
BETA ,X
GAMMA ,X
LOOP

NOTE: ALPHA, BETA, and GAMMA must be in the direct addressing range and adjusted for
offset for this example (See indexed addressing for further details).
This routine uses indexed address to select the bytes to be added, starting with the least significant.
The carry is cleared at the start and is affected only by the DAA and ADCA instructions. This allows the carry to
be included in the next byte addition.
Expanding sllbtraction to multiple precision is accomplished in a manner similar to the single byte
case; 10's complement arithmetic is used. A suitable routine is shown in the Assembly Listing of Figure
2-1.5-1.
This routine first finds the 9's complement of the subtrahend and stores it in the result buffer. The
carry is then set to add 1 to 9's complement, making it the 10's complement which is then added to the minuend
and stored in the result buffer. Note that this routine has 2 loops, the first to calculate the 9's complement, the
second to add anddecimal adjust the result. The decimal add and subtract routines operate on 10's complement
numbers as well as packed BCD numbers. A number is known to be negative in 10's complement form when
the most significant digit in the most significant byte is a 9. When in the 10's complement form, this digit is
reserved for the sign and the actual number of magnitude digits is one less than 2 times the number of bytes. A
routine similar to the above subtract program will convert the 10's complement number to decimal magnitude
with sign for display or output purposes:
DCONV

DCONVl

DCONV2

END

CLR
LDAA
BPL
LDX
LDAA
SUBA
STAA
DEX
BNE
LDX
CLRA
SEC
ADCA
DAA
STAA
DEX
BNE
DEC
RTS

SINFLG
RESULT+l
END
#8
#$99
RSLT,X
RSLT,X

CLEAR SIGN FLAG
GET MSBYTE
POSITIVE: END
NEGATIVE:
SUBTRACT RESULT FROM
ALL 9's INCLUDING
SIGN DIGIT

DCONV1
#8

RSLT,X

ADD 1 TO RESULT

RSLT,X
DCONV2
SINFLG

SET SIGN FLAG
RETURN

The sign flag would be used to indicate plus when clear and minus when not clear.
2-10

000'32

NA,..l
D:5:UB 1 E.
OPT
:S:'iME:!I t'lE"'l=MEMSUE:
:S:UBTF.~H EG!U
o
,..1 I t"iUEt-i EG!U
F.':S:L T
EOU
16
OPG
256
• DECIMAL SUBTPACT SUBPOUTINE FOR 16 DECIMAL DIGIT

000'34
000'35
000'36

•
•
•

TH I :5: POUT I ,..iE :S:U:E:TF.~ACTS THE :S:IJ:BT~?AHEtiD (" SUE:TF.~H
FPOrl THE ,..1 I t"iUEND (",..1 I NUEN "::' At-iII PLACES: THE
D I FFEF.~Et~CE Iti "F.~:S:L T • "

.000'37

•
•
•
•
•
•

THE MEMORY ALLOCATION IS AS FOLLOWS:
ADDPESS PANGE
LSB
SUBTRAHEND
1-8
:::
MINUEND
'3-16
16
DIFFERENCE
17-24
24
ADDPESS VALUES APE DECIMAL

00010

000:30
0000
000:::
0010

OOOE.O
00070
00080

000'30 0100

00097
000'37
000'37

000'3?
000'37
00100
00110
)120
00130
00140
00150

0100
0103
0105
fl107
109

001~,O

10e
10F
110
112
1J114
0115
0117
0118
011A

00170
00180
001'30
00200
00210
00220
00230
00240

lOA

CE 000:::: IISUB
DSUE: 1
AO 00
A7 10
09
26 F7
CE 0008
OD
AE. o~=:
DSUB::::
A9 10
19
A7 10
09
26 FE,
39

::::E. '39

00251
00252

•
•

LD::<
LDA
SUB
:5:TA
DE>::
Br-iE
LD;:'=:
SEC
LDA
ADe
DAA
:5:TA
DE;:'::

E:r-iE
PTS

~~:=~

A
A

A
A
A

:5:ET B'lTE

COUtiTEF.~

FINn 9---S COt'lPLEMEtiT
SUBTRH !I>::
J;:~SL T !I ~:<
USE "P:S:L T" AS TE,..lP STOPE
DECPE"'lEt-iT B ....'TE COUt-~TEP
D:5:UB 1
LOOP '-'t-~T I L LA:S:T B'iTE
~~;=:
RESTO~~E B ....'TE COUt~TER
:5:ET CAF=:~F.:·r' TO AIID 1 TO COt'lPL
,..1 I NUEt-~ !I ;:-::
LOAD t'l I f'iUEt-iD
P:S:L T !I::<
ADII CDt'lPLE,..lENT SUB T F.~ AHE ti II
DEC It'lAL ADJU:S:T
P:5:L T !I;:'::
STORE II I FFEF.'EtiCE
DECREMEtiT B'lTE COUr-1TEF.:
D:5:UB2
LOOP '-'t-iT I L LAST B'y'TE
RETURN TO HO:5:T PROGRAt1

THE EXECUTION TIME OF THIS SUBROUTINE IS
384 MPU CYCLES EXCLUDING THE RTS.

S'r'MBDL TA:E:LE

_-dBT~~H

0100 DSUBI
0 I) 0 0

0103 DSUB2

::.

~~$9'3

00254

-~UB

0110 MINUEN 0008 RSLT

FIGURE 2·1.5·1. Decimal Subtract Assembly Listing

2-11

0010

MULTIPLICATION

2-1.6

Multiplication increases programming complexity. In addition to the addition and subtraction
instructions, the use of the shift and rotate instructions is required. The general algorithm for binary
multiplication can be illustrated by a short example:
(1) Test the least significant multiplier bit for 1 or O.

(a) If it is 1, add the multiplicand to the result, then 2.
(b) If it is 0, then 2.
(2) Shift the multiplicand left one bit.
(3) Test the next more significant multiplier bit; then la or lb.
DECIMAL

BINARY

1101

MULTIPLICAND

1011

MULTIPLIER LSB=I; ADD MULTIPLICAND TO RESULT (A)

1101
13
13

1101

(B)

SHIFT MULTIPLICAND LEFT ONE BIT (B)

100111

(C)

LSB+1

1101

(D)

SHIFT MULTIPLICAND LEFT ONE BIT (D)

(E)

LSB+2 = 0; SHIFT MULTIPLICAND LEFT 1 (E)

(F)

LSB+3 = 1; ADD MULTIPLICAND TO RESULT (F)

1101
143

10001111
128

(A)

1; ADD MULTIPLICAND TO RESULT (C)

= 143

Signed binary numbers in 2 's complement form cannot be multiplied without correcting for the cross
product terms which are introduced by the 2 's complement representation of negative numbers. There is an
algorithm which generates the correct 2's complement product. Since positive binary numbers are correct 2's
complement notations, they also may be multiplied using this procedure. It is called Booth's Algorithm.
Simply stated the algorithm says:
(1) Test the transition of the mUltiplier bits from right to left assuming an imaginary 0 bit to the
immediate right of the multiplier.
(2) If the bits in question are equal, then 5.
(3) If there is a 0 to 1 transition, the multiplicand is subtracted from the product, then 5.
(4) If there is a 1 to 0 transition, the multiplicand is added to the product, then 5.
(5) Shift the product right one bit with the MSBit remaining the same. (This has the same effect as
shifting the multiplicand left in the previous example).
(6) Go to 1 to test the next transition of the multiplier.

2-12

The following example (Figure 2-1.6-1) shows the typical steps involved in an actual calculation.
A Flowchart and Assembly Listing for a program using the MC6800 instruction set is shown in
Figures 2-1.6-2 and 2-1.6-3, respectively. The results of simulating this program, Figure 2-1.6-4, shows worst
case processing time to be approximately 1.662 msec. The worst case condition results when alternate
additions and subtraction are required in each of the 16 loops required to have the result in the proper location.

Sign Bits

5 Bits

~:9

o 0 \0 0 0 0 0 0 1 1 1

-3

= -5
=

+15

"""

1 0 Bits

o
o

Multiplicand

1 ~O)

Multiplier

o to 1; subtract by adding the 2's

o 000 0 0
+00001

complement of the multiplicand

0 0 1
00000 1
o 0 0 000

+ 1

PRODUCT
Shift PRODUCT
1 to 1 shift PRODUCT
1 to 0 add

PRODUCT

Shift PRODUCT

o to

+000011

1 su btract

o0 0 0 0 1
000 000 1
000 0 000

Shift PRODUCT

~~ 0 0 0 ~..-0_1_ _..,.!,

1 to 1 shift

Sign

PRODUCT
1 to 1 shift

FIGURE 2-1.6-1. Multiplication Using Booth's Algorithm

2-13

Clear the Working Registers
This Includes the Previous LS Bit
of the Multiplier Test Byte
Initialize the Shift Count to 16

YES

Subtract the Multiplicand
from the Product with
the MS Bytes Lined Up

Add the Multiplicand
to the Product with
the MS Bytes Lines Up

Clear the Previous
LS Bit of the Multiplier Test Byte

Shift the Multiplier Right One
Bit with the LS Bit Going into
the LS Bit of the
Multiplier Test Byte

Shift the Product Right One Bit,
the MS Bit Remaining the Same

Decrement the
Shift Counter

Return
from
Subroutine

YES

FIGURE 2-1.6-2. Flow Chart for Booth's Algorithm

2-14

0001

nAt'1

r'1UL T 16

00020
00030

O;::'T

t'1t:: t'1

•
•

0'004 (I
00060
0';::- (I

I) (I

o(I o~=: (I
(I I) CI? (I

001 00
001 1 0
00120 I) ;=: n
001 ~: (I 0 ::;:0 00 ,::.-

:; ~:.: on

•
•.

i-!

00200

.
•..

OO.~:4

"_I

00.='1 1)
Oi=~':-: (I

o. ~·=:
. (I
240
,::~5 I)

:7:.:;. I) U4 no

0(1

1-.

....

U (t'E: F: ')

U + 1 ~ i..l + c: ~ U + 3

\X~)X+l

~~t'1B

~:t'1B

":.;;

er'1B
:;;:r'1B

,..

Y~Y+l

Of;:~(3

.
.

!=' P 0 DU C T = U

THE TEST BYTE FOR Y(LSB-l)

'I'

4
0Olf.O (,0'':::::: 00 1
i
001 7,-,
0(11 -'-,- (I
00 1 90

r i-i E

•

":./

THE MULTIPLIER = Y = i(~SB)~Y(L5B) =
THE MULTIPLICAND =~X=~X(M:B)~XX(LSB)

00140
001 50

T HIS PO UT Ir'4 E t'1 ULTIP LIE -s: T ! ,.I iJ j 6 E. I T c: ", S
COMPLIMENT ~UMPERS USING BOnTHS 8LGORITHM

'...

00050

THE t,t!)!... T I p~ I EP i=inp THf~ r'1ULT I C:'!._l '=:At·.j D i:1US T PE
i=tr'1D ::{':< F:E'S:PEC T I \"EL \' ~ THEH ,; )
TO
i"k!LT16 !..JILL l':;Ef'1E;:;:~ATE iHF .::"':S: COr'1 P L Ii'ltEr'iT e':;'ODt',::T

='q

:: TOPED 1['1 ",'

OF Y AND
TH~=-

IM U.

;.1UL T I ;::'L. I CAt·{[ (,} I LL.. bE iJr'iCHh r 16.:=n .P·4E

MULTIPLIE?

WIL~

BE DESTROYED.

FIGURE 2-1.6-3: Assembly Listing for Booth's Algorithm (Sheet 1 of 2)

2-15

oO,=:7 n

0400 CE
04(13 4F--

002'?0

04 (14 A?

o(I .~: (I (I

0005 r'1UL T 1.,:. i_Ii>:;
eLf::: H
L ;::. 1
:: T ~i FI
S·::~

ij'-l

06 C'::;'
00310 040;:' i.:"6 FE:

DE::<

00320 0409 CE 0010

L.D><

LF'l
~~ 1 ,_,

LDA A

/+1

AND A

o(133 I)

I) 4

CLEA~~

(I'::;' 0 C 9 -::.

(I (I ':: 4 (I

04 0 E
00350 0410
0036 (I 041.1
o(13 ? 0 04 1 ::::
I) (I :.: .~: I)

BnE

(14 1. S

00390 041t:.
00400041:::
(I 04 1 (I /}:1 1 A
o0 4~::: I) (14 1. C
(I (14 3 C' 04 1. E

::; 1
::: 4 0 1
16
9·:; '-.,::
2? 1 II
5D
27 OE
96 :::3
D~. ::;: 4
9 I) '::::3
Ii i:;: ::: 2
97 !=::::i

0044 (I 04;:;: (I
00450 0422 D7 84
00460 0424 20 OC

00470 0426 96 35
00480 0428 D6 84
00490 042A 9B 8~

00500 042C
00510 042E
00520 0430
00530 043~
00540 0435
00550 0438

ADD

97
D7
?F
76

85
84
0088
0080
76 0081

S~VE;(LSBIT)

E:EO
TS:T B

S:H IF r

BEG

ADD

LDA A

'-'+1

LDA .B

SU,t: FI

;:':;';':;+1

::f;C B
'S:TA A

U +-1

STA B
BRA
LDA A
LDA B
~DD A
ADe B
STA A
STA B

'~:'-j

1FT

U+1
U
;;-::::<+ 1

~:OL

77 0084

ASR

76 0085
76 0086
76 0087
09
044£ 26 BF
044D 39

POR
POP

U
U+1
U+2

00570
00530
00590
00600
00610
00620
00630
00640

043E
0441
0444
0447
044A

ROR

DOE? Y(LSBIT)

IN ReeF

= Y(LSB-l)

'/E:: ':3U TO :S:H 1FT ':;;'OUT I t'~E
riO: DOE'S:''''':: L.S:B I T.:r = (I "7'
'r'E'S:: <3D TO ADD ROUT I r-iE
NO: SUBTRACT M0LTIPLICAND

PRODUCT WITH THE MSBYTES
LInED UP

THEN GO TO SHIFT ROUTINE
ADD THE r'1UL T I F'L I CAt-iIi TO THE
PPODUCT r.d I TH THE r·1SB ....'TES
~ I r-iED UP

U+1

POP

CLP

U:,

I) O::~;:::

043B 79

SHI~T

InI T"':_ SHIFT CDut'iTEP TO
!:ET \' (LS.B IT')

U
FF
l
\'+ 1

(1056 I)

,><

TAE:

EOP Ii

THE WORKING REGISTERS

ROR
DEX

U+~:

BNE

LP2

CLEAR THE TEST BYTE
SrlIFT THE MULTIPLIER RIGHT
ONE BIT WITH THE LSBIT
IHTD THE LSBIT OF FF
SHIFT THE PRODUCT RIGHT ONE
BIT. THE MSB REMAINING THE
~:A~'1E

DECREMENT THE SHIFT COUNT
IF NOT 0 CONTINUE

RTS

END
FIGURE 2-1.6-3: Assembly Listing for Booth's Algorithm (Sheet 2 of 2)

2-16

.:: TPT;

11:::,.

~rRT;

P,X,A~B~T

r" i~:~"r;

t·~ ~~:

~)!=i.

.=::

::.

JO,OAA~OAB~5~,55.
ST!~:T

~;:~ F.: T ~

1. B

1. 6 •

~: T P T;

II F:

l~,.

t:? ;:: I) 0 •
I tE:T Fi=iUi._T

0001

F' 20 U

0000 lC (7

? Dl"1 !:: (I

0001635

,:::

T
Dr'1 f (I •
:; E...
__';....
:' ....
1 --.C.-7
(I 0::: 0 0 I) 0 0 5.'5 '5 S .-E;.,,;;;.;_:__;:.....
? STi~'T

6 .

.~: r j~~ T; He
.~:

T F: T;

? SM
S~

:~: P

F' 4

(I I) ,

T (I

•

80~7F,OF~q7F,OFF

80~7F~OFF,7F~OF~.

? P;~ C 0
1 H.=:T ,=-!=tUL. T
HH;:'

>:~

0001 0000

.FE 7F 0001256

? '[11'1 ;:; 0 ~ ::::

0080 00 00 7F FF 3F FF 00 01

FIGURE 2-1.6-4: Simulation of Booth's Algorithm

2-17

In the transaction terminal design described in Chapter 6, it is necessary to multiply price by
quantity, price by weight, and total price by tax. All these operations, as defined, require a 5 by 3 digit
unpacked BCD multiply, where unpacked means one BCD digit per byte. Decimal point poisition is
determined by the executive program's use of the subroutine buffers. The main multiply loop XKMPLY (refer
to the flow chart of Figure 2-1.6-5 and the Assembly Listing of Figure 2-1.6-6) is similar to the basic multiply
algorithm shown in the first example of this Section except that it has been modified to test the shifted multiplier
byte for zero. This minimizes the number of shifts required to generate the correct result. This result or partial
product is generated in ACCA and then decimal adjusted to determine the number of tens and the number of
ones it contains. The number of ones results is in ACCA and the number of tens is in ACCB. ACCA is then
added to the result buffer for the present partial product, ACCB is added to the result buffer for the next more
significant partial product. The maximum number stored in any result buffer before it is added to the new partial
product is 18 (9 max from its previous decimal adjustment plus 9 max from number of tens from the adjustment
of the next least significant partial product.) This value, when added to the maximum partial product of 81, is
less than 255, the maximum value in one byte so no carry or overflow will occur. This combined with the fact
that the multiplication progresses from the least to the most significant byte says that the last partial product to
be adjusted will be for the most significant result and that it and all previous result bytes will be in the proper
decimal format.

The simulation for XKMULT gave the following results:
99999
X 999
99899001

4.651 ms

1.108ms

III

1.426 ms

974 ms

00009
X 007
63
00079
X 700
55300
00005
X 100
500

From this, the worst case multiplication is approximately 4.7 milliseconds, most of which is used up
in determining the number of 10's and 1 's in each partial product. The program is general in nature, i.e., it can
easily be expanded (or shortened) to any number of unpacked BCD digits by increasing or decreasing the
maximum value of the various address pointers and their corresponding memory buffers.
2-1.7

DIVISION
Another arithmetic routine developed for the transaction terminal demonstrator divides a timing

2-18

MULTCND
MUL TPLR
RESULT

T1T2T3T4TS-+TN
X

SI S2 S3 -+ SM

Rl R2 R3 R4 RS R6 R7 RS -+ Rp

Initialize Result Address Pointer: P = 8

Initiali;~e~U~~;~~~ '!.u;~~:s~~:":'~

M = 3

If Multiplier Digit = 0
Skip Partial Product Loops

YES

If Multiplicand Digit = 0
Skip this Partial Product Loop

Right Shift
BCD Multiplier
One Bit

Set Result and
Multiplicand Pointers
for Next
Multiplicand Digit

Set Multiplicand
Pointer for Next
Multiplicand Digit
Add Partial

Product to
Accumulator A

Decimal Adjust
Partial Product

in ACCA

ACCA = # of Units
ACCB = # of Tens

Update Result Buffer
Set Result Pointer for
Next Multiplicand Digit

NO:
Get Next Multiplicand
Digit

Has the Last Multiplicand

Digit Been Used?

YES:
Reset Result Pointer
for Next Multiplier
Digit

Set Result and
Multiplier Pointers
for Next
Multiplier Digit

FIGURE 2-1.6-5. XKMUL T Flow Chart

Has the Last Multiplier
Digit Been Used?

NO:
Get Next
Multiplier Digit

YES:
Return to Main Program

2-19

00100
00100
00110
00120
00130 5860
00150
00160
00170
001.80
00190
OO,~OO

00210
00220
00240
00250
00260
00270

oOi~::: 0

00290
00300
00310
00320

OPT

•
••
••
••
••
••
••
••
••
••
••
••
••

••

••
••
••
••

:'~At'l

::-::~:::r'1UL

OPT

r'lEt1

1•0

OPG
$5860
THIS SUBROUTINE MULTIPLIES THE 5 DIGIT DECIMAL
NUMBER STORED IN THE 5 BYTES STARTING AT
XKMT (ES) BY THE 3 DIGIT DECIMAL NUMBER StORED
IN THE 3 BYTES STARTING AT XKMS (E2) AND
STORES THE RESULT IN THE 8 BYTES STARTING AT
XKMR (EA). THE MULTIPLICAND [T], THE
MULTIPLIER (S] AND THE RESULT [R] ARE UNPACKED
RIGHT JUSTIFIED BCD NUMBERS
XKMTMM = M = INDEXED ADDRESSING POINTER FOR S
:: r'lA::':: ~~ OF DEC I j'lAL DIG I TS I t'i 'S:
XKMTMN = N - INDEXED ADD~ESSING POINTER ~OR T
= t'lA;:':: ~~ OF DEC rr'lAL DIG I TS I r-i T
XKMTMP = P = INDEXED ADDRESSING POINTER FOR R
= t'lR>-:: ~~ Ot=" DEC I r'1AL DIG I TS I r'1 R
;:·:;t::J'fS:CR
-::
;'lU'- T I F'L I CAND Ii I G I T 'S:CRATCH F'RD
BY GHANGr~G THE POINTER INIT~L •• AND THE
MEMORY BUFFER SIZES LARGER NUMBERS M8Y BE
MULTIPLIED WITH THIS SUBROUTINE.

FIGURE 2·1.6·6: XKMUL T Assembly listing (Sheet 1 of 2)

2-20

00350
00360
00370
00380
00390
00400
00410
00420
0043n
0044
0045
0046
0047
004S
004-~

5:::6 (I CE 000:::
5:::63 DF F6
5:::65 4F

;:-:;~(r'1UL

T Ln;:·::
·S:T;:·:;
CL~~

~:-::Kr'1LP 1
5~::'::'9

26 FE:

5:::6E: I::E

t=~E

c: ,-, -,-,

86 E4

_":t

>:~:::r'l::-:; TT

~_DA

::< t( ,..l·S: I:: ~~
;:-:;vr'lTZO

SAVE

~KMSHF

03
583D DF F4
~88C

588F DE F6
5391 AB E9
589? 81 OR

00640 5397 30 OA

00650

58~9

00660
00670
00680
00690
00700

5S9A 20 F7
SS9C ~B E8
S89E 87 ~9
S3AO E7 E8
5882 J3

prr

X(~SCR

NO~

~KMLP3

XkMCl

LDX
ADD A

::-:: k: r-1 T r'1 F'

CMF' 9
BLT
SUB R
INC B

8DD R TO AeCA

XKMR-l~X

::-:: t::: t'1 T ~'1 f'~
:« f'1>< T T

;="S:H A
:....DA 9

ADD rl

.. &.~.
'It" _I

••

INIT'l 5=N ••
nIT . ' L ")

I:' =F' +-1--1':: I

8
c'UL A
-~:TA

>< :: <(-1 T"1 t·,
;--1='"'1--1

I 1= r-1

~ if] T

0:3 0 TO

PT'::

DE;:'::

(:-~

1::(

::TACY

P=F'-1

00850 SSBB (,S OOF?
5::: F:;: 2 (I

WITH THIS T.
LEFT SHIFT T 1NE BIT

B~A

~KMC2

5 ;:: PI:' :'
0080n 53B2 7~ OOF? ':<:<" r'1D':: F' Ii EC
>.: r::' r-~ >:: r :~: 1_ D';.:
I) (131 0 5::: B'5 [il:: F,~
DE>:;
I) 0::::2 (I 5;:: E: 7 o·~
Br',E
(11):::3 (I 5:::B3 E':- :84
(10340 5:::BA :::::;

NO~

DOES gCCB=O

~INISHED

STX

(I I) ('9 (I

YES~

r'~ '=r'~-1

DE~

DEX
~6

8:::A+T

:HlcT T:

TST B

5 ::: A'::' DE F 4

O'::65·::BE

XKM:CR

BRA
XkMC4

S:::AB -3::' F7
o0 ('7 0 5 ':; A II:::; f; I) S
(107::: 0 S'::AF 97 F?

(10:::7
00'::::

ADD H

~KMSCR

00630 5395 2D 05

TO i"iE>::T .. T"

l:3i]

RIGHT SHIFT AceB INTO CARRY
IF C=O GO TO :HIFT T

BEO

~;!=-

..;.

~KMSHF

XKMPlY LSP B

ASL

c. ,:-

11.::-.11

S:A',/E .. :S:" lJn S:TRCJ:::

588? 78 OOF8
588A 20 F3

5~::~A

••

5885 27 05

00740 5;:: A:::

M=3

IF B:::Q THEN GO TO NEXT
•• I~IT~L N:::5 ••

XKMC4

(1075 (I

I~IT'L

CLR A

5884 5D

00710 58A3 09
00720 58A4 D~

••

B:::"s"
:::;
:-A',/E /"'1 PO I t-1TE~~
;:< K r'1 T t'l r-l

F'S:H E:

00500 587E 4F

oO?~- (I

-::T>::

BEG!

00510 S87F 54
00520 5380 24 02
00530 ~882 9B F8

o(17 ::: (I

, ..... "-.
:..

L DR f:

::TA A

00540
00550
00550
00570
00530
00590
00600
00610
00620

CLEAR RESULT BUFFER

BEl)
LIt;:.::

0005

5 ::74
1

Br'iE
::<~:::t'l:~: TP

••

'S:TA A
DE>:;

'_II::-:;

I) 0 1)3

5:::6E E6 E 1
5:::70 DF F2

•• I~IT'L P=8=N+M
I nIT . ' ,_ P POI r'i TE~~

r-i

=n -

B~'9

Er'1D
FIGURE 2·1.6·6: XKMUl T Assembly listing (Sheet 2 of 2)

2·21

r'~ E >:: T

'1 .::-.1.
..:.

Subtract 9 from Saved Shift Count

Initialize Shift Count to 8 (S = 8)
Clear Quotient Buffers

Store Result in Remainder
Displacement Buffer

LSB Goes into Carry

(

DVDEND )

Save Shift Count for Determining
the Offset of the Remainder
Shift Divisor Back Right One Bit
Divisor is Now Left
Justified and the Shift
Count is in ACCB

YES

Shift Quotient Left One Bit
with LSB = 0

Shift Quotient Left One Bit
with LSB = 1
Subtract: Dividend (MS Byte) =
Dividend (MS Byte) - Divisor

Shift Dividend Left One Bit with:
LSB = 0 and MSB into Carry

YES

FIGURE 2-1.7-1. XKDIVD Flow Chart

2-22

count accumulated in the index register (up to 4 HEX digits) by the constant 7. This routine is used to determine
an average module width during a portion of the UPC label scan routine. (See the description of the UPC label
scanner in Chapter 5 for further details.) The routine permits division by a 2-digit Hex number as shown in
Figures 2-1.7-1 and 2-1.7-2; it calculates the displacement of the remainder left in the dividend and sets the
quotient to FFFF if division by zero is attempted.
The algorithm used for this straight forward binary division is as follows:
(1) Left justify the divisor byte.
(2) If the MS byte of the dividend is less than the divisor byte, shift quotient left one bit with the LS
bit

0; then 4.

(3) If the MS byte of the dividend is greater than or equal to the divisor, (2) shift the quotient left one
bit with the LS Bit = 1; (b) subtract the divisor from the MS byte of the dividend, the result
being stored in the MS byte of the dividend; then 4.

= 0, and the MS Bit going into the carry.

(4) Shift the dividend left one bit with the LS Bit
(5) If the carry is set, go to 3a.
(6) If the carry is not set, go to 2a.

The process continues until the number of quotient shifts equals 8

+ the number of shifts required to

left justify the divisor. A simulation (Figure 2-1.7 -3) shows a typical divide takes approximately 1 millisecond.
This section is, by no means, comprehensive. It is intended to provide some examples that can be
used as is or that will suggest the direction for modifying them for other specialized applications.

J?T

00100
00000
00010

00040
00050
000::·0

00070
I) I) 0:: (I

00090
0(11)0

OOil0
00120

00130
00140

00150
001.':,0

00170
1 ~:; (I
(1) 1. ':'40
I) 1.')2 0 0

(I (I

f) 0·:::1 0
(I

'::c: 0

0::::::0
(I 240
;) .:::50

>:1< Ii I 1,.,1 Ii

CPT

t'lEt'1
1;5'3 (I 0

:JF:J~

000;:::0 5900

oI) (I~; I)

r'~8r'1

•
•

•

••
•

TO DIVIDE 8N U~iIGNED 4 DIGIT
HEX NUMBER [16 BIT BINARY] BY AN UNSIGNED
SUB~~UrINE

DI :; I T 1-1 E. ;:.:;

ri Ui'l E: E P r: ':;

THE DIVISOR = X
T:.-f E DI ',.,! I II E j"i D

•
•

•

BIT B I r'1 A;:;;~ \' ] •

= ~KDVS~ = (F9J

= '/.:: "1 > ,",' (" '. _>

- \KDVND,XKDVND+l
THE QUOTIENT

•

= [FA~FBJ

=
=

O(~)~](~)

XkOUOT~~~QUOr+l

= [FC,FDJ

SHIFT COUNTER

TrlE

THE '_EFT D r:''::'LACEP1Er'iT 0;:- TYE

•

T!-f E DI '/ I .::] ::;;: A("i D THE DI ./ I II :::: r-i[l \'1 U::;. T BE

•
•

••

INTO XKDVSR AND \(DV0D,XKDVND+l RESPECTIVELY
THEN A JSR TO XkDIVO.
Trl~

..
..

.::1-/ I!= rED i_E!=T THE ~:: OF E: ITS: I r"1D I CATEr' I n :';~t:'Tf'S:F'L
TH::: DI \,1 IS:c]P (,I I i_L BE f: P'lA~~ I L.... ~_EFT JIYS'T I F I ED

•

•
..

ACeB
~'tJ'1A

I r-iDEP

;: [XKDVNDJ,

FIGURE 2-1.7-2: XKDIVD Assembly Listing (Sheet 1 of 2)

2-23

~ 0 AII E II

oOZ:f. (I

5'3

("I

'.. ,:'

(,':;:

00270 59 2
00290 5? ~

OOFe
OocD

oOE9 (I
o(I ,;! I~: (!

':~'3:'

:: '~

',::

1 (I

S~::.j I) f:;

(I (I ':::

1 1 (I
.:? .:+

:-: I::'

:~:!Ui.J

;:< ,< .D :/ '::: ,;;:.

: •..:j.

F .:'

B,:'C

00340 5912 D7
00350 5914 76

::<:< DSF'L

oo~s

,:·:;r:::D'·/S:;:;::

5 ':; 1 I)

003t::,O

oo::;?O
00390
00400
00410
00420
00430
00440
00450
00460
00470
00430
0049n

5919 91

531B ~~ OD
591D OD
591E 73 OO~D

[i·/Di_C'I)

•.
DiDLP1 CMP

Be?
DVD~P2

~EC

5921 79 OOFC
~DL
5924 30 cg
SUB A
~?26 97 cA
?fR ~
5929 20 07
B~A
5928 OS
DVMSUB elC
:;~O'._
592B 7~ OocD
592E 73 OO~C
(105 (I I) 5'331. 5,~
It\.' S:HF T
00510 5932 27 12
-°

OOS~,O

S'3~:D

r= r4~ DIVIDEND ( DIVISOR
DON/f SUBTRACT
IF T4~ DIVIDEND >J~= DIVI=~
: 0
~EFT

I >~ T 0 ,=: Al:;;~ ;.~ \'

\'1 ~;. B
I~
13:]

GET

Ti]

GO TO LOOP2

LC1iJ P

COUNT INTO A2CB

S~I~T

~XDSP~

~KDSPL-9

::'::K [I ~:F='L : : 4
D\iDLC'3

:::UB B
[1',/[11..):::3 STFi B

~E~T

B = (I

D".. "1 [!

00570 593F 20 D2
(1060(1 5946

IF ;)16 DIVIDE E~~OR
IF S(16 ~EFT SHIFT DIVISOR
IF C=O CO~/T LGOP
I~ C=1
~(DSPL = SHIFT CaUNT
?HIFf THE DrVISO~ 88:k 1
SHIFT COUNT ~aw IN ReeF
DrVISJR LEFT JUST. I~ X

DVNSUB

~OL

C0530 5 Q 35 73 OOFB
00540 5938 73 OOFA
00550 593B 35 FA

B0FFER

;~ 1~.
D\"DE':;:~':;;:

g :r..

oI) 3 3 I)

='::;

)JQTI~NT

T +- 1

OO~9

00320 590D 73

2ERO

~~4

>:: to::: [is: F' L

TO RETURN
!::VD'S:PL

;:;:·T :::

:::r-iD
FIGURE 2·1.7·2: XKDIVD Assembly Listing (Sheet 2 of 2)

2-24

STF.:T;
STF.:T;
STF.:T;
SrF.:T;
STF.:T;
:S:TF.:T;

SS.
lB.

DB 16.

SP P5:::6 O!l S7FF!I TO.
S:D PAB::-::CT.
HF.: 5.
? SF.: P5'3 0 (I

FFFF

P 100

r'1Er'1 FAUL T

*1DC1
,0;:-

0000*00*02

000000 0001020

Dt'1 OFC!I 2

[11"1 OFC, 2
(lOFC ~ S5 00

FIGURE 2-1.7-3: Simulation Results, Division

2-25

1
::::

1 ms

5555

2-2

COUNTING DELAY MEASUREMENT/GENERATION

When microprocessor systems are initially considered as replacements for conventional logic
designs there is a natural tendency to formulate. such questions as: What is the program that replaces a flip-flop?
A counter? A shift register? A one-shot? Etc. ? Such questions are better posed as: What is the function that must
be performed? The answer to the question then often falls in one of two categories: (1) The number of times
something occurs must be determined (counted); (2) A particular time interval must be measured or generated
prior to taking some action.
These functions are also commonly used for controlling internal program flow; the MC6800
provides a variety of ways for performing them. Short (up to 8-bits or decimal 255) counter requirement can be
implemented using either of the two accumulators or any RAM location. The increment (INC) and decrement
(DEC) instructions apply to random access memory locations outside the MPU as well as the accumulators.
(The instruction set for the MC6800 is discussed in Section 1-3) The data test instructions BITA, BITB, CMPA,
CMPS, CBA, TST (memory), TSTA, and TSTB that are available for updating the Condition Code Register
combined with the branch instructions permit complete control of counter operations.
For applications requiring long counters (up to 16-bits or decimal 65 ,535) the Index Register and its
full complement of instructions are availabie. When more than one long counter is required simultaneously, a
short program can be written that permits two adjacent RAM locations to be used as a 16-bit counter:

CNTNUE

INC
BNE
INC
xxx

N+ 1
CNTNUE
N

Increment memo loco (N + 1)
if result not = 0 continue

xxxxxx

Next program instruction

This sequence effectively increments a 16-bit word located in memory locations Nand N + 1. A similar
procedure is available for decrementing a 16-bit word:

TST
BNE
DEC

N+l
NEXT
N

Mem. loco N+ 1 = O?

DEC

N+l

Decr. N=1

No, go decr. N + 1
Yes, first decr. N

2-26

In addition to their use for long counters, these instruction sequences can be used for modifying return
addresses. During execution of subroutines and interrupt service routines the program counter containing the
return address is stored on the stack, a designated area in RAM. The increment or decrement sequences can be
used to change the program counter value on the stack and thus cause the return from subroutine or interrupt to
be to a different location in the main program.
It is possible in some cases to use the index Register and Accumulators for two functions
simultaneously when one is a counting function. As an example, assume that data from a peripheral device is to
be entered into the MPU's memory via an MC6820 PIA 1 • The peripheral is to indicate the presence of data by
setting a flag, bit 7 of the PIA's Control Register. Each time the flag is set the MPU is to retrieve the data from
the PIA Data Register and store it in an internal memory location until a total of 8 bytes have been accumulated.
Since the PIA's Data Register and Control Register look like memory to the MPU, a program is required that
will cause the MPU to monitor one memory location for a change in a flag bit and then fetch the data from
another location. This operation is to be repeated the specified number (8) of times.
The following sequence of instructions uses a single register, Accumulator B, for both the
monitoring and counting functions:

LDAB
LOOP I

BITB
BPL
LDAA
PSHA
INCB
BNE
xxx

#08
PIACRA
LOOP I
PIADRA

LOOP I
xxxxxx

Put 2's CompI. of byte count in ACCB.
Byte Available flag set?
Not yet; loop back, chk. again.
Yes; Fetch byte.
Put byte on stack.
Eight bytes yet?
No, go wait for next byte.
Yes, continue with program.

This program takes advantage of the fact that incrementing an accumulator containing FF cause it to "roll
over" to 00. The two's complement of the required count is entered as the byte count. Since this will cause the
sign bit (bit 7) of ACCB to be positive and since the BIT test does not affect ACCB but does update the
Condition Code Register, the Bit test followed by the Branch on Plus instruction can be used to monitor the flag
bit. As soon as bit 7 of the Control Register is set to one, the BPL test fails and the MPU fetches the current data
byte by reading the Data Register (PIADRA) and then pushes the byte onto a stack location in RAM. The design
of the PIA is such that the flag is automatically cleared by the LDAA PIADRA operation. The byte count is then
"reduced" by incrementing ACCB and tested by the Branch on Not Equal Zero instruction. Unless the eighth
byte has just been transferred the program loops back to wait on the next data byte. If the current byte was the
eighth, the INC B instruction cause the count to roll over to zero, the branch test fails, and program flow falls
through to the next instruction. The other test instructions (TST, CMP, and CBA) can also be used in a similar
lOperation of the PIA is described in detail in Section 3-4.

2-27

fashion since they too update the condition Code bits but do not affect register contents. Note also that it was not
necessary to bring the contents of the Control Register into the MPU in order to examine the flag.
Delays can be generated in a variety of ways. A typical procedure is shown in the following
sequence:

LOOP 1

LDAA
DEC A
BNE

#32

Takes 4 cycles to execute.

LOOP 1

(2 cycles)
(4 cycles)

In this example, the MPU will go through LOOP1 32 times so that the total delay introduced by these
instructions is, for a 1.0 JLsec cycle time:
4 + 32 (2+4) = 196 JLsec
The number of times through the loop is calculated as the program is developed. If, for instance, the required
delay is 200 JLsec, the value to be loaded into ACCA is determined from:
(200 - 4)/6

= 32.6 = 32

Note that since the nearest smaller integer is selected, the actual delay generated in only 196 JLsec. If greater
accuracy is required, the sequence above could be followed by two NOP instructions, since each NOP advances
the program counter and takes up two cycles. Delays beyond the capacity of an 8-bit Register and a single loop
can be generated by using the Index Register and/or multiple loops. It is also sometimes desirable to write the
delay sequence as a callable subroutine that can be used to generate variable delays. This is illustrated by the
following routine. This sequence assumes that the amount of delay, in milliseconds, is loaded into a RAM
location identified as "DLYBFR" prior to calling the routine.

DELGEN
LOOP 1
LOOP2

LDAA

DLYBFR

LDAB
DECB
BNE
DECA
BNE

#165

RTS

LOOP2
LOOP 1

(a) 4
(b) 4
(c) 2
(d) 4

cycles
cycles
cycles
cycles

(e) 42cycles
(f) 4 cycles
(g) 5 cycles

2-28

The MPU will go through LOOP2 165 times each time it is entered: 165 (c+d)

= (165)(6)

+ 990 cycles. For

every time through LOOP 1 there will be a total LOOP2 time plus the b, e, and f cycle times, or the total time,
including the RTS cycle time, is:
Total delay = DLYBFR (990+4+2+4) + 5
= DLYBER(1000) + 5

If, for example, DLYBFR had been loaded with 17, indicating that a 17 msec delay was required, then for a 1.0
JLsec cycle time. The total delay is 17,005 JLsec

17 msec with small error. The value 165 that is loaded into

ACCB was of course selected to provide the desired scale factor, i.e., so that the delay could be entered as an
integral number of milliseconds. Variation on these procedures can be used to generate virtually any amount of
delay. Note that if for some reason it is undesirable to disturb the contents of the Accumulators or Index Register
while generating a delay, RAM memory registers may be used. The INC and DEC instructions also operate
directly on memory.

2-29

2-3

EVALUATING PERIPHERAL CONTROL ROUTINES
Data handling often involves the transfer of data between a microprocessor's memory and a time

dependent peripheral. It is necessary to synchronize the data transfer program to the peripheral because the
peripheral data clock is asynchronous with respect to the program clock. The I/O controller which handles the
data transfer consists of both hardware and software. An implicit assumption is that the best trade-off occurs by
minimizing the hardware in the controller.
In a microprocessor based I/O controller, it is necessary to determine:
(1) How fast can the microcomputer transfer program move data (as contrasted with a direct
memory access scheme)?
(2) Will a given data transfer program work successfully in the system?
(3) Is there any processing time remaining after handling the data movement?
(4) Can any additional time dependent functions be performed?

(5) What is the maximum length routine that can be performed in addition to the data transfer?
An analysis is required that will provide a technique for testing the operation of a proposed program. In
addition, if there is unused processing time in the system, it may be possible to eliminate additional hardware
(e.g., buffer registers). If a given program does not work in the system, the analysis should enable the user to
modify the program or add additional hardware to allow the system to work.
Specific examples of the word transfer problem for a floppy disk and the bit transfer problem for a
cassette system will be used to illustrate the typical problems. The cassette data transfer example also illustrates
the technique for increasing the amount of usable spare time by borrowing it from adjacent data cells. In this
case, the spare time is used to refresh a display.
When a peripheral signals the MPU requesting processing time, it will be referred to as a Service
Request, (SR). When the service request is periodic, as in the above mentioned examples, it is called a time
dependent service request. Read or Write Data Transfers are both examples of such service requests and where
the examples show programs or terms referring to a Read Data Transfer, they are meant to be illustrative of both
Read and Write Data Transfers.

2-3.1

NOTATION USED SERVICE REQUESTS AND PROGRAMS AS WAVEFORMS ON A
TIMING DIAGRAM

The process of synchronizing a data transfer program to a peripheral can be visualized more easily
when the SR's and the program are both represented as waveforms on a timing diagram. The peripheral SR
waveform is developed from the specifications of the peripheral which identify the maximum time, TIm it takes
to load the data buffer (the period during which data is invalid), and the minimum period, Tom between service
requests.' The subscript m refers to the parameters of the mth peripheral.
The data transfer waveform is developed by writing the actual data transfer program and then
calculating the time it takes to:
( 1) Capture the data (T4m)

2-30

(2) Process the data (T2m -

includes period T4m)

(3) Loop in a synchronization delay loop until a SR is active. (nT3 -

where T3 is the single loop

time and n is the number of times the program loops).
These values are calculated by counting the number of processor clock cycles required to execute
each function, and multiplying the numbers by the MPU clock rate. The waveforms and notation for a typical
situation are illustrated in Figure 2-3.1-1. Figure 2-3.1-2 shows a flow chart for a data transfer program for a
single peripheral. Figure 2-3.1-3 details the technique for calculating the program parameters and Figure
2-3.1-4 illustrates the relation between the peripheral word ready service request and the program timing. The
values of the SR parameters are for a floppy disk data transfer.
The period TOl is the worst case (fastest) peripheral data word rate, and it is calculated taking into
consideration floppy disk motor speed variations. The SR update time T 11, is the time during which a new word
is being loaded into the data buffer, and at the end of which there exists an active SR.
The timing diagram of Figure 2-3.1-4 shows a processor clock running at a 1 'Ilsec cycle time and
shows how the word capture time is developed from a knowledge of the point in the instruction cycle when the
word capture begins and ends. In this case, the program begins the word transfer at the positive edge of the
fourth processor clock cycle during the LDAA RDCTL instruction and completes it at the negative edge of the
fourth clock cycle during the LDAA RDDATA instruction which moves the data. Therefore, T 41 is equal to the
number of clock periods between initiation and the end of transfer, 8.5 cycles = 8.5JLs. The first two
instructions form the sync loop (T3) and the total program represents the program processing time (T21).

~Tom

PERIPHERAL SRm
(word ready)

-i
--., ,..- T1m

lJ~-----IU

---tf T4m f4-

PROGRAM DATA
TRANSFER ----~...IJ
(word fetch)
t1 m

~------"!"'-----'

I
k---- T2m

Period of service request of mth peripheral (word ready period).
Service request update time (Data Invalid) for mth peripheral.
Program Processing Time of the mth SR. Includes
time to capture data.

Synchronization Loop time when the program has checked
and found no active service requests.
Data Capture Time of the mth SR.
Initial offset between the SR and Program Data
Transfer Waveforms.
number of times the program goes through the
synchronization delay loop.

.,. nT 3--.1t-- T 2m----.f

TOm
T 1m
T2m

T4m
t1 m

FIGURE 2-3.1-1. Peripheral Service Request (SR) and Data
Transfer Program Waveforms and Notation

2-31

.,L -

"""-----~--I

2-3.2

DEVELOPMENT OF EQUATIONS AND INEQUALITIES USED TO TEST SUCCESSFUL
SYSTEM OPERATION
A successful data transfer means that each time the peripheral indicates, via an SR, that a data word

is available, the program is able to capture the data before it is replaced by the next data word. It is implied that
the program is able to proces the data between data word transfers. (In the floppy disk data transfer program,
processing involves storing the data in Random Access Memory (RAM) and checking whether it was the last
word that needed to be transferred.) Similarly for data transfers to the peripheral, the program must make the
data word requested available before the succeeding request arrives. In other words, a successful data transfer
consists of avoiding an overrun (during READ) and underflow (during WRITE).
If the SR is not ative at the time that the program checks for a SR, (i.e., the data word is not ready),

then the program goes into a synchronization (sync) loop, which causes a delay (T3). At the end of a sync loop,
the program again checks for an active SR.
In the following analysis, it is assumed that the values of the parameters detailed in Figure 2-3.1-1
are at their worst case limits and are constant for simplicity, the single SR model (where m
initially.

= 1) will be used

For the system to transfer data successfully the average wotd processing time T.'\VG must be
approximately equal to the peripheral data word SR period To!.
TAVG

= Tot

(1)

More precisely stated, in the limit as the number of words transferred, p, approaches infinity, the
average word processing time, T A VG, is exactly equal to the byte cell period To!.

STORE
WORD

DECREMENT
WORD COUNTER

FIGURE 2-3.1-2. Flow Chart for a Typical Data Transfer Program
for a Single Service Request

2-32

LABEL
RDLOOP

PROCESSOR CYCLES

MNEMONIC

OPERAND

COMMENT

LDAA
BPL

RDCTL
RDLOOP

LOAD CONTROL WORD
j-SYNC
LOOPIFSR I S I N A c : 3 I V E LOOP
(T )
3

LDAA
PSHA

RDDATA

LOAD READ DATA
STORE ON STACK

DEX
BNE

4
4

DATA
CAPTURE
(T 41 )

~~~~ESSING 4
(T 2 1)

DECREMENT WORD COUNT
IF WORD COUNT IS NOT
ZERO RETURN FOR NEXT WORD

RDLOOP

PROGRAM
4

4
4

EXIT

24 CYCLES

TOTAL

IF THE MPU CLOCK PERIOD IS 111s THEN SYNC LOOP TIME T 3 = 8 11s
PROGRAM PROCESSING TIME T 21 = 24 11s
DATA CAPTURE TIME T41 = 8.511S (See Text)

FIGURE 2-3.1-3. Data Transfer Program Indicating Method Used to
Calculate Program Parameters

..
~ _ _ _ _ TO 1 - - - -...
~~~-----T O1------.1101~

PERIPHERAL

-------=6----. T11

WORD READY SR

~-T-1-1

WORD IN READ

----.J

~ T1

BUFFER

fUUUUlJlJ

PROCESSOR
CLOCK

1.0,u.

INSTRUCTION

-.lit- :
g T21 (equation 4),

then the offset Tll gets smaller and smaller until it is negative or zero, which means that after the program has
processed one word, the next word will not be ready. At this time, the program goes into the synchronization
loop, and samles the peripheral Word Ready line until the SR is again active.
The maximum value of the synchronization loop for which the system will work may be determined
from the following argument. Since the peripheral SR and the program are independent, it is entirely possible
that the SR occurs immediately after the program has initiated a sync loop. Since the data capture time is T 41
and the data is invalid for a period Tll out of every TOl, it is necessary that:
T3

(8)

TOl - Tll - T41

This is the inequality used to calculate the maximum permissible value of T3.
2-3.3

Floppy Disk Data Transfer Routine
The parameters of the Floppy Disk Data transfer routine are listed in Figure 2-3 .1-4. The parameters
2-34

can now be tested with equations (7) and (8):
From Equation (7)
n=1
24 ::.;; 29.7

(9)

< 32/J-s

and from Equation (8)
(8)

8 ::.;; 29.7 - 0.75 - 8.5
Both requirements are met and the program will transfer data successfully, (at a maximum rate when TOl =
T21).

1
1
Max Data Rate = = - - = 41.6K Bytes/sec.
T2l 24/J-s
Note that in this example, the time left over in each data byte after processing is:
(10)

TOl - T2l = 29.7 - 24 = 5.7/J-s
This time is too small to be usable for other tasks by the M6800.

2-3.4

CASSETTE DATA TRANSFER ROUTINE
The data transfer routine of Figure 2-3.1-3 is equally valid for the case of word data transfer between

the cassette and an MPU. The significant difference is the slower data rate, i. e. , the SR period for word transfer
is much longer. For the cassette with a worst case data transfer rate of 1.85 KBytes/sec (15KBits/sec):
1
TOl = - - = 540.5/J-s
1850
All other parameters remain essentially the same.
Tll = l/J-s

It may be verified that both Equation 7 and 8 are satisfied by the above parameters for n = 65. The time available
after processing the word is:
TOl - T21 = 540.5 - 24 = 516.5/J-s
This time is normally used up in synchronization delay loops. Since so much additional time is
available, it may be possible to transfer cassette data in serial form (bit transfer), and eliminate the hardware
2-35

associated with the serial to parallel conversion. The Serial Data Transfer Flow Chart and Program are shown in
Figures 2-3.4-1 and 2-3.4-2 respectively. Equation 7 and 8 are both satisfied for n=4. The unused processing
time per bit cell is:
(11)

TOl - T21 = 66.6 - 40 = 26.6/Ls
2-3.5

UTILIZATION OF MPU PROCESSING TIME

Assume that it is required that a program must service a cassette for serial data transfers, as described
earlier, and simultaneously refresh a dynamic display (display without memory). Let the subscripts 1 and 2 be
used to refer to parameters of the cassette and displays respectively. Assume that the program processing time
T22, to refresh the display, is longer than the available processing time in a single bit cell, i.e.
T22 > 26.6 s (From Equation 11)
However, if the period of the display SR is longer than that of the Cassette (To2

> TOl) an interesting question

arises. Is it possible to borrow time from adjacent data cells and process SR2 without losing SRI data? The
following analysis shows that it is, if the parameters meet certain requirements.
To maximize the utilization of an MPU's processing time the extra time spent in synchronization
delay loops can be used for doing other routines. This is similar to adding a time equal to the additional delay
loops to the program processing time T 11. The condition that must now be satisfied by the program and the
peripheral SR period may be stated as:
(11)

where
T'21 = T21

+ (n-l)

(12)

and (n - ) T3 is the additional time now used for processing. The length of the program processing time has been
extended; however, there is still only one independent service request being serviced as illustrated in the flow
chart in Figure 2A.
It is often required that the unused processing time be used to process SR's from another time

dependent peripheral. Assume that it is required that the unused processing time be used to process SR's from a
display, i.e. , to refresh the display. Will the system be able to successfully handle the two SR's? This question
leads to considering the program model for handling multiple SR's, and the conditions that must be satisfied for
successful operation.

2-36

FIGURE 2·3.4·1. Flow Chart for Serial Data Transfer

LABEL

MNEMONIC

OPERAND

COMMENT

LOOPC

LDAA

CLKDAT

LOAD CLOCK & DATA WORD
(CLOCK IN BIT 7, DATA IN
BIT 1)

BPL

LOOPC

PROCESSOR CYCLES

LOOP IF SR IS INACTIVE

RORA

TRANSFER DATA BIT TO CARRY

ROLB

ASSEMBLE WORD IN
ACCUMULATOR B
IF WORD IS NOT ASSEMBLED
RETURN FOR NEXT BIT

LOOPC

BCC
PSH B

STORE ASSEMBLED WORD ON
STACK

LDA B

401

RESET BIT COUNTER

DEC

COUNT

DECREMENT WORD COUNT

BNE

LOOPC

IF WORD COUNT NOT ZERO
RETURN FOR NEXT WORD

EXIT
TOTAL
At MPU clock rate of 1 MHZ

and

B[.I5

T21

= 40[.15

T41

=0.5[.15

TOl

1
15000

66.6 [.15

FIGURE 2·3.4·2. Casette Bit Serial Data Transfer Program

2·37

40 CYCLES

2-3.6

PROGRAM MODEL FOR TWO PRIORITIZED SERVICE REQUESTS

When two independent periodic SR's are allowed, the program model for servicing them may be
prioritized. The prioritizing is done such that the SR with the shorter period (hgher frequency) has the higher
priority. Figure 2-3.6-1 indicates the programming model for two SR's where SR #1 (SRI) has higher priority.
Notice that SRI is tested first, regardless of which SR was last processed.
The parameters of the SRI, SR2 waveforms are derived as before, from specifications of the two
peripherals. The parameters for the program are derived in conjunction with the prioritized model. For
example, the synchronization loop time T3, is now the time it takes the program to test for an active SRI, and

YES

PROCESS
SR2

PROCESS
SR1

YES

FIGURE 2-3.6-1. Program Model for Two Prioritized Time Dependent
Service Requests

2-38

then test for an active SR2, and find them both inactive. Similarly, T22, the program processing time for SR2,
includes the time to test for SR 1, (which is inactive) and then test for SR2 (active), process SR2, and test if it is
the end of SR2 processing.
2-3.7

REQUIREMENTS THAT MUST BE SATISFIED WHEN AN MPU SERVICES MULTIPLE
SR's
The following requirements were developed by studying the failure mechanisms using the program

model for two prioritized time-dependent service requests. A failure was defined as an overflow or underflow,
and the program was run to process a very large number of consecutive SR's (up to 100,000 service requests).
Each time there was a failure, the timing relationships between the two SR waveforms and the program
processing waveform was studied to give a clue to the failure mechanism. The results are listed in Figure
2-3.7-1. Of the requirements listed in Figure 2-3.7 -1, Equations 7 and 8 have already been discussed. Equation
12 is really implied by the program flowchart model for a single SR where the data capture time is included in
the SR processing time.
Equation 13 states that the sum of the processing times expressed as a fraction of the SR frequency is
no greater than unity. This is true because of the periodic nature of each SR and the fact that each SR uses
T2m/Tom of the MPU's processing time. As an example, if the cassette serial data transfer routine uses 40JLs
every 66.6JLs then it uses 40/66.6 = 60% (approx.) of the MPU's capability. Hence, 40% of the remaining
MPU capability may be used by another SR. This result is used shortly to test the cassette-display service
program.

For each SR it is required that:

T2m

Tom

T2m

Tom

T1m

T4m

T2m

nT3

(7)

T4m

(8)

(12)

For the system it is required that:

(T2m)
TOm

;;;.

(13)

The equality is the synchronous case where no synchronization loops are taken.
E. For each peripheral when compared to the fastest peripheral k,
(14)
Where k is the peripheral with the highest frequency of operation, and the
SR's are prioritized by frequency with the highest frequency SR being first.
(15)

FIGURE 2-3.7-1. Timing Constraints for Successful System Operation
for Prioritized Multiple Service Requests

2-39

Equation 14 is best illustrated by the timing diagram in Figure 2-3.7-2 where SR2 and SRI occur
almost simultaneously, but SR2 is active first. This implies that just prior to this occurrence, the last SR from
both SRI and SR2 has already been processed and SRI has been tested first, according to the prioritized model,
and found to be inactive. SR2 must be processed in a time T22; then data from SRI must be captured in time T 41,
before it becomes invalid. The data becomes invalid a time T 11 prior to the next SR 1. Therefore, the condition
that must be satisfied is:
T01 -

Tll -

T41

(14)

T22 (m=2)

Equation 15 implies that the program should be able to synchronize, then process SRI, and capture
data from SR2 before it becomes invalid. This situation occurs after the last SRI has just been processed, and
then neither SRI nor SR2 are active (see Figure 2-3.7-3). After the sync loop, SRI is processed, and SR2 data
must be captured:
T02 -

T12 -

T 42

T21

(15)

T3 (m=2)

Equations 14 and 15 are stated in a general form for m SR's in Figure 2-3.7-1 but they have been verified only
for the case of two SR's. Equations 7: 8 and 13 of that Figure, however; must be satisfied by any set afm SR's.

SR1

~1"

_ _ _ _ T02----~'

SR2
T3
starts just
i
:::::~ SR'" ~:,i

Ur---:i

---:

,I::,!::

~ T12

rtL

PROGRAM
--'----+----~~"
T
PROCESSING- T 21 -----.- T3
T21
T42 ~ 12

.;4

FIGURE 2-3.7-2. Timing Diagram Showing Requirements of
Equation 15 for Two SR's

~T01-_~

SR1 _ _....,

SR2 _ _....,

r-------..~

I I
y

T11

:1
,.

U
I

--.j T42 j4-

I
I
I
I

T01~
~ T41 ~

n . . .__....n :

Program

_ _ _....

Processing

IHI

SR2 is active
before SR1 by a
nominal time

~~
T22

.14

~T11 :
T21--':

= 2)

(14)

FIGURE 2-3.7-3. Timing Diagram Showing Requirements of
Equation 15 for Two SR's

2-40

2-3.8

SERIAL DATA TRANSFER AND DYNAMIC DISPLAY REFRESH PROCESSING

The cassette serial data transfer program is now modified and extended to service both the cassette
data SR and the Display Refresh SR. The combined program, listed in Figure 2-3.8-1 follows the model of two
prioritized SR's of Figure 2-3.6-1. SR2 is generated by a 16 character dynamic display, and the characters are
refreshed cyclically. Figure 2-3.8-2 lists the parameters of the two SR's and verifies that all requirements are
met for the two SR's to be successfully serviced. Note that use of Equation 13 provides a measure of the
efficiency of usage of the MPU processing time. In this case:
1 - ( - 40
66.6

+ -50~ = 1 - 0.985 = 0.015
130

which implies that 98.5% of the total processing time is being used.
The amount of spare time remaining is calculated by multiplying the left-hand side of Equation 13 by
the period of the highest frequency SR. Thus,
Unused processing time = 0.015 x 66.6 = 1.00j.ts every SRI period.

LABEL

MNEMONIC

OPERAND

LOOPC

LDAA

CLKDAT

LOAD CLOCK & DATA

BPL

LOOPD

BRANCH TO DISPLAY IF SRt
IS INACTIVE

COMMENT

PROCESSOR CYCLES

WO~ T41

Ton

RORA

I
I

ROLB

4
6

I
I

BCC

LOOPC

T21

SEE FIG. 3B

PSH B

LOA B

#01

DEC

COUNT

BNE

LOOPC

2
6

......L

EXIT

TOTAL

LOOPD

DSP2

LDAA

DSPCTL

LOAD DISPLAY CONTROL WORD

BPL

LOOPC

BRANCH TO CASSETTE IF SR2
IS INACTIVE

BSR

DSP2

BRANCH TO DISPLAY SUBROUTINE IF SR2 IS ACTIVE

LDAA

DATA,X

LOAD DISPLAY CHARACTER
(INDEXED ADDRESSING)

STAA

DISPLY

REFRESH DISPLAY

DEX

DSPEND

5
5

DECREMENT INDEX REG

T22

BNE

DSPEND

16 CHARACTERS REFRESHED?

LOX

#16

LOAD THE NUMBER 16 IN INDEX
REGISTER

RTS

T42

RETURN FROM SUBROUTINE

EXIT 2

TOTAL

4
3
~

42 + 8

FIGURE 2-3.8-1. Serial Data Transfer and Dynamic Display Refresh Routine

2-41

PARAMETERS OF SR1

(SERIAL DATA)

T01

66.6J,Ls

T21

T11

1J,Ls

AND T3
16
T01

T01

66.6
~

+ 2 x 16

T01

66.6

+ nT3

T21

T11

T41

0.5

T02

PARAMETERS OF SR2 (DISPLAY REFRESH)
130J,LS
50

130

5 x 16

AND

50J,LS

1 -

FROM EQU. 13

1 _ L T2m
m TOm
1

- (40
66.6

+ 50)

0.015

130

FROM EQU. 14
T 01

66.6 -

T 11

1 - 0.5

T 41

T 22

FROM EQU. 15

130

1 -

+ 16

FIGURE 2·3.8·2. Serial Data Display SR Parameters and
System Requirement Test

2-3.9

INCREASING MPU PROCESSING EFFICIENCY WITH THE FLIP-FLOP MODEL FOR
TWO "EQUAL" PERIOD SR'S
When the SR's have approximately equal SR periods, as in Read/Write, or bi -directional data flow,

the processing time for SR2 may be reduced if a flip- flop model is used in place of the prioritized model. Figure
2-3.9-1 shows the Flip-Flop model in which, after completion of SR 1 processing, the program checks SR2 first
and vice versa.
242

PROCESS
SRl

PROCESS
SR2

FIGURE 2-3.9-1. Flip-Flop Model for Two "Equal" Period SR's

The advantage gained in processing efficiency is reflected in the fastest data rate that the program
can successfully transfer for both SR 's. This can be illustrated using the example of cassette serial data transfer.
Let SRI and SR2 programs be identical in form such that:
T4l = T42 = 0.5JLs
Tll = T12 = IJLs
T3 = 16JLs
MAX TOl =T02 = ?
If the prioritized model is used, then:

T21 = 40JLs and T22 = 50JLs
because it takes 8JLs to test if SRI is active and this is always tested first.
In this case, the maximum data transfer rate for the two SR's may be calculated by using the equality
in Equation 13.
40

-+
TOl

50
(T02 = TOl)

1
TOl = - - = 11.IKbits/sec.
90JLs
If the flip-flop model is used then.

2-43

and the maximum data transfer rate for the two SR's may be calculated from Equation 13 as:

-+---- =
T01

(To2 = T01)

T01 = - - = 12.5 Kbits/sec.
80ILS
This provides approximately a ten percent increase in maximum data rate.
Note, however, that when the flip-flop model is used there is an additional condition that now must
be satisfied. This is required because both SRI and SR2 may occur simultaneously. Therefore,
(16)

The techniques described in this section enable the user to determine if a given data transfer program
will work in the microprocessor system. If it is found that the program does not work, the user may modify the
program/hardware to allow the system to work. The techniques also provide a measure of the utilization of the
microprocessor's capability. This provides the opportunity to add functions to or delete hardware from the
system until the microprocessor is being used to its full capability. The techniques may be extended to cover
operation of systems where interrupts are the periodic service requests.

2-4

USE OF INDEX REGISTER
Effective programming of the MPU makes extensive use of the Indexed Addressing mode. For this

mode, the address is variable and depends on the current contents of the Index Register. A source statement
such as
Operator

Operand

Comment

LDAA

Load ACCA from M=X

will cause the contents of the memory location specified by the contents of the Index Register to be loaded into
accumulator A, that is, the effective address is determined by X. Since there are instructions for manipulating
the contents of the Index Register during program execution (LDX, INX, DEX, etc.), the Indexed Addressing
mode provides a dynamic "on the fly" way to modify program activity.
The Index Register can be loaded either with "constants" such as the starting address of a file in
ROM or with a variable located in RAM that changes as the program runs. The Indexed Addressing mode also
allows the address to be modified by an offset. The operand field can include a value that will be automatically
added to X during execution. The format for this technique is:
Operator

Operand

Comment

STAA

K,X

Store ACCA in M=(X+K)

When the MPU encounters the opcode for LDAA (Indexed), it looks in the next memory location for the value
to be added to X and calculates the required address, X + K in this example. (See Section 1-2.3.5 for additional
information on the Indexed Addressing Mode.) The control program is normally in ROM, hence, the offset is a

2-44

constant that was established during program development and cannot be changed during program execution.
There are numerous examples of indexed addressing techniques in the sample programs throughout
this Manual, however, it is of interest to summarize some of the methods in this Section. A common usage is
shown in the following sequence of instructions for setting a series of RAM locations to zero (perhaps part of an
initialization routine):
Label

LOOP!

Operator

Operand

Comment

LDX

#FIRST

CLR
INX

Get starting Address
Clear current location.
Move to next location.

CPX
BNE

LAST+!
LOOP!

xxx

xxxxxx

Finished yet?
No, continue clearing.
Yes, continue with program.

This sequence causes the consecutive memory locations FIRST through LAST to be cleared. The labels
FIRST, LAST, NEXT, etc., will have been assigned specific values during assembly of the program. Note that
only every other memory location would be operated on if a second INX had been included in the program:

LOOP!

LDX
CLR
INX

INX
CPX
BNE

LAST +2
LOOP!

xxx

xxxxxx

This technique is commonly used to establish the "size" of the increment that will be stepped through. If the
size of the step is large (many INXs) or if it is desirable to have a variable step size, another procedure can be
used to advantage. The following sequence of instructions can be used to effectively add a variable offset to X:
2-45

Label

LOOPl

Operator

Operand

Comment

LDAB
LDX

VALUE
#FIRST

INX
DECB
BNE

LOOPl

Get variable into ACCB.
Get Starting Address.
Advance address pointer.
Is ACCB zero yet?
No, continue advancing pointer.

xxx

xxxxxx

Yes, proceed with program.

This sequence has the effect of adding the contents of accumulator B to the Index Register, that is, a variable
offset is generated. If, for example, the value in ACCB is one, the INX instruction increases X by one and the
DECB instruction reduces ACCB to zero. The program flow falls through to NEXT since the BNE test fails but
the Index Register is now loaded with X + 1 rather than X. A different value for B would cause the program to
pass through the loop until B is reduced to zero. Since X is increased by one during each pass, the net effect is to
add the variable "VALUE" to X.
This technique is illustrated in the following example: A program is required that will check for a
zero result in every 8th location in a block of memory extending from FIRST to LAST. The first zero result
encountered is to cause the program to branch to location ZROTST. If no zero results are encountered,
processing is to continue:

BEGIN

LDX

#FIRST

Get starting address.

START
LOOPl

LDAB
INX
DECB

#$08

BNE

LOOPl

Load step size.
Advance address pointer.
Next location yet?
No, continue advancing pointer.

TST
BEQ

ZROTST

CPX
BNE

LAST+l
START

xxx

xxx xxx

Yes, test for zero result.
Branch to zero test if zero.
Finished?
No, move to next location.
Yes, continue with program.

In this case, the program will pass through LOOPl eight times prior to each test, effectively adding eight to the
value in the Index Register. Note also that the INX instruction could be replaced by the decrement X
instruction, DEX, thus providing a means of "negative" or backward indexing if desired.
There is another "variable indexing technique" that combines the Indexed Addressing mode with
suitable memory allocation to obtain dynamic indexed addressing. Assume that a program is required that will
2-46

select a mask pattern that is determined by the current contents of a counter. The counter content is variable and
depends on the results of previous program operation. Such sequences are useful for establishing particular bit
patterns required by the program.
As an example, assume that one of the bit patterns shown below is required, depending on the
current value of BITCNT, a value that has been previously computed and stored in RAM:
Bit Pattern

Bit Count
b7

1
0
0

0
0
0
0

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
1

5
6
7

b2
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

0
0
0
0
0
0

The following memory allocation can be used to permit indexed addressing of the desired pattern:
COLBIT

STARTI (XH) n
} RAM
BITCNT (XL) n+ 1
~

START 1

1
2
3

BIT COUNT 4
5

6
7

10000000
01000000
00100000
00010000
00001000
00000100
00000010
00000001

m
m+l

By putting the upper byte of the starting address of the table (upper byte of m

ROM

= START 1) in the RAM location

immediately preceding BITCNT , the LDX instruction can be used to load the Index Register with the address of
the desired bit pattern. This method has the limitation that the lookup table must begin (STARTl above) at an
address whose least two significant Hex digits are zero, that is, of the form XXOO. Such tables can be at the
beginning of any multiple of 256 ROM locations.
This technique is illustrated in the following sample program for updating a bit pattern stored in two
PIA Output Registers, PIA ORA and PIA ORB . The registers contain a pattern for driving an external display
array that must be updated to include the results of each new calculation of a word count, WRDCNT, and a bit
count, BITCNT. The current update goes to PIA ORA if the word count is odd and to PIAORB if even. The
steps involved in the update are:
(1) Test WRDCNT for odd or even and set a flag.
(2) Get PIA ORA (odd WRDCNT) or PIA ORB (even WRDCNT) into accumulator A.

2-47

(3) Determine the bit pattern that corresponds to the current BITCNT.
(4) Combine with the contents of accumulator A, preserving any previously set bits.
(5) Write updated pattern back into appropriate PIA register.
The following program can be used if the memory allocation recommended above is used:

ROR

WRDCNT

Sets Carry if odd.

ROR
BMI

COLFLG
TAG!

Set sign bit on odd WRDCNT.
Get appropriate register.

LDAA
BRA

PIAORB
TAG2

LDAA
LDX

PIAORA
COLBIT

* into
* ACCA
* for update

ORAA
TST

BMI

TAG3

STAA
BRA

PIAORB
TAG4

TAG3

STAA

PIAORA

TAG4

xxx

xxxxxx

TAG!
TAG2

COLFLG

Point to bit pattern.
Combine with previous pattern.
Put updated pattern.

* back.
* out
* to
* display

Note that the single instruction LDX COLBIT is all that is required to locate a ROM location that depends on a
dynamic program result.

2-48

CHAPTER 3
3.

INPUT/OUTPUT TECHNIQUES

3-1

INTRODUCTION

Due to the type of applications in which they are used, the capability to efficiently handle
Input/Output (I/O) information is perhaps the most important characteristic of microprocessor systems. The
M6800 architecture incorporates supervisory controls and interface devices that permit a wide variety of I/O
techniques to be used. This Chapter describes the I/O characteristics of the M6800 system and their use in
typical applications.
Most I/O information can be placed in one of two general categories: (1) control and status signals;
(2) data that is to be processed by the MPU. Much of the MC6800's flexibility in handling control and status
information depends on three system features:
(1) Many of the routine peripheral control tasks can be delegated to the interface adapters.
(2) Because the design of the interface adapters allows the MPU to treat peripherals exactly like
other memory locations, the memory reference instructions that operate directly on memory are
also used to control peripherals.
(3) While all MPU's must be able to continuously control simple peripherals under program
control, in many typical applications, the peripheral information to the MPU is often
asynchronous in nature and is best handled on an interrupt basis. The interrupt structure of the
MC6800 allows such applications to be processed in an orderly manner, that is, interrupts are
handled without disrupting other system tasks in progress.
The currently available interface devices are described in detail in Section 3-4. The various interrupt
control techniques are discussed in Sections 3-2 and 3-3.
In the M6800 system, all data movement between family elements (memory and/or peripheral
interface adapters) is normally done through the MPU via the Data Bus. This means that the transfers are
program controlled, that is, the movement is accomplished by execution of instructions such as Load, Store,
Push, Pull, etc. Numerous examples of programmed controlled data transfers are shown throughout this
manual. For example, a program for moving 8-bit bytes from a peripheral to memory (at the rate of 43,000
bytes per second) is described in conjunction with the floppy disk application discusse~ in Section 5-4.
In most system designs, it is possible to "speed up" data movement by surrendering program
control and transferring data directly between the other system elements. This bypassing of the MPU, usually
called Direct Memory Access (DMA) , requires that the MPU be provided with supervisory signals. In addition,
external hardware for generating addresses and controlling the transfer must be provided. The MC6800's
supervisory control features allow DMA to be accomplished in a variety of ways. The details of implementation
depend on the particular system configuration and timing requirements. Several methods and their relative
merits are discussed in Section 3-5 of this Chapter.
3-1

3-2

MC6800 INTERRUPT SEQUENCES
In a typical application, the peripheral devices may be continuously generating asychronous signals

(interrupts) that must be acted on by the MPU. The interrupts may be either requests for service or
acknowledgements of services performed earlier by the MPU. The MC6800 MPU provides several methods for
automatically responding to such interrupts in an orderly manner.
In the control of interrupts, three general problems must be considered: (1) It is characteristic of most
applications that interrupts must be handled without permanently disrupting the task in process when the
interrupt occurs. The MC6800 handles this by saving the results of its current activity so that processing can be
resumed after the interrupt has been serviced. (2) There must be a method of handling multiple interrupts since
several peripherals may be requesting service simultaneously. (3) If some signals are more important to system
operation or if certain peripherals require faster servicing than others, there must be a method of prioritizing the
interrupts. Techniques for handling each of these problems with the MC6800 will be described in the following
paragraphs.
The MPU has three hardware interrupt inputs, Reset (RES)l, Non-Maskable Interrupt (NMI) , and
Interrupt Request (IRQ). An interrupt sequence can be initiated by applying a suitable control signal to any of
these three inputs or by using the software SWI instruction. The resulting sequence is different for each case.

3-2.1

INTERRUPT REQUEST (IRQ)

The IRQ input is the mainstay of system interrupt control. Inputs to IRQ are normally generated in
PIAs and ACIAs but may also come from other user-defined hardware. In either case, the various interrupts
may be wire-ORed and applied to the MPU's IRQ input. This input is level sensitive; a logic zero causes the
MPU to initiate the interrupt sequence 2 • A flow chart of the IRQ sequence is shown in Figure 3-2.1-l.
After finishing its current instruction and testing the Interrupt Mask in the Condition Code
Register, the MPU stores the contents of its programmable registers in memory locations specified by
the Stack Pointer. (Operation of the Stack Pointer is discussed in Section 1-3 A.l.) This stacking process
takes seven memory cycles: two each for the Index Register and Program Counter, and one each for
Accumulator A, Accumulator B, and the Condition Code Register. The Stack Pointer will have been
decremented seven locations and is pointing to the next empty memory location.
The MPU's next step of setting the Interrupt Mask to a logic one is an important aspect of system
interrupt control. Setting the mask allows the control program to determine the order in which multiple
interrupts will be handled. If it is desirable to recognize another interrupt (of higher priority, for example)
before service of the first is complete, the Interrupt Mask can be cleared by a CLI instruction at the beginning of
the current service routine. If each interrupt is to be completely serviced before another is recognized, the eLI
instruction is omitted and a Return from Interrupt instruction, RTI, placed at the end of the service routine
restores the Interrupt Mask status from the stack, thus enabling recognition of subsequent interrupts.
Note that if the former method is selected (immediate enable of further interrupts), the original
interrupt service will still eventually be completed. This is due to the fact that the later interrupt also causes the
current status to be put on the stack for later completion. This process is general and means that interrupts can be
IThe bar convention over the symbols is used to indicate an active low signal condition.
2IRQ is a maskable input. If the Interrupt Mask Bit within the MPU is set, low levels on the IRQ line will not be recognized; the MPU
will continue current program execution until the mask bit is cleared by encountering the Clear Interrupt (CLI) instruction in the control
program, or an RTI is encountered.

3·2

Continue Executing
Current Program

r--_
~

c:::::>

Stack MPU
Contents

SP-7

S P-6

CCR

SP-5

ACCB

SP-4

ACCA

SP-3

INXH

SP-2

INXL

SP-1

PCH

PCL

...

Load Program Counter
With Contents of Memory
Locations: FFF8~ PCH
FFF9~ PCL

"'---

Jump to Interrupt
Service Routine as
Determ ined by PC

FIGURE 3-2.1-1: Hardware Interrupt Request Sequence

CONTENTS

ADDRESS

RES (Low Byte)

FFFF

RES (High Byte)

FFFE

NMI (Low Byte)

FFFD

NMI (High Byte)

FFFC

SW I (Low Byte)

FFFB

SW I (High Byte)

FFFA

IRQ(LowByte)

FFF9

IRQ (High Byte)

FFF8

FIGURE 3-2.1-2: Interrupt Vector, Permanent Memory Assignments

3-3

"nested" to any depth required by the system limited only by memory size. The status of the interrupted
routines is returned on a Last-In-First-Out (LIFO) basis. That is, the last result to be stacked is the first to be
returned to the MPU.
After setting the Interrupt Mask, the MPU next obtains the address of the first interrupt service
routine instruction from memory locations permanently assigned to the IRQ interrupt input. This is
accomplished by loading the Program Counter's high and low bytes from memory locations responding to
addresses, FFF8 and FFF9, respectively. The MPU then fetches the first instruction from the location now
designated by the Program Counter.
This technique of indirect addressing (also called vectoring) is also used by the other interrupt
sequences. The' 'vectors" are placed in the memory locations corresponding to addresses FFF8 through FFFF
as shown in Figure 3-2.1-2 during program development.
The MPU places two of the address bytes in the range FFF8 - FFFF on the Address Bus during
interrupt sequences. It should be noted that the vector data is fetched from the memory locations that respond to
these addresses even though they may not actually be FFF8 - FFFF. For example, in the memory allocation
that was illustrated in Section 1-1.2.1 of Chapter 1, the ROM was assigned the 1024 memory locations between
CODa and C3FF (decimal 49152 to 50175) by tying Address Lines Al5 and A14 to the ROM's chip enables:
Address
Lines

A15 Al4 Al3 A12 Al1 Alo A9

ROM
Connections

x x
-----

X
Not Connected
......
~--_./

Notice that if the MPU outputs the address FFFF (all ones) while fetching the vector data for a Reset,
it is actually addressing memory location C3FF in the system memory.
The significant point is that the eight locations that respond to FFF8 - FFFF must be reserved for
the interrupt vectors.
3-2.2

NON-MASKABLE INTERRUPT (NMI)

As implied by its name, the Non-Maskable Interrupt (NMI) must be recognized by the MPU as soon
as the NMI line goes to logic zero. This interrupt is often used as a power-failure sensor or to provide interrupt
service to a "hot" peripheral that must be allowed to interrupt.
Except for the fact that it cannot be masked, the NMI interrupt sequence is similar to IRQ (See
Figure 3-2.2-1). After completing its current instruction, the MPU stacks its registers, sets the Interrupt mask
and fetches the starting address of the NMI interrupt service routine by vectoring to FFFC and FFFD. (See
Figure 3-2.1-2).
3-2.3

RESET (RES)

The Reset interrupt sequence differs from NMI and IRQ in two respects. When RES is low, the
MPU places FFFE (the high order byte of the RES vector location) on the Address Bus in preparation for
executing the RES interrupt sequence. It is normally used following power on to reach an initializing program
that sets up system starting conditions such as initial value of the Program Counter, Stack Pointer, PIA Modes,
34

etc. It is also available as a restart method in the event of system lockup or runaway. Because of its use for
starting the MPU from a power down state, the RES sequence is initiated by a positive going edge. Also, since it
is normally used only in a start-up mode, there is no reason to save the MPU contents on the stack. The flow is
shown in Figure 3-2.3-1. After setting the Interrupt mask, the MPU loads the Program Counter from the
memory locations responding to FFFE and FFFF and then proceeds with the initialization program.

Stack MPU
Contents

Set 1m

SP-7
SP-6

CCR

SP-5

ACCB

SP-4

ACCA

SP-3

INXH

SP-2

INXL

SP-1

PCH

PCL

Load Program Counter
With Contents of Memory
Locations: FFFC'-"PCH

FFFD~PCL

Jump to Interrupt
Service Routine as
Determined by PC

FIGURE 3-2.2.1: Non-Maskable Interrupt Sequence

Load Program Counter
With Contents of Memory
Locations: FFFE~ PCH
FFFF~PCL

Jump to Interrupt
Service Routine as
Determined by PC

FIGURE 3-2.3-1: Reset Interrupt Sequence

3-5

3-2.4

SOFTWARE INTERRUPT (SWI)
The MPU also has a program initiated interrupt mode. Execution of the Software Interrupt (SWI)

instruction by the MPU initiates the sequence shown in Figure 3-2.4-1. The sequence is similar to the hardware
interrupts except that it is ini tiated by "software" and the vector is obtained from memory locations responding
to FFFA and FFFB.
The Software Interrupt is useful for inserting break-points in the program as an aid in debugging and
troubleshooting. In effect, SWI stops the process in place and puts the MPU register contents into memory
where they can be examined or displayed.

r--~

c:::!>

SP-7
SP-6

CCR

SP-5

ACCB

SP-4

ACCA

SP-3

INXH

SP-2

INXL

SP-l

PCH

PCL

Load Program Counter
With Contents of Memory
Locations: F F FA PCH
FFFB PCL

Jump to Interrupt
Service Routine as
Determined by PC

FIGURE 3-2.4-1: Software Interrupt Sequence

3-6

3-3

INTERRUPT PRIORITIZING
In the previous section, the various methods available for finding the "beginning" of an interrupt

control program were described. If there is only one peripheral capable of requesting service, the source of the
interrupt is known and the control program can immediately begin the service routine. More often, several
devices are allowed to originate interrupt requests and the first task of the interrupt routine is to identify the
source of the interrupt.
There is also the possibility that several peripherals are simultaneously requesting service. In this
case, the control program must also decide which interrupt to service first. The IRQ interrupt service routine in
particular may be complex since most of the I/O interrupts are wire-ORed on this line.
The most common method of handling the multiple and/or simultaneous IRQ interrupts is to begin
the service routine by "polling" the peripherals to see which one generated the request. If the interrupts are
generated by peripheral signals coming in through a PIA or an ACIA, the polling procedure is very simple. In
addition to causing IRQ to go low, the interrupting signal also sets a flag bit in the PIA's or ACIA's internal
registers. Since these registers represent memory locations to the MPU, the polling consists of nothing more
than stepping through the locations and testing the flag bits 3 .
Establishing the priority of simultaneous interrupts can be handled in either of two ways. The
simplest is to establish priority by the order in which the PIAs and ACIAs are polled. That is, the first I/O flag
encountered gets the service, so higher priority devices are polled first. The second method first finds all the
interrupt flags and then uses a special program to select the one having highest priority. This method permits a
more sophisticated approach in that the priority can be modified by the control program. For example, it might
be desirable to select the lower priority of two simultaneous requests if the lower priority has not been serviced
for some specified period of time.
Software techniques can, in theory, handle any number of devices to any sophistication level of
prioritizing. In practice, if there are many sources of interrupt requests, the time required to find the appropriate
interrupt can exceed the time available to do so. In this situation, external prioritizing hardware can be used to
speed up the operation.
One method for implementing hardware prioritized interrupts is shown in block diagram form in
Figure 3-3-1. With this technique, each interrupting device is assigned its own address vector which is stored in
ROM memory similarly to the RES, SWI, IRQ, and NMI vectors. An external hardware priority encoder
selects the interrupt to be recognized and directs the MPU to the proper locations in memory for obtaining the
vectors.
Operation of the MPU itself is unchanged; after recognizing an IRQ, the MPU still outputs addresses
FFF8 and FFF9 as before. However, some of the address lines are no longer tied directly to memory but go
instead to a 1-of-2 Data Selector. The other set of inputs to the Data Selector are generated by a Priority Encoder
that outputs a binary number corresponding to the highest priority interrupt signal present at the time the
interrupt was recognized by the MPU.
Detection of the FFF8 and FFF9 addresses by the Address Bus monitoring circuitry then causes the
outputs of the priority encoder to be substituted for part of the normal address. Hence, even though the MPU
outputs FFF8 and FFF9, other locations in ROM are read by the MPU. Suitable vectors for sending the MPU
directly to the appropriate service routine are stored in these locations. Specific circuits for implementing this
prioritizing method are described in Section 4-2.1.
3See Section 5-4 for a specific example of software polling.

3-7

Interrupt
Address
Decode

Address Bus

12
13

I (n-1)

•

Priority
Encoder
Interrupt
Partial Address

1-of-2
Data
Selector

MPU
Memory
(MCM6830
ROM)

Data
Bus

FIGURE 3-3-1: Hardware Interrupt Prioritizing Block Diagram

3-4

PROGRAM CONTROLLED DATA TRANSFERS

3-4.1

MC6820 PERIPHERAL INTERFACE ADAPTER

3-4.1.1

Input/Output Configuration:
The MC6820 Peripheral Interface Adapter (PIA) provides a flexible method of connecting

byte-oriented peripherals to the MPU. The PIA, while relatively complex itself, permits the MPU to handle a
wide variety of equipment types with minimum additional logic and simple programming. An Input/Output
Diagram of the MC6820 is shown in Figure 3-4.1.1-1.
Data flows between the MPU and the PIA on the System Data Bus via eight bi-directional data lines,
DO through D7. The direction of data flow is controlled by the MPU via the Read/Write input to the PIA.
The" MPU side" of the PIA also includes three chip select lines, CSO, CS 1, and CS2, for selecting a
particular PIA. Two addressing inputs, RSO, and RS 1, are used in conjunction with a control bit within the PIA
for selecting specific registers in the PIA. The MPU can read or write into the PIA's internal registers by
addressing the PIA via the system Address Bus using these five input lines and the R!W signal. From the MPU' s
point of view, each PIA is simply four memory locations that are treated in the same manner as any other
read/write memory.
The MPU also provides a timing signal to the PIA via the Enable input. The Enable (E) pulse is used
to condition the PIA's internal interrupt control circuitry and for the timing of peripheral control signals. Since
all data transfers take place during the cp2 portion of the clock cycle, the Enable pulse is normally cp24.
The "Peripheral side" of the PIA includes two 8-bit bi-directional data buses (PAO-PA7 and
PBO-PB7), and four interruptlcontrollines, CAl, CA2, CB1, and CB2. All of the lines on the "Peripheral
Side" of the PIA are compatible with standard TTL logic. In addition, all lines serVing as outputs on the "B"
side of each PIA (PBO-PB7, CB1, CB2) will supply up to one milliamp of drive current at 1.5 volts.
4

See Section 4-1. 3 for exceptions required in some applications.

3-8

CA1
IRQA
CA2

IRQB
DB - DB7

RS
RS1
CS
CS1

PA-PA7

MC6820
Peripheral
Interface
Adapter
(PIA)

CS2
PB - PB7
R/W

Enable

CB2

Res

CB1

::l

~
ro
0

FIGURE 3-4.1.1-1: MC6820 PIA 1/0 Diagram

3 -4. 1.2

Internal Organization:
An expanded Block Diagram of the PIA is shown in Figure 3-4.1.2-1. Internally, the PIA is divided

into two symmetrical independent register configurations. Each half has three main features: an Output
Register, a Control Register, and a Data Direction Register. It is these registers that the MPU treats as memory
locations, i.e., they can be either read from or written into. The Output and Data Direction Registers on each
side represent a single memory location to the MPU. Selection between them is internal to the PIA and is
determined by a bit in their Control Register.
The Data Direction Registers (DDR) are used to establish each individual peripheral bus line as
either an input or an output. This is accomplished by having the MPU write "ones" or "zeros" into the eight
bit positions of the DDR. Zeros or ones cause the corresponding peripheral data lines to function as inputs or
outputs, respectively.
The Output Registers, ORA and ORB, when addressed, store the data present on the MPU Data Bus
during an MPU write operation 5 . This data will also appear on those peripheral lines that have been

As used here, an "MPU Write" operation refers to the execution of the "Store" instruction, i.e., writing into Output Register A is
equivalent to execution of STAA PIAORA by the MPU. Similarly, an "MPU Read" operation is equivalent to execution of the
"Load" instruction: LDAA PIAORA.

3-9

IROA

38.

04 29
05

I nterrupt Status
Control A

Data Direction
Register A
(DORA)

Data Bus
Buffers
(DBB)

Output Bus
2
Output
Register A
(ORA)

Bu~ iflput.

4 PA2

CS2

RSO

RSl

R/W

Enable

Reset

PA4

....:)

c.
c

PA6

PA7

10 PBO

VSS= Pin 1

5 PA3
6

7 PA5

III
:)

VCC = Pin 20

PAO

3 PAl

Peripheral
Interface
A

CSl

39 CA2

CSO

40 CAl

Output
Register B
(ORB)

PBl

12 PB2
Peripheral
Interface
B

Chip
Select
and
R/W
Control

PB3

14 PB4
15

PB5

16 PBS
17 PB7

Data Direction
Register B
(DDRB)

Interrupt Status
Control B

IROB 37

FIGURE 3-4.1.2-1: MC6820 PIA - Block Diagram

3-10

18 CB1
19 CB2

programmed as outputs. If a peripheral line has been programmed as an input, the corresponding bit
position of the Output Register can still be written into by the MPU, however, the data will be
influenced by the external signal applied on that peripheral data line.
During an MPU Read operation, the data present on peripheral lines programmed as inputs is
transferred directly to the system Data Bus. Due to differing circuitry, the results of reading positions
programmed as outputs differ slightly between sides A and B of the PIA. On the B side, there is three-state
buffering between Output Register B and the peripheral lines such that the MPU will read the current contents
of ORB for those bit positions programmed as outputs. (See Figure 3-4.1.2-2.) During an MPU Read of the A
side, the data present on the Peripheral lines will effect the MPU Data Bus regardless of whether the lines are
programmed as outputs or inputs. The bit positions in ORA designated as outputs will be read correctly only if
the external loading on the Peripheral lines is within the specification for one TTL load. That is, a logic one
level could be read as a logic zero if excessive loading reduced the voltage below 2.0 volts.
The two Control Registers, CRA and CRB, allow the MPU to establish and control the operating
modes of the peripheral control lines, CAl, CA2, CB 1, and CB2. It is by means of these four lines that control
information is passed back and forth between the MPU and peripheral devices. The control word format and a
summary of its features is shown in Figure 3-4.1.2-3.
The Data Direction Register access bit (b2 = DDR Access) is used in conjunction with the register
select lines to select between internal registers. For a given register select combination, the status of the DDR
bit determines whether the Data Direction Register (b2 of DDR = 0) or the Output Register (b2 of DDR = 1) is
addressed by the MPU.
+5

To Data
Bus
From ORA

~----<

t------_.......__

PAx

»----------4

0= True Data

A) A - Side

From DDR

To Data Bus

~--~-------_+----_e~

From ORB

1 = True Data
B) B - Side

FIGUR E 3-4.1.2-2: PIA Output Circuit Configurations

3-11

__-~PBx

Determine Active CA 1 (CB 1) Transition for Setting
Interrupt Flag I RQA(B)1 -(bit b7)
b1 = 0: IRQA(B)1 set by high-to-Iow transition on
CA 1 (CB1).
b1 = 1

I RQA(B) 1 set by low-to-high transition on
CA1 (CB1).

CA 1 (CB1) Interrupt Request Enable/Disable
bO = 0: Disables IRQA(B) MPU Interrupt by CA1 (CB1)
active transition. 1
bO = 1 : Enable I RQA(B) MPU Interrupt by CA 1 (CB1)
active transition.

I RQA(B) 1 Interrupt Flag (bit b7)
Goes high on active transition of CA1 (CB1); Automatically
cleared by MPU Read of Output Register A(B). May also be
cleared by hardware Reset.

I RQA( B) will occur on next (MPU generated) positive
transition of bO if CA1 (CB1) active transition occurred
while interrupt was disabled.

I
b6

b7
I RQA(B)1
Flag

CA2(CB2)
Control

I RQA(B)2
Flag

DDR
Access

bet>

CA1(CB1)
Control

I RQA(B)2 Interrupt Flag (bit b6)
CA2 (CB2) Established as Input (b5 = 0): Goes high on active
transition of CA2 (CB2); Automaticallv cleared by MPU RpFtrl
of Output Register A(B). May also be cleared by hardware
Reset.
CA2 (CB2) Established as Output (b5 = 1): IRQA(B)2
not affected by CA2 (CB2) transitions.

Determines Whether Data Direction Register Or Output
n~9ister is Addressed
b2 =

a : Data

Direction Register selected.

= 0,
b2 = 1 : Output Register selected.

1
CA2 (CB2) Established as Output by b5
b5

CA2 (CB2) Established as Input by b5

(Note that operation of CA2 and CB2
output functions are not identical)

~CA2

b3 = 0:

Read Strobe With CA 1 Restore
CA2 goes low on first high-tolow E transition following an
MPU Read of Output Register
A; returned high by next
active CA 1 transition.

b3 = 1:

b3 = 0:

Disables I RQA(B) MPU
Interrupt by CA2 (CB2)
active transiti on. 1

b3 = 1:

Enables I RQA(B) MPU
Interrupt by CA2 (CB2)
active transition.

I RQA(B) will occur on next (MPU
generated) positive transition of b3
if CA2 (CB2) active transition
occurred while interrupt was
disabled.

Write Strobe With E Restore

b4 = 0:

I RQA(B)2 set by high-to-Iow
transition on CA2 (CB2).

b4 = 1:

I RQA(B)2 set by low-to-high
transition on CA2 (CB2).

CB2 goes low on first low-tohigh E transition following an
MPU Write into Output
Register B; returned high by the
next low-to-high E transition.

CA2 (CB2) Interrupt Request Enable/
Disable

' - - - -....
Determines Active CA2 (CB2) Transition
for Setting Interrupt Flag I RQA(B)2 (bit b6)

Write Strobe With CB1 Restore
CB2 goes on low on first lowto high E transition following
an MPU Write into Output
Register B; returned high by
the next active CB1 transition.

.2.£

~CB2

b3 = 1:

Read Strobe with E Restore
CA2 goes low on first high-tolow E transition following an
MPU Read of Output Register
A; returned high by next
high-to-Iow E transition.

b3 = 0:

b4
-,-

Set/Reset CA2 (CB2)
CA2 (CB2) goes low as MPU writes
b3 =
into Control Register.

CA2 (CB2) goes high as MPU writes
b3 = 1 into Control Register.

FIGURE 3-4.1.2-3: PIA Control Register Format

3-12

Each Control Register has two interrupt request flags, b7

= IRQA(B) 1 and b6 = IRQA(B)2; they are

set by transitions on the CA1(CB 1) and CA2(CB2) control lines and can be read by an MPU read Control
Register operation. The status of the interrupt flags cannot be altered by an MPU write instruction, that is,
IRQA(B) 1 and IRQA(B)2 are Read Only with respect to the MPU. They are indirectly reset to zero each time
the MPU reads the corresponding Output Register or can be cleared with the hardware Reset.
Bits bo and bl of the Control Registers determine the CA1(CB 1) operating mode. A "one" written
into bl by the MPU will cause subsequent positive-going transitions of the CA1(CB 1) input to set IRQA(B)1; if
bl = 0, negative-going transitions on CA1(CB 1) cause IRQA(B)1 to set. If bo = 1 when the IRQA(B)1 flag
goes high, the PIA's external interrupt request line, IRQA(B), immediately goes low, providing a hardware
interrupt signal to the MPU. The external interrupt is disabled if bo = 0 when the internal interrupt is set by
CA1(CB1). Ifbo is later set by an MPU Write Control Register operation, the disable is immediately released
and a pending external interrupt request will occur.
When b5 = 0, b3 and b4 of the Control Register perform similarly to bo and bl, controlling the
IRQA(B)2 interrupt via the CA2(CB2) input. The IRQA(B) interrupt terminal, when enabled, responds to
either IRQA(B) 1 or IRQA(B)2.
Ifb5

= 1, CA2(CB2) acts as an output and will function in one of three modes. Ifb4 is also equal to

one, CA2(CB2) serves as a program-controlled set/reset output to the peripheral and follows b3 as it is changed
by MPU Write Control Register operations. If b4 = 0 when b5 = 1, CA2(CB2) can be used in either a
pulse-strobed or handshake mode. Operation of the two sections differ slightly for these two operating modes.
In the handshake mode (b3 = 0) CA2 is taken low by the negative transition of the MPU Enable Pulse following
an MPU Read Output Register operation and returns high when IRQA1 is next set by CAl. This, in effect, tells
the peripheral it has been read and allows it to acknowledge via CA 1. The' 'B" Side operation is similar except
that CB2 is taken low following an MPU Write Output Register operation and returned high by the next CB 1
transition; this tells the peripheral it has been written into and allows it to respond via CB 1.
In the pulse-strobed mode (b3 = 1), CA2 is again set low by a Read Output Register command, but is
now returned high by the negative transition of the next MPU originated Enable Pulse. CB2 operation is similar
except that an MPU Write Operation initiates the pulse. Relative timing waveforms for the strobe control
modes are shown in Figures 3-4.1.2-4 and 3-4.1.2-5. The use of A side for Read and B side for Write in those
figures is not meant to imply that the A and B sides must be used only for peripheral data in and out,
respectively. However, the strobe modes are implemented only as shown, i.e., a strobe is not generated by an A
side Write or a B side Read. Strobes can be generated for these cases by including "dummy" instructions in the
program. For example, an A side Write instruction can be followed immediately by an A side dummy Read to
generate the strobe. Similarly, a B side Read can be followed by a dummy Write.

3-13

Enable

~~~---r--~----------------~-------------------------2.4V

Address

1'---.,.....---+----+-------------+------------------------ 0.4 V

2.4V
0.4
~-T-H-R---~--+--------------2.4 V
---------------/ ~At:2==========3====:=r======T=R=S=1================ 0.4 V
CA2
2.4
2.0------------V
(CRA-5 = CRA-3 = 1, CRA-4 =
------0.4 V
-----2.4V
CA1
Peripheral

--------~ j~~~_4----~--~~----------------_+-----------------------------

Data

~....;;;....;....------1r--t--------------_+---------------------

Data Bus

0.8 V

CA2 = CRA-4 = 0)
(CRA-5 = 1, CRA-3

\----------------------~
Loading

= 30 pF and one TTL load for PAO·PA 7, PBO·PB7, CA2, CB2
= 130 pF and one TTL load for DO-D7 IROA IROB)
Symbol

Min

Typ

Max

Unit

TAEW

180

Delay Time, Enable positive transition to Data valid on bus

TEDR

395

Peripheral Data Setup Time

TPDSU

300

THR

Delay Time, Enable negative transition to CA2 negative transition

TCA2

1.0

!J.s

Delay Time, Enable negative transition to CA2 positive transition

!J.s

Characteristic
Delay Time, Address valid

Enable positive transition

Data Bus Hold Time

TRSl

1.0

Rise and Fall Time for CA 1 and CA2 input signals

tr,tf

1.0

!J.s

Delay Time from CA 1 active transition to CA2 positive transition

TRS2

2.0

!J.~

trE, tfE

Rise and Fall Time for Enable input

FIGURE 3-4.1.2-4: Read Timing Characteristics

3-14

Enable

.---l---------+------------- 2.4 V
'--4-----------lf------------ 0.4 V

Address

2.4 V
Read/Write

-,..;..:;.:..::......:;......-+-+-". , - - - - 1 · - - - - - - - - - 1 - - - - - - - - - - - - -

0.4

2.4

Data 8us
--------------~ ,~-J~~,__~~~----------------_4------~------------------- 0.4V

Vee - 30%

---------:..:::..:..:..-..:...-_..JIo"-....i...oL---------+--------------2.4V
Peripheral Data

(CR 8-5

C82
CR8-3 = 1. CR 8-4

----------- 1O;;;;';:'~~--------I__~----------- 0.4 V
1 . - - - - - - - - - - - - 2.4 V

= 0)

0.4 V
2.4 V

C81

0.4 V

(CR8-5

C82
1. CR8-3

2.4V

CR8-4

Characteristic

Symbol

Min

Typ

Max

Unit

0.470

J..LS

Delay Time. Address valid to Enable positive transition

TAEW

180

Delay Time. Data valid to Enable negative transition

TDSU

300

Delay Time. Read/Write negative transition to Enable positive transition

TWE

130

Data Bus Hold Time

THW

Delay Time. Enable negative transition to Peripheral Data valid

TPDW

1.0

J..LS

TCMOS

2.0

J..LS

TCB2

1.0

J..LS

TDC

1.5

J..LS

TRS1

1.0

J..LS

tr,tf

1.0

J..LS

TRS2

2.0

J..LS

Enable Pulse Width

Delay Time. Enable negative transition to Peripheral Data Valid. CMOS
PAO-PA 7. CA2
(VCC - 30%)
Delay Time, Enable positive transition to CB2 negative transition
Delax Time, Peripheral Data valid to CB2 negative transition
Delay Time, Enable positive transition to CB2 positive transition
Rise and Fall Time for CB1 and CB2 input signals
Delay Time, CB1 active transition to CB2 positive transition

FIGURE 3-4.1.2-5: Write Timing Characteristics

3-15

3 -4. 1.3

Addressing and Initialization:
Chapters 6 and 7 of this manual include numerous examples of PIA addressing and initialization,

however, some basic considerations are discussed in the following paragraphs. As indicated in Section 3 -4. 1. 1 ,
the MPU addresses the PIA via the five chip select and register select inputs and bit 2 of the Control Registers.
The correspondence between internal registers and the address inputs is shown in Figure 3-4.1.3-1.
eS2

eS1

escf>

cf>
cf>
cf>
cf>
cf>
cf>

RS1

RScf>

cf>
cf>
cf>

cf>
cf>
1

cf>
1

cf>
cf>

cf>
1

X
X
X

X
X
X
X

X
X

cf>

X
X

X
X
X

Data Direction Register A (PIADRA)
Output Register A (PIAORA)
Control Register A (PIACRA)
Data Direction Register B (PIADRB)
Output Register B (PIAORB)
Control Register B (PIACRB)
PIA Not Selected
PIA Not Selected
PIA Not Selected

X = Doesn't Matter

FIGURE 3-4.1.3-1: PIA Register Addressing

Addressing a PIA can be illustrated in conjunction with the simple system configuration shown in
Figure ~-4. 1.3-26. The method sho'.vn is typical fer assigning mutually exclusive memory addresses to the
family devices without using additional address decode logic. The connections shown in Figure 3-4.1.3-2
assign memory addresses as follows:
RAM

0000 - 007F

PIA

4004 - 4007

ACIA

4008 - 4009

ROM

COOO- C3FF

(Hexadecimal notation)
In most cases, the desired I/O configuration and Control Register modes are established as part of an
initialization sequence. The steps involved depend on the particular application but can be clarified by means of
a specific example.
Assume that a PIA is to be used as the interface between two peripherals. When interrupted by a
positive transition on a control line, the MPU is to fetch 8 bits of data from Peripheral # 1 and then send an
acknowledgement pulse. The MPU must be able to transfer a byte of data to Peripheral #2 and receive
acknowledgement that it was accepted. Peripheral #2 must be provided with a control signal indicating that
there is data ready for it.
A suitable hardware configuration is shown in Figure 3-4.1.3-3. Peripheral Lines PAO-PA7 are
assigned to "read" Peripheral #1 and, hence, must be established as inputs. CAl provides the interrupt input
and must be conditioned to recognize incoming positive transitions. CA2 will be used to signal that data has
been read, hence, it must be established as an output using the pulse strobe mode, i.e., reading PIAORA 7 will
automatically transmit a pulse to the peripheral.
Peripheral Lines PBO-PB7 are assigned for transmitting data to Peripheral #2 and, hence, must be
established as outputs. CB2 will be used as an output for signalling that there is data ready. CB 1 will be
6Figure 3-4.1.3-2 is identical to Figure 1-1.2-1 and is discussed in Section 1-1.2 of Chapter 1.
7In order to use symbolic labels instead of absolute addresses in the initialization program, the labels introduced in Figure 3-4.1.3-1 will
be used to refer to PIA registers.

3-16

START-

02
CLOCK

MPU

VMA·02

VMA

DBO-DB7

AO-A9
ROM

- - -....-IE
L-_ _ _ _ _ _ _ _ _ _ _ _
- - -....-IE

'-----y---' '-----v--'
PARALLEL 1/0 (DATA AND CONTROL)
AO
A3

DBO-DB7

CSO
CS1
CS2

ACIA
E
R/W
IRO
CTS DCD RTS

FIGURE 3-4.1.3-2: Family Addressing

3-17

IRO

---

Data Ready

CA1

Data Accepted

CA2

PAO
PA1

-----

PA2

PA3
PA4
PA5
PA6

PA7

---

PBO

-..
..
..
---..
-

PB1
PB2
PIA

Peripheral
#1

PB3
PB4
PB5
PB6
PB7

Peripheral

Data Ready
CB2
CB1

Data Accepted

FIGURE 3-4.1.3-3: Typical I/O Configuration

3-18

conditioned to accept a negative transition acknowledgement signal from Peripheral #2. CB2 is to be restored
by that transition.
If it is known that a hardware system Reset is to be applied prior to initializing, all PIA register bits

will be zero initially and the following sequence can be used:
10

LDAA

#$2F

SELECT ORA; SET MODE CONTROL

STAA

PIACRA

30
40

COM
LDAA

PIADRB

ESTABLISH PBO-PB7 AS OUTPUTS

STAA

#$24
PIACRB

SELECT ORB; SET MODE CONTROL
FOR "B" SIDE

FOR "A" SIDE

The constantS $2F = 0010 1111 loaded into the A Control Register by Instruction 20 has the following effect: bO

= 1 enables a CA 1 interrupt; b 1 = 1 selects positive transition for interrupt recognition; b2 = 1 selects ORA
(the initial zeros in DDRA establishPAO-PA7 as inputs); b3 = 1, b4 = oselects read strobe with Erestore; b5 =
1 establishes CA2 as an output; b6 and b7 are don't cares since MPU cannot write into those two positions:
b7

b6
0

b5
1

b4
0

b3
1

b2
1

b1
1

nO
1 = 2F (Hex)

Instruction 30 writes "ones" into the B Data Direction Register, thus establishing PBO-PB7 as outputs. The
constant loaded into the B Control Register by instruction 50 has the following effect: bO

0 disables IRQB

interrupt by CB 1 transition (it is assumed that the MPU will read flag bit b7 to check for acknowledgement
rather than allowing an interrupt); b1

= 0 selects recognition of negative transition on CB 1 for setting flag bit 7;

b2 = 1 selects ORB; b3 = 0, b4 = 1 selects Write strobe with CB 1 restore; b5 = 1 establishes CB2 as an output;
b6 and b7 are don't cares:
b3

00100

o =

24 (Hex)

If there is no assurance that the PIA internal register bit positions are initially zero prior to

initialization, the following sequence can be used:
10

CLRA

STAA

PIACRA

30
40

STAA
STAA

PIACRB
PIADRA

AND DATA DIRECTION REGISTER B.
ESTABLISH PAO-PA7 AS INPUTS.

LDAA

SELECT ORA; SET MODE

STAA
LDAA

#$2F
PIACRA
#$FF
PIADRB

ESTABLISH

#$24

SELECT ORB; SET MODE

70
80
90

STAA
LDAA

100

STAA

SELECT

PIACRB

DATA DIRECTION REGISTER A

CONTROL FOR" A" SIDE.
PBO-PB7 AS OUTPUTS.
CONTROL FOR "B" SIDE.

Note that if the initialization sequence is started from a known hardware clear only half as many instructions are
required.
8Refer to Figure 3-4.1.2-3 for derivation of the Control Register words.

3-19

3-4.1.4

System Considerations:
The information provided in the preceding paragraphs has been limited to only the more obvious

characteristics of the PIA. The features described greatly simplify

VO processing, as will be seen in the

examples of later chapters. There are several general techniques worth considering as a system is configured.
The fact that the PIA registers are treated as memory combined with the fact that many of the MPU' s
instructions (CLR, ASL, COM, TST, etc) operate directly on memory makes possible a variety of I/O
techniques. This characteristic should be given careful attention when hardware/software tradeoffs are being
considered.
The flexibility inherent in being able to change the I/O direction of individual peripheral lines under
program control was not adequately stressed in the initialization discussion. A detailed example making use of
this feature to decode a switch matrix is included in Section 5-1.1.1.
Only a simple case of address assignment was considered. Other approaches may lead to a more
efficient system. As an example, consider the memory allocation that results from applying AO, and Al of the
address bus to RSO and RS 1, respectively:
RSI
(AI)

RSO
(AO)

PIAORA

1
0
1

PIACRA

PIA ORB
PIACRB
~

Here the registers alternate between output and Control 9 Registers. If AO is connected to RSI and Al to RSO,
the following result is obtained:
RSI
(AO)

RSO
(AI)

PIAORA

PIA ORB

0
1

PIACRA
PIACRB

Notice that the output registers are now in adjacent memory locations. This configuration can be used to
advantage in applications where 16 bits must be brought into memory. With both the A and B sides established
as input ports, the LDX and STX instructions can be used to efficiently transfer two bytes at a time. A specific
example of this technique is described in Section 5-4. If this allocation is selected, initialization routines such as
the first example of Section 3 -4 .1. 3 can also be simplified:
10

LDX

#$2F24

ESTABLISH CONTROL MODES

STX

PIACRA

FOR BOTH SIDES.

In this sequence, the single instruction STX causes the appropriate constant to be loaded into both Control
Registers.
9This assumes that b2 of the Control Registers has been set to select the Output Registers.

3-20

3-4.2

MC6850 ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER

3-4.2.1

Input/Output Configuration

The MC6850 Asynchronous Communications Interface Adapter (ACIA) provides a means of
efficiently interfacing the MPU to devices requiring an asynchronous serial data format. The ACIA includes
features for formatting and controlling such peripherals as Modems, CRT Terminals, and teletype
printer/readers. An Input/Output Diagram of the MC6850 is shown in Figure 3-4.2.1-1.
Data flow between the MPU and the ACIA is via 8 bi-directionallines, DBO through DB7, that
interface with the MPU Data Bus. The direction of data flow is controlled by the MPU via the Read/Write input
to the ACIA.
The "MPU side" of the ACIA also includes (see Figure 3-4.1.3-2) three chip select lines, CSO,
CS 1, and CS2, for addressing a particular ACIA. An additional addressing input, Register Select (RS), is used
to select specific registers within the ACIA. The MPU can read or write into the internal registers by addressing
the ACIA via the system Address Bus using these four input lines. From the MPU's addressing point of view,
each ACIA is simply two memory locations that are treated in the same manner as any other read/write memory.
The MPU also provides a timing signal to the ACIA via the Enable input. The Enable (E) pulse is
used to condition the ACIA's internal interrupt control circuitry and for the timing of status/control changes.
Since all data transfers take place during the 4>2 portion of the clock cycle, 4>2 is applied as the E signal.
The "Peripheral side" of the ACIA includes two serial data lines and three control lines. Data is
transmitted and received via the Tx Data output and Rx Data inputs, respectively. Control signals
Clear-To-Send (CTS) , Data Carrier Detect (DCD), and Request-To-Send (RTS) are provided for interfacing
with Modems such as the MC6860. Two clock inputs are available for supplying individual data clock rates to
the receiver and transmitter portions of the ACIA.

Clk Tx
Tx Data

IRQ
DBO - DB7

CTS
RTS

RS
CSO
CS1
CS2

MC6850
Asynchronous

DCD

Communications
Interface
Adapter
(ACIA)

R/W

E
Rx Data

If)

:::l

If)

:::l

~
(0
0

If)

:::l

If)
If)

"0
"0

Clk Rx

FIGURE 3-4.2.1-1: MC6850 ACIA I/O Diagram

3-21

elk Tx 4
~

Transmit
Clk. Gen.

Parity
Generation

j
DO 22
01

02 20

.........

.-.
18 ...--.
17 ...--.
16 .-..

03 19
04
05
06

07 15

IRQ 7

~
-

.........

+
Transmit
Data Reg.

JI.

Data Bus
Multiplexor/
4Buffers

,;t--"-r-

..........

hl
t-

Status
Register

Interrupt
Control

Transmit
Shift Reg.

6 Tx Data

Transmit
Control

Clock
Select

f4-

...
Control
Register

eso

CS1

CS2

'-----.
---.
11 -----.

R/W 13

-J

---.
----

I
Chip Select
and
R/W Control

24 CTS

Receive
Control

Receive
Data Reg.

Parity
Check

---41

Receive
Shift Reg.

5 RTS
23 DCD

2 Rx Data

+
Clk Rx 3

L+o

-..

Receive
Clk. Gen.

.....-

Sync .
Logic

FIGURE 3-4.2.2-1: ACIA Block Diagram

3 -4.2.2

Internal Organization
An expanded Block Diagram of the ACIA is shown in Figure 3-4.2.2-1. While the ACIA appears to

the MPU as two addressable memory locations, internally there are four registers, two that are Write Only and
two that are Read Only. The Read Only registers are for status and received data and the Write Only registers
are for ACIA control and transmit data.
The Status Register format and a summary of the status bits is shown in Figure 3-4.2.2-2. The first
two bits bO and b 1 indicate whether the Receiver Data Register is full (RDRF) or if the Transmit Data Register is
empty (TDRE). bO will go high when Rx data has been transferred to the Receiver Data Register (RDR). bO will
go low on the trailing edge of the Read Data command (reading the Receiver Data Buffer) or by a master reset
command from bits bO and b 1 of the Control Register.
Status bit bl (Tx Data Register Empty) will go high when a transmitter data transfer has taken place
indicating that the Transmit Data Register (TDR) is available for new data entry from the MPU Bus. Bit bl will
return low on the trailing edge of a write data command. bl will be held low if Clear-To-Send is not received
from a peripheral device (CTS = "1")
Status bits b2 (Data Carrier Detect) and b3 (Clear-To-Send) are flag indicators from an external
modem. Bit b2 (DCD) will be high when the received carrier at the modem has been lost (ACIA's DCD input is
high). Bit b2 will remain high until the interrupt is cleared by reading the Status Register and the Receiver Data
Register. Bit b3 (CTS) is low during reception of a Clear-To-Send command from a modem or other peripheral
device.
3-22

Data Carrier Detect
b2 = 0:
I ndicates carrier is present.
b2 = 1:
I ndicates the loss of carrier.
1. The low-to-high transition of the DCD input causes b2=1 and generates an interrupt
(b7=1), (IRQ=O)
2. Reading the Status Register and Rx Data
Register or master resetting the ACIA
causes b2=0 and b7=0.

Receiver Data Register Full
Indicates that the Receiver Data
Register is empty.
I ndicates that data has been transbO = 1:
ferred to the Receiver Data Register
and status bits states are set (PE,
OVRN, FE).
1. The Read Data Command on the high-tolow E transition or a master reset causes
bO = O.
2. A "high" on the DCD input causes bO=O
and the receiver to be reset.
bO

Interrupt Request
The interrupt request bit is the complement of
the I RQ output. Any interrupt that is set and
enabled will be available in the status register
in addition to the normal I RQ output.

l
r

b7
IRQ

b5
OVRN

.----_ _ _---ll

I
b4

CTS

b2
DCD

b1
TxDRE

Framing Error
b4

I ndicates the absence of the first stop
bit resulting from character synchronization error, faulty transmission, or
a Break condition.
1: The internal Rx data transfer signal causes
b4=1 due to the above conditions and causes
b4=0 on the next Rx data transfer signal if
conditions have been rectified.
= 1:

Transmitter Data Register Empty
b1 = 1:
b1
1.
2.

Overrun Error
3.

b5 = 1:

'--

Indicates that a character or a number of characters were received but
not read from the Rx data register
prior to subsequent characters being
received.
1. The Read Data Command on the high-tolow E transition causes b5=1 and bO=1 if an
overrun condition exists. The next Read
Data Command on the high-to-Iow E transition causes b5=0 and bO=O.

Indicates that the transmitter data
Register is empty.
= 0:
I ndicates that the transm itter data
Register is full.
The internal Tx transfer signal forces b1=1.
The Write Data Command on the high-tolow E transition causes b1=0.
A "high" on the CTS input causes b1=0.

Clear to Send

Parity Error

The CTS bit reflects the CTS input status for
use by the MPU for interfacing to a modem.
NOTE: The CTS input does not reset the
transmitter.

b6 = 1:

I ndicates that a parity error exists.
The parity error bit is inhibited if no
parity is selected.
1. The parity error status is updated during
the internal receiver data transfer signal.

FIGURE 3-4.2.2-2: ACIA Status Register Format

3-23

Bit b4 (Framing Error) will be high whenever a data character is received with an improper start/stop
bit character frame. The framing error flag b4 is cleared by the next data transfer signal if the condition causing
the framing error has been rectified. Bit b5 (Receiver Overrun) being high indicates that the Receiver Data
Register has not been read prior to a new character being received by the ACIA. This bit is cleared by reading
the Receiver Data Register. Status Register bit b6 (Parity Error) is set whenever the number of high (" 1 's' ') in
the received character does not agree with the preselected odd or even parity. Bit b7 (Interrupt Request) when
high indicates the ACIA is requesting interrupt to the MPU via the ACIA IRQ output and may be caused by bO
or b 1 or b2 being set. All of the Status Register bits (except b3) will be cleared by an ACIA Master Reset.
The Control Register is an eight bit write only buffer which controls operation of the ACIA receiver,
transmitter, interrupt enables, and the modem Request-To-Send control line. The Control Register format and a
summary of its features is shown in Figure 3-4.2.2-3.
Control bits bO and bl select a Master Reset function for the ACIA when both bits are high and
selects different clock divide ratios for the transmitter and receiver sections for the other combinations:
bl
(CDS2)

bO
(CDSI)

0
0
1
1

0
1
0
1

Clock Division
+ 1
+16
+64
Master Reset

The next 3 control bits, b2, b3, and b4, are provided for character length, parity, and stop bit
selection. The encoding format is as follows:
b4
(WS3)

b3
(WS2)

b2
(WSl)

1
1
1
1

0
1
1

Character Frame
7 Bit + Even Parity + 2 Stop Bits
7 Bit + Odd Parity + 2 Stop Bits
7 Bit + Even Parity + 1 Stop Bit
7 Bit
8 Bit
8 Bit
8 Bit
8 Bit

+ Odd Parity + 1 Stop Bit
+ No Parity + 2 Stop Bits
+ No Parity + 1 Stop Bit
+ Even Parity + 1 Stop Bit
+ Odd Parity + 1 Stop Bit

The ACIA transmitter section is controlled by control bits b5 (TC 1) and b6 (TC2). The four
combinations of these two inputs provide transmission of a break command, Modem Request-To-Send (RTS)
command, and a transmitter inhibit/enable for the ACIA Interrupt Request output. When both b5 and b6 are
low, the Request-To-Send (RTS) output will be active low and the transmitter data register empty flag is
inhibited to the ACIA's Interrupt Request (IRQ) output. If b5 is high and b6 is low the RTS output remains
active low but the transmit IRQ input is enabled. To turn off the RTS output b6 should be high and b510w. This
selection also inhibits the transmitter interrupt input to the IRQ output. When both b5 and b6 of the control
register are high, Request-To-Send is on (RTS) = 0, IRQ is inhibited for the transmitter, and a break is
transmitted (a space).
3-24

Enable for Receiver Interrupt
b7 = 1:

b7 = 0:

Counter ratio and Master reset select used
in both transmitters and receiver sections

Enables Interrupt Output in
Receiving Mode
Disables Interrupt Output in
Receiving Mode

Function (Tx, Rx)
-;-1

-;-16

-;-64

MASTER RESET

~
b7

RIE

TC2

TC1

WS3

WS2

WS1

CDS2

CDS1

I
Word Length, Parity, and Stop Bit Select

Transmitter Control Bits: Controls the Interrupt Output* and RTS
Output, and provides for Transmission of a Break

b4 b3 b2 Word Length + Parity + Stop Bits
0

Even

Odd

Sets RTS = 0 and inhibits Tx interrupt (TI E)

Even

Sets RTS = 0 and enables Tx interrupt (TI E)

Odd

Sets RTS = 1 and inhibits Tx interrupt (TI E)

None

Sets RTS = 0, Transmits Break and inhibits Tx
interrupt (TI E)

None

Even

Odd

Function

*TI E is the enable for the interrupt output in transmit mode.

FIGURE 3-4.2.2-3: ACIA Control Register Format

Bits b7 controls the Receiver Interrupt Enable to the IRQ output. When b7 is high IRQ will indicate
an interrupt request of the Receiver Data Register is Full (RDRF).
3-4.2.3

Addressing. and Initialization

A specific example of ACIA usage is shown by the application described in Section 5-3, however,
some basic considerations are discussed in the following paragraphs. As indicated in Section 3-4.1.2, the MPU
addresses the ACIA via the chip select and register select inputs from the Address Bus. The correspondence
between internal registers and the address inputs is shown in Figure 3-4.2.3-l.
With the chip selects properly enabled and RS = 0, either the Status or Control Register will be
selected, depending on the current state of the Read/Write line: R/W = 0 = Write, Control Register is selected;

3-25

CS2
¢
¢
¢
¢
X
X

CS1

CS¢

1
¢
X
X

X
¢
X

R/W

¢
¢

¢
1
¢

X
X
X

Control Register
Status Register
Transmit Data Register
Receive Data Register
ACIA Not Selected
AC!A Not Selected
ACIA Not Selected

X = Don't Care

FIGURE 3-4.2.3-1: ACIA Register Addressing

R/W = 1 = Read, Status Register is selected. Similarly, when RS = 1, either the Receive Data Register (R/W
= 1 = Read) or the Transmit Data Register (RjW = 0 = Write) is selected.
Addressing the ACIA can be illustrated in conjunction with the simple system configuration shown
in Figure 3-4.1.3-210. The method shown is typical for assigning mutually exclusive memory addresses to the
family devices without the use of additional decode logic. The connections shown assign memory addresses as
follows:

RAlvl
0000 - 007F
4004 - 4007
PIA
4008 - 4009
ACIA
ROM
COOO- C3FF
(Hexadecimal notation)
As voltage is applied to the ACIA during the power-on sequence, its internal registers are cleared to
zerollby circuitry within the ACIA to prevent spurious outputs. This initial condition means that interrupts are
disabled, IRQ to theMPU is high (no interrupt request), and the Ready-To-Send, RTS, output is high. The first
step in preparation for using the ACIA must be a master reset via bits bO and b 1 of the Control Register, that is,
the MPU must write ones into those positions. Once reset, the ACIA operating mode is established by writing
the appropriate data into the Control Register.
3-4.2.4

System Considerations

The ACIA is used primarily to transfer serial data between the microprocessor and real time
peripheral devices such as teletypes, CRT terminals, etc. The most common data format used for the transfer of
real-time data is the asynchronous data format. Use of this format is generally limited to low transmission rates
- below 1200 bps or 120 char/sec. For example, the maximum transmission rate of a teletype is 10 char/sec.
Here, the transmission of data to the MPU depends on the operator's dexterity of depressing a key on the
keyboards. Since the transmission of data is dependent on the operator, gaps (non transmission of data)
between data characters occur as a general rule.
In the transmission of asynchronous data, there is no pre-synchronized clock provided along with
the data. Also, the gaps between data characters in this transmission mode requires that synchronization be
re-established for each character. Therefore, the receiving device must be capable of establishing bit and
IOFigure 3-4.1.3-1 is identical to Figure 1-1.2-1 and is discussed in Section 1-1.2 of Chapter 1.
11 If external

high signals are present on the DCD and CTS inputs, their respective bits, b2 and b3, in the Status Register will also be

high.

3-26

character synchronization from the characteristics of the asynchronous format. Each character consists of a
specified number of data bits preceded by a start bit and followed by one or more stop bits as shown in Figure
3-4.2.4-1.
These start and stop elements do not contain any information and they actually slow down the
effective transmission rate. Since the asynchronous format is used in real time systems, the effect of the start
and stop bits on the transmission rate is negligible. The purpose of the start bit is to enable a receiving system to
synchronize its clock to this bit for sampling purposes and thereby establish character synchronization. The
stop bit is used as a final check on the character synchronization.
Since the MPU processes eight bit parallel bytes that do not include start and stop elements,
received serial data in an asynchronous format must be converted to parallel form with the start and
stop elements stripped from the character. Likewise, in order to transmit serial data the parallel data
byte from the MPU must be converted to serial form with the start and stop elements added to the
character. This serial-to-serial/parallel-to-parallel conversion is the primary function of the ACIA.
Desired options such as variable clock divider ratios, variable word length, one or two stop bits, odd
or even parity, etc. are established by writing an appropriate constant into the ACIA's Control Register. The
combination of options selected depends on the desired format for a particular application. The general
characteristics of data flow through the ACIA are described in the following paragraphs.
A typical transmitting sequence consists of reading the ACIA status register either as a result of an
interrupt or in the ACIA's turn in a polling sequence. A character may be written into the Transmit Data
Register if the status read operation has indicated that the Transmit Data Register is empty. This character is
transferred to a shift register where it is serialized and transmitted from the Tx Data output preceded by a start
bit and followed by one or two stop bits. Internal parity (odd or even) can be optionally added to the character
and will occur between the last data bit and the first stop bit. After the first character is written in the data
register, the Status Register can be read again to check for a Transmit Data Register Empty condition and
current peripheral status. If the register is empty, another character can be loaded for transmission even though
the first character is in the process of being transmitted. This second character will be automatically transferred
into the shift register when the first character transmission is completed. The above sequence may be continued
until all the characters have been transmitted.

Start

I
I

Start Bit - "Space" - Logic Zero
Start Bits - "Mark" - Logic One
Idling Bits - "Mark"

FIGURE 3-4.2.4-1: Asynchronous Data Format

3-27

Data is received from a peripheral by means of the Rx Data input. A divide by one clock ratio is
provided for an external clock that is synchronized to its data; the divide by 16 and 64 ratios may be used for
internal synchronization. Bit synchronization in the divide by 16 and 64 modes is obtained by detecting the
leading mark-to-space transition of the start bit. False start bit detection capability insures that a full halfbit of a
start bit has been received before the internal clock is synchronized to the bit time. As a character is being
received, parity (odd or even) will be checked and the possible error indication will be available in the status
register along with framing error, overrun error, and receiver data register full. In a typical receiving sequence,
the Status Register is read to determine if a character has been received from a peripheral. If the receiver data
register is full, the character is placed on the Data Bus when the MPU reads the ACIA Receive Data Register.
The status register can be read again to determine if another character is available in the receiver data register.
The receiver is also double buffered so that a character can be read from the data register as another character is
being received in the shift register. The above sequence may be continued until all characters have been
received.

Telephone
Network

Data Flow

MC6860

Kp-II
4--

. Transmit
Data

Modulator

Buffer

Receive
Data

Asynchronous
Communications
Interface
Adapater
(ACIA)

I
I

Demodulator

Limiter

Duplexer

Receive
Filter

Data
Coupler

Control

Term.
Control
Logic

Auto
Answer/
Discon.
Logic

, ,
~

I Threshold

I Detector

Control Signals

Clock &
Timing

FIGUR E 3-4.3.1-1: Typical MC6860 System Configuration

3-4.3

MC6860 LOW SPEED MODEM

3-4.3.1

Input/Output Configuration

The MC6860 Modem provides a very effective method of interfacing a MPU based system, via a
MC6850 ACIA, to a telephone network as shown in Figure 3-4.3.1-1. The modem provides full automatic
answer/originate and initiate disconnect capability under MPU program control thru the ACIA. Data may be
asynchronously sent and received over the telephone network at data rates up to 600 bits per second.

3-28

The Input/Output configuration of the MC6860 when used with the MC6850 ACIA and the MC6800
MPU family is shown in Figure 3-4.3.1-2. Data flow from the terminal side of the modem enters in serial digital
format via the transmit data line of the modem. It is then digitally processed by the modulator section and exits
the telephone network side of the modem via the transmit carrier line. This digitized sinewave FSK signal is
post filtered by an output buffer/low pass filter. The filtered analog sinewave passes through a line duplexer to
the telephone line via a data coupler.
The returning analog signal from the remote modem at the other end of the telephone line passes
through the data coupler and duplexer and is applied to a bandpass filter/amplifier. The receive bandpass filter
bandlimits the incoming signal to remove noise and adjacent transmit channel interference. After being bandlimited the analog signal is full limited to a 50% duty cycle TTL level signal by the input limiter. This digital
signal is the receive carrier that is applied to the modem. The output signal from the bandpass filter is also
routed to a threshold detector to determine if the input signal to the limiter is above the minimum detectable signallevel presented to the modem. When the signal input level exceeds the bias point of the threshold detector,
the detector's output goes low at the threshold input pin to the MC6860 modem indicating that carrier is present.
A complete listing and functional description of all I/O pins for the MC6860 (Figure3-4. 3.2-1) is
provided in the following:

Data Terminal Ready (DTR)
The Data Terminal Ready signal must be low before the modem function will be enabled. To initiate
a disconnect, DTR is held high for 34 msec minimum. A disconnect will occur 3 seconds later.

MC
14411
BRG

Bandpass
Filter/
Amplifier

xTal
1 - - -___--' DTR

en
:l

....coco

A14
A13
en
:l

:::

1J
1J

Tx Data
CS1
CS2

VMA¢2
en
:l

gc:

E
R/W
IRQ

MC
6850
ACIA

I - - -____~

Rx~~------------~

Car
Tx
Car

I------~

Tx Data

Rx Data 1 4 - - - - ; Rx Data

MC
6860

CTS

R/W
IRQ

DCD

AnPh

FIT

-v

'-------1---1 S H

CBT Data
Coupler
Telephone

'-------1---1 R I

....._ _---t 0 H

Line
DA

FIGURE 3-4.3.1-2: I/O Configuration For MC6860 Modem

3-29

Gnd

Data Terminal 0
Ready
2

Clear-to-Send 23

19 Ring Indicator

Auto
Answer/
Disconnect
Logic

Terminal
Control
Logic

Answer Phone

21 Switch Hook

Break Release

Receive Break

15 Mode

Transmit Break

VD D = Pin 12
VSS = Pin 1

Digital Carrier 11
Transmit Data

Threshold Detect

Modulator

Transm it Carrier 10

Receive Data 24
Receive 14
Data Rate

Demodulator
NOTE 1.

Receive Carrier 17
ESD = Enable Space Disconnect
FI S = Fngb!e

LO!'1g Space

D!scamH~ct

ESS = Enable Short Space Disconnect
Crystal 13

Test Clock 18

Self Test

ESS (Note 1)

ESD ELS

FIGURE 3-4.3-2-1: MC6860 Modem Block Diagram

Clear-To-Send (CTS)
A low on the CTS output indicates the Transmit Data input has been unclamped from a steady Mark,
thus allowing data transmission.
Ring Indicator (RI)
The modem function will recognize a receipt of a call from the CBT if at least 20 cycles of the 20-47
Hz ringing signal are present. The CBS RI signal must be level-converted from EIA RS-232 levels before
interfacing it with the modem function. The receipt of a call from the CBS is recognized if the RI signal is
present for at least 51 msec. This input is held high except during ringing. A RI signal automatically places the
modem function in the Answer Mode.
Switch Hook (SH)
SH interfaces directly with the CBT and via a EIA RS-232 level conversion for the CBS. An SH
signal automatically places the modem function in the Originate Mode.
SH is low during origination of a call. The modem will automatically hang up 17 seconds after the
release of SH if the handshaking routine between the local and remote modem has not been accomplished.

3-30

Threshold Detect (TD)
This input is derived from an external threshold detector. If the signal level is sufficient, the TD
input must be low for 20JLs at least once every 32 msec to maintain normal operation. An insufficient signal
level indicates the absence of the Receive Carrier; an absence for greater than 32 msec will not cause channel
establishment to be lost; however, data during this interval will be invalid.
Answer Phone (An Ph)
Upon receipt of Ring Indicator or Switch Hook signal and Data Terminal Ready, the Answer Phone
output goes high [(SH + RI) • DTR]. This signal drives the base of a transistor which activates the Off Hook
(OH) and Data Transmission (DA) control lines in the data coupler. Upon call completion, the Answer Phone
signal returns to a low level.
Mode
The Mode output indicates the Answer (low) or Originate (high) status of the modem. This output
changes state when a Self Test command is applied.

Transmit Break (Tx Brk)
The Break command is used to signal the remote modem to stop sending data.
A Transmit Break (low) greater than 34 msec forces the modem to send a continuous space signal for
233 msec. Transmit Break must be initiated only after CTS has been established. This is a negative edge sense
input. Prior to initiating Tx Brk, this input must be held high for a minimum of 34 msec.
Receive Break (Rx Brk)
Upon receipt of a continuous 150 msec space, the modem automatically clamps the Receive Break
output high. This output is also clamped high until Clear-To-Send is established.
Break Release (Brk R)
After receiving a 150 msec space signal, the clamped high condition of the Receive Break output can
be removed by holding Break Release low for at least 20 JLS.
Transmit Data (Tx Data)
Transmit Data is the binary information presented to the modem function for modulation with FSK
techniques. A high level represents a Mark.
Receive Data (Rx Data)
The Receive Data output is the data resulting from demodulating the Receive Carrier. A Mark is a
high level.
Receive Data Rate (Rx Rate)
The demodulator has been optimized for signal-to-noise performance at 300 bps and 600 bps. The
Receive Data Rate input should be low for 0-600 bps and should be high for 0-300 bps.
Digital Carrier (FO)
A test signal output is provided to decrease the chip test time. The signal is a square wave at the
transmit frequency.

3-31

Transmit Carrier (Tx Car)
The Transmit Carrier is a digitally-synthesized sinewave derived from the 1.0 MHz crystal
reference. The frequency characteristics are as follows:

Mode
Originate
Originate
Answer
Answer

Transmit
Frequency
Data
Mark
1270 Hz
1070 Hz
Space
Mark
2225 Hz
2025 Hz
Space
*The reference frequency tolerance is not included.

Accuracy *
-0.15 HZ
+0.09 Hz
-0.31 Hz
-0.71 Hz

The proper output frequency is transmitted within the 3.0 ILS following a data bit change with no
more than 2.0 ILS phase discontinuity. The typical output level is 0.35 V (RMS) into a 200 k-ohm load
impedance.
The second harmonic is typically 32 dB below the fundamental.

Receive Carrier (Rx Car)
The Receivt: Carrier is the FSK input to the demodulator. The local Transmit Carrier must be
balanced or filtered out prior to this input, leaving only the Receive Carrier in the signal. The Receive Carrier
must also be hard limited. Any half-cycle period greater than or equal to 429 ± 1.0 ILs for the low band or 235 ±
1.0 ILs for the high band is detected as a space.
Enabled Space Disconnect (ESD)
----When ESD is strapped low and DTR is pulsed to initiate a disconnect, the modem transmits a space
for either 3 seconds or until a loss of threshold is detected, whichever occurs first. If ESD is strapped high, data
instead of a space is transmitted. A disconnect occurs at the end of 3 seconds.
Enable Short Space Disconnect (ESS)
ESS is a strapping option which, when low, will automatically hang up the phone upon receipt of a
continuous space for 0.3 seconds. ESS and ELS must not be simultaneously strapped low.
Enable Long Space Disconnect (ELS)
ELS is a strapping option which, when low, will automatically hang up the phone upon receipt of a
continuous space for 1.5 seconds.
Crystal (Xtal)
A 1.0-MHz crystal with the ·following parameters is required to utilize the on-chip oscillator. A
1.0-MHz square wave can also be fed into this input to satisfy the clock requirement.
Mode:

Parallel
1.0 MHz ±0.1 %
750 ohms max
7.0 pF max
0-70°C

Frequency:
Series Resistance:
Shunt Capacitance:
Temperature:
Test Level:

1.0mW

Load Capacitance:

13 pF
3-32

When utilizing the 1.0-MHz crystal, external parasitic capacitance, including crystal shunt
capacitance, must be ~9 pF at the crystal input.

Test Clock (TST)
A test signal input is provided to decrease the test time of the chip. In normal operation this input
must be strapped low.
Self Test (ST)
When a low voltage level is placed on this input, the demodulator is switched to the modulator
frequency and demodulates the transmitted FSK signal. Channel establishment, which occurred during the
initial handshake, is not lost during self test. The Mode Control output changes state during Self Test,
permitting the receive filters to pass the local Transmit Carrier.

ST
H
H
L

INPUTS
SH
L
H
L
H

RI
H
L
H
L

OUTPUT
Mode
H
L
L
H

MODE CONTROL TRUTH TABLE

3-4.3.2

Internal Organization

The MC6860 Modem may be broken down into internal functional sections as shown in Figure
3 -4.3.2-1. The terminal control logic and auto answer/disconnect logic sections are referred to as the
supervisory control section. This section contains digital counters which provide the required time out intervals
and necessary control gating logic. This provides logic outputs Clear-To-Send and Answer Phone from inputs
Ring Indicator, Switch Hook, and Data Terminal Ready. Also the control section has some local strapping
options available on pins 5, 6, and 22. These options provide time outs for line hang-up or termination of the
data communication channel.
The oscillator/timing blocks accept a 1.0 MHz clock into pin 13 either from an external clock source
or by connecting a 1.0 MHz crystal between pin 13 and ground. A test clock input is provided to allow more
rapid testing of the MC6860 timing chains used for various timeouts. This input must be strapped low during
normal operation.
The modulator section takes the input digital data and converts it to one of two FSK tones for
transmission over the telephone network. There are two tones for transmission and two tones used for reception
during full depulx operation. During data transmission from the call origination modem the transmit tones are:
1270 Hz for a Mark and 1070 Hz for a Space. This originating modem will receive two frequencies in the high
band which are: 2225 Hz for a Mark and 2025 Hz for a space. If the local modem answers the data call it will
transmit in the high band 2225/2025 Hz and receive in the low band 1270/1070 Hz. The modulator section
generates these frequencies digitally by synthesizing a sinewave with an 8 step D to A available on pin 10 and a
digital square wave output at the above frequencies available on pin 11.
The demodulator accepts a 50% duty cycle TTL level square wave derived from amplifying,
filtering, and limiting the incoming line FSK analog signal. The binary data is recovered from the FSK signal
by detecting when the signal has a zero crossing and digitally using post detection techniques to discriminate
3-33

between the two incoming mark/space tones. A receive data rate input (pin 14) is used to optimize the post
detection filter at either 300 or 600 bits per second.
3 -4.3.3

Handshaking and Control
The supervisory control section of the modem can function in four different modes. Two are

associated with data communication channel initialization (Answer Mode and Originate Mode) and two are for
channel termination or hang-up (Automatic Disconnect and Initiate Disconnect).

Answer Mode
Automatic answering is first initiated by a receipt of a Ring Indicator (RI) signal. This can be either a
low level for at least 51 msec as would come from a CBS data coupler, or at least 20 cycles of a 20-47 Hz ringing
signal as would come from a CB T data coupler. The presence of the Ring Indicator signal places the modem in
the Answer Mode; if the Data Terminal Ready line is low, indicating the communication terminal is ready to
send or receive data, the Answer Phone output goes high. This output is designed to drive a transistor switch
which will activate the Off Hook (OH) and Data Transmission (DA) relays in the data coupler. Upon answering
the phone the 2225-Hz transmit carrier is turned on.
The originate modem at the other end detects this 2225-Hz signal and after a 450 msec delay (used to
disable any echo suppressors in the telephone network) transmits a 1270-Hz signal which the local answering
modem detects provided the amplitude and frequency requirements are met. The amplitude threshold is set
external to the modem chip. If the signal level is sufficient the TD input should be low for 20 /-LS at least once
every 32 msec. The absence of a threshold indication for a period greater than 51 msec denotes the loss of
Receive Carrier and the modem begins hang-up procedures. Hang-up will occur 17 seconds after RI has been
released provided the handshaking routine is not re-established. The frequency tolerance during handshaking is
± 100 Hz from the Mark frequency.
After the 1270-Hz signal has been received for 150 msec, the Receive Data is unclamped from a
Mark condition and data can be received. The Clear-To-Send output goes low 450 msec after the receipt of
carrier and data presented to the answer modem is transmitted.
Automatic Disconnect
Upon receipt of a space of 150 msec or greater duration, the modem clamps the Receive Break high.
This condition exists until a Break Release command is issued at the receiving station. Upon receipt of a 0.3
second space, with Enable Short Space Disconnect at the most negative voltage (low), the modem
automatically hangs up. If Enable Long Space Disconnect is low, the modem requires 1.5 seconds of
continuous space to hang up.
Originate Mode
Upon receipt of a Switch Hook (SH) command the modem function is placed in the Originate Mode.
If the Data Terminal Ready input is enabled (low) the modem will provide a logic high output at Answer Phone.
The modem is now ready to receive the 2225-Hz signal from the remote answering modem. It will continue to
look for this signal until 17 seconds after SH has been released. Disconnect occurs if the handshaking routine is
not established.
Upon receiving 2225 ± 100 Hz for 150 msec at an acceptable amplitude, the Receive Data output is
unclamped from a Mark condition and data reception can be accomplished. 450 msec after receiving a 2225-Hz

3-34

signal, a 1270-Hz signal is transmitted to the remote modem. 750 msec after receiving the 2225-Hz signal, the
Clear-To-Send output is taken low and data can now be transmitted as well as received.

Initiate Disconnect
In order to command the remote modem to automatically hang up, a disconnect signal is sent by the
local modem. This is accomplished by pulsing the normally low Data Terminal Ready into a high state for
greater than 34 msec. The local modem then sends a 3 second continuous space and hangs up provided the
Enable Space Disconnect is low. If the remote modem hangs up before 3 seconds, loss of Threshold Detect will
cause loss of Clear-To-Send, which marks the line in Answer Mode and turns the carrier off in the Originate
Mode.
If ESD is high the modem will transmit data until hang-up occurs 3 seconds later. Transmit Break is

clamped 150 msec following the Data Terminal Ready interrupt.
Each of the four above operational modes are shown in Figures 3-4.3.3-1 through 3-4.3.3-4.

Call Received

-----1

51Min
ms

I----

R'
I d'
mg n Icator

""""CBSlL..__---'

Ring Indicator

~ n ~~ n ~ 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CBT

;.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

U UUU U

Mode {Originate ~
Answer - -

Data~inal

On (Low)

Answer (Low)

I
~------------------------------

Ready
Answer Phone

III-- - - - - - - - 2 2 2 5 Hz, 900 ms

F450

I' 2025

Hz or 2225 Hz

Transmit Carrier _ _ _ _ _...J

m ' - - - - - t - - 1 2 7 0 Hz, 300 ms--+----

Receive Carrier - - - - - - - - - - - - - - - - - - '
Threshold Detect --.,;.(_H...:ig:,...h.:,...}- - - - - - - - - - - - - - - h - - - r - - . - r - - - r - - f - - - - r - - . . . - + . - - r - r - - r - - - , , - Clear-to-Send _O_f_f_(H_·..;;:.19_h}_ _ _ _ _ _ _ _ _ _ _ _ _-+-_ _ _ _ _ _ _t -_ _--;
~--450ms--~----~~~~~-----

Transmit {Mark
Data
Space Clamped at Mark
Receive
Data

{Mark
Space

-------------+----------+-----!'""'"''''''''''''......................................~;..,

-------------------------1-- 150 ms
150 ms
- - - - - - - - - - - - - - C l a m p e d -------------+-1-0-------- Unclamped - - - - - - at Mark

FIGURE 3-4.3.3-1: Answer Mode

3-35

High

Ring Indicator

CBS

High
Ring Indicator ----------------------~C~B~T~------------------------------------------------------------------Answer (Low)
Mode
On (Low)
Data Terminal
Ready
Answer Phone

- - - - - - - - - - - - - - 2025 Hz or 2225Hz
Transmit Carrier

----------i-I

~tinuousSpace
---1070 Hz or 1270 Hz--

---1

- 1070
0 . 3 s ESS or 1.5 s ELS /"\.

/"\.(

Receive Carrier
Threshold Detect
On (Low)
Clear-to-Send
. {Mark
Transmit
S
pace

Clamped at Mark

------------Unclamped
Receive .{ Mark Wd$&y~~d&#~
Data
l ~pace

i----

C!ernped at

I
Unclamped ~

!\~a!"k

FIGUR E 3-4.3.3-2: Automatic Disconnect - Long or Short Space

Switch Hook
Data Terminal
Ready
Originate
Mode { Answer

SH Can Be Released

IL----I:~~~~:a.0~:@/W~~W~{L~:a.0LL.~LL.;g;:L.:::.:::LW:L::c::.:;c.::::~~CLLL...LL£.L.LLLL..
~~CLLL.t.~~~~~~
On (Low)
Originate (High)
Answer (High)
2025 Hz

Answer Phone
f------

Establ ish Call - - - - - 1 - - -

Receive Carrier
Threshold Detect

Receive Data
Clamped at Mark

-----------4--------~

Transmit Carrier
Clear-to-Send
Transmit Data
Enable Space

--------------------------------t~~~~~~~~~~~~~~~~~7~5~0~m--s~===============:~~o~n~(~L~o:W~)_
Clamped at Mark
On (Low)

Unclamped

Disconnect

FIGURE 3-4.3.3-3: Originate Mode

3-36

Switch Hook

High

r--

---j
Data Terminal

_____
O_n_(~L_o_W_)______~r___lL

34 ms Pulse Initiates Space Disconnect

__________________________________________________________

Ready
Mode
Answer Phone

Originate (High)
Off Hook
On Hook

Receive Carrier
Threshold Detect

.1 ·1·

- - - - - - - - - - Unclamped

50 ms Internal Threshold Detect Delay

Receive Data

Clamped at Mark
---1070 Hz or 1270 Hz

Transmit Carrier

Clear-to-Send
Transmit Data
Enable Space

1070 Hz

----,..,1--

~----s
On (Low)

Off (High)

~ unclamped~

Clamped at Space

On (Low)

Disconnect

FIGURE 3-4.3.3-4: Initiate Disconnect

3-37

Clamped at Mark

3-5

DIRECT MEMORY ACCESS

The term Direct Memory Access (DMA) is applied to a variety of techniques for speeding up overall
system operation by loading and unloading memory faster than can be done using an MPU control program.
DMA is often described as a means of allowing fast peripherals (perhaps another Microprocessor), to access the
system memory without' 'bothering" the MPU. However, most DMA procedures do interfere with normal
operation to some extent. The capability for handling the various techniques is an often used figure of merit for
evaluating Microprocessors.
The MC6800's supervisory control features permit any of three commonly used DMA techniques to
be used; (1) Transfer data with MPU halted; (2) Transfer data on burst basis (cycle stealing) with MPU running;
(3) Transfer data synchronously with MPU running. Methods for implementing each of these techniques are
described in Section 4-2.2 therefore, only qualitative descriptions are included here.
The simplest procedure for DMA merely uses the Halt control to shut the MPU down while the
DMA takes place. In the Halt state, the MC6800 effectively removes itself from the Address and Data Buses by
putting all buffers in the high impedence off state. This method has the disadvantage that it can take a relatively
long time for the MPU to "vacate" the buses. The MC6800 is designed to finish executing its current
instruction before entering the Halt or Wait state; the resulting delay depends on which instruction is being
executed and may be as much as 13 machine (clock) cycles. However, due to its simplicity this is the preferred
method if the delay can be tolerated and long transfers are required.
In contrast to this, the Three-State Control (TSC) may be used to obtain DMA control within 500
nanoseconds of initiation but must be used only for short transfers. Activation ofTSC puts the MPU's buffers in
the high impedence off state. This technique has the disadvantage that activation of TSC should be
synchronized with the ~1 clock and both clocks must be "frozen" (~1 high, ~210w) for the duration of the
DMA. Due to the MPU's address and R/Wrefresh requirements, the clocks can only be frozen for a maximum
of 5 microseconds, thus limiting the duration of the transfer.
A third method can be used that is completely transparent to the MPU. This technique takes
advantage of the fact that MPU data transfers take place only during ~2 of the clock cycle. If the DMA control
signals are properly synchronized and the memory is fast enough, DMA can be accomplished during ~1 of each
clock cycle.
Each of these three methods is described in greater detail in Section 4-2.2. It should be noted that the
faster methods impose additional external hardware requirements on the system.
The techniques described above of course do not exhaust all methods for performing DMA. As an
additional example, DMA can be program controlled in the sense that a control program and hence the MPU
can be used to establish the memory area to be used and to grant permission for the DMA. In this case the DMA
circuitry is treated as another peripheral from which status and control signals can be passed through a PIA.
This technique is also outlined in Section 4-2.2.

3-38

CHAPTER 4
4

M6800 FAMILY HARDWARE CHARACTERISTICS

There are four classes of control signals which control the execution of the MC6800 MPU. The first
pair of control signals is the two phase clock cf>1 and cf>2 which time the entire MPU system. The second pair of
signals, HALT and Bus Available (BA), are used to stop program execution and free up the Address and Data
Bus for other uses such as a DMA channel. The interrupt signals make the MPU responsive to outside control
and are listed in decreasing order of priority: RESET, Non-Maskable Interrupt (NMI) and Maskable Interrupt
(IRQ). The Three-State Control (TSC) and Data Bus Enable (DBE) control lines provide a way to momentarily
remove the MPU from the busses and can be used for implementing a burst type DMA channel.
4-1

CLOCK CIRCUITRY FOR THE MC6800 MPU

4-1.1

Clock Requirements and Circuitry
Figure 4-1.1-1 is a summary of the MC6800 Microprocessor clock waveform requirements. The cf> 1

and cf>2 clock inputs require complementary 5 volt non -overlapping clocks. The clock inputs of the MPU appear
primarily capacitive being 110 pf typical and 160 pf maximum plus 100 p.,a of leakage. Provision is made in the
specification for the undershoot and overshoot that will result from the generation of a high speed transistion
into a capacitive load.
The clock specifications which constrain the clock driver the most are the rise and fall times required
to meet the pulse widths at the maximum operating frequency of 1 MHz, the non-overlapping requirement, and
the logic level requirements of Vss + 0.3 volts and Vee -0.3 volts. The clock buffer circuit that drives the
MPU clock inputs must be designed to meet the rise and fall time requirements as well as the logic level
requirements. The non-overlapping requirement of the clock signals can be met by the design of the control
logic which drives the buffers. A clock buffer, the MPQ6842 *, will guarantee the clock designer the speed and
saturation voltages necessary to design the clock circuit to meet the MPU clock requirements. Relevant
specifications of the MPQ6842 for this design are detailed in Figure 4-1.1-2. Note that the VeE (SAT),s, rise
and fall times are specified to meet this clock driver requirement.
Figure 4-1.1-3 is a circuit designed with TTL logic devices and the MPQ6842 buffer to meet the
MPU clock requirements while operating from a single +5 volt supply. The oscillator can be any source with a
maximum frequency of 1 MHz, TTL logic levels and 50% duty cycle. This oscillator signal source could vary
from a commercial oscillator such as a K1100A available from Motorola's Component Product Department, 1
to a signal derived from a higher frequency signal already available in the system. The TTL gates shown are
standard MC3000 and MC3001 (74HOO and 74H08) which were chosen for their speed and drive characteristics. The discrete buffers require good" 1" level pull up and drive capability which is provided by the MC3001.
The circuit was constructed on a wire wrap board and tested on an EXORciser. 2 Good power and ground
distribution practice was followed but no special care was taken in parts layout.
12553 N. Edgington, Franklin Park, Illinois 60131,312-451-1000
2A system prototyping tool for the M6800 Microprocessor family.
*To be introduced first quarter 1975.

4-1

~------------tCLK---------------4~
~------------tUT----------~~

2
" - - - - - PWO H --_-.I

UNDERSHOOT

SYMBOL

MIN

Input High Voltage cpl, cp2
Input Low Voltage cp 1, cp2

VIHe
VILe

Vee-0.3
Vss-O.l

Clock Overshoot/U ndershoot
Input High Voltage
Input Low Voltage

Vas

CHARACTERISTIC

Input Leakage Current cp 1, cp2
(VIN = 0 to 5.25 V, Vee

TVP

Vee
Vss

+ 0.1
+ 0.3

Vee + 0.5
Vss + 0.5

Vee-0.5
Vss-0.5

MAX

UNITS
Vdc
Vdc
Vdc
Vdc

100

/-La

160

0.1

1.0

MHz

tcyc

1.0

/-LS

PWaH

430
450

4500
4500

ns
ns

tr, tf

9100

Overshoot/U ndershoot Duration

tas

Clock High Times

tUT

940

Capacitance
(VIN = 0, TA

25°C, f

MAX)

lIN

1.0MHz)

CIN

Frequency of Operation
Clock Timing
Cycle Time
Clock Pulse Width
(Measured at Vee-0.3 V)

cpl
cp2
cp 1, cp2

Rise and Fall Times
(Measured between
Vss + 0.3 V and Vee-0.3 V)
Delay Time or Clock Overlap
(Measured at Vav = Vss + 0.5 V)

FIGURE 4-1.1-1 MPU Clock Waveform Specifications

4-2

120

CONNECTION DIAGRAM
MP06842

DEVICE CHARACTERISTICS: T = 25°C, VCC = 5.00 VDC
Characteristic

Symbol

Propagation Delay

TpD

Measurement Levels

Min

Typ

Max

Units

50% Points TP1 to TP3
50% Points TP2 to TP4

5
5

15
15

nsec
nsec

Rise Time

0.3 V to 4.7 V
TP3 and TP4

nsec

Fall Time

4.7 V to 0.3 V
TP3 and TP4

nsec

IC = 0.5 ma, IS = 0.05 ma
T = OoC to 70 0 C

0.10

0.15

VDC

Collector-Emitter
Saturation Voltage

VCE(sat)

TEST CI RCUIT
VCC

1/4 MC3001 (74H08)
~--~------~IJ TP3

TP1

~
1.

Pulse
Generator
to 5 V
51
t r • tf ,,;;; 2 ns
PW "'" 200 ns
Period"'" 1 000 ns

VCC
3.

4.
5.

1/4 MC3000
(74HOO)
~-""----iO)

TP4

TP2

FIGURE 4-1.1-2. MPQ6842 Clock Buffer

4-3

Unless otherwise noted, all resistors
carbon composition Y.. W ±5%, all
capacitors dipped mica ±2%.
Use short interconnect wiring with
good power and ground busses.
TP1~TP4 are coaxial connectors to
accept scope probe tip and provide a
good ground.
Device under test is MP06842.
200 pf load includes strays plus
scope probe capacitance.

+5V

. '1IJ.f Ceramic

Oscillator

K1100A

Y.. MC3000

Y.. MC3001

Y.. MC3001 I Y.. MC3000

Y.. MC3001

(74H08)

(74HOO)
MHz 50 ± 2% Duty Cycle

SPARE

=0~

.i:..

+5V

Y.. MC3001

.1/-Lf Ceramic

and

DBE

NOTES:
1. Unless otherwise noted
All resistors are carbon composition Y..W, = 5%
All capacitors are dipped mica ± 2%
2, * MPQ6842

Y.. Mc3000

'--------Il- h
FIGURE 4-1.1-3 MPU Clock Circuit

BUS2

Waveforms typical of the circuit in Figure 4-1.1-3 at T = 20°C and Vee = 5.00 volts are shown in
Figure 4-1.1-4. Figure 4a and 4b depict the logic levels and pulse widths achieved by this circuitry with Vee
and GND as reference levels. Figure 4c superimposes the two clock waveforms so that their phase relationship
can be seen. Figure 4d shows the phase relationship of BUS cf>2 and MPU cf>2. Figures 4e and 4f examine the
non-overlap regions as well as rise and fall times typical of this clock drive circuit. Table 4-1.1-1 presents
test data taken over a voltage range of 4. 75 volts to 5.25 volts and over a temperature range ofO°C to 70°C. Note
the stability of these measured parameters and that the logic levels achieved will provide noise margin on the
system clocks. Both cf>1 and cf>2 clock high times were designed to be about 20 ns wider than the minimum
required by the MPU (cf>1 - 430 ns, cf>2 - 450 ns) to provide system margin. Rise and fall times were
minimized to provide maximum clock high times consistent with non-critical circuit layout considerations. The
overlap margin shown easily meets the MPU requirement of 0 ns at 0.5 volts but will decrease as the capacitive
loading increases. The MPU tested for this data had a clock input capacitance on the order of the 110 pf typical
value.

Test Conditions

MPU cJ>1
"1" LL * "0" LL*

Non-Overlap Region
MPU cJ>2
"1" LL* "0" LL* cJ>1 to cJ>2t cJ>2t to cJ>1t

T = 20°C
Vee

4.75 V

460 ns

15 ns 10 ns

4.75 V

0.1 V

465 ns

15 ns 10.5 ns

4.75 V

10.5 ns

12 ns

Vee

5.00 V

460

5.00

0.1

465

5.00

5.25 V

460

5.25

0.1

465

5.25

9.5

10.5

450

15.5

5.00

0.1

460

5.00

5.5

Vee = 4.75 V

460

4.75

0.1

465

4.75

10.5

= 5.00 V

460

5.00

0.1

465

4.75

8.5

Vee = 5.25 V

455

12.5

5.25

0.1

465

5.25

Vee

= 5.00 V, eL

= 210 pf

T = 70°C

Vee

T=OoC
Vee =4.75 V

460

4.75

0.1

465

10.5

4.75

Vee = 5.00 V

460

5.00

0.1

465

5.00

10.5

11.5

Vee = 5.25 V

460

10.5

5.25

0.1

465

5.25

10.5

*Resolution of this measurement

±50 mv

LEGEND:
PW:

Pulse width measured at Vee - 0.3 V

RT:

Rise time measured from 0.3 V to Vee - 0.3 V

FT:

Fall time measured from Vee - 0.3 V to 0.3 V

"0" LL:

Zero logic level

"1" LL:

One logic level

Non-Overlap:

TABLE 4·1.1-1. Performance of Circuit in Figure 4-1.1-3

Measured from 0.5 volt levels

In many systems, especially in the breadboard and evaluation stage, it may be desirable to have the
flexibility to vary the system clock to test the effects on data throughput, real time operation with interrupts or to
help diagnose a system timing problem. In these applications, or in those not requiring crystal oscillator
stability, an even simpler clock circuit can be used. A pair of cross coupled monostable multivibrators with
individual pulse width adjustments can be used as the clock oscillator with the previously described clock
driver. This approach is shown in Figure 4-1.1-5. The non-overlapping clock is generated by the propagation
delays through the monostable multivibrators . Figure 4-1. 1-6 shows waveforms resulting from this circuit.
Table 4-1.1-2 shows test data taken of this circuit over the voltage and temperature range driving a typical MPU
(CL = 110 pf). Note the small variations in the pulse widths.

4-5

MPU It

= 20°C

Vee

4.75 V

470 ns

11 ns 11.5 ns 4.75 V

0.1 V

450 ns

12 ns 12 ns

4.75 V

12 ns

11 ns

Vee

5.00 V

470

12.5

5.00

0.1

460

12.5

5.00

9.5

Vee

5.25 V

470

5.25

0.1

460

13.5

12.5

5.25

a
a

= 70°C

Vee

4.75 V

455

12.5

13.5

4.75

0.1

450

4.,75

Vee

5.00 V

455

5.00

0.1

450

5.00

Vee

5.25 V

455

14.5

5.25

0.1

450

5.25

a
a
a

8.5

= OOC

Vee

4.75 V

473

4.75

0.1

470

4.75

Vee

5.00 V

475

5.00

0.1

470

12.5

5.00

Vee

5.25 V

475

12.5

5.25

0.05

473

12.5

5.25

a
a
a

*Resolution of this measurement ;::::::;±50 mv

LEGEND:
PW:

Pulse width measured at Vee - 0.3 V

RT:

Rise time measured from 0.3 V to Vee - 0.3 V

FT:

Fall time measured from Vee - 0.3 V to 0.3 V

"0" LL:

Zero logic level

"1" LL:

One logic level

Non-Overlap:

TABLE 4·1.1·2. Performance of Circuit in Figure 4·1.1·5

Measured from 0.5 volt points

The fast rise and fall times produced by this circuitry and the highly capacitive loads require some
care in layout to avoid excessive ringing and/or pulse distortion. While no particular care was taken in the
construction of the wirewrap test boards other than placing all of the discretes into one header board, the
following construction guidelines are recommended. Wide power and ground lines (50-100 mils) should be
used to provide low impedance voltage and ground sources. The clock driver should be physically located as
near the MPU as possible to avoid ringing down long lines. Close proximity of the clock circuitry to the MPU
allows common power and ground connections so that any noise appears common mode rather than differential
to the MPU and clock driver. Finally, it is recommended that the MPU ~2 clock signal not be used to clock any
device other than the MPU so that it is not distributed allover the system with the possibility of picking up noise
and causing reflections. The circuits shown in this section provide an additional buffer for the other ~210ads in
the system to isolate MPU

from all the other

loads.

For further discussion on clock generators for the MC6800 including interface with dynamic and
slow memories, the reader is referred to Section 4-2.5.1.
4-1. 1.2

Clock Module
A hybrid clock module is being developed by the Communications Division of Motorola 1 for the

M6800 Microprocessor family. This module is composed of a crystal oscillator and associated buffering
circuitry to provide either 1 MHz or user specified frequency operation of the M6800 family. Provision is made
within this module for cycle stealing in order to interface with dynamic memory (see Section 4-2.5.1) or
implement a DMA channel (see Section 4-2.2.2). The module is designed to provide a MEMORY READY
'Component Products, 2553 N. Edgington St., Franklin Park, Illinois 60131, 312-625-0020

4·6

+5.00 V

1 V/cm

Gnd

200 ns/cm

FIGURE 4-1.1-4a MPU

+5.00 V

1 V/cm

Gnd

100 ns/cm

FIGURE 4-1.1-4c. MPU 1 and 2 Clocks

Bus 2: 4V Pulse

MPU 2: 5 V Pulse

+5.00 V

1 V/cm

Gnd

100 ns/cm

FIGURE 4-1.1-4d. MPU 2 Clock and Bus 2

4-8

5.00 V

1 V/em

Gnd

5 ns/em

F I GU R E 4-1.1-4e. MPU Clock Non-Overlap Region

qy2

5.00 V

qy1

Gnd

1 V/em

5 ns/cm

FIGURE 4-1.1-4f. MPU Clock

4-9

Non~Overlap

Region

+5 V

11 K 1%

MC8602

Bus 1>2

+5 V

1/3 MC7404

33 pf

.1 J.l.f Ceramic

+5 V

470

+5 V
NOTE:
1) Unless otherwise noted
All resistors are carbon composition Yt.W, ±5%
All capacitors are dipped mica ±2%
2) * MPQ 6842

+5 V

I . 1 J.l.f Ceramic
470

"'MPQ6842

FIGURE 4-1.1-5. Monostable Clock Generator

4-10

ct>1

ct>2

ct>1

5.00 V

1 V/cm

GND

200 ns/cm

FIGURE 4-1.1-6a. MPU Clock Waveforms

ct>1

5.00 V

ct>2

GND

1 V/cm

5 ns/cm

FIGURE 4-1.1-6b. MPU Clock Non-Overlap Region

4-11

5.00 V

1 V/cm

GND

5 ns/cm

FIGURE 4·1.1·6c. MPU Clock Non·Overlap Region

Bus ¢2

2 V/cm

MPU ¢2

200 ns/cm

FIGURE 4·1.1·6d. MPU ¢2 Clock and Buss ¢2

4·12

function in order to interface with slow memories (see Section 4-2.5.1). Those interested in this device should
contact their Motorola salesman for further details.
4-1.2

HALTING THE MC6800 AND SINGLE INSTRUCTION EXECUTION
The HALT line provides an input to the MPU to allow control of program execution by an outside

source. If HALT is high, the MPU will execute; if it is low, the MPU will go to a halted or idle mode. A response
signal, Bus Available (BA) provides an indication of the MPU's current status. When BA is low, the MPU is in
the process of executing the control program; if BA is high, the MPU has halted and all internal activity has
stopped. When BA is high, the Address Bus, Data Bus, and R/W line will be in a high impedance state,
effectively removing the MPU from the system bus. VMA is forced low so that the floating system bus will not
activate any device on the bus that is enabled by VMA.
While the MPU is halted, all program activity is stopped and, if either a NMI or IRQ interrupt
occurs, it will be latched into the MPU and acted on as soon as the MPU is taken out of the halted mode. If a
RESET command occurs while the MPU is halted, the following states occur: VMA-low, BA-low (while
RESET is low), Data Bus-high impedance, R/W-Read state (while RESET is low), and the Address Bus will
contain the reset address FFFE (while RESET is low). As soon as the HALT line goes high, the MPU will go
to locations FFFE and FFFF for the address of the reset routine.
Figure 4-1.2-1 shows the timing relationships involved when halting the MPU and executing a
single instruction. Both of the instructions illustrated are single byte, 2 cycles, such as CLRA and CLRB. The
MPU always halts after completing execution of an instruction when HALT is low. If HALT is low within 100
nsec after the leading edge of cf> 1 in the last cycle of an instruction (point A in the figure) then the MPU will halt
at the end of the current instruction. The fetch of the OP code by the MPU is the first cycle of an instruction. If
HALT had not been low at point A but went low during cf>2 of that cycle, the MPU would have halted after
completion of the next instruction after instruction X. BA will go high within 470 nsec of the leading edge of the
next cf>2 clock after the last instruction cycle executed. At this point in time, VMA is low and the R/W line,
Address Bus, and the Data Bus are in the high impedance state.
To single cycle the MPU, HALT must be brought high for one MPU cycle and then returned low as
shown at (B). Again, the transitions of HALT must occur within 100 nsec of the leading edge of cf> 1. BA will go
low within 300 nsec of the leading edge of the next cf>1 indicating that the Address Bus Data Bus, VMA and
R/W lines are back on the bus. A single byte, 2 cycle instruction, such as CLRB is used for this example also.
During the first cycle, the instruction Y is fetched from address M + 1. BA returns high 470 nsec after cf>2 on the
last cycle indicating the MPU is off the bus. If instruction Y had more than two cycles, the width of the BA's
low time would have been increased proportionally.
4-1.3

MC6800 RESET AND INTERRUPT CONTROLS
The RESET input is used to reset and start the MPU from a power down condition resulting from a

power failure or initial start-up of the processor. This input can also be used to reinitialize the machine at any
time after start up. If a positive edge is detected on this input, this will signal the MPU to begin the restart
sequence. During the reset sequence, all of the higher order address lines will be forced high. The contents of
the last two locations (FFFE, FFFF) in memory will be loaded into the program counter to point to the reset
program. During the reset routine, the interrupt mask bit is set and must be reset by an Instruction in the
initializing program before the MPU can be interrupted by IRQ. While RESET is low (assuming 8 clock cycles
4-13

Last Cycle
of Current
Instruction

r~,

cJ>1

cJ>2

lllll~~--l

-'1--

......
VMA

R/W

1--

--I

470 n, M"

_ _ _ _ _ _- - - J

mote '.....
..
_

•
Fetch

Address
Bus

'00n 'M"

Halt

+:-

Single Cycle
Fetch

A~dr

-l f.'00n'Max~

y-;

300 n'

Max~"

j4--

----1

f.---470 n' Max

I--~ \~_ _ __

Note 2

~---

•

Execute

~:\=-~

. , . . . . - - - - - . . . , ..
,
.

--------.....,,,

Data
Bus

~~~r

~--

-----~

M
NOTE 1: Crosshatch indicates data not valid
intervals.
NOTE 2: Midrange waveform indicates high

impedance state.

Single Cycle
Execute

FIGURE 4-1.2-1. Halt and Single Instruction Execution

+ 1

= 100116, Y = CLRB (OP = 5F)

have occurred) the MPU output signals will be in the following states: VMA-Iow, BA-Iow, Data Bus-high
impedance, R/W (Read State) and the Address Bus will contain the reset address FFFE.
Figure4-1.3-1 illustrates a power up sequence using the RESET control line. After the power supply
reaches 4.75 volts, eight clock cycles are required for the processor to stabilize in preparation for restarting.
During these eight cycles, VMA will be in an indeterminate state so any devices that are enabled by VMA
which could accep.t a false write during this time (such as a battery backed RAM) must be disabled until VMA is
forced low after 8 cycles. RESET can go high asynchronously with the system clock, however, its rise time
must be less than 500 nsec. If RESET is high at least 200 nsec before the leading edge of cf>1 in any given cycle,
then the restart sequence will begin in that cycle as shown in Figure 4-1.3-1. The RESET control line may also
used to reinitialize the MPU system at any time during its operation. This is accomplished by pulsing RESET
low for the duration of at least three complete cf>2 pulses. The RESET pulse can be completely asynchronous
with the MPU system clock.
The MC6800 is capable of handling two types of interrupts, maskable (IRQ) and non-maskable
(NMI). The handling of these interrupts by the MPU is the same with the exception that each has its own vector
address. The behavior of the MPU when interrupted by these two Wpes of interrupts falls into two categories as
shown in Figure 4-1.3-2. Figure 4-1.3-2a details the MPU response to an interrupt while the MPU is executing
the control program. The interrupt shown could be either an IRQ or NMI and can be asynchronous with respect
to cf> 1. The Interrupt is shown going low 200 nsec before the leading edge of cf> 1 in cycle #2 which is the first
cycle of an instruction (OP code fetch). This instruction is not executed but instead the Program Counter, Index
Register, Accumulators, and the Condition Code Register are pushed onto the stack. The Interrupt Mask is then
set to prevent further IRQ interrupts. The address of the interrupt service routine is then fetched from FFFC,
FFFD, for a NMI interrupt and from FFF8, FFF9 for an IRQ interrupt. Upon completion of the interrupt service
routine, the execution of RTI will pull the PC, X, ACCUMULATORS, and CCR off of the stack.
Figure 4-1.3-2b is a similar interrupt sequence except, in this case, a WAIT instruction has been
executed in preparation for the interrupt. This technique speeds up the MPU's response to the interrupt because
the stacking of the PC, X, ACCUMULATORS, and the CCR is already done. While the MPU is waiting for the
Interrupt, Bus Available will go high indicating the following state of the control lines: VMA-Iow, Address
Bus-R/W-Data Bus all in the high impedance state. After the interrupt occurs, it is serviced as previously
described.

4-15

cj.>1

Power on
Switch

----1

4.75:;:r

ruu ,. , ,--, ,--, ,--, .-. .-.
2

n+2

n+1

n+3

n+4

n+5

1rJ------~--------------------

..u

5.25 V

Power
Supply

----..t

.p.

Reset

.......

R/W
VMA

---0

1""

500 ns max

-~~IFFFE
~~
~~~~~-----~

'-1/

Data
Bus

--=-f--t/~

of f

~~
~~

Reset Routine
Address Bits 0-7

~-~~~~~.
Reset Routine
Address Bits 8-15

FIGURE 4-1.3-1. RESET Timing

Instruction of
Reset Routine

Cycle
#1

----,

Cycle

r--I

Cycle

Cycle
#4

Cycle
#5

Cycle
#6

Cycle
#7

r-l

Cycle

Cycle
#10

Cycle
#11

r-1

Cycle
#12

Cycle
#14

Cycle
#13

Cycle
#15

rfJ1

Address
PLS
IRQ or
NMI
1M
Data
Bus
Inst (X)

PCO-7

XO-7

PC8-15

ACCA

X8-15

ACCB

~NeWPC8-15

First Inst. of
Interrupt Routine

Address

R/W

~
.......

VMA

FIGURE 4-1.3-2a Interrupt Timing

-.J

Address
Bus

Note 1
n+1

n+2

n+3

n+4

Cycle
#n+5

R/W
VMA

~ ~200ns

IRQ
NMI
Data
Bus

-~,'f--

==:J
Wait
Inst

x==:x

PCO-7

XPC8-15 X IX-0-7 XIX8-15 X ACCA X~?
ACCP
CCR

BA
NOTE 1: Midrange waveform indicates high
impedance state.

rfJ2 of Cycle
#10

FIGURE 4-1.3-2b Wait Instruction Timing

(

~
First Inst.
of Interrupt
Routine

CA(~~~1f~B)2 {

- - - - - - - - - - - - - -____

~.-------------~t~--------------

FIGURE 4-1.3-3. Interrupt signal Format

INTERRUPT ENABLING DURING HALT AND/OR WAI
While there are nominally no restrictions on the format of interrupt signals into CA 1, CA2, CB 1,
and CB2 of the PIA, there are certain combinations of system situations that require special consideration.
Assume that the interrupt signal format follows one of the cases shown in Figure 4-1.3-3 and that the PIA has
been conditioned by the MPU to recognize the transition polarity represented by the "trailing edge" of the
interrupt pulse.
The design of the PIA is such that at least one E pulse must occur between the inactive and active
edges of the input signal if the interrupt is to be recognized. Relative timing requirements are shown in Figure
4-1.3-4. Note that an internal enable signal that is initiated by the first positive transition of E following the
inactive edge of the input signals is included.
E=VMA~

PIAlnte,"aIEn'b~~

iA'O.

Enables}

Int. to CA(B)lnpu"

(Int. req. to MPU)

~------------------------

FIGURE 4-1.3-4: Interrupt Enabling

When the MPU has been halted either by hardware control or execution of the Wait For Interrupt
(WAI) instruction, its VMA output goes low. Since VMA is normally used to generate the Enable signal (E =
VMAecp2) either of these two conditions temporarily eliminates the E signal. The effect of this on the trailing
edge interrupt format is shown in Figure 4-1.3-5 where it is assumed that VMA went low and eliminated the
Enable pulses before the PIA's interrupt circuitry was properly conditioned to recognize the active transition. It
should be noted that this condition occurs only when an active transition is preceded by an inactive transition
and there are no intervening E pulses.
~ After Halt or WAI

VMA

F = VMA·1j>2

r-,
I

,-,
\

,-,
I

_ _~_ _~\~~I_ _~\~-LI_ _ _ _~\_ _~/_ _ _ _~)_ _~I~

PIA Internal Enable

,--------------------------

~~,~-:

Interrupt to CA(B) Inputs

IRQ (Int. req. to MPU)

_ _ _ _ _ _ _ _ _

FIGURE 4-1.3-5. Interrupt not properly enabled

4-18

If this combination occurs during system operation, valid interrupts will be ignored. Either of two

simple precautions can be adopted. If the format of the interrupt signals is up to the designer, the potential
problem can be avoided by not using the pulse-with-trailing-edge-interrupt format.
If this format is compulsory, the Chip Select signal can be generated by ANDing VMA and one of

the PIA's chip select inputs as shown in Figure 4-1.3.6, while the cf>2 clock is used to enable the PIA.

Acj)

From
Address
Bus

RScj)

RS1

CScj)

A13

CS1

A14

CS2

VMA

cj)2

FIGURE 4-1.3-6. Alternate Enable Generation

4-1.4

THREE-STATE CONTROL LINE OPERATION
When the Three-State Control (TSC) line is a logic one, the Address Bus and the R/W line are placed

in a high impedance state. VMA and BA are forced low whenever TSC = "1" to prevent false reads or writes
on any device enabled by VMA. BA is low to indicate that the bus is not available for long term use. While TSC
is held high, the cf> 1 and cf>2 clocks must be held high and low, respectively, in order to delay program execution
(this is required because of the bus lines being in the high impedance state). Since the MPU is a dynamic device,
the clocks can be stopped for no more than 4.5 JLsec without destroying data within the MPU.
Figure 4-1.4-1 shows the effect of TSC on the MPU. TSC must have its transitions within 50 nsec of
the leading edge of cf>1 while holding cf>1 high and cf>210w as shown. Within 500 nsec of TSC going high, the
Address Bus, and R/W line will reach the high impedance state with VMA being forced low. In this example,
the Data Bus is also in the high impedance state while cf>2 is being held low because DBE is controlled by cf>2. At
this point in time, a DMA transfer could occur as explained in Section 4-2.2.2.
When TSC is returned low, the MPU's Address and R/W lines return to the bus within 500 nsec.
Because it is too late in cycle number 5 to access memory, this cycle is a dead cycle used for synchronization
and program execution resumes in cycle 6.

4.1.5

M6800 FAMILY INTERFACE AND ENABLING CONSIDERATIONS
The specifications of the M6800 family allow easy interfacing with other family members and with

TTL systems. All logic levels (with the exception of the clocks) are TTL compatible with the outputs having a
fanout of 1 7400 TTL load and 130 pf shunt capacitance at a 1.0 MHz clock rate. TTL logic level compatibility
allows the system designer access to a whole realm of standard interface and memory devices to complement
the M6800 family.
The limiting factor on size in building a M6800 system without buffering will usually be the loading
on the data bus. Data bus loading by family devices in the high impedance state is 10 JLa of leakage current with
10 pf of capacitance each for the PIA and ACIA and 15 pf of capacitance each for the MPU, RAM, and ROM.

4-19

Cycle

System
cf>1

MPU cf>1

Max

Address
Bus

R/W

.-.;;,,,--~'"'l

VMA

Data
Bus

~~~

cf>2 = DBE

TSC

--~

50 ns
Max

Data Not Valid

FIGURE 4-1.4-1. Three-State Control Timing

Each family device can source 100;.,ta and drive a 130 pfload at rated speed (refer to the family uala sheeis for
more detail), thus, the data bus fanout varies from 7 to 10 family parts when assuming 25-30 pf of stray
capacitance. Once the system becomes larger than the 7 to 10 family parts of a minimum system, Bus Extenders
(BEX) are necessary in order to increase the fanout.
Figure 4-1.5-1 shows a generalized block diagram of a buffered M6800 system. The different
modules shown could be composed of family members (PIA, ACIA, 128 X 8 RAM, and lK X 8 ROM) or other
devices such as 4K RAMS (forlarge memory arrays) or bipolar PROMs (for bootstrap loaders). Bus drivers and
receivers are available which provide a fanout on the order of 50 receivers for each driver, providing almost
unlimited system expansion.
The buffers shown are used on the unidirectional lines, i.e., Address, R/W, VMA and 2 of a valid read cycle in
which case the driver is disabled and the receiver enabled. The logic of the data transceivers for the module
enables the receiver and disables the driver except during cf>2 of a valid read cycle for that module (For a valid
read cycle, the receiver is disabled and the driver enabled). The AD DR input to this logic is used to enable only
one driver of the modules on the bus at anyone time and is dependent on the address decoding method used.

Address and
Control Bus ••

Data
Bus

r----------. AO-A 15, R/W
VMA, (j>2
19

MC6800
MPU

Buffer
(Driver)

r - - - - - - - - - - - - - - - ,I
I Module #1
I

---

---+----+-~-

00-07

I
I

Buffer
(Receiver)

I __ AO-A15
R/W,(j>2
VMA

I
Data
Transceiver

_
~---+--

I
I

..
II -I

I
I
I
I

Data
Transceiver

I --

00-07

I
I

(j>2, VMA, R/W

I\.

Buffer
(Receiver)

AO-A15
- . R/W,(j>2
VMA

Data
Transceiver

. . . . 00-07

FIG U R E 4-1.5-1. Buffered M6800 System

4-21

OTHER MODULES
MC8T97
AO

r - MC6800
MPU

- - - - - - - - - - - - - - - MODULE #N

MC8T97

MC8T26

•
•
•

A15

DO
R/W

•
•
•

VMA
RAM
<1>2

•

ROM

•

PIA
MC8T26

•
ACIA

DE
<1>1

•

<1>2

•

1/3 MC7410
<1>2
D<1>
VMA
R/W

1/2 MC7420
RE

<1>2
VMA

R/W
Addr

I
L

_ _ _ _ _ _ _ -.1

OTHER MODULES

FIGURE 4-"1.5.2. M6800 Bus Expansion Example

4-22

Enabling Considerations of Module Devices
VMA, R/W, and 4>2 are all available to enable RAMs, ROMs, and PIA/ACIAs. In some cases, it
may be desirable to eliminate one of these enabling signals so that the enable input is available for address
decoding. The following discussion indicates which control signals could be deleted for a given device and the
effects on the system operation:

ROM
R/W and 4>2 can be used to enable the ROMs without using the VMA signal. Not using
the VMA signal means that the ROM may be enabled during a non-memory reference read cycle
(VMA would be low but since it is not used, the ROM may be enabled). A false read of the ROM
will have no effect on the system and if the non-memory reference cycle had been a write, then the
R/W signal would have disabled the ROM.

RAM
VMA can be left off as an enable to a RAM if the MPU will not be halted, the WAI instruction
not used, or if the TSC will not be used. Either of these conditions cause the Address lines and the
R/W lines to float which could produce a false write into RAM if not prevented by VMA. During
normal operation of the MPU, only one instruction, TST, causes a false write to memory (i. e. , the
R/W line going low without VMA going high). This instruction does not pose a problem because it
first reads the memory and then rewrites the same data. If VMA was used to enable the RAM, this
false write would not occur, however, since the memory is rewritten with the same data, no problem
occurs by not using VMA as an enable.

PIA/ACIA
All three signals must be used to enable or select a PIA or ACIA. Both of these devices
automatically clear the Interrupt Flags when the MPU reads the PIA or ACIA data registers so that a
false read of a PIA or ACIA may cause an interrupt on CAl, CB 1, CA2, or CB2 to be missed. In
addition, it is suggested that VMA.4>2 not be used as an Enable signal for a PIA because, if the
machine is halted, VMA is forced low removing the clocks from the PIA. Without the Enable input
to the PIA, an external interrupt may not be recognized. 1 4>2 should be used for the PIA Enable
signal so that the PIA Enable clock always occurs whether or not the MPU is halted. VMA may then
be taken directly to Chip Select inputs or be gated with address signals to the Chip Select inputs.

lRefer to Section 4-1.3 for a complete explanation.

4-23

4-2

M6800 SYSTEM HARDWARE TECHNIQUES

INTERRUPT PRIORITY CIRCUITRY

4-2.1

The interrupt control features of the MC6800 are described in Sections 3-2 & 3-3. The software
polling and prioritizing methods discussed there are adequate for most applications. However, in s,ystems
having several interrupts that must be handled quickly on a priority basis, hardware prioritizing circuitry can be
used to advantage.
The prioritizing method recommended in Chapter 3 is shown in more detail in the block diagram of
Figure 4-2.1-1. With this technique, each interrupting device is assigned a separate ROM location which is
used to store the starting address of a service routine. After the MPU recognizes an interrupt, external circuitry
selects the interrupt that is to be serviced and directs the MPU to the proper location in memory.

---

The MPU responds to an IRQ by trying to fetch the IRQ vector address from locations FFF8 and
FFF9. However, some of the address lines are no longer tied directly to memory but go instead to a l-of-2 Data
Selector. The other set of inputs to the Data Selector is generated by a Priority Encoder that outputs a binary
number corresponding to the highest priority interrupt signal present at the time the interrupt is recognized by
the MPU.
Detection of addresses FFF8 and FFF9 by the INTERRUPT ADDRESS DECODE circuitry then
causes the outputs of the Priority Encoder to be substituted for part of the normal address. Hence, even though
the MPU outputs FFF8 and FFF9, other locations are read by the MPU.
8-Level Prioritizing

4-2.1.1

Specific circuitry for prioritizing eight interrupts is shown in Figure 4-2.1.1-1. The interrupting

System
Clock

-..

Interrupt
Address
Decode
&
Control

2
Interrupt
Inputs
In Order
of
Priority

------.
--

--.
5 --.
4

6
7

S ~

...

(

Address Bus

IRQ To MPU

Clk

Interrupt
Register
(latches
or
fl ip-flops)

-.
-...

----

r-----

~
~

I--

--....
-

Priority
Encoder

-----

r----

Quad
1-of-2
Data
Selector

r--------

...

---.

FIGURE 4-2.1-1. 8-level Priority Interrupt Configuration Block Diagram

4-24

A9
AS
A7
A6
A5
A4
A3
A2
A1
AI/>

Read
Only
Memory

Data Bus

r---2), thus initiating an IRQ.
After setting the Interrupt Mask and stacking its contents, the MPU responds in the normal manner
by outputting FFF8 and FFF9 onto the Address Bus where it is decoded by the INTERRUPT ADDRESS
DECODE circuitry. The resulting decode pulses are shown in the relative timing diagram of Figure 4-2. 1. 1-2.
The INTERRUPT DECODE signal causes the MC8266 Data Selector to select the Priority Encoder
outputs for addressing inputs Al through A4 of the ROM. If any address other than FFF8 or FFF9 is on the
Address Bus, INTERRUPT ADDRESS DECODE is low and the normal AI-A4 address lines are routed to the
ROM.
The INTERRUPT ADDRESS DECODE signal is also used in generating the LATCH CLOCK
DISABLE signal. When the INTERRUPT DECODE pulses are not present, the contents of the D flip-flops in
the Interrupt Register are updated by each negative transition of 1>2. During retrieval of the current interrupt
vector, further changes on the interrupt inputs are shut out by disabling the LATCH CLOCK. The clock is
disabled by the presence of the INTERRUPT DECODE signal on the D input of the LATCH CLOCK Disable
flip-flop which causes the disable signal to go high on the next negative transition of 1>1.
On the negative transition of 1> 1 following the FFF9 decode pulse the D input to the disable flip- flop
will again be low, the disable signal will go low, and sampling of the interrupts will be resumed.
When no interrupts are present, all inputs to the Interrupt Register/Priority Encoder are low and IRQ
is high. With one or more of the interrupt inputs high, the Priority Encoder translates the highest priority input
into a corresponding 4-bit output. The priority is an indicated in Table 4-2.1.1-1; IO is the highest, 11 is second
highest, etc. The response of the Priority Encoder to various combinations of interrupts is shown in Table
4-2.1.1-1.
The AI-A4 outputs corresponding to each priority are obtained by encoding a 256 X 4 PROM with
the desired results. 2 The code is determined by where the vectors are to be located in memory. In this case, the

VMA

Int. Addr.
Decode

Latch Clk.
Disable

Latch
Clock

,-----,,

FIGURE 4-2.1.1-2. Prioritizing Interrupt Circuitry Relative Timing

IThe MC8502 Longitudinal Redundancy Check/Data Register is a dual-mode circuit developed for use in 9-channel magnetic tape
systems. It contains nine flip-flops and logic to detect an all zeros condition. All nine flip-flops have common reset, clock, and mode
control inputs. Each flip-flop may operate either as a Toggle (mode control high) or D (mode control low) flip-flop. The flip-flops are
edge-triggered and are updated on the negative edge of the clock input. An all zero condition in the register is indicated by a low state at
the Match output.
2 A complete code listing is shown in Table 4-2.1.1-2.

4-26

IRQ vectors are contiguous with the RES, NMI, and SWI vectors as shown in Figure 4-2.1.1-3. The code that
must be generated by the Priority Encoder to accomplish this is enclosed by dashed lines in the Figure.
If a conventional8-input priority encoder such as the MC9318 (see next section) was used only five
interrupts could be implemented without additional address decoding. This is due to the fact that three of its
inputs would, if active, cause the addresses for RES, NMI, and SWI to be accessed by an IRQ. Use of the
PROM allows any desired code and, hence, any memory locations to be selected.
In this example, addressing is shown for an MCM6830 1024 X 8 ROM assigned memory locations
FFOO to FFFF with the interrupt vectors located at the top of memory. If no interrupts are being processed, lines
AO through A9 of the Address Bus select individual ROM locations in the usual manner. A suitable chip enable
for locating the ROM at FFXX is developed by decoding A10-A15 and tying it to an E on the ROM. The chip
enable requires no additional logic since A10-A15 must be decoded for the interrupt circuitry anyway.

Interrupt
Priority

1 (H ighest)
2
3
4
5
6
7
8 (Lowest)

0
0
0
0
0
0
0

X
X

0
0
0
0
0

X
X
X
X
1

X
X
X
X
X

X
X
X
X
X
X

0
0
0

X
X
X
X
X
X
X

0
0

1
0

X
X
X

0
0
0
0
0

0
0
0
0

0
1
0
1
0

0
0
1
0
0
0
0

0
0

1
0

1
0
0
1
0
0

0
1
0

IRQ
0
0
0

0
0

0
0
0

Vector Location
FFF8 - FFF9
FFF6 - FFF7
FFF4-FFF5
FFF2 - FFF3
FFFO - FFF1
FFEE-FFEF
FFEC-FFED
FFEA-FFEB

X = Doesn't matter

TABLE 4-2.1.1-1. 8·Level Priority Circuitry Truth Table

4-2.1.2

13-level Prioritizing

For the 8-level prioritizing circuitry described in the preceding section, the vector addresses were
located near the top of a block of memory assigned locations FFOO to FFFF. This required decoding address
lines AIO-A15; in addition, for purposes of illustration, the Interrupt Address Decode signal was generated by
doing a complete decode of the Address Bus.
In a typical application, the block memory assignments may be different and the decoding can be
simplified. This is illustrated in Figure 4-2.1.2-1 where the specific circuitry for prioritizing 13 levels of
interrupt is shown. The addressing follows the example of Section 1-1.2.1 and assigns the ROM to memory
locations COOO through C3FF by tying address lines A14 and A15 to chip enables on the ROM.
The requirements for decoding the IRQ Interrupt Address Decode signal are determined by the
following considerations:
(1) When the MPU places addresses on the Address Bus during interrupt sequences the vector data
is fetched from the memory locations that respond to those addresses even though they are not
actually locations FFF8 through FFFF. For example, if the MPU outputs the address FFFF (all
ones) while fetching the vector data for a Reset, in this case it is actually addressing memory
locations C3FF in the ROM since the A15 and A14 "ones" on the chip enable selects the
particular ROM and the X3FF portion of the address is determined by the ones on AO-A9.

4-27

ADDR
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85

IS II IS 15 I4 13 .I2 11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

A4A3A2A1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

000
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
0 0 1
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
0 0 0
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
0 0 1
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
1 1 1
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
0 0 1
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
0 0 0
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
0 0 1
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
1 1 0
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
0 0 1
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0
0 1 1
1 0 0
0 0 0
1 0 0
0 1 1
1 0 0
0 1 0
1 0 0

ADDR

IS 17 16 15 14 I3 12 11

86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0

0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1

1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

A4A3A2A1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1

0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1

o
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0

1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

ADDR

18 17 16 15 14 13 12 11

172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

TABLE 4-2.1.1-2 PROM Coding for Priority Encoder

4-28

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
,0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

A4A3A2A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0

0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
0
0

(2) During system operation, the unused lines All and A12 will be high only when the MPU is
processing an interrupt; otherwise the address generated would be outside (below) the highest
system assignment.
(3) If one of the lines All-A13 is included in the decode, the MPU's response to an IRQ can be
decoded by distinguishing between XXX8 and XXX9 and the other fourteen possibilities that
can be generated by Al through A4.
The resulting decode requirement is simply A 1·A2·A3·Al 3 , as shown in Figure 4-2. 1.2-1. INTERRUPT ADDRESS DECODE will be high only when the MPU has put FFF8 or FFF9 on the Address Bus.
Operation of the clock disable and data selection control for the 13-level circuitry is identical to that
described in the preceeding section for the 8-level case. However, a different priority encoding method that
uses two cascaded MC9318 8-input Priority Encoders is shown (this technique can be extended to any required

ADDRESS BUS

A15 A14 A13 A12 A11 A1D A9 A8 A7 A6 A5 A4 A3 A2 A1 AD

(V MA • A 1 5 • A 14 • A 13 • A 1 2 • A 11 • A 10)
,

ROM Connection

--.......,,-

E
0

FFFF}_
RES

FFFE

FFFD}_
NMI
FFFC

0
1

FFFB}SWI
FFFA

FFF9 }

FFF8

FFF7 }
FFF6

FFF5}
FFF4

r,-1"-o--o-'

I
I

I
L

1
0
0

0_ _ ~ _

I
I
I

_.2.J

1
0

FFF3} 4
FFF2
FFF1} 5
FFFO
FFEF}
6
FFEE
FFED}
7
FFEC
FFEB} S
FFEA

FIGURE 4-2.1.1-3. Interrupt Vector Memory Allocation

number of priority levels). The five additional interrupt register stages are obtained by using the ninth flip-flop
in the MC8502 and an MC4015 Quad D Flip-Flop.
The characteristics of the MC9318 Priority Encoder introduce several other minor differences
between the 13-level and 8-level circuits. Their operation requires active low input signals, hence the interrupts
must be active low. The OUT of the lowest priority MC9318 stage can be used to generate IRQ. EOUT of the
highest priority stage (E'OUT in Figure 4-2.1.2-1) is used for the fourth bit, A4.
The resulting truth table for this configuration is shown in Figure 4-2.1.2-2. The' 'substitute partial

4-29

I nterrupt Address Decode:
1/2 7479

I ~ ro(l=~~L 2, BA or DMA

- - ---

GRANT, VMA, HALT or DMA REQUEST, and R/W. The cf>2 clock occurs whether the MPU is halted or not
and is used to synchronize the DMA data.
The Bus Available (BA) signal from the MPU goes to a logic" I " when the MPU has halted and all
three-state lines are in the high impedance state. The VMA signal is from an open collector gate and is high
when the MPU is halted. This signal can be wire-ORed with an external signal from the DMA circuitry to
enable the RAM during a DMA transfer. The HALT (DMA REQUEST) signal from the DMA circuitry
commands the MPU to halt and place all three-state lines in the high impedance state. The R/W line is a
command signal from the DMA channel to control the direction of transfer through the DMA interface. For this
system to operate correctly, the DMA circuitry connected to the MPU's Address Bus, Data Bus, and R/W line
must have three-state outputs which are in the high impedance state when BA is low and the MPU is controlling
the Address, Data, and Control Busses. The address assignment of this system is given in Table 4-2.2.1-1.
A timing diagram of the DMA/MPU interface using this technique is presented in Figure 4-2.2.1-2.
A DMA transfer is initiated by the DMA channel pulling the HALT (DMA REQUEST) low. HALT must go low
synchronously with cf>1. The negative transition of HALT must not occur during the last 250 nsec of cf>1 for
proper MPU operation to occur. It is suggested that HALT be brought low coincident with the rising edge of cf> 1.
The MPU always completes the current instruction before halting. If the HALT line is low within 100 nsec after
the leading edge of the cf> I in the last cycle of an instruction, the MPU will halt at the end of that instruction (this
case is shown in Figure 4-2.2.1-2). If the HALT line goes low after this 100 nsec region from the leading edge of
cf> I in the last cycle of an instruction, then the MPU will not halt at the end of the current instruction but will halt
at the end of the next instruction.
SELECTION ADDRESS
BITS
A15
1

o
o

A14
1

o
1

DEVICE
ROM
RAM
PIA

ADDRESS

AMOUNT OF
MEMORY

COOO-C3FF
0000-007F
4000-4003

1024 Bytes
128 Bytes
4 Bytes

T ABL E 4-2.2.1-1. Address Assignment

What this means to the OMA channel is that the time from the HALT line going low to the MPU
halting and producing a BA (OMA GRANT) will be variable depending on what instruction is being executed
at the time HALT goes low and in which cycle of that instruction HALT goes low. Since the HALT (OMA
REQUEST) signal will probably be asynchronous with respect to the instruction currently being executed, this
will result in a variable time delay from HALT going low to BA (OMA GRANT) responding by going high. The
minimum time delay between HALT and BA is shown in Figure 4-2.2. 1-2 as being two cycles which would be
2 JLseconds at the maximum clock rate of 1 MHz. The maximum time delay would occur if the HALT line goes
low on the first cycle of a long instruction such as Software Interrupt (SWI), which is 12 cycles long. Added to

4-32

VMA

cj>2

Clock

MPU

R/W
VMA
V M A 1----11......-

MPU MC6800

AO-A9

DBO-DB7
ROM

cj>2
E
R/W

MCM6830

AO-A6

DBO-DB7

E
E

E
RAM
E

E
E

R/W
MCM6810

VMA

MC6820
AO

...1;·

CScj>

RSO
DBO-DB7

A1
RS1
PIA
A14

A15

CS1

E
RES
R/W

CS2

IRQA

CA1 CA2

Parallel I/O
(Data & Control)

DMA

-~2

Address

VMA

Bus
AO-A15

FIGURE 4-2.2.1-1. OMA Transfers by Halting Processor

4-33

HALT

R/W

Interface

Data

Bus
DO-D7

Last Cycle
of Current
Instruction
430 ns

MPU c/>1
470 ns

MPU c/>2

--f~

I
\

----I I--

0r
DMA REQUEST

470
BA or
DMA GRANT

VMA

I. rYf----l ~~

100n,---.jf-

i=i"Ai:T

f--

n,I Max--.lI

Iff

---------~~--~'

(

100 n'

_I
--.,

I-

~ 300

ns Max

'IIi

lWfL

'11/

DMA

~ =A~~r1

DMA

300n, Max

/'------

R/W

Address
Bus

)-if-{

Hf\

DMA

)

DMA

)

Data
Bus

LJ)/ U

Vi\iiA from
DMA Channel

Data Not Valid

FIGURE 4-2.2.1-2. Timing of DMA Transfers by Halting the Microprocessor

(

~d~r

•

=~~r1

)

the twelve cycles required to complete SWI is the one cycle required for the MPU's address, data and R/W
signals to go into the high impedance state. In summary then, the delay time for the BA signal to go high after
HALT goes low (assuming it occurs within 100 nsec of the leading edge of cf>1) will vary from two to thirteen
machine cycles. This delay must be taken into account in the design of the DMA channel, however, it should
not present a significant problem in most systems.
The other signals shown in Figure 4-2.2.1-2 indicate the response of the MPU to the HALT
command. The VMA signal is forced low within 300 nsec of the leading edge of the cf> 1 signal that occurs after
the last instruction cycle has been completed. This signal going low will prevent false reads or writes to memory
or peripherals on the MPU bus as the address and R/W lines go into the high impedance state. VMA from the
MPU will remain low as long as the MPU is halted. The address, R/W, and data lines will be in the high
impedance state when BA reaches the logic" 1" state, indicating that DMA transfers can begin. Addresses,
R/W commands, and Data to or from the DMA interface are shown in the timing dIagram synchronized with cf>2
to indicate the DMA transfers. The MPU can remain in the halted mode indefinitely placing no constraints on
the length of the DMA transfer.
Note that the RAM is enabled by VMA which is the output of an open collector inverting gate with
VMA (from the MPU) as its input. This VMA signal is provided to the DMA interface so that the RAM can be
enabled during the DMA transfer. During the transition into the DMA mode, the VMA signal from the MPU
was forced low (forcing VMA high) to disable the RAM in order to protect it from false writes or reads as the
address and R/W lines went into a high impedance condition. During DMA transfers, the VMA signal is
wire-ORed with a DMA controller signal to enable the RAM. In order to exit the DMA mode, the HALT line is
switched high (synchronously with the leading edge of cf>1), the BA signal returns low and the MPU resumes
control. When BA returns low, it is required that the DMA channel's address, R/W and data lines be in the high
impedance state and that VMA from the DMA channel be high so as not to affect MPU operation.
4-2.2.2

DMA Transfers by Cycle Stealing
The previous section discussed the transfer of DMA information by completly halting the MPU

which stops program execution. This section discusses a technique of DMA transfer which slows down
program execution during DMA transfer but does not completely stop execution. The basic technique is to
"steal" MPU clock cycles for a DMA transfer; this results in a apparently lower clock rate and, therefore,
slower program execution during the DMA transfer.
The block diagram of Figure 4-2.2.2-1 uses the same minimum system concept as was used in
Section 4-2.2.1 to illustrate this DMA technique. The DMA Interface using this technique is composed of the
following signals: a 16-bit Address Bus, an 8-bit Data Bus, CLOCK, VMA, Three-State Control (TSC), and
Read/Write (R/W). The CLOCK signal is an uninterrupted system clock that is used to synchronize DMA data
transfers with the execution of the MPU. The VMA signal frrom the DMA interface is wire-ORed with the
VMA signal generated in the clock circuitry to enable the RAM for either MPU access or a DMA transfer. The
Three-State Control (TSC) or DMA ENABLE signal causes the address bus and the R/W signal to go into the
high impedance state and forces the VMA signal low. This signal can also "stretch" the cf> 1 and cf>2 clock
signals. The Read/Write (R/W) line controls the direction of the data in or out of the DMA Interface. The
Address Bus, Data Bus, and R/W signals at the DMA Interface must have three-state outputs so that when TSC
is low, the DMA signals will not interfere with normal MPU execution.
A timing diagram of the DMA/Microprocessor interface using this technique is shown in Figure
4-2.2.2-2. Assume that the clock rate is initially adjusted to 1JLsec and that the MPU is executing the control
4-35

IRQ
RESET
BA
2
OBE
2
1

MPU

TSC
VMA
R/W
VMA

TSC
VMA

MPU MC6800

AO-A9

OBO-OB7
ROM

E
E

R/W
E

MCM6830

AO-A6

OBO-OB7

E
RAM

E
E

R/W
MCM6810

(f)
(f)

"tl
"tl

OBO-OB7

A1
RS1
PIA
A14

A15

CS1

RES

CS2

IRQA

R/W

CAl CA2

Parallel I/O
(Data & Control)
-

Clock

Address

VMA

TSC

Bus

R/W

Data

Bus
00-07

AO-A15

FIGURE 4-2.2.2-1. Block Diagram of DMA Transfers by Cycle Stealing

4-36

OMA
Interface

-1

r - 1 j.Ls Min

Clock

"OJ

()

CII

)

c::

....co
(J)
M

CII

c::

()

DATA

'---

I-

>
"ai
DATA

4:1~
:?!Ia:
o W

.....

-..

i=iALT"

= "1"
TSC = "0"
DBE =

Addresses, R/W, VMA, Clock

....Q)

....co

!l
U?

~r--

PIA, ACIA, ROM

-j

~:
I
I

I
I
1 __

FIGURE 4-2.2.3-1" Multiplexed DMA/MPU Operation

MA ADDR
W, VM1
MA Clock

MA Synch

1....
..
- - - - - - 600 ns - - - -......
-.11
C1

I
~~
___- - - - - - 6 0 0 n s - - - -___~~1

....
1...------560nS------~~-.l1

I
1
560 ns

MPU Address
Bus, VMA, R!W

MCM6605 Address,
R!W, CS Inputs
104-----i~

__- 3 8 0 n s -__~

180 ns
MCM6605 CE
Input

~ J ~;'~~~~5
U

-g

MPU
Data Bus

II:
Q)

(

MPU

Data Bu,
40

ns~ ~

320 ns

MCM6605
Data Bus

Not Valid

FIGURE 4-2.2.3-3. Timing of Multiplexed DMA/MPU Operation Using MCM6605 4k RAM

During a Read cycle, data is specified to be valid 190 nsec after the leading edge of the CE signal,
assuming that the addresses are valid 20 nsec before the CE signal (which is the case here). Assuming a 40 nsec
delay between the data lines of the memory array and the MPU data bus results in 150 nsec of valid data before
the trailing edge of cp2. This exceeds the MPU requirement of 100 nsec by 50 nsec. In a Write cycle, the data is
valid on the MPU Data Bus within 200 nsec of the leading edge of

cp2.

Again, assuming a 40 nsec delay

between the MPU data bus and the data lines of the memory array results in 320 nsec of valid data before the
trailing edge of CE. This exceeds the minimum DIN stable requirement of the 4K RAM (160 nsec) by a factor of

2.
This timing has been based on the MCM6605, which is one of the faster MOS memories available.
Even with this memory, the processor is required to run slightly slower to avoid exceeding the memory's speed.
Many other timing diagrams could be drawn for the variety of memory devices available but the exact system
implemention depends on the following considerations: DMA channel speed requirement, MPU execution rate
requirement, and the speed of memory devices available.

441

4-2.2.4

Summary of DMA Techniques
Table 4-2.2.4-1 summarizes the DMA techniques previously discussed plus a comparison with a

technique of bringing the data in through a PIA under software control, which is described in Section 5-4 on the
Floppy Disk Controller design.

TECHNIQUE

MAX DMA CHANNEL RATE

Halt Processor
Cycle Steal
Mu Iti plexed D MA
Software/PIA

1 byte/1 J.lS11
1 byte/2.5J.ls
1 byte/1.2J.ls
1 byte/14 J.lS

MPUPROGRAM
EXECUTION RATE

HARDWARE
COMPLEXITY

Lowest
Medium
Highest
Lowest

1 cycle/5J.ls
1 cycle/1.2J.ls
Dedicated to service
DMA Channel

1 Limited only by memory speed.

TABLE 4·2.2-4.-1: Summary of DMA Techniques

The first DMA technique is to halt the processor and transfer the DMA data at the maximum rate the
memories can handle. This technique has the advantage of requiring the least amount of hardware of the
techniques discussed, but has the disadvantage of stopping program execution. The second technique of cycle
stealing is a compromise between DMA transfer rate, MPU execution rate, and hardware complexity. The
MPU execution time and the DMA transfer rate can be maximized using the third technique with an increase of
system hardware complexity and memory speed by using a multiplexing technique for DMA. The Software/
PIA technique is based on the data being brought into memory through a PIA or ACIA interface under MPU
software control. Using this technique, the MPU can be used at full capacity to service a data channel with a
date rate of approximately 1 byte every 14 /LS.
This brief description of DMA techniques is intended to provide a basic understanding of how the
various control signals of the MPU can be used to implement a DMA channel. Each system design will involve
different tradeoffs in order to satisfy the specific system requirements.

4-2.3

AUTOMATIC RESET AND SINGLE CYCLE EXECUTION CIRCUITRY
In an MPU based system where a manual reset is not desirable (manual reset can be accomplished

with a switch and a debounce circuit), such as a remote peripheral controller, an automatic RESET signal must
be provided. A circuit designed to accomplish this must satisfy the two start up criteria:
(1) It must insure that the power supply to the MPU has reached the minimum required operating
voltage of 4.75 Vdc.
(2) The RESET line must then be held low for a minimum of 8 complete clock periods.

Of the many ways in which these criteria can be met, the circuit shown in Figure 4-2.3-1 is among the cheapest
and simplest.
The MC 1455 TIMER MODULE provides the delay necessary to complete a minimum of 8 clock
cycles with the R2C2 time constant after the RlCl time constant input has triggered the device insuring that Vee

4-42

VCC
All resistors are 10% % W carbon
all capacitors are ceramic

RST

VCC
3.3 k

I:J VSS
I -

0 Re'e'
TSC

Cl Halt

I 9
4

cf>2

IRQ
VMA

N on-Maskable Interrupts

•

OSE

cf>1
•

•

R/W

IClk

OutPut~I--"'''__----------------~

o
•

Iinput

Halt Inputs

A3
Flip-Flop

N.C.

A15

A14

A13

A10

A12

A11 _ _ __
L..-_
VSS

•

6 '

10SCRG.

t---+----II Out

1/6 MC7405

MC1455
Gnd

,J::.

NMI

- -....
CI
..... VCC

.J:::.

cf>1

Tng
I Thres

•

3.3 k

VCC .

Maskable Interrupts

RESET Inputs

C2
C3

RESET Circuit for Automatic
Power on RESET or
Power Failure Restart

R1 =
C1 =
R2 =
C2 =
C3 =

n.}
n.

1 Meg
.1 IJf
1 Meg
.4lJf (4 x .1 IJf)
.1 IJf

}

Delay for a
Minimum of
8 Clock
Periods

Note: A RESET switch may be used where
automatic operation is not required
2

p~---...."
1

VCC

* HALT

may be tied high similarly to IRQ
-and NME. as long as the HALT circuitry
will not allow the HALT transition to
occur during the last 250 ns of cf>1

5 ms
Time

FIGURE 4-2.3-1. Automatic Reset and HALT Synchronization

400 ms

has reached the minimum level. The particular RC values shown were chosen to be used with a crystal oscillator
clock circuit which has a start-up time of approximately 100 ms. A 400 ms time out was used to cover the
tolerances of the components used with room to spare. In an application requiring minimum reset delay, a
counter could be used to determine when the 8 clock cycles were complete.
The interrupt inputs, IRQ and NMI, need not be tied high if they are not used due to internal pull up
resistors, but greater noise immunity will be had if they are tied high with a 5.IKO resistor. In wired-or
interrupt applications, a pull up resistor of 3.3KO will provide optimum device operation.
The HALT input must not make a transition during the last 250 ns of cp 1. If this input is to be used in
applications requiring the MPU status be saved (most applications), it must be synchronized with the leading
edge of cpI or the trailing edge of cp2. A flip-flop will accomplish this synchronization, or the circuitry
generating the HALT request may use the system clock and not require extra hardware. This input also may be
wire-ORed using an external 3. 3Kfi pull up resistor.
Single instruction operation, which is useful during debug, is accomplished by holding the HALT
high for one cpI clock cycle (Figure 4-2.3-2).

Non Overlapping Clock
Is Exaggerated

c:f>2

~----~?~?----------------

For Single Instruction
Operation ON L Y

. . . - No MPU ActivitY--I.......
I· __- - - - Execute One Instruction - - - - - 1......1

FIGURE 4-2.3-2. Single Instruction Timing

The circuit and timing diagrams of Figure 4-2.3-3 show how the single instruction execution can be
accomplished in conjunction with the HALT input restrictions.
When the GO/HALT switch (S2) is in the GO position, A will be low after the first cpI clock
causing the HALT input to be high. When the GO/HALT switch (S2) is in the HALT position, A will be high
after the first cpI clock. Since S 1's normal position causes C to be low, signal B will be high. A and B
high cause the HALT to go low halting MPU activity.
When S 1 is pushed, C goes high allowing the next positive cpI transition to clock Fl. Since the J
and K inputs of FI are 1 and 0 respectively, this clock will cause D to go high and B to go low. The J and K
inputs of FI are now both 1. The next positive cpI transition will cause D to go low and B to go high
clocking F2. J of FI now goes low. With both J and K of FI low, any further clock transitions will cause no
change in the outputs until C is again made to go low. A and Bare NANDed to produce the HALT input
signal.

4-44

VCC
S1 is a Momentary
Contact Push Button
Switch

VCC

2
Step One Instruction
When S2 in HALT

ClR

CLK

ClK

7473

F1
3

7400

Q 13

VCC

+5
13

h - - - - - - - - - TO

HALT
Of MC6800

Q 9
11
S2 Toggle
Switch

A
CLK

10k

Timing for GO to HALT/one instruction

%7479

VCC

Timing for HALT to GO

((

)
B

HALT
HALT

)

--GO

-I"

.1 ..

HALT

FIGURE 4-2.3-3. Single Cycle Instruction Execution

4-45

Execute One
Instruction

((I

HALT-

4-2.4

INTERVAL TIMER
A hardware interval timer circuit can be used to provide the MPU system with timing interrupts that

are under program control. This allows the system to perform other functions while long critical timing
functions, e.g., disk head step time during seek, printer line feed solenoid hold period, cassette gap and record
length, etc., are performed by the interval timer. An interval timer using an MC6820 PIA to interface to TTL
timing circuitry shown in Figure 4-2.4-1.
Table 4-2.4-1 shows how the interval timer of Figure 4-2.4-1 is programmed. An 8 bit binary count
(COUNT) is preset into the MC74455 up/down counter from Output Register B of the controlling PIA (If a
MC74454 counter was used, a 2-digit BCD value may be used). The counter then counts this value down to
zero using the clock rate provided by the programmable divider circuits. When the counter reaches 0, the SEO'
output triggers the CB 1 input of the PIA generating an interrupt to the operating system.

CB1
PB<1>

1
2

1
0
N

3
2

CX)
(0

CB2r-i>
--u7

::.!:

PRESET( Load)

III
II

01
02
03
04
05

L!)
L!)

""""U
"

PRST

10
SET

IlL

11t~

--IL

0<1>

UE
U/O

14
Clock

SED
~
14
11
PA <1>
0
N

CX)

U
~

10
3

MC9312

C
E

X5 X4 X3 X2 X1 Xo X6 X7

fr--

... ...1

TIT
<1>1
Clock
In

.,..8

13 12

3
MC74452
1

14 15

1 I
I

:II

13 12

MC74452
1

FIGURE 4-2.4-1. Interval Timer

4-46

T I
2

14 15

I 1 I ~II
-- J

PAO-PA3
b2 b1 bO

CLOCK
FREQ

0
0
1
1
0
0
1
1
0

0
100 Hz
1 KHz
10 KHz
100 KHz
1 MHz
0
0
0

0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
0

0
1
0
1
0
1
0
1
0

INTERVAL
TIMER DELAY
-

COUNT
COUNT
COUNT
COUNT
COUNT

X
X
X
X
X

10 ms
1 ms
100J,ts
10J,ts
·1J,ts

Count = Binary Value of PBO - PB7

•

01800

•

01801
01801
01801
01801
01801
01801
01900

0500
0400
0300
0200
0100
5000

I nterval Timer 8-8 it Prescale Constants

01US
010US
0100US
01MS
010MS

0005
0004
0003
0002
0001

01800
01800
01800
01800
01800

EQU
EQU
EQU
EQU
EQU

5
4
3
2

10
100
1
10

Microsecond Clock
Microsecond Clock
Microsecond Clock
Millisecond Clock
Mi II isecond Clock

I nterval Timer 16-8it Prescale Constants

S1US
S10US
S10PUS
S1MS
S10MS

EQU
EQU
EQU
EQU
EQU
ORG

1280
1024
768
512
256
15000

10
100
1
10
10

Microsecond Clock
Microsecond Clock
Microsecond Clock
Mill isecond Clock
Millisecond Clock
Millisecond Clock

TABLE 4-2.4-1. Interval Timer Programming Chart

The programmable divider uses the P AO-PA2lines of the PIA to control the MC9312 8-channel data
selector which acts as a single pole 8 position switch. A 4 decade divider chain is provided by the 2-MC74452
dual decade counters. The input clock (cf>1, nominally 1 MHz) and all 4 decade outputs (l00 KHz, 10KHz, 1
KHz, 100 Hz) are provided as inputs to the data selector. Table 4-2.4-1 shows the various data selector output
frequencies and the resulting delay generated. The binary value of COUNT is preset into the MC74454 counter
as the starting point of the count down. The counter counts down at the rate determined by the code in P AO-P A3
until the zero state is reached at which time SEO goes low causing a MPU interrupt. A one written in ba of
Peripheral Register A causes PA3 to go high, disabling the clocks to the MC74455 and the interval timer. The
timer may also be disabled by selecting a grounded input code on the 9312 as noted by "0" clock frequency in
Table 4-2.4-1.
Figure 4-2.4-2 shows examples of software control of the interval timer hardware in Figure 4-2.4-1.
In these examples, it is assumed that the PIA's are already intialized to provide PBO-PB7 and PAO-PA3 as data
output lines (ones in the Data Direction Registers). In the first example, the control registers for the A and B
sides of the PIA are initialized to provide access to Peripheral Register B, to provide a negative pulse on CB2
when the B Data Register is written into, and to cause an interrupt on the IRQ line when CB 1 sees a negative
transition. Control Register A is set up to provide access to Peripheral Register A. The clock rate of 1
millisecond is binary 0010 or decimal 2 from Table 4-2.4-1 and is stored in XP2DRA (peripheral Data Register
A) which outputs 0010 on PAO-PA3 selecting the clock rate. The counter value of decimal 236 is stored into
XP2DRB (peripheral Data Register B) causing binary 1110 1100 to appear on PBO-PB7 and CB2 to pulse low,

4-47

** 236 MS TIME OUT USING 8 BIT PRESCALE
LDAA
STA
LDAA
STA
LDAA
LDAB
STAA
STAB
C1 MS EQU

#%00101101
XP2CRB
#%00000100
XP2CRA
#C1MS
#236
XP2DRA
XP2DRB
2

PRB ACCESS, CB2 PULSE LOW, CB1 +
STORE IN CONTROL REGISTER B
PRA ACCESS
STORE IN CONTROL REGISTER A
CLOCK RATE
COUNTER VALUE
OUTPUT RATE TO PAO-PB3
OUTPUT COUNTER VALUE TO PBO-PB7
1 MI LLiSECOND CLOCK RATE

** 236 MS TIME OUT USING 16 BIT PRESCALE
LDAA
STA
LDX
STX
S1MS EQU

#$0010101
XP2CRB
#S1 MS+236
SP2DRA
512

PRB ACCESS, CB2 PULSE LOW, CB1
STORE IN CONTROL REGISTER B
LOAD INDEX REGISTER WITH S1 MS+236
RATE TO PAO-PA3, VALUE TO PBO-PB7
1 MILLISECOND CLOCK RATE

FIGURE 4-2.4-2. Timer Software Examples

thereby, presetting the MC74455 counter. CB 1 is monitoring the SED output of the counter waiting for a low
transition indicating that the counter has reached the zero state, resulting in the required 236 msec delay.
The second example uses different software code to arrive at the same result. The initialization of the
PIA's is the same as discussed previously. In this case, the index register is used to form a 16-bit word which is
then loaded into PRA and PRB. Address line AD is connected to RS 1 and Al is connected to RSD of the PIA so
that PRA and PRB are consecutive memory locations. The 16-bit word is formed by loading the sum of S2MS
and decimal 236 into the index register. Note that SIMS always will occupy XH and the offset (which has to be
less than 255) will always occupy XL of the index register. By storing this value to XP2DRA (peripheral
Register A), SIMS will be loaded into PRA and 236 will be loaded into PRB (the next memory location). This
technique of connecting the PIA for adjacent Peripheral Reg. locations and using the Index instructions to store
two bytes at a time produces the same result as the previous example with less code.
4-2.5

MEMORY SYSTEM DESIGN

4-2.5.1

Interfacing the MC6800 with Slow and Dynamic Memories
There are many different system configurations utilizing the MC6800 microprocessor (MPU) with

memories that are not a part of the M6800 family. In many applications, the most cost effective system will use
memories that are slower than the 575 ns access time required by the MC6800 running at maximum speed or
will be of the dynamic type so that the refresh requirement of the memory will have to be handled by the system.
4-48

The purpose of this section is to discuss methods of operating the MC6800 with these two classes of memories
and to describe the operation of the MC6800 in relationship to memory usage in enough detail so that the user
can develop system configurations using slow and/or dynamic memories.
The MC6800 microprocessor uses two non-overlapping clocks to time the execution of the program
by the MPU. Figure 4-2.5. 1-1 details the specification of the clock requirements for the M6800 family. The use
of dynamic registers inside of the MC6800places the following timing restriction on the clock waveforms. The
clocks can be held in one state for a maximum of 5 JLS without loss of the information contained in the dynamic
registers.
In Figures 4-2.5.1-2 and 4-2.5.1-3 are the timing diagrams of a M6800 Read and Write cycle. As
can be seen from these timing diagrams, during cp1 control lines (address, R/W and VMA) are placed valid on
the MPU bus and during cp2, data is transferred between the MPU and memories or peripherals.
The minimum cycle time is 1.0 JLsec and the following control signals are valid 300 nsec after the
leading edge of cp1: R/W (TASR), address lines (TASC), and VMA (Tvsc). During a read cycle, the data must be
valid on the data bus 100 nsec (TDSU) before the trailing edge of

cJ>2, allowing 575 nsec for memory or

peripheral access time (TACC) assuming a rise time on the clock waveform of 25 nsec. During a write cycle, the
timing is the same for the control signals; the MPU places data to be written on the data bus within 200 nsec
(TASD) after the leading edge of cJ>2 and will hold the data valid for a minimum of 10 nsec (TH) after the trailing
edge of cp2. This produces a minimum of280 nsec (470 + 10 -200) of valid data (TDATA VALID) available to be
written into the memory or peripheral. Many memory or peripheral devices including the M6800 family
devices can meet this timing requirement and their use poses no problems.
SLOW MEMORY INTERFACE
The following discussion will describe some techniques that can be used to interface the MC6800
with memories or peripherals that have an access time slower than 575 nsec and/or require data valid during a
write operation for longer than 280 nsec. The basic technique of using the MC6800 with slower memories is to
lengthen or stretch cp2, the data transfer portion of the MPU cycle. cJ>2 can be stretched to a maximum of 5.0
JLsec, allowing use of memories with an access time of 5,105 nsec (575 + 5000 -470) and a write data valid
time of 4,810 nsec (280

+ 5000

- 470). Operation of the MPU at these speeds is slow enough for the vast

majority of memory or peripheral devices on the market today. Operation with a slower device than can be
accomplished by stretching cJ>2 to 5 JLsec is possible by using the interrupt feature of the MC6820 Peripheral
Interface Adapter and treating the extremely slow memory as one would a slow peripheral.
There are two ways to implement the stretching of cp2 to accommodate slower memories. The first
and the simplest method is to stretch cp2 every cycle regardless of whether the current cycle is an access to slow
memory or not.

cp2 should be lengthened by the amount the access time of the slowest peripheral or memory

exceeds 575 nsec (TACC of 6800). Examples are shown in Figures 4-2.5.1-4 and 4-2.5.1-5 for a slow memory
with access time of 1000 nsec with cp2 increased by 425 nsec (1000-575). The cycle time of the MPU has now
become 1.425 JLsec, resulting in slower program execution by about 30% due to the slow memory. The
advantage of this approach is that it is the simplest to implement in hardware (only a change in the clock
waveforms is required). The disadvantage is the reduction of execution time and corresponding reduction in
data throughout.
If the MPU is servicing several slow peripherals, the reduction in MPU speed may not affect system

operation. However, in many systems such as real time control, the MPU speed is critical to system operation
and a 30% reduction would be undesirable. The second method of operation with slow memories that has a

4-49

~------------tCLK---------------1~
~------------tUT-----------'~

cp1

cp2

UNDERSHOOT

CHARACTERISTIC

SYMBOL

MIN

Input High Voltage 4> 1, 4>2
Input Low Voltage 4> 1, 4>2

VIHe
VILe

Vee-0.3
Vss-0.1

Clock Overshoot/Undershoot
Input High Voltage
Input Low Voltage

Vas

Input Leakage Current cf> 1, 4>2
(VIN = 0 to 5.25 V, Vee

TYP

Vee
Vss

MAX)

Capacitance
(VIN = 0, TA = 25°C, f = 1.0MHz)

+ 0.1
+ 0.3

Vee = 0.5
Vss + 0.5

Vee-0.5
Vss-0.5

MAX

lIN
120

UNITS
Vdc
Vdc
Vdc
Vdc

100

JLa

160

CIN

0.1

1.0

MHz

tcyc

1.0

JLS

PWaH

430
450

4500
4500

ns
ns

tr, tf

9050

Overshoot/U ndershoot Duration

tas

Clock High Times

tuT

940

Frequency of Operation
Clock Timing
Cycle Time
Clock Pulse Width
(Measured at Vee-0.3 V) 4>1
4>2
Rise and Fall Times 4> 1, 4>2
(Meas ured between
Vss + 0.3 V and Vee-0.3 V)
Delay Time or Clock Overlap
(Measured at Vav = Vss + 0.5 V)

FIGURE 4-2.5.1-1. MPU Clock Waveform Specifications

4-50

I~----------------------------__- -________ tcyc ----------------------------------------~

1>1

1>2

R/W

Address
From MPU
-+~

__~~~~~~--------------------------------------------------------_t~~~2.4V
---.~r------------------------TACC--------------------------~~

2.0 V----::::=-~-~===~~

Data

From Memory --------------------------------------------------------------------__a=~~~
or Peripherals
0.8 V----"""'..,.-;;;;;;;;;;;;;:;==;pr=

T ASA

= T ASC =

Data Not Valid

tcyc = 1.425 J.1s
TVSC = 300 ns Min
TACC = 1.0 J.1s Max
TDSU = 100 ns Min

1>1 PWO H = 430 ns Min
1>1 PWO H = 895 ns Min

FIGURE 4-2.5.1-4. Read Cycle With 1.0 J.1S Memory

4·52

Start of Cycle
~-------------------------------tcyc ------------------------------~

cf>1

VCC-0.3V
cf>2
- - -.....IE::T~:....r.-~~1--- 2.0 V

R/W
0.8 V ' - - - - - - - = T - - - - - - - - - - t - - - - - - - - - - - - - - - - - - _ - - - + - - _ 0.4 V
Address

~~~~~~----~--~----_+----------------------------h~~--2.4V
2.0 V

FromMPU

~0~.8~V~~~~--~1_=-----------+_-----------------------------~~~~-0.4V
2.0 V -+----~~~I-------------t--------------------------+~"""'~ 2.4 V

VMA

Data
From MPU

--~J.~-------------------n:_--------+----------------------+----~~

--~~~-------------_+.r_----

2.4 V
0.4 V

DBE = cf>2
~-----------------TEH-------------~~

Data Not Valid

cf>1 PWO H = 430 ns Min
cf>2 PWOH = TEH = 895 ns Min

tcyc = 1.425 J,1S
T ASR = T ASC = TVSC = 300 ns Max
T ASD = 200 ns Max

FIGURE 4-2.5.1-5. Write Cycle With 1.0 p,s Memory

smaller reduction in MPU execution time involves the use of a Memory Ready concept. In this configuration, a
MEMORY READY signal is used between the slow memory and the MPU clock circuitry to indicate that a
slow memory has been accessed. This signal goes low long enough for data to become valid out of the slow
memory. While MEMORY READY is low, cf>2, is stretched or lengthened as shown in Figure 4-2.5.1-6. This
technique only slows execution of the processor when the slow memory is being accessed. The amount by
which the throughput of the MPU is reduced due to the slow memory is directly proportional to the number of
slow memory accesses and can be evaluated for each system configuration. Memory devices do not inherently
provide a MEMORY READY type signal; this signal must be generated by the interface circuitry associated
with the slow memory system.

MPU cf>1

MPU cf>2

Memory Ready

FIGURE 4-2.5.1-6. Effect of MEMORY READY on Clock Signals

4-53

A block diagram of a generalized MPU to memory interface is shown in Figure 4-2.5.1-7. The
address and control signals are shown buffered from the MPU bus to increase fanout (in a small system, this
may not be required). The low order address lines (AO to A9 for a lK memory) and the R/W signal are routed to
the memory devices directly. The high order address lines, VMA, and cf>2 are decoded to select this memory
system using the Chip Select input of the memory devices. All high order address lines may be decoded,
however, in many small systems, this decoding logic may be eliminated by selecting the memory devices with
only one or two of the high order address bits. By not decoding all address lines, multiple areas of the 65K
address map are selected at the same time requiring careful assignment of addresses for memory and peripherals
(see the minimum system discussion in Chapter 1 for further explanation). The data buffers may be required for

AC/>

•
•
•
•
A15

Address
Buffers

•
•

Low Order
Address Lines
(AO - A9 For
1 K of Memory)

Memory Array

High Order
Address Lines

R/W

Control
Signal
Buffers

VMA
C/>2

C/>2

Memory
Decode
Logic

'---~

DC/>

•
•
•
•
•
07

VMA

Data
Buffers

Pulse
Generator

1--+--___

Memory Ready

I nput and Output Data Lines

•

• Optional Depending on Size of MP U System
··Required For Memory Ready Feature
*. * Can Be Replaced by Multiple Chip Select Inputs on Memory Devices

FIGURE 4-2.5.1-7. General MPU to MEMORY INTERFACE

system fanout considerations or may be required to combine the separate data input and data output lines found
on many memory devices into bidirectional data lines as required by the MPU. If the memory devices chosen
are not fast enough to meet the MPU timing requirements at maximum operating frequency of 1 MHz, pulse
generating circuitry can be added to provide the MEMORY READY signal. This signal can be triggered by the
Chip Select decoding logic to stretch cf>2 of the current cycle long enough to allow proper operation of the slow
memory devices.

4-54

DYNAMIC MEMORY INTERFACE
All dynamic memories have the basic characteristic that they require periodic refreshing of their data
storage elements (usually capacitors). Most dynamic memory devices handle this refresh requirement by
performing 32 or 64 refresh cycles every 2 msec. During these refresh cycles, the memory is not available for a
Read or Write cycle from the system bus (by MPU or DMA). The "memory busy" period for most dynamic
memory devices is of short duration, normally 1-5% of the total time.
The simplest method for handling this refresh requirement is to steal MPU cycles in order to refresh
the memory. The effect of the stolen processor cycles on system operation is to slow program execution or data
throughput. Figure 4-2.5.1-8 shows the dynamic memory interface and the clock waveforms associated with a
cycle steal configuration. During cf>1, address control signals are set valid by the MPU in preparation for the

..
cp2
cpl

Address and
Control Bus
MC6800

r----

r+'

..
"I;

f--cpl
Clock
Circuitry

I--cp2

en
:::I

"'-

~
(1J
0

...

Dynamic
Memory

'IIi

Refresh Request
Refresh Grant
Memo ry C lac k

MPU Bus

cpl

MPU Buscp2
Occurs Every 62.5 IlS

War'J

Refresh Request

Refresh Grant

____.-1

Memory Clock

Don't Care

FIGURE 4-2.5.1-8. Dynamic Memory Interface

4-55

data transfer during 1>2. By stretching or lengthening the 1> 1 portion of the cycle, program execution is delayed,
allowing memory refresh to take place. Circuitry in the memory system controller multiplexes in the refresh
addresses and controls the memory R/W and CS lines to provide proper signals for the refresh cycle. For a
dynamic memory that requires 32 cycles of refresh every 2 msec and with the MPU running at the maximum
clock rate of 1 f.Lsec, the reduction in MPU speed due to clock stealing would be 32 x 1 f.Lsec (100) = 1.6%.
2 msec
In most systems, this reduction in program execution time would not affect system performance.
In some systems, the design constraints may be such that a reduction in program execution time due
to memory refresh requirements cannot be tolerated. For these types of systems, a "hidden" refresh
configuration may be used. The place to hide or perform the memory refresh independent of MPU program
execution time is during 1>1 as no data is being transferred between the MPU and memory or peripherals. This
technique places the additional constraint on the dynamic memory system of being able to perform a complete
refresh cycle during 1>1 (430 ns minimum) and a complete Read or Write cycle during 1>2 (470 ns minimum) if
the MPU is to operate at full speed. Using this concept only 32 of the 1>1 periods every 2 msec are used for
refreshing (for the dynamic memory discussed earlier) leaving the other 1>1 time periods open for other uses.
One use would be for a DMA transfer from some external source. In this mode, DMA and memory refresh
would share the 1> 1 portion of the cycle while the MPU would have access to the memory during 1>2 portion of
the cycle. See Section 4-2.2 for a further discussion of DMA techniques.

4-56

CLOCK CIRCUITRY FOR SLOW AND DYNAMIC MEMORIES
The circuitry to modify the clock signals to interface the M6800 with dynamic and slow memories as
described above can be evolved from the clock circuitry described in Section 4-1.1.1. Figure 4-2.5.1-9
illustrates a previous clock circuit (Figure 4-1.1.1-3) with a crystal stabilized source which has been extended
to include interface signals for dynamic (REFRESH REQUEST and REFRESH GRANT) and slow memories
(MEMORY READY). Note that the only extra parts required are a MC7479 dual latch, MC7404 hex inverter,
and a pair of 10K ohm pull-up resistors. The state of REFRESH REQUEST is sampled during the leading edge
of cp1 and, if it is low, the cp1 and cp2 clocks to the MPU are held in the high and low states respectively for at
least one full clock cycle. A high REFRESH GRANT signal is issued to indicate to the dynamic memory
system that this cycle is a refresh cycle. Upon receipt of the REFRESH GRANT signal, the memory system
controller sets REFRESH REQUEST back high which is clocked through on the next leading edge of cp 1,
thereby restoring the system back to normal operation. The MEMORY READY line is sampled on the leading
edge of cp2 and, iflow, the MPU cp1 and cp2 clocks are held in the low and high states, respectively. The clocks
will be held in these states until the MEMORY READY line is brought high by the slow memory controller,
allowing the slow memory controller to determine the amount by which cp2 is stretched. Figures 4-2.5.1-10a, b
show the effect of REFRESH REQUEST and MEMORY READY signals on the MPU clocks. Note that the
REFRESH REQUEST signal is asynchronous with the MPU clocks as it is generated by the refresh oscillator in
the dynamic memory controller. Figures 4-2.5.11a, b shows the phase relationship between MPU cp2, BUS
cp2, and DYNAMIC MEMORY CLOCK. Note that BUS cp2 and MPU cp2 are in phase and that DYNAMIC
MEMORY CLOCK leads MPU cp2 to help offset delays added by the memory system controller in decoding
the level shifting this signal onto the memory array.

4-57

+5V

% MC3001

1/6 MC7404

Dynamic
....- - - - - - - - - •• Memory
Clock
.1Mf Ceramic

Oscillator

K1100A

% MC3000

% MC3001

% MC3000

MHz 50 ±2% Duty Cycle

% MC3001

% MC3000

% MC3001

(74H08)

(74HOO)

+5V

Y:. MC7479

10K
Refresh
~

Y:. MC7479
+5V

Request

.1Mf Ceramic

1/6 MC7404'

1/6
MC7404

+5V

+5V
Refresh
Grant

4.__----------------~
+5V

DBE
10K
Memory
Ready

NOTES:
~ss otherwise noted
All resistors are carbon composition %W, = 5%
All capacitors are dipped MICA ± 2%
2. *MPQ 6842

FIGURE 4-2.5.1-9. MPU Clock Circuitry with Interface for
Slow and Dynamic Memory

% Mc3000
10

•

BUS C/J2

MPU cjJ1

MPU cjJ2

E
()

);
l!)

REFRESH REQUEST

REFRESH GRANT

500 ns/cm

(a)

MPU Clocks, REFRESH REQUEST, REFRESH GRANT

E
()

MPU cjJ1

);
l!)

MPU cjJ2

MEMORY READY

500 ns/cm

(b)

MPU Clocks, MEMORY READY
FIGURE 4-2.5.1-10: MPU Clock Circuitry

4-59

Mem elk: 4 V Pulse

MPU ¢2: 5 V Pulse

1 V/cm

100 ns/cm
(a)

Dynamic Memory Clock and MPU 02

MPU ¢2: 5 V Pulse

Bus ¢2: 4 V Pulse

1 V/cm

100 ns/cm

(b)
Bus 2 and MPU ¢2
FIGURE 4-2.5.1-11: MPU Clock Circuitry

4-60

The circuit in Figure 4-2.5.1-12 shows how the MEMORY READY concept can be added to the
cross coupled monostable clock generator of Figure 4-1.1.1-5. The MEMORY READY feature is incorporated
into this circuit by switching an additional timing resistor in or out of the cp2 pulse width generator. By selection
of the timing resistors for cf> 1 and cf>2, all combinations of cf> 1, cf>2, and stretched cf>2 pulse width can be
generated.

+5 V

22 K 1%

11 K 1%

~~------------~__---------4~----------------~ Memory
Ready

T2
Bus

MC8602

+5 V

1/3 MC7404

33 pf

cp2

.1 Mf Ceramic

+5 V

470

+5 V

NOTE:
1) Unless otherwise noted
All resistors are carbon composition Yo.W, ±5%
All capacitors are dipped mica ±2%
2) *MPQ6842

470

*MPQ6842

FIGURE 4-2.5.1-12. Monostable Clock Generator with Memory Ready

4-61

I.1

Mf Ceramic

4-2.5.2

2K X 8 RAM Memory Design Example
This section will describe the design of a memory system for the MC6800 microprocessor using

memory devices that are not a part of the MPU family but that are cost-effective choices in many MPU based
system designs. The intent is to demonstrate the ease with which memory systems can be designed around the
MC6800 because of its straightforward architecture. The MPU signals to be considered in the memory system
design are the clock signals (cf>1 and cf>2), the 16 bit Address Bus, the 8-bit bidirectional Data Bus and the control
signals: Valid Memory Address (VMA), Read/Write (R/W), and clock control signals such as MEMORY
READY, REFRESH REQUEST or REFRESH GRANT if they are required.
The MCM6602, lK X 1 static RAM, can be a cost-effective choice for MPU memory systems in the
size range of lK bytes up to about 8K bytes. Below lK bytes, memory systems composed of the MCM6810
will probably be the cost effective choice. Memory systems larger than 8K bytes will probably use a 4K RAM
such as the MCM6605 in order to be cost effective. In this section, the detailed design of a 2K X 8 memory
system is described for the MC6800 MPU using sixteen MCM6602 L-l N-channel static MOS RAMs. This
memory system is available from Motorola as a component module of the EXORciser.
The 2K Static Memory System (illustrated in Figure 4-2.5.2-1) receives the 16 address bits AO
through A15, the cf>2 timing signal, the 8 bit bidirectional data bus, VMA (Valid Memory Address) signal, and
a R/W (Read/Write) command during each MPU memory operation. The system address lines connect to the
address bus interface and the cf>2, VMA, and R/W inputs from the MPU connect to the control bus interface.
Data lines connect to the Data Bus Interface.
CE1
Ram1
Memory
Array

•
AO-A9

AO-A15

-;.
16

Address
Bus
Interface

A10-A 15

CE2

•

r---

RAM1
Select
Circuit
~

RAM2
Memory
Array

4--

;--

6
~

RAM2
Select
Circuit

.L._

A10-A15

cf>2

---

----..
R/W ----..

VMA

t ....

cf>2
Control
Bus
Interface

VMA
R/W & R/W

-R1

---..

Control
Logic

- R/W
R2 R/W
DOE

FIGURE 4-2.5.2-1. 2k X 8 Memory System Block Diagram

4-62

Data
Bus
Interface

The address bus interface, after buffering the inputs, applies the ten address bits AO through A9 to
the RAM 1 and RAM 2 memory blocks. (Refer to Figure 4-2.5.2-2, the Schematic Diagram) The address bus
interface, at the same time, applies the six address bits A10 through A15 with their complements to the RAM 1
and RAM 2 select circuits. The control bus interface applies the VMA signal to the RAM 1 and RAM 2 select
circuits and cp2 with the R/W signal and its complement to the control logic. The two RAM select circuits
decode the address bits and determine whether the MPU is addressing their respective RAM memory block.
Since the two RAM select circuits and the RAM memory blocks are identical, only the RAM 1 select circuit and
the RAM 1 memory block will be discussed in detail.
The RAM 1 select circuit consists of two base memory address switches and a decoding circuit. The
address switches allow the 2K X 8 of memory to be allocated as two independent 1K X 8 blocks any where in
the system's 65K memory field. The base address switches select the base memory address for the RAM 1
memory block and the decoding circuit determines when its memory is being addressed. The RAM 1 select
circuit, on determining that its memory is being addressed, couples a CE1 (Chip Enable 1) signal to the RAM 1
memory block and to the control logic. The RAM 1 memory block, consisting of eight 1K X 1 bit MOS static
RAM chips, is then enabled to perform a memory read or memory write operation.
During a memory read operation, the control bus interface receives a high level R/W signal and
applies this signal with its complement to the control logic. The control logic now transfers a high level R1 R/W
(Read Memory 1 Read/Write) pulse to the RAM 1 memory block and couples a DOE (Data Output Enable)
signal to the data bus interface. The high level R1 R/W pulse instructs the RAM 1 memory block to perform a
memory read operation (providing the address select signal, CE1, is low) and the DOE signal instructs the data
bus interface to transfer the memory's output to the MPU via the system bus.
During a memory write operation, the control bus interface receives a low level R/W signal and the
data bus interface receives the eight data bits DO through D7. The control bus interface applies the low level
R/W signal and its complement to the control logic and the data bus interface applies the data bits to the RAM
memory blocks. The control logic now reads the position of the RAM 1 RAM/ROM switch and determines
whether the RAM 1 memory block is protected or may be written into. When this RAM/ROM switch is in the
ROM position, the switch inhibits the control logic from initiating a memory write operation. When the switch
is in the RAM position, however, it enables the control logic to generate a 470 nsec low level R1 R/W pulse.
This low level pulse instructs the RAM 1 memory block to perform a memory write operation and to store the
data it receives from the data bus interface. (If the address select signal (CE1) is low).
The following paragraphs discuss the operation of the various circuits contained on the 2K Static
RAM Module. Refer to the module's block diagram in Figure 4-2.5.2-1 and schematic diagram in Figure
4-2.5.2-2 as required.
The address bus interface, consisting of U1 through U4, receives and buffers the 16 MPU address
bits Al through A15. Address bits AO through A9 are applied to the RAM 1 and RAM 2 memory blocks. The
address bus interface applies the six address bits A10 through A15 and their complements to the RAM 1 and
RAM 2 select circuits. The control bus interface, U5, receives and buffers the cp2, the VMA, and the R/W
signals. The control bus interface couples the cp2 and VMA signals to the RAM 1 and RAM 2 select circuits and
applies the R/W signal and its complement to the control logic circuit. U1 through U5 are MC8T26* bus
receivers which provide very light loading on the MPU bus so that the fanout is not reduced appreciably. The
loading of these devices is - 200 /-La for a logic 0 and + 20 /-La for a logic 1.
The RAM 1 and RAM 2 select circuits decode the address bits and determine whether the MPU is
addressing their respective RAM memory blocks. Since the two RAM select circuits are identical, only the
*To be introduced third quarter, 1975.

4-63

RAM 1 select circuit is discussedin detail with the RAM 2 select circuit components identified parenthetically
after the RAM 1 select circuit components.
The RAM 1 select circuit consists of the two switches S 1 and S2 (S3 and S4) along with gate U8
(U9). Switches Sl and S2 (S3 and S4) are set during use and, through their switching of bits A10 through AI5,
select the base memory address for their respective memory block. The position of each switch determines
whether the switch is coupling the address bit or its complement to gate U8 (U9). Gate U8 (U9), on receiving a
VMA signal, decodes the switches outputs and determines whether the MPU is addressing its memory block. If
its memory block is being addressed, U8 (U9) couples a CE1 (CE2) signal to the RAM 1 memory block (RAM
2 memory block) and to gate U10A of the control logic circuit.

- - ---

The control logic circuit decodes the CE1 (CE2) signal, the R/W, the cp2 clock signal, and the
position of the RAM/ROM switches to determine whether to read data from, to write data into, or to inhibit the
write function of the selected RAM memory block. Each time one of the RAM select circuits determines that
the MPU is addressing its RAM memory block, this circuit causes gate U10A to couple a high level to gates
U6A and U6B. During a memory read operation, the control bus interface applies a high level R/W pulse to gate
U6A and R/W to gate U6B. Gate U6A is enabled by U10A when either memory is selected and with gate U6D
applies the DOE Data Out Enable signal to the data bus interface. The low level R/W pulse to U6B inhibits this
gate. The output of gate U6B remains low and forces gates UIOB and U10C to continue holding the R1 R/W
and R2 R/W signals high. The high level R1 R/W and R2 R/W signals instruct the enabled RAM memory block
to perform a memory read operation.
During a memory write operation, the control bus interface applies a low level R/W pulse to gate
U6A and R/W to gate U6B. Gate U6A is now inhibited from generating a DOE signal. The high level R/W
pulse to U6B enables this gate and gates U10B and 10C. Gates U10B and U10C decode their RAM/ROM
switches and determine whether the selected RAM memory block is to perform a memory write operation. If
the RAM/ROM switch to the selected RAM memory block (switch S5 for the RAM I memory block and switch
S6 for the RAM 2 memory block) is in the ROM position, the low level from this switch inhibits its respective
gate from going low. If, on the other hand, the RAM/ROM switch is in the RAM position, the

cp2 pulse is

coupled to U 1OB and U 1OC to generate a low going write pulse. This low level pulse instructs the enabled RAM
memory block to perform a write operation.
The RAM 1 and RAM 2 memory blocks consist of eight 1024 X 1 bit memory chips. The ten address
bits AO through A9 and the output of its RAM select circuit determine when the MPU is addressing this memory
block. The control logic determines whether data is to be written into or read from the selected RAM memory
block.
The data bus interface, consisting of U27 and U28, provides a two-way data transfer of data bits DO
through D7 between the MPU and the 2K Static RAM Memory. These integrated circuits provide TTL
compatible inputs and three-state outputs. When the MPU has selected one of the module's RAM memory
blocks during a memory read operation, the data bus interface receives a high level DOE signal and is enabled
to transfer data from the 2K Static RAM. At all other times, these outputs are in the high impedance state.
The timing diagram of Figure 4-2.5.2-3 shows a Read operation of the memory system design in
Figure 4-2.5.2-2 operating with the MPU's control lines and busses driving the memory board directly. The
waveforms assume a delay of 20 nsec through the driver portion and 18 nsec through the receiver portion of the
MC8T26. The control lines R/W, Address, and VMA are specified to be valid within 300 nsec after the leading
edge of cp1 (TASR, TASC, and TVSC). The delay from the address bus of the MPU to the address inputs of the
MCM6602 is composed of a receiver and a driver portion of a MC8T26 in series. This time totals 20 + 18 = 38

4-64

15
i ----~

~'
R

12:
:

-P~~l;

'L:
"

: 14

36~9~:~~~)o--~~~~!~1~1-----,
~

_":. __

VOC

D~~T 10 ~ ~:N 11,0~2UT 10 ~ ~:N

0~~T ~:, 0: O':N
114

.
4

U12

U13

I [0~~T :,4
14

:3
6

~:N
4

I O'~UT ~:5 ~ ~:N 1

Io1l3

I
14

2'
1

6
7

4
5

.ll3

D'~UT ~~6 :5 ~:N

6
7

OUT

0 IN

U1706

14 16

5 .1...13

I
I

36~12++~~o--I"~>-II-i-:
_'4..,
~
....

______ J

15
r------..,
~ V3~

3 39~~~VX.-~~~~I~IL--------------------------------+--------+-----~H4~~~--++HH~++~--~HH~~~--4+++~4++_--_H~~4++_--_HH+~~H_--_HH4++~H_--_HHH~

2 UU~~7~~~~~~L~5---------------------------------~------_r---__H~~~~~~~---~~~---~~~r____T~~~~~~HT---~~~---~~
V

L~'-'--------------------------~------_;----++H++H~--_HH+~~--_+rH+H~~--rH+H~H_--~~+H~--_+H+rH~r_~+MH+~+_--~+r~

1 V~9~+~~Q--~~~~~14~------------------------------------------t_----------t_----_t~~rr++~----_t+i~~rH~-----hrrt+++~H-----1-rr++++~H-----~HH~~r.+_----~~Yrrr+t+-----++++~Yrr.t_--~~rr+i~~
~
V

T
'4

. - ,!.5 _

~4---'"
"

5 33 ~...;-HV)~o-iT..~~>-I....;...,;.6- . .
M

. . ... . t "

2
3

1.. T"L
"

9 r:J."

roo---

r;=======~;:~

o..u

1..--------""-1:

~~BOW'4

r-;_-_-_-_-_-_-_-'-:~~~

-----,+
pt

r-------=2+'----O0 15

15
2

U2405

0+..:..------------4

V6»<

DIN

5
6

8
4

3
13

U2506

DOUT

7
2

DOUT
12
10

DIN
11

34~...;-~V~~T..~~~-~1,0-~r+~r+·

r u2"7 - - - - - -,

:;p". ..... h3

141

ru; - 1
1
1
121

10
~Q

r-----'
I
I

3571~
:

4: r-t:l

"'"

r--....

~ -0

o
o

-l

1,3

I
/

ADDITIONAL MEMORY
READY CI RCUITAY

,,:

91.c

1'0

... - -- - --..,
15

~U5,....

12 U108 11

- r. ,'I-~-_-_- '- - . . Jr

....
"'-;:t

I
I

CSl

~7 f~

f;9

t~10 t~11 t~12

7:~

2::

:.1 r

L..::: _____ J

FIGURE 4-2.5.2-2 2K x 8 Memory System Schematic Diagram

~:3

~~--~~----~------~..:..---_+_+~}_._:~~29

'5 VOC

~~---.----~--~~--~~--~----~--~~--~-~JL~-~---L----.JL----~--

4-65

"T:

1
I
' ..
1
L-__________________________________________________________________________________~5~1----~~~~J_~1~6_________
~__
-_-~-~--------J----~31

CS2

'-;+__S~_.J_'~-1I:.-M--~--I1l-J
'5 VDC

~4 +~5

~----------------------------________________________~·r:-CN~~-+--~:
L-__________________________________________________________________

L-~::~:~U6)A-3~--------IJrrrl_'~::
V6)D~1~1_________~I----------~

+f~ov +~2 +~3

:,0

~21~--~_K4~XJ~~3--------~I----+_+_----~I~-;;

l~~~~~~~--~~~~~~~--~~--~~

~J,

~--------------------------------~:----~~--_+------~5~:--_+_+~o(r;~:.~~H

"V10D

L-__________________________________________________

~_+_L
..;»-~~~X>-+..;...:..:,

1
1
1
I

I
I

r--t_-----~r_------------------------------------t_----~8~~

L-------------------~~--_+_K)C1~~~------~--~~------~~32

LSB

,.,c

,,:

540
-+
"-------'

-----

T~:3
IL _ _ _ _ _ oJI
:

,..c:-

~--~:~--~~----~:------~~,----+-~~~J-~T:~~30

~~~9~-----O
O~7~--~

PIO Vi

121

~-------------------~yc--------------------~

cf>1

cf>2

0.3 V
~______~~--------------------------------~~----2.4V

R/W

MPU
Address Bus

~~__~J-==------------------------------~~----2.4V

~~~~~~~~~--~------------------------------~~~2.4V
-t------~~~--------------------------------~~~~2.0V

VMA

Memory
Addresses

ffi

60 ns

or CE2

~------TACC--------~

Memory
Output

MPU
Data ------tr----------+------------------~
Bus

Data Not Valid
MPU/2k X 8 Memory Read Cycle
FIGURE 4-2.5.2-3

nsec. At this point in time, the addresses on the memory devices are valid and the access time can begin. The
access time of the MCM6602L-l is 500 nsec maximum, that is, data out of the RAMs during a read cycle is
valid 500 nsec after the addresses are valid. The data encounters an MC8T26 driver delay of 20 nsec before
reaching the MPU data bus. The data set up requirement of the MPU is 100 nsec before the falling edge of cJ>2.
By using the above data, the margin in this system when operating at the maximum MPU clock period of 1000
nsec can be calculated as follows (refer to Figure 4-2.5.2-3):

TASR

25 nsec
300 nsec

MC8T26
TACC

38 nsec
500 nsec

MC8T26

20 nsee

TDSU

100 nsee

TCYCLE

983 nsec

4-67

Since this is 17 nsec less than the minimum MPU clock period of 1000 nsec, this MPU/memory
system configuration has a margin of 17 nsec during a read cycle. The CE signals are. enabled by decoding the
upper address lines, AI0-AI5, in gates U8 and U9. Since the addresses are valid during cf>1, the CE signals
become the inversion of VMA when the correct addresses are decoded. The CE signals will be held low past the
falling edge of cf>2 due to the holding effect of bus capacitance and the delay into the next cP1 for the MPU to set
new addresses.
The write cycle of this system may be analyzed in the same manner using the timing diagram shown
in Figure 4-2.5.2-4. The control signals from the MPU (Addresses, VMA, and R/W) become valid within 300
nsec after the leading. edge of cf> 1. The CE signals are delayed from the address and VMA valid points by a
receiver and driver section of the MC8T26 and the delay of the MC7430 Nand gate. This delay is 18

+ 20 + 22

= 60 nsec. Assuming that the RAM/ROM switch is in the RAM position, the R/W pulse on the memory devices
is cf>2 delayed by a receiver and driver of the MC8T26 plus the delay of U 10 (MC7400). This time is (18 + 20 +
22) also 60 nsec producing a write pulse skewed from cf>2 as shown. The data hold requirement of 100 nsec for
the MC6602 is met by extending Data Bus Enable (DBE) beyond the trailing edge of cf>2 to hold the data on the

1 4 - - - - - - - - - - - -t c y c - - - - - - - - - - - . . I
tjJ1

Vee - 0.3 V

tjJ2

2.0 V

R!W
0.8 V

Address
From MPU

-t----=~~--------~~------------------~-----O.4V

2.0 V
0.8 V

2.0 V
VMA
0.8 V
60 ns

"" 150 ns

CIT or CE2
(750 ns)

R!W

60 ns
TASD

100 ns Min

MPU Data Output

Memory Data Input

2.0 v-J~--------"t--k;::----

-----------~---~~~

N~-----

0.8 V ----'i""'~-------___4~

~------ Teh - - -...........

2.4 V

DBE

Data Not Valid

FIGURE 4-2.5.2-4. MPU/2 k

4-68

8 Memory Write Cycle

bus valid. Memories of this type vary in their data setup requirement (tDW) from 150 ns to 330 ns depending on
manufacturer. The MCM6602L-l as well as the 2102 types have the 330 ns requirement. In order to meet this
requirement the

pulse width required can be calculated as follows (see Figure 4-2.5.2-4):
PW =TASD + 18 ns + t,ow - 60 ns.
PW = 200 + 18 + 330 - 60 = 488 ns.

~2
~2

In many system designs, it may be cost effective to design this memory system with the MCM6602L
which has an access time of 1 /LS. This slower memory can be handled using one of the two methods discussed
in Section 4-2.5.1. The first method is to stretch ~2 every processor cycle to accommodate the slow memory as
detailed in Figures 4-2.5. 1-4 and4-2.5.1-5. The other method is to use the Memory Ready concept. This can be
accomplished as simply as the following: Assume that the clock circuitry used for the MPU is as shown in
Figure 4-2.5.1-9. A low level on the MEMORY READY line will stretch ~2 for that cycle. The time constants
of the UI-B monostable can be adjusted to provide the correct ~2 width during normal operation (470 nsec) and
to provide the correct width (895 nsec for TACC = 1 /Lsec) when the MEMORY READY line is low indicating a
slow memory access. The additional circuitry required in the 2K memory system of Figure 4-2.5.2-2 to
implement MEMORY READY consists of one inverter. The output of UI0A goes high 360 nsec after the
leading edge of ~ 1 if this memory is addressed. The inverse of this signal, called MEMORY READY, controls
the clock circuit of Figure 4-2.5.1-9. These signals are shown in Figure 4-2.5.2-3.

r
MPU 1>1

MPU 1>2

Normal
Cycle
1 }lS

Slow Memory
Access

·1

1.425 }lS

1--

·1
I

l
~

J.--360 ns

U10A Output
Fig. 4-2.5.2-2

Memory Ready

FIGURE 4-2.5.2-5. 2 k X 8 Memory System with Memory Ready

4-2.5.3

8K X 8 Non-Volatile RAM Deisgn Example

Many system designs can be optimized by using the high bit density and low cost/bit offered by
dynamic memories (i.e., those that store information on a capacitor which must periodically be recharged or
refreshed). At this time, the 4K X 1 dynamic RAM is the most cost effective choice for large memory systems
(~4K bytes). Because these memories are dynamic and require refreshing, the system designer must handle the

4-69

dynamic memory slightly differently than static memories. Refer to Section 4-2.5.1 for a discussion of
techniques and clock circuitry used for interfacing the MPU with dynamic memories.
This section describes the design of a 8192 byte Non- Volatile memory system for an MPU based
system using dynamic 4K RAMs and CMOS control logic. This system was designed to be an add-on memory
for the EXORciser, * a System Development Tool in the M6800 Microprocessor family.
MEMORY DEVICE DESCRIPTION
The memory device used in this system is the MCM6605L-1, a 4096 word X 1 bit, dynamic Random
Access Memory (RAM). The dynamic characteristic of this memory device requires that refreshing of the
memory cells be performed at periodic intervals in order to retain the stored data. This device was chosen for the
following features: high bit density per chip and correspondingly low price per bit, standby mode with low
power dissipation, TTL compatability of inputs and outputs, and speed characteristics compatible with
microprocessors and the EXORciser.
Figure 4-2.5.3-1 is a functional block diagram of the MCM6605L-1. The single external Chip
A10A9A8
20 19 18

A7A6 A5
1 7 16 1 5

AOA2A4
1310 9

Chip
{]:<1>1
Enable 6
<1>2
<1>3

rr==;:=====::;:::::;J
Bit
4095

Bit
4064

'"C

...J

.~
...J

QlN

...

-..-1

2o---------L,,--____________

Bit
3071

Bit
3040

...

Row
Decode
And
Bit
Sense
Line
Select

Column Decode
A3

III

.~
...J

QlN

IIIC')

Bit
992

Bit
31

Bit

...

3 0------41

Bit
1023

alN

"'C')

Preset

Column Decode

...J

Bit
2079

Bit
1024

21o--------r~------------~

Bit
1055

Bit
3072

Bit
2016

IIIC')

"'M
c~

Bit
3103

Bit
2047
III

Bit
2048

Data Control Cells

Data In 4 0 - - - - - - + 1
Chip

8O-----------~r_-----_+--------~

Select

5
Read/Write

A 11

V DD = Pin 22
VSS = Pin 12
V BB =Pin1
VCC= Pin 11

FIGURE 4-2.5.3-1. MCM6605 4 k RAM Block Diagram

*Trademark of Motorola, Inc.

4-70

Enable clock starts an internal three phase clock generator which controls data handling and routing on the
memory chip. The lower 5 address lines (Ao to A4) control the decoding of the 32 columns and the upper 7
address lines control the decoding of the 128 rows within the memory chip. The Chip Select (CS) input is used
for memory expansion and controls the I/O buffers: when CS is low the data input and output are connected to
the memory data cells and when CS is high, the data input is disconnected and the data output is in the high
impedance state. Refreshing is required every 2 ms and is accomplished by performing a write cycle with CS
high on all 32 columns selected by Ao through A4. The read/write line controls the generation of the internal cP3
signal which transfers data from the bit sense lines into storage.
All inputs and outputs with the exception of the high level Chip Enable signal are TTL compatible
and the outputs feature 3-state operation to facilitate wired-or operation. The Chip Enable signal has GND and
+ 12V as logic levels. Power requirements are typically 330 mw per device in the active mode from + 12V,
+ 5V, and - 5 volt power supplies and 2.6 mw in standby with refresh from the + 12 V and - 5 volt power
supplies (the + 5V supply powers the output buffers and is not required during standby operation).
Memory timing is outlined in Figure 4-2.5.3-2 and operates as follows for a read cycle (2a). The
Chip Enable line is brought high after the correct addresses are set up, which starts the internal three phase clock
and latches the addresses into an internal register. Chip Select must be brought low in order to connect the data
input and output to the data cells and the Read/Write line must be brought high to inhibit the cP3 cycle which
writes data into the storage cells. A write cycle (2b) occurs in exactly the same manner as a read cycle except
that the R/W line is placed in the Write mode, which gates the input data onto the bit sense lines, and enables a
cP3 cycle to write into the data cells.
A write and a refresh cycle are the same with the exception of Chip Select, which is held high for a
refresh cycle and low for a write cycle.
The Read-Modify-Write cycle is a read followed by a write within the same CE cycle. CS is brought
low shortly after the leading edge of CE and R/W is held high long enough for the Data Out to become valid.
The R/W line can then be strobed low for a minimum write time to enter the Data In (which has been placed on
the input) into the data cells.

-----

By holding the Chip Select high during refresh, the input data is inhibited from modifying the bit
sense lines and the original data is returned to the data cells during cp3 of the cycle. This refreshing action
recharges the storage cells and must be done at least every two milliseconds if the memory is to retain the
information. The fact that the data is stored on a capacitor in a dynamic memory (rather than an "ON"
transistor in a static memory) requires that the capacitor be recharged periodically. This capacitive storage
produces a low power standby mode of operation where only refreshing takes place, which is the foundation of
this low current drain non-volatile memory design. The memory device typically dissipates 330 mw in the
active mode but only 2.6 mw in the standby mode (refreshing only).
MEMORY SYSTEM DESIGN REQUIREMENTS
This memory system was designed with the following major design goals:
First, non-volatility for a period of time in the range of 7 to 10 days from a reasonable sized battery.
It is also desirable for the system to operate from one battery voltage during the standby mode to simplify the

battery requirements. Second, the memory size was desired to be 8K bytes on a PC card easily expandable
upward and addressable in 4K byte blocks. Third, the memory system must be able to interface with the
MC6800 microprocessor which has a basic cycle time of llLsec. Fourth, the memory system controller must
handle all refresh requirements in a manner as invisible as possible to microprocessor operation.
4-71

Stable Address

Address
1.2 V--VIL

VCEH -----+-~------'""\
VDD-2.0V---Chip Enable

Timing Shown for MCM6605L-1.

~~~

- Don't Care

FIGURE 4-2.5.3-2a. Read Cycle Timing (Minimum Cycle)

>------tcyc(w) = 470 ns min _ _ _ _~

r---+-------

t -.
o I.
!

I Stable

Address

Timing Shown for MCM6605L-1.

- Don't Care

FIGURE 4-2.5.3-2b. Write and Refresh Cycle Timing (Minimum Cycle)

4-72

Address

Stable Address

1.2 VVIL

V
0 ns min~
CEH
VDD-2.0 V - - - ..l_ -

1--60 ns min

~------------------------"

/ . . , . . . - - - - - 4 3 o ns
Chip Enable

min----~

2.0 V - - VCEL
V IH

Chip Select
VIL

.,................-.-"r""'!'"I'-T--.-~-IT--\.

o ns min --+O>--~I4_'*_O ns min

~~~I~~~~~------------------~~--~..~~~~

Read/Write

V I H -r'I"""'r"I~~~~~rr""~

Data In
V IL

~. . . . . , II. . . . . -"-lo.~. . .lI. ,;"lo-" "';" " --l:--______________
.............

1-=280 ns max

+_ _ _ _ _ _ _ _ _

2.0V--=---3- =+Data Out
F I~ating
- - - - - V a l i d - - - I 4 - - - Floating 0.8V-i---- VOL - - - F t : ; : 3 0 0 ns m a x - - - - l - - - - - - - - - - - - - - - -

ES\\ \\i -

Don't Care

Timing shown for MCM6605L-1.

FIGURE 4-2.5.3-2c. Read-Modify-Write Timing (Minimum Cycle)

MEMORY SYSTEM DESCRIPTION
A block diagram of the memory system is shown in Figure 4-2.5.3-3. This system can be split into
three main sections as follows. The first section is comprised of the address buffers, Read/Write and Chip
Select decoding logic. The second section consists of the data bus buffering and the memory array. The
memory array consists of sixteen memory devices (4K words X 1 bit) organized into two rows of 4096 bytes
each. The third section consists of the refresh and control logic for the memory system. This logic provides the
timing of the refresh handshaking, request for refresh, generation of the refresh addresses, synchronization of
the POWERF AIL signal, multiplexing of the external MEMORY CLOCK with the internal clock (used during
standby), and generation of the - 5 volt supply on the board by a charge pump method.
Figure 4-2.5.3-4 is a worst case timing diagram of the read and write cycles of the EXORciser and
the 4K memory system. The timing is composed of two phases. During phase 1 (cpl) addresses are setup and
during phase 2 (cp2) data is transferred. Figure 4~2.5.3-5 is a timing diagram of the memory system in standby
showing refresh cycles only. This timing analysis will be referred to in the following discussions of the memory
control circuitry.

ADDRESS BUFFERS AND DECODING
Figure 4-2.5.3-6 is a schematic of the address buffers, decoding logic, and refresh address
mUltiplexer. Addres.S and data lines from the EXORciser are buffered from the capacitance of the memory array
in order to provide a small load to the bus. Since the addresses are valid on the EX ORciser bus 300 nsec into cp 1,
200 nsec is available to setup the address on the memories. The worst case input capacitance on the address

4-73

r--------------------------------.
Address Buffers and Decoding Logic

Refresh and Power Fail Logic

BAO

A4
Refresh Addresses
AO
Address
Buffers

Refresh Addresses
,6.5

CSA
BA15

CSB

!II

::l

!Xl

...

III

R/W

0
X

VMA

'(3
II:

R/WA

To
Memory
Array

CEA

CEB

Memory Clock

r----------------- __ L

___________

I
DO

...

DoutO

...

Dout7

Data
Transceivers

DinO

I
:

Refresh
Grant

R/WB

Buffers

Memory
Clock

I
I

Refresh
Request

CMOS
Refresh/Power Fail
Logic

A11

L ______________

Din7
~~~~~~~~~

I
8K x 8 Memory Array
16 MCM6605L-1
2 Rows x 8 Columns

__________

I
I
I
~

FIGURE 4-2.5.3-3. Non-Volatile Memory System Block Diagram

lines of the MCM6605 is 5 pf/input. A system of 16 memory devices (SK bytes) presents a total capacitive load
on the address lines of only 100 pf (20 pf stray capacitance). Since 200 nsec is available to set up the addresses
on the memory devices, no high current buffers are required to drive the memories. For address lines A5
through All the output of the MCST26 address receiver drives the address lines directly. AO through A4 must
be multiplexed with the refresh addresses so that all 32 columns will be refreshed every 2 msec. Because of the
requirement of low current drain in the standby mode, an MMSOC97* CMOS buffer with a 3-state output is
used to meet the multiplexing requirement. The buffers have sufficient current drive capability to drive the
address line's capacitance within 100 nsec. An open collector TTL gate (MC7406) is used to translate to + 12
volt CMOS levels. AO through A4 are driven with GND and 12 volt logic levels so that + 5 volts is not required
in the standby mode.
The high order address lines (A12-A15) are used to decode one 4K block of memory out of the 16
total possible blocks in the 65K address map. The addresses and their complements are routed through
hexidecimal switches to MC7430 Nand gates in order to create a CS signal for each 4K bytes of memory. By
rotating the hexidecimal switches (S3 and S4), all combinations of true and complement addresses can be
routed to the Nand gates, thereby selecting one of the sixteen 4K blocks. VMA and REFA are also inputs to
these Nand gates VMA is a Valid Memory Address signal on the bus indicating that the address lines are valid
and REFA is a control signal indicating that a refresh cycle is taking place. During a refresh cycle REFA goes

low forcing CSA and CSB high (a refresh cycle for the memory devices is a write cycle with the Chip Select
*To be introduced as MC14503, third quarter 1975

4-74

Time (ns)

4>1

400

200

1000

800

600

1200

----~------+-------~/

Memory Clock \ .
(4)2)

I
1~.r------300ns+-----

EXORciser Address /"X
andVMABus
)()

__~

---

~lX~~

100ns__
Memory Address Bus

~ XXXXXXXX xxx~r

t:::.

120 ns......
Memory Chip Select

t:i?>--:~~~

MC7430

id?+
L" :

~--------IU-

~>--+:--+--,,3N\_3

~t-I-'

r L:,::'
1/6MC7407

I
I
I

f- -

I
~

I
I

BA14

BA15

Bat

Write Inhibit A

'--------------t--"'~ CA

'-------r----~,=--

12 k

5
1/2_MC7420

~Lt>>---~:-----.---++---~t

1 k

I-I--i

~ :
-

1/6-MC7407

12k

~-I~~~-'V
S2n\

1
~

5~ pF

.....--I"II-_Jo"'.1"'1--o 5

3.3k

1 k

/2_MC7420

r t- H
~

;

1/4~~~7~08 1~ti?t

.....
---1-...,
T1
T2

1~
i.~

AMP 53137-1

1/6-MC74:7

•

12 V

~ 4>>---~:-----,

MC14503

~ II.--::r ;
t 4~>--+i----*",~R'WA

-0

R/W

ROM
51

~
~i -1

L.:...;"-------t-o
BA13

_....l

-MC8T26 - - ,

I
BA12

k--o 12 V

>--1--+---. GS B

r- ----.. . . . . ---1
I

GSA

",V

3.3 k

ROM

Write

Inhibit B1/4_MC7408

>---'-___- ....~R/WB

I
1

LL1

3.3 k

6
+
_- I
J

Bat

IrLr ~;4-MC7400

Write Inhibit Pulse

FIGURE 4-2.5.3-6. Address Buffers and Decoding Logic
(continued from preceding page)

4-77

held high). The output of the MC7430 is translated to 12 volt CMOS levels with the open collector gates and
buffered with the MM80C97 3-state buffer. The capacitive loading on each set of 3 paralleled drivers is 60 pf
allowing Chip Select to be decoded and valid 120 nsec after addresses are valid on the data bus. During the
standby mode (BAT = "I") the CMOS buffer is disabled allowing the 3.3K ohm resistors to pull CSA and
CSB high for continuous refreshing.
The Read/Write signal is received by an MC8T26 and then decoded in the following manner. A
write inhibit feature is provided using switches S 1 and S2 for each 4K byte block of memory so that in a ROM
simultation application, the memory can be protected from inadvertant writes due to programming or operator
errors. The Ready-Modify-Write cycle of the MCM6605 is used in this application because it requires a shorter
data valid time (TData Stable) than a normal write cycle (See Figure 4-2.5.3-2b and 4-2.5.3-2c). This feature is
desirable because the EXORciser places valid data on the bus for the last 300 nsec of a Write cycle. In order to
delay the write pulse to the memory array until the data is valid on the Data Inputs of the memory array, ~ write
inhibit pulse is combined with the EXORciser's R!W signal in the MC7420 Nand gates. This write inhibit pulse
is generated by the MC8602 monstable multivibrator triggered from the leading edge of the memory clock
(MEM CLOCK) bus signal. The effect of this added delay can be seen from Figure 4-2.5 .3-4 when comparing
the memory array's R/W line for a read and a write cycle. Note that for a write cycle, the R!W of the memory
array is inhibited from dropping to the Write mode until memory input data is valid.
The refresh control signal (REFA) is combined with the output of the MC7420 in a MC7408 AND
gate in order to force a write signal on the memory array's R/W lines while in a refresh cycle. Translation and
buffering is accomplished in a similar manner to that for the Chip Select signals. When in the standby mode
(BAT = "1") the MM80C97 buffers are disabled allowing the 3.3K resistor to establish a zero level on the
R/W line of the memory array for continuous refreshing.
DATA BUFFERS AND MEMORY ARRAY
The EXORciser data bus is bidirectional while the MCM6605 memory has separate data inputs and
outputs. The MC8T26* data bus receiver/driver buffers the capacitance of the memory array (very low, about
30 pf per data line) and combines the Data Input and Data Output of the memory array into one bidirectional bus
as shown in Figure 4-2.5.3-7. The Data Out of the memory devices is inverted from the Data In requiring an
extra inverter (MC7404) in the data path when working with a non-inverting bus (Le., the data is returned to the
bus in the same sense it was received).
During a memory write cycle, the data is valid on the data bus 200 nsec (T ASD) after the leading edge
of cP2. With a 50 nsec delay through the bus translators, the data setup requirement of the memories (210 nsec)
is easily met (See Figure 4-2.5.3-4). A memory read cycle requires a data setup time on the data bus of 120
nsec. The access time of the memory from the leading edge of the CE signal plus the bus transceiver delay of
305 nsec is compatible with this setup time.
REFRESH AND CONTROL LOGIC
The refresh control logic shown in Figure 4-2.5.3-8 handles the refreshing of the memory during
both operating and standby modes. The timing is shown in Figure 4-2.5.3-9.
The refresh timing is controlled by an astable multivibrator constructed with a MC3302 comparator.
This device was chosen for its low current consumption (1.5 ma max) and single supply voltage operation, both
*To be' introduced third quarter 1975

4-78

----i
Ir - MC8T26
I

5V
DinO

DoutO

5V
0.1

Din1

D out 1
5V
02

Din2

D out 2
5V
Din3

03
1/6-MC7404

Dout3
1

EXORciser Bus
:- -

MC8T26--1

Din4
1/6-MC7404
Dout4

I
05 )

06 )

07 )

10 k

res

:
:

~5V

Din5

1/6-MC7404

Dout5

10k

~
~

[> C--0

1/6-MC7404

Din6

Dout6

10k

~5V

[> -

:D;n7

1/6-MC7404

L _____ --.JI

FIGURE 4-2.5.3-7. Data Buffers and Memory Array (Sheet 1 of 2)

4-79

Dout7

R/W A

CSA

AO ... All

CEA

DinO

AO ... All

Din1

AO ... All

Din2

AO ... All

Din3

AO ... All

Din4

AO ... All

Din5

AO ... All

Din6

AO ... All

Din1

AO ... All

Din2

AO ... All

Din3

AO ... All

Din4

AO ... All

Din5

AO . . All

Din6

AO ... All

Din7

00
o

R/WS

AO ... All

CSs

CEs

DinO

FIGURE 4-2.5.3-7: Data Buffers and Memory Array
(Sheet 2 of 2)

Din7

important for battery operation. The refresh requirement of 32 refresh cycles every 2msec is handled by
stealing cycles from the processor. This cycle stealing results in a 1.6% slower program execution rate than the
basic microprocessor clock frequency. During the refresh cycle, the clocks to the microprocessor are
"stretched" during the cf>1 high and the cf>2 low times by 1 /Lsec as shown in Figure 4-2.5.3-9. During this 1
/Lsec period, the memory executes a refresh cycle. In order to minimize the effects of memory refresh on
microprocessor program execution the 32 refresh cycles are distributed over the 2 msec period, one occuring
every 62.5 /Lsec. Refresh could be done in a burst of 32 cycles every 2 msec but this would cause a larger gap in
program execution which in this case was undesirable.
The MC3302 produces the 62.5 /Lsec signal to time the refresh requirement and also is used in the
generation of the - 5 VDC supply required by the MCM6605 memory. Since these functions are required in the
standby mode, which is powered by the battery, a CMOS buffer is used in a charge pump circuit to minimize
current drain from the battery. This charge pump creates -5 VDC at 3 rna from the + 12 volt battery to satisfy
the bias requirements of the memory devices.
The REFRESH CLOCK is used to increment the address counter (MC14024) and to clock the
refresh handshaking logic (MC14027). REFRESH REQUEST goes low on the leading edge of the REFRESH
12 V
100pF

221 k 1%
1!6MC14049

22 k

12 \

0.022 J.lF

100 k
1%

/ AO

01
47.5 k 1%
______---.JVV\r--~-a C

A 1

02 03 04
M C 14024

Refresh
Clock

100 k
1%

lN4~48

Refresh Addresses

__----A------...

12 V

lN4148

I~
100/lF
10V

1
'T:
L

-=-

A4 "
05

-5.1 V to
0
V ••
MZ4625

0 1----1 J

C 1 12·MC 14027-

C 1/2-MC 14027

Ref

1/2.MC14049

0 1-----4I~__l

12 V

-=1/6-MC7406

3.3 k

Refresh Grant

1/6-MC14049 1/6-MC7404

Bat _ _ _ _ _ _ _ _ _ _ _

FIGUR E 4-2.5.3-8. Refresh Control Logic

EXORciser Bus cj>1

EXORciser Bus cj>2
Occurs Every 64 /Jos
Refresh Req uest

--------~~~~~~~~~~~I~--------------

Refresh Grant

Memory Clock

tz2ZZ2l

Don't Care

FIGURE 4-2.5.3-9. Refresh Timing

4-81

CLOCK thus requesting a refresh cycle. Logic in the clock generation circuitry stretches the high portion of cf> 1
and the low portion of cf>2 while sending back a REFRESH GRANT signal. This stretching of the cf> 1 signal
delays program execution during this cycle. The leading edge of REFRESH GRANT starts the refresh cycle
and cancels REFRESH REQUEST. The trailing edge of REFRESH GRANT returns the refresh logic to the
normal state and the memory is ready for a memory access. The trailing edge of the REFRESH CLOCK then
increments the refresh counter in preparation for the next refresh cycle.
Decoding of the memory clock (CEA and CEB) and the circuitry to synchronize the POWERFAIL
signal is shown in Figure 4-2.5.3-10 with the timing given in Figure 4-2.5.3-11.
The memory device clock (CEA and CEB) during standby is generated by a monostable multivibrator (MCI4528) and buffered from the memory array by three MM80C97 buffers in parallel. This clock is
multiplexed with the MEMORY CLOCK by use of the 3-state feature of the MM80C97. The MEMORY
CLOCK (used during normal operation) is translated to 12 volt levels by use a MC3460 clock driver. *
Decoding of the CE signals (Le., only clocking the memory bank addressed) to conserve power is
accomplished by internal logic within the MC3460.
Since the POWERFAIL signal will occur asynchronously with both the MEM CLOCK and the
refreshing operation (REF CLOCK), it is necessary to synchronize the POWERFAIL signal to the rest of the
system in order to avoid aborting a memory access cycle or a refresh cycle. An MC14027 dual flip flop is used
as the basic synchronization device. The leading edge of the REFRESH CLOCK triggers a 3 JLsec monostable
multivibrator which is used as a refresh pretrigger. The trailing edge of this pretrigger triggers a 500 nsec
monostable which creates the CE pulse during standby operation. The 3 JLsec pretrigger signal is used to direct
set half of the MC14027 flip-flop, the output of which then inhibits a change over from the standby to the
operating modes (or vice versa). This logic prevents the system from aborting a refresh cycle should the
POWERFAIL signal change states just prior to or during a refresh cycle. The trailing edge of the 500 nsec
monostable clears the MC14027 flip-flop enabling the second flip-flop in the package. The state of
POWERFAIL and POWERFAIL is applied to the K and J inputs, respectively, of this second flip-flop and is
synchronized by clocking with MEM CLOCK.
The outputs of this flip-flop, labeled BAT and BAT, lock the system into the refresh mode and
mUltiplexes in the internal clock for standby operation when BAT = "1".
SYSTEM PERFORMANCE
Figure 4-2.5.3-12 is a photograph of the breadboard of this dynamic memory system. This
breadboard was interfaced with an EXORciser system and tested using a comprehensive memory test program
written in-house.
Figure 4-2.5.3-13 is a photograph of waveshapes associated with alternate reads and writes in one
4K bank of the memory system. Included also is the simple MC6800 program used to generate these
waveforms. This type of operation produces repetitive signals on the memory board in order to aid
troubleshooting. Note the refresh cycle sandwiched in amongst the read and write cycles and that the decoding
of the CE signals produces no clocks on CEA (accesses are to bank B), except during refresh.
Figure 4-2.5.3-14 shows the printed circuit memory array used to interconnect the memories. The
addresses are bused between the 4K memory chips in the horizontal direction. Data lines are bused in the
vertical direction. The MCM6605 4K RAM has power and ground pins on the corners of the package allowing
*To be introduced first quarter 1975

4-82

~--~--~~--012V

5.11 k

520 pF

1%
T2

r---~--~~---o12V

T2
Q~---------------------e

Refresh Clock

1I2-MC14528

112 MC14528
500 ns

).lS

12 V

s
Bat

1/3-MC 14049

MC14503

r------.
I
I

5.11 k

82 pF

1/2-MC14027

1/2·MC14027

X~--=--1C

C
CEB

1/4-MC14001
12 V

Q~---+-------"'-

+12

1k
Memory Clock

12 V

1/6-MC7407
1/4-MC3302

22 k

12 V
100 k

1/4·MC3302

22 k

12 k

IVIC3460

---------------------------1 AS E L
A

---------------------1 REF

SEL

-----------------------1 BSEL
BI-----I

+ 5 V ___--'-_ _...J

FIGURE 4-2.5.3-10. Power Fail Logic and Chip Enable Driver

4-83

o
Refresh Clock
(64 J..Ls Period)
3 J..Ls Monostable
(Refresh Pretrigger)

1.0 J..Ls

2.0 J..Ls

3.0J..Ls

4.0J..Ls

J
~----------.

\~------

----i!\\-____

500 ns Monostable - - -_ _ _ _ _ _ _ _ _

CE A or CE B
r--\.
(Standby)
_ _ _ _ _ _ _ _ _ _ _ _ _--',

Clock Input
Inhibit

®
®--.I

_ __

'--I
\'---Power Fail signal changes will not
be recognized during this time.

FIGURE 4-2.5.3-11. Power Up/Down Synchronization

FIGURE 4.2.5.3-12. Memory System Breadboard

wide, low impedance power and ground interconnects within the memory array. Decoupling capacitors were
used as follows within the memory array: + 12 volt - one 0.1 p.J ceramic per package, +5 volt - one 0.01 J-Lf
ceramic for every three packages, and -5 volt - one 0.01 J-Lf ceramic for every three packages. Figure

4-2.5.3-15 is a photograph showing the ripple on the power supplies in the memory array caused by accesses to
one 4K byte bank of memory as shwon in the photograph. The + 12 volt line supplies the most current to the
array and is the one on which the most care in decoupling (wide PC lines and distributed capacitance) should be
taken. Placement of the Vnn pin on the corner of the package gives the designer the option to do this easily.
The dc power dissipation of this memory system is shown in Table 4-2.5.3-1. Of these current
drains, the most critical to non-volatile operation is the current requirement in the Standby mode where the
current would probably be supplied from a battery. A breakdown of the typical current required from + 12 volts
to maintain the memory in the Standby mode is shown in Table 4-2.5.3-2.
By using CMOS for the refresh logic and capacitance drivers, a dynamic memory, and alow current
refresh oscillator; the standby current has been reduced to a level that can be supplied easily by a battery. Table
3 is a brief list of various capacity 12 volt batteries that could be used to power a system of this type in the
Standby mode. Support time runs from one-half to 35 days and can be made as long as desired if sufficient
battery capacity is available.
4-84

"0
(0
Q)

-5i
Q)

co;:
Q)

a: a:

co
Q)

CE B
CS B

;;
0
....

R/W B

5 J.Ls/Oiv

M6800 Program to Generate Waveforms Shown
Mnemonic

Comment

Address

Data

0000
0001

B6
55

LOA #$55

Load data to be written (55)

0002
0003
0004

B7
30
00

STA A $3000

Store data in address 300016

0005
0006
0007

F6
30
00

LOA B $3000

Read data from address 300016

0008
0009
OOOA

7E
00
02

JMP $0002

Loop back

FIGURE 4.2.5.3-13. Alternate Read and Write Memory Accesses

TABLE 4.2.5.3-1 8K x 8 Non-Volatile Memory System Power
Requirements (l-MHz EXORciser Clock Rate)

Current
Mode

Typical
100 mA

Maximum
300mA

+5 V

600mA

860mA

+12 V

14 mA

20mA

Power Supply*
+12 V**

Operating

Standby
No +5 V Supply required

+5 V

*5 V supply is not listed because it is generated on the board
from +12 V
**8ecause memory is dynamic, the +12 V current requirement
is dependent on rate of memory access.

4-85

4K x 8
Bank A

+5'0:::v?illllllllllllii~~:

Gnd : : ' .

+12 V\
Gnd

~Gnd~

eE30

1
vss

A30

OAI
OA10
OA9
OA8
OA7
OA6
OAS
ORlW

All 0
elKO

eE40
A40
A20

OAO

vee

0001

Data o u t /

•
VOO

0001

1
VSS 0001

DO 01

1
DO 01

0001

-/ \
Data Out

' D a t a In

Bit 0

Bit 7

FIGURE 4-2.5.3-14. Memory PC Board Array

4-86

vee
Data In

4K x 8
Bank B

Circuit Section

Typical Current

+12 V Current (VDD)
Charge Pump
Comparator
Capacitance Drivers
Total

5mA
3mA
2mA
4mA
14mA

TABLE 4.2.5.3-2 Standby Mode Current Allocation

Battery

-20

Globe GC 12200
4.5
Globe GC 1245-1
1.5
Globe GC 1215-1
0.6
Burgess MP 202
Burgess 12.0V 225 Bh 0.225

Size
(LxWxH)

Weight

Support Time*

6.9" x 6.5" x 4.9"
6" x 2.5" x 4"
7" x 1.3" x 2.6"
3.4" x 1.4" x 2.3"
3.5" H x 1" Diam.

16.75Ibs.
4.51 Ibs.
1.51 Ibs.
11.6 oz.
4.65 oz.

35 days (850 hrs)
8 days (192 hrs)
2.6 days (63.75 hrs)
1.25 days (30 hrs)
.47 days (11.25 hrs)

* Assumes 20 ma average current drain (14 ma for memory and 6 ma for powerfail detection
circuitry) and a battery voltage range during discharge of from 13 to 11 volts.

TABLE 4-2.5.3-3. Battery Characteristics

10V/Oiv

CEB

+12 V Power Line

1 V/Oiv

+5 V Power Line

1 V/Oiv

-5 V Power Line

1V/Oiv

5 ILs/Oiv

FIGURE 4.2.5.3-15 Power Line Ripple

4-87

4-2.5.4

Design Considerations When Using Non-Family Memories with the MC6800

The previous sections have discussed general interfacing with slow and dynamic memories and two
design examples using the MCM6602 lK X 1 static RAM and the MCM6605 4K X 1 dynamic RAM.In this
section, the general interface characteristics of the M6800 family will be discussed as well as methods for
interfacing with various classes of memory devices. The categories of memories to be discussed are the
following: Bipolar PROMS!ROMS, MOS PROMS!ROMS, Bipolar RAMS, and MOS RAMS.
Table 4-2.5.4-1 lists the relevant characteristics of the M6800 family parts to be considered when
interfacing with each other or with non-family parts. In most small systems, the limiting factor will be the data
bus load exceeding 130 pf maximum capacitance and/or 1 TTL (7400) load. Depending on the mix of
PIA/ACIA and memories, the fanout can be 7 to 10 family parts before buffering is required.
BIPOLAR PROMS !ROMS
The PROMS available in bipolar technology are constructed with nichrome or poly silicon links
which can be "blown" or programmed in the field to provide a custom program for small quantity, quick turn
around, requirements. In many cases, a pin for pin equivalent is available in a mask programmable ROM for
large quantity usages of a known bit pattern. Common memory organizations available are 64 X 8, 256 X 4,
512 X 4, and 512 X 8 from several manufacturers. Because these devices are constructed in bipolar TTL
technology, their speed is much greater than required by the MPU. A typical device of this type will have a
IDATA*
(3 st)

I DATA (drive)

DEVICE

CIN

COUT

liN

MC6800 MPU

10 pf logic
15 pf data

12 pf logic
15 pf data

2.5Ma

10Ma

-100Ma +130 f
1.6 ma
p

MCM6810 RAM
7.5 pf
(128 X 8)

15 pf

2.5Ma

10Ma

-1 OOMa + 130 f
1.6 ma
p

MCM6605 RAM
MCM6815 RAM
(4K X 1)
5 pf

5 pf

10Ma

-100Ma + 50 f
2 ma
p

10 pf

2.5Ma

10Ma

-100Ma +130 f
1.6 ma
p

MCM6830 ROM
(1 K X 8)
7.5 pf

15 pf

2.5Ma

10Ma

-100Ma +130 f
1.6 ma
p

MCM6832 ROM
(2K X 8)
8 pf

10 pf

10Ma

-40Ma +30 f
1.6 ma
p

10 pf

2.5Ma

10Ma

-1 OOMa + 130 f
1.6 rna
p

MC6820 PIA

MC6850 ACIA

7 pf logic
10 pf data

*Current leakage on data bus in high impedance state is into the device.
TABLE 4-2.5.4-1. MPU Family Interface Chart

4-88

maximum access time of 70 nsec from address valid while the MPU only requires 575 nsec access time when
operating at full speed. Because of their programmability, these types of devices find use in system prototypes,
bootstrap loaders, and system debug packages. Devices of these types are the MCM5003 PROM and its mask
programmable equivalent, the MCM4003.
Interfacing with these devices requires buffers for the MPU because each bipolar PROM/ROM is
one unit TTL load. Since the MPU has TTL levels on all inputs and outputs, no level translation is necessary.
Timing interface between the MPU operating at full speed and these TTL memories can be accomplished easily
because the TTL memories are much faster.
MOSPROMS/ROMS
The mask programmable MOS ROMS are both P-channel and N-channel with the newer faster
devices being N-channel. Memory organizations commonly available at lK X 8 and 2K X 8. Most of these
ROMS require multiple power supplies with +12V, +5V, -3V, or +5V, -12V, being common. Current
requirements on the non - 3 V supply voltages are in many cases low so that charge pump techniques can be
used. The majority of these devices are TTL compatible on the inputs and outputs making MPU interfacing
easy. Because of the MOS technology, these devices all present light loads on their inputs usually 10 /La leakage
and 5-10 pf shunt capacitance and, therefore, can be interfaced without buffering up to 130 pf + 1 TTL load.
Those parts with an access time of longer than 575 nsec will require usage of the slow memory techniques
described in Section 4-2. 5.1 in order to operate with an MPU at a 1 MHz clock rate. These devices vary in speed
from 350 nsec to 1800 nsec depending on manufacturer and process type. Devices of this type are the
MCM6830 and the MCM6832.
The PROMS available in MOS technology are electrically programmable and erasable by exposure
to ultraviolet light. Device organizations available are 256 X 8 with 512 X 8 under development. Inputs and
outputs are TTL compatible with the use of pull up resistors on the inputs and access times range from 500 nsec
to 2.5 /Lsec. Input loading is on the order of 1-5 /La and 15 pf. A MPU system operating at full speed may require
the slow memory techniques described in Section 4-2.5.1 to operate with the devices.
DYNAMIC MOS RAMS
These devices are available in P-channel in a 1K X 1 organization with the newer devices being
N-channel and 4K X 1 organization. Their dynamic characteristics require that periodic refreshing of the
memory take place. The number of refresh cycles varies from 16 to 64 every 1 or 2 ms. Several ways to handle
this refresh requirement in the MPU system were described in Section 4-2.5. 1. The access time of these devices
is usually less than 500 nsec resulting in easy timing interface with the MPU at full speed. Inputs and outputs of
most of these devices are TTL compatible with input loading being typically 10 /La leakage and 5 pf shunt
capacitance. These devices typically require a clock signal which can be derived from the cp2 MPU clock
signal. A design of a memory system for the MPU using dynamic memories is detailed in Section 4-2.5.3.
Devices of this type are the MCM6605 and the MCM6815.

4-89

STATIC MOS RAMS
Static RAMS do not require refreshing and as such are simple to interface into a MPU system. In
N-channel MOS technology, the common organizations are 128 X 8, 256 X 4, and 1024 X 1. The inputs and
outputs are TTL level compatible with the input loading on the order of 10 /La and 5-10 pf Output drive
capability typically is one TTL gate and 100 pf shunt capacitance. These devices operate from a single 5 volt
power supply with access times between 200 and 1000 nsec.
Example of this type of device are the MCM681 0 and the MCM6602. A design of a static memory
design for the MPU using the MCM6602 is detailed in Section 4-2.5.2

4-90

CHAPTER 5
5.

PERIPHERAL CONTROL TECHNIQUES

The MC6800's general I/O handling capability is described in detail in Chapter 3 of this manual.
This Chapter further demonstrates the I/O characteristics of the M6800 system by applying them to a variety of
specific peripheral control problems. The emphasis here is on control of the peripherals; system integration
procedures are described in Chapter 6.
The development of both hardware and software is described for representative peripherals in the
following categories:
(1) Input devices such as keyboards and label scanning wands;
(2) Output devices such as visual displays and hard-copy printers;
(3) Data interchange devices such as teletype terminals, tape cassettes, and floppy disks. Where
appropriate, the possible hardware/software trade-offs and their effect on system efficiency and
cost are discussed. However, the main objective was to minimize the external conventional
circuit requirements by using the MC6820 PIA and the MC6850 ACIA family interface
devices. The PIA and ACIA are described in detail in Sections 3-4.1 and3-4.2, respectively, of
Chapter 3.
5-1

DATA INPUT DEVICES

5-1.1

KEYBOARDS FOR MANUAL ENTRY OF DATA

Keyboards represent particularly good examples of the hardware/software tradeoffs that should be
considered when configuring a system. They can be obtained from original equipment manufacturing (OEM)
sources with widely varying amounts of electronics provided.
At one extreme is the fully decoded l keyboard complete with multiple key rolloverprotection 2 and a
strobe signal for indicating that data is available. Use of these units with an MPU results in the simplest
interface and also requires a minimum control program.
At the opposite extreme is the keyboard with no electronics at all; only the terminals of the individual
key switches are provided. With this type, the designer may choose to add a full complement of external
electronics, do a partial decode, or let the MPU perform the complete task in software.
Representative examples of each approach are described in the following paragraphs. In each case,
the MC6820, Peripheral Interface Adapter (PIA), is used for interfacing to the MC6820 Microprocessor.
5-1. 1.1

Decoded Keyboard for a POS Terminal

A MICROS WITCH 26SW3-1 POS Keyboard was selected for use with the Transaction Terminal
described in Chapter 6. A schematic representation of the key configuration is shown in Figure 5-1. 1. 1-1. The
function keys CODE ENTRY, SUBTOTAL (+), SUBTOTAL (-), and CLEAR each provide a logic level out
when depressed. The remaining keys are decoded, that is, closure generates a 6-bitcode word accompanied by
1

Each switch closure is converted to a unique code word.

2The first of near-simultaneous closures is selected.

5-1

Gmwy

Code Entry

Tax

[J D D
[] [] [J
[J [] 8
I

I SUb~tal I

0
EJ
Tol

B
B

FIGURE 5.1.1.1-1 POS Keyboard Configuration

Key Function

Key Number

0
1
2
3
4
5
6
7
8

43
13
14
15
23
24
25
33
34
35
45

9
. (Demical pt.)

Code to PIA
b5
0
0
0
0
0
0
0
0
0
0
0

b4
0
0
0
0
0
0
0
0
0
0
0

b3
0
0
0
0
0
0
0
0
1

0
0

b6
0
0
0
0
0
0
0
0
0
0
0

b2
0
0
0
0
1
1
1
1
0
0
0

b1
0
0
1
1
0
0
1
1
0
0
1

bO
0
1
0
1
0
1
0
1
0
1
0

0
0
0
0
0

0
0
0
1
1

0
1
1
0
0

1
0
1
0
1

0
0
1
0
1
0

0
1
1
1
·1
1

0
1
1
0

b7
0
0
0
0
0
0
0
0

Grocery
Dairy
Meat/Coupon
Produce/Bottles
Hshld/Stamps

1
11
21
31
41

0
0
0
0
0

Weight
.No Tax
Quantity
Total
Cash
Check

3
7
17
20
30
40

0
0
0
0
0
0

0
0
0
0
0
1

Code Entry
Subtotal (-)
Subtotal. (+)
Clear

5
10
37
50

0
1
1

1
0
1

Will. be holding
data from
previous entry
[C2 interrupt]
1
1
0
0
[C1 interrupt]

,".\

Strobe

1. Strobe .wiU be high while any key is closed
FIGURE 5.1.1.1-2 Keyboard Coding/PIA Interface

5-2

0
0
1
1
0

1
1

a strobe pulse. The code generated by the keyboard is shown in Figures 5-1.1.1-2. That Figure also shows the
interconnection to an MC6820 PIA as represented schematically in Figure 5-1.1.1-3.
For system purposes, it was decided that any key closure should cause an interrupt via the PIA's CAl
Input. The interrupt was generated by using a Quad Exclusive OR gate package to combine the four function
key outputs and the STROBE signal. The CLEAR signal was also required as a separate interrupt and is, hence,
applied to the CA2 Interrupt Input. The remaining three function outputs, CODE ENTRY, SUBTOTAL ( +),
and SUBTOTAL (-), were decoded by using two 2-input NAND gates applied to PA6 and PA7 of the PIA.
Operation of the system executive program described in Chapter 6 is largely determined by data that
is input through this keyboard. However, the control program for the actual capture of the data is relatively
simple. When the MPU is ready to accept manually entered data, it polls the keyboard PIA interrupt flag bits
until an input is detected. A Flowchart and an Assembly Listing of the relevant portion of the executive
program3 are shown in Figures 5-1.1.1-4 and 5-1.1.1-5, respectively.
After recognizing an interrupt, the MPU checks for a keyboard closure by testing flag bits 6 and 7 of
the keyboard PIA's Control Register. These bits would have been set by transitions on CA.1 or CA2. If neither is
set, the MPU branches to check for a Wand interrupt service request. If one is set, the MPU tests for a CLEAR
closure (bit 6) and, if it is present, branches to the CLEAR service routine. If the CLEAR flag is not set, the
MPU assumes bit 7 was set and proceeds with the keyboard service routine.
This sequence is typical for encoded keyboards. Aside from the interrupt service housekeeping,
capturing the data consists of nothing more than the MPU "reading" a PIA Data Register as it would any other
memory location.
3See Section 6-4.2.4 of Chapter 6 for the relationship to the remainder of the executive program.

Microswitch
265W3-l
Keyboard

PIA - Side A
bl

PAO

PAl

PA2

PA3

PA4

PA5
PA6
PA7

"'.J"
+5 V

FIGURE 5-1.1.1-3 Keyboard/PIA Hardware Interface

5-3

CA2

CAl

Get Keyboard
Data From Keybaord
PI A Data Register
Go To Clear
Key Processing

Turn Off Ready
Light

Go To Keyboard Data
Processing Routine

FIGURE 5-1.1.1-4 Flow Chart for Keyboard Service Routine

5-4

Go To Wand
Data Processing
Routine

::-::I<.SFTP riOP

00072 81C3 01
(I F

:EI

00076 Ale5 01

t'~CP

(I I) I) 7 4
(I (I 07:::

Ale 4

H 1 C~,

t-~OP

00080 AlC? F~ COlO
00090 FllCA CA FO
00100 AICC F7 COlO

LIlA E:

>::F'2DPA

OPR B

~~'f,F I)

.:: TFt E:

::-::P2DF.'A

:) (I 1 1 (I

eLI

A 11~. F

(IE

•

00120
(I (I

t -:: Ci

I) 0 1 4 (I
I) (I

o0 1 6 (I
I) (I

1 7' I)

A 1 D (I
h 1 D':::
A 1 Ii c:;
A 1 It 7
A 1 II '3

kEYBOA~D

E: ...:'
;:: 5 C I)
2"? 1 '3
'::' 5 4 (I
2 ? (I ?

(12 ':i (; AlE (!

c I)

ENABLE INTERRUPTS
PECUEST ?

LDA A

'-::F' ::CF'A

£: I T A

! ~ 'I; C 0

:.<~:: 1 065
EEO
EIT A ~~$4 U
:.::r 1 04 (i
BEO
LIlA A !~ :1; 1 ':'

00180 AlDE ~~ 1°
00190 RIDD F6 8008
I)~:

TURN ON READY lIGHT
:.ET PA-E.

LIlA B

:.:: F'::~ II J; A

E~'A

::<~::

READ r. E\'f;OAFD P I A COr-iTPDL
,::HECK CRA?, CPA':'
I F no f:='EO'-:E·:. T, CHECK IdAr-iD
CHECK FOR CLEAR KEY
IF NC~ CONTINUE kYBD SERVIC
I F 'i E::: !' LOA It CL EHF.: COIl E
CLEPP I t-1 TEf:;~PUF'T

1045

00210 AlE2 16 8008 XK1040 LIiH A

>-::P·;:DF.:A

LOAD K\'E:D ItATA.··· CLEAF.: H1TEF.:P

E
COlG XKI045
Anr B
E: F="
:TA E:
COlO
-' :~: F.~
8203

,:·:;P2IFA

TURN OF="F READY LIGHT
elf:;: F'A-6

00220 AIE5 F6
(I ;) 2 3

U AlE ::: C4

00240 A1ER F7
00250 FIlED ED

LD~

00260
00270
002:=:0

00290 AIFO £:6 COlO
(I

•
•XK1065

•

1).IAt-iD~·EF')

AIF5
A1 F :::
AIFA
AIFD
8200

F6
C4
F7
BD
7E

COlO
E: F
COlO
B60C
AIC3

'I; BF

;:'::P2r:;;;:'A
>::Kt< \' ! ~i

GO TO KYBD RDUTINE!'ACCA=DAT

I CE F:EOUE:::T?

lDA E
AnD B

>::F'2D;:;:A
>< ~'.: l).i Ht 1II
>:L.:S:FTF

DTHERWI2E!' GO TO WAND ROUTI

::: ~:.. S· F T F'

0 :~: 1 (I A 1 F.:;: 2 E C E

00320
(I (1:;::3 0
00340
00350
00360

.-,r·lF

PFt-6

FIGURE 5-1.1.1-5 Keyboard Service Assembly Listing

5-5

CBl

10 kn

PBO

10 kn

FIGURE 5-1.1.2-1: Keyboard/PIA Interface

PBl
:;

~::':BP DPP

1 '3 i) ,) 1 1 9 8 1 :) U
o02 (I (I '~I i 1 B 2? (1 '3
I) (I;:: 1 0 I) 11 II 'S C
(I 1)2::: (I (I! 1 E (I ':;

I t·{:<

00230

011~

:::F'>:'

(I (I

I) I)

c' 4- (I

(:6

~:::TRBLE

p
~TA~H

aSR
STR

.'y'E::::
+r'K1

~'~.F.:~.

~::::~:ETI_'F

LDA £
2T8 B

~~J;

(!=:

:;$04

l It

.TO 2ELECT DIRECTION ~EG.
SELECT PBG-~~3 AS CUTPUT~

;;~I:TUPt'~

00:::;4 (I

(11.::6 ':'6 01=
1=7 ~00~
0 1. :~; P C ~ F (1

LDA B

.:~:J;

00?50 0138

STR B

KBF.'DDR

I) (I? 6 (I

L.D A B

~~$

STA B

KBRDCP

800S

1 4 1 ? "Cr E E

n 1 4 :::~ E ~

BDPEAD
~"T=';_[I:~::U~'E

~::'S!::TJJP

STR B

I) I) 4 I) (:

Et'~API_E

•

80n~

(I I) 4

f3IJ i:;:'E - I!'i I T I ;~L L::E

PTI

0133 F?

(,UPF:=''::t'~T TAl.:'~"E I,/AU)E?
1::;0 PrJ T DATH I i"~ .PJ..II=FEP
AII'·... ncE t·i.E:P ':·Odt'.ff A~'iD

K~XIT

OO~30

00370 013D

+MDVE TO NEXT fRBLE LOCATIO
.S:EA;'(·H CDt'1':'L ETF::";:.NC~GO TO LJQKUP~CCNT SR(~
+YE~~GD TO B~D~EA~ PTN

~-~~--+---4~~+---4~--+----4

I-

PB2>-~~-~--4~--+---4~~~--~

PB3>-"~~~-~~-~----~--~---4

o
1

PB4

PB6

PBS

PB7

TO PIA

FIGURE 5-1.1.2-4: Initial PIA I/O Configuration

CBl

PBl

>-~~--~--~~~~---.~~~-~

o
I-

PB4

PBS

.....

PB6

TO PIA

FIGURE 5-1.1.2-5: Result of Key Closure

5-9

PB7

100

000

FIGURE 5-1.1.2-6: Contents of Accumulator A

CBl

PBO
1

PBl

PB2

PB3

PB4

PBG

PB5
TO PIA

FIGURE 5-1.1.2-7: I/O Conditions Reversed

PB7

5-1.1.2-7). ACCB is used in order to avoid disturbing the contents of ACCA. The ORAA instruction is then
used to replace the row bit positions with ones (see Figure 5-1.1.2-8) and the resulting word is written back into
PIRB.
The time required for the MPU to perform the steps just described is very short compared to typical
minimum switch closure times. Therefore, the switch is still closed and the conditions are as shown in Figure
5-1. 1.2-7. The column zero that was preserved and written back into PIRB is coupled through the still closed
switch and applies a low signal to a row input now established as an input. PIRB is immediately re-read back
into ACCA by the MPU. For a single key closure, the word thus captured must be one of the sixteen stored in
memory locations 0143 to 0152 in the Assembly Listing of Figure 5-1.1.2-3. The first four values are also
illustrated in Figure 5-1.1.2-9.
The MPU sequentially compares the contents of ACCA to the lookup table (stored in ROM)
containing the words until a match is obtained. ACCB is incremented following each comparison; when the
match occurs, a binary number corresponding to the key number is stored in ACCB and is available for transfer
to a buffer location in RAM.
If a match is obtained, the MPU stores the key count, re-initializes the PIA, and returns from the
service routine interrupt. If no match is obtained, it is assumed that the data is bad and a Bad Read subroutine is
called. Since only data corresponding to valid single key closures is stored in the lookup table, this approach
automatically takes care of both multiple key closures and inadvertent noise.
The specific action to be taken following a bad read is not shown since it depends on the particular
application. In many practical designs, affirmative action such as an audible approval tone is taken following
the entry of good data. The Bad Read subroutine in this case would merely disable the approval sequence. A
different routine would be used in designs requiring positive indication (blinking light, tone, etc.) of bad data.
In either case, the Bad Read sequence should end with a return from subroutine instruction, RTS, so that the
PIA will be properly re-initialized.
Many mechanical switches exhibit contact bounce when they are initially closed. A bad read will
result if the MPU reads PIRB during one of the bounce intervals. This problem can be avoided by inserting a
suitable delay routine (see Section 2-2 for examples) as the initial steps of the keyboard service routine. The
duration of the bounce varies with switch design but is normally in the range of one millisecond or less. The
keyboard manufacturer should be able to provide specific information.
The extension of this procedure to larger keyboards is straight forward. For instance, a sixty-four
key matrix could be implemented using both halves of a PIA and similar programming techniques.

b7
ACCA

~ K1

ACCA

I1I0 I1I1I0 I0 I0 I0I

~
to

I0 I0I0I1I1I1I1I
1 I 0 I 1 I 1 I 1 I 1 I 1 I 1 I

CONSTANT = OFI 0
ORA #OF

0..

~ K2

o
o K3
-J

FIGURE 5-1.1.2-8: Generation of Output Word

•

FIGURE 5-1.1.2-9: Lookup Table

5-11

5-1.2

SCANNING WAND FOR CAPTURING DATA FROM PRINTED SYMBOLS
The use of scanning techniques to retrieve information from machine readable labels, badges, credit

cards, etc., is gaining acceptance in a wide variety of business machine applications. This is due in large part to
the development and acceptance of industry-wide standards. The simultaneous growth of systems based on
microprocessors will give additional impetus to this trend.
Few tasks are as made-to-order for an MPU as the conversion of scanned data to a usable format. The
specifications for both magnetic and optical recording formats were designed to allow for either mechanical or
manual capture techniques. In addition, it was desirable for the labels to be humanly readable and verifiable in
case of equipment failure. The net result is that emphasis is given to the human aspects of the problem rather
than simplification of the electronics involved.
5-1.2.1

Universal Product Code (UP C) Symbol
The grocery industry's Universal Product Code (UPC) symbol is an excellent example of the genre.

Labels similar to the example shown in Figure 5-1.2.1-1 are beginning to appear on virtually every kind of retail
grocery product. They are intended to facilitate the use of automatic checkstand equipment and are the result of
an industry-wide effort to improve productivity in the grocery industry!. The symbol is optimized for ease of
printing, reading, and manually checking results. The symbol is designed to minimize the cost of marking by
the manufacturers and their suppliers. The symbol size is infinitely variable to accommodate the ranges in
quality achievable by various printing processes. It can be uniformly magnified or reduced from the nominal
size without significantly affecting the degree to which it can be scanned. An example of the human orientation
is indicated by the error check calculation described in Section 5-1.2.5. The error check is an involved addition,
multiplication, and modulo-ten reduction, a formidable task for conventional digital IC's, but relatively simple
for people (and microprocessors).
A suitable control method depends on both the characteristics of the symbol and the scanning
technique that is used. The symbol is designed for use with either fixed position scanners (label passes by on a
conveyor belt) or handheld wands. The" wandable" approach will, in general, be more difficult to implement
since allowance must be made for variable human scanning techniques. The control program described in this
section is suitable for either but was developed specifically for use with handheld wands.
A 10-digit numbering system was adopted by the grocery industry for product identification. Each
participating supplier is issued a 5-digit manufacturer's identification number. The remaining 5 digits are
assigned to generic product categories, that is, tomato soup, canned peas, tissue paper, etc. , each have specific
numbers regardless of brand name. This 10-digit number2 is combined with error checking features and
encoded into a symbol similar to that shown in Figure 5-1.2.1-2.
The standard symbol consists of a series of parallel light and dark bars of different widths. The
symbol will be referred to as the' 'bar code" to distinguish it from the" UPC code" that it represents. The basic
characteristics of the bar code are summarized in Figures 5-1.2.1-2 and 5-1.2.1-3 and the following list of
features from the UPC specification:
1

Information concerning the UPC symbol described in this Section is from the upe Symbol Specification obtained from: Distribution
Number Bank, 1725 K Street N. W., Washington, D.C. (Telephone- (202)833-1134), Administrator of the Universal Product Code
and UPC Symbol for the Uniform Grocery Product Code Council.
Although the symbol is primarily designed for these 1O-digit codes, it also includes growth capacity for longer codes to facilitate future
compatibility in other distribution industries.

5-12

~dr

... rder.
payable

.•n good only in

••ates. Allow 4 to 6
... ,ivery. Offer void where
restricted or license re.•• red. Offer expires ~June 30. 1975.
.... (1.

heck or
'or:
leenex®
Is from

s.
leenex®
Delsey®

FIGURE 5-1.2.1-1 UPC Symbol from Box of Kleenex 1 Tissues
Registered trademark of Kimberly-Clark Corp., Neenah, Wis.

Right 5 Characters of Code

COde~Tall

.r 1
Left 5 Characters of
Number System
Character

~ ~'d

Right·Hand

Center
Bar
Modulo
Pattern
(01010)
Check
Character

S" .,,"'" (101)

I
I

I Right Light Margin

I Minimum 7 Modules Wide

~/
I

I
I
I
I
I

Number System I

;;;;;j~ j!~~12
345 67890
~

\
11-Character
NDC Code

r4\
~

National Health·
Related Items Code

W[D
H
R
I

N
D
C

I
I
I
I

Characters Per
OCR·B Font

10"\. Regular

National
Drug Code

UPC Code

Number System
Character Format

Number
System:

rrespond:..~

Digit Co
ing to L ead Di gi t
if NDC Grows to
6·Digit Labeler
Code

FIGURE 5-1.2.1-2: UPC Standard Symbol

5-13

H
R

Light Modu

7 Modules
2 Bars/2 Spaces

The Above
Character
Represents a
Left-Hand "6"
Which is
Encoded 0101111

The Above
Character
Represents a
Left-Hand "0"
Which is
Encoded 0001101

FIGURE 5-1.2.1-3: UPC Character Structure

• Series of light and dark parallel bars (30 dark and 29 light for any 10-character code) with a light
margin on each side.
• Overall shape is rectangular.
• Each character or digit of a code is represented by 2 dark bars and 2 light spaces.
• Each character is made up of 7 data elements; a data element hereinafter will be called a
"module. "
• A module may be dark or light.
• A bar may be made up of 1, 2, 3, or 4 dark modules, as shown in Figure 5-1.2.1-3.
• Each character is independent.
• The symbol also includes two characters beyond the 10 needed to encode the UPC.
One character, a modulo check character (see Section 5-1.2.5 for details) is embedded in the
right-most position of the symbol to insure a high level of reading reliability. (See Figure
5-1.2.1-2.)
Another character, embedded in the left-most position of the symbol, shows which number
system a particular symbol encodes. Concurrent number sets are used to accommodate such
things as meat and produce without the need to set aside code numbers in the UPC.

5-14

• The symbol prevents tampering. Unauthorized addition of lines is readily detectable by scanning
devices. In the same way, poor printing will not result in scanning devices reading a wrong
number. This is facilitated by multiple error-detecting features which allow scanner designers to
build equipment to automatically detect and reject a very poorly printed symbol or one that has
been tampered with.
• The symbol also incorporates and presents the code number in a human-readable form.
The nominal dimensions of a typical symbol (as printed on a product) are shown in Figure 5-1.2.1-4.
The dark and light bars are built up from nominal O.OI30-inch modules, however, some of the characters
involve undersize dark bars and oversize light spaces. There are 95 modules in the symbol itself and 18 modules
in the white marginal guard bands.
Starting at the left side of the symbol, it is encoded first with" guard bars", then a number system
character (' '0" in the figure) followed by five UPC characters on the left side of the center' 'guard bars. " To the
right of the center bars is the remaining five UPC characters followed by a modulo ten check character. Finally,
the same guard bar pattern is repeated on the right-hand side.
y

,---

rimllll

.......

l--b
I

o
o

: I

I
1

.039

-=:

~~$

1.1.1

~~~I;7E,

Bi·~t:

tlJClPBl

I_It::-=:

.~~~I;

t:[
2Et F'-'
0014 :1 B601 :::9
B5~F

1 02

~~$1

i::3

tdCLPB;::

F I t'i t

:~:HED?

u
j'-10
COt-iTUE n r'ES ,GC t·i::·::T :ELK
GET ·S:T~~T ADD~: OF tt~:~T BLDCV

t'10 '",'E TO N::::

I t·i::-::
;::·F'>=:
Bt-iE

FlDDP

I::F'::-=:

!..JCLP:B2 ClF.:

l ':'

·S:T~'Tt·~I::;

GET

ClEAj;' CIJPF.:E,··1T LOCAT I or·i
LDeAT IO~·1
t·10'·/E TO t'~E>;:

::-::

I t·1::-=:

00110 B5FB f.."-'
0Ol;~O "E:5FC ac 012-:;
00130

$B5EB

1,.'CLP.t:L CLI-?

00060 :B5F1 !:::C 0076
00070 :B5F4 2E~ F'-"='
'-'
000:::0 B5F6 CE 01 OE:

001 00 B5F'3 6F 00

V I 1.1.1 t·i II

nAt'1
Of:::G

COt'~T
!I

I t'iU,:

F:E TUI:;::t·i

:~·EAPCH

I t·iG

TO E::·::ECUT I '·lE

FIGURE 5-1.2.5-2: XKIWND Assembly Listing

(2) Data Recovery -

YKWAND -

(Figure 5-1.2.5-3 and 5-1.2.5-4) This routine is entered from

the executive's Keyboard/Wand Interrogation loop. The Interrogation loop continually tests bit
7 of XP4DRB, the PIA Data Register until a "zero" is encountered. The zero is assumed to
result from reading the high reflectivity white space caused by the wand passing across the white
guard band at the edge of a symbol. The wand output will normally be high at other times. For
example, the wand just laying on a counter is equivalent to reading' 'black" or some other low
reflectivity surface. The objective of YKWAND is to measure the time between transitions and
store the results in RAM memory.
(3) Data Processing -

WSORT -

(Figures 5-1.2.5-5 and 5-1.2.5-6) The objective ofWSORT is

to reduce the timing data captured during YKWAND to set up UPC characters in binary format.
There are several additional routines associated with recovering the data: WERCHK tests the data to
see if it is a valid UPC number by performing an error check based on the check character included in the
symbol; (2) WBCDPK converts the data into packed BCD (two digits per byte), the format required for the
price look-up routine; (3) WBADRD, the error processing routine, may be called for a variety of reasons during
execution of YKWAND, WSORT, WCDTST, or WPACK. Each of these routines include validation tests and
will call WBADRD if a bad read occurs. The action to be taken following a bad read depends on the particular
application and may be performed by either the MPU or the human operator. Therefore, no specific WBADRD
routine is included in this description. The system described in Chapter 6 generates an audible" approval" tone
for "good data." In this case, the WBADRD routine could be nothing more than a deletion of the approval
tone, indicating that either another scan or manual entry is required.
Details of the YKWAND routine are shown in the Flow Chart and Assembly Listing of Figures
5-1.2.5-3 and 5-1.2.5-4, respectively. Following entry from the Keyboard/Wand Interrogation Loop, bit 7 of
the PIA Register (XP4DRB) is again tested to insure that the data is still low. If the entry was caused by a short

5-23

YKWAND
Enter from
I nterrogation Loop
WBDRLP
Yes (Reading White)

Increment
Timer.

Start Timer

Yes

Start Timer.

WHITLP

Yes

Increment
Storage Buff. Addr.

I ncr. Space Count
Reset "From Black"

Incr. Bar Count
Set "From Black"

Store Time per
Storage Buffer
Address.

WSTRGE

Figure 5-1.2.5-3 Flow Chart for YKWAND Routine

Yes

Increment
Timer.

00010
00010
00010

•
•

00020
000:3 I) B60C

nAr'1
>::KI.,.lAt·~D
OPT
LIST
r'iAt'1E: >::KI).lAt·~D
PEI",I:
1. 2 . . . 1.3 . . . 74
ope;
$B60C

•••••••••••••••••••••
••

00040
00050
00060

00080
00090 B60C 7E B610 XKWAND JMP
00095 B60F 39
XKIWND RTS
o Oc~8 (I

00290
0030r
00:31
00:32

0033
0034

0035

0036
00370
003::: I) E:61 (I
003::: 1 B613
003::;:2
00:;::::3
00:::::::4

B61E.
B61 ':;.
B61C

00:;:'30 B61F
00400 :E:E.22
o 04c~ 0
004:30 B624
00440 H62?

7F
7F
?F
?F
?F
FE.
2B

01 06

•
•
•
•
•
•
•
•
•
•. . ·KI.IJAr·iD

01 04
01 05
01 14

THIS PART OF THE ROUTINE IS THE
DATA GATHERING SECT. OF XKWAND.
IT READS THE UPC CODED LABEL
AS 60 BLACK AND WHITE BARS AND
STORES THE SCANNING TIME OF EACH
BAR OR SPACE IN LOCATIONS $00-$?5
elR

1.I.lBPC~iT

eLF.:

I.I"FLAG

CLF.~

1.1) :S: P C ~~ T

I.,J:S:E:FAIt
I..JSBFAD+ 1

COl 0

Bt'1 I

!..JBAD

•

LD>::
CE 0000
F6 COlO t..JBDRLP LDA B
00460 B62A 2B OS
BP1 I
00470
004::;: (I

004'30
00500

E:62C

~::C

FFOO

-:,.::- L-:. __
00510 B62F ......
00520 B6:;: 1 08
00530 E:E.:~:2 20 F'-'-';:'

~-:,1

•
•
•

••••••••••••••

Et-iTF.:\' PO I r-1T:S:
NO INITIALIZATION

eLF.:
ClR
LDA B

01 15

WAND ROUTINE

;:'::P2D~:A

~~$OOOO

::'::P2DF.:A
I.I"BLKLP

L I r'iE lOI. .! ~ SPACE?
t'iO: EF.: F.: OF.:
·. . E:S:
LINE HIGH~ BAR?
'r'ES: TO T I 1'1 I t'H3 BAF.: LOOP

:S:ET t'1 A>:: I t'1 Ut'1 T I r'1E ALLO!.,.lEII
00

Ot~

:B 0 F.~ It EF.~

CP::<

~~$FF

BEO
I t'i::-::
BF.:A

t,JBAII

:
GUAF.~It E:At-iIl DELAY
TOO LDt'H:i Dt'i GUAPD BAt1D:

I.I.lBIIPLP

LOOP BACK

t·~O

FIGURE 5-1.2.5-4: YKWAND Assembly Listing (Sheet 1 of 2)

5-25

EF.:F.~

•

00540

00550 B634 CE 0000 !.dBLKLP LD::-:;

~~$OOOO

00560 E:E.:::7 F6 COl

::::
LIt;:.::
0114
0102
LDA A
0103
LItA B
:S:TA A
00
:~:TA B
01
I ~i>::
In::-=:
:S:T::-::
0114
0104
T:S:T
A5
BEG!
C4
BF.:A

1...IItUrlBF
1.I.lSE:FAIt
1...IItUt'l:E:F
1...IItUrlE:F + 1
.....
.0.
$1, ::,::

LOOP

'r'E~S: :
Et'iD LOOP
t'iO
SPACE COUt-1T = 30?
·...'E:S: , TOO r'lAt'i\' :S:F'ACES:

:S:ET r'lA;:':; I t'1U,..1 T I~1E ALLOI.I.IED

0:::

•

NO, T I NEF.~ = 4::-:;U?
....'ES
t'iO
LOOP BACK

~~$OOOO

;:-:;P2DF.:A
1...IH:5:2
1...1S F' C t'i T

20 EC

FF
FE
B6
F6
A'?
E7

SCAt-~

Inc BAR COU,..iT
SET " FF.:O,..l :BLACI<" FLAG

1..,1 BAn

•

= 30?

1.1.1 B F.: e t'i T
I.I.lFLAG
1).1 :S: T F.: GE

CP::<
BEG!
It·,,::-=:

.-c..
....., EE:

E:66C ?C 0105 1..,IHS2
B66F 7F 0104
B672 7E B675

E:E.75
E:E.?::::
B6?E:
B67E
B681

~~$ OE:2'j
1...tBAD

BEG!
I t'i::-::
BPA

.Jr'lF'

1.I.lBAD

TIt'lIt'H3 LOOP
:S:PACE?
LOOP

:S:ET t'lA>:: I MUt'l T I,..lE ALLOI,.jEII Ot'i BLK BAF.:

B64:B 7C 01 Ot. I.I.lH:S: 1
B64E 7C 0104
B651 7E F.:675

oo·~o

0091
0092
00'33
n0940
0950
09';:,0
0970
09:::0
0'j'30
1000
1020
./1030
01040
01050
01060
01070

•
'*
•

BLACK BA~~
L 1 t'iE LOhJ,
\'E:S: :
Et'1D
t'10
HAP COUt'iT
··f'E:S: :
Et'iD

NO, T I
....·ES
NO

Ot·~

I.a.lHITE

ERF.~O

BAF.~

~1EF.:=7>::U?

I t'iC :~:PACE COUt-iT
PE:S:ET " FF.~O"'1 BLACK" FLAG

LOAIt A AtiIt B
COt'iTEtiTS OF
I tiItE;:':: F.~EG. (T I t'lEF.~)

I...IITH

S:TDF.:E T II"1ER I ti STORAGE BUFF
I riCREI"lEtiT STOF.~AGE
BUFFEF.~

AItDF.~ES::S:

1...ISE:FAIt
I.~FLAG

I...IE:LKLP
I...IHITLP

TEST FLAt::;
.JU,..lP TO CORF.~ECT
TI,.,11,..iG LOOP

FIGURE 5-1.2.5-4: YKWAND Assembly Listing (Sheet 2 of 2)

5-26

Addr. 1st Group of
4. Reset WF612.
Set Addr (WSBFAD=06).
Initialize WCBFAD.
Set 4 Bar End*
Values (WBEN D)

Load Bar
with Mod. time

Determine WMODTM,
1st WTSAMP.

* End #1 = T me for Bar 1;
WEVNBR

WODDBR

End #2 = T me for 1 st 2 Bars;
End #3 = T me for 1 st 3 Bars;
End #4 = T me for all 4 Bars;

Yes

-...l

Shift a Zero
into WCHBUF

Shift a One
into WCHBUF

Shift a Zero
into WCHBUF

AddWMODTM
to WTSAMP.
Addr. Next Char. Buff;
Incr. Char. Count;
Addr. Next Group of 4;

Set WF712
Set WSBFAD

FIGURE 5-1.2.5-5 Flow Chart for WSORT Routine

Yes

01:~:20

01330
01340
01350
01360
01370
013:::0
01390
01400
01410
01420
(1430
1440
1450
1451
1470
1480
J 14'3 0
015:3 -,
0154
0155
0156
0157
0.15:::
015'3u
01600
01610
01620
01630
(11 E.40
(11650
1660
1670
1680
16'30
1700
1710
'-'1720
I) 17:3 0
01740
01750
I) 17E, (I
01770
01 7:::: 0
01 7'30
01:::00
01::::10

•
•
•
•
•
•
•
•
•
•
•
•
•1.1.i

•

:~: 0 F.~ T

B6A::::
B6A6
B6AS
B6AA
B6AD
B6E:O
B6B2
B6B4
E:E,:B7
BE.:BA
B6BC
B6BE
B6Cl
B6C4
B6C6
B6C:::
B6CB

1 14 I.I.lSPTLP LD>::
LItA A
0
LIlA B
1
STA A
lOS
:S:TA E:
109
ADD B
-1":'
'-'
)2
ADC A
STA A
010A
:::TA B
C110£;
AnD B
05
AIIC A
04
'S:TA A
010C
:~:TA B
01 OD
ADD B
07
ADe A
OE.
STA A
01 OE
:S:TA B
010F

B6CE
B6DO
B6It2
B6It4
:B6DE.
.BE-D'3

F7
EB
A'3
E'::'I
F7

'37
D7
:::6
97
BD
D6
B6DB 7F
..
B6DE F-:"
B6El 4F
(11 :::2 (I B6EE~ 56
01::::30 E:6E3 B?
01840 B6E6 F?

DE.
D?
0"7
It5
BA53
D'3
0110
01 11

•

:s:r::-:;

I.,.I:S:BFAD

:S:ET 1...I:BEnD~~ VALUE:S:

I.IJ:S:BFAD
1.1.IF712

CLF.:
LD::-=:
ST::<
eLF.:

STA
'::TA
LIlA
STA

1.,.lCBFAD
I.dCHPCT

INIT DATA TO :S:TAF.:T
AFTEF.: GUAF.:It F.:F.IF.: :s:
~:E:S:ET FLAG 7-12
I ~i IT CHAF.:ACTEF.: BUFFEF.:
ADDF.:ES:S:
CLEAF.: CHAF.:ACTEP COUr-iT

~~E.

LD>::

0006
0114
0104
0116
0102
0106

•

"'_IJSOF.:T"

THIS PA~:T OF THE POUT I ~iE U:~:E:S:
THE DATA I ~i ~:A~1 $00-$75 At-iD
DEC IPHEF.::S: IT I ~iTD 12 7-BIT
E: I t-i A F.~ ..... 1.,.loPDS t,.IHICH AF.:E CODED
A:S: Ot-iE OF THE UPC CHAF.:ACTEF.:
CODES At'iD LOADED It-iTO I...I:S:TGBF
A 12 B'r'TE BUFFEF.:

B691 CE
B6'34 FF
E:E.'3(' 7F
B6'31A CE
B6'3D FF
B6AO 7F
FE
AE.
E6
I'-:='
'1
F7
EB
A9
E'-:='
'1
F7
EE:
A'3
I'-:='
'I

:S:ECT IOt-i

~~I.,J:S:TGBF

>::
$1 , ::<
/.•./BEt"iD 1
I.a.iBEt-iD 1 + 1

::;: , ;:.:;
$2, >::
~I;

I..JBEt·iD2
I..JBEnD2+ 1
~I;5,

::-::

$4, >::
1.I'!£:Et"iD3
i.dBEt"iD3+ 1
~t;

or, >::

$6, >-::
I.rJBEnD4
1.,.IBEt-iD4+ 1

;:':;KDi·/t·iD

F.'.'

;:-:; K It 1",1 ~1 D + 1
~~$ 07

A
A

J:~:P

LIlA B
CLP
-~:TA B

elF.: A
~:DF.:

01 12

:~:TA

01 1-:'
'-'

:S:TA B

:S:ET DIVIDEND

:~:ET D I 1.,,1 I :S: 0 F.:
II 1 1,.,1 I DE B..,.' "('

::-::KD\l:::F.:

;:·:;KD I VD
F.~ECD,·.,IE~: At·~ :S: 1.,.1 E F.:
>::KOUDT+ 1
1.I.it·10DT ~1
LOAD r'1DDULE T I t'lE
I.,Jr·lDDTt·1+ 1
D I I•••! I DE E"'"
'
2

BUF.

I.lJTSA~lP
I.lJT:~:A,",1P+

LOAD SAt·1P. T I t'lE BUF.
1...11 TH
I r-1 I AL 1.,.IALUE

FIGURE 5-1.2.5-6: WSORT Assembly Listing (Sheet 1 of 3)

5-28

01::::50
01::::60
01::;:70

01::;:80
01890
01900
01910
01920
01930
01940
01950
01960

B6E9
B6EC
B6ED
B6FO

B6 0113
44
BE 0113
B? 0107

•
•
•
•

LDA
LSF.:
ADD
:S:TA

I.I.ITSAMP+ 1

A
A

WTSAMP+l
CALCULATE 3/4 OF MODULE T
W34MOD
STORE FOR USE

•
B6F3 FE 0114
B6F6 FE. 0111
B6F9 B6 0107

01970

019:::: (I

••

1...1 :S: E: F AII
1).I~1DIITM+

1.,.134t'10D

IF ANY BAR IS TOO NARROW,THE NOMINAL
MDIIULE WIIITH IS USEII TO REPLACE IT,
THIS ALLOWS FOR MORE ACCURATE I1ATA PROC.
TST
X
CHECK FIRST BAR
E:t'1E
1.1.IC~lP 1
Ct'1P A $1 , >::
BCS
1••.ICt·lP 1
:S: TAB :I; 1 , >::
BRA
1••,1SF.:TLP
WCMPI TST
$2,X
CHECK SECOND BAR

02000
02020 B6FC 6D 00
020::::0 B6FE 26 0::::
02040 B700 Al 01
02050 B702 25 04
0206 -, B704 E7 01
0207 B706 20 '3B
020::: B70!:: ErD 02
020'3 B?OA 26 0:::
BlOC Al 0:3
0210
0211 B70E 25 04
02120 B710 E7 03
02130 B712 20 8F
WCMP2
OE~140 B714 6D 04
02150 B716 26 08
02160 B718 Al 05
02170 B71A 25 04
02180 B71C E7 05
021'30 B71E 20 83
WCMP3
02200 B720 6D 06
02210 B722 26 0'3
02220 B724 Al 07
022:::: I) B72E, 25 05
02240 B728 E7 07
02250 B?2A ?E B6A3
Oc~26

0
02270

02280 B72D FE
022'30 B730 68
0230lj B732 ?D
02310 B?:;:5 27
02320 .B737 6C
02330 £:?::;::'3 E: I)

LII>-=:
LIlA B
LIlA A

•
•

01':;'90

OC~::::4 0
02350

ADJUSTMENT TEST: IS ONE OF THE
BARS DR SPACES TOO NARROW?

0102

•
•
WODDBR

Bt'~E
C~1P

BC:S:
STA B
BF.:A
TST
Bt-1E
Ct'lP A
BCS
:S:TA B
BRA
TST
Bt'~E

cr'lF' A
Be'S:
STA B
.Jt'lP

1 (I

LIIX
ASL
TST
BEl]

I r-iC

0104

•

1...IC~lP2

:BF.~R

B73B FE 0102 WEVNBR LDX
02::::60 B73E 68 00
ASL
TST
02370 B740 ?D 0104
BNE
02380 B743 26 02
Inc
0;::39 (I B?45 6C (10

$3, ::-:;
I..JCt'lP2

'1;3.,;:'<

I..JSF.:TLP
$4,X
I..JCt'1P::::

CHECK THIRD EAR

$5, ::<

I. JCt'lP:;:
$5, ::<
I..JSRTLP
$6,X
I. .I0IlDEF.:
$7, >::
I...IODIIBR
$7, ::<
I..ISF.:TLP
.lCBFAII

1.•

CHECK FOURTH :E:AF.:

LOAD I t-H3 LOOP 1

1...IF712

.lH:S::::

1.•

i...IH:S:S

1.I.lCBFAD

LOADING LOOF' 2

i..JF712
i.,JH::::::=:

FIGURE 5-1.2.5-6: WSORT Assembly Listing (Sheet 2 of 3)

5-29

02400
02410
02420
024:30
02440
02450
02460
02470
02480
024'30
02500
02510
02520
025:30
02540
02550
02560
02570
025::::0
025'30
02600
02610
02620
02630
02640
02650
02660
02670
02680
02690
02700
02710
02720
027:30
'02740
02750
02760
02?70
027:::0
027'30
02800
02810

•

0112 I...IHSS
o11 :~:
0111
0110
0112
0113

B747
E:74A
B74I1
B750
E:75:3
£:756

B6
F6
FE
E'3

E:759
E:75C
E:75F
E:762

E:E. 0112

E:7E.4
E:7E,6
B769
B76E:
B?6E
:B770

E:772
E:775
E:777

E·...,
(

F6
Bl
25
26
Fl
25
:B 1
25
26
Fl
25
H1
25
26
Fl

01 1'::'
'-'
010:::

C9
05
010'3

C2
010A

1,•.IH:5:9

B78F 7C
E:7 32 7C
B?95 Bt==.
1

B6
:::1
26
7C

01 OB
C4
010C 1..,IHS10
E: 1

•

0103 1,I,IH:::::l:.::
0106
0115
0115
0106

•

06
0:::

•

2? 0:3
?E B6A3

20 00

I.IJHS 15

•
•

TIME

I.~MoIITM+l

1...I~loDTM
1.•.ITSAt'lP
1..,IT:S:Af"lP+ 1
F IRS:T TES:T

Ct'1P .B
BC:S:
I t,~C
I t'iC
LItA A
AnI! A
STA A

ADItf;:~E:S::S: t'1E:>::T CHAF.~ • BUF.
l,dCBFAD+ 1
I t'iC • CHAf;:~ • COU~iT
I.t.lCHPCT
1..J:S:BFRIt+ 1
AIInPE:S::S: t'iE::-::T GF.~OUP OF
~~~I; (I ::!
FDUF.: STFU3E. BUF.
l,dS:BFAD+ 1

LIlA A

I.,'!CHPCT

C~1P

~~$O6

E:
A

BCS
Bt'~E

B~iE

0106 1,I.lH:S:14

UPDATE S:At'lP.
I..JTSAt'1P
I.•.ITS:AMP+ 1

1.s.lT:S:Af'olP
1.•.ITSAt·lP+ 1
I,.,IE:EtiII 1
1...IoDIIE:F.:
1,••IHS'3
1.',IE:ENIll + 1
1,.,10 II II E:F.:
1,•.IE:EtiII2
I.a.lE\,lt'iE:f;::
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I..JBEtiIl::::+ 1
1.•.I0IlDE:f;::
1,I.lBEtiIl4
1,IJE\ltiE:P
1,I.lH:S:13
I.dBEt'iD4+ 1
1.1.1 E I.,.' t'i E: P

BC:~:

0104
::!E. 40
1:",7
011 :'
"
B6
81

A
B
A

Bt'iE
CI"lP
BCS
Cf"1P
BCS
Ht-iE
CI"lP
BC:S:
Ct'lP

Ci2::::~:

B7Ae
E:?AF
B7B1
E:7E;3
E:7B6

LIlA
LIlA
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BC:S:
E:t'iE
CI"1P
BCS
Cr'lP

£:7'3::: :::E! OS

B?9A £.-;:0
'I

A
B
E
A
A
B

CE:

:B77A
E:77C
05
B77E
01 QII
.-.c::
E:7:31 .::.._1
AA
E:·?:=::~: :B1
010E I,IJHS 11
E:'7:=:E. 25 £::3
E··..,·-··-·
II· . :••=,
26 05
E:7:::A F1 010F
B?:::II 25 Ae

B79D
B7AO
B7A2
f:7A4
B7A7
02:::20 B7A"::!

0284
02:::5
02:::6
02:::7
028:::
02:::'30
02'300

•

LIlA
LDA
ADD
ADC
STA
:S:TA

Inc
LIlA A
:S:TA A
LItA A
cr'1P A
BEG!
Jt'lP
BF.:A

1...IH:S:14
1.I.lF712
~~$4 0
1,I.lSBFAD+ 1

IF TSA~lP EtiIt 1
IF TSA~lP EtiD2
IF TSAMP Et'iIl::::
IF TSAMP END4
IF TSAt'1P
198 >
30 <
48 >
41

33
33
33
33

If all the bars are greater than % of the nominal bar width, the program branches to the next main
sequence, WODDBR. If, as in the case of the third bar in this example, some of the bars are undersize, they are
replaced with the nominal value and the checking procedure is repeated until all bars are at least the nominal
width. For example, this leads to:
41

198

(45)

30
with new values:
WBEND1: 41
WBEND2:239
WBEND3:284
WBEND4:332
WMODTM: 47
WTSAMP: 23
%(WMODTM): 33
and the test is now satisfied by all four bars.
By repeatedly increasing the initial sample time by WMODTM, a set of sampling times are
generated that can be compared to the Bar End values in order to determine which bars are currently being
sampled. For the example:
23
41
41
41
41
239
284

<
<
<
<
<
<
<

= 41; therefore, in 1st Bar.
23 + 47 = 70) < WBEND2 = 239; }
70 + 47 = 117 < 239;
therefore, in 2nd Bar.
164 < 239;
211 < 239;
WBEND

258 < WBEND3
305

< WBEND4

= 284; therefore,

in 3rd Bar.

= 332; therefore, in 4th Bar.

332 < 352; therefore, beyond last Bar.
Since the symbol and code are defined such that the first module of a character (scanning from either
direction) is a zero, the result of this sequence indicated that the upe code for this character is 0111101 , or from
Figure 5-1.2.1-5, the decimal value is "3." Note that it was assumed that the code was a left-hand character
implying a left-to-right sweep since the character was recovered immediately followed the initial guard bar
pattern. The program as shown in Figure 5-1.2.5-6 is for left-to-right scans only. A simple parity check is
adequate to determine whether left or right hand characters are being read since each side has opposite parity.
The data for all 12 characters is recovered in this fashion and stored in consecutive RAM buffer

5-33

locations. At this point, the data is still encoded in the UPC format of Figure 5-1.2.1-5. The UPC code follows
no simple algorithm and, hence, must be converted to weighted binary before error check calculations can be
made.
The Flow Chart and Assembly Listing for WCNVRT, a suitable conversion routine, is shown in
Figures 5-1.2.5-7 and 5-1.2.5-8, respectively. The conversion routine uses a table look-up procedure. Code
words corresponding to each of the ten UPC characters is stored in a permanent table in ROM (see Figure
5-1.2.5-9). The MPU tests each recovered data byte against the values in the table until a match is obtained.
When this occurs, the current UPC data is replaced with its weighted binary equivalent. Since the desired
equivalent is weighted binary, it can be generated by using accumulator B as a counter that tracks with the UPC
look-up table position. When a match results, the value that is to be substituted is then available in the B
accumulator. Note that while there are two sets of codes, left-hand and right-hand, for the UPC characters, only
one table is required. This is due to one's complement relationship of the two sets. The look-up table contains
the left-hand set. If the MPU tests a given data byte against all ten left-hand words without obtaining a match, it
then complements each bit of the UPC data and goes through the look-up table again. If no match is obtained
after a second pass, the program causes an exit to WBADRD. When all twelve characters have bee.n
successfully converted, the MPU proceeds to the next sequence, an error calculation to determine if the data
represents a valid UPC number.
The Error Check Character included in the symbol was originally obtained by applying the
following steps to the UPC number:
Step 1.

Starting at the left, sum up all the characters in the odd positions (that is, first on the left, third from
the left, etc.), starting with the number system character.

Step 2.

Multiply the sum obtained in Step 1 by 3.

Step 3.

Again starting at the left, sum all the characters in the even positions.

Step 4.

Add the product of Step 2 to the sum of Step 3.

Step 5.

The modulo-1 0 check character value is the smallest number which when added to the sum of Step 4
produces a multiple of 10.

The error check routine, WERCHK, applies this algorithm to the first eleven digits of the recovered
data and checks the result against the recovered check character. The Flow Chart and Assembly Listing are
shown in Figures 5-1.2.5-10 and 5-1.2.5-11, respectively.
The error check is performed by duplicating the steps taken during the original generation of the
check character and comparing the result to the recovered check character. The modulo-1 0 result for Step 5 is
obtained by repeated subtraction of 10 until the result is less than or equal to zero. If no match is obtained the
program exits to WBADRD. If the test is satisfied, the program proceeds to the last step in the sequence,
placement of the 10-:digit UPC number in five bytes. of RAM as packed BCD characters.
The Flow Chart and Assembly Listing for the packing routine, WBCDPK, are shown in Figures
5-1.2.5-12 and 5-1.2.5-13, respectively. The packing order is indicated in Figure 5-1.2.5-9.
5-1.2

PRINTER CONTROL

A great many different printers are in use; they range from the slow but economical devices for

5-34

UPC Characters are in WSTGBF
WPACK

Put Starting Addr.
of WSTGBF into
WSBFAD CLR 2nd
Pass Flag

Load X with Current
addr. of Strg. Buff.
Load A with Current
UPC Character. Point
X at next Buff.
Location, Store in
WSBFAD.

ClrB (Char. Value).
Load X with Starting
Addr. of UPC Table.

Compare UPC Char.
I n A to Current
Table Value

Complement Current
UPC Char., Set 2nd
Pass Flag, go thru
Table Again.

Yes

Incr. Char. Value.
Move to next table
Location and Test
For Srch W/O Match

Replace UPC Char.
with BCD Equiv.
Reduce Conversion
Count.

Figure 5-1.2.5-7 Flow Chart for WCNVRT UPC to BCD Conversion Routine

5-35

00010
OOO;~O

E:7B7

t'tAt'1

h.lCt'~"lF.'T

OF.~C;

~1;E:7:E:'7

00040 B7:B7 CE 011E. i,IJ C1'1 '.,.' F' T LIt::-=:
:S:T::'::
00050 B7E:A FF 0114
OOO~,O B7BD :3E, OC
LDA A
00070 :B7:BF :E''7
STR A
'I 0112

00250 B7DF
002f,O B7EO
OOi~rO F.:71::1
I) O;~:3 (I E:7E4
oO;~9 0 B7EE.
00300 :B7E'3
;) 0::: 1 (I B7EE:
00320 B'?EC
00:::'30 B7EF
00::::40

00.341

00:::42

00343
00:344

oO:~:45

B7F1
B'7F2
B7F::::
B?F4
B7F5
B7F6
B7F7
B7F:::
00:346 B'7F'3
.B7FA

A1
E~E.

1.,.I:5:PCtiT

!.I.ISBFAD

1.,.IPASS2 CLR E:
LII;:'::

~~h.lPCTBL

InITIALIZE .::HAR BCD i",'ALUE
GET :S:TAh;~T i=!f!IIP OF '-'PC TAE:L

I,.JCr'1PPE Ct'1P A

>::

BnE

1.1.1 t·~ ';.:: L 0 C
b.lS:E:FAD

LII:;'::

DEC

I,..I:S:PC~~T

27 20
.;,.
20 E'-'

BEG!

l.dIiCDPK

E:F.'A

i,I.lt"1>::TCH

:~:TA.

INC

::~::

TST

OE.

BriE

4:::~

~~I"IPCr:BL

1,1.1 Ct'l P F.~ E
I.I.IFLAG
I"JBADPD

COr'1 A

rr'K:

7C 0110

DFt

B7Fl
01 14
01 1 i7.,
C,
01 1'-'

01 10
1'3
1'-'
'.,:,
If.
01

.BRA
i,.JBA'DF.'D EOU
I.I.I:S:BFAD EG!U

EOU
1.•,iSPCt·1T EOU
EOU
'-'-'FLAG
I...IPCTBL FeB
I.IJ'~:TGBF

UPC CHAR t'1A TCH TF:LE CHAR?
t'iiJ ~ CDNT I ~iUC: :S:EAF.~CH
GET CUPF.'Et~T ADIi~~ FF.'Ot'i BUF
>·,·E.S ~ PEF'LAC~ UPC I,I,IITH BCD E
F.~EnUCE COt·1""Ic.F.~S I on COUt'~T
IF DlJt'iE ~ E:;·::IT TO I.IJBCDP~:::
IF t'iOT ~ GET ~~E::':~T CHAf;,~
r·~E::.;: T UPCTBL LOCATIO
I t·~CF.~EA:S·E BCD CHAF.~ \·'ALUE
:S:EA~'CHED E,'fTIRE TABLE?
~~!J ~ COt'~T I t'1UE THRU TA:BLE
'lE:::;: !f SEE IF Dt·.j SECDt'~D PA:S':S:
,-,
,:. PA'S~SE:S: 1).iT .-1 "'~D t'1TCH = BAnF.1ST PA:S::S:~ COt'1PLEMEt'iT UPC CH
~~:ET E'r'~D PASS: FLAG

r'10 '",'E TO

CP::-:;
Bt'1E

2E. E9
7D 0110

i~O

p
......

i,I,i t'i >:~ L 0 C I r·i::·:;

!:::C :B7F 1,
~~E.

IN>::
:S:T>::

1.1.IFLAf:.i

FE 0114
E7 00
7A 0112

08
5C

1.I.lFLAr:;
1.•.IPASS2

GO THPDUGH TABLE AGA I

$0114
.. ·-r

$01 .i.c,
$01 .1 (I
$1'3 ~:f.;13 !' $16 ~ 'I; 0 1

OS
o;~

FeB

t·~

$01. 16

0'('

CLEAJ:;;' 2t'HI PFt:s::s: FLAG
I:;ET CURF.~Et·~T UPC CHAF.'ACTER
PO I t'iT TO t'1E,~::T UPC LOCAT Ior'1
::H1D STORE I ;,.~ BUFFER

00140 B7CE: SF

B7CF
B7D1
B7Ir3
OOi~O
B7D6
0021
E:7D:3
0022C B7D:B
002:;:0 :E:7DD

oe:

::-::

1.1.1 r'i ;:.:;

001?
001:::
001'3

~~$

GET :S:TAF.~T I ;"H3 ADDf;.'E:S::S: OF
STr;:GE BUFF I t'~TO BUF AIIDR
LOAD I,I.iSPCt'iT '",IITH ........ OF
CHAPS TO :BE: CO t·"I",1 E RT E It

LIlA A

000'30 B7C2 7F 0110
0010:) :B7C5 AE. 00
001 10 :B7C? 0:3
00120 B7C::: FF 0114

001'50 :B7CC CE B7F1

T CH CLF.'

~~I,I.I·S:TG:BF

'.I.tSE:FAD

$04 ,:f1R

lA
FIGURE 5-1.2.5-8: WCNVRT Assembly Listing

5-36

~$OE ~.I,

~$C!:::

,$Oi.=2

ROM
RAM
YKWAND

$7F(CLR)

UPC#9 UPC#10

$8610

$01

$0000

UPC#7 UPC#8
UPC#5 UPC#6

-----

UPC#3 UPC#4
$3B(RTI)
WPCTBL

$19

$B _ _

UPC#1 UPC#2

$B _ _

$13
WSBFAD

$16

$0004

$0114

$01
$OE

WSTGBF

#System Char.

$08

UPC #2

$02

UPC #3
UPC#4

$04
$LA

$0116

UPC #1

$07

$B _ _

UPC #5

--------

UPC #6
UPC #7
UPC #8
UPC #9
UPC #10
WSTGBF+11

Check Char.

-------- FIGURES 5-1.2.5-9 XKWAND Table and Buffer Memory Allocation.

5-37

$0121

BCD Equivalents of UP Char. are in WSTGBF

Add Current Value
of WSTGBF to A.
I ncr. X twice.

Multiply Odd Sum
by 3. Get Strting
addr. of Even lacs.

Add Current Value of
WSTGBF to A. Increment X twice

Su btract 10. Test
for Result';;;;; Zero

Test for Binary
Value less than 127

Form Binary from
2's campi. and test
for match with
Check Character

FIGURE 5-1.2.5-10 Flowchart for WERCHK Error Check

5-38

0001C:
I)

0 O;~ 0 :B'7FE

(I I)

04 0 B ('FE 1::E

(I 11~,

t"c~'CH~::'

00050 ESOI 4F
(10070

:p':' (I:::

RE (10

1;.\ ~:TEF'

IF:?FE

i,_Ii>::

~~I.r.l:::TGF.:F

T E P;~ TAB

1F:

00140 P80D 1B
(I I) 1 SOB ::: (I F.

L II .:-::

eEl) 1 1 (

0(11 (' (I "B::::11 A B (10

IJF ODD

CU~PENT ODn LOCATI
ME!T LOCATION

"'1 U L T I F'L '/

~ ~ bJ

!d,::TEP3 ADD A

HDD~t

~LEAR

~~1,1.!:~' fGBF + 1;::
ADDED HL.L enn LOCAT I Dt<:::
WSTEPl
IF NO CD~T~~~;IF YES~GO 2TE

CPX
BNE
11.i '~:,

ADD FROM
M~VETD

It',>::
INX

ABA
ABA

0013~

I:;ET :S:TPTt-1(=

LOCATION:;

1 i:iIID A

n .E'~:: 04 l !:=~
00090 8805 r~
0010G BS06 8e 0122
0011n POO? 26 ~7
L:.(i P !:=: c:~'
B80 r

b.iEf:;'CHV

CLR A

I) (I o':~

I) (I

nAt'1
OP':';

s: T I:; ,E F + 1

:-:

'::.; E f

MDV~

F.' E :::;' U L T

RESULT

L~AVE

E 1:/ E N

ADD FRor'1

it:-:,

:~: T .:: P 1

BY THREE.
IN ACCR

:~: T R T ~--I (3

CU~'REi--~T

A I! L; ~~

LDCAT I

or-~

TO NEXT LOCATION

00190 B814 08

INX

00200 B815 8e 0116
(1021 0 :r::S 1 ~:: ;=~6 F7

CPX
B!--iF.::

!.,.I:::TEP3

IF r-i!] ~ COr-iTt--! .lE;

TST A
BPl

WMDD10
I)

GREATER T~A~ 127 BINRRY?
ND~ CONTINUE MODULO CALC.
YES~ SUBTRA:T 10~CHECK

TEF4

FOP :::T I LL

~STEP4

00230 B81A 4D

00240 B81B 2R
(I I) 2 '5 (I

B:=~ 1 It ::: (; 0 A

00260 B21F

oO:~::: 0

B:::21

;::: (\

00290
00300
00310
00320

B823 2E
£825 40

B326 11

Ol~l

:~;:UB

F9
0,;

B829 26 C6

~=JSTGB~

:B!';:~A

!._!;"10D 1. U

:~:UB

jt.l:~
~1

Bsr
NEG A
eMP A
BNE

t (;

ADDED ALL

:~:UB T~:ACT

WMODI0

~VEN

LOCATIONS?
I F 'lE~' ~ GO '~::

;-127
1 (I

KEEP SUBBIN3 UNTIL 0 OR
FORM BINARY FROM 2/S CDMPLE
WSTSBF+l1
MATCH WITH CHK CHAR?
WBAD~D
NO, GO BADP~~D; YE?~ CONTIN

FIGURE 5-1.2.5-11: WERCHK Assembly Listing

5-39

00001

n0 1 0

:t::::i:'I~::

Or-

O(i O':~ 1..1 P:;;;:'D BF C'l 14
0(1 C :: f r::':::; ;..l '::!7. I) 0 n·.;

nH~J1

'.Ii I: C DF i<'

Or?G

~t; B ::; ;=~ i::

i).!,E:r:I'PV :':E I
..::.T·~·
L.D:S:
LD::":
L.D~

.::: A',,.' t: CUF!;~E t·~ r :~::F'
P C I i'i T :S' n< ~~ r F' AC ~::. I t'iI:::; !_I] C
~;l.,J:S:T:::;EF:+ 1
:'3f:: .~: TFT;'i l:;:; AnDP IJ~:'- Uhr-'81~'

!t,I :~. BF AD

:; ~ I: (; 0 I) 4

GET CiJPF'::::r'1'i ODD FeD CHPj:;:'

i)o~)(n

E: ~~ :;;:

.::J. ::~

!='i.::L A

SHIFT ODD

00 n·:: r

~~ ~:~ :-:: '~

,;1- ~:::!

A·~:L.

uPp~p

OOO'~'!

t: :::: :? :=i .:.1 :~:
~;::::3'B 4:::
E;~;':!C A4

0(11)

0011.
001E
(I

n 1'-~'

001.4

0015
001.6
001.7
J (I 1 ::-::
0(11 ':j

(11

E: e :;: F 0 ;::~
0 C':
E:::~41 =::C 0121
:p ;::~ ,:l .::t :: l:, F I).
D'::!4~, BE C1114-~~; ~:; 4·

.F;:~:4'? Of::
S::!41=i .:.:'?

A:~'L A
A.::L A
ArH' A
P·S.H A
I f'i':.:;
I n':.:;
CP;:<
Br'i1::
LD:S:
CL I

C~AP

FDUP B I T:S: OF
CUP~-;:'i::t'~T L.OC ,=iT I 'Jr',!

1,X

PACK CUQRENT EVEN CHAR
PUSH INTO PACKING LOCRTION
MQV~ TO NEXT ADDR
LtJ('A T IOr·{
PACK I ~.~(:; COt'iF'LETE?

:BUFFE~'
~~;t.i:~:TGB;= +

WPAVLP

NO,

CDNTINU~

YES~

R~STOP;

RETU~N

TO E/ECUTIVE

PTS
FIGURE 5-1.2.5-13: WBCDPK Assembly Listing

Save Old S.P. Point S.P.
at Packing location. Get
starting addr of unpacked
data into X.

Get current ODD BCD
Char. from WSTGBF and
move to leftmost 4 bits
of A. Pack EVEN Char.
into rightmost 4 bits of
A. Push A into Packing
Location. Move to next
ODD location and test
for finished

FIGURE 5-1.2.5-12 WBCDPK Flowchart for WBCDPK Packing Routine

540

PACKING
SP AND

printing out supermarket receipts, to the super-machines capable of printing 1200 132-character lines per
minute. The broadest common ground for printers and microprocessors appears to be in the medium to low
speed printing applications.
Medium performance is taken here to include auxiliary printers used with terminals or small
computing systems printing up to a maximum of 200 132-character lines/minute. The gamut of printers
spanning the medium to low speed range includes: electronic discharge printers, thermal printers, chain
printers, drum printers, matrix printers, serial printers, etc., with types and speed ranges available for almost
any conceivable application.
High performance microprocessors like the MC6800 provide an efficient means for controlling the
higher speed printers and in the lower speed applications, additional functions can be combined with the
controller function to produce a more cost-effective system.
Designing the microprocessor into the controlling system allows hardware (logic)/software (programming) tradeoffs to be made to satisfy the specific system requirements. For example, in the high speed
printers, additional logic might be required if the desired data transfer rate is to be met even though the MPU is
only used for printer control.
At the other end of the spectrum, using one of the newer high performance MPUs as a dedicated
controller for a slower printer amounts to gross overkill. More often the relationship is similar to that shown in
Figure 6-4. 1-1, a generalized diagram of an MPU based transaction terminal described in Chapter 6. In
applications of this type, the printer is merely one of several peripherals and its control is a relatively minor task
that involves a small percentage of the MPU's attention.
It is in applications such as this that the real value of an MPU shows. They permit the designer to

reduce a relatively complex system to a number of manageable tasks. Service routines are developed for the
various peripherals and a suitable executive control program then ties the system together.
In a typical case, there are several factors to be considered in the development of a peripheral control
routine. The device selected must, of course, satisfy the basic system requirements such as speed, reliability,
etc. Beyond that, some devices of the same class are more amenable to MPU control than others. Some of these
factors are illustrated in the following paragraphs where the development of hardware and software for a
representative low speed printer application is discussed.

5-41

SEIKO AN-IOIF Operating Characteristics

5-2.1.1

A SEIKO AN-I0IF printer was selected as the hard copy output device for the transaction terminal
design described in Chapter 6. The SEIKO AN-I0IF Printer employs a continually rotating print drum
mechanism using what is referred to as the flying printer technique. The printing principle of the mechanism is
indicated schematically in Figure 5-2.1.1-1.
The print drum and the ratchet shaft are geared together and rotate continuously in the direction
shown. During a non-print condition, the right end of the trigger lever is removed from the ratchet's pawl locus
by the downward force of the trigger lever spring. In the non-printing condition, the trigger magnet is not
actuated and the hammers are lifted upward to a neutral position by the hammer lever springs.
When actuated, the trigger magnet's actuating lever forces the opposite end of the trigger lever into
the locus of the ratchet pawl. During its next rotation, the pawl will engage the right end of the trigger lever
causing a downward motion to the right hand end of the hammer. The hammer thus strikes through the inked
ribbon and paper, causing the character then under the hammer to be printed.
Hammer Lever Spring

Paper

FIGURE 5-2.1.1-1 SEIKO AN-101F Printing Mechanism

Trigger Magnet

Hammer

~ Trigger

Lever Spring

Trigger Lever
Trigger Lever Guide

~--------~,nked
V-J:J-I

Ribbon

P,pe,

Characters
'~!Ir----

Print Drum

FIGURE 5-2.1.1-2 Timing Signal Generation

Detecting Wheel T

---+--tt--Detecting Wheel R
.'~

Ferrite Ch ip

_____ Detecting Head R
TLO

TP1

Timing Signal

Ratchet Shaft

Reset Signal

\J Ferrite Chip

-----t--------FIGURE 5-2.1.1-3 Timing Signals

5-42

Any of 42 characters (alphanumeric plus special characters *, $, " -, ., and /) may be printed in a
21-column format. Each column position has a complete character set spaced evenly around the drum. Because
of a 42: 1 gear ratio, the ratchet rotates 42 times for each complete drum rotation. Hence, each character of the
set is positioned under a print hammer once during every rotation of the drum.
From this brief description of the printer mechanisms characteristics, it is evident that the control
circuitry must actuate the hammers at just the right time if printing is to occur. Timing signals are generated
electromagnetically by means of detection heads and ferrite magnets associated with the ratchet shaft and drum
(See Figures 5-2.1.1-2 and 5-2.1.1-3).
Rotation of the ratchet shaft generates signals TP and TL for each of the 42 characters. TP provides
timing for energizing the trigger magnets, TL for de-energizing. A reset signal R is generated by each complete
rotation of the drum. The resulting waveform for a complete drum rotation is illustrated in Figure 5-2.1.4-1.
5-2.1.2

Printer Hardware/Software TradeofTs
It is at this point that a designer must start considering trade-offs in order to arrive at the most

effective design. A suitable peripheral device has been selected and its characteristics have been studied. In this
case, the manufacturer provides a suggested controller design that can be implemented (exclusive of Trigger
Magnet drive circuitry) with 16-20 SSI and MSI integrated circuits. If this approach is adopted, the MPU
merely monitors status and transfers data bytes to the controller at the proper time.
At the other extreme, the MPU could assume as much of the control function as possible and
eliminate all of the external conventional circuits. When overall system timing permits it, this is usually the
most cost effective approach.
There may be reason to adopt some intermediate approach. For example, a sixteen column format
was required for the application described here. The required information for identifying one of the sixteen
items can be handled by four encoded bits. The design could have been implemented using 4 PIA data lines and
external decode circuitry. However, it was decided to assign each column its own PIA data line, using up the
data capability of one PIA but requiring little external circuitry (See Figure 5-2.1.3-1). Had there been four
"spare" PIA lines elsewhere in the system, the alternate approach would have been given greater consideration.
As a further consideration in the trade-off area, note that while only 16 columns are used in this
design, the AN-IOIF has 21 columns available. If all 21 were to be used, the designer could decide between
using five more PIA lines as opposed to an external 5-bit shift register. Unless there happened to be 5 "spare"
PIA lines somewhere, the relative cost would probably dictate using the shift register.
Selection of a particular configuration is, of course, not made in pure hardware vacuum. Knowledge
concerning the MPU's capability to handle the control problem heavily influences the method that is finally
selected.
5-2.1.3

Printer I/O Configuration

As is generally the case with MPU based designs, there are numerous ways to solve a given problem.
The method to be discussed here was selected to satisfy three basic objectives: (1) Use minimum external
electronics; (2) Use the timing signals provided with no additional external processing other than pulse shaping;
(3) Minimize the time in which the MPU must be involved with printer control activity. The hardware
configuration selected is shown in Figure 5-2.1.3-1.

5-43

1.2K
+5

5K
'III

CB1
CB2
PBO

VV~

H:>-

PB1

1.6K
AAA

L[>r[>r-

PB2

-.-.

MC74452

H-

MC74452

~--O

--....

PB4

PB5

-.-.

~.-

PB6

---- >
-..
---...

PB7

.......-

PAO
PA1

PA2

r-O

MC74452

........

PA3

MC74452

.
~

PA5

........

-....

PA6

PA7

CA1

I---

...

'....,
""

CA2

1/6 MC7404
(4 Places)

'III

1/4 MC3302
(2 Places)
620

~~
A

vvv

5K
1.2K ~

•

:~
+5

To Hammer
Magnets

---

PA4

....

--..

PB3

MC 6820
P IA

MC74452

Timing

Paper

rc-s

-:.!::-

-..

'III

Ribbon

Reset

>
1.6K

.
~>

>
>

-::i- _L-

FIGURE 5-2.1.3-1: SEIKO Printer Circuit Requirements

544

As indicated in the earlier discussion of hardware/software trade-offs, each hammer driver is
controlled by one of the PIA's sixteen data lines. These lines are the outputs of Registers ORA and ORB in the
PIA which are regarded as memory locations by the MPU; hence, the MPU can enable the activation of a
particular column hammer by setting the appropriate bit position in the memory locations assigned to ORA and
ORB.
During initialization, CB2 is established as an output and is used by the MPU to strobe the enabled
hammer drivers at the proper time. At the end of a print cycle, the printer's paper and ribbon must be advanced.
This requires a 36 msec pulse which is generated by the control program and is applied through CA2 which is
also established as an output during initialization.
After being shaped and inverted by the MC3302 Comparators, the printer timing and reset pulses are
applied to the CB1 and CAl inputs, respectively. It is by means of these signals and the MC6800 interrupt
structure that the Printer' 'tells" the MPU it requires servicing. Part of the printer control program's function is
to establish suitable interrupt modes using tfie PIA Control Registers.
As an example, in the control sequence described below, negative transitions on the CB 1 timing
input during a print cycle must cause the MPU to service the printer. The MPU sets this up by writing bO= 1 and
b1 =0 into Control Register B during initialization. The subsequent timing transitions then cause the PIA to
issue an Interrupt Request to the MPU via the system IRQ line.
The MPU responds by interrupting its current activity (the MPU's internal registers are saved on a
"stack" so that the task may be resumed later) and fetches the starting address of an executive service routine
from a memory location permanently assigned to the Interrupt Request. The service routine directs the MPU to
"poll" its peripherals by testing the flag bits in the PIA Control Registers to see which one needs servicing.
Flag bit b7 of the printer PIA's Control Register was set by the same transition that caused the interrupt. When
the MPU finds this flag set, it jumps out of the polling routine to an appropriate printer control program.
5-2.1.4

Printer Control Program

The basic task, or algorithm, of the control program is to examine the text of the message to be
printed and make sure that the appropriate bits in the PIA's Output Registers, ORA and ORB, are set at the
proper time. The details of timing and program flow are shown in Figures 5-2.1.4-2 through 5-2.1.4-7.
Understanding of the operation is aided by regarding the time for one print drum rotation as
forty- two equal intervals, to through t41. With this in mind, note that all similar characters in the text are printed
simultaneously, i. e. , all 0' s are printed during tj), alII's during h, etc. For example, if the text requires the letter
C in columns 3 and 9 (as in Figure 5-2.1.4-1), column hammers 3 and 9 must be engaged during the time
interval t12 during which all C's are under the hammers.
Following each "TL" interrupt, the MPU examines the entire message to see if there are any
characters to be printed during the next time interval. The text to be printed may be either a "canned" message
stored in ROM or variable information generated by the executive program and stored in RAM. Messages are
stored in memory in 16-byte blocks with each memory position corresponding to a printer column position.
Prior to calling the printer, the executive program loads the starting address of the message to be printed into a
buffer. The printer routine then uses this address in conjunction with the MPU's indexed addressing mode to
locate the desired message; this technique permits using the same subroutine for all of the system printer
requirements.

5-45

Reset

U
,....

""f-

....J

Timing

JJ
o

,....

....J

t""'-

....J

•••

""f-

M
....J

....J

I II II II II II II II J~ I II II II c II II II II II II II II II II II II o II II II II s Ilffll II II II II II
- .1 /1
1M
~t:~2
----t
3

,....

....J

(j)

•••

Jf
o

t41 , . -

2
3

I 7

III

.l::.

I I

roc::
Ul

---------'n

I I

C'l

U5
'-

"10

I
c::

::J

(5
U

n~~I~I

__________________________________
R

15
16
FIGURE 5-2.1.4-1 Print Cycle Timing:

"Microproce~or"

~n~

____- -

________

PKIPRT

Set PI A I nterface Reg's
as outputs. Disable hammer
strobe and paper ribbon
feed control lines. Set PIA
Interrupt Masks

RTS = Return from Subroutine
R = Reset Timing Pulse

(a)

00280
00:300
00310
00320
00:330
00340
00350
00360
00:370
00380
00390
00400
00410

7C4C
7C4F
7C52
7C53
7C54
7C57
7C5A
7C5C
7C5F
7C62
7C65
7C6S

7F
7F
4F
4:3
B7
B7
86
B7
B7
B6
F6
39

•• INITIALIZE
8009 PKIPRT CLR
800B
CLR
CLR A
COM A
8008
STA A
:;TA A
eOOA
3C
LDA A
800';'
:STA A
BOOB
STA A
8008
LDA A
SOOA
LIlA B

PRINTER PIA
XPICRA
~-~T FOR FIRST CHAR DR MAKE PPR/RBN FEED
CLR INTRF'T AND FLAG
PRNTIR LDA A XPIDRA
LDA A :X:PtC~:A
TEST IF CAt POS OR tiEG
BIT A ~~$02
Il"iTRPT
BEQ
NEG, GO INT"L SCAN LOOP
PKSCN1
TRUE, PPR/RBN FEED
LDA B ~;$3C
~~:P1CRB
STA B
DISABLE HAMMERS;INTRPT MASt8.0 ms

....

R>10.0 ms

1
2

PRINTIR active· Enables interrupt by TL41.
PRNTIT active

1
2
3
4
5

PRINTIR
PRNTIT
PRNTIT
PRNTIT
PR INTI R

active
active
active
active
active

Enables interrupt by TL41.
Selects hammers to be engaged at PTO.
Enagages selected hammers.
Disengages hammers and selects hammers to be engaged at next TP.
Terminating the print cycle; then performs a paper/ribbon feed.

FIGURE 5-2.1.4-5 Printer Loading of MPU Activity

lK'- \

ir--4A7?Til
~

PRNTIT

Clear Previous
R Interrupts
Unmask CA1

Store Character
File Pointer in
the I ndex Reg.

Print Characters under hammers (CB2 low,
back high on
next TP/TL Int.)

PKSCAN
(Figure 16)

RTI = Return from Interrupt
R = Reset Timing Pulse
(a)

870

880
900 7CB3
910 7CB6
920 7CB9
9:30 7CBB
940
950 7CBD
960 7CCO
970 7CC2
980 7CC5
990 7CC7
1000 7CCA
1010 7CCC
1020 7CCF
1030 7CDO

F6 800A
F6 800B
C5 02
27 13
B6 8008

86 3F
B7 8009
C6 25

F7
D6
F7
3B
DE

SOOB
DA
aOOA
D7

•• INTRPT VECTORED HERE IF CBl INTRPT
•• PRINT CHAR UNDER HAMMERS DR SCAN TEXT
PRNTIT LDA B XP1DRB
CLR INTRPT AND FLAG
LDA B XP1CRB
TEST IF CBl IS A P~S
BIT B #$02
DR NEG INTRPT
BEQ
PKSCN2
NEG, GD SCAN
•
POSITIVE, PRINT
LDA A XP1DRA
CLR PREV RESET INTRPT
LDA H ~~$:3F
SET CA 1 TO I NTRPT ON NE>Cf
STA A XP1CRA
POS TRANS DF RESET PULSE
LDA B ~~$25
PF:INT CHAR tUJW UtiDER HAM.~
STA B XP1CRB
CB2 LOW, HI NEXT NEG CB
LDA B BF1DRB
GET SIDE B OUTPUT INFO
STA B XP1DRB
STORE IT AND START PRINT
RTI
RETURN - WAIT FOR NEXT
PKSCN2 LDX
PVXBFR
LOAD CURRENT CF POINTER
(b)

FIGURE 5-2.1.4-6 Print Service

5-53

Again the first thing done is to clear the IRQB flag and the IRQ line by reading ORB (XP1DRB).
Then lines 910- 930 test b1 of CRB to determine whether the CB 1 input was positive or negative edge sensitive.
(A) If bl = 0, CB 1 was a negative transition and the program branches to PKSCN2 (line 1030)
which loads the index register with the current character file (CF) address pointer. The scan loop follows and
will be discussed later.
(B) Ifbl = 1, CB 1 was a positive transition, i.e., a TP timing pulse. This means that the hammers
must now be strobed. Before this is done, CAl is cleared and enabled (lines 950- 970) to allow the next positive
reset transition at CAl to signal the end of the print cycle. The hammer strobe is then armed to be set low on the
next write in ORB by storing #$25 in CRB (lines 980 and 990). This combination of b3, b4, and b5 also returns
CB2 high on the next CB 1 interrupt at TL. The 8 data bits set by the previous scan loop for the B side outputs are
then stored in ORB (lines 1000 and 1010) causing CB2 to go low. The strobe inputs on the driver AND gates go
high activating those hammers whose data lines have been set high.
Line 1020 returns control to the place the interrupt occurred. The scan loop, PSKCAN (Figure
5-1.2.4-7), is the actual data processing section of the program. The column counter (Accumulator B) is
cleared and the current character file character stored in the test buffer (lines 1410-1430). The next character
file character address is then stored (lines 1440-1450) for initializing the next loop. The first text character
address is loaded into the index register before starting the scanning process.
The first instruction in the actual loop (line 1470) compares the column count with #$10 (decimal
16) to see if the last text character has been checked. If it has, the program enables an interrupt by the next
positive timing pulse transition (lines 1490-1510) and returns control to the executive program. If the last
character has not been tested, the program branches to PVNXT1. Line 1520 loads accumulator A (ACCA) with
the text character corresponding to the present column counter value. This is then compared with the current
character file (CF) character (lines 1530 and 1540) with the carry bit being set if they match (line 1550), cleared
if they don't (line 1570). The carry is then saved by the TP A instruction so that it will not be destroyed by the
following test. Lines 1550 and 1600 determine which output register is to be operated on. If the column count is
;?;8, ORA; if <8, ORB. In either case the carry bit is restored by the TAP instruction (line 1610 for side B, 1640
for side A) before it is shifted into ORA or the ORB buffer, BFIDRB, using the ROL instructions on line 1620
for side B and line 1650 for side A, (since a write into ORB is required to activate CB2, the data is stored in c;t
buffer until time for hammer activation). Figure 5-2.1.4-8 is the schematic representation of the ROL
instruction. As the scan progresses, the bits are shifted from right to left. At the end of the loop, the bits
representing the character to be printed will be shifted into the position indicated in Figure 5-2.1.4-9. When the
shift has been completed, the column counter and text address pointers are incremented (lines 1660 and 1680),
then a branch is executed to the start of the loop.
The control operation just described might appear at first glance to be a slow and cumbersome
approach. However, it should be kept in mind that during an actual print operation, less than 4% (30 msec out of
850 msec) of the MPU's capability is used.
This combined with the fact that only twenty conventional integrated circuits are being replaced
seems to indicate that the control of printers of this class is a trivial task for high performance microprocessors.
The proper perspective in this situation is to remember that the MPU is controlling 7 -1 0 other peripheral
devices while also performing the executive function and that the control of the printer is accomplished with a
minimum of additional expense in hardware (200 bytes of ROM) and engineering development time.

5-54

PKSCAN

Zero Column
counter. Store
CF character in
test buffer.

Increment CF
pointer. I nitializ·e text
char. pointer.

Store text
char. in ACCA

Set PIA for
interrupt on
next positive
transition of
TL/TP

SIDE A (ACCB ~ $08)*

SIDE B

Shift Carry into Side A Data
Register
ORA

Shift Carry into side B Data
Buffer

CF = Character File

$ I ndicates that a
hexadecimal number
follows.

Increment column counter.
I ncrement text
char. pointer.
(ACCB+1)

FIGURE 5-2.1.4-7(a): PKSCAN Flow Chart

5-55

01 ::::'3 0
01410
01420
01430
01440
01450
01460
01470
014:::0
014'30
01500
01510
01520
01530
01540
01550
01560
01570
015:::0
01590
01600
01610
01620
016:30
01640
01650
01660
01670
01680

E:'3 !::::
B'3E:9
B9f:E:
B'3I:E
B'3BF
B'3C2
E:'3C5
B'3C7
B'3C'3
B'3CB
B9CE
B'3CF
B'3II1
B9D4
H'3I16
H'3II?
B'3II9
B9DA
B9I1:B

B9I/D

••

CL~~

I:
LIlA A
STA A
I t·~::-::

RE- 00
:E'7
'I

012:~:

FF 0121
FE 011F
C1 10
2':, 06
86 3F
I'''''
'I' COO.E:
3I:
A6 00
H1 012:~:
26 03
OIl
20 01
OC
07
C1 0:::
2C 06
06
79 0124
20 04
06
7'3 C008

B'3I1F
E:9EO
B'3E3
B9E5
B'3E6
B'3E'3 5C
B'3EA I)::::
B'3EB 20 ItS

TE::-:~T

SCAt-.,

PK:S:CAt-~

PKCLOP

P\,IN>::T1

P'",'N::-::T2
P I".'N;:':: T3

P'·/~i;:'::T 4

FOP CUPPEt-iT CHAP At-iD SET OUTPUT L
2E~~O COLUI'1t-1 COUt-iTE~~

>::

CHAP

PI·/CFI:F

STO~~E

sr::-:;

p'·/;:'::BF~~

LII::-:;
Ct'1P
I:t'iE
LIlA
STA
J;~T I
LIlA
Ct'1P
Ht-iE
SEC
BPA
CLC
TPA
Ct'1P
BGE
TAP
POL
BPA
TAP

F I...' T::-:;BF

STORE t-iE;:';:T CF AIIIIPESS:
GET TE::-:;T CHA~: AD"DPES-S:
HA:S: LA:5:T TE::-:;T COLUt·1t·i
BEEt.., TESTErl
SET CI:1 TO !t,.,TPPT ON t-~E;:-:;T
PDS: TPAt'iS' OF T I t'l I Nt:; PUL:S:E
..,.'ES: !I PETupr·.,
:0 ••
'S:TOPE T·····
CHAP In liCCA
DOES TE;:'::T f'lA rCH

~~$1 (I

PI,lN::

}

TRUTH TABLE

FIGURE 5-2.2-1: Burroughs Self·Scan Display Characteristics

:#
$

39
40
41

'i-'.

(BLANK)

G
H

CHAR.

13
14
15

DATA PRESENT
CONTROL
CIRCUITRY

CHAR.

-..

Pin 15

Pin C

Pin 16

Pin 3 _

Pin 17

Pin B _

Pin 18

Pin 2

PBO

B4 (2)

PB1
PB2

B2 (8)
Pin 19

Pin 1

Pin 20
PB5
PIA

Pin 21
PB6

Pin 22

CB2

Display

B1 (16)
BO (32)

Pin E _

PB7

CB1

---

Pin A_

PB4

B3 (4)

PB3

B5 (1)

Pin 5

.-.

Pin 23

Pin F

Pin 24

Pin 0 _

Backspace
Clear
Data Taken

Data Present

Pin 4

Pin 10 Pin J

Pin L

-'-

-12V +250V +5V

FIGURE 5-2.2-2: PIA/Burroughs Display Interface

5-59

}

(CR)
Formatting for printer
(LF)
readability; ignored
(NULL) by leader
S = Start-of-record
CC = Type of Record

Frame
1
2
3
4

5
6
7
8
9
10

~
53
CC

....0

(/)

.:,t.

*...

J::

0
,....

(,)

>co

!tI

Leader (Nulls)

}

Byte Count (two frames =
one byte)

}

Address/Size

}

Date

}

Checksum

Frames 3 through N are hexadecimal digits (in 7-bit ASCII) which are converted
to BCD. Two BCD digits are combined to make one 8-bit byte.
The checksum is the one's complement of the summation of 8-bit bytes.

Frame
1. Start-of-Record
2. Type of Record
3.
4. Byte Cou nt
5.
6. Address/Size
7.
8.
9.
10. Data

CC = 31
Data
Record

CC ~ 30
Header
Record

2L
~
31

.2L
30
30
30

S
0
12

0000

~
34

~
35

.-R-

31
31

-1L
31
31
30

48-11
44-0

--52-R

39
38
30
32

ffi
48

N. Checksum

2L
39

-2L

1100

-1SL

~
34

-2L

CC = 39
End-of-File
Record

30
30
30
46
43

0000

FC
(Checksum)

A8 (Checksum)

Head of Record

5-60

.2L
98

FIGURE 5-3_1-1: Paper Tape Format

S
9

TELETYPE

I--

TTY
Current
Interface

MPU
SYSTEM

ACIA

I . ..I
PIA

I
TTY to ACIA System

6-TELETYPE

TTY
Current
Interface

MODEM

FIGURE 5-3.1-2 TTY/ACIA and MODEM/ACIA Systems

I . . .I
Burroughs Self Scan

MC1489A

r---------,

r---------:--D---i--------,
r--------i----D---:-------j
I

I
MC1488
I
L _________ ...J RS232C

r------

I
:

-------,
4N33

20m A

+12

Rx Data

MPU
System

RS232
Common

ACIA
Tx Data

L_~ ______________ ~ ~

1..L
, -=Serial In

TTY

-vJ

+12

V~-I

-12

Serial
I,
Common

4N33

I
I
I

1.2 k

,I
-12 V

r---------------------------,I

4N33

I
I
I
I
I

+12

I
,
I
,
I

____________~I~~

I
I
I

IL ___________________________
Relay Driver
I
~

FIGURE 5-3.1.1-1 MPU to TTY Interface

5-62

Reader Common

are teletype requirements. The manual paper tape reader requires an externally provided relay to turn the reader
on and off via the ACIA. For the system shown in Figure 5-3.1.1-1, the Request to Send (RTS) output of the
ACIA is used to control the relay; the RTS output is normally used for interfacing to a modem. There are
separate data lines for serial-in and serial-out data transfer from the teletype which connect to the transmit data
output and receive data input of the ACIA via the interface circuits. The current/voltage options for the serial-in
and serial-out data lines of the teletype are (1) 20 rna, (2) 60 rna, or (3) RS232C. Typical interface circuits for
options 1 and 3 are shown in Figure 5-3.1.1-1. The 4N33 optical coupler can provide the 20 rna requirement,
and the MC1488 and MC1489A line driver/receiver provide the RS232C specifications. Communication
between the teletype and other devices is accomplished with an asychronous data format. This format requires
that the data bits are preceded by a START bit (space) and followed by 1 or more STOP bits (mark). The
teletype requires a minimum of 1~ STOP bits for completion of mechanical operations within the teletype.
5-3.1.2

TTY To ACIA Software

The flow diagram and assembled program for the communications routine are shown in Figure
5-3.1.2-1 and 5-3.1.2-2 respectively. The shaded areas in these figures represent requirements for using a
modem and therefore would be deleted in a program that does not utilize a modem. Referring to the assembled
program and flow diagram, the internal power-on reset of the ACIA is released by master resetting the ACIA
via the control register. Then, the control register of the ACIA is set for word length, parity, etc. If at any time a
power-fail occurs, these two steps must be repeated to initialize the ACIA. Next, in lines 150-200 the PIA is
initialized to receive data from the MPU System and output this data to the Burroughs Self-Scan display.
Line 240 turns on the teletype by the control character" DC 1. " If a relay is being used to tum the
reader on instead of a control character, the RTS output of the ACIA could have been used to control the relay.
Line 260 initializes a memory location that stores error conditions from the data that is received.
Lines 280-370 ignores all data that is on the tape until an S 1, S9, or S8 indication is 'found. An S 1
indicates a data record as shown in Figure 5-3.1-1, and the following is performed on the data record in lines
400-590. The memory location for accumulating a checksum is cleared. Next, the number of bytes in the data
record (minus two for the byte count) is stored in memory. The next four bytes on the tape represent the
beginning address for the data and these four bytes are loaded into two consecutive addresses. Line 480 loads
the X register with the two consecutive addresses making a 16-bit address.
In lines 520- 590 the remaining data in the record is stored in consecutive addresses beginning at the
address specified on the tape. A byte count of zero indicates the end of the record and the checksum is checked
for a data error indication. The final checksum is generated by adding the accumulated checksum to the
checksum (1 's complement) at the end of the record and incrementing the total by one resulting in all zero's
with a carry. If the checksum does not equal zero, the error memory location is loaded with a one at line 580.
The remaining data records are handled as above until the end of file (S9) is read. Then, at line
600-620 the error memory location is checked for an error indication. If an error was stored in this location, the
routine looks for a duplicate of the message on the tape and processes data as before. If data is read into the MPU
without any errors the tape reader is turned off by a "DC3" control word at line 680. Again, if a teletype with a
relay is used, the RTS output of the ACIA could be used to turn off the relay. In lines 810-970 the data is
fetched from memory and displayed at a program controlled rate on the Burroughs self-scan display.
The input and output of characters through the ACIA is done by the subroutine contained in lines
980- 1300. Beginning at line 980, the status of the receiver data register is checked until a full condition exists.

5-63

Mast~r

Reset
ACIA

Load Accum B

FIGURE 5-3.1.2-1 Flow Diagram for Comm. Program
(Sheet 1 of 4)

5-64

Yes

Load Accum B

Yes

FIGURE 5-3.1.2-1 Flow Diagram for Comm. Program;
(Sheet 2 of 4)

5-65

FIGURE 5-3.1.2-1 Flow Diagram for Comm. Program
(Sheet 3 of 4)

5-66

Return to
Executive

FIGURE 5-3.1.2-1 Flow Diagram for Comm. Program
(Sheet 4 of 4)

5-67

000'50
00060·

~=:c:

00
:::;::~ I) 1

eCl 00

(lOt}70

:::('2:::

F'I Ai::

:=:O2!~

PIAnI

000:3 (I

000'30

ee1

o;~oo

Oc~ o;~

p-'

._1 (

:::;:: (I

.Et"iT~P

CI< 140

001 .30 Ot~ (:5
001 40 (I~:' 07
00150 020A
001 60 020C

::::i:, 149
!::2Ci C!
'E'"
'I
;:::E, .=.'-:'
i..-._'

00170
001::::0
00190

!::~I

OOl':~OO

CI~OJ;:'

OE~ 1

BEi

02C4 Ct<2E·j i

C' ;:~ ,:;~, ;:~ ? .::; F
=IE3;:; ::! 1 31
023A 27 n8

1 .39

00350
00360 023C 81 38
(10:3 {O (!;=~3E ;~6 EA
003'30

0;::40 CEo
O.::4;::~ ':'0

04
:ii_

ACIADA
PIA

~~:!;.E'

eel 00

MASTER

LItA A

eel 00

PESEr~RTS=O

~~'t;H9

:~:TA

l)2;:4

:::TA "i
LIlA i=i
STA A

LIlA

riCIACS

$,~OO

PDI"JEF.'

e02J

(11)'31:: I)

I) !)'3;::: I)

:1;;:: o;:~;~

;~~c

e (1:::2

I) I) .,:;: '=~:

(10::;::4 (I

EOU

(I ~~ ::::

F'IAC

00::90 022D 81 52
00300 022F 26 ~9
00310 0231 ED 02C4
Ct

~I; !::

::TA A
LIlA A
STA A
LDA A

00250 0222 B? 8201
0;::,::'5 :::~, u u
CK;::54
00270 0227 B? 0328
OE'c~A

EG!U

::~'f;;:: .3

(I O!~6 (I

C02::: 0

$::::20 (I
CC 1 00+1

, ....., ::: 02;:
c· ..

1 B?

O~='l4
o~~ 16

EOU
EOU
O~'G

001 00
001 1 0 0200 ::;t=:t B::':

(10 1 c~o

1 (I

~~$i="F

PlAT! I
~~'f.;;~C

PIAC

CeltO

IHITIALIZ£ ZEF'G

L.IIA Fi
.::TA

-' .~:~.

1--1

Cl"lP A
Hr'·ir
J:S'!:;:'
l:r'iF' A

'tr

....

BEO
C r'1 r:':=1

Ck: 7

BE9
i:: 1'1 F' A
HriE

CK :~:::;

L DR

.BF~A

' • 1.
·r

~::

Ct<26 n
::~14

'::K?4 I)
'~:k:.:::,:~: III

00410 0;::47 E:D

f!,~ (i!

(I 04,=~;)

CI<'3nnn

SUB H

004::n
004,4 i
(1045 :)

~'TA

J::'4t= ID
(I.:? '5 l::~ f:?
n C'4~. n (; ;:: ':1 '5 B II

(I'~ I)

I)':~ '::~3

IJ:: j-i 1

CI 0,-+ .., (I
(11)4;:.

t·::·!,:,

;=t

Ct',. :,,: 1 0

J':'F

:::T ~ f=t
..J ~:~:'
:S:TA :;
LD',::

C/.? '_."

B\'TE f:,iJUr',j T
~~. F. A Ii .::.
t=~. i~' A 1·1 ,::

Ci< .=,.:: :.\.1
cv~::

-:::!..

C~::' ~, ,- ri . i
,=: ~:: '3 !:' 1. C

BEO
I) nSj~:' (I

OE66 A?

II (I

C~:::5:: I!

STA A,"

: T!J!:;:'E DATA

FIGURE 5-3.1.2-2 Assembled Data Comm Program (Sheet 1 of 3)

5-68

00530 026::: OS

I t-i;:':;

00540 0269 20 F3
00550 026B 7C 0326 CK530
00560 026E 27 B~

Br:'A
I r-~c
BEO
LD,=t A

005?0

O;~70

:::6

00580 0272 B7 0328
00590 0275 20 B3
00600 0277 B6 0328 CK700
00610 O~7A 27 02
(:6 (I I)
CV 730
00640 0280 B6 8200 CK740
00650 0283 47
00660 0284 47
00670 0~85 24 F9
00680 0287 86 93
00690 0289 B7 8201
00700 028C £6 8200 CK751
o Ot:,:~; (I

Oc~?E

(10710 O!:::::F 4?
(1072 0 I) i=:"3 (I 4 ?

o(I? 7 (I

~~l

S:TA A

CK.3;::;~ I)

"BPA

CK260

LDR A
BEO

CK?3 (I

C~(3a2

BPA

CK254

LDR:B

~~ I)

LDA A
ASR 8
ASP A

eCl00

Bee

Ci<"74 CI

LDA A

~~'I;9:::~

:::TA A

cellO

LIlA A

ce1'OO

CHECK

DC:;:

A
ASh:' A

Bee

4('
0;:: '3!4 ::1- 7
O!~-~9

CV?51
f~

CCI10

LDA A
fiSF.' A

eCl00

STA

A:::~~

0031 1) (!c:Ai::: :_,1': (I!J (I;) :;::TA~'T
BEl:'; 1.
00820 02A5 C6 4~
T I r'iE~~
00830 0287 8~ FF
(10;::4 C! CL~H'3 ,jp'
Tlt'1El
08850 02AA 26 ~D

oo~::t=, (I

CI<'::I:,O

A:~:F.~

00730 0291 24 F9
00?40 0293 B7 8201
00750 0296 B6 8200 CK756
(I 07~,

Cr<4? 0
CK:;:;:: 0 (I

LD::'::

~~$

LItFl f:

~~l4F

LD~7i A
DEC A

~::t;FF

DEC :B

02t=1C SA

00870 02AD 26 F8

oO':~::: {)

O;~~AI=

(I I)':::.~

OE.'B 1 0::::

i_DR H
I r'1::<
C:j'1P A

::-:~

r'1 ~ >< T

(I (19:: (1 O;:::F.:7 H? e CiC~:~ nE> To Tape Drive

Clock
24 kHz
Clock
12 k Hz
Erase

Strobe
CRC
Enable
Write Data
N.R.Z. (PBO)

~J
I

l---

Preamble

------------~I

Write Data

1111
0
1

If
0

·~I·

Postamble"l

I ""--CRC Data

---+-:"""""f~

FF #1
Output

FF #2
Output
(P.E. Data)
CRC
Shift

Shift CRC

FIGURE 5-3.2.1-4. Write Operation Timing and Format Conversion

Recovered Clock

~------------------------------------~{rr--

Strobe
CRC Enable

________________________________

"- CRC Reg. Reset
CRC Error

Read Data
(PAO)

~r--J

I---

Preamble

-1-

o
Data

~ Check All Zeros

(No Error)

r~f-

l---

Postamble

"-CRC Data

FIGURE 5-3.2.1-5. Read Operation Timing

5-77

The Read data goes to the PIA directly (PAO) while the recovered clock goes to the PIA (CAl) via
the clock selector circuit. The clock selector selects between the read and write clock during a read or write
operation. During a search operation, the gap-detector retriggerable single shot output is substituted for the
read-write clock.
During a Read operation, the CRC Generator is turned on after the preamble has been read and
remains on throughout the data block, including the appended CRC character. At the end of the CRC character
the CRC Error line is examined to see ifit is low (all zeros line out of the MC8503, CRC Generator). If the data
has been read correctly, the line will be low. (For additional details on the use of the CRCC Generator see the
Applications Section of the MC8503 Data Sheet.)
An UNDERFLOW-OVERFLOW Error interrupt is provided in order to abort the current operation
in the event of such an error. The interrupt signal is generated when the MPU fails to either write or read data
after every clock pulse during the write or read operation. The error flip-flop output should always be high. The
normal response to a clock pulse on the clock line (CAl) is to provide a strobe by reading the data and clearing
the flag set by the clock pulse.

Status Signals from Transport and Electronics
The tape transport contains two micros witches , one to sense the presence of a tape cassette in place,
and the other to see if the write protect tab is removed. If the tab is removed, the tape is "Write-protected" ,and
hardware logic disables the write circuitry (the three-state gates at the output of the write flip- flop are turned off,
and the clock to the write flip-flop is gated off.) These two signals are available at the PIA interface, and the
MPU checks them prior to issuing any "motion" commands.
The Available signal from the electronics and tape drive is essentially a ground-loop which checks
whether all of the cables interconnecting the PIA to the electronics and drive are in place. If a cable is
disconnected, the group loop is not completed and a high logic level will be present at the PIA interface.
The EaT/BOT sensor on the tape drive provides a transition when the EaT or BOT is seen. During a
Read or Write Operation, this transition triggers a single shot whose output appears at CB2 and P A 7 of the PIA
(Figure 5-3.2.1-6). The single-shot period is set to a time such that one complete record may be read or written.
If the single shot times out, then it will generate an interrupt to the MPU system via the PIA, and will stop the
tape transport. This hardware controlled stop is a safety feature, and prevents damage to the tape cassette if
there is system failure. Normally, the MPU examines the EaT/BOT line at the end of each record being read or
written. If the EaT/BOT transition has occurred, the MPU will stop the transport (and this will reset the
single-shot). During a Search Operation if EaT or BOT is seen an interrupt is generated to the PIA
immediately. Note that the EaT/BOT signal is used both as a status signal (on PA7) and as an interrupt signal
(CB2). This allows the MPU to read the EaT/BOT status before system operation is interrupted. If tape is at
Clear Leader, then PA7 will remain low when the speed select line (PB4) is at a Search Speed (high).
The Phase-Locked-Loop (PLL) Data Recovery circuit is shown in Figure 5-3.2.1-7. The first PE
transition after Read is enabled sets the First Bit Detector flip-flop, FF2. P.E. Data is clocked into a two bit shift
register (FF3 and FF4) by the PLL clock (Fout). Each time there is a transition on the P.E. data line, a pulse, one
VCM period in duration is generated from the exclusive OR gate tied to the outputs of the two bit shift register.
The VCM also clocks a window counter whose carry-out output (TC

1 during count $F) generates the read

clock which clocks the Read Data to the PIA (PAO). The time during which the Q3 output of the counter is high
(count 8 through $F) is defined as the data window (or data time). If a P.E. transition occurs during the data
window, it is gated through to the Preset Enable (PE) input of the counter, and presets the counter to the middle

5-78

EOT or BOT
xr------------~CB2

Clear Leader

+v
xr------------- PA 7

"1"
"1"

o
C

EOT
BOT
From
Tape
Drive

0----1-----1 C

Hardware
Stop

DelaY 4
Inverters

Auto/Manual--------~

Switch

Stop/Go
Manual {

Speed Rd-Wrt/Search

Fwd/Rev

(PB7) - Stop/Go

Stop/Go

ZOI-----4--------------~

Speed (Rw-Search)
Z11--__~~--------------Di rection (Fwd/Rev)

Auto {
From
PIA

(PB4) Speed Rd-Wrt/Search
(PB5) Fwd/Rev

Y1
Y2

Auto/Manual
Multiplexer

FIGURE 5-3.2.1-6. EOT/BOT Circuitry with Hardware Safety Feature

5-79

Start/Stop Signal
to Drive
(Stop = 1)

"1"
Read
"1" r-_ _ _-.._ _ _ _ _ _ _ _ _ _ _ _....:D:.:a:.:t:::a...:.l...:.n_ _ _ _~

NRZ
Read Data to
PIA (PAO)

Read Ckts.

- - - -,....---------,- 1

Positive and
Negative Pulses
from Read
-----~ C
Comparator

I
I
I P.E.
I
I
I
I
I

Read
Data
F.F.

Data

"1"
Exclusive OR
Output

-1

" 1 " - - -.....-~ 0
FF2
First Bit
Detector F.F.

C
"1"

Read
Enable
Read Clock
To Clock Selector

-----------

..,

-Enable CRC
-Read

Wrt.
Osc.
(12 kHz)

Not in Sync

I
I
I
I

I
I
"1"
IL _______ _

I
I

MC4024

F out

VCM

cf>

Det.

MC9316

TC
Prescaler

I
I
I
I
I

Not-in-Sync
Circuit

---------------,

I
I
I
I
I

_____ ..J

"1"

FIGURE 5-3.2.1-7: Phase Locked Loop
Data Recovery

5-80

Phase-locked-Loop

= 16

x Data Rate (192 kHz)

of the data window (count of $C). The timing diagram in Figure 5-3.2.1-8 shows nominal system operation
after the preamble has been read and the system is in exact lock. If the P.E. transitions occur anywhere within
the "data window", the P.L.L. system will track them and adjust its output frequency accordingly. P.E.
transitions during window-counter counts of 0 to 7 will be gated off because the Q3 output will be low. Thus,
only the data transitions affect the P.L.L. system frequency. For additional details ofP.L.L. data recovery, see
Section 5.4 (Floppy Disk). Additional details on the design of the P.L.L. system are described in Motorola's
Phase Locked-Loop Systems Data Book and Application Note AN-535, "Phase Locked Loop Design Fundamentals." These publications may be obtained by writing to the Literature Distribution Center, Motorola
Semiconductor Products, Inc., P. O. Box 20912, Phoenix, Arizona 85036.
The Not-In-Sync circuit checks to see if a data transition occurred during the data window. (The
circuit is enabled after the preamble has been read, and remains enabled throughout the data record via the
Enable CRC line.) If there is no P.E. transition within the "data window", the Not-In-Sync latch is set. The
Not-In-Sync signal is ORed with the Overflow/Underflow signal, and generates an interrupt to the PIA (on line
CB1).
An Auto/Manual multiplexer (see Figure 5-3.2.1-6) is used to allow tape motion operation either
under MPU or manual control. Manual operation is useful during program and system debugging.
A complete logic diagram of the tape-cassette Read-Write and Control circuitry that was used is
shown in Figure 5-3.2.1-9.

VCM Frequency

P.E. Data
Read Data in
to Rd. Data F.F.
Exclusive
OR
Output
1st Bit

Data Transition

Phase Transition

~1--~--iLl

No Phase
If'Transition

_________

5C "0"
"1"
"1"
rlL..._ _ _ _ _....r1, _ _ _ _ _ _ _ _....r1, ______________________________r-'L-

~~~--_--------------------------------------------------------------------MI£:::
Preamble 1st Bit

~~~~~:

I B 1 C 1 DIE

I FlO 11 1213141516
£.Data Time

03 Output of
Window Counter
Preset I nput to
Window Counter

17 I a I 91 A I B I C 1DIE I Flo 11

~Phase Time

7 I al91 A I B I C I

t--- Data Window~

--11

r""1.-

Carry-Out
Window Counter
(Ref. Input
to PLL)

Prescaler
Carry-Out
(Feedback
Input to PLL)

Rd Data
NRZ to PIA

12131 4 151 61

.1_

"1"

FIGURE 5-3.2.1-8. Read Data Recovery Timing (After Preamble, with Loop in Lock)

5-81

--D

(PA7) ....~-----------------,

.....1-'1

EaT . ._

.-----(1)

indicates signals to sheet 2

D-- indicates signals from sheet 2

BOT . . . . .---11-"'-

(2)

,..------t-+---(3)

(CB2)

(4)

(5)

(6)

Man.
Auto/Manual (0'1)

(7)

Auto

Stop/Go (1/0)

(8)

(PB7)

RW/S,ch
(PB4)

(9)

(PB5)

Fwd/Rev

RW/srch
Stop/Go
(PB6)

Wrt
(PBO)

Data

Cas. Ad. Data
(PAO)
(PB1)
+5
(CAl)
(PAl)
Wrt. Protect
(PA5)
(PA6)
(PB3)
(CA2)

(PB2)
Overrun/Underflow
(CB1)

(PA2)

Not in Sync (1)

(12)

FIGURE 5-3.2.1-9: Cassette Serial ReadIWrite and Control Logic (Sheet 1 of 3)

5-82

(1)--------------------------------------------------------------------------------,
(2)--------------------------~~----------------------------~--~~
(3) -----------------------------=t----,

(4)
(5)

(6)

(7)----------------------------------~

(8)------------------------------------~

o01

1'F

47K

(9)

"1"

~--------~ Cassette Read Data

(10)

+-------+------,

(11) - - - - - - - - - - - - - - - - - - - -....

(12) - - - - - - - - - - - - - - - - - - - - - -.....

FIGURE 5-3.2.1-9: Cassette Serial Read/Write and Control Logic (Sheet 2 of 3)

5-83

36K

A
B

+24

D--

indicates signals

frOfTl

sheet 1

270n
indicates signals to sheet 1

FIGURE 5-3.2.1-9: Cassette Serial Read/Write and Control Logic (Sheet 3 of 3)

5-84

...llr----------------------------------

·
Read/Write
(PB1)--IIr

Read

M~~~~~~~~7)

Stop

Pinch Roller
Disengages

~_---------------------------0"""'"""!...-:t=-+---Pinch Roller

r--<-r'

---,L._G_O........

~f>'i Pinch
R~~~;fle ~ Pinch Roller I_ _

Roller Engages

Engagement +~
Tape Accln.
Time
\..
Jt... Tape up to Speed

CRC Enable - - - - ~-I~L.I
(PB3)
=-

Read
Preamble

~ Disengage Time

•
~
I

'(..!... Read Postamble

Check for Data Accuracy \..
CRCError(PA1)
,

___________________...I.--------

,} r---- '

Data Recovery Circuits Synchronized

R(~~~ra-------.,iJIIDJJIDJI01Z7JOJJZDZDJII1ZTJlZfLZl£0.1I.IJl]lJ

Valid Read Data
to MPU
Pinch Roller Engage/Disengage Time = 30 msec
Tape Acceleration Time = 20 msec
:. Tape up to Speed 50 msec after start motion command

FIGURE 5-3.2.1-10. Read Operation Sequence Timing

For MPU controlled operation, the Auto/Manual switch is placed in the Auto position. Tape Motion
and Read/Write functions are then controlled via the PIA interface. For example, if it is desired that the tape be
moved forward at Read/Write speed, the interface at the PIA must be set to:
Data Reg. B

FWD RD/WRT
where X denotes a "don't care" condition

e.g.

If the binary word 00100000 is present at the interface, then the tape will move in a forward direction

at Read/Write speed. Similarly if the binary word 00000000 is present at PBO-7, then the tape will move in a
reverse direction at Read/Write Speed.
Examples of other basic tape motion commands are shown below:

Operation
7

Required PIA Word
6 5 4 3 2 1

STOP

X X

Motion-Fwd-RD. WRT .SPD.

X X

Motion-Rev-RD. WRT .SPD.

X X

Motion-Fwd-SEARCH SPD.

Motion-Rev-SEARCH SPD.

X X

HEX
EQUIV.

Example
5 4 3 2

X X

0
0
0
0

X X

OA
3A
lA

For a typical read operation, the MPU issues a sequence of commands to the circuitry via the PIA.
The sequence may be depicted by the timing diagram of Figure 5-3.2.1-10. The tape motion command initiates
motion in the forward direction at Read/Write Speed. The MPU then allows sufficient time for the pinch roller
5-85

to engage the capstan and for the tape to come up to stable Read/Write speed. The MPU next reads the preamble
(by counting eight P.E. transitions) and then enables the CRC generator. It is assumed that by this time the
P.L.L. read circuitry is in lock and has begun to successfully track the data rate variations. The MPU begins to
transfer data in bit serial form to the Read/Write Data Buffer in the MPU system. If any read errors occur due to
loss of synchronization in the P.L.L. circuits or due to overflow, the hardwired logic generates an interrupt to
the MPU system via the PIA.
In the description of the above sequence, only the PIA B side interface operation has been discussed.
Typically, the MPU performs other operations, such as initializing the PIA so that it can communicate with the
read/write and control electronics; checking to see if the tape drive is available for the desired operation;
enabling the EaT/BOT and Read Error interrupts; and using an Interval Timer to generate the required delays
for allowing the tape to come up to speed. These additional operational details are discussed within the software
documentation.
The Write operation sequence is illustrated in Figure 5-3.2.1-11. Tape motion is started in the Erase
mode, and a start-gap is written. The Start-Gap duration is slightly longer than the total time it takes for pinch
roller engagement and for the tape to come up to stable speed. The MPU then disables the Erase mode and
enables write data to be gated to the P.E. write circuits. After the preamble word has been transferred, the CRC
is enabled (so that it accumulates the checksum). The CR C remains enabled till the data from the MPU has been
transferred. Next, the CRC is shifted out to the Write circuitry followed by the postamble word from the MPU.
The MPU then issues a stop command and allows the stop-gap to be written by keeping the write current on until
the tape stops. At this time, the tape drive is placed in a Read-Forward Mode (PBl = 1; PBS = I;PB7 = 1) ifno
other records are to be written.

Start, Stop, and Interblock Gaps
An Interblock gap is defined as the distance between two successive blocks of data, and it is
specified by the A.N.S.!. specification, referenced earlier, to have a nominal length of20.3 mm (0.8 in) with a
minimum length of 17.8 mm (0.7 in) and a maximum length of 500 mm (19.7 in). Any gap in excess of 500 mm
(19.7 in) is considered to be end of data.
From a study of the tape drive specifications, a tape motion velocity profile may be generated (see
Figure 5-3.2.1-12) and used to calculate Start, Stop, and Interblock gap lengths. With reference to Figure 8,
note that tape motion begins 30 msec after the motion command is issued and reaches stable speed 20 msec

Read/Write

:a~i~n
(PB7)

Write Data

Read
::::1

Write

~L:""_-G_O-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-......
-.:_-_---i-+-___
j'"

Tape up

' I I ' !O Speed

Ena~~CRCSh~t~:
~--------------------~~
(PB6)

F;:~i

l... ;:;:r====

Shift
: CRC :

Erased
Tape

CRfp~~)ble,

wr:~eB~ta

i4-- :

Startgap

;

IN\."\tffiSill~~~'Ds\'\'''~"\'~"\'\'~~~"lNN~~

I... :
L-

__ I

Write Data
MPU to Tape

Preamble

5-86

--+-i..--E-;:-~e-edStopgap

~\.\S-Jr-I- - - - -

:-----~
I CRC

I... · I ... ~
Data

FIGURE 5-3.2.1-11. Write Operation Sequence

~i-,

~ Postamble

later. This is the Startgap delay. Since the tape is actually moving for only the last 20 msec of the start gap delay,
the Physical Startgap corresponds to the length of tape moved during the Startgap delay. If desired, a longer
Startgap may be written by continuing in Erase even after stable tape speed has been reached. Similarly, the
Physical Stopgap is the length of tape moved after the Stop command and until tape motion actually stops. If
desired, a longer Stop-Gap may be written by enabling Erase at the end of data, prior to issuing a Stop
command.
Two operations are performed at Search speed: (1) Rewinding tape; (2) Searching to a given record
on tape.
Typically, tape is rewound at Search speed until the BOT marker is seen and then moved forward at
Read/Write speed to the Load Point. The Load Point (Figure 5-3.2.1-13) is the logical beginning of tape and
establishes the reference point from which record counts are kept. The Load Point is located in the Initial Gap
between the BOT marker hole and the first record to be written or read.
Note that when rewinding tape to Load Point, the BOT marker is encountered twice, and this must
be accounted for in the MPU control program for this operation.
E~~t~f
\/

Stop Motion
Command

TapeL
Speed
Time

Tape Motion
Stops
t4 = 20 Msec
8 Msec
. .~~. .__----~. .- - - t 2
14------1..._ - -. . . . .- 1 2 Msec
Tape
Pinch Roller
Tape
Acceleration
Disengage. Deceleration
Time to
Pinch Roller
Time
Time
to
90% Speed
Engage. Time
90% Drop
Stable
(30 Msec)
14---- Total Time to - - - 1. . .. . - - - - Read/Write
in Speed
Stable Speed
Speed (15 ips)
(20 Msec)

Il... ...------

Physical
Startgap
(Tape Motion)

Approximate Length of Startgap =

~ axt~ + v2t2 + v2t3

Physical
Stopgap

------II~

where
a = tape acceleration = v 1 /t1
t1 = time of acceleration (8 Msec)

1 x(.9 x 15 iPS)x
2
8 x 10- 3

(8 x

10- 3\ 2

)

+ 15 ips x 1 2 x 10- 3
=

0.054 + 0.18

= 0.23

= tape speed

at end of acceleration (13.5 ips)

t2 = time to final speed after acceleration (12 Msec)
v 2 = final speed = 15 ips
[v1 = 90% v2]
t3 = additional time after stable speed = 0

inches

Approximate Length of Stopgap = v2 x t4 + Startgap length (when t3 = 0)

= 15

= pinch

roller disengagement time

ips x 20 Msec + 0.23

= 0.30

+ 0.23

= 0.53 inches

I nterblock Gap Length = Startgap Length + Stopgap Length
= 0.53

+ 0.23

= 0.76 inches

FIGURE 5-3.2.1-12: Start/Stop and Interblock Gaps Derived from the Tape Velocity Profile

5-87

= 20

Msec

To search to a given record, the MPU counts the interrecord gaps while moving the tape at Search
Speed. Since the tape is moving at a much faster speed during Search, it is necessary to slow down the tape to a
Read/Write speed prior to getting to the desired record to enable the tape to stop within the required Interrecord
gap. For example, to read or write the 15th record, tape is moved at search speed until the 13th Inter-Record
Gap (I.R.G.) and then switched to a Read/Write speed until the 14th I.R.G. is reached before a stop command
is issued. (It may not be necessary to stop the tape in the I.R.G. prior to reading or writing the 15th record. The
two operations may be performed sequentially without issuing the stop command.)
5-3.2.2

SOFTWARE DESCRIPTION
The Tape Cassette Subsystem uses a 256-byte Data Buffer for storage of Read and Write data and 20

bytes of storage for flags and variables. The variables determine the direction and speed of tape motion, the
number of records being written, and other similar directive commands to the subsystem.
At Power-On, the Tape PIA is initialized so that the A-side is defined as inputs and the B-side is
defined as outputs, and the tape is moved to the Load Point. An Interval Timer is used to generate the delays
needed during tape operations.

Move to Load Point
When a tape cassette is inserted in the Drive, it may be at Clear Leader either on the BOT or EOT
end, or it may be in the "Middle" of the tape between the BOT and EOT markers. A number of different
schemes may be used to move the tape to the Load Point. The method used may be either completely automatic
or require some operator intervention. The Rewind to Load Point operation described here assumes that the tape
has, at some prior time, been advanced past the BOT marker and it is desired to rewind the tape to the Load
Point. (This operation is distinguished from the Load Forward operation where the tape has been rewound to
Clear Leader and needs to be moved forward to the Load Point. The Load Forward operation requires that the
tape be moved forward until the BOT is seen and then advanced past the BOT to the Load Point. To enable the
MPU to determine if the tape has been rewound to clear leader, where both EOT and BOT sensors will be
triggered, it may be desirable to bring the EOT and BOT lines as separate inputs to the PIA interface. It is also
possible to generate a Clear Leader status signal from the EOT and BOT sensors.) The flow chart for the System
Integration of the Rewind to Load Point operation is shown in Figure 5-3.2.2-1. Additional details are shown in
the Flow Chart and Assembly Listing of Figures 5-3.2.2-2 and 5-3.2.2-3, respectively.

BOT
Marker
Hole

LOAD POINT

Oxide Coated Tape

......- - I n i t i a l Gap
- - - - 1...
~

-I-

I II I I I I I

I I I I I I I I I I

-------.l

' - - - Second---l
Record

First
Record~

Forward
Tape Motion

FIGURE 5-3.2.1-13. Load Point

5-88

First
I nterrecord
Gap (LR.G.)

EXECUTIVE PROGRAM

TAPE DRIVERS

Call Rewind to
Load Point Subroutine
("TKRELP")

Arm Timer and Counter

to I nterrupt if Rewind
Takes too Long

Timer Interrupt
when Moving Forward
to Load Point

Arm Timer to
I nterrupt if
BOT is Not
Sensed Soon
Enough

Arm Timer to
Interrupt when
Tape has Reached
Load Point

Set Rewind to
Load Point
Complete OP Flag

Adjust Stack
Pointer to Return
to Executive

FIGURE 5-3.2.2-1: System Integration of
Rewind to Load Point

5-89

Write Routine
The Write Routine consists of three subroutines, TKWRT1, TKWRT2, and TKWRT8. TKWRT1 is
used to write the Startgap, TKWRT2 is used to write one complete record (Preamble, Data, CRCC, and
Postamble), and TKWRT8 is used to write the Stopgap. If more than one record is to be written, tape motion is
not stopped in the Interrecord Gaps.
The Executive Program determines the ending address of the Data Buffer and stores the address in
the end address buffer TKDATA.
There are three possible sources of Interrupts during the execution of the Write program. They are:
(1) Underflow Interrupt, (2) EOT Interrupt, and (3) Interval TimerInterrupt. The Underflow Interrupt occurs if

the MPU does not provide the next Data Bit when it is requested by the Write Clock transition on the CAl
Interrupt input to the PIA. The operation will then be aborted by the MPU. The EOT interrupt should not
normally occur during the Write operation since the EOT single-shot period is set to a time greater than the
length of one record. The hardware design is such than even if an EOT transition is seen on starting Write
motion, there is enough time to complete that record before being interrupted by the EOT single-shot. The
MPU, via the Executive Program, checks if EOT was seen and alerts the operator to insert a new tape cassette
into the drive when necesary. If no Write Clock is present, then the Write Operation is aborted after a time
slightly longer than the length of one record. This results in one record being erased. It may be desirable to set a
shorter time period (e. g. , a time equal to two bit times or 166. 6 milliseconds) to abort the Write operation. The
details of the Write Operation are shown in the Flow Charts of Figures 5-3.2.2-4 and 5-3.2.2-5 and in the
accompanying Assembly Listing of Figure 5-3.2.2-6.

Read Forward Routine
The Read Forward Routine consists of four subroutines: TKRDOO,TKRD02, TKRD09, and
TKRDST. TKRDOO is used to check tape status and to bring the tape up to speed if the status is good. The Tape
Status check consists of checking for Tape Available, Ready, Cassette in Place, In Sync, EOT Seen, and CRCC
Error. Whenever the tape is stopped, the hardware sets the In Sync and CRCC Error status bits to a good status.
This allows a single Read Status Check subroutine, TKRDST, to be used both while the tape is stopped and
while it is in motion. TKRD02 is the basic Read Routine which reads the Data portion of a record including the
two bytes of CRCC. (Data is transferred to the Read Data Buffer in serial format). The CRCC is checked at the
end of the Data portion, and appropriate operation codes are set to inform the Executive of the operation status.
TKRD09 is used to stop the tape motion and store ending status.
The details of the Read operation are described in the Flow Chart and Assembly Listing of Figures
5-3.2.2-7 and 5-3.2.2-8, respectively. There are three possible sources of Interrupts during the execution of the
Read program. They are: (1) Overflow Interrupt, (2) EOT Interrupt, and (3) Interval Timer Interrupt. The
Overflow interrupt occurs if the MPU does not read the next Data Bit when its presence is indicated by the Read
Clock transition on the CAl Interrupt input to the PIA. The operation will then be aborted by the Overflow
Interrupt. The EOT interrupt should not normally occur during the Read operation since the EOT single-shot
period is set to a time greater than the length of one record. This implies that even if an EOT transition is seen on
starting Read motion, there is enough time to complete that record before being interrupted by the EOT
single-shot. If no Read Clock is present, then the Read Operation is aborted after a time corresponding
approximately to the length of one record.

5-90

Begin Rewind
to Load Point

Rewind Tape
(Go Backward)
at Search Speed

Interval
Timer
Interrupt
for 40 Sec
Delay Routine
Set I nterval Timer
I nterrupt Vector for
Delay Routine

"TKRLP 1"

Status Checked
a. Available
b. Cassette in Place
c. Ready

TKRLP 7
Store OP Flag

FIGURE 5-3.2.2-2: Move to Load Point Flow Chart (Sheet 1 of 2)

5-91

Move Forward
to Load Point
Stop at Load
Point Routine

TKRLP 5

Interval Timer
I nterrupt for
Load Point Delay

Arm for 0.99 Sec Delay
and Set I nterval Timer
Interrupt Vector for
Error Abort Routine

Preload Rewind to
Load Point Complete
OP Code

TKRLP 7
Store OP Code
I nterval Timer
I nterrupt when
Moving Forward
to Load Point
YES

Arm for 1 Sec Delay
and Arm I nterval Timer
Interrupt Vector for
Stop at Load Point

RTS

FIGURE 5-3.2.2-2: Move to Load Point Flow Chart (Sheet 2 of 2)

5-92

00010
00020
OOO:~:O

00040

r'Hit'1
TKPELP
OPT
:~:
• REV 0.6 AS OF 1-2-75

•

00060

•• REWIND TO LOAD-POINT SUBROUTINE •• INTRPT-DRIVEN ••

000:::0
00090
00100
00110
00120

•
•
•
•
•

THIS SUBROUTINE MOVES THE TAPE FROM
BETWEEN THE BOT AND EDT MARKERS~ TO THE
LOAD- POINT. IT REWINDS THE TAPE AT SEARCH
SPEED TO THE BOT MARKER AND THEN MOVES
FORWARD PAST THE BOT MARKER TO THE LOAD-POINT.

00140
00150
00160
00170
001:::0
00190

•
•
•
•

THE INTERVAL TIMER IS USED TO ABORT
THE OPERATION IF NO BOT INTERRUPT IS SEEN
DURING THE TIME IT SHOULD TAKE TO REWIND
THE TAPE FROM EDT. THIS TIME IS APPROXIMATELY
40 SECONDS (AT 100 I.P.S.).
NOTE THAT THE DRIVER PROGRAM MUST ENSURE
THAT THE INTERVAL TIMER IS AVAILABLE FOR
USE BY THIS SUBROUTINE. SINCE THE MAXIMUM
DELAY FROM THE INTERVAL TIMER IS 990 MSECS.
A DELAY COUNTER TVDLYC IS USED TO COUNT TO
THE REQUIRED DELAY TIME. THE INTERVAL TIMER IS
RESTARTED AND ALLOWED TO INTERRUPT THE MPU UNTIL
THE DELAY COUNT IS COMPLETE.

00200

00210
00220

00230
00240
00250

00260
002:::0
00290

00:'::00
00310
00320
003,:::0
00340

•

•
•
•
•
•

•
•
•

• ERROR SUBROUTINES TO STOP INTERVAL TIMER
• AND SET OPERATION STATUS FLAGS.
• OPERATION STATUS FLAGS IN TVOPST
• AS FOLLOI.•JS

00::::60
00370
00:::::::0
00390
00400

•
•
•
•
•
•
•
•
•

00420
004:30

• THE OPERATION STATUS CODES USED ARE
• A:S: FOLLOI.•.IS:

00::::50

00440

00450
00470
00480

00490
00500
00510
00520

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

7 6 -

0 =COt'1PLETE ;
0 =t·~O ERf;;' .
c:- 0 =E;AC~:::I.•JARD ;
4 - 0 =t-iO Ef;;~A:S:E ;
:~: 0 =RD-I"Jf;;~T :s:p
2 - 0 =t"i0 I.,.lf;;~ I TE ;
1 - 0 =t"i0 REAII
0 - 0 =STOP

.
~

,_I

1 = I t-~CO"'lPLETE

l=ERf;;'OR
1= FI.•JD DI f;;~CTt·~ .
l=E~~A·S.E

l=:~:EARCH

S:PII.

1=I.,JR I TE
1=READ
1=GO

•
•
•
•
•
•
•
•

REWIND TO B.O.T. IN PROGRESS
REWIND TO B.O.T. ABORT
MOVE FWD TO L.PT. IN PROGRESS
MOVE FWD TO B.O.T. ABORT
MOVE FWD TO L.PT. ABORT
REWIND TO LOAD PT. COMPLETE

FIGURE 5-3.2.2-3. Move to Loadpoint Assembly Listing (Sheet 1 of 4)

5-93

10001001
11001001
10100001
11100001
11100000
00100000

00540 001 0
00560
005::::0
005'30
00600
0061 I)
00615

$1 I)

D~~G

• VARIABLES USED BY THE ROUTINE
001 I)
001 1
0013
0014
0015

T',/OP:S:T
I ".·':S:Er;:~ . .,'
T. .·'STAT
T. . . DL ..,.·C
T'·."S'·.":S:P

0001
0002
0001
0001
0002

00630

F.'t1B
P,..lE:
P,..lB

1
2
1
1
2

r;:~t'lE:

RMB

OPERATION STATUS BUFF.
INTRPT SERVICE ADDR. BUFF.
TAPE STATUS BYTE BUFF.
DELA''''' CDUt01TEP
STACK POINTER STORE

• CONSTANTS USED BY ROUTINE

00650
0066'0067
006:::
0069
0070
0071
0072 )
00730
00740 0300
00770

>::P2DRA EQU
>::P2DF.~E: EOU
::::P5DF.~E: EG!U
::-::P5CF.~A EOU
;:'::P5CRE: EI)U
S1 Ot'lS EI)U

$C01 0
$C01 1
$C012
$C013
$1 000
$1 001
$1 002
$1 003
256
$300
DF.~G
• BEGIN REWIND TO LOAD

COl 0

COl 1
C012
C013
1 000
1 001
1 002
1 003
01 00

0300
OJ 02
0304
0306
030'3

00'370
00980
00'3'30
01000
01010

0312 C6 C'3
TKRLP1 LIlA B
._ISR
0314 E:D 0365
0317 26 44
BNE
0319 7A 0014
IIEe
O:~:lC 27 :3F
BEG!

T~:::F.~ELP

•
•
•
•
•
•
•
•

TAPE PIA ADDR & DATA

10 MILLISECOND CLOCK
POINT ROUTINE

1 0 (I (11 001
OF'EF.~AT I Otoi IN PROGRES::S:
TVOPST
STORE OPERATION STATUS
~~~.~ 0 I) 0 01111
:S:PCH-Rlo•.It-iII cnTRL. I.•.ID.
XP5DPB
REWIND AT SRCH. SPD.
~~41
:SET DELA . . · croiTR TO !'
A
COUNT 40 DELAY INTERVALS.
A TVDLYC
~~ TKRLP 1
~S:T::·::
SET RETRN ADDR FOR ITIMER
I'·.·':S:ERV
SUBROUTINE TO CHECK IF DELAY COUNT IS COMPLETE
THIS SUBROUTINE IS INTERRUPT DRIVEN.
IF THE DELAY COUNT IS COMPLETE THEN THE
PROGRAM WILL CONTINUE WITH THE REST
OF THE LOAD-PO I NT F.~OUT I ~iE. I F THE IIELA·. .
IS NOT COMPLETE!' THE PROGRM WILL SET THE
SAME INTRPT SERVICE ADDRESS,PESTART
THE InTERVAL TIMER AND RETURN.

00790
00::::00
00:::: 1 0
00:::20
00::::30
(10::::40
00:::50
00:::60
008:::0
00::::'30
00'300
00'310
OO'j20
00'330
00940
00'350

C6 ::::'~
II7 1 I)
::::6 OF
E'-:=' 1 001
86 29
030F: 97 14
030D CE 0312
0:31 I) DF 1 1

ITIMER PIA ADDR & CONTRL

LDA
STA
LDA
STA
LDA
STA
LD>::

B
E:
A
A

~~\

11 0 0 1 0 0 1
ERROR I ~iCOMPLETE FLAG
CHI< • :STATUS
TI::P2DRA
F..'ETURN TO HOST PF.:OGRAM
~~s

STOP AT LOAD POINT SUBROUTINE
LItA E:
--'SF.:
BNE
LDA B

~~~.~ 111 00000
PF.:ELOAIt EF.:R. CODE
CHK EtiD I t-iG STATUS
TI<:STAT
TKRlP7
~~~.~ 001 I) 0000
t'10'·,,'E TO LII. PT. DOt'iE

E:F.~A

TKF.~LP7

INTERVAL TIMER ERROR INTERRUPT ENTRY POINT
WHEN MOVING FORWARD TO B.O.T.
~~~~ 111

0 (I 0 01
ERROF!: ON MOVE FORWARD.
TVSVSP
RESTORE STACK POINTER

EXIT FROM INTERVAL TIMER INTERRUPT

D7 10
TKRLP7 S:TA B
LDA A
86 EE
STA A
B7 1001
:39
RTS

STORE OPERATI[]N STATUS:
TVOPST
RD-FltJD-ST[]P CtiTRL. It.ID.
~~~.~ 111 0111 0
STOP TAPE
::'~P5DRB
F.:ETURN

FIGURE 5-3.2.2-3. Move to Loadpoint Assembly Listing (Sheet 3 of 4)

5-95

01530

••

01550
01560
01570
015:::0
01590
01600

•
•
•
•
•
•

0162('
01630
01640
01650
01660
I)

STATUS CHECK SUBROUTINE

••

THIS SUBROUTINE CHECKS THE CURRENT STATUS
OF THE TAPE WHICH IS AVAILABLE AT PAO-PA?
THE STATUS IS COMPARED WITH THE EXPECTED
GOOD STATUS (AVAIL.,CAS. IN PLACE, RDY.)
AND THE RESULT OF THE COMPARISON IS SAVED
IN THE TAPE STATUS BUFFER TVSTAT.

0365 .B6 1 000 TJ::P2CRA
;:':;P5CRB

0325
0365
C012
1 00:::

TJ::P5DF.:A

01 00
o::::::::n
0014
C013
1 000

TVRELP
TKRLP5
T'·/OPST
;:'::P2nRA
::·::P5DF.:B

T~::RLP 1 0:312 T~:;P5DRA EOU
$1001
;:'::P5DRB EG!U
XP5CRA EQU
$1002
XP5CRB EQU
$1003
210MS EQU
256
10 MILLISECOND CLOCK
••• PIA INTERFACE DEFINITION ••••••••••••••••••••••

;:':;P2Cf:::A

•
•
•

• OUTPUTS- WRT DATA AND CONTROL

•
•
•
•
•
•
•

•
•
•

PEO
PBI
PB2
PB3
PB4
PBS
PB6
PB7

- WRITE DATA

WRITE =0 ~ READ = 1
ERASE =1 ~ RD ENABLE =0
eRC RESET = 1 ~CRC ENABLE = 0
- •• SPEED •• RD-WRT = 0 ,SEARCH =1
- •• DIRECTION •• FWD =1 ~REV =0
- CRC SHIFT = 0 ~WRT DATA ENABLE =1
- •• MOTION •• STOP = 1, GO = 0

• INPUTS -RD DATA AND STATUS

PAO - READ DATA
• PAl - CRC ERROR =1
• PA2 - NOT IN SYNC = 0
• PA3 - READ\' = 1
• PA4 - CASSETTE IN PLACE = 1
• PAS - ~RT PROTECTED = 0
• PA6 - AVAILABLE = 0
• PA7 - EDT-BOT SEEN = 1

••

CAl - CLOCK (LOW TO HIGH)
• CA2 - STROBE (RD WRT HANDSHAKE- HIGH TO LOW)

•

• CBl - .INTRPT. OVFL-UNDFL (LOW TO HIGH)
• CB2 = .INTRPT* EDT-BOT TIMEOUT (LOW TO HIGH)
FIGURE 5-3.2.2-6. Write Routine Assembly Listing (Sheet 2 of 6)

5-101

01170

•••

01190

• CHECK TAPE STATUS FOP WRITE

01210 0400 C6
01220 0402 ED
o12:~:O 0405 26
01240 0407 C6
01250 040':;' :=:E.
01260 040B 97
01270 040It ::::6

TKI.t'/RT1 LDA E:
EO
I·:::·/;'
04F2
E:t·~E
16
B5
LItA B
f=F
LItA A
·S:TA A
20
6C:
LDA A

01290
0131 0
01320
013:;:0
01340
01350
o13f, 0
01370

WRITE START GAP (INTERVAL TIMER USED)

00000
PRELOAD ERJ;~ .OF'CDnE
TKI.'-'P:S:T
CHEel< TAPE STAT. FOJ;:' I.I.IRT.
TI::
~ ~ .~: 1 (I j'1 ::. + $ 2 2
F~ E c. LEn GT H (2;~ I) r'1 :S· E C )
1530 042C CE 0122
STX
XP2DRA
SET & START ITIMER
1540 042F FF COl (I
1550
•• WRITE PREAMBLE
1560
• NOTE THAT A SHIFTED PREAMBLE IS LOADED
t 1570
• Ir·~TO THE CUPRENT '.'-'ORD BUFFER SI~iCE
015:::0
• THERE IS A 1-BIT DELAY IN THE HARDWARE.
01590
• THE FIRST BIT OF THE PREAMBLE IS PRESET AND
01600
• THE BIT COUNTER IS SET TO 7 FOR THE
01 E, 1 0
• P~'EA"'1BLE.
01620
• EACH DATA BYTE TO BE WRITTEN IS TRANSFERRED
01630
• FROM THE DAT~ BUFFER INTO THE CURRENT WORn
01,::'40
• BUFFER.
01650 0432 CE 0027
LDX
==TKDATA
STARTING ADDR OF DRTA BU~F

FIGURE 5-3.2.2-6. Write Routine Assembly Listing (Sheet 3 of 6)

5-102

01660
01670
016::::0
01E.·~0

•

0170~

0171
0172
017~:

0174
0175
0176
0177'017::::0
01790

01::::10
01820
01830
01840
018S0
01:::60
01S70
01::::::::0
01::::90
01900
- 191 0
1920
19:::::0
1'340
1950
1'3160

043B
043E
0440
0443
0445
0448
044A
044C
044F

FE.
C6
F7
C6
F7
C6

1000

•

._1._1

0129
OF
1003
F9

:=:E. E.::::
E'7
'I 1001
20 2:::

LIlA
LIlA
:S:TA
LIlA
::;:TA
LIlA
LIlA
:S:TA
BRA

E:
B
E:
B

B
B
A
A

:S:H 1FT
•T~:::CRC:S:
LIlA

C~~CC

04S1
0453
0456
0458
045B
04SE
0460
0461
0464
0466
0469
046Ft
04E,C
046E

;::!E. 20

-,19::::0 0470
01'390 0472
02000 0475
02010 0477

A
Fl 100c' TI::
F5 1002 TI=~PSDRE:
II I :S:A:E:LE EF.:A:S:E
T 1< 1.1.1 F.: T 5

LOOP
~~\OOl

00000

T~:::CRC::::

>:;P5I1RB
>:;PSIIPA
~~ 0-1 5

GET nE::<
TI",ICIIAT
r'1D I,/E DATA TO CU~:REt'iT I.IID BUF
~~ (1-:::
:::ET BIT
TO ::: BIT:S:
~~\ (I 1 1 00000
1.r.lPT·- F I.r.lD -G 0 C~~TF.:L • 1.r.iD.

cnTP

TI",ICDAT
;:'::F'SDF.~ B
>::P5DPA
T~:::!.,JPT5

r'~\:

CP::-=:
Br-1E

Inc:

POLL FOR BIT REG!UE:S:T
E~iABLE :S:HIFT CRce
CLF.~ If'iTRR FLAG
·S:ET BIT cr·iTF.' FDF.~ c.-, c~'c B'lTE
I r'~c • '-'.III • cnT~~ • FOR PO:S:TAt'1BL

POLL FOR BIT REOUE:S:T
CLR I r'iTPR FLAG
I t"1CPEt'1Et-iT BIT cnTR
C~~CC :S:H I FT DOt'iE ·7"
TI::P5DRA

;:':;P5CPA
TKI.,JPT5

POL F
.S:T'=t A

P~~ELDAII

;:'::P5C~~A

BIT E:
BPL
POP A

I
012C
DE
0020

BYTE

.s:·r'NCHF.~O"'i

c"c"

1'~70

02030
02040
OE: OS 0
02060
02070
020:::0
02090
02100
0211 I)
02120
02130
02140
02150

DE::-=:

ACCOU"'~T FOR PREAME:LE
I ZAT I Oti TO I.,JPITE CLOCte::
>:;P5eF.~A
0436 FE. 1002 T~:::S:''''''''i 1 LIlA B
TKS·.... ,..~ 1
0439 2A FB
BPL
POLL FO~~ BIT REO

04:35 0'3

T",,IDATA
TV I.I./PT3
T",·ICPCF

POLL FOP BIT PEOUE:S:T
PUPGE OLD DATA BIT
:::H I FT NEt,J :1:: IT TO CA~'~:\'
CAPF.:·"( TO DATA BIT PD·:: I T I Ot·~
t·~E'-r.I BIT TO PIA
elP I r'~TPp FLAG
I nCF.:Et·1E~iT BIT Ct-1T~~
IF r'~OT DonE GET t·iE::·:;T BIT
I I'~C • Ir./D. ADDP. Cl~TP •
CDr'1P. FOf;;~ END ADDP.
LFr::T I.dOF.'D --;:.
CHAr'H;E CPC E~iABLED FLAG

FIGURE 5-3.2.2-6. Write Routine Assembly Listing (Sheet 4 of 6)

5-103

02160
02170
02180
02190
02200
02210
02220
02230
02240
02250
02260
02270
02280
02290
02:~: 0 (I
02:':::10
02:~:20

02:':::30
02:340
02.350
02:3E.0
02370
02400
02410
02420
02430
02440
02460
02470
024:::0
02490
02500
02510
02520
025::::0
02540
02550

0495 27 BA
0497
049A
049C
049F
04Al
04A4
04A6
04AS
04AA
04AD
04BO
04B2
(l4B4
04E:6
04E:9
04BC
04E:E
04C1
04C4
04C7

04C::::
04CE:
04CD
04[;0
04I12
04Ii4
04D6
04I19
04I!B
04DE
025':.0 04EO
02570 04E-':::
025::::0 04E6
02590
02E. I) (I
02':.1 (I
02E·20 04E7
02'::.]0 04E9
02E.40 04EC
02E.50 04EE
02'::.60 04Fl

Fl
2B
F6
D7
7A
26

::::A
eE.
FE
FF
20
9A

1002
FB
1000
24
012E:
oe
8C
F.: 4
340(:
1002
04

BEG!

r.,JRITE
•••
TKS·...·N2

CMP
B,..lI
LDA
STA
DEC
BNE
ORA A
LDA E:
LD::<

S:T::<
BF.~A
T~::'I.,.lF.~T6

C6 B5
E'7
'I 1001
04C8
DF 21
CE 0102
FF COlO
F7 012A

T~:::I.,JF.'T7

:~:r3t

7C
C6

0023
'-Ie:

-="-'

E:6 012E:
26 1 1
C6 22
::':::6 EE
p7
:
1001
:=:E, 04
F7 1003
::':::6 2(:
E''I-:=' C013
F7 012Ft

:~:.~

96 EE
J3'7
1001
'1
::::E. E4
:p7
. '1
012A
39

TI::

~~:S: 1 O~1:S:+$ 02
:5:TOPGAP DELA''''' 20 t'l:S:EC: •
;:'·;P2DPA
STAPT I t'~TVL TIMER
T'·.·'OPST
STORE OPEF.~AT I O~" :S:TATU:S:
~~T:S:
F.:ETURt"i FF.~O"'l :S:UBF.'OUT I NE
IF t'iO OTHER RECOF.'D'S: TO EE I...lR I TTE~i!l THEf"i
TUI;;~N OFF I.I.IPITE C '-' P F.' E t'i T At'in F.'ESET FOR
f:;:EAD-FI.I.lD. IF t'liJPE PECD~'n:s' TO :BE I•.IP I TTEf"i
THEt·~ LEA\,IE I...IJ~' I IE (Er;:~A:S:E ::. CUF.~PENT Ot"i
At-iII PETU~:t'1 FOf;: THE NE::::PSDPE:
:S:TDP TAPE IN PI; FI.•.ID
~~$O4
LDA Ft
;:'::F'SCr;::E:
STA E:
DISABLE TAPE PIA I t-iTF=::F'TS •
LItA A ~~$2C
'S:TA A
>::P2CPF.:
IiIAE:LE I t'i T I,..' L T I t'lEP I t'1TPPTS •
-S:TA B
T·'.,'OPST
:S:TOPE OPEPAT IOt'1 S:TATUS
E~fn 05
PTS:
PETUPN F F.: 0,..1 :S:UBPDUT I t"iE
EPPOP ItiTPPT POUT It-iE

:5:T::O:;
:S:TA E'

•
•
•
•
•

•
• 'S:ET EPPOP ABOF.:T
•TKPECE LItA A 'f;EE
:5:TA A
LIlA A
:5:TA A
~:TS

:~.:

PETUr;:'f"i TO E::·:;EC
F.:EAD FI.•.iD COt·1TF.:OL 1...10
::::F'5D~:A

PEAII TAPE :S:TATU:S:
111 11100
t'lAS:I< UNI.,.lA~iTEn BIT:S:
~~\ 00011100
COt'1PARE I.,.IITH GOOIJ STAT.
T'",'STAT
SA'",'E ERPOR STATUS
PETRt-i F~:O~l SUE:~~OUT I ~iE
~~~.~

S'r't'lBOL TABLE

Et"1D05
TKCRC:S:
T K :5: \. ~~ C·
TK 1.I.lPT3
TKI,I.lF.:TS
T',,"DATL
>::P2CRA
>::P5CRE:

04E3 I'",'SER'",' 0021
0451 TKDATA 0027
04'3'7 T~:::I."IR 0 1 041D
0470 TKI,Ij~'T4 0472
04C8 TO~:ECC 012B
0025 T'",'LI,dA
0127
C012 >::P2CRE: C 01 ::::
1 003 ;:':;P5I PA 1 000
'

:::1 or'1:S'
TVDEL1
TKI"JR:S'T
TKI"JPT5
T1,.,'CDAT
T'",'DF'ST
':::F'5DPB

01 00 T~::,CPC::::
0412 T~:::RECE
04F2 TKI.,.I~'T 1
047'3 T~:::I".lRT6
0129 T',.,'CRCF
012A T","F.'ECC
COl (I ::-:;P2DRA
;:':;P2DRB
;::;P2CRE:
;:::P5r'F.~B
~~~~1 01 00001
t'10VE -FI,.,II' IN PROG.
~~:s: 1 Ot1S+$ 04
40 t1SEC UPTO 'S:PI' • DEL A ....'
::::
:::T::-:;
LD;:'::
:S:T;:':;
Et'~ABLE READ
LDA A
STA A
LDA E:
:S:TA E''
LDA B
LD;:'::

XP5DRA

0621
0624
0627
0629
062C

~~TKRIIAB

CLR TAPE
INTRPT. FLAGS
:S:ET RI! AE:Or;t:T RET AIJIIF.:ES:

I '.,l:S:ER'·,·'
~~:S: 1 or'lS+$:3 0

RECF.:D. LE~iG TH 3 (I (I t'l:5:EC.
SET & START ITINER.
(LOOK FOR FIRST BIT)
~~~,~ 001 01 01 I)
PEAD-FI.,.ID CNTF.'L. II,II;.
XP5DRB
CONTINUE MOTION IN PD
::~\ 1 01 I) (1011
RD-FI.I.1Ii H'i PF.:OG.
TVDPST
STORE OPERATION STATUS
~~ (1-:::
:SET BIT cnTR
~~TVDATA
LOAII F I PST 1".loRD AI;DF.:.

XP2DRA

•

POLL FOP E:I T F.: EO
UPDATE BIT Ct·iTF.·

~~\OOOO1111
ENAE:L O..... EF.:FLO I
;:':;P5CPB
~ ~ ~.~ 1 1 1 1 0 1 1 1
Et'~AE:LE CF.:C PEG
;:':: P 5 II F.: E:
~~ 0-::;:
:::ET E: IT Ct'~TP

t'~TPPT

;:'::P5C~:A

TK F.: II 04
::;:
cp;:.:;

0029
EA
ENE
FO
LDA B
1002 TKPD05 BIT B
FE
EPL
1000
LDA A
INC B
F5
ENE

0677 C6 E3
0679 ED 06B2
06lC 26 09
O~.?E C6 A3
0680 CE 069D
06::::~: II? 2::::
0685 20 05
0687 D7 28

I) 1 E.:::: (I

01690
01700
01710
01720
01730
01 74 0
01750
017E.O
01770
01780

0689
068C
068E
0691
0694
0697

CE
DF
CE
FF
7C
:::6

06A6
21
0103
COlO
0023
2E

0699 B? 1001
069C :~:9

01800
0181 0
01:=:30
fl1840
1850
1860
1870
1880
1890
'-'1900

0 , ;:<
TKF.~D

STOPE BIT IN DATABUFF.
UPDATE 1:: I T Ct-~TR
04

~~TI

SET BIT Ct"iTP
INCPEMENT WORD CNTR
COMPARE LAST WD ADDR.
LAST 1",.lOF.~D --;SET BIT CNTP FOR CRC

>::P5Dr;~A

POLL FOP BIT PEQ
CLP INTRPT. FLAG &PD STATUS
UF'DATE E I T Ct"~TF.~

. .IDATA
Tt:;P2CF.:A
;:':;P 5C F.: I:

0100
OE,54
06A6
0029
(:012
100::::

Tf:;P5IIJ;:~A

1000

FIGURE 5-3.2.2-8. Read Routine Assembly Listing (Sheet 5 of 5)

5-112

5-4.1

INTRODUCTION

The floppy disk is fast becoming an important storage media. The promise of low cost and direct
access has encouraged minicomputer users to select the floppy disk for mini-mass storage requirements. As
microprocessing systems enter the marketplace, proposed applications for the floppy disk broaden to include
the "less-than-mini" market. These new applications include:
• Program loaders for intelligent terminals and larger systems
• Key-to-disk keypunch replacement
• Price look-up and credit card verification files for POS systems
• Message buffers for communications systems.
In these applications, the floppy disk will contend with cassettes and paper tape. The attractiveness of floppy
disk over other means of mass storage rests in:
• Cost per bit of usable storage
•
•
•
•

Cost of the floppy disk subsystem
Reliability and maintainability
Ease of media handling and transportability
Compatibility of recorded data with other systems, large or small.

The purpose of this section is to show techniques for controlling a floppy disk with the MC6800
microprocessor. Because the floppy disk data rates lie at the extreme high end of the MC6800's data handling
capability, this section also serves to demonstrate optimization techniques that can be used in applications other
than the floppy disk.
The floppy disk itself (often referred to as a diskette) is a removable magnetic storage media which is
permanently contained in a paper envelope. The diskette drive is a low cost peripheral which performs the
electro-mechanical and read/write functions necessary to record and recover data on the diskette. Reprints from
the reference manuals for the CALCOMP 140, Orbis Syst~ms Model 74 and Shugart SA 900 floppy disk drives
are appended to this section. Familiarity with floppy disk terminology, operations and specifications will be of
value in understanding the design techniques illustrated in this section.
Data is recorded serially on the floppy disk. Due to the high serial data rates, it is necessary to use
auxiliary logic for the serial/parallel conversion, data recovery, and data error checking when interfacing the
floppy disk to the M6800 system. The hardware which performs this function is usually called aformatter. The
formatter also serves as a buffer between the M6800 system and the disk (Figure 5-4.1-1).

,-----------------.
I

FLOPPY DISK CONTROLLER

I
I

M6800
MICROPROCESSING
SYSTEM

FORMATTER

I
I

,
I

L _____ _ ________ J

FIGURE 5-4.1-1. M6800/FIoppy Disk Subsystem

5-113

DISKETTE
DRIVE

The purpose of the M6800 system and the formatter is to control the diskette drive. Therefore, the
combination of the M6800 SYSTEM and FORMATTER blocks in Figure 5-4.1-1 is referred to as the Floppy
Disk Controller. As used here, the term "controller" includes not only the system hardware, but also those
microprocessing system programs which directly or indirectly control the diskette drive. The program routines
for the floppy disk are often referred to as floppy disk drivers or control modules. A more complete diagram of
the controller is depicted in Figure 5-4.1-2.

Control Modules

Initialize
Seek

wr'~lte__________~I

Read

System
Memory

MPU

Interval
Timer

Floppy Disk
Formatter

Diskette
Drive

To Other
System
Elements

FIGURE 5-4.1-2. Floppy Disk System

5-4.2

OVERALL CONSIDERATIONS

The content of the blocks shown in Figure 5-4.1-2 is the subject of this section. However, before
describing the system, it is of interest to discuss the tradeoffs involved in microprocessor-based floppy disk
controllers. The decision to design a floppy disk controller using the M6800 system depends upon:
5-114

Exec
MPU

Exec
Memory

Control
MPU

Control
Memory

Shared R/W
Memory

Control/
Command PIA

Floppy Disk
Formatter
Disk

To Other
Exec System
Elements

To Other
Control System
Elements

FIGURE 5-4.2-2. Multiple MPU System

5-115

(1) The way the disk system will be used in the overall system;
(2) The cost difference between the alternative design methods (such as hardwired logic); and,
(3) Both the short term and long term goals with respect to the use of the disk subsystem.
Due to the high data rates of the floppy disk, the microprocessor is, in effect, busy 100% of the time
during data handling. This means no other microprocessor peripherals can be serviced while in a disk read or
write operation. This is true provided that the transfer of data is controlled by the microprocessor and not via
some type of Direct Memory Access (DMA) hardware.
Since no other peripherals can be serviced, interrupts generated by the other system elements must
be disabled during disk read or wri te operations. Allowances must be made in the system design to permit 100%
system dedication to floppy disk during read and write operations. This can be accomplished in three ways:
(1) If feasible, design the system such that other peripherals will not need service during floppy disk
data transfer time. An example of this is a serial task system where each system task is executed
in sequence with no overlap (Figure 5-4.2-1).
(2) Dedicate a microprocessor to handle peripherals which never interfere with disk operations and
assign the disk to that microprocessor. This microprocessor would then be a peripheral control
processor which is subservient to an executive processor (Figure 5-4.2-2). The executive
processor could be another micro, a mini or even a large processor.
(3) Dedicate a microprocessor to the disk subsystem.
Alternatives (1) and (2) can represent significant cost savings over a hardwired logic disk controller
because the M6800 hardware is shared by the other system peripherals. In alternative (3) the cost of the M6800
parts is directly attributable to the disk system. A dedicated full capability floppy disk subsystem would require
a minimum of the MC6800 MPU, lK of program storage (usually ROM), 256 bytes of RAM, two PIA's for
formatter interface, one half a PIA for the interval timer, one half a PIA for interface to the external world,
system clock logic, and approximately 40 SSI and MSI IC's for the formatter. This is compared to approximately 180 SSI and MSI IC's in a hardwired logic design of the controller plus the interface in the executive
processor system. Depending on the system design goals, it is possible that the dedicated MPU based design
can be more expensive than hardwired logic. Of course, the MPU based design is much more flexible and can
be programmed to have a higher level of "intelligence" than its hardwired logic counterpart. If the system has a
potential to grow (long term consideration), or if there is a need to design a flexible floppy disk system, a
dedicated MPU based design would be a wise decision.
The design described here is limited to non-DMA design, that is, all data transfer is under program
control via the MPU. The design discussion will cover methods of R!W head electro-mechanical control (seek
operation), write, read, and a specific application called UPC lookUp. In this manual, the various routines have
not been completely integrated as an operating system, that is, the discussion does not completely link the
routines together nor does it include error or malfunction processing.
Single diskette drive formatter logic is described in this section. Expansion of the subsystem to
multiple drive control is dependent on the specific floppy disk drive's interface. For example, the Shugart SA
900 interface is designed for "radial" interconnection (Figure 5-4.2-3). In the "radial" interface, all
interconnections are dedicated to specific drives.
The CAL-CaMP 140 interface is designed for "daisy chain" interconnection (Figure 5-4.2-4). In

5-116

Formatter

To/F,om
Drives

I
SA900
Orbis 74

SA900
Orbis 74

FIGURE 5-4.2-3. Radial Interface

r-r--

To/From
Drives

Formatter

}

CC140
Orbis 74

...
•••

)

CC140
Orbis 74

FIGURE 5-4.2-4. Daisy Chain Interface

the "daisy chain" configuration, some of the lines are shared and some are dedicated while the Orbis 74 allows
for either configuration.
Each type of interface has its advantages. The' 'radial" interface isolates (buffers) each drive but the
"daisy chain" interface requires less system hardware.
The single drive formatter described in this section is designed to interface to either the Shugart SA
900 ("radial") or the CALCOMP 140 ("Daisy chain") interface. The Orbis 74 will operate in both modes. On
earlier Model 74's a minor modification must be made to generate the ERASE GATE signal. Because more
than one model of diskette drive can be connected certain interface signals are controlled which may not be
required by one or the other diskette drive.
The IBM 3740 recording format has been chosen for this design description. Appendix 5-4.D is a
description of the recording formats commonly used in floppy disk applications. (Courtesy of Shugart
Associates) .
The limited scope of this Section is not intended to imply that the MC6800 can not be used in other
floppy disk applications. The techniques are general enough to aid the systems designer in most floppy disk
applications.

5-117

Initialize
System

Display Entry

Process Entry

YES

Floppy Disk
Write Operation

FIGURE 5-4.2-1. Example of a Serial Task System

5-118

5-4.3

SYSTEM HARDWARE/SOFTWARE INTERFACE
Figure 5-4.3-1 is a functional block diagram which shows all the signal lines between the floppy disk

system and the PIAs. Note that two PIA's are used to control the disk system. The following is a brief
description of the signals. More detailed descriptions from a programming view follow the brief descriptions.
PIA # 1 is used primarily as a data buffer. Peripheral Register A is the WRITE CLOCK buffer
register for write operations and the READ DATA gate for read operations. Peripheral Register B is the WRITE
DATA buffer for write operations and is used as a status signal gate for read operations. The four read status
signals which are routed to PIA # 1, Peripheral Port Bare:
PBO + 1ST BIT
PB3 - CRC=OO
PB6 - INDEX CLOCK MARK
PB7 - ID/DATA MARK
NOTE: The + signifies the signal is active in the high logic level when the - signifies low logic level is active.
PIA # 1 peripheral ports A & B are used as both inputs (read operation) and outputs (write operation). Because
all data field write operations must be preceded by a read ID field operation, the Direction Registers must be
restored to all "D's" in preparation for a read operation.
CAl and CA2 of PIA # 1 are used to synchronize the timing of the program to the data rate during
read or write operations. CA 1 is a service request line. In the read operation a positive transition of the CA 1 line
indicates that a complete 8-bit byte has been assembled and is present at the A port. In the write operation a
positive transition of CAl means that the clock and data patterns in Peripheral Registers A & B have been
moved to the external parallel-to-serial shift registers and the Peripheral Registers can now be updated.
Data synchronization is controlled by polling for Interrupt Flag # 1. An active transition of the CA 1
line causes Interrupt Flag # 1 of Control Register A to be set to a "1". It takes the MPU a minimum of 8 cycles
to recognize that the flag has been set (if the PIA is located in the extended address range $0100 to $FFFF).
After the flag is recognized by the MPU, write or read data is transferred to or from the PIA. At a 1 MHz MPU
clock rate, there is a minimum 8 microseconds delay between recognition of the service request and servicing
the PIA.
The BYTE READY/BYTE REQUEST CAl signal is one bit period in duration. It goes low at the
beginning of the last serial bit time of a byte, then returns high at the beginning of the next serial byte (Figure
5-4.3-2). Due to the 8 microsecond program delay, the interrupt flag could be set at the beginning of the last bit
period even though the data won't be ready until the end of that period. This lookahead technique can provide
additional processing time in critical timing areas of the program.
Serial
Bit Period

I
I

~
PIA #1-CA1
(Byte Ready /
Byte Request)

Set PIA # 1 )
Interrupt
Flag 1 A

1'4'-4 p,S (Nominal)

LJ
Read OP -

Transfer Byte to
Read Buffer

Write OP -

Transfer Byte to
Shift Register

FIGURE 5-4.3-2. Byte Ready/Request Interface

5-119

I
)
CAl
CA2
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PIA #1

PA7
PB7
PB6

..-

.. .. ..
..
--

--~-

PB5
PB4
PB3

PB2
PBl
PBO
CB2

(

- ..
..

-Byte Request, Byte Ready
+R/W Handshake
+Wrt Clk, Read Data, Bit 0
+ Wrt Clk, Read Data, Bit 1
+Wrt Clk, Read Data, Bit 2
+Wrt Clk, Read Data, Bit 3
+Wrt Clk, Read Data, Bit 4
+Wrt Clk, Read Data, Bit 5

Read/
Write
&
Error
Detect
Circuitry

+Wrt Clk, Read Data, Bit 6
+Wrt Clk, Read Data, Bit 7
+Wrt Data Bit 0, -I D/Data Clk Mark
+Wrt Data Bit 1, -Index Clock Mark
+Wrt Data Bit 2
+Wrt Data Bit 3
+Wrt Data Bit 4, -CRC = 00
+Wrt Data Bit 5
+Wrt Data Bit 6

Serial
Write Data

+Wrt Data Bit 7, +lst Bit
+Above Trk 43

~sedal Os
Read

CBl

)

CBl
CB2
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
PIA #2
PA7
PA6

_ +Not in Sync

+Disk Sys Inoperable

+Underflow

---..

+Wrt Protected

PA3

...

PA2

PAO
CA2
CAl

+Forward Direction
-Head Load
Diskette
Drive

-Ready
+Index
+Track 00

PA4

PA1

_ +R/W Error

..-.

PA5

(

_ +Index

....
..
..

+Read Enable
-File Inop Reset
-Disk Select
-Shift Crc
-Enable Crc
-Enable Wrt
-Write Gate
-Step
-Ready

t'
)

FIGURE 5-4.3·'. Floppy Disk Functional Interface

5·120

The CA2line is the MPU's response to the disk system indicating that the service request at CAl has
been accepted. It is used to signal overrun errors for the read operation and underflow errors for the write
operation. The CA1/CA2 operation of PIA #1 is a handshake mode of operation in which CA2 is set high on an
active transition of CAl and returned low by a MPU read instruction (LDA, BIT, etc).
CB2 of PIA #1 is a control signal called "ABOVE TRK 43" that is used only in write operations.
When recording data on a diskette track greater than 43, this line is raised high. This signal is used by the
CALCOMP 140 and Orbis 74 to control the write current amplitude on inner tracks in order to reduce the effects
of a phenomena called "bit shift." 1
PIA #2 is used as a control, status and interrupt interface. The control signals are:
PAO
PAl

WRITE GATE
ENABLE WRITE

PA2
PA3
PA4
PAS
PA6

ENABLE CRC
SHIFT CRC

PB4

+
+

PBS
CA2
The status signals are:
PA7
PBO
PB1
PB2
PB3
PB6
PB7

FORWARD DIRECTION
HEAD LOAD
STEP

+
+
+
+
+
+

The interrupt signals are:
CAl
CB1
CB2

DISK SELECT (CALCOMP 140 ONLY)
FILE INOP RESET
READ ENABLE

TRACK 00
NOT IN SYNC
DISK SYSTEM INOPERABLE
UNDERFLOW/OVERRUN
WRITE PROTECTED
READY
INDEX
READY

+
+

INDEX
R/W ERROR

The use of the control, status and interrupt signals is described with the appropriate operation.
The following is a general summary of PIA Control Register and Peripheral Register assignments in
the floppy disk programs as seen by the operating programs. Refer to Section 3-4 of Chapter 3 for additional
information on PIA operation.

lThe bit density of the diskette increases as the radius of the track location decreases. This means that the magnetic flux reversal ofthe bit
being written affects the bit that had just been written. The magnetic field generated by the R!W head is approximately proportional to
the amount of current in the head. The ABO VE TRK 43 signal causes less current to pass through the R!W head thereby reducing the
intensity of the magnetic field. This signal is not used by the Shugart SA 900 Diskette Drive.

5-121

FPICRA -PIA #1, Control Register A; Address $8082;
b7
bo

I I I I I I 10101
Describes CAl operation. CAl is the input signal BYTE REQUEST for Write Operations and BYTE
READY for Read Operations. Interrupt Flag #1 (Bit 7, FPICRA) is set to a "1" by a high-to-Iow
transition of the BYTE REQUEST/BYTE READY signal. Interrupts to the MPU from Interrupt Flag #1
are disabled.
b7
bo

I I 111010 I I I I
Describes CA2 operation during data transfer programs. CA2 is the output signal R!W HANDSHAKE.
When BYTE REQUEST/BYTE READY (CAl) makes a high-to-Iow transition, CA2 responds with a
low-to-high transition. The CA2 output is restored low by a Read Peripheral Register A (DPlPRA)
instruction such as:
or

LDAA FPlPRA
BITB FPlPRA.

During data transfer, the program must execute a Read FPlPRA instruction before the next BYTE
REQUEST/BYTE READY high-to-Iow transition at CAlor an Underflow (WRITE OP)/Overrun
(READ OP) error latch will be set.
b7
bo

I \ 11\1\ 0\ \ I I
Describes CA2 operation when not transferring data. This Control Register bit configuration holds R!W
Handshake (CA2) low when not transferring data to prevent the UNDERFLOW/OVERRUN latch from
being set.

FPIPRA -

PIA # 1, Peripheral Register A; Address $8080;

Write Operation:
b7

~~ItE :C~O~~

o < P A > 7, Write Clock Buffer;
For a Write Operation, these PIA lines are defined as outputs. Peripheral Register A stores the clock
pattern to be recorded on disk.
Read Operation:
b7

I I~E1D:D~T~ I I

o < PA > 7, Read Data;

For a read operation, these lines are defined as inputs. The PIA lines PO-P7 are the parallel read data lines.

5-122

PIA # 1, Peripheral Register B; Address $8081

FPIPRB -

Write Operation:
b7

I I WR~T$

PATA
o < PB > 7, Write Data Buffer;
For a write operation, these lines are defined as outputs. Peripheral Register B stores the data pattern to be
recorded on disk.
Read Operation:
b7

IOJ 0 I I

101
11/
For a read operation, these lines are defined as inputs.
PBO, + 1ST BIT;
b7
bo

IIIIIII

111
1ST BIT is a read status signal which latches when a " 1" data bit has been detected in the serial read data.
The 1ST BIT latch is enabled and cleared by the ENABLE CRC control signal.
b7
bo

I I I I \01 I I I
PB3, -CRC

00;

CRC = 00 is a Read Data validity error check. CRC = 00 goes low for one byte period after a record has
been read if there were no read errors detected.
b7
bo

I 10 1 I I I I I I
PB6, -INDEX CLOCK MARK;
INDEX CLOCK MARK goes low for one byte time during a read operation when the serial data stream
contains $D7 in the clock bits. This unique pattern is recorded 46 bytes after the INDEX signal and is
referred to as "Soft Index."
b7
bo

/01 1 1 1 1 1 1
PB7, - ID/DATA CLOCK MARK;
ID/DATA CLOCK MARK goes low for one byte time during a read operation when the special clock
pattern $C7 is detected. When this signal occurs, it means the next BYTE READY signal (CAl) is for the
first data byte of the record.
PI CRB -

PIA # 1, Control Register B; Address $8083;

IIII

111111
CB2 is used as an output to generate the ABOVE TRACK 43 control signal. When the disk track address

is greater than 43, the CB2 line is set high.
b7
bo

III

1111101
When the track address is less than 43, CB2 is restored low. During a write operation, the ABOVE
TRACK 43 signal controls the write current amplitude.
5-123

I I I I I 11 I I I
Select PIA # 1 Peripheral Register B;
b7
bo

IIIII

101

Select PIA # 1 Direction Register B
FP2CRA -

PIA #2, Control Register A; Address $8042
bo

IIIIII

10111

CAl is programmed to generate an MPU interrupt when the diskette drive goes from a Not Ready to
Ready status during initialization.
b7
bo

IIIIII

11111

When in a data transfer operation CAl is programmed to generate an MPU Error Interrupt when the drive
goes Not Ready.
b7
bo
1 1 101

IIIIII

When not in a data transfer operation, the Ready Interrupt is disabled.
b7
bo

I I 11/ 0 111 I I 1
CA2 is the output control signal STEP. During a seek operation, the R!W Head is moved one track by
pulsing the STEP signal (CA2). When in the seek operation, the step pulse is generated by reading PIA #2
Peripheral Register A (FP2PRA).
b7
bo

1111 11 I

I 1I

When not in the seek operation, the STEP signal is held high.
b7
bo

I I I I I 111 I I
Select PIA #2 Peripheral Register A;
b7
bo
I I I I I 10 1 I I
Select PIA #2 Direction Register A;
FP2PRA -

PIA #2, Peripheral Register A; Address $8040;
bo

I I I I 1 I I 101
PAO, -WRITE GATE, (output);
WRITE GATE turns the diskette drive's write current on.
b7
bo

I I I I I I 101 I
PAl,

ENABLE WRITE (output);

ENABLE WRITE switches the formatter hardware to write mode.
5-124

I1 1II

101
PA2, -ENABLE CRC (output);
Write Operation:
ENABLE CRC gates the Polynomial CRC Generator on. ENABLE CRC is set low during the byte time in
which the address mark is moved to the write buffer.

Read Operation:
When ENABLE CRC is set low, the read operation begins. The CRC Polynomial Generator is gated on
automatically at 1st bit time. Raising ENABLE CRC high resets the Formatter read circuits.
b7
bo

I \ \ \ \0 \ I I I
PA3, -SHIFT CRC (output);
SHIFT CRC is used during write operation. SHIFT CRC is set low the byte time after the last data byte is
moved to the write buffer. This causes the accumulated CRC bytes to be appended to the serial write data
stream. SHIFT CRC must be held low for two byte times.
b7
bo

101

I I
1

P A4, - DISK SELECT (output);
DISK SELECT enables the diskett drive's interface.
b7
bo
10/ I I 1 I I
PAS, -FILE INOPERABLE RESET (output);

I 1

FILE INOPERABLE RESET clears any latched error conditions. If the error condition is "hard", i.e.,
present at time of reset, the error latch will not reset.
b7
bo

I 111 I I I I I I
PA6, +READ ENABLE (output);
READ ENABLE enables the NOT IN SYNC error latch to be set in the event serial read data
synchronization is lost. READ ENABLE is raised high during a read operation after the desired address
mark is recognized by the program.
b7
bo

IIII III

111
PA7, + TRACK 00 (input);
TRACK 00 is a diskette drive status signal which goes high when the R!W head is at Track 00.
FP2PRB b7

PIA #2, Peripheral Register B; Address $8041;
bo

I I I I I I I 111
PBO, +NOT IN SYNC (input);
NOT IN SYNC is an error latch signal which is set when a zero bit is detected in the clock pattern being
read. The NOT IN SYNC error latch cannot be set when READ ENABLE is low.

5-125

IIIIII

111

PBl, +DISK SYSTEM INOPERABLE (input);
DISK SYSTEM INOPERABLE is the logical OR of FILE INOPERABLE from the diskette drive and
ENABLE WRITE if the drive WRITE PROTECTED status is active. This signal is an error latch output
which means that the disk system is unsafe to use.
Note: Unsafe in this context means recorded data may be destroyed.
b7

I I I I I 11 I I I
PB2, +UNDERFLOW/OVERRUN (input);
UNDERFLOW/OVERRUN is an error latch which is set when the microprocessing system did not
respond to the disk system BYTE REQUEST/BYTE READY in time. This indicates that data has been
lost. The PIA #1 CAl & CA2 handshake mode of operation govern the timing of this error condition.
b7
bo

I I I I III I I I
PB3, + WRITE PROTECTED (input);
WRITE PROTECTED is a diskette dri ve status signal which indicates that a write operation should not be
attempted. An error condition will result if ENABLE WRITE or WRITE GATE is made active while the
drive is write protected.
b7
bo

III

111

I III

PB4, +FORWARD DIRECTION (output);
When high, FORWARD DIRECTION will cause the R/W head to move toward the center (increasing
track address) of the disk with a step pulse. When low, the R/W head will move away (toward TRACK 00)
from the hub with a step pulse.
b7
bo

II III

101
PB5, - HEAD LOAD (output).
When low, the R/W head contacts the diskette recording surface.
b7
bo

I 101 I I I I I I
PB6, -READY (input).
READY is a diskette drive status signal which indicates that the drive is ready to be operated.
b7
bo

11 I

IIII III

PB6, +INDEX (input).
INDEX is a pulse of approximately 450 microseconds in duration which occurs once every revolution
(167 milliseconds). INDEX indicates the beginning of a track.

5-126

FP2CRB - PIA #2, Control Register B. Address $8043.
b7
bo
I 1 1 1 I I

11111

During write data operations, the leading edge of INDEX implies a WRITE ERROR.
b7
bo

I I I I I I 11'0 I
During the format write operation, the leading edge of INDEX is the initial timing reference. The INDEX
interrupt is disabled in the format write and when not in a data write operation.
b7
bo

I I 10 101 II

R/W ERROR interrupt is enabled during data transfer operation. R/W ERROR is the
logical OR of NOT IN SYNC, DISK SYSTEM INOPERABLE and UNDERFLOW/OVERRUN. During
data transfer operations, a low to high transition on CB2 generates an MPU interrupt. The interrupt
program then aborts the data transfer operation.
b7
bo

1010101

III

When not in a data transfer operation, the interrupt is disabled.
b7

I I I I I 11 I I I
Select PIA #2 Peripheral Register B.
b7
bo

I I I I I (0 I I I
Select PIA #2 Direction Register B.

5-127

5-4.4

DISK PROGRAM ROUTINE LINKING CONTROL

The programs listed in this section operate under a supervisory (host) program. In order to enable the
host program to determine the operational status of the floppy disk, three bytes of RAM storage are maintained
by the floppy disk drivers.
The first byte, called FVDELT, defines how far away the R!W head is from the desired track
location (Table 5-4.4-1).
TRACK DELTA CODES

oxxxxxxx

HEAD NOT ON DESIRED TRACK

00000000

HEAD SETTLING ON DESIRED TRACK

11111 1 1 1

SEEK NOT IN PROGRESS (I.E., COMPLETED OR ABORTED)

TABLE 5-4.4-1. 'FVDEL T' Ram Location

The second byte (Figure 5-4.4-2) is the overall ending status of the last disk operation executed.
Operation status is stored in RAM location FVABOR. The codes are used by the executive and error processing
routines to determine the major state of the disk system. FVABOR is also tested in the interrupt poll routine to
determine if an interrupt occurred during a floppy disk Read or Write operation. If an interrupt occurs during
floppy disk read or write, the normal interrupt poll is not executed. Instead a special disk interrupt routine is
executed that aborts the disk routine that was interrupted.
FVABOR

OPERATION CODE

00010000
01010000
00010010
00010001
01010010
00010010
01111111
10001000
01001000
01101000
00001010
10000100
01000100
01100100
00000110
10001100
01001100
01101100
00001110

SEEK IN PROGRESS
SEEK ABORTED
SEEK COMPLETED
RESTORE IN PROGRESS
RESTORE ABORTED
RESTORE COMPLETED
SEEK VERIFY ABORT
READ IN PROGRESS
READ ABORT BY PROGRAM
READ ABORT BY INTERRUPT
READ COMPLETE
WRITE IN PROGRESS
WRITE ABORT BY PROGRAM
WRITE ABORT BY INTERRUPT
WRITE COMPLETE
WRITE FORMAT IN PROGRESS
WRITE FORMAT ABORT BY PROGRAM
WRITE FORMAT ABORT BY INTERRUPT
WRITE FORMAT COMPLETE

TABLE 5-4.4-2. 'FVABOR' Ram Location

5-128

The third byte is the error status code. Any bit set to a "1" in this code indicates a disk system
malfunction has occurred. When a disk subsystem error is detected, an error code which describes the cause of
the error is stored in RAM location FVSTAT. (Table 5-4.4-3).

BIT
POSITION

MEANING

BITO

READ OPERATION - NOT IN SYNC
IN A READ OPERATION IINOT IN SYNC" MEANS THE DATA RECOVERY
CIRCUITS ARE NOT SYNCHRONIZED TO THE SERIAL DATA.

BIT 1

DISK SYSTEM INOPERABLE
THIS SIGNAL IS AN OR OF THE FOLLOWING ERROR CONDITIONS.

BIT2

OVERRUN/UNDERFLOW

BIT3

WRITE OPERATION - WRITE PROTECTED

BIT4

READ OPERATION - CRC NOT EQUAL TO 00

BIT5

NOT HEAD LOAD

BIT6

NOT READY

BIT7

WRITE OPERATION - INDEX

TABLE 5-4.4-3. 'FVSTAT' Ram Location

5-4.5

SEEK AND RESTORE OPERATIONS

The floppy disk records data on 77 circular tracks numbered 00 - 76. In order to access a certain
record, the R/W head must first be locked in position at the track which contains that record. The operation
which performs the head movement function is called a seek operation. For the floppy disk, a seek is executed
by stepping the head one track at a time. The timing between steps is controlled from an interval timer.
The restore operation is similar to the seek operation. The main difference between seek and restore
is that a restore operation always moves the R/W head to track 00. After the seek operation has completed, the
only way to verify that the proper track has been accessed is to read the track address of the ID field. When track
00 is accessed, the diskette drive generates a TRACK 00 status signal from an electrical/mechanical sensor. The
restore operation is completed when the TRACK 00 signal goes active.
Figure 5-4.5-1 is a partial system flow chart which shows how the floppy disk seek routines might
integrate into the system program. Referring to the flow chart, entry into the disk routines is controlled by a host
program -

sometimes referred to as an executive program.

The seek function is divided into two parts, the SEEK INITIALIZATION routine and the INTERRUPT DRIVEN SEEK routine.
The SEEK INITIALIZATION routine is entered by the host program. The routine calculates the
number of tracks and direction the head must move, sets up the disk control signals, and generates the first
interval timer interrupt to begin head movement.

5-129

Power On or
System Restart

Initialize
System

Sets the seek
direction and
calculates number of tracks

'FKSEEK'
I nterrupt Driven
Seek Routine
Steps the
R/W head
a single
track

Execute Other
System Task

FIGURE 5-4.5-1. Typical Host/Floppy Disk Program Interaction

5-130

Execute Disk
Operation

Head movement from track to track is controlled by the INTERRUPT DRIVEN SEEK program
routine. This routine is interrupt driven by the interval timer. Because the actual seek is interrupt driven, the
host program is free to execute other routines while the seek is in progress. The interval timer is set to 9.9
milliseconds for each step of the seek. However, the interrupt poll plus additional processing time causes the
time between steps to be closer to 10 milliseconds. When the seek is completed, a seek complete indicator flag
is set. It is the responsibility of the host program to test this flag before advancing to a disk read or write
operation.
For seek and restore control, the MC6800 interfaces to the diskette drive via a PIA as shown in
Figure 5-4.5-2. The two control signals DIRECTION and STEP govern head movement from track to track
The diskette drive specifications also require that the HEAD LOAD signal be active and WRITE GATE signal
be inactive during head movement. The status signal, TRACK 00, is active when the head is located at the
outermost track.
The STEP signal clocks a three bit left/right rotating shift register. The DIRECTION signal controls
the direction of bit rotation in the shift register. The outputs of the shift register enable DC current through two
of three windings of a three-phase stepper motor (Figure 5-4.5-2). The repetition rate of the STEP pulse is
determined by the minimum time it takes the motor to rotate one-third of a tum.
The seek and restore operations are further clarified by the flow charts of Figures 5-4.5-3 & 5-4.5-4.
The Assembly Listings are included as Figures 5-4.5-5 & 5-4.5-6.
A review of the seek initialization routine shows that the current track memory location
"FVCTRK" is stored in positive binary notation for a forward seek and negative notation for a reverse seek.
Then in the interrupt driven seek routine "FVCTRK" is incremented to update the current track location.
One of the primary reasons to use floppy disk as a storage media instead of another type of media
such as tape cassette is improved data access time. By definition, access time include:
(a) seek-time - the time for the R!W head positioner to move from its present location to the newly
specified location (10 milliseconds/track);
(b) settle time - the time for the positioner to settle onto the new track (10 milliseconds from last
step pulse); and
(c) latency time - the time required for the diskette to rotate to the desired position (83.3
milliseconds , average).
The diskette spins at the fixed rate of 167 milliseconds per revolution. On the average, the data will be one half
of a revolution - 83.3 milliseconds - away from the head. This is known as average latency time. While there
is no way to decrease latency time of a disk system, there are ways to improve overall seek time.
Consider a system in which a single record must be accessed from a large number of records. An
example of this type of system is a grocery store price lookup in a point-of-sale terminal. The lookup begins
when a commodity with the UPC bar code imprinted on it is scanned. Then the resultant numerical UPC code is
decoded to the floppy disk track number where the price data is recorded. A seek operation then moves the R/W
head to that track.
The seek portion of data access time is the number of tracks times approximately 10 milliseconds.
Accessing the track where the price information is located can be considered to be a random access seek. If the
head were initially located at a central track in the price lookup area, then the average and maximum seek times
would be minimized. This means that after each price lookup operation, a seek back to the central track would
be initiated. Since a seek is interrupt driven, the operation is essentially transparent to the host program.
Further, returning the head to a central track can be considered a low priority operation. If the host program
5-131

Diskette Drive
Formatter

PIA #2

-Step

CA2 ....-....I--+-..-..4
-Track 00

P A 0 ....-.......-+--0::
-Write Gate

PB7

""-_-+---1

PB6

....-_-+---i

PB4

t-_-+---i

-Head Load

-Direction
Line
Drivers and
Receivers

Rotating Shift
Register
-Direction

-------i L/R
Clk

Light from Track 00
Sensor

-Head load

~~T,a'kOO

+24 V

FIGURE 5·4.5·2. Seek/Restore Interface

5·132

RESTORE
OPERATION
ENTRY

SEEK
OPERATION
ENTRY

FKRSTR

FKSKIN

Find Magnitude
of Current Track

The current track ("FVCTRK")
is the current location of the R/W
head.

_ Current track ("FVCTRK") is a signed binary number.
The magnitude is the positive value of the number.

Target track ("FVTRKA") is the track number where
the R/W head is to be moved to.

Make Delta
Positive
(Negate Delta)

Make Current
Track Negative
(Negate "FVCTRK")

YES

Set I nterval Timer
for
I mmediate Interrupt

FKSP05
Clear System
I nterrupt Mask

FKSP04
Store Current Track
Location in
Signed Binary
- = Reverse Seek
+ = Forward Seek

Clear Disk Error
Latches (if Set)
and Select Disk

Error latches are set override.
I f any "hard" errors are present the latches will not clear.

The step pulse will be generated automatically by PIA #2
when FP2 PRA is read.
Return to
Host Program

FIGURE 5-4.5·3. 'FKSKIN' Flow

5-133

I n the system for wh ich th is
routine was designed a busy
interval timer means that an
interrupt will occur. The interrupt poll is designed such
that the seek operation will
be serviced each interval timer
interrupt.

A zero time interval is started.
This will cause an interrupt
after the interrupt mask is
cleared.

Interval
Timer

~lnterruPt
FKSEEK
This is an interrupt routine.
The routine is called when the
interval timer interrupts the
system. The interval timer is
stopped by the interrupt poll
routine.

_ Good status is 00
in "FVSTAT"

FKSK04

The restore is complete. An
extra step was issued. This
step pulse nullifies the extra , -_ _ _--''--_ _ _ _,
step.

Set Restore
Complete Flag
Restart Interval
Timer for 9.9 ms
Time Out

Return to
I nterrupt Poll

FIGURE 5-4.5-4. 'FKSEEK' Flow

5-134

FLDIS1(

82878

SEEK/RESTORE PREPARATION ROUTIHE

82898
82188
92119
82128
82138
82148
92158
92169
82178
82189
82198
82298

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

THIS ROUTIHE PREPARES THE DISKETTE DRIVE
AND RA" LOCATIONS FOR A SEEK OR RESTORE
OPERATION. FOR A RESTORE OPERATIOH THE CURRENT
TRACK ADDRESS (MFYCTRK a ) IS PRESET TO 83 AND
THE TARGET TRACK AJDRESS (-FVTRKA·) IS
CLEARED TO 89. FOR A SEEK OPERATION THE
CURRENT TRACK VALUE IS DETERMINED BY THE LAST
SEEK OR RESTORE OPERATION. THE TRACK DELTA
(-FYDElTR) IS CALCULATED BY SUBTRACTING THE
CURRENT TRACk FRO" THE TARGET TRACK AND
CONVERTING THE SIGNED BINARY RESULT TO A
POSITIVE BINARY HU"BER.

82228
92238
82248
82258
82279
82289

92299
82388
82318
82328

82338
82348

82358

THE DIRECTION OF THE SEEK IS DETER"INED BY
SIGH OF THE TRACK DELTA BEFORE IT IS CONYERTED
TO A POSITIVE BINARY HU"BER. IF THE SIGH IS
NEGATIVE THE SEEK IS REVERSE (TOWARD TRK 88).
TO INITIATE THE INTERRUPT DRIVEN SEEK ROUTINE
A DU""V INTERVAL TI"ER INTERRUPT IS GENERATED
IF THE Tl"ER 15 HOT BUSY.
IF THE TI"ER IS
BUSY IT IS ASSU"ED THAT THE INTERRUPT WILL
OCCUR WHEN THE TIMER RUNS OUT, SO A DU"''''Y
INTERVAL TIMER INTERRUPT IS HOT GENERATED.
THUS INTERFERENCE WITH CONCURRENT OPERATIONS
USIHG THE TI"ER IS ElI"IHATED, 1. E. THE SEEK
WILL HOT BEGIN UNTIL THE TIMER IS AYAIL4BLE.

TABLE 5-4.5-5. Seek/Restore Preparation Routine (Sheet 1 of 3)

5-135

FlDISK

92388
82488 5861 8F
82419
82429
92438
92449

5862
5865
5867
5859

7F
C6
86
28

9894
33
11
85

RESTORE OPERATION ENTRY

FKRSTR SEI
CLR
LDA 8

LDA A
BRA

92469

82488 5858 SF
82498 58se D6 83
92588 586E 86 18
92518 5978 97 99
92528 5872 5D
82~38 5873 2A 81
82548 5975 S8

FKSKIH SEI
LDA B

"FKRSTR-

"ASK SYSTEM INTERRUPTS
TARGET TRACK = 88
PRELOAD ARTIFICIAL CURR TRK
'~89818801
PRELOAD RESTORE OP CODE
FKSP81

FYTRKA
183

SEEK OPERATION ENTRY = -FKSKIN"

LDA A

F!(SP81 STA A
TST B
BPL
NEG B

MASK SYSTEM IHTERRUPTS
FYCTRK
FETCH CURRENT TRACK
1%09019998
PRELOAD SEEK O? CODE
FVABOR
STORE OP CODE
FKSP82

BRANCH IF ·FYCTR~u POSITIYE
"AKE -FYCTRK- POSITIVE

* SINCE -DYCTRK" IS IN SIGHED BINARY FOR"AT IT

82368
82579
82388

*
*

8 2 6. 8 8 3 87 6 '6 84
92618 5078 18
82628 5879 2A 97

SA R Y Toe 0 NV ERTIT TOP 0 SIT I VE BE FOR E

SBA
8PL

*
*
97
4F
28
97
86
87
D7
8D
86
87
86
85
26

:~ E CE S

FYTRKA

FETCH TARGET TRACK
CALCULATE TRACK DELTA

FKSP03

BRANCH IF DELTA POSITIVE
HAKE DELTA POSITIVE
NEGATE CURRENT TRK ADDR.

HEG A
NEe 8

82668
82678
587D
S87F
5888
5882
5884
5886
5889
5888
588D
588F
5892
5895
5897
5899

I S

CALCULATING THE TRACK DELTA.

FKSP82 LDA A

82638 5878 48
82648 587e 58

82698
82788
82718
82728
82738
82748
82758

MFYCTRK M IS A NEGATIYE BINARY NU"BER IF THE
SEEK IS REVERSE
STA A

FYDElT

ClR A

84
BRA
82
FKSP83 STA A
18
lDA A
8841 FKSP84 STA A
83
STA 8
82768
15
BSR
82778
24
lDA A
82788
8842
STA A
82799
8818
lDA A
82888
87
BIT A
82818
88
SHE
82828
SA 85
ORA A
82838 5898 B7 8818
STA A
82848 589E 7F 8811
ClR
82858 S8AI 8£
FKSP85 ell
92868 S8A2 39
RTS

STORE TRACK DELTA

PRELOAD REVERSE DIRECTION
FKSP94
FVDELT

STORE TRACK DELTA
PRELOAD FORWARD DIRECT.
SET DISK DIRECTION
STORE CURRENT TRK ADDRESS
RESET DISK ERROR LATCHES

'~88018880

FP2PRB
FYCTRK
FKERST

1%88188198

FP2CRA
FP3PRA

EHABLE STEP PULSE
FETCH TI"ER STATUS
'~88889111
"ASK NON-TI"ER STATUS
FKSP85
BRANCH IF TIMER BUSY
'C1US
FP3PRA
-START INTERYAL TIMER
FP3PRB
-FOR I""EDIATE INTERRUPT
CLEAR SYSTEM INTERRUPT "ASK
RETURN TO HOST PROGRAM

TABLE 5-4.5-5. Seek/Restore Preparation Routine (Sheet 2 of 3)

5-136

FLDISK

*
*

82898

82918
82921
82938
82948
02958
92968

S8A3
58A5
S8A8
58AA
59AD

86
87
86
87
Be

82988

82999
83998
83828 5888 39

THIS ROUTINE RESETS THE DISKETTE DRIVE
ERROR LATCHES AND SELECTS THE DRIYE.

IF
FKERST lDA A
STA A
8848
2F
LIA A
STA A
8948
CPX
8849

1%88881111

FP2PRA

RESET ERROR LATCHES

1%88181111

FP2PRA
FP2PRA

RE"OYE RESET & SELECT DRIVE
CLEAR ERROR INTERRUPT FLAGS

THE ·CPX- INSTRUCTIOH PERFOR"S A DU""Y READ

* TO -FP2PRA & FP2PRS- TO CLEAR THE PIA
* INTERRUPT FLAGS.
RTS
TABLE 5·4.5·5. Seek/Restore Preparation Routine (Sheet 3 of 3)

5·137

FLDISK

89588

*IHTERRUPT DRIYEN SEEK/RESTORE ROUTINE

88688
89618
88628
88639
89648
88658
98668
88678
8868e
98698
88788

* THIS ROUTINE EXECUTES A ONE TRACK STEP OF
• A SEEK OR RESTORE SEQUENCE. THE DISKETTE
* DRIVE MOYES THE HEAD ONE TRACK POSITION
* EACH TIME THE STEP SIGNAL IS PULSED.
* ENTRY INTO THIS ROUTINE IS GOVERNED BY
• INTERRUPTS FROtt THE INTERVAL TIMER. THE
• TIHER IS PRESET TO 9.9 HILLISECOHDS FOR
* EACH STEP. THE HUMBER OF TRACKS THE HEAD
* "UST "OVE FOR A SEEK OPERATION IS STORED
* IN RA" LOCATION wFYDElT.·
FOR A RESTORE
* OPERATION "FYDELT w IS PRESET TO 83 TO INSURE
• THAT THE MAXIMUM HU"BER OF TRACKS (77) CAN
* BE STEPPED. WHEN THE SEEK OR u RESTORE IS
* CO"PLETED OR ABORTED RFYDELT IS SET TO
* ALL ONES. WHILE THE SEEK I S IN PROGRESS
* BIT 7 OF "FYDELTw IS ZERO.

88718

98728
88738
88748

88758
e8778

99788
88798
88S88

88818
88828
88838

09848
88858
99878

98888
89898
88988
88918
88928
88938
88948
88958
88968
89978

*
*
*
*
*

RA" LOCATION -FYCTRK- CONTAIHS THE CURRENT
TRACK ADDRESS OF THE HEAD. THE VALUE
uFYCTRK w IS IN SIGNED BINARY FOR"AT.
IF THE SEEK DIRECTION IS FORWARD
(FRO" TRACK 80) uFYCTRK· IS A POSITIVE
* BIHARY HUMBER, I.E. BIT 7 IS ZERO. IF
* THE SEEK DIRECTION IS REVERSE (TOWARD
* TRACK 88) "FVCTRK· IS A NEGATIYE BIHARY
* HUMBER, 1. E. BIT 7 IS A ONE.

DISK STATUS IS CHECKED EACH STEP. IF
THE STATUS IS GOOD AND THE SEEK OR
RESTORE IS HOT CO"PLETE THE INTERYAL TIMER
IS RESTARTED TO Tl"E OUT THE HEXT STEP.
AN EXCEPTION TO THE ABOVE IS IF SEEK
COMPLETE IS DETECTED ("FVDELT u BIT 7=1)
* DURING A RESTORE OPERATION THE TI"ER IS NOT
• RESTARTED AND THE RESTORE OPERATIOH IS
* ABORTED. IF SEEK CO"PLETE, RESTO~E COMPLETE
* OR A STATUS ERROR IS DETECTED THE TI"ER
* IS HOT RESTARTED.

*
*
*
*
*

TABLE 5-4.5-6. Interrupt Driven Seek/Restore Routine (Sheet 1 of 4)

5-138

FlDISI(

88998
81988
81811
81928
81838

81848
81858

*
*
*
*
*
*

AN OPERATION/ABORT FLAG IS "AIHTAIHED
IN RA" LOCATIOH -FYABOR- AS FOLLOWS:
118t81eX SEEK/RESTORE IH PROGRESS
8181818X SEEK/RESTORE ABORTED
8e81881X SEEK/RESTORE CO"PLETE
X=8 SEEK OPERATIOH
X=l RESTORE OPERATION

TABLE 5-4.5-6. Interrupt Driven Seek/Restore Routine (Sheet 2 of 4)

5-139

FLDISK

818a8
81898
81188
81118
81128
81138

5888
5882
5883
5885
5888
S88A

96
46
C6
F4
D7
26

FKSEEk LDA
ROR
LDA
62
8841
AND
STA
81
SHE
16

*
*
*
*

81158
81168
81178
81188
81288
81218
81228
81238

588C
588F
5811
5814

7A 8882
28 l'
7C 8883
86 8848

81238
81268
81278

B
8
B

DEC
I He
LDA A

81298 3817 24 82
81388 5819 28 ID

FETCH OP CODE
IF RESTORE op, CARRY=1
SET STATUS "ASk
'~81188818
FP2PRB
FETCH "ASKED STATUS
FYSTAT
STORE ERROR STATUS
FKSK82
BRANCH IF ERROR

FYDELT
FKSK84
FYCTRK
FP2PRA

DECRE"EHT TRK DELTA
BRANCH IF SEEK CO"PLETE
UPDATE CURRENT TRK
FETCH COHTROL WORD

READING THE DISK CONTROL WORD FP2PRA
AUTO"ATICALLY GENERATES THE STEP

PULSE.
BCC
B"I

F kS K 01
FKSK87

BRANCH IF NOT RESTORE OP
BRAHCH IF TRK 80

• RESTORE OPERATION IS CO"PLETE
* WHEN TRACK 88 IS DETECTED.

81338 5818 CE 8363 FKSK81 L DX
81368 S8tE FF a818
5TX
81378 5821 39
RTS

81398
81418
81428
81438
81448

FYABOR

STATUS CHECKED:
1 = DISK SYSTE" INOPERABLE
5 = NOT HEAD LOAD
6 = NOT READY

ERROR
BIT
BIT
BIT

B"I

*
**

81328
81338

A
A

5822
5824
5826
5828

86 58
C6 FF
D7 82
28 82

IS188US+99
FP3PRA
REARM TIMER FOR 9.9"8
RETURN TO INTERRUPT POLL

ERROR DETECTED IN STATUS

FKSK82 LDR A
FKSK83 LDR 8
STA 8
BRA

1~81818888

PRELOAD SEEK A90RT FLAG

I$FF
FYDELT
FKSK05

RESTORE TRK DELTA
CO TO EXIT PREPARATION

TABLE 5·4.5·6. Interrupt Driven Seek/Restore Routine (Sheet 3 of 4)

5·140

FLDISI(

81478
81498
81588
81518
81528
81538

S82A
582C
582E
5831

86
C6
F7
24

FKSK84 LDA A
12
3C
FKSK85 LDA B
STA B
8842

Bec

82
5933 86 51

lDA A

*
*
*
**
*
*
1ft

81558
81568
81578
81588
81598
81688
81618
81628
81648 383~ 97
81658 5037 39

SEEK CO"PLETE DETECTED

RESTORE OP IH PROGRESS IS INDICATED WHEN
THE CARRY BIT IS SET. BECAUSE THE TRACK
DELTA IS SET TO A HIGH YALUE (83) PRIOR
TO BEGINHING A RESTORE OPERATION AN ERROR
IS l"PLIED IF SEEK CO"PLETE IS DETECTED.
BEFORE TRACK 88 STATUS IS SENSED.
ALSO THIS PATH IS TAKEN IF DISK STATUS IS
BAD DURING A RESTORE OPERATIOH.

FKSK86 STA A
RTS

81678

*
*

81758
91779
81789
81798

5848
5941
5844
5846

IC
7F 8983
86 13
28 DC

FYABOR

SET OP/ABORT FLAG WORD
RETURH TO INTERRUPT POLL

RESTORE OPERATION CO"PLETE

01699 5838 86 18
FKSK87 LDA A
STA A
81799 593A 87 8841
LDA A
81719 583D 96 8848
81738
81748

PRELOAD SEEK CO"PL FLAG
'~89818818
1%88111188
FP2CRA
DISABLE STEP PULSE
BRAHCH IF HOT RESTORE
FKSK86
PRELOAD RESTORE ABORT
l~elele8el

'~88818118

FP2PRB
FP2PRA

SET FORWARD DIRECTION
GENERATE STEP PULSE

THE FORWARD STEP IS USED TO RESTORE THE HEAD
STEPPER MOTOR TO TRACK 00 PHASE.
eLC
CLR
LDA A

BRA

CLEAR RESTORE OP FLAG
SET CURRENT TRk TO 9a
RESTORE COMPLETE FLAG
l~e0019911
GO TO RESTORE EXIT PREP
FkSk03
FYCTRk

TABLE 5-4.5-6. Interrupt Driven Seek/Restore Routine (Sheet 4 of 4)

5-141

EXAMPLE: SEEK FORWARD
CURRENT TRACK
TARGET TRACK

= 33
= 36

"FVCTRK" = 0010 0001
"FVTRKA" = 0010 0100
"FVDE LT" = 0000 0011

VALUE AFTER INTERRUPT SERVICE
INTERRUPT
DUMMY

#1
#2
#3
#4

IIFVCTRK"

"FVDEL T"

0010
0010
0010
0010

0000
0000
0000
1111

0010
0011
0100
0100

0010
0001
0000
1111

EXAMPLE: SEEK BACKWARD
FV CT RK" = 11 01 1111
"FVTRKA" = 0001 1101
"FVDEL T" = 0000 0100

CURRENT TRACK = 33
TARGET TRACK = 29

VALUE AFTER INTERRUPT SERVICE
INTERRUPT
DUMMY

#1
#2
#3
#4
#5

IIFVCTRK"

"FVDEL T"

1110
1110
1110
1110
1110

0000
0000
0000
0000
1111

1110 0011 NEGATED

TABLE 5-4.5-7. Seek Examples

5-142

0000
0001
0010
0011
0011

0001 1101

0011
0010
0001
0000
1111

must call or execute a critical time dependent operation during the return seek, the interval timer interrupt can
be masked off at the PIA. This would prevent interference from the seek operation.
In some systems, it is desirable to issue a new seek before the last seek has completed. For example,
a new price lookup may be issued while the head is returning to the central track. To account for this possibility,
the SEEK INITIALIZATION routine masks system interrupts to take control of the RAM locations used by
FKSEEK. (NOTE: In some systems, it may be more desirable to disable the interval timer interrupt and allow
other system interrupts.) Also, before generating the first interval timer interrupt, it is determined whether or
not the timer is being used. If the timer is busy, control is immediately returned to the host program and the seek
is deferred. This extra processing insures that interval timer operation is not interfered with whether the timer is
being used for the last step of the former seek operation or for some other purpose.
The safety circuits in the diskette drive should prevent destruction of data during head movement.
Therefore, checking the disk status during seek may be considered unnecessary in some systems. If an error is
detected by the FKSEEK routine, the seek operation aborts and an appropriate error flag is stored in RAM.
5-4.6

READ OPERATION
An IBM 3740 compatible floppy disk system records data at 250 K bits/second or 4 microseconds/

bit. Because the serial data rate is too high for the MC6800 MPU to handle directly, a hardware/software
tradeoff must be made.
Since the MC6800 is an 8-bit parallel processor, its reasonable to see if a program can be written to
handle the data in 8 bit bytes. In order to do this the worst case byte data rate must be determined. The nominal
data rate is 250 + 8 = 31.25 K bytes/second or 32 microseconds/byte.
Conceivably, the system could record (write) data with the disk running at one rotational speed
tolerance, then try to read the data back with the diskette at the other tolerance extreme. This difference
represents the worst case tolerance of the floppy disk read rate. Both the microprocessor program and the data
recovery circuits must be capable of operating within the maximin extremes.
The worst case speed tolerances can be derived by assuming a 2.5% speed variation from nominal,
both upward and downward. Then the worst case data rate extremes can be calculated as:
MAX
31.25(1 + .025)
(1 - .025)

= 32.85KB

MIN
_31_._25_(_1_-_'_0_25_)
(1 + .025)

= 29. 73KB
= 33.74JLs/B

= 30.44JLs/B

The above MAX/MIN read data rates account only for a ± 2.5% diskette speed variation. Other factors must
also be considered. Variations in the microprocessor clock rate, MPU clock cycle stealing for dynamic memory
refresh, and the disk write oscillator frequency variations are other factors which affect the systems ability to
successfully read data.
The frequency deviations of the MPU clock and the write oscillator can be minimized by using stable
oscillators. However, if cycle stealing is necessary to refresh dynamic memory the time lost for refresh must be
accounted for in the programs which control the transfer of data.
For purposes of this design description, the ± 2.5% speed variation is conservative enough to
account for small frequency deviations in the MPU clock and write oscillator. A complete analysis of the
system including memory refresh time can be made using the techniques outlined in Section 2-3. The memory

5-143

refresh can be treated mathematically as secondary peripheral service requests which must be serviced in an
interlaced manner with floppy disk service requests. The analysis of the floppy disk service programs may be
all that is necessary if the "time available" figure from the analysis ensures that there is sufficient time to
refresh the memory. The data transfer routines in this section were analyzed using a one microsecond out of 50
( worst case) RAM memory refresh cycle.
Other important design requirements due to the worst case read data rate are data capture time and
the ability of the data recovery system to remain locked to the bit data rate through the missing clocks of address
marks. This requirement is further discussed in Section 5-4.6.2, Data Recovery.
In summary, the key to writing the read programs and designing the read circuits is to work within
the framework of the worst case specifications of the entire system. The hardware and software development
can not be treated separately if the optimum system is to be designed. The analytical tools techniques of Section
2-3 can be used to find the best hardware/software tradeoffs and prove the feasibility of the final design before it
is committed to hardware. An example of the analysis is shown for the write operation in Section 5-4.7, Write
Operation.
5-4.6.1

The Read Operation Interface
Figure 5-4.6.1-1 is a block diagram which shows the major formatter functions used in a read

operation.
When ENABLE WRITE is not active, the formatter circuits are in the Read mode of operation.
When WRITE GATE is not active to the selected diskette, the drive SERIAL READ DATA is present. The
SERIAL READ DATA signal contains both clock and data information. This signal is routed to the Data and
Clock Recovery block of Figure 5-4.6.1-1. The outputs of the recovery block are separated serial NRZ data, a
clock that is synchronized to the data and serial NRZ clock information, and another clock that is synchronized
to the recovered clock pattern. To prevent confusion with the term" clock" the synchronizing clock signals are
referred to as DATA TIME and CLOCK TIME. The data recovery system is described in Section 5-4.6.2.
The Read Data Logic block (Figure 5.4.6.3-1) contains the serial to parallel shift register, a read data
buffer register, the bit counter (used to determine the byte boundaries) and the CRC polynomial generator (used
for detection of read errors). Detailed description of the Read Data Logic is in section 5.4.6.3.
The Read Clock Logic block of Figure 5-4.6.1-1 contains the clock shift register and the decode of
the clock portion of the data, deleted data, ID and index address marks as shown in Figure 5-4.6.1-2. Another
signal developed in this block is called IN SYNC. Since the clock pattern is all "1' s" except during an address
mark the first position of the clock shift register in Figure 5-4.6.1-2 should be high except at mark time.
Therefore, once an address mark has been detected, a low out of the first shift register position means the data
recovery system is not locked to the data rate. When this signal goes low during the data portion of an ID or Data
Field the system is said· to be not in sync.
The IN SYNC signal is routed to the Error Detect Logic block (Figure 5-4.6.1-3). This block
contains error latches which when set generate an interrupt to the M6800 system.
The NOT IN SYNC latch is set when the IN SYNC signal goes low (as previously discussed) if the
ENABLE READ signal from PIA #2 is high. The Read routine raises ENABLE READ after an address mark is
detected.
The OVERRUN/UNDERFLOW latch is set when the Read routine does not respond to the last
BYTE READY service request before new data overruns the data in the read buffer register. This operation was
discussed in section 5-4.3.
5-144

(

-Byte Ready

CAl
CA2

-- +R/W Handshake
_

'A'!i;"":i:!!:\:":;~

PAO
PAl
PA2

Read

PA3
PA4

Clock
Logic

+Data Out

PA5

+Data Time -~

PA6
PA7
PIA #1

+ID/Data
Clk Mk

PB7
PB6

Data
&
Clock
Recovery

+Index Clk Mk

~__
~~--------~--~

PB5
PB4
PB3

-CRC = 00
___-----------r--~

PB2

-B7 Time
+In Sync

Clock Out

Read
Clock
Logic

4------------C-IO-C-k-T-im--err~r-~------~~

PBl
PBO

CB2
CBl

+1 st Bit
-B7 Time

---11-0

+ Sync'd Enable CRC

)

L~-----------.

~----~

Error
Detect

I
J

+File Inoperable --~
CBl
CB2
PBO
PBl

__ +R/W Error

__ +Not in Sync

+Overrun
+Disk Sys Inop

PB2 M----~~~~--~-------4-4--+----------------------+~r---~----------------~J
PB3
PB4
PB5

L.-._ _+-~--<
~____
+s_e_r_ia_I_R
__
ea_d__D_a_t_a____-+______-r-<~~
~1_~_-~H~e~a~d_L_o~a_d__________4-4-___a-~~________________+-____~__"J~~

-Ready
-""
PB6 ~__
~----~--------~----+-4------------U~
PIA #2

PB7
PA7
PA6
PA5

)

V--

Diskette
Drive
--""

+Read Enable

- : -File Inop Reset

~~_------~------~----+-+------UI ~

-Disk Select
v
PA4 ~~~--------------+-----+-+-----------~
PA3

.. -Enable Crc
~
PA2 ~--~-+a
..
PAl
_ -Enable Wrt

PAO
CA2
CAl

-Ready

(

J
FIGURE 5·4.6.1-1. Read Operation Interface

5-145

+EnableVVrt---------------------------------------------------------------------,

+Clock Out

--------1

Clock
Shift Register

+Clock Time -----------1 C

-Data/l D Clk Mark

-Index Clk Mark

-87 Time
+In Sync

FIGURE 5-4_6.1-2. Read Clock Logic

+Overrun
or
Underflow
+87 Tim e ------------1----------------4 CI k
+R/VV Handshake----------+------,--~
+Sync'd Enable Crc---...r--.

+F i Ie Inoperable

---+--------f-+---------------------.

+ E nab Ie VV rt - ...---------t---t-.,
Xl....-.------- +DiskSys
Inoperable

+VV rt Protected ------------t---t----f

+ R/VV Error

+lnSync
+ E nab Ie Read _______-+_-+---1
>-------+---------+Not in Sync

+F ile Inoperable
Reset

FIGURE 5-4.6.1-3. Error Detect Logic

5-146

The third error latch is OR'd with the diskette drive status signal FILE INOPERABLE (see appendix
5.4.B). The output signal is called DISK SYS INOPERABLE. Further discussion of this latch will be found in
section 5-4.7.3, Write Operation Formatter Error Detect Logic.
Although the error programs are not included in this Manual, one observation of diagnostic aids is
appropriate at this time. Many of the floppy disk system detectable malfunctions are of a "snowball" nature.
That is, one malfunction causes the next. The error detect logic of Figure 5-4.6.1-3 inhibits secondary error
trapping by blocking the set mechanisms of the error latches after anyone of the error latches or FILE
INOPERABLE goes active. This means that diagnostic programs would be able to detect the original cause of
the malfunction.
Data Recovery
The data recovery system of Figure 5-4.6.2-1 is designed to generate a synchronized clock from the
diskette drive's raw digitized data. Other goals of the design shown in Figure 5-4.6.2-1 are:

5-4.6.2

(1) Separate and recover both clock and data bits from the serial data stream.
(2) Generate a continuous clock even when clocks are missing, i.e., address marks.
(3) Track the long term changes in data rate but not the short term data rate changes.
The MC4044/4024 Phase Lock Loop (PLL) is the heart of the data recovery system.In this system the MC4024
Voltage Controlled Multivibrator (VCM) is phase and frequency locked to 16 times the data rate. Each record
is preceded by a preamble of all zero's which the PLL uses to lock to the data rate. Mathematical analysis of the
PLL system is not treated in this section, however, equations for the 4044/4024 PLL system are treated in
Motorola's Phase-Locked Loop Systems Data Book and Application NoteAN-535,Phase-LockedLoopDesign
Fundamentals. These publications may be obtained by writing to the Literature Distribution Center, Motorola
Semiconductor Products Inc., P. O. Box 20912, Phoenix, Arizona 85036.
Figure 5-4.6.2-2 is a timing diagram of the data recovery system shown in Figure 5-4.6.2-1. This
timing diagram is idealized for illustrative purposes. Raw digitized read data enters the system as a series of
pulses. Each pulse toggles a flip-flop, forming the signal READ DATA -;- 2. The output of the divide by two
flip/flop is clocked into a two bit shift register by the MC4024 VCM's frequency output. Each time the divide
by two flip/flop output switches, a pulse one VCM period in duration is generated from the exclusive OR gate
tied to the output of the two bit shift register. Thus each pulse of serial read data generates a single pulse of one
VCM period in duration.
The VCM frequency also clocks a counter called the window counter. When the VCM is locked to
the serial data rate, the decoded output of the window counter generates a waveform called DATA TIME which
is nominally high 10/16ths of a bit cell (count "6" to count "F")l. When thePLL system is in lock the clock bit
occurs between count "6" and count "F". When DATA TIME is high, the pulse generated by the exclusive
OR presets the window counter to "B." If the VCM is in perfect lock with the data as in Figure 5-4.6.2-2, the
window counter is being advanced to "B" at the time of the exclusive OR pulse. If the V CM is running slower
than the data rate, the window counter will be at a count less than "B." Or if the V CM is running faster than the
window counter the count will be greater than "B." These cases are shown in Figures 5-4.6.2-3 and 5-4.6.2-4,
respectively. Due to presetting of the window counter to "B" when DATA TIME is high, the data window
(when DATA TIME is low) tracks the preceding clock bit. Likewise the R input to the MC4044 phase detector
tracks the preceding clock bit.
1

Hexadecimal notation is used in reference to the window counter. The counter has a range 0-15 in decimal which corresponds to 0-Fin
hexadecimal.

5-147

+Data
Out

+ Clk
Out
+R
Clk
Time

D
Serial Read Data

"'" "'"

"'"
"'"

, k
+5 V -'V'V'I.,---,

.051J.F

"'" "'" "'" "'" "'"
"'"
"'"

CEP PE

CET

MC93'6
Prescaler
QO

90 pf

4
R

4044
TC
3
Q2

Phase-Lock Loop

FIGURE 5-4.6.2-1. Floppy Disk IBM 3740 Format
Data and Clock Recovery

5-148

"0" "'"

PO
CET

MC93'6
Window Center

' - - - - - - - - +R
Data
Time

VCM Freq.
+Read Data

.-J

Clk Bit

1 Bit

1-4
+R ead Data -7- 2
+EX OR Out
Window
Counter
+Reference
Clock (R)

.
......

+Oata Out

+R Data Time

Clk Bit

Address Mark 1st Bit Cell

J-------l

--.n

r-------:

1 Bit

1S1t

-L

Missing CIOCk-.J

n'----_

19\A\BIC\OIEIFloI1121314\516\7Ia\g\A\B\clo\E\FloI112\3141516\7Is\gIAIBlc\oIE\FloI1\21314151

____

____-1,--- ------- -

L-J

______

L-J

'---_ _--',------- --- 1_____-----'

+Oata Shift
Register QA
+Clk Out

..J

11--_ _ _ _ _ _ _ _ __

+R Clk Time
+Clk Shift
Register QA
+1 st Bit
Bit Counter

Counter Cleared

_I_

Bit 0

~14

FIGURE 5-4.6.2-2: Data and Clock Recovery Timing

Bit 1

•

VCM Frequency too Slow

- - - - - - - - - - -...,j
......t - VCM Frequency Increases

VCM Frequency
Read Data

EX OR Out

Window Counter
Data Time

-4--

r- - - - - - - - l
r--,

------"I

ElF

Clock Window

Data Window

r--,

/0/1/213

1_____

:- - - - - - - - - -1

15/6

~..

alB

1 C

DIE

Clock Window

IF
..

10111213141516/

1___

Data Window ~.r-

NOTE: The change in VCM Frequency is exaggerated for purposes of illustration.

FIGURE 5.4.6.2-3. VCM Frequency Slower than Data Rate
VI
I

......
VI
o
I..

VCM Frequency too Fast

VCM Frequency Decreases

"I"

VCM Frequency
Read Data

F------,

EX OR Data

Window Counter
Data Time

i-- -- - ---

-1

r-, ______________________________h l

,.--------------------------------~I~I

IBIciDIEIFl0111213141516171al91AIBIcioIBIciDIEIFI
-4-Clock Window ..... 1-4- Data Window ~

I...

Clock Window

- - - - - - - - -,
r--'

I..

011

121314
Data Window

1516/71
..

NOTE: The change in VCM Frequency is exaggerated for purposes of illustration.

FIGURE 5.4.6.2-4. VCM Frequency Faster than Data Rate

The PLL reference frequency (R input to MC4044) is the carry out of the window counter. The
reference frequency of the system is beat against the VCM frequency divided by sixteen which is applied to the
MC4044 V input. When the VCM frequency is too slow the window counter carry out occurs before the VCM
-+- 16 carry out. This results in a "pump up" error voltage signal which causes the voltage at the V CM input to

rise and the VCM frequency to increase. Likewise, when the VCM frequency is too fast a "pump down" error
voltage causes the frequency to decrease.
The "pump up" and "pump down" error voltages are filtered before being applied to the VCM
input. The filter is designed to reduce the effects of the error voltage and gain long term stability. This results in
a data recovery system tradeoff -

long term stability causes long "capture time."

Long term stability is required to enable the system to remain in the lock frequency range when clock
bits are missing, i.e., during address marks. When a missing clock is encountered in the serial data stream, the
window counter is not preset to "B" when DATA TIME is high. Thus the window counter is not corrected.
During this time the window counter acts like a flywheel generating the R input to the MC4044 from the carry
out signal. The PLL system tends to drift upward in frequency. But, because the active filter was designed with
a low leakage the increase in frequency is kept within lock range. The system in Figure 5-4.6.2-1 is designed to

drift through three consecutive missing clock bits.
The tradeoff for long term stability is a longer capture time. Capture time refers to the amount of time
it takes thePLL system to lock to the data rate from an out of lock condition. Figure 5-4.6.2-5 is a representation
of the system response for worst case out of lock condition. The figure is a plot of the voltage input to the
MC4024 VCM. At 4.1 volts the VCM output is at the nominal data frequency. Above 4.1 volts the VCM
5.0

4.8

4.6

~
o

4.4

4.2

4.1

4.0

100

200

300

400

500

600

700

NOTE: "Grass" pulses are pump up/pump
down error voltages.

FIGURE 5-4.6.2-5. PLL Response - Worst Case Capture Time

5-151

1000

frequency is higher than nominal and below 4.1 volts the frequency is lower than nominal. Figure 5-4.6.2-6 is a
plot of VCM frequency versus voltage input.
The design goal for the floppy disk was to insure that the capture time did not exceed six bytes. For
the worst case read data rate, six byte times is approximately 180 /-LS (assuming 30 /-Ls/byte worst case). Six byte
times was chosen because it is the minimum write gate turn on time prior to a data record field.
Once the VCM is locked to the data rate, the window counter's 10/16 decode is used as a bit clock. In
Figure 5-4.6.2-1, each pulse out of the exclusive OR when DATA TIME is high presets the clock out flip/flop.
When DATA TIME is low, the pulse presets the data out flip/flop. On the rising edge of DATA TIME the
content of the data out flip/flop is moved into the data shift register. The content of the clock out flip/flop is
moved into the clock shift register on the falling edge of DATA TIME.
The data recovery signal is not gated on or off. During write the serial read data from the drive
contains no data pulses. Therefore, the MC4024 VCM frequency tends to rise to approximately 6 MHZ. It is
not necessary to get a nominal frequency into the R input of the MC4044 phase detector to keep the frequency
down, but the designer should be aware of the 6 MHZ signal presence during write to ensure that noise is not
picked up in the system.

VIN VS. FOUT
5.0~------------~-----------------T-----------------r----------------~----------------.-----------------~--------------.-------~

C = 62 PF

4.5~------~---------+--------~---------~--------~--------+---~~--r-----~

4.0r-------~---------+--------~----~=-~--------4_--------+_--------~----4

(i)
I-

-l

3.5

>
3.0

+5V

2.5 r--------+---------+---------t----------f

2.0

__________

2.0 MHZ

________

2.7

______________

3.0

______________

4.0

3.5

______________

4.5

______________

5.0

FREQUENCY

FIGURE 5-4.6.2-6 MC4024 Voltage vs. Frequency for Floppy Disk Data Recovery

5-152

__________

______

5.55

6.0

5-4.6.3

Read Data Logic

Figure 5-4.6.3-1 is a logic diagram of the read data logic. Figure 5-4.6.3-2 is a timing diagram
which shows the signal timing relationship when a read operation is begun.
The data recovery circuits are always active. When WRITE GATE is not active to the selected drive,
SERIAL READ DATA is fed to the data recovery circuits. When the recovery circuits are locked to the
incoming data, a clock called R DATA TIME which has a nominal period of 4 microseconds is fed to the Read
Data Logic.
A read operation is begun when the program activates the signal ENABLE eRe (PA2 of PIA #2).
ENABLE eRe removes the reset to the 1ST BIT latch and the bit counter control flip/flop. The 1ST BIT latch
sets when the first" 1" bit occurs on the DATA OUT line. The DATA OUT line goes high when a "1" bit is
present. The bit counter control flip/flop is set at R DATA TIME after the first" 1" bit is present on the DATA
OUT line.
The Me8503 eRe polynomial generator is enabled when the 1ST BIT latch is set. The read error
polynomial check begins to accumulate on the next R DATA TIME clock. The polynomial accumulates
throughout the read operation. The routine keeps track of the number of bytes transferred and, at the end of the
record, checks the eRe = 00 status. The eRe = 00 status signal is stable for one byte period (approx. 32
microseconds). Description of the eRe polynomial generator and its application to floppy disk may be found in
the Me8503 data sheet and Appendix 5-4.D of this section of the applications manual.
The bit counter is held cleared until after the first "1" bit is clocked into the data shift register.
Subsequent clocks then clock the bit counter. The bit counter is an eight bit counter which generates a pulse one
bit period in duration once every eight bits.
The value of the count when the pulse is generated is 7 . If ENABLE eRe was asserted during a gap
the first" 1" bit on DATA OUT is the first bit of an address mark byte. Then count 7 of the bit counter occurs at
bit 7 time (B7 TIME) of each data byte. At the end of B7 TIME the parallel data is transferred from the shift
register to a read data buffer register. The output of the read data buffer register is routed to PAO-PA7 of PIA
# 1. Data is moved into the M6800 system by executing an LDA instruction from Peripheral Register A of PIA
#1.
B7 TIME is also BYTE READY time for a read operation. The leading edge of BYTE READY sets
an interrupt flag in PIA # 1 to indicate to the program that the read buffer has new data.
If ENABLE eRe was not asserted during a gap (i.e., in a record field) the first "1" bit will still set
the 1ST BIT latch and start the bit counter as before. However, the first byte transferred to the read buffer
register and the clock pattern decode (see Figure 5-4.6.1-2) will not indicate the presence of an address mark. In
that case the program will remove ENABLE eRe to restore the Read Data Logic and then reassert ENABLE
eRe to search for an address mark again. This process is repeated until the desired address mark is found or the
read operation is aborted.

5-153

+Clk Time

d=~

"....,

+1 st Bit

Synchronous

Clk
roo--

,.-- J

CLK

~;-

-;-8

Clk

01 0 9

Qo Q1 Q2

SOl
(; CLK
"1"-X
"1"-Y

\)-

AZ ....,
Q8

,r-Z

+Enable Crc

+Data Out

+ Data Time

8503

-b

fr~
-{>r{)o- -

Data
Shift Register

o~
+Enable Wr t

~
-

DE
CLK

Tri-State
Register

-X
~
-

OE
QAQB QC QD

(

1
PIA #1

PRAO-7

FIGURE 5-4.6.3-1. Read Data Logic (Read Shift Register,
Read Buffer, Bit Counter and CRC Check)

5-154

= 0

-Byte Ready

B7 Time

QA QB QC QD QE QF QGQH

DA DB DC DO

r-- -CRC

J
DA DB DC DO
DE
CLK

Tri-State
Register

OE
QA QB QC QD

+R Data Time

~
I

-Enable Crc

+Data Out
+Data Shift
Register QA
+Clk Out

JlJlJ---1

+Clk Sh ift
Register Q A
(+In Sync)

r--J

+1 st Bit

VI
VI

Bit Counter

-Byte Ready

1......_ _ __

J -

......

L-

Counter Cleared

1 4

+RIW Handshake

-ID/Data Clk Mark

+Read Enable

FIGURE 5-4.6.3-2. Start Read Timing

5-4.6.4

Read Operation Program Routine

The read operation is controlled by the routine listed in Figure 5-4.6.4-1. A flow chart of the
program routine is shown in Figure 5-4.6.4-2. This routine is used to execute a general read operation of an ID
or Data record. By "a general read operation" it is meant that the routine obtains the data from the diskette and
stores the data in RAM. Other "non-general" types of read operations would perform more specific tasks than
that stated above. An example of a "tailored" read operation is the UPC Lookup operation which is the subject
of section 5-4.8.
A detailed explanation of the operation is included with the program listing. The following is an
explanation of some of the less straight-forward characteristics of the read program.
The read program of Figure 5-4.6.4-1 can be used to execute either an ID field or data field read
operation. The differences between an ID and data field read operation:
(1) The number of bytes in the field
a. ID field = 7 bytes
b. Data field (fixed format) = 131 bytes
(2) The data portion of the address mark
a. ID field = $FE
b. Data field = $FB
(3) The time interval over which the read operation should be completed.
These three differences are accounted for by requiring the following RAM locations to be initialized
to desired values prior to execution of the read routine:
(1) Byte counter = "FVBCNT"

a. ID field, "FVBCNT" = 256-4
b. Data field, "FVBCNT" = 256-128
(2) Address mark = "FVDMRK"
a. ID field, "FVDMRK" = $FE
b. Data field, "FVDMRK" = $FB
(3) Interval time = "FVTIME"
The value of FVTIME is dependent on the host system requirements.
Note that the byte counter, "FVBCNT," is shown as a number subtracted from 256. "256-4" is
decimal notation of an 8-bit negative binary number which has the magnitude of 4.
First, the magnitude is the number of bytes between the address mark and the first CRC byte (see
Appendix 5-4.D), i.e., the usable data portion of the physical record. The read program of Figure 5-4.6.4-1
does not use the byte counter for keeping track of the address mark byte and the two CRC bytes.
Second, the number of bytes is represented as a negative binary number to take advantage of
MC6800 MPU characteristics. In eight bit signed binary numbers a negative value from -1 to -128 has the
characteristic that the high order bit position (bit 7) is a "1" . Because the maximum byte count for the usable
data portion of the data field is 128, the byte counter will have a "1" in bit 7 throughout the data transfer.
"FVBCNT" is the initial byte count which is loaded into accumulator B prior to entering the basic read loop of
the read program. Then accumulator B is incremented each time a byte of data is transferred. When
accumulator B rolls over to all zeros the basic read loop is exited.

5-156

FLDISK

86619
86628
86638

*
*

FLOPPY DISK READ ROUTINE
THIS ROUTINE READS AND STORES ONE ID OR ONE

* DATA RECORD.

86658
86668
86678
86689
86699
16719
86718
86728
86739

* THE READ DATA RATE IS GOYERNED PRI"ARILY BY
• THE ROTATIONAL SPEED OF THE DISKETTE. THE
• WORST CASE READ DATA RATE IS DETER"INED BY
* ALLOWING FOR THE AC£U"ULATION OF THE
* ROTATIONAL SPEED ERROR DURING THE WRITE
* OPERATION PLUS THE SPEED ERROR DURING THE READ
* OPERATION. THE DESIGN CRITERION OF THIS ROUTINE
* IS TO OPERATE AT "AX/"IH DATA RATES OF,
*
29.75 TO 34.25 "ICROSECOHDS/BYTE

86758
86768
86778
86788

* SYNCHRONIZATION OF PROGRA" Tl"IHG TO THE READ
• DATA RATE IS ACCOHPLISHED BY WAITING UNTIL BYTE
* READY OCCURS. BYTE READY IS RECOGNIZED BY THE
• PROGRA" WHEN THE CAt INPUT TO PIA 11 "AKES A
• HIGH TO LOW TRANSITION AND SETS BIT 7 OF
* CONTROL REGISTER A (IHTERR FLAG 11) TO A ONE.
• THE INTERRUPT fLAG IS POLLED FOR BY THE PROGRA".
* AFTER BVTE READY IS RECOGNIZED THE DATA IS
• FETCHED FRO" THE PIA. "OVING THE DATA FRO"
• THE PIA TO THE "PU AUTO"ATICALLY CLEARS THE
• INTERRUPT FLAG.

86798
86888
86818
86828
86838
86848
86858
86878
86889
86899
86'88

86'18
86928
86938

8'959
86968
8"78
8'988

• THE INTERYAL TI"ER IS USED TO ABORT THE READ
• OPERATION IF THE READ IS NOT CO"PlETED BEFORE
• THE TIKE SPECIFIED IN "FYTI"E- IS EXHAUSTED.
* OTHER ERROR INTERRUPTS IHCLUDE:
•
A.
SYSTE" INOPERABLE
•
8.
OYERRUN
*
C.
NOT READY
•
•
•
•

DATA IS STACKED INTO A BUFFER AREA
SPECIFIED BY THE CONTENTS OF uFYDADR.· WHEN
THE READ OPERATION IS CO"PLETE THE ADDRESS OF
THE LAST DATA BYTE IS TRANSFERRED TO THE INDEX
REGISTER.

86'98

87818

* ACCU"ULATOR

87029

87838
87848
87958
87868

87878
17888
87898

87188

B IS USED AS THE DATA BYTE COUNTER
• IN THE READ ROUTINE. THE INITIAL BVTE COUNT
• I1UST BE STORED IN "FYBCHT.· THIS YALUE IS
• REQUIRED TO BE IN NEGATIYE BINARY FOR"AT.
* USING THE 18" 3748 FOR"ATI THE DATA RECORD IS
• 128 BYTES. THEREFORE THE BYTE COUNTER WILL HAYE
• A • 1" IN BIT 7 THROUGHOUT DATA TRANSFER. THE "I• IN BIT 7 EHABLES ACCUI1ULATOR B TO BE USED AS A
* BIT TEST MASK FOR BVTE READY AS WELL AS A BYTE
* COUNTER.
TABLE 5-4.6.4·1. Floppy Disk Read Routine (Sheet 1 of 5)

5-157

FLDISJ(

87128
87138
87148
87158
87168
87178

• AN OPERATION/ABORT FLAG IS MAINTAINED IN RAM
• LOCATION "FVASOR a AS FOLLOWS:
•
1888188e READ OPERATION IH PROGRESS
•
918818ge READ OPERATION ABORTED BY PROGRAM
•
81181889 READ OPERATION ABORTED BY INTERRUPT
•
88881819
READ OPERATION COMPLETE

TABLE 5-4.6.4-1. Floppy Disk Read Routine (Sheet 2 of 5)

5-158

FlDISK

87288 51E5 86 88
87218 51£7 97 88

FKREAD LDA A
STA A
87228 51E9 8D S8Al
JSR

*
*
*

87248
87258

87268
87278

87299 StEC 86 ES
87388 51E£ 84 8841
87318 51F1 26 74

"FkERST- IS A DISK SYSTE" ERROR LATCH RESET
SUBROUTIHE. THIS ROUTINE ALSO SELECTS THE
DISKETTE DRIVE AND CLEARS PIA 12 ERROR
INTERRUPT FLAGS.
LDt. A
AHD A
BHE

SET ERROR SiATUS MASK
FETCH "ASKED STATUS
BRANCH IF ERROR

'~1118e118

FP2PRB
FKRD89

• ERROR STATUS CHECKED
Bli 8 = HOT IH SYNC
BIT 1 = DISK SYSTE" IHOPERABLE
BIT 2 s OVERRUN
BIT ~ = HOT HEAD LOADED
BIT 6 = HOT READY

87338
87348

*
*
*
*
*

87358
87368
87378

87389
87At81 ~lF3 9F IS
87419 SlFS 9E 07

STS

LDS
LDX

87429 51F7 C£ lFIE
87At31 51FA FF 8842

STX

87448 SlFD DE 89
87458 51FF FF 8810

LDX
STX
LDX
LIA B
LDA A
STA A

87461 5282 CE 3E16

87478
87489
87498
87588
87519
87528

-PRESET READ IN
----PROGRESS OP CODE

1~lee81888

FVABOR
FKERST

5285 D6 8S
5287 86 24

5289 87 a082
528C 86 29
FKRD81 Lift A

BIT B
STA A

528E F5 8888
5211 87 8848

87548
87558

87569
87588 5214 96 85

*
*

FVSVSP
FVDADR

SAVE STACK POIHTER

POIHT TO DATA STACK

1$3FIE
FP2CRA
FVTI"E
FP3PRA
.3E16
FYBCHT

ENABLE ERROR IHTERRUPTS
FETCH TIKER VARIABLE
START IHTERYAL TI"ER
PRELOAD DISABLE INTERRUPTS

LOAD BYTE COUNTER

'%88189188
FP1CRA
ENABLE R/W HANDSHAKE
'~8elelel1
PRELOAD ENABLE CRt

FPIPRA
FP2PRA

CLR BYTE RDY IHTERR FLAC
ENABLE CRC

FOR A READ OPERATION -EHABLE CRC· AR"S THE
READ CIRCUITS TO SYNCHRONIZE TO THE FIRST
H1 8 DATA BIT DETECTED.
LDA A

FVDMRk

87598 5216 76 8881 FKRD82 ROR
87688 5219 24 F8
Bee
87618 5218 F5 8882 FKRD83 BIT B
87629 521E 2A FS
BPL
87638 5228 81 8888
C"P A
87648 5223 26 85
BHE
87658 5225 F5 8881
BIT B
87668 5228 2A 87
BPL
87678 S22A 86 2F
FKRD84 LDA A
87688 522C 87 8848
STA A
87698 522F 28 DB
BRA

FPIPRB
FKRD82
FPICRA
FKRD83
FPIPRA
FKRD84
FPIPRB
FKRD85

PRELOAD DATA "ARK
"OYE 1ST BIT TO CARRY
WAIT UNTIL 1ST BIT
WAIT FOR BYTE READY
CO"PARE "ARK PATTERN
BRANCH IF HOT "ARK
BRANCH IF ID/DATA

1%88181111

FP2PRA
FKRD81

DROP EHABLE CRC
DO AGAIH,LOOK FOR 1ST BIT

TABLE 5-4.6.4-1. Floppy Disk Read Routine (Sheet 3 of 5)

5-159

FLDISK

87718 5231 86 68
FKRD85 LDA A
87728 5233 87 8848
STA A

1%81181811
FP2PRA
RAISE READ EHABLE

87748
877S8
87768
87778
87788
87798

•

87818
87828

• THE FOLLOWING SERIES OF INSTRUCTIONS IS THE
• BASIC READ LOOP

•
•
•
•
•

·RE~D EH~BLE· EHABLES THE HOT IN SYNC
ERROR DETECTION LOGIC. KNOT IN SYNC" IS A
LATCHED ERROR SIGNAL WHICH IS SET WHEN THE
CLOCK RECOYERY CIRCUITS DO NOT
DETECT A MIM BIT AT CLOCK TIME AND MREAD
ENABLE - IS SET.

87848 '236

8882 FKRD86 BIT B

FPICRA

878S8
87868
87878
87888
87898

F KR D86

5239
5238
523E
523F
5248

BPL
LDA A
PSH A
INC B
BNE

86 8888
36
5C

26 F4

87'18 5242 Fl 8882 FKRD87 C"P 8
87928 5245 28 F9
B"I
•
•
•
•

87'48
87'S8
87968
87978
87998
88888
88818
88828
88838
88848
88858
88868
88878
88888
88898
88188
88118

5247 F5
~24A 86
524C C6
524E Fl
5251 28
5253 F4
5256 87
5259 FF
525C 7F
525F 86
5261 87
5264 38
5263 9E

FKRD86

WAIT FOR BYTE READY
GET DATA & CLR INTERR FLAG
STORE DATA
UPDATE BYTE COUNTER
LOOP UNTIL LAST BYTE

FP1CRA
FKRD07

WAIT FOR 1ST CRC BYTE RDY

FP1PRA

ACCU"ULATOR S IS 88 AT THIS TI"E. THE ·C"PB·
AND "S"I- INSTRUCTIONS TEST THE BVTE READY
INTERRUPT FLAG (FP1CRA, BIT 7). IF THE FLAG IS
A ""8· THE PROGRA" LOOPS BACk TO RFKRD87.
It

8888
CLEAR INTERRUPT FLAG
SIT B FP1PRA
2F
LDA A '%88181111
PRELOAD STOP READ
88
LOAD TST CRC MASk
LDA S 1%89881888
8882 FKRD8S C"P 8 FPICRA
FB
FKRD88
WAIT FOR 2ND CRC BYTE
B"I
8881
AND B FP1PRB
FETCH CRC STATUS
8848
STA A FP2PRA
STOP READ
8842
STX
FP2CRA
DISABLE INTERRUPTS
8818
ClR
STOP INTERYAL TI"ER
FP3PRA
34
lDA A 1%88118188
8882
STA A FP1CRA
TURN OFF R/W HANDSHAKE
TSX
XFER DATA POINTER TO INDEX
89
lDS
FYSYSP
RESTORE STACK POINTER
TABLE 5-4.6.4-1. Floppy Disk Read Routine (Sheet 4 of 5)

5-160

FLDISK

98138
98148
88158
88168
88178

5267 D7 81
5269 27 92

5268 C6 42
526D C8 8A
526F D7 89

FKRD89 STA
BEQ
LDA
FKRD18 EOR
STA

88199
88288
98218
88229
88238

*
*
*
*
*

88258
88269
88279
88288
88298
88398

*
*
*
*
*
*

88328 527 1 J 9

B
B
B

FYSTAT
STORE ERROR STATUS
FKRD18
SKIP IF NO READ ERROR
1%81888818
SET OP CODE "ODIFIER
1%88881818
GENERATE ENDING OP CODE
FYABOR
STORE OP/ABORT CODE

THE OP/ABORT CODE IS GENERATED FRO" THE
YALUE OF ACCU"UlATOR B. I F ANY ERROR
STATUS I S PRESENT B I S NON ZERO. IN THAT CASE
THE OP CODE "ODIFIER IS SET. IF NO ERROR STATUS
EXISTS ACCU"ULATOR S IS ZERO. THEN:
ERROR

-------81888819
B =
EOR B • 88881919
_.. _---_....
CODE

81881888

RTS

HO ERROR

---- .. ----

88898898
88881819

- .. -- ... ---

88881818

RETURN TO HOST PROGRA"

TABLE 5-4.6.4-1. Floppy Disk Read Routine (Sheet 5 of 5)

5-161

The above is one use of accumulator B. Because accumulator B has a "1" in bit 7 throughout data
transfer it can also be used as a bit test mask for the BYTE READY interrupt flag. Just prior to new data being
available the BYTE READY signal sets bit 7 of PIA # 1 control register A. To synchronize the program timing
to the read data rate the following instruction sequence is used:
FKRD5
BPL

BIT B FPICRA
FKRD5

The BIT B instruction is an AND operation which affects only the condition code register bits. Since
bit 7 of accumulator B is a "1" , the sign bit (Bit N) of the condition code register is "1" if the BYTE READY
interrupt flag is set and a "0" if the flag is not set. The BPL instruction will cause the program to loop until
BYTE READY occurs.
This programming technique enables accumulator B to serve double duty - byte counter and
interrupt flag test mask. Using this technique results in time savings during program execution. In contrast,
another way to perform the same interrupt mask test is as follows:
FKRD5
BMI

TST FPICRA
FKRD5

Although this instruction sequence performs the same task as the prior sequence in the same number of control
memory bytes, it takes two MPU cycles longer to execute. This means there would be two less cycles of time
available at the beginning and the end of the basic read loop to do necessary housekeeping tasks.
The interval timer is used to abort a read operation if the program should hang up in an infinite loop
due to hardware malfunction. When searching for a specific data record, the ID field must first be read to
determine where the R/W head is relative to the desired data sector. In this case, the interval timer could be
programmed to abort the read operation after the worst case time between any two ID Fields has elapsed. Or the
timer could be set up to abort the operation after one revolution of the diskette. The choice of how to use an
interval timer or even not to use a timer at all depends upon total system requirements.
If a variable interval timer is used, the abort time for a read data field operation after the proper sector
has been located is the maximum time it should take to fully execute the read routine. Allowing for 17 bytes of
prerecord gap plus 131 bytes of data field and interval timer accuracy, the timer should be initialized to:
or

17 + 131 = 148 byte times
148 bytes x 33.74 p,s/BYTE(MAX) + 1.0 ms

= 5.1 ms

In the floppy disk routine, the data is stored in RAM using the PSH instruction. The stack pointer
must be set up prior to executing the read program. One cautionary note should be made:
Because an error interrupt can occur any time the PIA interrupts are enabled, an additional seven
bytes of storage must be allotted for the data storage area. This ensures that if an interrupt occurs
there will be no over write of RAM data.
Figure 5-4.6.4-3 is a system flow chart which shows how the read program routine integrates into a
typical M6800 system. The labels used are:
FKSKIN - Seek Initialization Routine
FKSEEK - Interrupt Driven Seek Routine
FKREAD - Read Routine
FKWRIT - Write Routine
5-162

Note that FKREAD is called by the supervisor in both floppy disk read and write operations. In Figure
5-4.6.4-3 all read and write operations are said to be sector oriented. That is, a read or write data operation
begins only after the desired sector has been located. FKREAD is used to read ID records prior to reading or
writing the data record. To determine if the desired sector has been located after a sector read operation, the data
is pulled from the stack and compared against the desired track and sector address. If the track address does not
match, it is assumed that a seek error has occurred. If the sector address does not match, the read ID is repeated
until the proper sector is located.
Because the orientation of the R/W head is not known at the beginning of the sector search the worst
case is assumed. That is, it is conceivable that one full diskette rotation is required before the desired sector is
located. Prior to the first read ID record the interval timer variable is set to 180 milliseconds. Then after each ID
record, is passed 6 milliseconds is subtracted from the interval timer variable. If there are no hardware
malfunctions, 30 ID records will have been read before an interval timer interrupt aborts the search ID
operation.
Each time a CRC error is encountered a read error counter is incremented. This information is used
in error processing to determine if a retry should be attempted.
Note that if an error interrupt occurs, the program is not returned to by a RTI instruction. This is
typical of time critical operations. Once a timing is lost due to a malfunction, the error processing routines
determine what must be done to recover from the situation.
5-4.7

WRITE OPERATION

An IBM 3740 compatible floppy disk system records data at 250 K bits/second or 4 microseconds/
bit. As in the read operation, the serial data rate is too fast for the MC6800 system to handle. So the formatter
logic performs the function of converting the 8-bit parallel write data to serial data to be recorded on the
diskette.
The write data rate is not subject to the rotational speed variations of the diskette since it is controlled
by a fixed write oscillator (1.0 MHz). Therefore, the variations in write data rate are a function of oscillator
frequency specifications.
Because the write frequency range is small, the MC6800 system clock frequency specifications must
also be considered in calculating program timing requirements for the write operation. One way to minimize
variations is to use the MC6800 1.0 MHz oscillator as the floppy disk system's write oscillator. In this case
theMC6800 system and floppy disk system are synchronized and the net frequency error for a write operation is
zero. Then all timing can be calculated in MC6800 cycles where 32 cycles is equal to one byte. The total system
is synchronous as long as there is no cycle stealing from the MPU as is the case when dynamic RAM is used in
system memory. In a synchronous system, the write program can be optimized by taking advantage of the fact
that all timing can be calculated in terms of cycles. This case will not be documented in this Section.
The more general case is when the write oscillator is separate from the MC6800 system clock or
when the oscillators are common but dynamic RAM memory refresh steals MPU cycles. These are examples of
asynchronous control of the floppy disk. The programs and hardware described in this section are designed to
operate under these conditions.
Three factors affect program timing:
(1) Write Data Rate
(2) MC6800 Clock Rate
(3) Memory Refresh Rate
5-163

Good status results in a 00
byte. A non-zero byte
indicates an error condition.

~ta~us

Clear Byte Ready
Interrupt Flag

The stack pointer is saved as a
return entry pointer after read
complete or aborted.

- 1
I
Address Read Data
Storage with
Stack Pointer

Thi.s resets the serial to parallel
logic because the beginning of
the record was not found yet.

Read data will be stored by
"stacking."

"Read enable" the in sync
error logic on. Until the desired address mark is detected
it cannot be assumed that the
data recovery circuits are
locked to the serial data.

Error interrupts include:
1. R/Werror
a. Disk system inoperable
b. Overflow
c. Not in sync
2. Not ready

For IBM 3740 fixed format:
1. I D record = 4 bytes
2. Data record = 128 bytes

Move Data Byte
to MPU and Clear
Byte Ready
I nterrupt Flag

R/W handshake is enabled by
programming PIA #1 CA 1 and
-CA2 to operate in handshake
mode. (I.E. CA2 set high by an
active transition of CA 1 and
set low by a read peripheral
register A.) CA 1 is the byte
ready signal. CA 1 and CA2 are
used in conjunction to generate
an overrun error if the MPU
read is too late.

"Enable CRC" enables the
serial to parallel logic in the
formatter.

1st bit is set when the first "1"
data bit is detected after
"Enable CRC."

FIGURE 5-4.6.4-2: Read Routine Flow Chart (Sheet 1 of 2)

5-164

Basic Read Loop

If CRC = 00 bit 4 of the
error status byte will be
a 1 bit.

Stop Read
Drop Enable

eRC

Move Data Pointer
to Index Reg

Set Read Abort
OP Code

Clock Through
Two CRC Bytes
Return to
Host Program

FIGURE 5-4.6.4-2: Read Routine Flow Chart (Sheet 2 of 2)

5-165

Floppy Disk System
Read or Write
Operation

Data to be written is stored in
buffer area.
NOTE: Data can be moved to
write buffer area duping interrupt driven
cell.

Determine Record
Track Address and
Sector Address

Store track address in "FVTRKA"
Store sector address in "FVSECT"

"FKSKIN" subroutine prepares
the drive for an interrupt driven
seek routine. "FKSK I Nil generates the first interrupt.

"FKSKIN"

Each step of the seek operation
is called by an interval timer
interrupt. The interrupt routine steps the head one track
and restarts the interval timer.
When the seek is completed or
aborts the interval timer is not
restarted.

NO
Program loops until "FKSEEK"
sets seek complete or abort seek.
NO

YES
NO

Go to Error
Processing

/
Executive processing can include setting up the write
buffer and initializing RAM
memory locations for a read
I D record.

Call "FKREAD"

~
,.,.

Error interrupt generated by
interval timer, index or disk
error detection logic.

0,.

YES

FIGURE 5-4.6.4-3: System Integration of Floppy Disk Routines

(Sheet 1 of 2)
Return to
Executive
Processing

5-166

Go to Error
Processing

"FK READ" is used to locate
____ /' the desired ID sector, i.e., read
I D record.

,.,.

Call "FKREAD"

0,.

YES

CRC
Error

Error interrupt is generated by
interval time out or disk error
detection logic.

YES

Increment CRC
Error Counter

Track
Address
Match

Sector
Address
Match

Go to Error
Processing
The number of CRC read
errors are accumulated for
error processing.

>----..r

YES
Subtract 6 Ms
From Timer
Variable

Read

The interval timer is set each
time "FKREAD" is executed.

Call "FKWRIT"

OP
~~

Error interrupt generated by
interval timer, index or disk
error detection logic.

"0,.

________________~ YES
Write
Complete

YES

Return to
Executive
Processing

FIGURE 5-4.6.4-3: System Integration of Floppy Disk Routines (Sheet 2 of 2)

5-167

Go to Error
Processing

(1) Assume that the floppy disk write oscillator is accurate to 0.1 %. Then the worst case write data

rate extends over:
31.968JLs/BYTE ~ WRITE RATE ~ 32.032JLs/BYTE
(2) Assume that the MC6800 write oscillator is also accurate to 0.1 %. Then the worst case MC6800
clock rate extends over:
0.999JLs/cycle ~ CLOCK RATE ~ 1.001JLs/cycle
(3) Finally assume the dynamic memory refresh steals one clock cycle out of 50 (for a memory with
32 cycle refresh this corresponds to a memory refresh rate of 32 x 50 = 1.6 ms at a 1JLs clock
rate). Dynamic memory refresh is discussed is Section 4-2.5.1 of this manual.
The memory refresh and write rate can be treated as a two service request system for purposes of
calculations. Explanation of this type of calculation is the subject of Section 2-3.
In the maximum worst case memory refresh uses 1.001JLs out of 50.05JLs.
Let T20

= 49.95JLs
. 999JLs

T21 =
For the floppy disk

T10 = 31.968JLs
From Section 2-3.
TIl
T21
__
+ __
T10

T20

TIl

--+
31.968

TIl

NOTE: .999
49.95

1.001

50.05

= ----

31.328JLs

at 1.001p.s/MPU Cycle
31.328
1.001 ~ 31.297 ~PU cycles/byte

This means that the write data processing must not exceed 31 MPU cycles per byte.
The preceding analysis shows the effect of system specifications on the floppy disk write program.
The write data loop section of the program must not exceed 31 cycles.
Suppose, however, the dynamic refresh rate requirement was one out of 32 MC6800 clocks for a

5-168

memory with 64 cycles refresh this corresponds to a refresh rate of32 x 64 = 2.048 ms at a 1J.Ls clock rate. The
analysis in this case shows:
TIl

30.969

or in terms of MPU cycles:
30.93 MPU cycles/byte
This means that, given these specifications, a write data loop of30 cycles is maximum. In this case a
31 cycle write data loop can not be guaranteed to work.
The final case to be considered is:
(a) The write oscillator is derived from the 1 MHz MPU clock
(b) The dynamic refresh is one out of 32 MPU cycles (worst case).
In this case the data rate tolerance is the same as the MPU clock tolerance. If the clock tolerance is 1.0% then the
write data rate range is:
31.68J.Ls/Byte ~ WRITE RATE ~32.32J.Ls/Byte
From section 2-3.
TIl

-+-=
TIl

31.3 MPU cycles

Because the clock sources are common the tolerances are cancelling. The resultant maximum
execution time can be written in MPU cycles.
Other requirements outlined in Section 2-3, must also be met to ensure successful operation. As in
the case of the Read Operation in Section 5-4.6, the key to programming and designing the data handling
hardware is to work within the framework of the worst case specifications of the system - both the MPU and
the floppy disk, as well as any other system components (Le. dynamic memory).

5-4.7.1

The Write Operation Interface
Figure 5-4.7.1-1 is a block diagram which shows the major formatter functions used in a write

operation.
In a write operation, PIA # 1 is programmed as an output port. Both the clock pattern and data
pattern are supplied by the MC6800 system.
Before beginning the write operation, the ABOVE TRK 43 signal is set or cleared by the program. If
the program determines that the track location is greater than 43 the signal is raised high. ABOVE TRK 43 is
used by some models of diskette drives to control the write current on inner tracks.
A write operation is begun by making ENABLE WRT active to the formatter. This signal conditions
the formatter circuits to begin accepting data and clock information from PIA #1. the ENABLE WRT signal
also permits the BYTE REQUEST to pulse the CAl input of PIA #1 once every eight bit times.

5-169

(

CA1

-Byte R equ est

r--..

CA2

+R/W Handshake

PA1

--..

PA2

-.--

-..

--..

PA3
PA4
PA5
PA6
PA7
PIA #1

...

.-.

PAO

----

PB2

...
'\',t:>:

PB5

--..

....,...~

)

::'~

;

~
~
~

....

Write
Logic

+Serial Write
Data

r----+
~

PB1

PBO

~ ...

,;;,'

.• , •. ""Xl;...':2;,. •• ·~

PB6

PB3

r:'';

~
-.

PB7

PB4

) r\r~!~;~; :"~:,

+Above Trk
CB2

CB1

:
.I

+1 ndex

CB1
CB2

PB2
PB3
PB4
PB5
PB6
PB7
PIA #2

+Disk Sys Inop

f--

I-

+ F lie I noperab Ie

+Wrt Protected

/
)

+Underflow

+R/W Error

PBO
PB1

Error
Detect

'"'''J

~{>o-

-Head Load
-Ready

+Index

H>o~
-

....,

r"-'

- ..
DISKETT E
DRIVE

PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
CA2
CA1
(
.)

--..-

.,.,
V~~

-File Inop Reset
-Disk Select

-----..

-Shift Crc

-Ready

-Enable Crc
-Enable Wrt
-Write Gate

l,/""

"V"

FIGURE 5-4.7.1-1. Write Operation Interface

5-170

(
)

Serial data is gated into the diskette drive when WRITE GATE is made active.
In a write operation, a gap of all zeros is written in accordance with the IBM 3740 format. Then an
address mark is written with a special clock pattern. The address mark is followed by 128 bytes of data (data
field) or a 4 bytes of data. (lD field) and 2 CRC bytes.
ENABLE CRC is made active by the program at address mark time.
After the last byte of data has been transferred by the program, the SHIFT CRe is made active.
SHIFT eRe is dropped two byte times after it is raised. This causes the 2 byte CRC code to be appended to the
data record.
One byte time after the 2nd CRC byte, all the write control lines are dropped. The sequence diagram
of the write control signals is shown in Figure 5-4.7.1-2.

Gap

Enable Wrt

Enable CRC

- Shift

- Write Gate

----,L.___---.,;I~______________+:-~It__.....
I
I

----------------------------------~lUl
~I--------CRC
I
I

FIGURE 5-4.7.1-2. Write Control Signal Sequence

Other control signals required to be active for a write operation are DISK SELECT (required for
some models of Diskette Drives) and HEAD LOAD.
The FILE INOP reset is used to clear any error conditions detected by the logic.
The operation of CA 1 & CA2 of PIA # 1 (BYTE REQUEST & R/W HANDSHAKE) is described in
Section 5-4.3.
The status signals which describe the operating condition of the floppy disk system during the write
operation are also described in Section 5-4.3.

5-4.7.2

Formatter Write Logic

The formatter's write logic is shown in Figure 5-4.7.2-1. Timing diagrams for the beginning and
ending of a write operation are shown in Figures 5-4.7.2-2 and 5-4.7.2-3.
ENABLE WRT enables the write logic by removing the reset to the bit counter, enabling the parallel
load to the clock and data shift registers, and removing the reset to the serial data flip/flop. The write oscillator
advances the bit counter and shifts the shift registers every 4/Ls. At bit counter 7 time the shift registers are
loaded with PIA # 1 data. Note that the clock shift register and data shift register are 1800 out of phase. The data
shift register is loaded on the trailing edge of bit 7 time (or leading edge of bit 0 time) and the clock shift register
is loaded in the middle of bit 7 time.

5-171

r---

+Shift Crc

~p-----+------+EnableCrc-------------------------------------------r---,
Bit Counter

"1'~

Synchronous

r--I Clk

-;'-8
Clr 00 01 02
\

+Enable Wrt

r-tSr-P

•

f§

SOI

"1"

Clk
X

"1"

01 09
SOO

--+--+--.....

1-1

MC8503
Clr

-L

(

..--....J

1MHz
Crystal
Oscillator

ffir-t:~
0
0

p--

I I

PA P B Pc Po PE PF PGPH

IClk

?
I I I I I I I
PIA #1 PRS 0-7

Data Shift Reg

(

PIA #1 PRA 0-7

)

I I I I I I I I

P A P B Pc Po PE PF PG PH

Clk
Clock Sh;ft

r-Pt4-

L-------------------------------------------------------------~-----------ByteRequest

Serial
Data

F~O

r~
FIGURE 5-4.7.2-1. Floppy Disk Write Logic

+Serial
Write
Data

+500 kHz
+250 kHz
-Enable Wrt
Bit Count

-4-0

-Byte Request
-Enable Cre

16 I 7 I
L.-J

(

~
~

-8503 SR Input
+Clk SR QH

1 7

r--

+Data SR QH
+Serial Data F/F {Q}

--'---,-Serial Write Data

FIGURE 5·4.7.2-2. Beginning Write Data Timing

-.l
W

-Enable Wrt
Bit Count

-Byte Request

\31415161710

L.-J

1213141516171011\

-Enable Cre
+Shift Cre

---.J

-8503 SR Input
+Clk SR QH
+Data SR QH
+Serial Data F IF {Q}

CDCDCIDIC
Record '

_\_

Appended Cre

-Serial Write Data

FIGURE 5-4.7.2-3. Append CRC Timing

_I"

PostAmble

Serial data in digital frequency modulation format is generated by the serial data flip/flop and a NOR
gate. The flop/flop is clocked at twice the bit rate. The serial clock and data patterns are moved into the flip/flop
on alternate half bit cells. The resulting serial data output is gated by the 2x bit rate clock to develop a digital
frequency modulated serial data stream.
After the program moves the address byte into PIA # 1, the ENABLE CRC is made active. Then at
the trailing edge of the next bit 7 time the MC8503 Polynomial Generator is enabled. A CRC check polynomial
is generated until the SHIFT CRC signal is activated by the program. At the trailing edge of bit 7 time the
accumulated CRC character is serially gated into the serial data flip/flop in place of the data pattern. 16 bits of
CRe are appended to the end of the data before the program drops SHIFT CRC.
One byte time after the CRC pattern is recorded the program drops ENABLE WRT. and WRITE
GATE.
5-4.7.3

Formatter Error Detect Logic

The Error Detect Logic in Figure 5-4.7.3-1 traps logical malfunctions which could occur in the
diskette drive or formatter logic. When an error condition is trapped, an interrupt (R/W ERROR) is made active

+Overrun
or
Underflow
+B7Time---------;----------~

+R /W Handsh ake - - - - - t - - - - - 4 : - - ,
+Sync'd Enable Crc----r--.

+F ile I n o p e r a b l e - + - - - - - + - - + - - - - - - - - .
+ E nabla W rt ---'.-------+~I'-I
+Wrt Protected

X)----------

-----+--+---1

+Disk Sys
Inoperable

+R/W Error

+In Sync
+Enable R e a d - - - - - + - - + - - - I
> - - - - - t - - - - - + N o t in Sync

+F ile Inoperable
Reset

FIGURE 5-4.7.3-1. Error Detect Logic

5-174

to the MC6800 system via PIA #2. The trapped conditions are:
(1) OVERRUN/UNDERFLOW

(2) DISK SYSTEM INOPERABLE
(3) NOT IN SYNC
The OVERRUN/UNDERFLOW flip/flop is set when the write program does not respond to the last
BYTE REQUEST service request before the next BYTE REQUEST (Le. the data is not refreshed in PIA #1).
This operation is discussed in section 5-4.3.
The DISK SYSTEM INOPERABLE signal is active when the diskette drive status signal FILE
INOPERABLE (See appendix 5-4.A, 5-4.B & 5-4.C) or when WRITE ENABLE and WRITE PROTECTED
set the error latch in Figure 5-4.7.3-1.
The Error Detect Logic is designed such that when any error condition is detected the R/W ERROR
signal inhibits the setting of other error latches. Thus, the original cause of the failure is preserved for diagnostic
purposes.
When an error condition is detected, the drive control signal WRITE GATE is disabled to prevent
any further loss of data.
5-4.7.4

Write Operation Program Routine
The write operation is controlled by the routine listed in Figure 5-4.7.4-1. A flow chart of the

program is shown in Figure 5-4.7.4-2. This routine is used only to execute a write data record field. The index
address mark and ID record fields are written under control of a special program called Format Write. Deleted
data address marks are also written under control of the Format Write routine. The Format Write routine is not
shown in this Manual.
A detailed explanation of the operation is included with the program listing. As in the case of the
read operation, error interrupts abort the write operation. The error recovery routines are not included in this
Section. The following is an explanation of some of the unique characteristics of the write program.
Index Error - The IBM 3740 format is such that the index pulse should not be detected until after
the 26th record is recorded. Therefore, if index is encountered, the write operation is aborted by an index
interrupt.
Basic Write Loop -

In Section 5-4.7 the timing considerations of the write operation were

described. The following is the write data loop:
CYCLES
FKWRD06 LDAA
FKWR07
BITB
BPL
STAA
BIT B
DEX
BNE

FKDATA,X
FP1CRA
FKWR07

5
4
4

FP1PRB
FP1PRA

5
4

FKWR06

4
4
30 Cycles

5-175

FlDISK

FLOPPY DISK WRITE DATA ROUTINE

88488

•
•
•
•

THIS ROUTIHE OBTAINS BYTE PARALLEL DATA FRO~
RA" STORAGE AND "OYES·THE DATA TO THE DISK
FOR"ATTER. DATA IS THEN WRITTEN ON THE DISKETTE
IN SERIAL.

88428
88438
88448
88458
88468

• A CRVSTAL OSCILLATOR IS USED TO GENERATE THE
• WRITE FREQUENCY. THEREFORE, THE WRI TE DATA
* RATE WILL DEYIATE ONLY SLIGHTLV. THIS ROUTIHE
• WILL OPERATE WITH AS "UCH AS + OR - 5%
• FREQUENCY DEYIATION.

88488
88498
88588
88518
88528
88538
88548
88558
88568

•
•
•
•
•

88378
88388
883"

88578

885S8
88598
88688

•

DATA IS "OYED FRO" ME"ORY USIHG INDEXED "ODE
ADDRESSING. THIS ROUTINE USES THE INDEX REGISTER
AS BOTH A "E"ORV ADDRESS REGISTER AND AS A
BYTE COUNTER. BECAUSE OF THE TIMIHG REQUIREMENTS
OF THE FLOPPY DISK THE INDEX REGISTER IS TESTED
FOR ZERO TO DETERftINE THE END OF THE DATA
TtANSFER. TESTING FOR ZERO PLACES ADDRESSING
CONSTRAINTS ON THE LOCATION OF THE WRITE DATA
STORAGE AREA. THE HIGHEST ADDRESS OF THIS AREA
IS DETER"INED BY ADDING THE "A~I"U" OFFSET
YALUE TO THE DATA LENGTH:
"AX ADDRESS = 255 (OFFSET) + 128 (DATA)

88628
88638
88648
88658
88668

•
•
•
•
•

THE INTERYAL TIMER IS ARftED TO INTERRUPT THE
SYSTEM AFTER 4.6 "ILLISECONDS. THIS INSURES
THAT IF THERE IS A HARDWARE "AlFUHCTION THE
ONLY RECORD AFFECTED IS THAT ONE WHICH WAS TO
BE WRITTEN.

88688
88698
88789
88719
88728

•
•

OTHER ERROR INTERRUPTS INCLUDE:
A. SYSTE" INOPERABLE
B. UNDERFLOW
C. INDEX
D. HOT READY

88749
88758
88768
88778

•
•
•

*
*

•

= 383

• THE -ABOYE TRK 43- SIGNAL IS SET TO A -1- OR
* -8- PRIOR TO BEGINNING THE DATA TRANSFER. THE
* RA" LOCATION -FVTRKA- IS USED TO DETER"INE THE
• PRESENT LOCATION OF THE HEAD.
TABLE 5-4.7.4-1. Floppy Disk Write Data Routine (Sheet 1 of 5)

5-176

FLDISK

*
*
*
*
*
*
*
*

88798
88888
88818
88828
88838
88848
88858
88868
88878
88888
88898

SYNCHRONIZATION OF THE WRITE DATA RATE TO THE
PROGRA" IS ACCO"PLISHED BY WAITING UNTIL A BYTE
REQUEST OCCURS. THIS WAIT LOOP CONSISTS OF
TESTING BIT 7 OF PIA 11 CONTROL REGISTER A
AND LOOPING BACK TO TEST THE BIT AGAIN IF IT
HAD BEEN -8.- AFTER R -1- BIT IS DETECTED
A DATA BYTE IS "OYED TO THE PIA. AFTER
THE BYTE HAS BEEN "DYED A DU""Y READ CLEARS
• THE INTERRUPT FLAG. FAILURE TO EXECUTE THE
* DU""Y READ BEFORE THE NEXT BYTE REQUEST WILL
* CAUSE AN UNDERFLOW ERROR SIGNAL TO LATCH.

88918
88928

• WHEN THE WRITE ROUTINE IS COKPLETED OR ABORTED
* THE PIAJS ARE RETURNED TO READ "ODE.

88948
88958
88968
88978
88988
88998

• AM OPERATION/ABORT FLAG IS "AIHTAINED IN RAK
• LOCATION -FYABOR- AS FOLLOWS:
*
18888188 WRITE OPERATION IN PROGRESS
•
81888188 WRITE OPERATION ABORTED BY PROGRAK
*
81188188 WRITE OPERATION ABORTED BY INTERRUPT
•
88888118 WRITE OPERATION CO"PLETE
TABLE 5-4.7.4-1. Floppy Disk Write Data Routine (Sheet 2 of 5)

5-177

FlDISI(

89828
89838
89848
89858

5272
5274
5277
5279

FICWRIT lDA A
86 EF
AND A
84 8841
97 81
STA A
BEQ
27 85

• ERROR STATUS CHECKED:
•
BIT 8 = HOT IN SYNC
•
BIT 1 = DISK SYSTE" INOPERABLE
* BIT 2 = UNDERFLOW
•
BIT 3 = WRITE PROTECTED
•
BIT 5 = HOT HEAD LOADED
•
BIT 6 = NOT READY
•
BIT 7 = INDEX

89878

89888
89898
99188
99118
89128
89138
89148

LDA A
STA A
RTS

89168 5278 86 44
89178 527D 97 88
89188 527F 39
89288 5288 9F 88
89218 5282 86 84

FKWR81 STS

89228 5284 97 88
89238 5286 CE FF88
89248 5289 FF a989

89268

•
•

89278

89288

89388 528C 86 AD
89318 528E 87 8848
89338
89348
89358
89368
89379
89388
89398
89488
89428
89438
89448
89458

1%11181111
SET STATUS "ASK
FP2PRB
FETCH "ASKED STATUS
FVSTAT
STORE ERROR STATUS
FKWR81
BRANCH IF STATUS GOOD

1%81880198
FYABOR
STORE ABORT CODE
RETURN TO HOST PROGRAM

LDA A
STA A

FYSYSP
SAVE STACK POINTER
'''18888188
FYABOR
STORE WRITE OP CODE

L DX

I.FFee

STX

FPIPRA

"OYE GAP PATTERN TO PIA

-FF w IS "OYED TO FPIPRA AND M99" IS MOYED TO
FPIPRB. -FF- IS THE GAP CLOCK PATTERN AND
-88- IS THE GAP DATA PATTERN.

LDA A
STA A

1%18181181
FPZPRA
ENABLE WRITE

• -EHABLE WRITER GATES THE FOR"ATTER WRITE
* CIRCUITS ON. BECAUSE -WRITE GATER IS OFF THE
• SERIAL DATA IS NOT TRANSFERRED TO THE DRIVE.
• ALSO, THE READ STATUS SIGNALS WHICH ARE ROUTED
* TO PIA 11 ARE SWITCHED TO A HIGH IMPEDANCE
* STATE BV uENABlE WRITE- IN PREPARATION TO
• CHANGING THE PIA 11 I/O LINES FROM INPUTS TO
• OUTPUTS.
5291
5294
5297
529A

CE
FF
CE
FF

3838
8882
FFFF
8888

LDX

STX
LDX
STX

1$3838
FPICRA
'$FFFF
FPIPRA

SELECT DIRECTION REGS

DEFINE PIA 11 LINES OUTPUTS

TABLE 5-4.7.4-1. Floppy Disk Write Data Routine (Sheet 3 of 5 )

5-178

FlDISI(
LDA
LDft
C"P
BHI
82
LDA
23
13
FKWR82 EOR
STA
8883

89478 529D C6 34
89488 S29F 86 29
89498 52Al 91 84

89588 52A3 22
89518 S2A5 86
89528 52A7 88
89538 52A9 87

89558
89568

*
*

99589
89598

*
*
*
*
*

99688
99619
89628
99638

•

89658

*
*

89668
99670

89698 52AC

89898
89988
89918
89928
99939
89948

52D5
52D7

52DA

52DD F5
52E2 F6

99958 52E5 CE
89968 52£8 85
89978 52E8 2A

99988 52ED 87

43-8

88188811

IF THE TRACK IS GREATER THAN 43 THE CB2 SIGNAL
PIA 11 IS SET TO A HIGH. ALSO PERIPHERAL

FP1CRA

lDA B

'256-5
SET BYTE COUHTER
5
'%88188188
PRELOAD R/W HANDSHAKE

SELECT PERIPHERAL REG A

IS188US+46
FP3PRA
AR" Tl"ER FOR 4.6 "S
'$C7FB
PRELOAD ADDRESS "ARK
FP2PRA
SET WRITE GATE

LDX

S848

SERIAL WRITE DATA IS CATED IHTO THE DRIVE AT
THIS TI"E.

elR BYTE REQUEST
SET R/W HAHDSHAKE
PRELOAD ENABLE CRe
A '~18181888
B FPICRA
WAIT FOR BYTE REQUEST
FKWR83
CLR INTERRUPT FLAC
B FPIPRA
UPDATE BYTE COUHTER
B
LOOP UNTIL lAST GAP BYTE
FKWR83
B FPICRA
FKWR84
WAIT FOR BYTE REQUEST
FPIPRA
"OYE ADDR "ARK TO PIA
ENABLE C.C
A FP2PRA
FPIPRA
CLEAR INTERRUPT FLAG
8IT 8
a988
PRELOAD ClK PATTERN
LDA A I$FF
FF
GET 1ST DATA BYTE
LDA 8 FKDATA+128
817F
1127
LOAD BYTE COUNTER
se7F
LDX
8882 FKWR85 BIT A FPICRA
WAIT FOR BYTE REQUEST
FKWR85
FS
BPL
"OYE elK PATTERN TO PIA
STA A FPIPRA
8888

BIT
STA
lDA
BIT
8PL
F9
a888
81T
INC
SHE
26 F5
Fl 8882 FKWR84 C"P
28 F9
8"1
STX
FF 8888
STA
87 8848

52E8 86

DEC

89878 52D8

=/(

88118188

88181811

lDA A

TRK

88111188

8882

FOR" TRK ) 43 COHTR WOR
SET ABOVE TRK 43

1~11818811

FPICR8

89758 52BC

89888 52D2

FPICRB

88818111

L DX

99888 528F F5
99818 52C2 87
89828 52C5 86
89838 52C7 F5
99848 52CA 2A
89838 52CC F5
89868 52CF 5C

A
A

TEST TRK ADIR > 43
BRANCH IF > 43

88818111

STX

89778

FYTRKA
FkWR82
143-8

PRELOAD FP1CRA CONTROL

43 =
EORI

CE 832E

89780

1%88118188
143

TRK ) 43

89738 5286 FF a818
99748 5289 CE C7FB
7A

THE TRk > 43 CONTROL WORD IS GENERATED FRO" THE
VALUE 43 AS FOLLOWS:

89788 S2AF C6 F9
89718 5281 86 24

89728 5283

8888
8982
AS
8882 FKWR83

B
A

FPIPRA
FPICRA

TABLE 5-4.7.4-1. Floppy Disk Write Data Routine (Sheet 4 of 5)

5-179

FLDISK
STA 8

89"8 52F8 F7 8881
18888 52F3 FS 8888
18819 52F6 C6 A8

FPIPRB
FPIPRA

"OYE 1ST BYTE TO PIA
. CLR INTERRUPT FLAG
1%10188098
PRELOAD SHIFT CRC

• THE FOLLOWING SERIES OF INSTRUCTIONS IS THE
• BASIC WRITE LOOP.

18838

19848
19869 52F8
18878 52FA
19888 52FD
19898 52FF
18188 5382
18119 5385
19128 5386

BIT 8
LDA B

FKWR86 LDA A

A6 FF

F5 8882 FKWR97 BIT B
BPL
2A FS

STA A
BIT B
DEX
SNE

B7 S8S1
F5 8980

89
26 F8

STA B
19148 5388 F7 8849
191~8 5388 F~ 8082 FKWF.98 BIT B
BPL
19169 538£ 2A Fe
BIT B
18178 5318 FS 8880
CLR
18188 5313 7F 8881
LDA A
18198 3316 86 AD
LDA B
18288 5318 C6 A8
19218 531A FS 8082 FKWR09 BIT B
BPL
18228 531D 2A FS
BIT B
19230 531F F5 8889
STA B
18248 5322 F7 8848
L DX
19259 5325 CE 3E16
LDA B
19269 :5328 C6 AF
19270 532A F5 8882 FKWR19 BIT B
BPL
19288 532D 2A F9
STX
19298 :532F FF 8042
LDX
18390 5332 CE 3038
STX
18318 5335 FF 8882
STA A
18328 5338 87 8848

FKDATA,X
FPICRA
FKWR97

FPIPRB
FPIPRA
FKWR86

FETCH NEXT DATA BYTE
WAIT FOR BYTE REQUEST
"OYE DATA TO PIA
CLR INTERRUPT FLAG
DECREMENT BYTE COUNTER
LOOP UNTIL LAST BYTE

SHIFT CRC
FP2PRA
FPICRA
FKWR08
POLL FOR 1ST CRe BYTE
FPIPRA
CLR INTERRUPT FLAG
FPIPRS
"OYE M90 u TO DATA PIA
'%10191191
PRELOAD DROP WRITE GATE
1~101910e0
PRELOAD STOP SHIFT CRe
FPICRA
FKWR99
POLL FOR 2ND CRe BYTE
FPIPRA
CLR INTERRUPT FLAG
FP2PRA
STOP SHIFT CRC
1$3E16
PRELOAD DISABLE INTERRUPTS
1~191el111
PRELOAD STOP WRITE
FPICRA
POLL FOR LAST BYTE REQUEST
FI

"'" J-0

-Index Clk Mark
~

-J

t>--

rl---J

+Oata Out

.,..

+Enable Wr t

r-;--

+Enable Cr :

-{>-

"'"-

D-

SOO

*
4

I
5

,--C

)

PIA#1 PRB 0-7

-CRC = 00

.1.

+1 st Bit

0A DB DC 000EOF DG 0H

Load

Clk

j3=>-

8-Bit Shift Register

~--l-

AZ
08

CLR

°AOBOCOD
I

...I,,-,~

"{l

8503
P-Gener.

1- X
1- y

SOl
Clk

-ID/Data C Ik Mark

-Load St ift
Registel

-R/W Dc ta
Time

i--'

\0
\0

I~-

"1"
CEP Synchronous
CET
Binary
Counter
~ f - - CLK
CLR 00010203
"1 ;;

.-d-

1Ql1

I~-

DE °A DB DC 0D

-:;:-

CLK Tri-~tate
Register
OE

---

°AOBOCOD

These lines also
used in R/W clk
logic (Figure 5-4.9-2)

PIA #1 PRA 0-7
)

+Clk Shift
RegO H

+Data Time

I
1 MHz
Write
Osc

r+2
'--

CLK
OE

°AOBDCOD
Tri-State
Register
OA OBOC OD

--.!

CJ
-

H-

]

FIGURE 5-4.9-1. Combined ReadIWrite Data Logic

67 Time

-Byte Reque stl
Byte Ready

r--

1;-

,...

+Serial

pWrite
Data

234567
PIA #1 PRA 0-7

+Read Data Sit 7

5
4

3
2

o
-Load Shift
Register
+Clk Out
-RAN Data
Time

-T
La

Load

Clk

DADS DC DO DEDFDG 0 H
8-Sit Shift Register

QAQSQCQDQEQFQGQH
+Clk Shift
Reg QH

-S7 Time

~~~~

-Data/I 0
Clk Mark

...--- C
~

~t--IP
~

0
C

r--

-Index

'---

+In Sync
+Enable Wrt

FIGURE 5-4.9-2. Combined Read/Write Clock Logic

+Overrun
or
Underflow
+S7 Time - - - - - - - + - - - - - - - - ; Clk
+RAN Handshake------~--~--~
+Sync'd Enable C r c - - - ' - - - '

+F ile I noperable-4------4--~-----------......,
+E nable Wrt - .....------+-+_.
+Wrt Protected

Sys
x.-.------- I+Disk
noperable

------~-+___1

+RAN Error

+lnSync
+E nable Read - - - - - - - 4 - - + _ _ _ 1
' > - - - - - t - - - - - - + N o t in Sync

+F i Ie Inoperable
Reset

FIGURE 5-4.9-3. Error Detect Logic

5-200

APPENDIX 5-4.A
SHUGART ASSOCIATES
SA900/901
Diskette Storage Drive
SPECIFICATION SUMMARY
Performance Specifications
Capacity (Unformatted)

Per Disk
Per Track

Data Transfer Rate
Access Time

3. 1 megabits
41 kilobits
250 kilobits/second

Rotational Speed

10 MS
10 MS
260MS
360 RPM

Average Latency

83 MS

Recording Mode

Frequency Modu lation

Average Access Time

Track to Track
Settling Time

Media Characteristics
Cartridge Required

SA900
SA901

SA 100 or I BM "Diskette"
SA101

Physical Sectors

SA900
SA901

o
32

Index

Tracks
Density

Recording
Track

3200 bpi (approx. inside
track)
48TPI

Additional Features for SA900/901
50 Hz - 100 VAC, single phase
60 Hz - 208/230 VAC, single phase
50 Hz - 208/230 VAC, single phase
Write Protect (SA901 only)
-12 or -15V option to replace -5V input
Chassis Slide
10%" High Front Plate for use with
Chassis SI i de
5.25" x 11" Front Plate
5.25" x 10" Front Plate
READ ERROR RATE

SEEK ERROR RATE

1 x 109 bits read/soft error (nominal)

1 seek error in 106 seeks

1 x 10 12 bits read/hard error (nominal)
5-201

FIGURE 5-4.A-2. Loading SA900/901

5-202

SA900/901
DISKETTE STORAGE DRIVE
FUNCTIONAL CHARACTERISTICS
GENERAL OPERATION
The SA900/901 Diskette Drive consists of read/write and control electronics, drive mechanism,
read/write head, track positioning mechanism, and the removable Diskette. These components perform the
following functions:
• Interpret and generate control signals.
• Move read/write head to the selected track.
• Read and write data.
The relationship and interface signals for the internal functions of the SA900/901 are shown in
Figures 5-4.A-3 and 5-4.A-4 respectively.
The Head Positioning Actuator positions the read/write head to the desired track on the Diskette.
The Head Load Actuator loads the Diskette against the read/write head and data may then be recorded or read
from the Diskette.

SEP DATA
4

SEP CLOCK
UNSEP READ OATA

READ SIGNAL

READ
LOGIC

LIGHT
_____ EMITTING
~
DIODE

I
I

WRITE DATA
WRITE GATE
FILE INOPERABLE
FILE INOPERABLE RESET.

WRITE
AND
SAFETY
LOGIC

WRITE SIGNAL

HEAD
POSITION

I
I

~-----r-'

POWER ON
RESET

I
I

HEAD LOADED

STEP

ACTUAT~

I
~

HEAD LOAD ACTUATOR

DIRECTION SELECT
HEAD LOAD
CONTROL
LOGIC
INDEX

1>3

TRACK 00
LIGHT EMITTING DIODE
LIGHT EMITTING DIODE
INDEX

FIGURE 5-4.A-3 SA900 Functional Diagram, One Sector Hole

5-203

LIGHT EMITTING DIODE

SEP DATA
READ
LOGIC

SEP CLOCK

LIGHT
EMITTING
DIODE

UNSEP READ DAT.A

WRITE DATA
WRITE GATE
FILE INOPERABLE
FILE INOPERABLE RESET..

WRITE
AND
SAFETY
LOGIC

WRITE HEAD

WRITE PROTECT
POWER ON
RESET

HEAD LOADED

STEP
HEAD LOAD ACTUATOR
DIRECTION SELECT
HEAD LOAD
SECTOR

CONTROL
LOGIC

INDEX

1/>3

TRACK 00
LIGHT EMITTING DIODE
LIGHT EMITTING DIODE

FIGURE 5·4.A·4 SA901 Functional Diagram, 32 Sector Holes

The electronics are packaged on one PCB. The PCB contains:
(1) Index Detector Circuits (Sector/Index for 901).

(2) Head Position Actuator Driver
(3) Head Load Actuator Driver
(4) Read/Write Amplifier and Transition Detector

(5) Data/Clock Separation Circuits
(6) Safety Sensing Circuits
(7) Write Protect (SA901 only)

An electrical stepping motor (Head Position Actuator) and lead screw positions the read/write head.
The stepping motor rotates the lead screw clockwise or counterclockwise in 15° increments. A 15° rotation of
the lead screw moves the read/write head one track position. The using system increments the stepping motor to
the desired track.
The Diskette drive motor rotates the spindle at 360 rpm through a belt-drive system. 50 or 60 Hz
power is accommodated by changing the drive pulley. A registration hub, centered on the face of the spindle,
positions the Diskette. A -clamp that moves in conjunction with the latch handle fixes the Diskette to the
registration hub.
The read/write head is in direct contact with the Diskette. The head surface has been designed to
obtain maximum signal transfer to and from the magnetic surface of the Diskette with minimum head/Diskette
wear.

5·204

The SA900/90l head is a single element read/write head with straddle erase elements to provide
erased areas between data tracks. Thus normal tolerance between media and drives will not degrade the signal
to noise ration and insures Diskette interchangeability.
The read/write head is mounted on a carriage which is located on the Head Position Actuator lead
screw. (See Figure 5-4.A-5) The Diskette is held in a plane perpendicular to the read/write head by a platen
located on the base casting. This precise registration assures perfect compliance with the read/write head. The
Diskette is loaded against the head with a load pad actuated by the head load solenoid.

'ENEA~
SOLENOID

RETURN
SPRING

~i::::''''''''''''"-''''[==::=~:::J'''''-- BAI L
LOAD
SPRING

DISK

HEAD POSITIONING
LEAD SCREW

READ/WRITE HEAD

FIGURE 5-4.A-5 Head Load and Carriage Assembly

DISKETTE
The recording media used in the SA900 Diskette Storage Drive is a Mylar* disk enclosed in a plastic
envelope. The characteristics of the disk and envelope are:
Disk Diameter
Envelope Size
Rotational Speed
Rotational Period
Average Latency

7.875 inches
8 inches x 8 inches
360 RPM

Number of Tracks
Bit Density Inside Track

77
3200 bpi approx.

166.67 ms
83.33 ms

The SAlOO Diskette media is IBM compatible and can be used in the SA900 or the IBM 3740 Data
Entry System. (See Figure 5-4.A-6A)
The SAlOl Diskette is used with the SA901 and differs from the SAlOO in that there are 32 sector
holes and a file protect hole. (See Figure 5-4.A-6B)
*Trademark of Dupont Corp.

5-205

Index
Access
Hole

,..-------.....
./'

.............

Read/Write
Head Opening

1.5" Dia.
,---->.,----.,..;,_+_ Registration

S.O"

Opening

I
I
\

Index
Hole

\
\

Opening For
Drive Hub

'" " --t
.........

......-- / '

Track 76

Plastic
Envelope

FIGURE 5·4.A·6A SA100 Diskette and Cartridge Layout

File Protect
Hole

I ndex Sector
Access

(

)

0
0
0

0 00 0 0

FIGURE 5·4.A·6B SA101 Diskette and Cartridge Layout

5-206

0
0
0
0
0

SA900/901
DISKETTE STORAGE DRIVE
ELECTRICAL INTERFACE
The interface of the SA900/90 1 Diskette drive can be divided into two categories: Signal and Power.
The following sections provide the electrical definition for each line.
SIGNAL INTERFACE

The signal interface consists of the lines required to control the SA900/90l Diskette Storage drive
and transfer data to and from the unit. All lines in the signal interface are digital in nature and either provide
signals to the drive (input) or provide signals to the user (output).
Input

There are six (6) input signal lines to the SA900/90l Diskette Storage drive; each line has the
following input specifications.
Yin OV - .4 V = logical zero = true
Yin 2.5V -5.5V = logical one = false

Input Impedance = l50n
DIRECTION SELECT

This interface signal defines the direction of motion of the R/W head when the Step line is pulsed.
An open circuit or logical one level defines the direction as out, and if a pulse is applied to the Step line the R/W
head will move away from the center of the disk. Conversely, if this input is shorted to ground or a logical zero
level is applied the direction of motion is defined as in and if a pulse is applied to the Step line the R!W head will
move towards the center of the disk.
STEP

This interface line is a control signal which causes the R/W head to move with the direction of
motion defined by the Direction Select line. The access motion is initiated on each logical zero to logical one
transition of this signal. The timing restrictions on this signal are shown in Figure 5-4.A-13.

LOAD HEAD
This interface line performs two functions on all machines at or above E. C. level 45 . (The EC level
can be found in the rear upper corner of the PCB.) One function is to remove the 24 volts from the stepper motor
which will allow the motor to run cooler. This means to either step, read or write. The head load line must be a
logical 0 level. This function can be crippled by cutting a trace on the PCB. Then 24 volts will be applied to the
stepper at all times. This trace has been labeled "R" for easy identification.
5-207

DISKETTE DRIVE
HOST SYSTEM

P1
"

STEP

X
"

'-' 01 RECTION SELECT

X
'-'

-..

'-' FILE I NOPE RAB LE R ES~

WRITE PROTECT (SA90n

R12

,.... '-' SECTOR (SA901)

L14

X
,....HEAD LOAD

.....

~ UNSEPARATED READ DATA

U
lJ

U
r\.

WRITE DATA

L19
R19

...

L10
R10

,.... +24 VDC

X +24 VDC RETURN

-...

,.... '-' -5 OR -12 OR -15 VDC --:

Y ,.... +5 VDC
A X LOGIC GROUND
'V ' - '

FRAME GROUND

...

110 VAC

..-

110 VAC

DENOTES FRAME GROUND

L16

L17

SEPARATED CLOCK

L7
R7

R17

L18

R16
SEPARATED DATA

R14

R18

"" WR ITE GATE

X
r\

L21

L12

'-' ,.... TRACK ZERO

•

R21

,.... '-' INDEX

R15

X
'-'

L15

..
..

- -b
--

"FILE INOPERABLE

R2, L2
R3, L3
R20, L20
R 11, L 11
R1, L 1, R22, L22
P4

()

DENOTES SHI ELDED CABLE

DENOTES TWISTED PAl R

FIGURE 5-4.A-7 Standard Interface Lines

5-208

It also is a control signal to an actuator that allows the disk to be moved into contact with the R!W

head. An open circuit or logical one deactivates the head load actuator and causes a bail to lift the pressure pad
from the disk, which removes the load from the disk and R!W head. A logical zero level on this signal activates
the head load actuator and allows the pressure pad to bring the disk into contact with the R!W head with the
proper contact pressure.

FILE INOPERABLE RESET
This interface line provides a direct reset on the File Inoperable latch. The inactive level for this
signal is a logical one. The File Inoperable condition is reset with a logical zero level applied to this line. Note:
Under no circumstances should the drive be operated with this signal at a constant logical zero level since all
data safety circuitry will be defeated.

WRITE GATE
Write Gate is an interface line which controls the writing of data on the disk. A logical one level on
this interface line turns off the current source to the write drivers along with the current sinks for the write
current. A logical zero level on this line enables the write current source and current sinks, and disables the
stepping circuitry.

WRITE DATA
This interface line provides the data to be written on the disk and each transition from the logical one
level to logical zero level causes the current through the R!W head to be reversed. Input impedance for Write
Data = lOOn.
Output
There are six (6) output signal lines from the SA900 Disk Storage drive, and eight (8) from the
SA90l. Each line has the following output specifications:

Vout = OV - .4 V logical zero = true
Each output line appears as an open circuit (transistor in cut-oft) for the logical one level. (False)
Maximum sink current

100 rna.

TRACK 00
The Track 00 interface signal indicates when the R!W head is positioned at track zero (the outer most
data track) and the access circuitry is driving current through phase one of the stepping motor. This signal is at a
logical one level when the R!W head is not at track zero and is at a logical zero level when the R!W head is at
track zero.

FILE INOPERABLE
File Inoperable is the output of the data safety circuitry and is at a logical zero level when a condition

5-209

which jeopardizes data integrity has occured. Logically the signal is defined as follows:
File Inoperable

= (Write Gate. Write I Sense)
+ (Write Gate . Write I Sense)
+ (Write Gate . Head Load)
+ (Write Gate . Write Data)
+ (Write Gate . Door Closed)

INDEX
This interface signal is provided by the disk drive once each revolution (166.67 ms) to indicate the
beginning of the track. Normally, this signal is a logical one level and makes the transition to the logical zero
level for a period of 1.7 ms (.4 ms SA091) once each revolution. The timing of this signal is shown in Figure
5-4.A-8.

.---n. ._________________. . . .n. .__________

Index _ _ _

It..-

1.7ms
.4ms

± .2ms
± .2ms

(900)
(901)

166.7 ms

FIGURE 5-4.A-8 Index Timing

SECTOR (SA901 ONLY)
This interface signal is provided by the disk drive 32 times each revolution. Normally, this signal is a
logical one level and makes the transition to the logical zero level for a period of .4 ms 32 times each revolution.
The timing of this signal is shown in Figure 5-4.A-9.

Sector

__-n. .--n. .

-----n~-.---n

--J-f,

Jt-,----n---n. .---

5.21 ms Nominal

Index

~,-----~r-l. .--__

-------------+--......
2.605ms
Nominal

~
166.7ms

FIGURE 5-4.A-9 Index/Sector Timing

WRITE PROTECT (SA901 ONLY)
This interface signal is provided by the disk drive to allow the user an indication when a write
protected diskette is inserted in the SA901. The signal is a logical one level when the diskette is not protected
and a logical zero when it is protected.
5-210

SEPARATED DATA
Separated Data is the interface line over which read data is sent to the using system. The frequency
modulated signal written on the disk is demodulated by the drive electronics and the data pulses are sent to the
using system over this interface line. Normally, this signal is a logical one level and each data bit recorded on
the disc causes a transition to the logical zero level for 200 ns. The timing for this signal is shown in Figure
5-4.A-15.

SEPARATED CLOCK
The Separated Clock interface line provides the using system the clock bits recorded on the disk in
frequency modulation recording. The levels and timing are identical to the Separated Data line except that a
separated clock pulse occurs each 4 fJ-s.

UNSEPARATED READ DATA
The Unseparated Read Data interface line provides raw data (clock and data bits together) to the
using system that requires it. The levels and timing for this signal are shown in Figure 5-4. A-15.

POWER INTERFACE
The SA900/901 Diskette Storage Drive requires both AC and DC power for operation; the AC
power is used for the drive motor while the DC power is used for the electronics and stepping motor. The power
requirements are defined in the following sections.

AC Power
110 ± 10% VAC @ .75A
50/60 ± .5 Hz single phase

DC Power
+5 ± 0.25 VDC @ 1.5A max. 50 mV ripple
- 5 ± 0.25 VCD @ .20A max. 50 mV ripple
+24 ± 1.20 VCD @ 2.0A max.
100 mV ripple
DC POWER OPTIONS (- 5 VDC Replacement)
-12 ± .6 VDC @ .20A max. 50 mV ripple
(cut trace "L")
-15 ± .75 VDC @ .20A max. 50 mV ripple
(cut trace "L" and "M")

INTERFACE CIRCUITRY
Shugart Associates provides interface circuitry to connect the SA900/901 with the host system via
lines with 150 ohms characteristic impedance. The drivers and receivers are divided into two categories -

5-211

those lines carrying data and those lines carrying control information.
The following two sections describe the circuitry recommended for interfacing the SA900/901 with
the host system.
Figure 5-4.A-10 shows the interface circuitry for the Read Data, Separated Data, Separated Clock,
and Write Data interface lines.

+5V
+5V
Zo = 100n

I
510n

510n

Max. 20 Feet
Data Interface Circu itry

FIGURE 5-4.A-10 Data Line Driver/Receiver Combination

Data Line Driver
The line drivers for these interface signals must be capable of sinking 110 rna in the logical true state
with the maximum voltage in this state no greater than .3 volts with respect to logic ground. When the line
driver is in the logical false state, the driver transistor is in cutoff and the voltage at the output of the driver
should be no less than 3.0v with respect to logic ground.

Control Line Driver
The line driver for these signals consist of an open collector 2N2222A transistor. The driver must be
able to sink a maximum of 37 rna. in the logical true state with a maximum voltage of .3 volts with respect to
logic ground. When the line driver is in the logical false state the driver transistor is in cutoff and the collector
cutoff current should be no greater than 10 nanoamperes.

Data Line Receiver
The line receiver for the four interface lines is basically a Schmitt trigger with the switching
threshold at 1.7 volts to enhance the noise immunity on these signal lines . The signal line is terminated in lOOn
(±5%) for use with 93 to lOOn coaxial cable.
Figure 5-4.A-11 shows the interface circuitry for the control lines between the SA900/901 and the
host system.

5-212

Typical Recommended Line Driver-Receiver Combination

+5V

150n

7405

Cable Max. 20 Ft.

FIGURE 5-4.A-11 Control Signal Driver/Receiver Combination

Control Line Receiver
The line receiver consists of a standard 7400 family TTL gate with a termination resistor of 1500
(± 5%) to + 5 volts. The input characteristics for this receiver are:
Maximum logical state voltage = .8 v.
Minimum logical false state voltage = 2.0 v.
Note: These are measured at the input to the receiver.
For a detailed discussion of IBM 3740 compatibility, the system designer should read Shugart
Associates Guide to IBM 3740 Compatibility (Publication number SA 0001-2).
TRACK ACCESSING
Seeking the R!W head from one track to another is accomplished by selecting the desired direction
utilizing the Direction Select interface line and then pulsing the Step line. Multiple track accessing is
accomplished by repeated pulsing of the Step line until the desired track has been reached. Each pulse on the
Step line will cause the R/W head to move on track either in or out depending on the Direction Select line.
The head load line must be active (logical 0 level) in order to activate the stepper. When not
Accessing, Reading or Writing it is not necessary to have power to the stepper; therefore, the head load line
controls the 24 volts to the stepper motor which allows it to remain cooler. This function can be crippled by
cutting a trace which has been provided on the PCB. This trace has been labeled' 'R" for easy identification.
Figure 5-4.A-12 shows an SA901 recording format using sector recording.
Step Out
With the Direction Select line at a plus logic level (2.5V to 5.5V) a pulse on the Step line will cause
the R!W head to move one track away from the center of the disk. The pulse(s) applied to the Step line and the
Direction Select line must have the timing characteristics shown in Figure 5-4.A-13.
5-213

Sector

400}J.s
±200}J.s

I. -

1----1

~-------------------------------------------------------------

Clock

tr--

Data Identifier 8 Bits

104 Bits
(Min.)
128 Bits
1056 Bits Max.
_ Variable _
~ .515ms ....I..~
...- - - - 4.256ms ----------I~.lfoooII-~-F-i-II---i-.1

5.21ms Nominal

FIGURE 5-4.A-12 Sector Recording Format (SA 901 only)

( r
r-------------------------------4) J~--------------------------------------DC Power

~----------------_f(
) .J~(-------------------------------Load Head ------___________-'
~10}J.sMin

Direction
Select -------------------------,--.
I~

________________

-~t1}J.sMin

r
J

100ms ____
Min

1}J.s Min

~r_________~_~-----,Il~

Step - - - - - - - - - - - - - - - - - - - - - - - -.....
10}J.sMin.

J
~

------i~
. .1

~ 10ms Min

FIGURE 5-4.A-13 Track Access Timing

5-214

___

Step In
With the Direction Select line at a minus logic level (OV to .4 V), a pulse on the Step line will cause
the R/W head to move one track closer to the center of the disk. The pulse(s) applied to the Step line must have
the timing characteristics shown in Figure 5-4.A-13.
These timing specifications are required in order to guarantee that the R/W head position has
stabilized prior to reading.
READ OPERATION
Reading data from the SA900/901 Diskette Storage drive is accomplished by activating the interface
line, "Load Head" and "Write Gate" is not active. The timing relationships required to initiate a read
sequence are shown in Figure 5-4.A-14.
Once reading has commenced, the two interface lines, Separated Data and Separated Clock provide
the read data. The timing of the read signals, Separated Data, and Separated Clock are shown in Figure
5-4.A-15.
WRITE OPERATION
In order to write data on the SA900/901 Diskette Storage drive, certain timing relationships must be
assured. These timing requirements are required to:

r-______________________________________________

~r----------

)

DC Power - - - -

~--------------------------------------~J

J~---------

Load Head - - - - - - - - - -...

step ________________

~r__l~______________________________~r ~r----------J

10ms Min . . .

50ms Min

100ms Min

FIGURE 5-4.A-14 Read Initiate Timing

5-215

n. _____.n. _____. n
. . _____. n
. . ______
Data

Clock

Data

Read Data _ _ _ _

n. _____________n. .______

Separated Data _ _ _ _ _ _ _ _ _ _ _ _

. . . . - 200 ns ± 50 ns

n . ._____________n. _____________

Separated Clock _ _ _.......

2.00J-Ls - - - - .

± 200 ns

4-----

1..

4.00J-Ls ± 400 ns - - - -...
~I

FIGURE 5-4.A-15 Read Signal Timing

(1 ) Avoid destroying data due to a hardware failure or the position of the R/W head has not
stabilized.
These timing requirements are defined inFigure 5-4.A-16.
In order to ensure that a hardware failure or operator interference does not cause the unintentional
loss of data, data safety circuitry is provided. If the data safety circuitry detects an undesirable condition within
the drive a latch is set, writing is inhibited, and the signal File Inoperable is sent to the user. File Inoperable is
defined by:
File Inoperable

= (Write Gate. Write I Sense)
+ (Write Gate. Write I Sense)
+ (Write Gate. Head Load)
+ (Write Gate . Write Data)
+ (Write Gate . Door Closed)

POWER SEQUENCING
Applying AC and DC power to the SA900/901 can be done in any sequence, however, once AC
power has been applied, a 4 second delay must be introduced before any Read or Write operation is attempted.
This delay is for stabilization of the Diskette rotational speed. Also, initial position of the R/W head with
respect to data tracks is indeterminant immediately after application of DC power. In order to assure proper
positioning of the R!W head prior to any read/write operation, a Step Out operation should be performed until
the Track 00 indicator becomes active.
The Load Head signal can be applied any time after DC power has been applied, however, the signal
must be true for a minimum of 50 ms prior to a read or write operation.
5-216

)
------------------------------------------~r

I'
.J

DC Power _ _ __

I'
.J
Head Load

--------~----------~
. . 100ms Min ~

Step

Write Data

Write Gate

------+-----....;:...-___________

r-----fl' ,(

J~r-

I-~

"T1

:xJ

til

N
>-'
.......:J

J:.

1,O~s Min

---.1

;

2,OO~s

± ,5%

;:;:

!.
CD

-I

10msMin

50ms Min

100ms Min·

*4 seconds if AC and DC power are applied at same time,

..,

r---

4,OO~s ~

± ,5%

1....-

200ns ± 50ns

- -.....

SAFETY CIRCUITS
• Safety Circuits check for component failures, using system operational errors, and operator
errors.
The safety circuit, File Inop, in the SA900/901 is designed to check for the following:
(1) Write gate with no write current sense.

(2) No write gate with write current sense.
(3) Write gate without the head loaded.
(4) Write gate with no write data.
(5) Write gate with the door opened.
Figure 5-4.A-17 shows the functional diagram of the File Inop circuit. It is the responsibility of the
using system to test the -File Inop interface line. Upon detection of -File Inop, the using system should activate
-File Inop Reset and retry the operation.
When -File Inop becomes active, the SA900/901 will inhibit any further write operations until the
fault is corrected, and File Inop Reset or Power on reset is presented.

-Power on Reset

.....

I"""

-File Inop Reset
~

-Wrt Data Sense

-Write Gate

~
V-

-HD Load & DR Clsd

'"'-

---

I"""

L-o

.....

~
r-

----

J"'I

....
'"

roo--

-0

I-

.....

--Wrt Crnt Sense

V-

I"""

FIGURE 5·4.A·17 File Inop Circuit

5·218

:/'-

-Filelnop

APPENDIX 5-4.B
ORBIS MODEL 74 DISKETTE DRIVE
(Courtesy Orbis Systems, Inc.)
ORBIS MODEL 74 DISKETTE DRIVE
5-4.B.l

EQUIPMENT SPECIFICATIONS

The equipment specifications for the Model 74 Diskette Drive are as follows:
5-4.B.l.l ACCESSING TIME
Average Latency
Access Time
Head Load Time

83 mS
6 mS track to track; 14 mS Settle
16 mS/14mS Settle

5-4.B.1.2 RECORDING
Mode
Density (nominal)

Double Frequency (Standard)
1836 bpi (outer track)
3268 bpi (inner track)

Data Transfer Rate
Sectors (soft)
Sectors (hard)

250,000 Hz nominal
IBM 3740 or equivalent
Up to 32

5-4.B.1.3 DATA CAPACITY (Unformatted)
Bits/Track
Bytes/Track
Bits/Byte
Tracks/Disk
Bits/Disk

41,664
5,208
8
77
3,208,128

5-4.B.1.4 DISKETTE (IBM Compatible)
Disks/Cartridge
Useable Recording Surfaces/
Disk Cartridge
Disk Surface Diameter
Recording Diameters
Disk Surface Coating
Disk Rotational Speed

1 (8 x 8 inches including envelope)
1 or 2
7.88 inches
Track 76 (inner) 2.0290 inches nominal;
Track 00 (outer) 3.6123 inches nominal
Magnetic Oxide
360 ± 9 rpm

5-219

5-4.B.l.5 READ/WRITEIERASE HEAD
Head/Unit
Track Width
Track Spacing
Erase to Read/Write Gap

1
.014 inch
0.02083 inch (48 tracks per inch)
.033 ± 0.003 inch

5-4.B .1.6 PHYSICAL (Approx.)
Height

4.53 inches

Width

9.01 inches

Depth
Weight

14.12 inches
15 lbs.

5-4.B.1.7 ELECTRICAL
Power Supply (Supplied by User)
dc

+24 volts (± 5%) @ 1.5A
+5 volts (± 5%) @ 0.75A
-12 volts (± 5%) @ 0.10A (Early Machines Only)

100 Vac ± 10% 50/60 Hz ± 0.5 Hz
115 Vac ± 10% 60 Hz ± 0.5 Hz
208/230 Vac ± 10% 60 Hz ± 0.5 Hz
240 Vac ± 10% 50 Hz ± 0.5 Hz

5.4.B.1.8 DATA INTEGRITY
Soft Error Rate> 1 in 10 10 Bits
Hard Error Rate < 1 in 10 12 Bits

5-220

THEORY OF OPERATION
5-4.B.2

GENERAL
The Model 74 consists of control and read/write electronics, diskette drive motor, read/write head,

track access mechanism, and removable diskette cartridge. The basic functions of the Model 74 are:
Receive and generate control signals
Access the appropriate track
Write or read data on command
The functions of the Model 74 and the required interface signals to and from the using system are
shown in Figure 5-4. B-1. The Read, Write, File Unsafe and Control Logic are the interface electronics between
the host system and the drive. The stepping motor positions the read/write head to the desired track on the
diskette. The head load solenoid loads the disk against the read/write head and data may then be recorded on or
read from the diskette. Each of the logic blocks and signal names shown are later discussed under Logic and
R/W Functional Descriptions.
The electronic circuitry is packaged on one Printed Wiring Board (PWB).
The PWB contains:
(1) Index Transducer Circuit
(2) Track Position Stepping Motor Circuits
(3) Head Load Circuit
(4) Read/Write Circuits
(5) File Unsafe Sensing Circuits
(6) Drive Selection Circuits
The stepping motor and lead screw positions the read/write head. The stepping motor rotates the lead
screw clockwise or counterclockwise in 15° increments. A 15° rotation of the moves the read/write head one
track position. The host system steps the stepping motor to the desired track. Track verification is accomplished
by checking track and/or sector address.
The diskette drive motor rotates the spindle at 360 rpm through a belt-drive system. 50 or 60 Hz
power is accommodated by means of a pulley change. A registration cone, centered on the face of the spindle,
positions the diskette. A clamp (that closes with mechanical door linkage) fixes the diskette to the registration
cone.
The read/write head is in contact with the diskette when loaded. The head surface has been designed
to obtain maximum signal transfer to and from the magnetic surface of the disk with minimum head/diskette
wear. The tunnel erase DC erases the inter-track area to improve off track signal-to-noise ratio and permit
diskette interchangeability from unit to unit.
The read/write head is mounted on a carriage that is moved by the stepper motor drive shaft. Head
load is achieved when the diskette is loaded against the rigidly mounted head by moving a load pad against the
diskette with the solenoid actuated bail. Head to diskette compliance is achieved by restraining the diskette
between the head and the load pad.

5-221

Read Data
Read
Logic

Read Head

File Unsafe
Reset
Light
Source

File Unsafe
Write
and
Safety
Logic

Write Data

Write Head

Write Gate

Erase Gate

Power
On/Off
Reset

Head
Loaded

Track 00
Sensor

Step
Direction
Head

Load Head

Load Actuator

Index

Track 00
Control
Logic
Low Current

Head
Step Actuator

Ready

(Option)
Diskette
Spindle Motor

Track 00
Index Pulses
Light Source Detector

FIGURE 5-4.B-1 Model 74 Functional Block Diagram

5-222

FUNCTION

DISKETTE DRIVE

CONNECTOR Jl

CONNECTOR Jl
DRIVE AD DR A
RETURN
KEY
KEY
-READ DATA
RETURN
-READY
RETURN
-SECTOR*
RETURN
-INDEX
RETURN
-WRITE DATA
RETURN
-ERASE GATE (Early Machines Only)
RETURN
-WRITE GATE
RETURN
-FILE UNSAFE
RETURN
-FILE PROTECT*
RETURN
-TRACK 00
RETURN
-UNSAFE RESET

DISKETTE DRIVE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

RETURN
-LOW CURRENT
RETURN
-STEP
RETURN
-IN (DIRECTION)
RETURN
-LOAD HEAD
RETURN
-SEP CLOCK*
RETURN
-SEP DATA*
RETURN
DRIVE AD DR B
RETURN

+5 VOLTS
+5 VOLTS
-12 VOLTS(Early Machines Only)

o VOLTS
+24
+24
+24
+24
+24
+24

VOLT RETURN
VOLT RETURN
VOLT RETURN
VOLTS
VOLTS
VOLTS

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

*Option Signals

TABLE 5.4-B-3 Interface Pin Assignments

5-4.B.2

INTERFACE DESCRIPTION
The interface of the 74 is divided into two categories: Signal/Data Interface and Power Interface.

The initial Power up and Read/Write Sequence are shown in Figures 5-4.B-3 and 5-4.B-4.

5-4.B.4

SIGNAL AND DATA INTERFACE

5-4.B.4.1 INPUT LINES
There are nine low active TTL input lines to the 74: Direction, Step, Load Head, File Unsafe Reset,

5-223

Power (AC)

-1 r- O~"O

Power (DC)

f.-

2 Sec

Step

U-----'$ S

6ms Min
Track 00

5m,

--------------------------~ff~---

Direction

FIGURE 5-4.B-3 Power Up Sequence

Head Load

Step

'-----------------1((....- - - -

ul
I

6msMin

U-----~)f'-- -

30ms Min

Read Stable

50ms Min

30msMin

Write Gate

Write Data
0.45

Index

± 0.20 ms'"

---1r-

---------------~LJ-------~)

166.7ms

"'Some drives may be 2.2 ± 0.3 ms

FIGURE 5-4.B-4 ReadlWrite Sequence

5-224

Write Gate, Write Data, Drive Addr A, Drive Addr B, and Low Current. Each line has the following
characteristics (refer to Figure 5-4.B-5):
Logic 1
Logic 0
Input Impedance

-Active - OV to O.4V
-Inactive - +2.5V to +5.5V
-220 ohms to +5V and 330 ohms to GND.

(1) Direction (-In)
This interface signal defines the direction of motion of the R/W head when the Step line is
pulsed. A low active level on this line causes the Head Position Mechanism to move the
read/write head towards the center of the disk when the Step line is pulsed. With the Direction
line at an inactive level, a pulse on the Step line causes the Head Position Mechanism to move
the read/write head away from the center of the disk. The state of Direction must not change
until 200 nS after the leading edge of the Step pulse.
(2) Step
A low active level (10 J,LS min) on this line will cause the read/write head to be moved one track.
The direction of movement is controlled by the Direction line. The state of Direction line is
sampled 100 ± 30 nsec after the leading edge of step. Access timing relationships conform to
Figure 5-4.B-3.
(3) Load Head
A low active level on this line causes the storage element to be placed in close proximity to the
read/write head for data recording or retrieval. Load Head may be activated at any time after
power has been applied; however, this line must be activated at least 50 mS prior to a read or
write operation. During periods of no data transfer this line should be deactivated to provide for
maximum storage element and head life.
(4) File Unsafe Reset
A low active level (200 nS minimum) on this line resets the File Unsafe Latch, providing the
capability of a write retry operation without the need for operator intervention.
(5) Write Gate
A low active level on this line enables the write current source, and disables the stepping
circuitry (see Section 4.5.2 for further clarification).
(6) Write Data
This interface line provides the data to be written on the disk. Each transition to a low active
level on this line causes write current through the write coils to be reversed. A 200nS wide pulse
is required for each flux reversal to be written.
(7) Erase Gate

The Erase Gate input controls the DC Current through the erase element to provide tunnel erase while writing
on the disk. A low active level on this line turns on constant current to the erase head. (Refer to Figure 5-4.B-6
for timing considerations.)

5-225

+5V

4700 ohms

220 ohms

7438

330 ohms
Diskette
Drive
Output

Recommended
Host System
Receiver

-------4f

+5V

220 ohms

4700 ohms

7438

330 ohms
Diskette
Drive
Receiver

Recommended
Host System
Driver

FIGURE 5·4.8·5 Interface Driver and Receiver

5-226

(8) Low Current
A low active level on this line is recommended for writing on tracks 44 through 76. This input is
used to lower the write current which consequently improves the read output resolution of the
inner tracks.
(9) Drive Addr A & B

The interface lines may be used to define one of 4 drives to be selected in the following manner:
Drive

Address

B
0

A
0

Drive 0

Inactive

Drive 1 1 = Active
Drive 2

Drive 3

5-4.B.4.2 OUTPUT LINES
There are five output lines from the 74: Index, Track 00, File Unsafe, Read Data, and Ready. Each
line has the following characteristics (refer to Figure 5-4.B-5):
Active

o to O.4V

Inactive

4700 ohms to +5V
47 rnA

Maximum Sink
(1) Index

This interface signal is provided by the disk drive once each revolution (166.7 mS) to indicate
the beginning of the track. This signal makes a transition to a low active level for a period of 0.45
± 0.20 mS* (Refer to Figure 5-4.B-4).
(2) Track 00
A low active level on this line indicates that the read/write head is positioned at track 00. The
signal is valid 10 mS after the last Step command.
(3) File Unsafe
A low active level on this line indicates that a condition which may jeopardize data integrity has
occurred. File Unsafe may be reset by activating the File Unsafe Reset line. (See WRITE
MODE for list of File Unsafe conditions.)
(4) Read Data
Data is output to the host system in the same form as write data from the host system. Each flux
reversal sensed on the storage element will result in a transition to a low active level for a 200 nS
period on this line.
(5) Ready
A low active level on this line indicates that a diskette is loaded and rotating in the drive and that
the front door is closed.
*Some drives may be 2.2 ± 0.3 mS.

5-227

APPENDIX 5-4.C
CAL COMP 140 DISKETTE DRIVE
(Courtesy Cal Comp Corporation)

Century Data
A DIVISION OF

5-4.C.1

DESCRIPTION

The Century Data Model 140 Floppy Disk Drive is a high speed, random access, disk storage unit
which utilizes a flexible disk cartridge as the storage unit which utilizes a flexible disk cartridge as the storage
medium. Up to 3.20 million bits of data may be stored on the single recording surface of the flexible disk. When
utilizing the IBM 3740 data format, 1.94 million bits of data may be recorded. The Model 140 Floppy Disk
Drive features 48 tracks-per-inch and 3200 bits-per-inch technologies to provide media interchangeability with
the IBM 3740 series of data recording equipment.
The Model 140 contains features and options whereby a systems designer may incorporate the
Model 140 into his data storage system with a minimum of effort. Among these are a positive pressurized media
chamber, precise media registration, write protect capability, sector outputs, and a choice of data outputs.
Figure 5-4. C-1 shows the size and composition of the floppy disk cartridge.

I~.t---------8"-------+---~
/--

Sealed
Protective _ _ _ _
Jacket

Liner

.......

Spindle/Hub

,'------------------~MeLd~inaa:::t
=-Cds 140 Cartridge

.06"~~~~~$~~~~~$~~

Side View

FIGURE 5-4.C-1 Floppy Disk Cartridge

5-228

The disk drive comprises a read/write head positioning system, data decoder, and I/O gated control
and status circuits. Drive voltage is obtained from the host system, as well as, +24 and +5 vdc voltage
requirements.
I/O interface signals are routed between the controller and disk drive(s) in a radial or daisy-chain
fashion via standard paddle board connectors.
In multiple disk drive applications, each drive is individually selectable. Availability status of a disk
drive for on-line operations bypasses the addressing circuits; thereby, permitting ready status to be monitored
on a status interrupt basis.
5-4.C.2

PHYSICAL AND ELECTRICAL CHARACTERISTICS

Tables 5-4.C-2, 5-4.C-3 and 5-4.C-4 provide the physical and electrical characteristics and Table
5-4.C-5 gives the pertinent specifications.

Height
Width
Depth
Weight

8.40 inches
4.90 inches
15.75 inches including connector
18 pounds

TABLE 5-4.C-2 Physical Characteristics

AC Power

50Hz+0.5Hz 100vac ±10%, single phase
208 vac ± 10%, single phase
220vac ±10%, single phase
240 vac ± 10%, single phase
60Hz+0.5Hz 100 vac
115 vac
208 vac
230 vac

DC Power

± 10%, single phase
± 10%, single phase
± 10%, single phase
± 10%, single phase

+5 vdc ±2% at 1.5 amperes
+24 vdc ±5% at 1.0 amperes

TABLE 5-4.C-3 Power Requirements

Temperature
Relative Humidity
Heat Dissipation

60°F to 100°F with maximum gradient of 20°F/hour
20% to 80%, 78°F maximum wet bulb
540 BTU/hour

TABLE 5-4.C-4 Operating Environment

5-229

Storage Capacity
Unformatted
Per Disk
Per Track
Formatted (IBM 3740)
Per Disk
Per Track
Sector

3,208,128 Bits
41,664 Bits
1,943,552 Bits
1,943,552 Bits
26,624 Bits
1,024 Bits

Number of Tracks

Recommended Coding Technique

Double Frequency (PM)

Bit Transfer Rate

250,000 bits/sec, nominal

Positioning Mechanism

Stepper Motor, electrical detent

Head Stabilization Time

10 milliseconds

Head Load Time

16 milliseconds

Rotational Speed
Motor Start Time (To Ready)

360 RPM ± 2.5% (167 millisecond/revolution)
2 seconds maximum
TABLE 5-4.C-5 Specifications

5-230

6-5.C.3

INPUT/OUTPUT SIGNALS
A list of input and output signals, and characteristics, is provided in Tables S-4.C-S and S-4.C-6,

respectively.

Signal Name

Definition

SELECT/

A unique signal used to enable communication between a disk drive and its
controller. This line must be low (OV) to be active.

WRITE ENABLE/

Enable recording of data on the flexible disk. This line must be low (OV) to be
active. When this line is high (+ SV), reading from the flexible disk is enabled.

WRITE DATA/

This line carries low active (OV) pulses representing data to be recorded on the
flexible disk. Write current reverses direction on the trailing edge of each pulse.
Pulses must be 0.2 to 1.S microseconds wide with a maximum repetition rate of
2.0 microseconds.

ABOVE TRACK 43/ This line is used to control write current amplitude, guaranteeing IBM 3740
media interchangeability. This line must be high (+SV) when recording on
tracks 0 through 43, and low (OV) when recording on tracks 44 through 76.
ABOVE TRACK 43 must be stabilized 10 microseconds before activating
WRITE ENABLE.
STEP/
This line is used in conjunction with DIRECTION and is used to cause the
read/write head to be moved from track to track. A low pulse (OV) of 2
microseconds to 4 milliseconds causes the head to move one track in the
direction specified by the DIRECTION line. Maximum step rate is 167 steps per
second (6 milliseconds per step).
DIRECTION
This line is used in conjunction with STEP to cause the read/write head to be
moved from track to track. When this line is high (+ SV), direction is IN (higher
numbered tracks). When this line is low (OV), direction is OUT (lower numbered tracks). This line must be stable 100 nanoseconds minimum before
activating STEP and remain in the appropriate state for the duration of the step
period.
HEAD LOAD/
This line is used to move the flexible disk against the read/write head for data
recording or retrieval. This line must be low (OV) to be active. A 16 millisecond
delay is required after activating this line prior to commencing data transfers to
allow for media loading.
PLO SYNC/
A low level (OV) pulse 12 microseconds wide will cause the PLO data separator
to sync to preamble O's for data tracking.

TABLE 5-4.C-6 140 Disk Drive Output Signals

5-231

Signal Name

Definition

READ DATA

This line transmits read data to the controller. Exact line definition and timing
characteristics depend on the data separator present within the drive. When no
data separator is present within the drive, this line has no function.
With Standard
This line is a NRZ data line with the one-shot separator. The level of the line
One-Shot Separator represents data. A one bit is represented by a low (OV) level, and a zero bit is
represented by a high ( +5 V) level. The READ CLOCK line is used to clock data
into the controller.
Read DATA
This line outputs data pulses with the PLO separator. A one bit is represented
(Continued)
by an 800 nanosecond low (OV) level pulse. A zero bit is represented by the
With Optional PLO absence of a pulse. The READ CLOCK line is used to clock data into the
Data Separator
controller.
READ CLOCK/
Exact meaning and timing characteristics of this line depend on the data
separator used within the drive.
With No
When no data separator is used within the drive, this line outputs unseparated
Data Separator
data (clocks and data). This output is provided for the systems designer who
desires to use his own encoding scheme or provide data separation in the
controller. This output may be used to enable detection of IBM 3720-type
address marks by the controller. A modified one-shot decoder with a missing
pulse detector will allow detection of 3740 address marks. Each flux reversal
read from the disk is output as a 300 ± 100 nanosecond wide low (OV) pulse.
With One-Shot
This line will output 300 ± 100 nanosecond wide low (OV) pulses representing
Separator
separated clocks. The trailing edge of these pulses are used to strobe the READ
DATA line into the controller.
With PLO SeparatOl This line will output 800 nonosecond wide low (OV) pulses representing separated clocks. These pulses occur simultaneously with pulses occurring on the
READ DATA line.
INDEX/
The leading edge of a 450 microsecond wide low (OV) pulse on this line
represents the beginning of track. This pulse occurs once per revolution of the
flexible disk.
TRACK 00/
When this line is low (OV), the read/write head is positioned over track 00. This
line is intended as a head position reference. When this line is active, the stepper
motor drive circuits are inhibited from further outward movement.
READY
A low level (OV) on this line indicates that the flexible disk is up to speed. This
line is not gated by SELECT and is thus a unique line. This line serves as an
interrupt to the controller and is particularly useful during flexible disk changes.
SECTOR/
Low level (OV) pulses on this line represent sector marks. Sector pulses are 1
millisecond wide.
WRITE
A low level (OV) on this line indicates that a write enable tab is not present on the
PROTECTED/
flexible disk in the drive, thus no writing may take place.
TABLE 5-4.C-6 140 Disk Drive Output Signals

5-232

5-4.C.4

INTERFACE REQUIREMENTS

Table 5-4. C-7 gives the interface logic levels and the I/O cable specifications.
Characteristics

Specifications

Logic Levels
High
Low
Signal Cable
Length
Type
Conductor Size
Twists per foot

+5.5V to +2.2V
+0.4 V to O.OV
20 feet maximum
Twisted pairs (40 pair)
No. 24 or No. 26 AWG
30
TABLE 5-4.C-7

5-4.C.5

FUNCTIONAL DESCRIPTION

The disk drive is a mass memory device featuring a floppy disk and contact recording. The 250 kHz
transfer rate provides a high speed interchange of data between the disk drive and a host controller. The disk
drive(s) may be connected in a radial or daisy-chained configuration with individual selection and status
monitoring.
The disk drive requires operator intervention in loading and unloading the floppy disk, after which
the controller remotely operates the unit. Low-voltage, control signals, drive motor power, and write data are
supplied by the controller, while the disk drive responds with operating status and read data.
The disk drive (Figure 5-4.C-8) comprises the following functional circuits and mechanisms:
• Drive mechanism

• Power-on/ready logic

• Head load mechanism

• Read/Write head positioning logic

• Positioning mechanism

• Read/write logic

• Head load mechanism

Drive Mechanism

The drive system provides rotational disk movement using a single-phase motor selected to match
primary power of the controller system (see Figure 5-4.C-9). Various drive motors are available that
accommodate primary power ranging between 100 and 240 vac at 50 or 60 Hz. The disk diive attains ready
status within two seconds of primary power application.
The drive motor also provides positive pressurization by an impeller (squirrel cage) fan mechanically connected to one end of the rotor shaft.
Rotation of the disk is provided by a belt and pulley connected to the other side of the motor. The
drive pulley and drive belt are selected for either 50 or 60Hz input power. Floppy disk rotational speed is 360
rpm. The disk is engaged with the drive by the spindle mechanism centering cone.

5-233

THE CDS 140
r-----------

--1
Solenoid Drive
Head Load
Actuator

/'"

Centering Cone

Disk

<''-

/
/

I ./
./

Head Read/Write
Assef!lblY
Carnage

./ Lead Screw

i
!

N
w

+::0

Host
System

I
I
I
I

Read, Write,
Positioning
and
Ready Logic

I
I
I

Head Position Actuator

Disk
Drive
Motor

Cooling Fan

I~~·
I

View Showing Helix Drive

_.J
FIGURE 5-4.C-8 The CDS 140

Century I)ata
8G.8$~G

Impeller-----j~

~--

Spindle Drive
Pulley

........., . . . - - - - - Drive Belt

FIGURE 5-4.C-9 Drive Mechanism

5-4.C.5.1 Spindle Mechanism
The spindle mechanism consists of a centering-cone and a load plate. In the unload position, the load
plate is pivoted upwards creating an aperture through which the floppy disk is inserted. In this position, the
centering-cone disengages the disk from the drive mechanism.
To load a disk, the operator inserts the floppy disk then presses down on the load handle which
latches the load plate in the operating mode. The centering-cone is mechanically linked to the load plate and is
activated at the same time (see Figure 5-4.C-IO).
The centering cone is an open splined device that performs two functions: (1) engages disk media
and drive mechanism and (2) positions the disk media in the correct track alignment.
As the load plate is pivoted to the load position, the centering-cone enters the floppy disk center. At
approximately 80 mils from full-down position, a centering cone expander is automatically activated. This
device then expands the centering -cone which grips the inner diameter of the disk media in the correct track
alignment.
Track 00 (home) position serves as the disk drive reference track. This position is sensed by a
photo-transducer which generates track 00 status. This status is sent to the controller for initial track
positioning. All track addressing is relative. The controller generates step pulses to position the carriage from
the current track to a new track.
5-4.C.5.2 Positioning Mechanism
The positioning mechanism comprises a carriage assembly and a bi-directional stepper motor (see
Figure 5-4.C-ll). The stepper motor rotational movements are converted to linear motion by the rotor helix
drive.
The read/write head mount rides in the grooved helix shaft and is held in horizontal alignmep.t by the
way. When the stepper motor is pulsed, the helix drive rotates clockwise or counterclockwise moving the
mount in or out.
The stepper motor includes four pair of quadrature windings. In detent, current flows in one winding
and maintains the rotor in electro-magnetic detent. For positioning one or more step pulses are sequentially
applied to quadrature windings, causing an imbalance in the electro-magnetic field. The stepper motor,
consequently, revolves through detent positions until the step pulses are halted. The rotor then locks in that

5-235

-1---:

Expander Spring
- , - - - - - Centering Cone

I
Centering Cone
Expander
L - -_ _ _

Centering Cone

Spindle Drive
Hub

Spindle Drive
Pulley

4 C-10 Centering Cone and Drive Hub
FIGURE 5 -.

Track 00
Transducer

Read/Write
Head

Head Load
Arm

Front
Bearing
Mount

Helix Drive
Stri ker Stop

FIGUR E 5 -4 .C-"

.
Mechanism
Positioning

5-236

position. The sequence in which the stepper motor quadrature windings are pulsed dictates rotational direction
and, subsequently, higher or lower track addressing from a relative position.
5-4. C. 5.3 Head Load Mechanism
The head load mechanism is basically a relay driver and a solenoid. When activated by HEAD
LOAD/, the spring-loaded head load pad is released and rests in parallel alignment with the floppy disk surface.
Part of the casting provides the lower alignment dimensional surface while the head load solenoid bar provides
the upper alignment surface.
In the load position the read/write head tang rides between these two alignment surfaces and
maintains the read/write head in contact with the disk surface.
The load pad is located behind the read/write head and holds the floppy disk flat against the lower
alignment block.
To minimize disk surface and read/write head wear, the head load signal is gated with SELECT. In
the deselect or idle mode, head loading is automatically disabled. The head load command requires a 16
millisecond execution time.
5-4.C.5.4 Power-On/Ready Logic
Initially the controller applies ac drive motor power which, in turn, initializes the ready circuit (see
Figure 5-4.C-12). Rotational speed is measured by comparing index repetition rate to a ramp signal. When 60

Index
Pulses
Select

Primary
Power

Differ,
ential
Ampl

4-Bit
Counter

Ready
Status

Read
Read
Decode
Network

Clock
Read
Data

Carriage
Assembly

Write Data

Write Enable
Select
Above Trk 43
Step Pulses
--------~ Direction
Control t--S_te...;.p_ _ _~
Direction
and
_
_ _ _ _ _ _ _.... S equencer

Pulses

Stepper
Motor
Drivers

Select

FIGURE 5-4.C-12 Model 140 Functional Block Diagram

5-237

TrkOO
Status

percent rotational speed is attained, the ramp level is less than index pulse timing. This condition is detected by
a differential amplifier whose output is applied to the parallel load input of a 4-stage counter.
Prior to attaining speed, the 4-stage counter is held in the cleared state and maintains a not ready
status output. Once speed is increased to the operational level, the parallel load signal is inhibited and the
counter is incremented by index. At a 12-count, the decoded output inhibits further index counting and switches
the ready line to a low or disk drive ready status.
Ready status is not gated SELECT, allowing the controller to monitor this condition through a status
interrupt feature. The controller may elect to issue track addressing while waiting ready status. The positioning
system operates independently of the disk drive mechanism.
5-4.C.5.5 Read/Write Head Positioning Circuits
The read/write head positioning logic responds to STEP/pulses and the DIRECTION signal from the
controller. The number of step pulses designates track position. DIRECTION provides the step pulse sequence;
thereby, signifying a clockwise or a counter-clockwise decode.
The rotational decode is applied to Darlington drivers connected to the stepper motor quadrature
windings. The 2-bit decode successively enables one winding at a time, causing the read/write head to traverse
one track position.
Track 00 is optically detected by a photo-diode transducer. This position is attained by the controller
issuing a step-out command followed by approximately 100 stepping pulses. The positioning system responds,
by moving the read/write head to track 00, developing track 00 status, and inhibiting any further outward
movement.
5-4.C.5.6 Read/Write Logic
The read/write logic incorporates a single read/write head to record and retrieve data. Data is
recorded wide by the write circuit, then confined to 0.012-inch track width by the tunnel erase coil (see Figure
5-4.C-13).

I \\\
t

After
Erase

Written Data

FIGURE 5-4.C-13 Tunnel Erase

Each bit (clock or data) produces a flux change that is concentrated on a small area of the recording
surface. Flux pattern polarity is alternated for successive bits through the use of dual write coils, wound
anti-phase fashion. This technique assists data recovery during a read operation.
Flux transitions are detected by the read coils as the head passes over data. The analog output of the
read coils is applied to a differential amplifier for pre-amplification. Data is recovered from the bipolar signal
by a crossover detector whose output is linearily shaped then coupled to a read decode network.

5-238

APPENDIX 5-4.0
RECORDING FORMATS
(COURTESY SHUGART ASSOCIATES)
5-4.D

Recording Format

5-4.d.1

The format of the data recorded on the Diskette is totally a function of the host system. Data is

recorded on the diskette using frequency modulation as the recording mode, i.e. , each data bit recorded on the
diskette has an associated clock bit recorded with it. Data written on and read back from the diskette takes the
form as shown in Figure 5-4.D-1. The binary data pattern shown represents a 101.
5-4.d.2

Bit Cell

As shown in Figure 5-4.D-2, the clock bits and data bits (if present) are interleaved. By definition, a
Bit Cell is the period between the leading edge of one clock bit and the leading edge of the next clock bit.

Clock Bits

!----BitCell-----\

Data Bits

FIGURE 5-4.0-1 Data Pattern

5-4.d.3

FIGURE 5-4.0-2 Bit Cell

Byte
A Byte, when referring to serial data (being written onto or read from the disc drive), is defined as

eight (8) consecutive bit cells. The most significant bit cell is defined as bit cell 0 and the least significant bit cell
is defined as bit cell 7. When reference is made to a specific data bit (i.e., data bit 3), it is with respect to the
corresponding bit cell (bit cell 3).
During a write operation, bit cell 0 of each byte is transferred to the disc drive first with bit cell 7
being transferred last. Correspondingly, the most significant byte of data is transferred to the disc first and the
least significant byte is transferred last.
When data is being read back from the drive, bit cell 0 of each byte will be transferred first with bit
cell 7 last. As with reading, the most significant byte will be transferred first from the drive to the user.
Figure 5-4.D-3 illustrates the relationship of the bits within a byte and Figure 5-4.D-4 illustrates the
relationship of the bytes for read and write data.
5-239

Bit Cell 0 of Byte 0 is
First Data to be Sent
to the Drive When
Writing and From the
Drive When Reading

CDC

Bit Cell 7 of Byte 17 is
Last Data to be Sent to
the Drive When Writing
and From the Drive
When Reading

FIGURE 5-4.0-3 Byte

CDC

Bit Cell 0 Bi1 Cell 1 i ;i1 cell; ;i1 cell;

I;It I

CDC

Cell: ;i1 cell; ;i1 cell; Bi1 Cell 7 Bit Cell 0

MSB

LSB

~------------------------Byte------------------------~.~I

Binary Representation of
Data Bits

Clock Bits
Hexadecimal
Representation
of
Data Bits
Clock Bits

FIGURE 5-4.0-4 Data Bytes

5-4.D.4

Tracks

The SA900/90l is capable of recording up to 77 tracks of data. The tracks are numbered 0-76. Each
track is made available to the R/W Head by accessing the head with a stepper motor and carriage assembly.
Track accessing will be covered in Section 5.5.
Basic Track Characteristics:

5-4.D.5

Number of bits/track

41,300 bits

Index Pulse Width
Index/Sector Pulse Width
(SA901 only)

1.7 ± .5 ms
.4 ± .2 ms

Track Format

Tracks may be formatted in numerous ways and are dependent on the using system. The SA900/90l
use index and sector recording formats respectively.
5-4.D.5.l Index Recording Format
In this Format, the using system may record one long record or several smaller records. Each track is
started by a physical index pulse and then each record is preceded by a unique recorded identifier. This type of
recording is called soft sectoring. Figure 5-4.D-5 shows a typical Index Recording Format.

5-240

Nom'""'

46 Bytes

teo."
Data

Record
26

1r
r

Physical Index

Gap 4
Pre Index
320 Bytes

Index Addre

Gap 1
Post
Index
32
Bytes

ID
Record
"'1

ss Mark

Gap 2
ID
Gap

Data Field
Record
#1

Bytes

Gap 3
ID
Data
Record Gap 2
Gap
#2
33 Bytes

Data Field
Record
#2

Gap 3

ID
Record Gap 2
#3

Data Field
Record
#3

J
I

ID
Record
#26

I I
Gap 2

Data Field
Record
#26

Gap 4

ID
Address
Mark

Track
Address

Zeroes

Sector
Address

Zeroes

CRC
Byte 2

Data or
Deleted Data
Address
Mark

128 Bytes of User
Data

I_'B,,~I~_
FIGURE 5-4.0-5 Track Format

Write Turn-Off
For Update of
Previous Data Field

CRC
Byte 1

5-4.D.5.2 Sector Recording Format
In this Format, the using system may record up to 32 sectors (records) per track. Each track is started
by a physical index pulse and each sector is started by a physical sector pulse. This type of recording is called
hard sectoring. Figure 5-4.D-6 shows a typical Sector Recording Format.
5-4.D.6

Typical Track Index Format
Figure 5-4.D-7 shows a track Format, which is IBM compatible, using Index Recording Format

with soft sectoring.
5-4.d.6.1 Gaps (Ref. Figure 5-4.D-7)
Each field on a track is separated from adjacent fields by a number of bytes containing no data bits.
These areas are referred to as gaps and are provided to allow the updating of one field without affecting adjacent
fields. As can be seen from Figure 5-4.D-7, there are four different types of gaps on each track.

~
Index

1.7

+ 5ms

---.j

--.J

L
Lr--

Clock

Data

Data Identifier 8 Bits

128 Bits. __ ' ...._ _
.515
--,.~

40K Bits Max 161.2ms

. .-=-----------

Variable
Fill . . .
4.9ms (Min)

-----III.~I~

166.6ms Nominal

FIGURE 5·4.0·6 Index Recording Format

.4 ± .2ms

I... -I
Sector

1L.-.____________________--'
Clock

...... 128 Bits......
.515ms

Data

Clock

Data Identifier 8 Bits
104 Bits
(Min.)
1056 Bits Max. _ _ _ _ _....
~ .....
_-V-a-ri-a-bl-e_l-. .1
4.256ms
Fill
-

~
__- - - - - - - - 5.21 ms Nominal --------'---~
.~I
.
I..

FIGURE 5-4.0·7 Sector Recording Format

5·242

Gap 1 Post-Index Gap
This gap is defined as the 32 bytes between Index Address Mark and the ID Address Mark for Sector
one (excluding the address mark bytes.) This gap is always 32 bytes in length and is not affected by any
updating process.

Gap 2 ID Gap
The seventeen bytes between the ID Field and the Data Field is defined as Gap 2 (ID Gap). This gap
may vary in size slightly after the Data Field has been updated.

Gap 3 Data Gap
The thirty-three bytes between the Data Field and the next ID Field is defined as Gap 3 (Data Gap).
As with the ID Gap, the Data Gap may vary slightly in length after the adjacent Data Field has been updated.

Gap 4 Pre-Index Gap
The three hundred and twenty bytes between the last Data Field on a track and the Index Address
Mark is defined as Gap 4 (pre-Index Gap). Initially, this gap is nominally 320 bytes in length; however, due to
write frequency tolerances and disc speed tolerances this gap may vary slightly in length. Also, after the data
field of record 26 has been updated, this gap may again change slightly in length.

5-4.D.6.2 Address Marks
Address Marks are unique bit patterns one byte in length which are used in this typical recording
format to identify the beginning of ID and Data Fields and to synchronize the deserializing circuitry with the
first byte of each field. Address Mark bytes are unique from all other data bytes in that certain bit cells do not
contain a clock bit (all other data bytes have clock bits in every bit cell). There are four different types of
Address Marks used. Each of these used to identify different types of fields.

Index Address Mark
The Index Address Mark is located at the beginning of each track and is a fixed number of bytes in
front of the first record. The bit configuration for the Index Address Mark is shown in Figure 5-4.D-8.

ID Address Mark
The ID Address Mark byte is located at the beginning of each ID Field on the diskette. The bit
configuration for this Address Mark is shown in Figure 5-4.D-9.

Data Address Mark
The Data Address Mark is located at the beginning of each nondeleted Data Field on the diskette.
The bit configuration for this Address Mark is shown in Figure 5-4.D-IO.

5-243

..
Bit Cell 0

Bit Cell 1 Bit Cell 2

Bit Cell 3 Bit Cell 4

Bit Cell 5

Bit Cell 6

Bit Cell 7

Bit Cell 0

...

I ndex Address Mark Byte

Binary Representation of

Data Bits

Clock Bits
Hexadecimal
Representation of
Data Bits
Clock Bits

FIGURE 5-4.0-8 Index Address Mark

!...Bt-i-t-C-e-II--t7....B....i-t-C-e-II"""'O.......·B-it-C-e-II--'-t4-B-it-C-e-1i-2·1:" cell:

:" Cell

~I:;, cell: I:;, cell: :" Cell :

' - - - - - - - - - - - - - I D Address Mark Byte

Bit Cell 0

------------..j

Binary Representation of"

Data Bits
Clock Bits

Hexadecimal
Representation of
Data Bits
Clock Bits

FIGURE 5-4.0-9 10 Address Mark

Deleted Data Address Mark
The Deleted Data Address Mark byte is located at the beginning of each deleted Data Field on the
diskette. The bit configuration for this Address Mark is shown in Figure 5-4.D-l1.

5-244

5-4.D.6.3 CRC
Each field written on the diskette is appended with two Cyclic Redundancy Check (CRC) bytes.
These two CRC bytes are generated from a cyclic permutation of the data bits starting with bit zero of the
address mark and ending with bit seven of the last byte within a field (excluding the CRC bytes). When a field is
read back from a diskette, the data bits (from bit zero of the address mark to bit seven of the second CRC byte)
are divided by the same generator polynomial. A non-zero remainder indicates an error within the data read
back from the drive while a remainder of zero indicates the data has been read back correctly from the disk.
C

Bit Cell 7

Bit CeliO

CDC

\ - . - - - - - - - - - - Data Address Mark Byte - - - - - - - - - -__1

Binary Representations of

Data Bits

Clock Bits

Hexadecimal
Representation of
Data Bits
7

Clock Bits

FIGURE 5-4.0-10 Data Address Mark

·
Bit Cell 7

Bit Cell

-~ .
01

Bit Cell

.. -H

1\ Bit Cell 2

Bit Cell

31 Bit Cell 41 Bit Cell 5

Bh Cell

61:;,

cell: Bit Cell

14---------- Deleted Data Address Mark Byte - - - - - - - - - - . 1
Binary Representation of

Data Bits
Clock Bits

Hexadecimal
Representation of
Data Bits
7

Clock Bits

FIGURE 5-4.0-11 Deleted Data Address Mark

5-245

APPENDIX 5-4.E FLOPPY DISK PROGRAM LISTINGS
FLDISI(

88818
88821
88838
88858
88878
88888
88898
88188
98118
80128
88138

a8el
8888
8881
8882
0883
e8e4
9885

ORC
R"B
R"B
R"B
R"B
R"B
R"B
R"B

88158 9887 8882
89168 9899 9882
88178 0888 8882
88188 88BD Be8A
88198 9817 8881
S8288 9818 9881
88218 981' 0881
00229 aelA 9881
88238 8818 9881

FYABOR
FYSTAT
FYDELT
FYCTRK
FYTRKA
FVD"RK
FY8CHT
FYDADR
FYTI"E
FVSVSP
FYUPC
FYFLGl
FV"'F LG Z
FYFLG3
FYFlG4
FYFLG5

882S8
88268

08FF

88FF

FKDATA EQU
FK"TCH EQU

88288
882'8
88388
88318

8888
8881
8882
8883

FPIPRA
FPIPRB
FP1CRA
FP1CRB

88320

8048

88338
88348
88358
88368
88379

8841
8842
8843

FP2PRA
FP2PRB
FP2CRA
FP2CRB
FP3PRA
FP3PRB

88148

9881
8881
8881
8881
0881
9881
9886 8881

8819
8911

R"B

OP/ABORT CODE
ERROR STATUS WORD
TRACK DELTA
CURRENT TRACK ADDRESS
TARGET TRACK ADDRESS
ID/DATA "ARK PATTERH
BYTE COUNTER
READ DATA STACK ADDRESS
VARIABLE INTERYAL TIME
TEMP STACK PTR STORAGE
UPC STORAGE AREA
FLAG 1
FLAG 2
FLAG 3
FLAG 4
FLAG 5

2~5

INDEX OFFSET FOR DATA STORE

1
1
1
1

1
1
2

R"B
R"B
R"B
R"B

2
2

R"B
R"B

1
1
1

R"B
R"B

EQU
EQU
EQU
EGU
EQU
EGU
EQU
EGU
EQU
EQU

FKDATA
$8880
$8881
$8882
$8883
$8840
$8841
$8842
$8843
$8810
$ 8811

5-246

PIA ADDRESSES

FLDISK

99398
99418
88428
88438
88448

90458

9885
8884
9883
eee2
98el

88498
98588
88518
98529
98538
89540 5888

C1US
C18US
C198US
Cl"S
Cl9ns

88478
8588
8499
8388
8288
9188

INTERVAL T I "ER 8-81T PRESCAlE CONSTANTS
EQU
EQU
EQU
EQU
EQU

4
3
2
1

1 "ICROSECOHD CLOCK
18 MICROSECOND CLOCK
188 "ICROSECOHD CLOCK
1 "ILLISECOHD CLOCK
19 MILLISECOND CLOCK

t HTERVAL TInER 16-81T PRESCALE CONSTAHTS

EQU
S18US EGU
S 18 au S EQU
EQU
SII1S
S19"S EQU
ORC

1288
1824

SlUS

768

512
256
$5888

5-247

1 "ICROSECOHD CLOCK
18 MICROSECOHD CLOCK
188 "ICROSECOHD CLOCK
1 "IlLISECOHD CLOCK
18 MILLISECOND CLOCK

FLDISK

88:588

.INTERRUPT DRIVEN SEEK/RESTORE ROUTINE

88688
88618
88628
88638
88648
88658
88668
'8678
88688
81698
88788
88718
88728
88738

* THIS ROUTINE EXECUTES A ONE TRACK STEP OF
• A SEEK OR RESTORE SEQUENCE. THE DISKETTE
* DRIVE "OVES THE HEAD ONE TRACK POSITION
* EACH TIME THE STEP SIGNAL IS PULSED.
* ENTRY INTO THIS ROUTINE IS GOVERNED BV
* 1 NTERRUPTS FROM THE 1 NTERYAL T I "ER. THE
* TI"ER IS PRESET TO 9.9 "ILLISECONDS FOR
• EACH STEP.
THE HU"BER OF TRACKS THE HEAD
* "UST "OYE FOR A SEEK OPERATION IS STORED
• IN RA" LOCATION -FYDELT.- FOR A RESTORE
* OPERATION ·FYDELT· IS PRESET TO 83 TO INSURE
• THAT THE "AXIMU" HUMBER OF TRACKS (77) CAN
• BE STEPPED. WHEN THE SEEK OR RESTORE IS
• CO"PlETED OR ABORTED -FVDELT· IS SET TO
• ALL OHES. WHILE THE SEEK IS IN PROGRESS
* BIT 7 OF -FYDELT- IS ZERO .

8874.

88758
• 8778

• RAM LOCATION ·FVCTRK- COHTAIHS THE CURR£HT

88788
88798

• TRACK ADDRESS OF THE HEAD. THE VALUE
• ·FYCTRK· IS IN SIGHED BINARY FOR"AT.
• IF THE SEEk DIRECTIOH IS FORWARD
* (FRO" TRACK 88) -FYCTRK- IS A POSITIYE
• BIHARY HU"BER, I.E. BIT 7 IS ZERO. IF

88888

88818
88828

.8838
88848
98858
88878
88888
88898
98988
88918
88928

88938
8894.
88958
88968
88978

• THE SEEK DIRECTION IS REYERSE (TOWARD
* TRRCK 88) "FYCTRK- IS R NEGATIYE BINARY

*
*

HUK BE R,

E. BIT 7 I SAO HE.

DISK STATUS I S CHECKED EACH STEP.

* THE STATUS IS GOOD AND THE SEEK OR
* RESTORE IS HOT CO"PLETE THE INTERYAL TI"ER
• IS RESTARTED TO TI"E OUT THE NEXT STEP.
• AN EXCEPTION TO THE ABOYE IS IF SEEK
* CO"PLETE IS DETECTED (PFYDELT BIT 7=1)
* DURING A RESTORE OPERATION THE TIMER IS HOT
• RESTARTED AND TUE RESTORE OPERATION IS
* ABO RTED. I F SEE K CO" PLET E, RES TO~ E CO f1 PLET E
* OR A STATUS ERROR IS DETECTED THE Tl"ER'
• IS NOT RESTARTED.
d

5-248

FlDISK

8e998
81888
81818
81828
81938
81848

81858

•
•
•
•
•

AM OPERATIOH/ABORT FLAG IS "AIHTAINED
IN RAM LOCATION -FYABOR- AS FOLLOWS:
8881888X SEEK/RESTORE IH PROGRESS
8181888X SEEK/RESTORE ABORTED
8881881X SEEK/RESTORE CO"PLETE
X=8 SEEK OPERATION
X=l RESTORE OPERATION

5-249

FLDISK

81888
81898
81188
81119
81129
81138

5888 96
5892 46
5893 eli
5885 F4
5888 D7

saBA

Ff(SEEK lDA
ROR
LDA
62
8841
AND
81
STA
89

81288
81219
81228
81238

*
*
*
*
5e8e
selF
5811
5814

7A 9892
28 19
7C 8883
96 8948

81259
81268
81278

ERROR
BIT
BIT
BIT

*
*

81418
81428
9 1 43 8
81440

5822 86 58
5824 C6 FF'
582 6 D7 8·2
5928 29 02

DECREMENT TRK DELTA
BRAHCH IF SEEK COMPLETE
UPDATE CURREHT TRK
FETCH CONTROL WORD

FKSK01
FKSK87

BRANCH IF NOT RESTORE OP
BRANCH IF TRK 80

RESTORE OPERATION IS COMPLETE
WHEN TRACK 08 IS DETECTED.

81358 5818 CE 8363 FKSK81 L DX
81368 selE FF 8818
STX
81379 5821 39
RTS

81398

FVDELT
FKSK04
F YC TRK
FP2PRA

READING THE DISK CONTROL WORD FP2PRA
AUTOMATICALLY GENERATES THE STEP
PULSE.

Bce
B"I

81298 5917 24 82
81388 5919 28 ID

FETCH OP CODE
IF RESTORE OP, CARRY=1
SET STATUS "ASK
'~81188818
FETCH HASKED STATUS
FP2PRB
STORE ERROR STATUS
FYSTAT
FKSK02
BRANCH IF ERROR
FYABOR

STATUS CHECKED:
1 = DISK SYSTE" INOPERABLE
5 = NOT HEAD LOAD
6 = NOT READY
DEC
B"I
1 Ne
LDA A

*
**

81328
81338

8
8
B

SHE

26 16

81158
81168
81178
81188

A
A

IS188US+99
FP3PRA
REARM TIMER FOR 9.9"5
RETURN TO INTERRUPT POLL

ERROR DETECTED IN STATUS

FKSK82 LDA A
FKSK83 LDA 8
STA B
BRA

1~818188e8

I$FF
FYDELT
FKSK0S

5-250

PRELOAD SEEK A90RT FLAG

RESTORE TRK DELTA
GO TO EXIT PREPARATION

FLDISK

81478
81498 S82A 86
01588 582C C6
91519 592£ F7
01528 5831 24
01538 5933 86

SEEK CO"PLETE DETECTED

12
FKSK84 LIft A
3C
FKSK85 lDIl B
8842
STA B
82

Bec

LDA A

*
*

81558

01568

RESTORE OP IN PROGRESS IS IHDICATED WHEN
THE CARRY BIT IS SET. BECAUSE THE TRACK
DELTA IS SET TO A HIGH VALUE (83) PRIOR
TO BEGINNING A RESTORE OPERATION AH ERROR
IS l"PLIED IF SEEK CO"PLETE IS DETECTED.
BEFORE TRACK 88 STATUS IS SEHSED.
ALSO THIS PATH IS TAKEN IF DISK STATUS IS
BAD DURING A RESTORE OPERATION.

81628

*
*
*
*
*
*

81648 383~ 97 88
81650 5837 39

FKSK86 STA A
RTS

81678

81570

81588
81598
81688

81618

*
*

81740
81768
91779
81789
81798

S849 8C
5844 86 13
5846 28 DC

SET OP/ABORT FLAG WORD
RETURH TO INTERRUPT POLL

1~88818888

FP2PRB
FP2PRA

SET FORWARD DIRECTION
GENERATE STEP PULSE

THE FORWARD STEP IS USED TO RESTORE THE HEAD
STEPPER MOTOR TO TRACK 88 PHASE.
CLC
ClR
lDA A
BRA

5841 7F 9993

FYABOR

RESTORE OPERATION COMPLETE

01698 5938 86 18
FKSK87 LDA A
81798 583A 87 8841
STA A
81718 S03D 96 8848
LDA A
81739

1%88818818
PRELOAD SEEK CO"PL FLAG
1%88111188
FP2CRA
DISABLE STEP PULSE
FKSK86
BRAHCH IF NOT RESTORE
1~81918881
PRELOAD RESTORE ABORT

CLEAR RESTORE OP FLAG
SET CURREHT TRK TO 88
RESTORE CO"PLETE FLAG
1%88018811
GO TO RESTORE EXIT PREP
FKSK83
FYCTRK

01829

* UPC LOOKUP PREPARATION ROUTINE

01848

* THIS ROUTINE CALCULATES ONE

81858
91868
81878
81888

81899

OF 58 TRACKS
FRO" THE lEAST SIGNIFICANT TWO DECIMAL
CHARACTERS OF THE upe CODE. THE RESULTANT
* TRACK IS THEN STORED IN "FVTRKA" AND THE
* THE SEEK PREPARATION ROUTINE IS BRANCHED TO .
• TRACKS 8 THROUGH 57 CONTAIN THE upe DATA.

*
*

5-251

FlDISK

:5848
S84A
584C
584E

D6 17

GET LSC OF UPC CODE
FYUPC+10
FYUPC+9
GET 2ND LSC OF upe CODE
F Kl U92
BRANCH IF 2HD CHAR = 9
119
CONYERT DECIMAL-BINARV

82018 ~85A 97 88
82828 sesc 39
82938 50SD D7 84
82948 585F 28 SA

FKlKUP LDA
LDA
BEQ
FKLUet ADD
DEC
BHE
FKlU82 LSR
C"P
BLS
LDA
STA
RTS
FKLU83 STA
BRA

82878

SEEK/RESTORE PREPARATION ROUTINE

82890
82188
82119
82128
82138

*
*
*
*
*
*
*
*
*
*

THIS ROUTIHE PREPARES THE DISKETTE DRIYE
AND RA" LOCATIONS FOR A SEEK OR RESTORE
OPERATION. FOR A RESTORE OPERATIOH THE CURRENT
TRACK ADDRESS ("FYCTRK a ) IS PRESET TO 83 AND
THE TARGET TRACK ADDRESS (aFVTRKAa) IS
CLEARED TO 89. FOR A SEEK OPERATION THE
CURRENT TRACK V~LUE IS DETERMINED BY THE LAST
SEEK OR RESTORE OPERATION. THE TRACK DELTA
(RFYDElTR) IS CALCULATED BY SUBTRACTING THE
CURRENT TRACK FRO" THE TARGET TRACK AND
CONYERTING THE SIGHED BINARY RESULT TO A
POSITIVE BINARY NU"BER.

81910
81928
81938
81940
81950

96 16
27 85

CB
sese 4A

81969 5951

81978 5053 54
81988 50S4 Cl 31
81999 5856 23 85
82009 5858 86 49

82148
92158
02169
82178
82188
82198
82288
92228
92239

92249
82258
82278
82289
02298
82388

82318
92328
82338

82348
82358

A
B

A
LOOP UNTIL CONVERSION COMPL
DIYIDE RESULT BY 2
TEST RESULT MAGNITUDE
149
FKlU93
BRAHCH IF TRK ADDR GOOD
'%01008080
SET LOOKUP ABORT CODE
FYABOR
RETURN TO EXEC PROGRAM
STORE TRACK ADDRESS
FYTRKA
GO TO SEEK PREP
FKSKIN
F KL U 01

B
B
A

A
B

*
* THE DIRECTIOH OF THE SEEK IS DETERJ1IHED BY
* SIGH OF THE TRACK DELTA BEFORE IT IS CONVERTED
* TO A POSITIVE BINARY HU"BER. IF THE SIGH IS
* NEGATIYE THE SEEK IS REVERSE (TOWARD TRK 88).
* TO INITIATE THE IHTERRUPT DRIVEN SEEK RJUTIHE
* A DUn"V INTERVAL TIMER INTERRUPT IS GENERATED
* If THE TI"ER IS HOT BUSY. If THE TI"ER IS
* BUSY IT IS ASSU~ED THAT THE INTERRUPT WILL
* ace UR WHEN THE T I MER RUHSOU T SO A DU,.. 11 Y
* INTERVAL TI"ER INTERRUPT IS NOT GENERATED.
* THUS IHTERFERENCE WITH CONCURRENT OPERATIONS
* USING THE TI"ER IS ELI"INATED, 1. E. THE SEEK
* WILL HOT BEGIN UHTILTHE TIMER IS AVAILABLE.
I

5-252

FLDISI(

92388
82488 5861 SF
82419 5852 7F
82428 5855 C6
92439 5957 86
82448 5859 28

9894

RESTORE OPERATION ENTRY

FKRSTR SEI
CLR

LDA B

11
95

LDA A
BR~

92468

82488 5958 8F

FKSKIN SEI

82498 58se D6 83

92588
82519
82528
82'38
82548

585E
5878
5872
5873
5875

86 18
97 99
5D
2A 81
58

82698 5876
82619 5978
82628 5879
82638 5878
82649 587e

96 84
19

LDR A

1%89818898

STORE OP CODE

FKSP82

BRANCH IF -fYCTRK u POSITIVE

"AKE aFYCTRK- POSITIVE

FYTRKA

FKSP0J

8PL

NEG A
HEG B

FETCH TARGET TRACK

CALCULATE TRACK DELTA
BRANCH IF DELTA POSITIVE
"AKE DELTA POSITIVE
HEGATE CURRENT TRk ADDR.

RFYCTRK· IS A NEGATIYE BINARY HUMBER IF THE
SEEK IS REYERSE

STA
ClR
588e 28 94
BRA
5882 97 82
F! 43
BRANCH IF ) 43

A '43-8
A

FOR" TRK ) 43 CONTR WOR
SET ABOYE TRK 43

'~88918811

A FPICRB

THE TRK > 43 CONTROL WORD IS GEHERATED FRO" THE
VALUE 43 AS FOLLOWS:
TRK > 43
43

EOR.

FPICRB

88181811

88818111
88111188

TRIC
43-8

=/(

88198811

88818111
88118188

IF THE TRACK IS GREATER THAN 43 THE CB2 SIGNAL
OF PIA 11 IS SET TO A HIGH. ALSO PERIPHERAL
REGISTER B IS S£LECTED BY BIT 2.

89698 52AC F7 8982
89798 S2AF C6 F9
89719 5281 86 24
89728 5283 CE 832E
99739 5286 FF 8819
89748 5289 CE C7FB

STA B
LDA 8
LDA A

FP1CRA
SELECT PERIPHERAL REG A
'256-5
SET BYTE COUNTER ~ 5
'%89188188
PRELOAD R/W HANDSHAkE

l DX

89758 S2SC 7A 8848

DEC

.S18eUS+46
FP3PRA
AR" TI"ER FOR 4.6 "5
'$C7FB
PRELOAD ADDRESS "ARK
FP2PRA
SET WRITE CATE

89778
897S8

STX
lDX

*
*

SERIAL WRITE DATA IS GATED INTO THE DRIVE AT
THIS TIME.

89888
89818
89828
89838
89848
89858

52BF F5 a8S8
CLR BYTE REQUEST
BIT B FPIPRA
52C2 87 S982
SET R/W HANDSHAKE
STA A FPICRA
52C5 86 AS
PRELOAD ENABLE CRe
LDA A 1~18181888
52C7 F5 S882 FKWR83 BIT B FPICRA
52CA 2ft FS
WAIT FOR BYTE REQUEST
BPl
FKWR93
52CC F5 8888
CLR INTERRUPT FLAG
BIT B FPIPRA
89868 S2CF 5C
UPDATE BYTE COUNTER
IHC 8
89878 52D8 26 F5
LOOP UNTIL LAST GAP BYTE
FKWR83
BHE
89888 52D2 Fl 8882 FKWR84 C"P B FPICRA
89898 52D5 28 F9
FKWR84
WAIT FOR BYTE REQUEST
8MI
89988 52D7 FF S888
STX
FPIPRA
"OYE ADDR "ARK TO PIA
99918 52DA 87 8840
ENABLE CRC
STA A FP2PRA
89928 52DD F5 8888
CLEAR INTERRUPT FLAG
BIT S FPIPRA
89938 S2E8 86 FF
PRELOAD CLK PATTERN
LDft A I$FF
89948 52E2 F6 817F
GET 1ST DATA BYTE
lDA B FKDATA+128
99958 52E5 CE 887F
1127
LOAD BYTE COUNTER
L DX
89968 52E8 B5 8882 FKWR85 BIT A FPICRA
89978 52E8 2A F8
FKWR85
WAIT FOR BYTE REQUEST
BPl
89988 52ED B7 8888
STA A FPIPRA
"OYE elK PATTERN TO PIA
5-272

FLDISK

STA 8
BIT 8
LDA B

89'98 52F8 F7 8881
18888 52F3 F5 8888
18819 52F6 C6 AS

* THE

18838
18848

18869
18879
18888
18898
18188
18119
19129

52F8
S2FA
52FD
52FF
5382
5385

F5
2A
87
F5
89

FOLLOWING SERIES OF INSTRUCTIONS IS THE

DEX
BHE

STA B
19149 5388 F7 8849
191~8 539S F~ 8082 FKWF.88 BIT B
BPL
18168 538£ 2A FS
BIT B
18178 5318 F5 8889
CLR
19188 5313 7F 8881
LDA A
19198 3316 86 AD
LDA B
18288 5318 C6 AS
18210 S31A F5 8082 FKWR89 BIT B
BPL
19228 531D 2A FS
BIT B
18230 531F F5 8989
STA S
18248 5322 F7 8948
L DX
18258 5325 CE 3E16
LDA B
IB269 5328 C6 AF
18278 532A F5 8882 FKWR19 BIT B
BPL
18288 532D 2A FS
STX
18298 S32F FF 8942
LDX

18388 5332 CE 3030
18318 5335 FF 8982
18328 5338 87 8848

STX
STA A

FETCH NEXT DATA BVTE
FKDATA,X
FPICRA
WAIT FOR BYTE REQUEST
FKWR97
"'OYE DATA TO PIA
FPIPRB
CLR INTERRUPT FLAG
FPIPRA
DECRE"EHT BYTE COUNTER
LOOP UNTIL LAST BYTE
FKWR86
FP2PRA
FPICRA
FKWR08
FPIPRA
FPIPRB

SHIFT CRe

POLL FOR 1ST CRe BYTE
CLR INTERRUPT FLAG
"OYE M00" TO DATA PIA
l~le181181
PRELOAD DROP WRITE GATE
'~10101ge0
PRELOAD STOP SHIFT CRe
FPICRA
FKWR99
POLL FOR 2ND CRe BYTE
FPIPRA
CLR INTERRUPT FLAG
FP2PRA
STOP SHIFT CRC
1$3E16
PRELOAD DISABLE INTERRUPTS
'~le181111
PRELOAD STOP WRITE
FPICRA
POLL FOR LAST BYTE REQUEST
FKWR19
DISABLE IHTERRUPTS
FP2CRA
-GATE R/W HANDSHAKE OFF
'$3830
- AND SELECT DIRECT. REG.
FPICRA
DROP WRITE GATE
FP2PRA

• MYRITE GATE- IS DROPPED 38 TO 38 "ICROSECOHDS
• AFTER THE LAST BYTE REQUEST. THIS ENSURES THAT
• THE LAST CRC BYTE HAS PASSED THE TRIMMER ERASE
* COIL IN THE R/W HEAD.

18348
18358
18369
18378

CLR
lDX
STX
LDX
STX
STA B

19398 5338 7F 8819

19488
10410
18428
10438
10440

"OYE 1ST BYTE TO PIA
CLR INTERRUPT FLAG
'~1018800e
PRELOAD SHIFT CRe

BASIC WRITE LOOP.

F~
FKWR86 LDA A
S982 FKWR97 BIT B
BPL
FS
STA A
8881
BIT B
8980

5386 26 F8

FPIPRB
FPIPRA

S33E
5341
5344
5347
534A

CE 0808
FF S0S0
CE 3434
FF S082
F7 8048

10469
1e489 534D 86 05

FP3PRA

STOP INTERVAL TI"ER

FP1PRA

CHANGE PIA 11 TO INPUTS

1$3434

FPICRA
FP2PRA

RESELECT PERIPHERAL REG.
DROP ENABLE WRITE

PIA 11 IS HOW IH READ MODE.
lDA A

1%88809118
5-273

FlDISI(

18498 534F 97 88
10589 5351 39

STA A
RTS

10529

END

FYA80R

SET WRITE COMPLETE FLAG
RETURN TO HOST PROGRA"

SYMBOL TABLE

eeel ClaMS 0801 Claus
80F!= FKERST 50A3 FKLKUP
595D FKI1TCH 98FF FKRD81
522r.4 FKRDBS 5231 F!.

-12

,----- Gnd

r-- +5

Data

Add

Control

Data

Add

Control

/').

'---

-12

+5 V
+12 V
Gnd

FIGURE 6-4.1-2: Control Circuitry Configuration

(c!l\
'\.p

~tf'l~
-

5
Bit Rate Gener.

7400

---

r-r-

91K

r- t- t-

2K
Set

VDD

.- r-

v SS

VMA A15

Decode

ocol--

t---

t-----.

TXD
MC6850
IRO
(8200CS
MC1488

_ ___

N4001

ic - -- i

L ___ .J

6NC +5
1

:-----,~~i

4.3K

~o
u

"
~
m

~
a

o
"

""
m

c
0

E
E
0
U

'"
.~

C/J

ll-

~'"

II-

-g
;

(fj

~ M~ ~

<:'

C/J

0::

'"0::

<;"
C/J

0::

.... IWVSS

I--

PAO

CA2

PAl

IRclA

PA2

IROB
RS
-

lI-

CA2

PAl
PA2

IRCA

PA3

RS
MC3001
1

MC1489

!tio f.-'
At"
R'ES- f-~

RSO
RSl -'-'-'- ~

Dl ----oJ
02 ----oJ

I
I
L 4

-12

f--

PAO

PB2

CA1~

"SS

1<> MC1489

+12
820

+12
Control

PA7

lN4001

lOOK

lK-

Control

- - - - - - - :1
"

1:''t--.. . -e-,

• I y, MC1458

Address

Y,MC1489~

lOOK

_y,

Data

+12

75K

100KJ+

510.11

5 l/Jf

~---------------t----rW~'~~

-!-

1,0/Jf

"OK, OOO.,;T '"

T
NC

2_K~it, Y,MMCCl144558;~~12K

MC1453S

+12

+12'

_ _-+_ _ _

10K

II-<

10K

RX RATE MLM311 8 6

t--

D
C
B

3
+

L-+-_2_K::~~:~~~~~~~~~~~~~~~~

4.,!
7

r--5;-...,....-+t--+It--l-~~G~;~AR MOde~vt-'--

-12

SE"LFTST

t-4

1- BRK REL

DTRf-f-f-

r-----+-+-l T_
RES
HD ET TST t.... f- TX BRK RX CARl...

R/Wh

VDO

ANS PHONE SWHf-f-

... ill

D2~

Dl~

ACIA

Jutput

Reset Mono

Out2
,... 8-Bypass
' - f - Clk Inh

rr-

r-LV_S_S_ _ _ _1_1_0~-----,...--~--~+---.
S3

50~;----,'[
.....¥."'.J-l.-HH-1ln. asc. Inh'l(
~6::-:2~0-Pf:-1"t---t-+-1--1 a utl

15M

MC14411

""---

CRX
CTX
RTS

... I·v ss
RX Data ~
.... 1- TX DATA
CTS I--1- RXBRK
ESDI-

CTS~

RXD

s2"

Crystal E l l ,8432T
MHz-l...fc:::::J

Modem MC6860

1L tss

Rate Sell------+---o--C~
~

r - - 4800
+5

"'•. . . - - - - - - . . . ,
15K
Sl
VOD H"-W'v----,
Rate Sel I------+.....;~:':'C~

---

BIT RATE ADJUST

Carrier
on Lamp

:t
0

I-

Ii!

0::
I

'"+ '"+ 'i'"

III I

!
U

Z
(9

Control Buss

FIGURE 6-4.1-3: I/O Control Card Schematic Diagram

6-13

The schematic diagram for the MPU/Control Card is shown in Figure 6-4. 1-4. The circuitry associated
with the individual peripheral devices is described in detail in their respective sections of Chapter 5. This section
will describe the remaining circuitry including the MIKbug PIA circuit (a feature of the M6800 Evaluation
Module), the clock and control circuits, the BUS EXTENDERS, RES and powerfail circuits, and the ACIA and
Modem.
The MIKbug PIA interfaces either teletype (TTY) or RS-232 type devices to the Transaction Terminal
(see Figure 6-4.1-5) for purposes of loading programs into RAM or for debugging. The TTY interface is an
optically isolated 20 rna current loop. By selecting the appropriate SI position, either the TTY or the RS232
interface will be enabled, thus allowing the selected interface to function. Paper tape reader control is also
provided. The BIT RATE oscillator is used to shift the data in and out of the PIA at the frequency required by the
interface selected, i.e., 10 cps for the TTY and 30 cps for the RS232, etc. The oscillator must be adjusted to the
frequency required for the desired data transfer rate.
+5 V

+12 V

-12 V

r
I
R20
510

20
AO 36
A135

PIA
(8004)

+5 V
R21
2200

A224
A823
A522

4
5
U29Bt-- - . . . -

0033
0132

CR1
1 N4001

+5 V

+12 V
1

L__ _ _ ~

2
PAO

0231

R24
320
1W

1N4001

i~ --I

P3
15 Serial
Output

-12 V

R25
1100
1W

L-_-.J....:..l-....--'VV'I---C:Y

13 Serial
Input

C5
I·1J..LF

0330

Serial
Common

0429
0628

U26

.---~U30P------------------------------------;--~

0627

RS-232C
Output

RS-232C
Input

0726
R/W

~~~-~U29C~---------------------------------v

RS-232C
Sig Gnd

VMA ·2 25
Reset

+5V

Q---A./IItv- V CC

R22
510

I
I

NC
6

~
,

I
I

Reader
Control

Reader
Control
Return

91K

R23
50K

FIGURE 6-4.1-5: MIKBUGTM PIA and TTV/RS-232 Circuitry

6-17

R26
150

14
1/2W
11
......
_""'--.J'-------..JVVlr----c

B it Rate Adjust

C4
620 pF

---I

D---"''''''-....:....L----J_ U22 4A3~ _

+12V
5

Since the 8K memory, 3 PIAs, and the ACIA are located" outside" the bus extenders, some address
decoding for the data bus receivers is required in order to prevent contention for control of the data bus. The system
memory map is shown in Figure 6-4. 1-6. The allocation with respect to address decoding and location with
respect to the bus extender is shown in Figure 6-4.1-7.
Note that all "external" memory has A15 and A14 at logic one and zero levels, respectively. By
Exclusive ORing A15 and A14 and combining them as shown in Figure 6-4.1-8 with R!W and (VMA· cp2),the
data bus receivers are enabled only when devices off the MPU card are addressed, that is, when:
R/W· (VMA· cp2)· (A15

+ A14)

O. The data bus drivers are enabled whenever R/W (VMA· cp2) = O. The

address bus drivers are controlled by the TSC line which is grounded for normal operation and the address bus
receivers are disabled at all times. VMA is ANDed with A15 to enable the PIAs via their CS 1 inputs. This insures
that the address on the bus is valid before the PIA is enabled.
The remaining control circuitry on the MPU card includes the MEMORY refresh control signals and
the G/H sync circuit. The memory circuit is described in detail in Section 4-1.5.3 of Chapter 4.
Control lines are provided to the output connector so that future functions such as DMA may be
implemented. These include G/H, BA and TSC. Other controls brought out for system operation are REFRESH
REQUEST, REFRESH GRANT, IRQ, NMI, RES, cp1, cp2 (memory clock), VMA, R!W, and an off board
address decode input (A15 E9 AI4).
Since the R/Wline is a tri-state output, a tri -state buffer must be used to drive the system. An MC8T26
(Figure 6-4 .1-9) was used since it will provide the inversion necessary for the data bus extender driver control line
and provides the tri-state output capability required.
Many considerations go into the memory mapping of a system. As the system design is developed and
as programs are written, changes will invariably be required in the memory allocation due to programs that are
longer than anticipated, more I/O requirements, system partitioning changes, etc.
As an example, the original transaction terminal memory allocation had all PIAs defined from
$8008-8083 as follows:
PIA-O
$8004-8007
PIA-1
PIA-2

$8008-800B
$8010-8013

PIA-3

$8020-8023

PIA-4
PIA-5

$8040-8053
$8080-8083

In order to simplify the address decoding for memory location outside the bus extenders, PIAs 1, 2,
and 3 were moved to locations C008-C023:
PIA -1

C008-COOB

PIA-2

C010-C013

PIA-3

C020-C023

This allowed the same address decoding scheme at the devices (see Figure 6-4.1-7) while allowing
simple "inside" /"outside" decoding for the data bus extender receivers. Figure 6-4.1-7 shows the address
decoding scheme used for the Transaction Terminal. Shading of the address line indicates that the line is tied to
either a device enable (E or E) or a chip select (CSx or CSx) line. A 1 indicates the line is tied to a true input (CSx or
E) a zero indicates the line is tied to a not true input (CSx or E).

6-18

# of Bytes

Address
Range

Name

Function

E3FF
Mikbug
ROM

1 K Bytes

~xxxx

xxxxxxxxxx

::ixxxx

xxxxxxxox>.::

~OOOO

OOOXOOO

Mikbug Program
Firmware

EOOO

C023

4 Bytes

C020
C013

4 Bytes

PIA-3

K eyb oa rd/D isp lay
Interface

PIA-2

I nterval Timer/Misc.
Interface

C010

en
COOB

4 Bytes

C008

PIA-1

Printer Interface

:::i
~
W

0::

o
o

BFFF

"0
(Il

:0
to

4 Bytes

8083
8080

PIA-5

Disk/Cassette Interface

4 Bytes

8043
8040

PIA-4

Disk/Cassette Interface

C
UJ

en
enw

w(!I

~o::
8007
8004

4 Bytes

OIFF
5K Bytes

PIA-O

Mikbug TTY/RS232
Interface

Direct RAM and Shared
RAM Scratch Pad Memory
N

0000

(3 (3

FIGURE 6-4.1-6: Transaction Terminal Memory Map

6-19

enUJ
I-

o
Z

en
en
~

"0
"0

==>
==>
==>
==>
==>
==>
==>

TAX % CHANGE
ENTER OPERATOR ID.
CASH CHECK
REMOVE CASH FROM REG
ADD CASH TO REGISTER
TRANSACTION VOID
CHECK AUTHORIZATION

LOOK UP CHECK
ADDR BY NAME

XACTION
VOID

ADD CASH
TO REGISTER

REMOVE CASH

PRINT/DISPLAY
"ADD CASH"

PRINT /DISPLAY
"REMOVE CASH"

CASH

SET F14

DISPLAY
NO CAN DO

CHECK

FUTURE
CODE WORDS

SET F15

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 6 of 15)

6-27

LOAD TEMP SUFFER

- -ACCA-+88
-- --

INCREMENT NO. COUNT

>---.....+--

+ 1 -+89

YES

RESET NO. COUNT
RESET 89

XFER UPC CODE INTO IN UPC

GO TO UPC
(1M = 1)

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 7 of 15)

6-28

SUBMINUS

PRINT PRETAX TOTAL
B2~PRINTER

PRINT TAXABLE TOTAL
B27 -+PRINTER
PRINT TAX
B12-+PRINTER
PRINT W!TAX TOTAL
B11 -+PRINTER

CLEAR SUBTOTAL
0-+B3

JUMP SUBTOTAL +

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 8 of 15)

6-29

SUBTOTAL <±)

WGHT

CALCULATE ITEM SUM
B2P X B2W -+B25

QUANT

CALCULATE ITEM SUM
B2P X B2Q -+B2S

(XKSQNT)

....1---+_ _ F ROM WAN
(F4 = 1)

o
DISPLA Y SUM & CAT
B2S & B2C -+DISPLAY

...
~-------------l.oIIII~-------- (F4
FROM WAN
'"
0)
=

RESET F30

SET F17

XKFG03

ADD IN-1 TO PARTIAL PRODUCT
B1P+B3-+B3

~I-------------- F ROM TOTAL

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 9 of 15)

6-30

PRINT In-1 PRICE
B1 P, "EA-" -+PRINTER
LOAD In-1 SUM/CATEG
BIS, BIC -+PRINT BUFFER

LOAD CASSETTE RAM WD 7,6
BIQ -+B4-WD 7,6
(XKFG21)

In-'

PRI NT In-1 PRICE/LB
BIP, "/LB-" -+PRINTER

WGHT

LOAD In-1 PRICE, CATEG
BIP, BIC -+PRINT-BUFFER

(XPRINT)
LOAD In-1 SUM/CRTEG
BIS, BIC -+PRINT BUFFER

LOAD CASSETTE RAM WD 7,6,0
BIW -+B4 - WD 7,6
XXXXXXI X -+B4 - WOO

In-1
NO TAX

UPDATE NO TAX BUFFER
B1P + B10-+B10
LOAD "NT" IN PRINT BUFF

START In-1 PRINT
B25-+PRINTER

LOAD CASSETTE RAM WD 5,4,3,2,',0
B1 U -+B4 - WD 5,4,3,2,1
XXXXXXXI -+B4 - WOO

>-----------------------~ GO TO "TOTAL"

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 10 of 15)

6-31

INCREMENT CASSETTE BUFFER CNT
B19 + 1 ---+B19

TRANSFER In ---+In-1
B2U ---+BIV

(XKXFER)
TRANSFER In ---+In-.1
B2P---+BIP
B2C---+BIC

QUANT

TRANSFER In ---+In-1
B2Q ---+B1Q
SET 20

1 WEGHT

TRANSFER In ---+In-1
B2W ---+B1W
SET 21

(XKX325)

(XKFGRS)
RESET FLAGS
2,4,5,16

SET F18

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 11 of 15)

6-32

TRANSFER In ---+In-1
32B ---+B 15

ADD CASH

ADD CASH TO TOTAL CASH

TO REGISTER

B8 + B15 -+B15

o
PRINT/DISPLAY
"CASH +"

SET F18
RESET F13

REMOVE CASH
FROM REGISTER

SUBT CASH FROM TOTAL CASH
B15-B18-+B15
L-__________

~----------~

o
PRINT/DISPLAY
"CASH - "

SET F18
RESET F14
CASH
CHECK

ADD CHECK TO CHECK TOTAL
B8 + B17 -+B17
DISPLAY
"SORRY"

PRINT/DISPLAY
"NO. CHECK"

SET F18
RESET F15

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 12 of 15)

6-33

FIRST
TOTAL

SET F31
SET F8
SET F18

o
o

XKSENT

TO
SUBPLUS

PRINT PRETX TOTAL
B28 -+PRINTER
PRINT TAXABLE SUBTOTAL
B27 -+PRINTER

XKDSPR

FROM
SUBPLUS

PRINT TAX
B12 -+PRINTER
DISPLAY SUBTOTAL
B3 -+DISPLA Y

PRINT W/TAX TOTAL
B11-+PRINTER

SAVE SUBTOTAL
B3 -*328
ENTER
SUBPLUS
COMPUTE TAX
B28-B 1 0 -+B27
B27 X B18-+B12

COMPUTE W/TAX TOT
B 1 7 + B 28 = B 1 1

COMPUTE FINAL TOTAL
B11-B3-+B13

DISPLAY W/TAX TOTAL
B11 -+DISPLAY

DISPLAY FINAL TOTAL
B13-+DISPLAY

SET F18
SET F22

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 13 of 15)

6-34

QUANTITY

SET F4

XFER QUANTITY INTO IN QNT

--.--

B8~B2Q

SET F5

DISPLAY "EA"
XFER WEIGHT INTO IN WGT
B8~2W

DISPLAY"#"

RESET NO. COUNT
B9~O

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 14 of 15)

NOTAX

DECIMAL PT

DO ASAP

FIGURE 6-4.2.1-1: Flow for Key Entry Data (Sheet 15 of 15)

6-35

Jrable 6-4.2.1-1
TRANSACTION TERMINAL KEYBOARD/WAND ENTRY

Keyboard

(Sheet 1 of 9)

Peripheral Action

Executive Program Action

reset display

load temp buffer

STANDARD ENTRY
#5

display #

5
CATEGORY

load In category

display #*cat*

load In price

51 4 1
SUB

add In - 1 to partial product

display #*cat*
51 4 11

load In -1 into cassette buffer

print In-l

move In to In-l

NO TAX ENTRY
NO TAX

depress key prior to SUB

set "no tax" flag

(standard entry) or 10#s (UPC entry)
SUB +
10# (UPC)
STANDARD/QUANTITY ENTRY
OPTION 1:
#s

load temp buffer

reset display
display #

CATEGORY

load In category

display #*cat*
51 4 1

load In price
load temp buffer

display # *cat*#
51 4 11

QUANTITY

load In quantity

display #*cat*#ea*
51 4 112 1

SUB

compute In total
add In - 1 to partial product

display #*
51 4 11

load In - 1 into cassette buffer

print In-l

move In to In-l
OPTION 2:

load temp buffer

reset display
display #
6-36

Table 6-4.2.1-1
TRANSACTION TERMINAL KEYBOARD/WAND ENTRY

(Sheet 2 of 9)

Keyboard

Peripheral Action

Executive Program Action

QUANTITY

display #ea *
12 1

load In quantity

display #ea*#
12 15

load temp buffer

CATEGORY

display #ea*#*cat*
12 151 4 1

load In category
load In price

display # *cat*
51 4 11
print In-l

compute In total

SUB

approval tone

add In - 1 to partial product
load In - 1 into cassette buffer
move In to In-l

reset display

load temp buffer

STANDARD/WGT ENTRY
OPTION 1:
#s

display #
CATEGORY

display # *cat*
51 4 1

load In category
load In price

display #*cat*#
51 4 14

load temp buffer

WEIGHT

display #*cat*##
51

load In weight

display #*cat*
51 4 11
print In-l

compute In total

SUB

add In -

to partial product

load In - 1 into cassette buffer
move In to In-l
OPTION 2:
#s

reset display
display #
4

load temp buffer

WEIGHT

display ##
41

load In weight

6-37

1rable 6-4.2.1-1
Keyboard

TRANSACTION TERMINAL KEYBOARD/WAND ENTRY (Sheet 3 of 9)
Peripheral Action
Executive Program Action

display ###
415

load temp buffer

CATEGORY

display ###*cat*
4151 4 1

load In category
load In price

display #*cat*
51 4 11
print In-l

compute In total

SUB

add In - 1 to partial product
load In - 1 into cassette buffer
move In to In-l

KYBD UPC ENTRY
CODE ENTRY

reset display
display UPC*ENTR Y
315
turn on UPC light

enable wand

reset display
display #
10

load tump buffer

10#s

go to disk routine
reset display
display #*cat*
51 5 11
print In-l

load In UPC
add In - 1 to partial product
load In -1 into cassette buffer

CODE ENTRY

reset display
display UPC*ENTRY
315
turn on UPC light

enable

WAND INPUT

go to disk routine
reset display
display #*cat*
print In-l

load In UPC
add In - 1 to partial product
load In -1 into cassette buffer
move In to In-l

move In to In-l
reset # count

WAND UPC ENTRY

6-38

Keyboard

llable 6-4.2.1-1
TRANSACTION TERMINAL KEYBOARD/WAND ENTRY (Sheet 4 of 9)
Executive Program Action
Peripheral Action

KYBD UPC/QUANT ENTRY

reset display
display #

load temp buffer
increment # count

QUANTITY

display #ea*

reset # count

12 1
#s

load In quantity
load temp buffer
increment # count

display #ea*#

12 110
10#s

reset display

load In UPC; compute In total

display #*cat*

add In - 1 to partial product
reset # count
load In - 1 into cassette buffer

51 5 11

move In to In-l
WAND UPC/QUANT ENTRY (in UPC mode)

QUANTITY

reset display

load temp buffer

display #

increment # count

display #ea*

load In quantity

12 1
WAND

reset # count
load In UPC; compute In total
add In - 1 to partial product

reset display
display #*cat*

51 5 11

reset # count
load In - 1 into cassette buffer
move In to In-l

EXIT UPC MODE

(#)

operator may not exit the UPC mode subsequent to depressing a # key

CODE ENTRY

reset display
display UPC DISABLE
disable upe light
disable wand

TRANSACTION TOTAL
SUB

update buffers

display #*cat*

51 4 11
print In-l
6-39

Keyboard
TOTAL

Table 6-4.2.1-1
TRANSACTION TERMINAL KEYBOARD/WAND ENTRY (Sheet 5 of 9)
Peripheral Action
Executive Program Action
reset display
add In - 1 to partial product
display #*PRETAX*TOT
load In-l into cassette buffer
51 6 1
print In-l
print # PRETAX TOTAL

TOTAL

reset display
display #*TOTAL
51
print tax/deductions
print # TOTAL

xxxx tax
compute post tax total
store tax/total on casette buffer

reset display
display #

load temp buffer

CASH

display #CA
5 2

load cash buffer

DECIMAL POINT

display #CA *#CHG
5 215 3
print cash
print change
open register drawer

calculate change
reset flags and buffers
store on cassette tape

CASH ENTRY

CHECK ENTRY -

update register cash

~uffer

no authorization

reset display
display #

load temp buffer

CHECK

display #CK
5 2

load check buffer

DECIMAL POINT

display #CK*#CHG
5 215 3
print check
print change
open register drawer

update register check buffer
calculate change
store on cassette tape
reset flags and buffers

DEDUCTION ENTRY -

(between 1st and 2nd total)
load temp buffer

reset display
display #

640

Table 6-4.2.1-1
TRANSACTION TERMINAL KEYBOARD/WAND ENTRY

(Sheet 6 of 9)

Keyboard

Peripheral Action

Executive Program Action

CATEGORY

display #*DED*

load deduct

41 4 1
SUB -

load deduct price
load deduct buffer

display #*DED*

41 4 11
MULTIPLE DEDUCTION ENTRY
OPTION 1:

load temp buffer

reset display
display #

QUANTITY

load In quantity

display #ea *

12 1
#

load temp buffer

display #ea*#

12 15
CATEGORY

display #ea*#*DED*

12 151 4 1
SUB -

load deduct
load deduct price

reset display

calculate mult price

display #*DED*

load deduct buffer

51 4 11
MULTIPLE DEDUCTION ENTRY
OPTION 2:

load temp buffer

reset display
display #

CATEGORY

load deduct

display #*DED*

41 4 1
#

load deduct price
load temp

display #*DED*#

41 4 11
QUANTITY

display #*DED*#ea*

load In category

51 4 112 1
SUB -

reset display

calculate multiple price

display #*DED*

load deduct buffer

51 4 11

6-41

Keyboard

Table 6-4.2.1-1
TRANSACTION TERMINAL KEYBOARD/WAND ENTRY (Sheet 7 of 9)
Executive Program Action
Peripheral Action

CHECK ENTRY -

with authorization/approval

# (Olnnn)

reset display

load temp buffer

display #
CODE ENTRY

display ENTER *CHECK* AMNT

look up check

51514

reset display

load temp buffer

display #
CHECK

display #CK

load check buffer

DECIMAL POINT

display #CK*#CHG

update register check buffer
calculate change
load cassette
reset flags and buffers

52 15 3
print check
print change
open register drawer
CHECK ENTRY -

with authorization (override disapproval)

# (Olnnn)

reset display
display #

load temp buffer

CODE ENTRY

display #*SORRY
1 5

look up check

reset display
display #

load temp buffer

CHECK

display #CK

load check buffer

5 2
DECIMAL POINT

display #CK*#CHG

update register check buffer
calculate change
load cassette
reset flags and buffers

5 215 3
print check
print change
open register drawer
CASH ENTRY -

subsequent to check disapproval

#(Olnnn)

reset display
display #

load temp buffer

CODE ENTRY

display #*SORRY

look up check

1 5

642

Keyboard

Table 6-4.2.1-1
TRANSACTION TERMINAL KEYBOARD/WAND ENTRY (Sheet 8 of 9)
Executive Program Action
Peripheral Action

reset display
display #

load temp buffer

CASH

display #CA
5 2

load cash buffer

DECIMAL POINT

display #CA *#CHG

update cash buffer
calculate change due
load cassette
reset flags and buffers

5 215 3
print cash
print change
open register
TRANSACTION VOID
# (02)

reset display
display #

load temp buffer

CODE ENTRY

display "TRANSACTION VOID"

reset transaction buffer and flags

DELETE PRESENT ENTRY
#,CAT,WT,QTY,NO TAX Same as a "standard" entry
CLEAR

reset display

reset In buffers and flags

DELETE PREVIOUS ENTRY
delete previous item:
SUB

CLEAR

Same as a "standard" entry
display DEL#*cat*

*DEL

6 51 4 111 3
DELETE PREVIOUS DEDUCTION
SUB -

Same as "deduction" entry

CLEAR

display #*DED*

*DEL

update deduct total

41 4 111 3
DELETE CASH ENTRY
CASH

Same as "cash" entry

CLEAR

display #CA *DEL

reset cash buffer

52 1 3
643

1l:able 6-4.2.1-1
TRANSACTION TERMINAL KEYBOARD/WAND ENTRY (Sheet 9 of 9)

Keyboard

Executive Program Action

Peripheral Action

DELETE CHECK ENTRY
CHECK

Same as "check" entry

CLEAR

display #CK*DEL

reset check buffer

52 1 3
ADD CASH -

(between transactions)

#s (03nn)

display #

CODE ENTRY

reset display
print/display "add cash"

reset display
display #

load temp buffer

TOTAL

print/display #*CASH +

update register cash buffer

REMOVE CASH -

load temp buffer

(between transactions)

#s (04nn)

display #

CODE ENTRY

reset display

load temp buffer

print/display "remove cash"
#s

load temp buffer

reset display
display #

TOTAL
CASH CHECK #s

print/display #*CASH-

update register cash buffer

(between transactions)
load temp buffer

reset display
display #

CODE ENTRY

reset display
print/display "cash check"

reset display

load temp buffer

display #
TOTAL

print/display #*CHECK

extra heads & titles

644

Jrable 6-4.2.1-2

TRANSACTION TERMINAL KEYBOARD BUFFERS
Buffer Number

Description

BIC

In-l CATEGORY POINTER

BIP
BIQ

In-l PRICE
In-l QUANTITY
In-l WEIGHT

BIW
BIS
BIU
B2P
B2Q
B2W

In-l SUM (IF QUANTITY/WEIGHT ENTRY)
In-l UPC CODE
In PRICE
In QUANTITY

B2S
B2C

In WEIGHT
In SUM (IF QUANTITY/WEIGHT ENTRY)
In CATEGORY POINTER

B2U

In UPC CODE

B3
B4
B5

TRANSACTION/DEDUCTION PARTIAL PRODUCT
CASSETTE RAM BUFFER
TRANSACTION NUMBER

TEMPORARY BUFFER (UNPACKED BCD)

B9
BI0
B 11

UPC KEYBOARD NUMBER COUNT
TRANSACTION NONTAX SUMMATION (PRICE SUMMATION)
POST TAX TOTAL

Bt2

TRANSACTION TAX

B13
B14

DEDUCTION TOTAL
SINGLE TRANSACTION CASH

B15
B16

TOTAL CASH IN REGISTER
SINGLE TRANSACTION CHECK

B17
B18
B19

TOTAL CHECKS IN REGISTER
TAX PERCENT
CASSETTE BUFFER COUNT

B20
B22

TRANSACTION CHANGE
TOTAL DOLLAR SALES

B23
B24
B25

OPERATOR IDENTIFICATION NUMBER
LOOKUP KEY SUBROUTINE MSP ADDRESSES (line 1140)
PRINTER BUFFER

B26
B27

DISPLAY BUFFER
TAXABLE TOTAL

B28

PRETAX TOTAL

6-45

Table 6-4.2.1-3
TRANSACTION TERMINAL KEYBOARD flAGS
Flag
No.

(Sheet 1 of 2)

Description

Set

Reset

Test

"TOTAL" KEY DEPRESSED TOTAL
TWICE

INITIALIZE (SU ,BT)

SUBTOTAL -

NUMBER ENTRY

INITIALIZE (SU,BT,BI)

CLEAR
CODE ENTRY

NUMBER

CLEAR
CODE ENTRY
SUBTOTAL +

UPC ENTRY MODE

CODE ENTRY
QUANTITY

INITIALIZE (SU)

CODE ENTRY

NUMBER
SUBTOTAL +

WEIGHT

In MULTIPLE ITEM ENTRY

In WEIGHT ENTRY

QUANTITY

WEIGHT

INITIALIZE (SU ,BT ,BI)

SUBTOTAL +

CLEAR
SUBTOTAL +

SUBTOTAL -

INITIALIZE (SU ,BT ,BI)

SUBTOTAL +

CLEAR
SUBTOTAL +

INVALID CHECK

CODE ENTRY

INITIALIZE (SU)

CHECK

CLEAR

CLEAR
CODE ENTRY
TOTAL

F7
F8

INITIALIZE (SU ,BT)

SUBTOTAL +

TOTAL

"TOTAL" KEY DEPRESSED TOTAL

INITIALIZE (SU)

ONCE

TOTAL

CATEGORY
NUMBER

ITEM DELETION

SUBTOTAL -

SUBTOTAL +
SUBTOTAL TOTAL

In-l UPC ENTRY

SUBTOTAL +

INITIALIZE (SU)

SUBTOTAL +

FlO

DEDUCTION ENTRY

SUBTOTAL -

INITIALIZE (SU)

SUBTOTAL -

CATEGORY

TOTAL

INITIALIZE (SU)

CLEAR

FII

CASH ENTRY

CASH

SUBTOTAL -

Fl2

CHECK ENTRY

INITIALIZE (SU ,BT)

CHECK

SUBTOTAL -

6-46

CLEAR
SUBTOTAL -

Jrable 6-4.2.1-3

TRANSACTION TERMINAL KEYBOARD FLAGS
(Sheet 2 of 2)

Flag
Description

Set

Reset

Jrest

F13

ADD CASH TO REGISTER

CODE ENTRY

INITIALIZE (SU)
TOTAL

TOTAL

F14

REMOVE CASH FROM
REGISTER

CODE ENTRY

INITIALIZE (SU)

TOTAL

CASH A CHECK

CODE ENTRY

No.

F15

TOTAL
INITIALIZE (SU)

TOTAL

TOTAL
F16

In NO TAX FLAG

SUBTOTAL

INITIALIZE (SU ,BT)

SUBTOTAL

INITIALIZE (SU)

NUMBER

INITIALIZE (SU ,BT ,BI)

NO TAX

CLEAR
SUBTOTAL
F17

In-l HAS BEEN LOADED

SUBTOTAL

F18

DISPLAY IS FULL

INITIALIZE

(BT,BI)
CLEAR
CODE ENTRY
SUBTOTAL +
SUBTOTAL TOTAL
F19

In-l NO TAX FLAG

SUBTOTAL

INITIALIZE (SU ,BT)

SUBTOTAL

F20

SUBTOTAL

INITIALIZE (SU ,BT)

SUBTOTAL

F21

In-I MULTIPLE ITEM
ENTRY
In-I WEIGHT ENTRY

SUBTOTAL

INITIALIZE (SU ,BT)

SUBTOTAL

F22

FINAL TOTAL MUST

TOTAL
BE PRINTED

CASH/CHECK

DECIMAL

F29

PRINTER FINISHED

PRINT ROUTINE

SUBTOTAL
TOTAL

F30

CLEAR LAST PUSHED

CLEAR

F31

PRETAX TOTAL MUST
PRINTED

TOTAL

POINT

TOTAL
SUBTOTAL -

6-47

6-4.2.2

Development of Macro Flow Diagram
The groundwork has been laid. The transaction terminal specification has been translated into a

detailed set of flow charts that describe the action required when a given key is depressed. At this point, the
development consists of 13 independent flow diagrams. A high level program may now be defined to interweave
all programs into an operating system.
The macro flow of the executive program is shown in Figure 6-4.2.2-1. The flow diagram has two
basic elements: initialization and item entry. The initialization is further broken down into three elements. The
first, system startup, initializes the entire system from a power on condition. The other two initialization routines
are entered between items and transactions.
The item entry procedure indicated in Figure 6-4.2.2-1 becomes the basis for the entire terminal
operation. The terminal has two methods of data entry: the keyboard or an electronic scan of encoded labels on the
products (wand). The executive program is organized so that both the keyboard and wand are serviced on a polling
basis. Immediately after initialization, the MPU begins a software poll of the keyboard and wand, looping until
service is requested.
If the keyboard requests service, the MPU begins to decode the input data to determine which key has

been depressed (keyboard decode). This data is then checked to determine if the key is allowed and the data is
processed. This check is accomplished by a Failsafe Interlock routine that protects the executive program from
processing data as a result of an operator error.
Data from the keyboard may be either standard price/category or ten numbers to represent the
universal product code (see Section 5-1.2 for a description of the UP C) . If the entry is standard, the executive will
process the data as required. Ifthe data is the result of a UPC entry, the executive will first access the floppy disk to
obtain price/category information. Upon data retrieval from the disk, the executive will then process data.
Ifthe wand requests service, the executive jumps to the wand interpreter routine. Here the stream of 0' s

and 1's read optic all y from a label is converted into ten UPC numbers. The UPC numbers are then used by the disk
program to access the associated price/category information (similar to a disk lookup as a result of 10 UPC
numbers entered from the keyboard). Once the information is retrieved from the disk, the executive program
begins normal processing of data.
As seen in Figure 6-4.2.2-1, the executive program returns to the polling loop until all necessary data
to enter an item is entered from the keyboard. If the item is a standard keyboard entry, the" subtotal

key

terminates the item. If the item is a keyboard UPC entry (10 numbers), the tenth key depressed initiates disk
lookup and item processing. The item entry is automatically considered complete at the tenth number entry and
the" subtotal + " terminator is not required. All wand entries are also considered complete item entries. Once the
item entry is completed, the MPU then reinitializes for either a new item or transaction. If the transaction is
complete, the MPU also accesses the cassette and saves the transaction data on tape.
The preceding discussion of Figure 6-4.2.2-1 is intended to review the high level flow of the
transaction terminal executive program without regard to detail. The following sections will examine the macro
flow in greater detail to demonstrate the developmental process and, in some instances, show the final objective
-

the source code itself.

648

Power On

System
Start Up
Initialization

New
Item
Initialization

--,
_J

Load
Transaction
Data On
Cassette

Initialization
New
Transaction
Initial ization

Keyboard/
Wand
Poll

\
I

Wand

KYBD

Wand
Interpreter

Keyboard
Decode

Item
Entry

~GOC

Fail Safe
Interlock

Process
Data
Continue
Entry
Item Entry
Complete

Disk UPC
Lookup

Transaction Entry
Complete

FIGURE 6-4.2.2-1: Transaction Terminal Flow Diagram

6-49

6-4.2.3

Technique of Executive Program Organization
Development of the executive program requires organized bookkeeping from the beginning. In the

flow diagrams of Figure 6-4.2. 1-1 , the tabulation of buffers and flags are just a first pass at the requirements of the
executive program. Recognizing that growth is inevitable, program management techniques must be developed
to organize the program formation.
A desirable management technique is to partition the potentially extensive program into shorter
controllable units. The program "blocks" of Figure 6-4.2.2-1 are, for example, identified as separate subroutines. As the program grows, the content of and number of subroutines often continually changes. Then with
this procedure, only related subroutines need to be updated and reassembled as alterations are made.
Individual subroutines must often reference labels used in other subroutines and/or the executive
program. Housekeeping is simplified by organizing the labels used to identify subroutine entry points, PIA
registers, RAM buffer/scratchpad, and fixed constants in ROM into an index or cross reference file. The label file
for this sytem, XLABEL, is shown as Figure 6-4.2.3-1. It defines a list of constant memory locations or addresses
that the various subroutines may reference during assembly. This eliminates the need for maintaining individual
label files with each routine as it is developed. It also insures that duplicate label naming will not later complicate
debugging since the Assembler will flag such errors during program development. Note that the listing provides
visibility as to the actual memory addresses represented by the lables. This is useful when looking for a place to
"insert" additional buffer locations and/or I/O devices if the system should be expanded.
The specific location of RAM, ROM, and I/O addresses is determined by the actual hardware
configuration (see Section 6-4.1 for a description of the hardware system). The locations shown in the label file
are assigned in accordance with the hardware. For example, the printer PIA is located in memory starting at C008
(HEX). The statement ORG C008 defines the memory address which the subsequent labels will begin filling.
Therefore, the labels on lines 110 -130 will be assigned the following values:
XP1DRA = C008
XP1CRA
C009
XP1DRB = COOA
XP1CRB

COOB

In this fashion, the four address labels used in the routines to communicate with the printer have been identified in
the software to match the hardware wiring. Should the hardware design require moving the PIA to a different
memory area, the software can be modified accordingly by simply changing the ORG statement in Table
6-4.2.3 -1, line 90.
RAM memory is the second category of lables defined in Figure 6-4.2.3-1. Similarly to the PIA
address labels, the RAM labels are prefaced by an ORG statement to define where the memory block begins.
Subsequent labels are then assigned a portion of memory as defined by the associated RMB (Reserve Memory
Byte) assembler directive.
General purpose constants used by executive subroutines are also categorized in the ROM memory
section of the listing ofFigure6-4.2.3-1. Examples seen in Figure 6-4.2.3-1 define such items as the ASCII code
for the alpha-numeric characters, canned display messages, and program masks.

6-50

00010
00020
00025
000:30
00060
00070
00080
000'30
00100
00110
00120
00130
00140
00150
00160
00170
00180
00200
00210
00220
002:30
00240
00250
00260
00270
00280
002'30
OO:~:OO

NAM
OPT
OPT

>::LABEL
t~G

•••••••••••••••••••••••••••••••••••••••••••••••••••
t~AME:

•••••

:"~LABEL

PIA ADDRESSES

•••••••••••••••••••••••

••••••••••••••••••••••••••••••••••••••••••••••••••
C008
C008
CO 0'3
COOA
COOB
COlO
COlO
C011
C012
C01:3
C020
C020
C021
C022
C02:3
8(140
8040
~::: 041
8042
804:3
8080
80::::0
::::081
::::(1:=:2
808:3

(10:310
00:320
003:30
00340
00:350
I) 0:~:6 0
00:370
003::::0
00390 0000
00400
00410
00420 0000
004:~:0 OOOA
00440 OOOB
00450
00460 OOBO
00470
00480
00490
00500 0080
00510 008A
00520
005:30
00540 008I1

ORG
0001
J) 00 1
0001
0001
0001
0001
0001
0001

::·::P 1 IIRA
::-::P 1 CRA
:=-=:P 1 IIRB
:"::P 1 eRB
~-::P2IIRA

>::P2DF::B
::·::P2CRA
::·::P2C~:B
::·::P~:IIRA

0001
0001
0001
0001

:"::P:3CF.:A
::.:: P:3 II F.: B
::-:: FI:3 ':: ~~ B

0001
0001
0001
0001

>::P4DF.:A
::-:;P4DRE:
>::P4CF.:A
::·:;P 4 CF.: E:

0001
0001
0001
0001

::::VPROD
::-::I<:I"lPLC
::-::Kl"lPLR
::-::KRSL T
::.:: K II V S~:
::·::KIt'..,'ND
::·::KG!UOT ~:MB
::·::KDSPL RMB
:;.~VFLI:; 1 ~:MB
::-::'·lFLG2 ~:MB
::·:: ..... FLG:3 ~:MB
::·::VFLI:;4 RMB
:;.~VKBTP

F.:ESUL T
MULTIPLIER POINTER (M)
::·::VMPLR
POINTER FOR XKADD AItD RROUT
RESULT POINTER (P)
2
::·::TMPLC-l
CALCULATE POINTER OFFSETS
;:'::TMPLR-l

::-~TPROIt-l

1
2
2
1
1
1
1

~:"'lE:

EG!U

::-~""'FLG4

;:'::VI"lE:2P ~:MB
5
c::,_I
::·::VI"lB 1 P F.:I"lB
c::._I
:;.::'...IME:2S RMB
::·:: ...·'MB21.a.1 ~:MB
::-::I.... MB27 RMB
5
c::;:·::Vt'lB3
F.:t-1B
._'
::.::1•••1ME: 7
~:t-l B
4
;:-:;VI"1E:26 F.:I"lB
17
:;.::I·... MB25 ~:l"lB
16
c::._I
::-:: ..... t-1B 1 S F.:ME:
;:O::Vt'lB 11,,1 Rt-1B
••
E;:·::TENDEII F.:AM
••
ORG
256
F.:,..lB
::-:;VTPE:8 ~:I"lE:
1
;:.::I·... ,..lB 1 C F.:MB
2
::·::VMK"'~C Rt-1B
1
::-:;Vt'lSGP F.:ME:
2
;:'::VMB8P F.:t'lB
2
.-.
Co
::·::Vt'lB2C F.:ME:
:;'::".·'TEI"lP ~:ME:
2
::-:: ...·'t'lE:6
F.: t1 E:
4
::·:: ..... ,..lE:2G! F.:I"lB
1
;:-:;Vt'lSTK F.:ME:
2
IlyISER ..... RME:
2
p~:eNTR F.:ME:
1

•P ..... T::-::E:F

RMB

P '. •' >:: E: F F.: F.: 1"1 B
PVCFE:F
BF 1 D~:E:
1.I.lCBFAIi
'.JDur·lBF
I...IFLAG
1.I.lF712

F.:t'1B
RMB
F.:MB
EG!U
F.: 1"1 B
EG!U

DI ..... ISOR
UNSIGNED HEX NUMBE
II I V I ItEt·iD
G!UOTIEtiT
LEFT DISPLACEMENT OF REMAIN
DEFINE GENERAL PURPOSE
BUFFERS: •

2
2
1
1
2
t,.ICBFAD
1
t..IFLAG

AVAILABLE FOR USE
I/ti PF.:ICE
I.····N-l PF::ICE
I.····ti :S:UI"1
I .····ti I}.IE I GHT
TA::·::ABLE TOTAL
PART PROD;100,10,1,.1,.Ol
I/N DEDUCTION AMOUNT
D I SPLA·...· E:UFFER
F'F.: I tiTE~: E:UFFER
1./ (ti-l ) SU,..1
I.···· (t·i-l) I.,.IE I GHT
••
ADItRESSES 256 OR ABO ..... E
STACK KEYBOARD BUFFER-I0 WO
TOP OF KYBD STACK
I/N-l CATEGORY POINTER
KEYBOARD NUMBER COUNT
DISPLAY MESSAGE POINTER
E:UFFE~: ::: PO I tiTEr;.:
I/N CATEGORY POINTER
2·BYTE TEMP STORAGE
I/N DEDUCT DESCRIPTION
G!UAtiT I T'l
TEMP STACK POINTER BUFFER
SERVICE ROUTINE STARTING AD
PAPER RIBBON FEED TIME
COUt·iTEF.:
PRINTER BUFFER POINTER
CHARACTER FILE ADDRESS
CHARACTER FILE BUFFER
PRINTER DATA REGISTER
CHARACTER BUFFER ADDRESS
DU,..l1"l'"!"' BUFFER
BAF.:.····SPACE FLAI:;
7-12 FLAG

FIGURE 6-4.2.3-1: XLABEL Assembly Listing (Sheet 2 of 6)

6-52

01040
01050
01060
01070
01080
010'30
01100
01110
01120
011:30
01140
01150
01160
01161
01162
01163
01164
01165
01170
011:=:0
011'30
01200
0121 P
01220
01230
01240
01250
01260
01270
012:3 0
012'30
01:;:00
01:310
01320
013:3 I)
I) 1 :~:4 (I
01 :35 0

0128 0001
012'3 0001
012'3
012A 0001
012B 0002
012D 0002
012F 0002
01:31 0002
013:3 0002
01:35 0002
01:37 0002
01:3'3 OOOC
0145 0005
014A 0001
014B 0005
0150 0005
0155 0005
015A 0005

1.•.ISPCt~T RME

1...IE:~~Ct~T
I...ICH~~CT
1...l:34MOII
1.•JE:ENIll
1...IBEND2
1••.IBEtiD3
1.•.1E: E t~ D4
1...lt·10DTM
t...ITSAMP
b.ISE:FAD
I.•.ISTGE:F
;:'::VME:l0
>:: ',.,' ~1 E: 1 G!

~~MB

EG!U
~~MB
~~MB
~:t-1B

.-.c.

~:ME

2
2
2
2
2

~:t-1:B

~~"'1:B
~~MB
~~I"1:E:

~:M:E:

.-.

. 1'-'
c.

~~I"1:B

a:::-

~:t-1B

1
5
5

::-::'a.,'t-1E:2E: Rt-lE:
::·::Vt-1E: 12
::.:: '",' ~1 E: 1 1
::·::V,..lB 13

1
1
I..JE:~~CtiT
1

~:MB
~~MB
~~1"1:E:

._I

'-'c'-'

:~~PACE

COUtiT
COUt'iT
CHA~:ACTER COUtiT
3/4 MODULE COUNT TIME
1.••IBEt·~D ::~ E:UFFEF.:S
BA~:

~10DULE

T I t1E
T I ~lE
STORAGE BUFFER ADDRESS
WAND STORAGE BUFFER
t'iO TA::·:: E:UFFE~~
I ..... (t'~-l) G!UAtiT I TV .
PF.:ETA::-:: TOTAL
:S:A~lPLE

AFTEF.: TA::·:: TOTAL
F I tiAL TOTAL

••••••••••••••••••••••••••••••••••••••••••••••••••
LINKING SUBROUTINES
••••••••••••••••••
••••••••••••••••••••••••••••••••••••••••••••••••••

•••••

O~~G

A043
A043 0003
A046 017D
A1C:3 01 00
A2C:~:

000:3
A2C6 000:3
A2C'3 OO?O
A:~::~:'3

A3:;:C
A5:~:'3

0003
01FD

0003
0003
01:~:E,0 A53F 0003
01370 A542 0003
01 :3:3 0 A545 01 00
01:3'30
01400 A645 000:3
01410 A648 000:3
01420 A64B 0003
014:30 AE.4E 0003
01450 A651 01E5
01460 AE::~:E. OOOF
01470 A845 3'3
014:30 A846 OOFF
014'30 A'345 :~:'3
01500 A'346 02:3F
01510 AB85 0040
A5:~:C

$A043
• XKINIT - 3 ROUTINES
XKBGIN RMB
3
~MP SFTP
XKTEND RMB
381
PUL,PUL,JMP XKBGIN
• XKYBRD - INCLUDES POLL AND KEUBOARD DECODE
XKSFTP RMB
256
JMP SFTP
.XKFLAG - 3 SUBROUTINES - RTS
::·::KTSTF ~~"'1E:
:3
::::KGF.:OC F.~"'1E
:3
::-::KDA I~: Rt-1:B
:~:
>::Kt'1TCP F.:,..1I:
:3
::~I::Kl"l:S:GD
;:'::Kl"l:S:GP
::::.::: I t·~ TP
:::: P F.: T1.1.1
::::KGF.:C··,,· FCC
2
•• TWO SPARE CONSTANT BYTE
F.:l"lB
9,$12,$15,$18,$21,$24,$27
TABLE ••
FeB
. . . t'lEAT ....... .
;:'::KI"lEAT FCC
3
••
THPEE SPARE CONSTANT BY
F.: 1"1 B
$16,$20,$24,$28,$32,$36
TABLE ••
FCB
. . . PF.:OIl ..........
::·::KF'F.:OI! FCC
.····EA-·····.····
::-::KEA
FCC
TAE:LE ••
FCB
. . . H:S:HD ..........
::·::KHSHII FCC
. . . TOTAL.····
>::KTOAL FCC
$36,$42,$48,$54
FeB
. . . EA ..........
>::f::KF.:ED'l Fr:r:
;:'::KCOUP FCC
FeB
>::t::KL I ST EG!U
;:'::KLSTT EG!U
::::1< L:S: TT
$2700

02500

+ FOLLOWING IS A FLOW OF "EXEC PROGRAM MOVEMENT:

0251 (I

02520
025::::0
02540

+ SFT TO KVBD TO IDIOT TO KVBD TO BUTTON TO SFT
(.J:S:P)
(F.:T:S:)
(.J:S:F.: )
(F.:TS)
+

02550
02560
025:::0
02600

+ SFT TO WAND TO DISK TO EXEC TO SUEP TO SFT
+
(JSP)
(JMP)
(JMP)
(JMP)
(PTS)
+ 16 - BIT TIMER PRESCALE CONSTANTS
Et'iD
FIGURE 6-4.2.3-1: XLABEL Assembly Listing (Sheet 6 of 6)

6-56

"Linking Subroutines" is the final section of the XLABEL program and is used to identify starting
addresses of subroutines. Each subroutine has a six character label as a "header" in the first instruction,
Interprogram jumps are then referenced by the header label. If, for example, the program desires to jump from the
XKSUBP program to the XKMULT program, the XLABEL will provide a link between the two by providing an
address for the assembler. Also note that the exit for each program is identified as an aid to program management.
PUSHSM is, for example, exited by a return from subroutine (RTS) instruction, implying that the program may
be called by either a branch to subroutine (BSR) or jump to subroutine (JSR) instruction.
In summary, management of labels of all subroutines are concentrated in the XLABEL program.
When all the subroutines are ultimately combined into a single executive program, the XLABEL program will no
longer be useful. However, XLABEL or some similar procedure is a useful method of linking undefined labels
during program development.
6-4.2.4

Description of Macro Flow Diagram Initialization

Initialization
The first task of the software is initialization. As shown in Figure 6-4.2.2-1, the initialization is
organized into three different elements; start-up, new transaction, and new item. The system start-up initialization is entered from the MPU's power on sequence. The MPU obtains the starting address of the Initialization
sequence as described in Section 3 -2.3. For this system, the program counteris loaded with a value A043 to begin
the start-up initialization. The portion of the start-up sequence for initializing memory, PIAs and peripherals, is
shown in Figure 6-4.2.4-1.
Memory initialization first clears all scratch pad locations from 0000 to 01FF. This area of memory
will contain temporary flags and buffers for the executive program as items are entered into the terminal. The
remainder of the memory initialization presets flag 18 (lines 240 - 250) and establishes the top address of buffer 8
(lines 270 -280).
Initialization of the PIAs is the next step in the start up routine. This segment of the program loads the
control and data direction registers of the PIAs to define the characteristics of the interface. As an example, lines
490 - 500 load 06 into the keyboard control register. This defines the CA 1 control line of the PIA to be an input
which is active on a low-to-high transition but does not cause an interrupt to the MPU. As a result, a subsequent
rising edge from the keyboard strobe (CAl) will set an interrupt flag in the PIA.
A thorough understanding of the initialization routines requires a working knowledge of the PIA and
each peripheral device. The PIA operation and details of coding are described in Section 3-4.1. The detailed
description of PIA operation with their associated peripherals are in Chapter 5.
Table 6-4.2.4-1 shows initialization code for PIAs interfacing with the keyboard, display, interval
timer, and miscellaneous controls. Additional initialization of the PIAs is performed within the peripheral
subroutines referenced in lines 630 - 772. These subroutines set up both thePIAs and their peripheral for entry of
data into the terminal.
The remainder of the initialization routines shown in Figure 6-4.2.2-1 perform housekeeping
functions when entering new items or new transactions. When entering item information from the keyboard, i. e. ,
price, category ,quantity, etc., the entry is closed with a "subtotal +." The MPU will then process the item and
return to "new item initialization" to prepare for the next entry . When initializing for a new entry, the MPU resets
appropriate flags and buffers and begins to poll for the next entry.
After finishing a transaction, the MPU returns to the initialization routine to prepare for the next
transaction. At this point, a major portion of memory must be cleared before the MPU returns to the waiting loop
6-57

00010
00010
00010
00020
00040
00050
00060
00070
00080
000'30
00100
00110
00120
00120
00121
001:30
00140
00150
00160
00170
001E:0
001'30
00200
00210
00240
00250
00260
00270
00280
00410
00420
004:30
00440
00450
00460
00470
004::::0
004'30
00500
00510
00520
005:30
00540
00550
00560
00570
00580
00590
00600
00610
00620

•
•

NAM
::-::KINITO
OPT
LIST
NAME: XKINIT
REV:
2.0 01-31-75

A043
ORG
A043 7E A049 XKBGIN JMP
A046 7E AOA7 XKTEND JMP

A049
A04A
A04B
A04E
A051

SA04:3
·...·KBGIN
·. . KTEI'iD

••••••••••••••••••••••••••••••••••••••••••••••••••
••••
SYSTEM INITIALIZATION
••••••••
••••••••••••••••••••••••••••••••••••••••••••••••••

·. . t.~E:G I N
01
OF
8E 01FF
CE BAA8
FF FFF8

•
•
•

NOP
SEI
LIIS
LDX

~~$OlFF

~~XI~
~~>!.1<"1 I TA
CLEAR MEMORY TOP AIIDRESS
A054 CE 0200
::-::1< 0 19 0 CLR
: -:;
A057 6F 00
IIE::<
GET NEXT LOWER ADDRESS
A059 09
CP;X:
~~;:·~I!.KSETF
A061 BII A2C6
.-'SR
B8 ADDRESS POINTER
•• I ti I T I AL I ZE
A064 CE 010~
A067 FF 010F

••
•

A06A
A06I1
A070
A071
A072
A074
A077

7F
7F
4F
4·:'._.
CEo
F7
C6

C021
C020

•

INITIALIZE PIAS ••••••••••••••••••••••••••••••••
INITIALIZE KEYBOARD PIA
CLR

:>:;P:3CRA

CL~:

>::P:~:IIRA

SET CRA=O
SET DATA DIRECTION

CL~: A
COl"l A
06
LDA E: ~~$06
S:TA B ::-::P:~:CF~A
SET COtiTROL REG A=06
C021
LIlA E: ~~$2C
2C
ItilTIALIZE II ISPLA·. . PIA
••
A07'3 BIt E:8BF
JS~:
DKINIT
REI~ISTER B = 00
•• I t·iTERVAL T I MER . . . 1"1 I SC P I A
SCALE FACTOR
• PAO-PA5
BINARY
COUtiT
• PBO-PE:7
bJAND
INPUT
• PA7
LIGHT OUTPUT
• PA6
BUZZER COl'iT~~OL
• CA2
SPARE
• CAl
tiOT USEABLE.····CAF.:II PIN L 11"1 I TED
• PA4,PA5

•

FIGURE 6-4.2.4-1: System Initialization Assembly Listing (Sheet 1 of 2)

6-58

00630
00740
00750
00760
00770
00771
00772
00780
00790
00800
00810
00811
00812
00820
00830
00831
00832
00832
008:~:2

00833
00834
00835
00840
00:::5 (I
00860
00870
00880
00880
00:::80
008::: 0
00880
00880
00880
00880
00880
00880
00881

A07C BD BB8C
A07F BD B919
A082 01
A08:3 01
A(1:34 (11
A085 BD B60F
A088
A08B
A08C
A08D
A090
A093
A095
A098
A09B
A09D
AOAO
AOA2
AOA5

BD
01
OE
CE
BD
C6
BD
CE
C6
BD
C6
BD
20

AFE9
BEEB
B8C2
03
B928
BE32
04
B92E
02
B928
16

AOA7
AOAA
AOAB
AOAII

E:6 C012
16
84 C7
E:A 28

AOAF
AOB2
AOB5
008'30 AOB:::
00900 AOB'3
00910 AOBA
00920 AOBD
009:30

B7 C012
B6 COlO
F7 C012

.JS~:
I I< I ti I T
•• ItiITIALIZE PRINTER PIA
-JSF.:
Pt< I PRT
•
INITIALIZE DISI< AND CASETTE ••••••••••••••
tiOP
NOP
NOP
•
INITIALIZE WAND ••••••••••••••••••••••••
.JSF.:
::-::K I WNII
.INITIALIZE FOR FAILSAFE ROUTINE •••••••••••••••••
.JSF.:
GET:S:ET
NOP
CLI
ENABLE INTERRUPTS
LD::-::
~~>~I::1< 1 065
BEG~
27 1'3
85 40
BIT A ~~$40
.-.""?
>::1<1040
C(
07
BEG!
~~$1 :::
:::6 1'='
LIlA
A
'-'
FE. C020
LDA B >::P:3DF.:A
::-:;1<1045
BF.:A
20 0:3
:E:6 C020 ::<1< 1 040 LIlA A ::::1< 1045 LIlA B ::·::P2DF.:A
~~$BF
At~II B
C4 E:F
STA B >::P2DF.:A
F7 COlO
>::1<1< ..... I t·~
.JSF.:
BD A20:3

•

TURN ON READY LIGHT
SET PA-6
ENABLE INTERRUPTS

READ KEYBOARD PIA CONTROL
CHECI< CRA?, CRAE.
IF NO PEQUEST, CHECI< WAND
CHECK FOR CLEAR KEY
IF NO, CONTINUE KYBD SERVIC
IF YES, LOAD CLEAR CODE
CLEAR I NTEF.:F.:UPT
LOAD KYBD DATA/CLEAR INTERR
TURN OFF READY LIGHT
ClF.: PA-E.
GO TO KYBD ROUTINE,ACCA=DAT

• At-i D SEF.:V ICE F.:EG!UE:S:T?
•
•>::1< 1 065 LIlA A ::-:;P2IIF.:A IS
I)_I

A1FO
A1F3
A1F5
A1F8
A1FA
A1FII
A200

BE. COlO
CE
FE. COlO
C4 BF
F7 COlO
BII B60C
7E A1C:3
2E:

Bt-l I

LDA B
At'HI B
STA B
--'SF.:
.Jt'lF'

::::P2DF.:A
~~$BF

>::P2DPA
>::KI)JAtiD
;:.::t<:SFTP

WAND ON SPACE, B7=0?
IF t-iOT LOOP E:ACI<
TURN OFF READY lIGHT
CLF.: PA-6

OTHERWISE, GO TO WAND ROUTI

FIGURE 6-4.2.4-2: Software Poll for Service Assembly Listing

6-61

Microswitch
265W3-1
Keyboard

PIA - Side A
b1

PAO

PA1

PA2

PA3

PA4

PA5
PA6
PA7
~

..r
+5 V

FIGURE 6-4.2.4-3 Keyboard/PIA Hardware Interface

6-62

CA2

CA1

Key Function

Code to PIA

Key Number

b4
0
0
0
0
0
0
0
0
0
0
0

b3
0
0
0
0
0
0
0
0
1
1

b2
0
0
0
0
1
1
1
1
0
0
0

b1
0
0
1
1
0
0
1
1
0
0
1

bO
0
1
0
1
0
1
0
1
0
1
0

0
0
0
0
0

0
0
0
1
1

0
1
1
0
0

1
0
1
0
1

0
0
0
0
0
0

0
0
0
0
0
1

0
0
0
1
1
0

0
0
1
0
1
0

0
1
1
1
1
1

0
1
1
0
1
1

0
1
1

1
0
1

Will be holding
data from
previous entry
[C2 interrupt]
1
1
0
0
[C 1 interrupt]

43
13
14
15
23
24
25
33
34
35
45

b7
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0

Grocery
Dairy
Meat/Coupon
Produce/Bottles
Hshld/Stamps

1
11
21
31
41

0
0
0
0
0

Weight
No Tax
Quantity
Total
Cash
Check

3
7
17
20
30
40

0
0
0
0
0
0

Code Entry
Subtotal (-)
Subtotal (+)
Clear

5
10
37
50

0
1
2
3
4
5
6
7

8
9
. (Demical pt.)

Strobe

0
0
0
0
0
0
0
0
0
0

0
0
0
0

0
0

0
0
0
0

1. Strobe will be high while any key is closed
FIGURE 6-4.2.4-4 Keyboard Coding/PIA Interface

6-63

in question is allowed at this point in a transaction. Referring back to Figure 6-4.2.4-5, there is a prescribed entry
procedure that the keyboard operator must follow. If the operator depresses a key that is disallowed at that point of
entry, the failsafe routine will ignore the key and return to the software poll to wait for another entry. This does not
mean that the operator must follow a rigid entry procedure. The intent is to prevent the executive routine from
operating on incomplete data. If, for example, the operator depresses three numbers after a decimal point, the
failsafe routine will ignore the third number, thereby preventing the executive routine from operating on this last
entry.
The failsafe routine categorizes all keys into 11 classes. When a key is depressed, the failsafe routine
then determines, on the basis of the state of the entry, which class of keys is allowed. The failsafe routine,
therefore, has 11 subroutines, each of which is entered from the keyboard decode routine shown in Figure
6-4.2.4-5. Notice the comments in Figure 6-4.2.4-5 which asks the question "allowed?" There are 11 such
comments throughout the listing, each of which identifies an entry into the failsafe routine. When the keyboard
routine determines which key has been depressed, it then jumps to the corresponding failsafe subroutine (1 of 11).
The failsafe routine will determine whether or not the entry is to be permitted. If allowed, the failsafe routine will
issue a return from subroutine thereby re-entering the decode routine. The decode return will continue execution
by jumping into the appropriate "data process" routine. If the key is not allowed, the failsafe routine will read
from the stack twice (to restore the stack pointer as a result of the JSR to the failsafe subroutine) and then jump to
the software poll.
6-4.2.4

Keyboard Interlock Program
As programs were developed for the keybaord and display, including rudimentary transaction

calculations, it became obvious that some sort of keyboard interlock was needed to prevent unwanted key input
sequences from hanging up program flow. A program, XKSAFE, was developed which allows only the desired
input sequences (defined in Table 6-4.2.1-1). A positive feedback audible approval tone or "beep' , is generated
when an allowed key is depressed.
Keys depressed out of sequence are ignored by the system and no "beep" is generated. The operator
may then enter a proper key without any corrections. If an erroneous allowed key is depressed, i.e., a wrong
number, etc., the CLEAR key will return the transaction to the start of the erroneous entry.
The program is a sequence of flag checking routines which

dete~ines

from the states of the tested

flags where the current operation is in an allowed transaction flow and then determines the set of keys allowable
for the next key entry. The flow is divided into four parts as shown in Figure 6-4.2.4-6:
(1) Initialization (Figure 6-4.2.4-7)

(2) Entry Routines (Figure 6.4.2.4-8)
(3) Main Processing (Figure 6-4.2.4-9)
(4) Defining Sections (Figure 6-4.2.4-10)
The Initialization subroutine is used at power on and before each new transaction. It simply sets and
clears the flags required for the start of a transaction (see Figure 6-4.2.4-7).
The entry routines are entered from the keyboard interrogation routine. Each section sets and clears
flags according to the key that has been depressed (see Figure 6-4.2.4-8).
The main body of the program follows the entry routines and determines the point where the

6-64

00:370
00:380
00:3"::10
00400
00410
00420
00430
00440
00450
00460
00470
00480
004'30
00500
00510
00520
00530
00540
00550
00560
00570
00580
00590
00600
00610
00620
00630
00640
00650
OOE,60
00670
00680
00690
00700
00710
00720

••••••••••••••••••••••••••••••••••••••••••••••••••
•••••
KEYBOARD INTERROGATION
•••••••••••••
••••••••••••••••••••••••••••••••••••••••••••••••••
A20:3
A204
A206
A207
A20"::l
A20C
A20F
A212

OF
06
AFD4
A:345
AFD1
A645

A215
A216
A21:3
A21B

5:3
2A 06
BD AFD7
7E A945

A21E
A21F
A221
A222
A224
A227
A22A
A22B
A22D
A22E

58
2A 33

A2~:0

A23:3
A236

007:~:0

00740
00750
00760
00770
00780
00790
00800
00810
00820
00830

16
2A
5:3
2B
BD
7E
BD
7E

•• SUBTOTAL + DR SUBTOTAL - ?
;:'::KK'y' I N TAB
BPL
XK3045
IF NO, CONTINUE INTERROGATI
ASL B

A23C
A23D
A23F
A242
A245
A246
A248
A24B
A24E
A251

BI"11

.JSR
Jl"lP
:X:~:::3 0:35 JSR
.Jr'lP

•••
•

:;.~K3045

ASL B
BPL
JSF.: .
--IMP

•
••• 13F.:OUP A ?
•
::·::K:3 OE.5 ASL B
BPL
ASL B
BPL
JSR

06
AFE6
AEE:5

JI"1P
::·::~::30"::lO

::-::KSUE:~l

PUSHSP
::·::KSUBP

ALLOI..JEIr?
GO TO "SUB -" ROUTltiE
ALLOI.a.lED?
GO TO "SUB+" ROUT I tiE

CODE ENTRY KEY ?

5:::

2A
BD
7E
58
2A
58
2A
E:II
7E
E:D
7E
58
2A
BD
7E
58
2A
BD
7E
BD
7E

PUSHS:~l

AS:L B
BPL
ASL B
BPL

06
AFE6
JS~:
Jl"lP
AE45
AFE3 >::K:3115 J:5:R
Jl"lP
AC45
::·::K:3120 ASL B
BPL
06
JSR
AFDD
.JMP
AB85
A:5:L B
E:PL
06
JSR
AFDA
.JMP
A836
JSR
AFEO
.Jl"lP
ABC5

PUSHCE
;:'::KCODE

IF NO,CONTINUE INTERROGATIO
ALLOI.dED?
GO TO "CODE" ~:OUT I NE

IF NO,CONTINUE INTERROGATID
:;.~K30·30

PUSHCC
>::KCASH

ALLOl.aJEII?
130 TO "CASH" "-ROUTINE

::-::K3115
PUSHCC
XKCHCK
PUSHTO
::·::KTOTL

ALLOI.aJED?
130 TO "CHECK ROUT I NE
ALLOIJJED?
130 TO "TOTAL" ROUT It-iE

PUSHQT
:;.~KI~NTV

ALLOWEII?
GO TO "QUANTIT').... ROUTINE

::-::.<:3155
PUSHN:X:
: .: Kti TA :;.~
PUSHI..JT
>::K ....IGHT

ALLOWED?
GO TO "NO TAX" ROUTINE
ALLOWED?
GO TO "I..JEIGHT" ROUTINE

FIGURE 6-4.2.4-5: Keyboard Decode Assembly Listing (Sheet 1 of 2)

6-65

00::::40
00::::50
00::::60
00::::70
00::::::::0
00::::'30
00'300
00910
00920
(10'3:30
0094n
0'35
096
0'37
09::::
0'39
100
0101)
01020
010:30
i 1040
1050
1060
1070
108
10'3
11 0
111
112
11:3
0114
0115l
01160
0117 n
0118
011'3
0120
i 121
122
12:3
124
125(
1260
(1270
012::::0
01290
01300
01310
01320
01330
01340
Ol:~:50

•••
•::·::K:3165

GF.~DUP

A254
A255
A"257
A25::::
A25A
A25D
A260
A262
A265
A267
A26E:
A26A
A26E:
A26C
A26E
A271
A274
A275
A277
A27:3
A27A
A27D
A280

5::::
2A 2C

5::::
2A
BD
7E
II7
BD
D6
5::::
2A
58

06
AFC5
AEC5
A7
::::K3225
0'3
0:3
A5:3F
A53C XK3255
A5:39 XK3260

81 OA
A285 26 10

A2::::'3
A2:3C
A2:3E
A2'31
A2'34

BD
27
7E
ED
7E

A297
A299
A29E:
A29I1
A29F
A2A2
A2A4
A2A6
A2A9
A2AC
A2AE

97
:::1
27
::::6

ED
20
::::6

ED
ED
96
7E

•••
•

ASL E:
E:PL
A:~:L B
BPL
.J:~:F.~

.J,..lP
STA
.-'SF.:
LDA
ASL
BPL
ASL
ASL
BPL
.Jr'lP
.JMP
ASL
BPL
ASL
BPL
.Jt'lP
.JMP
JMP

>::K:3270
;:::
'-•.IITH THE I t-~TEF.~F.~UPT SEF.:V. ADD
J:S:P
I F.:G!2F~1
~~ ~J; Er :::
~lA:S:K Ut-i I..J A t-i TED BITS
F.:G!2F~1 A~iD A
~~~1;4:::
TE:S:T IF I t-~PUT, Et~ABLED ,
Ct'lP A
I ~~TF.~PT FLAG :S:ET
t-iO
EtiII
BtiE
I F~G!E~iD
....·ES ADJU:S:T STACK At-iD
PUL A
PUL A
-jUt'lP TO THE It-iTRPT
:;.::
S EF.: 1•••1 I CE F.:OUT I t-~E
.Jt·lP

FIGURE 6-4.3-2: Interrupt Poll Assembly Listings (Sheet 2 of 2)

6-94

At-in

CHAPTER 7
7.

SYSTEM DEVELOPMENT TASKS
The development of any system is, in a sense, like Figure 7-1 where the desired end product is shown

as being analogous to the visible above-water portion of an iceberg. It is only this portion that contributes to the
ultimate success (or failure) of a project. Beneath the surface are the many necessary steps that must be
performed if the project is to be successful. Such tasks as design, prototyping, evaluation, documentation, etc.,
must be performed regardless of whether or not the design incorporates an MPU.
In one respect, using a microprocessor simplifies the effort. Major reasons for using an MPU are,
after all, to reduce the design cycle time and replace many conventional logic packages with a few LSI devices.
However, in order to benefit fully from the attendant reductions in evaluation time and manufacturing cost, the
additional tasks introduced by the use of the MPU must be handled efficiently.
The main additional task in an MPU -based system is generation of the control program that will
eventually serve as the system's "intelligence". This program, while generally referred to as "software"
throughout the development stage, will ultimately be stored in the system memory in most designs. This

WATER LINE

MANUFACTURE

DESIGN/PROTYPE EVALUATE/DOCUMENT
TRAI N/MAI NTAI N
MPURELATEDTASK:CONTROLPROGRAM

CROSS ASSEMBLER

INTERACTIVE SIMULATOR

EXORciserS

COMPUTER GENERATED MEMORIES

TRAINING
TEST AND DIAGNOSTIC PROGRAMS
LIBRARY OF MPU ROUTINES

FIGURE 7-1: System Development: Like an Iceberg

7-1

Chapter briefly describes the design aids and products that Motorola provides for assistance in efficiently
performing this task. The principle items, as shown in the lower portion of the iceberg, are the Cross
Assembler, an Interactive Simulator, and an EXORciser.
The recommended procedure for developing and verifying a design using these aids is indicated in
the Flowchart of Figure 7-2. Briefly, the control program is written, assembled, simulated, and exercised. The
output of the process is system documentation and a tape suitable for generating appropriate memories. Each of
these steps are discussed in subsequent sections of this Chapter, however, greater detail can be obtained by
referring to the M6800 Programming Manual and the several manuals associated with the EXORciser.

7-1

ASSEMBLY OF THE CONTROL PROGRAM
While programs can be written in the MPU's language, that is, binary numbers, there is no easy way

for the programmer to remember the particular binary number that corresponds to a given operation. For this
reason, the MPU's instructions are assigned a three letter mnemonic symbol that suggests the definition of the
instruction. Normally, the program is written as a series of source statements using this symbolic language and
then translated into machine language. The translation can be done manually using an alphabetic listing of the
symbolic instruction set such as that shown in Table 7-1-1. More often, the translation is accomplished by
means of a special computer program. When the target program is assembled by the same microprocessor (or
computer) that it will run on, the program that performs the assembly is referred to simply as an Assembler. If,
as is often the case, the target program is assembled by some other computer, the process is referred to as
cross-assembly.
Motorola provides such a program, the M6800 Cross-Assembler, on severaP nationwide
timesharing services. This permits subscribers to the services to efficiently assemble their control programs as
indicated in Figure 7-2. The source program is entered via their in-house terminal and assembled. If necessary,
the host system's Edit package is available for incorporating corrections and changes. In addition to the
assembled output file, the Cross-Assembler provides other useful outputs. If the user is satisfied that the code as
assembled is correct, a punched paper tape that is compatible with Motorola's EXORciser and ROM
programming computer can be generated. The Cross-Assembler also provides a hard-copy output of the
Assembly Listing. For properly commented and formatted programs, this Listing is an important part of the
system documentation.

7-1.1

M6800 CROSS-ASSEMBLER SYNTAX
The syntax or language requirements for using the Motorola Assembler (and other support software)

falls into one of two categories: (a) Requirements for conversing with the host computers operating system; (2)
Requirements for conversing with the Motorola programs.
The first category varies from service to service. The documentation of the specific service being
used should be obtained and referred to when using the support software. Where references are made to the host
computers syntax in this Chapter, the General Electric procedures are shown. The emphasis in this Chapter is
IG .E. plus others to be announced later. The M6800 Cross-Assembler and the other special programs (Simulator, Build Virtual
Machine, Help) described in this Chapter are maintained by Motorola and are dynamic programs that are constantly being improved.
The descriptions in this Chapter reflect the status as of the time this Manual was printed. All changes are indicated in the Help program
and can be obtained at the actual time the programs are to be used.

7-2

PROCEDURE FOR DESIGNING
AND VERIFYING A SYSTEM USING
THE MOTOROLA MBIDD MICROCOMPUTER
FLOWCHART
FUNCTIONS TO BE
PERFORMED

ENTER INTO
TIME·SHARING
SYSTEM

ASSEMBLY
LISTING

SIMULATION
LISTING

PUNCHED PAPER
TAPE

ENTER

'-_""OI!!§~~~~~I;,:NTO

EXORciser

(DESIGN VERIFICATION)

(FOR DOCUMENTATION PURPOSES)

FIGURE 7-2:

7-3

Mnemonic
Code

Addr.
Mode

Hex
Code

Mnemonic
Code

Addr.
Mode

Hex
Code

Mnemonic
Code

Addr.
Mode

Hex
Code

Mnemonic
Code

Addr.
Mode

Hex
Code

ADA
ADC(A)
ADC(A)
ADC(A)
ADC(A)
ADC(B)
ADC(B)
ADC(B)
ADC(B)
ADD(A)
ADD(A)
ADD(A)
ADD(A)
ADD(B)
ADD(B)
ADD(B)
ADD(B)
AND(A)
AND(A)
AND(A)
AND(A)
AND(B)
AND(B)
AND(B)
AND(B)
ASL(A)
ASL(B)
ASL
ASL
ASR(A)
ASR(B)
ASR
ASR
BCC
BCS
BEQ
BGE

Inherent
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended

BMI
BNE
BPL
BRA
BSR
BVC
BVS
CBA
CLC
CLI
CLR(A)
CLR(B)
CLR
CLR
CLV

Relative
Relative
Relative
Relative
Relative
Relative
Relative
Inherent
Inherent
Inherent

2B
26
2A
20
8D
28
29

31
08
6E
7E
AD
BD
86
96
A6
BE
CE
DE
EE
FE
8E
9E
AE
BE
CE
DE
EE
FE
44
54

ROR
RTI
RTS
SBA
SBC(A)
SBC(A)
SBC(A)
SBC(A)
SBC(B)
SBC(B)
SBC(B)
SBC(B)
SEC
SEI
SEV

Extended
Inherent
. Inherent
Inherent
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Inherent
Inherent
Inherent

76
3B
39
82
92
A2
B2
C2
D2
E2
F2
OD
OF
OB

BGT
BHI
BIT(A)
BIT(A)
BIT(A)
BIT(A)
BIT(B)
BIT(B)
BIT(B)
BIT(B)
BLE

Relative
Relative
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Relative

2E
22
85
95
AS
B5
C5
D5
E5
F5
2F

STA(A)
STA(A)
STA(A)
STA(B)
STA(B)
STA(B)
STS
STS
STS
STX
STX
STX
SUB(A)
SUB(A)
SUB(A)
SUB(A)
SUB (B)
SUB(B)
SUB(B)
SUB (B)
SWI
TAB
TAP

Direct
Indexed
Extended
Direct
Indexed
Extended
Direct
Indexed
Extended
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Inherent
Inherent
Inherent

97
A7
B7
D7
E7
F7
9F
AF
BF
DF
EF
FF
80
90
AO
BO
CO
DO
EO
FO
3F
16
06

Inherent
Inherent

17
07

TST(A)
TST(B)
TST
TST
TSX

Indexed
Extended
Inherent

4D
5D
6D
7D
30

TXS
WAI

Inherent
Inherent

35
3E

Relative
Relative

23
2D

INS
INX
JMP
JMP
JSR
JSR
LDA(A)
LDA(A)
LDA(A)
LDA(A)
LDA(B)
LDA(B)
LDA(B)
LDA(B)
LDS
LDS
LDS
LDS
LDX
LDX
LDX
LDX
LSR(A)
LSR(B)
LSR
LSR
NEG(A)
NEG(B)
NEG
NEG
NOP
ORA(A)
ORA(A)
ORA(A)
ORA(A)
ORA(B)
ORA(B)
ORA(B)
ORA(B)
PSH(A)
PSH(B)
PUL(A)
PUL(B)
ROL(A)
ROL(B)
ROL
ROL
ROR(A)
ROR(B)
ROR

Inherent
Inherent
Indexed
Extended
Indexed
Extended
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended

Indexed
Extended
Relative
Relative
Relative
Relative

89
99
A9
B9
C9
D9
E9
F9
8B
9B
AB
BB
CB
DB
EB
FB
84
94
A4
B4
C4
D4
E4
F4
48
58
68
78
47
57
67
77
24
25
27
2C

BLS
BLT

Indexed
Extended

CMP(A)
CMP(A)
CMP(A)
CMP(A)
CMP(B)
CMP(B)
CMP(B)
CMP(B)
COM(A)
COM(B)
COM
COM
CPX
CPX
CPX
CPX
DAA
DEC(A)
DEC(B)
DEC
DEC
DES
DEX
EOR(A)
EOR(A)
EOR(A)
EOR(A)
EOR(B)
EOR(B)
EOR(B)
EOR(B)
INC(A)
INC(B)
INC
INC

Indexed
Extended
Inherent
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended

Indexed
Extended
Immediate
Direct
Indexed
Extended
Inherent

Indexed
Extended
Inherent
Inherent
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended

Indexed
Extended

OC
OE
4F
SF
6F
7F
OA
81
91
Al
Bl
Cl
Dl
El
Fl
43
53
63
73
8C
9C
AC
BC
19
4A
SA
6A
7A
34
09
88
98
A8
B8
C8
D8
E8
F9
4C
5C
6C
7C

Indexed
Extended

Indexed
Extended
Inherent
Immediate
Direct
Indexed
Extended
Immediate
Direct
Indexed
Extended

Indexed
Extended

Indexed

TAB L E 7-1-1: Alphabetic Listing of I nstruction Mnemonics

7-4

74
40
50
60
70
02
8A
9A
AA
BA
CA
DA
EA
FA
36
37
32
33
49
59
69
79
46
56
66

TBA
TPA

on the language requirements of the Motorola programs. These requirements are constant and, except for minor
variations in format, do not vary from system to system.
The source program is nothing more than a list of instructions that the MPU is to execute during
system operation. All that is required is that the mnemonic instructions used by the programmer to write the
program be translated into bInary machine language acceptable to the MPU. However, if the Cross-Assembler
is to be used to perform the translation, the language and format described in the following paragraphs should
be used.
The source program is written in an assembler language consisting of the 72 executive instructions
and the assembly directives shown in Table 7-1.1-1. The assembly directives are useful in generating,
controlling, and documenting the source program. With the exceptions of FCB, FCC, and FDB, they do not
generate code. The characters recognized by the Assembler include A through Z of the alphabet, the integers cf>
through 9 , and the four arithmetic operators +, -, *, and /. In addition, the following special prefixes and
separating characters may be used:

(pounds sign) specifies the immediate mode of addressing.
$ (dollar sign) specifies a hexadecimal number.
@ (commercial at) specifies an octal number.
% percent) specifies a binary number.
apostrophe) specifies an ASCII literal character.
SPACE
Horizontal TAB
CR (carriage return)
(comma)

The character set is a subset of ASCII (American Standard Code for Information Interchange, 1968) and
includes the ASCII characters, 20 (SP) through 5F (+-). The ASCn code is shown in Table 7-1.1-2.

7-5

END -

End of Program
The assembler directive" END" , if used, marks the end of a source program, and can be followed
only by a statement containing the assembler directive "MON" . The operator in the last statement
of a source program must be either "END" or "MON". If the program ends with a "MON"
directive, the use of "END" is optional. The "END" directive must not be written with a label, and
it does not have an operand.

EQU -

Equate Symbol
The "EQU" directive is used to assign a value to a symbol. The "EQU" statement must contain a
label which is identical with the symbol being defined. The operand field may contain the numerical
value of the symbol (decimal, hexadecimal, octal, or binary). Alternatively, the operand field may
be another symbol or an expression which can be evaluated by the Assembler. The special symbol

"*,, which represents the program counter must not be used.
Examples of valid "EQU" statements:

Data

Label

Operator

Operand

OA01

SUN

EQU

$A01

0003

AB
AA

EQU

OA01

EQU

3
SUN

OA04

EQU

AB+AA

OFC1

ABC

EQU

$FCI

If a symbol or an expression is used in the operand field, only one level of forward referencing will

assemble correctly. This reflects a two-pass characteristic of the assembly process. An illegal
example of two levels of forward referencing would be:
E

EQU

This will not assemble correctly because E will not be assigned a numerical value at the end of pass
2. E and Yare both undefined throughout pass 1 and will be listed as such at the end of pass 1. E is
undefined throughout pass 2 and will cause an error message.
FCB - £orm ~onstant !!yte
The "FCB" directive may have one or more operands, separated by commas. An 8-bit unsigned
binary number, corresponding to the value of each operand is stored in a byte of the object program.
If there is more than one operand, they are stored in successive bytes. The operand field may contain

the actual value (decimal, hexadecimal, octal or binary) or be a symbol or an expression which can
be assigned a numerical value by the Assembler. An "FCB" directive followed by one or more void
operands separated by commas will store zeros for the void operands. An "FCB" directive may be
written with a label.

TABLE 7-1.1-1 Assembler Directives (Sheet 1 of 6)

7-6

Examples of valid "FCB" directives:

FCC -

Location

Data

Label

Operator

Operand

0000
0001
0002

FF
00
OF

TOP
TAB

FCB
TCB

$9FF
,$F,23,

0003
0004
0005

17
00
E5

FCB

*+$EO

Form Constant Characters
The "FCC" directive translates strings of characters into their 7-hit ASCII codes. Any of the
characters which correspond to ASCII hexadecimal codes 20 (SP) thru 5F ( ~) can be processed by
this directive. Either of the following formats may be used:
1. Count, comma, text. Where the count specifies how many ASCII characters to generate and the
text begins following the first comma of the operand. Should the count be longer than the text,
spaces will be inserted to fill the count. Maximum count is 255.
2. Text enclosed between identical delimiters, each being any single character. (If the delimiters are
numbers, the text must not begin with a comma.)
If the stringjn the operand consists of more than one character, the ASCII codes corresponding to

the successive characters are entered into successive bytes of memory.
An "FCC" directive may be written with a label.
Examples of valid "FCC" directives:

Location

Data

Label

Operator

Operand

OAOO
OAOI

MSG1

FCC

TEXT

MSG1

FCC

9,TEXT

OA02
OA03
OA04
OA05
OA06
OA07
OA08
OA09
OAOA
OAOB
OAOC

45
58
54
54
45
58
54
20
20
20
20
20

TABLE 7-1.1-1 Assembler Directives (Sheet 2 of 6)

7-7

FDB - !'orm .Qouble Constant Byte
The "FDB" directive may have one or more operands separated by commas. The I-bit unsigned
binary number, corresponding to the value of each operand is stored in two bytes of the object
program. If there is more than one operand, they are stored in successive bytes. The operand field
may contain the actual value (decimal, hexadecimal, octal or binary) or be a symbol or an expression
which can be assigned a numerical value by the assembler. An "FDB" directive followed by one or
more void operands separated by commas will store zeros for the void operands.
An "FDB" directive may be written with a label.
Examples of valid "FDB" directives:

MON -

Location

Data

Label

Operator

Operand

0010
0012
0014
0016
0018

0002
0000

TWO
MASK

FDB
FDB

OOlA

OAFF

,$F ,$EF ,,$AFF

OOOF
OOEF

0000

Return to Console
The assembler directive "MON", if used, must be in the last statement of a source program. (See
assembler directive "END" above.) The "MON" directive instructs the assembler that the source
program just completed is the last to be assembled, and will return control to the user at the keyboard
of the terminal by printing the input request "READY".
The last statement of a source program must contain either" END" or" MON" . If the last statement
of the program has" END" as its operator, the Assembler will request another file upon completion
of assembly, by printing:
SI FILENAME
?
If the user does not wish to assemble another file he may type" .EOF" (Le. type a period followed

by an "END OF FILE" character). The assembler directive "MON" must not be written with a
label, and no operand is used.
NAM-Name
The' 'NAM" (or NAME) directive names the program, or provides the top of page heading text
meaningful to users of the assembly. The "NAM" directive must not be written with a label. The
"NAM" directive cannot distinguish the operand field from the comment field. Both the operand
field and the comment field are treated as continuous text.
TABLE 7-1.1-1 Assembler Directives (Sheet 3 of 6)

7-8

OPT -

Option
The "OPT" directive is used to give the programmer optional control of the format of assembler
output. The "OPT" directive is not translated into machine code. No label may be used with the
"OPT" directive. The options are written in the operand field following the directive, and are
separated by commas.
The available options are:

Long Form

Short Form

LIST

Selects listing of the assembly in long format (selected by default).

SLIST

SLIS

Selects listing of the assembly in an abbreviated form.

NOLIST

NOL
NL

Suppresses the printing of the assembly listing.

SYMBOL

SYMB

Causes the symbol table to be printed (selected by default).

NOSYMBOL

NOSYMB Suppresses the printing of the symbol table.
NOS
NS

GENERATE

GENE

Causes full printing of all code generated by FCC directive (selected
by default).

NOGENERATE NOGENE Causes only one line of listing to be generated by FCC directive.
NGENE
NOG
NG
ERROR

Selects printing of error messages in long format (selected by
default).

SERROR

SER

NOERROR

NERROR Suppresses the printing of error messages.
NOE
NE

Selects printing of error messages in an abbreviated form.

PAGE

Causes the listing to be page formatted and to have a heading on each
page (selected by default).

NOPAGE

NPAGE

Causes the listing to be continuous without page formatting.

TAB

Causes horizontal formatting of the listing (selected by default).

NOTAB

NOT
NT

Suppresses horizontal formatting of the listing.

TABLE 7-1.1-1 Assembler Directives (Sheet 4 of 6)

7-9

DB8

Octal display base.

DB10

Decimal display base

DB16

Hexadecimal display base (selected by default).
M

MEM

Instructs the assembler to save the object program in a permanent
file.

NOMEM

Assembler does not save the object program (selected by default).

NOM
NM

The assembler directive "ORG" defines the numerical address of the first byte of machine code
which results from the assembly of the immediately subsequent section of a source program. There
may be any number of "ORG" statements in a program. The "ORG" directive sets the program
counter to the value expressed in the operand field.
The operand field may contain the actual value (decimal, hexadecimal, octal or binary) to which the
program counter is to be set or may contain a symbol or an expression which can be assigned a
numerical value by the assembler. The special symbol" *" , which represents the program counter
must not be used.
The location counter is initialized before each assembly. If no "ORG" statement appears at the
beginning of the program, the location counter will begin as if an "ORG" zero had been entered.
Examples of valid "ORG" statements:

Location

Data

Label

Operator

Operand

(1)

0064

(blank)

ORG

100

(2)

AF23

(blank)

ORG

BEGIN
(BLANK)

EQU

1100

$AF23
$1100
BEGIN

(3)

ORG

PAGE -Advance Paper to Top of Next Page
The' 'PAGE" directive causes the Assembler to advance the paper to the top of the next page. The
PAGE directive does not appear on the program listing. No label or operand is used, and no machine
code results.
RMB -Reserve Memory ~ytes
The' 'RMB" directive causes the location counter to be increased by the value of the operand field.
This reserves a block of memory whose length is equal to the value of the operand field. The operand
field may contain the actual number (decimal, hexadecimal, octal or binary) equal to the number of

TABLE 7-1.1-1 Assembler Directives (Sheet 5 of 6)

7-10

bytes to be reserved or may be a symbol or an expression which can be assigned a numerical value by
the assembler.
The block of memory which is reserved by the "RMB" directive is unchanged by that directive.
The "RMB" directive may be written with a lable.
Examples of valid "RMB" directives follow:

SPC -

Location

Data

0100

0104
0118

00
00

Spa~e

Label
TABLE 1
TABLE 2

Operator

Operand

RMB

RMB
RMB

20
20

Lines

The "SPC" directive provides vertical spaces for formatting the program listing. It does not itself
appear in the listing. The number oflines to be left blank is stated by an operand in the operand field.
The operand would normally contain the actual number (decimal, hexadecimal, octal or binary)
equal to the number of lines to be left blank. A symbol or an expression is also allowed but must be
assigned a numerical value during assembly by means of an EQU statement.

TABLE 7-1.1-1 Assembler Directives (Sheet 6 of 6)

7-11

ASCII CHARACTER SET (7-BIT CODE)
M.S.
CHAR
L.S.
CHAR

0
0000
1
0001
2
0010
3
0011

1000
9

1001
A
1010
B
1011

0
000

1
001

010 011 100 101 110 111

NUL DLE SP

SOH DC1

STX DC2

ETX DC3

CAN

(

)

SUB

ESC

TABLE 7-1.1-2 ASCII Code

7-12

j
k

7-1.1.1

Line Numbers
When preparing a source program for entry via a timesharing terminal, each source statement is

normally assigned a line number. The line number is followed by a SPACE and the character position
immediately following that SPACE is then the first character position of the source statement. The line numbers
are usually assigned in multiples of a base so that additional statements can be inserted later, if necessary. For
example, numbering as 1, 5, 10, 15, 20, etc., leaves room for 4 statements to be added between each of the
original statements.

7 -1. 1.2

Field of the Source Statement

Each statement in the source program may have from one to four fields: a label, a mnemonic
operator (instruction), an operand, and a comment. Each statement must have at least the mnemonic operator
field. An operand mayor may not be required, depending on the nature of the instruction. The comment field is
optional at the programmer's convenience for describing and documenting the program.
The successive fields in a statement are normally separated by one or more spaces. An exception to
this rule occurs for instructions that use dual addressing in the operand field and for instructions that must
distinguish between the two accumulators. In these cases, A and Bare' 'operands' , but the space between them
and the operator may be omitted. This is commonly done, resulting in apparent four character mnemonics for
those instructions.
If the statement includes a label, it must begin in the first character position of the statement field. A
SPACE in the first position will indicate that no label is included with the statement. Note that if line numbers
are being used, there must be two or more spaces between the number and the operator when labels
are not used.
7 -1. 1. 3

Labels
Labels may be up to six characters long and use any alphanumeric combination of the character set

with the restriction that the first character be alphabetic. Three single character labels, A, B, and X, are
reserved for referring to accumulator A, accumulator B, and the Index Register, respectively. In general, labels
may correspond to either numerical values or memory locations. The use of symbolic references to memory
permits initial programming to be done without using specific absolute memory locations.
Labels are required for source statements that are the destination of jump and branch instructions.
(Such an instruction would have the same label as its operand.) Labels may be used with any executable
instruction at the option of the programmer.
A label is normally used with the assembly directives FCB, FCC, FDB, and RMB. A label must be
used with the directive EQU and will be equated to the symbol which the EQU statement is defining. Labels
must not be used with the other assembler directives. See Table 7-1. 1-1 for examples.
7-1.1.4

Operands

The operand field can contain numerical values, labels, or algebraic expressions that can be
evaluated by the Assembler. Such expressions can include the arithmetic operators + (addition), - (subtraction),

* (multiplication), or / (division).
The assembler evaluates expressions algebraically from left to right without parenthetical grouping,
7-13

with no heirarchy of precedence among the arithmetic operators. A fractional result, or intermediate result, if
obtained during the evaluation of an expression, will be truncated to an integer value. The use of expressions in
the source language does not imply any capability of the microprocessor to evaluate those expressions, since
the expressions are evaluated during assembly and not during execution of the machine language program.
7-1.1.5

Comments

Comments for improving understanding of the program can be included in source statements by
inserting a SPACE and then the comment after the operand. If the instruction does not require an operand,
everything following the insertion of one or more SPACEs after the operator will be treated as a comment.
Additional documentation information will appear on the assembler generated program listing if an
asterisk is used in the first character position of a statement. Everything following the asterisk is then converted
into a comment and does not affect the machine language generated by the assembler.

7-1.2

ACCESSING A TIMESHARE SERVICE

As indicated earlier, the details of accessing vary from service to service, however, the following
example based on the G .E. system serves to illustrate the procedure. It is assumed that a series of source
statements have been prepared and are to be entered into the host computer in preparation for assembly.
(1) Dial the telephone number assigned for computer access.
(2) When the network responds, enter HHHH on the keyboard so that the terminal's speed can be
determined.
(3) In each case, conclude entries with a carriage return. The computer acknowledges entries by
providing a line feed.
(4) Enter user number and password.
(5) If the computer requests additional identification, a code may be entered for additional
protection of the program. If this is unnecessary, enter a carriage return to bypass.
(6) Identify the system language that will be used by the Assembler. The Motorola
Cross-Assembler language is identified by entering: FIV.
(7) When the computer acknowledges a command, rather than merely the entry of information, it
responds with the word "READY" in addition to the usual line feed.
(8) After identifying the system, the user must specify whether an old or new file is to be used.
Therefore, the user must enter: OLD:xxxxxx where xxxxxx represents the name of the old 'file
that is to be changed, or NEW:xxxxxx where xxxxxx is the name of the new program.
(9) After the computer has responded "READY", the source statements may be entered, line by
line.
(10) The computer must be told to make a permanent record of the entires. This is done by giving

7-14

the command: SAVE. If this is not done, the computer will not recognize the name of the old
file if called for later; the program will have to be entered again.
(11) When the source program is ready to be assembled, the Assembler is called by entering: RUN
MPCASM
(12) If an assembled program is to be simulated, the Simulator may be called by entering: RUN
MPSSIM
(13) If the user wants to change the memory file form, address range, or name of the assembled
program or to link it to another memory file, the Build Virtual Machine program may be called
by entering: RUN MPBVM
(14) Build Virtual Machine can also be used to punch out a tape of the assembled program for
entering the EXORciser or to order ROM from Motorola.
7-1.3

ENTERING A SOURCE PROGRAM

Entry of a typical source program is illustrated in Figure 7 -1.3 -1. It is recommended that the input be
, 'saved" in the host computers permanent files following every few lines of code. This protects against loss due
to a system failure. This is shown in the example by the SAVE command entered following the source
statement numbered 200. Note that the command REP (replace) is used to "save" subsequent statements. This
is a characteristic of the G .E. system.
Figure 7-1.3-2 shows the results of listing a previously entered program. It is assumed that the
system is accessed at a later time after AAA was entered. Note that the file OLD AAA is called, i.e., AAA is
now an "old" file.

7-15

J~EI.I.I

AAA

~:EAD\'

S ....·:S: F 1 1•••1

PEAD\'
t-iAt'1 I TEt'12
OPT t'1Et'1
120 * ADDITION OF TWO MULTIPLE-PRECISION
130 * BINARY-CODED-DECIMAL NUMBERS.

100
11 (I

140 *
150 NB EQU 8

160
170

*
*

1 ::: I)

190
2 I) (I

SPECIFIES 8-BYTE OPERANDS.

BEGIN SUBROUTINE.
0 RG $ 1 (I (I (I

BCD LDA B
LD::-=: ADDP

~~t{B

LOADS DATA ADDRESS.

PEAD\'
21 0 CLC
;:::2 I) nE>::T LDA A

AIte A =·+t·fE!-l, ::<

240
250
260
270
2:=:0

DAA
STA
DE>::
DEC B
pnE NEXT

2'30

PT"~:

:~:OO

START LOOP

NB-1~X

230

END OF LOOP
END OF BCD SUBROUTINE.

E1E
PEAD\'
310 *
320
330
340
350

*
*

BEGIN MAIN PROGRAM ..•...
TEST OF SUBROUTINE BCD.
ORG ~1;11 00
LDS ~~$13F
!t·n T I AL I ZE STCK pt·nR .
LD>:: ~::P
LOA IrS: ADD~:E:S':S: OF P.
ST::< ADDR
.JS~' BCD
nop
BRA +-1
EnD OF MAIn PROGRAM.

.36 (I

370
3::::'0

:3'30
400

Jill::.
READ'"!,
41 (I +
4;~0

430 + ALLOCATE A DATA AREA IN
440 + READ-WRITE MEMORY.
450 ORI:; $0100
460 + (1) FOR THE SUBROUTInE.
47(1 ADDR Rt'1E: 2
4:::0 + (2) FOR THE t'1AIN

P~:.oGRAt'1.

4'3 (I P ra'1E: t·U:
500 C! ~:t'1E: NE:
51 (I F!:ES F.:t1E: t'~E:

520
5:::: 0

E~iD

t'10t-i

.ESl:.
READ')"'

NOTE: System Commands Entered by User are Underlined.
FIGURE 7-1.3-1: Entering the Source Program "AAA"

7-16

OLD AAA
~:EAD'''''

-LIST
1 00
11 (I
120
130
14
15
16
17
1:::
19 I
20
21
22
23
24'250
260
270
280
29
::::0

31
32
33

01 . . . 24.····75

1:::: 1 (lEST

AAA

r'iAt'l I TEt'12
OPT t'1E~1
+ ADDITION OF TWO MULTIPLE-PRECISION
+ BINARY-CODED-DECIMAL NUMBERS.
+

NB EQU 8

SPECIFIES 8-BYTE OPERANDS.

+ BEGIN SUBROUTINE.
ORI:; $1 000
BCD LDA B ~~t{B
LDX ADDR
LOADS DATA ADDRESS.
CLC
NEXT LDA A NB-l,X START LOOP
ADC A 2+NB-1,X
DAA
STA A 3+NB-1,X
DE::-=:
DEC B
BNE NEXT END OF LOOP
RTS
END OF BCD SUBROUTINE.
+
+

+ BEGIN MAIN PROGRAM ..•.•.
+ TEST OF SUBROUTINE BCD.
:;:41)
OF.~G $11 00
35 (I LDS ~~$1 :3F
I t·~ I T I AL I ZE STCK PtiTR.
:360 LD>:: ~~P
LOADS ADDF.~ESS OF P.
:370 ST::·:: AD DR
:;:80 .JSR BCD
::::90

4'00
410
420
430
440
45 (I
460
470
480
49 (I
500
51 0
520
530

t·~op

BF.~A

+-1

END OF MAIN PROGRAM.

+
+ ALLOCATE A DATA AREA IN
+ READ-WRITE MEMORY.
OF.~I:; $ 0 1 00
+ (1) FOR THE SUBROUTINE.
ADDR RI"1E: 2
• (2) FOR THE MAIN PROGRAM.
P F.:1"1B. r'iB
Q F.:MB tiE:
RES F.~MB t'iB
Et-iD
MDt·~

NOTE: System Commands Entered by User are Underlined.

FIGURE 7-1.3-2: listing of the Source Program "AAA"

7-17

ASSEMBLING A SOURCE PROGRAM

7-1.4

Prior to assembly, a source program must have been placed in memory accessible to the Assembler
(see previous section). When the Assembler is called, it will request that a source input file (SI) be specified.
This source input file will be the source program that was previously saved.
If a MEM option was included in the source program, the Assembler will also request that a memory
file (MF) be named. At this time, the user must specify a name for the file that is different from the source input
file name. The machine language code resulting from the assembly will be stored in that file.
After the assembly is completed, the Assembler prints out a listing of the code that was generated.
The OPT (Option) assembly directive may be included in the source program and allows the user to vary the
format of the Assembly Listing. If other options are not specified, the Assembler will automatically select the
fullest format (see the OPT directive in Table 7-1.1-1 for a list of the options). The long format for a
representative line from an Assembly Listing is shown in Figure 7-1.4-1.
A sample Assembly Listing for the program AAA is shown in Figure 7-1.4-2. A number of the
characteristics of source statements and the assembly process are illustrated:
(1) Instruction labels: BCD, NEXT.
(2) Assembler directives: NAM, OPT, EQU, ORO, RMB, END.
(3) Assembler directive labels: NB, ADDR, P, Q, RES.

NOTE: Diagram correct only if no format option specified.

Character
Position

00200

OOFF

CE
12

00F2
13

EP, CALC

LOX
27

#BUFFER
34

Step 1: Sum Odd Data Positions
43

80 max

Lcomment
OPERAND (or Effective Address)

Operator-Instruction or Directive Mnemonic

Label

Value of Operand or Effective Address

OP Code

Instruction Address

Statement Number

FIGURE 7·1.4·1: Fields of Assembly Listing

7·18

15=19EST

01 . . . 24.····75

INC. OWNS AND IS RESPONSIBLE FOR MPCASM
COPYRIGHT 1973 & 1974 BY MOTOROLA INC

MDTOROLA~SPD,

MOTOROLA MPU CROSS ASSEMBLER, RELEASE 1.2
ENTER SI FILENAME
?AAA
ENTER MF FILENAME
?DEF456
DEFAULT MACHINE FILE 06/20/74.
PAGE

ITEM2

00100
00110
00120

t·1At'1
I TEt'12
OPT
~1EM
• ADDITION OF TWO MULTIPLE-PRECISION
* BINARY-CODED-DECIMAL NUMBERS.

OOl:~:O

00140
00150
00160
00170
00180
00190
00200
00210
00220

01/24/75 15:19.00

0008

•

t'~B

EOU

:=:

SPECIFIES :::-E:')"TE OPERANDS:.

*
* BEGIN SUBROUT I tiE.
$1000
1000
DRG
E:
~~tiB
1000 C6 0:3
BCD
LDA
LOADS: DATA ADDF.~ES:S: •
ADDF.:
1002 FE 0100
LD:X:
1005 OC
CLC
100E, A6 07
t"iE::-::T
START LOOP
LDA A t'iE:-l , : -:
002:~:0 100::: A9 OF
2*NB-l
,
:
.
:
ADC A
00240 100A 1':'IIAA
00250 100B A7 17
STA A ~~:*t"iB-l , X
00260 100D 0':'IIE::'~
00270 100E 5A
DEC E:
Et'i II OF LOOP
t'iE:X:T
00280 100F 2E, F5
ENE
F.:TS:
END OF E:CD SUBF.~OUT I tiE.
00290 1011 :~:9
NOTE: System Commands Entered by User are Underlined.
FIGURE 7-1.4-2: Assembly Listing for Sample Program "AAA" (Sheet 1 of 2)

7-19

•
•
•

00:300
00:::: 1 0
00:320

00:3:30
1100
1100
110:3
110E.
00:380 110'3
003'30 110C
00400 110D
00410
00420
004:30
00440
00450 0100
00::::40
00:350
00::::60
00:370

BEGIN MAIN PROGRAM ••••••
• TEST OF SUBROUTINE BCD.
OPt:;
$1100
::~$1 :3F
::::E 01:3F
LDS
INITIALIZE STCK PNTR.
LD::-::
CE 0102
LOAtiS ADDRESS OF P.
:S:T::~
FF 0100
ADDF.~
1000
.JSR
BCD
BD
NDP
02
+-1
20 FII
BF.~A
END OF MAIN PROGRAM.

•

00460

0047(1 0100 0002
0048
004'3 0102 000:::
0050
010A 0008
0051 0112 000:::
0052

• ALLOCATE A DATA AREA IN
• READ-WRITE MEMORY.
$0100
ORG
(1) FOR THE S'-'BF.~OUT I t-iE •
ADDR
R~lB
2
(2) FOR THE talA I t-i PRDGF.~AM •
t-iE:
RME:
P
t-iB
RI"lB
G!
t-iB
F.~ES
~~MB
Et-iD

•
•

:S:'"I't'lBOL TABLE

000::::

010A

BCD
RES

1000
0112

nE::-::T

100E.

ADDP

0100

PROGRA,..1 STOP AT 0
U-SED

20.72 Ut-i I TS
FIGURE 7-1.4-2: Assembly Listing for Sample Program "AAA" (Sheet 2 of 2)

7-20

0102

(4) Comments in comment field and also on lines where an asterisk appeared in the first character
position of the source program.
(5) Instructions without labels, on lines in the source program where two spaces separated the line
number and operation mnemonic.
(6) Operands consisting of an expression to be evaluated by the Assembler: NB-l, 2* NB-1,
3* NB-1, *-1.
(7) Operands indicating immediate addressing: #NB, #$13F, #P, so that NB, which is equal to 8,

is loaded into accumulator B (line 190), $13F, a hexadecimal number, is loaded into the stack
pointer register (line 350), and the address labeled P, rather than its contents, is loaded into the
Index (X) register (line 360).
During the assembly of the source file, the Assembler may detect inconsistencies or deletions in the
usage of some symbols, labels, operation codes or directives that prevent it from continuing. Errors of this type
are printed out on the terminal, and it is up to the user to correct the referenced source statement before
attempting to reassemble. Other errors may be detected by the Assembler, such as undefined or doubly defined
symbols, out-of-range relative addressing or syntax that do not prevent the Assembler from continuing but
cause an incorrect assembly. These errors are identified at the end of the incorrect assembly. A list of typical
error messages that might be printed out are shown in Table 7 -1.4-1. If an error message not included in the list
should be encountered, the user can obtain additional information from the HELP program (see Section 7 -1. 6).
There are many additional errors that the Assembler cannot recognize, and the Assembly Listing
must be checked carefully to see that the addresses, operations and data that have been assembled are accessible
or executable and that the program can run to completion. For instance, note that in the sample program AAA
(Figure 7 -1.4-2), the operand of the instruction on Line 400 is: *-1. This is one of the three uses of the asterisk,
and, in this case, refers to the present value of the program counter. BRA *-1 is an instruction to branch to one
less than the present value of the program counter which causes the program to continue execution at the
preceding instruction located at 110C. Note that this instruction is a NOP and has no effect other than advancing
the program to the next instruction. During an examination of the Assembly Listing or during Simulation, it
would be seen that this is not a very useful pair of instructions; the program would hang up, continuously
repeating these two instructions.
It should be noted that an error-free assembly does not mean the program will perform the desired
function. A good assembly means only that the language of the M6800 system has been used properly.
Significant programs will usually still require some additional debugging.
7-1.5

SIMULATION

The M6800 Simulator is a special program that simulates the logical operation of the MC6800
Microprocessor. It is designed to execute object programs generated by the M6800 Cross-Assembler and is
useful for checking and debugging assembled programs prior to committing them to ROM "firmware".
7 -1.5. 1

Simulator Commands
The Simulator is normally controlled 1 by means of an interactive conversation with the operator via

lIt is also possible to simulate programs in a batch-processing mode. Refer to the M6800 Programming Manual for details.

7-21

8281
281

HAft DIRECTIVE ERROR
MESSAGE:
****ERROR 281
"E~HING:
THE SOURCE PROGRAM DOES HOT START WITH AHA" DIRECTIYE STATE"ENT OR THE HAM DIRECTIYE IS MISSIHG.

8282

282

lA3El OR OPCODE ERROR
MESSAGE:
*.*.ERROR 282
"EAHING:
THE LABEL OR OPCODE SYMBOL DOES HOT BEGIN WITH AN
ALPHABETIC CHARACTER.

9283

283

ST~TE"EHT

MESSAGE:
MEANING:

ERROR
****ERROR 283
THE STATEMENT IS BLANK OR ONLY CONTAINS A LABEL.

9204

284

SYNTAX ERROR
MESSAGE:
* ••• ERROR 284
"EANING:
THE STATE"ENT IS SYNTACTICAllY INCORRECT.

0205
285

LA3EL ERROR
MESSAGE:
****ERROR 285
MEANING:
THE STATEMENT LABEL DOES HOT END WITH A SPACE.

0286
285

REDEFINED SV"BOL
* * * *£ RR0 R 286
"EAHIHG:
THE SYMBOL HAS PREVIOUSLY BEEN DEFINED.
11 E S SAG F. :

9207
287

UNDEFINED OPCODE
•• *.ERROR 287
MEANING:
THE SYMBOL IN THE OPCODE FIELD IS HOT A VALID
OPCODE "NE"OHIC OR DIRECTIVE.
MESSAGE:

8288

288

BRANCH ERROR
MESSAGE:

"EANING:

•• **ERROR 288

THE BRANCH COUNT IS BEVOND THE RELATIYE 8VTE~S
THE ALLOWABLE RANGE IS:
(*+2) - 128 < D < <*+2> + 128
WHERE: * = ADDRESS OF THE FIRST BYTE OF THE
BRANCH INSTRUCTION
n = ADDRESS OF THE DESTINATION OF THE
BRANCH INSTRUCTION.

RANGE.

TABLE 7-1.4-1. Assembler Error Messages (Sheet 1 of 3)

7-22

8289
289

ILLEGAL ADDRESS "ODE
MESSAGE:
****ERROR 289
"EAHIHG:
THE "ODE OF ADDRESSING IS HOT ALLOWED WITH THE
CODE TYPE.

op-

8218
210

BYTE OVERFLOW
MESSAGE:
****ERROR 218
"E~HIHG:
A CONSTANT CONYERTED TO A YALUE GREATER THAN
(DECI"AL).

2~'

8211
211

UNDEFINED SYMBOL
MESSAGE:
****ERROR 211
ME~HIHG:
THE SYMBOL DOES HOT APPEAR IN A LABEL FIELD.

8212

212

DIRECTIVE OPERAND ERROR
MESSAGE:
****ERROR 212
MEANING:
SYNTAX ERROR IN THE OPERAND FIELD OF A DIRECTIYE.

8213
213

EQU DIRECTIVE SYNTAX ERROR
MESSAGE:
****ERROR 213
ME~HING:
THE STRUCTURE OF THE EQU DIRECTIVE IS SYNTACTICALLY INCORRECT OR IT HAS HO LABEL.

8214

214

FC3 DIRECTIVE SYNTAX ERROR
MESSAGE:
****ERROR 214
ME~NING:
THE STRUCTURE OF THE FeB DIRECTIVE IS SVNTACTICALLY INCORRECT.

8215
215

FDa DIRECTIVE SYNTAX ERROR
MESSAGE:
****ERROR 215
MEANING:
THE STRUCTURE OF THE FDB DIRECTIVE IS SYNTACTICALLY INCORRECT.

8216
216

DIRECTIVE OPERAND ERROR
~ESSAGE:
****ERROR 216
MEAHING:
THE DIRECTIVE/S OPERAND FIELD IS IN ERROR.

0217
217

OPT DIRECTIYE ERROR
HESSAGE:
****ERROR 217
MEANING:
THE STRUCTURE OF THE OPT DIRECTIVE IS SYNTACTICALLY INCORRECT OR THE OPTION IS UNDEFINED.
TABLE 7-1.4-1. Assembler Error Messages (Sheet 2 of 3)

7-23

8218
218

ADDRESSI~G

MESSAGE:
MEANING:

ERROR
****ERROR 218
AN ADDRESS WAS GENERATED WHICH LIES OUTSIDE THE
LEGAL MEMORY BOUNDS OF THE VIRTUAL MACHINE FILE.
TO EXTEND THE LAST ADDRESS (LWA) OF THE MACHINE
(HF FILE); RUN THE MPBY" PROGRAM. ENTER "LW LWA"
WHERE LWA IS THE HEW LAST WORD ADDRESS. THE
SYSTEM WILL PROMPT THE USER FOR THE NAME OF THE
MF FILE.

8228
228

PHASING ERROR
MESSAGE:
****ERROR 220
~E~HING:
THE VALUE OF THE P COUNTER DURING PASS 1 AND
PASS 2 FOR THE SAME INSTRUCTION IS DIFFEREHT.

9221
221 - SYKBOL TABLE OVERFLOW
MESSAGE:
****ERROR 221
ME~HING:
THE SYMBOL TABLE HAS OYERFLOWED. THE HEW SYMBOL
WAS NOT STORED AND ALL REFERENCES TO IT WILL BE
FLAGGED AS AN ERROR.
9222
222 - SYNTAX ERROR IN THE SYMBOL
MESSAGE:
****ERROR 222
MEANING:
THE SYMBOL WHICH USED AN OPERAND WAS REDEFINED OR
HAS AN ERROR IN IT'S DEFINITION. THIS ERROR IS ONLY
USED TO SHOW WHERE THE SYMBOL WAS USED.
8223
223 - THE DIRECTIVE CANHOT HAVE A LABEL
MESSAGE:
****ERROR 223
MEANING:
THE DIRECTIYE CANNOT BE LABELED. REMOVE THE LABEL.
0224
224 -

ERRO~

"ESSAGE:
MEANING:

USING THE OPTION DIRECTIVES OTAPE OR ME"ORY

***.ERROR 224 X~XXX
THE OTAPE=FILEHAKE OR MEMORY=FILENAME IS HOT THE
FILENA"E USED ON THE 1ST OCCURRENCE OF THE OPTION.
OR THE OPTION WAS TURH OFF (HOMEMORY) AND A FILENA"E WAS SPECIFIED.
TABLE 7·1.4·1. Assembler Error Messages (Sheet 3 of 3)

7-24

a timesharing terminal. Simulator requests for input may be responded to using any of the following typical
commands:
1. Format Control for Commands and Print-Out

IB2

Set input number base to BINARY

IB8

Set input number base to OCTAL

IB 10 Set input number base to DECIMAL
IB16

Set input number base to HEXADECIMAL

These commands are used to set the format control of the Simulator to the number
base of the user. Thereafter, the user enters commands with this base. There is a choice of binary
(IB2), octal (IB8), decimal (IBI0), or hexadecimal (IBI6).
DB8

Set display number base to OCTAL.

DBI0

Set display number base to DECIMAL.

DB16

Set display number base to HEXADECIMAL.
Notes: (i) The format of the above commands is invariable, and does not depend on
the current input number display base.
(ii) The display base command does not apply to the display of the number of

cycles of execution time, which is always shown as a 7 -digit decimal
number.
These commands select the number base that the simulator will use when it prints out
information for the user. There is a choice of octal (DB8), decimal (DBI0), or hexadecimal
(DB 16). The one exception is the print out of execution time cycles, which is always displayed in
decimal.
SD

IOEPXABCST

This command selects the registers that will be displayed by the D command. It does
not cause them to be displayed. The user may select any or all of the following ten:
IA OC EA PXABCST-

instruction address
Operation mnemonic code
effective address
program counter
index register
accumulator A
accumulator B
condition codes
stack pointer
time

7-25

IA can also be addressed as I, OC as 0, and EA as E as in the command format line
above. The contents of all these registers are printed out by the Simulator as initial status when
the name of the memory file is entered. In addition, the first item of the initial status display is a
two letter code which informs the user of the input and display base being used. This code
consists of the letters, H (hexadecimal), D (decimal), 0 (octal), and B (binary). Binary can be
used as an input base, but not as a display base. The first letter is the input base and the second is
the display base.
Initial status display:
HH

0000

***

0000* 0000 0000

000000

0000

0000000

In the above example, HH means that both the input and display base are
hexadecimal.
HRn
This command causes the Simulator Register Header to be displayed, at intervals of n
lines of print. The header has the same appearance as in the initial status display.
LM
List each command before it is executed. Useful as a check and reminder after a string
of commands has been entered.
NOLM
To not list command before execution. Normally used sometime after an LM
command has been entered when the echo listing is no longer desired.

2. Set Values
SM s ,no ,nl ,n2, . . . . ,nrn
Set memory location s to no, s

1 to nl, s

+ 2 to n2,

.... , s

m to nrn.

This command is used to load specified data into selected memory addresses. By
altering the machine code stored in particular addresses, the program instructions can be changed
or modified to improve the program. The contents of the selected memory addresses can be
checked with the Display Memory (DM) command. SM requires only the lowest memory
address in a continuous sequence. Each data value specified is automatically placed in the next
higher address. These data values are separated by commas.
SR Pnl,Xn2,An3,Bn4,Cns,Sn6
Set registers to the respective values represented by nl, n2, . . ., n6. Register codes
may be in any order and only the registers to be changed need be entered.
This command is used to load specified data into selected registers. It can also be used
to move the Simulator around in the program by resetting the program counter to a different

7-26

instruction and then doing a Trace or Run. After using the Set Register (SR) command, the
contents of those registers can be checked by using the Display D, command.

3. Display Values
DM s,n
Display memory starting at the memory location s and displaying n locations. Numerical
values will be displayed in the display number base selected by the DB command. The
numerical values are followed by ASCII literal interpretations of the 7 -bit codes from
hexadecimal value 20 through 5F.
The DM command displays up to sixteen memory locations per line of print. This is
shown by the following example, for which the input and display bases had been set previously to
hexadecimal (by simulator commands IB16 and DBI6):
?SM 18FO,00, 11 ,22,33,44,55,66,77 ,88,99,OAA,OBB,OCC,ODD,OEE,OFF
?DM 18FO, 10
18FOOO 11 22 33 44 55 6677 88 99 AA BB CC DD EE FF .. "3DU ....
Each line of memory display shows the numerical address of the first memory
location being displayed. This is followed by the numerical coding of the specified number of
successive memory locations. The numerical codes are followed by their corresponding ASCII

literal interpretations. For the ASCII literals, only bit positions through 6 are considered, bit
No.7 being ignored. Literals corresponding to seven bit codes 20 through 5F are printed, all
others are indicated by a period (.). As an example, note that the contents of the first two
locations, 00 and 11, are less than 20 and, hence, cause periods to be printed instead of ASCII
literals. The last 10 locations contain values greater than 5F and also display as periods.
D

Display the registers selected with the SD command. Numerical values will be
displayed in the display number base selected by the DB command.
DL
Display the last instruction previously executed.

4. Program Execution
Tn
.Trace n instructions, printing the selected registers after each instruction is executed.
Rn
Run n instructions without printing, and then print the selected registers.
The trace command traces the execution of successive instructions of the program.
The format of the trace is identical with that of the second line of the display of initial status, as
described above. The run command (Rn) also results in a printed line in the same format, but this
is printed after execution of the specified number of instructions.
7-27

The trace may also include register header lines, in the form described earlier. The
frequency of appearance of the register header line in the trace depends on the value set in by the
Display Register Header command (HRn).
The user may command either Trace mode or Run mode. The trace mode (T) is
selected for a number (n) of instructions specified by the user. The n instructions are then
executed, and the simulator displays the contents of selected registers after the execution of each
instruction. The trace is capable of showing the current status of all of the registers of the
programming model, the address and coding of the current instruction, the source language
mnemonic operator corresponding to the instruction, and the total time of execution in cycles.
The user has complete control of the content of the trace and by using a simulator
command (SD) is able to set the display so as to eliminate unwanted elements.
The Run mode (R), like the Trace, is selected for a number (n) of instructions
specified by the user. The successive instructions are executed without display by the simulator
until n instructions have been executed. The nth instruction is then displayed in the same format
as for the trace.

5. Repetition
RCn
Execute the next command n times. If the command RCn is the last command in a
line, the command which will be repeated is the first command in the next command
line.
A typical application could be for increment or decrement instructions which are part
of a counter subroutine. Repeating the instruction advances the counter.
RLn
Execute the remaining portion of the command line (to the right of the RLn command)
n times. If the command RLn is the last command in a line, it will have no effect. The
RLn command must not be included in the definition of a MACRO command.

6. Memory File Status
SS
Save the simulator status in the memory file. All register settings and selected options
are saved. The MACRO library and current MPU memory pages are not saved.
Useful fOL terminating an incomplete simulation that will be resumed later.
RS
Restores status saved by SS command. The saved status is transferred from the
memory file back into the Simulator registers.

EX
Exit from the simulator after saving the status as for the SS command, and also saving
the MACRO library, and all of memory including the current memory pages. Informs
host computer that present usage of Simulator is complete.

7-28

Numerical Substitution in the Commands

Where applicable, n, no, nl, nz, .... , nrn, and s are replaced by numbers when entering a
simulator command. The number so substituted will be interpreted as octal, decimal, or hexadecimal,
according to the input base set previously by a command IB2, IB8, IBIO, or IBI6.
Hexadecimal Input

When entering a hexadecimal number in a simulator command, the hexadecimal number must begin
with a digit from to 9. If the hexadecimal number would otherwise begin with A, B, C, D, E or F, a leading
zero must be used.

7-1.5.2

Operating the Simulator

After the host computer has been accessed as described in Section 7-1.2 (for the G.E. system), the
Simulator is called by the command RUN MPSSIM followed by a carriage return. Once accessed, the
Simulator will request a source input file. The user responds with the name of the desired memory file as
assigned during assembly of the original source program. The Simulator extracts control information, the
source language, and the machine code from the memory file. It then prints out the initial status of the
microprocessor registers and then requests a command by typing a question mark on the next line. Thereafter,
each time the Simulator prints a question mark, the user may respond by entering a Simulator command, a
Macro command, or a string of commands and/or Macros. A Macro (see Section 7-1.5.3) is itself a string of
Simulator commands which are performed in the order entered each time the Macro name is entered. Any
portion of a program may be simulated by setting the P (program) register to the address of the first instruction
and using the Trace or RUN commands to cause the Simulator to advance through the program.
If a single command is being entered, it is followed by typing a carriage return to put the command
into effect. More than one simulator command may be entered in reply to a simulator request. The multiple
commands are entered on a single line with a period (.) typed between the commands as a separator. The string
of commands is followed by a carriage return which puts the commands into effect in serial order from left to
right. The string of commands entered in a single line must not exceed 70 characters. The simulator will accept
minor variations of format in the entering of commands such as extra spaces inserted in a string of commands in
some instances.
The use of some of the Simulator commands is illustrated in the following examples:
Example I:

Assume that the user wishes to have the simulator perform as follows:
1. Save the simulator status in the memory file.
2. Set the display registers so as to display the program counter, and the accumulators A and B.
3, Display the registers as selected at (2).
4. Trace five instructions.
The commands to carry out this sequence may be entered on a single line, in response to a simulator command
request, as follows:
? SS.SD PAB.D.T5
7-29

Example II:
Assume that a one line command is to be entered to do the following:
1. Set the program counter to hexadecimal 1000, and register A to hexadecimal value AO.
2. Set four memory locations, beginning at hexadecimal address 5000, to the hexadecimal values 12,34,
CD, and EF.
3. Display the four memory locations set by the instruction (2).
4. Display the registers as previously selected.
5. Trace sixteen instructions.
Assuming that the input base (lB) has been set to hexadecimal, the commands required for the above sequence
may be entered on a single line as follows:

? SR PI000, AOAO.SM5000, 12,34,OCD,OEF.DM5000,4.D.TI0
In this example, there are some formatting details that should be noted:
(1) After the SR command, there is a space preceding the first designated register.

(2) There is no space between the register designation and the data value to be entered.
(3) The designated register and its data value is separated by a comma from the next one.
(4) When the data value is a hexadecimal digit greater than 9, a zero must precede it. (Data value
OAO into the A register, Data value OEF into memory address 5003)
(5) SM requires only the lowest memory address in a continuous sequence. Each data value
specified is automatically placed in the next highest address. These data values are separated by
commas.
(6) DM requires the number of memory addresses to be specified.
(D refers to the registers previously designated on the same line (P and A).

7-1.5.3

Macro Commands
Macros are special user defined commands that cause the Simulator to carry out a string of normal

commands. By carefully defining a few macros that include all the repetitious commands, the time and effort of
reentering those commands each time they are required is saved. Instead,only the Macro is entered. The
Macros, once defined, can be saved in a Macro Library in memory for recall during later similar simulations.

Naming a MACRO Command
A Macro command may be named and defined in reply to any of the simulator command requests
(after the initial status display). The format for naming and defining a MACRO is as follows:
? Name [Definition]
The name may consist of from 1 to 4 alphabetic characters. The definition of the Macro command is
enclosed in brackets, followirig the name.

7·30

(Any combination of 1 to 4 letters may be used for the name even if it is identical with one of the
simulator commands. However, in such a case, the Macro takes precedence, so that the simulator command
which it displaces cannot then be used except within the definition of a Macro.)
The simplest type of Macro command consists of a series of constant simulator commands, which
are to be put into effect in the order written. The definition in this case consists of the corresponding string of
simulator commands, with a period (.) as a separator.

Calling a Constant Macro Command
A Macro command is put into effect exactly the same as any of the simulator commands. The name
of the Macro is typed as if it were a simulator command. The names of one or more Macros may be included in a
string of commands entered on a single line, in response to a simulator command request. The Macro names are
separated by periods (.) the same as for basic simulator commands. The Macro, or a string of commands
including one or more Macros, is put into effect by the carriage return. Examples:

Example I:
Assume that the one-line string of commands shown below is frequently required.
?SS.SD PAB.D.RS
To avoid repetitive typing, the Macro" AB" may be defined by typing the following in replay to a
simulator command request:
?AB[SS.SD PAB.D.RS]
The string of commands will be put into effect by calling the Macro AB followed by a carriage
return:
? AB

Example II:
To replace the sequence of simulator commands which could be typed:
? SR PIOOO,AOAO.SMSOOO,12,34,OCD,OEF
A Macro command, which may be named "CD", could be defined by entering as follows:
? CD[SR PIOOO,AOAO.SMSOOO,12,34,OCD,OEF]
Both of these Macros, AB and CD, having once been defined are retained by the Simulator for
further usage.
In some cases, the same Macro could be useful if only the memory addresses, registers, data content
or trace and run cycles requested by it were different. That is, the Macro command remains constant but the
relevant parameters are variable.
There are two ways to do this, called Parameter Substitution, and Text Substitution.

7-31

Parameter Substitution
Example 1:
Consider the sequence of simulator commands entered as follows:
? SM5000,OA2.RI5.D.DM5000,1
A constant Macro, say "EF", could be defined. This might be entered by:
? EF [SM5000,OA2.RI5.D.DM5000,1]
However, this can be replaced by a Macro in which the address and the numerical data can be
substituted at the time that the MACRO is called. To do this, the numbers are replaced by symbols, consisting
of the pound sign (#) followed by a serial number.
In place of the above constant Macro substitute a Macro with two numerical parameters denoted by
# 1 and #2. The Macro would be defined by:
? EF[SM#I,#2.RI5.D.DM#1,l]
The foregoing Macro with not more than two numerical parameters, may be called, in response to a simulator
command request, as follows:
? EF ,5000,OA2
The actual values 5000 and A2 are substituted for the parameters represented by #1 and #2. (This
format assumes that the input base (IB) has been set to hexadecimal.)
The Macro could also be called in a string of commands, as for example by:
? R20. T5.EF,5000,OA2. T5

Example 2:
Another set of Simulator commands might be:

? SM5000,12,34, OCD,OEF.R50.D.DM5000,OC
To provide for substitution of all of the numerical content, this could be replaced by a Macro defined
by:
? GH[SM#1,#2.R#3.D.DM#I,#4]
It should be noted that there are four 'substitutable parameters here. In this case, the Text Substitution mode
must be used to call the Macro since there are more than two parameters.

Text Substitution Validity
In text substitution, the parameters in the Macro represented by #1, #2, etc., are replaced by
specified text when the Macro is called. The text corresponding to each parameter is delineated by the colon (:)
and the semi-colon (;) in the calling command.
More generally, the text corresponding to any parameters may be any string comprising alphanumeric symbols, spaces, and commas, subject to the following rule: when every text has been substituted

7-32

for the corresponding parameter, the result must be identical with a valid constant Macro command, consisting
of a sequence of simulator commands separated by periods.
Accordingly, the text substitution mode allows for substituting commands, as well as numerical
data, whenever a Macro command containing parameters is called.
For the example Macros, GH and EF defined previously, the Text Substitution call is as follows:
? GH:5000: 12,34, OCD,OEF:50:0C
? EF:5000:0A2

The Macro could also be called in a string of commands, as for example by:
? R20. T5.GH:5000: 12,34,OCD,OEF:50:0C;T5

and
? R20.T5.EF:5000:0A2;T5

Text Substitution of Simulator Commands
The general nature of the Text Substitution method requires only that a valid Macro result from the
substitution. For this reason, it is also feasible to replace an undefined symbol in the Macro with one or more
Simulator commands.
Example:
Consider again the Macro command GH and suppose that the user anticipates that he may need to
run or trace variable numbers of instructions between the SM and D commands. A Macro command could be
defined by:
? I1[SM#1,#2.#3.D.DM#1,#4l

The Macro command might be called by entering:
? 11:5000: 12,34,OCD,OEF:R10. T10.R30:0C;T5

The four substitutable parameters are replaced by text, as follows:
#1 - 5000
#2 - 12,34,OCD,OEF
#3 - R10.T10.R30
#4-0C
The semi-colon (;) denotes the close of the Macro command.

Restrictions in Defining a Macro Command
The line of typing including the name, brackets, and definition, must not exceed 70 characters.
When substitution of parameters or text takes place, a virtual Macro command is formed. The virtual
Macro command must not exceed 70 characters.
A Macro command must not be used within the definition of another Macro command.
The simulator command "RLn" must not be included in the definition of a Macro command.

7-33

To Delete a Macro Command
To delete one or more previously defined Macro commands named "Nam 1", "Nam 2", respond
to any simulator command request in the following format:
? MD,Nam I,Nam2, ... ,Nam N
For example, to delete previously defined Macro commands named AB ,EFG, JKLM, respond as
follows:

? MD,AB ,EFG ,JKLM

Macro Library Commands
MS

Save the current Macro library in the memory file.

MR Read in the Macro library from the memory file. (Destroys the current library).
ML List the current Macro library and the number of characters remaining in the library for more Macro
storage.
MD,Naml,Nam2, . . . . ,NamN
Delete the Macro commands named "Naml", "Nam2" ...... "NamN", from the Macro
library.
7 -1. 5.4

Sample Simulated Program
Figure 7-1.5.4-1 illustrates the print out by the Simulator of a sample program (see Section 7-1.4,

Figure 7 -1.4-2 for an Assembly Listing) which adds together two 8 byte binary coded decimal (bcd) numbers.
This program is saved in memory file "DEF456."

Explanation of Sample Simulation
Initital Status
The first two lines of printed output, shown after MF filename DEF456, are the dispiay of the initial
register status of the memory file. The case shown in the tables represents the first simulated execution of the
program "AAA" (see Section 7-1.5.4), following the assembly of the program. The initial status of the
memory file is such that the input and display bases are both hexadecimal, all possible registers will be
displayed, and all registers, including time, are set to zero.

If execution of the program contained in the specified memory file had been simulated previously,
the initial status might differ from that represented, both in format and in content.

Simulator Command Requests
Following the initial status display, the simulator prints the first simulator command request,
indicated by a question mark (?). In response to successive simulator command requests, the typed commands
and definitions described below have been entered.

Repetition of Commands and Input Base Definition
In the example shown, the operator has replied to the first simulator command request with a string
7-34

RUt~

~lPSS

1M
11:42EST

MOTOROLA SPD, INC. OWNS AND IS RESPONSIBLE FOR MPSSIM
COPYRIGHT 1973 & 1974 BY MOTOROLA INC
MOTOROLA MPU SIMULATOR, RELEASE 1.1
ENTER MF F I LEI"~AME
·-;:·DEF45E,
DEFAULT MACHINE FILE 06/20/74.
HH IA
DC
EA
P
X
A E
CST
0000 •••
0000 0000 0000 00 00 000000 0000 0000000
?L~l. IE16
L~1.

IB 16.
?SETP[LM.SD IOEPXABCST.IB16.DB16.HR5.SR Pll00,TO]
SETP[LM.SD IOEPXABCST.IBI6.DB16.HR5.SR Pll00,TO]
01 02, ~~ 1]

?S;:-:; [St'l

S>:: [St'l 01 02, ~~ lJ
?:s:'. . [St'l 01 OA, ~~ 1]
:S:'r' [SM 01 OA,

~~ 1]
?ZSUM[SM 0112,0,0,0,0,0,0,0,0]

ZSUM[SM 0112,0,0,0,0,0,0,0,0]
?DMEM[NDLM.DM 0102,8.DM 010A,8.DM 0112,8.LM]
DMEM[NDLM.DM 0102,8.DM 010A,8.DM 0112,8.LM]
?ML
t'1L.
MACRO LIBRARY LISTING
SETP [LM.SD IDEPXABCST.IBI6.DB16.HR5.SR PltOO,TO]
:S:;:o::
[St'l 01 02, ~~ 1]
S:'....
[St'1 01 OA, ~~ 1]
ZSUM [SM 0112,0,0,0,0,0,0,0,0]
DMEM [NDLM.DM 0102,8.DM 010A,8.DM 0112,8.LM]
1056 REMAINING CHARACTERS
NOTE: User I nput Underlined.
FIGURE 7-1.5-4-1: Simulation of "AAA" (Sheet 1 of 3)

7-35

'?:S:ETP
SETP;
SETP;
SETP;
SETP;
SETP;
SETP;

L~l.

SD
IB
lIB
HR
SR

IDEPXABCST.
16.
16.
5.
Pll00,TO.

SY:92,58,14,70,36,74,1S,52; SM 010A,92,58,14,70,36,74,1S,52.

?1..i!::!!:1
ZSUM; SM 0112,0,0,0,0,0,0,0,0.
?D~lEt'l. D
Dt'1EM; tiDLM.
IC''"'!'
7C"
0102 13 "_II"
'30 24 ~,=_'1_' 0'3 , ...' :31 .1...1.$ ••• 1
5:3 14 70 :~:E, 74 lS 1:""-'
010A q":'
...'e: .::-:: •• 6 •• R
-"~
01120. 00 00 00 00 00 00 00 00
II.
::.::
:S:
C
HH IA
DC
T
P
A B
EA
0000
0000000
0000
0000+1100 0000 00 00 000000
?TOE

.... ....

•••

OE.
.1100
+11 O~:
+1106
+110'3
HH IA
+1000
+1002
+1005
+1006
.1008
HH IA
+100A
+100B
+100D
.100E
+100F

.11 02.11 O:~: 0000 00 00
.1105.1106+0102 00 00
:~~T::'::
.01 01.11 0'3 0102 00 00
.J:S:R .01:3E+1000 0102 00 00
,..,
P
DC
EA
A B
LDA B.1001.1002 0102 00.08
LII:>~
.0101+1005 0102 00 08
CLC .1005+1006 0102 00 08
LIlA A+Ol09.1008 0102,.31 OS
AIle A.Ol11.100A 0102.83 OS
::<
DC
P
A B
EA
IIAA .100A+100B 0102 S"-'
OS
".;.0
STA A+0119+100D 0102 83 OS
DE>:: .100D.100E+010l S3 08
DEC B.100E+100F 0101 83.07
BNE .1010+100E, 0101 8"-::'
"-' 07

LDS
LD:X:

I .....

FIGURE 7-1.5.4-1:

000000+01:3F
000000 013F
000000 013F
000000+01:3D
C
S
000000 013D
000000 013D
000000 013D
000000 013D
OOt-iOVO 013D
S:
C
OONOOO 013D
OOr-iOOO 013D
0000,00 013D
000000 013D
000000 013D

Simulation of "AAA" (Sheet 2 of 3)

7-36

000000:3
0,000006
0000011
00'00020
T
0000022
0000027
0000029
0000034
0000039
T
0000041
0000044
0000048
0000050
0000054

?HR100.NOLM.RC7.R7
HR 1 I) O.
t~OLtt1.

HH IA

100F E:t-iE
10 OF BtiE
10 OF E:t~E
1 I) OF BtiE
100F :BtiE
100F E:tiE
10 OF BtiE
7T5. II~1E~1
.1 011 f;.~T:S:
.110e t-iOP
.11 011 B~:A
.110e tiDP
.110II BRA
0102 1:3 57
010A '32 58
0112 06 16

E ,'·..··',

....
EA
P
A E:
1
006.01
I) 0.9:~:. 06
1010
1010 1006.00FF.83.05
1010 100E.• 00FE.04.04
1010 1 I) 06. 0 OFII.'3S. 0:3
1010 1006.00FC.04.02
1010 1006.00FB.16.01
1010.1011.00FA.06.00
I ....

e
000000
000000
OOOOOC
000000
OOOOOC
HOOOOC
00020C

T
013I1 0000079
01:311 0000104
01 :3 II 0000129
01:~:11 0000154
01~:D 0000179
013I1 0000204
01311 0000229

.013F.lloe OOFA 06 00 a0020e.013F
.110C.l10Il OOFA 06 00 00020C 013F
.110E·110C OOFA 06 00 00020C 013F
.110C.l10Il OOFA 06 00 00020C 013F
.11 OE.11 oe OOFA 06 00 00020e 013F
'30 24 68 09 75 31 .W.$ ••• l
14 70 36 74 18 52 • ::-::. • E.. • ~~
04 95 04 83 93 83 .•••••••

PROGRAM STOP AT 0
USED

:~~

22.11 UNITS
FIGURE 7-1.5.4-1: Simulation of "AAA" (Sheet 3 of 3)

7-37

0000234
0000236
0000240
0000242
0000246

of two simulator commands. These commands instruct the simulator to repeat all commands (LM), and to set
the input base to hexadecimal (lB 16).
Entering the command IB 16 is actually redundant in this example, since as is shown by the initial
status display, the input base was already hexadecimal.
The simulator repeats the IB 16 command, because of the preceding entry of the LM command. All
subsequent commands will be repeated by the simulator until the LM command is cancelled by "NOLM".

Definition of Macro Commands
The user has next defined five Macro commands, to facilitate running the program. The purposes of
the Macro commands are as follows:
SETP -to set the program counter to the beginning of the program, at hexadecimal address 1100; to ensure

SX
SY

format control for repeating commands, displaying all possible registers in the trace, and printing a
header line every five lines of the trace; to ensure that input and display bases are both hexadecimal:
to set initial cycle time to zero.
-to facilitate entry of the first of the two 8-byte bcd numbers which are to be added together; this
number will be placed in memory at consecutive addresses beginning at hexadecimal 0102.
- to facilitate entry of the second of the two 8-byte bcd numbers which are to be added together; this

number will be placed in memory at consecutive addresses beginning at hexadecimal 010A.
ZSUM -to enter zeros in the memory locations where the result of the bcd addition will be stored, beginning
at hexadecimal address 0112.
DMEM - to display the locations in memory where the two bcd numbers which are to be added together are
stored, and where the bcd sum is stored; NOLM and LM are used to eliminate the repetition of
commands during execution of this Macro.

Macro Library Listing

The operator then entered a command (ML) to obtain a listing of the Macro library. The simulator
displays the Macros SETP, SX, SY, ZSUM and DMEM, in a standard format. This is followed by an indication
of the space which remains for MACRO definitions, expressed as the number of remaining characters.

Program and Data Initialization
The operator next initialized the program by calling successively the Macros SETP, SX, SY and
ZSUM. Text substitution is used with the Macros SX and SY to enter the values of the two 8-byte
binary-coded-decimal numbers which are to be added together.
In the example shown, numbers have been entered for carrying out the addition represented by:
1357902468097531
+9258147036741852

Display of Program and Data Initialization
The operator then called the Macro "DMEM" , and entered the display command (D). The Macro

7·38

"DMEM" display the operands of the arithmetic program which have been entered into the memory, and also
displays the memory locations where the result will be stored, and which have been set to zero. The display
command (D), at this point, enables the user to check that the program counter has been set to the start of the
program at hexadecimal address 1100.
Execution of the bcd Addition
The operator then entered a command to trace 14 instructions (TOE). After repeating this command
the simulator has executed and traced 14 instructions in the program, reaching the end of the first pass through
the loop in the subroutine.
The operator then decided to eliminate the header line and the repetition of commands and run the
program to the end of the last pass through the loop in the subroutine, then obtain a display of the registers at the
end of the loop on each pass. This was achieved by the string of commands:
?HRI00.NOLM.RC7.R7
The command HR 100 has set the header interval to a sufficiently high value to eliminate the header in the
remainder of the execution.
To verify that execution of the addition is complete, the user entered a command to trace five
instructions, (T5), and on the same line has called the MACRO command DMEM for displaying the results of
the computations. The trace shows that execution has returned to the main program (RTS) and has entered the
perpetual loop of two instructions (NOP and BRA). The purpose of the perpetual loop is to provide an easily
recognized indication of the completion of the computations but should be removed when the program is
satisfactorily debugged.
The display of memory obtained by calling the Macro "DMEM" shows the results of the 8-byte
binary-coded-decimal addition as follows:
1357902468097531
+9258147036741852
0616049504839383
which is the correct result.
Exit from the Simulator
The user entered a string of two commands to restore the status (RS) and to exit from the simulator
(EX). The RS command has restored the registers to the status after program initialization and before execution
of the program. Following the EX command the computer system has printed information regarding system
status and usage.

7 -1.5.5

Simulation Results

The comparison of an instruction sequence as shown in the Assembly Listing of Figure 7 -1. 4-2, and
as traced by the Simulator, provides some insight into the internal operations of the microprocessor. The
content of the accumulators, index register and stack pointer can be checked before and after each instruction.
The instruction address oegins with the starting point specified in the ORG directive and advances by the
7-39

number of bytes required for each instruction. The program counter indicates where the next instruction is
located. Of particular significance is the condition code register which shows the effect of accumulator
operations, register data transfers and the base status for conditional branching. The T display keeps the count
of expended microprocessor cycles. By subtraction of the beginning from the end count, the duration of
instruction sequences, loops and subroutines can be calculated. The stack pointer and index register should be
checked to make sure they are not overlapping memory reserved for other program instructions or parameters.
Furthermore, when an instruction which manipulates the stack pointer is executed, it should be
observed that the pointer moves accordingly. For example, a JSR instruction causes the stack pointer to be
decremented two addresses. At the end of the subroutine, the RTS instruction increments it by two, thus
restoring it to its former setting. In the same way, the Push Data instruction decrements the pointer by one,
while the Pull Data instruction restores it.
Memory addresses for temporary storage of data may be examined at crucial points in the program to
make sure the expected value has been stored. The PIA control and data registers may be checked the same way,
since they appear to the microprocessor and the Simulator as memory addresses too.
Errors
Errors detected by the Simulator are printed out in the same format as Assembly errors. Typical
Simulator errors are listed in Table 7-1.5.5-1.
7-1.6

HELP
HELP is a special program designed to provide on-line assistance to the users of the Motorola

support software. It can be called to obtain additional information on error messages printed out during
operation of the Assembler, Simulator, or Build Virtual Machine programs. In addition, it includes a Help
Message File that provides up-to-date information on improvements and new developments in the M6800
System. The Message File is organized into groups. Following are the groups, the related message number
range, and the HELP command which places the HELP program in the group mode.
eMD

A
S
H

SYSTEM

---------------------

ERRORS
BUILD YIRTUAl I1ACHINE
ASSEMBLER
SI""UlATOR
HELP
RESERVED

MESSAGE HUMBER RAHGE
-------------------~

8888
1998
2998
3988
4998
5989

TO 8999
TO 1999
TO 2999
TO 3999
TO 4999
TO 9999

To obtain additional information while running the other software programs, HELP is called by
entering: RUN HELP. Then enter the HELP error command, E, followed by the number of the error message in
question. A current listing of the error messages is shown in Table 7-1.6-1. For a listing of all the error
messages, enter E followed by 1 to 999. At the completion of the listing, the user must enter the exit command,
EX, in order to return to other programs.
HELP can be invoked from within! the Simulator and Build Virtual Machine programs by entering a
Help command in response to any command request. An up-to-date list of all the Simulator and Build Virtual
1

Because the Assembler operates in the batch mode, to obtain HELP during assembly, the user must exit from the Assembler and enter
the Help program by RUN HELP.

740

8381
381
8302
392

UNDEFINED SIMULATOR COMMAND
MESSAGE:
****ERROR 301 """""M
"E~HI~G:
AN UNDEFINED SIMULATOR CO""AND WAS EHTERED.
SYNTAX ERROR
MESSAGE:
****ERROR 302 """"M"
"E~NING:
THE STRUCTURE OF THE SIMUALTOR COMMAND IS SYNTACTICALLY INCORRECT.

8383
393

DEFINITION ERROR
MESSAGE:
****ERROR 393 M"M"MM
ME~HIHG:
THE MD SIMULATOR COMMAND CANNOT BE USED IN A MACRO
DEFINITION.

~ACRO

8304
394

8395
395

MACRO NOT IN LIBRARY
MESSAGE:
****ERROR 394 MHMMMM
ME~HING:
THE MACRO TO BE DELETED USING THE MD COMMAND IS
NOT IN THE "ACRO LIBRARY.
MACRO DEfINITION ERROR
MESSAGE:
****ERROR 395 ""MKKK
ME~HIHG:
THE RL SIMULATOR COMMAND CANNOT BE USED IN A MACRO
DEFINITION.

8396

3aS

8307
397

8308
398

REGISTER OVERFLOW
MESSAGE:
****ERROR 306 KMK"""
MEANING:
AH OPERAND IN THE SR COM"AND IS TOO LARGE FOR
THE ASSOCIATED REGISTER.
MACRO LIBRARY OVERFLOW
MESSAGE:
****ERROR 387 """KKK
ME~NIHG:
THERE IS INSUFFICIENT STORAGE IN THE MACRO LIBRARY FOR THE HEW MACRO.
THE MACRO IS NOT STORED.
"ACRO DEFINITION ERROR
MESSAGE:
****ERROR 3es """"""
MEANIHG:
THE "AC~O VARIABLE PARAMETER (IN) IS GREATER THAN
30.

8309
399

CO~"AHD

MESSAGE:
t1E~HIHG:

BUFFER OVERFLOW

"""""M

****ERROR 399
MORE THAH 72 CHARACTERS WERE EHTERED AS A COMMAND
LINE.
THE TOTAL HUKBER OF CHARACTERS IN A COMMAND
LINE INCLUDES THOSE CHARACTERS IN A MACRO DEFIHITION IF THE COMMAND LINE COHTAINS A MACRO CALL.

8319

310

HELP REQUEST
t1ESSAGE:' ****ERROR 310 ""M"""
"E~HIHG:
EHTER "HP ALL sn FOR A COMPLETE LIST OF ALL SIMULATOR COM"ANDS.
TABLE 7-1.5.5-1. Typical Simulator Errors (Sheet 1 of 2)

7-41

8311
311
8312
312

8313
313

SYHTAX ERROR
"ESSAGE:
•••• ERROR 311 """"""
"E~HIHG:
SYNTAX ERROR IN THE SIHULATORIS HELP

CO""A~D.

ILLEGAL HELP "~SSAGE HUMBER
MESSAGE:
•• **ERROR 312 """"""
MEANING:
THE HELP MESSAGE NU"BER WAS NOT FOUND IN THE HELP
MESSAGE FILE.
ADDRESSI~G

MESSAGE:
MEnNING:

ERROR
**.*ERROR 313 """"""
AN ATTEMPT TO STORE BEYOND THE DEFINED "E"ORY
BOUNDS OF THE VIRTUAL "ACHINE FILE WAS MADE.

0314
314 SYNTAX E~ROR IN A SET OR CLEAR BREAK POINT
MESSAGE:
****ERROR 314 """"""
MEANING:
THERE IS A SYNTAX IN THE SIMULATORIS
BPI BSI OR BC CO""AND.
0315
315 ILLEGAL MEMORY ADDRESS
MESSAGE:
****ERROR 315 """""M
MEANI~G:
A BREAK POINT REQUEST TO CLEAR OR SET A BREAK
POINT AT AN ILLEGAL ME"ORY ADDRESS FOR THE UHFFILE. USE -BD- TO DISPLAY BREAK POIHTS SET OR
CLEARED.
8316

POIHT SET AT MEMORY ADDRESS
MESSAGE:
****ERROR 316 """"""
ME~NI~G:
NO BREAK POINT FLAC WAS SET AT THE ME"ORY LOCATION ON THE REQUEST TO CLEAR IT'S FLAG. USE -BDTO DISPLAY BREAK POINTS STILL SET.

316 NO

0317
317

0318
318

~RE~K

:OMMAND HOT TERMINATED WITH A PERIOD
MESSAGE:
****ERROR 317 MHHH""
ME~HING:
THE CO"~AND WAS NOT TERMINATED WITH A PERIOD OR
OR THE COM"AND HAS UNSED PARAMETERS.
SY~TAX

MESSA~~:

MEANIHG:

0319
319

0328
320

IN ·OH OR -OF- CO"MAND
****ERROR 318 MHMMMM
SYNTAX ERROR IN THE ·OH a OR "OF- CO""AND.
A) UNDEFINED CODE, NOT X, A, BI 5, T, BP, "F OR F.
B) OPERAT ION HOT =, < OR ).
C) DEFINING A MACRO FOR THE COMMAND SECTION OF A
"ON- IS ILLEGAL.
D) NO COMMAND FOLLOWS THE CONDITIONS.

~RROR

"OH" COMMAND HOT FOUND IN THE ·OH· LIBRARY
MESSAGE:
**.*ERROR 319 """"""
MEANING:
THE "ON" COMMAND WAS NOT FOUND IN THE -OH R CONDITION LIBRARY.
ILLEGAL INTERRUPT TYPE OR TIME BASE IS ZERO
MESSAGE:
*.**ERROR 328 H""""H
!1EAHIHG:
~IHEN A "IR- CO"HAND IS USED,
THE INTERRUPT TYPE
IS UNDEFINED OR THE DELTA TI"E BASE FOR THt FIRST
INTERRUPT IS ZERO.
TABLE 7-1.5.5-1. Typical Simulator Errors (Sheet 2 of 2)

742

••• 1

111

FILE IS HOT A ·"F· FILE
MESSAGE:
•••• ERROR 891 LU FILENAME:PASSYORD:USER-ID
MEANING:
THE FILE WHOSE FILENAME WAS EHTERED IN RESPONSE TO
THE -EHTER MF FILENAHEM REQUEST IS NOT A VIRTUAL
MACHINE FILE.
THE LOGICAL UNIT IDENTIFIER (LU),
THE FILENAMEI THE PASSWORDI AND THE USER-ID OF THE
FILE CAUSING THE ERROR IS LISTED IN THE ERROR MESSAGE.
THE SYSTEM WILL REPEAT THE REQUEST.

8882
882

MF YERSION NUMBER ERROR
MESSAGE:
••• *ERROR 882 HF FILENAME:PASSWORD:ijSER-ID
ME~NING:
THE -MF" OPENED IH RESPONSE TO THE "EHTER MF FILENAME· REQUEST IS NOT A CURRENT VIRTUAL MACHINE
FILE.
THE FILE CAN BE CONVERTED TO THE CURRENT
VERSION BY RUNNING THE BUILD VIRTUAL MACHINE PROGRAM ("PBY").

8883
803

TERMINATION DUE TO OLD MF YERSION
MESSAGE:
.***SVSTEM ABORT 003
"EANING:
THE PROGRAM WAS ABORTED BECAUSE OF AN "OLD A VIRTUAL
USING THE BUILD VIRTUAL MACHINE PROGRAM ~

- E>nT
FO~t'1AT

FUHCTIOH:

EX
EXIT FRO" THE SIMULATOR AFTER SAVING THE STATUS
AS FOR THE SS CO""AHD, AND ALSO SAVING THE MACRO
LIBRARY . AND ALL OF MEMORY INCLUDING THE CURRENT
MEMORY PAGES.

3011

HR - SET HEADER COUNT
FO;:MAT:
HR COUHT-t
FUNCTION:
PRINT THE REGISTER HEADER LINE EVERV COUHT-l
LINES OF PRINT.
TABLE 7-1.6-2. HELP Listing of Simulator and BVM Commands (Sheet 8 of 13)

7-58

3012
HP - HELP
FORMAT:
FUNCTION:

HP "ESSAGECODE-f[ SWITCH-l]
INFORMATION ABOUT MESSAGECODE-l IS PRINTED.
MESSAGECODE-l HAS ONE OF THE FOLLOWING FORMS:
HNNN
WHERE HHHH IS A NUMBER FROM 1 TO 9999
CORRESPONDING TO ANY HELP MESSAG~
eMD
WHERE CMD IS A SIMULATOR COMMAND
ALL
WHERE THE WORD MAll" REQUESTS THAT
INFORMATION FOR ALL SIMULATOR COMMANDS
BE PRINTED.
SWITCH-l CONTROLS THE AKOUHT OF DETAIL TO BE
PRIHTED AND HAS ONE OF THE FOLLOWING FORMS:
1
PRINT INDEX OF KESSAGE ONLY
T
PRINT TEXT OF "ESSAGE ONLY
B
PRINT BOTH THE IHDEX AND TEXT
IF SWITCH-l IS OMITTED, THEN OPTION I IS USED.
ENTER

'HP

4912

FOR

ItfFOR"ATION ON

THE

SYN-

TAX USED IN THE HELP HESSAGES.
EHTER 'HP ALL I' FOR
COMMANDS.

LIST OF ALL SIMULATOR

3013

IB - SET INPUT BASE
FO~MAT

IS BASE-l

FUNCTIOri:

THE INPUT BASE IS SET TO BINARY,
OR HEXADECIMAL WHEN BASE-l IS 2,
RESPECT I . . . ELy.

EX;~11PlES:

(WHERE

BASE-t

l{L

OR 16)

OCTAL ..

DECl~1Al,

19,

16~

IS 8

THE INPUT BASE IS SET TO OCTAL.
ALL NUMBERS
1N THE COMMANDS WILL 9E IHTERPRE)ED AS OCTAL
UNLESS THERE IS DIFFERENT BASE lMPLIED AS PART
OF THE BASE (IE.J DM 9/$10 WILL DUMP 10 HEXADECIMAL LOCATIONS).
3014

lR - SET IHTERRUPT REQUEST
F o~r1AT:

FUNCTION:

II< FWA-l [, LWA-l 1
NO DOCUMENT AVAILABLE.

3015

LM - LIST "ACRO SWITCH
FORMAT:

Li1

FUHCTIOH:

LIST EACH COMMAND BEFORE IT IS EXECUTED.
EHTER
THE NOl" COMMAND TO INHIBIT THE PRINTING OF EACH
COMMAND.

3816

MD - MACRO DELETE
FORMAT:
t1D MACRO-1( MACRO-2, ... ]
FUNCTIOH:
DELELTE MACROS "ACRO-ll KACRO-2,
MACRO LIBRARY.
I

TABLE 7·1.6·2. HELP Listing of Simulator and BVM Commands (Sheet 9 of 13)

7·59

FROM THE

3917

ML - MACRO LISTING
FO~MAT:
ML
FUNCTION:
A LISTING OF THE "ACRO LIBRARY AND THE AYAILABLE
STORAGE REKAINIHG FOR NEW "ACROS IS PRINTED.
3018
MR -

RESTORE

MACRO

FO~MAT:

FUNCTION:

RESTORE THE MACRO LIBRARY WHICH WAS SAVED BY THE
LAST MS OR EX CO""AND.

3019

MS -

SA~~

MACRO LIBRARY

FO~M~~T:

FU~CTIOH:

THE CURREHT MACRO LIBRARY (AS IT APPEARS WHEN
DISPLAYED WITH THE ML COMMAND) IS SAYED IN THE
MACHINE FILE.

3020

DEi.ETE

) ON'

FORMAT:
FUNCTION:

fX:H1PlES:

COMMANDS

OF [CONDITION-1)

'ON' COHI1AHDS ARE REMOVED FROM THE 'ON' ClNDITION
LIBRARY. IF THE CONDITION-t IS SPECIFIED) THEN
ONLY THAT IOHI COMMAHD IS REMOVED. IF NO CONDITION IS SPECIFIED THEN ALL 'ON' COHDITIOHS ARE
REMOVED. SEE THE ION' COMMAND FOR COHDITION-t'S
FORMAT.

OF
REMOVES ALL 'ON' COMMANDS FROM THE LIBRARY.
OF/A=0FF.
REMOVE ONLY THE 'ON' COMMAND WITH THE CONDITION
A=0FF.

WILL BE DELETED.
3021

OL - LIST

THE

FO~f1AT:

FUHCTIJH:

CONDITION LIBRARY
OL
A LISTING OF THE 'OH' CONDITION LIBRARY AND THE
AVAILASLE STORAGE REMAINING FOR NEW 'OH' CO"MANDS
WILL BE PRINTED.

'ON'

TABLE 7·1.6-2. HELP Listing of Simulator and BVM Commands (Sheet 10 of 13)

7-60

3822
ON - SET AND STORE A 'OH' CONDITION to""AND INTO THE LIBRARY
FOR"AT~
OHICONDITIOH-t,CO""AND-l.
FUNCTION:
WHEN CONDITION-l IS TRUEI THE CURRENT CO""AND
LINE IS TERMINATED. THE COM"AND CO""AHD-l IS THEN
EXECUTED. THE ~ L"~ CO""AND SHOULD BE ON SO THE
COMMANDS ARE LISTED BEFORE THEV ARE EXECUTED.
CONDITION FOR"AT: CODE-l [OPERATIOH-l YAULE-l]
WHERE CODE-l IS ANY OF THE FOLLOWING REGISTER
CODES:
X - INDEX RECISTER
A - ACCU"ULATOR A
B - ACCUnULATOR B
5 - STACK POINTER
T - TIME
OR FAUL T CODES:
Sf - BREAK POIHT FAULT
MF - MEMORY FAULT
F - ALL OTHER FRULTS
OPERATIOH-l IS OPTIONAL AND "AY BE ANY OF THE
FOLLOWING LOGIC$L OPERTIOHS:
= IF THE CODE EQUALS THE YAULE THE COMIllOM IS
TRUE AND THE CO""AND IS EXECUTED.
< IF THE CODE IS LESS THAN THE YAULE THE CONDITION IS TRUE AND THE COM"AHD IS EXECUTED.
> IF THE CODE IS GREATER THAN THE YAULE THE CONDITION 15 TRUE AND THE CO""AHD IS EXECUTED.
VALUE-l IS THE PARAMETER WHICH IS COMPARED TO
CODE-l AND IS INCLUDED IN THE CONDITION IF AND
ONLY IF OPERATION-l IS INCLUDED.

EXRMPLES:

COMMAND-l IS ANY CO""AHD OR "ARCO WITH OR WITHOUT
PARAMETERS. ONLY ONE CO"MAND CAN BE ENTERED. THE
FIRST PERIOD TER"INATES THE CO""AND LINE.
ONLY ONE REGISTER 'OH' COMMAND MAY BE ENTERED AT
A T II1E, BUT MUL Tl PLE FAUL T5 I1AY BE TESTED.
ON, A)0F21 SA", 1,2.
ON THE A ACCU"ULATOR GREATER THAN SF2 (HEX) THE
MACRO CO""AHD ISAMJ AN IT/S PARAMETERS WILL BE
EXECUTED. (THE TRACE OR RUN WILL BE STOPPED)
ON, BP=1081 D", 188,5.
WHEN A BREAK POINT OCCURS AT LOCATION 188, THE
TENTS OF ME"ORY LOCATIONS 10e THRU 184 WILL BE
DISPLAYED. THE TRACE OR RUN WILL BE STOPPED.
ON BP D11, 1 88 5
WHEN ANY BREAK POINT OCCURS, THE CONTENTS OF "EMORY LOCATIONS tee THRU 184 WILL BE DISPLAVED. THE
SIMULATOR WILL REQUEST A COM"AHD.
I

3923
PF -

SI~ULATE

FORMAT:
FUNCTION:

POWER FAIL
f'F
SI.I'IULATES POWER FAIL BV PUSHING THE REGISTERS
O'Nro THE~T,ACK AND LOAD INC THE POWER FAI L VECTOR
(LAST WORD ADDRESS-3) INTO THE P REGISTER.

TABLE 7·1.6·2. HELP Listing of Simulator and BVM Commands (Sheet 11 of 13)

7·61

3124

PI - PRINT INTERRUPT REQUESTS WHEN THEY OCCUR
FORMAT:
PI [,Ll
FUHCTIOH:
NO DOCU"ENT AYAILABLE.
3025

PO - SI"ULATE POWER ON
FORHAT:
PO
FUNCTION:
SI"ULATES THE POWER ON BY LOADING THE POWER ON
VECTOR (LAST WORD ADDRESS-i) INTO THE P REGISTER
AND LOADING RANDO" INFOR"ATION INTO THE OTHER
REGISTERS.
3826
R - RUN
FO~HAT:
R COUHT-l
FUNCTION:
RUN COUHT-t INSTRUCTIONS WITHOUT PRINTING, AND
THEN PRINT THE REGISTERS SELECTED BY THE SR COMMAND.
THE IHPUT BASE OF COUHT-l IS SET BY THE
IS COMMAND.
3927
RC - REPEAT CO""AND
FORMAT:
RC COUHT-1
FUNCTION:
THE NEXT COMMAND IS EXECUTED COUHT-l TI"ES.
IF
THE RC CO"MAND IS THE LAST COHMAND IN A LINE,
THEN THE FIRST COMMAND IN THE NEXT LINE WILL BE
REPEATED COUNT-l TI"ES.
3028
RL - REPEAT LINE
FORMAT:
Rl COUHT-l
FUNCTION:
THE REMAINIHG PORTION OF THE COMMAND LINE (TO
THE RIGHT OF THE RL COMMAND) IS EXECUTED COUHT-l
THE RL COMMAND WILL HAVE NO EFFECT IF IT
TIMES.
IS THE LAST CO""AND IN THE LINE.
3029
RS - RESTORE SIMULATOR STATUS
FORMAT:
RS
FUNCTION:
RESTORE THE SIMULATOR STATUS SAVED WITH THE SS
CO""AHD.
3830

SD - SELECT DISPLAY REGISTERS
FORMAT:
SD REGISTER-l[REGISTER-2 ... ]
FUNCTION:
REGISTERS REGISTER-1, REGISTER~2, .. , ARE SELECTED TO 8E DISPLAYED WHEN THE D, BLI R, AND T COM"ANDS ARE EXECUTED. REGISTER-l, REGISTER-2, ...
CAN BE ANY OF THE FOLLOWING ONE CHARACTER CODES:
I - INSTRUCTIOH ADDRESS
o - OPERATOR ""E"OMIC CODE
E - EFFECTIYE ADDRESS
P - PROGRA" COUNTER
X - INDEX REGISTER
A - ACCU"ULATOR A
B - ACCU"ULATOR B
C - CONDITION CODES
S - STACK POINTER
T - Tl"£
TABLE 7-1.6·2. HELP Listing of Simulator and BVM Commands (Sheet 12'of 13)

7-62

3031
SM - SET MEMORY
FO~MAT:

SM FWA-l VALUE-l[, YALUE-2, ... ]

FUNCTION:

LOCATION FWA-t IS SET TO VALUE-II
TION IS SET TO VALUE-21 ETC.

EX~MPlES:

SM 1 e,l
THE CONTENTS OF LOCATION 10 IS SET TO 1.

THE HEXT LOCA-

20,1/2,3,4.,5,6,7,8

THE CONTENTS OF LOCATIONS 28 THROUGH 27 ARE SET
TO 1 THROUGH 8.
3032
SR

SET REGISTER
FORMAT:
SR RECISTER-l VALUE-l[,RECISTER-2 VALUE-2, ... 1
FUHCTION:
THE REGISTERS IN THE LIST ARE SET TO THEIR RESPECTIVE VALUES. REGISTER-I, REGISTER-2, ... CAN
BE ANY OF THE FOLLOWING ONE CHARACTER CODES:
P - PROGRAM COUNTER
X - INDEX REGISTER
A - ACCUMULATOR A
B - ACCUMULATOR B
C - CONDITION CODES
S - STACK POINTER
T - TIME

3033

SS -

SA~E

SIMULATOR STATUS

FO~MAT:

FUNCTION:

SAVE THE SIMULATOR STATUS IN THE MEMORY FILE.
ALL REGISTER SETTINGS AND SELECTED OPTIONS ARE
SAYED.
THE "ACRO LIBRARY AND CURRENT "PU "EMORY PAGES ARE HOT SAVED.

3034

T8 - TRACE BRANCHES
FO~f1AT:
TB [COUNT-11
FUHCATIOH: RUN COUHT-l INSTRUCTIONS AND PRINT THE SELECTED
REGISTERS AFTER EYERY BRANCH, J"P, JSR, BSR, RTI,
RTS, OR SUI INSTRUCTION IS EXECUTED. IF COUHT-l
IS O"ITTED ONLY ONE IHSTRUCTOH IS EXECUTED. SEE
CO" "A NDS S DAN D DB FOR SELEe TI HG THE REG 1ST ER.S'
DISPLAYED AND THE DISPLAY BASE
E X A t1 P LE S :

TB 7

RUN 7 INSTRUCTIONS AND TRACE ANY BRANCHES FOUND
(PRINT THE SELECTED REGISTERS).
3835

- TRACE INSTRUCTION EXECUTIOH
FORMAT:
T COUNT-l
FUNCTION:
COUNT-l INSTRUCTIONS ARE TRACED.
THE REGISTERS
THE EXECUTION OF EACH INSTRUCTION.
TABLE 7-1.6-2. HELP Listing of Simulator and BVM Commands (Sheet 13 of 13)

7-63

4 •••

HELP DIRECTORY
FOR "ORE IHFOR"ATION CONCERNING A CIVEN SUBJECT ENTER THE
SUBJECT'S INDEX FOLLOWED BY A CARRIAGE RETURN.
INDEX
SUBJECT
4811
HELP CO""AHDS
4812
SYNTAX HOTATION CONYENTION
MESSAGE FILE
4813
4811

HELP COM"AHDS
GENERAL: THE HELP SYSTE" OPERATES ON A "ESSAGE FILE.
THE "ESSAGE
FIlE CONSISTS OF ENGLISH TYPE STATEMENTS DESIGNED TO ASSIST
THE USER WITH I'IOTOROLA'S "PU SOFTWARE.
THERE IS AN INDEX
AND A TEXT PART TO EACH "ESSAGE.
MESSAGE CREATION DATES AHD
MESSAGE HUHBERS ARE ASSIGNED TO THE "ESSAGES.
THE MESSAGES
ARE FURTHER ORGANIZED INTO SYSTEM GROUPS.
THERE ARE INDIVIDUAL "ESSAGE GROUPS FOR ERRORS, FOR THE ASSE"BlERI
BUILD YIRTUAL MACHINE, SI"ULATOR, AND HELP SYSTEMS.
A USER
MAY ACCESS THE MESSAGES BY SPEC~FYIHG A "ESSAGE HUMBER, A
RANGE OF "ESSAGE NU"BERS, A RANGE OF CREATION DATES, OR THE
ENTIRE "ESSAGE FILE.
A "ODE CAN BE ENTERED WHERE THE RAHGEOF-DATES AND PRINT-ALL-MESSAGES COMMANDS APPLY ONLY TO THE
SELECTED GROUP (ERRORS, ASSEMBLER, BUILD VITUAL, SIMULATOR,
OR HELP GROUPS).
THREE TOGGLE COMMANDS SELECT/DESELECT THE
PRIHTIHG OF THE "ESSAGE HUI'IBER-CREATIOH DATE, INDEX, AND
TEXT PORTIONS OF EACH MESSAGE.
PRINT MESSAGE COMMANDS
COM"AHD:
FUNCTION:

NU"BER-l
PRINT MESSAGE NU"BER-l

COMMAND:
FUNCTION:

NU"BER-I, NU"BER-2, NU"BER-31 ...
PRINT MESSAGES NUMBER-I, HUt18ER-2, NUt1BER-3 ...

COMMAND:
FUNCTION:

HUMBER-l TO HU"BER-2
PRINT ALL MESSAGES FRO" "ESSAGE NUMBER
TO "ESSAGE HU"BER HUI'IBER-2.

COM"AHD:
FUNCTION:

DATE-l
PRINT ALL "ESSAGES WHICH WERE ENTERED (CREATED)
FROM DATE-l UNTIL TODAVJS DATE. DATES ARE
ENTERED IN THE FOR"AT: "M/DD/VY WHERE "M IS THE
"OHTH., DD IS THE DAY AND YY I S THE YEAR.

NU~BER-l

FORMAT:
FUNCTION:

DATE-l TO DATE-Z
PRINT ALL MESSAGES WHICH WERE ENTERED (CREATED)
FROM DATE-l TO DATE-Z.

COH"AHD:
FUNCTION:

ALL
PRINT EVERY I'IESSAGE IN THE MESSAGE FILE OR EYERY
CO""AHD WAS PREVIOUSLY EXECUTED.
TABLE 7·1.6·3. HELP Messages (Sheet 1 of 3)

7·64

SELECT GROUP CO""AHDS
CO~"AND

FUNCTION:

SELECT THE ASSE"BLERIS "ESSAGE GROUP,

CO~"AND:

FUNCTION:

SELECT THE BUILD VIRTUAL "ESSAGFIS GROUP.

COt1"AND:

FUNCTION:

SELECT THE ERROR'S MESSAGE GROUP.

COM"AND:

FUNCTION:

SELECT THE HELP SYSTEM1S "ESSAGE GROUP.

COi1"AND:

FUNCTION:

SELECT THE SIMULATOR'S MESSAGE GROUP.

COi1"AND:

FUNCTION:

TOGGLE THE PRINT INDEX SWITCH (ON/OFF)

COt1"AHD:

FUNCTION:

TOGGLE THE PRINT MESSAGE HUMBER

COi1"AND:
FUNCTION:

S~ITCH

(ON/OFF)

TOGGLE THE PRINT TEXT SWITCH (ON/OFF)

COMMAND:

FUNCTION:

TOGGLE THE PAGING SWITCH (ON/OFF)
THE HELP MESSAGE WILL BE PRINTED ON 65 LINES PER
PAGE. (53 LINES OF TEXT),

CO""AND:
FUNCTION:

EX
EXIT THE HELP SYSTE".

NOTES:

"ULTIPLE CO""ANDS CAN BE ENTERED ON A SINGLE LINE BY

SEPERATIHG THE CO""AHDS WITH A SPACE.
2.

A SI"ILAR HELP STRUCTURE IS CURRENTLY AVAILABLE IN
THE BUILD VIRTUAL "ACHINE AND SIMMULATOR SYSTEMS.
USER INSTRUCTIOHS FOR THESE HELP SYSTEMS ARE PROYIDED
IN THE' RESPECTIVE SYSTEM.
TABLE 7·1.6-3. HELP Messages (Sheet 2 of 3)

7-65

4012

SYNTAX

HOT~TION

GENERAL

CONVENTION

- BUILD VIRTUAL AND SIMULATOR COMMANDS CONSIST
OF A COMMAND CODE FOLLOWEDJ

USUALLY B'( ONE

O~:

MORE OPERANDS.
OPERANDS PROVIDE THE SPECIFIC
INFORMATION FOR THE COMMAND TO PERFORM THE
REQUESTED OPERATION.
THE FOLLOWING SET OC SYMBOLS IS USED TO DEFINE THE FORMAT OF EACH COMMAND, BUT THEY SHOULD NEVER BE ENTERED AS PART
Of THE COMMAND.
HYPHEtt
[] BRACKETS
ELLIPSIS
COMMANDS - BUILD VIRTUAL AND SIMULATOR COMMANDS ARE TWO
LETTER MNEMONIC CODES.
MACRO COMMANDS (USER
DEFINED COMMANDS) CONSIST OF ONE TO FOUR LETTER
CODES.
A COMPLETE LIST OF THE SYSTEM COM~ANDS
IS PRIHTED WHEN THE JHP AL I COMMAND IS ENTERED
DURING A BUILD VIRTUAL OR SIMULA~OR SESSION
A
LIST Of ALL MACRO COMMANDS IS PRINTED WHEN THE 'ML
COt1MAHD IS ENTERED.
I

OPERANDS - OPERANDS AR£ IDENTIFIED BY THE HYPHEN.
A~
OPERAND WILL CONSIST OF A SYMBOLIC NAME FJLLOWED
BY THE HYPHEN WHICH IS FOLLOijED BY A NUMBER.
A
USER SUPPLIED VALUE IS SUBSTITUTED FOR TH~ OPERAND
IN THE COMMAND LINE.
THE HYPHEN AND THE NUMBER
APPEHD£D TO EACH SYMBOLIC NAME IS USED TO DIFFERENTIATE AMOHG THE POSSIBLE MULTIPLE OCCURRENCES OF
A GIVEN OPERAND IN A COMMAND DEFINITION.
HYPHENS

- HYPHENS IDEHTIFY AN OPERAND IN THE STATEMENT DEFINITION.
THEY ARE NOT ENTERED IN THE ACTUAL COMMAN D~

BRACKETS - BRACKETS IMPLY OPTIONAL INPUT.
EVERTHIHG WITHIN
A MATCHED PAIR OF BRACKETS IS OPTION~L AND MAY BE
OMITTED.
THE BRACKETS ARE NOT INCLUDED IN THE

COMMAND LINE.
HOTE:

THE USE OF THE BRACKETS IN THE DEFINITION OF

CO""AHD SYNTAX AND FORMAT IS NOT TO BE CONFUSED WITH THEIR USE IN MA eRO DEFINITIONS.
ELLIPSIS - AN ELLIPSIS INDICATES THAT THE PRECEDING ITEM OR
GROUPS OF ITEMS MAY BE REPEATED MORE THAN ONCE
IN SUCCESSION.
TABLE 7-1.6-3. HELP Messages (Sheet 3 of 3)

7-66

As the result of assembly, the original source program was converted into numerical machine
language acceptable to the microprocessor. If the Assembler option "Memory" was chosen, the entire
assembled program was saved by the timeshare computer and may now be used to create an output tape. This
tape will not contain any of the source language, comments or Assembler directives provided by the Assembler
listing. It will, however, contain all of the machine language instructions, addresses and data specified by the
source program.
To create the output tape, the first step is to select and reformat the appropriate memory files. This is
accomplished by using the Build Virtual Machine program on the timeshare service. The resulting
reconfigured file is given a new name and saved. The next, and final step, is performed by requesting the
timeshare computer to list the new file on a terminal that has the ability to punch or record a tape. The required
B VM commands for generating the tape are repeated as Table 7-1.7-1 for review.
As an example of their use, the sequence for generating a tape using the Texas Instruments "Silent
700" terminal will be described.
(1) Access the host computer as described in Section 7-1.2.

(2) In response to the query "Type Old or New" , type "OLD".
(3) In response to the query "File Name", type the name of the present memory file.
(4) Call the Build Virtual Machine program by typing "RUN MPBVM."
(5) MPBVM answers with a message and then a question mark.
(6) Enter "MF XYZ", where "XYZ" is the name of the memory file.
(7) In response to the next question mark, type "OM NEW (FA ,LA) " where "NEW" is the name

selected for a new memory file to be configured by B VM. "FA" means the first address in
memory of the user's program, and "LA" means the last address. These addresses are entered
in hexadecimal notation.
(8) When B VM again responds with a question mark, it means the new reconfigured file has been
created.
(9) Next type "EX". This command causes the new file to be saved and then exits the BVM
program.
(10) At this time, the terminal should be prepared for either printing or recording a tape of the new
file.
(11) For the" SILENT 700" , a tape cassette is inserted, rewound and loaded. The Record control is
placed on-line, tape format control set to line, and keyboard and printer turned on if a
printed-out check listing of the tape is desired.
(12) The user types "OLD NEW" where "NEW" is the name of the file that was created in Step 8.
(13) When the terminal prints "ready", type "LIST N H". This command will cause the file to be
listed without a header when a carriage retutn is typed.

7-67

MF - MACHINE FILE
FORMAT:
MF FILENAME-l
FUNCTION: THE MF COMMAND LOADS FILE FILENAME-l INTO A WORK
AREA. THE CC, CF, DM, 1M, LW, ML, MO, OM, RF,
:s:t1, TI, AtiD U~l COMMANIIS ALL ~:EQU I RE A MF FILE
TO BE LOADED PR
SOURCE
EXAMPLES:

MF MEMORY
THE ,..lACH I tiE FILE "MEMOR')"'" I S I IIENT I F I ED AS THE
MF FI~E.
"
OM - OUTPUT MEMORY
FORMAT:
OM FILENAME-l(FWA-l,LWA-l[ ,RFWA-l])
[(FWA-2,LWA-2[ ,RFWA-2]) ••• ]
FUNCTION: OUTPUTS THE SPECIFIED REGIONS OF MEMORY FROM THE
"r'lF" FILE INTO FILE FILENAME-I. FIJJA-l 1:5: THE
FIRST WORD ADDRESS AND LWA-l IS THE LAST WORD
ADDRESS OF THE FIRST REGION. RFWA-l IS THE ROM
MEMORY FIRST WORD ADDRESS. IF PRESENT, MEMORY
IS RELOCATED TO THIS STARTING ADDRESS IN THE ROM
OUTPUT F.ILE.
ROM PAPER TAPE FORMAT
BYTE 1 - RECORD TYPE
SO - HEADER RECORD
SI - DATA RECORD
S9 - END OF FILE RECORD
BYTE 2 - RECORD LENGTH IN BYTES (DOES NOT
ItiCLUDE BYTE 1)
BYTE 3 - UPPER BYTE OF MEMORY ADDRESS
BYTE 4 - LOWER BYTE OF MEMORY ADDRESS
LA:5:T
BYTE - CHECKSUM OF BYTES. THE CHECKSUM +
THE SUM OF BYTES = 255 (MODULO 256).
ALL BYTES BETWEEN BYTE 4 AND THE
CHECKSUM BYTE ARE DATA BYTES. THE
MEMORY ADDRESS OF THE FIRST DATA
BYTE IS IN BYTES 3 AND 4. SUCCESSIVE
DATA BYTES HAVE SUCCESSIVE MEMORY
ADD~:E:S:SES .
EXAMPLES:

OM TOM(O,OFF)
MEMORY IS OUTPUT IN ROM PAPER TAPE FORMAT INTO
FILE "Tor'l". THE F.~EG I ON OF MEMOR~"' OUTPUT 1:5:
LOCATIONS 0 THROUGH FF.
OM DICK(100,lFF,2000)
THE ADDRESSES FOR THE REGION OF MEMORY FROM
TIONS 100 THROUGH IFF ARE REASSIGNED TO LOCATIONS
2000 THROUGH 20FF BEFORE BEING OUTPUT INTO ROM
FILE "DICK".
OM HARRY(0,2FF)(300,4FF,600)
TWO REGIONS OF MEMORY ARE OUPUT TO ROM FILE
HAF.: F::'r'
ADDRESS:ES FOR THE S:ECOt"iII, F.:EG I Ot., AF.~E
REASSIGNED TO LOCATIONS 600 THROUGH 7FF.
II

•

TABLE 7-1.7-1: BVM "Machine File" and "Output Memory" Commands

7-68

(14) The terminal Record button is pressed and a carriage return is typed on the Keyboard.
(15) The program machine code will now be recorded on the tape. Simultaneously, if the printer is
turned on, it is listed line by line on the terminal.
The resulting tape is suitably formatted either for ordering ROMs or for entry into an EXORciser for
further debug and checkout with the system peripherals.
7-2

THE EXORCISER

The EXORciser (Figure 7-2-1) is a flexible test instrument based on actual M6800 hardware
devices. Because of this it can be used as an extension of the system prototype for evaluating and improving
hardware/software compatibility. It includes built-in diagnostic and utility programs that can be used to debug
the prototype system.
In contrast to the Simulator, which is a software program, the EXORciser is primarily hardware.
Programs under development can be run with the actual system peripheral hardware under real time conditions.
This allows both the software and hardware to be modified as required to improve system operation.
A typical EXORciser configuration is shown in block diagram form in Figure 7-2-2.

FIGURE 7-2-1: The EXORciser

7-69

-Debug
System

Debug
Module

----

......

Baud
Rate
Module

-..

-f---

l
MPU
Module

2, VMA, R/W

I/O
Module
32 Input/
Output Lines

FIGURE 7-2-2: Typical EXORciser tm System Block Diagram

7-70

7-2.1

HARDWARE COMPONENTS

The EXORciser chassis fits conveniently on a table top or in a rack. Communication with the user is
through a separate data terminal keyboard and printer. The EXORciser controls are on its front panel. The
microprocessor, memory, input/output interface, and other additional system elements are contained on
plug-in boards which connect to the system busses on the backplane when the boards are inserted.
The basic EXORciser contains three functional modules. Two of these are mounted on separate
plug-in boards. They are:
(1) Microprocessor Module
(2) Debug Module
The third, contained in the housing, is the Baud Rate Module which interfaces to the communication terminal.
In addition to the housing, control panel, card cage, and the two modules mentioned above, the
EXORciser also has a power supply with reserve for up to 14 plug-in boards. This means there are 12 slots
available for additional boards to implement the system configuration, since the EXORciser control nucleus
only occupies two.

7-2. 1. 1

Hardware Specifications
The basic M6800SDT EXORciser Assembly consists of:

1. Equipment Housing: (Includes Chassis, Power Supply, Card Cage for 14 cards, and Band Rate
Module.)

Chassis
Size: Tabletop:
Rackmount:
Weight:

7" X 17%" X 19%."
7" x 17" X 19"
45 lbs. maximum

7-71

Module Compartment
Front Panel Controls:

Rear Control

Power Supply
AC Power Requirements:
DC Power Supplies:

Operating Environment:
Indicators (Front Panel):

Accommodates fourteen 5%" X 9%" modules
ON/OFF switch
ABORT pushbutton switch
RESTART pushbutton switch
Baud Rate Switch
(110-9600 Baud) 8 pos.

60 Hz, 120 ± 10% VAC, 300 Watts
+5 VDC @ 15A
+ 12 VDC @ 2.5A
-12 VDC @ lA
O°C to 55°C
RUN, ON/OFF, and Battery

Baud Rate Module
• Communications Clock Circuit
• Twelve switch selectable baud rates from 110 to 9600
• TTY (20 milliamp) and/or RS232C

2. Microprocessor Module
• Complete microprocessor (MC6800)
• System crystal clock (1 MHz or external osc.)
•
•
•
•
•
•
•

8-Bit data word
Bi-directional data bus
16-bit address bus
72 Instructions - variable length
Seven addressing modes
Variable length stack
Real time interrupt capability

• Restart capability
• Non-Maskable interrupt
• Six internal registers - two accumulators, index register, program counter, stack pointer, condition
code register
• 2/-Lsec instruction cycle (1 MHz clock)
• Memory ready circuit for slow memories
This Card includes the MPU, and the necessary peripheral circuitry to provide the clock,
powerfail/Restart and DMA functions. The clock circuit generates two phase signals for use by the MPU and
the rest of the system. All Address, data, and control lines are equipped with bus drivers and brought out to the
connector.
The DMA circuitry is utilized to transfer data to or from other devices at high speed and allows the
use of memory units that operate at any speed up to the 1 MHz maximum.
7-72

3. DEBUG Module
Hardware Features
•
•
•
•

Stop-on-address comparison circuit
Provision for executing one instruction at a time
ABORT and RESTART pushbutton switches
Address selectable scope trigger

Programmed Features (EXbug)
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Load (reads tape into RAM)
Verify (compare tape with memory)
Punch (outputs memory contents on tape)
Print (prints memory contents on terminal)
Search (searches tape for desired object program)
Examine and/or change memory
Set/reset breakpoints
Set breakpoint loop count
Display/change registers
Trace n instructions
Trace to address
Search memory for bit pattern
Calculate offset for branch instructions
Hex-octal-decimal conversions

4. Table Top Cover Kit or Rack Mounting Kit
The table top version is designated as M6800SDT -T(O) and the Rack mounted version is designated as
M6800SDT -R(O)
Optional Items Include:
1. I/O Module (PIA's sold separately)
2. Static RAM Module (2K X 8)
3. Universal Wirewrap Module
4. Extender Module
5. Rack Mounting Kit
6. Table Top Cover Kit

(Spec.
(Spec.
(Spec.
(Spec.
(Spec.
(Spec.

1810-103)
1810-102)
1810-105)
1810-104)
1810-106)
1810-108)

Input/Output Module (optional)
•
•
•
•
•
•
•
•

Four 8-bit peripheral data busses (TTL compatible)
Each buss programmable for any input/output combination
Wirewrap sockets for special interface circuits
Eight individually controlled interrupt input lines - four usable as peripheral control lines
Handshake control logic for input/output peripheral operation
High impedance three-state and direct Darlington transistor drive peripheral lines
Program controlled interrupt and interrupt mask capability
Address select logic switchable to any memory location.
7-73

Static RAM Module (optional)
• 2K

8 random access memory using 1K

1 RAMs

• Address select logic for each 1K block assignment
• Expandable to 65K
• RAM/ROM control per 1K

8 block of memory

• +5 VDC (only) operation
• No clocks required
• Compatible with Microprocessor Module
• 1JLsec cycle time
• Interfaced via bus driver/receiver

Universal Wirewrap Module
• Plug-in board to accommodate integrated circuit sockets
• Wirewrap pins for simple breadboarding of prototype designs

Extender Module
• Plug-in board to extend another board for easy access to components.
7-2.2

SOFTWARE COMPONENTS

7-2.2.1

EXORciser Control

The EXORciser is controlled by EXbug, a diagnostic program which resides in 3072 bytes of ROM
on the Debug board. This board also includes 256 bytes of RAM which the EXbug program uses to store
interrupt addresses and variable parameters.
EXbug never has to be loaded into the EXORciser since it is permanently stored in ROM. The user's
target program, however, must be loaded into the EXORciser's memory. EXbug performs this function along
with several related ones.
After the tape holding the user's program (generated by the B VM program on the time share
terminal), has been placed in position, EXbug is commanded to Search. When it locates the beginning of the
program, it prints out an identification header. EXbug is then commanded to Load. This operation transfers the
target program from tape into EXORciser memory. At this time, it is advisable to verify that the machine code
of the tape has been corrected stored in memory. To do this, the tape is rewound to the beginning of the
program, and EXbug is given the command, VERF. Each byte of memory is then compared with the
corresponding byte on tape. Checksum errors are detected and printed out on the terminal. MAID, the
debugging function of EXbug, may then be used to examine and alter memory or to trace, modify, or run the
program.
After the program has been debugged or for an interim inspection, it may be desirable to print it or put it
back on tape again. When given the command, PRNT, and the appropriate memory addresses, EXbug will
output each stored byte to the terminal. To copy the program onto tape, the user first positions the tape and turns
the recorder on. The EXbug command PNCH with the beginning and end memory addresses of the program,
will then cause it to copied, byte by byte, from memory onto the tape.
7-2.2.2

MAID
The MAID (Motorola Active Interface Debug) routine of the EXORciser EXbug control program
7-74

enables the user to perform the following operations in debugging a program:
• Examine and change data in a memory location.
• Examine and change the data in the MPU program registers and counters.
• Calculate the offset in the relative addressing mode.
• Insert, display, and remove breakpoints in the program.
• Freerun or trace the target program under MAID control.
• Perform decimal-octal-hexadecimal conversions.
• Search memory for a bit pattern.
These operations are carried out when one or more of the MAID control commands are entered on
the data terminal keyboard. With the exception of the decimal-octal-hexadecimal base conversions, numerical
values or addresses associated with the commands must be entered in hexadecimal notation.
After executing a command, MAID prints out an asterisk to indicate it is ready for another one. If
MAID can not perform the command, it indicates this by ringing the bell on the terminal. In either case, the
asterisk signifies that EXbug is still running the MAID routine and another command may be entered. The
MAID commands are summarized in Table 7-2.2.2-1.
7-2.3

MEMORY UTILIZATION
As shown on the memory map of Figure 7-2.3-1 the EXORciser has an addressing range of 65,536

bytes. Therefore, the highest address is 65,535 or hexadecimal FFFF. This address, and the one below it are
reserved for the Restart subroutine of EXbug. The entire EXbug program is assigned the highest 4096 bytes of
the addressing range. The three ROMs which contain permanent EXbug instructions have hexadecimal
addresses FOOO to FCOO. Addresses FFOO to FFFF are used for interrupt subroutines, to stack register contents,
and to keep track of variable program parameters. The remaining EXbug addresses, FCOO to FFOO, are
assigned to devices within the system, such as the PIA's and ACIA's for input/output.
The target program· is assigned to memory addresses between 0000 and FOOO. This is a range of
61,440 bytes of storage. Few systems require this large memory capacity, therefore, it can be allocated to
minimize the number of address bits for unambiguous access, or to simplify microprocessor operations. As an
example, suppose that the target program is to be stored in two 1024 byte ROMs. Each one has an addressing
range of 400 hexadecimal. One ROM can be assigned addresses 4000 to 43FF, and the other 4400 to 47FF.
Address lines left unconnected cause the respective bit to appear as a O. Therefore the first ROM address can be
specified:
bit

value

I1IoI0

NOTE: X represents either a 1 or a 0
Address lines 10, 11, 12, 13, and 15 are left unconnected. For this address range Line 14 is always 1, therefore
it can be connected to a ROM chip select line. The remainder of the address is determined by bits 0 to 9. Only
address lines 0-9 and 14 have to be tied to the microprocessor address buss in this case.
The second ROM would be connected the same way, except for line 10, which should also be tied to
a chip select line. A similar procedure can be used for the PIA'S, ACIA's, or other system components.

7-75

MAID
Command
n

Description
Print the contents of memory location n and enable the EXORciser to change the
contents of this memory location.
Print the contents of the next sequential memory location and enable the EXORciser
to change the contents of this memory location. (LF - Line Feed Character)
Print the contents of the previous sequential memory location and enable the EXORciser to change the contents· of this memory location. (1 - up arrow character or
SHIFT and N characters)

n;V

Set a breakpoint at memory location n.

Display the breakpoint memory locations.

n;P

Continue executing from the encounter breakpoint until this breakpoint is encountered
n times.

n;U

Remove the breakpoint at memory location n.

Remove all the breakpoints.

n;W

Search for the n bit pattern.

Display the search mask.

Executes the user program starting at the auto restart memory location.

n;O

Execute user program starting at memory location n.

Display/change the user program registers.

Continue executing from the current program counter setting.

(Carriage Return) Close open address and accept next command.

Disable stop-on-address interrupt, leaving stop address at location previously set.

Discontinue trace mode.

Convert the decimal number n to its hexadecimal equivalent.

#n $ n

Convert the hexadecimal number n to its decimal equivalent.

#@ n

Convert the octal number n to its hexadecimal equivalent.

n;O

Calculate the address offset (for relative addressing mode instructions).

Set the trace mode.

Trace one instruction.

n;N

Trace n instructions.

Display/set the stop-on-address compare.

TABLE 7-2.2.2-1 MAID Control Commands

7-76

FFFF
FFOO

65535-----1~--~R~A~M~~
64511~,~.___R_A
___
M __~

I
I
FOOO

64512

(

Interrupt Addresses
Variable Storage
For EXbug

Device Address for
EXbug's ACIA and PIA

I
I

1024

ROM2
63

Dedicated
Memory In
EXORciser

ROM1

1024
EXBUG Program

ROMO
61

FOOO

61440

~
83FF

33791

ROM/RAM

Etc.

8000

32768

R.ot."

PowerfailAdd,."
Address
Software Interrupt
I nterrupt Service
Addresses

Maximum
Program
Usable
With
Debug
Feature

...!.-...--J..,
Typical
Users
Program

0800

02048

ROM/PAM

1024

2
0400

01 024 ---t_~f-------I...-

I
I
I
0025

:~II-::-:~~:~~~:::I ~)

00255 - -......
0000

128

I/O
Device
Addresses

Typical Users Stack
Location and Variable
Scratch Pad

OOOOO--~--~·~--------~·

FIGURE 7·2.3-1: Memory Map and Addressing

7-77

Microprocessor operations are more efficient if a fewer number of bytes, and processor cycles, are
needed to access memory. Those locations which are the object of frequent Load and Store instructions, within
the user's program, should be assigned an address in the range 00 to FF. They can then be defined by a single
byte of machine code, rather than two. This permits the Assembler to use direct addressing instead of extended
for the relevant memory access instructions. This can result in a saving in memory size and cycle time of up to
33%.
EXbug assumes that the average target program may be contained within half of the maximum range
of the EXORciser memory. For this reason EXbug expects address 83FF to be the top of the target memory
range, and looks for the user specified interrupt subroutine pointers in bytes 83F8 to 83FF when initialized.
These pointers are then transferred to locations FFF8 to FFFF in EXbug' s memory. If the user prefers a different
top of memory location for the interrupt pointers, however, the alternate preferred top of memory location may
be entered into EXbug address FFOO, using the memory change command of MAID. After the interrupt
pointers have been placed in the preferred locations, they are transferred to EXbug's memory when the user
presses the ABORT button.
In order to allow for program expansion within memory, it is recommended that the program
initially be placed in the approximate middle of the addressing range. This would be address 8000 to 83FF if
less than 1024 bytes, 7COO to 83FF for a 2048 byte program, 7400 to 83FF for 4096 bytes, 7COO to 83FF for a
2048 byte program, 7400 to 83FF for 4096 bytes, etc. In this manner, the program instructions are expanded
downward in memory. At the same time, the scratch pad and stack area, in the bottom 256 bytes may be
expanded upward.

7-2.4

HARDWARE OPERATIONS AND CONTROLS

7-2.4.1

Combined Hardware/Software
Many of the EXORciser features are entirely implemented by software routines, but a number of

them also utilize hardware to achieve the desired results. One of the special hardware circuits included on the
DEBUG card generates a "Psuedo Powerfail" interrupt. The NMI and RES (Restart) inputs to the
Microprocessor are switched OFF and then ON again after a short delay. The Microprocessor then performs the
"power down" and "Restart" functions even though the system power has remained on at all times. Other
hardware/software features are:
(a) Trace (or Run) one instruction
(b) Multiple loop breakpoint
(c) Stop-on-address

Run-One-Instruction
When the command to "trace" ($T) or "run" one (or more) instructions is entered (n;N), the
hardware cycle counter is enabled and an RTI instruction is executed. This utilizes 12 clock cycles to move the
contents of pseudo registers established on the stack into the internal registers of the MPU Unit. The instruction
addressed by the P counter (just loaded) is started but since the hardware cycle counter was preset to 13, a
pseudo powerfail interrupt is initiated after the 1st cycle. The MPU completes the instruction in progress,

7-78

whether it is one, two, or three bytes and then enters a normal "Restart" routine by fetching the Restart
routine's address from the top two bytes of memory. These bytes are always reserved for this purpose. (When
the EXORciser was first turned ON, the EXbug program preset its own entry address into those top locations.)
As a result, when a pseudo powerfail occurs, the program stops running after completing the current
instruction, and returns to EXbug. EXbug's "Restart" routine stores the contents of all internal registers in
memory and prints them out on the terminal. The system then waits for the next command.

Multiple Loop Breakpoint
The Breakpoint routine utilizes the "Run-one-instruction" routines; therefore, whenever the
second breakpoint is tested (by entering n;P) it will also depend on the hardware counter to interrupt the system.

Stop-On-Address
This is another of the combination Hardware/Software features. It is called by typing the command
$S, which then transmits the desired address to the comparators in the DEbug card. Whenever the selected
address appears on the address bus, a Psuedo Powerfail interrupt is started. On completion of the instruction at
that address, the program enters the EXbug routine to save the internal registers on the stack and display them
(on the printer). The program counter is displayed, and this identifies the program location which activated the
Stop-On-Address compare. The system then waits for another command.

7-2.4.2

ABORT Button Circuit

One of the unique features of the EXORciser is the ABORT circuit. It operates similarly to the other
Pseudo Powerfail functions except it is manually activated. When a typical program is being tested, and it
, 'runs away" , or locks-up in a loop, (which occasionally happens with an untried program), the ABORT button
should be pressed. This causes a printout on the TTY which identifies t~e location (P counter) and all other
internal register contents (so the diagnosis of the cause can be determined). The system then waits for the next
\

command. The recovery occurs in this case without reinitialization so that prior work is not destroyed.

7-2.4.3

RESTART Button Circuit

Occasionally, when a program "runs away" (due to improper instructions), it destroys some of the
preset data in various places throughout memory. If this included EXbug stack contents, the ABORT button
could not restore operation in EXbug. If this occurs, the "RESTART" button must be used to reinitialize the
system in the same way as initial Tum-On or a true power failure. It is not the same, however, because any
program already in RAM will not be lost by use of the RESTART button.

7-2.4.4

VMA Inhibit Decoder

A requirement of the technique of utilizing EXbug routines, at addresses above the users program in
memory, is that the users program must be inhibited whenever interrupts are serviced or EXbug routines are
entered. Since a user's program might not be fully decoded (and need not be) it could respond along with
EXbug. To prevent this, a decoder circuit is included in the Debug card which inhibits VMA to the users
program whenever an address in EXbug is encountered.

7-79

7 -2.4.5

Asynchronous Communications Interface
The EXORciser utilizes an ASR33 Teletype! (or equivalent) for the user to communicate with the

system. It provides the means to enter commands, load data via the tape reader, punch (or record) data from
memory, or to display the status or data for examination.
An interface is provided which uses duplex serial data in ASCII format. Either 20 milliamperes
neutral circuitry or RS232C is accommodated. Also a switchable baud rate is available (from 110 to 9600 baud)
to work with a variety of terminals. This circuitry is implemented on a separate card located in the rear of the
EXORciser chassis. The RS232C interface and the variable baud rates make it possible to use a number of
teletype substitutes but the TI 733 ASR/KSR2 is particularly recommended. The EXbug program
accommodates 30 baud printers and 1200 baud transfer rates for recording and playback of cassettes. The 12
times improvement in program loading or recording speed plus the much reduced noise level, makes a dramatic
difference in efficiency of EXORciser operations.
7-2.4.6

Scope SYNC
A connector is installed on the DEBUG card and 4 thumbwheel switches are provided on the

DEBUG card to implement a Scope SYNC feature. The switches can be adjusted to correspond to any address
in the range 0 to 65K. When peripheral interface circuitry is being debugged, it is frequently very helpful to
examine the signals on the control leads for that peripheral while triggering the scope at a particular time in the
input or output cycle. By setting the thumbwheels to correspond to a specific address in the peripheral service
routine, and by causing the program to loop through that routine if necessary, a careful study of the signals can
be made.
7-2.5

INTERRUPTS

The MPU reserves two bytes at the top of memory for each of four interrupt vectors. Each two byte
vector contains the starting address of the subroutine to be used when the corresponding interrupt occurs. The
MPU always completes its current instruction before recognizing an interrupt. Then, automatically, without
programmed instructions, it transfers the contents of its registers, program location and status to the memory
stack and carries out the subroutine. At the conclusion of the subroutine, a RTI instruction restores the stacked
information to the MPU.
Three of the four interrupts are used by the EXORciser for internal control, but can be exploited for
additional system functions providing that these do not conflict with EXbug. They are: (1) NMI, (2) Reset, (3)
SWI. The fourth one, the Hardware interrupt, is intended for use with the prototype interface. These interrupts
are described below.

The Non-Maskable-Interrupt is best used to signal when urgent control operations are to be
performed independently of the program. For this reason, it is often used to detect imminent power failure
conditions. The EXORciser also reacts to certain user commands by means of this interrupt:
ITeletype is a trademark of the Teletype Corp.
2Texas Instruments Co.

7-80

(1) MAID commands to run through a breakpoint or trace the target program, as follows:

n;G (commence program execution at address n)
;G (commence program execution at Restart address)
;N (run one instruction)
N (run one instruction)
n;N (run n instructions)
$T (run instructions until select address reached)
;P (proceed from current instruction)
n;P (proceed from current instruction through breakpoint n times)
(2) STOP-ON-ADDRESS COMPARE ($S) also uses the NMI interrupt, although it does not
involve breakpoints or tracing. It is obtained by means of a hardware comparator on the
EXORciser DEbug Module.
(3) ABORT sets the NMI interrupt when the front panel button is pressed. Program control is
returned to EXbug.
NMI always causes the MPU registers to be printed. The memory addresses for the NMI vector are
bytes FFFC and FFFD.

7-2.5.2

RESET

This interrupt occurs when the EXORciser is first turned on, or if the front panel RESTART button is
pressed. EXbug is reinitialized and the EXORciser's internal I/O interfaces are set with starting parameters.
These control the baud rate of the attached data terminal and Debug Module hardware. The Reset subroutine is
also performed if the NMI interrupt is set by a power failure. The interrupt vector for the Reset subroutine is at
memory addresses FFFE and FFFF.
If program control is lost and the ABORT button does not return it to EXbug, the RESTART button
should be pressed to reinitialize the EXORciser. MAID may then be called to check that the user's program has
not been altered.

7-2.5.3

The software interrupt is generated by a program instruction, and as such, is not maskable. As in the
case of all other interrupts, however, the MPU is automatically masked while the interrupt subroutine is being
performed. If desired, the user may deliberately defeat this mechanism by putting a Clear Interrupt Mask
instruction (CLI) in the interrupt subroutine. The SWI vector is at locations FFFA and FFFB. The EXORciser
uses this interrupt in MAID to execute breakpoints that have been set in the program. The breakpoint target
instruction is temporarily replaced by an SWI instruction. This switches control to EXbug when the breakpoint
is encountered, and the MPU registers are printed out. Other uses of SWI are to simulate interrupt-driven
synchronous I/O operations, or to insert entire display, data retrieval or test subroutines into a predefined
program without having to change more than a single instruction byte.

7-2.5.4

Hardware Interrupt
Unless the MPU actively scans the status of I/O devices attached to the system, it depends on this

interrupt to signal peripheral conditions. Like user designed equipment that must perform peripheral functions

7-81

most efficiently, the EXORciser interfaces to the MPU with PIA and ACIA chips. These programmable
devices can be set to provide essential control signals, while buffering data and interrupts to the MPU. In order
to expand EXORciser control to the prototype peripherals, the user connects additional PIA's or ACIA's into
the system to act as the interface. The chip and register select lines of the PIA's or ACIA's are tied to appropriate
bits of the address buss, corresponding to the addresses to be used in the prototype equipment. The MPU data
buss is directly connected to the PIA's or ACIA's. If the prototype hardware was constructed on an EXORciser
type plug-in board, all of these connections are made simultaneously when the board is inserted into the
EXORciser, since the EXORciser backplane ties all board sockets into the MPU busses and control lines.
Under ordinary circumstances, the PIA or ACIA interrupt lines are wire-ored to the MPU. The interrupt signal
is not ambiguous, however, since any or all of the interrupts can be selectively inhibited by the MPU.
For "instant" interfacing and least prototype development time, it is recommended that the
EXORciser I/O Module be used. This optional printed circuit plug-in board can be ordered with the
EXORciser. It allows the user to quickly set the PIA register addresses and, by means of screwdriver adjustable
switches, connect two peripheral data busses to each one of its two PIA's. Additional circuitry in the form of
integrated circuits in 14, 16 or 24 pin wire-wrap sockets may also be added.
Interrupts from the user's equipment to the PIA or ACIA are latched and held until the MPU
dismisses them. Depending on their urgency, the target program may react immediately, or when it has reached
a particular instruction. This is possible because the MPU can mask all interrupts or enable only particular PIA
sections. In any case, when the interrupt is recognized the MPU automatically stacks its registers and status. It
next fetches the subroutine pointer from locations FFF8 and FFF9. The interrupt subroutine is then performed,
and an RTS instruction returns the MPU to its central program. If this was the MAID routine of EXbug, control
commands previously entered by the user will be carried out during and after the interrupt subroutine.
Care must be taken to avoid using the MAID Trace command when an interrupt is anticipated. If this
occurs, EXbug may lose control of the EXORciser. This effect is due to the MPU receiving the NMI and
hardware interrupts simultaneously, each of which have a separate subroutine pointer address. The RESTART
button must then be pressed to reinitialize the EXORciser. One method to avoid tracing through an interrupt is
to set breakpoints around it and then use the program run (;P) to go from the first breakpoint to the second. The
first breakpoint is set into the program just before the interrupt mask is cleared or when a PIA input is expected.
The second is placed in the top of the interrupt subroutine. The program run command will then carry the
system through the interrupt into the subroutine without tracing intermediate instructions. After the second
breakpoint is encountered, tracing may be resumed through an RTI instruction at the end of the subroutine.
A frequently used technique for dealing with multiple wire-ored hardware interrupts is for the
interrupt subroutine to scan each of the interrupt generating PIA's or ACIA's. They may be assigned relative
priorities by the program, and if their interrupt flags are set, appropriate instructions executed according to the
priority sequence.

7-2.6

TEST SIGNALS

System address, data and control signals are readily available for observation since the EXORciser
backplane (see Figure 7 -2.6-1) distributes them to all the board connectors. An extender board may be plugged
into an empty connector, or used to lift an operating board above the chassis. To observe a signal, oscilloscope
probes can then be placed on the appropriate board connector pin or to a wirewrap pin on the board. The
following signals are common to all EXORciser boards:

7-82

Component Side

Circuit

Component Side

Pin Number

Function

Side

Function

Pin Number

A
B
C
D
E

+5VDC
+5VDC
+5VDC
IRQ
NMI
VMA
GND
02
GND
Memory Clock
-12VDC
TSC
B.A.
Memory Ready
Refresh Clock
+12VDC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+5VDC
+5VDC
+5VDC
Go/HALT
RESET
R!W
01
GND
GND
VUA
-12VDC
Ref. Req.
Ref. Gnt.

A
B
C
D

F
H

J
K

L
M
N
P

R
S
T
U
V
W
X
y

Function

Side

Function

D3
D7
D2
D6
A14
A13
A10
A9
A6
A5
A2
Al
GND
GND
GND

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

Dl
D5
DO
D4
A15
A12
All
A8
A7
A4
A3
AO
GND
GND
GND

F
H

T
K

L
M
N
P

R
S
+ 12VDC

Circuit

T
U
V
W
X
y

FIGURE 7-2.6-1 Exorciser Backplane Connections for all Boards

7-83

BI-DIRECTIONAL DATA LINES (DO-D.7) - The bi-directional data lines DO'through D7 permit the transfer
of data between the EXORciser MPU and other modules. The data bus output drivers are three-state
devices that remain in the high impedance (off) state except when the MPU performs a memory
write operation.
ADDRESS BUS (AO-Al5) - The sixteen address bus lines are inputs to the bus receiver and select the
memory location to be accessed (write into or read from) by the EXORciser MPU.
NON-MASKABLE INTERRUPT (NMI) - This TTL output requests that the EXORciser MPU performs a
non-maskable interrupt sequence. As with the Interrupt Request Signal, the processor will complete
the current instruction that is being executed before it recognizes the NMI signal. The interrupt mask
bit in the Condition Code Register has no effect on NMI.
The Index Register, Program Counter, Accumulators, and Condition Code Register are
stored away on the stack. At the end of the cycle, a l6-bit address will be loaded that points to a
vectoring address which is located in memory locations FFFC and FFFD. An address loaded at these
locations causes the MPU to branch to a non-maskable interrupt routine in memory.
VALID USERS ADDRESS (VUA) - This output when true indicates to the other Modules that there is a valid
address on the bus and the EXORciser is not addressing an EXbug routine. It is capable of sinking 20
rna. and the voltage levels are TTL compatible.
PHASE 1 CLOCK (cpl) - The cpl clock is the first phase of the non-overlapping clock signals.
PHASE 2 CLOCK (cp2) - The cp2 clock is the second phase of the non-overlapping clock signals.
READ/WRITE SIGNAL (R/W) - This is generated by the EXORciser MPU and determines whether the
MPU is to read (high) data from or write (low) data into other modules or devices. The normal
standby state of this signal is read (high). Three-State Control going high will cause Read/Write to
go into the off (high impedance) state. Also, when the MPU is halted, R/W will be in the off state.
VALID MEMORY ADDRESS (VMA) - This input when true indicates to the DEBUG Module that there is a
valid address on the address bus. This signal is not used by other modules in the EXORciser. See
VUA.
RESET (also called MASTER RESET) - The RESET TTL compatible output, when low, resets the PIA
circuits on the I/O Modules and when high restarts the MPU. This line goes low each time the
EXORciser RESTART switch is actuated or when power is first applied to the EXORciser.
GO/HALT (G/H) - The GO/HALT line is pulled up to 5 volts by the circuitry on the DEBUG card. This TTL
, , 1" is the Go condition for the MPU Module. The user can control this line through the bus if
desired. When this input is in the high state, the machine will fetch the instruction addressed by the
program counter and start execution. When it is low, all activity in the MPU will be halted. This
input is level sensitive. In the halt mode, the MPU will stop at the end of an instruction, Bus
Available will be at a one level, Valid Memory Address will be at a zero, and all other three-state
lines will be in the three-state mode.
The halt line must go low with the leading edge of phase one to insure single instruction
operation. If the halt line does not go low with the leading edge of phase one, one or two instruction
operations may result, depending on when the halt line goes low relative to the phasing of the clock.
THREE-STA TE CONTROL (TSC) - This input causes all of the address lines and the Read/Write line to go
into the off or high impedance state. The Valid Memory address and Bus Available signals will be
forced low. The data bus is not affected by TSC and has its own enable, (Data Bus Enable). In DMA

7-84

applications, the Three-State Control line should be brought high on the leading edge of the Phase
One Clock. The

clock must be held in the high state for this function to operate properly. The

address bus will then be available for other devices to directly address memory. Since the MPU is a
dynamic device, it must be refreshed periodically or destruction of data will occur in the MPU.
INTERRUPT REQUEST (IRQ) -

This input requests that an interrupt sequence be generated within the

MPU. The processor will wait until it completes the current instruction that is being executed before
it recognizes the request. At that time, if the interrupt mask bit in the Condition Code Register is not
set (interrupt masked), the MPU will begin an interrupt sequence. The Index Register, Program
Counter, Accumulators, and Condition Code Register are stored away on the stack. Next the MPU
will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts
may occur. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address
which is located in memory locations FFF8 and FFF9. An address loaded at these locations causes
the MPU to branch to an interrupt routine in memory.
The Go/Halt line must be in the Go (high) state for interrupts to be recognized. If it is in
the Halt (low) state, the MPU will be halted and interrupts will have no effect.
BUS AVAILABLE (BA) - The Bus Available signal will normally be in the low state; when activated, it will
go to the high state indicating that the microprocessor has stopped and that the address bus is
available. This will occur if the Go/Halt line is in the Halt (low) state or the processor is in the WAIT
state as a result of the execution of a WAIT instruction. At such time, all three-state output drivers
will go to their off state and other outputs to their normally inactive level. The processor is removed
from the WAIT state by the occurrence of a maskable or non-maskable interrupt.
MEMOR Y CLOCK -

This clock signal provides basic timing for the optional 8K memory boards, DMA if

used, and memory refresh cycles. It is synchronized with
REFRESH CLOCK -

of the MPU clock.

This clock determines the frequency of MPU and dynamic memory refresh cycles.

REFRESH REQUEST REFRESH GRANT -

This signal indicates when the MPU and dynamic memory should be refreshed.

This signal acknowledges the Refresh Request, when an MPU clock cycle has been

stolen to refresh the MPU and/or dynamic memory.
MEMORY READY -

This signal is used when interfacing slow memories (TACC

> 575 nanosec.). If this

signal is brought low, it will stretch the high portion of cp2 of all clocks.
+5 VOLTS - This voltage is available to all EXORciser boards. Total load should not exceed 15 amps
+ 15 VOLTS -12 VOLTS GROUND -

This voltage is available to all EXORciser boards. :rotalload should not exceed 2.5 amps.
This voltage is available to all EXORciser boards. Total load should not exceed 1.0 amp.
Common electrical reference point for all EXORciser voltages, signals and chassis. When

grounding an oscilloscope, or connecting external circuitry, care must be taken to avoid noise
pickup at the ground point. There are ten separate grounds on the EXORciser backplane, tied
together at a single point, that can be selected for minimum noise on a particular signal line.
All the card slots in the EXORciser housing are wired in parallel so any card could be
inserted in any slot. However, the I/O and Universal Wirewrap cards require 1~ inches between
slots while the MPU RAM and Debug Modules (which are standard PC construction) require only
%" . The slots are arranged so that the 6 in the center are % " apart while the 4 on each side are spaced
1~" .

The M6800 Microprocessor Family utilizes an Address and Data Bus structure to
interconnect all units and uses the technique of treating all peripherals as memory. Address decoding
7-85

is thus provided for each I/O channel. Output from or input to a peripheral via the Microprocessor
Bus is achieved by "Storing to" or "Loading from" a specific address which has been assigned to
the PIA's or ACIA's.
In the EXORciser, each Module has MC8T26 Bus Driver/Receivers incorporated so that
an almost unlimited number of memory or I/O Modules can be used. Also each memory or I/O
Module is equipped with address decoding which utilizes hexadecimally marked, screwdriver
adjustable switches to provide instant address assignment for rapid system assembly.

Special Signals
The following signals are not bussed to all boards, but provide essential timing for an individual
module or device:
MPU Module Only:
DATA BUS ENABLE (DBE) - This input is the three-state control signal for the MPU data bus and
will enable the bus drivers when in the high state. This input is TTL compatible; however
in normal operation, it should be driven by the phase two clock. During an MPU read
cycle, the data bus drivers will be disabled internally. When it is desired that another
device control the data bus such as in Direct Memory Access (DMA) applications, DBE
should be held low.
FRONT PANEL
RUN -

The RUN signal is present whenever the MPU is executing in user memory (0 to 60K).

ABORT (Two Lines) - These two inputs are connected to a cross-coupled TTL anti-bounce circuit
so that one line is normally low and the other high. The EXORciser ABORT switch is
SPDT and connected so that the grounded side is transferred to the other line when the
button is pressed. The output of this circuit is used to activate NMI.
RESTART (Two Lines) - These two inputs are connected to a cross-coupled TTL anti-bounce
circuit so that one line is normally low and one high. The EXORciser RESTART switch
is SPDT and connected so that the grounded side is transferred to the other line when the
button is pressed. The output of this circuit is the RESET signal.
Baud Rate Module:
READER ON - This signal is the output of a TTL F/P in series with 510 ohms and is applied to the
Baud Rate Module and used to control the reader of a modified teletypewriter. This line
provides approximately 5 rna. to drive the diode in the optical coupler.
TTY SERIAL OUT - This signal is the output of a TTL inverter with a series 510 ohm resistor. It is
intended to drive the diode of an optical coupler on the Baud Rate Module. The signal
switches the 20 milliampre line to the teletype in response to the data from the U AR T .
RS232 INPUT - The RS232 OUT line transfers serial data through the level conversion in the Baud
Rate Module to the terminal device. This output is TTL compatible at this point.
RS232 INPUT - The RS232 INPUT line is a TTL compatible input through which data is received
in a serial format from the level converters on the Baud Rate Module.
TTY SERIAL INPUT -

The TTY SERIAL INPUT line is a TTL compatible input through which

data is received in a serial format from the TTY inputs on the Baud Rate Module.
7-86

RS232 DTR -

This input is TTL compatible. The signal is generated on the Baud Rate card.

CLOCK (CLK) - The CLK input from the Baud Rate Module determines the baud rate at which the
EXORciser will exchange data with its terminal device. This input is TTL compatible
and represents two standard loads. (3.2 rna. at 0.4 V)
STOP BIT SELECT - This input is TTL compatible. When high, two stop bits are selected by the
UART. When low, one stop bit is selected. The signal is generated by the Baud Rate
Module in the EXORciser.

Reader and Punch Control
The 1.1 version of the EXbug program is designed to work with several models of teletypes as well
as with a Texas Instruments ASR733 Cassette/printer terminal with 1200 baud and Remote Device Control
options.
The EXbug program utilizes the usual ASCII control codes to control teletypes equipped with
Automatic Readers and punches. The codes are: (Shown in hexadecimal notation)
DCl Reader ON -

(11)

DC2 Punch ON - (12)
DC3 Reader OFF - (13)
DC4 Punch OFF - (14)
The program also includes routines to control teletypes which have been modified by the addition of
a reader control relay. A Flip/Flop on the DEbug card and an optical coupler (U4) on the Baud Rate Card
implement this function. The' 'D" type Flip/Flop is set by outputting to address FCF4, a data word in which bit
5 is a "1". This turns the reader relay ON. Since both these methods of control are included, either type of
teletype will work.

TI ASR733 Operation
The Texas Instruements ASR733 terminal recommended for use with this version of EXbug utilizes
an Remote Device Control (RDC) card to provide the extra control functions needed for control of the printer
and Cassettes when using the 1200 baud option. For 10 and 30 character per second (CPS) rates, the tape is
started and stopped (in playback) by the usual ASCII Reader Control codes DCl and DC3 but for 120 CPS
operation the "Block Forward" command oftheRDC card (DLE,7) is used to control the Cassette. The printer
is commanded ON and OFF by the (DLE,9) and (DLE,O) codes to avoid garbled printing. In initialization, the
Auto Device "ON" code (DLE,:) is used to make sure the RDC card will respond.

Baud Rate Control
Another feature of "EXBUG 1.1" is its ability to be adjusted for operation at various baud rates.
Programs written for a TTY require at least two character times (200 milliseconds) for the carriage to return.
For this reason, the CR is issued followed by a (LF) Line Feed so that the next character will print at the
beginning of the next line. When the TI terminal is used at 30 characters per second, the carriage return time ~s
similar so it is necessary to insert 4 additional character delays by outputting null characters (0). The command
S30. is typed to accomplish this.

7-87

In the case where the Verify routine is used, it is very desirable to run the tape at 1200 baud but also
necessary to print the differences found (between the tape and memory). Since the Printer mechanism will only
print at 30 characters per second and the data transfer rate is at 120 CPS, three null characters are inserted
between each character to be printed and 22 nulls are output after each carriage return. Typing" S 120" after the
baud rate has been set for 1200 baud, switches this version (1.1) of EXbug to provide this format.

Formatted Binary Object Program Tapes (i.e. LOAD, VERF, SRCH and PNCH)
The first four routines in EXbug involve the handling of "Formatted Binary Object Program
Tapes." These tapes are generated by the MPU Build Virtual Machine Program on timeshare, or by the PNCH
routine in EXbug. The tape can be the conventional paper tape (if the system terminal is a Teletype) or may be a
Cassette tape such as that produced by the Texas Instruments ASR33 terminal. The procedure for using the
Build Virtual Machine time-share program to generate a suitably formatted tape is described in Section7 -1. 7.
This Section is included in order to summarize the principle features of the EXORciser. For
additional information, the several Manuals provided with the EXORciser should be referred to.

7-3

EVALUATION MODULE
The M6800 Evaluation Module is a pre-engineered assembly that provides an efficient means of

becoming familiar with the M6800 Microcomputer family of parts. The Module (see Figure 7-3-1) is designed
to demonstrate the M6800 Family operating with their specified loading at clock frequencies up to 1.0 MHz. In
addition to its use for evaluating the family devices, it can be used to enter and de-bug simple programs
including the operation!control of peripheral devices. The circuit configuration is shown in block diagram form
in Figure 7-3-2. A brief summary of the specifications is shown in Table 7-3-1.

FIGURE 7-3-1: The Evaluation Module

7-88

An interface is provided for either a 20 rna current loop TTY or an RS-232C compatible terminal.
The terminal can be used to communicate with the Module's diagnostic control program, MIKBUG. The
MIKBUG program is stored in read only memory, and in conjunction with the terminal can be used to perform
the following functions:
.' Load data into the Evaluation Modules random access memory.
• Display and, if desired, change the data in the Modules random access memory.
• Print out or generate a tape of the data stored in the modules memory.
• Display and, if desired, change the contents of the MPU's registers.
• Run User Programs
• Evaluate Interrupts
• Set Breakpoints
The use of each of these features plus a complete description of the Module is provided in the M6800 Evaluation
Module User's Guide; it may be referred to for additional details.
Characteristics

Specifications
+5 VDC @ 2A

Power Requirements:

+12 VDC @ 250 rnA
-12 VDC @ 250 rnA
Clock Frequency:

100 KHz to 1 MHz (adjustable)

Signal Characteristics:
Connector (P 1)
Address bus
Data bus
Input
Output

Three-state TTL voltage compatible
TTL voltage compatible
Three-state TTL voltage compatible

Input and output commands

TTL voltage compatible

MC6820 Peripheral Interface Adapter (P2)
Data signals
PAO-PA7 input/output lines

TTL voltage compatible

PAO-PB7 input/output lines

Three-state TTL voltage compatible

Control Signals
CAl, CA2, and CB1

TTL voltage compatible

CB2

Three-state TTL voltage compatible

Terminal Interface Specifications (P3)
Data transfer rate

110 or 300 Baud

Signal characterisitcs

TTY or RS-232C Compatible

Reader control signal

Control signal for modified TTY devices

Data Format

ASCII
TABLE 7-3-1 Evaluation Module Specifications

7-89

~VA-;;AT~ M~LE- -

-- -- -

-- --

-- -- -- -- --

--,

I
I

RESET

RESET
CI RCUIT

TSC

bEl

TSC

G/H

\0
o

VMA

R7W ~

CONTROL
BUS
INTERFACE

MICRO
PROCESSING
UNIT

~
~

TERMINAL
INTERFACE

CLOCK

RlW_

-T

VMA-2

I+--

_ DATA
BUS
OUTPUT
ENABLE

R/W

I
j

,V8

BUS

DATA
BUS
INTERFACE

8/
/

ENABLE

FIGURE 7-3-2: Evaluation Module Block Diagram

SERIAL OUTPUT
READER CONTROL
RS-232C INPUT

CAl
CA2
PAO thru PA7
CB2
PBO THRU PB7

I
LJ

6E8
YE10
_ _ _ _ _ _ _ -.J
E9

SERIAL INPUT

I
I
I

PROM
MEMORY

1
IROB

AOTHRUA15

RS-232C OUTPUT

" I

L ________ _

nr I
ENABL

Ell~
E12.£

E14

PIA

IROA
DATA

, -12

DATA
BUS
INPUT
ENABLE

E136-

BIT
RATE
CLOCK

R/W

I
I

AO-A2,
5 A13,A15

RAM
MEMORY

I-=-

VUA

AO-A9
A12-A15
AO,Al,
14 V
A3,A13,
A15

I iE4
BA

A13-A15

AO-A8,
A13-A15

ROM
MEMORY

-.....J

(5 E7

0?E6~1-'12

tE2

ADDRESS
BUS
INTERFACE

ADDRESS BUS

09 THRU 07

The Module includes two PIAs. One is used for the terminal interface, however, the other is
available for general use. It can be used in exactly the same manner as in an EXORciser or a prototype hardware
design for interfacing to peripherals. This PIA has, for instance, been used to control a TTY type keyboard and
a self-scan visual display used in conjunction with a portable demonstration kit for the Evaluation Module.
A memory map of the Evaluation Module is shown in Figure 7 -3 -3. The Module provides up to 640
bytes (hex addresses 0000 to 027F) for storage of evaluation programs. The 128 bytes of random access
memory at base memory address AOOO is used as scratch-pad memory for the MIKBUG firmware. MIKBUG is
located at base memory address EOOO. An interface is provided for adding additional blocks of memory. The
additional memory could be located anywhere from 0000 through DFFF except for addresses 8004 through
800B and AOOO through A07F.
In addition to the Evaluation Module printed circuit assemble itself, the following items are
provided:
• An 86-pin connector compatible with the PI connector of the Module
• TTY/RS-232C 16-pin Flatribbon Cable WI for connection between the Module and a terminal.
• PIA Connector/Flatribbon Cable W2 for connecting the Module to external peripheral devices.
• M6800 Evaluation Module Users Guide which contains a complete description of the Module and
includes detailed operating instructions.
This package provides a simple but useful method for evaluating the M6800 Family's characteristics in a
realistic environment.

7-91

Not Use

~------------------------------------~ EFFF

~------------

Mikbug

EOOO

....

Mikbug Program

t07F
AOOO

800B
PIA Addresses
8008
8007
Terminal Addresses
8004
.. r-'

0279

640 Bytes
Random Access
Memory

0000

FIGURE 7-3-3: Evaluation Module Memory Map

7-92

APPENDIX A
(Questions and Answers)
1 M6800 SYSTEMS OPERATION
Q 1.

Is it possible to read a PIA address unintentionally?

A 1.

Yes. If the PIA is assigned an address in memory such that the address location immediately preceding
it contains a single byte (inherent address mode) instruction, then the execution of that instruction will
cause the PIA to be read. The MPU always fetches the byte following the operator byte. If the PIA
address that is read happens to be a Data Register, then the interrupt flags may be inadvertently cleared.
This may be avoided by separating PIA addresses from the main program by at least a single byte gap.

Q 2.

What is the MPU's drive capability?

A 2.

The MPU can drive 130 pf of capacitance and one standard TTL load while operating at 1 MHz. Since
the PIA, RAM, and ROM have Data Bus load capacitances of 10 pf, 15 pf, and 15 pf, respectively, the
MPU can drive from 7 to 10 family devices at 1 MHz.

Q 3.

What is the state of the PIA's 1/0 lines at initialization?

A 3.

The RES signal to the PIA will reset all six of the internal registers (Control, Data Direction, and
Output Data) to zero. Since all the Data Direction Register bit positions are zero, the I/O Data lines
PAO-PB7 and PBO-PB7 will be established as inputs. Since b5 of both Control Registers is zero, the
CA2 and CB2 control lines are also established as inputs. This has the following effect on lines that will
later be established as outputs (that is, they may be hardwired to the inputs of external logic elements):
Since the B side of the PIA has three-state outputs and the lines are "initially established as inputs, they
represent a high impedance" off" device and will not affect the inputs of gates that may be connected.
The A side lines have an internal pullup resistor and will' 'look" like logic ones to gate inputs. External

---

circuitry tied to the A side should require active low signals if they are not to be affected by RES.
On the B side lines that are to be established as outputs and used to drive active high Darlington inputs,
a resistor to ground can be used to avoid initial turn on:

If the output lines are to drive TTL and must be active high, the peripheral logic should be disabled with
a hardware control during the initialization sequence. Note that, as far as system operation is
concerned, the initial state of some lines may not matter. For example, in a tape cassette system if the
motion control circuitry is disabled during initialization, the other lines such as direction and speed are
"don't cares."

A-I

Recommended procedure for initializing the PIAs is as follows:
1. Set b2 = 1 in the Control Register in order to select the Data Register.
2. Write the desired initial logic states into the Data Register.
3. Then establish the required outputs by selecting the Data Direction Register by setting b2
Control Register and writing the appropriate pattern into the Direction Register.

= 0 in the

Q 4.

What causes the PIA to miss interrupts when the MPU is halted or in the WAIT mode?

A 4.

While there are nominally no restrictions on the format of interrupt signals into CAl, CA2, CB 1, and
CB2 of the PIA, there are certain combinations of system situations that require special consideration.
Assume that the interrupt signal format follows one of the cases shown in Figure Al and that the PIA
has been conditioned by the MPU to recognize the transition polarity represented by the "trailing
edge" of the interrupt pulse.

Interrupt
Signals Into
,PIA CA(B) 1
and CA(B)2

{

-----~

FIGURE A1. Interrupt Signal Format

The design of the PIA is such that at least one E pulse must occur between the inactive and active edges
of the input signal if the interrupt is to be recognized. Relative timing requirements are shown in Figure
A2. Note that an internal enable signal that is initiated by the first positive transition of E following the
inactive edge of the input signals is included.

E = VMA· 2

PIA Internal Enable

Int. to CA(B) Inputs

I RQ (Int. Rqt to MPU)

FIGURE A2. Interrupt Enabling

When the MPU has been halted either by hardware control or execution of the Wait For Interrupt (WAI)
instruction, its VMA output goes low. Since VMA is normally used to generate the Enable signal (E =
VMA· cp2) either of these two conditions temporarily eliminates the E signal. The effect of this on the
trailing edge interrupt format is shown in Figure A3 where it is assumed that VMA went low and
eliminated the Enable pulses before the PIA's interrupt circuitry was properly conditioned to recognize
the active transition. It should be noted that this condition occurs only when an active transition is
preceded by an inactive transition and there are no intervening E pulses.

A-2

VMA

E = VMA •

After Halt or WAI

r-,

cJ>2

r-,

,..--------------

PIA Internal Enable

Int. to CA(B) Inputs

I RQ (Int. Rqt to MPU)

L
FIGURE A3. Interrupt Not Properly Enabled

If this combination occurs during system operation, valid interrupts will be ignored. Either of two

simple precautions can be adopted. If the format of the interrupt signals is up to the designer, the
potential problem can be avoided simply by not using the pulse-with-trailing-edge-interrupt format.
If this format is compulsory, it is recommended that ~2 be used as the Enable signal with VMA ANDed

with an address line and applied to one of the PIA's chip select inputs as shown in Figure A4.

AO
A1
A3
A13
VMA

CS1
CS2

A14

cJ>2

FIGURE A4. Alternate E Generation

Q 5.

Is there any change in the CA2 (CB2) line if it is set to a logic "0" (Control Register bits 5, 4, 3,
are 110 respectively - defining CA2 (CB2) as an output) and then the control register is put in
the handshake mode (CR bits 5, 4, 3, are changed to lOX, respectively)?

A 5.

When the control register bits are changed to put the PIA in the handshake mode, the CA2 (CB2) lines
remain low.

Q 6.

What are the threshold points for the M6800 family from which the delays are measured?

A 6.

The M6800 input thresholds are specified as Logic 1 = 2.0v, Logic 0

= O.8v; the delays are measured
from these points. TTL and M6800 family devices provide output signals having logic 1 = 2.4v and
logic 0 = O.4v, providing 400 mv of noise margin. The delays are measured as shown:
A-3

2.4 V
_~~_---.~ Noise Margin = 400 mv

- - i I I - - 2.0 V

-+-+-.8 V
2.4 V
---.....~-#--

2.0 V

-~-~-.8V

'-----------------~---'

'-------.4 V

~----DelaY---"""""1--

Q 7.

What happens in the ACIA when a control word is loaded after an ACIA reset condition? (How is
the ACIA initialized in the system?)

A 7.

When power is turned on in the system, the ACIA interrupts may be enabled and generate a system
interrupt. This can happen if there is a glitch in the power supply as the power came on:

~-----------------Vcc
Supply

Voltage
--~------------------------------------~"time

The procedure for initializing the ACIA is to do a master-reset by writing into the control register
(CR 1 = 1; CRO= 1), while the interrupts are masked in the system. The master reset clears the interrupt,
transmit data register empty, and receive data register full flags, and clears both the receive and
transmit data registers. The ACIA interrupts may then be enabled as required.

NOTE: Since a master reset clears the Transmitter buffer, an interrupt will be generated from the ACIA
provided the Transmitter Interrupt Enable (TIE) is activated when loading the control register
subsequent to the master reset.
Q 8.

How large a load is the MC8T26 bus driver?

A 8.

The MC8T26 has a PNP input and loads the MPU as shown:
200 IJ-a max at "0"
25 IJ-a max at "1"
= 10 pf input capacitance

Q 9.

Why is 100 KHz specified as the minimum operating frequency?

A 9.

The MPU is a dynamic device and (like dynamic memories) requires refreshing via the clock. The
maximum time between refresh transitions on the clock line is 5 IJ-S corresponding to an MPU cycle
time of 10 IJ-S; ora frequency of 100 KHz.

A-4

2 M6800 CONTROL
Q 1.

Can ODE be tied to a OC level?

A 1.

No, the DBE signal is used to refresh the output buffers which are dynamic. DBE cannot be held in one
state for more than 4.5 /LS without degrading the data held in the output buffers.

Q 2.

What does ODE control?

A 2.

DBE controls the three-state enable on the data output buffers. When DBE is low, the data output
buffers are in the high impedance state. When DBE is high, the data output buffers drive the data bus.
The data output buffers are also in the high impedance state during the execution of a read cycle (R/W
= 1).

Q 3.

What should be used as a ODE control signal?

A 3.

Most applications will use cp2 as the DBE control signal. A longer data hold time requirement during a
write cycle may be met by holding DBE high past the trailing edge of cp2. The MPU data setup time
(TADS) can be shortened from the 200 ns specified by bringing DBE high before the leading edge of

cp2.

The exact timing relationships are currently being characterized.

Q 4.

What is the relationship od ODE and TSC?

A 4.

DBE is the three-state strobe for the data buffers while TSC is the three-state strobe for the address bus
and the R/W line. TSC also forces VMA low. In many applications, it will be desired that the MPU
always drive the bus, thus, TSC will be tied low. In other applications, TSC will be used to implement a
Direct Memory Access, (DMA), or to force VMA low during system power-up rather than using
RESET to disable the devices on the bus. DBE and TSC cannot be tied together because DBE must
change states every 5 /LS whereas, in many systems, TSC will be tied low.

Q 5.

Will interrupts (IRQ or NMI) and RESET be recognized while the MPU is halted?

A 5.

Interrupts will not be acted on while the MPU is halted. These control signals are latched on the MPU
and will be serviced as soon as the MPU is taken out of the halted state. RESET going low while the
MPU is halted causes the following: VMA-low, BA-low, Data Bus-high impedance, R/W -Read State,
and the Address Bus will contain the restart address FFFE.

Q 6.

What happens if the MPU is halted and the + 5 volt power fails?

A 6.

The MPU stops program execution and all internal register contents will be lost.

Q 7.

How can one tell whether the MPU has halted?

A 7.

When the MPU is halted the BA signal will be high. The MPU completes execution of an instruction
before halting. Once the execution is completed, BA will go high within 470 nsec after the leading edge
of the next ~2 signal. Whenever BA goes high the MPU is inactive (halted) and the address bus, R/W
line and data bus are available for use by another device for as long as necessary. One caution to be
observed is that TSC going high will force BA low whether or not the MPU is halted. When the MPU is
halted all MPU outputs are in the high impedance state, therefore, there is no reason for TSC to be high,
however if it is brought high BA will go low and the indication that the MPU is halted will be lost.

A-5

Q 8.

What is the timing relationship between HALT and BA?

A 8.

If HALT is low during the first lOOns of cf> 1 in the last cycle of an instruction the MPU will halt at the

end of that instruction. If HALT is not low during the first lOOns of cf> 1 in the last cycle of an instruction
the MPU will halt at the end of the next instruction. The fastest instructions such as LDAA (Immediate)
execute in 2/-Ls while the longest instructions such as SWI require 12/-Ls to execute, (assuming a 1 MHz
clock rate). Depending on the instruction being executed when HALT goes low, BA will go high no
sooner than 2/-Ls and no longer than 14/-Ls after the negative transition of HALT.

Q 9.

How is single instruction execution accomplished with the MC6800?

A 9.

Single instruction execution is accomplished by holding the HALT line active low and pulsing the
HALT line high for one clock cycle when an instruction is to be executed. The transitions of this pulse
must occur within lOOns of the leading edge of cf> 1. The machine will come out of the halted mode and
execute the next instruction which will require from 2 to 12 machine cycles to complete. After
completion of the current instruction the MPU will return to the halted mode. In order to avoid incorrect
operation of the MPU when" stepping" through a program at a very high rate, the HALT line must not
be pulsed high until the MPU has completed executing the instruction commanded by the previous
HALT pulse. The BA signal going high will indicate that the MPU has halted and is available for
another single cycle pulse on the HALT line.

Q 10.
A 10.

What effect on the other MPU signals does a low logic level on the RESET pin have?
RESET is intended to be used to initiate the power up sequence. RESET should be held low while
power is coming up and for at least 8 clock cycles after the power supply voltage goes above 4.75 volts
to properly initialize the MPU. During this time the address bus, R/W line, VMA line and data bus will
be in an indeterminate state. If any devices on the data bus could accept a write pulse during this time (a
battery backed RAM for example) they should be disabled until RESET goes high to avoid system
problems. After 8 clock cycles VMA will go low and RESET may be brought high causing the MPU to
vector to the restart addresses FFFE and FFFF.

Q 11.

With the MPU power up and the system running can RESET be pulsed low to re-initialize the
system?

All.

Yes. Assuming that the processor has been running for at least 8 clock cycles, the processor can be
restarted by pulsing the RESET line low. This pulse must remain low for at least three

cP2 cycles.

While the RESET line is low the MPU output signal will go to the following states: VMA-Iow,
BA-Iow, Data Outputs-high impedance, R/W (Read State), and the Address Bus will contain the
restart address FFFE. This will occur within 300 ns of the
RESET went low.

cP1 cycle following the cP1

cycle in which

Q 12.

How can a 'DMA channel be implemented with the MC6800 MPU?

A 12.

Two methods of controlling the MPU to allow DMA involve the use of the HALT and TSC lines.
(a) When the HALT line is pulled low the MPU will finish the current instruction and then go into the
halt mode as indicated by BA being high. All address lines, data lines, and R/W lines will be in the
high impedance state, allowing the DMA channel to assume these functions. VMA will be forced

A-6

low. Once the MPU enters the halt state (which can take up to 14 nsec to finish the current
instruction), DMA transfers can begin and control the bus as long as necessary. The speed of DMA
is limited only by the constraints imposed by the memory system speed and DMA controller
design.
(b) TSC used in combination with stretching of the clock signals can provide a DMA channel which

allows DMA transfers without stopping MPU program execution. In order to transfer DMA
information using this technique TSC is brought high on the leading edge of cp1 when a DMA
transfer is requested. While TSC is held high the cp1 clock is held in the high state and the cp2 clock
is held in the low state in order to stop program execution by cycle stealing. Assuming that DBE is
driven by cp2 the result of pulling TSC high will be to place the address bus, R/W line, and the data
bus in the high impedance state. VMA and BA will be forced low. Due to the use of dynamic
registers within the MPU the clock signals cannot be held in any given state for more than 4. 511-s
producing a lower limit on clock frequency of 100KHz. This factor limits DMA transfers on the
bus to this 4.511-s interval when cp1 is held high. After the 4.511-s interval when cp1 is being held high
the MPU must be clocked in order to refresh the dynamic registers. This technique of DMA has the
advantage of fast response to a request for a DMA transfer (TSC = 1) but has a limitation on how
much data can be transferred in one block. Halting the machine as described in (a) has a longer
response time before DMA transfers can start but there is no limitation to the block size of the
DMA data.

Q 13.

What control signals could be used to select ROMS, RAMS, and PIA/ACIA?

A 13.

VMA, R/W and cp2 are all available to enable RAMS, ROMS and PIA/ACIA's. In some cases it may
be desirable to eliminate one of these enabling signals so that enable input may be freed for address
decoding. The following discussion indicates which control signals could be deleted for a given device
and the effects on the system operation.
ROM -

R/W and cp2 can be used to enable the ROMS without using the VMA si.gnal. Not using the
VMA signal means that the ROM may be enabled during a non-memory reference read cycle
(VMA would be low but since it is not used the ROM may be enabled). A false read of the
ROM will have no effect on the system and if the non-memory reference cycle had been a
write then the R/W signal would have disabled the ROM.

RAM -

VMA can be left off as an enable to a RAM if the MPU will not be halted, WAI Instruction
executed or if the TSC will not be used. Either of these conditions cause the Address lines and
the R/W lines to float which could produce a false write into RAM if not protected by VMA.
During normal operation of the MPU only one instruction, TST, causes a false write to
memory (i.e. the write line going low

with~ut

VMA also going low). This instruction does

not pose a problem because it first reads the memory and then rewrites the data read. If VMA
was used to enable the RAM this false write would not occur, however, since the memory is
rewritten with the same data no problem occurs by not using VMA as an enable.

A-7

PIA/ACIA --.,;. All three signals must be used to enable or select a PIA or ACIA. Both of these devices
automatically clear the Interrupt Flags when the MPU reads the PIA or ACIA data
registers so that a false read of a PIA or ACIA may cause an interrupt on CAl, CB I,
CA2, or CB2 to be missed. In addition it is suggested that VMAecf>2 not be used as an
Enable signal for a PIA because if the machine is halted, (HALT active or W AI
instruction) VMA is forced low removing the clock from the PIA. Without the Enable
input to the PIA an external interrupt may not be recognized. cf>2 should be used for the
PIA Enable signal so that the PIA Enable clock always occurs whether or not the MPU is
halted. VMA may then be taken directly to chip select inputs or be gated with address
signals to the chip select inputs.

A-8

3 M6800 INTERRUPT OPERATION
Q 1.

What happens if the interrupt mark is set (1=1) and (a) a SWI occurs; (b) a WAI occurs?

A 1.

(a) The interrupt service routine indicated by the SWI vector will be processed. The Interrupt Mask
status (1= 1) will be saved on the stack with the other Condition Code Register bits. The RTI at the end
of the service routine then restores the 1= 1 status when the stacked condition code register is returned
to the MPU.
(b) If a W AI is executed while the Interrupt Mask is set, the MPU will cycle in a wait loop unless a

non-maskable interrupt (NMI) occurs.

Q 2.

Is the interrupt mask always cleared after an RTI?

A 2.

An RTI returns the I to the status that existed before the interrupt occurred. If the interrupt mask is set
then only the NMI or SWI can cause interrupts. The interrupt mask will be set following execution of
RTI if it was set prior to the above interrupts.

Q 3.

If power goes down how does the programmer know where the MPU contents are stacked?

A 3.

If the system uses NMI as a power fail detect input and there is non-volatile memory in the system the
MPU status will be saved on the stack. As part of the NMI service routine the STS instruction can be
used to store the stack pointer into a predetermined non-volatile memory location. If the MPU status is
also to be saved the stack must be in non-volatile memory.

Q 4.

How can the NMI input be used as an operator interrupt?

A 4.

If NMI is not used for starting a power down sequence, it may be used directly as an operator interrupt
by having an operator interrupt service routine specified at the NMI vector location.
If NMI is used for power down and operator interrupt, some external circuitry may be added so that a
test in the NMI service routine can determine whether a power fail or an operator interrupt has
occurred. In the diagram shown below, the test may be accomplished by reading the PIA data bit,
PAO. IfNMI occurs, a test of the appropriate PIA data register will determine whether a power down
or an operator interrupt occurred.
Powerfail -------~........
}--------.
Operator I ntrpt

PAO
- - -..... NMI

PIA

MPU

A-9

Q 5.

What instructions set the interrupt mask?

A 5.

TAP, SEI, SWI, WAI (after interrupt occurs).
The interrupt mask will also be set by NMI, RES, and IRQ interrupt inputs to the MPU.

Q 6.

If NMI occurs while the MPU is halted will the MPU respond to the NMI when it is returned to
the "go" state?

A 6.

Yes, there are flip-flops in the MPU to save NMI and IRQ. When the halt condition is removed, the
MPU will execute one instruction and then operate on NMI.

Q 7.

How will the MPU react to the following conditions?
HALT

RES (Case 1)

RES (Case 2)

A 7.

'T3

In both cases the MPU will eventually recognize the RES. The RES sequence will be initiated when
RES goes high in Case I and when HALT goes high in Case 2. During TI, the MPU is halted and its
outputs are in the three-state high impedance mode. When the RES line goes low at the beginning of
T2, a halt latch is reset, the MPU goes out of three-state, and (after 3 machine cycles) the Address bus is
outputting FFFE, the most significant half of RES vector address
In Case I, the HALT line goes high and the MPU waits in its current state until RES high at the end of
T4; the MPU then fetches the starting address of the RES service routine from FFFE and FFFF and
processes the RES interrupt.
In Case 2, the RES line goes high at the end of T2 and the MPU loads the Program Counter with the data
(starting address of RES routine) from locations FFFE and FFFF and enters the halt mode again. The
RES service routine begins executing when HALT goes high at the end of T3.

Q 8.

Can the Interrupt Mask be changed by the TAP instruction?

A 8.

Yes. The contents of accumulator A is stored in the Condition Code Register, including the Interrupt
Mask. Note that bits 6 and 7 will not be stored.

Q 9.

What happens when an NMI interrupt occurs during a SWI?

A 9.

It is a characteristic of the MPU that if an NMI occurs while a Software Interrupt (SWI) is being
executed, the interrupt vector will be retrieved from the IRQ location rather than either the SWI or NMI
locations. If there is a possibility of this situation developing during system operation, precautions
should be taken to avoid an ambiguous result. In most applications, the NMI must be recognized and
serviced whenever it occurs.
A simple procedure is to always set a flag immediately prior to each use of SWI:

A-IO

NOP
SEI
INC NMIFLG
SWI
DEC NMIFLG
CLI

Set possible NMI Flag.
Execute Software Interrupt
Clear flag if SWI was normal

Testing this flag can then be made the first step of the normal IRQ service routine. As an example,
assume that the IRQ vector has been fetched and directs program control to IRQ service routine
START:
START

TST
BEQ
JMP

NMIFLG
IRQSVC
NMIAUX

IRQSVC

xxx

xxxxxx

Was this NMI via SWI?
No, branch to normal IRQ
Yes, go to NMI Service routine

For a normal IRQ, the flag will be zero and the routine will branch to the normal service routine,
IRQSVC. If the IRQ was entered via a Simultaneous SWI-NMI, the flag is non-zero and control is
transferred to an auxiliary NMI routine, NMIAUX:

NMIAUX

HIBYTE
NMISVC

TSX
TST
BNE
DEC
DEC
xxx

6,X
HIBYTE
5,X
6,X
xxxxx

Get SP into X reg
Lobyte of PC on Stack = q,q,?
Yes, go decrement Hibyte
No, decrement lobyte
Decrement Hibyte
Begin normal NMI service

A normal NMI would be vectored to NMISVC. IfNMISVC is entered via a simultaneous SWI/NMI
and it is required that the program resume normal operation following service of the non-maskable
interrupt, NMIAUX will insure an orderly return to the main program. The NMIAUX sequence causes
the value of the Program Counter that was stacked by the SWI instruction to be decremented by one so
that the stacked program counter is pointing to the S WI instruction's location. This will cause the S WI
instruction to re-execute following an RTI from the NIMSVC service routine. Program flow will then

A-11

proceed as if the NMI had not occurred. If there is no system requirement to return to the SWI
sequence, the auxiliary instructions can be deleted and exit from START becomes JMP NMISVC.
Note that the system initialization procedure should include provisions for clearing the NMIFLG flag.
Note also that IRQ is masked while the NMI flag (NMIFLG) is set to prevent an improper branch at
IRQ START.

Q 10.

When will the MPU recognize an IRQ pulse?

A 10.

The IRQ input is latched internal to the MPU providing the pulse duration is at least two MPU cycles.
Therefore, the MPU will recognize pulses active for two cycles. Three exceptions are to be noted as
follows:
1. If 1M

= 1 while a pulse occurs, the MPU will miss the interrupt.

2. If IRQ and NMI are active concurrently, the MPU will recognize NMI. In so doing, the interrupt
latches are reset and the IRQ pulse will be lost.
3. If IRQ occurs during an SWI instruction, the pulse will be lost because SWI clears the interrupt
latches.

Q 11.

What happens if an NMI occurs after an IRQ but before the MPU enters the IRQ service
routine?

All.

The instruction being executed when the IRQ occurred will be completed. The IRQ interrupt sequence
will be initiated and continue (for 9 cycles) until the MPU status has been stacked. Assuming that NMI
occurs during this interval, the MPU will select NMI since it has higher priority . (Note that iflRQ was a
pulse, it is permanently lost unless it lasts until the Interrupt Mask is cleared by software.) The MPU
fetches the starting address of the NMI service routine from locations FFFC and FFFD and begins
servicing the non-maskable interrupt. If the IRQ line is still low when the Interrupt Mask is cleared by
either a CLI during the NMI service routine or the RTI at the end of it, a normal IRQ will then be
initiated.

Q 12.

Assume 1m = 1, IRQ is active (low), and 1m on the stack = 0; then an RTI is encountered. Will one
instruction after the RTI be executed?

A 12.

No. the IRQ will be serviced prior to the instruction.

Q 13.

Assume 1m = 1, IRQ is active, and 1m on the stack = 1; then an RTI is encountered. Will the
interrupt be recognized after the RTI has executed?

A 13.

No. The next program instruction will be executed. IRQ will not be serviced until 1m is reset by
software.

Q 14.

Will the MPU recognize an interrupt occurring during the last cycle of an instruction during that
instruction?

A 14.

Yes. The interrupt must occur during the second to the last cycle of an instruction if it is to be
recognized during that instruction. The interrupt inputs are sampled during 4>2 and clocked during the
next 4> 1 so the interrupt must be present

= 200 ns prior to the end of the 4>2 in the last cycle of an

instruction if it is to be recognized during that instruction. The first cycle of any given instruction is
considered to be the OP CODE fetch from memory.
A-12

Q 15.

H the Interrupt Mask is set and an interrupt is pending, how fast does the MPU recognize the
interrupt after the mask is cleared by a eLI instruction?

A 15.

The interrupt will be serviced not more than one instruction after execution of the CLI. If the opcode of
the instruction immediately preceding the CLI instruction has a zero in its least significant bit position,
a pending interrupt will be recognized as soon as execution of CLI is complete. If there was a one in the
least significant bit position of the previous instruction's opcode, the instruction following the CLI will
be executed before the pending interrupt is recognized.
The Wait for Interrupt instruction (WAI) is often used to expedite the handling of interrupts by causing
the MPU to stack its contests and enter a waiting mode. It is normally used in anticipation of an
interrupt that requires the quickest possible handling. It is possible for the MPU to hang-up in the wait
mode if the WAI instruction is used following a Clear Interrupt Mask instruction (CLI) if the
anticipated interrupt is already pending when CLI executes and the interrupt is serviced as soon as the·
mask clears. Completion of the interrupt service routine will return the program to the W AI instruction
and cause the MPU to begin waiting for an interrupt that has already been serviced. If the opcode of the
instruction immediately preceding the CLI instruction had a one in its least significant bit position,
clearing of the Interrupt Mask by CLI is sufficiently delayed such that execution of the W AI instruction
begins before the interrupt can be recognized and the desired result is obtained. That is, W AI executes
and then the interrupt is serviced rather than vice versa. It is recommended that whenever W AI is
preceded by CLI, the CLI should be preceded by a NOP:

NOP
CLI
WAI

Use of the NOP insures that the least significant bit of the instruction preceding CLI will contain a one.

Q 16.

How is NMI masked once it is activated?

A 16.

The NMI is not masked. The NMI input is reactivated 3 cycles prior to executing the first instruction of
the service routine. Another NMI input will be recognized if a falling edge occurs after this time.

Q 17.

When are the IRQ and NMI reactivated during the interrupt service routine?

A 17.

Both are reactivated after the 9th cycle of the interrupt sequence, i.e. , after they have been tested to see
which interrupt input caused the sequence to start.

Q 18.

How fast can the MPU service an interrupt?

A 18.

The MPU can vector to the first instruction of the interrupt service routine in 13 ~ 23 clock periods
depending on what instruction is being executed and how far that execution has progressed at the time
of the interrupt.

A-13

Q 19.

Why is the interrupt mask placed in front of the IRQ flip-flop?

A 19.

The interrupt mask is placed prior to the IRQ flip-flop to prevent the flip-flop from being set again by
the present interrupt. The interrupt sequence sets the interrupt mask bit just prior to resetting the
interrupt flops.

Q 20.

How fast can an interrupt be serviced using the WAI instruction?

A 20.

Four MPU cycles are required to start the interrupt sequence after a WAI instruction

Q 21.

When is a puD up resistor required for the IRQ and NMI MPU inputs?

A 21.

When multiple signals are wired to the interrupt inputs, a 3.3KO pull up resistor is recommended.

Q 22.

WiD the MPU recognize IRQ and NMI when in a single instruction mode of execution, i.e., Gill
high for one cPt high clock cycle?

A 22.

The IRQ and NMI interrupts will not be recognized in this mode of operation.

Q 23.

When does the MPU recognize an IRQ or an NMI when the HALT line goes high and the
interrupt is present?

A 23.

The MPU will execute one instruction after the Go/Halt line goes high before the IRQ or NMI is
recognized.

Q 24.

What happens if an NMI occurs immediately after the RES line goes high?

A 24.

Since the stack is undefined at this time the MPU status will be stored at some unknown location in
memory, overwriting any RAM programs if the stack pointer happened to be pointing at them.
Similarly ifan IRQ occurs after the interrupt mask is cleared and before the stack pointer is initialized
the MPU status will be stored starting at an unknown location.
It is therefore recommended that the stack pointer be defined (using the LDS instruction) very early in
the program.

A-14

4 M6800 PROGRAMMING
Q 1.

What is meant by dual operand addressing?

A 1.

In computer terminology, "dual operand instructions" refers to instructions which reference two
values. The values may be specified as data (immediate operand), contents of a register, or contents of
a memory location.
In the MC6800, dual operand instructions reference an accumulator (register) and either data
(immediate operand) or a memory address:
IMMEDIATE DUAL
OPERAND INSTRUCTION

MEMORY REFERENCE
DUAL OPERAND INSTRUCTION

Add A #17

EOR B $8130
Operand # 1 =. Contents of B
Operand #2 = Contents of memory location
8130 (hex)

Operand # 1 = Contents of A
Operand #2 = 17 (decimal)

Q 2.

When is there an arithmetic carry?

A 2.

Add Instructions
Carry occurs when the sum of the binary operand values is greater than 255. When DAA follows an add
instruction carry occurs when the sum of the binary coded decimal values is greater than 99. Add
instructions include: ADD, ABA, and ADC.
Subtract Instructions
In subtract operations the condition code register carry (C) bit is used as a borrow bit. When the binary
subtrahend is greater than the minuend the C bit is set. Otherwise it is cleared. Subtract instructions
include: CMP, CBA, NEG SUB, SBA and SBC.

Q 3.

How is the H bit (bit 5) in the condition code register used?

A 3.

The "H" stands for Half-carry.
In the MC6800 two BCD digits can be obtained in one eight bit byte. Decimal addition is accomplished
by two instructions - an add instruction followed by a DAA (Decimal Adjust Accumulator)
instruction.
The MC6800 add instructions are binary adds. The H bit is set during the add when the binary sum of
the low order decimal digit (bits 0-3) exceeds 15. When the binary sum is less than or equal to 15 the H
bit is cleared. The DAA instruction then uses the H bit to determine how the result of the add must be
adjusted to convert the binary sum to decimal. The H bit is affected by the following add instructions:
ADDA, ADDB, ABA, ADCA, and ADCB. The H bit is not tested by any branch instructions. If it is
desirable to test the H bit a program routine can be written.

Q 4.

How is decimal subtraction accomplished?

A 4.

There is no Decimal Adjust Subtract instruction for the MC6800. Decimal subtraction is accomplished
by using 9's complement arithmetic. The 9's complement of the subtrahend is found and then added to

A-15

the minuend plus 1. The 9' s complement of a decimal number is found by subtracting each digit from
nine. The following subroutine is a decimal subtract routine of 16 digit numbers.

• DECIMAL SUBTRACT SUBROUTINE FOR 16 DECIMAL DIGIT
• TH 1: : : tw::UU TINE :SUBTRACTS THE SUBTRAHEND <: SUBTRH
• FROM THE MI N~JEND (" MI NUEN ") AND PLACES THE
• II I FFE~:ENCE I N RSL T •
II

II:5:UB
Ir:S:UB 1

LII:X:
LDA
SUB
:5:TA
DE:X:
BNE
LII:X:
:S:EC
LDA
AIIC
DAA
STA
DE:>::
BNE
RTS

II:S:UB2

)

~~:3
SET B'rTE COUr-iTER
A ~~$'39
FINII 9···:5: COMPLEMENT
A :5:UBTRH ,X
U:5:E RSLT" A:5: TEMP STORE
A RSLT,X
DECREMENT BYTE COUNTER
II:5:UBl
LOOP UNTIL LAST B,YTE
~~:3
RESTORE B'y'TE COUNTER
:5:ET CARRY TO ADD 1 TO COMPL
LOAD MINUEND
A MINUEN,X
ADD CO~lPLEf'lENT SUBTRAHEND
A F.:SL T ,:x:
DECIMAL AD.JUST
S:TORE DIFFERENCE
A R:S:L T ,:x:
DECREMENT B'y'TE COUNTER
D:S:UB2
LOOP '-'tiT I L LAST BYTE
F.:ETURN TO HOST PROGRAM
II

• THE EXECUTION TIME OF THIS SUBROUTINE IS
• 384 MPU CYCLES EXCLUDING THE RTS.

Note that if the subtrahend is less than or equal to the minuend a positive 16 digit difference results.
This is known as unsigned 16 decimal digit precision subtraction. The preceding subroutine Call also be
used for signed (algebraic) subtraction. In this case the precision is 15 decimal digits. The high order
digit position is used to indicate the sign of the number. A zero in the high order digit means positive
and the remaining 15 decimal digits are in true binary coded decimal format. A 9 in the high order digit
means minus and the remaining 15 decimal digits are in 9' s complement binary coded decimal format.

Q 5.

What is the difference between the:
BGT and BHI instructions?
BLE and BLS instructions?

A 5.

BGT -

Branch if Greater Than

BHI -

Branch if Higher

BLE BLS -

Branch if Less Than or Equal To
Branch if Less Than or Same

The BGT and BLE instructions are used to test the result of a signed binary operation. The BHI and
BLS instruction is used to test the result of an unsigned binary operation.
A-16

When using signed binary notation the high order bit of a byte represents the sign of the value. A "0" in
bit seven means positive and a" 1" means negative.
In unsigned binary notation, bit 7 of the number implies a weight of 128.
The correlation between signed and unsigned branch tests subsequent to a subtract or compare
instruction is as follows:
ACC = Accumulator value of tested instruction.
OPRND = Operand value of tested instruction.
SIGNED TEST

UNSIGNED TEST

ACC < OPRND

BLT

ACC < OPRND
ACC 5> OPRND
ACC 5> OPRND

BLE

BCS
BLS

BGE
BGT

BCC
BHI

Q 6.

When using the TSX instruction why is the value in the stack pointer register increased by I?

A 6.

When stacking data in memory the MC6800 first addresses the memory location referenced by the
stack pointer register and stores the data. Then the value in the stack pointer register is decremented by
one to point to the next stack address.
The TSX instruction adds one to the stack pointer register value as it is transferred to the index register
so that the index register is pointing at the last address of the stack that has stacked data. The TXS
instruction subtracts one from the index register value as it is transferred to the stack pointer register to
reverse the operation.
The value stored in the stack pointer register is not changed due to the execution of the TSX instruction.
Likewise, the value stored in the index register is not changed due to the TXS instruction

Q 7.

How fast can data be transferred via aPIA?

A 7.

There are two types of data transfer-synchronous and asynchronous. In synchronous data transfer the
source of the data transfer clock is derived from the M6800 system timing. In asynchronous data
transfer the data transfer clock is derived separately from the M6800 system timing.
In the following examples it is assumed that the number of words transferred is known prior to entry
into the data transfer routine.
EXAMPLE 1: 8-bit Word Synchronous Read Transfer
NOTE: Accumulator B is the word counter.
LOOP

LDAA
PSHA
DECB
BNE

PIAPRA

LOOP

FETCH DATA
STORE DATA
DECREMENT WORD COUNTER
LOOP UNTIL DONE

Executive time @ 1 /Ls/cycle = 14 /LS
Max data rate = 71.4K words/sec.

A-17

EXAMPLE 2: 8-bit Word Asynchronous Read Transfer
NOTE: a) Accumulator B is the word counter.
b) PIA Control Register A, bit 7 = 1 signifies a word is ready for transfer.
LOOP

LDAA
BPL
LDAA
PSHA
DECB
BNE

PIACRA
LOOP
PIAPRA

FETCH CONTROL WORD
WAIT FOR WORD READY
FETCH DATA
STORE DATA
DECREMENT WORD COUNTER
LOOP UNTIL DONE

LOOP

Execution time @ I/Ls/cycle = 22 /LS.
Max data rate = 45.4K words/sec.
EXAMPLE 3: 8-bit Word Asynchronous Write Transfer
NOTE: a) Index register is the word counter.
b) PIA Control Register B bit 7 = 1 signifies a word transfer is requested by the peripheral.
LOOP 1
LOOP 2

LDAA
LDAB
BPL
STAA
LDAB
DEX
BNE

DATA, X
PIACRB
LOOP 2
PIAPRB
PIAPRB

FETCH DATA FROM MEMORY
FETCH CONTROL WORD
WAIT FOR WORD REQUEST
MOVE WORD TO PIA
CLR CRB, BIT 7
DECREMENT WORD COUNTER
LOOP UNTIL DONE

LOOP 1

Execution time @ 1 /Ls/cycle = /Ls.
Max data rate = 33.3K words/sec.
EXAMPLE 4: I6-bit Asynchronous Word Read Transfer
NOTE: a) Accumulator B is the word counter.
b) PIA Control Register A, bit 7 = 1 signifies a word is ready for transfer.
LOOP

LDAA
BPL
LDAA
PSHA
LDAA
PSHA
DECB
BNE

PIACRA
LOOP
PIAPRB

FETCH CONTROL WORD
WAIT FOR WORD READY
FETCH HIGH ORDER BYTE
STORE HIGH ORDER BYTE
FETCH LOW ORDER BYTE
STORE LOW ORDER BYTE
DECREMENT WORD COUNTER
LOOP UNTIL DONE

PIAPRA

LOOP

Execution time @ I/Ls/cycle = 3 /LS.
Max data rate = 33.3K words/sec or 66.7K bytes/sec.
The maximum data rates shown in the preceding examples represent simple transfer tasks using
software polling rather. than interrupt service requests. It should be noted that if any other tasks that
must be performed while transferring data would reduce the maximum data rate.

A-I8

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