MC141000 Series Programming Manual 1978
MC141000_Series_Programming_Manual_1978 MC141000_Series_Programming_Manual_1978
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MC141000 Series PROGRAMMING REFERENCE MANUAL The information in this document has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the product described any license under the patent rights of Motorola Inc. or others. Motorola reserves the right to change specifications without notice. © MOTOROLA INC., 1978 2 TABLE OF CONTENTS INTRODUCTION ..................................................................... 6 MC141 000/1200/1 099 Microcomputers Microprogramming MC141000 Family Support Products MC141000 Microcomputer Resources ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8 Functional Blocks Status and Status Latch Power Up and Initialize Assembly Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 Coding Format Input Format Comments Labels Operands Assembler Directives Additional Documentation Instruction Tables .................................................................. 11 Functional Listing Alphabetical Listing Machine Operation ................................................................. 13 ROM Array Branch, Call and Return Operations Random Access Memory (RAM) Output Ports Inputs Arithmetic Logical Unit (ALU) Instruction Decode Instruction Details .................................................................. 18 Applications and Software Examples ................................................ 34 BCD Addition BCD Subtraction LCD Display LCD Display plus Keyboard Expanding Number of R-Outputs External RAM Storage ILLUSTRATIONS Figure 1 The MC141000 ............................................................. 6 Figure 2 EXORciser-Based Software Development System ............................ 7 Figure 3 MC141099-Based Software Development and Debug System . . . . . . . . . . . . . . . .. 7 Figure 4 Motorola Custom Software and Debug Development System ..................... 7 Figure 5 Functional Block Diagram - MC141000/1200/1099 ............................ 8 Figure 6 Internal BR, CALL and RETN Operations ..................................... 13 Figure 7 BR, CALL and RETN Summary ............................................. 14 Figure 8 RAM Addressing and BIT Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 Figure 9 Output PLA Configured for Seven-Segment Display. . . . . . . . . . . . . . . . . . . . . . . . . . .. 16 3 Table 1 Power Up and Initialize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9 Table 2 MC141 000/1200 Standard Instruction Set, Functional Listing ...................... 11 Table 3 MC141000/1200 Standard Instruction Set, Alphabetical Listing .................... 12 Applications and Software Examples BCD Addition and Subtraction Flowchart ........................................35 LCD Display Hardware and Software ...........................................36 LCD Display Plus Keyboard Hardware ..........................................37 Software ....................................................................38 Expanding the number of R-Outputs, Hardware and Software ................................................................39 External RAM Storage Hardware and Software ................................. .40 LIST OF ABBREVIATIONS A ALU Accumulator Arithmetic Logic Unit CKI CL Constant and K-Input Logic Call Latch I(B) I(C) I(W) Bit Field of Instruction Constant Field of Instruction Branch Address of Instruction Ki K inputs LSB LSD Least Significant Bit Least Significant Digit MSB MSD Most Most M(X,V) RAM M(X,V,B) RAM Significant Bit Significant Digit Memory Location = X Address (0 to 7), Y Address (0 to 15) Memory Bit Location (B = 0, 1,2, or 3) a Output Register PA PC PLA PLAIR ROM Page Address Register ROM Page Buffer Register Program Counter Programmable Logic Array PLA Input Register R R(V) RAM ROM R-Output Register R-Output Latch Y Random Access Memory (Read/Write) Read Only Memory S SL SRR Status Status Latch Subroutine Return Register x RAM X Address Register v RAM Y Address Register PB 4 5 INTRODUCTION MC141000/1200/1099 Microcomputers Figure 1. The MC141000 - A Single-Chip Microcomputer featuring CMOS Technology. The MC141000 and MC141200 single-chip microcomputers are complete four-bit microcomputers which contain read-only program memory, random-access memory, arithmetic logical unit, buffered inputs, and output drivers. The MC141200 has 16 outputs (R lines) in a 40-pin package. The MC141000 is a limited pinout version with 11 R outputs in a 28-pin package. Electrical and mechanical specifications can be found on the MC141 000 and MC141200 Data Sheet. The MC141099 is a 48-pin version of the MC141200, intended primarily as a design tool for prototyping and debugging MC141 000/1200 systems prior to manufacture. As such, it is designed for use with external programmable logic (PLA) and memory and does not have these functions on-chip. The larger number of package pins permits interfacing with these external functions. Microprogramming If the standard instruction set, Page 11, is found to be inadequate to meet the requirements of a specific application, the instruction set may be modified to a limited extent by redefining the instruction-decode programmable logic array. Please consult the Motorola MOS Facility in Austin, Texas for details. 6 MC14100 Family Support Products To support the MC141000 microcomputer family, Motorola offers a complete hardware /software package for the development of a user system through system simulation, Figure 2. The software package consists of a cross-assembler, a loader and debugging capability. The hardware consists of a dedicated component board (MEX141000M) that interfaces with Motorola's standard EXORciser*, permitting its use as an MC141 00 system simulator. The system runs under the control of the MOOS operating system and provides powerful development and debug capability prior to commitment to final production masks. The debug phase of program development is expedited by use of the SIMULATOR breakpoint, trace, and single-step features, and the relative ease of program changes on a diskbased development system. Detailed information concerning this system is available in the MC141000 CROSS-ASSEMBLER MANUAL and the MC141000 SIMULATOR MODULE MANAUL. A hardware approach to system development and debug can be implemented with the MC141099 processor. It is identical to the MC141200 with the exceptions that the program storage memory and output PLA are external, Figure 3. RAM, PROM or EPROM memory can be used for program storage and a PLA decoder or random logic can be used to simulate the output PLA. For those who prefer to purchase a turnkey device, Motorola offers an in-house design, programming and development capability. Figure 4 outlines a typical development program from software specification to device production. Your local sales representative can supply cost and scheduling information for this service. Cable 28 or 40 Pm Plug ""'r--1 User's 141000/1200 System Simulator Hardware 141000/1200 Simulator Board EXORciser Terminal Figure 2 - EXORciser Based Software Development System MC141000/1200 SIMULATOR K INPUTS USER'S HARDWARE R-OUTPUTS O-OUTPUTS Figure 3 - MC141099 Based Software Development and Debug System *EXORciser is a trademark of Motorola Inc. CHANGES Figure 4 - Motorola Custom Software and Debug Development Schedule 7 A Outputs _6 CONSTANT & K-INPUT MULTIPLEXER EXTERNAL WITH MC141099 r-----'I I I I OUTPUT PLA I I _____ .JI L Figure 5 - Functional Block Diagram - MC141 000/1200/1099 MC141000 MICROCOMPUTER RESOURCES FUNCTIONAL BLOCKS Figure 5 shows a block diagram of the resources available to the MC141000/1200/1099 programmer. They are: A The accumulator is used to store the result of an ALU operation for subsequent operations. ALU The arithmetic logical unit perform calculation and decision-making tasks. KINPUTS The K lines are the data input port. Since there are only four input lines, they are usually multiplexed under control of the R lines using external hardware. The inputs are diode protected and have a pull-down resister of approximately 50 K ohms; therefore, open inputs are read as a logic low. a OUTPUTS PLA PLAIR The eight outputs of the PLA are connected to output drivers which comprise the a-outputs. These output drivers may be manufactured as open emitter, active sink, or push-pull at the user's option. The output programmable logic array is user-defined to specify the state of each of the eight a-outputs for each of the 32 possible PLAIR outputs. ROM ARRAY The user's instructions are mask programmed into the Read Only Memory (ROM). Instructions are addressed by a page address register (PA) and program counter (PC). A single subroutine return register (SRR) and page buffer register (PB) permit subroutine calls to any location within theHOM. R OUTPUTS The output of the Y register is decoded to select one of the R-output lines which can then be set or reset under program control. The R lines are used as control lines to scan keyboards and displays, perform handshakes, and interface external logic. The R-outputs may be manufactured as open emitter, active sink, or push-pull at the user's option. S All branches and subroutine calls are dependent on the state of status logic. It may be set or reset on logical or arithmetic operations and is set by the remainder of the instructions. SL The status latch latches the state ofthe status logic in order to preserve it for subsequent a-output operations. The programmable logic array input register is a five-bit latch which latches the four accumulator bits and output of the status latch. NOTE: Sand SL are NOT identical. Y REGISTER RAM Variable data is stored in the 64-word, 4-bit per word Random Access Memory. Data is accessed by decoding a 2-bit file address (X register) and 4-bit word address (Y register). 8 The Y register is a multipurpose register used to address a word in a RAM file, to select an R output for manipulation by subsequent instructions, or as a general purpose counting and storage register. Status and Status Latch All program-modifying instructions (BRanch or CALL) are conditional on the state of the status logic. If status is set, the BRanch or CALL is executed by jumping to the ROM address specified by the operand field of the BRanch or CALL instruction and the contents of the page buffer register (PB). If status is reset, the BRanch or CALL is not to be taken, and the instruction following the BRanch or CALL is the next to execute. The BRanch or CALL takes six clock cycles (one instruction cycle) to execute whether the status is set or reset. The status logic is normally set. Whenever it is reset, the reset condition only lasts for one instruction cycle and then returns to the set state. The only means to keep it reset for more than one instruction cycle is to execute more than one instruction in series which causes it to reset in series. The status latch takes the state of the status logic and saves it during the execution of a YNEA instruction. Power on reset and INIT have no effect on the status latch. Therefore, a YNEA instruction must be executed before a TDO instruction to ensure that the desired state of status latch is placed into the PLA input register. Power Up and Initialize TABLE 1. Power Up and Initialize PC PA PB CL PLAIR R OUTPUTS Power Up 0 15 15 0 0 0 Initialize 0 K K 0 0 0 When power is applied, the registers shown in Table 1 are loaded as shown for power up. All other internal registers and RAM come up in an arbitrary state. After power is applied, the initialize (INIT) input may be used to reinitialize the processor. Internally, INIT has a 50 K ohm pull-down resistor which holds the INIT line low. It must be held high for a minimum of 6 full clock cycles and then returned to the low state. If a mechanical switch or other mechanical device is used to control INIT, it may be necessary to include a method of contact debounce to ensure a valid INIT pulse. A valid INIT pulse will cause the registers to be loaded as shown in the table. The contents of registers other than those shown will remain unchanged during initialize. Note that the PA and PB are loaded with the 1's complement of the K-input lines (Ka =MSB). This feature allows the MC141000 to be initialized to the first instruction on any page by controlling the K-inputs during initialization. This is useful where the same circuit may be used for several applications. Since the K-inputs have 50 K pull-down resistors, they will be a 0 (unless driven from another device) and the 1's complement (F) will be loaded into PA and PB. 9 MOTOROLA MC141000 ASSEMBLY FORMAT Coding Format Users who choose to develop their own software should provide assembler-compatible code conforming to the assembler input rules. The following syntax rules will allow user-generated source code to be assembled on any of the Motorola MC141000 cross-assemblers. Input Format 11 I 2 13 14 15 I 6 17 I 8I 91 10 111 11211-31141151161171181191201 21 122123124125126127128129130 131 132 133 1 k * Label Field Operator Field *' Operand Field * Comment ~ Field Labels Labels are a maximum of six alphanumeric characters. (Columns 7, Band 9 are not used.) The first character must be alphabetic. Labels may not contain imbedded blanks. Assembler mnemonics and directives must not be used as labels. Valid characters are: A through Z o through 9 = Comments An asterisk in column 1 indicates that the entire line is a comment. Operands Operands must be non-negative decimal constants or valid labels. Assembler Directives All versions ofthe Motorola MC141000 assembler support the following assembler directives (pseudo-ops). Assembler directives must start in COL 10. ORG nnnn (Where nnnn is a decimal number) This causes the assembler to place the machine code at offset nnnn. Any number of ORGs may be used, but they must always be in ascending order. EJECT This causes the printer to go to top of form. PAGE Similar to ORG but causes the next instruction to be placed at location 00 of the next sequential ROM page. label 1* BL Label 2 "BRANCH LONG" Causes two machine instructions to be generated. First an LOP to the page of Label 2, than a BR to that label. label 1* Call L Label 2 "CALL LONG" Causes two machine instructions to be generated. First an LOP to the page of Label 2, then a BR to that label. *Optional Several versions of the cross-assembler are in use at Motorola and some have more extensive capabilities than those outlined above. For more information on source-code submittal, please consult the Motorola MOS Facility, Austin, Texas. Additional Documentation Detailed hardware specifications for the MC141 000/1200/1 099 are available in the data sheet, and information concerning the M6BOO EXORciser-based MC141000/1200 development! debug system is contained in the MC141000 CROSS-ASSEMBLER MANUAL and the MC141000 SIMULATOR MODULE MANUAL. Your local distributor or Motorola sales representative can supply documentation. 10 INSTRUCTION TABLES The MC141000 microcomputer instruction set consists of 43 standard instructions. These are summarized in Table 2, which lists the instructions by function, and Table 3, which lists the instructions alphabetically. TABLE 2. MC141000/1200 Instruction Set, Functional Listing Function Mnemonic Condition Setting Status Action ROM Addressing BR CALL LOP RETN Always Always Always Always See Fiq. 7 See Fig. 7 I(C) ~ PB See Fig. 7 RAM X Addressing COM X LOX Always Always X~X Output CLO RSTR SETR TOO Always Always Always Always o ~ PLAIR o ~ R(Y) KNEZ TKA K-inputs not zero Always K CLA TAM TAMIY TAMZA TAY TCY TCMIY TMA TMY TYA XMA Always Always Always Always Always Always Always Always Always Always Always Input Internal Oata Transfer ~, I(B) ~ X 1 ~ R(Y) SL,A ~ PLAIR ~ 0 K~A O~A A A A ~ M(X,Y) M(X,Y), Y + 1 ~ Y ~ M(X,Y), 0 ~ A ~ A~Y I(C) ~ Y I(C) ~M(X,Yt, Y + 1 ~Y M(X,Y) ~ A M(X,Y) ~ Y Y~A M(X,Y)~A o ~ M(X,Y, B) Bit RBIT Manipulation SBIT TBIT1 Always Always Bit equal to 1 Arithmetic A6AAC A8AAC A10AA AMAAC CPAIZ OAN OMAN OYN IA IMAC IYC SAMAN Carry Carry Carry Carry Carry Carry Carry Carry Always Carry Carry If no borrow A+6~A ALEC ALEM MNEZ YNEA YNEC Accumulator less than or equal to constant Accumulator less than or equal to memory Memory not equal to zero V-register not e~ual to accumulator V-register not equal to constant A ~ (C) A ~ M(X,Y) M(X,Y) ~ 0 Y ~ A,S ~SL Y ~ (C) Logical 1 ~ M(X,Y, B) M(X,Y, B) = 1 A+8~A A + 10 ~A M(X,Y) + A ~ A A+1~A A-1~A M(X,Y) - 1 ~A Y-1~Y A+1~A M(X,Y) + 1 ~ A ~ A Y+1~Y M(X,Y) - A 11 TABLE 3. MC141000/1200 Standard Instruction Set, Alphabetical Listing Opcode Description Mnemonic 0111 (C) 00101001 00100101 00000110 00000001 00000101 10 (W) 11 (W) 00101111 00001011 00000000 00101101 00000111 00101010 00101100 00001110 00101000 00101011 00001001 0001 (C) 001111 (B) 00100110 001101 (B) 00001111 00001100 00100111 ALEC ALEM AMAAC A6AAC A8AAC A10AAC BR CALL CLA CLO COMX CPAIZ DAN OMAN DVN IA IMAC IVC KNEZ LOP LOX MNEZ RBIT RETN RSTR SAMAN 001100 (B) 00001101 00000011 00100000 00000100 00100100 001110 (B) 0100 (C) 0110 (C) 00001010 00001000 00100001 00100010 00100011 00101110 00000010 0101 (C) SBIT SETR TAM TAMIV TAMZA TAV TBIT1 TCV' TCMIV TOO TKA TMA TMV TVA XMA VNEA VNEC If accumulator is less than or equal to I(C) field, status = 1. If accumulator is less than or equal to M(X,V), status = 1. Add memory to accumulator. Accumulator = result, status = carry. Add 6 to accumulator. Accumulator = result, status = carry. Add 8 to accumulator. Accumulator = result, status = carry. Add 10 to accumulator. Accumulator = result, status = carry. Branch to label if status = 1. Call subroutine if status = 1. Clear contents of accumulator. Clear PLA Input Register. Complement X-Register. Complement accumulator, then add 1. If accumulator = 0, status = 1. Decrement accumulator. If no borrow, status = 1. Load M(X, V) into accumulator and decrement. If no borrow, status = 1. Decrement V-register. If no borrow, status = 1. Increment accumulator. Load M(X, V) into accumulator and increment. Status = carry. Increment V-Register. Status = carry. If K-inputs not equal to zero, status = 1. Load page buffer with I(C) field. Load X-register with I(B) field. If M(X, V) not equal to zero, status = 1. Reset bit I(B) of M(X,Y). Return from subroutine. Reset R-line specified by V-register. Subtract accumulator from memory. Accumulator = result. If no borrow, status = 1. Set Bit I(B) of M(X,V). Set R-line specified by V-register. Transfer accumulator contents to M(X,V). Transfer accumulator contents to M(X,V), increment V-register. Transfer accumulator contents to M(X,V), zero accumulator. Transfer accumulator contents to V-register. If bit I(B) of M(X,V) is one, status = 1. Transfer I(C) field to V-register. Transfer I(C) field to M(X,V), increment V-register. Transfer status latch and accumulator to O-output' register. Tranfer K-inputs to accumulator. Transfer M(X, V) to accumulator. Transfer M(X, V) to V-register. Transfer V-register contents to accumulator. Exchange contents of M(X, V) and accumulator. . If V-register is not equal to accumulator, status and status latch = 1. If V-register is not equal to I(C) field, status = 1. 12 MACHINE OPERATION The MC141000 microcomputer consists of 6 subsystems: 1) 2) 3) 4) 5) 6) Read Only Memory (ROM) Random Access Memory (RAM) Output ports Input port Arithmetic Logical Unit (ALU) The Instruction Decoder The following sections will describe how each of these subsystems is controlled by the instruction set. Every instruction occupies a single memory byte and is executed in one instruction cycle (6 clock cycles). ROM Array The ROM consists of 8192 bits of mask-programmed memory organized as 1024 8-bit instructions. It is divided into 16 pages of 64 instructions per page. Instructions within ROM are addressed by the page address register (PA) which contains the page number, and the program counter (PC) which contains the location of the instruction relative to the beginning ofthe page. The PC is incremented prior to fetching the next instruction (unless diverted by a BRanch or CALL) so each instruction is accessed in the numerical order of its address. A carry from the PC is not added to the PA so the program will "wraparound" within the page rather than executing the first instruction of the following page. Upon power up, the PC is set to zero and the PA and PB are set to 15. Branch, Call and Return Operations - Figure 6 The normal sequence of instruction execution may be diverted by branch (BR) or subroutine call (CALL) instructions which are conditional on the state of the status logic. If the status equals one, the BR or CALL will be executed. If the status is zero the instruction following the BR or CALL will be executed. BR (Branch) A successful BR causes the PC to be loaded from the last six bits I (W) of the BR instruction. If the call latch (CL) is zero, the PA will also be loaded from the PB; however, if the CL is one, the PAwili not be altered. A load page (LOP) instruction can be used prior to a BR to cause program control to be transferred anywhere within the ROM. Note: A BR within a subrolltine CALL is limited to a short branch within the same page in order to preserve the subroutine return address. Figure 6 - Internal BR, CALL and RETN Operations 13 Status Logic Instruction BR (Branch) CALL (Call subroutine) RETN (Return from subroutine) * PA PB PC Call Latch Action 1 0 I(W) ~ PC, PB 1 1 I(W) ~ PC 0 *0 PC + 1 ~ PC, 1 0 PC + 1 ~SRR,I(W)~PC, PA~PB, 1 ~CL 1 1 I(W) 0 * PC * 1 SRR ~ PC, PB ~ PA, 0 ~ CL * 0 PC Don't Care Page Address Register Page Buffer Program Counter ~ PC, PA + 1 ~ PC, +1 ~ ~ PA 1 ~ Status ~ PB 1 ~ Status Logic PC, PB ~ PA SRR = Subroutine Return Register CL = Call Latch I(W) = 6 Least Significant Bits of a Call or BR Figure 7 - BR, CALL and RETN Summary CALL The CALL instruction permits the use of subroutines in MC141000 programs. The successful CALL instruction causes: 1) 2) 3) 4) the the the the PC to be PC to be call latch PB to be incremented and stored in the subroutine return register (SRR) loaded from the six least significant bits of the CALL instruction (CL) to be set to one exchanged with the PA Since there is a single level of subroutine-return-address storage, nested subroutines are not permitted. A CALL within a subroutine will cause the return PB to be loaded with the PA. Branch instructions beyond the current page are not permitted within a subroutine since the PB is used as the storage register for the subroutine return page address. RETN The return from subroutine instruction (RETN) causes the PC to be loaded from the SRR, the PA to be loaded from the PB, and the CL to be reset. BR and CALL Summary - Figure 7 The conditions imposed on Branch and Call instructions are: 1) they will only be executed when status is set 2) a long BR or CALL off the current page will result if the PB is loaded by an LDP instruction prior to execution of the BR or CALL 3) only branches within the current page are allowed within a subroutine 4) instruction execution requires six clock cycles whether or not the BR or CALL was successful 14 X Register Select File 0 Y Register Select Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word File 1 File 2 File 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1(8) = 3 1(8) = 2 1(8) = 1 1(8) = 0 l' JJ Figure 8. RAM Addressing and Bit Selection Random Access Memory - RAM RAM consists of 256 bits organized into 64 4-bit words. For purposes of addressing, the 4-bit words are organized into four files of 16 4-bit words per file, Figure 8. The X register is decoded to select one of the 4 RAM files; and the Y register is decoded to address one of the 16 words in the selected file. Instructions which can be used to select the RAM file are the LOX which loads the X register from ROM, and the COMX instruction which complements the X register. The Y register can be loaded from ROM (TCY) , from RAM, (TMY) , or the accumulator (TAY). The Y register can also be incremented (IYC, TCMIY and TAMIY) and decremented (OYN). Individual bits within the RAM can be set (S8IT), reset (R8IT), and tested (T8IT1) under program control. The RAM word to be operated on is defined by the X and Y registers, and the 2-bit 8 field of the bit manipulation instruction selects the bit to be operated on. Instructions which directly access RAM are: ALEMAMAACDMANIMACMNEZSAMANTAMTAMIYTAMZATMATMYXMA- Accumulator less than or equal to memory Add memory to accumulator, store result in accumulator Load accumulator with decremented memory contents Load accumulator with incremented memory contents Compare for memory not equal to zero Subtract the accumulator from the memory and store the result in the accumulator Transfer accumulator to memory Transfer accumulator to memory, increment Y register Transfer accumulator to memory, load the accumulator with zero Transfer memory to accumulator Transfer memory to Y register Exchange memory and accumulator 15 Since the Y register is an integral part of the memory addressing scheme, Y register manipulation instructions are important to RAM. The Y register can be changed by the following instructions: IYCDYNTAYTCYTMYTAMIYTCMIY- Increment the Y register Decrement the Y register Transfer accumulator to Y register Load the Y register with a constant Transfer memory to Y register Transfer accumulator to memory, increment to Y register Transfer constant to memory, increment Y register 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132 07 06 05 04 a Outputs 03 02 01 00 Seven Segment Display Output 0, o Output Connections To Seven Segment Display Figure 9 - Output PLA Configured for Seven-Segment Display Output Ports Two output ports (R and 0) are included in the microcomputer. The MC141000 has 11 R-outputs and the MC14200 has 16 R-outputs while both machines have eight O-outputs. The number of R-outputs is the only difference between the MC141000 and the MC141200. R-output lines are used primarily as control or "handshake" lines, and to mutiplex external hardware. The R-output which is to be operated on is selected by a binary decode of the contents of the Y register and is set by the SETR instruction and reset RSTR instruction. The eight O-output lines are the decoded output of the contents of the 5-bit PLAIR. Since the PLAIR is loaded from the A and the SL, these registers must be "set up" prior to an output operation. The status latch can only be loaded by the YNEA (Y register not equal to accumulator) instruction while the contents of the accumulator may be modified by numerous other instructions. The 0 output instructions are: TOO CLO - Transfer data from the accumulator and status latch to the PLAIR Clear PLAIR, i.e., load with zeros In a typical application, the first four R lines might be used as digit selects for outputting a four-digit decimal number using the PLA programmed as a seven-segment decode as shown in Figure 9. The software needed to accomplish this task is shown in the application sections. Inputs The input lines consist of the four K-input lines and the initialize (IN IT) line. The two input instructions are: KNEZ TKA - If the K input lines are not equal to zero, set the status logic to one Transfer the contents of the four input lines to the accumulator Operation of the INIT is described previously (Table 1). 16 Arithmetic Logical Unit (ALU) The ALU is the calculating and decision-making portion of the MC141000 hardware and consists of a 4-bit adder/comparator and the status logic. The status logic will be selectively set or reset by add, subtract, increment, decrement, compare and bit-test operations. Other instructions always set the status logic to a one. The adder/comparator can add, subtract, compare two numbers, add +1, -1, 6, 8, and 10. The logical instructions are: The arithmetic instructions are: ALEM- AMAAC- Add memory to accumulator, results to accumulator. Carry to status SAMAN- Subtract accumulator from memory, results to accumulator. If no borrow, one to status IMACLoad memory into accumulator, increment accumulator. Carry to status DMANLoad memory into accumulator, decrement accumulator. If no borrow, one to status IAIncrement accumulator, no status effect IYCIncrement Y register. Carry to status DANDecrement accumulator. If no borrow, one to status DYN Decrement Y register. If no borrow, one to status A8AAC Add 8 to accumulator, results to accumulator. Carry to status A 1OAAC - Add 10 to accumulator, results to accumulator. Carry to status A6AAC Add 6 to accumulator, results to accumulator. Carry to status CPAIZ Complement accumulator increment. If zero, one to status ALECKNEZMNEZTBIT1 YNEAYNEC- Instruction Decode The instruction decode logic latches every instruction fetched from ROM and configures the internal logic to correctly execute the curthe current instruction. The MC141000 includes within the instruction decode logic the capability of modifying the standard instruction set. Typical examples of useful nonstandard instructions are: SRDYTDOIYTKMANEM- Set R-Output and decrement Y Transfer A and SL to PLAIR and increment Y Transfer K inputs to memory and increment the Y Register A not equal to M(X, Y) The factory should be consulted for feasibility of specific instruction-set modifications. 17 If accumulator less than or equal to memory, one to status If accumulator less than or equal to a constant, one to status If K-inputs not all zero, one to status If memory not equal to zero, one to status If the selected bit is one, one to status If Y register not equal to accumulator, one to status and status latch If Y register not equal to a constant, one to status INSTRUCTION DETAILS On the following pages, the MC141000 Instruction Set is described in detail. The descriptions use the following format: MNEMONIC INSTRUCTION DEFINITION ACTION: Symbolically shows the instructions effect. One or more cases may be shown here, depending on the instruction. DESCRIPTION: Explains the instruction operation in detail. STATUS: Shows the effect of the instruction on the status logic. OPERATION: A diagramatic representation of the effect of the operation on pertinent registers. Register contents BEFORE execution and AFTER execution are shown. Any register not shown (with the exception of the PC) is unchanged by the instruction. Where two conditions may result from execution of an instruction, a diagonal line separates examples showing both results. OPERATION CODE: The binary code, including field designations. 18 ALEC IF ACCUMULATOR IS LESS THAN OR EQUAL TO CONSTANT, ONE TO STATUS. ACTION: A < I(C) A = I(C) A > I(C) 1~S 1~S O~S DESCRIPTION: If the contents of the accumulator are less than or equal to the C field of the instruction, the status will be set to one; if not, the status is set to zero. If the constant 15 is used, this instruction effectively becomes a no-op. STATUS: Set if A :::::; constant, reset if not. OPERATION: BEFORE AFTER OPERATION CODE: Registers I(C) 9/2 9/2 A 4 4 I °I1 I1 I1 I L-----L_-.L.-_...L-----I ~SB S * 1/0 c I I I MSB I ALEM IF ACCUMULATOR IS LESS THAN OR EQUAL TO MEMORY, ONE TO STATUS. ACTION: A < M(X, Y) A 1~S 1~S A > M(X, Y) = M(X, Y) O~S DESCRIPTION: If the contents of the accumulator are less than or equal to the contents of RAM file X, word Y status is set, if not status is reset. STATUS: Set if A :::::; RAM contents, reset if not. OPERATION: BEFORE AFTER OPERATION CODE: S * ° ---'-_....1.------JI...---.L-_--L..-_'---~ I I°I I° ° 1 0 _0-----JII...-- L-I Registers M(X, Y) 10/4 10/4 A 6 6 1/ 1 I I 1 I AMAAC ADD MEMORY TO ACCUMULATOR. LOAD RESULT INTO ACCUMULATOR. ACTION: A + M(X, Y) CARRY ~A ~S DESCRIPTION: The contents of RAM file X, word Yare added to the contents of the accumulator, and the result is loaded into the accumulator. The status is set if a carry results from the addition and reset if there is no carry. STATUS: Set if carry, reset if not. OPERATION: BEFORE AFTER OPERATION CODE: *Don't Care I ° I° A 4/9 12/1 1 1 1 Registers M(X, Y) S 8 8 * 0/1 ° ° 1 19 1 1 10 I 1 I A6AAC ADD SIX TO ACCUMULATOR. ACTION: A+6~A CARRY ~S DESCRIPTION: Six is added to the accumulator. If a carry results, the status is set. This instruction is commonly used for correction during BCD addition. STATUS: Set on carry, reset if not. OPERATION: Registers A S * 4/15 10/5 0/1 BEFORE AFTER OPERATION CODE: _o----JI'---0-.l-_.....L....._L...______L..._-'------L_~ I 0 I 0 I 0 I 1 I 1 I 0 I 1-1 A8AAC ADD EIGHT TO ACCUMULATOR. ACTION: A+8~A CARRY ~S DESCRIPTION: Add 8 to the accumulator. Set the status if a carry results. STATUS: Set on carry, reset if not. OPERATION: BEFORE AFTER OPERATION CODE: I 0 Registers S A 6/9 * 14/ 1 0/ 1 I0 I0 I0 I 0 I0 I 0 I1 I A10AAC ADD TEN TO ACCUMULATOR. ACTION: A + 10 ~A CARRY ~S DESCRIPTION: Ten is added to the accumulator. If a carry results, the status is set. This instruction is commonly used for correction during BCD subtraction.- STATUS: Set on carry, reset if not. OPERATION: BEFORE AFTER Registers A S * 3/9 13/4 0/1 0 I 0 0 OPERATION CODE:lL-_0----JI~0____L..._--'-_L...__---'_1 I I I I0 I 1I *Don't care 20 __'__'----___J BR BRANCH ON STATUS EQUALS ONE. ACTION: S = 1 CL = 0 I(W) ~ PC If Then BRANCH S = 1 CL = 1 I(W) ~ PC NO BRANCH S =0 CL = Don't Care PC+1~PC PB~PA DESCRIPTION: If the status is zero, the next sequential instruction after the branch will be executed and the program will not branch. If the status is set and the call latch is one, the program counter is loaded from the W field of the instruction and the program will branch within the page. Interpage branching is not successful if CL = 1. If the status is set and the call latch is zero, the page address will be loaded from the page buffer and the program counter will be loaded from the instruction, permitting a branch to anywhere in ROM. Execution of the BR instruction requires 6 clock cycles whether or not the branch is successful. STATUS: Set. OPERATION CODE: 1 I0 M_S_B...a-'_____W""----"....&.....-_I'--L_SB---'I 1--1 CALL CALL SUBROUTINE ON STATUS EQUALS ONE. ACTION: NO CALL CALL If S = 1 CL = 0 S =1 Then I(W) ~ PC PC ~SRR PB ~PA 1 ~CL I(W) CL S =0 =1 ~ PC PC+1~PC PA~PB DESCRIPTION: If the status is zero, the call is unsuccessful and the next sequential instruction after the call is executed. If the status is set and the call latch is one, the program counter is loaded from the W field of the instruction and the program will branch within the page and the return page may be lost. If the status is set and the call latch is zero, the page address and the page buffer are exchanged and the program counter is incremented, stored in the subroutine return register, and loaded from the W field of the instruction, permitting a branch to anywhere in ROM. STATUS: Set. .OPERATION CODE: W '----1_____ 1 --41 MSB I ILSBI 21 CLA CLEAR ACCUMULATOR. ACTION: O~A DESCRIPTION: STATUS: The accumulator is loaded with zero. Set. OPERATION: Registers A S 7 * 1 BEFORE AFTER OPERATION CODE: ° 1 1 1 1 1 1 1 1 1 _0---1....1_0----1._---'--_...1...-.-----1._--'-_"------' 1 1 1 L-I ° CLO CLEAR PLAIR OUTPUT. ACTION: ° DESCRIPTION: The five bits of the programmable logic array input register are set to zero. STATUS: Set. ~ PLAIR OPERATION: Registers PLAIR BEFORE AFTER * ° ° ° ° ° OPERATION CODE: I 1 1 1 1 1 1 ° 1 1 1 1 I COMX COMPLEMENT X REGISTER. ACTION: X~X DESCRIPTION: The contents of the X register are one's complemented. STATUS: Set. OPERATION: BEFORE AFTER OPERATION CODE: L...I Registers X S * 0/2 1 3/1 _0_1-1_0----L._-L-_L-----L._--L..---JL.-----I 1 ° I ° I ° 1 ° I 1 ° 1 ° *Oon't care 22 CPAIZ COMPLEMENT AND INCREMENT ACCUMULATOR. ACTION: A+1~A Carry ~ S DESCRIPTION: The accumulator is complemented and incremented. If a carry results status is set, no carry resets status. STATUS: Set on carry, reset if not. OPERATION: Registers A S * 3/0 13/0 0/1 BEFORE AFTER OPERATION CODE: I L-I_O_L......I_0---'-_-1------IL......----L-_-L.----I1......-----I I 1 I 0 I 1 I 1 I 0 I 1 DAN DECREMENT ACCUMULATOR. ACTION: A - 1 ~A 1 - Borrow ~ S DESCRIPTION: The contents of the accumulator are decremented by one. If no borrow results, the status is set to one. If the accumulator contains zero prior to execution, status is reset and the accumulator is set to 15. STATUS: Set on no borrow, reset on borrow. OPERATION: BEFORE AFTER OPERATION CODE: I 0 Registers A S 9 / 0 * 8 / 15 1/ 0 I0 I0 I0 I0 I1 I1 I1 I OMAN DECREMENTED MEMORY INTO ACCUMULATOR. ACTION: M(X, Y) - 1 ~ A 1 - Borrow ~ S DESCRIPTION: The contents of M(X, Y) are loaded into the accumulator and decremented. The status is set only if M(X, Y) = 0, A = F. M(X, Y) is not modified by this operation. STATUS: Set if no borrow, reset if borrow. OPERATION: BEFORE AFTER OPERATION CODE: A * 3/15 Registers M(X, Y) 4/0 4/0 S * 1 /0 I I I I I I I I I 0 0 1 1 0 *Don't care 23 0 1 0 DYN DECREMENT Y REGISTER. ACTION: Y-1~Y 1 - Borrow ~ Status DESCRIPTION: The Y register is decremented by 1. If no borrow results, the status bit is set. If Y = 0 prior to execution, a borrow will result and the status logic will be reset. All other values of Y will result in status being set. STATUS: Set on no borrow, reset on borrow. OPERATION: BEFORE AFTER o o OPERATION CODE: Registers S Y 6/0 * 5 / 15 1/ 0 1 o 1 1 o o IA INCREMENT ACCUMULATOR. +1 ~A ACTION: A DESCRIPTION: The contents of the accumulator are incremented by one. STATUS: Set. OPERATION: BEFORE AFTER OPERATION CODE: o o Registers S A 5 / 15 * 6/0 1 o o 1 1 1 o IMAC INCREMENTED MEMORY TO ACCUMULATOR. ACTION: M(X, Y) + 1 ~ A CARRY ~ S DESCRIPTION: The contents of RAM file X, word Yare loaded into the accumulator and incremented. The status bit is set to one on a carry or to zero for no carry. STATUS: Set if carry, reset if no carry. OPERATION: A BEFORE AFTER OPERATION CODE: *Don't care o o * 3/0 1 Registers M(X, Y) 2/15 2/15 o 1 24 S * 0/1 o o o lye INCREMENT Y REGISTER. ACTION: Y +1~Y CARRY ~S DESCRIPTION: The contents of the Y register are incremented by one. If a carry results, the status bit is set to one. STATUS: Set on carry, reset if no carry. OPERATION: BEFORE AFTER OPERATION CODE Registers Y S * 4/15 5/0 0/1 :1 _0----ll_0--...L-_-'--_"---"-_-'-----..I~___I I1 I I1 I I 1 I1 I ° I..- ° KNEZ IF K INPUTS ARE NOT EQUAL TO ZERO, SET STATUS. ACTION: K = ° ° K f- 1~S DESCRIPTION: Compare the data on the four K input lines with zero. If the input data is not zero, set the status bit. STATUS: Set if K ~ 0, reset otherwise. OPERATION: Registers S * 7/0 K BEFORE AFTER OPERATION CODE: 7/0 1/ ° I°I° ! I °!°I I _0-.J!L...---0- " - _ - ' - - _ " - - - - - 1' - _ . . . . . & . - - _ ' - - -1- - ' 1..-1 LOP LOAD THE PAGE BUFFER. ~ ACTION: I(C) PB DESCRIPTION: The C field of the instruction is loaded into the page buffer register. STATUS: Set OPERATION: Registers I(C) PB 4 * * 4 BEFORE AFTER OPERATION CODE: 1 0 I 0 I0 11 I . LSB, C , *Don't care 25 ,MSB I LOX LOAD X REGISTER WITH A CONSTANT. ~ ACTION: I(B) DESCRIPTION: The B field of the instruction is loaded into the X register. STATUS: Set. X OPERATION: Registers I(B) 2 * X * 2 BEFORE AFTER S * 1 I LSB~MSB I OPERATION COD E: \L..-_0______1"'--0 ______1"'---1- - -1- ' -1- _ " "1' - -1- - - ' -1- - -1- - I MNEZ IF MEMORY NOT EQUAL TO ZERO, ONE TO STATUS. ACTION: M(X,Y) = O~S ° M(X,Y) ~ 1~S ° DESCRIPTION: If the contents of memory file X, word Yare equal to zero, the status logic is reset. If the contents of that memory location are not zero, the status is set. STATUS: Reset if M(X, Y) OPERATION: OPERATION CODE: = 0, set if M(X, Y) ~ 0. Registers S M(X,Y) BEFORE 0/7 AFTER 0/7 * 0/1 I ° I ° I 1 I ° I° I1 I 1 I° I RBIT RESET RAM BIT. ° ACTION: DESCRIPTION: ~ M(X,Y, B) The bit defined by the I(B) field of RAM file X, word Y, is reset to zero. RAM bits are I STATUS: I 3 MSB 2 I 1 BEFORE AFTER *Oon't care LSB I Set. OPERATION: OPERATION CODE: ° I I °I °I 1 M(X,Y) Registers S I(B) 12/6 * 3 4/6 1 * I 1 I 26 ° I 1 ILSB~MSB I RETN RETURN FROM SUBROUTINE. ACTION: CL = 1 SRR ~ PC PB ~PA IF THEN CL = 0 PC+1~PC PB ~PA O~CL DESCRIPTION: The RETN instruction loads the program counter from the subroutine return register, loads the page address register from the page buffer and resets the call latch. STATUS: Set. OPERATION CODE: I 0 I 0 I 0 I 0 I I 1 1 I 1 I 1 I RSTR RESET R OUTPUT LINE. ~ ACTION: 0 DESCRIPTION: The R output line selected by the Y register is reset to zero. STATUS: Set. R(Y) OPERATION: Registers R(Y) S * * 1 BEFORE AFTER OPERATION CODE: I 0 I 0 I 0 o I 0 I I 1 1 I 0 I 0 I SAM AN SUBTRACT ACCUMULATOR FROM MEMORY. LOAD RESULT INTO ACCUMULATOR. ACTION: M(X,Y) - A ~A 1 - BORROW ~ S DESCRIPTION: The contents of the accumulator are subtracted from the contents of RAM file X, word Y, and the result is loaded into the accumulator. If A is greater than M(X,Y), the status bit is reset to zero, but if A is less than or equal to M(X,Y), the status bit is set to one. STATUS: Set if no borrow, reset if borrow. OPERATION: A OPERATION CODE: Registers M(X,Y) S BEFORE 3/6 4 * AFTER 1/14 4 1/0 I 0 I 0 I1 I0 I0 *Don't care 27 I I 1 1 I 1 I SBIT SET RAM BIT. ~ ACTION: 1 M(X,Y, B) DESCRIPTION: The bit defined by the I(B) field of RAM file X, word Y is set to a one. RAM bits are 3 2 1 0 MSB LSB I I I I M(X,Y) Registers I(B) S BEFORE 10/14 2 * AFTER 14/14 * 1 STATUS: I Set. OPERATION: OPERATION CODE: I 0 I 0 I 1 I1 I 0 I °1 LSB~MSB 1 SETR SET R OUTPUT LINE. ~ R(Y) ACTION: 1 DESCRIPTION: The R output line selected by the Y register is set to one. STATUS: Set. OPERATION: BEFORE AFTER OPERATION CODE: I 0 Registers S R(Y) * * 1 1 I 0 I0 I 0 I1 I 1 I° I1 I TAM TRANSFER ACCUMULATOR TO MEMORY. ~ ACTION: A DESCRIPTION: The contents of the accumulator are stored in RAM file X, word Y. STATUS: Set. M(X,Y) OPERATION: BEFORE AFTER OPERATION CODE: *Don't care A 6 6 Registers M(X,Y) * 6 S * 1 1,--_0____1___0 -I..._....a...-~_---'-_--i.I0 I0 I0 I0 11 I1 I ____' " _ - - - J 28 TAMIY TRANSFER ACCUMULATOR TO MEMORY. INCREMENT Y REGISTER. ~M(X,Y), Y + 1 ~Y ACTION: A DESCRIPTION: The contents of the accumulator are stored in RAM file X, word Y. The contents of the Y register are incremented. STATUS: Set. Registers M(X,Y) A * 3 OPERATION: Y 5 6 BEFORE AFTER OPERATION CODE :1 _O----l.I_0----L1_1 I L- 3 S * 1 3 °I °I ° ° °I 1 1 --L...._.....L.-_.L..------I._----L.._---' TAMZA TRANSFER ACCUMULATOR TO MEMORY. ZERO ACCUMULATOR. ° ACTION: A ~ M(X,Y), ~A DESCRIPTION: The contents of the accumulator are stored in RAM file X, word Y. The accumulator is then loaded with zero. STATUS: Set. OPERATION: A 8 BEFORE AFTER OPERATION CODE: Registers M(X,Y) * S 8 1 ° 1°I °I °I °I ° I 1 * I 0 I °I TAY TRANSFER ACCUMULATOR TO Y REGISTER. ACTION: A~Y DESCRIPTION: The contents of the accumulator are loaded into the Y register. STATUS: Set. OPERATION: Registers Y BEFORE AFTER OPERATION CODE: I °I°I A 9 9 * 9 1 I °I *Oon't care 29 0 I S * 1 1 I °I 0 I TBIT1 TRANSFER ONE RAM BIT TO STATUS ~ ACTION: M(X,Y, B) DESCRIPTION: If the bit selected by the I(B) field in RAM file X, word Y is a one, the status logic is set to one. If it is zero, the status logic is reset to zero. RAM bits are I 3 I 2 I 1 I 0 I MSB LSB STATUS: Set if bit = 1, reset if bit = O. S OPERATION: OPERATION CODE: I M(X,Y) Registers B S BEFORE 9/14 0 * AFTER 9/14 * 1/0 0 I 0 I 1 I I 1 1 I 0 ILSB BI MSB I TCMIY TRANSFER CONSTANT TO MEMORY. INCREMENT Y REGISTER. ACTION: I(C) ~ M(X,Y) Y + I~Y DESCRIPTION: The ROM constant contained in the C field of the instruction, I(C), is loaded into RAM file X, word Y. The Y register is incremented byone. STATUS: Set. OPERATION: Registers M(X,Y) S * * 9 1 Y 4 BEFORE AFTER OPERATION CODE: I 0 I 1 5 I 1 I 0 I LSB I C I ITCl 9 * IMSBI TCY TRANSFER CONSTANT TO Y REGISTER. ACTION: I(C) ~ Y DESCRIPTION: The constant contained in the C field of the instruction, I(C), is loaded into the Y register. STATUS: Set. OPERATION: BEFORE AFTER OPERATION CODE: I 0 I 1 Registers S * 1 Y * 10 I 0 I 0 ILSB I *Oon't care 30 lie) 10 * C I IMSBI TOO TRANSFER DATA TO OUTPUTS SL,A ~ PLAIR ACTION: DESCRIPTION: The status latch and accumulator contents are loaded into the programmable logic array input register. The 5-bit word selecting one of the 32 possible output terms is: I SL I As I A4 I A2 I A1 I MSB LSB STATUS: Set. OPERATION: Registers PLAIR A SL OPERATION CODE: I S BEFORE 1/0 4/7 */* * AFTER 1/0 4/7 36/7 1 0 I °I °I 0 I 1 I 0 I 1 I I 0 TKA TRANSFER K INPUTS INTO ACCUMULATOR. ACTION: K~A DESCRIPTION: Data from the four K inputs is loaded into the accumulator. STATUS: Set. OPERATION: BEFORE AFTER OPERATION CODE: I Registers S * 1 A * 6 °I °I 0 I 0 I 1 I K 6 * °I °I 0 I TMA TRANSFER MEMORY TO ACCUMULATOR. ~ ACTION: M(X,Y) A DESCRIPTION: The contents of RAM file X, word Y, are loaded into the accum'ulator. STATUS: Set. OPERATION: A * BEFORE AFTER OPERATION CODE: *Don't care Registers M(X,Y) 4 4 4 I °I I S * 1 °I I 1 0 1 0 ,-I_o--...&-I_0--1...1_1----L_---L-._.L...-.---L-_--L-----I 31 TMV TRANSFER MEMORY TO Y REGISTER. ~ ACTION: M(X,Y) Y DESCRIPTION: The contents of RAM file X, word Y, are transferred to the Y register. STATUS: Set. OPERATION: BEFORE AFTER OPERATION CODE: Registers M(X,Y) 11 11 Y * 11 1'--_0_''---0----'-,_1 I S * 1 , ° °I°I 1 I ° I ---'--_......1..-_-'-----'-_---'-_---' TVA TRANSFER Y REGISTER TO ACCUMULATOR. ACTION: Y~A DESCRIPTION: The contents of the Y register are loaded into the accumulator. STATUS: Set. OPERATION: Registers A * Y 4 4 BEFORE AFTER OPERATION CODE: I S * 1 4 °I ° I1 I ° I °I ° I 1 I 1 I XMA EXCHANGE MEMORY AND ACCUMULATOR. ~A ACTION: M(X,Y) DESCRIPTION: The contents of RAM file X, word Y and the accumulator are exchanged. STATUS: Set. OPERATION: A 11 5 BEFORE AFTER OPERATION CODE: I °I °I 1 I Registers M(X,Y) S * 1 5 11 °I *Don't care 32 1 I 1 I 1 I ° , YNEA IF Y REGISTER =F- A, ONE TO STATUS AND STATUS LATCH. ACTION: Y~A Y=A 1~S O~S 1 o ~SL ~SL DESCRIPTION: The contents of the accumulator and the Y register are compared. If they are not equal, the status and status latch are set. This is the only instruction which sets or resets the status latch, consequently if SL = 0, PLA terms 0-15 may be output, if SL = 1, PLA terms 16-31 may be output. STATUS: Set if Y ~ A, reset otherwise. OPERATION: Registers A S Y OPERATION CODE: SL BEFORE 12 8/12 * * AFTER 12 8/12 1/0 1/0 0 0 0 0 0 1 0 0 YNEC IF Y REGISTER #- CONSTANT, ONE TO STATUS. ACTION: ~ Y = I(C) Y O~S 1~S I(C) DESCRIPTION: The contents ofthe Y register are compared with the C field ofthe instruction. If they are equal, the status logic is reset to zero, if they are not equal, the status logic is set to one. STATUS: Set if Y ¢ C, reset if Y = C. OPERATION: OPERATION CODE: I(C) Registers Y S BEFORE 4 4/3 * AFTER 4 4/3 o 1 0 1 ILSBI *Don't care 33 0/1 C I IMSBI APPLICATIONS AND SOFTWARE EXAMPLES The following hardware and software examples illustrate how the MC141000 is used in typical applications. The examples include BCD addition and subtraction, controlling a display, monitoring a keypad, interfacing an external CMOS memory, and expanding the number of R-Outputs. 34 BCD Addition and Subtraction Flowchart SUBTRACT ADD IN ITIALIZE Y (LSD) = 5 A (BORROW) = 0 INITIALIZE Y (LSD) = 5 A (CARRY) = 0 A~M (X, O~A A + 6~A A~M (X, Y) 1~A Y) A+10~A A~M (X, Y) 1 ~A * * ** * * * ***** ** **** * * * * *** * ** ** ** * * * * ** * ** * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** ** * BCD ADDITION SUBROUTINE SUMS TWO 6-DlGIT BASE TEN NUMBERS LOCATED IN Y=O(MSD) THRU Y=5(LSD) OF COMPLEMENTARY X FILES. THE AUGEND IN X IS REPLACED BY THE SUM AND THE ADDEND IN X-COMPLEMENT IS UNCHANGED. AN OVERFLOW CONDITION IS INDICATED BY A CARRY=1 IN THE ACCUMULATOR ON RETURN. * * * * ** * * *** * ** * ** ** * ** * * * * * * * * * * * * ** * * * ** **** * * ** ** * * * * * * * * * ** * * * * * * * * * * * * * ** BCD SUBTRACTION SUBROUTINE SUBTRACTS TWO 6-DIGIT BASE TEN NUMBERS LOCATED IN Y=O (MSD) THRU Y=5 (LSD) OF COMPLEMENTARY X FILES. THE MINUEND IN X IS REPLACED BY THE DIFFERENCE AND THE SUBTRAHEND IN X-COMPLEMENT IS UNCHANGED. AN UNDERFLOW CONDITION IS INDICATED BY A BORROW IN THE ACCUMULATOR ON RETURN. ***************************************************************************** ADD CLA TCY ADD1 COMX AMAAC COMX AMAAC BR ALEC BR CARRY A6AAC TAMZA IA ADD2 DYN BR RETN CLEAR CARRY ADDRESS LSD COMPLEMENT X (ADDRESS ADDEND) ADDEND DIGIT + CARRY ADDRESS AUGEND ADD AUGEND TO ACCUMULATOR CARRY BRANCH IF SUM CAUSES CARRY 9 VALID NUMBER? ADDOK YES, BRANCH SUM GREATER THAN 10, ADD CORRECTION UNITS TO MEMORY, ZERO ACCUMULATOR CARRY = 1 TO ACCUMULATOR DECREMENT Y UNTIL BORROW ADD1 BRANCH ON NO BORROW RETURN ON BORROW * * ** ** ** ** * *** ** ** * * * * * * * * * * ** * * * * ** ** ** * * *** * ** ** ** * * ** ** * * * * * * * * * * ** * * * * ** * 5 ADDOK TA,MZA BR ADD2 SUBT TCY 5 CLA SUBT1 COMX AMAAC COMX SAMAN BR SUBOK A10AAC TAMZA IA SUBT2 DYN BR SUBT1 RETN ADDRESS LSD AT Y=5 CLEAR BORROW COMPLEMENT X REGISTER ADD SUBTRAHEND DIGIT TO ACCUMULATOR COMPLEMENT X SUBTRACT SUBTRAHEND FROM MINUEND BRANCH IF NO BORROW ADD CORRECTION FACTOR IF BORROW UNITS TO MEMORY, ACCUMULATOR = 0 SET BORROW = 1 DECREMENT Y TO ADDRESS NEXT DIGIT BRANCH IF NO BORROW RETURN TO CALLING ADDRESS SUBOK TAMZA DIFFERENCE TO MEMORY, BORROW = 0 BR SUBT2 BRANCH TO ADDRESS NEXT DIGIT SUM TO MEMORY, ZERO CARRY BRANCH TO ADDRESS NEXT DIGIT 35 LCD Display Hardware and Software LCDs BCD-7 Seg. Latch/Dec./Dr. -- 7) LD MC14543 4~ A2 PH -- -- BP (MSD) A1 - MC14100 AO 7; LD ~ 0 4) 4 -- 4) MC14543 PH MC14543 -- Back plane Signal (50-120 Hz S q uare Wave ***************************************************************************** SUBROUTINE TO SCAN AN LCD DISPLAY. THREE DIGITS ARE ASSUMED HERE, BUT UP TO SIXTEEN CAN BE ACCOMMODATED MERELY BY CHANGING THE CONSTANT ON THE TCY INSTRUCTION. THE DATA IS ASSUMED TO BE IN RAM FILE 0 WITH Y=O BEING THE LSD. SCAN NEXT LOX TCY TMA TOO SETR RSTR DYN BR RETN 0 2 NEXT ADDRESS THE DATA TRANSFER THE DATA TO THE O-OUTPUTS LATCH THE DATA INTO THE LCD DRIVER SELECT NEXT DIGIT, OR IF DONE, RETURN 36 BP 7J LD PH - - BP (LSD) LCD Display Plus Keyboard Hardware 7-Seg. Latch/Dec./Drs. <> - 7) MC14543 LD PH LCDs -- -- BP (MSD) ~t 4~ - vi - 24 Key X-V Encoded Keyboard -- -- -- 4~ yI MC14543 LD PH --- 7~ yI - BP -- BP MC14543 - ,I ,I , It K8 K4 K2 K1 RO 4~ vi- I"""- R1 MC14543 R2 R3 4)- R4 R5 MC141000 0 MC14543 4 \ 4) - MC14543 LD PH - (LSD) ~ 50 to 120 Hz for sa WAVE Backplane 37 Software ***************************************************************************** SUBROUTINE TO SCAN AN LCD DISPLAY AND A 24-KEY KEYBOARD. SIX DIGITS ARE ASSUMED HERE, BUT UP TO FOURTEEN CAN BE ACCOMMODATED MERELY BY CHANGING THE CONSTANT ON THE TCY INSTRUCTION. THE DISPLAY DATA IS ASSUMED TO BE IN RAM FILE 0 WITH Y=5 BEING THE LSD. IF Y=15 ON RETURN, NO KEY WAS DEPRESSED. IF A KEY WAS DEPRESSED, THE Y VALUE WILL BE IN LOCATION 14 AND THE K-INPUTS WILL BE IN LOCATION 15 UPON RETURN. ***************************************************************************** SCAN LOX TCY NEXT TMA TDO SETR KNEZ BR RSTR NOKEY DYN BR RETN KEYDN TVA TCY TAMIY TKA TAM TVA WAIT DYN BR DAN BR TKA SAMAN TCY TMY RSTR DAN BR RETN 0 5 ADDRESS THE DISPLAY DATA. TRANSFER THE DATA TO THE O-OUTPUTS LATCH THE DATA INTO THE LCD DRIVER CHECK IF KEY DOWN, IFYES, GO TO KEY DOWN KEYDN ROUTINE. SELECT NEXT DIGIT, OR IF DONE, RETURN NEXT 14 WAIT TRANSFER Y VALUE TO ACCUMULATOR SET Y = 14 STORE CURRENT Y VALUE, INCREMENT Y TRANSFER K INPUTS TO ACCUMULATOR K INPUTS TO MEMORY AT Y = 15 15 TO ACCUMULATOR FOR DELAY DELAY 34*16=544 INSTRUCTION CYCLES TO BE CERTAIN THE KEY IS DEPRESSED AND NOT DUE TO BOUNCE WAIT K INPUTS TO ACCUMULATOR SUBTRACT NEW K INPUTS FROM PREVIOUS 14 ADDRESS STORED Y VALUE STORED Y VALUE TO Y REGISTER RESET CURRENT R-LiNE DECREMENT K INPUTS DIFFERENCE NOKEY BRANCH IF NOTZERO (K INPUTS WERE NOT SAME) VALID KEY DEPRESSION, RETURN 38 Expanding the number of R-Outputs, Hardware and Software QO Q1 0 3 3 ADR Q2 MC141000 Q3 MC14099B Q4 DATA R9 Q5 We R10 Q6 Q RESET - Note that R9 & D's are still usable for other functions except while executing SETQ or RSTQ routines. This scheme is easily expandable to 32 Q's while dedicating only 4 R's, (for the WE lines) for a net gain of 28 outputs. The output PLA would of course need to be coded appropriately. *********************************************w****************************************************************** ROUTINE TO EXPAND R-LiNES USING MC14099B 8-BIT ADDRESSABLE LATCH. (NEW OUTPUTS WILL BE REFERRED TO AS a-LINES IN THE ROUTINE AND THE ACCOMPANYING DIAGRAM) CALLING SEaUENCE: (ASSUME THE NUMBER OF THE DESIRED a-LINE IS IN THE ACC. THE USE OF R9 & R10 IS ARBITRARY. IT IS ASSUMED THAT R10 HAS BEEN INITIALIZED TO A ONE AND SL TO A ZERO.) CALL SETa CALL RSTa (OR) ***************************************************************************** TDO TCY SETR BR RSTa TDO TCY RSTR CLOKIT TCY RSTR SETR RETN SETa 9 ADDRESSES LATCH SET DATA LINE = 1 CLOKIT 9 ADDRESSES LATCH SET DATA LINE = 0 10 STROBE THE DATA INTO THE LATCH * * END 39 External RAM Storage Hardware and Software VDD U J:l, [" R 4 6 P1 Q1 r - - - P2 Q2 11 12 13 13 ,....- P3 Q3 P4 Q4 3 ,..R1 30 2 1 P5 VDD CLOCK CI W v~~ 5 151 R4 f--- 5V MC14516s Binary Up/Down Counters 4 Ll f lJ CE1 I...- AO m 22 VDD 3 i-o..- A1 7 1,0 CO 25 4 24 12 ~ 1 6 27 Q1 23 02 19 3 29 1 03 RO 13 P2 Q2 P3 Q3 P4 Q4 PE VDD 11 5 16 6 2 W 1 8 Clock 15 1 R CI VSS 9 7 9 11 ...-.......!!.. 15 GND A2 A3 A4 A5 MC15101 A6 16 A7 D04 D03 012 12 D02 ~ 013 D01 LSB K1 ~ 15 P/W OD 18 R2 ~ 011 ,..- 014 ~ R3 Il 20 36 31 7 8 K2 K4 9 10 MSB K8 VSS - h THE FOLLOWING THREE SUBROUTINES ARE USED FOR INTERFACING EXTERNAL DATA STORAGE RAM TO THE MC141000/1200. • SUBROUTINE TO WRITE A SINGLE RAM LOCATION SUBROUTINE TO SET EXTERNAL RAM ADDRESS WRITE TCY TMA TDO RSTR SETA ADR TCY TMA TDO SETR RSTR TCY TMA TDO SETR RSTR RETN 0 FETCH LEAST SIGNIFICANT BYTE OF ADDRESS FROM THE INTERNAL RAM AND OUTPUT IT ON THE O-LiNES LATCH THIS ADDRESS INTO THE EXTERNAL MEMORY ADDRESS REGISTER FETCH MOST SIGNIFICANT BYTE OF ADDRESS FROM THE INTERNAL RAM AND OUTPUT IT ON THE O-LiNES LATCH THIS ADDRESS INTO THE EXTERNAL MEMORY ADDRESS REGISTER * FETCH THE DATA TO BE WRIDEN FROM THE INTERNAL RAM AND OUTPUT IT ON THE O-LiNES WRITE THE DATA INTO THE EXTERNAL RAM SUBROUTINE TO READ A SINGLE RAM LOCATION READ 40 2 TCY RSTR TKA TAM SETR RETN 3 ENABLE THE OUTPUT DATA BUS OF THE EXTERNAL RAM TRANSFER THE READ DATA INTO THE INTERNAL RAM DISABLE THE OUTPUT DATA BUS OF THE EXTERNAL RAM
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