MC68HC08AZ60, MC68HC08AZ48 Data Sheet MC68HC08AZ60

User Manual: MC68HC08AZ60

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List of Paragraphs
Table of Contents
List of Figures
List of Tables
Section 1. General Description
- 1.1 Contents
- 1.2 Introduction
- 1.3 Features
- 1.4 MCU Block Diagram
- 1.5 Pin Assignments
- 1.6 Ordering Information
  - 1.6.1 MC Order Numbers
Section 2. Memory Map
- 2.1 Contents
- 2.2 Introduction
- 2.3 I/O Section
Section 3. RAM
- 3.1 Contents
- 3.2 Introduction
- 3.3 Functional Description
Section 4. ROM-1 Memory
- 4.1 Contents
- 4.2 Introduction
- 4.3 Functional Description
- 4.4 Low-Power Modes
  - 4.4.1 WAIT Mode
  - 4.4.2 STOP Mode
Section 5. ROM-2 Memory
- 5.1 Contents
- 5.2 Introduction
- 5.3 Functional Description
- 5.4 Low-Power Modes
  - 5.4.1 WAIT Mode
  - 5.4.2 STOP Mode
Section 6. EEPROM-1
- 6.1 Contents
- 6.2 Introduction
- 6.3 Future EEPROM Memory
- 6.4 Features
- 6.5 Functional Description
- 6.6 Low-Power Modes
  - 6.6.1 Wait Mode
  - 6.6.2 Stop Mode
Section 7. EEPROM-2
- 7.1 Contents
- 7.2 Introduction
- 7.3 Future EEPROM Memory
- 7.4 Features
- 7.5 Functional Description
- 7.6 Low-Power Modes
  - 7.6.1 Wait Mode
  - 7.6.2 Stop Mode
Section 8. Central Processing Unit (CPU)
- 8.1 Contents
- 8.2 Introduction
- 8.3 Features
- 8.4 CPU registers
- 8.5 Arithmetic/logic unit (ALU)
- 8.6 Low-power modes
  - 8.6.1 WAIT mode
  - 8.6.2 STOP mode
- 8.7 CPU during break interrupts
- 8.8 Instruction Set Summary
- 8.9 Opcode Map
Section 9. System Integration Module (SIM)
- 9.1 Contents
- 9.2 Introduction
- 9.3 SIM Bus Clock Control and Generation
- 9.4 Reset and System Initialization
  - 9.4.1 External Pin Reset
  - 9.4.2 Active Resets from Internal Sources
- 9.5 SIM Counter
- 9.6 Program Exception Control
- 9.7 Low-Power Modes
  - 9.7.1 Wait Mode
  - 9.7.2 Stop Mode
- 9.8 SIM Registers
Section 10. Clock Generation Module (CGM)
- 10.1 Contents
- 10.2 Introduction
- 10.3 Features
- 10.4 Functional Description
- 10.5 I/O Signals
- 10.6 CGM Registers
- 10.7 Interrupts
- 10.8 Low-Power Modes
  - 10.8.1 Wait Mode
  - 10.8.2 Stop Mode
- 10.9 CGM During Break Interrupts
- 10.10 Acquisition/Lock Time Specifications
Section 11. Mask Options
- 11.1 Contents
- 11.2 Introduction
- 11.3 Functional Description
- 11.4 Mask Option Register
Section 12. Break Module (BRK)
- 12.1 Contents
- 12.2 Introduction
- 12.3 Features
- 12.4 Functional Description
- 12.5 Low-Power Modes
  - 12.5.1 Wait Mode
  - 12.5.2 Stop Mode
- 12.6 Break Module Registers
  - 12.6.1 Break Status and Control Register
  - 12.6.2 Break Address Registers
Section 13. Monitor ROM (MON)
- 13.1 Contents
- 13.2 Introduction
- 13.3 Features
- 13.4 Functional Description
Section 14. Computer Operating Properly (COP)
- 14.1 Contents
- 14.2 Introduction
- 14.3 Functional Description
- 14.4 I/O Signals
- 14.5 COP Control Register
- 14.6 Interrupts
- 14.7 Monitor Mode
- 14.8 Low-Power Modes
  - 14.8.1 Wait Mode
  - 14.8.2 Stop Mode
- 14.9 COP Module During Break Interrupts
Section 15. Low Voltage Inhibit (LVI)
- 15.1 Contents
- 15.2 Introduction
- 15.3 Features
- 15.4 Functional Description
- 15.5 LVI Status Register
- 15.6 LVI Interrupts
- 15.7 Low-Power Modes
  - 15.7.1 Wait Mode
  - 15.7.2 Stop Mode
Section 16. External Interrupt (IRQ)
- 16.1 Contents
- 16.2 Introduction
- 16.3 Features
- 16.4 Functional Description
- 16.5 IRQ Pin
- 16.6 IRQ Module During Break Interrupts
- 16.7 IRQ Status and Control Register
Section 17. Serial Communications Interface (SCI)
- 17.1 Contents
- 17.2 Introduction
- 17.3 Features
- 17.4 Pin Name Conventions
- 17.5 Functional Description
- 17.6 Low-Power Modes
  - 17.6.1 Wait Mode
  - 17.6.2 Stop Mode
- 17.7 SCI During Break Module Interrupts
- 17.8 I/O Signals
  - 17.8.1 PTE0/SCTxD (Transmit Data)
  - 17.8.2 PTE1/SCRxD (Receive Data)
- 17.9 I/O Registers
Section 18. Serial Peripheral Interface (SPI)
- 18.1 Contents
- 18.2 Introduction
- 18.3 Features
- 18.4 Pin Name Conventions and I/O Register Addresses
- 18.5 Functional Description
  - 18.5.1 Master Mode
  - 18.5.2 Slave Mode
- 18.6 Transmission Formats
- 18.7 Interrupts
- 18.8 Queuing Transmission Data
- 18.9 Resetting the SPI
- 18.10 Low-Power Modes
  - 18.10.1 WAIT Mode
  - 18.10.2 STOP Mode
- 18.11 SPI During Break Interrupts
- 18.12 I/O Signals
- 18.13 I/O Registers
Section 19. Timer Interface Module B (TIMB)
- 19.1 Contents
- 19.2 Introduction
- 19.3 Features
- 19.4 Functional Description
- 19.5 Interrupts
- 19.6 Low-Power Modes
  - 19.6.1 Wait Mode
  - 19.6.2 Stop Mode
- 19.7 TIMB During Break Interrupts
- 19.8 I/O Signals
  - 19.8.1 TIMB Clock Pin (PTD4/ATD12/TBLCK)
  - 19.8.2 TIMB Channel I/O Pins (PTF5/TBCH1-PTF4/TBCH0)
- 19.9 I/O Registers
Section 20. Programmable Interrupt Timer (PIT)
- 20.1 Contents
- 20.2 Introduction
- 20.3 Features
- 20.4 Functional Description
- 20.5 PIT Counter Prescaler
- 20.6 Low-Power Modes
  - 20.6.1 Wait Mode
  - 20.6.2 Stop Mode
- 20.7 PIT During Break Interrupts
- 20.8 I/O Registers
Section 21. Input/Output Ports
- 21.1 Contents
- 21.2 Introduction
- 21.3 Port A
  - 21.3.1 Port A Data Register
  - 21.3.2 Data Direction Register A
- 21.4 Port B
  - 21.4.1 Port B Data Register
  - 21.4.2 Data Direction Register B
- 21.5 Port C
  - 21.5.1 Port C Data Register
  - 21.5.2 Data Direction Register C
- 21.6 Port D
  - 21.6.1 Port D Data Register
  - 21.6.2 Data Direction Register D
- 21.7 Port E
  - 21.7.1 Port E Data Register
  - 21.7.2 Data Direction Register E
- 21.8 Port F
  - 21.8.1 Port F Data Register
  - 21.8.2 Data Direction Register F
- 21.9 Port G
  - 21.9.1 Port G Data Register
  - 21.9.2 Data Direction Register G
- 21.10 Port H
  - 21.10.1 Port H Data Register
  - 21.10.2 Data Direction Register H
Section 22. MSCAN Controller (MSCAN08)
- 22.1 Contents
- 22.2 Introduction
- 22.3 Features
- 22.4 External Pins
- 22.5 Message Storage
- 22.6 Identifier Acceptance Filter
  - 22.6.1 MSCAN Extended ID Rejected if Stuff Bit Between ID16 and ID15
    - 22.6.1.1 Work- around
- 22.7 Interrupts
  - 22.7.1 Interrupt Acknowledge
  - 22.7.2 Interrupt Vectors
- 22.8 Protocol Violation Protection
- 22.9 Low Power Modes
- 22.10 Timer Link
- 22.11 Clock System
- 22.12 Memory Map
- 22.13 Programmer’s Model of Message Storage
- 22.14 Programmer’s Model of Control Registers
Section 23. Keyboard Module (KBD)
- 23.1 Contents
- 23.2 Introduction
- 23.3 Features
- 23.4 Functional Description
- 23.5 Keyboard Initialization
- 23.6 Low-Power Modes
  - 23.6.1 Wait Mode
  - 23.6.2 Stop Mode
- 23.7 Keyboard Module During Break Interrupts
- 23.8 I/O Registers
  - 23.8.1 Keyboard Status and Control Register
  - 23.8.2 Keyboard Interrupt Enable Register
Section 24. Timer Interface Module A (TIMA)
- 24.1 Contents
- 24.2 Introduction
- 24.3 Features
- 24.4 Functional Description
- 24.5 Interrupts
- 24.6 Low-Power Modes
  - 24.6.1 Wait Mode
  - 24.6.2 Stop Mode
- 24.7 TIMA During Break Interrupts
- 24.8 I/O Signals
  - 24.8.1 TIMA Clock Pin (PTD6/ATD14/ TCLK)
  - 24.8.2 TIMA Channel I/O Pins (PTF3-PTF0/TACH2 and PTE3/TACH1-PTE2/TACH0)
- 24.9 I/O Registers
Section 25. Analog-to-Digital Converter (ADC-15)
- 25.1 Contents
- 25.2 Introduction
- 25.3 Features
- 25.4 Functional Description
- 25.5 Interrupts
- 25.6 Low-Power Modes
  - 25.6.1 Wait Mode
  - 25.6.2 Stop Mode
- 25.7 I/O Signals
- 25.8 I/O Registers
Section 26. Electrical Specifications
- 26.1 Contents
- 26.2 Electrical Specifications
- 26.3 Mechanical Specifications
  - 26.3.1 64-Pin Quad Flat Pack (QFP)
Section 27. Appendix: Future EEPROM Registers
- 27.1 EEPROM Timebase Divider Control Registers
- 27.2 EEDIVH and EEDIVL Registers
- 27.3 EEDIV Non-volatile Registers
Section 28. Appendix: HC08AZ48 Memory Map
- 28.1 Contents
- 28.2 Introduction
- 28.3 I/O Section
Glossary
Revision History

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