MIPS R2000 Assembly Language Instructions
MIPS-instructions
MIPS-instructions
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MIPS R2000 Assembly Language Arithmetic and Logical Instructions Instruction Format Comment Absolute value abs rdest, rsrc pseudoinstruction Put the absolute value of register rsrc in register rdest Addition (with overflow) add rd, rs, rt 0 rs rt rd 0 0x20 6 5 5 5 5 6 Addition (without overflow) addu rd, rs, rt 0 rs rt rd 0 0x21 6 5 5 5 5 6 8 rs rt imm 6 5 5 16 Addition immediate (without overflow) addiu rt, rs, imm 9 rs rt imm 6 5 5 16 AND and rd, rs, rt 0 rs rt rd 0 0x24 6 5 5 5 5 6 0xc rs rt imm 6 5 5 16 Divide (with overflow) div rs, rt 0 rs rt 0 0x1a 6 5 5 10 6 Divide (without overflow) divu rs, rt 0 rs rt 0 0x1b 6 5 5 10 6 Addition immediate (with overflow) addi rt, rs, imm AND immediate andi rt, rs, imm Divide (with overflow) div rdest, rsrc1, src2 pseudoinstruction Divide (without overflow) div rdest, rsrc1, src2 pseudoinstruction Put the sum of the register rs and rt into register rd Put the sum of register rs and the sign-extended immediate into register rt Put the logical AND of register rs and rt into register rd Put the logical AND of register rs and the zero-extended immediate into register rt Divide register rs by register rt. Leave the quotient in register lo and the remainder in register hi. If an operand is negative, the remainder is unspecified by the MIPS architecture and depends on the convention of the machine on which SPIM is run. Put the quotient of register rsrc1 and src2 into register rdest. Multiply mult rs, rt 0 rs rt 0 0x18 6 5 5 10 6 Unsigned multiply multu rs, rt 0 rs rt 0 0x19 6 5 5 10 6 Multiply registers rs and rt. Leave the low-order word of the product in register lo and the high-order word in register hi Multiply (without overflow) mul rdest, rsrc1, src2 pseudoinstruction Multiply (with overflow) mulo rdest, rsrc1, src2 pseudoinstruction Unsigned multiply (with overflow) mulou rdest, rsrc1, src2 pseudoinstruction Put the product of register rsrc1 and src2 into register rdest. Negate value (with overflow) pseudoinstruction neg rdest, rsrc Negate value (without overflow) negu rdest, rsrc pseudoinstruction NOR nor rd, rs, rt NOT not rdest, rsrc 0 rs rt rd 0 0x27 6 5 5 5 5 6 pseudoinstruction rs rt rd 0 0x25 6 5 5 5 5 6 0xd rs rt imm 6 5 5 16 Remainder rem rdest, rsrc1, rsrc2 pseudoinstruction Unsigned remainder rem rdest, rsrc1, rsrc2 pseudoinstruction Shift left logical sll rd, rt, shamt Shift right arithmetic sra rd, rt, shamt Shift right logical srl rd, rt, shamt Put the remainder of register rsrc1 divided by register rsrc2 into register rdest. If an operand is negative, the remainder is unspecified by the MIPS architecture and depends on the convention of the machine on which SPIM is run. rs rt rd shamt 0 6 5 5 5 5 6 0 rs rt rd 0 4 6 5 5 5 5 6 0 rs rt rd shamt 3 6 5 5 5 5 6 0 rs rt rd 0 7 6 5 5 5 5 6 0 rs rt rd shamt 2 6 5 5 5 5 6 Shift right arithmetic variable srav rd, rt, rs Put the logical OR of registers rs and rt into register rd. Put the logical OR of register rs and the zero-extended immediate into register rt. 0 Shift left logical variable sllv rd, rt, rs Put the logical NOR of registers rs and rt into register rd Put the bitwise logical negation of register rsrc into register rdest. 0 OR or rd, rs, rt OR immediate ori rt, rs, imm Put the negative of register rsrc into register rd. Shift right logical variable srlv rd, rt, rs 0 rs rt rd 0 6 6 5 5 5 5 6 Rotate left rol rdest, rsrc1, rsrc2 pseudo-instruction Rotate right ror rdest, rsrc1, rsrc2 pseudo-instruction Rotate register rsrc1 left (right) by the distance indicated by rsrc2 and put the result into register rdest. Subtract (with overflow) sub rd, rs, rt 0 rs rt rd 0 0x22 6 5 5 5 5 6 Subtract (without overflow) subu rd, rs, rt 0 rs rt rd 0 0x23 6 5 5 5 5 6 Exclusive OR xor rd, rs, rt 0 rs rt rd 0 0x26 6 5 5 5 5 6 0xe rs rt imm 6 5 5 16 XOR immediate xori rt, rs, imm Shift register rt left (right) by the distance indicated by the immediate shamt or the register rs and put the result into register rd. Argument rs is ignored for sll, sra, and srl. Put the difference of registers rs and rt into register rd. Put the logical XOR of registers rs and rt into register rd. Put the logical XOR of register rs and the zero-extended immediate into register rt. Constant-Manipulating Instructions Load upper immediate lui rt, imm Load immediate li rdest, imm 0xf 0 rt imm 6 5 5 16 Load the lower halfword of the immediate imm into the upper halfword of register rt. The lower bits of the register are set to 0. pseudoinstruction Move the immediate imm into register rdest. Comparison instructions Set less than slt rd, rs, rt 0 rs rt rd 0 0x2a 6 5 5 5 5 6 Set less than unsigned sltu rd, rs, rt 0 rs rt rd 0 0x2b 6 5 5 5 5 6 0xa rs rd imm 6 5 5 16 0xb 0 rt imm 6 5 5 16 Set less than immediate slti rd, rs, imm Set less than unsigned immediate sltiu rd, rs, imm Set equal seq rdest, rsrc1, rsrc2 pseudoinstruction Set register rd to 1 if register rs is less than rt, and to 0 otherwise. Set register rd to 1 if register rs is less than the sign-extended immediate, and to o otherwise. Set register rdest to 1 if register rsrc1 equals rsrc2, and to 0 otherwise. Set greater than equal sge rdest, rsrc1, rsrc2 pseudoinstruction Set greater than equal unsigned sgeu rdest, rsrc1, rsrc2 pseudoinstruction Set greater than sgt rdest, rsrc1, rsrc2 pseudoinstruction Set greater than unsigned sgtu rdest, rsrc1, rsrc2 pseudoinstruction Set less than equal sle rdest, rsrc1, rsrc2 pseudoinstruction Set less than equal unsigned sleu rdest, rsrc1, rsrc2 pseudoinstruction Set register rdest to 1 if register rsrc1 is less than or equal to rsrc2, and to 0 otherwise. pseudoinstruction Unconditionally branch to the instruction at the label. Set register rdest to 1 if register rsrc1 is greater than or equal to register rsrc2, and to 0 otherwise. Set register rdest to 1 if register rsrc1 is greater than register rsrc2, and to 0 otherwise. Branch instructions Branch instruction b label Branch coprocessor z true bczt label 0x1z 8 1 offset 6 5 5 16 Branch coprocessor z false bczf label 0x1z 8 0 offset 6 5 5 16 Branch on equal beq rs, rt, label 4 rs rt offset 6 5 5 16 Branch on greater than equal zero bgez rs, label 1 rs 1 offset 6 5 5 16 Branch on greater than equal zero and link bgezal rs, label 1 rs 0x11 offset 6 5 5 16 Branch on greater than zero bgtz rs, label 7 rs 0 offset 6 5 5 16 Conditionally branch the number of instructions specified by the offset if z’s condition flag is true (false). z is 0, 1, 2, or 3. The floating point unit is z = 1. Conditionally branch the number of instructions specified by the offset if register rs equals rt. Conditionally branch the number of instructions specified by the offset if register rs is greater than or equal to 0. Conditionally branch the number of instructions specified by the offset if register rs is greater than or equal to 0. Save the address of the next instruction in register 31. Conditionally branch the instructions specified by the offset if register rs is greater than 0. Branch on less than equal zero blez rs, label 6 rs 0 offset 6 5 5 16 Branch on less than zero and link bltzal rs, label 1 rs 0x10 offset 6 5 5 16 Branch on less than zero bltz rs, label 1 rs 0 offset 6 5 5 16 Branch on not equal bne rs, rt, label 5 rs rt offset 6 5 5 16 Branch on equal zero beqz rsrc, label pseudoinstruction Branch on greater than equal bge rsrc1, rsrc2, label pseudoinstruction Branch on greater than equal unsigned bgeu rsrc1, rsrc2, label pseudoinstruction Branch on greater than bgt rsrc1, src2, label pseudoinstruction Branch on greater than unsigned bgtu rsrc1, src2, label pseudoinstruction Branch on less than equal ble rsrc1, src2, label pseudoinstruction Branch on less than equal unsigned bleu rsrc1, src2, label pseudoinstruction Branch on less than blt rsrc1, src2, label pseudoinstruction Branch on less than unsigned bltu rsrc1, src2, label pseudoinstruction Conditionally branch the instructions specified by the offset if register rs is less than or equal to 0. Conditionally branch the instructions specified by the offset if register rs is less than 0. Save the address of the next instruction in register 31. Conditionally branch the instructions specified by the offset if register rs is less than 0. Conditionally branch the instructions specified by the offset if register rs is not equal to rt. Conditionally branch to the instruction at the label if register rsrc equals 0. Conditionally branch to the instruction at the label if register rsrc1 is greater than or equal to rsrc2. Conditionally branch to the instruction at the label if register rsrc1 is greater than src2. Conditionally branch to the instruction at the label if register rsrc1 is less than or equal to src2. Conditionally branch to the instruction at the label if register rsrc1 is less than src2. Branch on not equal zero bnez rsrc, label pseudoinstruction Conditionally branch to the instruction at the label if register rsrc is not equal to zero Jump instructions 2 target 6 26 Jump and link jal target 3 target 6 26 Jump and link register jalr rs, rd 0 rs 0 rd 0 9 6 5 5 5 5 6 Jump register jr rs 0 rs 0 0 0 8 6 5 5 5 5 6 Jump j target Unconditionally jump to the instruction at target. Unconditionally jump to the instruction at target. Save the address of the next instruction in register $ra. Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31). Unconditionally jump to the instruction whose address is in register rs. Load instructions Load rdest, address la rdest, address pseudoinstruction Load computed address – not the contents of the location – into register rd. 0x20 rs rt offset 6 5 5 16 0x24 rs rt offset 6 5 5 16 Load halfword lh rt address 0x21 rs rt offset 6 5 5 16 Load unsigned halfword lhu rt, address 0x25 rs rt offset 6 5 5 16 Load word lw rt, address 0x23 rs rt offset 6 5 5 16 Load word coprocessor lwcz rt, address 0x3z rs rt offset 6 5 5 16 Load word left lwl rt, address 0x22 rs rt offset 6 5 5 16 Load byte lb rt, address Load unsigned byte lbu rt, address Load the byte at address into register rt. The byt is signextended by lb, but not by lbu. Load the byte at address into register rt. The byt is signextended by lh, but not by lhu. Load 32-bit word at address into register rt. Load the word at address into register rt of coprocessor z (0-3). The FP unit is z = 1. Load word right lwr rt, address 0x26 rs rt offset 6 5 5 16 Load the left (right) bytes from the word at the possibly unaligned address into register rt. Load doubleword ld rdest, address pseudoinstruction Load the 64-bit double word at address into registers rdest and rest + 1. Unaligned load halfword ulh rdest, address pseudoinstruction Unaligned load halfword unsigned ulhu rdest, address pseudoinstruction Load the 16-bit halfword at the possibly unaligned address into register rdest. The halfword is sign-extended by ulh, but not ulhu. Unaligned load word ulw rdest, address pseudoinstruction Load the 32-bit word at the possibly unaligned address into register rdest. Store instructions Store byte sb rt, address 0x28 rs rt offset 6 5 5 16 Store halfword sh rt, address 0x29 rs rt offset 6 5 5 16 Store word sw rt, address 0x2b rs rt offset 6 5 5 16 0x2z rs rt offset 6 5 5 16 0x2a rs rt offset 6 5 5 16 0x2e rs rt offset 6 5 5 16 Store word coprocessor swcz rt, address Store word left swl rt, address Store word right swr rt, address Store the low byte from register rt at address. Store the low halfword from register rt at address. Store the word from register rt at address. Store the word from register rt of coprocessor z at address. The FP unit is z=1. Store the left (right) bytes from register rt at the possibly unaligned address. Store doubleword sd rsrc, address pseudoinstruction Store the 64-bit double word in registers rsrc and rsrc+1 at address Unaligned store halfword ush rsrc, address pseudoinstruction Store the low halfword from register rsrc at the possibly unaligned address. Unaligned store word usw rsrc, address pseudoinstruction Store the word from register rsrc at the possibly unaligned address. Data movement instructions Move from hi mfhi rd Move from lo mflo rd 0 0 0 rd 0 0x10 6 5 5 5 5 6 0 0 0 rd 0 0x12 6 5 5 5 5 6 The multiply and divide unit produces its results in two additional registers, hi and lo. These instructions move values to and from these registers. Move the hi (lo) register to register rd. Move to hi mthi rs 0 rs 0 0 0 0x11 6 5 5 5 5 6 Move to lo mtlo rs 0 rs 0 0 0 0x13 6 5 5 5 5 6 0x1z 0 rt rd 0 0 6 5 5 5 5 6 Move from coprocessor z mfcz rt, rd Move register rs to the high (lo) register. Coprocessors have their own register sets. These instructions move values between these registers and the CPU’s registers. Move coprocessor z’s register rd to CPU register rt. The FP unit is z=1. Move double from coprocessor 1 mfc1.d rdest, frsrc1 Move to coprocessor z mtcz rd, rt pseudoinstruction Move FP registers frsrc1 and frsrc1+1 to CPU registers rdest and rdest+1. 0x1z 4 rt rd 0 0 6 5 5 5 5 6 Move CPU register rt to coprocessor z’s register rd. FP instructions (vergl. Patterson/Hennessy: Computer Organization & Design) Exception and interrupt instructions 0x10 1 0 0 0 0x20 6 1 9 5 5 6 System call syscall 0 0 0 0 0 0xc 6 5 5 5 5 6 Break break code 0 code 0xd 6 20 6 No operation nop 0 0 0 0 0 0 6 5 5 5 5 6 Return from exception rfe Restore the status register. Register $v0 contains the number of the systems call provided by SPIM Cause exception code. Exception 1 is reserved for the debugger. Do nothing MIPS Register und Konventionen für die Verwendung der Register Register name $zero $at $v0 $v1 $a0 $a1 $a2 $a3 $t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $t8 $t9 $k0 $k1 $gp $sp $fp $ra Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Usage constant 0 reserved for assembler expression evaluation and results of a function expression evaluation and results of a function argument 1 argument 2 argument 3 argument 4 temporary (not preserved across call) temporary (not preserved across call) temporary (not preserved across call) temporary (not preserved across call) temporary (not preserved across call) temporary (not preserved across call) temporary (not preserved across call) temporary (not preserved across call) saved temporary (preserved across call) saved temporary (preserved across call) saved temporary (preserved across call) saved temporary (preserved across call) saved temporary (preserved across call) saved temporary (preserved across call) saved temporary (preserved across call) saved temporary (preserved across call) temporary (not preserved across call) temporary (not preserved across call) reserved for OS kernel reserved for OS kernel pointer to global area stack pointer frame pointer return address (used by function call) Reference: http://www.cs.wisc.edu/~larus/SPIM/cod-appa.pdf
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No Page Count : 9 Title : MIPS R2000 Assembly Language Author : Sybille Hellebrand Creator : Writer Producer : OpenOffice.org 2.0 Create Date : 2006:05:17 13:28:57+02:00EXIF Metadata provided by EXIF.tools