MPR601UM 01_Power PC_601_Users_Manual_1995 01 Power PC 601 Users Manual 1995

User Manual: MPR601UM-01_PowerPC_601_Users_Manual_1995

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1.1 PowerPC 601 Microprocessor Overview
- 1.1.1 601 Features
- 1.1.2 Block Diagram
- 1.1.3 Instruction Unit
  - 1.1.3.1 Instruction Queue
- 1.1.4 Independent Execution Units
- 1.1.5 Memory Management Unit (MMU)
- 1.1.6 Cache Unit
- 1.1.7 Memory Unit
- 1.1.8 System Interface
1.2 Levels of the PowerPC Architecture
1.3 The 601 as a PowerPC Implementation
- 1.3.1 Features
- 1.3.2 Registers and Programming Model
  - 1.3.2.1 PowerPC Registers and Programming Model
  - 1.3.2.2 Additional Registers in the 601
- 1.3.3 Instruction Set and Addressing Modes
  - 1.3.3.1 PowerPC Instruction Set and Addressing Mod...
  - 1.3.3.2 601 Instruction Set
- 1.3.4 Cache Implementation
  - 1.3.4.1 PowerPC Cache Characteristics
  - 1.3.4.2 601 Cache Implementation
- 1.3.5 Exception Model
  - 1.3.5.1 PowerPC Exception Model
  - 1.3.5.2 The 601 Exception Model
- 1.3.6 Memory Management
  - 1.3.6.1 PowerPC Memory Management
  - 1.3.6.2 601 Memory Management
- 1.3.7 601 Instruction Timing
- 1.3.8 System Interface
2.1 Normal Instruction Execution State
- 2.1.1 Changing Privilege Levels
2.2 User-Level Registers
- 2.2.1 General Purpose Registers (GPRs)
- 2.2.2 Floating-Point Registers (FPRs)
- 2.2.3 Floating-Point Status and Control Register (...
- 2.2.4 Condition Register (CR)
- 2.2.5 User-Level SPRs
2.3 Supervisor-Level Registers
- 2.3.1 Machine State Register (MSR)
- 2.3.2 Segment Registers
- 2.3.3 Supervisor-Level SPRs
2.4 Operand Conventions
- 2.4.1 Data Organization in Memory and Data Transfe...
  - 2.4.1.1 Alignment and Misaligned Accesses
- 2.4.2 Effect of Operand Placement on Performance
- 2.4.3 Byte and Bit Ordering
- 2.4.4 Structure Mapping Examples
  - 2.4.4.1 Big-Endian Mapping
  - 2.4.4.2 Little-Endian Mapping
- 2.4.5 PowerPC Byte Ordering
- 2.4.6 PowerPC Instruction Memory Addressing in Lit...
- 2.4.7 PowerPC Input/Output in Little-Endian Mode
2.5 Floating-Point Execution Models
- 2.5.1 Execution Model for IEEE Operations
  - 2.5.1.1 Execution Model for Multiply-Add Type Inst...
- 2.5.2 Floating-Point Data Format
- 2.5.3 Sign of Result
- 2.5.4 Normalization and Denormalization
- 2.5.5 Data Handling and Precision
- 2.5.6 Rounding
2.6 PowerPC Registers Unimplemented in the 601
2.7 Reset
- 2.7.1 Hard Reset
- 2.7.2 Soft Reset
3.1 Memory Addressing
- 3.1.1 Effective Address Calculation
- 3.1.2 Context Synchronization
3.2 Exception Summary
3.3 Integer Instructions
- 3.3.1 Integer Arithmetic Instructions
- 3.3.2 Integer Compare Instructions
- 3.3.3 Integer Logical Instructions
- 3.3.4 Integer Rotate and Shift Instructions
  - 3.3.4.1 Integer Rotate Instructions
  - 3.3.4.2 Integer Shift Instructions
3.4 Floating-Point Instructions
- 3.4.1 Floating-Point Arithmetic Instructions
- 3.4.2 Floating-Point Multiply-Add Instructions
- 3.4.3 Floating-Point Rounding and Conversion Instr...
- 3.4.4 Floating-Point Compare Instructions
- 3.4.5 Floating-Point Status and Control Register I...
3.5 Load and Store Instructions
- 3.5.1 Integer Load and Store Address Generation
- 3.5.2 Integer Load Instructions
- 3.5.3 Integer Store Instructions
- 3.5.4 Integer Load and Store with Byte Reversal In...
- 3.5.5 Integer Load and Store Multiple Instructions...
- 3.5.6 Integer Move String Instructions
- 3.5.7 Memory Synchronization Instructions
- 3.5.8 Floating-Point Load and Store Address Genera...
  - 3.5.8.1 Register Indirect with Immediate Index Add...
  - 3.5.8.2 Register Indirect with Index Addressing
- 3.5.9 Floating-Point Load Instructions
  - 3.5.9.1 Double-Precision Conversion for Floating-P...
- 3.5.10 Floating-Point Store Instructions
  - 3.5.10.1 Double-Precision Conversion for Floating-...
- 3.5.11 Floating-Point Move Instructions
3.6 Branch and Flow Control Instructions
- 3.6.1 Branch instruction Address Calculation
- 3.6.2 Conditional Branch Control
- 3.6.3 Basic Branch Mnemonics
- 3.6.4 Branch Mnemonics Incorporating Conditions
- 3.6.5 Branch Instructions
- 3.6.6 Condition Register Logical Instructions
- 3.6.7 System Linkage Instructions
- 3.6.8 Simplified Mnemonics for Branch Processor In...
- 3.6.9 Trap Instructions and Mnemonics
3.7 Processor Control Instructions
- 3.7.1 Move to/from Machine State Register and Cond...
- 3.7.2 Move to/from Special-Purpose Register Instru...
3.8 Memory Control Instructions
- 3.8.1 Supervisor-Level Cache Management Instructio...
- 3.8.2 User-Level Cache Instructions
- 3.8.3 Segment Register Manipulation Instructions
- 3.8.4 Translation Lookaside Buffer Management Inst...
3.9 External Control Instructions
3.10 Miscellaneous Simplified Mnemonics
- 3.10.1 No-Op
- 3.10.2 Load Immediate
- 3.10.3 Load Address
- 3.10.4 Move Register
- 3.10.5 Complement Register
4.1 Cache Organization
4.2 Cache Arbitration
4.3 Cache Access Priorities
4.4 Basic Cache Operations
- 4.4.1 Cache Reloads
- 4.4.2 Cache Cast-Out Operation
- 4.4.3 Cache Sector Push Operation
- 4.4.4 Optional Cache Sector Line-Fill Operation
4.5 Cache Data Transactions
4.6 Access to I/O Controller Interface Segments
4.7 Cache Coherency
- 4.7.1 Memory Management Access Mode Bits—W, I, and...
- 4.7.2 MESI Protocol
- 4.7.3 MESI State Diagram
- 4.7.4 MESI Hardware Considerations
- 4.7.5 Coherency Precautions
  - 4.7.5.1 Coherency in Single-Processor Systems
  - 4.7.5.2 Coherency in Multiprocessor Systems
- 4.7.6 Memory Loads and Stores
- 4.7.7 Atomic Memory References
- 4.7.8 Snoop Response to Bus Operations
- 4.7.9 Cache Reaction to Specific Bus Operations
- 4.7.10 Internal ARTRY Scenarios
- 4.7.11 Enveloped High-Priority Cache Sector Push O...
4.8 Cache Control Instructions
- 4.8.1 Cache Line Compute Size Instruction (clcs)
- 4.8.2 Data Cache Block Touch Instruction (dcbt)
- 4.8.3 Data Cache Block Touch for Store Instruction...
- 4.8.4 Data Cache Block Set to Zero Instruction (dc...
- 4.8.5 Data Cache Block Store Instruction (dcbst)
- 4.8.6 Data Cache Block Flush Instruction (dcbf)
- 4.8.7 Enforce In-Order Execution of I/O Instructio...
- 4.8.8 Instruction Cache Block Invalidate Instructi...
- 4.8.9 Instruction Synchronize Instruction (isync)
4.9 Bus Operations Caused by Cache Control 4.9 Ins...
4.10 Memory Unit
- 4.10.1 Memory Unit Queuing Structure
- 4.10.2 Memory Unit Queuing Priorities
- 4.10.3 Bus Interface
4.11 MESI State Transactions
5.1 Exception Classes
- 5.1.1 Precise Exceptions
- 5.1.2 Exception Priorities
- 5.1.3 Recognition of Exceptions
  - 5.1.3.1 Recognition of Asynchronous, Imprecise Exc...
  - 5.1.3.2 Recognition of Precise Exceptions
5.2 Exception Processing
- 5.2.1 Enabling and Disabling Exceptions
- 5.2.2 Steps for Exception Processing
- 5.2.3 Returning from Supervisor Mode
5.3 Process Switching
5.4 Exception Definitions
- 5.4.1 Reset Exceptions (x'00100')
  - 5.4.1.1 Soft Reset
  - 5.4.1.2 Hard Reset
- 5.4.2 Machine Check Exception (x'00200')
  - 5.4.2.1 Machine Check Exception Enabled (MSR[ME] =...
  - 5.4.2.2 Checkstop State (MSR[ME] = 0)
- 5.4.3 Data Access Exception (x'00300')
- 5.4.4 Instruction Access Exception (x'00400')
- 5.4.5 External Interrupt (x'00500')
- 5.4.6 Alignment Exception (x'00600')
- 5.4.7 Program Exception (x'00700')
- 5.4.8 Floating-Point Unavailable Exception (x'0080...
- 5.4.9 Decrementer Exception (x'00900')
- 5.4.10 I/O Controller Interface Error Exception (x...
- 5.4.11 System Call Exception (x'00C00')
- 5.4.12 Run Mode/Trace Exception (x'02000')
  - 5.4.12.1 Run Mode Exception
  - 5.4.12.2 Trace Exception
6.1 MMU Overview
- 6.1.1 Memory Addressing
- 6.1.2 MMU Organization
- 6.1.3 Address Translation Mechanisms
- 6.1.4 Memory Protection Facilities
- 6.1.5 Page History Information
- 6.1.6 General Flow of MMU Address Translation
- 6.1.7 Memory/MMU Coherency Model
- 6.1.8 Effects of Instruction Fetch on MMU
- 6.1.9 Breakpoint Facility
- 6.1.10 MMU Exceptions Summary
- 6.1.11 MMU Instructions and Register Summary
- 6.1.12 TLB Entry Invalidation
6.2 ITLB Description
6.3 Memory/Cache Access Modes
- 6.3.1 Write-Through Bit (W)
- 6.3.2 Caching Inhibited Bit (I)
- 6.3.3 Memory Coherence Bit (M)
- 6.3.4 W, I, and M Bit Combinations
6.4 General Memory Protection Mechanism
6.5 Selection of Address Translation Type
- 6.5.1 Address Translation Selection for Instructio...
  - 6.5.1.1 Instruction Address Translation Disabled: ...
  - 6.5.1.2 Instruction Address Translation Enabled: M...
- 6.5.2 Address Translation Selection for Data Acces...
6.6 Direct Address Translation
6.7 Block Address Translation
- 6.7.1 BAT Array Organization
- 6.7.2 Recognition of Addresses in BAT Array
- 6.7.3 BAT Register Implementation of BAT Array
- 6.7.4 Block Memory Protection
- 6.7.5 Block Physical Address Generation
- 6.7.6 Block Address Translation Summary
6.8 Memory Segment Model
- 6.8.1 Page Address Translation Resources
- 6.8.2 Recognition of Addresses in Segments
  - 6.8.2.1 Selection of Memory Segments
  - 6.8.2.2 Selection of I/O Controller Interface Segm...
- 6.8.3 Page Address Translation
  - 6.8.3.1 Segment Register Definition
  - 6.8.3.2 Page Table Entry (PTE) Format
- 6.8.4 Page History Recording
  - 6.8.4.1 Reference Bit
  - 6.8.4.2 Change Bit
- 6.8.5 Page Memory Protection
- 6.8.6 Page Address Translation Summary
6.9 Hashed Page Tables
- 6.9.1 Page Table Definition
- 6.9.2 Page Table Search Operation
- 6.9.3 Page Table Updates
- 6.9.4 Segment Register Updates
6.10 I/O Controller Interface Address Translation
- 6.10.1 Segment Register Format for I/O Controller ...
- 6.10.2 I/O Controller Interface Accesses
- 6.10.3 I/O Controller Interface Segment Protection...
- 6.10.4 Memory-Forced I/O Controller Interface Acce...
- 6.10.5 Instructions Not Supported in I/O Controlle...
- 6.10.6 Instructions with No Effect in I/O Controll...
- 6.10.7 I/O Controller Interface Summary Flow
7.1 Terminology and Conventions
- 7.1.1 Definition of Terms
- 7.1.2 Timing Tables
7.2 Pipeline Description
- 7.2.1 Processor Core
- 7.2.2 Memory Subsystem
7.3 Pipeline Timing
- 7.3.1 Common Stages/BPU Pipeline Stages
- 7.3.2 BPU Pipeline Stages
  - 7.3.2.1 Speculative Execution and Mispredict Recov...
  - 7.3.2.2 Branch Pipeline Timing
- 7.3.3 Integer Pipeline Stages
- 7.3.4 Floating-Point Pipeline Stages
7.4 Execute Stage Delay Summary
8.1 Signal Configuration
8.2 Signal Descriptions
- 8.2.1 Address Bus Arbitration Signals
- 8.2.2 Address Transfer Start Signals
  - 8.2.2.1 Transfer Start (TS)
  - 8.2.2.2 Extended Address Transfer Start (XATS)
- 8.2.3 Address Transfer Signals
- 8.2.4 Address Transfer Attribute Signals
- 8.2.5 Address Transfer Termination Signals
- 8.2.6 Data Bus Arbitration Signals
- 8.2.7 Data Transfer Signals
- 8.2.8 Data Transfer Termination Signals
- 8.2.9 System Status Signals
- 8.2.10 COP/Scan Interface
- 8.2.11 Clock Signals
8.3 Clocking in a Multiprocessor System
9.1 PowerPC 601 Microprocessor System Interface 9....
- 9.1.1 Operation of the On-Chip Cache
- 9.1.2 Operation of the Memory Unit for Loads and S...
- 9.1.3 Operation of the System Interface
- 9.1.4 I/O Controller Interface Accesses
9.2 Memory Access Protocol
- 9.2.1 Arbitration Signals
- 9.2.2 Address Pipelining and Split-Bus Transaction...
9.3 Address Bus Tenure
- 9.3.1 Address Bus Arbitration
- 9.3.2 Address Transfer
- 9.3.3 Address Transfer Termination
  - 9.3.3.1 Address Retry Sources
9.4 Data Bus Tenure
- 9.4.1 Data Bus Arbitration
  - 9.4.1.1 Using the DBB Signal
- 9.4.2 Data Transfer
- 9.4.3 Data Transfer Termination
  - 9.4.3.1 Normal Single-Beat Termination
  - 9.4.3.2 Data Transfer Termination Due to a Bus Err...
- 9.4.4 Memory Coherency—MESI Protocol
9.5 Timing Examples
9.6 Memory- vs. I/O-Mapped I/O Operations
- 9.6.1 I/O Controller Interface Transactions
  - 9.6.1.1 Store Operations
  - 9.6.1.2 Load Operations
- 9.6.2 I/O Controller Interface Transaction Protoco...
  - 9.6.2.1 Packet 0
  - 9.6.2.2 Packet 1
- 9.6.3 I/O Reply Operations
- 9.6.4 I/O Controller Interface Operation Timing
9.7 Interrupt, Checkstop, and Reset Signals
- 9.7.1 External Interrupt
- 9.7.2 Checkstops
- 9.7.3 Reset Inputs
- 9.7.4 Soft Stop Control Signals
9.8 Processor State Signals
- 9.8.1 Support for the lwarx/stwcx. Instruction Pai...
9.9 IEEE 1149.1-Compatible Interface
- 9.9.1 Deviations from the IEEE 1149.1 Boundary-Sca...
- 9.9.2 Additional Information about the IEEE 1149.1...
- 9.9.3 IEEE 1149.1 Interface Description
- 9.9.4 IEEE Interface Clock Requirements
- 9.9.5 IEEE 1149.1 Interface Reset Requirements
- 9.9.6 IEEE Interface Instruction Set
- 9.9.7 IEEE 1149.1 Interface Boundary-Scan Chain
9.10 Using DBWO (Data Bus Write Only)
10.1 Instruction Formats
- 10.1.1 Split-Field Notation
- 10.1.2 Instruction Fields
- 10.1.3 Notation and Conventions
10.2 Instruction Set
10.3 Instructions Not Implemented by the 601

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