MSP430FR58xx, MSP430FR59xx, And MSP430FR6xx Family User's Guide (Rev. O) MSP430FR58xx 59xx 6xx User

user_guide%20for%20msp430fr6989

User_Guide_slau367o

MSP430UsersGuide

MSP430FR59xx%20User%20Guide

UserGuideMSP430FR5994

User Manual:

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Table of Contents
Preface
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)
- 1.1 System Control Module (SYS) Introduction
- 1.2 System Reset and Initialization
  - 1.2.1 Device Initial Conditions After System Reset
- 1.3 Interrupts
- 1.4 Operating Modes
- 1.5 Principles for Low-Power Applications
- 1.6 Connection of Unused Pins
- 1.7 Reset Pin (RST/NMI) Configuration
- 1.8 Configuring JTAG Pins
- 1.9 Vacant Memory Space
- 1.10 Boot Code
- 1.11 Bootloader (BSL)
- 1.12 JTAG Mailbox (JMB) System
- 1.13 JTAG and SBW Lock Mechanism Using the Electronic Fuse
  - 1.13.1 JTAG and SBW Lock Without Password
  - 1.13.2 JTAG and SBW Lock With Password
- 1.14 Device Descriptor Table
- 1.15 SFR Registers
- 1.16 SYS Registers
2 Power Management Module (PMM) and Supply Voltage Supervisor (SVS)
- 2.1 Power Management Module (PMM) Introduction
- 2.2 PMM Operation
- 2.3 PMM Registers
3 Clock System (CS) Module
- 3.1 Clock System Introduction
- 3.2 Clock System Operation
- 3.3 CS Registers
4 CPUX
- 4.1 MSP430X CPU (CPUX) Introduction
- 4.2 Interrupts
- 4.3 CPU Registers
- 4.4 Addressing Modes
- 4.5 MSP430 and MSP430X Instructions
  - 4.5.1 MSP430 Instructions
  - 4.5.2 MSP430X Extended Instructions
- 4.6 Instruction Set Description
5 32-Bit Hardware Multiplier (MPY32)
- 5.1 32-Bit Hardware Multiplier (MPY32) Introduction
- 5.2 MPY32 Operation
- 5.3 MPY32 Registers
  - 5.3.1 MPY32CTL0 Register
6 FRAM Controller Overview
- 6.1 FRAM Controller Overview
7 FRAM Controller (FRCTL)
- 7.1 FRAM Introduction
- 7.2 FRAM Organization
- 7.3 FRCTL Module Operation
- 7.4 Programming FRAM Devices
- 7.5 Wait State Control
  - 7.5.1 Wait State and Cache Hit
- 7.6 FRAM ECC
- 7.7 FRAM Write Back
- 7.8 FRAM Power Control
- 7.9 FRAM Cache
- 7.10 FRCTL Registers
8 FRAM Controller A (FRCTL_A)
- 8.1 FRAM Controller A (FRCTL_A) Introduction
- 8.2 FRAM Controller A (FRCTL_A) Operation
- 8.3 FRAM ECC
- 8.4 FRAM Power Control
- 8.5 FRAM Cache
- 8.6 FRCTL_A Registers
9 Memory Protection Unit (MPU)
- 9.1 Memory Protection Unit (MPU) Introduction
- 9.2 MPU Segments
- 9.3 MPU Access Management Settings
- 9.4 MPU Violations
  - 9.4.1 Interrupt Vector Table and Reset Vector
  - 9.4.2 Violation Handling
- 9.5 MPU Lock
- 9.6 How to Enable MPU and IPE Segments
  - 9.6.1 IP Encapsulation (IPE) Instantiation Using IPE Signatures
    - 9.6.1.1 IP Encapsulation Signatures
      - 9.6.1.1.1 Trapdoor Mechanism for IP Structure Pointer Transfer
    - 9.6.1.2 IP Encapsulation Init Structure
  - 9.6.2 IP Encapsulation Removal
- 9.7 MPU Registers
10 RAM Controller (RAMCTL)
- 10.1 RAM Controller (RAMCTL) Introduction
- 10.2 RAMCTL Operation
  - 10.2.1 Considerations for Complete Power Down
  - 10.2.2 DACCESSIE and DACCESSIFG Bits in RCCTL1 Register
- 10.3 RAMCTL Registers
  - 10.3.1 CTL0 Register (Offset = 0h) [reset = 6900h]
  - 10.3.2 CTL1 Register (Offset = 2h) [reset = 0h]
11 DMA Controller
- 11.1 Direct Memory Access (DMA) Introduction
- 11.2 DMA Operation
- 11.3 DMA Registers
12 Digital I/O
- 12.1 Digital I/O Introduction
- 12.2 Digital I/O Operation
- 12.3 I/O Configuration
- 12.4 Digital I/O Registers
13 Capacitive Touch I/O
- 13.1 Capacitive Touch I/O Introduction
- 13.2 Capacitive Touch I/O Operation
- 13.3 CapTouch Registers
  - 13.3.1 CAPTIOxCTL Register (offset = 0Eh) [reset = 0000h]
14 AES256 Accelerator
- 14.1 AES Accelerator Introduction
- 14.2 AES Accelerator Operation
- 14.3 AES Accelerator Registers
15 CRC Module
- 15.1 Cyclic Redundancy Check (CRC) Module Introduction
- 15.2 CRC Standard and Bit Order
- 15.3 CRC Checksum Generation
  - 15.3.1 CRC Implementation
  - 15.3.2 Assembler Examples
- 15.4 CRC Registers
16 CRC32 Module
- 16.1 Cyclic Redundancy Check (CRC32) Module Introduction
- 16.2 CRC Checksum Generation
- 16.3 CRC32 Register Descriptions
  - 16.3.1 CRC32 Registers
17 Low-Energy Accelerator (LEA) for Signal Processing
- 17.1 LEA Introduction
- 17.2 LEA Operation
- 17.3 LEA Registers
18 Ultrasonic Sensing Solution (USS, USS_A)
- 18.1 Introduction
- 18.2 Operation of the USS Module
  - 18.2.1 Auto Mode and Register Mode
    - 18.2.1.1 Six Time Mark Events in Auto Mode
    - 18.2.1.2 How to Start in Auto Mode
  - 18.2.2 Control Signals
- 18.3 Debug Features
19 Universal USS Power Supply (UUPS)
- 19.1 Introduction
- 19.2 USS Power-up Sequence
- 19.3 USS Power States
- 19.4 Interface to the ASQ (Acquisition Sequencer)
- 19.5 Interrupts
- 19.6 Debug Mode
- 19.7 UUPS Registers
20 High-Speed PLL (HSPLL)
- 20.1 Introduction
- 20.2 OSC Control Register (HSPLLUSSXTCTL)
- 20.3 PLL Control (CTL) Register
- 20.4 Start-up Sequence of the USSXT Oscillator
  - 20.4.1 USSXT Start-up Behavior
- 20.5 Interrupts
- 20.6 HSPLL Registers
21 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH, SAPH_A)
- 21.1 Introduction
- 21.2 Programmable Pulse Generator (PPG or PPG_A) Block
- 21.3 Physical Interface (PHY) Block
- 21.4 Acquisition Sequencer (ASQ)
- 21.5 Ultra-Low-Power Bias Mode
- 21.6 Interrupts Triggers
- 21.7 DMA Triggers
- 21.8 SAPH and SAPH_A Registers
22 Sigma-Delta High Speed (SDHS)
- 22.1 Introduction
- 22.2 SDHS Functional Operation
- 22.3 Interrupts
  - 22.3.1 IIDX, Interrupt Vector Generator
- 22.4 Debug Mode
- 22.5 SDHS Registers
23 Metering Test Interface (MTIF)
- 23.1 MTIF Introduction
- 23.2 MTIF Operation
- 23.3 MTIF Block Diagram
  - 23.3.1 Test Interface Input
- 23.4 MTIF Registers
24 Watchdog Timer (WDT_A)
- 24.1 WDT_A Introduction
- 24.2 WDT_A Operation
- 24.3 WDT_A Registers
  - 24.3.1 WDTCTL Register
25 Timer_A
- 25.1 Timer_A Introduction
- 25.2 Timer_A Operation
- 25.3 Timer_A Registers
26 Timer_B
- 26.1 Timer_B Introduction
  - 26.1.1 Similarities and Differences From Timer_A
- 26.2 Timer_B Operation
- 26.3 Timer_B Registers
27 Real-Time Clock (RTC) Overview
- 27.1 RTC Overview
28 Real-Time Clock B (RTC_B)
- 28.1 Real-Time Clock RTC_B Introduction
- 28.2 RTC_B Operation
- 28.3 RTC_B Registers
29 Real-Time Clock C (RTC_C)
- 29.1 Real-Time Clock (RTC_C) Introduction
- 29.2 RTC_C Operation
- 29.3 RTC_C Operation - Device-Dependent Features
  - 29.3.1 Counter Mode
  - 29.3.2 Real-Time Clock Event/Tamper Detection With Time Stamp
    - 29.3.2.1 Real-Time Clock Event/Tamper Detection Interrupts
- 29.4 RTC_C Registers
30 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode
- 30.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview
- 30.2 eUSCI_A Introduction – UART Mode
- 30.3 eUSCI_A Operation – UART Mode
- 30.4 eUSCI_A UART Registers
31 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode
- 31.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview
- 31.2 eUSCI Introduction – SPI Mode
- 31.3 eUSCI Operation – SPI Mode
- 31.4 eUSCI_A SPI Registers
- 31.5 eUSCI_B SPI Registers
32 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode
- 32.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview
- 32.2 eUSCI_B Introduction – I2C Mode
- 32.3 eUSCI_B Operation – I2C Mode
- 32.4 eUSCI_B I2C Registers
33 REF_A
- 33.1 REF_A Introduction
- 33.2 Principle of Operation
  - 33.2.1 Low-Power Operation
  - 33.2.2 Reference System Requests
- 33.3 REF_A Registers
  - 33.3.1 REFCTL0 Register (offset = 00h) [reset = 0000h]
34 ADC12_B
- 34.1 ADC12_B Introduction
- 34.2 ADC12_B Operation
- 34.3 ADC12_B Registers
35 Comparator E (COMP_E) Module
- 35.1 COMP_E Introduction
- 35.2 COMP_E Operation
- 35.3 COMP_E Registers
36 LCD_C Controller
- 36.1 LCD_C Introduction
- 36.2 LCD_C Operation
- 36.3 LCD_C Registers
37 Extended Scan Interface (ESI)
- 37.1 ESI Introduction
- 37.2 ESI Operation
- 37.3 ESI Registers
38 Embedded Emulation Module (EEM)
- 38.1 Embedded Emulation Module (EEM) Introduction
- 38.2 EEM Building Blocks
- 38.3 EEM Configurations
Revision History
Important Notice

MSP430FR58xx, MSP430FR59xx, And MSP430FR6xx Family User's Guide (Rev. O) MSP430FR58xx 59xx 6xx User

user_guide%20for%20msp430fr6989

User_Guide_slau367o

MSP430UsersGuide

MSP430FR59xx%20User%20Guide

UserGuideMSP430FR5994

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