MT7686 Reference Manual

MT7686_Reference_Manual

User Manual:

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1. Documentation General Conventions
- 1.1. Abbreviations for control modules
- 1.2. Abbreviations for registers
2. Bus Architecture and Memory Map
3. External Interrupt Controller
- 3.1. Overview
- 3.2. Features
- 3.3. Block diagram
- 3.4. Wakeup event management
- 3.5. Functions
- 3.6. External interrupt or event line mapping
- 3.7. Register mapping
  - 3.7.1. Register definitions
4. Direct Memory Access
- 4.1. Overview
- 4.2. Features
- 4.3. Functions
- 4.4. Application and programming sequence
- 4.5. Register mapping
5. Universal Asynchronous Receiver/Transmitter
- 5.1. Overview
- 5.2. Features
- 5.3. Block diagram
- 5.4. Functions
- 5.5. Register mapping
6. Serial Peripheral Interface Master Controller
- 6.1. Features
- 6.2. Block diagram
- 6.3. Functions
- 6.4. Register mapping
7. Serial Peripheral Interface Slave Controller
- 7.1. Features
- 7.2. Block diagram
- 7.3. Functions
  - 7.3.1. SPI slave control flow
  - 7.3.2. SPI slave modes
- 7.4. Register mapping
8. Inter-Integrated Circuit Controller
- 8.1. Overview
- 8.2. Features
- 8.3. Block diagram
- 8.4. Functions
- 8.5. Programming guide
- 8.6. Manual and DMA transfer modes for I2C controller
- 8.7. Register mapping
9. SD/SDIO Card Controller
- 9.1. Overview
- 9.2. Features
- 9.3. Block diagram
- 9.4. Functions
  - 9.4.1. Pin assignment
- 9.5. Programming sequence
  - 9.5.1. MSDC recommended command sequence
- 9.6. Register mapping
10. I2S0
- 10.1. Overview
- 10.2. IO interface
- 10.3. I2S OUT and I2S IN
- 10.4. DL FIFO and UL FIFO
- 10.5. Data format of FIFO
- 10.6. Programming guide
- 10.7. Register mapping
11. I2S1
- 11.1. Overview
- 11.2. IO interface
- 11.3. I2S OUT and I2S IN
- 11.4. DL FIFO and UL FIFO
- 11.5. Data format of FIFO
- 11.6. Programming guide
- 11.7. Register mapping
12. I2S0 and I2S1 Audio PLL Settings
- 12.1. XPLL block diagram
- 12.2. Fractional-N PLL power on sequence
- 12.3. XPLL frequency setting (Integer)
- 12.4. DDS PCW setting
- 12.5. XPLL frequency change sequence
- 12.6. XPLL turn on programming sequence
- 12.7. XPLL turn off programming sequence
13. SDIO
- 13.1. Overview
- 13.2. Features
- 13.3. Block diagram
- 13.4. Functions
  - 13.4.1. Signal pins
  - 13.4.2. SDIO timing waveform (3.3V)
- 13.5. Register mapping
  - 13.5.1. Firmware register
  - 13.5.2. Host domain register
14. General Purpose Timer
- 14.1. Overview
- 14.2. Features
- 14.3. Limitations
- 14.4. Block diagram
- 14.5. Functions
- 14.6. Programming sequence
- 14.7. Register mapping
15. Pulse Width Modulation
- 15.1. Overview
- 15.2. Features
- 15.3. Block diagram
- 15.4. Functions
- 15.5. Register mapping
16. Cortex-M4 L1 Cache Controller
- 16.1. Overview
- 16.2. Cache optimization
- 16.3. Register mapping
- 16.4. Cacheable region controller
- 16.5. Remapping
  - 16.5.1. Register mapping
17. Auxiliary ADC Unit
- 17.1. Features
- 17.2. Block diagram
- 17.3. Functions
- 17.4. Programming sequence
- 17.5. Register mapping
18. Reset Generation Unit
- 18.1. Features
- 18.2. Block diagram
- 18.3. WDT timeout and interval source
- 18.4. Register mapping
19. True Random Number Generator
- 19.1. Overview
- 19.2. Features
- 19.3. Block diagram
- 19.4. Function description
- 19.5. Programming sequence
- 19.6. Register mapping
20. Real Time Clock (RTC)
- 20.1. Features
- 20.2. Block diagram
- 20.3. Functions
- 20.4. Programming sequence
- 20.5. Register mapping
21. General Purpose Inputs/Outputs
- 21.1. Overview
- 21.2. IO pull up or down control truth table
- 21.3. Register mapping
22. Clock Configuration
- 22.1. Clock configuration programming guide
- 22.2. Register mapping

MT7686 Reference Manual

MT7686_Reference_Manual

MT7686_Reference_Manual

MT7686_Reference_Manual

MT7686_Reference_Manual

MT7686_Reference_Manual

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