MT7686 Reference Manual

Version: 1.1

Release date: 16 August 2017

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Document Revision History

Revision Date Description

1.0 30 June 2017 Initial draft

1.1 16 August 2017 Modified section 5.5

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Table of Contents

1. Documentation General Conventions .................................................................................................... 1

1.1. Abbreviations for control modules ..................................................................................................... 1

1.2. Abbreviations for registers ................................................................................................................. 2

2. Bus Architecture and Memory Map ....................................................................................................... 3

3. External Interrupt Controller ................................................................................................................. 7

3.1. Overview ............................................................................................................................................. 7

3.2. Features .............................................................................................................................................. 7

3.3. Block diagram ..................................................................................................................................... 7

3.4. Wakeup event management .............................................................................................................. 7

3.5. Functions ............................................................................................................................................ 8

3.6. External interrupt or event line mapping ........................................................................................... 9

3.7. Register mapping .............................................................................................................................. 10

4. Direct Memory Access .......................................................................................................................... 20

4.1. Overview ........................................................................................................................................... 20

4.2. Features ............................................................................................................................................ 20

4.3. Functions .......................................................................................................................................... 21

4.4. Application and programming sequence .......................................................................................... 23

4.5. Register mapping .............................................................................................................................. 24

5. Universal Asynchronous Receiver/Transmitter ..................................................................................... 52

5.1. Overview ........................................................................................................................................... 52

5.2. Features ............................................................................................................................................ 52

5.3. Block diagram ................................................................................................................................... 52

5.4. Functions .......................................................................................................................................... 53

5.5. Register mapping .............................................................................................................................. 55

6. Serial Peripheral Interface Master Controller ....................................................................................... 70

6.1. Features ............................................................................................................................................ 70

6.2. Block diagram ................................................................................................................................... 72

6.3. Functions .......................................................................................................................................... 72

6.4. Register mapping .............................................................................................................................. 74

7. Serial Peripheral Interface Slave Controller .......................................................................................... 83

7.1. Features ............................................................................................................................................ 83

7.2. Block diagram ................................................................................................................................... 85

7.3. Functions .......................................................................................................................................... 85

7.4. Register mapping .............................................................................................................................. 89

8. Inter-Integrated Circuit Controller ........................................................................................................ 98

8.1. Overview ........................................................................................................................................... 98

8.2. Features ............................................................................................................................................ 98

8.3. Block diagram ................................................................................................................................... 98

8.4. Functions .......................................................................................................................................... 99

8.5. Programming guide ........................................................................................................................ 101

8.6. Manual and DMA transfer modes for I2C controller ...................................................................... 102

8.7. Register mapping ............................................................................................................................ 102

9. SD/SDIO Card Controller ..................................................................................................................... 115

9.1. Overview ......................................................................................................................................... 115

9.2. Features .......................................................................................................................................... 115

9.3. Block diagram ................................................................................................................................. 116

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9.4. Functions ........................................................................................................................................ 116

9.5. Programming sequence .................................................................................................................. 117

9.6. Register mapping ............................................................................................................................ 117

10. I2S0 ..................................................................................................................................................... 149

10.1. Overview ......................................................................................................................................... 149

10.2. IO interface ..................................................................................................................................... 149

10.3. I2S OUT and I2S IN .......................................................................................................................... 151

10.4. DL FIFO and UL FIFO ....................................................................................................................... 152

10.5. Data format of FIFO ........................................................................................................................ 152

10.6. Programming guide ........................................................................................................................ 153

10.7. Register mapping ............................................................................................................................ 156

11. I2S1 ..................................................................................................................................................... 164

11.1. Overview ......................................................................................................................................... 164

11.2. IO interface ..................................................................................................................................... 164

11.3. I2S OUT and I2S IN .......................................................................................................................... 165

11.4. DL FIFO and UL FIFO ....................................................................................................................... 166

11.5. Data format of FIFO ........................................................................................................................ 166

11.6. Programming guide ........................................................................................................................ 167

11.7. Register mapping ............................................................................................................................ 169

12. I2S0 and I2S1 Audio PLL Settings ......................................................................................................... 180

12.1. XPLL block diagram ......................................................................................................................... 180

12.2. Fractional-N PLL power on sequence ............................................................................................. 180

12.3. XPLL frequency setting (Integer) .................................................................................................... 181

12.4. DDS PCW setting ............................................................................................................................. 182

12.5. XPLL frequency change sequence ................................................................................................... 182

12.6. XPLL turn on programming sequence............................................................................................. 182

12.7. XPLL turn off programming sequence ............................................................................................ 186

13. SDIO ................................................................................................................................................... 187

13.1. Overview ......................................................................................................................................... 187

13.2. Features .......................................................................................................................................... 187

13.3. Block diagram ................................................................................................................................. 188

13.4. Functions ........................................................................................................................................ 188

13.5. Register mapping ............................................................................................................................ 191

14. General Purpose Timer ....................................................................................................................... 331

14.1. Overview ......................................................................................................................................... 331

14.2. Features .......................................................................................................................................... 331

14.3. Limitations ...................................................................................................................................... 331

14.4. Block diagram ................................................................................................................................. 332

14.5. Functions ........................................................................................................................................ 332

14.6. Programming sequence .................................................................................................................. 332

14.7. Register mapping ............................................................................................................................ 333

15. Pulse Width Modulation ..................................................................................................................... 354

15.1. Overview ......................................................................................................................................... 354

15.2. Features .......................................................................................................................................... 354

15.3. Block diagram ................................................................................................................................. 354

15.4. Functions ........................................................................................................................................ 355

15.5. Register mapping ............................................................................................................................ 356

16. Cortex-M4 L1 Cache Controller ........................................................................................................... 359

16.1. Overview ......................................................................................................................................... 359

16.2. Cache optimization ......................................................................................................................... 361

16.3. Register mapping ............................................................................................................................ 366

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16.4. Cacheable region controller ........................................................................................................... 372

16.5. Remapping ...................................................................................................................................... 375

17. Auxiliary ADC Unit .............................................................................................................................. 379

17.1. Features .......................................................................................................................................... 379

17.2. Block diagram ................................................................................................................................. 379

17.3. Functions ........................................................................................................................................ 380

17.4. Programming sequence .................................................................................................................. 380

17.5. Register mapping ............................................................................................................................ 382

18. Reset Generation Unit ........................................................................................................................ 386

18.1. Features .......................................................................................................................................... 386

18.2. Block diagram ................................................................................................................................. 386

18.3. WDT timeout and interval source .................................................................................................. 386

18.4. Register mapping ............................................................................................................................ 387

19. True Random Number Generator ....................................................................................................... 398

19.1. Overview ......................................................................................................................................... 398

19.2. Features .......................................................................................................................................... 398

19.3. Block diagram ................................................................................................................................. 398

19.4. Function description ....................................................................................................................... 399

19.5. Programming sequence .................................................................................................................. 400

19.6. Register mapping ............................................................................................................................ 401

20. Real Time Clock (RTC) ......................................................................................................................... 405

20.1. Features .......................................................................................................................................... 405

20.2. Block diagram ................................................................................................................................. 405

20.3. Functions ........................................................................................................................................ 406

20.4. Programming sequence .................................................................................................................. 406

20.5. Register mapping ............................................................................................................................ 406

21. General Purpose Inputs/Outputs ........................................................................................................ 417

21.1. Overview ......................................................................................................................................... 417

21.2. IO pull up or down control truth table ........................................................................................... 417

21.3. Register mapping ............................................................................................................................ 419

22. Clock Configuration ............................................................................................................................ 482

22.1. Clock configuration programming guide ........................................................................................ 482

22.2. Register mapping ............................................................................................................................ 488

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Lists of Tables and Figures

Table 2.1-1. MT7686 bus connection ...................................................................................................................... 3

Table 2.1-2. Top view memory map ....................................................................................................................... 3

Table 2.1-3. Always-on domain peripherals ........................................................................................................... 4

Table 2.1-4. Power-down domain peripherals ........................................................................................................ 5

Table 3.6-1. External interrupt sources................................................................................................................... 9

Table 4.4-1. Virtual FIFO access ports ................................................................................................................... 23

Table 5.5-1. SPI master controller interface ......................................................................................................... 70

Table 6.4-1. SPI slave controller interface ............................................................................................................ 83

Table 7.3-1. SPI slave controller interface ............................................................................................................ 85

Table 7.3-2. SPI slave status description (use RS command to poll SPI slave status) ........................................... 87

Table 9.4-1. Sharing of pins for SD memory card controller ............................................................................... 116

Table 9.6-1. MSDC register definition ................................................................................................................. 117

Table 10.2-1. I2S mode interface – master mode ............................................................................................... 149

Table 10.2-2. I2S mode interface – slave mode .................................................................................................. 150

Table 10.2-3. TDM mode interface – master mode ............................................................................................ 150

Table 10.2-4. TDM mode interface – slave mode ............................................................................................... 150

Table 10.2-5. Relationship between MCLK and sample rate .............................................................................. 150

Table 10.3-1. Down rate example for slave mode .............................................................................................. 151

Table 10.5-1. 16bits I2S data format of FIFO ..................................................................................................... 152

Table 10.5-2. 16bits TDM 4 channel data format of FIFO .................................................................................. 152

Table 11.2-1. I2S mode interface – master mode ............................................................................................... 164

Table 11.2-2. I2S mode interface – slave mode .................................................................................................. 165

Table 11.2-3. Relationship between MCLK and sample rate .............................................................................. 165

Table 11.5-1. 16bits I2S data format of FIFO ...................................................................................................... 166

Table 11.5-2. 24bits I2S data format of FIFO ...................................................................................................... 167

Table 13.4-1. SDIO pin definitions ....................................................................................................................... 188

Table 13.4-2. Bus signal voltage .......................................................................................................................... 189

Table 13.4-3. Bus timing parameter values (default) .......................................................................................... 190

Table 13.4-4. High-speed timing parameter values ............................................................................................ 191

Table 14.5-1. GPT operation modes ................................................................................................................... 332

Table 16.1-1. TCM address spaces for different cache size settings ................................................................... 360

Table 16.2-1. Write-back mode cache read or write operations ........................................................................ 365

Table 16.2-2. Write-through mode cache R/W action summary ........................................................................ 366

Table 16.4-1. Cacheable attribute bit encoding .................................................................................................. 373

Table 16.5-1. Region size and bit encoding ......................................................................................................... 377

Table 17.3-1. AUXADC channel description ........................................................................................................ 380

Table 22.1-1. Clock switch ................................................................................................................................... 483

Table 22.1-2. Relationship between XO_PDN_COND0 bit number and configuration register ......................... 484

Table 22.1-3. Clock multiplexer switch method of HF_FSYS_CK ......................................................................... 485

Table 22.1-4. Relationship between PDN_COND0 bit number and configuration register ................................ 485

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Table 22.1-5. Clock multiplexer switch method of HF_FSFC_CK ........................................................................ 486

Table 22.1-6. Clock multiplexer switch method of F_FSDIOMST_CK .................................................................. 486

Table 22.1-7. Clock multiplexer switch method of F_FSDIOMST_CK .................................................................. 487

Table 22.1-8. Clock multiplexer switch method of F_FSDIOMST_CK .................................................................. 487

Table 22.1-9. Clock multiplexer switch method of F_FSDIOMST_CK .................................................................. 488

Figure 3.3-1. EINT block diagram ............................................................................................................................ 7

Figure 4.1-1. Variety data paths of DMA transfers ............................................................................................... 20

Figure 4.2-1. DMA block diagram .......................................................................................................................... 21

Figure 4.3-1. Ring buffer and double buffer memory data movement ................................................................ 22

Figure 4.3-2. Unaligned word accesses ................................................................................................................. 22

Figure 4.3-3. Virtual FIFO DMA ............................................................................................................................. 23

Figure 5.3-1. UART block diagram ......................................................................................................................... 53

Figure 5.4-1. UART data format ............................................................................................................................ 54

Figure 5.5-1. Pin connection between SPI master and SPI slave .......................................................................... 70

Figure 6.1-1. SPI transmission formats ................................................................................................................. 71

Figure 6.1-2. Operation flow with or without PAUSE mode ................................................................................. 71

Figure 6.1-3. CS de-assert mode ........................................................................................................................... 71

Figure 6.1-4. SPI master controller delay sample ................................................................................................. 72

Figure 6.2-1. Block diagram of SPI master controller ............................................................................................ 72

Figure 6.3-1. SPI master single mode .................................................................................................................... 73

Figure 6.3-2. SPI master dual mode write data ..................................................................................................... 73

Figure 6.3-3. SPI master dual mode read data ...................................................................................................... 73

Figure 6.3-4. SPI master quad mode write data ................................................................................................... 73

Figure 6.3-5. SPI master quad mode read data..................................................................................................... 74

Figure 6.4-1. Pin connection between SPI master and SPI slave .......................................................................... 83

Figure 7.1-1. SPI transmission formats ................................................................................................................. 84

Figure 7.1-2. SPI slave controller early transmit ................................................................................................... 84

Figure 7.2-1. Block diagram of SPI slave controller ............................................................................................... 85

Figure 7.3-1. SPI slave controller commands waveform ....................................................................................... 86

Figure 7.3-2. Config read/write (CR/CW) command format ................................................................................. 86

Figure 7.3-3. SPI slave control flow diagram ......................................................................................................... 87

Figure 7.3-4. SPI slave single mode write data ..................................................................................................... 88

Figure 7.3-5. SPI slave single mode read data ....................................................................................................... 88

Figure 7.3-6. SPI slave dual mode write data ........................................................................................................ 88

Figure 7.3-7. SPI slave dual mode read data ......................................................................................................... 88

Figure 7.3-8. SPI slave quad mode write data ....................................................................................................... 89

Figure 7.3-9. SPI slave quad mode read data ........................................................................................................ 89

Figure 8.3-1. I2C block diagram............................................................................................................................. 99

Figure 8.4-1. I2C single transfer single byte access ............................................................................................... 99

Figure 8.4-2. I2C single transfer multi byte access .............................................................................................. 100

Figure 8.4-3. I2C multi transfer multi byte access .............................................................................................. 100

Figure 8.4-4. I2C multi transfer multi byte access with RS.................................................................................. 100

Figure 8.4-5. I2C multi transfer multi byte access with direction-change function ............................................ 101

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Figure 8.5-1. I2C transfer format programming guide ........................................................................................ 101

Figure 8.5-2. I2C timing format programming guide .......................................................................................... 102

Figure 9.3-1. MSDC block diagram ...................................................................................................................... 116

Figure 10.1-1. I2S block diagram ......................................................................................................................... 149

Figure 10.3-1. I2S protocol waveform ................................................................................................................. 151

Figure 10.3-2. Sample m of TDM32 with nT delay .............................................................................................. 151

Figure 10.3-3. Sample m of TDM32 with nT delay and bclk inverse ................................................................... 152

Figure 10.3-4. Sample m of TDM64 with nT delay .............................................................................................. 152

Figure 11.1-1. I2S block diagram ......................................................................................................................... 164

Figure 11.3-1. I2S protocol waveform ................................................................................................................. 166

Figure 12.1-1. XPLL block diagram ...................................................................................................................... 180

Figure 12.2-1. Fractional-N PLL power on sequence .......................................................................................... 181

Figure 12.4-1. DDS PCW settings ........................................................................................................................ 182

Figure 12.5-1. XPLL frequency change sequence ................................................................................................ 182

Figure 13.3-1. SDIO controller block diagram ..................................................................................................... 188

Figure 13.4-1. Signal connections to 4-bit SDIO cards ........................................................................................ 188

Figure 13.4-2. Bus signal levels ........................................................................................................................... 189

Figure 13.4-3. Bus timing diagram (default) ....................................................................................................... 190

Figure 13.4-4. High-speed timing diagram .......................................................................................................... 191

Figure 14.4-1. GPT block diagram ....................................................................................................................... 332

Figure 15.1-1. PWM waveform ........................................................................................................................... 354

Figure 15.3-1. PWM block diagram ..................................................................................................................... 355

Figure 15.4-1. PWM waveform with register values........................................................................................... 356

Figure 16.1-1. MCU, Cache, TCM and AHB bus connectivity .............................................................................. 359

Figure 16.1-2. Cache size and TCM settings ........................................................................................................ 360

Figure 16.2-1. Cache lookup for 4-way set associative ....................................................................................... 362

Figure 16.2-2. Cache miss/refill criteria .............................................................................................................. 364

Figure 16.4-1. Cacheable setting example .......................................................................................................... 372

Figure 16.5-1. Example settings of cache remapping ......................................................................................... 375

Figure 16.5-1. SAR ADC waveform ...................................................................................................................... 379

Figure 17.2-1. AUXADC block diagram ................................................................................................................ 380

Figure 17.4-1. Immediate mode programming sequence .................................................................................. 381

Figure 18.2-1. Block diagram of RGU .................................................................................................................. 386

Figure 18.3-1. WDT timeout length and interval time ........................................................................................ 387

Figure 19.3-1. TRNG block diagram .................................................................................................................... 398

Figure 19.3-2. Ring Oscillator .............................................................................................................................. 399

Figure 19.3-3. Inverter Core ................................................................................................................................ 399

Figure 19.4-1. TRNG operation flow ................................................................................................................... 400

Figure 20.2-1. RTC block diagram ....................................................................................................................... 406

Figure 21.1-1. GPIO block diagram ..................................................................................................................... 417

Figure 22.1-1. Clock source architecture ............................................................................................................ 483

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1. Documentation General Conventions

1.1. Abbreviations for control modules

Abbreviation Full name

EINT External interrupt controller

DMA Direct memory access

UART Universal asynchronous receiver transmitter

SPI master Serial peripheral interface master controller

SPI slave Serial peripheral interface slave controller

I2C Inter-integrated circuit interface

MSDC SD memory card controller

I2S0 Inter-IC sound channel 0

XPLL Audio phase-locked loop

SDIO Secure digital input/output

I2S1 Inter-IC sound channel 1

GPT General purpose timer

PWM Pulse width modulation

AUXADC Auxiliary ADC

RGU Reset generation unit

RTC Real-time clock

TRNG True random number generator

GPIO General purpose input/output

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1.2. Abbreviations for registers

Abbreviation Full name

RW Read and write

RO Read only

WO Write only

RC Read 1 to clear

WC Write 1 to clear

RWC Read or write 1 to clear

FM Frequency measurement

FRC Free running counter

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2. Bus Architecture and Memory Map

MediaTek MT7686 adopts 32-bit multi-AHB matrix to provide low power, fast and flexible data operation for IoT

and Wearables applications. Table 2.1-1 shows the interconnections between bus masters (Cortex-M4, four SPI

masters, SPI slave, debug system, Wi-Fi connectivity system, crypto engine and direct memory access (DMA)

controller) and slaves (AO APB peripherals, PD APB peripherals, TCM, SFC, EMI, SYSRAM, RTC RAM, Wi-Fi

connectivity system).

Table 2.1-1. MT7686 bus connection

Master

Slave

ARM

Cortex-M4 PD DMA SPM SPI Master SPI Slave SDIO

Master

SDIO

Slave

Crypto

Engine

CONNSYS

Master

AO APB

Peripherals

● ● ● ●

PD APB

Peripherals

● ● ● ●

TCM ● ● ● ●

EMI ● ● ● ● ● ● ● ● ●

SFC ● ● ● ●

SYSRAM ● ● ● ● ● ● ● ● ●

RTC SRAM ● ● ● ● ● ● ● ● ●

CONNSYS ● ● ● ●

Table 2.1-2. Top view memory map

Start Address End Address Module

0x0000_0000 0x03FF_FFFF EMI

0x0400_0000 0x0400_7FFF Cortex-M4 TCM/cache

0x0400_8000 0x0401_7FFF Cortex-M4 TCM

0x0410_0000 0x041F_FFFF Boot ROM

0x0420_0000 0x0425_FFFF SYSRAM

0x0430_0000 0x043F_FFFF Retention SRAM

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Start Address End Address Module

0x0440_0000 0x044F_FFFF Wi-Fi ROM

0x0800_0000 0x0FFF_FFFF SFC

0xA000_0000 0xA0FF_FFFF PD APB peripherals

0xA100_0000 0xA1FF_FFFF PD AHB peripherals

0xA200_0000 0xA20F_FFFF AO APB peripherals

0xC000_0000 0xCFFF_FFFF CONNSYS

0xE000_0000 0xE003_FFFF Cortex-M4 private peripheral bus

- internal

0xE004_0000 0xE00F_FFFF Cortex-M4 private peripheral bus

- external

0xE010_0000 0xE01F_FFFF Cortex-M4 peripheral

Table 2.1-3. Always-on domain peripherals

Start Address Module Bus Interface Notes

A200_0000 VERSION_CTRL APB Mapped to 0x8000_0000

A201_0000 Configuration registers APB Clock, power down, version and

reset

A202_0000 BBPLL control APB

A203_0000 XPLL control APB

A204_0000 Analog chip interface controller APB PLL, CLKSQ, FH, CLKSW and

SIMLS

A205_0000 Top clock control APB DCM, CG

A206_0000 RF XTAL control APB

A207_0000 PMU configuration APB

A208_0000 Real-time clock APB

A209_0000 Reset generation unit APB

A20A_0000 eFuse APB

A20B_0000 General purpose inputs/outputs APB

A20C_0000 IO configuration 0 APB

A20D_0000 IO configuration 1 APB

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Start Address Module Bus Interface Notes

A20E_0000 SEJ APB

A20F_0000 SPM APB

A210_0000 Interrupt controller (EINT) APB

A211_0000 GP Timer APB

A212_0000 Pulse width modulation outputs 0 APB

A213_0000 Pulse width modulation outputs 1 APB

A214_0000 Pulse width modulation outputs 2 APB

A215_0000 Pulse width modulation outputs 3 APB

A216_0000 Pulse width modulation outputs 4 APB

A217_0000 Pulse width modulation outputs 5 APB

A21D_0000 Configuration Registers APB Clock, 96MHz

A21E_0000 CM4_CFG_PRIVATE APB

A21F_0000 INFRA BUS configuration APB

Table 2.1-4. Power-down domain peripherals

Start Address Module Bus Interface

A001_0000 TRNG APB

A002_0000 DMA controller APB

A003_0000 INFRA MBIST configuration APB

A004_0000 Serial flash APB

A005_0000 External memory interface APB

A006_0000 Crypto Engine APB

A007_0000 ADUIO APB

A008_0000 ASYS APB

A00A_0000 SPI_MASTER 0 APB

A00B_0000 SPI_SLAVE APB

A00C_0000 UART 0 APB

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Start Address Module Bus Interface

A00D_0000 UART 1 APB

A00E_0000 UART 2 APB

A010_0000 I2C_0 APB

A011_0000 I2C_1 APB

A012_0000 Auxiliary ADC Unit APB

A100_0000 PD DMA AHB

A101_0000 ADUIO AHB

A102_0000 ASYS AHB

A103_0000 SDIO Master AHB

A104_0000 SDIO Slave AHB

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3. External Interrupt Controller

3.1. Overview

The external interrupt controller (EINT) consists of up to 32 edge detectors to generate event or interrupt

requests. Each input line can be independently configured to select type (event or interrupt) and the

corresponding trigger event (rising edge or falling edge or both or level). Each line can also be masked

independently. A pending register maintains the status line of the interrupt requests.

3.2. Features

The EINT controller offers the following main features:

• Independent trigger and mask on each interrupt/event line.

• Dedicated status bit for each interrupt line.

• Generation of up to 32 software interrupt/event requests.

3.3. Block diagram

Figure 3.3-1 shows the block diagram of the EINT controller.

AMBA APB bus

Peripheral interface

De-bounce

circuit

Polarity

detect

circuit

Edge detect

circuit Sync circuit

De-bounce

config

register

32

Polarity

set/clear

register

32

Software

interrupt

register

32

Sensitivity

set/clear

register

32

Dual edge

sensitivity

set/clear

register

32

Interrupt

mask

set/clear

register

32

Wakeup

event mask

set/clear

register

32

Interrupt

mask

set/clear

register

32

1

To NVIC

interrupt

controller

To SPM event

cotroller

Figure 3.3-1. EINT block diagram

3.4. Wakeup event management

MT7686 is able to handle external or internal events in order to wake up the core (WFI). The wakeup event can be

generated by:

• Configuring an external or internal EINT line in event mode. When the CPU resumes from WFI, it is not

necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending

bit corresponding to the event line is not set.

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3.5. Functions

To generate an interrupt, an interrupt line should be configured and enabled. Program two trigger registers with

desired edge detection (EINT_SENS, EINT_DUALEDGE_SENS, EINT_POL) and enable an interrupt request by

writing “1” to the corresponding bit in the interrupt mask clear register (EINT_MASK_CLR). When the selected

trigger occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to

the interrupt line is also set in the EINT interrupt status register (EINT_STA). This request is reset by writing “1” in

the EINT interrupt acknowledge register (EINT_INTACK).

To generate the event, the event line should be configured and enabled. Program three trigger registers with

desired edge detection (EINT_SENS, EINT_DUALEDGE_SENS, EINT_POL) and enable the event request by

writing “1” to the corresponding bit in the event mask clear register (EINT_WACKUP_MASK_CLR) and interrupt

mask clear register (EINT_MASK_CLR). When the selected trigger occurs on the event line, an event request is

generated. The pending bit corresponding to the event line is also set in the EINT interrupt status register

(EINT_STA). This request is reset by writing “1” in the EINT interrupt acknowledge register (EINT_INTACK).

3.5.1. Hardware interrupt

To configure the 32 lines as interrupt sources:

• Configure the mask bits of the 32 interrupt lines (EINT_MASK_CLR).

• Configure the trigger selection bits of the interrupt lines (EINT_SENS_SET, EINT_SENS_CLR,

EINT_DUALEDGE_SENS_SET, EINT_DUALEDGE_SENS_CLR, EINT_POL_SET, EINT_POL_CLR).

Register setting

Trigger Type

EINT_SENS_SET EINT_SENS_CLR EINT_DUALEDGE

_SENS_SET

EINT_DUALEDGE

_SENS_CLR

EINT_POL_SET EINT_POL_CLR

↑

(Rising Edge)

0

1

0

1

0

↓(Falling Edge)

0

1

0

1

0

1

↑↓

(Dual Edge)

0

1

0

Don’t care

(High Level)

1

0

Don’t care

1

0

(Low Level)

1

0

Don’t care

0

1

• Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt

controller (EINT) so that an interrupt coming from one of the 32 lines can be correctly acknowledged.

3.5.2. Hardware events

To configure the 32 lines as event sources:

• Configure the mask bits of the 32 event lines (EINT_WACKUP_MASK_CLR and EINT_MASK_CLR).

• Configure the trigger selection bits of the event lines (EINT_SENS_SET, EINT_SENS_CLR,

EINT_DUALEDGE_SENS_SET, EINT_DUALEDGE_SENS_CLR, EINT_POL_SET, EINT_POL_CLR).

3.5.3. Software interrupt

The 32 lines can be configured as software interrupt lines. To generate a software interrupt:

• Configure the mask bits of the 32 interrupt lines (EINT_MASK_CLR).

• Set the required bit in the software interrupt register (EINT_SOFT_SET).

MT7686 Reference Manual

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3.6. External interrupt or event line mapping

Up to 21 GPIOs are connected to the 20 external interrupt/event lines, as shown in Table 3.6-1.

Table 3.6-1. External interrupt sources

EINT Source pin

EINT0 PAD_GPIO_0 if (GPIO0_MODE==1)

EINT1 PAD_GPIO_1 if (GPIO1_MODE==1)

EINT2 PAD_GPIO_2 if (GPIO2_MODE==1)

EINT3 PAD_GPIO_3 if (GPIO3_MODE==1)

EINT4 PAD_GPIO_4 if (GPIO4_MODE==3)

EINT5 PAD_GPIO_5 if (GPIO5_MODE==3)

EINT6 PAD_GPIO_6 if (GPIO6_MODE==3)

EINT7 PAD_GPIO_7 if (GPIO7_MODE==3)

EINT8 PAD_GPIO_8 if (GPIO8_MODE==3)

EINT9 PAD_GPIO_9 if (GPIO9_MODE==3)

EINT10 PAD_GPIO_10 if (GPIO10_MODE==1)

EINT11 PAD_GPIO_11 if (GPIO11_MODE==1)

EINT12 PAD_GPIO_12 if (GPIO12_MODE==6)

EINT13 PAD_GPIO_13 if (GPIO13_MODE==8)

EINT14 PAD_GPIO_14 if (GPIO14_MODE==8)

EINT15 PAD_GPIO_15 if (GPIO15_MODE==8)

EINT16 PAD_GPIO_16 if (GPIO16_MODE==8)

EINT17 PAD_GPIO_17 if (GPIO17_MODE==8)

EINT18 PAD_GPIO_18 if (GPIO18_MODE==8)

EINT19 PAD_GPIO_19 if (GPIO19_MODE==2)

PAD_GPIO_21 if (GPIO19_MODE==2) in MT5932

EINT20 PAD_GPIO_20 if (GPIO20_MODE==2)

PAD_GPIO_22 if (GPIO20_MODE==2) in MT5932

EINT21 uart0_rxd

EINT22 uart1_rxd

EINT23 uart2_rxd

EINT24 rtc_event_b

EINT25 conn2ap_hif_int_b

EINT26 conn2ap_pse_irq_b

EINT27 conn2ap_wdt_irq_b

EINT28 conn2ap_mac_irq_b

EINT29 pmu_int_b

EINT30

EINT31

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3.7. Register mapping

Module name: EINT Base address: (+A2100000h)

Address

Name

Width

Register Function

A2100300

EINT_STA

32

EINT interrupt status register

A2100308

EINT_INTACK

32

EINT interrupt acknowledge register

A2100310

EINT_EEVT

32

EINT wakeup event_b status register

A2100320

EINT_MASK

32

EINT interrupt mask register

A2100328

EINT_MASK_SET

32

EINT interrupt mask set register

A2100330

EINT_MASK_CLR

32

EINT interrupt mask clear register

A2100340

EINT_WAKEUP_MA

SK

32

EINT wakeup event mask register

A2100348

EINT_WAKEUP_MA

SK_SET

32

EINT wakeup event mask set register

A2100350

EINT_WACKUP_MA

SK_CLR

32

EINT wakeup event mask clear register

A2100360

EINT_SENS

32

EINT sensitivity register

A2100368

EINT_SENS_SET

32

EINT sensitivity set register

A2100370

EINT_SENS_CLR

32

EINT sensitivity clear register

A2100380

EINT_DUALEDGE_S

ENS

32

EINT dual edge sensitivity register

A2100388

EINT_DUALEDGE_S

ENS_SET

32

EINT dual edge sensitivity set register

A2100390

EINT_DUALEDGE_S

ENS_CLR

32

EINT dual edge sensitivity clear register

A21003A0

EINT_POL

32

EINT polarity register

A21003A8

EINT_POL_SET

32

EINT polarity set register

A21003B0

EINT_POL_CLR

32

EINT polarity clear register

A21003C0

EINT_SOFT

32

EINT software interrupt register

A21003C8

EINT_SOFT_SET

32

EINT software interrupt set register

A21003D0

EINT_SOFT_CLR

32

EINT software interrupt clear register

A2100400 ~

A210047C

EINTi_CON[n]

(n=0~31)

32

EINTi configuration register

3.7.1. Register definitions

A2100300

EINT_STA

EINT interrupt status register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Mne

EINT_STA[31:16]

Type

RO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Mne

EINT_STA[15:0]

Type

RO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_STA

External interrupt status

This register tracks

interrupt request status generated by certain EINT

sources. If the EINT sources are set to edge sensitivity, EINT_IRQ is de-

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asserted while the corresponding EINT_INTACK is set to 1.

EINT_STA[i]

for EINTi.

•

0: No external interrupt request is generated.

•

1: External interrupt request is pending.

A2100308

EINT_INTACK

EINT interrupt acknowledge register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Mne

EINT_INTACK[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Mne

EINT_INTACK[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_INTACK

Interrupt acknowledgement

Writing "1" to the specific bit position will acknowledge the interrupt

request correspondingly to the external interrupt line source.

EINT_INTACK[i] for EINTi.

0: No effect

1: Interrupt request is acknowledged.

A2100310

EINT_EEVT

EINT wakeup event_b

status register

00010000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Reset

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EEB

Type

RO

Reset

0

Bit(s)

Mnemonic

Name

Description

0

EEB

EINT wake up event_b

This register is a debugging port to monitor internal signals. It is an

asynchronous signal.

0: EINT wakes up the system from sleep mode.

1: EINT does not wake up the system from sleep mode.

A2100320

EINT_MASK

EINT interrupt mask register

FFFFFFFF

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_MASK[31:16]

Type

RO

Reset

1

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_MASK[15:0]

Type

RO

Reset

1

Bit(s)

Mnemonic

Name

Description

31:0

EINT_MASK

Interrupt mask

This register controls whether the EINT source is allowed to generate

MT7686 Reference Manual

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Bit(s)

Mnemonic

Name

Description

an interrupt request. Setting a specific bit position to "1" will prevent

activation of the external interrupt line.

EINT_MASK[i] for EINTi.

0: Interrupt request is enabled.

1: Interrupt request is disabled.

A2100328

EINT_MASK_S

ET

EINT interrupt mask set register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_MASK[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_MASK[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_MASK

Enables mask for the associated external interrupt source

This register is used to set up individual mask bits. Only the bits set to 1

are effective. EINT_MASK bits are also set to 1. Otherwise,

EINT_MASK bits will retain the original value.

EINT_MASK[i] for EINTi.

0: No effect

1: Enables the corresponding MASK bit.

A2100330

EINT_MASK_C

LR

EINT interrupt mask

clear register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_MASK[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_MASK[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_MASK

Disables mask for the associated external interrupt source

This register is used to clear individual mask bits. Only the bits set to 1

are effective. EINT_MASK bits are also cleared (set to 0). Otherwise,

EINT_MASK bits will retain the original value.

EINT_MASK[i] for EINTi.

0: No effect

1: Disables the corresponding MASK bit.

A2100340

EINT_WAKEU

P_MASK

EINT wakeup event mask register

FFFFFFFF

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_WAKEUP_MASK[31:16]

Type

RO

Reset

1

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_WAKEUP_MASK[15:0]

Type

RO

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Reset

1

Bit(s)

Mnemonic

Name

Description

31:0

EINT_WAKEUP_M

ASK

Wakeup event mask

This register controls whether the EINT source is allowed to generate a

wakeup event request. Setting a specific bit position to "1" will prevent

activation of the external interrupt line.

EINT_WAKEUP_MASK[i] for EINTi.

0: Wakeup event request is enabled.

1: Wakeup event request is disabled.

A2100348

EINT_WAKEU

P_MASK_SET

EINT wakeup

event mask set register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_WAKEUP_MASK[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_WAKEUP_MASK[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_WAKEUP_M

ASK

Enables mask for the associated external interrupt source

This register is used to set up individual mask bits. Only the bits set to 1

are effective. EINT_WAKEUP_MASK bits are also set to 1. Otherwise,

EINT_WAKEUP_MASK bits will retain the original value.

EINT_WAKEUP_MASK[i] for EINTi.

0: No effect

1: Enables the corresponding MASK bit.

A2100350

EINT_WAC

KU

P_MASK_CLR

EINT wakeup event mask clear register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_WAKEUP_MASK[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_WAKEUP_MASK[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_WAKEUP_M

ASK

Disables mask for the associated external interrupt source

This register is used to clear individual mask bits. Only the bits set to 1

are effective. EINT_WAKEUP_MASK bits are also cleared (set to 0).

Otherwise, EINT_WAKEUP_MASK bits will retain the original value.

EINT_WAKEUP_MASK[i] for EINTi.

0: No effect

1: Disables the corresponding MASK bit.

A2100360

EINT_SENS

EINT sensitivity register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_SENS[31:16]

MT7686 Reference Manual

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Type

RO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_SENS[15:0]

Type

RO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_SENS

Sensitivity type of the associated external interrupt source

Sensitivity type of external interrupt source.

EINT_SENS[i] for EINTi.

0: Edge sensitivity (active high or low depends on POL setting)

1: Level sensitivity (active high or low depends on POL setting)

A2100368

EINT_SENS_S

ET

EINT sensitivity set register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_SENS[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_SENS[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_SENS

Enables sensitive for the associated external interrupt

source.

This register is used to set up individual sensitive bits. Only the bits set

to 1 are effective. EINT_SENS bits are also set to 1. Otherwise,

EINT_SENS bits will retain the original value.

EINT_SENS[i] for EINTi.

0: No effect

1: Enables the corresponding SENS bit.

A2100370

EINT_SENS_C

LR

EINT sensitivity

clear register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_SENS[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_SENS[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_SENS

Disables sensitive for the associated external interrupt

source.

This register is used to clear individual sensitive bits. Only the bits set

to 1 are effective. EINT_SENS bits are also cleared (set to 0).

Otherwise, EINT_SENS bits will retain the original value.

EINT_SENS[i] for EINTi.

0: No effect

1: Disables the corresponding SENS bit.

MT7686 Reference Manual

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A2100380

EINT_DUALED

GE_SENS

EINT dual edge sensitivity register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_DUALEDGE_SENS[31:16]

Type

RO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_DUALEDGE_SENS[15:0]

Type

RO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_DUALEDGE_

SENS

Dual edge sensitivity type of the associated external interrupt

source

Dual edge sensitivity type of external interrupt source. (EINT_SENS

should be 0)

EINT_DUALEDGE_SENS[i] for EINTi.

0: Disable

1: Enable (no dependency on POL).

A2100388

EINT_DUALED

GE_SENS_SET

EINT dual edge sensitivity set register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_DUALEDGE_SENS[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_DUALEDGE_SENS[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_DUALEDGE_

SENS

Enables dual edge sensitivity for the associated external

interrupt source.

This register is used to set up individual dual edge sensitive bits.

(EINT_SENS should be 0)

Only the bits set to 1 are effective. EINT_DUALEDGE_SENS bits are

also set to 1. Otherwise, EINT_DUALEDGE_SENS bits will retain the

original value.

EINT_DUALEDGE_SENS[i] for EINTi.

0: No effect

1: Enables the corresponding DUALEDGE bit.

A2100390

EINT_DUALED

GE_SENS_CLR

EINT dual edge sensitivity clear register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_DUALEDGE_SENS[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_DUALEDGE_SENS[15:0]

Type

WO

Reset

0

MT7686 Reference Manual

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Bit(s)

Mnemonic

Name

Description

31:0

EINT_DUALEDGE_

SENS

Disables dual edge sensitive for the associated external

interrupt source.

This register is used to clear individual sensitive bits. Only the bits set

to 1 are effective.

EINT_DUALEDGE_SENS bits are also cleared (set to

0). Otherwise, EINT_DUALEDGE_SENS bits will retain the original

value.

EINT_DUALEDGE_SENS[i] for EINTi.

0: No effect

1: Disables the corresponding DUALEDGE bit.

A21003A0

EINT_POL

EINT polarity register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_POL[31:16]

Type

RO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_POL[15:0]

Type

RO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_POL

Configures polarity of the associated external interrupt

source.

Activation type of the EINT source.

EINT_POL[i] for EINTi.

0: Active low

1: Active high

A21003A8

EINT_POL_SE

T

EINT polarity set register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_POL[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_POL[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_POL

Enables polarity configuration for the associated external

interrupt source

This register is used to set up individual polarity bits. Only the bits set

to 1 are effective. EINT_POL bits are also set to 1. Otherwise,

EINT_POL bits will retain the original value.

EINT_POL[i] for EINTi.

0: No effect

1: Enables the corresponding POL bit.

A21003B0

EINT_POL_CL

R

EINT polarity clear register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_POL[31:16]

Type

WO

Reset

0

MT7686 Reference Manual

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Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_POL[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_POL

Polarity configuration set

This register is used to clear individual polarity bits. Only the bits set to

1 are effective. EINT_POL bits are also cleared (set to 0). Otherwise,

EINT_POL bits will retain the original value.

EINT_POL[i] for EINTi.

0: No effect

1: Disables the corresponding POL bit.

A21003C0

EINT_SOFT

EINT software

interrupt register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_SOFT[31:16]

Type

RO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_SOFT[15:0]

Type

RO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_SOFT

Software interrupt

This register is used for debugging purposes.

EINT_SOFT[i] for EINTi.

0: No effect

1: Triggers an EINT

A21003C8

EINT_SOFT_S

ET

EINT

software interrupt set register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

EINT_SOFT[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_SOFT[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_SOFT

Enables software for the associated external interrupt source

This register is used to set up individual software bits. Only the bits set

to 1 are effective. EINT_SOFT bits are also set to 1. Otherwise,

EINT_SOFT bits will retain the original value.

EINT_SOFT[i] for EINTi.

0: No effect

1: Enables the corresponding SOFT bit.

A21003D0

EINT_SOFT_C

LR

EINT software

interrupt clear register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

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Name

EINT_SOFT[31:16]

Type

WO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

EINT_SOFT[15:0]

Type

WO

Reset

0

Bit(s)

Mnemonic

Name

Description

31:0

EINT_SOFT

Disables software for the associated external interrupt

source

This register is used to clear individual software bits. Only the bits set

to 1 are effective. EINT_SOFT bits are also cleared (set to 0).

Otherwise, EINT_SOFT bits will retain the original value.

EINT_SOFT[i] for EINTi.

0: No effect

1: Disables the corresponding SOFT bit.

A2100400~

A210047C

(step =

0x4)

EINTi_CON[n]

(n=0~31)

EINTi config register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

RSTD

BC

DBC_

EN

Type

WO

RW

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

DBC_CON

Type

RW

Reset

0

Bit(s)

Mnemonic

Name

Description

24

RSTDBC

EINTi debounce count reset

Write 1 to reset the de-bounce counter so that EINT can be updated

immediately without de-bounce latency. This option needs 100usec

latency to take effect.

0: no effect

1: reset

16

DBC_EN

EINTi debounce circuit enable

0: disable

1: enable

14:0

DBC_CON

EINTi debounce count setting

DBC_CNT = DBC_CON[10:0]

EINTi debounce duration config

(clock period is determined in PRESCALER)

Note: When DBD_CON[10:0] = 0 and DBC_EN = 1

, there are still two

32K clock cycles (62.5 us) debounce. If you want to disable debounce

function, DBC_EN should be set to 0 (Zero).

PRESCALER = DBC_CON[14:12]

EINTi debounce clock cycle period prescaler.

000: 32,768Hz, max. 0.0625sec

001: 16,384Hz

010: 8,192Hz

011: 4,096Hz

100: 2,048Hz, max. 1sec

101: 1,024Hz

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Bit(s)

Mnemonic

Name

Description

110: 512Hz

111: 256Hz, max. 8secs

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4. Direct Memory Access

4.1. Overview

A DMA controller is placed on AHB bus to support fast data transfers and off-load the processor. With this

controller, specific devices on AHB or APB buses can benefit greatly from quick completion of data movement from

or to memory modules. Such generic DMA controller can also be used to connect two devices other than memory

modules as long as they can be addressed in memory space. Figure 4.1-1 illustrates the system connections.

Memory Arbiter

DMA

Peripheral

MCU-DSP

Interface

ABP

Bridge

Peripheral

AHB Bus

APB Bus

Figure 4.1-1. Variety data paths of DMA transfers

4.2. Features

There is a round-robin arbitration mechanism to support up to 16 channels working simultaneously. Each channel

has a similar set of registers to be configured to different schemes as desired. Both interrupt and polling based

schemes are supported to handle the completion events.

The block diagram of DMA operation is shown in Figure 4.2-1.

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PDMA

VDMA

GDMA

Global Controller

APB

Interface AHB

Interface

Configuration

Configuration Transaction

Transaction

Configuration

Figure 4.2-1. DMA block diagram

4.3. Functions

There are three types of DMA channels in the DMA controller: full-size DMA, half-size DMA and virtual FIFO DMA.

Channel 1 is a full-size DMA channel, channels 2 to 6 are half-size channels and channels 7 to 16 are virtual FIFO

DMA channels. The difference between the first two types of DMA channels is that source and destination

addresses are programmable as full-size DMA channels, but the address of either source or destination only can be

programmed as a half-size DMA channel, while the address of the other side is fixed.

4.3.1. Ring buffer and double buffer memory data transfer

DMA channels 1 to 7 support ring-buffer and double-buffer memory data transfer. This can be achieved by

programming DMA_WPPT and DMA_WPTO, as well as setting up WPEN in the DMA_CON register to enable, as

shown in Figure 4.3-1. The next address jumps to WPTO address after WPPT data transfer is complete, once the

transfer counter reaches WPPT.

Note that only one side can be configured as ring-buffer or double-buffer memory, and this is controlled by WPSD

in the DMA_CON register.

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Figure 4.3-1. Ring buffer and double buffer memory data movement

4.3.2. Unaligned word access

The address of word access on AHB bus must be aligned to word boundary (the address must be multiple of 4), or

the two LSB are truncated to 00b. If the LSB is truncated incorrect data may be fetched. If the data is moved from

unaligned to aligned address, the word is usually split into four bytes then moved byte by byte. Thus, the four read

and four write transfers will appear on the bus.

To improve bus efficiency, the unaligned-word access is provided in DMA 2 to 7. If “byte-to-word (B2W)” function

is enabled in PDMAx_CON, the DMAs will move data from the unaligned address to aligned address by executing

four continuous byte-read accesses and one word-write access, reducing the number of transfers on the bus by

three, as shown in Figure 4.3-2.

Figure 4.3-2. Unaligned word accesses

4.3.3. Virtual FIFO DMA

Virtual FIFO DMA is used to ease UART control. The difference between the virtual FIFO DMA and the ordinary

DMA is that the virtual FIFO DMA contains additional FIFO controllers. The read and write pointers are kept in the

virtual FIFO DMA. To read from FIFO, the read pointer points to the address of the next data. To write into the

FIFO, the write pointer moves to the next address. If the FIFO is empty, a FIFO read will not be allowed. Similarly,

the data will not be written to the FIFO if the FIFO is full. Due to UART flow control requirements, an alert length

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(VDMAx_ALTLEN) is programmed. If the FIFO space is smaller than this value, an alert signal is issued to enable the

UART flow control. The type of flow control performed depends on the UART configuration settings.

Each virtual FIFO DMA can be programmed as receive (RX) or transmit (TX) FIFO. This depends on the DIR setting in

the DMA_CON register. If DIR is “0” (READ), the virtual FIFO DMA is specified as a TX FIFO. On the other hand, if

DIR is “1” (WRITE), the virtual FIFO DMA will be specified as an RX FIFO.

The virtual FIFO DMA provides an interrupt to MCU to notify data availability in the FIFO and the amount of data is

above or under the value defined in the DMA_COUNT register. Based on this, the MCU does not need to poll the

DMA to know when the data must be removed from or put into the FIFO.

Memory

Destination Address

FIFO Size

Virtual FIFO

Read Pointer

(MCU)

Write Pointer

(UART RX)

Memory

Source Address

FIFO Size

Virtual FIFO

Read Pointer

(UART TX)

Write Pointer

(MCU)

Figure 4.3-3. Virtual FIFO DMA

4.4. Application and programming sequence

DMA channels 7 to 16 are virtual FIFO DMA with corresponding peripherals. The access ports for the MCU of each

VDMA are listed in Table 4.4-1. MCU treats the virtual FIFO access port as a real FIFO, but the physical location or

size is configured by registers of each channel.

Table 4.4-1. Virtual FIFO access ports

DMA number Address of virtual FIFO access port Reference UART

DMA7 A100_0000h AUD_TX

DMA8 A100_0100h AUD_RX

DMA9 A100_0200h ASYS TX

DMA10 A100_0300h ASYS RX

DMA11 A100_0400h UART2 TX

DMA12 A100_0500h UART2 RX

DMA13 A100_0600h UART1 TX

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DMA number Address of virtual FIFO access port Reference UART

DMA14 A100_0700h UART1 RX

DMA15 A100_0800h UART0 TX

DMA16 A100_0900h UART0 RX

Due to different types of DMA, the limitations for each peripheral are listed below.

Table 4-2. Function list of DMA channels

DMA number Type Ring

buffer

Double

buffer

Burst

mode

Unaligned

word access

Peripheral

DMA1 Full size

●

DMA2 Half size

●

I2C0 TX

DMA3 Half size

●

I2C0 RX

DMA4 Half size

●

I2C1 TX

DMA5 Half size

●

I2C1 RX

DMA6 Half size

●

HIF_TX,RX

DMA7 Virtual

FIFO

●

AUD_TX

DMA8 Virtual

FIFO

●

AUD_RX

DMA9 Virtual

FIFO

●

ASYS TX

DMA10 Virtual

FIFO

●

ASYS RX

DMA11 Virtual

FIFO

●

UART2 TX

DMA12 Virtual

FIFO

●

UART2 RX

DMA13 Virtual

FIFO

● UART1 TX

DMA14 Virtual

FIFO

● UART1 RX

DMA15 Virtual

FIFO

● UART0 TX

DMA16 Virtual

FIFO

●

UART0 RX

4.5. Register mapping

There are 16 DMA channels in this SOC. The usage of the registers below is the same except that the base address

should be changed to respective ones.

Module name: DMA Base address: (+a0020000h)

Address

Name

Width

Register Functionality

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A0020000

DMA_GLBSTA

32

DMA global status

A0020008

DMA_GLB_CPU0_CF

G

32

DMA top hierarchy interrupt

configuration

A002000C

DMA_GLB_CPU0_SE

T

32

DMA top hierarchy interrupt

setting

A0020010

DMA_GLB_CPU0_CL

R

32

DMA top hierarchy interrupt clear

A0020028

DMA_GLBLIMITER

32

DMA global bandwidth limiter register

A0020020

DMA_GLB_SWRST

32

DMA global software reset

A0020040

DMA_GLB_BUSY

32

DMA global busy status

A0020044

DMA_GLB_INTR

32

DMA global interrupt status

A0020100

GDMA1_SRC

32

DMA channel 1

source address

A0020104

GDMA1_DST

32

DMA channel 1 destination address

A0020108

GDMA1_WPPT

32

DMA channel 1 wrap point address

A002010C

GDMA1_WPTO

32

DMA channel 1

wrap to address

A0020110

GDMA1_COUNT

32

DMA channel 1 transfer count

A0020114

GDMA1_CON

32

DMA channel 1 control

A0020118

GDMA1_START

32

DMA channel 1 start

A002011C

GDMA1_INTSTA

32

DMA channel 1 interrupt status

A0020120

GDMA1_ACKINT

32

DMA channel 1 interrupt acknowledge

A0020124

GDMA1_RLCT

32

DMA channel 1 remaining

length of

current transfer

A0020128

GDMA1_LIMITER

32

DMA channel 1 bandwidth limiter

A0020208

PDMA2_WPPT

32

DMA channel 2 wrap point address

A002020C

PDMA2_WPTO

32

DMA channel 2 wrap to address

A0020210

PDMA2_COUNT

32

DMA channel 2 transfer count

A0020214

PDMA2_CON

32

DMA channel 2 control

A0020218

PDMA2_START

32

DMA channel

2 start

A002021C

PDMA2_INTSTA

32

DMA channel 2 interrupt status

A0020220

PDMA2_ACKINT

32

DMA channel 2 interrupt acknowledge

A0020224

PDMA2_RLCT

32

DMA channel 2

remaining length of

current transfer

A0020228

PDMA2_LIMITER

32

DMA channel 2 bandwidth limiter

A002022C

PDMA2_PGMADDR

32

DMA channel 2 programmable address

A0020308

PDMA3_WPPT

32

DMA channel 3 wrap point address

A002030C

PDMA3_WPTO

32

DMA channel 3 wrap to address

A0020310

PDMA3_COUNT

32

DMA channel 3 transfer count

A0020314

PDMA3_CON

32

DMA channel 3 control

A0020318

PDMA3_START

32

DMA channel 3 start

A002031C

PDMA3_INTSTA

32

DMA channel 3 interrupt status

A0020320

PDMA3_ACKINT

32

DMA channel 3 interrupt acknowledge

A0020324

PDMA3_RLCT

32

DMA channel 3 remaining length of

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current transfer

A0020328

PDMA3_LIMITER

32

DMA channel 3

bandwidth limiter

A002032C

PDMA3_PGMADDR

32

DMA channel 3 programmable address

A0020408

PDMA4_WPPT

32

DMA channel 4 wrap point address

A002040C

PDMA4_WPTO

32

DMA

channel 4 wrap to address

A0020410

PDMA4_COUNT

32

DMA channel 4 transfer count

A0020414

PDMA4_CON

32

DMA channel 4 control

A0020418

PDMA4_START

32

DMA channel 4

start

A002041C

PDMA4_INTSTA

32

DMA channel 4 interrupt status

A0020420

PDMA4_ACKINT

32

DMA channel 4 interrupt acknowledge

A0020424

PDMA4_RLCT

32

DMA channel 4

remaining length of

current transfer

A0020428

PDMA4_LIMITER

32

DMA channel 4 bandwidth limiter

A002042C

PDMA4_PGMADDR

32

DMA channel 4 programmable address

A0020508

PDMA5_WPPT

32

DMA channel 5 wrap point address

A002050C

PDMA5_WPTO

32

DMA channel 5 wrap to address

A0020510

PDMA5_COUNT

32

DMA channel 5 transfer count

A0020514

PDMA5_CON

32

DMA channel 5 control

A0020518

PDMA5_START

32

DMA channel 5 start

A002051C

PDMA5_INTSTA

32

DMA channel 5 interrupt status

A0020520

PDMA5_ACKINT

32

DMA channel 5 interrupt acknowledge

A0020524

PDMA5_RLCT

32

DMA channel 5 remaining length of

current transfer

A0020528

PDMA5_LIMITER

32

DMA channel 5 bandwidth limiter

A002052C

PDMA5_PGMADDR

32

DMA channel 5 programmable address

A0020608

PDMA6_WPPT

32

DMA channel 6 wrap point address

A002060C

PDMA6_WPTO

32

DMA channel 6 wrap to

address

A0020610

PDMA6_COUNT

32

DMA channel 6 transfer count

A0020614

PDMA6_CON

32

DMA channel 6 control

A0020618

PDMA6_START

32

DMA channel 6 start

A002061C

PDMA6_INTSTA

32

DMA channel 6 interrupt status

A0020620

PDMA6_ACKINT

32

DMA channel 6 interrupt acknowledge

A0020624

PDMA6_RLCT

32

DMA channel 6 remaining length of

current transfer

A0020628

PDMA6_LIMITER

32

DMA channel 6 bandwidth limiter

A002062C

PDMA6_PGMADDR

32

DMA channel 6 programmable address

A0020710

VDMA7_COUNT

32

DMA

channel 7 transfer count

A0020714

VDMA7_CON

32

DMA channel 7 control

A0020718

VDMA7_START

32

DMA channel 7 start register

A002071C

VDMA7_INTSTA

32

DMA channel 7

interrupt status

A0020720

VDMA7_ACKINT

32

DMA channel 7 interrupt acknowledge

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A0020728

VDMA7_LIMITER

32

DMA channel 7 bandwidth limiter

A002072C

VDMA7_PGMADDR

32

DMA channel 7 programmable address

A0020730

VDMA7_WRPTR

32

DMA channel 7 write pointer

A0020734

VDMA7_RDPTR

32

DMA channel 7 read pointer

A0020738

VDMA7_FFCNT

32

DMA channel 7 FIFO count

A002073C

VDMA7_FFSTA

32

DMA channel 7 FIFO status

A0020740

VDMA7_ALTLEN

32

DMA channel 7 alert length

A0020744

VDMA7_FFSIZE

32

DMA channel

7 FIFO size

A0020810

VDMA8_COUNT

32

DMA channel 8 transfer count

A0020814

VDMA8_CON

32

DMA channel 8 control

A0020818

VDMA8_START

32

DMA channel 8 start register

A002081C

VDMA8_INTSTA

32

DMA channel 8 interrupt status

A0020820

VDMA8_ACKINT

32

DMA channel 8 interrupt acknowledge

A0020828

VDMA8_LIMITER

32

DMA channel 8

bandwidth limiter

A002082C

VDMA8_PGMADDR

32

DMA channel 8 programmable address

A0020830

VDMA8_WRPTR

32

DMA channel 8 write pointer

A0020834

VDMA8_RDPTR

32

DMA

channel 8 read pointer

A0020838

VDMA8_FFCNT

32

DMA channel 8 FIFO count

A002083C

VDMA8_FFSTA

32

DMA channel 8 FIFO status

A0020840

VDMA8_ALTLEN

32

DMA channel 8

alert length

A0020844

VDMA8_FFSIZE

32

DMA channel 8 FIFO size

A0020910

VDMA9_COUNT

32

DMA channel 9 transfer count

A0020914

VDMA9_CON

32

DMA channel 9 control

A0020918

VDMA9_START

32

DMA channel 9 start register

A002091C

VDMA9_INTSTA

32

DMA channel 9 interrupt status

A0020920

VDMA9_ACKINT

32

DMA channel 9 interrupt

acknowledge

A0020928

VDMA9_LIMITER

32

DMA channel 9 bandwidth limiter

A002092C

VDMA9_PGMADDR

32

DMA channel 9 programmable address

A0020930

VDMA9_WRPTR

32

DMA

channel 9 write pointer

A0020934

VDMA9_RDPTR

32

DMA channel 9 read pointer

A0020938

VDMA9_FFCNT

32

DMA channel 9 FIFO count

A002093C

VDMA9_FFSTA

32

DMA channel 9

FIFO status

A0020940

VDMA9_ALTLEN

32

DMA channel 9 alert length

A0020944

VDMA9_FFSIZE

32

DMA channel 9 FIFO size

A0020A10

VDMA10_COUNT

32

DMA channel 10 transfer

count

A0020A14

VDMA10_CON

32

DMA channel 10 control

A0020A18

VDMA10_START

32

DMA channel 10 start register

A0020A1C

VDMA10_INTSTA

32

DMA channel 10 interrupt

status

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A0020A20

VDMA10_ACKINT

32

DMA channel 10 interrupt acknowledge

A0020A28

VDMA10_LIMITER

32

DMA channel 10 bandwidth limiter

A0020A2C

VDMA10_PGMADDR

32

DMA

channel 10 programmable address

A0020A30

VDMA10_WRPTR

32

DMA channel 10 write pointer

A0020A34

VDMA10_RDPTR

32

DMA channel 10 read pointer

A0020A38

VDMA10_FFCNT

32

DMA channel 10 FIFO count

A0020A3C

VDMA10_FFSTA

32

DMA channel 10 FIFO status

A0020A40

VDMA10_ALTLEN

32

DMA channel 10 alert length

A0020A44

VDMA10_FFSIZE

32

DMA

channel 10 FIFO size

A0020B10

VDMA11_COUNT

32

DMA channel 11 transfer count

A0020B14

VDMA11_CON

32

DMA channel 11 control

A0020B18

VDMA11_START

32

DMA channel 11

start register

A0020B1C

VDMA11_INTSTA

32

DMA channel 11 interrupt status

A0020B20

VDMA11_ACKINT

32

DMA channel 11 interrupt acknowledge

A0020B28

VDMA11_LIMITER

32

DMA channel 11 bandwidth limiter

A0020B2C

VDMA11_PGMADDR

32

DMA channel 11 programmable address

A0020B30

VDMA11_WRPTR

32

DMA channel 11 write pointer

A0020B34

VDMA11_RDPTR

32

DMA channel 11 read pointer

A0020B38

VDMA11_FFCNT

32

DMA channel 11 FIFO count

A0020B3C

VDMA11_FFSTA

32

DMA channel 11 FIFO status

A0020B40

VDMA11_ALTLEN

32

DMA channel 11 alert length

A0020B44

VDMA11_FFSIZE

32

DMA channel 11 FIFO size

A0020C10

VDMA12_COUNT

32

DMA channel 12 transfer count

A0020C14

VDMA12_CON

32

DMA channel 12 control

A0020C18

VDMA12_START

32

DMA channel 12 start register

A0020C1C

VDMA12_INTSTA

32

DMA channel 12 interrupt status

A0020C20

VDMA12_ACKINT

32

DMA channel 12 interrupt acknowledge

A0020C28

VDMA12_LIMITER

32

DMA channel 12 bandwidth limiter

A0020C2C

VDMA12_PGMADDR

32

DMA channel 12 programmable address

A0020C30

VDMA12_WRPTR

32

DMA channel 12 write pointer

A0020C34

VDMA12_RDPTR

32

DMA channel 12 read pointer

A0020C38

VDMA12_FFCNT

32

DMA channel 12 FIFO count

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A0020C3C

VDMA12_FFSTA

32

DMA channel 12 FIFO status

A0020C40

VDMA12_ALTLEN

32

DMA channel 12 alert length

A0020C44

VDMA12_FFSIZE

32

DMA channel 12 FIFO size

A0020D10

VDMA13_COUNT

32

DMA channel 13 transfer count

A0020D14

VDMA13_CON

32

DMA channel 13 control

A0020D18

VDMA13_START

32

DMA channel 13 start register

A0020D1C

VDMA13_INTSTA

32

DMA channel 13 interrupt status

A0020D20

VDMA13_ACKINT

32

DMA channel 13 interrupt acknowledge

A0020D28

VDMA13_LIMITER

32

DMA channel 13 bandwidth

limiter

A0020D2C

VDMA13_PGMADDR

32

DMA channel 13 programmable address

A0020D30

VDMA13_WRPTR

32

DMA channel 13 write pointer

A0020D34

VDMA13_RDPTR

32

DMA channel

13 read pointer

A0020D38

VDMA13_FFCNT

32

DMA channel 13 FIFO count

A0020D3C

VDMA13_FFSTA

32

DMA channel 13 FIFO status

A0020D40

VDMA13_ALTLEN

32

DMA channel 13

alert length

A0020D44

VDMA13_FFSIZE

32

DMA channel 13 FIFO size

A0020E10

VDMA14_COUNT

32

DMA channel 14 transfer count

A0020E14

VDMA14_CON

32

DMA channel 14

control

A0020E18

VDMA14_START

32

DMA channel 14 start register

A0020E1C

VDMA14_INTSTA

32

DMA channel 14 interrupt status

A0020E20

VDMA14_ACKINT

32

DMA channel 14

interrupt acknowledge

A0020E28

VDMA14_LIMITER

32

DMA channel 14 bandwidth limiter

A0020E2C

VDMA14_PGMADDR

32

DMA channel 14 programmable address

A0020E30

VDMA14_WRPTR

32

DMA channel 14 write pointer

A0020E34

VDMA14_RDPTR

32

DMA channel 14 read pointer

A0020E38

VDMA14_FFCNT

32

DMA channel 14 FIFO count

A0020E3C

VDMA14_FFSTA

32

DMA channel 14 FIFO status

A0020E40

VDMA14_ALTLEN

32

DMA channel 14 alert length

A0020E44

VDMA14_FFSIZE

32

DMA channel 14 FIFO size

A0020F10

VDMA15_COUNT

32

DMA channel 15 transfer count

A0020F14

VDMA15_CON

32

DMA channel 15 control

A0020F18

VDMA15_START

32

DMA channel 15 start register

A0020F1C

VDMA15_INTSTA

32

DMA channel 15 interrupt status

MT7686 Reference Manual

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A0020F20

VDMA15_ACKINT

32

DMA channel 15 interrupt acknowledge

A0020F28

VDMA15_LIMITER

32

DMA channel 15 bandwidth limiter

A0020F2C

VDMA15_PGMADDR

32

DMA channel 15 programmable address

A0020F30

VDMA15_WRPTR

32

DMA channel 15 write pointer

A0020F34

VDMA15_RDPTR

32

DMA channel 15 read pointer

A0020F38

VDMA15_FFCNT

32

DMA channel 15 FIFO count

A0020F3C

VDMA15_FFSTA

32

DMA channel 15 FIFO status

A0020F40

VDMA15_ALTLEN

32

DMA channel 15 alert length

A0020F44

VDMA15_FFSIZE

32

DMA channel 15 FIFO size

A0021010

VDMA16_COUNT

32

DMA channel 16 transfer count

A0021014

VDMA16_CON

32

DMA channel 16 control

A0021018

VDMA16_START

32

DMA channel 16 start register

A002101C

VDMA16_INTSTA

32

DMA channel 16 interrupt status

A0021020

VDMA16_ACKINT

32

DMA channel 16 interrupt acknowledge

A0021028

VDMA16_LIMITER

32

DMA channel 16 bandwidth limiter

A002102C

VDMA16_PGMADDR

32

DMA channel 16 programmable address

A0021030

VDMA16_WRPTR

32

DMA channel 16

write pointer

A0021034

VDMA16_RDPTR

32

DMA channel 16 read pointer

A0021038

VDMA16_FFCNT

32

DMA channel 16 FIFO count

A002103C

VDMA16_FFSTA

32

DMA channel 16 FIFO

status

A0021040

VDMA16_ALTLEN

32

DMA channel 16 alert length

A0021044

VDMA16_FFSIZE

32

DMA channel 16 FIFO size

A0020000

DMA_GLBSTA

DMA global status

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name IT16

RUN1

6

IT15

RUN1

5

IT14

RUN1

4

IT13

RUN1

3

IT12

RUN1

2

IT11

RUN1

1

IT10

RUN1

0

IT9

RUN9

Type

RO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

IT8

RUN8

IT7

RUN7

IT6

RUN6

IT5

RUN5

IT4

RUN4

IT3

RUN3

IT2

RUN2

IT1

RUN1

Type

RO

Reset

0

Bit(s)

Name

Description

31

IT16

Channel 16 interrupt status

30

RUN16

Channel 16 running status

29

IT15

Channel 15 interrupt status

MT7686 Reference Manual

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28

RUN15

Channel 15 running status

27

IT14

Channel 14 interrupt status

26

RUN14

Channel 14 running status

25

IT13

Channel 13 interrupt status

24

RUN13

Channel 13 running status

23

IT12

Channel 12 interrupt status

22

RUN12

Channel 12 running status

21

IT11

Channel 11 interrupt status

20

RUN11

Channel 11 running status

19

IT10

Channel 10 interrupt status

18

RUN10

Channel 10 running status

17

IT9

channel 9 interrupt status

16

RUN9

channel 9 running status

15

IT8

Channel 8 interrupt status

14

RUN8

Channel 8 running status

13

IT7

Channel 7 interrupt status

12

RUN7

Channel 7 running status

11

IT6

Channel 6 interrupt status

10

RUN6

Channel 6 running status

9

IT5

Channel 5

interrupt status

8

RUN5

Channel 5 running status

7

IT4

Channel 4 interrupt status

6

RUN4

Channel 4 running status

5

IT3

Channel 3 interrupt status

4

RUN3

Channel 3 running status

3

IT2

Channel 2 interrupt status

2

RUN2

Channel 2 running status

1

IT1

Channel 1 interrupt status

0

RUN1

Channel 1 running status

A0020008

DMA_GLB_CPU0_CFG

DMA top hierarchy interrupt config

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Reset

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

CPU0

_CFG

16

CPU0

_CFG

15

CPU0

_CFG

14

CPU0

_CFG

13

CPU0

_CFG

12

CPU0

_CFG

11

CPU0

_CFG

10

CPU0

_CFG

9

CPU0

_CFG

8

CPU0

_CFG

7

CPU0

_CFG

6

CPU0

_CFG

5

CPU0

_CFG

4

CPU0

_CFG

3

CPU0

_CFG

2

CPU0

_CFG

1

Type

RW

Reset

0

Bit(s)

Name

Description

15

CPU0_CFG16

Channel 16 CPU0 interrupt enable configure

MT7686 Reference Manual

Page 32 of 536

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14

CPU0_CFG15

Channel 15 CPU0 interrupt enable configure

13

CPU0_CFG14

Channel 14 CPU0

interrupt enable configure

12

CPU0_CFG13

Channel 13 CPU0 interrupt enable configure

11

CPU0_CFG12

Channel 12 CPU0 interrupt enable configure

10

CPU0_CFG11

Channel 11 CPU0 interrupt enable configure

9

CPU0_CFG10

Channel 10 CPU0 interrupt enable

configure

8

CPU0_CFG9

Channel 9 CPU0 interrupt enable configure

7

CPU0_CFG8

Channel 8 CPU0 interrupt enable configure

6

CPU0_CFG7

Channel 7 CPU0 interrupt enable configure

5

CPU0_CFG6

Channel 6 CPU0 interrupt enable configure

4

CPU0_CFG5

Channel 5

CPU0 interrupt enable configure

3

CPU0_CFG4

Channel 4 CPU0 interrupt enable configure

2

CPU0_CFG3

Channel 3 CPU0 interrupt enable configure

1

CPU0_CFG2

Channel 2 CPU0 interrupt enable configure

0

CPU0_CFG1

Channel 1 CPU0 interrupt enable configure

A002000C

DMA_GLB_CPU0_SET

DMA top hierarchy interrupt set

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Reset

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

CPU0

_SET

16

CPU0

_SET

15

CPU0

_SET

14

CPU0

_SET

13

CPU0

_SET

12

CPU0

_SET

11

CPU0

_SET

10

CPU0

_SET

9

CPU0

_SET

8

CPU0

_SET

7

CPU0

_SET

6

CPU0

_SET

5

CPU0

_SET

4

CPU0

_SET

3

CPU0

_SET

2

CPU0

_SET

1

Type

WO

Reset

0

Bit(s)

Name

Description

15

CPU0_SET16

Channel 16 CPU0 interrupt enable set

14

CPU0_SET15

Channel 15 CPU0 interrupt enable set

13

CPU0_SET14

Channel 14 CPU0 interrupt

enable set

12

CPU0_SET13

Channel 13 CPU0 interrupt enable set

11

CPU0_SET12

Channel 12 CPU0 interrupt enable set

10

CPU0_SET11

Channel 11 CPU0 interrupt enable set

9

CPU0_SET10

Channel 10 CPU0 interrupt enable set

8

CPU0_SET9

Channel 9 CPU0 interrupt

enable set

7

CPU0_SET8

Channel 8 CPU0 interrupt enable set

6

CPU0_SET7

Channel 7 CPU0 interrupt enable set

5

CPU0_SET6

Channel 6 CPU0 interrupt enable set

4

CPU0_SET5

Channel 5 CPU0 interrupt enable set

3

CPU0_SET4

Channel 4 CPU0 interrupt enable set

2

CPU0_SET3

Channel 3 CPU0 interrupt enable set

1

CPU0_SET2

Channel 2 CPU0 interrupt enable set

0

CPU0_SET1

Channel 1 CPU0 interrupt enable set

MT7686 Reference Manual

Page 33 of 536

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A0020010

DMA_GLB_CPU0_CLR

DMA top hierarchy interrupt clr

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Reset

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

CPU0

_CLR

16

CPU0

_CLR

15

CPU0

_CLR

14

CPU0

_CLR

13

CPU0

_CLR

12

CPU0

_CLR

11

CPU0

_CLR

10

CPU0

_CLR

9

CPU0

_CLR

8

CPU0

_CLR

7

CPU0

_CLR

6

CPU0

_CLR

5

CPU0

_CLR

4

CPU0

_CLR

3

CPU0

_CLR

2

CPU0

_CLR

1

Type

WO

Reset

0

Bit(s)

Name

Description

15

CPU0_CLR16

Channel 16 CPU0 interrupt enable clear

14

CPU0_CLR15

Channel 15 CPU0 interrupt enable clear

13

CPU0_CLR14

Channel 14 CPU0 interrupt

enable clear

12

CPU0_CLR13

Channel 13 CPU0 interrupt enable clear

11

CPU0_CLR12

Channel 12 CPU0 interrupt enable clear

10

CPU0_CLR11

Channel 11 CPU0 interrupt enable clear

9

CPU0_CLR10

Channel 10 CPU0 interrupt enable clear

8

CPU0_CLR9

Channel 9 CPU0

interrupt enable clear

7

CPU0_CLR8

Channel 8 CPU0 interrupt enable clear

6

CPU0_CLR7

Channel 7 CPU0 interrupt enable clear

5

CPU0_CLR6

Channel 6 CPU0 interrupt enable clear

4

CPU0_CLR5

Channel 5 CPU0 interrupt enable clear

3

CPU0_CLR4

Channel 4 CPU0

interrupt enable clear

2

CPU0_CLR3

Channel 3 CPU0 interrupt enable clear

1

CPU0_CLR2

Channel 2 CPU0 interrupt enable clear

0

CPU0_CLR1

Channel 1 CPU0 interrupt enable clear

A0020028

DMA_GLBLIMITER

DMA global bandwidth limiter

register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Reset

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

LIMITER

Type

WO

Reset

0

Bit(s)

Name

Description

7:0

LIMITER

Utilization suppression

This register suppresses the bus utilization of the DMA channel.

From 0 to 255. 0 means no limitation, 255 means totally banned.

All other values indicate bus access permission for every (4 x n)

AHB clock.

A0020020

DMA_GLB_SWR

ST

DMA global software reset

00000000

MT7686 Reference Manual

Page 34 of 536

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Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Reset

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

SW_

RESE

T

Type

RW

Reset

0

Bit(s)

Name

Description

0

SW_RESET

Software reset

Write 1 to the register to reset

A0020040

DMA_GLB_BUSY

DMA global busy status

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Reset

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

RUN1

6

RUN1

5

RUN1

4

RUN1

3

RUN1

2

RUN1

1

RUN1

0

RUN9

RUN8

RUN7

RUN6

RUN5

RUN4

RUN3

RUN2

RUN1

Type

RW

Reset

0

Bit(s)

Name

Description

15

RUN16

Channel 16 running status

14

RUN15

Channel 15 running status

13

RUN14

Channel 14 running status

12

RUN13

Channel 13 running status

11

RUN12

Channel 12 running status

10

RUN11

Channel 11 running status

9

RUN10

Channel 10 running status

8

RUN9

Channel 9 running status

7

RUN8

Channel 8 running status

6

RUN7

Channel 7 running status

5

RUN6

Channel 6 running status

4

RUN5

Channel 5 running status

3

RUN4

Channel 4 running status

2

RUN3

Channel 3 running status

1

RUN2

Channel 2 running status

0

RUN1

Channel 1 running status

A0020044

DMA_GLB_INTR

DMA global interrupt status

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Reset

MT7686 Reference Manual

Page 35 of 536

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Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

IT16

IT15

IT14

IT13

IT12

IT11

IT10

IT9

IT8

IT7

IT6

IT5

IT4

IT3

IT2

IT1

Type

RW

Reset

0

Bit(s)

Name

Description

15

IT16

Channel 16 interrupt status

14

IT15

Channel 15 interrupt status

13

IT14

Channel 14 interrupt status

12

IT13

Channel 13 interrupt status

11

IT12

Channel 12 interrupt status

10

IT11

Channel 11 interrupt status

9

IT10

Channel 10

interrupt status

8

IT9

Channel 9 interrupt status

7

IT8

Channel 8 interrupt status

6

IT7

Channel 7 interrupt status

5

IT6

Channel 6 interrupt status

4

IT5

Channel 5 interrupt status

3

IT4

Channel 4 interrupt status

2

IT3

Channel 3 interrupt status

1

IT2

Channel 2 interrupt status

0

IT1

Channel 1 interrupt status

A0020100

GDMA1_SRC

DMA channel 1 source address

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

SRC

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SRC

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

SRC

GDMA source address

This register contains the base or current source address that the

DMA channel is currently operating on.

•

Writing into this register specifies the base address of the

transfer source for a DMA channel.

•

Reading this register will return the address value from which

the DMA is reading.

A0020104

GDMA1_DST

DMA channel 1 destination address

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

DST

MT7686 Reference Manual

Page 36 of 536

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e

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

DST

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

DST

GDMA destination address

This register contains the base or current destination address that

the DMA channel is currently operating on.

•

Writing into this register specifies the base address of the

transfer destination for a DMA channel.

•

Reading this register will return the address value to which the

DMA is writing.

A0020108

GDMA1_WPPT

DMA channel 1 wrap point

address

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

WPPT

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

WPPT

Transfer counts before jump

This register specifies the transfer count required to perform before

the jump point. This can be used to support ring buffer or double

buffer memory access. To enable the wrap function, two control

bits,

WPEN and WPSD in the DMA control register must be

programmed. If the transfer counter in the DMA engine matches

this value, an address jump will occur, and the next address will be

the address specified in

GDMAn_WPTO. To enable this function,

set up

WPEN in GDMAn_CON.

Note, that the total size of data specified in the wrap point count in

a DMA channel is determined by WPPT together with

SIZE in

GDMAn_CON

, such as WPPT x SIZE.

A002010C

GDMA1_WPTO

DMA channel 1 wrap to address

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

WPTO

Type

RW

Rese

0

MT7686 Reference Manual

Page 37 of 536

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t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

WPTO

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

WPTO

Jump address

This register specifies the destination address of a given DMA transfer to

support ring buffer or double buffer memory access. To enable the wrap

function, set the two control bits,

WPEN and WPSD

in the DMA control register.

A0020110

GDMA1_COUNT

DMA channel 1 transfer count

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

COUNT

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

COUNT

Number of transfers

This register specifies the number of transfers of the DMA channel is required to

perform. Upon completion, the DMA channel generates an interrupt request to

the processor while

ITEN in GDMAn_CON is set to 1.

•

Note that the total size of transfer data is determined by LEN and SIZE in

GDMAn_CON, such as LEN x SIZE.

A0020114

GDMA1_CON

DMA channel 1 control

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

ITE

N

SETTING

Type

RW

BURST

DR

EQ

Rese

t

0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SIZE DIRECTION

Type

RW

WP

EN

WP

SD

DIN

C

SIN

C

Rese

t

0 0 0 0 0 0

MT7686 Reference Manual

Page 38 of 536

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Bit(s)

Name

Description

24

ITEN

Enable DMA transfer

completion interrupt

•

0: Disable

•

1: Enable

19:16

SETTING

[16] Throttle and handshake control for DMA transfer.

The DMA master is able to throttle down the transfer rate by

request

-grant handshake process.

[19:18] Transfer type.

The burst

-type transfers have better bus efficiency. Apply this type

for larger data movement.

Note that the burst

-type transfer will not stop until all of the beats

in a burst are complete or the transfer length is reached. The

transfer type is restricted by SIZE. If SIZE is 00b,

i.e. byte transfer,

all four transfer types can be used. If SIZE is 01b (half

-word

transfer), 16

-

beat incrementing burst cannot be used. If SIZE is 10b,

i.e. word transfer, only single and 4

-beat incrementing burst can be

used.

•

[16] DREQ: 0, No throttle control during DMA transfer or

transfers occurred only between memories; 1, Hardware

handshake management.

•

[19:18] BURST: 00 = Single; 01 = Reserved; 10 = 4-beat

incrementing burst; 11 = Reserved;

9:8

SIZE

Data size within the confine of a bus cycle per

transfer.

These bits confine the data transfer size between the source and

destination to the specified value for individual bus cycle. The size

is in bytes and the maximum value is 4 bytes. It is mainly decided

by the data width of a DMA master.

•

00: Byte transfer/1 byte

•

01: Half-word transfer/2 bytes

•

10: Word transfer/4 bytes

•

11: Reserved

3:0

DIRECTION

[0] Incremental source address.

The source addresses increments after each transfer. If SIZE is in

bytes, the source address will increase by 1, if it’s in

half-word, it

will increase by 2 and if word, increase by 4.

[1] Incremental destination address.

The destination address increments after each transfer. If SIZE is in

bytes, the destination address will increase by 1, if it’s in half

-word,

it will incre

ase by 2 and if word, increase by 4.

[2] Wrap select

The side using address

-wrapping function. Only one side of a DMA

channel can activate the address

-wrapping function at a time.

[3] Wrap enable

Address

-wrapping for ring buffer and double buffer. The next

address of DMA jumps to

WRAP TO address when the current

address matches

WRAP POINT count.

•

[0]SINC:0=Disable; 1=Enable

•

[1]DINC:0=Disable; 1=Enable

•

[2]WPSD: 0=Address-wrapping on source; 1=Address-

wrapping on destination

MT7686 Reference Manual

Page 39 of 536

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

•

[3]WPEN: 0=Disable; 1=Enable

A0020118

GDMA1_START

DMA channel 1 start

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

ST

R

Type

RW

Rese

t

0

Bit(s)

Name

Description

15

STR

Start control for a DMA channel

This register controls the activity of a DMA channel. Note, that

prior to

setting STR to 1, all the register settings should be

configured. Once STR is set to 1, the hardware will not clear it

automatically no matter the DMA channel accomplishes the DMA

transfer or not. In other words, the value of STR stays at 1

regardless of t

he completion of the DMA transfer. Therefore, the

software program should reset STR to 0 before restarting another

DMA transfer. If this bit is cleared to 0 when DMA transfer is

active, the software should poll RUNn in DMA_GLBSTA after this

bit is cleared

to ensure the current DMA transfer is terminated by

the DMA engine.

•

0: The DMA channel is stopped.

•

1: The DMA channel is started and running.

A002011C

GDMA1_INTSTA

DMA channel 1 interrupt status

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

INT

Type

RW

Rese

t

0

Bit(s)

Name

Description

15

INT

Interrupt

status for DMA channel

•

0: No interrupt request is generated.

•

1: An interrupt request is pending and waiting for service.

A0020120

GDMA1_ACKINT

DMA channel 1 interrupt acknowledge

00000000

MT7686 Reference Manual

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Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

AC

K

Type

WO

Rese

t

0

Bit(s)

Name

Description

15

ACK

Interrupt acknowledge

for the DMA channel

•

0: No effect

•

1: Interrupt request is acknowledged and should be

relinquished.

A0020124

GDMA1_RLCT

DMA channel 1 remaining length of

current transfer

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

RLCT

Type

RO

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

RLCT

This register is to reflect the remaining length of current

transfer (RLCT).

Note that this value is the transfer count, not the transfer data size.

A0020128

GDMA1_LIMITER

DMA channel 1 bandwidth limiter

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

LIMITER

Type

RW

Rese

t

0 0 0 0 0 0 0 0

MT7686 Reference Manual

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Bit(s)

Name

Description

7:0

LIMITER

Utilization Suppression

This register suppresses the bus utilization of the DMA channel.

From 0 to 255. 0 means no limitation, 255 means totally banned,

and others mean bus access permission every (4 x n) AHB clock.

A0020208

PDMA2_WPPT

DMA channel 2 wrap point address

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

WPPT

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

WPPT

Transfer counts before jump

This register specifies the transfer count required to perform before

the jump point. This can be used to support ring buffer or double

buffer memory access. To enable the wrap function, two control

bits,

WPEN and WPSD in the DMA control register must be

p

rogrammed. If the transfer counter in the DMA engine matches

this value, an address jump will occur, and the next address will be

the address specified in

GDMAn_WPTO. To enable this function,

set up

WPEN in GDMAn_CON.

Note, that the total size of data specified in the wrap point count in

a DMA channel is determined by WPPT together with

SIZE in

GDMAn_CON

, such as WPPT x SIZE.

A002020C

PDMA2_WPTO

DMA channel 2 wrap to address

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

WPTO

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

WPTO

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

WPTO

Jump address

This register specifies the address of the jump destination of a given DMA transfer

to support ring buffer or double buffer memory access. To enable this function, set

the two control bits, WPEN and WPSD in the DMA control register.

MT7686 Reference Manual

Page 42 of 536

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

A0020210

PDMA2_COUNT

DMA channel 2 transfer count

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

COUNT

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

COUNT

Number of transfers

This register specifies the number of transfers of the DMA channel is required to

perform. Upon completion, the DMA channel generates an interrupt request to

the processor while

ITEN in GDMAn_CON is set to 1.

Note that the total size of transfer data is d

etermined by LEN and SIZE in

GDMAn_CON

, such as LEN x SIZE.

A0020214

PDMA2_CON

DMA channel 2 control

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

ITE

N

SETTING

Type

RW

BURST

B2

W

DR

EQ

Rese

t

0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SIZE DIRECTION

Type

RW

DIR

WP

EN

WP

SD

DIN

C

SIN

C

Rese

t

0 0 0 0 0 0 0

Bit(s)

Name

Description

24

ITEN

Enable DMA

transfer completion interrupt

•

0: Disable

•

1: Enable

19:16

SETTING

[16] Throttle and handshake control for DMA transfer.

The DMA master is able to throttle down the transfer rate by

request

-grant handshake process.

[17]Byte to word

Word to byte or byte to

word transfer for the applications of

transferring non

-word-aligned-address data to word-aligned-

address data. Note that BURST is set to 4

-

beat burst this function is

enabled, and the SIZE is set to byte.

[19:18] Transfer type.

The burst-type transfers have better bus efficiency. Apply this type

MT7686 Reference Manual

Page 43 of 536

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

for mass data movement.

Note that the burst

-type transfer will not stop until all of the beats

in a burst are complete or the transfer length is reached. The

transfer type is restricted by SIZE. If SIZE is 00b,

i.e. byte transfer,

all four transfer types can be used. If SIZE is 01b (half

-word

transfer), 16

-

beat incrementing burst cannot be used. If SIZE is 10b,

i.e. word transfer, only single and 4

-beat incrementing burst can be

used.

•

[16] DREQ: 0, No throttle control during DMA transfer or

transfers occurred only between memories; 1, Hardware

handshake management.

•

[17]B2W: 0=Disable; 1=Enable

•

[19:18] BURST: 00 = Single; 01 = Reserved; 10 = 4-beat

incrementing burst; 11 = Reserved;

9:8

SIZE

Data size within the

confine of a bus cycle per transfer.

These bits confine the data transfer size between the source and

destination to the specified value for individual bus cycle. The size

is in bytes and the maximum value is 4 bytes. It is mainly decided

by the data width

of a DMA master.

•

00: Byte transfer/1 byte

•

01: Half-word transfer/2 bytes

•

10: Word transfer/4 bytes

•

11: Reserved

4:0

DIRECTION

[0] Incremental source address.

The source addresses increments after each transfer. If SIZE is in

bytes, the source address wil

l increase by 1, if it’s in half-word, it

will increase by 2 and if word, increase by 4.

[1] Incremental destination address.

The destination address increments after each transfer. If SIZE is in

bytes, the destination address will increase by 1, if it’s

in half-word,

it will increase by 2 and if word, increase by 4.

[2] Wrap select

The side using address

-wrapping function. Only one side of a DMA

channel can activate the address

-wrapping function at a time.

[3] Wrap enable

Address

-wrapping for ring buffer and double buffer. The next

address of DMA jumps to

WRAP TO address when the current

address matches

WRAP POINT count.

•

[0]SINC:0=Disable; 1=Enable

•

[1]DINC:0=Disable; 1=Enable

•

[2]WPSD: 0=Address-wrapping on source; 1=Address-

wrapping on destination

•

[3]WPEN: 0=Disable; 1=Enable

•

[4]DIR: 0=peripheral TX; 1=peripheral RX

A0020218

PDMA2_START

DMA channel 2 start

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

MT7686 Reference Manual

Page 44 of 536

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

ST

R

Type

RW

Rese

t

0

Bit(s)

Name

Description

15

STR

Start control for a DMA channel

This register controls the activity of a DMA channel. Note that prior

to setting STR to 1, all the register settings should be configured.

Once STR is set to 1, the hardware will not clear it automatically no

matter the DMA channel accomplishes the DMA transfer or not. In

other words, the value of STR stays at 1 regardless of the completion

of the DMA transfer. Therefore, the software program should reset

STR to 0 before restarting another DMA transfer. If this bit is

cleared to 0 when DMA transfer is active, the software should poll

RUNn in DMA_GLBSTA after this bit is

cleared to ensure the

current DMA transfer is terminated by the DMA engine.

•

0: The DMA channel is stopped.

•

1: The DMA channel is started and running.

A002021C

PDMA2_INTSTA

DMA channel 2 interrupt status

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

INT

Type

RW

Rese

t

0

Bit(s)

Name

Description

15

INT

Interrupt status for DMA channel

0: No interrupt request is generated.

1: One interrupt request is pending and waiting for service.

A0020220

PDMA2_ACKINT

DMA channel 2 interrupt acknowledge

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

AC

K

Type

WO

MT7686 Reference Manual

Page 45 of 536

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

Rese

t

0

Bit(s)

Name

Description

15

ACK

Interrupt

acknowledgement for the DMA channel

•

0: No effect

•

1: Interrupt request is acknowledged and should be relinquished.

A0020224

PDMA2_RLCT

DMA channel 2 remaining length of

current transfer

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

RLCT

Type

RO

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

RLCT

This register is to reflect the

remaining length of current

transfer (RLCT).

Note that this value is transfer count, not the transfer data size.

A0020228

PDMA2_LIMITER

DMA channel 2 bandwidth limiter

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

LIMITER

Type

RW

Rese

t

0 0 0 0 0 0 0 0

Bit(s)

Name

Description

7:0

LIMITER

Utilization Suppression

This

register suppresses the bus utilization of the DMA channel.

From 0 to 255. 0 means no limitation, 255 means totally banned,

and others mean bus access permission every (4 x n) AHB clock.

A002022C

PDMA2_PGMADDR

DMA channel 2 prog

rammable address

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

PGMADDR

MT7686 Reference Manual

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Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

PGMADDR

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

PGMADDR

PDMA programmable address.

The above registers specify the address for a half

-

size DMA channel.

This address represents the source address if DIR in DMA_CON is

set to 0 and represents the destination address if DIR in

PDMAn_CON

is set to 1.

A0020710

VDMA7_COUNT

DMA channel 7 transfer count

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

COUNT

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

COUNT

FIFO threshold

For virtual FIFO DMA, this register is used to configure the RX

threshold and TX threshold. The interrupt is triggered when FIFO

count is larger than or equal to RX threshold in RX path or FIFO

count is less than or equal to TX threshold in TX path.

Note,

that the ITEN bit in the VDMAn_CON register shall be set or

no interrupt will be issued. n is from 1 to 16.

A0020714

VDMA7_CON

DMA channel 7 control

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

ITE

N

DR

EQ

Type

RW

Rese

t

0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SIZE DIRECTION

Type

RW

DIR

Rese

t

0 0 0 0 0 0 0

MT7686 Reference Manual

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Bit(s)

Name

Description

24

ITEN

Enable DMA transfer completion interrupt

•

0: Disable

•

1: Enable

16

DREQ

Throttle and handshake control for DMA transfer.

The DMA master is able to throttle down the transfer rate by request

-grant

handshake.

•

0: No throttle control during DMA transfer or transfers occurred only

between memories

•

1: Hardware handshake management

9:8

SIZE

Data size within the confine of a bus cycle per transfer.

These bits confine the data transfer size between the source and destination

to the specified value for individual bus cycle. The size is in terms of byte,

and the maximum value is 4 bytes. It is mainly decided by the data width of

a DMA master.

•

00: Byte transfer/1 byte

•

01: Half-word transfer/2 bytes

•

10: Word transfer/4 bytes

•

11: Reserved

4:0

DIRECTION

[4]Directions of VDMA transfer

The direction is from the perspective of the DMA masters. WRITE means

reading from master and then writing to the address specified in

VDMAn_PGMADDR

, and vice versa. No effect on channel 1.