MegaAVR 0 Series Manual Mega AVR0 40002015A
User Manual:
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- Introduction
- Features
- Table of Contents
- 1. Block Diagram
- 2. megaAVR® 0-series Overview
- 3. Conventions
- 4. Acronyms and Abbreviations
- 5. Memories
- 6. Peripherals and Architecture
- 7. AVR CPU
- 7.1. Features
- 7.2. Overview
- 7.3. Architecture
- 7.4. Arithmetic Logic Unit (ALU)
- 7.5. Functional Description
- 7.6. Register Summary - CPU
- 7.7. Register Description
- 8. Nonvolatile Memory Controller (NVMCTRL)
- 9. Clock Controller (CLKCTRL)
- 10. Sleep Controller (SLPCTRL)
- 11. Reset Controller (RSTCTRL)
- 12. CPU Interrupt Controller (CPUINT)
- 12.1. Features
- 12.2. Overview
- 12.3. Functional Description
- 12.4. Register Summary - CPUINT
- 12.5. Register Description
- 13. Event System (EVSYS)
- 14. Port Multiplexer (PORTMUX)
- 15. I/O Pin Configuration (PORT)
- 16. Brown-Out Detector (BOD)
- 17. Voltage Reference (VREF)
- 18. Watchdog Timer (WDT)
- 19. 16-bit Timer/Counter Type A (TCA)
- 19.1. Features
- 19.2. Overview
- 19.3. Functional Description
- 19.4. Sleep Mode Operation
- 19.5. Register Summary - TCAn in Normal Mode (SPLITM in TCAn.CTRLD=0)
- 19.6. Register Description - Normal Mode
- 19.6.1. Control A
- 19.6.2. Control B - Normal Mode
- 19.6.3. Control C - Normal Mode
- 19.6.4. Control D
- 19.6.5. Control Register E Clear - Normal Mode
- 19.6.6. Control Register E Set - Normal Mode
- 19.6.7. Control Register F Clear
- 19.6.8. Control Register F Set
- 19.6.9. Event Control
- 19.6.10. Interrupt Control Register - Normal Mode
- 19.6.11. Interrupt Flag Register - Normal Mode
- 19.6.12. Debug Control Register
- 19.6.13. Temporary Bits for 16-Bit Access
- 19.6.14. Counter Register - Normal Mode
- 19.6.15. Period Register - Normal Mode
- 19.6.16. Compare n Register - Normal Mode
- 19.6.17. Period Buffer Register
- 19.6.18. Compare n Buffer Register
- 19.7. Register Summary - TCAn in Split Mode (SPLITM in TCAn.CTRLD=1)
- 19.8. Register Description - Split Mode
- 19.8.1. Control A
- 19.8.2. Control B - Split Mode
- 19.8.3. Control C - Split Mode
- 19.8.4. Control D
- 19.8.5. Control Register E Clear - Split Mode
- 19.8.6. Control Register E Set - Split Mode
- 19.8.7. Interrupt Control Register - Split Mode
- 19.8.8. Interrupt Flag Register - Split Mode
- 19.8.9. Debug Control Register
- 19.8.10. Low Byte Timer Counter Register - Split Mode
- 19.8.11. High Byte Timer Counter Register - Split Mode
- 19.8.12. Low Byte Timer Period Register - Split Mode
- 19.8.13. High Byte Period Register - Split Mode
- 19.8.14. Compare Register n For Low Byte Timer - Split Mode
- 19.8.15. High Byte Compare Register n - Split Mode
- 20. 16-bit Timer/Counter Type B (TCB)
- 20.1. Features
- 20.2. Overview
- 20.3. Functional Description
- 20.3.1. Definitions
- 20.3.2. Initialization
- 20.3.3. Operation
- 20.3.3.1. Modes
- 20.3.3.1.1. Periodic Interrupt Mode
- 20.3.3.1.2. Time-Out Check Mode
- 20.3.3.1.3. Input Capture on Event Mode
- 20.3.3.1.4. Input Capture Frequency Measurement Mode
- 20.3.3.1.5. Input Capture Pulse-Width Measurement Mode
- 20.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode
- 20.3.3.1.7. Single-Shot Mode
- 20.3.3.1.8. 8-Bit PWM Mode
- 20.3.3.2. Noise Canceler
- 20.3.3.3. Synchronized with TCAn
- 20.3.3.1. Modes
- 20.3.4. Events
- 20.3.5. Interrupts
- 20.3.6. Sleep Mode Operation
- 20.4. Register Summary - TCB
- 20.5. Register Description
- 21. Real-Time Counter (RTC)
- 21.1. Features
- 21.2. Overview
- 21.3. Clocks
- 21.4. RTC Functional Description
- 21.5. PIT Functional Description
- 21.6. Crystal Error Correction
- 21.7. Events
- 21.8. Interrupts
- 21.9. Sleep Mode Operation
- 21.10. Synchronization
- 21.11. Register Summary - RTC
- 21.12. Register Description
- 21.12.1. Control A
- 21.12.2. Status
- 21.12.3. Interrupt Control
- 21.12.4. Interrupt Flag
- 21.12.5. Temporary
- 21.12.6. Debug Control
- 21.12.7. Calibration
- 21.12.8. Clock Selection
- 21.12.9. Count
- 21.12.10. Period
- 21.12.11. Compare
- 21.12.12. Periodic Interrupt Timer Control A
- 21.12.13. Periodic Interrupt Timer Status
- 21.12.14. PIT Interrupt Control
- 21.12.15. PIT Interrupt Flag
- 21.12.16. Periodic Interrupt Timer Debug Control
- 22. Universal Synchronous and Asynchronous Receiver and Transmitter (USART)
- 22.1. Features
- 22.2. Overview
- 22.3. Functional Description
- 22.3.1. Initialization
- 22.3.2. Operation
- 22.3.2.1. Clock Generation
- 22.3.2.2. Frame Formats
- 22.3.2.3. Data Transmission - USART Transmitter
- 22.3.2.4. Data Reception - USART Receiver
- 22.3.2.5. USART in Master SPI mode
- 22.3.2.6. Half Duplex Operations
- 22.3.2.7. Start Frame Detection
- 22.3.2.8. Break Character Detection and Auto-Baud
- 22.3.2.9. Multiprocessor Communication Mode
- 22.3.2.10. IRCOM Mode of Operation
- 22.3.3. Events
- 22.3.4. Interrupts
- 22.4. Register Summary - USARTn
- 22.5. Register Description
- 22.5.1. Receiver Data Register Low Byte
- 22.5.2. Receiver Data Register High Byte
- 22.5.3. Transmit Data Register Low Byte
- 22.5.4. Transmit Data Register High Byte
- 22.5.5. USART Status Register
- 22.5.6. Control A
- 22.5.7. Control B
- 22.5.8. Control C - Async Mode
- 22.5.9. Control C - Master SPI Mode
- 22.5.10. Baud Register
- 22.5.11. Debug Control Register
- 22.5.12. IrDA Control Register
- 22.5.13. IRCOM Transmitter Pulse Length Control Register
- 22.5.14. IRCOM Receiver Pulse Length Control Register
- 23. Serial Peripheral Interface (SPI)
- 24. Two-Wire Interface (TWI)
- 24.1. Features
- 24.2. Overview
- 24.3. Functional Description
- 24.3.1. Initialization
- 24.3.2. General TWI Bus Concepts
- 24.3.3. TWI Bus State Logic
- 24.3.4. Operation
- 24.3.4.1. Electrical Characteristics
- 24.3.4.2. TWI Master Operation
- 24.3.4.2.1. Clock Generation
- 24.3.4.2.2. Transmitting Address Packets
- 24.3.4.2.2.1. Case M1: Arbitration Lost or Bus Error during Address Packet
- 24.3.4.2.2.2. Case M2: Address Packet Transmit Complete - Address not Acknowledged by Slave
- 24.3.4.2.2.3. Case M3: Address Packet Transmit Complete - Direction Bit Cleared
- 24.3.4.2.2.4. Case M4: Address Packet Transmit Complete - Direction Bit Set
- 24.3.4.2.3. Transmitting Data Packets
- 24.3.4.2.4. Receiving Data Packets
- 24.3.4.2.5. Quick Command Mode
- 24.3.4.3. TWI Slave Operation
- 24.3.4.4. Smart Mode
- 24.3.5. Interrupts
- 24.3.6. Sleep Mode Operation
- 24.4. Register Summary - TWIn
- 24.5. Register Description
- 24.5.1. Control A
- 24.5.2. Dual Mode Control Configuration
- 24.5.3. Debug Control
- 24.5.4. Master Control A
- 24.5.5. Master Control B
- 24.5.6. Master Status
- 24.5.7. Master Baud Rate
- 24.5.8. Master Address
- 24.5.9. Master DATA
- 24.5.10. Slave Control A
- 24.5.11. Slave Control B
- 24.5.12. Slave Status
- 24.5.13. Slave Address
- 24.5.14. Slave Data
- 24.5.15. Slave Address Mask
- 25. Cyclic Redundancy Check Memory Scan (CRCSCAN)
- 26. CCL – Configurable Custom Logic
- 27. Analog Comparator (AC)
- 28. Analog-to-Digital Converter (ADC)
- 28.1. Features
- 28.2. Overview
- 28.3. Functional Description
- 28.3.1. Initialization
- 28.3.2. Operation
- 28.3.3. Events
- 28.3.4. Interrupts
- 28.3.5. Sleep Mode Operation
- 28.4. Register Summary - ADCn
- 28.5. Register Description
- 28.5.1. Control A
- 28.5.2. Control B
- 28.5.3. Control C
- 28.5.4. Control D
- 28.5.5. Control E
- 28.5.6. Sample Control
- 28.5.7. MUXPOS
- 28.5.8. Command
- 28.5.9. Event Control
- 28.5.10. Interrupt Control
- 28.5.11. Interrupt Flags
- 28.5.12. Debug Run
- 28.5.13. Temporary
- 28.5.14. Result
- 28.5.15. Window Comparator Low Threshold
- 28.5.16. Window Comparator High Threshold
- 28.5.17. Calibration
- 29. Unified Program and Debug Interface (UPDI)
- 29.1. Features
- 29.2. Overview
- 29.3. Functional Description
- 29.3.1. Principle of Operation
- 29.3.2. Operation
- 29.3.3. UPDI Instruction Set
- 29.3.3.1. LDS - Load Data from Data Space Using Direct Addressing
- 29.3.3.2. STS - Store Data to Data Space Using Direct Addressing
- 29.3.3.3. LD - Load Data from Data Space Using Indirect Addressing
- 29.3.3.4. ST - Store Data from Data Space Using Indirect Addressing
- 29.3.3.5. LCDS - Load Data from Control and Status Register Space
- 29.3.3.6. STCS (Store Data to Control and Status Register Space)
- 29.3.3.7. REPEAT - Set Instruction Repeat Counter
- 29.3.3.8. KEY - Set Activation KEY
- 29.3.4. System Clock Measurement with UPDI
- 29.3.5. Interbyte Delay
- 29.3.6. System Information Block
- 29.3.7. Enabling of KEY Protected Interfaces
- 29.3.8. Events
- 29.3.9. Sleep Mode Operation
- 29.4. Register Summary - UPDI
- 29.5. Register Description
- 30. Instruction Set Summary
- 31. Data Sheet Revision History
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