4 Technical Reference Manual 1985 Tandy

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TRS-8CT
MODEL 4/4P
TECHNICAL
REFERENCE
MANUAL
CAT. NO. 26-2119

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TRSDOS* Version 6.2.0 Operating System:
£ 1984 Logical Systems.
Licensed to Tandy Corporation.
All Rights Reserved.
Model 4 4P Technical Reference Manual; Hardware Part:
& 1985 Tandy Corporation.
All Rights Reserved.
Model 4 4P Technical Reference Manual: Software Part:
c 1985 Tandy Corporation and Logical Systems.
All Rights Reserved.
Reproduction or use, without express written permission from Tandy Corporation of
any portion of this manual is prohibited. While reasonable efforts have been taken
in the preparation of this manual to assure its accuracy, Tandy Corporation assumes no liability resulting from any errors or omissions in this manual, or from the
use of the information contained herein.
TRSDOS is a registered trademark of Tandy Corporation.

10 9 8 7 6 5 4 3 2 1

SECTION I

4 THEORY OF OPERATION

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Hardware 1

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Part 1 / Hardware
SECTION I
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
1.1.10
1.1.11
1.1.12
1.1.13
1.2
1.3

Model 4 Theory of Operation
Introduction
CPU and Timing
Buffering
Address Decoding
ROM
RAM
Keyboard
Video
Real Time Clock
Cassette Circuitry
Printer Circuitry
I/O Connectors
Sound Option
Model 4 I/O BUS
Port Bits

1
3
3
3
3
3
7
7
7
7
9
9
9
9
10
13
16

SECTION II
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
2.1.10
2.1.11
2.1.12
2.1.13
2.1.14
2.1.15
2.1.16
2.1.17

Model 4 Gate Array Theory of Operation
Introduction
Reset Circuit
CPU
System Timing and Control Register
Address Decode
ROM
RAM
Video Circuit
Keyboard
Real Time Clock
Line Printer Port
Graphics Port
Sound Port
I/O Bus
Cassette Circuit
FDC Circuit
RS-232C Circuit

19
21
21
21
21
21
28
36
36
36
41
41
41
41
44
44
48
48
51

SECTION III
3.
3. .1
3. .2
3. .3
3. .4
3. .5
3.1.6
3.1.7
3.1.8
3.1.9
3.1.10
3.1.11
3. .12
3. .1 3
3. .14
3. .15
3. .16

Model 4P Theory of Operation
Introduction
Reset Circuit
CPU
System Timing
Address Decode
ROM
RAM
Video Circuit
Keyboard
Real Time Clock
Line Printer Port
Graphics Port
Sound
I/O Bus Port
FDC Circuit
RS-232C Circuit

55
57
57
57
57
57
60
60
71
85
87
87
87
91
91
91
93
98

SECTION IV
42
42 1
422
423
424
425
426
427
428
429
4210
4211
4 2 12
4 2 13
4 2 14
4215
4216
SECTION V

4P Gate Array Theory of Operation
Introduction
Reset Circuit
CPU
System Timing
Address Decode
ROM
RAM
Video Circuit
Keyboard
Real Time Clock
Line Printer Port
Graphics Port
Sound
I/O Bus Port
FDC Circuit
RS232C Circuit
Chip Specifications

101
103
103
103
103
103
105
105
116
130
132
132
132
136
136
136
138
142
147

INDEX

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1.1 MODEL 4 THEORY OF OPERATION
1.1.1 Introduction
The TRS 80 Model 4 Microcomputer is a self contained
desktop microcomputer designed not only to be completely
software compatible with the TRS 80 Model III, but to pro
vide many enhancements and features System distinctions
which enable the Model 4 to be Model III compatible
include a Z80 CPU capable of running at a 4 MHz clock
rate, BASIC operating system in ROM (14K), memory
mapped keyboard, 64 character by 16 line memory mapped
video display, up to 128K Random Access Memory, cassette
circuitry able to operate at 500 or 1500 baud, and the
ability to accept a variety of options These options include
one to four 5 1/4 inch double density floppy disk drives, one
to four five megabyte hard disk drives, an RS 232 Serial
Communications Interface, and a 640 by 240 pixel high
resolution graphics board

1.1.2 CPU and Timing
The central processing unit of the Model 4 microcomputer
is the Z80 A microprocessor - capable of running at either
a two (2 02752) or four (4 05504) MHz clock rate The mam
CPU timing comes from the 20 MHz (20 2752 MHz) crystal
controlled oscillator, Y1 and Q1 There is an additional
12 MHz (12672 MHz) oscillator, Y2 and Q2, which is
necessary for the 80 by 24 mode of video operation The
oscillator outputs are sent to two Programmable Array
Logic (PAL) circuits, U3 and U4, for frequency division
and routing of appropriate timing signals
PAL U3 divides the 20 MHz signal by five for 4 MHz CPU
operation, by ten for a 2 MHz rate, and slows the 4 MHz
clock for the M1 Cycle (See Figure 1-3) U3 also divides the
master clock by four to obtain a 5 MHz clock to be sent to
the RS-232 option connector as a reference for the baud
rate generator PAL U4 selects an appropriate 10 MHz or 12
MHz clock for the video shift clock, and using divider U5
provides additional timing signals to the video display circuitry (See Fig 1 -4)
Hex latch U18 is clocked from the 20 MHz clock, and is
used to provide MUX and CAS timing for the dynamic

1.1.3 Buffering
Low level signals from and to the CPU need to be buffered,
or current amplified in order to drive many other circuits
The 16 address lines are buffered by U55 and U56, which are
unidirectional buffers that are permanently enabled The
eight data lines are buffered by U71 Since data must flow
both to and from the CPU, U71 is a bi directional buffer
which can go into a three state condition when not m use
Both direction and enable controls come from the address
decoding section
The clock signal to the CPU (from PAL U3) is buffered by
active pullup circuit Q3 RESET and WAIT inputs to the
CPU are buffered by U17 and U46 Control outputs from
the Z80 (M1*, RD*, WR*, MREQ*, and IORQ*) are sent
to PAL U58, which combines these into other appropriate
control signals consistent with Model 4's architecture Other
than MREQ*, which is buffered by part of U38, the raw
control signals go to no other components, and hence require
no additional buffering

1.1.4 Address Decoding
The address decoding section is divided into two sub
sections Port address decoding and Memory address
decoding
In port address decoding, low order address lines (some
combined through a portion of U32) are sent to the address
and enable inputs of U48, U49, and U50 U48 is also enabled
by the IN* signal, which means that is decodes port input
signals, while U49 decodes port output signals A table of
the resulting port map is shown below

Read Function

Write Function

FC FF

Cassette In, Mode Read

F8 FB
F4 F7
F3
F2
F1

Read Printer Status
reserved
FDC Data Reg
FDC Sector Reg
FDC Track Reg

Cassette Out, resets
cassette data latch
Output to Printer
Drive Select latch
FDC Data Reg
FDC Sector Reg
FDC Track Reg.

Port Addr. (Hex)

(1)
(1)
(1)
(1)

memory circuits Also, with additional gates from U16,
U19, U20, U31, and U32, this chip provides the wait cir
cuitry necessary to prevent the CPU from accessing video
RAM during the active portion of the display This is done
by latching the data for the video RAM and simultaneously
forcing the Z80 CPU into a "WAIT" state and is necessary
to eliminate undesirable "hashing" of the video display
(See Fig 1-4)

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During screen refresh, the data outputs of the Video RAM
(ASCII character codes) are latched by U8 and become the
addresses for the character generator ROM (U23) In cases
of low resolution graphics a dual 1 of 4 data selector (U9)
is the cell generator with additional buffering from U10
The shift register U11 inputs are the latched data outputs
of the character or cell generator The shift clock input
comes from the PAL U4, and is 10 1376 MHz for the 64
by 16 mode and 12 672 MHz for 80 by 24 operation The
serial output from the shift register later becomes actual
video dot information
Special timing in the video circuit is handled by hex latch
U2 This includes blanking (originating from CRTC) and
shift register loading (originating from U4) Additional
video control and timing functions, such as sync buffering,
inversion selection, dot clock chopping, and graphics disable
of normal video are handled by miscellaneous gates in U12,
U13, U14, U22, U24,and U26

1.1.9 Real Time Clock
The Real Time Clock circuit in the Model 4 provides a 30
Hz (in the 2 MHz CPU Mode) or 60 Hz (in the 4 MHz CPU
Mode) interrupt to the CPU By counting the number of
interrupts that have occured, the CPU can keep track of the
time The 60 Hz vertical sync signal from the video circuitry
is divided by two (2 MHz Mode) by U53, and the 30 Hz at
pm 1 of U51 is used to generate the interrupts In the 4
MHz mode, signal FAST places a logic low at pm 1 of U51,
causing signal VSYNC to trigger the interrupts at the 60 Hz
rate Note that any time interrupts are disabled, the accuracy
of the clock suffers

1.1.10 Cassette Circuitry
The cassette write circuitry latches the two LSBs (DO and
D1) for any output to port FF (hex) The outputs of these
latches (U27) are then resistor summed to provide three
discrete voltage levels (500 Baud only) The firmware toggles
the bits to provide an output signal of the desired frequency
at the summing node
There are two types of cassette Read circuits — 500 baud and
1500 baud The 500 baud circuit is compatible with both
Model 1 and III The input signal is amplified and filtered
by Op amps (U43 and U28 Part of U15 then forms a
Zero Crossing Detector, the output of which sets the latch
U40 A read of Port FF enables buffer U41, which allows
the CPU to determine whether the latch has been set, and
simultaneously resets the latch The firmware determines
by the timing between settings of the latch whether a logic
"one" or "zero" was read in from the tape

The 1500 baud cassette read circuit is compatible with the
Model III cassette system The incoming signal is compared
to a threshold by part of U15 U15's output will then be
either high or low and clock about one half of U39, depend
mg on whether it is a rising edge or a falling edge If
interrupts are enabled, the setting of either latch will gene
rate an interrupt As in the 500 baud circuit, the firmware
decodes the interrupts into the appropriate data
For any cassette read or write operation, the cassette relay
must be closed in order to start the motor of the cassette
deck A write to port EC hex with bit one set will set latch
U42, which turns on transistor Q4 and energizes the relay
K1 A subsequent write to this port with bit one clear
will clear the latch and de energize the relay

1.1.11 Printer Circuitry
The printer status lines are read by the CPU by enabling
buffer U67 This buffer will be enabled for any input from
port F8 or F9, or any memory read from location 37E8
or 37E9 when in the Model III mode For a listing of bit
status, refer to the bit map
After the printer driver software determines that the printer
is ready to receive another character (by reading the status),
the character to be printed is output to port F8 This latches
the character into U66, and simultaneouly fires the one shot
U65 to provide the appropriate strobe to the printer

1.1.12 I/O Connectors
Two 20 pm single mime connectors, J7 and J8, are provided
for the connection of a Floppy Disk Controller and an
RS 232 Communications Interface, respectively All eight
data lines and the two least significant address lines are
routed to these connectors In addition, connections are
provided for device or board selection, interrupt enable,
interrupt status read, interrupt acknowledge, RESET, and
the CPU WAIT signal
The graphics connector, J10, contains all of the above inter
face signals, plus CRTCLK, the dotclock signal, a graphics
enable input, and other timing clocks which synchronize
the graphics board with the CRTC.
The I/O bus connector, J2, contains connections for all
eight data lines (buffered by U74), the low order address
lines (buffered by U73), and the control lines (buffered by
U75) IN*, OUT*, RESET*, M1*, and IORQ* In addition,
the I/O bus connector has inputs to allow the device(s),
connected to generate CPU WAIT states and interrupts

Hardware 9

is sent out to port 90H, alternately setting and clearing
data bit DO. The state of this bit is latched by sound board
U1 and amplified by sound board Q1, which drives a piezoelectric sound transducer. The speed of the software
loop determines the frequency, and thus, the pitch of the
resulting tone.

The sound connector, J11, contains only four connections:
sound enable (any output to port 90 hex), data bit DO,
Vcc, and ground.

1.1.13 Sound Option
The Model 4 sound option, available as standard equipment
on the disk drive versions, is a software intensive device. Data

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1.2 MODEL 4 I/O BUS
The Model 4 Bus is designed to allow easy and convenient
interfacing of I/O devices to the Model 4 The I/O Bus
supports all the signals necessary to implement a device com
patible with the Z 80s I/O structure That is
Addresses
A0 to A7 allow selection of up to 256^ input and 256
output devices if external I/O is enabled

For input port device use you must enable external I/O de
vices by writing to port 0ECH with bit 4 on in the user soft
ware This will enable the data bus address lines and control
signals to the I/O Bus edge connector When the input device is selected the hardware will acknowledge by asserting
EXTIOSEL* low This switches the data bus transceiver and
allows the CPU to read the contents of the I/O Bus data
lines See Figure 1 6 for the timing EXTIOSEL* can be generated by NANDmg IN and the I/O port address

^Ports 80H to 0FFH are reserved for System use
Data
DB0 to DB7 allow transfer of 8 bit data onto the pro
cessor data bus if external I/O is enabled
Control Lines
a
IN* — Z 80 signal specifying that an input is in pro
gress Gated with IORQ
b OUT* — Z 80 signal specifying that an output is in
progress Gated with IORQ
c
RESET* — system reset signal
d
IOBUSINT* - input to the CPU signaling an inter
rupt from an I/O Bus device if I/O Bus interrupts
are enabled
e
IOBUSWAIT* - input to the CPU wait line allow
mg I/O Bus device to force wait states on the Z 80
if external I/O is enabled
f
EXTIOSEL* - input to CPU which switches the
I/O Bus data bus transceiver and allows an INPUT
instruction to read I/O Bus data
g
M1* — and IORQ* -standard Z 80 signals

Output port device use is the same as the input port device in
use in that the external I/O devices must be enabled by writ
mg to port 0ECH with bit 4 on in the user software — in the
same fashion
For either input or output devices, the IOBUSWAIT* control
line can be used in the normal way for synchronizing slow
devices to the CPU Note that since dynamic memories are
used in the Model 4, the wait line should be used with cau
tion Holding the CPU in a wait state for 2 msec or more may
cause loss of memory contents since refresh is inhibited during
this time It is recommended that the IOBUSWAIT* line be
held active no more than 500 /jsec with a 25% duty cycle
The Model 4 will support Z 80 mode 1 interrupts A RAM
jump table is supported by the LEVEL II BASIC ROMs and
the user must supply the address of his interrupt service
routine by writing this address to locations 403E and 403F
When an interrupt occurs the program will be vectored to
the user supplied address if I/O Bus interrupts have been
enabled To enable I/O Bus interrupts the user must set bit
3 of Port 0E0H

The address line, data line, and control lines a to c and e to g
are enabled only when the ENEXIO bit in EC is set to a one
To enable I/O interrupts the EN IOBUSINT bit m the CPU
IOPORT E0 (output port) must be a one However, even if
it is disabled from generating interrupts the status of the
IOBUSINT* line can still read on the appropriate bit of CPU
IOPORT E0 (input port)
See Model 4 Port Bit assignment for port O F F 0 EC and
0E0 on pages 14 and 15
The Model 4 CPU board is fully protected from "foreign
I/O devices" in that all the I/O Bus signals are buffered and
can be disabled under software control To attach and use an
I/O device on the I/O Bus certain requirements (both hard
ware and software) must be met

Hardware 14

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Hardware 19

2.1 MODEL
OPERATION

4 GATE A R R A Y THEORY OF

2.1.1 Introduction

CPU Clock and RS232 Clock

The following discusses each element of the mam board of
the Model 4 Gate Array block diagram (see Figure 2-1) In
each case the intent is understanding the operation on a
practical level sufficient to aid in isolating a problem to the
failing component

Most of the timing generation for the board is shown in Figure 2-5 The Gate Array 4 1 1 is the basis for this timing as
it produces the 20 2752 MHz clock and then divides this
down to produce most of the other clocking functions used
on the board

2.1.2 Reset Circuit

The first clock that is produced is PCLK (pin 23) which
drives the CPU It is a divide by ten of the 20 2752 MHz in
the 2 MHz mode and a divide by 5 in the 4 MHz mode The
transition from one mode to the other is without glitches and
both modes are 50 percent duty cycles

Figure 2-2 shows the Reset circuit for generation of reset on
power up and when the reset switch is pushed on the keyboard The time constant determined by R8 and C25, is
used to allow the system to stabilize before triggering a one
shot (U63) with an approximate pulse width of 70 microsecs
When the reset switch is pushed, the input pin is brought to
ground and fires the one shot when the switch is released

Note that the signal that controls this mode also controls the
Real Time Clock circuit described later.

A second point to be noted is the signal POWRS* which is
used to reset the drive select latch in the FDC circuit

As a simple divide by four of the fundamental 20 2752 MHz,
the RS232CLK on pin 22 of U9 provides the basic clock to
the RS232C circuit

2.1.3 CPU

Video and Graphics Clocking and Timing

The central processing unit of the Model 4 microcomputer is
a Z80A microprocessor, and will run in either 2 or 4 MHz
mode All of the output lines of the Z80A are buffered The
address lines are buffered by two 74LS244s (U2 and U3
with the enable tied to ground), the control lines by a 74F04
(U27), and the data lines by a 74LS245 (U28 with the enable tied to BUSEN* and the direction control tied to
BUSDIR*)

The timing for both of these functions may be viewed as one
since they must operate synchronously and the same timing
must be generated for both The additional signals sent to
the Graphics Board allow it to maintain synchronization by
knowing the phase relation of the signals sent to both of
them To further understand the circuit of Figure 2-5 notice
the PLL Module (U8) This chip develops a 12 672 MHz signal which is phase locked to the 1 2672 MHz input on pin 5
and is a divide by 16 of the primary 20 2752 MHz clock
This provides the Gate Array 4 1 1 with two clocks to drive
the video display and the graphics circuits, 10 1376 MHz for
64 character display, and a 12 672 MHz for the 80 character
display

2.1.4 System Timing and Control Registers
Control Registers
The first of these registers is the WRINTMASKREG (U34)
This is only part of the register as this function is shared
with the Gate Array 4 5 The mam register contains RTC
ENCASINTFALL AND ENCASINTRISE The Gate Array has
the interrupts for the RS232C Interface and the I/O bus interrupts and a duplicate of the RTC
The second is the OPREG (U33) which contains the added
options of the Model 4 for video and Memory mapping
The last of the registers is MODOUT (U53) and is also readable through the CASSIN (U52) buffer It contains the Cassette motion controls, and the FAST control for Model 4

The following discussion will consider both the 64 and 80
character displays to be the same, the difference being the
primary frequency and not the phase relation or function of
the signals generated
The reference clock for the timing is DCLK (U9-15) and the
other clocks that are produced for the video output are derived from this clock (DOT* at U9-17 is a phase shift of
DCLK and is provided as an option for the the dot clock for
variations in delay paths in the video section) U9 then generates SHIFT* (pin 21), XADR7* (pin 20), CRTCLK (pin 19),
LOADS* (pin 18), and LOAD* (pin 16) for the proper timing
for the four video modes In addition for the Graphics Board
to synchronize with this timing H (pin 14), I (pin 13), and J
(pin 11) are fed to connector J12 See Figures 2-6 and 2-7
for the timing diagrams for video clocks generated by Gate
Array 4 1 1

Hardware 21

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Timing Generation
(Page 3 of Schematic)

Hardware 25

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DRAM Timing

The Video RAM and DRAM timing share the timing delay
line (U80) This is done by 'OR"mg the two signals GRAS*
and AINPRG* at U39 to get the signal STDEL* This is possible because the signals VIDEO and MREQ or MCYCEN
are gated in to mask off the signals that are not desired.

The DRAM timing is shown in Figure 2-9 At the begmmg of
the CPU cycle the address lines settle-out first and are,
therefore, decoded to allow maximum access speed (see
Address Decode) With the generation of MREQ, U39-11
generates PMREQ and enables U42 and gates this with the
type of cycle to develop GRAS* (U30-6), RASO* (U30-3),
and RAS1* (U30-11) GRAS* is then "OR"ed with AINPRG
as mentioned above The timing from this point is very
straight forward With RASO* and RAS1* generated next
MUX (U80-12) is built to switch the addresses to memory
then GCAS is generated and clocks flip-flop U31 with
MCYEN on the J term This is done to make sure this is a
true memory cycle Then if this is an M1 cycle VLATCH*
clocks at U31 and cuts off PMREQ* at U39 to end the cycle
For timing diagrams of the memory interface see Figures 210 to 2-12

Since the CRTC and the CPU are operating independently
and at different clock rates, when the CPU wants to access
the Video RAM the two must synchronize with each other
This is accomplished when a video access is decoded
WAIT* it is pulled low, when it is determined whether the access is a read or write and the correct cycle of the CRTC
clock is present, the actual access can begin, hence
AINPRG* is generated and WAIT* is released
From this point the actual sequence depends on whether a
read or a write is done On a read the address is enabled to
the RAM, the delay through U80 to VLATCH* when data is
latched in the 74LS373 where the CPU can pick-up the data
at the completion of this cycle On a write the sequence is
more complex The address is enabled to the RAM, the output is disabled (VRAMDIS* at U7-12), write is delayed with
respect to the address (DLYWR* at U60-6) and the buffer on
the data lines is enabled (VBUFEN* at U60-8), then after a
delay the write is cutoff to end the cycle for the RAM
(ENDVW* at U80-10) For the timing diagram of the Video
RAM CPU access see Figure 2-8

MAPI*

MAP II

This section is divided into two parts, the memory addressing and the I/O addressing This separation is a reflection of
the separate mapping of memory and I/O of the Z80A itself
For reference of both sections, see Figure 2-13

Memory Address
The memory map for the Model 4 is shown in Table 2-1 and
is best described as an option overlay in the sense that at
each step of additional memory, the new options overlap the
previous and the new options are added on Moreover, the
added options have no effect on previous levels and are invisible at those levels.

Address in hex
MAP III

0000-37FF
0000-37E7
37E8-37E9
37EA-37FF
3800-3BFF
3COO-3FFF"
4000-7FFF
4000-FFFF

2.1.5. Address Decode

3800-3BFF
3COO-3FFF**

MAP IV

0000-F3FF

0000-FFFF

Function
of block
RAM (64K)
ROM

Printer Status
ROM
Keyboard
Video RAM
RAM (16K)
RAM (64K)

F400-F7FF
F800-FFFF

4000-FFFF

Table 2-1
* Only map available on 16K machine
Page bit is used to select 1K of 2K Video RAM

The decoding of the addresses for the memory map described above is done for the most part by U5 The only decode not done by U5 is the line printer memory status port
at 37E8 and 37E9 hex These needed additional address
lines hence the decode LPADD as an input to U5

Hardware 28

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(Page 2 of Schematic)

Hardware 30

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Hardware 34

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Table 2-2. RAM Memory

Hardware 35

I/O port Address
The Port Map decoding is accomplished by three 74LS138s
(U43,U44, and U59) These ICs decode the low order address lines (AO - A7) from the CPU and decode the port
being selected The IN* signal and OUT* signal are used in
the decode for U59 and U43, but U44 is a pure address decode and, therefore, needs to be gated with IN*, OUT*, or
IOREQ* later For a complete I/O map see Table 2-3

The Model 4 also has an option for either 64 character or 80
character wide screen The 64 character screen is compatible with the Model III and displays 16 lines The 80 character screen displays 24 lines In addition each of these has a
double width mode These options are controlled by two bits,
MODSEL and 8064 which provide the screens as shown in
the following table

2.1.6. ROM
The A ROM is enabled by the decode as appropriate by the
address logic described above, and is addressed in a simple
straight forward fashion The enable for the B/C ROM is also
similarly accomplished, however, the address has a jumper
option available This option is designed to allow for testing
of the board logic in the factory When jumper is moved from
JP8 to JP7, the ROM is in the test mode, with the options
appearing on the screen

8064

MODSEL

Video Screen Size

0

0

64 x 16
32 x 16
80x24
40x24

0

1
1

1
0
1
Table 2-4

2.1.7 DRAM
The DRAM timing was described earlier in the timing section, the actual DRAM is contained in two banks of eight
each U65 to U74 and U85 to U92 They are arranged in order of data bits DO through D7, U65 and U85 being DO,
through U74 and U92 being D7 Note in Figure 2-15 that the
two banks are different with jumper options in the lower
bank, these options are for the possible use of 16k three
voltage parts When jumpered as shown in Figure 2-14 the
bank is identical to the second bank and is for using 64k
DRAMs With both banks filled there is 128k available to the
user

2.1.8 Video Circuit
Video Modes
The Model 4 has many video options available through
hardware and software Software has control of inverse
video on a character by character basis by turning on INVIDE Note that this implies the available number of characters is now 128 since the most significant bit of the character
code in memory is now used to indicate inverse character
Similarly, an alternate character set can be enabled by turning on ENALTSET This enables a new 64 characters in
place of the last 64 characters, that is, the Kana set in place
of the game set An option not available to software is an
enhanced character, which moves characters down one row
in their character block to make an inverse character appear
within the inverse block and not on the edge of the block
This is done by moving jumper JP11 to JP12 As an example of a combination of hardware and software options available in the video is the overlay, which not only requires the
Graphics Board to be installed, but also software to enable
the graphics data and the video data with text at the same
time

With this information of the options available to the user we
can now view the actual operation of the circuit with the final
objectives in mind and see how they are achieved For the
rest of this section all references will be made to Figure 216 The first task to be accomplished would be the screen
refresh and this is done by the CRTC or 68045 (U11) which
will generate the addresses continuously on its address
lines Then to allow the CPU access to the same memory
the address lines are multiplexed at U12, U14, and U15 on
opposite phases of the CRT clock The CPUs access timing
is then handed by the timing circuit described earlier
The data bus of the RAM (U16) is a two way bus with the
RAM as a source or destination on all accesses, the video
gate array (U17) is the destination on the screen refresh half
of the cycle, the 74LS373 (U36) is the destination on a read
of the RAM by the CPU, and the 74LS244 (U35) is the
source on writes to the RAM

c

The video gate array then gates the RAM data INVIDE, and
ENALTSET to determine the ROM addressing for these two
options and CHRADD to the 74LS283 (U13) which takes the
row address from the 68045 and adds a zero to the row address or a minus one to form the character enhanced mode
The data out of the ROM is then sent back to the gate array
where it is then changed to a serial stream of data which is
synchronized with the data that would come from the graphics board, GRAFVID The signal CL166 will inhibit the data
out of the serial register and the signal ENGRAF enables
the graphics data, hence, if both are enabled the effect is an
overlay The output data is sent to U20 pin 9 where it is
gated with one of two phases of the dot clock, then after
being filtered to lower the R F I it is output to the sweep
board

Q
Hardware 36

Model 4 Port Bit Map

07
F C - FF

Cass

(READ)

data
500 bd

D6

D5

04

D2

03

D1

DO
Cassette

( M I R R O R of PORT

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1500 bd

(Note, also resets cassette data latch)

FC-FF
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cass.

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data out

F 8 - FB
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Prntr
BUSY

Prntr
Paper

Prntr
Select

Prntr

x

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Fault

X

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(WRITE)

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D7

Prntr
D6

Prntr
D5

Prntr
D4

Prntr
D2

Prntr
D1

Prntr

DO

(Any Read causes reset of Real Time Clock Interrupt)

EC-EF
EC-EF
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CPU
Fast

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Receive
Error

E O - E3
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Enable
Rec Err

Enable
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Enable
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Select

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Receive
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Xmit
Empty

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RTC
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CFall
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Enable
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Enable
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Enable
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Enable
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x
x

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Bit 0

Invert
Video

80/64

90-93
(WRITE)
84-87
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Prntr
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Page

Fix Upr
Memory

Memory
Bit 1

Table 2-3. I/O Port Map

Hardware 37

Sound
Bit
Select
Bit 1

Select
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Figure 2-14. ROM Circuit
(Page 1 of Schematic)

Hardware 38

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Hardware 40

2.1.9 Keyboard

Pin Number

The interface to the keyboard is a matrix composed of address lines in one direction and data lines in the other. The
address lines have two open collector buffers (U26 and U40)
on the output to the keyboard.
The input is pulled-up with an 820 ohm resistor and is then
fed into two CMOS Inputs (U55 and U56) which act as a
driver on data lines.

2.1.10 Real Time Clock
The Real Time Clock circuit in the Model 4 provides a 30 Hz
(in the 2 MHz CPU Mode) or 60 Hz (in the 4 MHz CPU
Mode) interrupt to the CPU. By counting the number of interrupts that have occured, the CPU can keep track of the
time. The 60 Hz vertical sync signal from the video circuitry
is divided by two (2 MHz Mode) by U10 and the 30 Hz at
pin 9 of U46 is used to generate the interrupts. In the 4 MHz
mode, the signal FAST places a logic low at pin 4 of U10,
causing the signal VSYNC to pass through U46 at its normal
rate and trigger interrupts at the 60 Hz rate. Note that any
time interrupts are disabled, the accuracy of the clock
suffers.

2.1.11 Line Printer Port
The printer status lines are read by the CPU by enabling
buffer U108. This buffer will be enabled for any input from
port F8 or F9, or any memory read from location 37E8 or
37E9 when in the Model III mode. For a listing of bit status,
refer to the bit map.
After the printer driver software determines that the printer is
ready to receive a character (by reading the status), the
character to be printed is output to port F8. This latches the
character into U107, and simultaneously fires the one-shot
U63 to provide the appropriate strobe to the printer.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
26
29
30
31
32
33
34

Signature

DO
D1
D2
D3
D4
D5
D6
D7
GEN*
DCLK
AO
At
A2
J
GRAPVID
ENGRAF
DISBEN
VSYNC
HSYNC
RESET*
WAIT*
H
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GND

+5
N/C

CL166
GND

+5
GND

+5
GND
+5

2.1.12 Graphics Port
Table 2-5
The graphics port on the Model 4 is provided to attach the
optional high resolution graphics board and provides the
necessary signals to interface not only to the CPU (such as
data lines, address lines, address decodes, and control
lines), but also the signals needed to synchronize the output
of the Video Circuit and the Graphics board and control to
provide features such as overlay.

\

Hardware 41

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Hardware 42

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Figure 2-20. Sound
(Page 4 of Schematic)

Hardware 43

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2.1.13 Sound Port
The sound circuit is compatible with the optional sound
board on the older version of the Model 4 and works in a
similar fashion Sound is generated by setting and clearing
data bit zero on successive OUTs to port 90H The state of
DO is latched in U18 which is amplified by Q2 to drive the
speaker (SP1)

2.1.14 I/O Bus Port
The Model 4 Gate Array Bus is designed to allow easy and
convenient interfacing of I/O devices to the Model 4 The I/O
Bus supports all the signals necessary to implement a device compatible with the Z-80s I/O structure That is
Addresses
AO to A7 allow selection of up to 256 input and 256 output
devices if external I/O is enabled
Ports 80H to OFFH are reserved for System use
Data
DBO to DB7 allow transfer of 8-bit data onto the processor data bus if external I/O is enabled
Control Lines
a IN* — Z-80 signal specifying that an input is in
progress Gated with IORQ
b OUT* — Z-80 signal specifying that an output is in
progress Gated with IORQ
c RESET* — system reset signal
d IOBUSINT* — input to the CPU signaling an interrupt from an I/O Bus device if I/O Bus interrupts are
enabled
e IOBUSWAIT* — input to the CPU wait line allowing
I/O Bus device to force wait states on the Z-80 if
external I/O is enabled
f EXTIOSEL* — input to CPU which switches the I/O
Bus data bus transceiver and allows an INPUT instruction to read I/O Bus data
g M1* — and IORQ* — standard Z-80 signals
The address line, data line, and control lines a to c and e to
g are enabled only when the ENEXIO bit is set to a one

To enable I/O interrupts, the ENIOBUSINT bit in the CPU IOPORT EO (output port) must be a one However even if it is
disabled from generating interrupts the status of the IOBUSINT* line can still read on the appropriate bit of CPU IOPORT EO (input port)
See Model 4 Port Bit assignment for OFF OEC and OEO
The Model 4 CPU board is fully protected from foreign I/O
devices in that all the I/O bus signals are buffered and can
be disabled under software control To attach and use an I/O
device on the I/O Bus, certain requirements (both hardware
and software) must be met
For input port device use, you must enable external I/O devices by writing to port OECH with bit 4 on in the user software This will enable the data bus, address lines, and
control signals to the I/O Bus edge connector When the input device is selected, the hardware will acknowledge by asserting EXTIOSEL* low This switches the data bus
transceiver and allows the CPU to read the contents of the I/
O Bus data lines See Figure 2-21 for the timing EXTIOSEL* can be generated by NANDmg IN and the I/O port
address
Output port device use is the same as the input port device
in use, in that the external I/O devices must be enabled by
writing to port OECH with bit 4 on in the user software — in
the same fashion
For either input or output devices, the IOBUSWAIT* control
line can be used in the normal way for synchronizing slow
devices to the CPU Note that since dynamic memories are
used in the Model 4, the wait line should be used with caution Holding the CPU in a wait state for 2 msec or more
may cause loss of memory contents since refresh is inhibited during this time It is recommended that the IOBUSWAIT* line be held active no more than 500 msec with a
25% duty cycle
The Model 4 will support Z-80 mode 1 interrupts A RAM
jump table is supported by the LEVEL II BASIC ROMs and
the user must supply the address of his interrupt service
routine by writing this address to locations 403E and 403F
When an interrupt occurs, the program will be vectored to
the user supplied address if I/O Bus interrupts have been
enabled To enable I/O Bus interrupts, the user must set bit
3 of Port OEOH
The actual implementation is shown in Figure 2-22 The data
is buffered in both directions using a 74LS245 (U101) The
addresses are buffered with a 74LS244 (U102) and the
control lines out are buffered by a 74LS367 Note that RESET* is always enabled out, this is to power-up reset any
device or clear any device before enabling the bus structure
This prevents any user from tymg-up the bus when enabling
the port in an unknown state

Hardware 44

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Figure 2-21. I/O BUS TIMING DIAGRAM

Hardware 45

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Hardware 46

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Data Bit
DO
D1
D2
D3
D4
D5

D6
D7

Function
Selects Drive 0 when set*
Selects Drive 1 when set*
Selects Drive 2 when set*
Selects Drive 3 when set*
Selects Side 0 when reset
Selects Side 1 when set
Write precompensation
enabled when set disabled when reset
Generates WAIT if set
Selects MFM mode if set
Selects FM mode if reset

Clock Generation Logic
A 16 MHz crystal oscillator and Gate Array 4 4 (U76) are
used to generate the clock signals required by the FDC
board The 16 MHz oscillator is implemented internal to U76
and a quartz crystal (Y2) The output of the oscillator is divided by 2 to generate on 8 MHz clock This is used by the
FDC 1773 (U75) for all internal timing and data separation
U76 further divides the 16 MHz clock to drive the watchdog
timer circuit

Disk Bus Output Drivers
High current open collector drivers U96, 94 and 93 are used
to buffer the output signals from the FDC circuit to the disk
drives

*Only one of these bits should be set per output
Hex D flip-flop U79 (74L174) latches the drive select bits,
side select and FM* MFM bits on the rising edge of the control signal DRVSEL* Gate Array 4 4(U76) is used to latch
the Wait Enable and Write precompensation enable bits on
the rising edge of DRVSEL* The rising edge of DRVSEL*
also triggers a one-shot (Internal to U76) which produces a
Motor On to the disk drives The duration of the Motor On
signal is approximately three seconds The spindle motors
are not designed for continuous operation Therefore, the inactive state of the Motor On signal is used to clear the Drive
Select Latch, which de-selects any drives which were previously selected The Motor On one-shot is retriggerable by
simply executing another OUT instruction to the Drive Select
Latch

Write Precompensation and
Write Data Pulse Shaping Logic
All write precompensation is generated internal to the FDC
chip 1773 (U75) Write Precompensation occurs when WG
goes high and write precompensation is enabled from the
software ENP is multiplexed with RDY and is controlled by
WG at pin 20 of U75 Write data is output on pin 22 of U75
and is shaped by a one-shot (1/2 of U98) which stretches
the data pulses to approximately 500 nsec

Clock and Read Data Recovery Logic
The Clock and Read Data Recovery Logic is done internal
to the 1773(U75)

Wait State Generation and WAITIMOUT Logic
Floppy Disk Controller Chip
As previously mentioned, a wait state to the CPU can be initiated by an OUT to the Drive Select Latch with D6 set Pin
10 of U76 will go high after this operation This signal is inverted by 1/4 of U96 and is routed to the CPU where it
forces the Z80A into a wait state The Z80A will remain in
the wait state as long as WAIT* is low Once initiated, the
WAIT* will remain low until one of five conditions is satisfied
If INTRO, DRQ, or RESET inputs become active (logic
high), it causes WAIT* to go high which allows the Z80 to
exit the wait state An internal timer on U70 serves as a
watchdog timer to insure that a wait condition will not persist
long enough to destroy dynamic RAM contents This internal
watchdog timer logic will limit the duration of a wait to 1024
p,sec, even if the FDC chip should fail to generate a DRQ or
an INTRO

The 1773 is an MOS LSI device which performs the
functions of a floppy disk formatter/controller in a single chip implementation. The following port addresses
are assigned to the internal registers of the 1773 FDC
chip:

If an OUT to Drive Select Latch is initiated with D6 reset
(logic low), a WAIT is still generated The internal timer on
U70 will count to 2 which will clear the WAIT state This allows the WAIT to occur only during the OUT instruction to
prevent violating any Dynamic RAM parameters
NOTE This automatic WAIT will cause a 5 to 1 ^sec wait
each time an out to Drive Select Latch is performed

Hardware 47

Port No.
FOH
F1H
F2H
F3H

Function
Command/Status
Register
Track Register
Sector Register
Data Register

2.1.15 Cassette Circuit

Control and Data Buffering

The cassette write circuitry latches the two LSBs (DO and
D1) for any output to port FF (hex) The outputs of these
latches (U51) are then resistor summed to provide three discrete voltage levels (500 Baud only) The firmware toggles
the bits to provide an output signal of the desired frequency
at the summing node

The Floppy Controller is an I/O port-mapped device which
utilizes ports E4H, FOH, F1H, F2H, F3H, and F4H The decoding logic is implemented in the Address Decoding (for
more information see Port Map) U78 is a bi-directional, 8-bit
transceiver used to buffer data to and from the FDC and
RS-232 circuits The direction of data transfer is controlled
by the combination of control signals DISKIN*, RDINTSTATUS*, RDNINSTATUS*, and RS232IN* If any signal is active
(logic low), U78 is enabled to drive data onto the CPU data
bus If all signals are inactive (logic high), U78 is enabled to
receive data from the CPU board data bus A second buffer
U77 is used to buffer the FDC chip data to the FDC/RS232
Data Bus, (BDO-BD7) U77 is enabled by Chip Select and its
direction controlled by DISKIN* Again, if DISKIN* is active
(logic low), data is enabled to drive from the FDC chip to the
Mam Data Busses If DISKIN* is inactive (logic high), data is
enabled to be transferred to the FDC chip

There are two types of cassette Read circuits — 500 baud
and 1500 baud The 500 baud circuit is compatible with both
Model I and III The input signal is amplified and filtered by
Op amps (U23 and U54) Part of U22 then forms a Zero
Crossing Detector, the output of which sets the latch U37 A
read of Port FF enables buffer U52 which allows the CPU to
determine whether the latch has been set, and simultaneously resets the latch The firmware determines by the timing between settings of the latch whether a logic '"one" or
'"zero" was read in from the tape
The 1500 baud cassette read circuit is compatible with the
Model III cassette system The incoming signal is compared
to a threshold by part of U22 U22's output will then be
either high or low and clock about one-half of U37, depending on whether it is a rising edge or a falling edge If interrupts are enabled, the setting of either latch will generate an
interrupt As in the 500 baud circuit, the firmware decodes
the interrupts into the appropriate data.
For any cassette read or write operation, the cassette relay
must be closed in order to start the motor of the cassette
deck A write to port EC hex with bit one set will latch U53,
which turns on transistor Q3 and energizes the relay K1 A
subsequent write to this port with bit one clear will clear the
latch and de-energize the relay

2.1.16 FDC Circuit
The TRS-80 Model 4 Floppy Disk Interface provides a standard 5-1/4" floppy disk controller The Floppy Disk Interface
supports single and double density encoding schemes Write
precompensation can be software enabled or disabled beginning at any track, although the system software enables
write precompensation for all tracks greater than twenty-one
The amount of write precompensation is 125 nsec and is not
adjustable One to four drives may be controlled by the interface All data transfers are accomplished by CPU data requests In double density operation, data transfers are
synchronized to the CPU by forcing a wait to the CPU and
clearing the wait by a data request from the FDC chip The
end of the data transfer is indicated by generation of a nonmaskable interrupt from the interrupt request output of the
FDC chip A hardware watchdog timer insures that any error
condition will not hang the wait line to the CPU for a period
long enough to destroy RAM contents

^^^^J^

Non-maskable Interrupt Logic
Gate Array 4 4 (U75) is used to latch data bits D6 and D7
on the rising edge of the control signal WRNMIMASKREG*
This enables the conditions which will generate a non-maskable interrupt to the CPU The NMI interrupt conditions
which are programmed by doing an OUT instruction to port
E4H with the appropriate bits set If data bit 7 is set, an FDC
interrupt is enabled to generate an NMI interrupt If data bit
7 is reset, interrupt requests from the FDC are disabled If
data bit 6 is set, a Motor Time Out is enabled to generate an
NMI interrupt If data bit 6 is reset, interrupts on Motor Time
Out are disabled An IN instruction from port E4H enables
the CPU to determine the course of the non-maskable interrupt Data bit 7 indicates the status of FDC interrupt request
(INTRQ) (0 = true, 1 -false) Data bit 6 indicates the status
of Motor Time Out (0 = true, 1 = false) Data bit 5 indicates
the status of the Reset signal (0 = true, 1 = false) The control signal RDNMISTATUS* gates this status onto the CPU
data bus when active (logic low)

Drive Select Latch and Motor ON Logic
Selecting a drive prior to disk I/O operation is accomplished
by doing an OUT instruction to port F4H with the proper bit
set The following table describes the bit allocation of the
Drive Select Latch

Hardware 48

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2.1.17 RS-232C Circuit

RS-232C Technical Description
The RS-232C circuit for the Model 4 computer supports
asynchronous serial transmissions and conforms to the EIA
RS-232C standards at the input-output interface connector
(J3) The heart of the circuit is the TR1865 Asynchronous
Receiver/Transmitter U84 It performs the job of converting
the parallel byte data from the CPU to a serial data stream
including start, stop, and parity bits For a more detailed description of how this LSI circuit performs these functions, refer to the TR1865 data sheets and application notes The
transmit and receive clock rates that the TR1865 needs are
supplied by the Baud Rate Generator U104 This circuit
takes the 5 0688 MHz supplied by the system timing circuit
and the programmed information received from the CPU
over the data bus and divides the basic clock rate to provide
two clocks The rates available from the BRG go from 50
Baud to 19200 Baud See the BRG table for the complete
list.

Interrupts are supported in the RS-232C Circuit by the Interrupt mask register and the Status register internal to Gate
Array 4 5 (U82) The CPU looks here to see which kind of
interrupt has occurred Interrupts can be generated on receiver data register full, transmitter register empty, and any
one of the errors — parity, framing, or data overrun This allows a minimum of CPU overhead in transferring data to or
from the UART The interrupt mask register is port EO (write)
and the interrupt status register is port EO (read) Refer to
the IO Port description for a full breakdown of all interrupts
and their bit positions
All Model I, ill, and 4 software written for the RS-232C interface is compatible with the Model 4 Gate Array RS-232C circuit, provided the software does not use the sense switches
to configure the interface The programmer can get around
this problem by directly programming the BRG and UART for
the desired configuration or by using the SETCOM command of the disk operating system to configure the interface
The TRS-80 RS-232C Interface hardware manual has a
good discussion of the RS-232C standard and specific programming examples (Catalog Number 26-1145)

BRG Programming Table

Nibble
Loaded

OH
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH

Transmit/
Receive
Baud
Rate

Suported
16X

Clock
0.8 kHz
1 .2 kHz
1 .76 kHz
2 1523kHz
2.4 kHz
4.8 kHz
9.6 kHz
192kHz
28.8 kHz
32.081 kHz
38.4 kHz
57.6 kHz
76.8 kHz
115.2kHz
153.6kHz
307.2 kHz

50
75
110

134.5
150
300
600

1200
1800
2000
2400
3600
4800
7200
9600
19200

SETCOM

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Pinout Listing
The RS-232C circuit is port mapped and the ports used are
E8 to EB Following is a description of each port on both input and output.
Port
E8

Input
Modem status

EA

UART status

E9

Not Used

EB

Receiver Holding
register

Output
Master Reset, enables
UART control register
load
UART control register
load and modem control
Baud rate register load
enable bit
Transmitter Holding
register

The following list is a pmout description of the DB-25 connector (P1)
Pin No.
Signal
1
PGND (Protective Ground)
TD (Transmit Data)
2
RD (Receive Data)
3
RTS (Request to Send)
4
CTS (Clear To Send)
5
DSR (Data Set Ready)
6
SGND (Signal Ground)
7
CD (Carrier Detect)
8
SRTS (Spare Request to Send)
19
20
DTR (Data Terminal Ready)
22
Rl (Ring Indicate)

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DCLK, the reference clock selected, is output from U127.
DCLK is fed back into U127 for internal timing reference and
is also fed to the clock input of U128 (74LS161). U128 is
configured to preload with a count of 9 each time it reaches
a count of 0. This generates a signal output of TC (128 pin
15) that occurs at the start of every character time of video
output. TC is used to generate LOADS* (Load Shift Register). QA and QC of U128 are used to generate SHIFT*,
XADR7*, CRTCLK and LOAD* for proper timing for the four
video modes. QA, QB, and QC which are referred to as H, I,
and J are fed to the Graphics Port J7 for reference timings
of Hires graphics video. Refer to Video Timing, Figs. 3-3 and
3-4 for timing reference.

The Model 4P Boot ROM contains all the code necessary to
initialize hardware detect options selected from the keyboard
read a sector from a hard disk or floppy and load a copy of the
Model III ROM Image (as mentioned) into the lower 14K of
RAM
The firmware is divided into the following routines
*
*
*
*
*
*
*
*
*

3.1.5 Address Decode
The Address Decode section will be divided into two subsections: Memory Map decoding and Port Map decoding.

Hardware Initialization
Keyboard Scanner
Control
Floppy and Hard Disk Driver
Disk Directory Searcher
File Loader
Error Handler and Displayer
RS-232 Boot
Diagnostic Package

3.1.5.1 Memory Map Decoding

Theory of Operation

Memory Map Decoding is accomplished by a 16L8 PAL (U109)
Four memory map modes are available which are compatible
with the Model III and Model 4 microcomputers A second 16L8
PAL (U110) is used in conjunction with U109 for the memory
map control which also controls page mapping of the 32K RAM
pages. Refer to Memory Maps below.

This section describes the operation of various routines in the
ROM Normally, the ROM is not addressable by normal use
However, there are several routines that are available through
fixed calling locations and these may be used by operating systems that are booting

3.1.5.2 Port Map Decoding
Port Map Decoding is accomplished by three 74LS138s (U87,
U88, and U107). These ICs decode the low order address (AOA7) from the CPU and decode the port being selected The IN*
signal from U108 enables U87 which allows the CPU to read
from a selected port and the OUT* signal, also from U108, enables U88 which allows the CPU to write to the selected port
U107 only decodes the address and the IN* and OUT* signals
are ANDed with the generated signals.

a

On a power-up or RESET condition, the Z80 s program counter
is set to address 0 and the boot ROM is switched-m The memory map of the system is set to Mode 0 (See Memory Map for
details ) This will cause the Z80 to fetch instructions from the
boot ROM
The Initialization section of the Boot ROM now performs these
functions:

3.1.6 ROM
The Model 4P contains only a 4K x 8 Boot ROM (U70). This
ROM is used only to boot up a Disk Operating System into
the RAM memory. If Model III operation or DOS is required,
then the RAM from location 0000-37FFH must be loaded with
an image of the Model III or 4 ROM code and then executed.
A file called MODEL A/Ill is supplied with the Model 4P which
contains the ROM image for proper Model III operation. On
power-up, the Boot ROM is selected and mapped into location 0000-OFFFH. After the Boot Sector or the ROM Image is
loaded, the Boot ROM must be mapped out by OUTing to
port 9CH with DO set or by selecting Memory Map modes 2
or 3. In Mode 1 the RAM is write enabled for the full 14K.
This allows the RAM area mapped where Boot ROM is located to be written to while executing out of the Boot ROM.
Refer to Memory Maps.

1.
2
3
4
5
6
7
8
9
10.
11.

Disables maskable and non-maskable interrupts
Interrupt mode 1 is selected
Programs the CRT Controller
Initializes the boot ROM control areas in RAM
Sets up a stack pointer
Issues a Force Interrupt to the Floppy Disk Controller
to abort any current activity
Sets the system clock to 4mhz
Sets the screen to 64 x 16
Disables reverse video and the alternate character
sets
Tests for key being pressed*
Clears all 2K of video memory

o

" This is a special test If the •
is being pressed then
control is transferred to the diagnostic package in the
ROM All other keys are scanned via the Keyboard
Scanner

«
Hardware 60

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<.2>
< 3 >
- Left-Shift - Right-Shift^
-.Ctrl >
^Caps -

Selection Group
A
B
C
D
E
F
G

Special Keys


Misc Keys
Enter
Break

The Selection group keys are used in determining which file will
be read from disk when the ROM image is loaded For details
of this operation see the Disk Directory Searcher If more than
one of the Selection group keys are pressed the last one detected will be the one that is used
The Miscellaneous keys are
Break

When any key in the Function Group is pressed it is recorded
in RAM and will be used by the Control routine in directing the
action of the boot If more than one of these keys are pressed
during the keyboard scan the last one detected will be the one
that is used The Function group keys are currently defined as

-- F1 ^ or - 1 >
<^F2^or<.2^
<.F3sor- 3^
- Left-Shift -~ Right-Shifts
^Ctrl >
<,Caps ->

Will cause hard disk boot
Will cause floppy disk boot
Will force Model III mode
Reserved for future use
Boot from RS-232 port
Reserved for future use
Reserved for future use

Enter


Set Transfer
Address to
4300H
Note: 2

Set Transfer
Address at end
of ROM Image
(Normally 3015H)
Note: 2
Stop

^

•"N

Hardware 65

Switch boot ROM
out of Memory

Jump to
Transfer

Address

Yes

Display
"ROM Image
is loaded"
message

Initialize
RS-232 Port
Note: 6

Wait for
< E N T E R > or
 to
be pressed

Wait for
Carrier Detect

C

^
Determine
Correct
Baud Rate

\U
Write-protect
memory (Mode 0)

Transmit Baud
Rate Detect
Message

V
Set CPU speed
to 2MHz

9
Hardware 66

Packages that do not reference the Model III ROM in the
boot sector can still cause the Model III ROM image to be
loaded by coding a CDxxOO somewhere in the boot sector
It does not have to be executable At the same time Model
4 packages must take care that there is no sequence of
bytes in the Doot sector that could be mis interpreted to be
a reference to the Boot ROM An example of this would be
sequence 06CDOEOO which is a LD B OCDH and a LD
C 0 If the boot sector cannot be changed then the user
must press the F3 key each time the system is started
to inform the ROM that the d sk contains a Model III pack
age which needs the Mode' III ROM image

Vvai^ for
Sync Byte
FFH)

(2) If you are loading a Model 4 operating system then the
boot ROM will always transfer control to the first byte of the
boot sector which is at 4300H If you are loading a Model
III operating system or about to use Model III ROM BASIC
then the transfer address is 3015H This is the address of
a jump vectonn the C ROM of the Model III ROM image
and this will cause the system to behave exactly like a
Model III If the ROM image file that is loaded has a differ
ent transfer address then that address will be used when
loading is complete If the image is already present the
Boot ROM will use 3015H

Load program
from RS-232

Display and
transmit error

(3) Two different tests are done to insure that the Model III
ROM image is present The first test is to check every third
location starting at 3000H for a C3H This is done for 10 lo
cations If any of these locations does not contain a C3H
then the ROM image is considered to be not present
The next test is to check two bytes at location OOOBH If
these addresses contain E9E1H then the ROM image is
considered to be present

Transfer
control
to address
received

(4) See Disk Director Searcher for more information

^

Notes
(5) See File Loader for more information
(1) If the boot sector was not 256 bytes in length then it is as
sumed to be a Model III package and the ROM image will
be needed If the sector is 256 bytes in length then the
sector is scanned for the sequence CDxxOOH The CD is
the first byte of a Z80 unconditional subroutine call The
next byte can have any value The third byte is tested
against a zero What this check does is test for any refer
ences to the first 256 bytes of memory All Radio Shack
Model III operating systems and many other packages all
reference the ROM at some point during the boot sector
Most boot sectors will display a message if the system can
not be loaded To save space these routines use the
Model III ROM calls to display the message Several ROM
calls have their entry points in the first 256 bytes of mem
ory and these references are detected by the boot ROM

(6) The RS 232 loader is described under RS 232 Boot
Disk Directory Searcher
When the Model III ROM image is to be loaded it is always read
from the floppy in drive 0
Before the operation begins some checks are made First the
boot sector is read m from the floppy and the first byte is
checked to make sure it is either a OOH or a FEH If the byte
contains some other value no attempt will be made to read the
ROM image from that disk The location of the directory cylinder
is then taken from the boot sector and the type of disk is deter
mined This is done by examining the Data Address Mark that

-N

Hardware 67

was picked up by the Floppy Disk Controller (FDC) during the
read of the sector If the DAM equals 1 the disk is a TRSDOS
1 x style disk If the DAM equals 0 then the disk is a LDOS 5 1
TRSDOS 6 style disk This is important since TRSDOS 1 x
disks number sectors starting with 1 and LDOS style disks
number sectors starting with 0
Once the disk type has been determined an extra test is made
if the disk is a LDOS style disk This test reads the Granule Allocation Table (GAT) to determine if the disk is single sided or
double sided
The directory is then read one record at a time and a compare
is made against the pattern 'MODEL%
for the filename and
'III1 for the extension The '% means that any character will
match this position If the user pressed one of the selection
keys (A-G) during the keyboard scan, then that character is
substituted in place of the '% character For example, if you
pressed 'D', then the search would be for the file MODELD ,
with the extension 'III' The searching algorithm searches until
it finds the entry or it reaches the end of the directory
Once the entry has been found, the extent information for that
file is copied into a control block for later use
File Loader
The file loader is actually two modules — the actual loader and
a set of routines to fetch bytes from the file on disk The loader
is invoked via a RST 28H The byte fetcher is called by the
loader using RST 20H Since restart vectors can be re-directed,
the same loader is used by the RS-232 boot The difference is
that the RST 20H is redirected to point to the RS-232 data receiving routine The loader reads standard loader records and
acts upon two types
01

Data Load
1 byte with length of block, including address
1 word with address to load the data
n bytes of data, where n + 2 equals the length specified

02

Transfer Address
1 byte with the value of 02
1 word with the address to start execution at

Floppy and Hard Disk Driver
The disk drivers are entered via RST 8H and will read a sector
anywhere on a floppy disk and anywhere on head 1 (top-head)
in a hard disk drive Either 256 or 512 byte sectors are readable
by these routines and they make the determination of the sector
size The hard disk driver is compatible with both the WD1000
and the WD1010 controllers The floppy disk driver is written for
the WD1793 controller
Serial Loader
Invoking the serial loader is similar to forcing a boot from hard
disk or floppy In this case the right shift key must be pressed at
some time during the first three seconds after reset The program does not care if the key is pressed forever making it convenient to connect pins 8 and 10 of the keyboard connector with
a shorting plug for bench testing of boards This assumes that
the object program being loaded does not care about the key
closure
Upon entry, the program first asserts DTR (J4 pin 20) and RTS
(J4 pin 4) true Next, Not Ready is printed on the topmost line
of the video display Modem status line CD (J4 pin 8) is then
sampled The program loops until it finds CD asserted true At
that time the message "Ready" is displayed Then the program
sets about determining the baud rate from the host computer
To determine the baud rate, the program compares data received by the DART to a test byte equal to 55 hex The receiver
is first set to 19200 baud If ten bytes are received which are not
equal to the test byte the baud rate is reduced This sequence
is repeated until a valid test byte is received If ten failures occur
at 50 baud, the entire process begins again at 19200 baud If a
valid test byte is received, the program waits for ten more to arrive before concluding that it has determined the correct baud
rate If at this time an improper byte is received or a receiver error (overrun, framing, or parity) is intercepted, the task begins
again at 19200 baud

o

In order to get to this point the host or the modem must assert
CD true The host must transmit a sequence of test bytes equal
to 55 hex with 8 data bits odd parity and 1 or 2 stop bits The
test bytes should be separated by approximately 0 1 second to
avoid overrun errors

Any other loader code is treated as a comment block and is ignored Once an 02 record has been found, the loader stops
reading, even if there is additional data, so be sure to place the
02 record at the end of the file

When the program has determined the baud rate, the message
"Found Baud Rate x"
is displayed on the screen where ' x" is a letter from A to P
meaning
A
B
C
D

- 50 baud
= 75
= 110
= 134 5

E = 150
F - 300
G - 600
H - 1200

1-1800
J = 2000
K - 2400
L - 3600

M - 4800
N - 7200
O - 9600
P - 19200

«
Hardware 68

The same message less the character signifying the baud rate
is transmitted to the host, with the same baud rate and protocol
This message is the signal to the host to stop transmitting test
bytes
After the program has transmitted the baud rate message it
reads from the UART data register in order to clear any overrun
error that may have occurred due to the test bytes coming in
during the transmission of the message This is because the receiver must be made ready to receive a sync byte signalling the
beginning of the command file For this reason it is important
that the host wait until the entire baud rate message (16 characters) is received before transmitting the sync byte which is
equal to FF hex
When the loader receives the sync byte the message
"Loading1
is displayed on the screen Again, the same message is transmitted to the host, and, again the host must wait for the entire
transmission before starting into the command file
If the receiver should intercept a receive error while waiting for
the sync byte, the entire operation up to this point is aborted
The video display is cleared and the message
"Error, x'
is displayed near the bottom of the screen, where x is a letter
from B to H, meaning
B
C
D
E
F
G
H

=
=
=
=
=
=
=

parity error
framing error
parity & framing errors
overrun error
parity & overrun errors
framing & overrun errors
parity & framing & overrun errors

(Since the file represents Z80 machine code and all 256
combinations are meaningful it would be disastrous to
transmit nulls or other ASCII control codes as fillers acknowledgement or start-stop bytes The only control
codes needed are the standard command file control
bytes )
Data can be transmitted to the loader at 19200 baud with no delays inserted Two stop bits are recommended at high baud
rates
See the File Loader description for more information on file
loading
If a receive error should occur during file loading the abort procedure described above will take place, so when attempting remote control, it is wise to monitor the host receiver during
transmission of the file When the host is near the object board
as is the case in the factory application or when more than one
board is being loaded, it may be advantageous or even necessary to ignore the transmitted responses of the object
board(s) and to manually pace the test byte, sync byte and
command file phases of the transmission process using the
video display for handshaking
System Programmers Information
The Model 4P Boot ROM uses two areas of RAM while it is running These are 4000H to 40FFH and 4300H to 43FFH (For
512 byte boot sectors, the second area is 4300H to 44FFH ) If
the Model III ROM Image is loaded additional areas are used
See the technical reference manual for the system you are using for a list of these areas
Operating systems that want to support a software restart by reexecuting the contents of the boot ROM can accomplish this in
one of two ways If the operating system relies on the Model III
ROM Image, then jump to location 0 as you have in the past If
the operating system is a Model 4 mode package, a simple way
is to code the following instructions in your assembly and load
them before you want to reset

The message
"Error"
is then transmitted to the host The entire process is then repeated from the ' Not Ready' message A six second delay is
inserted before reinitialization This is longer than the time required to transmit five bytes at 50 baud, so there is no need to
be extra careful here
If the sync byte is received without error, then the "Loading1
message is transmitted and the program is ready to receive the
command file After receiving the ' Loading message the host
can transmit the file without nulls or delays between bytes

Absolute Location
0000
0001
0003

Instruction
Dl
LD
A1
OUT
(9CH) A

These instructions cause the boot ROM to become addressable After executing the OUT instruction the next instruction
executed will be one in the boot ROM (These instructions also
exist in the Model III ROM image at location 0 ) The boot ROM
has been written so that the first instruction is at address 0005
The hardware must be in memory mode 0 or 1, or else the
boot ROM will not be switched in This operation can be
done with an OUT instruction and then a RST 0 can be executed to have the ROM switched in

Hardware 69

Restarts can be redirected at any time while the ROM is
switched in All restarts jump to fixed locations in RAM and
these areas may be changed to point to the routine that is to be
executed
Restart
0
8
10
18
20
28
30
38
66

RAM Location
none
4000H
4003 H
4006H
4009H
400CH
400FH
401 2H
4015H

Default Use
Cold Start Boot
Disk I O Request
Display string
Display block
Byte Fetch (Called by Loader)
File Loader
Keyboard scanner
Reserved for future use
NMI (Floppy I O Command
Complete)

Display String (RST10H)
Accepts
HL
DE

Returns
Success Always
A
DE
HL

Pointer to text to be displayed
Text must be terminated with a null (0)
Offset position on screen where text is to
be displayed
(A OOOOH will be the upper left-hand corner of the display )

Altered
Points to next position on video
Points to the null (0)

Display Block (RST 18H)
The above routines have fixed entry parameters These are described here

Accepts
HL

Disk I/O Request (RST 8H)
Accepts
A
B

DE
HL

1 for floppy 2 for hard disk
Command
Initialize
Restore
Seek
Read
12 (All reads have an implied seek)
Sector number to read
The contents of the location disktype
(405CH) are added to this value before
an actual read If the disk is a two sided
floppy just add 18 to the sector number
Cylinder number (Only E is used in
floppy operations)
Address where data from a read operation is to be stored

Points
+0
+2
null
+4
null
+n

to control vector in the format
Screen Offset
Pointer to text, terminated with
Pointer to text terminated with

word FFFFH

End of control
vector
or
+n
word FFFEH
Next word is
new Screen
Offset
If Z flag is set on entry, then the first screen offset is read from
DE instead of from the control vector
Each string is positioned after the previous string unless a
FFFEH entry is found This is used heavily in the ROM to reduce duplication of words in error messages
Returns
Success Always
DE

Points to next position on video

Returns
Z
NZ

Byte Fetch (RST 20H)

Success Operation Completed
Error Error code in A

Error Codes
3
4
5
6
7

8
9
11
12

Hard Disk drive is not ready
Floppy disk drive is not ready
Hard Disk drive is not available
Floppy disk drive is not available
Drive Not Ready and no Index (Disk in
drive door open)
CRC Error
Seek Error
Lost Data
ID Not Found

Accepts None
Returns
Z
NZ

Success byte in A
Failure error code in A

Errors

Hardware 70

2
10

Any errors from the disk I O call and
ROM Image can t be loaded — Too many
extents
ROM Image can t be loaded — Disk drive
is not ready

o

File Loader (RST28H)
Accepts None
Returns
Z
NZ

Success
Failure, error code in A

Errors

0

Any errors from the disk I/O call or the
byte fetch call and:
The ROM image was not found on drive 0

There are several pieces of information left in memory by the
boot ROM which are useful to system programmers. These are
shown below:
RAM Location
401 DH
4055H

4056H
4057H
4059H

^
405BH
405CH

Description
ROM Image Selected (% for none
selected or A-G)
Boot type
1 - Floppy
2 - Hara disk
3 - ARCNET
4 - RS-232C
5 - 7 = Reserved
Boot Sector Size (1 for 256, 2 for 512)
RS-232 Baud Rate (only valid on RS232 boot)
Function Key Selected
0 - No function key selected
 or ^1 86

82
•- Right-Shift
83
80-81 and 89-90
Reserved
Break Key Indication (non-zero if
• Break - pressed)
Disk type
(0 for LDOS
TRSDOS6.1 for
TRSDOSLx)

The DRAMs require multiplexed incoming address lines. This
is accomplished by ICs U111 and U112 which are 74LS157
multiplexers. Data to and from the DRAMs are buffered by a
74LS245 (U117) which is controlled by Page Map PAL. U110.
The proper timing signals RASO*. PAST, MUX*. and CAS* are
generated by a delay line circuit U97. U115 (1 2 of a 74S112)
and U116 (1 4 of a 74F08) are used the generate a precharge
circuit. During M1 cycles of the Z80A in 4 MHz mode, the high
time in MREQ has a minimum time of 110 nanosecs. The specification of 6665 DRAM requires a minimum of 120 nanosecs so
this circuit will shorten the MREQ signal during the M1 cycle.
The resulting signal PMREQ is used to start a RAM memory
cycle through U113 (a 74S64). Each different cycle is controlled
at U113 to maintain a fast M1 cycle so no wait states are required. The output of U113 (PRAS*) is ANDed with RFSH to not
allow MUX* and CAS* to be generated during a REFRESH
cycle. PRAS* also generates either RASO* or RAS1*, depending on which bank of RAM the CPU is selecting. GCAS* generated by the delay line U97 is latched by U115 (1 2 of a
74S112) and held to the end of the memory cycle. The output
of U115 is ANDed with VIDEO signal to disable the CAS* signal
from occurring if the cycle is a video memory access. Refer to
M1 Cycle Timing (Figure 3-8. and 3-9.), Memory Read and
Memory Write Cycle Timing (Figure 3-10.) and (Figure 311.).

Keep in mind that Model III ROM image will initialize these
areas, so this information is useful only to the Model 4 mode
programmer.

3.1.7 RAM
Two configurations of Random Access Memory (RAM) are
available on the Model 4P: 64K and 128K. The 64K and 128K
option use the 6665-type 64K x 1 200NS Dynamic RAM. which
requires only a single - 5v supply voltage.

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Memory Map — Model 4P

ModeO

0000 — OFFF
1000 — 37FF
37E8 — 37E9
3800 — 3BFF
3COO — 3FFF
4000 — FFFF

SELO
SEL1
ROM

0 - 0V
0
0V
1
0V
Boot ROM
RAM (Read Only)
Printer Status (Read Only)
Keyboard
Video
RAM

Mode 1

4K
10K
2
1K
1K
48K

0000 — 37FF
3800 — 3BFF
3COO — 3FFF
4000 — FFFF

Mode 2
ModeO

0000 — 37FF
37E8 — 37E9
3800 — 3BFF
3COO — 3FFF
4000 — FFFF

Mode 1

0000 — OFFF
0000 — OFFF
1000 — 37FF
3800 — 3BFF
3COO — 3FFF
4000 — FFFF

SELO - 0 - 0V
SEL1 - 0 - 0V
ROM - 0 - -r 5V
RAM (Read Only)
Printer Status (Read Only)
Keyboard
Video
RAM

14K
2
1K
1K
48K

SELO - 1 - + 5V
SEL1 - 0 - 0V
ROM - 1 - 0V
Boot ROM
RAM (Write Only)
RAM

Keyboard
Video
RAM

0000 — F3FF
F400 — F7FF
F800 — FFFF

Mode3

0000 — FFFF

4K
4K
10K
1K
1K
48K

Hardware 79

SELO - 1 - - 5V
SEL1 - 0 - 0V
ROM - 0
-5V
RAM
Keyboard
Video
RAM

14K
1K
1K
48K

SELO - 0 - 0V
SEL1 - 1 - +5V
ROM - X - Don t Care
RAM
Keyboard
Video

61 K
1K
2K

SELO = 1 - ^5V
SEL1 = 1 - +5V
ROM - X - Don t Care
RAM

64K

I/O Port Assignment

Port#
FC — FF
F8 — FB
F4 — F7
FO— F3

Normally
Used
FF
F8
F4
-

EC — EF
E8 — EB

FO
F1
F2
F3
EC
-

E8
E9
EA

E8
E9
EA

EB

EB

E4—E7
EO—E3
AO—DF
9C — 9 F
94 —9B
90 — 93
8C —8F
88 — 8 B
88, 8A
89, 8B
84 — 87
80 — 83

E4
EO

FO
F1
F2
F3

9C
90

88
89
84

Out
CASSOUT *
LPOUT *
DRVSEL *
DISKOUT *
FDC COMMAND REG.
FDC TRACK REG.
FDC SECTOR REG.
FDC DATA REG.
MODOUT *
RS232OUT *
UART MASTER RESET
BAUD RATE GEN. REG.
UART CONTROL AND
MODEM CONTROL REG.
UART TRANSMIT
HOLDING REG.
WR NMI MASK REG. *
WR INT MASK REG. *
(RESERVED)
BOOT*
(RESERVED)
SEN*
GSELO *
CRTCCS *
CRCTADD. REG.
CRCT DATA REG.
OPREG *
GSEL1 *

In
MODIN*
LPIN*
(RESERVED)
DISKIN*
FDC STATUS REG.
FDC TRACK REG.
FDC SECTOR REG.
FDC DATA REG.
RTCIN *
RS232IN *
MODEM STATUS
(RESERVED)
UART STATUS REG.
UART HOLDING REG.
(RESET D.R.)
RD NMI STATUS *
RD INT MASK REG. *
(RESERVED)
(RESERVED)
(RESERVED)
(RESERVED)
GSELO *
(RESERVED)
(RESERVED)
(RESERVED)
(RESERVED)
GSEL1 *

o

Hardware 80

Name:
Port Address:
Access:
Description:

I/O Port Description
Name:
Port Address:
Access:
Description:

Note:

CASSOUT *
FC — F F
WRITE ONLY
Output data to cassette or for sound
generation

The Model 4P does not support cassette storage,
this port is only used to generate sound that was to
be output via cassette port. The Model 4P sends
data to onboard sound circuit.

DO

= Cassette output level (sound data output)

D1

= Reserved

D2 — D7

= Undefined

Name:
Port Address:
Access:
Description:

DO —D3

- (RESERVED)

D4

=- FAULT
1 - TRUE
0 - FALSE

D5

- UNIT SELECT
1 - TRUE
0 - FALSE

D6

- OUTPAPER
1 - TRUE
0 - FALSE

D7

= BUSY
1 = TRUE
0 - FALSE

MODIN * (CASSIN *)
FC —FF
READ ONLY
Configuration Status

DO

-0

D1

- CASSMOTORON STATUS

Name:
Port Address:
Access:
Description:

D2

- MODSEL STATUS

Note:

D3

- ENALTSET STATUS

D4

- ENEXTIO STATUS

OS

- (NOT USED)

D6

= FAST STATUS

D7

=0

Name:
Port Address:
Access:
Description:
DO — D7

LPOUT *
F8 —FB
WRITE ONLY
Output data to line printer

LPIN *
F8 — F B
READ ONLY
Input line printer status

DRVSEL *
F4 — F 7
WRITE ONLY
Output FDC Configuration

Output to this port will ALWAYS cause a 1 -2 msec.
(Microsecond) wait to the Z80.

DO

- DRIVE SELECT 0

D1

= DRIVE SELECT 1

D2

= (RESERVED)

D3

- (RESERVED)

D4

- SDSEL
0 = SIDEO
1 - SIDE 1

D5

= PRECOMPEN
0 = No write precompensation
1 = Write Precompensation enabled

D6

- WSGEN
0 = No wait state generated
1 = wait state generated

= ASCII BYTE TO BE PRINTED

Note:

D7

Hardware 81

This wait state is to sync Z80 with FDC chip during
FDC operation.
- DDEN *
0 = Single Density enabled (FM)
1 = Double Density enabled (MFM)

Name:
Port Address:
Access:
Description:

DISKOUT *
FO—F3
WRITE ONLY
Output to FDC Control Registers

D4

ENEXTIO
0 - External IO Bus disabled
1 - External IO Bus enabled

D5

= (RESERVED)

D6

- FAST
0 ~ 2 MHZ Mode
1 - 4 MHZ Mode

07

- (RESERVED)

Port FO = FDC Command Register
Port F1 = FDC Track Register
Port F2 - FDC Sector Register
Port F3 = FDC Data Register
(Refer to FDC Manual for Bit Assignments)

Name:
Port Address:
Access:
Description:

DISKIN *
FO —F3
READ ONLY
Input FDC Control Registers

Port FO = FDC Status Register
Port F1 = FDC Track Register

Name:
Port Address:
Access:
Description:
DO —D7

RTCIN *
EC—EF
READ ONLY
Clear Real Time Clock Interrupt

•

- DON T CARE

Name:
Port Address:
Access:
Description:

Port F2 = FDC Sector Register

RS232OUT *
E8—EB
WRITE ONLY
UART Control Data Control Modem Control,
BRG Control

Port F3 = FDC Data Register

Port E8 = UART Master Reset

(Refer to FDC Manual for Bit Assignment)

Port E9 - BAUD Rate Gen Register
Port EA = UART Control Register (Modem Control Reg )

Name:
Port Address:
Access:
Description:

MODOUT *
EC — E F
WRITE ONLY
Output to Configuration Latch

DO

- (RESERVED)

D1

= CASSMOTORON (Sound enable)
0 - Cassette Motor Off (Sound enabled)
1 = Cassette Motor On (Sound disabled)

D2

= MODSEL
0 = 64 or 80 character mode
1 = 32 or 40 character mode

D3

- ENALTSET
0 = Alternate character set disabled
1 = Alternate character set enabled

Port EB = UART Transmit Holding Reg
(Refer to Model III or 4 Manual for Bit Assignments)

Name:
Port Address:
Access:
Description:

c

RS232IN *
E8 — E B
READONLY
Input UART and Modem Status

Port E8 - MODEM STATUS
Port E9 = (RESERVED)
Port EA = UART Status Register
Port EB - UART Receive Holding Register (Resets DR)
(Refer to Model III or 4 Manual for Bit Assignments)

w
Hardware 82

Name:
Port Address:
Access:
Description:

WRNMIMASKREG *
E4 — E 7
WRITE ONLY
Output NMI Latch

DO —D5

= (RESERVED)

D6

- ENMOTOROFFINT
0 = Disables Motoroff NMI
1 - Enables Motoroff NMI

D7

= ENINTRQ
0 = Disables INTRQ NMI
1 = Enables INTRQ NMI

Name:
Port Address:
Access:
Description:

=0

D2 —D4

= (RESERVED)

D5

= RESET (not needed)
0 = Reset Asserted (Problem)
1 = Reset Negated

O6

D7

- ENRECINT
0 - RS232 Rec Data Reg. full int. disabled
1 - RS232 Rec. Data Reg. full mt enabled

D6

- ENERRORINT
0 - RS232 UART Error interrupts disabled
1 - RS232 UART Error interrupts enabled

D7

- (RESERVED)

Name:
Port Address:
Access:
Description:

RDNMISTATUS *
E4 — E 7
READ ONLY
Input NMI Status

DO

D5

- MOTOROFF
0 = Motoroff Asserted
1 = Motoroff Negated

DO — D 1

= (RESERVED)

D2

= RTCINT

D3

= IOBUS INT

D4

= RS232 XMIT INT

D5

= RS232 REC INT

D6

- RS232 UART ERROR INT

D7

- (RESERVED)

Name:
Port Address:
Access:
Description:

= INTRQ
0 = INTRQ Asserted
1 - INTRQ Negated

WRINTMASKREG *
EO —E3
WRITE ONLY
Output INT Latch

DO —D1

= (RESERVED)

D2

= ENRTC
0 = Real time clock interrupt disabled
1 = Real time clock interrupt enabled

D3

= ENIOBUSINT
0 = External IO Bus interrupt disabled
1 = External IO Bus interrupt enabled

D4

D1—D7

BOOT *
9C — 9F
WRITE ONLY
Enable or Disable Boot ROM
ROM *
0 - Boot ROM Disabled
1 = Boot ROM Enabled

DO
Name:
Port Address:
Access:
Description:

RDINTSTATUS *
EO — E 3
READ ONLY
Input INT Status

- (RESERVED)

Name:
Port Address:
Access:
Description:

SEN *
90 — 93
WRITE ONLY
Sound output

DO

= SOUND DATA

D1—D7

= (RESERVED)

= ENXMITINT
0 = RS232 Xmit Holding Reg. empty int.
disabled
1 = RS232 Xmit Holding Reg. empty int.
enabled

Hardware 83

Name:
Port Address:
Access:
Description:

OPREG *
84
WRITE ONLY
Output to operation reg.

DO

= SELO

D1

= SEL1
SEL1
0

SELO
0

MODE
0

0
1
1

1
0
1

1
2
3

•

D2

= 8064
0 = 64 character mode
1 = 80 character mode

D3

= INVERSE
0 = Inverse video disabled
1 = Inverse video enabled

D4

= SRCPAGE — Points to the page to be mapped
as new page
0 = U64K, L32K Page
1 = U64K, U32K Page

D5

= ENPAGE — Enables mapping of new page
0 = Page mapping disabled
1 = Page mapping enabled

D6

- DESPAGE — Points to the page where new
page is to be mapped
0 = L64K, U32K Page
1 = L64K, L32K Page

D7

= PAGE
0 = Page 0 of Video Memory
1 = Page 1 of Video Memory

Hardware 84

0

3.1.8 Video Circuit
The heart of the video display circuit in the Model 4P is the
68045 Cathode Ray Tube Controller (CRTC), U85 The CRTC
is a preprogrammed video controller that provides two screen
formats 64 by 16 and 80 by 24 The format is controlled by pin
3 of the CRTC (8064*) The CRTC generates all of the necessary signals required for the video display These signals are
VSYNC (Vertical Sync), HSYNC (Horizontal Sync) for proper
sync of the monitor, DISPEN (Display Enable) which indicates
when video data should be output to the monitor, the refresh
memory addresses (MAO-MA 13) which addresses the video
RAM, and the row addresses (RAO-RA4) which indicates which
scan line row is being displayed The CRTC also provides hardware scrolling by writing to the internal Memory Start Address
Register by OUTmg to Port 88H The internal cursor control of
the 68045 is not used in the Model 4P video circuit
Since the 80 by 24 screen requires 1,920 screen memory locations, a 2K by 8 static RAM (U82) is used for the video RAM
Addressing to the video RAM (U82) is provided by the 68045
when refreshing the screen and by the CPU when updating of
the data is performed These two sets of address lines are multiplexed by three 74LS157s (U83, U84, and U104) The multiplexers are switched by CRTCLK which allows the CRTC to
address the video RAM during the high state of CRTCLK and
the CPU access during the low state A10 from the CPU is controlled by PAGE* which allows two display pages in the 64 by
16 format When updates to the video RAM are performed by
the CPU, the CPU is held in a WAIT state until the CRTC is not
addressing the video RAM This operation allows reads and
writes to video RAM without causing hashing on the screen
The circuit that performs this function is a 74LS244 buffer
(U103), an 8 bit transparent latch, 74LS373 (U102) and a Delay
line circuit shared with Dynamic RAM timing circuit consisting
Of a 74LS74 (U95), 74LS32 (U94), 74LS04 (U74), 74LSOO
(U96), 74LS02 (U75), and Delay Line (U97) During a CPU
Read Access to the Video RAM, the address is decoded by the
PAL U109 and asserts VIDEO* low This is inverted by U74 (1/
6 of 74LS04) which pulls one input of U96 (1/4 of 74LSOO) and
in turn asserts VWAIT * low to the CPU RD is high at this time
and is latched into U95 (1/2 of 74LS74) on the rising edge of
XADR7* XADR7* is inverse of CRTCLK which drives the
CRTC (68045), and the address multiplexers U83, U84, and
U104

When RD is latched by U95 the Q output goes low releasing
WAIT* from the CPU The same signal also is sent to the Delay
Line (U97) through U116 (1 4 of 74F08) The Delay line delays
the falling edge 240 ns for VLATCH* which latches the read
data from the video RAM at U102 The data is latched so the
CRTC can refresh the next address location and prevent any
hashing MRD* decoded by U108 and a memory read is ORed
with VIDEO* which enables the data from U102 to the data bus
The CPU then reads the data and completes the cycle A CPU
write is slightly more complex in operation As in the RD cycle,
VIDEO* is asserted low which asserts VWAIT* low to the CPU
WR is high at this time which is NANDed with VIDEO and
synced with CRTCLK to create VRAMDIS that disables the
video RAM output On the rising edge of XADR7*, WR is
latched into U95 (1/2 of 74LS74) which releases VWAIT* and
starts cycle through the Delay Line After 30ns DLYVWR* (Delayed video write) is asserted low which also asserts VBUFEN*
(Video Buffer Enable) low VBUFEN* enabled data from the
Data bus to the video RAM Approximately 120ns later
DLYVWR* is negated high which writes the data to the video
RAM and negates VBUFEN* turning off buffer The CPU then
completes WR cycle to the video RAM Refer to Video RAM
CPU Access Timing Figure 5-12 for timing of above RD or WR
cycles
During screen refresh, CRTCLK is high allowing the CRTC to
address Video RAM The data out of the video RAM is latched
by LOAD* into a 74LS273 (U101) D7 is generated by INVERSE* through U125 (1/6 of 74S04), and U123 (1/4 of
74LS08) This decoding determines if character should be alpha-numeric only (if inverse high) or unchanged (INVERSE*
low) The outputs of U101 are used as address inputs the character generator ROM (U42) A9 is decoded with ENALTSET
(Enable Alternate Set) and Q7 of U101, which resets A9 to a
low if Q7 and ENALTSET are high See ENALTSET Control Table below

Hardware 85

ENALTSET
0
0
0

A9
0
0

Q6
0
0

1

Q7
0
1
1
0
0

1

1

1

1

0

1

1

1

0
0

1

1

1

0

0

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RAO-RA3 row addresses from the CRTC are used to control
which scan line is being displayed The Model 4P has a 4-bit full
adder 74LS283 (U61) to modify the Row address During a
character display DLYGRAPHIC* is high which applies a high to
all 4 bits to be added to row address This will result in subtracting one from Row address count and allow all characters to be
displayed one scan line lower The purpose is so inverse characters will appear within the inverse block When a graphic
block is displayed DLYGRAPHIC* is low which causes the row
address to be unmodified Moving jumper from E14-E15 to
E15-E16 will disable this circuit
DLYCHAR* and DLYGRAPHICS are inverse signals and control which data is to be loaded into the shift register U63
When DLYCHAR* is low and DLYGRAPHIC* is high, the
Character Generator ROM (U42) is enabled to output data
when DLYCHAR* is high and DLYGRAPHIC* is low the
graphics characters from U41 (74LS15) is buffered by U43
(74LS244) to the shift register The data is loaded into the
shift register on the rising edge of SHIFT* when LOADS* is
low Blanking is accomplished by masking off LOADS* so no
data will be loaded and zero data will be shifted out with the
serial input of U63, pin 1, grounded Serial video data is output U63 pin 13 and is mixed with inverse and/or hires graphics information by (1/4 or 74LS86) U143 The video data is
then mixed with a DO7 Rate clock, either DOT* and DCLK,
to create distinct dots on the monitor DOT* and DCLK are
inverse signals and are provided to allow a choice to obtain
the best video results The video information is filtered by
F34, R45 (47 ohm resistor), and C241 (100 pf Cap) and output to video monitor VSYNC and HSYNC are buffered by
(1/2 of 74LS86) U143 and are also output to video monitor
Refer to Video Circuit Timing Figure 3-13, Video Blanking
Timing Figure 3-14, and Inverse Video Timing Figure 3-15
for timing relationships of Video Circuit

3.1.9 Keyboard
The keyboard interface of the Model 4P consists of open collector drivers which drive an 8 by 8 key matrix keyboard and an
inverting buffer which buffers the key or keys pressed on the
data bus The open collector drivers (U56 and U57 (7416) are
driven by address lines AO-A7 which drive the column lines of
the keyboard matrix The ROW lines of the keyboard are pulled
up by a 1 5 kohm resistor pack RP2 The ROW lines are buffered and inverted onto the data bus by U58 (74LS240) which is
enabled when KEYBD* is a logic low KEYBD* is a memory
mapped decode of addresses 3800-3BFF in Model III Mode
and F400-F7FF in Model 4/4P mode Refer to the Memory Map
under Address Decode for more information During real time
operation, the CPU will scan the keyboard periodically to check
if any keys are pressed If no key is pressed, the resistor pack
RP2 keeps the inputs of U58 at a logic high U58 inverts the
data to a logic low and buffers it to the data bus which is read
by the CPU If a key is pressed when the CPU scans the correct
column line, the key pressed will pull the corresponding row to
a logic low U58 inverts the signal to a logic high which is read
by the CPU

3.1.10 Real Time Clock
The Real Time Clock circuit in the Model 4P provides a 30 Hz
(in the 2 MHz CPU mode) or 60 Hz (in the 4 MHz CPU mode)
interrupt to the CPU By counting the number of interrupts that
have occurred, the CPU can keep track of the time The 60 Hz
vertical sync signal (VSYNC) from the video circuitry is used for
the Real Time Clock s reference In the 2 MHz mode, FAST is
a logic low which sets the Preset input, pin 4 of U22 (74LS74),
to a logic high This allows the 60 Hz (VSYNC) to be divided by
2 to 30 Hz The output of 1/2 of U22 is ORed with the original
60 Hz and then clocks another 74LS74 (1/2 of U22) If the real
time clock is enabled (ENRTC at a logic high), the interrupt is
latched and pulls the INT* line low to the CPU When the CPU
recognizes the interrupt, the pulse is counted and the latch reset by pulling RTCIN* low In the 4 MHz mode, FAST is a logic
high which keeps the first half of U22 in a preset state (the Q*
output at a logic low) The 60 Hz is used to clock the interrupts
NOTE: If interrupts are disabled, the accuracy of the real
time clock will suffer

3.1.11 Line Printer Port
The Line Printer Port Interface consists of a pulse generator, an
eight-bit latch, and a status line buffer The status of the line
printer is read by the CPU by enabling buffer U3 (74LS244)
This buffer is enabled by LPRD* which is a memory map and
port map decode In Model III mode, only the status can be read
from memory location 37E8 or 37E9 The status can be read in
all modes by an input from ports F8-FB For a listing of the bit
status, refer to Port Map section
After the printer driver software determines that the printer is
ready for printing (by reading the correct status), the characters
to be printed are output to Port F8-FB U2, a 74LS374 eight-bit
latch, latches the character byte and outputs to the line printer
One-half of U1 (74LS123), a one-shot, is then triggered which
generates an appropriate strobe signal to the printer which signifies a valid character is ready The output of the one-shot is
buffered by 1/6th of the U21 (74LS04) to prevent noise from the
printer cable from flase-tnggering the one-shot

Hardware 87

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3.1.12 urapnics port

Addresses

The Graphics Port (J7) on the Model 4P is provided to attach
the optional Graphics Board The port provides DO-D7 (Data
Lines), AO-A3 (Address Lines), IN*, GEN* and RESET* for the
necessary interface signals for the Graphics Board GEN* is
generated by negative ORmg Port selects GSELO* (8C-8FH)
and GSELI* (80-83H) together by (1 4 of 74LS08) U23 The resulting signal is negative ANDed with IORQ* by (1 4 of 74S32)
U62 Seven timing signals are provided to allow synchronization of Mam Logic Board Video and Graphics Board Video
These timing signals are VSYNC, HSYNC, DISPEN, DCLK, H,
I, and J Three control signals from the Graphics Board are
used to sync to CPU access and select different video modes
WAIT* controls the CPU access by causing the CPU to WAIT till
video is in retrace area before allowing any writes or reads to
Graphics Board RAM ENGRAF is asserted when Graphics
video is displayed ENGRAF also disables inverse video mode
on Mam Logic Board Video CL166* (Clear 74L166) is used to
enable or disable mixing of Mam Logic Board Video and Graphics Board Video If CL166* is negated high, then mixing is allowed in all for video modes 80 x 24, 40 x 24, 64 x 16, and 32 x
16. If CL166* is asserted low, this will clear the video shift register U63, which allows no video from the Mam Logic Board In
this state 8064* is automatically asserted low to put screen in
80 x 24 video mode Refer to Figure 3-16 Graphic Board
Video Timing for timing relationships Refer to the Model 4/
4P Graphics Board Service information for service or technical information on the Graphics Board

3.1.13 Sound
The sound circuit in the Model 4P is compatible with the Sound
Board which was optional in the Model 4 Sound is generated
by alternately setting and clearing data bit DO during an OUT to
port 90H The state of DO is latched by U130 (1/2 of a 74LS74)
and the output is amplified by Q2 which drives a piezoelectric
sound transducer The speed of the software loop determines
the frequency, and thus, the pitch of the resulting tone Since
the Model 4P does not have a cassette circuit, some existing
software that used the cassette output for sound would have
been lost The Model 4P routes the cassette latch to the sound
board through U142 When the CASSMOTORON signal is a
logic low, the cassette motor is off, then the cassette output is
sent to the sound circuit

3.1.14 I/O Bus Port
The Model 4P Bus is designed to allow easy and convenient interfacing of I/O devices to the Model 4P The I O Bus supports
all the signals necessary to implement a device compatible with
the Z80s I/O structure

AO to A7 allow selection of up to 256* input and 256 output
devices if external I O is enabled
*Ports 80H to OFFH are reserved for System use
Data
DBO to DB7 allow transfer of 8-bit data onto the processor
data bus is external I O is enabled
Control Lines
1

M1* — Z80A signal specifying an M1 or Operation Code
Fetch Cycle or with IOREQ*, it specifies an Interrupt
acknowledge

2

IN* — Z80A signal specifying than an input is in progress
Logic AND of IOREQ* and WR*

3

OUT* — Z80A signal specifying that an output is in progress Logic AND of IOREQ* and WR*

4

IOREQ* — Z80A signal specifying that an input or output
is in progress or with M1*, it specifies an interrupt
acknowledge

5

RESET* — system reset signal

6

IOBUSINT* — input to the CPU signaling an interrupt from
an I/O Bus device if I/O Bus interrupts are enabled.

7

IOBUSWAIT* — input to the CPU wait line allowing I/O Bus
device to force wait states on the Z80 if external I/O is
enabled

8

EXTIOSEL* — input to I/O Bus Port circuit which switches
the I/O Bus data bus transceiver and allows and INPUT instruction to read I/O Bus data

The address line, data line, and all control lines except RESET*
are enabled only when the ENEXIO bit in port EC is set to one
To enable I/O interrupts, the ENIOBUSINT bit in the PORT EO
(output port) must be a one However, even if it is disabled from
generating interrupts, the status of the IOBUSINT* line can still
read on the appropriate bit of CPU IOPORT EO (input port)
See Model 4P Port Bit assignments for port OFF, OEC, and OEO

Hardware 91

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Hardware 92

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The Model 4P CPU board is fully protected from foreign I O devices in that all the I O Bus signals are buffered and can be disabled under software control To attach and use and I O device
on the I O Bus certain requirements (both hardware and software) must be met
For input port device use, you must enable external I/O devices by writing to port OECH with bit 4 on in the user software. This will enable the data bus address lines and control
signals to the I/O Bus edge connector. When the input device is selected, the hardware should acknowledge by asserting EXTIOSEL* low. This switches the data bus
transceiver and allows the CPU to read the contents of the I/
O Bus data lines. See Figure 3-17 for the timing. EXTIOSEL* can be generated by NANDing IN and the I/O port
address.
Output port device use is the same as the input port device in
use, in that the external I'O devices must be enabled by writing
to port OECH with bit 4 on in the user software — in the same
fashion
For either input or output devices, the IOBUSWAIT* control line
can be used in the normal way for synchronizing slow devices
to the CPU Note that since dynamic memories are used in the
Model 4P, the wait line should be used with caution Holding the
CPU in a wait state for 2 msec or more may cause loss of memory contents since refresh is inhibited during this time It is recommended that the IOBUSWAIT* line be held active no more
than 500 jj-sec with a 25% duty cycle
The Model 4P will support Z80 Mode 1 interrupts A RAM jump
table is supported by the LEVEL II BASIC ROMs image and the
user must supply the address of his interrupt service routine by
writing this address to locations 403E and 403F When an interrupt occurs, the program will be vectored to the user-supplied address if I'O Bus interrupts have been enabled To
enable I/O Bus interrupts, the user must set bit 3 of Port OEOH

3.1.15 FDC Circuit
The TRS-80 Model 4P Floppy Disk Interface provices a standard 5-1 4" floppy disk controller The Floppy Disk Interface
supports both single and double density encoding schemes
Write precompensation can be software enabled or disabled
beginning at any track, although the system software enables
write precompensation for all tracks greater than twenty-one
The amount of write precompensation is 250 nsec and is not
adjustable The data clock recovery logic incorporates a digital
data separator which achieves state-of-the-art reliability One
or two drives may be controlled by the interface All data transfers are accomplished by CPU data requests In double density
operation, data transfers are synchronized to the CPU by forcing a wait to the CPU and clearing the wait by a data request
from the FDC chip The end of the data transfer is indicated by
generation of a non-maskable interrupt from the interrupt request output of the FDC chip A hardware watchdog timer insures that any error condition will not hang the wait line to the
CPU for a period long enough to destroy RAM contents

Hardware 93

Input or Output Cycles.

Tw'

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READ
CYCLE

WRITE
CYCLE

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Input or Output Cycles with Wait States.

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A* A7

DATA BUS

READ
CYCLE

RD-

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WRITE
CYCLE

'Interred by Z80 CPU
^Coincident with IORQ* only on INPUT cycle

Figure 3-17. I/O Bus Timing Diagram

Hardware 94

Control and Data Buffering

*Only one of these bits should be set per output

The Floppy Disk Controller Board is an I O port-mapped device
which utilizes ports E4H FOH F1H F2H F3H and F4H The
decoding logic is implemented on the CPU board (Refer to Par
agraph 5 1 5 Address Decoding for more information on Port
Map) U31 is a bi-directional 8-bit transceiver used to buffer
data to and from the FDC and RS-232 circuits The direction of
data transfer is controlled by the combination of control signals
DISKIN* and RS232IN* If either signal is active (logic low) U31
is enabled to drive data onto the CPU data bus If both signals
are inactive (logic high), U31 is enabled to receive data from the
CPU board data bus A second buffer (U12) is used to buffer the
FDC chip data to the FDC RS232 Data Bus (BDO-BD7), U12 is
enabled all the time and it s direction controlled by DISKIN*
Again, if DISKIN* is active (logic low) data is enabled to drive
from the FDC chip to the Mam Data Busses If DISKIN* is inactive (logic high) data is enabled to be transferred to the FDC
chip

Hex D flip-flop U32 (74L174) latches the drive select bits side
select and FM* MFM bits on the rising edge of the control signal
DRVSEL* A dual D flip-flop (U98) is used to latch the Wait Enable and Write precompensation enable bits on the rising edge
of DRVSEL* The rising edge of DRVSEL* also triggers a oneshot (1 2 of U54 74LS123) which produces a Motor On to the
disk drives The duration of the Motor On signal is approximately three seconds The spindle motors are not designed for
continuous operation Therefore, the inactive state of the Motor
On signal is used to clear the Drive Select Latch, which de-selects any drives which were previously selected The Motor On
one-shot is retnggerable by simply executing another OUT instruction to the Drive Select Latch

Nonmaskable Interrupt Logic
Dual D flip-flop U100 (74LS74) is used to latch data bits D6 and
D7 on the rising edge of the control signal WRNMIMASKREG*
The outputs of U100 enable the conditions which will generate
a non-maskable interrupt to the CPU The NMI interrupt conditions which are programmed by doing an OUT instruction to
port E4H with the appropriate bits set If data bit 7 is set, an FDC
interrupt is enabled to generate an NMI interrupt If data bit 7 is
reset interrupt requests request from the FDC are disabled If
data bit 6 is set a Motor Time Out is enabled to generate an
NMI interrupt If data bit 6 is reset interrupts on Motor Time Out
are disabled An IN instruction from port E4H enables the CPU
to determine the source of the non-maskable interrupt Data bit
7 indicates the status of FDC interrupt request (INTRO)
(0-true 1-false) Data bit 6 indicates the status of Motor
Time Out (0 - true, 1 - false) Data bit 5 indicates the status of
the Reset signal ( 0 - t r u e , 1 - f a l s e ) The control signal
RDNMISTATUS* gates this status onto the CPU data bus when
active (logic low)

Drive Select Latch and Motor ON Logic
Selecting a drive prior to disk I O operation is accomplished by
doing an OUT instruction to port F4H with the proper bit set The
following table describes the bit allocation of the Drive Select
Latch
Data Bit
DO
D1
D2
D3
D4
D5
D6
D7

Function
Selects Drive 0 when set*
Selects Drive 1 when set*
Selects Drive 2 when set*
Selects Drive 3 when set*
Selects Side 0 when reset
Selects Side 1 when set
Write precompensation enabled when set
disabled when reset
Generates WAIT if set
Selects MFM mode if set
Selects FM mode if reset

Wait State Generation and WAITIMOUT Logic
As previously mentioned, a wait state to the CPU can be initiated by an OUT to the Drive Select Latch with D6 set Pin 5 of
U98 will go high after this operation This signal is inverted by
I 4th of U79 and is routed to the CPU where it forces the Z80A
into a wait state The Z80A will remain in the wait state as long
as WAIT* is low Once initiated, the WAIT* will remain low until
one of five conditions is satisfied One half of U77 (a five input
NOR gate) is used to perform this function INTO DRQ, RESET, CLRWAIT, and WAITIMOUT are the inputs to the NOR
gate If any one of these inputs is active (logic high) the output
of the NOR gate (U77 pin 5) will go low This output is tied to the
clear input of the wait latch When this signal goes low, it will
clear the Q output (U98 pin 5) and set the Q* output (U98 pin
6) This condition causes WAIT* to go high which allows the
Z80 to exit the wait state U99 is a 12-bit binary counter which
serves as a watchdog timer to insure that a wait condition will
not persist long enough to destroy dynamic RAM contents The
counter is clocked by a 1 MHz clock and is enabled to count
when its reset pin is low (U99 pin 11) A logic high on U99 pin
I1 resets the counter outputs U99 pin 15 is a divide-by-1024
output and is used to generate the signal WAITIMOUT This
watchdog timer logic will limit the duration of a wait to
1024^sec, even if the FDC chip should fail to generate a DRQ
or an INTRO
If an OUT to Drive Select Latch is initiated with D6 reset (logic
low), a WAIT is still generated The 12-bit binary counter will
count to 2 which will output CLRWAIT and clear the WAIT state
This allows the WAIT to occur only during the OUT instruction
to prevent violating any Dynamic RAM parameters
NOTE:

Hardware 95

This automatic WAIT will cause a 1 -2 t^sec wait each
time an out to Drive Select Latch is performed

Clock Generation Logic
A 4 MHz crystal oscillator and a 4-bit binary counter are used to
generate the clock signals required by the FDC board The 4
MHz oscillator is implemented with two inverters (1 3 of U39)
and a quartz crystal (Y2) The output of the oscillator is inverted
and buffered by 1 6 of U39 to generate a TTL level square wave
signal U37 is a 4-bit binary counter which is divided into a divide-by-2 and a divide-by-8 section The divide-by-2 section is
used to generate the 2 MHz output at pin 12 The 2 MHz is
NANDed with 4MHz by 1 4 of U19 and the output is used to
clock the divide-by-8 section of U37 A 1 MHz clock is generated at pin 9 of U37 which is 90 phase-shifted from the 2 MHz
clock This phase relationship is used to gate the guaranteed
Write Data Pulse (WD) to the Write precompensation circuit
The 4 MHz is used to clock the digital data separator U18 and
the Write precompensation shift register U55 The 1 MHz clock
is used to drive the clock input of the FDC chip (U13) and the
clock input of the watchdog timer (U99)

Disk Bus Output Drivers
High current open collector drivers U20 and U56 are used to
buffer the output signals from the FDC circuit to the disk drives

Write Precompensation and Write Data Pulse Shaping Logic
The Write Precompensation logic is comprised of U55
(74LS195) 1 4 of U19 (74LSOO) 1 4 of U74 (74LS04) and
1 2 of U77 (74LS260) U55 is a parallel in serial out shift register and is clocked by 4 MHz which generates a precompensation value of 250 nsec The output signals EARLY and LATE
of the FDC chip (U13) are input to PO and P2 of the shift register A third signal is generated by 1 4 of U75 when neither
EARLY nor LATE is active low and is input to P1 of U55 WD of
the FDC chip is NANDed with 2 MHz to gate the guaranteed
Write Data Pulse to U55 for the parallel load signal SHFT LD
When U55 pin 9 is active low the signals preset at P1-P3 are
clocked in on the rising edge of the 4 MHz clock After U55 pin
9 goes high the data is shifted out at a 250 nsec rate EARLY
will generate a 250 nsec delay NOT EARLY AND NOT LATE
will generate a 500 nsec delay and LATE will generate a 750
nsec delay This provides the necessary precompensation for
the write data As mentioned previously Write Precompensation is enabled through software by an OUT to the Drive Select
Latch with bit 5 set This sets the Q output of the 74LS74 (U98
pin 9) which is ANDed with DDEN which disables the shift register U55 DDEN disables Write Precompensation in the single
density mode The resulting signal also enables U75 to allow
the write data (WD) to bypass the Write Precompensation circuit The Write Data (WD) pulse is shaped by a one-shot (1 2 of
U54) which stretches the data pulses to approximately 500
nsec

Hardware 96

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Clock and Read Data Recovery Logic

BRG Programming Table

The Clock and Read Data Recovery Logic is comprised of one
chip U18 (FDC9216) The FDC9216 is a Floppy Disk Data Separator (FDDS) which converts a single stream of pulses from
the disk drive into separate clock and data pulses for input to
the FDC chip The FDDS consists of a clock divider a long-term
timing corrector a short-time timing corrector and reclockmg
circuitry The reference clock (REFCLK) is a 4 MHz and is divided by the internal clock divider CDO and CD1 of the FDDS
chip control the divisor which divides REFCLK With DC1
grounded (logic low), CDO (when a logic low) generates a divide-by-1 for MFM mode and when logic high generates a divide-by-2 for FM mode CDO is controlled by the signal DDEN*
which is Double Density enable or MFM enable The FDDS detects the leading edges of RD* pulses and adjusts the phase of
the internal clock to generate the separated clock (SEPCLK) to
the FDC chip The separate long and short term timing correctors assure the clock separation to be accurate The separated
Data (SEPD*) is used as the ROD* input to the FDC chip

Floppy Disk Controller Chip
The 1793 is an MOS LSI device which performs the functions
of a floppy disk formatter/controller in a single chip implementation The following port addresses are assigned to the internal
registers of the 1793 FDC chip
Port No.
FOH
F1H
F2H
F3H

Function
Command Status Register
Track Register
Sector Register
Data Register

Nibble
Loaded
OH
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH

CH
DH
EH
FH

Transmit
Receive
Baud
Rate
50
75
110

1345
150
300
600

1200
1800
2000
2400
3600
4800
7200
9600
19200

16X

Clock
08kHz
1 2kHz
1 76 kHz
2 1523kHz
24kHz
48kHz
96kHz
192kHz
28 8 kHz
32 081 kHz
38 4 kHz
57 6 kHz
76 8 kHz
1152kHz
1536kHz
307 2 kHz

Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes

MM
Yes
Yes
Yes
Yes
Yes
Yes

The RS-232C circuit is port mapped and the ports used are E8
to EB Following is a description of each port on both input and
output
Port
E8

Input
Modem status

EA

UART status

3.1.16 RS-232-C Circuit

E9

Not Used

RS-232C Technical Description

EB

Receiver Holding
register

The RS-232C circuit for the Model 4P computer supports asynchronous serial transmissions and conforms to the EIA RS232C standards at the input-output interface connector (J4)
The heart of the circuit is the TR1865 Asynchronous Receiver
Transmitter U30 It performs the job of converting the parallel
byte data from the CPU to a serial data stream including start
stop, and parity bits For a more detailed description of how this
LSI circuit performs these functions refer to the TR1865 data
sheets and application notes The transmit and receive clock
rates that the TR1865 needs are supplied by the Baud Rate
Generator U52 (BR1941L) or (BR1943) This circuit takes the
5 0688 MHz supplied by the system timing circuit and the programmed information received from the CPU over the data bus
and divides the basic clock rate to provide two clocks The rates
available from the BRG go from 50 Baud to 19200 Baud See
the BRG table for the complete list

Supported
by
SETCOM

Output
Master Reset, enables UART
control register load
UART control register load and
modem control
Baud rate register load enable
bit
Transmitter Holding register

Interrupts are supported in the RS-232C circuit by the Interrupt
mask register (U92) and the Status register (U44) which allow
the CPU to see which kind of interrupt has occurred Interrupts
can be generated on receiver data register full, transmitter register empty, and any one of the errors — parity, framing, or data
overrun This allows a minimum of CPU overhead in transferring data to or from the UART The interrupt mask register is
port EO (write) and the interrupt status register is port EO (read)
Refer to the IO Port description for a full breakdown of all interrupts and their bit positions

Hardware 98

c

9

All Model I, III, and 4 software written for the RS-232-C interface
is compatible with the Model 4P RS-232-C circuit, provided the
software does not use the sense switches to configure the interface. The programmer can get around this problem by directly programming the BRG and UART for the desired
configuration or by using the SETCOM command of the disk
operating system to configure the interface . The TRS-80 RS232C Interface hardware manual has a good discussion of the
RS-232C standard and specific programming examples (Catalog Number 26-1145).

Pinout Listing
The following list is a pinout description of the DB-25 connector
(P1).
Pin No.
Signal
1
PGND (Protective Ground)
2
TD (Transmit Data)
3
RD (Receive Data)
4
RTS (Request to Send)
5
CTS (Clear To Send)
6
DSR (Data Set Ready)
7
SGND (Signal Ground)
8
CD (Carrier Detect)
19
SRTS (Spare Request to Send)
20
DTR (Data Terminal Ready)
22
Rl (Ring Indicate)

J

Hardware 99

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»
SECTION IV

4P GATE ARRAY THEORY OF OPERATION

^

Hardware 101

4.2 MODEL 4P GATE A R R A Y THEORY OF
OPERATION
4.2.1 Introduction
Contained in the following paragraphs is a description of the
component parts of the Model 4P CPU Gate Array It is divided
into the logical operational functions of the computer All components are located on the Mam CPU board inside the case
housing Refer to Section 3 for disassembly assembly
procedures

4.2.2 Reset Circuit
The Model 4P reset circuit provides the neccessary reset
pulses to all circuits during power up and reset operations R25
and C214 provide a time constant which holds the input of U121
low during power-up This allows power to be stable to all circuits before the RESET* and RESET signals are applied When
C214 charges to a logic high, the output of U121 triggers the
input of a retnggerable one-shot multivibrator (U1) U1 outputs
a pulse with an approximate width of 70 microsecs When the
reset switch is pressed on the front panel, this discharges C214
and holds the input of U121 low until the switch is released On
release of the switch, C214 again charges up triggering U121
and U1 to reset the microcomputer Another signal POWRST*
is generated to clear drive select circuit immediately when
reset switch is pressed

4.2.3 CPU
The central processing unit (CPU) of the Model 4P microcomputer is a Z80A microprocessor The Z80A is capable of running in either 2 MHz or 4 MHz mode The CPU controls all
functions of the microcomputer through use of its address lines
(AO-A15), data lines (DO-D7), and control lines (/M1, IOREQ
RD, WR, /MREQ, and /RFSH) The address lines (AO-A15)
are buffered to other ICs through two 74LS244S (U67 and U27)
which are enabled all the time with their enables pulled to GND
The control lines are buffered to other ICs through a 74F04
(U87) The data lines (DO-D7) are buffered through a bi-directional 74LS245 (U86) which is enabled by BUSEN* and the direction is controlled by BUSDIR*

fed to the CPU U45 PCLK is generated as a symmetrical
clock and is never allowed to be short cycled (eg ) Not allowed to g e n e r a t e a low or high pulse under 110
nanoseconds

4.2.4.1 Video Timing
The video timing is also generated by U148 with the help of a
PLL Multiplier Module (PMM) U146 These two ICs generate all
the necessary timing signals for the four video modes 64 x 16,
3 2 x 1 6 8 0 x 2 4 and 40x24 Two reference clocks are required
for the four video modes One reference clock is 10 1376 MHz
It is generated internally to U148, and is used by the 64 x 16 and
32 x 16 modes The second reference clock is a 12 672 MHz
(12M) clock which is generated by the PMM U146 12M clock
is used by the 80 x 24 and 40 x 24 modes A 1 2672 MHz
(1 2M16) signal is output from pm 3 of U148 and is generated
from the master reference clock, the 20 2752 MHz crystal
1 2M16 is used for a reference clock for the PMM The PMM is
internally set to oscillate at 12 672 MHz which is output as 12M
U148 divides 12M by 10 to generate a second 1 2672 MHz
clock (1 2M10) which is fed into pm 5 of U146 (PMM) The two
1 2672 MHz signals are internally compared in the PMM where
it corrects the 12 672 MHz output so it is synchronized with the
20 2752 MHz clock
MODSEL and 8064* signals are used to select the desired
video mode 8064* controls which reference clock is used by
U127 and MODSEL controls the single or double character
width mode Refer to the following chart for selecting each
video mode

8064*
0
0

1
1

MODSEL
0
1
0

1

Video Mode
64 x 16
32 x 16
80x24
40x24

*This is the state to be written to latch U85 Signal is inverted
before being input to U148

4.2.4 System Timing
The mam timing reference of the microcomputer, with the
exception of the FDC circuit, is generated by a Gate Array
U148 and a 202752 MHz Crystal This reference is internally divided in the Gate Array to generate all necessary timing for the CPU, video circuit, and RS-232-C circuit The
CPU clock is generated U148 which can be either 2 or
4MHz depending on the logic state of FAST input (pin 6 of
U148) If FAST is a logic low, the U148 generates a 2 02752
MHz clock If FAST is a logic high U148 generates a
4 05504 MHz signal PCLK (pm 23 of U148) is filtered
through a fernte bead (FB2) and 22(1 Resistor (R9) and then

Hardware 103

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The keyboard scanner checks for several different groups of
keys. These are shown below:
Function Group

Selection Group




<1>
<2>
<3>





A
B
C
D
E
F
G

Special Keys




Misc Keys



The Selection group keys are used in determining which file will
be read from disk when the ROM-image is loaded. For details
of this operation, see the Disk Directory Searcher. If more than
one of the Selection group keys are pressed, the last one detected will be the one that is used.
The Miscellaneous keys are:
< Break >

When any key in the Function Group is pressed, it is recorded
in RAM and will be used by the Control routine in directing the
action of the boot. If more than one of these keys are pressed
during the keyboard scan, the last one detected will be the one
that is used. The Function group keys are currently defined as:
 or <1>
 or <2>
 or <3>





Instructs the Control routine to
load the Model III ROM-image,
even if it is already loaded This
is useful if the ROM-image has
been corrupted or when switching ROM-images. (Note that
this will not cause the ROMimage to be loaded if the boot
sector check indicates that the
Model III ROM image is not
needed. Press • F3 or • F3 •
and • L • to accomplish that.

Will cause hard disk boot
Will cause floppy disk boot
Will force Model III mode
Reserved for future use
Boot from RS-232 port
Reserved for future use
Reserved for future use



Pressing this key is simply recorded by setting location
405BH non-zero. It is up to an
operating system to use this
flag if desired.
Terminates the Keyboard routine. Any other keys pressed up
to that time will be acted upon.
 is useful for experienced users who do not want to
wait until the keyboard timer
expires.

The Control section now takes over and follows the following
flowchart.

o

The Special keys are commands to the Control routine which
direct handling of the Model III ROM-image. Each key is detected individually.




When loading the Model III
ROM-image, the user will be
prompted when the disks can
be switched or when ROM
BASIC can be entered by
pressing .
Instructs the Control routine to
not load the Model III ROMimage, even if it appears that
the operating system being
booted requires it.

9
Hardware 108

Beg i n

Goto (1]
(Hard Disk Boot)

Goto [2]
(Floppy Disk Boot)

Goto [ 3]
o x
O ) (Model III Boot)

4 AJ
No

Goto [ 4 ]
(RS-232 Boot)

At this point, no valid Function keys
have been pressed.

Display an error
message. (ARCNET
Boot ROM required
for ARCNET Boot)

Hardware 109

Display
Floppy Disk
Error
Message

No
(

Stop

J

Write-enable
0-37FFH
(Mode 1)
Note: 1

\/

o

Load ROM
Image
Note: 5
Set Transfer
Address to
4300H
Note: 2

Set Transfer
Address at end
of ROM Image
(Normally 3015H)
Note: 2
(

^-

Hardware 110

Stop

J

^

Switch boot ROM
out of Memory

Jump to
Transfer Address

>
Display
"ROM Image
is loaded"
message

Initialize
RS-232 Port
Note: 6

Wait for
 or
 to
be pressed

Wait for
Carrier Detect

t*
( 1 Hi

Load program
from RS-232

(2) If you are loading a Model 4 operating system then the
boot ROM will always transfer control to the first byte of the
boot sector, which is at 4300H If you are loading a Model
III operating system or about to use Model III ROM BASIC
then the transfer address is 3015H This is the address of
a jump vector in the C ROM of the Model III ROM image
and this will cause the system to behave exactly like a
Model III If the ROM image file that is loaded has a different transfer address then that address will be used when
loading is complete If the image is already present, the
Boot ROM will use 3015H

D isplay and
t ransnit error

Transfer
control
to address
received

(3) Two different tests are done to insure that the Model III
ROM image is present The first test is to check every third
location starting at 3000H for a C3H This is done for 10 locations If any of these locations does not contain a C3H
then the ROM image is considered to be not present
The next test is to check two bytes at location OOOBH If
these addresses contain E9E1H then the ROM image is
considered to be present

Notes:

(4) See Disk Director Searcher for more information

(1) If the boot sector was not 256 bytes in length then it is assumed to be a Model III package and the ROM image will
be needed If the sector is 256 bytes in length then the
sector is scanned for the sequence CDxxOOH The CD is
the first byte of a Z80 unconditional subroutine call The
next byte can have any value The third byte is tested
against a zero What this check does is test for any references to the first 256 bytes of memory All Radio Shack
Model III operating systems and many other packages all
reference the ROM at some point during the boot sector
Most boot sectors will display a message if the system cannot be loaded To save space these routines use the
Model III ROM calls to display the message Several ROM
calls have their entry points in the first 256 bytes of memory and these references are detected by the boot ROM

(5) See File Loader for more information
(6) The RS-232 loader is described under RS-232 Boot
Disk Directory Searcher
When the Model III ROM image is to be loaded it is always read
from the floppy in drive 0
Before the operation begins, some checks are made First the
boot sector is read in from the floppy and the first byte is
checked to make sure it is either a OOH or a FEH If the byte
contains some other value no attempt will be made to read the
ROM image from that disk The location of the directory cylinder
is then taken from the boot sector and the type of disk is determined This is done by examining the Data Address Mark that

Hardware 112

o

was picked up by the Floppy Disk Controller (FDC) during the
read of the sector If the DAM equals 1 the disk is a TRSDOS
1 x style disk If the DAM equals 0 then the disk is a LDOS 5 1
TRSDOS 6 style disk This is important since TRSDOS 1 x
disks number sectors starting with 1 and LDOS style disks
number sectors starting with 0
Once the disk type has been determined an extra test is made
if the disk is a LDOS style disk This test reads the Granule Al
location Table (GAT) to determine if the disk is single sided or
double sided
The directory is then read one record at a time and a compare
is made against the pattern MODEL°o
for the filename and
III for the extension The °0 means that any character will
match this position If the user pressed one of the selection
keys (A G) during the keyboard scan then that character is
substituted in place of the % character For example if you
pressed D then the search would be for the file MODELD
with the extension III The searching algorithm searches until
it finds the entry or it reaches the end of the directory
Once the entry has been found the extent information for that
file is copied into a control block for later use
File Loader
The file loader is actually two modules — the actual loader and
a set of routines to fetch bytes from the file on disk The loader
is invoked via a RST 28H The byte fetcher is called by the
loader using RST 20H Since restart vectors can be re directed
the same loader is used by the RS 232 boot The difference is
that the RST 20H is redirected to point to the RS 232 data re
ceivmg routine The loader reads standard loader records and
acts upon two types
01

Data Load
1 byte with length of block including address
1 word with address to load the data
n bytes of data where n + 2 equals the length specified

02

Transfer Address
1 byte with the value of 02
1 word with the address to start execution at

Floppy and Hard Disk Driver
The disk drivers are entered via RST 8H and will read a sector
anywhere on a floppy disk and anywhere on head 1 (top head)
in a hard disk drive Either 256 or 512 byte sectors are readable
by these routines and they make the determination of the sector
size The hard disk driver is compatible with both the WD1000
and the WD1010 controllers The floppy disk driver is written for
the WD1793 controller
Serial Loader
Invoking the serial loader is similar to forcing a boot from hard
disk or floppy In this case the right shift key must be pressed at
some time during the first three seconds after reset The pro
gram does not care if the key is pressed forever making it con
venient to connect pins 8 and 10 of the keyboard connector with
a shorting plug for bench testing of boards This assumes that
the object program being loaded does not care about the key
closure
Upon entry the program first asserts DTR (J4 pin 20) and RTS
(J4 pin 4) true Next Not Ready is printed on the topmost line
of the video display Modem status line CD (J4 pin 8) is then
sampled The program loops until it finds CD asserted true At
that time the message Ready is displayed Then the program
sets about determining the baud rate from the host computer
To determine the baud rate the program compares data re
ceived by the UART to a test byte equal to 55 hex The receiver
is first set to 19200 baud If ten bytes are received which are not
equal to the test byte the baud rate is reduced This sequence
is repeated until a valid test byte is received If ten failures occur
at 50 baud the entire process begins again at 19200 baud If a
valid test byte is received the program waits for ten more to ar
rive before concluding that it has determined the correct baud
rate If at this time an improper byte is received or a receiver er
ror (overrun framing or parity) is intercepted the task begins
again at 19200 baud
In order to get to this point the host or the modem must assert
CD true The host must transmit a sequence of test bytes equal
to 55 hex with 8 data bits odd parity and 1 or 2 stop bits The
test bytes should be separated by approximately 0 1 second to
avoid overrun errors

Any other loader code is treated as a comment block and is ig
nored Once an 02 record has been found the loader stops
reading even if there is additional data so be sure to place the
02 record at the end of the file

When the program has determined the baud rate the message
Found Baud Rate x
is displayed on the screen where x is a letter from A to P
meaning
A
B
C
D

=
=
-

50 baud
75
110
134 5

Hardware 113

E - 150
F = 300
G - 600
H - 1200

I = 1800
J = 2000
K = 2400
L = 3600

M - 4800
N = 7200
O - 9600
P - 19200

(Since the file represents Z80 machine code and all 256
combinations are meaningful it would be disastrous to
transmit nulls or other ASCII control codes as fillers acknowledgement or start stop bytes The only control
codes needed are the standard command file control
bytes )

The same message less the character signifying the baud rate
is transmitted to the host with the same baud rate and protocol
This message is the signal to the host to stop transmitting test
bytes
After the program has transmitted the baud rate message it
reads from the DART data register in order to clear any overrun
error that may have occurred due to the test bytes coming in
during the transmission of the message This is because the re
ceiver must be made ready to receive a sync byte signalling the
beginning of the command file For this reason it is important
that the host wait until the entire baud rate message (16 char
acters) is received before transmitting the sync byte which is
equal to FF hex
When the loader receives the sync byte the message
Loading
is displayed on the screen Again the same message is trans
mitted to the host and again the host must wait for the entire
transmission before starting into the command file
If the receiver should intercept a receive error while waiting for
the sync byte the entire operation up to this point is aborted
The video display is cleared and the message
Error x
is displayed near the bottom of the screen where x is a letter
from B to H meaning
B
C
D
E
F
G
H

=
=
=
=
=
=
=

parity error
framing error
parity & framing errors
overrun error
parity & overrun errors
framing & overrun errors
parity & framing & overrun errors

Data can be transmitted to the loader at 19200 baud with no delays inserted Two stop bits are recommended at high baud
rates
See the File Loader description for more information on file
loading
If a receive error should occur during file loading the abort procedure described above will take place so when attempting remote control it is wise to monitor the host receiver during
transmission of the file When the host is near the object board,
as is the case in the factory application or when more than one
board is being loaded it may be advantageous or even necessary to ignore the transmitted responses of the object
board(s) and to manually pace the test byte sync byte and
command file phases of the transmission process using the
video display for handshaking
System Programmers Information
The Model 4P Boot ROM uses two areas of RAM while it is running These are 4000H to 40FFH and 4300H to 43FFH (For
512 byte boot sectors the second area is 4300H to 44FFH ) If
the Model III ROM Image is loaded additional areas are used
See the technical reference manual for the system you are using for a list of these areas
Operating systems that want to support a software restart by reexecuting the contents of the boot ROM can accomplish this in
one of two ways If the operating system relies on the Model III
ROM Image then jump to location 0 as you have in the past If
the operating system is a Model 4 mode package a simple way
is to code the following instructions in your assembly and load
them before you want to reset

The message

Absolute Location
0000
0001
0003

Error
is then transmitted to the host The entire process is then re
peated from the Not Ready message A six second delay is
inserted before reinitialization This is longer than the time re
quired to transmit five bytes at 50 baud so there is no need to
be extra careful here
If the sync byte is received without error then the Loading
message is transmitted and the program is ready to receive the
command file After receiving the Loading message the host
can transmit the file without nulls or delays between bytes

Instruction
Dl
LD
A1
OUT
(9CH) A

These instructions cause the boot ROM to become addressable After executing the OUT instruction the next instruction
executed will be one in the boot ROM (These instructions also
exist in the Model III ROM image at location 0 ) The boot ROM
has been written so that the first instruction is at address 0005
The hardware must be in memory mode 0 or 1, or else the
boot ROM will not be switched in This operation can be
done with an OUT instruction and then a RST 0 can be executed to have the ROM switched in

Hardware 114

o

Restarts can be redirected at any time while the ROM is
switched in All restarts jump to fixed locations in RAM and
these areas may be changed to point to the routine that is to be
executed
Restart

RAM Location

none
4000H
4003H
4006H
4009H
400CH
400FH
401 2H
401 5H

0
8
10
18
20
28
30
38
66

Default Use
Cold Start Boot
Disk I O Request
Display string
Display block
Byte Fetch (Called by Loader)
File Loader
Keyboard scanner
Reserved for future use
NMI (Floppy I'O Command
Complete)

Display String (RST 10H)
Accepts
HL

DE

Returns
Success Always
A
DE
HL

Pointer to text to be displayed
Text must be terminated with a null (0)
Offset position on screen where text is to
be displayed
(A OOOOH will be the upper left-hand corner of the display )

Altered
Points to next position on video
Points to the null (0)

Display Block (RST 18H)
The above routines have fixed entry parameters These are described here

Accepts
HL

Disk I/O Request (RST 8H)
Accepts
A
B

DE
HL

Returns
Z
HZ
Error Codes
3
4
5
6
7

8

9
11

12

1 for floppy, 2 for hard disk
Command
1
Initialize
4
Restore
Seek
6
12 (All reads have an imRead
plied seek)
Sector number to read
The contents of the location disktype
(405CH) are added to this value before
an actual read If the disk is a two sided
floppy, just add 18 to the sector number
Cylinder number (Only E is used in
floppy operations)
Address where data from a read operation is to be stored

Points to control vector in the format
+0
Screen Offset
+2
Pointer to text, terminated with
null
+4
Pointer to text, terminated with
null
+n

word FFFFH

End of control
vector
Of
+n
word FFFEH
Next word is
new Screen
Offset
If Z flag is set on entry then the first screen offset is read from
DE instead of from the control vector
Each string is positioned after the previous string, unless a
FFFEH entry is found This is used heavily in the ROM to reduce duplication of words in error messages
Returns
Success Always
DE

Points to next position on video

Byte Fetch (RST 20H)

Success, Operation Completed
Error, Error code in A

Accepts None
Returns
Hard Disk drive is not ready
Floppy disk drive is not ready
Hard Disk drive is not available
Floppy disk drive is not available
Drive Not Ready and no Index (Disk in
drive, door open)
CRC Error
Seek Error
Lost Data
ID Not Found

Z
NZ

Success, byte in A
Failure, error code in A

Errors

2
10

Hardware 115

Any errors from the disk I;O call and
ROM Image can't be loaded — Too many
extents
ROM Image can't be loaded — Disk drive
is not ready

File Loader (RST 28H)
Accepts None
Returns
Z
NZ

Success
Failure, error code in A

Errors

0

Any errors from the disk I/O call or the
byte fetch call and:
The ROM image was not found on drive 0

There are several pieces of information left in memory by the
boot ROM which are useful to system programmers. These are
shown below:
RAM Location
401DH
4055H

4056H
4057H
4059H

405BH
405CH

Description
ROM Image Selected (% for none
selected or A-G)
Boot type
1 = Floppy
2 = Hard disk
3 = ARCNET
4 - RS-232C
5 - 7 = Reserved
Boot Sector Size (1 for 256, 2 for 512)
RS-232 Baud Rate (only valid on RS232 boot)
Function Key Selected
0 = No function key selected
or<1>
86
 or <2>
87
 or <3>
88

85

84

82

83
Reserved
80-81 and 89-90
Break Key Indication (non-zero if
 pressed)
Disk type
(0 for LDOS/
TRSDOS6.1 for
TRSDOS1.X)

The DRAMs require multiplexed incoming address lines. This
is accomplished by ICs U110 and U111 which are 74LS157
multiplexers. Data to and from the DRAMs are buffered by a
74LS245 (U118) which is controlled by Gate Array 4.2 (U106).
The proper timing signals RASO*. RAS1 *, MUX*. and CAS* are
generated by a delay line circuit U94. U116 (1 2 of a 74S112)
and U117 (1 4 of a 74F08) are used to generate a precharge
circuit. During M1 cycles of the Z80A in 4 MHz mode, the high
time in MREQ has a minimum time of 110 nanosecs. The specification of 6665 DRAM requires a minimum of 120 nanosecs so
this circuit will shorten the MREQ signal during the M1 cycle.
The resulting signal PMREQ is used to start a RAM memory
cycle through U114 (a 74S64). Each different cycle is controlled
at U114 to maintain a fast M1 cycle so no wait states are required. The output of U114 (PRAS*) is ANDed with RFSH to not
allow MUX* and CAS* to be generated during a REFRESH
cycle. PRAS* also generates either RASO* or RASV, depending on which bank of RAM the CPU is selecting. GCAS* generated by the delay line U94 is latched by U116 (1 2 of a
74S112) and held to the end of the memory cycle. The output
of U116 is ANDed with VIDEO signal to disable the CAS* signal
from occurring if the cycle is a video memory access. Refer to
M1 Cycle Timing (Figure 4-7 and 4-8), Memory Read and
Memory Write Cycle Timing (Figure 4-9) and (Figure 4-10).

Keep in mind that Model III ROM image will initialize these
areas, so this information is useful only to the Model 4 mode
programmer.

4.2.7 RAM
Two configurations of Random Access Memory (RAM) are
available on the Model 4P: 64K and 128K. The 64K and 128K
option use the 6665-type 64K x 1 200NS Dynamic RAM, which
requires only a single + 5v supply voltage.

Hardware 116

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RAO-RA3, row addresses from the CRTC are used to control
which scan line is being displayed The Model 4P has a 4-bit full
adder 74LS283 (U101) to modify the Row address During a
character display DLYGRAPHIC* is high which applies a high to
all 4 bits to be added to row address This will result in subtract
ing one from Row address count and allow all characters to be
displayed one scan line lower The purpose is so inverse characters will appear within the inverse block When a graphic
block is displayed DLYGRAPHIC* is low which causes the row
address to be unmodified Moving jumper from E14-E15 to
E15-E16 will disable this circuit
DLYCHAR* and DLYGRAPHICS are inverse signals and control
which data is to be loaded into the internal shift register of U102
When DLYCHAR* is low and DLYGRAPHIC* is high, the Character Generator ROM (U103) is enabled to output data When
DLYCHAR* is high and DLYGRAPHIC* is low the graphics characters are internally buffered to the shift register The data is
loaded into the internal shift register on the rising edge of
SHIFT* when LOADS* is low Serial video data is output
U102 19 The video information is inverted by U142 and F83, is
filtered by R14 (47 ohm resistor), and C227 (100 pf Cap) and
output to video monitor VSYNC and HSYNC are buffered by (1>
2 of 74LS86) U143 and are also output to video monitor Refer
to Video Circuit Timing Figure 4-12 and Inverse Video Timing Figure 4-13 for timing relationships of Video Circuit

4.2.9 Keyboard
The keyboard interface of the Model 4P consists of open collector drivers which drive an 8 by 8 key matrix keyboard and an
inverting buffer which buffers the key or keys pressed on the
data bus The open collector drivers (U57 and U77 (7416) are
driven by address lines AO-A7 which drive the column lines of
the keyboard matrix The ROW lines of the keyboard are pulled
up by a 1 5 kohm resistor pack RP2 The ROW lines are buffered and inverted onto the data bus by U78 (74LS240) which is
enabled when KEYBD* is a logic low KEYBD* is a memory
mapped decode of addresses 3800-3BFF in Model III Mode
and F400-F7FF in Model 4/4P mode Refer to the Memory Map
under Address Decode for more information During real time
operation, the CPU will scan the keyboard periodically to check
if any keys are pressed If no key is pressed, the resistor pack
RP2 keeps the inputs of U78 at a logic high U78 inverts the
data to a logic low and buffers it to the data bus which is read
by the CPU If a key is pressed when the CPU scans the correct
column line, the key pressed will pull the corresponding row to
a logic low U78 inverts the signal to a logic high which is read
by the CPU

4.2.10 Real Time Clock
The Real Time Clock circuit in the Model 4P provides a 30 Hz
(in the 2 MHz CPU mode) or 60 Hz (in the 4 MHz CPU mode)
interrupt to the CPU By counting the number of interrupts that
have occurred the CPU can keep track of the time The 60 Hz
vertical sync signal (VSYNC) from the video circuitry is used for
the Real Time Clock s reference In the 2 MHz mode, FAST is
a logic low which sets the Preset input pin 4 of U23 (74LS74)
to a logic high This allows the 60 Hz (VSYNC) to be divided by
2 to 30 Hz The output of 1/2 of U23 is ORed with the original
60 Hz and then clocks another 74LS74 (1 2 of U23) If the real
time clock is enabled (ENRTC at a logic high), the interrupt is
latched and pulls the INT* line low to the CPU When the CPU
recognizes the interrupt, the pulse is counted and the latch reset by pulling RTCIN* low In the 4 MHz mode, FAST is a logic
high which keeps the first half of U23 in a preset state (the Q*
output at a logic low) The 60 Hz is used to clock the interrupts
NOTE: If interrupts are disabled, the accuracy of the real
time clock will suffer

4.2.11 Line Printer Port
The Line Printer Port Interface consists of a pulse generator, an
eight-bit latch, and a status line buffer The status of the line
printer is read by the CPU by enabling buffer U3 (74LS244)
This buffer is enabled by LPRD* which is a memory map and
port map decode In Model III mode, only the status can be read
from memory location 37E8 or 37E9 The status can be read in
all modes by an input from ports F8-FB For & listing of the bit
status, refer to Port Map section
After the printer driver software determines that the printer is
ready for printing (by reading the correct status) the characters
to be printed are output to Port F8-FB U2, a 74LS374 eight-bit
latch, latches the character byte and outputs to the line printer
One-half of U1 (74LS123), a one-shot, is then triggered which
generates an appropriate strobe signal to the printer which signifies a valid character is ready The output of the one-shot is
buffered by 1/6th of the U51 (74LS04) to prevent noise from the
printer cable from false-triggering the one-shot

Hardware 132

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4.2.12 Graphics Port

Addresses

The Graphics Port (J7) on the Model 4P is provided to attach
the optional Graphics Board The port provides DO-D7 (Data
Lines) AO-A3 (Address Lines) IN* GEN* and RESET* for the
necessary interface signals for the Graphics Board GEN* is
generated by negative ORmg Port selects GSELO* (8C-8FH)
and GSELI* (80-83H) together by (1 4 of 74LS08) U4 The re
suiting signal is negative ANDed with IORQ* by (1 4 of 74S32)
U24 Seven timing signals are provided to allow synchronization of Mam Logic Board Video and Graphics Board Video
These timing signals are VSYNC, HSYNC, DISPEN, DCLK,
H, I, and J Three control signals from the Graphics Board
are used to sync to CPU access and select different video
modes WAIT* controls the CPU access by causing the CPU
to WAIT till video is in retrace area before allowing any
writes or reads to Graphics Board RAM ENGRAF is asserted when Graphics video is displayed ENGRAF also disables inverse video mode on Mam Logic Board Video
CL166* (Clear 74L166) is used to enable or disable mixing
of Mam Logic Board Video and Graphics Board Video If
CL166* is negated high, then mixing is allowed in all four
video modes 80 x 24, 40 x 24, 64 x 16, and 32 x 16 If
CL166* is asserted low, this will clear the video shift register
U63, which allows no video from the Mam Logic Board In
this state 8064* is automatically asserted low to put screen
in 80 x 24 video mode Refer to Figure 4-15 Graphic Board
Video Timing for timing relationships Refer to the Model 4/
4P Graphics Board Service information for service or technical information on the Graphics Board

4.2.13 Sound
The sound circuit in the Model 4P is compatible with the Sound
Board which was optional in the Model 4 Sound is generated
by alternately setting and clearing data bit DO during an OUT to
port 90H The state of DO is latched by U129 (1 2 of a 74LS74)
and the output is amplified by Q2 which drives a 811 speaker
The speed of the software loop determines the frequency and
thus, the pitch of the resulting tone Since the Model 4P does
not have a cassette circuit, some existing software that used
the cassette output for sound would have been lost The Model
4P routes the cassette latch to the sound board through U109
When the CASSMOTORON signal is a logic low the cassette
motor is off, then the cassette output is sent to the sound circuit

4.2.14 I/O Bus Port
The Model 4P Bus is designed to allow easy and convenient in
terracing of I O devices to the Model 4P The I O Bus supports
all the signals necessary to implement a device compatible with
the Z80s I O structure

AO to A7 allow selection of up to 256* input and 256 output
devices if external I O is enabled
*Ports 80H to OFFH are reserved for System use
Data
DBO to DB7 allow transfer of 8-bit data onto the processor
data bus is external I'O is enabled
Control Lines
1

M1* — Z80A signal specifying an M1 or Operation Code
Fetch Cycle or with IOREQ* it specifies an Interrupt
acknowledge

2

IN* — Z80A signal specifying than an input is in progress
Logic AND of IOREQ* and WR*

3

OUT* — Z80A signal specifying that an output is in progress Logic AND of IOREQ* and WR*

4

IOREQ* — Z80A signal specifying that an input or output
is in progress or with M1* it specifies an interrupt
acknowledge

5

RESET* — system reset signal

6

IOBUSINT* — input to the CPU signaling an interrupt from
an I O Bus device if I O Bus interrupts are enabled

7

IOBUSWAIT* — input to the CPU wait line allowing I O Bus
device to force wait states on the Z80 if external I O is
enabled

8

EXTIOSEL* — input to I O Bus Port circuit which switches
the I O Bus data bus transceiver and allows and INPUT instruction to read I O Bus data

The address line data line and all control lines except RESET*
are enabled only when the ENEXIO bit in port EC is set to one
To enable I O interrupts the ENIOBUSINT bit in the PORT EO
(output port) must be a one However even if it is disabled from
generating interrupts the status of the IOBUSINT* line can still
read on the appropriate bit of CPU IOPORT EO (input port)
See Model 4P Port Bit assignments for port OFF OEC andOEO

Hardware 136

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The Model 4P CPU board is fully protected from foreign I O devices in that all the I O Bus signals are buffered and can be disabled under software control To attach and use and I O device
on the I O Bus certain requirements (both hardware and software) must be met
For input port device use, you must enable external I/O devices by writing to port OECH with bit 4 on in the user software This will enable the data bus address lines and control
signals to the I/O Bus edge connector When the input device is selected, the hardware should acknowledge by asserting EXTIOSEL* low This switches the data bus
transceiver and allows the CPU to read the contents of the I/
O Bus data lines See Figure 4-16 for the timing EXTIOSEL* can be generated by NANDmg IN and the I/O port
address
Output port device use is the same as the input port device in
use, in that the external I O devices must be enabled by writing
to port OECH with bit 4 on in the user software — in the same
fashion
For either input or output devices, the IOBUSWAIT* control line
can be used in the normal way for synchronizing slow devices
to the CPU Note that since dynamic memories are used in the
Model 4P, the wait line should be used with caution Holding the
CPU in a wait state for 2 msec or more may cause loss of memory contents since refresh is inhibited during this time It is recommended that the IOBUSWAIT* line be held active no more
than 500 fxsec with a 25% duty cycle
The Model 4P will support Z80 Mode 1 interrupts A RAM jump
table is supported by the LEVEL II BASIC ROMs image and the
user must supply the address of his interrupt service routine by
writing this address to locations 403E and 403F When an interrupt occurs, the program will be vectored to the user-supplied address if I/O Bus interrupts have been enabled To
enable I/O Bus interrupts, the user must set bit 3 of Port OEOH

4.2.15 FDC Circuit
The TRS-80 Model 4P Floppy Disk Interface provices a standard 5-1 4 floppy disk controller The Floppy Disk Interface
supports both single and double density encoding schemes
Write precompensation can be software enabled or disabled
beginning at any track, although the system software enables
write precompensation for all tracks greater than twenty-one
The amount of write precompensation is 125 nsec and is not
adjustable One or two drives may be controlled by the interface All data transfers are accomplished by CPU data requests In double density operation, data transfers are
synchronized to the CPU by forcing a wait to the CPU and clearing the wait by a data request from the FDC chip The end of the
data transfer is indicated by generation of a non-maskable interrupt from the interrupt request output of the FDC chip A
hardware watchdog timer insures that any error condition will
not hang the wait line to the CPU for a period long enough to
destroy RAM contents

Hardware 138

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Hardware 139

Control and Data Buffering

*Only one of these bits should be set per output

The Floppy Disk Controller Board is an I O port mapped device
which utilizes ports E4H FOH F1H F2H F3H and F4H The
decoding logic is implemented on the CPU board (Refer to Paragraph 5 1 5 Address Decoding for more information on Port
Map) U70 is a bi-d'rectional 8-bit transceiver used to buffer
data to and from the FDC and RS-232 circuits The direction of
data transfer is controlled by the combination of control signals
DISKIIST RS232IN* RDINT* and RDNMI* If any of these signals is active (logic low) U70 is enabled to drive data onto the
CPU data bus If both signals are inactive (logic high) U70 is"
enabled to receive data from the CPU board data bus A second buffer (U36) is used to buffer the FDC chip data to the FDC
RS232 Data Bus (BDO-BD7) U36 is enabled all the time and
its direction controlled by DISKIN* Again if DISKIN* is active
(logic low), data is enabled to drive from the FDC chip to the
Mam Data Busses If DISKIN* is inactive (logic high) data is enabled to be transferred to the FDC chip

Hex D flip-flop U54 (74L174) latches the drive select bits side
select and FM* MFM bits on the rising edge of the control signal
DRVSEL* Gate Array 4 4 (U18) is used to latch the Wait Enable and Write precompensation enable bits on the rising edge
of DRVSEL* The rising edge of DRVSEL* also triggers a oneshot (1 2 of U54 74LS123) which produces a Motor On to the
disk drives The duration of the Motor On signal is approximately three seconds The spindle motors are not designed for
continuous operation Therefore the inactive state of the Motor
On signal is used to clear the Drive Select Latch which de-selects any drives which were previously selected The Motor On
one-shot is retriggerable by simply executing another OUT instruction to the Drive Select Latch

Nonmaskable Interrupt Logic
Gate Array 4 4 (U18) is used to latch data bits D6 and D7 on the
rising edge of the control signal WRNMI* This enables the conditions which will generate a non-maskable interrupt to the
CPU The NMI interrupt conditions which are programmed by
doing an OUT instruction to port E4H with the appropriate bits
set If data bit 7 is set an FDC interrupt is enabled to generate
an NM! interrupt If data bit 7 is reset interrupt requests request
from the FDC are disabled If data bit 6 is set a Motor Time Out
is enabled to generate an NMI interrupt If data bit 6 is reset, interrupts on Motor Time Out are disabled An IN instruction from
port E4H enables the CPU to determine the source of the nonmaskable interrupt Data bit 7 indicates the status of FDC interrupt request (INTRO) (0 = true, 1 = false) Data bit 6 indicates
the status of Motor Time Out (0 = true, 1 - false) Data bit 5 indicates the status of the Reset signal (0 = true 1 = false) The
control signal RDNMI* gates this status onto the CPU data bus
when active (logic low)

Wait State Generation and WAITIMOUT Logic
As previously mentioned, a wait state to the CPU can be initiated by an OUT to the Drive Select Latch with D6 set Pin 18 of
U18 will go high after this operation This signal is inverted by
1 /4th of U15 and is routed to the CPU where it forces the Z80A
into a wait state The Z80A will remain in the wait state as long
as WAIT* is low Once initiated, the WAIT* will remain low until
one of five conditions is satisfied If INTRO, DRQ and RESET,
inputs become active (logic high) it causes WAIT* to go high
which allows the Z80 to exit the wait state An internal timer in
U18 serves as a watchdog timer to insure that a wait condition
will not persist long enough to destroy dynamic RAM contents
This internal watchdog timer logic will limit the duration of a wait
to 1024|jLsec, even if the FDC chip should fail to generate a
DRQ or an INTRO
If an OUT to Drive Select Latch is initiated with D6 reset (logic
low), a WAIT is still generated The internal timer in U18 will
count to 2 which will clear the WAIT state This allows the WAIT
to occur only during the OUT instruction to prevent violating any
Dynamic RAM parameters
NOTE: This automatic WAIT will cause a 5-1 fxsec wait each
time an out to Drive Select Latch is performed

Drive Select Latch and Motor ON Logic
Selecting a drive prior to disk I O operation is accomplished by
doing an OUT instruction to port F4H with the proper bit set The
following table describes the bit allocation of the Drive Select
Latch
Data Bit
DO
D1
D2
D3
D4
D5
D6
D7

Function
Selects Drive 0 when set*
Selects Drive 1 when set*
Selects Drive 2 when set*
Selects Drive 3 when set*
Selects Side 0 when reset
Selects Side 1 when set
Write precompensation enabled when set,
disabled when reset
Generates WAIT if set
Selects MFM mode if set
Selects FM mode if reset

Hardware 140

o

Clock Generation Logic
A 16 MHz crystal oscillator and a Gate Array 4.4 (U18) are used
to generate the clock signals required by the FDC board. The 6
MHz oscillator is implemented internal to U18 and a quartz
crystal (Y2). The output of the oscillator is divided by 2 to generate an 8 MHz clock. This is used by the FDC 1773 for all internal timing and data separation. U18 further divides the 16
MHz clock to drive the watchdog timer circuit.

Disk Bus Output Drivers
High current open collector drivers U15 and U34 are used to
buffer the output signals from the FDC circuit to the disk drives.

Write Precompensation and Write Data Pulse Shaping Logic
All Write Precompensation is generated internal to the FDC
chip 1773 (U17). Write Precompensation is enabled when
W6 goes high and Write Precompensation is enabled from
software. This signal is multiplexed with RDY by W6 is fed
into pin 20 of U17. Write Data is output pin 22 of U17 and is
shaped by a one-shot (1/2 of U56) which stretches the data
pulses to approximately 500 nsec.

Hardware 141

Floppy Disk Controller Chip

BRG Programming Table

The 1773 is an MOS LSI device which performs the functions
of a floppy disk formatter controller in a single chip implementation The following port addresses are assigned to the internal
registers of the 1773 FDC chip
Port No.
FOH
F1H
F2H
F3H

Function
Command Status Register
Track Register
Sector Register
Data Register

4.2.16 RS-232-C Circuit
RS-232C Technical Description
The RS-232C circuit for the Model 4P computer supports
asynchronous serial transmissions and conforms to the EIA
RS-232C standards at the input-output interface connector
(J4) The heart of the circuit is the TR1865 Asynchronous
Receiver/Transmitter U33 It performs the job of converting
the parallel byte data from the CPU to a serial data stream
including start, stop, and parity bits For a more detailed description of how this LSI circuit performs these functions, refer to the TR1865 data sheets and application notes The
transmit and receive clock rates that the TR1865 needs are
supplied by the Baud Rate Generator U73 (BR1943) This
circuit takes the 5 0688 MHz supplied by the system timing
circuit and the programmed information received from the
CPU over the data bus and divides the basic clock rate to
provide two clocks The rates available from the BRG go
from 50 Baud to 19200 Baud See the BRG table for the
complete list

Transmit'
Receive
Baud
Rate

Nibble
Loaded
OH
50
75
1H
2H
110
3H
1345
150
4H
5H
300
6H
600
1200
7H
1800
8H
9H
2000
AH
2400
BH
3600
CH
4800
DH
7200
EH
9600
FH
19200

16X

Clock
08kHz
1 2kHz
1 76 kHz
2 1523kHz
24kHz
48kHz
96kHz
192kHz
28 8 kHz
32 081 kHz
38 4 kHz
57 6 kHz
76 8 kHz
1152kHz
1536kHz
307 2 kHz

Supported
by

SETCOM

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
to*
Yes
Yes
Yfcs
Yes
Yes
Yes

The RS-232C circuit is port mapped and the ports used are E8
to EB Following is a description of each port on both input and
output
Port
E8

Input
Modem status

EA

UART status

E9

Not Used

EB

Receiver Holding
register

Output
Master Reset, enables UART
control register load
UART control register load and
modem control
Baud rate register load enable
bit
Transmitter Holding
register

Interrupts are supported in the RS-232C circuit by the Interrupt
mask register and the Status register internal to GA 4 5 (U31)
which allow the CPU to see which kind of interrupt has occurred Interrupts can be generated on receiver data register
full, transmitter register empty, and any one of the errors — parity, framing, or data overrun This allows a minimum of CPU
overhead in transferring data to or from the UART The interrupt
mask register is port EO (write) and the interrupt status register
is port EO (read) Refer to the IO Port description for a full breakdown of all interrupts and their bit positions

Hardware 142

o

All Model I, III, and 4 software written for the RS-232-C interface
is compatible with the Model 4P RS-232-C circuit, provided the
software does not use the sense switches to configure the interface. The programmer can get around this problem by directly programming the BRG and DART for the desired
configuration or by using the SETCOM command of the disk
operating system to configure the interface. The TRS-80 RS232C Interface hardware manual has a good discussion of the
RS-232C standard and specific programming examples (Catalog Number 26-1145).

Pinout Listing
The following list is a pinout description of the DB-25 connector
(P1).
Pin No.
1
2
3
4
5
6
7
8
19
20
22

Signal
PGND (Protective Ground)
TD (Transmit Data)
RD (Receive Data)
RTS (Request to Send)
CTS (Clear To Send)
DSR (Data Set Ready)
SGND (Signal Ground)
CD (Carrier Detect)
SRTS (Spare Request to Send)
DTR (Data Terminal Ready)
Rl (Ring Indicate)

Hardware 143

Model 4P Gate Array
I/O Pin Assignments

Pin
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.

36.
37.
36.
39.
40.
41.
42.
43.
44.
46.
46.
47.
48.
49.
50.

Signal

Pin Signal
No.

DATA STROBE
GND
PDO
GND
PD1
GND
PD2
GND
PD3
GND
PD4
GND
PD5
GND
PD6
GND
PD7
GND
N/A
GND
BUSY
GND
OUTPAPER
GND
UNIT SELECT
NC
GND
FAULT
N/A
N/A
NC
N/A
NC
GND

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.

XDO
GND
XD1
GND
XD2
GND
XD3
GND
XD4
GND
XD5
GND
XD6
GND
XD7
GND
XAO
GND
XA1
GND
XA2
GND
XA3
GND
XA4
GND
XA5
GND
XA6
GND
XA7
GND
XIN*
GND
XOUT*
GND
XRESET*
GND
IOBUSINT*
GND
IOBUSWAIT*
GND
EXTIOSEL*
GND
NC
GND
XMI*
GND
XIOREQ*
GND

Pin Signal
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.

XDO
GND
XD1
GND
XD2
GND
XD3
GND
XD4
GND
XD5
GND
XD6
GND
XD7
GND
XAO
GND
XA1
GND
XA2
GND
XA3
GND
XA4
GND
XA5
GND
XA6
GND
XA7
GND
XIN*
GND
XOUT*
GND
XRESET*
GND
IOBUSINT*
GND
lOBUSWAir
GND
EXTIOSEL*
GND
NC
GND
XMI*
GND
XIOREQ*
GND

o

J4

Pin
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.

Signal

J5

Pin
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.

PGND
TD
RD

CTS
DSR
CD
SGND
CD

10.
11.
12.
13.
14.
15.
16.
17.
18.

19. SRTS

20. DTR
21.
22. Rl
23.
24.
25.
26.
27.
28.
29.
30.

31.
32.
33.
34.

Signal

Pin
No.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.

GND
GND
GND
.
* &
GND
DIP*
GND
DSO*
GND
DS1*
GND
• * *
GND
MOTORON*
GND
DIR*
GND
STEP*
GND
WD*
GND
WG*
GND
DTRKO*
GND
DWPRT*
GND
DRRD*
GND
SDSEL
GND

Signal

Pin
No.
1.
2.
3.
4.
5.
6.
7.

DO
D1
D2
D3
D4
D5
D6
D7
GEN*
DCLK
AO
A1
A2
J
GRAFVID
ENGRAF
DISPEN
VSYNC
HSYNC
RESET*
WAIT*
H
I
IN*
GND
+ 5V

8.
9.
10.
11.
12.
13.
14.
1«.
18.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.

CL166*
GND

30. +5V

31. GND
32. +5V
33. GND

34. +5V

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Hardware 145

Signal
GND
VOUT
GND
VERTSYNC*
GND
HORZSYNC

o

9

SECTION V

CHIP SPECIFICATIONS

J

Hardware 147

o

«

CHIP SPECIFICATIONS

4P

4 GATE ARRAY

4PGATE ARRAY

Motorola

Motorola

Motorola

Motorola

MC 6835

MC 6835

MC 6835

MC 6835

Western Digital

Western Digital

Western Digital

BR 1943

BR 1943

BR 1943

TR 1865

TR 1865

WD 1773

WD 1773

WD 1943-00

MATRA

MATRA

MMI

MMI

Timing A. (4.1.1)

Timing A. (4.1 .1)

PAL 16RGA(166)

PAL 16RGAS.T.

Address A. (4.2.0)

Address A. (4.2.0)

PAL 10L8 (208)

PAL 10L8 V.T.

Video A. (4.3.0)

Video A. (4.3.0)

PAL 16L8 MeMep

VTI

VTI

PAL 16L8 Page Mep

FDC A. (4.4.0)

FDC A. (4.4.0)

RS-232 A. (4.5.0)

RS-232 A. (4.5.0)

(BR 1941 L)

FD 1793
(WD 179X)

FDC9216
TR 1865

PAL10L8C.T.
PAL 16L8 (268)
PAL 16L8 (368)

Zilog

Zilog

Zilog

Zilog

280 A

280 A

280 A

280 A

Hardware 149

:

o

ARRAY*:

4.1.1

CIRCUIT NAME:
NO. OF PINS:

System Timing

24

MAX. CLOCK FREQ.:
OPERTEMP.:

20.2752 MHz

0° C to 70° C

OPERATING VOLTAGE & RANGE:

Hardware 151

5 V ± 5%

20.275; JL
MHZ
CRYSTA]r.T

OSC.

i

PCLK
• RS232CLK

1.26'72MHZ
11

16

—1
12.672MH Z
PLL
NE564
I—1
1
1.26'72MHZ

I
10

FAST
§#64*
MODS EL
MAtf

24 PIN CHIP

Hardware 152

. SHIFT*
XADR7*
• CRTCLK
• LOADS*
DDT*
LOAD*
DCLK
H
I
J

G

XTAL#
XTAL1

0
(T)

V

(24) VCC
(2j) PCLK
@ RS232CLK

1.2M16 @
12M
©

@ SHIFT*

1.2ML0T

@) XADR7*

FAST
8#64*
MODS EL
MAtf

N.C.
J
GND

©
©®
©
©
®
©

(Q) CRTCLK

4.1.1

(fi) LOADS*
(17) DOT*
@ LOAD*
(15) DCLK
©> H
(fi) 1

©

Hardware 153

SYSTEM TIMING SPECS
NUMBER

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

PARAMETER

MIN.

20M Cycle Time
20M Pulse Width (High)
20M Pulse Width (Low)
10M Cycle Time
1~0M Pulse Width (High)
T0M Pulse Width (Low)
RS232CLK Cycle Time
RS232CLK Pulse Width (High)
RS232CK Pulse Width (Low)
PCLK* (Fast) Cycle Time
PCLK* (Fast) Pulse Width (High)
PCLK* (Fast) Pulse Width (Low)
PCLK* (/Fast) Cycle Time
PCLK* (/Fast) Pulse Width (High)
PCLK* (/Fast) Pulse Width (Low)
PCLK* Rise Time
PCLK* Fall Time

TYP.

MAX.

49.3
20
20

98.6

4540
4540
197.2
92
92

246.6
110
110

493.2
180
180

13
13

UNITS

ns
n$
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

DC CHARACTERISTICS (ALL PINS)
Input Voltage Level (High)
Input Voltage Level (Low)
Output Voltage Level (High)
Output Voltage Level (Low)

2.0

.5

V
V
V
V

40
-1.6

jia
ma

.8

2.8

3.5
.35

(ALL PINS EXCEPT CRTCLK OUTPUT)
Input Current Level (High)
Input Current Level (Low)
Output Current Level (High)
Output Current Level (Low)

-160
3.2

M»
ma

(CRTCLK OUTPUT)
Output Current Level (High)
Output Current Level (Low)

-400
8

Hardware 154

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Hardware 155

EH
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EH
CO
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fa

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^
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^

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VIDEO TIMING SPECS
10.1376MHz
NUMBER

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

22
23
24
25
26
27

28
29
30

31
32
33
34
35
36
37
38

PARAMETER
VCLK Cycle Time
VCLK Pulse Width (High)
VCLK Pulse Width (Low)
DCLK Cycle Time
DCLK Pulse Width (High)
DCLK Pulse Width (Low)
DOT Cycle Time
DOT Pulse Width (High)
DOT Pulse Width (Low)
DCLK Ito DOTt
DCLK t t o H, I, J U
H Cycle Time
H Pulse Width (High)
H Pulse Width (Low)
I Cycle Time
I Pulse Width (High)
I Pulse Width (Low)
J Cycle Time
J Pulse Width (High)
J Pulse Width (Low)
SHI FT Cycle Time
(64x16 & 80x24 Mode)
(32x16 & 40x24 Mode)
SHI FT Pulse Width (Low)
SHIFT t t o LOADS!
LOADS i to SHI FT t
LOADS Pulse Width (Low)
LOADS t to SHI FT t
LOADS Cycle Time
(64x16 & 80x24 Mode)
(32x1 6 & 40x24 Mode)
SHIFT t t o LOAD t
LOAD Pulse Width (Low)
LOAD Cycle Time
(64x16 & 80x24 Mode)
(32x16 & 40x24 Mode)
LOAD t t o C R T C L K I
CRTCLK Cycle Time
CRTCLK Pulse Width (High)
CRTCLK Pulse Width (Low)
CRTCLK H to XADR7 It
XADR7 Cycle Time
XADR7 Pulse Width (High)
XADR7 Pulse Width (Low)

MIN.

TYP.

12.672MHz
M/

MIN.

TYP.

MAX.

78.9

98.6
40
40

ns
ns
ns
ns
ns
ns
ns
ns
ns

30
30

78.9

98.6
40

30
30

40

78.9

98.6
40

30

40

30

5
27

5
27

197.2

394.4

315.6

190
190

150
150

788.8

631.2

385
385

305
305

98.6
197.2

78.9
157.8

30

ns
ns
ns

30

0
50*
70
50*

27

0

27*

50*

98.6

70

ns
ns

631.2
1262.4

ns

5
40

5
30

788.8
1577.6
0

0

788.8
385
385

27
631.2

631.2
305
305

ns
ns

ns
ns
ns
5

385
385

o

ns

305
305

788.8

ns
ns
ns

631.2
1262.4
27

ns
ns

78.9

50*

788.8
1577.6

ns
ns

•

ns
ns
ns
ns
ns
ns
ns
ns
ns

157.8
70
70

90
90

UNITS

ns
ns

ns
ns

9
Hardware 156

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Hardware 158

CO
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9

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4.1

MAX.
CAPACITANCE

PIN

SIGNAL

23

PCLK

22

RS232CK

21

SHIFT*

35 pf

20

XADR7*

35 pf

19

CRTCLK

35 pf

18

LOADS*

35 pf

17

DOT*

35 pf

16

LOAD*

35 pf

15

DCLK

35 pf

14

H

35 pf

13

I

35 pf

11

J

35 pf

Hardware 159

35 pf
105 pf

ARRAY*:

4.2.1

CIRCUIT NAME: Address Decode
NO. OF PINS:

40

MAX. CLOCK FREQ.:
OPER. TEMP.:

4 MHz

0° C to 70° C

OPERATING VOLTAGE & RANGE: 5± 5%

O

Hardware 160

V

+5V

MI

^»

IN*

TOPFO te»

^^
^^

OUT*
MRD*
MWR*

^

^^

RASENtf'*

pvpqpAf-p ^

^^
^^
k^
^^
^^

RASENl*
MAPA15
RAMBUSDIR
RAMBUS EN*
RAMRDEN/MCYCEN (RAMRDMCYC)
RAMWREN/ROMB*

^^
^^

BUSDIR*
BUSEN*

^^

VIDEO*
KEYED*
ROMCE*/ROMC*

RD

^

WP

^»

M17FO

^

RFSH

EN PAGE ^

°L F T Pf

^

A15
^
All
^
A13 fe»
Al° fc
All
^
AlF ^

^^
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MOD 4 P

ROM* /ROM A*
(I/O)

>»

1
4J0T PINS USED
4-Cf PIN

LPRQ*

CHIP

4.2.J0"
ADDRESS DECODE

Hardware 161

V

(40) VEC
(39) IN*

•

(38) OUT*
(37) MRD*
(36) MOD4P
(35) MWR*
@ RASEN>er*
(^) RASENI*
(5|) MAPA15

4.2.1

(3^) RAMBUSDIR
(30) RAMBUS EN*
(^) RAMRDEN/MCYCEN

o

^) RAMWREN/ROMB*
(Q) BUSDIR*
@ BUSEN*
(2§) SIXTN
(Q) VIDEO*
^3) KEYBD*
(2^1 ROMCE*/ROMC*
53) ROM*/ROMA*

w
Hardware 162

SIGNAL NAME

MODEL A MODE

MODEL 4 MODE

MDD4P

"|" = +SV

"0" = GND

Ml

Ml

Ml

IOREQ

IOREQ
RD

RD
WR
MREQ

WR

IOREQ
RD
WR

MREQ

IOREQ

RFSH

RFSH

RFSH

D ESP AGE
ENRAGE
SRCPAGE
SEL1

DESPAGE
ENPAGE
SRCPAGE
SEL1

DESPAGE
ENPAGE
SRCPAGE

SEL0
A15
A14

SEL0

A13
A12
A11
A10
LPADD

SEL1
SEL0
A15
A14
A13
A12

A15

A14
A13
A12
A11
A10
LPADD

A11
A10
LPADD

SIXTN

SIXTN

SIXTN

IN*
OUT*
MRD*
MWR*
RASEN0*
RASEN1*

IN*
OUT*
MRD*
MWR*

MAPA15
RAMBUSDIR
RAMBUSEN*
(RAMRDMCYC) RAM RDEN/MCYCEN
RAM WREN/ROMB*

MAPA15
RAMBUSDIR

BUSDIR*
BUSEN*
VIDEO*
KEYBD*
ROMCE*/ROMC*
LPRQ*
ROM*/ROMA*

RASEN0*
RASEN1*

RAMBUSEN*
RAMRDEN
RAMWREN
BUSDIR*
BUSEN4P*
VIDEO4P*
KEYBD4P*
ROMCE*
LPRQ*
ROM*

I = INPUT
O = OUTPUT

Hardware 163

0
O
O
O
O
O
0
0
O
O
O
O
0
O
O
O
0

I

IN*
OUT*
MRD*

O
O
O

MWR*
RASEN0*
RASEN1*

O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

MAPA15
RAMBUSDIR
RAMBUSEN*
MCYCEN
ROMB*
BUSDIR*
DATACNT*
VIDEO4*
KEYBD4*
ROMC*
LPRQ*
ROMA*

SPECS
MIN.

PARAMETER

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

IOREQ tl * RD tlto IN It
IOREQ tl * WR tlto OUT It
RD tlto MRD It
WR tlto MWR It
A15 tlto RASEN0 tl
A15 tlto RASEN1 tl
A15 Hto MAPA15 H
RD It to RAMBUSDIR It
MREQ tlto RAMBUSEN It
A15-A10 tlto RAMRDMCYC tl
A15-A14 tlto RAMWREN tl
MREQ tlto ROMB It
IOREQ tlto BUSDIR It
RD tlto BUSDIR It
MREQ tlto BUSEN It
MREQ tlto VIDEO It
MREQ tlto KEYBD It
MREQ tlto ROMCE It
MREQ tlto ROMC It
MREQ tlto LPRQ It
MREQ tlto ROMA It
PCLK HtoPCLK It
PCLK Cycle Time
PCLK t t o M1 t
PCLK 1 to MREQ t
A10-A15 tlto MREQ t
PCLK Ito RD t
PCLK tto A10-A15 tl
PCLK tto A10-A15 tl
PCLK t t o M1 1
PCLK t t o MREQ I
MREQ I t o M R E Q t
PCLK t t o RD 1
PCLK t t o RFSH t
RFSH tl to RASEN 0 or RASEN1 tl
PCLK Ito MREQ 1
MREQ Pulse Width (High)
PCLK t t o RFSH 1
A1-A9 tlto LPADD tl
PCLK Ito WR tl
PCLK Ito RD 1
Control Lines tl to Affected Signals tl
A0-A15 tlto IOREQ t
PCLK t t o IOREQ t
PCLK t t o RD t
PCLK t t o WR t

Hardware 164

TYP.

MAX.

35
35
35
35
50
50
50
35
35
50
50
35
35
35
50
35
35
35
35
35
35
110

123
246

106
91

50
101
128
128
136
91
110

220

91
136
35
91
126

30
86
91
35
200

81
91
71

UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

•

o

44

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Hardware 166

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Hardware 167

DC CHARACTERISTICS (ALL PINS) 0° - 70° C

PARAMETER

MIN.

Input Voltage Level (High)

2.0

TYP.

MAX.

V

Input Voltage Level (Low)
Output Voltage Level (High)

.8
2.7

UNITS

3.5

Output Voltage Level (Low)

V
V

.35

.5

V

(ALL PINS EXCEPT OUT*, RAMRDEN/MCYCEN)
Input Current Level (High)

20

Input Current Level (Low)

—.4

Output Current Level (High)

-200

Output Current Level (Low)

4

jua
ma
jua
ma

(OUT*, RAMRDEN/MCYCEN)
Output Current Level (High)
Output Current Level (Low)

-400

jua

8

ma

Hardware 168

»

MAX.
CAPACITANCE

PIN

SIGNAL

39

IN"

35 pf

38

OUT*

35 pf

37

MRD*

35 pf

35

MWR*

128pf

34

RASEN0*

35 pf

33

RASEN1*

35 pf

32

MAPA15

35 pf

31

RAMBUSDIR

35 pf

30

RAMBUSEN*

35 pf

29

RAMRDEN/MCYCEN

35 pf

28

RAMWREN/ROMB*

35 pf

27

BUSDIR*

35 pf

26

BUSEN*

35 pf

24

VIDEO*

35 pf

23

KEYBD*

35 pf

22

ROMCE*/ROMC*

35 pf

ROMA*

35 pf

LPRQ*

35 pf

(OUTPUT) 21

14

Hardware 169

ARRAY*:

4.3.0

CIRCUIT NAME:
NO. OF PINS:

Video Support

40

MAX. CLOCK FREQ.:

1 2.672 MHz

OPER. TEMP.: 0°Cto70°C
OPERATING VOLT AGE & RANGE:

Hardware 170

5 ± 5%

O

+5V

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CGA /

"^

CGAo

^

CGA9

^

^

^^
^^

39 PINS USED
40 PIN CHIP
4.3.,8f

VIDEO SUPPORT
Hardware 171

^^O U
C\
UvorU

40

+ 5V

2

39

CGA6

CGA9

3

38

CGA5

CGAltf
3RD 7

4
5

37

CGA4

36

CGA3

SRD6

6

35

RA3

SRD5

7

34

RA2

SRD4

8

33

CGD7

SRD3 9
SRD2 10

32

CGD6

31

CGD5

SRDl

11

30

CGD4

SRDO

12

29

CGD3

CGA7

1

CGA8

V

DLYCHAR* 13

28 CGD2

DLYCHAR
DISPEN

14
15

27

CL166*
ENGRAF

16
17

25 INVERSE
24 ENALTSET

GRAFVID

18

23 LOAD*

VOUT *

19

22 LOADS*

GND

20

21

CGD1

26 CGDO

Hardware 172

SHIFT*

o

SPECS

1**
2*
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
20**
21
22
23**
24*
25
26*
271
28
29
30
31
32

PARAMETER

MIN.

SRD0-SRD7 tlto LOAD t
inputs D0-D7 of LS273 tl to LOAD t
LOAD ttoCGA3-CGA10 tl
R A2, R A3 tl to Outputs of LS153 tl
Inputs CGA3-CGA10of LS153 tl to Outputs
DLYGRAPHIC I to Outputs of LS244 tl
D LYG RAPH 1C t to Outputs of LS244 Tristate
ENALTSET tl to CGA9 tl
INVERSE tl to Inputs D7 of LS273 tl
INVERSE tl to INVDISPEN, CHAR tl
INVERSE t| to Input to 51 tl
SRD6 tl to CHAR tl
DISPEN t|to Input D0 of LS175 tl
DISPEN tl to INVDISPEN tl
ENGRAF tl to INVDISPEN tl
ENGRAF tl to Inputs of 51 tl
GRAFVID tlto Inputof 51 t|
CGD0-CGD7 Hto LOADS I & SHIFT t
RA3 tlto DLYBLANK t|
LOAD t t o DLYBLANK tl
LOADS I to SHIFT t
SHFT/LD I to SHIFT t
CL166 tl to OH tl
LOAD t t o SHIFT t
LOAD t to VIDEO2 tl - SHIFT t to VIDEO1
GRAFVID tlto VIDEO2 tl
VIDEO2 U, VIDEO1 tlto VOUT tl
ENGRAF tlto VIDE02 tl
DLYCHAR* t t o CGD0-CGD7 Tristate
CRTCLK I to DISPEN

61
29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
100
27
27
50
30
0

tl

0
0

tl
0
0
0

TYP.

MAX.

60
36
30
30
30
%
35
40
20
40
20
40
40
20
S
50
50

30
±5
±5
15
20
15
150
300

1 The delay from LOAD t t o VIDEO2 t| should equal the delay from SHIFT t t o VIDEO1 t+.
Specs required for TLL components—can be changed to meet the setup & hold time specs of array logic.
**Specs provided are for reference, timing is from external logic.

Hardware 173

UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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Hardware 175

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Hardware 176

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Hardware 177

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DC CHARACTERISTICS (ALL PINS) 0° - 70° C

PARAMETER

MIN.

Input Voltage Level (High)

2.0

TYP.

MAX.

V

Input Voltage Level (Low)
Output Voltage Level (High)

.8
2.7

Output Voltage Level (Low)

3.5

Output Current Level (Low)

.5

20

Input Current Level (Low)

—.4
-200

V
V

.35

Input Current Level (High)

Output Current Level (High)

UNITS

V

jua
ma
jja

4

ma

^/

Hardware 179

4.3

PJN

SIGNAL

MAX.
CAPACITANCE

4

CGA10

35 pf

3

CGA9

35 pf

2

CGA8

35 pf

1

CGA7

35 pf

39

CGA6

35 pf

38

CGA5

35 pf

37

CGA4

35 pf

36

CGA3

35 pf

13

DLYCHAR*

35 pf

14

DLYCHAR

35 pf

19

VOUT*

35 pf

o

V*$^a,

Hardware 180

ARRAY#:

4.4.0

CIRCUIT NAME: Floppy Disk Support
NO. OF PINS:

24

MAX. CLOCK FREQ.:

8 MHz

MAX. PROP. DELAY THROUGHPUT:
OPER. TEMP:

75ns

0°Cto70°C

OPERATING VOLT AGE & RANGE:

Hardware 181

5 V ± 5%

4.4.tf

+ 5V
T24
8MHZ
ENP/RDY

D#
Dl
D2
D3
D5
D6
D7

MOTORON
EXTSEL

NMI
WAIT

RESET*
WRNMI*
RDNMI*
DRVSEL*

O

XTALtf
16MHZ
XTAL

INTRQ
DRQ
WG

XTALl

12

24 PIN CHIP
FLOPPY DISK SUPPORT

Hardware 182

INTRQ

CD

CD
ENP/RDY @
WG
®
DO
©
Dl
®
D2
©
D3
®
D5
®
D6
@
D7
@
GND
£2)

V

DRQ

vcc
XTALfl'
XTAL1
MOTORON
EXT S EL
NMI

4.4

WAIT
WRNMI*
RDNMI*
DRVSEL*
8MHZ
RESET*

Hardware 183

SPEC.

1.
2.
3.
4.
5.
6.
* 7 .
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.

PARAMETER

MIN

Data Setup Time
Data Hold Time
Reset* Pulse Width
Reset* I to Wait or NMU
WRNMI* t to 74LS74Q's Outputs It
DRVSEL* I to MOTORON t
MOTORON Pulse Width (Low)
DRVSEL* I to WAIT t
DRVSEL* I t o C L R W A I T t
DRVSEL* ; to WAITIMOUTt
DRVSEL* t to ENP/RDY H
DRVSEL* t to EXTSEL tl
INTRO t o r D R Q t t o WAIT 4INTRO tor D R Q t t o CLRWAIT 4INTRO tor DRQ t to WAITIMOUT I
8 MHZ Cycle Time
8 MHZ Pulse Width (Low)
8 MHZ Pulse Width (High)
WG t! to ENP/RDY tl
RDNMI* I to D0, D5-D7 Valid
RDMMI* t t o D0, D5-D7 Tristate 0

560
50

TYP

70

3

4

500
1024

50
50

MAX

100
75
75
75
5
75
1100
1050
75
75
75
75
75

125
62.5
62.5

MOTORON Circuit Must Simulate a Retriggerable Monostable Multivibrator (74LS123)

75
75
75

UNITS
m
CIS
JJS
nf
ns
n$
f«C.
ff»
ns
jis
ns
ns
ns
ns
ns
ns
n$
ns
ns
ns
ns

o

v
Hardware 184

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Hardware 186

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CAPACITANCE LOAD
OUTPUT

CAPACITANCE MAX.

D0

80 pf

D5

80 pf

D6

80 pf

D7

80 pf

8 MHZ

15 pf

ENP/RDY

15 pf

MOTORON

15pf

EXTSEL

15pf

NMI

15 pf

WAIT

15pf

Hardware 187

DC CHARACTERISTICS 0° - 70° C
(ALL PINS)
PARAMETER

MIIM.

Input Voltage Level (High)
Input Voltage Level (Low)
Output Voltage Level (High)
Output Voltage Level (Low)

2.0

TYP.

MAX.

.5

V
V
V
V

20
-.4

V*
ma

&

2.7

3.5
.35

UNITS

V

(ALL PINS EXCEPT MOTORON & D0, D5-D7)

Input Current Level (High)
Input Current Level (Low)
Output Current Level (High)
Output Current Level (Low)

-160
3.2

M*
ma

MOTORON

Output Current Level (High)
Output Current Level (Low)

-240
4.8

*»

D0, D5-D7

Input Current Level (High)
Input Current Level (Low)
Output Current Level (High)
Output Current Level (Low)

20
-.4
-280
5.6

0*
ma
M>

o

w
Hardware 188

ARRAY*:

4.5.0

CIRCUIT NAME:

RS232 Support

NO. OF PINS:

40

OPER.TEMP.:

0°Cto70°C

OPER. VOLTAGE:

5V± 5%

Hardware 189

vcc
AO

1

9

RTS

Al

2

10

DTR

RDINTSTATUS

3

7

SRTS

WRINTMASKREG

4

8

ENTD

RS232IN

5

21

OUTE8

RS232OUT

6

38

OUTE9

CTS

14

11

OUTEA

DSR

15

4 •c3 •nU

23

OUTER

CD

16

40 PIN

18

INEB

RI

20

RD

13

37

INT

PE

26

FE

25

27

BDQT

DE

24

28

BDl

THRE

22

29

BD2

DR

19

30

BD3

RTCIN

36

31

BD4

XINT

35

32

BD5

WR

39

33

BD6

34

BD7

N. C.J±

^L
Hardware 190

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1 Voltage levels shown are V ( _ < 0 4 V, V^\>2 4 V unless otherwise noted
2 Measurement points shown are 0 8 V and 2 0 V unless otherwise noted

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FIGURE 3 - BUS TIMING TEST LOAD
O 50 V

Ri

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2 4 kfl

C = 1 3 0 p F for DO-D7
= 30 pF for MAO-MA13, RAO-RA4,
DE( HS( vs and CURSOR
R = 1 1 kO for DO-D7
= 24 kfl for All Other Outputs

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CRTC TIMING CHARACTERISTICS (See Figure 4)
Characteristics
Minimum Clock Pulse Width, Low
Minimum Clock Pulse Width, High
Clock Frequency
Rise and Fall Time for Clock Input

Symbol
PWc L
PWcH
fc
t r , tf

MC6835
Max

Mm
150
150
330
-

-

MC68A35
Max
140
140
300
20
160
160
250
250
250
250
-

Min

20

Memory Address Delay Time

1

MAD

~

160

Raster Address Delay Time
Display Timing Delay Time
Horizontal Sync Delay Time
Vertical Sync Delay Time
Cursor Display Timing Delay Time

tRAD
*DTD
*HSD
*VSP
*CDD

~
~
~

250

160
250
250
250

MC68B35
Min Max
130
130
270
20
160
160
200
200
200
200

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

FIGURE4-- CRTC TIMING CHART

PWCH |<
CLK

1

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NOTE Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 C volts unless otherwise noted

[ AA 1 JMFAT'OROLA

Semiconductor Product* %?
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CRTC INTERFACE SYSTEM DESCRIPTION

The MC6835 CRT Controller generates the signals
necessary to interface a digital system to a raster scan CRT
display In this type of display, an electron beam starts in the
upper left hand corner, moves quickly across the screen and
returns This action is called a horizontal scan After each
horizontal scan the beam is incrementally moved down in the
vertical direction until it has reached the bottom At this
point one frame has been displayed, as the beam has made
many horizontal scans and one vertical scan
Two types of raster scanning are used in CRTs, interlace
and non-mterlace, shown in Figures 5 and 6 Non-interlacing
scanning consists of one field per frame The scan lines in
Figure 5 are shown as solid lines and the retrace patterns are
indicated by the dotted lines Increasing the number of
frames per second will decrease the flicker Ordinarily, either
a 50 or 60 frame per second refresh rate is used to minimize
beating between the frequency of the CRT horizontal
oscillator and the power line frequency This prevents the
displayed data from weaving or swimming
Interlace scanning is used in broadcast TV and on data
monitors where high density or high resolution data must be
displayed Two fields, or vertical scans are made down the
screen for each single picture or frame The first field (Even

field) starts in the upper left hand corner, the second (Odd
field) m the upper center Both fields overlap as shown in
Figure 6, thus interlacing the two fields into a single frame
In order to display the characters on the CRT screen the
frames must be continually repeated The data to be
displayed is stored in the Refresh (Screen) memory by the
MPU controlling the data processing system The data is
usually written in ASCII code, so it cannot be directly
displayed as characters A Character Generator ROM is
typically used to convert the ASCII codes into the "dot" pattern for every character
The most common method of generating characters is to
create a matrix of "x" dots (columns) wide and "y" dots
(rows) high Each character is created by selectively filling m
the dots As "x" and "y" get larger a more detailed character
may be created Two common dot matrices are 5 x 7 and
7 x 9 Many variations of these standards will allow Chinese,
Japanese, or Arabic letters instead of English Since
characters require some space between them, a character
block larger than the character is typically used as shown m
Figure 7 The figure also shows the corresponding timing
and levels for a video signal that would generate the
characters

FIGURE 5 - RASTER SCAN SYSTEM (NON-INTERLACE)
• Active Display

Vertical Scan Period

Vertical Retrace Period

Horizontal Scan
Period

Horizontal Retrace
Period

FIGURE 6 - RASTER SCAN SYSTEM (INTERLACE)

• Even Number Field (First)
Odd Number Field (Second)

r--»x
^^
Semiconductor Products Inc.

FIGURE 7 - CHARACTER DISPLAY ON THE SCREEN AND VIDEO SIGNAL

e

One Charat ter
Clock









Character
Display

-(>-

One Line
14 Scan ^
Lines


10-

> Line Space
1214-

First Scan Line

Second Scan Line

n..n a_n

Referring to Figure 1, the MC6835 CRT controller
generates the Refresh addresses (MAO-MA13), row addresses (RAO-RA4), and the video timing (vertical sync —
VS, horizontal sync — HS and display enable — DE) Other
functions include an internal cursor register which generates
a Cursor output when its contents compare to the current
Refresh address A select input, PROG, allows selection of
one of two mask programmed video formats (e g , for 50 Hz
and 60 Hz compatibility)
All timing in the CRTC is derived from the CLK input In
alphanumeric terminals, this signal is the character rate The
video rate or "dot" clock is externally divided by high speed
logic (TTL) to generate the CLK signal The high speed logic
must also generate the timing and control signals necessary
for the Shift Register, Latch and MUX Control shown in
Figure 1
The processor communicates with the CRTC through an
8-bit data bus by writing into the five user programmable
registers of the MC6835
The Refresh memory address is multiplexed between the
processor and the CRTC Data appears on a secondary bus
separate from the processor's bus The secondary data bus
concept in no way precludes using the Refresh RAM for
other purposes It looks like any other RAM to the processor
A number of approaches are possible for solving contentions
for the Refresh memory
1 Processor always gets priority (Generally, "hash" occurs as MPU and CRTC clocks are not synchronized )

I

Processor gets priority access anytime, but can be
synchronized by an interrupt to perform accesses only
during horizontal and vertical retrace times
J Synchronize the processor with memory wait cycles
(states)
\ Synchronize the processor to the character rate as
shown in Figure 8 The M6800 processor family works
very well in this configuration as constant cycle
lengths are present This method provides no
overhead for the processor as there is never a contention for a memory access All accesses are
transparent

o

FIGURE 8 - TRANSPARENT REFRESH MEMORY
CONFIGURATION TIMING USING M6800 FAMILY MPU

Where m, n are integers, t c is character period

MOTOROLA Semiconductor Products Inc.

w

PIN DESCRIPTION
PROCESSOR INTERFACE
The CRTC interfaces to a processor bus on the data bus
(DO-D7) using CS, RS, E, and W for control signals
Data Bus (DO-D7) - The data lines (DO D7) comprise the
write only data bus
Enable (E) — The Enable signal is a high-impedance
TTL/MOS-compatible input which enables the data bus input/output buffers and clocks data to the CRTC This signal
is usually derived from the processor clock The high to low
transition is the active edge
Chip Select (CS) - The CS line is an active-low highimpedance TTL/MOS-compatible input which selects the
CRTC write to the internal register file This signal should
only be active when there is a valid stable address being
decoded from the processor
Register Select (RS) — The RS line is a high-impedance
TTL/MOS-compatible input which selects either the Address Register (RS = "0") or one of the Data Registers
(RS = "1") of the internal register file when CS is low
Write (W) - The W line is a high-impedance TTL/MOScompatible input which determines whether the internal
register file gets written A write is defined as a low level
CRT CONTROL
The CRTC provides horizontal sync (HS), vertical sync
(VS), and display enable (DE) signals
NOTE — Care should be exercised when interfacing to
CRT monitors as many monitors claiming to be "TTL compatible/' have transistor input circuits which require the
CRTC or TTL devices buffering signals from the CRTC/video
circuits to exceed the maximum rated drive currents
Vertical Sync (VS) and Horizontal Sync (HS) - These
TTL-compatible outputs are active-high signals which drive
the monitor directly or are fed to the video processing circuitry to generate a composite video signal The VS signal
determines the vertical position of the displayed text while
the HS signal determines the horizontal position of the
displayed text

the Memory Addresses and the Row Addresses continue to
run during vertical retrace thus allowing the CRTC to provide
the refresh addresses required to refresh dynamic RAMs
Refresh Memory Addresses (MAO-MA13) - These 14 outputs are used to refresh the CRT screen with pages of data
located within a 16K block of refresh memory These outputs
are capable of driving one standard TTL load and 30 pF
Row Addresses (RAO-RA4) - These five outputs from the
internal Row Address counter are used to address the
Character Generator ROM These outputs are capable of
driving one standard TTL load and 30 pF
OTHER PINS
Cursor — This TTL-compatible output indicates a valid
Cursor address to external video processing logic It is an
active-high signal
Clock (CLK) - The CLK is a TTL/MOS-compatible input
used to synchronize all CRT functions except for the processor interface An external dot counter is used to derive
this signal which is usually the character rate in an
alphanumeric CRT The active transition is high-to-low
Program Select (PROG) - This TTL-compatible input
allows selection of one of two sets of mask programmed
video formats Set zero is selected when PROG is low and
set one is selected when PROG is high
VCG, GND - These inputs supply +5 Vdc ±5% to the
CRTC
RESET - The RESET input is used to reset the CRTC
Functionality of RESET differs from that of other M6800
parts RESET must remain low for at least one cycle of the
character clock (CLK) A low level on the RESET input
forces the CRTC into the following state
a All counters in the CRTC are cleared and the device
stops the display operation
b All the outputs are driven low, except the MAO-MA13
outputs which are driven to the current value in the
Start Address Register
c The control registers of the CRTC are not affected and
remain unchanged
d The CRTC resumes the display operation immediately
after the release of RESET

Display Enable (DE) — This TTL-compatible output is an
active-high signal which indicates the CRTC is providing addressing in the active Display Area

CRTC DESCRIPTION

REFRESH MEMORY/CHARACTER GENERATOR ADDRESSING
The CRTC provides Memory Addresses (MAO-MA13) to
scan the Refresh RAM Row Addresses (RAO-RA4) are also
provided for use with character generator ROMs In a
graphics system both the Memory Addresses and the Row
Addresses would be used to scan the Refresh RAM Both

The CRTC consists of mask-programmable horizontal and
vertical timing generators, software-programmable linear address register, mask-programmable cursor logic and control
circuitry for interfacing to a M6800 family microprocessor
bus
All CRTC timing is derived from CLK, usually the output of
an external dot rate counter Coincidence (CO) circuits continuously compare counter contents to the contents of the

MOTOROLA Semiconductor Products Inc.

TABLE 1 - INTERNAL REGISTER ASSIGNMENT
Address Register Register
It
4 3 2 1 0

Program
Unit

cs

RS

1

X

X

X

X

X

X

X

-

-

0

X

X

X

X

X

AR

Address Register

-

0

-

No

Yes

RO

Horizontal Total

Char

No

No

R1

Horizontal Displayed

Char

No

No

R2

H Sync Position

Char

No

No

R3

Sync Width

-

No

No

V

R4

Vertical Total

Row

No

No

\

R5

V Total Adjust

Scan Line

No

No

\

R6

Vertical Displayed

Char

Row

No

No

\

Char

Row

\

\ Note 3 /

0
0
0
0

1
1
1
1

0
0
0
0

1
1
1
1

Register File

R7

V Sync Position

R8

Interlace Mode and Skew

R9

Char

Read

Write

No

No

Note 1

No

No

Max Scan Line Address

Scan Line

No

No

R10

Cursor Start

Scan Line

No

No

R11

Cursor End

Scan Line

No

No

1

0

0

R12

Start Address (H)

-

No

Yes

1

0

1

R13

Start Address (L)

-

No

Yes

1 1 0
1 1 1

R14

Cursor (H)

-

No

Yes

R15

Cursor (L)

-

No

Yes

7

6

Number of Bits
5 4 3 2 1 0

\ \\ \ \ \ \ \
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V

V

v

H H H H

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c c

D D

I

I

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P

0

0

0

0

(Note 2)

NOTES
1 The Interlace Control is shown in Table 2 while Skew Control is shown m Table 3
2 Bit 5 of the Cursor Start Raster Register is used to blink period control, and Bit 6 is used to select blink or non-blink
3 RO-R11 are mask-programmable and are not accessible via the data bus

mask programmable register file, RO-FU1 For horizontal tim
ing generation, comparisons result in
1 Horizontal sync pulse (HS) of a frequency, position
and width determined by the register contents
2 Horizontal Display signal of a frequency, position and
duration determined by the register contents
The horizontal counter produces H clock which drives the
Scan Line Counter and Vertical Control The contents of the
Raster Counter are continuously compared to the Max Scan
Line Address Register A coincidence resets the Raster
Counter and clocks the Vertical Counter
Comparisons of Vertical Counter contents and Vertical
Registers result in
1 Vertical sync pulse (VS) of a frequency, position and
width determined by the register contents
2 Vertical Display signal of a frequency, position, and
duration determined by the register contents
The Vertical Control Logic has other functions
1 Generate row selects, RAO-RA4, from the Raster
Count for the corresponding interlace or non-mterlace
modes
2 Extend the number of scan lines in the vertical total by
the amount programmed in the Vertical Total Adjust
Register
The cursor logic determines the size and blink rate of the

cursor as indicated by the register contents
The Linear Address Generator is driven by CLK and
locates the relative positions of characters in memory and
their positions on the screen Fourteen outputs, MAO-MA13,
are available for addressing up to four pages of 4K
characters, eight pages of 2K characters, etc
Five additional write-only registers define the Start Address and cursor position Using the Start Address Register,
hardware scrolling through 16K characters is possible The
Linear Address Generator repeats the same sequence of addresses for each scan line of a character row The Start Address Register and the Cursor Position Register are programmed by the processor through the data bus, DO-D7 and the
control signals - W, CS, RS, and E Refer to Figure 9

o

REGISTER FILE DESCRIPTION
The MC6835 has 17 control registers of which 12 are mask
programmable The remaining five registers — Address
register, Start Address register pair, and Cursor Position
register pair — are write-only registers programmed by the
MPU These registers control horizontal timing, vertical timing, interlace operation, row address operation and define
the cursor, cursor address, and start address The register
addresses and sizes are shown in Table 1

MOTOROLA Semiconductor Products Inc.

w

FIGURE 9 - CRTC BLOCK DIAGRAM
Prog

W CS RS

E

RESET

I MII

i_

RO-2

If

Address Register
and Decoder

-i

Horizontal Total
Reg.

H Display
D,
R1

I Horizonal Displayed
'
Reg.

R2 I

Sync Position Reg.
-**HS
Horizontal Sync
Width Register

R4|

Vertical Total Reg.

Vertical Total
Adjust Register
V Display
_ _ I Vertical Displayed
1

Reg.

Vertical Sync
Position Reg.

-** VS

R8 I Interlace Mode Reg.

DQI
Ky|

|

JRIOj

Max Scan Line
Address Reg.

Cursor Start Reg.

|
-CURSOR

Cursor End Reg.

jrcffi Start Address Reg.

irsor Address Reg.
DO-D7

AA) MOTOROLA Semiconductor Products Inc.

MASK PROGRAMMABLE REGISTERS RO-R11
The twelve mask programmable registers determine the
display format generated by the MC6835 The PROG input is
used to select one of two sets of register values
Figure 10 shows the visible display area of a typical CRT
monitor giving the point of reference for horizontal registers
as the left most displayed character position Horizontal
registers are programmed in character clock time units with
respect to the reference as shown in Figure 11 The point of
reference for the vertical registers is the top character position displayed
Vertical registers are programmed in
character row times or scan line times as shown in Figure 12
Horizontal Total Register (RO) - This 8-bit register determines the horizontal sync (HS) frequency by defining the HS
period in character times It is the total of the displayed
characters plus the non-displayed character times (retrace)
minus one
Horizontal Displayed Register (R1) — This 8-bit register
determines the number of displayed characters per line Any
8-bit number may be programmed as long as the contents of
RO are greater than the contents of R1
Horizontal Sync Position Register (R2) - This 8-bit
register controls the HS position The horizontal sync position defines the horizontal sync delay (Front Porch) and the
horizontal scan delay (Back Porch) When the programmed
value of this register is increased, the display on the CRT
screen is shifted to the left When the programmed value is

decreased the display is shifted to the right Any 8-bit
number may be programmed as long as the sum of the contents of R1, R2, and the lower four bits of R3 are less than
the contents of RO
Sync Width Register (R3) - This 8-bit register determines
the width of the vertical sync (VS) pulse and the horizontal
sync (HS) pulse Programming the upper four bits for 1-to-15
will select VS pulse widths from 1-to-15 scan-line times Programming the upper four bits as zeros will select a VS pulse
width of 16 scan line times The HS pulse width may be programmed from 1-to-15 character clock periods thus allowing
compatibility with the HS pulse width specifications of many
different monitors If zeros are written into the lower four
bits of this register, then no HS is provided
Horizontal Timing Summary (Figure 11) — The difference
between RO and R1 is the horizontal blanking interval This
interval in the horizontal scan period allows the beam to
return (retrace) to the left side of the screen The retrace time
is determined by the monitor's horizontal scan components
Retrace time is less than the horizontal blanking interval A
good rule of thumb is to make the horizontal blanking about
20% of the total horizontal scanning period for a CRT In inexpensive TV receivers, the beam overscans the display
screen so that aging of parts does not result in underscannmg Because of this, the retrace time should be about 1/3
the horizontal scanning period The horizontal sync delay,
HS pulse width and horizontal scan delay are typically programmed with 1 2 2 ratio

o

FIGURE 10 - ILLUSTRATION OF THE CRT SCREEN FORMAT
I

Number of Horizontal Total Char (Nht+ 1)-Number of Horizontal Displayed Char (Nhd)-

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Total Scan Line Adjust (Nadj) —
NOTE 1 Timing values are described in Table 8

MOTOROLA Semiconductor Products Inc.
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Value
00
10

One Character Skew
Two Character Skew

11

Not Available

01

tion the cursor anywhere on the screen and allow the start
address to be modified
The Address Register is a five-bit write-only register used
as an "indirect" or "pointer" register Its contents are the address of one of the other 18 registers When both RS_and CS
are low, the Address Register is selected When CS is low
and RS is high, the register pointed to by the Address
Register is selected

Skew
No Character Skew

Maximum Scan Line Address Register (R9) - This 5-bit
register determines the number of scan lines per character
row including the spacing thus controlling operation of the
Row Address counter The programmed value is a maximum
address and is one less than the number of scan lines

V

Start Address Register (R12-H, R13-L) - This 14-bit
write-only register pair controls the first address output by
the CRTC after vertical blanking It consists of an 8-bit low
order (MAO-MA7) register and a 6-bit high order (MASMAIS) register The start address register determines which
portion of the refresh RAM is displayed on the CRT screen
Hardware scrolling by character, line or page may be accomplished by modifying the contents of this register

Cursor Start Register (R10) and Cursor End Register (R11)
These registers allow a cursor of up to 32 scan lines in
height to be placed on any scan line of the character block as
shown in Figure 14 R10 is a 7 bit register used to define the
start scan line and blink rate for the cursor Bits 5 and 6 of
the Cursor Start Address Register control the cursor operation as shown in Table 4 Non-display, display and two blink
modes (16 times or 32 times the field period) are available
R11 is a 5-bit register which defines the last scan line of the
cursor
When an external blink feature on characters is required, it
may be necessary to perform cursor blink externally so that
both blink rates are synchronized Note that an mvert/noninvert cursor is easily implemented by programming the
CRTC for a blinking cursor and externally inverting the video
signal with an exclusive-OR gate

Cursor Register (R14-H, R15-L) - This 14-bit write-only
register pair is programmed to position the cursor anywhere
in the refresh RAM area thus allowing hardware paging and
scrolling through memory without loss of the original cursor
position It consists of an 8-bit low order (MAO-MA7) register
and a 6-bit high order (MA8-MA13) register

CRTC INITIALIZATION
Registers R12-R15 must be initialized after the system is
powered up The processor will normally load the CRTC
register file from a firmware table Figure 15 shows an M6800
program which could be used to program the CRT Controller

PROGRAMMABLE REGISTERS
The four programmable registers allow the MPU to posi

o

FIGURE 14 - CURSOR CONTROL

On

I Off
I On
I
[^
Blink Period =
I
16 or 32 Times
Field Period

Example of Cursor Display Mode
01234567891011-



Cursor Start Adr =9
Cursor End Adr = 9

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MC6835

OPERATION OF THE CRTC
format of this example is shown in Figure 10 Figure 17 is an
illustration of the relation between Refresh Memory Address
(MAO MA13), Raster Address (RAO-RA4) and the position
on the screen In this example, the start address is assumed
to be "0"

Timing of the CRT Interface Signals — Timing charts of
CRT interface signals are illustrated in this section with the
aid of programmed example of the CRTC When values
listed in Table 7 are programmed into CRTC control
registers, the device provides the outputs as shown in the
Timing Diagrams (Figures 11, 12, 16, and 17) The screen

«

TABLE 7 - VALUES PROGRAMMED INTO CRTC REGISTERS
Register
Number
RO
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15

Register Name
H
H
H
H

Value

Total
Displayed
Sync Position
Sync Width

V Total
V Scan Line Adjust
V Displayed
V Sync Position
Interlace Mode
Max Scan Line Address
Cursor Start
Cursor End
Start Address (H)
Start Address (L)
Cursor (H)
Cursor (L)

Programmed
Value

N h t +1

Nht

Nhd

Nhd

N
hsp
Nhsw

Nhsp
Nhsw

Nvt+1
Nadj

Nadi

Nvd
N

vsp

NSI

Nvt
Nvd
N

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0
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FIGURE 18 - ROM PROGRAM WORKSHEET

»

The value in each register of the MC6845 should be entered without any modifications. Motorola will take care of translating into the appropriate
format.
D All numbers are in decimal.
ROM
Program
Zero
(PROG = 0)

D All numbers are in hex.
ROM
Program
One
(PROG=1)

RO
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11

ORDERING INFORMATION
Package Type

Temperature

Order Number

Frequency (MHz)
1.0
1.0
1.5
1.5
2.0
2.0

0°C to 70°C
-50°C to85°C
0°C to 70°C
-50°C to85°C
0°C to 70 °C
-50°C to85°C

MC6835L
MC6835CL
MC68A35L
MC68A35CL
MC68B35L
MC68B35CL

Cerdip
S Suffix

1.0
1.0
1.5
15
2.0
2.0

0°C to 70°C
-50°C to85°C
0°C to 70°C
-50°Cto85°C
0°C to 70°C
-50°C to85°C

MC6835S
MC6835CS
MC68A35S
MC68A35CS
MC68B35S
MC68B35CS

Plastic
P Suffix

1.0
1.0
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2.0
20

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-50°C to85°C
0°C to 70 °C
-50°C to85°C
0°C to 70°C
-50°Cto85°C

MC6835P
MC6835CP
MC68A35P
MC68A35CP
MC68B35P
MC68B35CP

Ceramic
L Suffix

Semiconductor Products Inc.
21

PACKAGE DIMENSIONS

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PIN DESCRIPTION

CD
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SYMBOL

PIN NUMBER

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NAME

FUNCTION

1

XTAUEXT 1

Crystal or
External Input 1

This input receives one pin of the crystal package or
one polarity of the external input.

2

VCG

Power Supply

+ 5 volt. Supply

3

fR

Receiver Output
Frequency

This output runs at a frequency selected by the
Receiver Address inputs.

RA, RB. RC, RD

Receiver Address

The logic level on these inputs as shown in Tables 1
through 6, selects the receiver output frequency, f p.

8

SIR

Strobe-Receiver
Address

A high-level input strobe loads the receiver address
( R A> RB. RC, RD) into tne receiver address register.
This input may be strobed or hard wired to +5V.

9

VDD

Power Supply

+ 12 volt Supply

10

NC

No Connection

Internally bonded. Do not connect anything to this
pin.

11

GND

Ground

Ground

12

STT

Strobe-Transmitter
Address

A high-level input strobe loads the transmitter address
(TA. TB, TQ, TD) into the transmitter address register.
This input may be strobed or hard wired to +5V.

TD, TC, TB, TA

Transmitter
Address

The logic level on these inputs, as shown in Tables 1
through 6, selects the transmitter output frequency, fj.

17

*T

Transmitter
Output
Frequency

This output runs at a frequency selected
Transmitter Address inputs.

18

XTAL/EXT 2

Crystal or
External
Input 2

This input receives the other pin of the crystal
package or the other polarity of the external input.

4-7

13-16

V

by the

C
NOTE 1

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CRYSTAL OPERATION

STROBE
(STR/STT)
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74XX - TOTEM POLE OR OPEN COLLECTOR OUTPUT

TPW TIME OF THE INPUT STROBE

CONTROL TIMING

CRYSTAUCLOCK OPTIONS

ABSOLUTE MAXIMUM RATINGS
Positive Voltage on any Pin, with respect to ground

-f 20.0V

Negative Voltage on any Pin, with respect to ground

-0.3V
(plastic package) -55°Cto +125°C
(cerdip package and ceramic package) - 65°C to + 150°C

Storage Temperature

Lead Temperature (Soldering, 10 sec.)
•Stresses above those listed may cause permanent damage to the device. This is a stress
rating only and Functional Operation of the device at these or at any other condition
above those indicated in the operational sections of this specification are not implied.

390

+ 325°C

ELECTRICAL CHARACTERISTICS

DO

(TA = 0°C to -I- 70°C, Vcc = + 5V ± 5%, VDD = -I- 12V ± 5%, unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

COMMENTS

DC CHARACTERISTICS

CD

INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, VIH

VcC-1-5

OUTPUT VOLTAGE LEVELS
Low-level, VQL
High-level, VQH

VcC-1-5

0.8

VCG
0.4
4.0

INPUT CURRENT
Low- level, l||_
IN PUT CAPACITANCE
All Inputs, CIN
INPUT RESISTANCE
Crystal Input, R/TAL

2

V
V

See Note 1

V
V

IQL = 3.2 mA

IOH = 10(VA

0.3

mA

VIN = GND, excluding XTAL inputs

10

pf

VIM = GND, excluding XTAL inputs

KQ

Resistance to ground for
Pin 1 and Pin 18

5
1.1

POWER SUPPLY CURRENT

•cc
IDD

20
20

60
70

mA
mA

AC CHARACTERISTICS

TA = +25°C

CLOCK FREQUENCY

See Note 2

PULSE WIDTH (Tpw)
Clock
Receiver strobe
Transmitter strobe

150
150

INPUT SET-UP TIME (TsET-UP)
Address

50

ns

OUTPUT HOLD TIME 0"HOLD)
Address

50

ns

50% duty cycle ± 10%. See Note 2

DC
DC

ns
ns
See Note 3

NOTE1: BR1941 — XTAL/EXT inputs are either TTL compatible or crystal compatible. See crystal specification in Applications Information section.
All inputs except XTAUEXT have internal pull-up resistors.
NOTE 2: Refer to frequency option tables for maximum input frequency on XTAL/EXT pins.
Typical Clock Pulse width is 1/2xCL
NOTE 3: Input set-up time can be decreased to ^0 ns by increasing the minimum strobe width by 50 ns to a total of 200 ns.

OPERATION

Non-Standard Frequencies

Standard Frequencies

To accomplish non-standard frequencies do one of the
following:

Choose a Transmitter and Receiver frequency from the
table below. Program the corresponding address into TATD and RA-RD respectively using strobe pulses or by hard
wiring the strobe and address inputs.

1. Choose a crystal that when divided by the BR1941
generates the desired frequency.
2. Cascade devices by using the frequency outputs as an

391

CD
3

input to the XTAUEXT inputs of the subsequent
BR1941.

3. Consult the factory for possible changes via ROM mask
reprogramming.

FREQUENCY OPTIONS
TABLE 1. CRYSTAL FREQUENCY = 5.0688 MHZ

D
0
0
0
0
0
0
0
0

1

Transmit/Receive
Address
B
c
0
0
0
0
1
0
1
0
1
0
1
0

A
0

1

0

1

0

1

1
1

1
1

0

0
0
0
0

0
0

0

1
1
1
1

1
1

1
1

0

0
0

0

1

1

1
1

0

1

Baud
Rate
(16X Clock)
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19,200

Theoretical
Freq. (kHz)
0.8
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2

Actual
Freq. (kHz)
0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8

Percent
Error
—
0.016
—
—
—
—
—
0.253
—
—
—
3.125

Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
48/52
50/50

Divisor
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

Percent
Error
—
—
-0.006
-0.019
—
—
—
—
—
+ 0.465
—
-

Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50

Divisor
3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9

Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50

Divisor
7523*
5015*
3420
2797'
2508
1881*
1254
627'
31.3*
209'
188
157'
104
78
39"
20

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BR1941-00
TABLE 2. CLOCK FREQUENCY = 2.76480 MHZ

D
0
0
0
0
0
0
0
0

1
1

1

Transmit/Receive
Address
B
c
0
0
0
0
1
0
1
0
1
0
1
0

1

A
0

1
0

1
0

1

1
1

0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1

1
1

1

1
1

Baud
Rate
(16X Clock)
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
9600
19,200

Theoretical
Freq. (kHz)
0.8
1.2
1.76
2.152
2.4
3.2
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
153.6
307.2

Actual
Freq. (kHz)
0.8
1.2
1.76
2.152
2.4
3.2
4.8
9.6
19.2
28.8
32.15
38.4
57.6
76.8
153.6
307.2

o

BR1941-02
TABLE 3. CRYSTAL FREQUENCY = 6.018305 MHZ

D
0
0
0
0
0
0
0
0

1
1
1
1

1
1
1
1

Transmit/Receive
Address
B
c
0
0
0
0
1
0
1
0
1
0
1
0

1

1
0
0
0
0

1
1

1
1

A
0

1
0

1

0

1

1
1

0

0
0

0

1
1

0

0
0

0

1
1

1

1
1

1

0

1

Baud
Rate
Theoretical
(16X Clock) Freq. (kHz)
50
0.8
75
1.2
110
1.76
134.5
2.152
150
2.4
200
3.2
300
4.8
600
9.6
1200
19.2
1800
28.8
2000
32.0
2400
38.4
3600
57.6
4800
76.8
9800
153.6
19,200
307.2

BR1941-03

392

Actual
Freq. (kHz)
.7999
1.2000
1.7597
2.1517
2.3996
3.1995
4.7993
9.5986
19.2279
28.7959
32.0125
38.3334
57.8687
77.1583
154.3166
300.9175

Percent
Error
0
0
0
0
0
0
0
0
-1-0.14
0
0
-0.17
+ 0.46
-1-0.46
-»-0.46
-2.04

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i

D

TABLE 4. CLOCK FREQUENCY = 5.52960 MHZ

D
0
0
0
0
0
0
0
0

Transmi I/Receive
Address
B
C
0
0
0
0
0

1
1
1
1

0
0
0
0

1
1

1
1
1
1

0
1
1
0
0

A
0

1

0

1

0

1

1
1

0

0
0

0

1

1

1
1

0

0
0

0

1
1

1

1

0

1

Baud
Rate
Theoretical
(16X Clock) Freq. (kHz)
50
1.6
75
2.4
110
3.52
134.5
4.304
150
4.8
200
6.4
300
9.6
600
19.2
1200
38.4
1800
57.6
2000
64.0
2400
76.8
3600
115.2
4800
153.6
9600
307.2
19,200
614.4

Actual
Freq. (kHz)
1.6
2.4
3.52
4.303
4.8
6.4
9.6
19.2
38.4
57.6
64.3
76.8
115.2
153.6
307.2
614.4

Percent
Error
-0.006
-0.019
—
—
—
-1-0.465
—
—
—
-

Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50

Divisor
3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9

BR1941-04

TABLE 5. CRYSTAL FREQUENCY = 4.9152 MHZ
Transmit/Receive
Address

D
0
0
0
0
0
0
0
0

1
1

1

C
0
0
0
0

B
0
0

A
0

1

0

1
1
1
1

1
1

0
0

0

1
1

0

0
0
0
0

0
0

0

1
1
1
1

1
1
1

1

1
1

0

0
0

0

1
1

1

1

0

1

Baud
Rate
Theoretical
(32X Clock) Freq. (kHz)
50
0.8
75
1.2
110
1.76
134.5
2.152
150
2.4
300
4.8
600
9.6
1200
19.2
1800
28.8
2000
32.0
2400
38.4
3600
57.6
4800
76.8
7200
115.2
9600
153.6
19,200
307.2

Actual
Freq. (kHz)
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
57.8258
76.8
114.306
153.6
307.2

Percent
Error
—
-0.01
—
—
-0.19
-0.26
—
0.39
—
-0.77
-

Duty
Cycle
%
50/50
50/50
*
50/50
50/50
50/50
50/50
50/50
*
50/50
50/50
*
50/50
*
50/50
50/50

Divisor
6144
4096
2793
2284
2048
1024
512
256
171
154
128
85
64
43
32
16

Percent
Error
—
.026
—
—
—
—
—
—
—
—
—
2.941
3.125

Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
'
50/50
*
50/50

Divisor
3168
2112
1440
1178
1056
792
528
264
132
88
66
44
33
22
17
8

BR1941-05
TABLE 6. CRYSTAL FREQUENCY = 5.0688 MHZ
Transmit/Receive
Address

D
0
0
0
0
0
0
0
0

1

C
0
0
0
0

B
0
0

0

1
1
1

1
1

0
0

0

1
1

0

0
0
0
0

0
0

0

1

1
1
1
1

A
0

1

1
1
1
1

1

0

0
0

0

1

1
1

1
1

0

1

•When the duty cycle is not exactly 50% it

Baud
Rate
Theoretical
(32X Clock) Freq. (kHz)
50
1.6
75
2.4
110
3.52
134.5
4.304
150
4.8
200
6.4
300
9.6
600
19.2
1200
38.4
1800
57.6
2400
76.8
3600
115.2
4800
153.6
7200
230.4
9600
307.2
19,200
614.4
is 50% ± 10%
BR1941-06

393

Actual
Freq. (kHz)
1.6
2.4
3.52
4.303
4.8
6.4
9.6
19.2
38.4
57.6
76.8
115.2
153.6
230.4
298.16
633.6

CD
DO

I
I
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Bliley Electric Co.
2545 Grandview Blvd.
Erie, Pennsylvania 16508
(814)838-3571

CRYSTAL SPECIFICATIONS
User must specify termination (pin, wire, other)
Frequency — See Tables 1-6.
Temperature range 0°C to + 70° C
Sehes resistance < 50Q
Series resonant
Overall tolerance ± .01%
CRYSTAL MANUFACTURERS (Partial List)

M-tron Ind. Inc.
P.O. Box 630
Yankton, South Dakota 57078
(605)665-9321

American Time Products Div.
Frequency Control Products, Inc.
61-20WoodsideAve.
Woodside, New York 11377
(212)458-5811

Erie Frequency Control
453 Lincoln St.
Calisle, Pennsylvania 17013
(714)249-2232

V

APPLICATIONS INFORMATION
OPERATION WITH A CRYSTAL

a parallel ground lines
b. evenly spaced ground lines crossing the trace on the
opposite side of PC board
c. an inner plane of ground, e.g., as in a four layered PC
board.

The BR1941 Baud Rate Generator may be driven by either a
crystal or TTL level clock. When using a crystal, the waveform that appears at pins 1 (XTAUEXT1) and 18 (XTAUEXT
2) does not conform to the normal TTL limits of VIL < 0.8V
and VIH > 2.0V. Figure 1 illustrates a typical crystal
waveform when connected to a BR1941.

In the event that ringing exists on an already finished
board, several techniques can be used to reduce it. These
are:

Since the D.C. level of the waveform causes the least
positive point to typically be greater than 0.8V, the BR1941
is designed to look for an edge, as opposed to a TTL level.
The XTAUEXT logic triggers on a rising edge of typically 1V
in magnitude. This allows the use of a crystal without any
additional components.

1. Add a series resistor to match impedance as shown in
Figure 3.
2. Add pull-up/pull-down resistor to match impedance, as
shown in Figure 4.
3. Add a high speed diode to clamp undershoot, as shown
in Figure 5.

OPERATIONS WITH TTL LEVEL CLOCK
With clock frequencies in the area of 5 MHz, significant
overshoot and undershoot ("ringing") can appear at pins 1
and/or 18. The BR1941, may, at times, be triggered on a
rising edge of an overshoot or undershoot waveform,
causing the device to effectively "double-trigger." This
phenomenon may result as a twice expected baud rate, or
as an apparent device failure. Figure 2 shows a typical
waveform that exhibits the "ringing" problem.

o

The method that is easiest to implement in many systems
is method 1, the series resistor. The series resistor will
cause the D.C. level to shift up, but that does not cause a
problem since the BR1941 is triggered by an edge, as
opposed to a TTL level.
The BR1941 Baud Rate Generator can save both board
space and cost in a communications system. By choosing
either a crystal or a TTL level clock, the user can minimize
the logic required to provide baud rate clocks in a given
design.

The design methods required to minimize ringing include
the following:
1. Minimize the P.C. trace length. At 5 MHz, each inch of
trace can add significantly to overshoot and undershoot.
2. Match impedances at both ends of the trace. For
example, a series resistor near the BR1941 may be
helpful.
3. A uniform impedance is important. This can be accomplished through the use of:

POWER LINE SPIKES
Voltage transients on the AC power line may appear on the
DC power output. If this possibility exists, it is suggested
that one by-pass capacitor is used between + 5V and GND
and another between + 12V and GND.

394

w

09
ID
CD
£*
20- •

10 -

4X

T

2T

3T

\7

4T

Figure 1 TYPICAL CRYSTAL WAVEFORM

Figure 2 TYPICAL "RINGING" WAVEFORM

R2

PX^VVVV
R1

Typical Values
R1 = R 2 - 3 3 $ l

Figure 3 SERIES RESISTOR TO MATCH IMPEDANCE

+sv

Typical Values
R1 = R3 = ? 7K
R2 = R4 - 3 3K

Figure 4 PULL-UP/PULL-DOWN RESISTORS TO MATCH IMPEDANCE

Figure 5 HIGH-SPEED DIODE TO CLAMP UNDERSHOOT

See page 725 for ordering information.

395

1
0>

v

O

Information furnished by Western Digital Corporation is believed to be accurate and reliable However no responsibility is assumed by Western Digital
Corporation for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation Western Digital Corporation reserves the right to change
specifications at anytime without notice

396

Printed in U S A

w

WESTERN
C

O

R

P

O

R

DIGITAL
A

T

I

O

N

3
WD1943(8116)/WD1945(8136) Dual Baud Rate Clock

i

FEATURES

GENERAL DESCRIPTION

• 16 SELECTABLE BAUD RATE CLOCK FREQUENCIES

The WD1943/45 is an enhanced version of the BR1941 Dual
Baud Rate Clock The WD1943/45 is a combination Baud
Rate Clock Generator and Programmable Divider It is
manufactured in N-channel MOS using silicon gate
technology This device is capable of generating 16 externally selected clock rates whose frequency is determined by either a single crystal or an externally generated
input clock The WD1943/45 is a programmable counter
capable of generating a division by any integer from 4 to
2 15 — 1, inclusive

•OPERATES WITH CRYSTAL OSCILLATOR OR EXTERNALLY GENERATED FREQUENCY INPUT
•ROM MASKABLE FOR NON-STANDARD FREQUENCY
SELECTIONS
•INTERFACES EASILY WITH MICROCOMPUTERS
• OUTPUTS A 50% DUTY CYCLE CLOCK WITH 0 01 %
ACCURACY
•6 DIFFERENT FREQUENCY/DIVISOR PAIRS
AVAILABLE

The WD1943/45 is available programmed with the most
used frequencies in data communication Each frequency
is selectable by strobing or hard wiring each of the two sets
of four Rate Select inputs Other frequencies/division rates
can be generated by reprogrammmg the internal ROM
coding through a MOS mask change Additionally, further
clock division may be accomplished through cascading of
devices The frequency output is fed into the XTAUEXT
input on a subsequent device

•SINGLE +5V POWER SUPPLY
•COMPATIBLE WITH BR1941
•TTL, MOS COMPATIBILITY
• WD1943 IS PIN COMPATIBLE TO THE COM8116
• WD1945 IS PIN COMPATIBLE TO THE COM8136 AND
COM5036 (PIN 9 ON WD1945 IS A NO CONNECT)

The WD1943/45 can be driven by an external crystal or by
TTL logic

3
XTAUEXT 1

Hi D

is n

XTAUEXT 2
 RD) into *ne receiver address register. This input may be
strobed or hard wired to + 5V.

9

NC

No Connection

No Internal Connection

10

NC(1943)
f/4(1945)

No Connection
freq/4 Output

No Internal Connection
XTAL1 input freq divided by four.

11

GND

Ground

Ground

12

STT

Strobe-Transmitter
Address

T

TD,TC,TB,TA

Transmitter
Address

The logic level on these inputs, as shown in Table 1 thru 6,
selects the transmitter output frequency, fj.

17

fr

Transmitter
Output
Frequency

This output runs at a frequency selected by the Transmitter
Address inputs.

18

XTAUEXT2

Crystal or
External
Input 2

This input receives the other pin of the crystal package or the
other polarity of the external input.

3
4-7

13-16

This input receives one pin of the crystal package or one
polarity of the external input.

A high-level input strobe loads the transmitter address (TA,
B> TC> TD) into the transmitter address register. This input
may be strobed or hard wired to + 5V.

EXTERNAL INPUT OPERATION
WD1943/45

CRYSTAL OPERATION
WD1943/45
STROBE
(STR/STT)

/

CRYSTAL

T

r^r\

HOLD

L-Ci

isD-l

fs^

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183-1

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™Lx>4-[>>-c 1

18 >J

.

VIM

DRESS
V,L

e

\
^
74XX TOTEM POLE OR OPEN COLLECTOR OUTPUT

•ADDRESS NEED ONLY BE VALID DURING THE LAST
TPW TIME OF THE INPUT STROBE

CONTROL TIMING

CRYSTAL/CLOCK OPTIONS

ABSOLUTE MAXIMUM RATINGS
Positive Voltage on any Pin, with respect to ground

-I-7.0V

Negative Voltage on any Pin, with respect to ground

-0.3V

Storage Temperature

(plastic package) - 55°C to + 125°C
(Cerdip package and Ceramic package) - 65°C to + 150°C

Lead Temperature (Soldering, 10 sec.)

+ 325°C

*Stresses above those listed may cause permanent damage to the device. This is a stress
rating only and Functional Operation of the device at these or at any other condition
above those indicated in the operational sections of this specification are not implied.

398

 2.0V. Figure 1 illustrates a typical
crystal waveform when connected to a WD1943/45.

«

The 1943/45 Baud Rate Generator can save both board
space and cost in a communications system. By choosing
either a crystal or a TTL level clock, the user can minimize
the logic required to provide baud rate clocks in a given
design.

Since the D.C. level of the waveform causes the least
positive point to typically be greater than 0.8V, the
WD1943/45 is designed to look for an edge, as opposed to a
TTL level. The XTAUEXT logic triggers on a rising edge of
typically 1V in magnitude. This allows the use of a crystal
without any additional components.

POWER LINE SPIKES

OPERATIONS WITH TTL LEVEL CLOCK
With clock frequencies in the area of 5 MHz, significant
overshoot and undershoot ("ringing") can appear at pins 1
and/or 18. The clock oscilator may, at times be triggered on
a rising edge of an overshoot or undershoot waveform,
causing the device to effectively "double-trigger." This
phenomenon may result as a twice expected baud rate, or
as an apparent device failure. Figure 2 shows a typical
waveform that exhibits the "ringing" problem.

Voltage transients on the AC power line may appear on the
DC power output. If this possibility exists, it is suggested
that a by-pass capacitor is used between + 5V and GND.

CRYSTAL SPECIFICATIONS
User must specify termination (pin, wire, other)
Frequency — See Tables 1-6.
Temperature range 0°C to + 70°C
Series resistance < 50Q
Series resonant
Overall tolerance ± 0.01%

The design methods required to minimize ringing include
the following:
1. Minimize the P.C. trace length. At 5 MHz, each inch of
trace can add significantly to overshoot and undershoot.
2. Match impedances at both ends of the trace. For
example, a series resistor near the device may be
helpful.
3. A uniform impedance is important. This can be accomplished through the use of:
a parallel ground lines
b. evenly spaced ground lines crossing the trace on the
opposite side of PC board
c. an inner plane of ground, e.g., as in a four layered PC
board.

CRYSTAL MANUFACTURERS (Partial List)
American Time Products Div.
Frequency Control Products, Inc.
61-20WoodsideAve.
Woodside, New York 11377
(213)458-5811

o

Bliley Electric Co.
2545 Grandview Blvd.
Erie, Pennsylvania 16508
(814)838-3571

In the event that ringing exists on an already finished
board, several techniques can be used to reduce it. These
are:

M-tron Ind. Inc.
P.O. Box 630
Yankton, South Dakota 57078
(605)665-9321

1. Add a series resistor to match impedance as shown in
Figure 3.
2. Add pull-up/pull-down resistor to match impedance, as
shown in Figure 4.
3. Add a high speed diode to clamp undershoot, as shown
in Figure 5.

Erie Frequency Control
453 Lincoln St.
Calisle, Pennsylvania 17013
(714)249-2232

402

«•

^G

<

c

G
Figure 1. TYPICAL CRYSTAL WAVEFORM

Figure 2. TYPICAL "RINGING" WAVEFORM
from TTL INPUT

{>0

*U

Typical^Values
R1 = R2 = 33Q

Figure 3. SERIES RESISTOR TO MATCH IMPEDANCE

Typical Values
R3 = 2TK
R2 = R4 = 3 3K
R1~=

Figure 4. PULL-UP/PULL-DOWN RESISTORS TO MATCH IMPEDANCE

Figure 5. HIGH-SPEED DIODE TO CLAMP UNDERSHOOT

See page 725 for ordering information.
403

^

«

o
Information furnished by Western Digital Corporation is believed to be accurate and reliable However, no responsibility is assumed by Western Digital
Corporation for its use, nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation Western Digital Corporation reserves the right to change
specifications at anytime without notice

404

Printed in U S A

w

WESTS itIV DIGITAL
C

O

R

P

O

R

A

T

/

O

N

FD179X-02
Floppy Disk Formatter/Controller Family
• PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Side Select Compare
• INTERFACES TO WD1691 DATA SEPARATOR
• WINDOW EXTENSION
• INCORPORATES ENCODING/DECODING AND
ADDRESS MARK CIRCUITRY
• FD1792/4 IS SINGLE DENSITY ONLY
• FD179517 HAS A SIDE SELECT OUTPUT

FEATURES
•
•
•
•

TWO VFO CONTROL SIGNALS — RG & VFOE
SOFT SECTOR FORMAT COMPATIBILITY
AUTOMATIC TRACK SEEK WITH VERIFICATION
ACCOMMODATES SINGLE AND DOUBLE DENSITY
FORMATS
IBM 3740 Single Density (FM)
IBM System 34 Double Density (MFM)
Non IBM Format for Increased Capacity
• READ MODE
Single/Multiple Sector Read with Automatic Search or
Entire Track Read
Selectable 128,256,512 or 1024 Byte Sector Lengths
• WRITE MODE
Single/Multiple Sector Write with Automatic Sector
Search
Entire Track Write for Diskette Formatting
• SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus for
Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
OrvChip Track and Sector Registers/Comprehensive
Status Information

179X-02 FAMILY CHARACTERISTICS
FEATURES
Single Density (FM)
Double Density (MFM)
True Data Bus
Inverted Data Bus
Write Precomp
Side Selection Output

1791

1792

1793

1794

1795

1797

X
X

X

X
X
X

X

X
X

X
X
X

X

X

X
X

X
X

X
X

8" FLOPPY AND 51/4" MINI FLOPPY CONTROLLER
SINGLE OR DOUBLE DENSITY
CONTROLLER/ FORMATTER
_
DATA (8)

RAW READ

^>

RCLK
RG/SSO

AO

c

A1

LATE

0
M
P

CS

EARLY

RE

wo

U
T
E
R

WE

*

^
p

+5

^

MR

>10K

179X

FLOPPY DISK
CONTROLLER
FORMATTER

I

EARLY £

X
X
X

APPLICATIONS

2

1

0

7

6

5

4

n

TO
TO
TO
TO

0
0
0
0
0

0
0
0

0
0

1

0

1

1

1
0
0

0

1
1
1

0

1

0

0
1
T
T
T
m
m
0
0
1
1

M
M
M
M
C
C
0
0
0

rfj
0
ao
0
0
0

h

"o

1
1
1
1
1

1

1

1
1

3
h
h
h
h
h
L
L
0
0
0
13

2
V
V
V
V
V
E
E
E
E
E
l2

1
M
M

M
n
n

u
u
u
u
u

"1

TABLE 2. FLAG SUMMARY

FLAG SUMMARY

^N

4

5

Command
Type

Bit
No(s)

I

0,1

I

2

V = Track Number Verify Flag V = 0, No verify
V = 1, Verify on destination track

1

3

h = Head Load Flag

h =1, Load head at beginning
h = 0, Unload head at beginning

1

4

T = Track Update Flag

T = 0, No update
T = 1, Update track register

ii

0

ao = Data Address Mark

ao = 0, FB(DAM)
ao = 1, F8 (deleted DAM)

1!

1

C = Side Compare Flag

C = 0, Disable side compare
C = 1, Enable side compare

II & III

1

U = Update SSO

U = 0, Update SSO toO
U = 1, Update SSO to 1

II & III

2

E = 15 MS Delay

E = 0, No 15 MS delay
E = 1,15 MS delay

II

3

S = Side Compare Flag

S = 0, Compare for side 0
S = 1 , Compare for side 1

H

3

L = Sector Length Flag

Description
r

1 rO = Stepping Motor Rate
See Table 3 for Rate Summary

LSB's Sector Length in ID Field
00
01
10
11
L = 0
L = 1

II

4

IV

0-3

m = Multiple Record Flag
'x
'0
h
'2
'3
'3-lQ

256
128

m = 0, Single record
m = 1, Multiple records

= Interrupt Condition Flags
= 1 Not Ready To Ready Transition
= 1 Ready To Not Ready Transition
= 1 1ndex Pulse
= 1 Immediate Interrupt, Requires A Reset
= 0 Terminate With No Interrupt (INTRQ)

*NOTE: See Type IV Command Description for further information.

512
256

1024
512

128
1024

0

TO
ro
rrj

TO
'0
0
ao
0
0
0

«o

Head Load timing (HLT) is an input to the FD179X which is
used for the head engage time. When HLT = 1, the FD179X
assumes the head is completely engaged. The head
engage time is typically 30 to 100 ms depending on drive.
The low to high transition on HLD is typically used to fire a
one shot. The output of the one shot is then used for HLT
and supplied as an input to the FD179X.

TYPE I COMMANDS
The Type I Commands include the Restore, Seek, Step,
Step-in, and Step-Out commands. Each of the Type I
Commands contains a rate field (ro r1), which determines
the stepping motor rate as defined in Table 3.
A 2 MS (MFM) or 4 f-is (FM) pulse is provided as an output to
the drive. For every step pulse issued, the drive moves one
track location in a direction determined by the direction
output. The chip will step the drive in the same direction it
last stepped unless the command changes the direction.

HLD f-

The Direction signal is active high when stepping in and
low when stepping out. The Direction signal is valid 12 ^s
before the first stepping pulse is generated.

-50 TO 100mS-

The rates (shown in Table 3) can be applied to a StepDirection Motor through the device interface.

HLT (FROM ONE SHOT)

TABLE 3. STEPPING RATES
CLK

2 MHz

2 MHz

1 MHz

1 MHz

DDEN

0

1

0

1

R1 RO

TEST=1

TEST=1

TEST=1

TEST=1

0

0

1

6 ms

6 ms

12 ms

1

0

10 ms

10 ms

20 ms

30 ms

1

1

3 ms

15 ms

3 ms

15 ms

6 ms

6 ms

0

30 ms

V

HEAD LOAD TIMING

2 MHz
X
TEST=0

1 MHz

When both HLD and HLT are true, the FD179X will then
read from or write to the media. The "and" of HLD and HLT
appears as status Bit 5 in Type I status.

X
TEST=0

184Ms

368/iS

12 ms

190/us

38(Vs

20 ms

198/ms

396Ms

208^5

416/iS

In summary for the Type I commands: if h = 0 and V = 0,
HLD is reset. If h = 1 and V = 0, HLD is set at the
beginning of the command and HLT is not sampled nor is
there an internal 15 ms delay. If h = 0 and V = 1, HLD is
set near the end of the command, an internal 15 ms occurs,
and the FD179X waits for HLT to be true. If h = 1 and V =
1, HLD is set at the beginning of the command. Near the
end of the command, after all the steps have been issued,
an internal 15 ms delay occurs and the FD179X then waits
for HLT to occur.

After the last directional step an additional 15 milliseconds
of head settling time takes place if the Verify flag is set in
Type I commands. Note that this time doubles to 30 ms for
a 1 MHz clock. If TEST = 0, there is zero settling time.
There is also a 15 ms head settling time if the E flag is set in
any Type II or III command.

For Type II and III commands with E flag off, HLD is made
active and HLT is sampled until true. With E flag on, HLD is
made active, an internal 15 ms delay occurs and then HLT
is sampled until true.

When a Seek, Step or Restore command is executed an
optional verification of Read-Write head position can be
performed by settling bit 2 (V = 1) in the command word to
a logic 1. The verification operation begins at the end of the
15 millisecond Settling time after the head is loaded against
the media The track number from the first encountered ID
Field is compared against the contents of the Track
Register. If the track numbers compare and the ID Field
Cyclic Redundancy Check (CRC) is correct, the verify
operation is complete and an INTRQ is generated with no
errors. If there is a match but not a valid CRC, the CRC error
status bit is set (Status bit 3), and the next encountered ID
field is read from the disk for the verification operation.

o

RESTORE (SEEK TRACK 0)

The FD179X must find an ID field with correct track number
and correct CRC within 5 revolutions of the media;
otherwise the seek error is set and an INTRQ is generated.
If V = 0, no verification is performed.

Upon receipt of this command the Track 00 (TROO) input is
sampled. If TROO is active low indicating the Read-Write
head is positioned over track 0, the Track Register is loaded
with zeroes and an interrupt is generated. If TROO is not
active low, stepping pulses (pins 15 to 16) at a rate specified
by the r1 rO field are issued until the TROO input is activated.
At this time the Track Register is loaded with zeroes and an
interrupt is generated. If the TROO input does not go active
low after 255 stepping pulses, the FD179X terminates
operation, interrupts, and sets the Seek error status bit,
providing the V flag is set. A verification operation also
takes place if the V flag is set. The h bit allows the head to
be loaded at the start of command. Note that the Restore
command is executed when MR goes from an active to an
inactive state and that the DRQ pin stays low.

The Head Load (HLD) output controls the movement of the
read/write head against the media HLD is activated at the
beginning of a Type I command if the h flag is set (h = 1), at
the end of the Type I command if the verify flag (V = 1), or
upon receipt of any Type II or III command. Once HLD is
active it remains active until either a Type I command is
received with (h = 0 and V = 0); or if the FD179X is in an
idle state (non-busy) and 15 index pulses have occurred.

This command assumes that the Track Register contains
the track number of the current position of the Read-Write
head and the Data Register contains the desired track
number. The FD179X will update the Track register and
issue stepping pulses in the appropriate direction until the
contents of the Track register are equal to the contents of

SEEK

8

«.

(

FFH TO TR

^

0 0

TYPE I COMMAND FLOW

TYPE I COMMAND FLOW

the Data Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An interrupt
is generated at the completion of the command. Note:
When using multiple drives, the track register must be
updated for the drive selected before seeks are issued.

flag is on, the Track Register is incremented by one. After a
delay determined by the r1rO field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.

STEP

STEP-OUT

Upon receipt of this command, the FD179X issues one
stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command.
After a delay determined by the r1rO field, a verification
takes place if the V flag is on. If the U flag is on, the Track
Register is updated. The h bit allows the head to be loaded
at the start of the command. An interrupt is generated at
the completion of the command.

Upon receipt of this command, the FD179X issues one
stepping pulse in the direction towards track 0. If the U flag
is on, the Track Register is decremented by one. After a
delay determined by the r1rO field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
EXCEPTIONS

STEP-IN

On the 1795/7 devices, the SSO output is not affected
during Type 1 commands, and an internal side compare
does not take place when the (V) Verify Flag is on.

Upon receipt of this command, the FD179X issues one
stepping pulse in the direction towards track 76. If the U

9

then located and will be either written into, or read from
depending upon the command. The FD179X must find an
ID field with a Track number, Sector number, side number,
and CRC within four revolutions of the disk; otherwise, the
Record not found status bit is set (Status bit 3) and the
command is terminated with an interrupt.

VERIFY
SEQUENCE

V

o
NOTE JP

= 0. THERE IS NO 15MS DELAY
; 1 AND CLK = 1 MHz. THERE IS A 30MS DELAY

TYPE I COMMAND FLOW
TYPE II COMMANDS
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command
into the Command Register, the computer must load the
Sector Register with the desired sector number. Upon
receipt of the Type II command, the busy status Bit is set. If
the E flag = 1 (this is the normal case) HLD is made active
and HLT is sampled after a 15 msec delay. If the E flag is 0,
the head is loaded and HLT sampled with no 15 msec
delay. The ID field and Data Field format are shown on page
13.
When an ID field is located on the disk, the FD179X
compares the Track Number on the ID field with the Track
Register. If there is not a match, the next encountered ID
field is read and a comparison is again made. If there was a
match, the Sector Number of the ID field is compared with
the Sector Register. If there is not a Sector match, the next
encountered ID field is read off the disk and comparisons
again made. If the ID field CRC is correct, the data field is

/INTRO RESET BUSY\
ISET WRITE PROTECT^

•NOTE IF TEST = 0. THERE IS NO 15MS DELAY
IF TEST = 1 AND CLK = 1 MHz THERE IS 30MS DELAY

TYPE II COMMAND
Each of the Type II Commands contains an (m) flag which
determines if multiple records (sectors) are to be read or
written, depending upon the command. If m = 0, a single
sector is read or written and an interrupt is generated at the
completion of the command. If m = 1, multiple records are
read or written with the sector register internally updated
so that an address verification can occur on the next

10

w

record. The FD179X will continue to read or write multiple
records and update the sector register in numerical
ascending sequence until the sector register exceeds the
number of sectors on the track or until the Force Interrupt
command is loaded into the Command Register, which
terminates the command and generates an interrupt.

The Type II and III commands for the 1795-97 contain a side
select flag (Bit 1). When U = 0, SSO is updated to 0.
Similarly, U = 1 updates SSO to 1. The chip compares the
SSO to the ID field. If they do not compare within 5
revolutions the interrupt line is made active and the RNF
status bit is set.

For example: If the FD179X is instructed to read sector 27
and there are only 26 on the track, the sector register exceeds the number available. The FD179X will search for 5
disk revolutions, interrupt out, reset busy, and set the
record not found status bit.

The 1795/7 READ SECTOR and WRITE SECTOR commands include a '!_' flag. The 'L' flag, in conjunction with
the sector length byte of the ID Field, allows different byte
lengths to be implemented in each sector. * For IBM
Compatability, the 'U flag should be set to a one.

The Type II commands for 1791-94 also contain side select
compare flags. When C = 0 (Bit 1) no side comparison is
made. When C = 1, the LSB of the side number is read off
the ID Field of the disk and compared with the contents of
the (S) flag (Bit 3). If the S flag compares with the side
number recorded in the ID field, the FD179X continues with
the ID search. If a comparison is not made within 5 index
pulses, the interrupt line is made active and the RecordNot-Found status bit is set.

READ SECTOR
Upon receipt of the Read Sector command, the head is
loaded, the Busy status bit set, and when an ID field is
encountered that has the correct track number, correct
sector number, correct side number, and correct CRC, the
data field is presented to the computer. The Data Address

READ SECTOR
SEQUENCE

[
I

INTRO RESET BUSY
SET CRC ERROR

A
J
I

TYPE II COMMAND

«

TYPE II COMMAND

11

I

( INTRO RESET BUSY J

STATUS
BITS

WRITE SECTOR
SEQUENCE

1
0

Deleted Data Mark
Data Mark

WRITE SECTOR
Upon receipt of the Write Sector command, the head is
loaded (HLD active) and the Busy status bit is set. When an
ID field is encountered that has the correct track number,
correct sector number, correct side number, and correct
CRC, a DRQ is generated. The FD179X counts off 11 bytes
in single density and 22 bytes in double density from the
CRC field and the Write Gate (WG) output is made active if
the DRQ is serviced (i.e., the DR has been loaded by the
computer). If DRQ has not been serviced, the command is
terminated and the Lost Data status bit is set. If the DRQ
has been serviced, the WG is made active and six bytes of
zeroes in single density and 12 bytes in double density are
then written on the disk. At this time the Data Address
Mark is then written on the disk as determined by the ao
field of the command as shown below:

v

Data Address Mark (Bit 0)

an
1
0

Deleted Data Mark
Data Mark

The FD179X then writes the data field and generates DRQ's
to the computer. If the DRQ is not serviced in time for
continuous writing the Lost Data Status Bit is set and a
byte of zeroes is written on the disk. The command is not
terminated. After the last data byte has been written on the
disk, the two-byte CRC is computed internally and written
on the disk followed by one byte of logic ones in FM or in
MFM. The WG output is then deactivated. For a 2 MHz
clock the INTRQ will set 8 to 12 ^sec after the last CRC byte
is written. For partial sector writing, the proper method is to
write the data and fill the balance with zeroes. By letting the
chip fill the zeroes, errors may be masked by the lost data
status and improper CRC Bytes.

o

TYPE III COMMANDS

TYPE II COMMAND
Mark of the data field must be found within 30 bytes in
single density and 43 bytes in double density of the last ID
field CRC byte; if not, the ID field is searched for and
verified again followed by the Data Address Mark search. If
after 5 revolutions the DAM cannot be found, the Record
Not Found status bit is set and the operation is terminated.
When the first character or byte of the data field has been
shifted through the DSR, it is transferred to the DR, and
DRQ is generated. When the next byte is accumulated in
the DSR, it is transferred to the DR and another DRQ is
generated. If the Computer has not read the previous
contents of the DR before a new character is transferred
that character is lost and the Lost Data Status bit is set.
This sequence continues until the complete data field has
been inputted to the computer. If there is a CRC error at the
end of the data field, the CRC error status bit is set, and the
command is terminated (even if it is a multiple record
command).
At the end of the Read operation, the type of Data Address
Mark encountered in the data field is recorded in the Status
Register (Bit 5) as shown:

READ ADDRESS
Upon receipt of the Read Address command, the head
is loaded and the Busy Status Bit is set. The next
encountered ID field is then read in from the disk, and
the six data bytes of the ID field are assembled and
transferred to the DR, and a DRQ is generated for each
byte. The six bytes of the ID field are shown below:

TRACK
ADDR

SIDE
NUMBER

SECTOR
ADDRESS

SECTOR
LENGTH

1

2

3

4

CRC CRC
1
2
5

6

Although the CRC characters are transferred to the
computer, the FD179X checks for validity and the CRC
error status bit is set if there is a CRC error. The Track
Address of the ID field is written into the sector
register so that a comparison can be made by the
user. At the end of the operation an interrupt is
generated and the Busy Status is reset.

12

v

READ TRACK

i

is not activated during the command; no CRC checking is
performed; gap information is included in the data stream;
the internal side compare is not performed; and the address mark detector is on for the duration of the command.
Because the A.M. detector is always on, write splices or
noise may cause the chip to look for an A.M. If an address
mark does not appear on schedule the Lost Data status flag
is set.

Upon receipt of the READ track command, the head is
loaded, and the Busy Status bit is set. Reading starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse. All Gap, Header, and
data bytes are assembled and transferred to the data
register and DRQ's are generated for each byte. The accumulation of bytes is synchronized to each address mark
encountered. An interrupt is generated at the completion of
the command.

The ID A.M., ID field, ID CRC bytes, DAM, Data, and Data
CRC Bytes for each sector will be correct. The Gap Bytes
may be read incorrectly during write-splice time because of
synchronization.

This command has several characteristics which make it
suitable for diagnostic purposes. They are: the Read Gate

^J

TYPE III COMMAND WRITE TRACK

TYPE III COMMAND WRITE TRACK

13

CONTROL BYTES FOR INITIALIZATION
DATA PATTERN
IN DR (HEX)
00 thru F4
F5
F6
F7
F8 thru FB
FC
FD
FE
FF

FD179X INTERPRETATION
IN FM (DDEN = 1)

FD1791/3 INTERPRETATION
IN MFM (ODER = 0)

Write 00 thru F4 with CLK = FF
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write F8 thru FB, Clk = C7, Preset CRC
Write FC with Clk = D7
Write FD with Clk = FF
Write FE, Clk = C7, Preset CRC
Write FF with Clk = FF

* Missing clock transition between bits 4 and 5

Write 00 thru F4, in MFM
Write A1* in MFM, Preset CRC
Write C2** in MFM
Generate 2 CRC bytes
Write F8 thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM

»

** Missing clock transition between bits 3 & 4

WRITE TRACK FORMATTING THE DISK

sure Type I status in the status register. This command can
be loaded into the command register at any time. If there is
a current command under execution (busy status bit set)
the command will be terminated and the busy status bit
reset.

(Refer to section on Type III commands for flow diagrams.)
Formatting the disk is a relatively simple task when
operating programmed I/O or when operating under DMA
with a large amount of memory. Data and gap information
must be provided at the computer interface. Formatting the
disk is accomplished by positioning the R/W head over the
desired track number and issuing the Write Track command.

The lower four bits of the command determine the conditional interrupt as follows:
'O
h
'2
'3

Upon receipt of the Write Track command, the head is
loaded and the Busy Status bit is set. Writing starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse, at which time the
interrupt is activated. The Data Request is activated immediately upon receiving the command, but writing will not
start until after the first byte has been loaded into the Data
Register. If the DR has not been loaded by the time the
index pulse is encountered the operation is terminated
making the device Not Busy, the Lost Data Status Bit is set,
and the Interrupt is activated. If a byte is not present in the
DR when needed, a byte of zeroes is substituted.

=
=
=
=

Not-Ready to Ready Transition
Ready to Not-Ready Transition
Every Index Pulse
Immediate Interrupt

The conditional interrupt is enabled when the corresponding bit positions of the command ('3 - '0) are set to
a 1. Then, when the condition for interrupt is met, the INTRQ line will go high signifying that the condition specified
has occurred. If '3 - '0 are all set to zero (HEX DO), no interrupt will occur but any command presently under
execution will be immediately terminated. When using the
immediate interrupt condition ('3 = 1) an interrupt will be
immediately generated and the current command terminated. Reading the status or writing to the command
register will not automatically clear the interrupt. The HEX
DO is the only command that will enable the immediate
interrupt (HEX D8) to clear on a subsequent load command
register or read status register operation. Follow a HEX D8
. with DO command.

This sequence continues from one index mark to the next
index mark. Normally, whatever data pattern appears in the
data register is written on the disk with a normal clock
pattern. However, if the FD179X detects a data pattern of
F5 thru FE in the data register, this is interpreted as data
address marks with missing clocks or CRC generation.

Wait 8 micro sec (double density) or 16 micro sec (single
density before issuing a new command after issuing a
forced interrupt (times double when clock = 1 MHz).
Loading a new command sooner than this will nullify the
forced interrupt.

The CRC generator is initialized when any data byte from
F8 to FE is about to be transferred from the DR to the DSR
in FM or by receipt of F5 in MFM. An F7 pattern will
generate two CRC characters in FM or MFM. As a consequence, the patterns F5 thru FE must not appear in the
gaps, data fields, or ID fields. Also, CRC's must be
generated by an F7 pattern.

Forced interrupt stops any command at the end of an internal micro-instruction and generates INTRQ when the
specified condition is met. Forced interrupt will wait until
ALU operations in progress are complete (CRC
calculations, compares, etc.).

Disks may be formatted in IBM 3740 or System 34 formats
with sector lengths of 128,256,512, or 1024 bytes.

More than one condition may be set at a time. If for
example, the READY TO NOT-READY condition (h = 1)
and the Every Index Pulse ('2 = 1) are both set, the
resultant command would be HEX "DA". The "OR" function is performed so that either a READY TO NOT- READY
or the next Index Pulse will cause an interrupt condition.

TYPE IV COMMANDS
The Forced Interrupt command is generally used to terminate a multiple sector read or write command or to in-

14

o

c

READ TRACK
SEQUENCE

D

•If TEST= f NO DELAY
M TEST=1 and CLK=1 MHZ. 30 MS DELAY

TYPE III COMMAND
Read Track/Address

18

STATUS REGISTER

Upon receipt of any command, except the Force Interrupt
command, the Busy Status bit is set and the rest of the
status bits are updated or cleared for the new command. If
the Force Interrupt Command is received when there is a
current command under execution, the Busy status bit is
reset, and the rest of the status bits are unchanged. If the
Force Interrupt command is received when there is not a
current command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or cleared.
In this case, Status reflects the Type I commands.

READ ADDRESS
SEQUENCE

RESET BUSY
SET INTRO
SET RNF

J

v

The user has the option of reading the status register
through program control or using the DRQ line with DMA or
interrupt methods. When the Data register is read the DRQ
bit in the status register and the DRQ line are automatically
reset. A write to the Data register also causes both DRQ's
to reset.
The busy bit in the status may be monitored with a user
program to determine when a command is complete, in
lieu of using the INTRQ line. When using the INTRQ, a busy
status check is not recommended because a read of the
status register to determine the condition of busy will reset
the INTRQ line.

SHIFT 1 BYTE
INTO DSR

The format of the Status Register is shown below:

TRANSFER
BYTE TO DR

7
S7

6
S6

5
S5

(BITS)
4
3
S4
S3

2
S2

1
S1

0
SO

Status varies according to the type of command executed
as shown in Table 4.
Because of internal sync cycles, certain time delays must
be observed when operating under programmed I/O. They
are: (times double when clock = 1 MHz)

Operation
Write to
Command Reg.
Write to
Command Reg.
Write Any
Register

TRANSFER TRACK
NUMBER TO SECTOR
REGISTOR

Next Operation

o

Delay Req'd.
FM
| MFM

Read Busy Bit
(Status Bit 0)

12 MS

!
I

6 us

Read Status
Bits 1-7
Read From Diff.
Register

28 ^s

i
i

14 ^s

!

o

o

I

IBM 3740 FORMAT — 128 BYTES/SECTOR

Shown below is the IBM single-density format with 128
bytes/sector. In order to format a diskette, the user must
issue the Write Track command, and load the data register
with the following values. For every byte to be written, there
is one Data Request.

TYPE III COMMAND
Read Track/Address

16

w

9

IBM 3740 FORMAT — 128 BYTES/SECTOR

IBM SYSTEM 34 FORMAT- 256 BYTES/SECTOR

Shown below is the IBM single-density format with 128
bytes/sector. In order to format a diskette, the user must
issue the Write Track command, and load the data register
with the following values. For every byte to be written, there
is one Data Request.

Shown below is the IBM dual-density format with 256
bytes/sector. In order to format a diskette the user must
issue the Write Track command and load the data register
with the following values. For every byte to be written, there
is one data request.

NUMBER
OF BYTES
40
6
1
26
6
1
1
1
1
1
1
11
6
1
128
1
27
247**

•N

NUMBER
OF BYTES

HEX VALUE OF
BYTE WRITTEN

80
12
3
1

FF(orOO)1
00
FC (Index Mark)
FF(orOO)1
00
FE (ID Address Mark)
Track Number
Side Number (00 or 01)
Sector Number (1 thru 1A)
00 (Sector Length)
F7 (2 CRC's written)
FF(orOO)1
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF(orOO)1
FF(orOO)1

* 50
12
3
1
1
1
1
1
1
22
12
3
1
256
1
54
598**

*Write bracketed field 26 times
**Continue writing until FD179X interrupts out.
Approx. 247 bytes.
1-Optional '00' on 1795/7 only.

ssaa.H

f
TRACK
NUMBER

SIDE
NUMBER

StCTOR
NUMBER

4E
00
F6 (Writes C2)
FC (Index Mark)

4E
00
F5 (Writes A1)
FE (ID Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 1A)
01 (Sector Length)
F7 (2 CRCs written)
4E
00
F5 (Writes A1)
FB (Data Address Mark)
DATA
F7 (2 CRCs written)
4E
4E

*Write bracketed field 26 times
**Continue writing until FD179X interrupts out.
Approx. 598 bytes.

^J

ADDRESS

HEX VALUE OF
BYTE WRITTEN

SECTOR
LENGTH

«•»'«

1

IN ON FOR UPDATE

CRC
BYTE t

CRC

,j B Y T E S

—/

IBM TRACK FORMAT

17

1. NON-IBM FORMATS
Variations in the IBM formats are possible to a limited
extent if the following requirements are met:

1

K'-

1) Sector size must be 128,256,512 or 1024 bytes.

—|

^

2) Gap 2 cannot be varied from the IBM format.

[Ton

I

DRQ

!

3) 3 bytes of A1 must be used in MFM.
IKlTOr,

In addition, the Index Address Mark is not required for
operation by the FD179X. Gap 1, 3, and 4 lengths can be as
short as 2 bytes for FD179X operation, however PLL lock up
time, motor speed variation, write-splice area, etc. will add
more bytes to each gap to achieve proper operation. It is
recommended that the IBM format be used for highest
system reliability.

Gapl

FM
16 bytes FF

1 ,

—*-j 'SERVICE
T

HLD

11 bytes FF

22 bytes 4E

6 bytes 00

12 bytes 00
3 bytes A1

Gap III**

10 bytes FF
4 bytes 00

24 bytes 4E
8 bytes 00
3 bytes A1

AO A1 CS

16 bytes FF

16 bytes 4E

e

1

1
«•

TRE

^.

1
—"-J

T

S€T
T

DACC

}-•-

I

(DAT7 ——

-•-pooi J ••
NOTE

Gap IV

°L

-j 1-

MFM
32 bytes 4E

Gap II
*
*

1

f

1 CS MAY BE PERMANENTLY TIED LOW IF DESIRED
TIME DOUBLES WHEN CLOCK

1MH*

I SERVICE (WORST CASEl
•FM 2 7 5 u S
MFM
135uS
DRO RISING EDGE INDICATES THAT THE DATA REGISTER HAS ASSEMBLED
DATA
ORO FALLING EDGE INDICATES THAT THE DATA REGISTER WAS READ
INTRO RISING EDGE OCCURS AT END OF COMMAND
INTRO FALLING EDGE INDICATES THAT THE STATUS REGISTER WAS READ

*Byte counts must be exact.
**Byte counts are minimum, except exactly 3 bytes of A1
must be written.

READ ENABLE TIMING

o

TIMING CHARACTERISTICS
TA = 0°C to 70°C, VDD = + 12V z_ .6V, Vss = 0V, Vcc =+5V ± .25V
READ ENABLE TIMING (See Note 6, Page 21)
SYMBOL
TSET
THLD
TRE

TDRR
TIRR
TDACC
TDOH

CHARACTERISTIC
Setup ADDR & CS to RE
Hold ADDR & CS from RE
RE Pulse Width
DRQ Reset from RE
INTRQ Reset from RE
Data Access from RE
Data Hold From RE

MIN.

TYP.

MAX.

400
500

500

50
10
400

3000
350
150

50

UNITS
nsec
nsec
nsec
nsec
nsec
nsec
nsec

CONDITIONS

CL = 50 pf

See Note 5
CL = 50 pf
CL = 50 pf

WRITE ENABLE TIMING (See Note 6, Page 21)
SYMBOL
TSET
THLD
TWE

TDRR
TIRR
TDS
TDH

CHARACTERISTIC
Setup ADDR & CS to WE
Hold ADDR & CS from WE
WE Pulse Width
DRQ Reset from WE
INTRQ Reset from WE
Data Setup to WE
Data Hold from WE

MIN.

TYP.

MAX.

400
500

3000

50
10
350

250
70

18

500

UNITS
nsec
nsec
nsec
nsec
nsec
nsec
nsec

CONDITIONS

See Note 5

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no i->

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T, R P

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*

icnvicc

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-

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_,
h-TT"-^

I-

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1
^.

1

TWE

|

1

^

Ti

1

•»!

Tt

I-.
1^1

^1
|

wvF

^~| T SET
f DATA MUSTJ
1
BE VALID |

QJ^

NOMINA L

-H '°s
k 1[^_
-^|T

DISKETTE MODE

OH

8"
8"
5"
5"

NO TE 1 CS MAY BE PERMANENTLY TIED LOW IF DESIRED

2 WHEN WRITING DATA INTO SECTOR TRACK OH DATA
REGISTER USER CANNOT READ THIS REGISTER UNTIL
WHEN WRITING INTO THE COMMAND REGISTER STATUS
I SERVICE (WORST CASE)
IS NOT VALID UNTIL SOME 28 MSEC IN FM 14 MSEC IN MFM
fM
235uS
LATER THESE TIMES ARE DOUBLED WHEN CLK
1 MH*
MFM
USoS
T|
ME DOUBLES WHEN CLOCK
1MHz

MFM
FM
MFM
FM

DDEN
0
1
0
1

CLK

T.

2 MHz 1 Ms
2 MHz 2 Ms
1 MHz 2 M s
1 MHz 4 Ms

Tb

Tc

1 Ms
2^s
2Ms
4 Ms

2Ms
4 /us
4Ms
8 MS

INPUT DATA TIMING

Dffl3 RISING EDGE INDICATES THAT THE DATA REGISTER IS EMPTY
OR

RQ RISING EDGE INDICATE THE END OF A COMMAND
INI RO FALLING EDGE INDICATES THAT THE COMMAND
IS WRITTEN TO

WRITE ENABLE TIMING
INPUT DATA TIMING:
SYMBOL
CHARACTERISTIC
\

REGISTER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

Tpw

Raw Read Pulse Width

100

200

nsec

See Note 1

tbc

1500

2000
2000

nsec

1800 ns @ 70°C

Tc

Raw Read Cycle Time
RCLK Cycle Time

nsec

1800 ns@70°C

Txi

RCLK hold to Raw Read

40

nsec

See Note 1

TX2

Raw Read hold to RCLK

40

nsec

See Note 1

1500

WRITE DATA TIMING: (ALL TIMES DOUBLE WHEN CLK = 1 MHz) (SeeNoteG, Page21)
SYMBOL

CHARACTERISTICS

Twp

Write Data Pulse Width

Twg

Write Gate to Write Data

Tbc
T*
Th
Twf

Write data cycle Time
Early (Late) to Write Data
Early (Late) From
Write Data
Write Gate off from WD

Twdl

WD Valid to Clk

Twd2

WD Valid after CLK

MIN.

TYP.

MAX.

UNITS

CONDITIONS

500
200
2
1

65O
350

nsec
nsec
/xsec
/xsec
/msec
nsec
nsec

FM
MFM
FM
MFM
± CLK Error
MFM
MFM

/xsec
^sec

FM
MFM

nsec
nsec
nsec
nsec

CLK=1 MHZ
CLK=2 MHZ
CLK=1 MHZ
CLK=2 MHZ

2,3, or 4
125
125

2
1
100
50
100
30

19

V

- 250 NSCLK
(2 MHZ)

1_

DDEN = 1

i^^i I V//^7\

WD

"•-H 1 h""&

CLK
12MHZ)

DDEN =0)

125

Twd2

+ •4

-A

125

I
L

V/////A

j

V/JZft

WD MUST HAVE RISING EDGE IN FIRST SHADED AREA AND TRAILING
EDGE IN SECOND SHADED AREA.
WRITE DATA/CLOCK RELATIONSHIP

WRITE DATA TIMING

MISCELLANEOUS TIMING: (Times Double When Clock = 1 MHz)
SYMBOL
TCDi
TCD2
TSTP
TDIR
TMR
TIP
TWF

CHARACTERISTIC
Clock Duty (low)
Clock Duty (high)
Step Pulse Output
Dir Setup to Step
Master Reset Pulse Width
Index Pulse Width
Write Fault Pulse Width

MIN.
230
200

(See Note 6, Page 21)

TYP.
250
250

2or4
12
50
10
10

20

O
MAX.

UNITS

CONDITIONS

20000
20000

nsec
nsec
/xsec
^sec
/xsec
/xsec
fjisec

See Note 5
± CLK ERROR
See Note 5

«

NOTES:
1. Pulse width on RAW READ (Pin 27) is normally
100-300 ns. However, pulse may be any width if
pulse is entirely within window. If pulse occurs in both
windows, then pulse width must be less than 300 ns
for MFM at CLK = 2 MHz and 600 ns for FM at 2
MHz. Times double for 1 MHz.
2. A PPL Data Separator is recommended for 8" MFM.
3. tbc should be 2 /xs, nominal in MFM and 4 /AS nominal
in FM. Times double when CLK = 1 MHz.
4. RCLK may be high or low during RAW READ (Polarity
is unimportant).
5. Times double when clock = 1 MHz.

I—'-—I
I-—,—I
h'c«H

6. Output timing readings are at VOL = 0.8v and VOH =
2.0v.

l~

•"n.

I STEP IN

j — T DIR -—| T STFJ—

U» T OiR -*J T STP I—-

jT S T pL»_

rUJ-U,

TL

MISCELLANEOUS TIMING
•FROM STEP RATE TABLE

Table 4. STATUS REGISTER SUMMARY

ALL TYPE 1

READ

BIT
ADDRESS
COMMANDS
NOT READY
S7 NOT READY
0
S6 WRITE

~\

S5
S4
S3
S2
S1
SO

PROTECT
HEAD LOADED
SEEK ERROR
CRC ERROR
TRACK 0
INDEX PULSE
BUSY

0

READ
SECTOR
NOT READY

READ
TRACK
NOT READY

0

0
0
0
0

RECORD TYPE

RNF

RNF

CRC ERROR
LOST DATA

CRC ERROR
LOST DATA

LOST DATA

WRITE
SECTOR
NOT READY
WRITE
PROTECT
WRITE FAULT

WRITE
TRACK
NOT READY
WRITE
PROTECT
WRITE FAULT

0
0

RNF
CRC ERROR
LOST DATA

LOST DATA

DRQ

DRQ

DRQ

DRQ

DRQ

BUSY

BUSY

BUSY

BUSY

BUSY

STATUS FOR TYPE I COMMANDS
BIT NAME
MEANING
S7 NOT READY
This bit when set indicates the drive is not ready. When reset it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and logically 'ored' with MR.
S6 PROTECTED
When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.
S5 HEAD LOADED When set, it indicates the head is loaded and engaged. This bit is a logical "and" of
HLD and HLT signals.
S4 SEEK ERROR
When set, the desired track was not verified. This bit is reset to 0 when updated.
S3 CRC ERROR
CRC encountered in ID field.
S2 TRACK 00
When set, indicates Read/Write head is positioned to Track 0. This bit is an inverted
copy of the TROO input.
S1 INDEX
When set, indicates index mark detected from drive. This bit is an inverted copy of the
IP input.
SO BUSY
When set command is in progress. When reset no command is in progress.

21

STATUS FOR TYPE II AND III COMMANDS
MEANING
BIT NAME
This bit when set indicates the drive is not ready. When reset, it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II
and III Commands will not execute unless the drive is ready.
S6 WRITE PROTECT On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a
Write Protect. This bit is reset when updated.
S5 RECORD TYPE/ On Read Record: It indicates the record-type code from data field address mark.
1 = Deleted Data Mark. 0 = Data Mark. On any Write: It indicates a Write Fault. This bit
WRITE FAULT
is reset when updated.
When set, it indicates that the desired track, sector, or side were not found. This bit is
S4 RECORD NOT
reset when updated.
FOUND (RNF)
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in
S3 CRC ERROR
data field. This bit is reset when updated.
S2 LOST DATA
When set, it indicates the computer did not respond to DRQ in one byte time. This bit is
reset to zero when updated.
S1 DATA REQUEST This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read
Operation or the DR is empty on a Write operation. This bit is reset to zero when updated.
SO BUSY
When set, command is under execution. When reset, no command is under execution.
S7 NOT READY

^^^^

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
VDO with repect to Vss (ground): +15 to - 0.3V
Voltage to any input with respect to Vss = + 15 to - 0.3V
Ice = 60 MA (35 MA nominal)
IDD = 15 MA (10 MA nominal)

CIN & Cour = 15 pF max with all pins grounded except
one under test.
Operating temperature = 0°Cto70°C
Storage temperature = -55°Cto + 125°C

OPERATING CHARACTERISTICS (DC)
TA = 0 0 Cto70°C,Voo = -I- 12V ± .6V, Vss = OV,Vcc = + 5V ± .25V
SYMBOL

L
tot
V,H
VlL
VOH

VOL
Po

CHARACTERISTIC

MIN.

Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Dissipation

MAX.

UNITS

10
10

MA
MA
V
V
V
V
W

2.6
0.8
2.8
0.45
0.6

CONDITIONS

o

VIN = VDD**
Vour = VDD

lo= -100^A
lo = 1.6mA*

*1792 and 1794k) = 1.0mA
**Leakage conditions are for input pins without internal pull-up resistors. Pins 22, 23, 33, 36, and 37 have pull-up resistors.
See Tech Memo #115 for testing procedures.

22

w

T

.m

.015

100 MAX

MIN

•ii ,

2.025
MAX

1*

r*~MAX~^|

T-WWmmrnms*lk
•Ji^ i-sJ
II

100 TYP

MAX
1 i^

T n

-JU

-..OOTVP

014

l^

,««

2060

.? L " _

MAX

°15M|N
. |

^^Q MA y

Sf-Hk

f

40 LEAD RELPACK "B" or "BL"

|^

'15|5MAX

.015 MIN

SS

IHI

p=n

*

^^|^_

°
MAX

^-Hh-

! l . «^T1. .. .1

fffffffffffffl^-

—^J L^- 100
TYP

^i

I

62

.014

40 LEAD CERAMIC "A" or "AL"

r 150MAX

mvvwwwvwvwt

T"VW
T

021-Hk

L

r
r°^^
^f^

MIN
-fcH
•^l
, I
^| 1 r.12 OMIN
.040

2.080
MAX

-

1 w

I

yH/WWVWVIAWVWWVVif

^S^

—^1 |-^-. 100 TYP

_ .

620

^ I ,2^1

^ a^l^r

MIN

1

f1

.014

X)21

^

.021

40 LEAD CERDIP "CL"

40 LEAD PLASTIC "P" or "PL"

23

L

' I*"

J

~

^

H

u-^l

.014

-^

i^.

MA

%

o
Information furnished by Western Digital Corporation is believed to be accurate and reliable However, no responsibility is assumed by Western Digital
Corporation for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation Western Digital Corporation reserves the right to change
specifications at anytime without notice

WESTERN

DIGITAL

C

A

O

R

P

O

R

T

I

O

N

2445 McCABE WAY
IRVINE, CALIFORNIA 92714

24

(714) 557-3550, TWX 910-595-1139
Printed in U S A

w

TECHNICAL MEMO

»

MEMO:
DEVICE:

TITLE:
DATE:

WES
TERM
C
O
R
P
O
R

DIGITAL
T
i
O
N

A

2445 McCabe Way
Irvine, California 92714
(714)557-3550 TWX 910-595-1139

169
WD1770/1772/1773

Preliminary Data Sheet Update
8/29/83

The following information represents updates to the
current WD1770/72/73 Preliminary Data sheet. These updates
are performance enhancements.
1.

TRE (Page 19) Changed from MIN 150NS to MIN 200NS.

2.

TAH (Page 19) Changed from MIN 20NS to IONS.

3.

TWE (Page 19) Changed from MIN 150NS to MIN 200NS.

4.

H bit in Command (Page 6 last paragraph)
Changed from: "If the hFlag is set and motor on
line (Pin 20)"
Changed to:

3

"If the hFlag is NOT set and motor
on line (Pin 20)"

WESTERN

DIGITAL

C

A

O

R

P

O

R

T

I

O

N

WD1773 51/4" Floppy Disk Controller/Formatter
FEATURES
• 100% SOFTWARE COMPATIBILITY WITH
WD1793
• BUILT-IN DATA SEPARATOR
• BUILT-IN WRITE PRECOMPENSATION
• SINGLE (FM) AND DOUBLE (MFM) DENSITY
• 28 PIN DIP, SINGLE +5V SUPPLY
• TTL COMPATIBLE INPUTS/OUTPUTS
• 128, 256, 512 OR 1024 SECTOR LENGTHS
• 8-BIT BI-DIRECTIONAL HOST INTERFACE

csCZ

1

2
AOd 3
A1 I
4
DALO I
5
DAL1 d 6
DAL2 1
7
DAL3 1
8
DAL4 CZ 9
DAL5 d 10
DAL6CH 11
DAL7 1
12
MRd 13
GND d 14
R/W I

^

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

HJ INTRQ
HJDRQ
ZDDDEN
ZDWPRT
HJTF
ZDTROO
—1WD
—IWG
—1 ENP/RDY

=]RD
HDCLK
—1DIRC
—1STEP
=1VCC

PIN DESIGNATION

DESCRIPTION
The WD1773 is an MOS/LSI device which performs
the functions of a 5V4 W Floppy Disk Controller/
Formatter. It is fully software compatible with
the Western Digital WD1793-02, allowing the
designer to reduce parts count and board size on an
existing WD1793 based design without software
modifications.
With the exception of the enable Precomp/Ready
line, the WD1773 is identical to the WD1770 controller. This line serves as both a READY input from
the drive during READ/STEP operations, and as a
Write Precompensation enable during Write operations. A built-in digital data separator virtually
eliminates all external components associated with
data recovery in previous designs.
The WD1773 is implemented in NMOS silicon gate
technology and is available in a 28 pin, dual-in-line
package.

o

January, 1984

w

PIN DESCRIPTION
PIN
NUMBER
1

3

PIN NAME
CHIP SELECT

CS

MNEMONIC

2

READ/WRITE

R/W

3,4

ADDRESS 0,1

AO,A1

5-12

DATA ACCESS LINES
0 THROUGH 7

DALO-DAL7

13

MASTER RESET

MR

14

GROUND
POWER SUPPLY
STEP

GND

15
16

vcc

17

DIRECTION

DIRC

18

CLOCK

CLK

19

READ DATA

RD

20

ENABLE PRECOMP/
READY LINE

ENP/RDY

21

WRITE GATE

WG

22

WRITE DATA

WD

23

TRACK 00

TROO

24

INDEX PULSE

IP

25

WRITE PROTECT

WPRT

26

DOUBLE DENSITY
ENABLE

DDEN

STEP

FUNCTION
A logic low on this input selects the chip and
enable Host communication with the device.
A logic high on this input_ controls the
placement of data on the DO-D7 lines from a
selected register, while a logic low causes a
write operation to a selected register.
These two inputs select a register to Read/Write
data:
CS A1 AO
R/W = 1
R/W = 0
0
0
0 Status R e g
Command R e g
0
0
1 Track R e g
Track R e g
0
1
0 Sector R e g
Sector R e g
0
1
1 Data Reg
Data Reg
Eight bit bidirectional bus used for transfer of
data, control, or status. This bus is enabled by
CS and R/W. Each line will drive one TTL load.
A logic low pulse on this line resets the device
and initializes the status register. Internal pullup.
Ground.
-I- 5V ± 5% power supply input.
The Step output contains a pulse for each step
of the drive's R/W head.
The Direction output is high when stepping in
towards the center of the diskette, and low
when stepping out.
This input requires a free-running 40 to 60%
duty cycle clock (for internal timing) at 8 MHZ
±1%.
This active low input is the raw data line
containing both clock and data pulses from the
drive.
Serves as a READY input from the drive during
READ/STEP operations and as a Write Precomp
enable during write operations.
This output is made valid prior to writing on the
diskette.
FM or MFM clock and data pulses are placed on
this line to be written on the diskette.
This active low input informs the WD1773 that
the drive's R/W heads are positioned over Track
zero.
This active low input informs the WD1773 when
the physical index hole has been encountered
on the diskette.
This input is sampled whenever a Write
Command is received. A logic low on this
line will prevent any Write Command from
executing. Internal pull-up.
This input pin selects either single (FM) or
double (MFM) density. When DDEN = 0, double
density is selected. Internal pull-up.

PIN DESCRIPTION (CONTINUED)
PIN
NUMBER

PIN NAME

MNEMONIC

FUNCTION

27

DATA REQUEST

DRQ

This active high output indicates that the Data
Register is full (on a Read) or empty (on a Write
operation).

28

INTERRUPT REQUEST

INTRQ

This active high output is set at the completion
of any command or reset a read of the Status
Register.

_JMUX|
I
ENP/

EMP/RDY

,

RFW

CLK

H
O
S
T

RFA( DY

r— ' '

WG
WD

DO-D7

,

AO
A1

N
T
E
R
F
A
C
E

C5

WD1773

R/W

IP

WPRT

DIRC

DRQ

F
L
0
P
P
Y
D
R
I
V
E

STEP

^ INTRQ

+5

,

TROO

ftH

5V4"

RD

GND

J

V

CC

1L + 5V

EN 4i DDl

WD1773 SYSTEM BLOCK DIAGRAM

ARCHITECTURE
The Floppy Disk Formatter block diagram is illustrated on page 4. The primary sections include
the parallel processor interface and the Floppy Disk
interface.
Data Shift Register — This 8-bit register assembles
serial data from the Read Data input (RD) during Read
operations and transfers serial data to the Write Data
output during Write operations.
Data Register — This 8-bit register is used as a
holding register during Disk Read and Write operations. In Disk Read operations, the assembled data
byte is transferred in parallel to the Data Register
from the Data Shift Register. In Disk Write operations,
information is transferred in parallel from the Data
Register to the Data Shift Register.
When executing the Seek command, the Data Register holds the address of the desired Track position.

This register is loaded from the DAL and gated onto
the DAL under processor control.
Track Register — This 8-bit register holds the track
number of the current Read/Write head position. It is
incremented by one every time the head is stepped in
and decremented by one when the head is stepped
out (towards track 00). The contents of the register
are compared with the recorded track number in the
ID field during disk Read, Write, and Verify operations. The Track Register can be loaded from or
transferred to the DAL. This Register should not be
loaded when the device is busy.
Sector Register (SR) — This 8-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded sector
number in the ID field during disk Read or Write
operations. The Sector Register contents can be
loaded from or transferred to the DAL This register
should not be loaded when the device is busy.
Command Register (CR) — This 8-bit register holds
the command presently being executed. This register
should not be loaded when the device is busy unless
the new command is a force interrupt. The command
register can be loaded from the DAL, but not read
onto the DAL
Status Register (STR) — This 8-bit register holds
device Status information. The meaning of the Status
bits is a function of the type of command previously
executed. This register can be read onto the DAL but
not loaded from the DAL
CRC Logic — This logic is used to check or to
generate the 16-bit Cyclic Redundancy Check (CRC).
The polynomial is:
G(x) = x16 + X12 + X5 + 1.
The CRC includes all information starting with the
address mark and up to the CRC characters. The
CRC register is preset to ones prior to data being
shifted through the circuit.
Arithmetic/Logic Unit (ALU) — The ALU is a serial
comparator, incrementer, and decrementer and is
used for register modification and comparisons with
the disk recorded ID field.

9

O

(DAL)

WG

UMU

INTRQ

MR

WPRT

_

«

CS

D

R/W

AO

COMPUTER
INTERFACE
CONTROL

CONTROL

PLA
CONTROL
(240X19)

CONTROL

DISK
INTERFACE
CONTROL

rp
TROO
STEP
DIRC

A1

_

RDY

CLK(8MHZ) _
DDEN

WD1773 BLOCK DIAGRAM
Timing and Control — All computer and Floppy Disk
interface controls are generated through this logic.
The internal device timing is generated from an external crystal clock. The WD1773 has two different
modes of operation according to the state of DDEN.
When DDEN = 0, double density (MFM) is enabled.
When DDEN = 1, single density is enabled.
AM Detector — The address mark detector detects
ID, data and index address marks during read and
write operations.
Data Separator — A digital data separator consisting
of a ring shift register and data window detection
logic provides read data and a recovery clock to the
AM detector.

PROCESSOR INTERFACE
The interface to the processor is accomplished
through the eight Data Access Lines (DAL) and
associated control signals. The DAL are used to
transfer Data, Status, and Control words out of, or into the WD1773. The DAL are three state buffers that
are enabled as output drivers when Chip Select (CS)
and R/W = 1 are active or act as input receivers when
CS and R/W = 0 are active.
When transfer of data with the Floppy Disk Controller
is required by the host processor, the device address
is decoded and CS is made low. The address bits A1
and AO, combined with the signal R/W during a Read
operation or Write operation are interpreted as selecting the following registers:

A1 - AO
0
0
0
1
1
0

1

1

READ(R/W = 1)
Status Register
Track Register
Sector Register
Data Register

WRITE (R/W = 0)
Command Register
Track Register
Sector Register
Data Register

During Direct Memory Access (DMA) types of data
transfers between the Data Register of the WD1773
and the processor, the Data Request (DRQ) output
is used in Data Transfer control. This signal also
appears as status bit 1 during Read and Write
operations.
On Disk Read operations the Data Request is activated (set high) when an assembled serial input byte
is transferred in parallel to the Data Register. This bit
is cleared when the Data Register is read by the processor. If the Data Register is read after one or more
characters are lost, by having new data transferred into the register prior to processor readout, the Lost
Data bit is set in the Status Register. The Read operations continues until the end of sector is reached.
On Disk Write operations the Data Request is activated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data
byte. It is reset when the Data Register is loaded with
new data by the processor. If new data is not loaded
at the time the next serial byte is required by the
Floppy Disk, a byte of zeroes is written on the
diskette and the Lost Data is set in the Status
Register.
At the completion of every command an INTRQ is
generated. INTRQ is reset by either reading the
status register or by loading the command register
with a new command. In addition, INTRQ is generated if a Force Interrupt command condition is met.
The WD1773 has two modes of operation according
to the state DDEN (Pin 26). When DDEN = 1, single
density is selected. In either case, the CLK input (Pin
18) is at 8 MHZ.
GENERAL DISK READ OPERATIONS
Sector lengths of 128,256,512 or 1024 are obtainable
in either FM or MFM formats. For FM, DDEN should
be placed to logical "1" For MFM formats, DDEN
should be placed to a logical "0!' Sector lengths are
determined at format time by the fourth byte in the
"ID" field.
SECTOR LENGTH TABLE
SECTOR LENGTH
NUMBER OF BYTES
HELD (HEX)
IN SECTOR (DECIMAL)
128
00
256
01
512
02
03
1024
The number of sectors per tract as far as the WD1773
is concerned can be from 1 to 255 sectors. The

number of tracks as far as the WD1773 is concerned
is from 0 to 255 tracks.
GENERAL DISK WRITE OPERATION
When writing is to take place on the diskette the
Write Gate (WG) output is activated, allowing current
to flow into the Read/Write head. As a precaution to
erroneous writing the first data byte must be loaded
into the Data Register in response to a Data Request
from the device before the Write Gate signal can be
activated.
Writing is inhibited when the Write Protect input is a
logic low, in which case any Write command is immediately terminated, an interrupt is generated and
the Write Protect status bit is set.
For Write operations, the WD1773 provides Write
Gate (Pin 21) to enable a Write condition, and Write
Data (Pin 22) which consists of a series of active high
pulses. These pulses contain both Clock and Data information in FM and MFM. Write Data provides the
unique missing clock patterns for recording Address
Marks.
If Precomp Enable (ENP) is active when WG is
asserted, automatic Write Precompensation takes
place. The outgoing Write Data stream is delayed or
advanced from nominal by 125 nanoseconds according to the following table:
PATTERN
X
X
0

1

1
0
0
0

1
1
0
0

0

1
1

0

MFM
Early
Late
Early
Late

FM
N/A
N/A
N/A
N/A

Next Bit to be sent
Current Bit sending
Previous Bits sent

v

O

Precompensation is typically enabled on the innermost tracks where bit shifts usually occur and bit
density is at its maximun.
COMMAND DESCRIPTION
The WD1773 will accept eleven commands. Command words should only be loaded in the Command
Register when the Busy status bit is off (Status bit 0).
The one exception is the Force Interrupt command.
Whenever a command is being executed, the Busy
status bit is set. When a command is completed, an
interrupt is generated and the Busy status bit is reset.
The Status Register indicates whether the completed
command encountered an error or was fault free. For
ease of discussion, commands are divided into four
types. Commands and types are summarized in
Table 1.

W

TABLE 1.

COMMAND SUMMARY

TYPE COMMAND
I Restore
oeeK
I Step
I Step-in
I Step-out
II Read Sector
II Write Sector
III Read Address
III Read Track
III Write Track
IV Force Interrupt

7
6
0
0
0 I 0
0
0
1
0
1
0
1 0
1 0

1
1
1
1

1
1
1
1

5
0
0

1

0

1

0

1

0

1
1

0

BITS
4
3
h
0
1
h
T
h
h
T
T
h
m
L
m
L
0
0
0
0
1
0
1
"3

2
V
V
V
V
V
E
E
E
E
E
«2

1

M

H
H
ri
M

u
u
u
u
u
h

0
ro
ro

ro
ro

ro

0
ao
0
0
0

io

FLAG SUMMARY

D

COMMAND
TYPE
I

BIT
NO(S)
0,1

1

2

V = Track Number Verify Flag

1

3

h = Don't Care

1

4

T = Track Update Flag

T = 0, No update
T = 1, Update track register

H

0

^0 = Data Address Mark

ao = 0, FB(DAM)
ao= 1,F8 (deleted DAM)

II

1

C = Side Compare Flag

C = 0, Disable side compare
C = 1, Enable side compare

II & III

1

U = Update SSO

U = 0, Update SSO toO
U = 1, Update SSO to 1

II & III

2

E = 15 MS Delay

E = 0, No X MS delay
E = 1,15 MS delay

II

3

S = Side Compare Flag

S = 0, Compare for side 0
S = 1, Compare for side 1

II

3

L = Sector Length Flag

DESCRIPTION
r

1 ro = Stepping Motor Rate
See Table 3 for Rate Summary
V = 0, No verify
V = 1, Verify on destination track

L = 0
L = 1
II

4

IV

0-3

m = Multiple Record Flag
•x
k)
h
'2
•3
•3-h

LSB's Sector Length in ID Field
00
01
10
11
256
512
1024
128
128
256
512
1024

m = 0, Single record
m = 1, Multiple records

= Interrupt Condition Flags
= 1 Not Ready To Ready Transition
= 1 Ready To Not Ready Transition
= 1 1ndex Pulse
= 1 Immediate Interrupt, Requires A Reset
= 0 Terminate With No Interrupt (INTRQ)

* NOTE: See Type IV Command Description for further information.

TYPE I COMMANDS
The Type I Commands include the Restore, Seek,
Step, Step-in, and Step-Out commands. Each of the
Type I Commands contains a rate field (rO r1), which
determines the stepping motor rate as defined in
Table 3.
A 4 ^s (MFM) or 8 ps (FM) pulse is provided as an
output to the drive. For every step pulse issued, the
drive moves one track location in a direction determined by the direction output. The chip will step the
drive in the same direction it last stepped unless the
command changes the direction.
The Direction signal is active high when stepping in
and low when stepping out. The Direction signal is
valid 24 or 48 /usec before the first stepping pulse is
generated.
When a Seek, Step or Restore command is executed
an optional verification of Read-Write head position
can be performed by settling bit 2 (V = 1) in the
command word to a logic 1. The verification operation begins at the end of the 30 msec settling time.
The track number from the first encountered ID Field
is compared against the contents of the Track Register. If the track numbers compare and the ID Field
Cyclic Redundancy Check (CRC) is correct, the verify
operation is complete and an INTRO is generated
with no errors. If there is a match but not a valid CRC,
the CRC error status bit is set (Status bit 3), and the
next encountered ID field is read from the disk for the
verification operation.
The WD1773 must find an ID field with correct track
number and correct CRC within 5 revolutions of the
media; otherwise the seek error is set and an INTRO
is generated. If V = 0, no verification is performed.
RESTORE (SEEK TRACK 0)
Upon receipt of this command the Track 00 (TROO)
input is sampled. If TROO is active low indicating the
Read-Write head is positioned over track 0, the Track
Register is loaded with zeroes and an interrupt is generated. If TROO is not active low, stepping pulses at a
rate specified by the r1 rO field are issued until the
TROO input is activated. At this time the Track
Register is loaded with zeroes and an interrupt is
generated. If the TROO input does not go active low
after 255 stepping pulses, the WD1773 terminates
operation, interrupts, and sets the Seek error status
bit, providing the V flag is set. A verification operation
also takes place if the V flag is setjsjpte that the
Restore command is executed when MR goes from
an active to an inactive state and that the DRQ pin
stays low.
SEEK
This command assumes that the Track Register
contains the track number of he current position of
the Read-Write head and the Data Register contains
the desired track number. The WD1773 will update
the Track register and issue stepping pulses in the
appropriate direction until the contents of the Track

register are equal to the contents of the Data Register (the desired track location). A verification
operation takes place if the V flag is on. An interrupt
is generated at the completion of the command.
Note: When using multiple drives, the track register
must be updated for the drive selected before seeks
are issued.
STEP
Upon receipt of this command, the WD1773 issues
one stepping pulse to the disk drive. The stepping
motor direction is the same as in the previous step
command. After a delay determined by the r1rO field,
a verification takes place if the V flag is on. If the U
flag is on, the Track Register is updated. An interrupt
is generated at the completion of the command.

V

STEP-IN
Upon receipt of this command, the WD1773 issues
one stepping pulse in the direction towards track 76.
If the U flag is on, the Track Register is incremented
by one. After a delay determined by the M^O field, a
verification takes place if the V flag is on. An interrupt
is generated at the completion of the command.
STEP-OUT
Upon receipt of this command, the WD1773 issues
one stepping pulse in the direction towards track 0. If
the U flag is on, the Track Register is decremented by
one. After a delay determined by the M^O field, a
verification takes place if the V flag is on. An interrupt
is generated at the completion of the command.
TYPE II COMMANDS
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command into the Command Register, the computer
must load the Sector Register with the desired sector
number. Upon receipt of the Type II command, the
busy status Bit is set. The E flag is still active providing a delay of 1 to 30 msec for head settling time.
When an ID field is located on the disk, the WD1773
compares the Track Number on the ID field with the
Track Register. If there is not a match, the next encountered ID field is read and a comparison is again
made. If there was a match, the Sector Number of the
ID field is compared with the Sector Register. If there
is not a Sector match, the next encountered ID field
is read off the disk and comparisons again made. If
the ID field CRC is correct, the data field is then
located and will be either written into, or read from
depending upon the command. The WD1773 must
find an ID field with a Track number, Sector number,
side number, and CRC within five revolutions of the
disk; otherwise, the Record not found status bit is set
(Status bit 3) and the command is terminated with an
interrupt.
Each of the Type II Commands contains an (m) flag
which determines if multiple records (sectors) are to
be read or written, depending upon the command. If
m = 0, a single sector is read or written and an inter-

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DC ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Storage Temperature
Operating Temperature

Maximum Voltage to Any Input
with Respect to Vss

- 55°C to + 125°C
0°C to 70°C Ambient

(-15 to-0.3V)

DC OPERATING CHARACTERISTICS
TA = 0°C to 70°C, Vss = 0V, VQC = +5V ±.25V
SYMBOL

IIL
IOL
VIH
VIL
VOH
VOL
PD
RPU
ICG

CHARACTERISTIC
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Dissipation
Internal Pull-Up
Supply Current

MIN.

MAX.

UNITS
MA

10
10

MA
V

2.0

0.40
.75
1700
150

75(Typ)

VIN = VCG
VOUT = VCG

*

V

0.8
2.4

100

CONDITIONS

V

io = -IOO^A

V
W

IQ = 1.6mA

MA
mA

VIN = ov

AC TIMING CHARACTERISTICS
TA = 0°C to 70°C, Vss = OV, VQC = + 5V ± .25V
READ ENABLE TIMING — RE such that: R/W = 1, CS = 0.
SYMBOL
TRE
TDRR
TIRR
TDV
TDOH

CHARACTERISTIC
RE Pulse Width of CS
DRQ Reset from RE
INTRO Reset from RE
Data Valid from RE
Data Hold from RE

MIN.

TYP.

MAX.

200

25
100

50

100
8000
200
150

UNITS
nsec
nsec
nsec
nsec
nsec

CONDITIONS

CL = 50 pf
CL = 50pf

CL = 50 pf

o

Note: DRQ and INTRO reset are from rising edge (lagging) of RE, whereas resets are from falling edge (leading)
of WE.
WRITE ENABLE TIMING — WE such that: R/W = 0, CS = 0.
SYMBOL
TAS
TSET
TAH
THLD
TWE
TDRW
TIRW
TDS
TDH

CHARACTERISTIC
Setup ADDR to C§
Setup R/W to CS
Hold ADDR from CS
Hold R/W fromCS
WE Pulse Width
DRQ Reset from WE
INTRO Reset from WE
Data Setup to WE
Data Hold from WE

MIN.

TYP.

MAX.

100

200
8000

50
0
10
0
200

150

0

17

UNITS
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

CONDITIONS

V

X

DALS
0-7

T

- DS

»»

T

DV

CS

V

TDH

J

*

TDOH

iJ

h

SET—*J

x:

X

nx

TAS
AO, A1

«

/

-TRE. TWE-

T

R./W

X

VALID

J

U—TAH

x
T

DRR-

DRQ
T

DRQ

DRW-

1

REGISTER TIMINGS

1

CLK

A

i

J

^

A

i

|
'

i
'1

-^>

V.

C^IIO 01 I^C

;

EARL> ' TWP

NOMINAL TWP

LATE TWP

/

-5-1/2 CLKS-

TK

-4-1/2CLKS-

WRITE DATA TIMING

18

-L
V

WRITE DATA TIMING:
TYP.

SYMBOL
TWG

CHARACTERISTIC
Write Gate to Write Data

TBC
TWF

Write Data Cycle Time
Write Gate off from WD

4,6,8
4
2

TWP

Write Data Pulse Width

820
690
570
1380

MIN.

MAX.

4
2

UNITS
^sec
Msec
i*sec
Msec
^sec
nsec
nsec
nsec
nsec

CONDITIONS
FM
MFM
FM
MFM

Early MFM
Nominal MFM
Late MFM
FM

INPUT DATA TIMING:
SYMBOL
TPW
TBC

CHARACTERISTIC
Raw Read Pulse Width
Raw Read Cycle Time

TYP.

MIN.

MAX.

3000

200
3000

UNITS
nsec
nsec

CONDITIONS

UNITS
nsec
nsec

CONDITIONS
(60/40)
(40/60)

^sec

MFM
FM

i iQOf^
^sec

MFM
FM

MISCELLANEOUS TIMING:

TCD2
TSTP

CHARACTERISTIC
Clock Duty (low)
Clock Duty (high)
Step Pulse Output

TDIR

Dir Setup to Step

TMR
TIP

Master Reset Pulse Width
Index Pulse Width

SYMBOL
TCDi

MIN.

TYP.

50

67

50

67

MAX.

4
8
24
48

^sec
p

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Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.

WESTERN

DIGITAL

C

A

O

R

P

CP-OS/84221/1-84

O

R

T

I

O

N

2445 McCABE WAY
IRVINE, CALIFORNIA 92714

(714) 8634)102, TWX 910-595-1139
Printed in U S A

WESTERN
C

O

R

P

O

DIGITAL

R

A

T

I

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WD9216-00/WD9216-01
Floppy Disk Data Separator — FDDS
FEATURES
• PERFORMS COMPLETE DATA SEPARATION
FUNCTION FOR FLOPPY DISK DRIVES
• SEPARATES FM OR MFM ENCODED DATA
FROM ANY MAGNETIC MEDIA
• ELIMINATES SEVERAL SSI AND MSI DEVICES
NORMALLY USED FOR DATA SEPARATION
• NO CRITICAL ADJUSTMENTS REQUIRED
• COMPATIBLE WITH WESTERN DIGITAL 179X,
176X AND OTHER FLOPPY DISK
CONTROLLERS
• SMALL 8-PIN DUAL-IN-LINE PACKAGE
• + 5 VOLT ONLY POWER SUPPLY
• TTL COMPATIBLE INPUTS AND OUTPUTS

GENERAL DESCRIPTION
The Floppy Disk Data Separator provides a low cost
solution to the problem of converting a single stream
of pulses from a floppy disk drive into separate Clock
and Data inputs for a Floppy Disk Controller.
The FDDS consists primarily of a clock divider, a
long-term timing corrector, a short-term timing
corrector, and reclocking circuitry. Supplied in an 8pin Dual-ln-Line package to save board real estate,
the FDDS operates on + 5 volts only and is TTL compatible on all inputs and outputs.
The WD9216 is available in two versions; the
WD9216-00, which is intended for5 1 /4" disks and the
WD9216-01 for 5V4" and 8" disks.

§

S

U VCG

DSKD Q
SEPCLK Q

^ SEPD

REFCLK Q

Z)CD1

o

n CD°

GND Q

PIN CONFIGURATION

REFCLKCDO-

— + 5V
— GND

CLOCK
DIVIDER

CD1-

^

DATA/CLOCK
SEPARATION
LOGIC

PULSE
REGENERATION
LOGIC

SEPCLK
SEPD

\

DSKD-

EDGE
DETECTION
LOGIC

FLOPPY DISK DATA SEPARATOR BLOCK DIAGRAM

257

«

ELECTRICAL CHARACTERISTICS

i

^

MAXIMUM RATINGS*

Q
<0
£jj
CD
O
S
<
O
J§
-£
9*
2

Operating Temperature Range
0°C to + 70°C
Storage Temperature Range
- 55°C to 125°C
Positive Voltage on any Pin,
with respect to ground
+ 8.0V
Negative Voltage on any Pin,
with respect to ground
- 0.3V
* Stresses above those listed may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or at
any other condition above those indicated in the
operational sections of this specification is not
implied.

NOTE When powering this device from laboratory or
system power supplies, it is important that the
Absolute Maximum Ratings not be exceeded or
device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs
when the AC power is switched on and off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.

OPERATING CHARACTERISTICS (TA = 0°Cto70°C, VCG = +5V ± 5%, unless otherwise noted)
PARAMETER

MIN.

TYP.

MAX.

UNITS

0.8

V
V

0.4

V
V

10

MA

10

PF

50

mA

4.3
8.3
2500
2500

MHz
MHz

COMMENTS

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS

Low Level VIL
High Level VJH

2.0

OUTPUT VOLTAGE LEVELS

Low Level VOL
High Level VQH

2.4

lOL = 1.6mA
|QH= -lOO^A

INPUT CURRENT

Leakage IIL
INPUT CAPACITANCE
All Inputs
POWER SUPPLY CURRENT

IDD

D

OL

t

\

REFCLK

tsc)ON
SEPD

\

tSDOFF

A

r

J

SEPCLK

tSPCK
^—»

A

-IDW-

DSKD

Figure 3.

AC CHARACTERISTICS

258

WD 921600
WD 921 6-01

DESCRIPTION OF PIN FUNCTIONS
PIN
NUMBER

PIN NAME

SYMBOL

1

Disk Data

"DSKD

2

Separated Clock

SEPCLK

3
4

Reference Clock
Ground
Clock Divisor

REFCLK
GND
CDO, CD1

Separated Data
Power Supply

SEPD

5,6

7
8

FUNCTION
Data input signal direct from disk drive. Contains combined clock and data waveform.
Clock signal output from the FDDS derived
from floppy disk drive serial bit stream.
Reference clock input.
Ground.
CDO and CD1 control the internal clock divider
circuit. The internal clock is a submultiple of the
REFCLK according to the following table:
CD1
CDO
Divisor
0
0
1
0
1
2
1
0
4
1
1
8
SEPD is the data output of the FDDS
+ 5 volt power supply

vcc

i
№

o>

I
i
i
IO

4 MHz CRYSTAL
OSCILLATOR

1MHz

REFCLK
FLOPPY
DISK
DRIVE

DISK DATA

SEPD

REGENERATED DATA

DSKD
WD9216-00, 01
SEPCLK
CDO CD1

DERIVED CLOCK

CLK

RAW READ
WD179X, 176X or Equiv.
FLOPPY DISK
CONTROLLER
RCLK

o

\I

GND

GND

Figure 1.
TYPICAL SYSTEM CONFIGURATION
(51/4 " Drive, Double Density)

Separate short and long term timing correctors
assure accurate clock separation.
The internal clock frequency is nominally 16 times
the SEPCLK frequency. Depending on the internal
timing correction, the internal clock may be a
minimum of 12 times to a maximum of 22 times the
SEPCLK frequency.
The reference clock (REFCLK) is divided to provide
the internal clock according to pins CDO and CD1.

OPERATION
A reference clock (REFCLK) of between 2 and 8 MHz
is divided by the FDDS to provide an internal clock.
The division ratio is selected by inputs CDO and CD1.
The reference clock and division ratio should be
chosen per table 1.
The FDDS detects the leading edges of the disk data
pulses and adjusts the phase of the internal clock to
provide the SEPARATED CLOCK output.

259

w

TABLE 1:
CLOCK DIVIDER SELECTION TABLE

*

DRIVE
(S'orSVO

DENSITY
(DDorSD)

REFCLK
MHz

CD1

CDO

8

DD
SD
SD

8
8
4

0
0
0

0

0

5 /4

DD
DD

8
4

0
0

0

5V4
5V4
5V4

SD
SD
SD

8
4
2

1

0

0
0

0

8
8
5V4
1

1

1
1

REMARKS
^>

Select either one

>

Select either one

^|
>

Select any one

INTCLK JTJTJTJIJTJ-UTJTJTJT^^
SEPCLK

L

L

SEPD

always two internal clock cycles

3

Figure 2.
See page 725 for ordering information.

Information furnished by Western Digital Corporation is believed to be accurate and reliable However, no responsibility is assumed by Western Digital
Corporation for its use, nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation Western Digital Corporation reserves the right to change
specifications at anytime without notice

260

Printed in U S A

WESTERN DIGITAL
C

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A

T

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N

TR1863/TR1865
Universal Asynchronous Receiver/Transmitter (UART)
«

FEATURES
• SINGLE POWER SUPPLY — +5VDC
• D.C. TO 1 MHZ (64 KB) (STANDARD PART)
TR1863/5
• FULL DUPLEX OR HALF DUPLEX OPERATION
• AUTOMATIC INTERNAL SYNCHRONIZATION
OF DATA AND CLOCK
• AUTOMATIC START BIT GENERATION
• EXTERNALLY SELECTABLE
Word Length
Baud Rate
Even/Odd Parity (Receiver/Verification —
Transmitter/Generation)
Parity Inhibit
One, One and One-Half, or Two Stop Bit
Generation (11/2 at 5 Bit Level)
• AUTOMATIC DATA RECEIVED/TRANSMITTED
STATUS GENERATION
Transmission Complete
Buffer Register Transfer Complete
Received Data Available
Parity Error
Framing Error
Overrun Error
• BUFFERED RECEIVER AND TRANSMITTER
REGISTERS

VCGC
NCC

VSSE
RRDC
RR 8 C
RR7C
RR6C
R«5C
RR4C
RR 3 C
RR 2 C
RR1 C
PEC
FEC
OEC
SFDC
RRCC
DRRC
DRC
RIC

\^r

D TRC
3EPE
3 WLS!
3 WLS2
SBS
PI
CRL
TR8
TR7
TR6
TR5
TR4
TR3
TR2
TR1
DTRO
D TRE
DTHRL
3 THRE
D MR

RRD ,

• THREE-STATE OUTPUTS
Receiver Register Outputs
Status Flags
• TTL COMPATIBLE
• TR1865 HAS PULL-UP RESISTORS ON ALL
INPUTS

APPLICATIONS
• PERIPHERALS
• TERMINALS
• MINICOMPUTERS
• FACSIMILE TRANSMISSION
• MODEMS
• CONCENTRATORS
• ASYNCHRONOUS DATA MULTIPLEXERS
• CARD AND TAPE READERS
• PRINTERS
• DATA SETS
• CONTROLLERS
• KEYBOARD ENCODERS
• REMOTE DATA ACQUISITION SYSTEMS
• ASYNCHRONOUS DATA CASSETTES

RECEIVER HOLDING
REGISTER

TRANSMITTER
HOLDING
REGISTER

o

-THRL

-TRO

-TRC
-THRE
-TRE

PIN CONNECTIONS
TR1863STR1865 BLOCK DIAGRAM

321

w

9

•
33
-*
§J
CO
^j
33
03
O>
OT

GENERAL DESCRIPTION
The Universal Asynchronous Receiver/Transmitter
(DART) is a general purpose, programmable or
hardwired MOS/LSI device. The DART is used to
convert parallel data to a serial data format on the
transmit side, and converts a serial data format to
parallel data on the receive side.
The serial format in order of transmission and
reception is a start bit, followed by five to eight data
bits, a parity bit (if selected) and one, one and onehalf, or two stop bits.
Three types of error conditions are available on each
received character parity error, framing error (no valid
stop bit) and overrun error.

PIN DEFINITIONS
PIN
NUMBER

NAME

SYMBOL

1
2
3
4

POWER SUPPLY
NC
GROUND
RECEIVER REGISTER
DISCONNECT

vcc

5-12

RECEIVER HOLDING
REGISTER DATA

RR8RR-I

13

PARITY ERROR

PE

14

FRAMING ERROR

FE

3

The transmitter and receiver operate on external 16X
clocks, where 16 clock times are equal to one bit
time. The receiver clock is also used to sample in the
center of the serial data bits to allow for line
distortion.
Both transmitter and receiver are double buffered
allowing a one character time maximum between a
data read or write. Independent handshake lines for
receiver and transmitter are also included. All inputs
and outputs are TTL compatible with three-state
outputs available on the receiver, and error flags for
bussing multiple devices.

FUNCTION
-i- 5 volts supply
No Internal Connection
Ground = 0V
A high level input voltage, VIH, applied to this
line disconnects the RECEIVER HOLDING
REGISTER outputs from the RR-|-8 data outputs
(pins 5-12).
The parallel contents of the RECEIVER
HOLDING REGISTER appear on these lines if a
low-level input voltage, V|[_, is applied to RRD.
For character formats of fewer than eight bits
received characters are right-justified with RR1
(pin 12) as the least significant bit and the
truncated bits are forced to a low level output
voltage, VOL
A high level output voltage, VQH» °n this line
indicates that the received parity differ from
that which is programmed by the EVEN PARITY
ENABLE control line (pin 39). This output is
updated each time a character is transferred
to the RECEIVER HOLDING REGISTER. PE
lines from a number of arrays can be bussed
together since an output disconnect capability
is provided by Status Flag Disconnect line
(pin 16).
A high-level output voltage, VQH, on this line
indicates that the received character has no
valid stop bit, i.e., the bit (if programmed) is not
a high level voltage. This output is updated each
time a character is transferred to the Receiver
Holding Register, FE lines from a number of
arrays can be bussed together since an output
disconnect capability is provided by the Status
Flag Disconnect line (pin 16).

NC
VSS
RRD

322

PIN DEFINITIONS
PIN
NUMBER

15

NAME
OVERRUN ERROR

SYMBOL

STATUS FLAGS
DISCONNECT

SFD

17

RRC

19

RECEIVER REGISTER
CLOCK
DATA RECEIVED
RESET
DATA RECEIVED

DR

20

RECEIVER INPUT

Rl

21

MASTER RESET

MR

22

TRANSMITTER
HOLDING REGISTER
EMPTY

THRE

23

TRANSMITTER
HOLDING REGISTER
LOAD

THRL

24

TRANSMITTER
REGISTER EMPTY

TRE

18

n

OE

16

FUNCTION
A high-level output voltage, VQH, ° this line
indicates that the Data Received Flag (pin 19)
was not reset before the next character was
transferred to the Receiver Holding Register.
OE lines from a number of arrays can be bussed
together since an output disconnect capability
is provided by the Status Flag Disconnect line
(pin 16).
A high-level input voltage, VJH, applied to this
pin disconnects the PE, FE, OE, DR and THRE
allowing them to be buss connected.
The receiver clock frequency is sixteen (16)
times the desired receiver shift rate.
A low-level input voltage, VIL, applied to this
line resets the DR line.
A high-level output voltage, VQH, indicates that
an entire character has been received and
transferred to the RECEIVER HOLDING
REGISTER.
Serial input data A high-level input voltage, VJH,
must be present when data is not being
received.
This line is strobed to a high-level input voltage,
VIH, to clear the logic. It resets the TRANSMITTER and RECEIVER HOLDING REGISTERS, the TRANSMITTER REGISTER, FE, OE,
PE, DR and sets TRO, THRE, and TRE to a
high-level output voltage, VQHA high-level output voltage, VQH, on this line
indicates the TRANSMITTER HOLDING REGISTER has transferred its contents to the
TRANSMITTER REGISTER and may be loaded
with a new character.
A low-level input voltage, VIL, applied to this
line enters a character into the TRANSMITTER
HOLDING REGISTER. A transition from a lowlevel input voltage, VIL, to a high-level input
voltage, VIH, transfers the character into the
TRANSMITTER REGISTER if it is not in the
process of transmitting a character. If a
character is being transmitted, the transfer is
delayed until its transmission is completed.
Upon completion, the new character is
automatically transferred simultaneously with
the initiation of the serial transmission of the
new character.
A high-level output voltage, VQH. on *his line
indicates that the TRANSMITTER REGISTER
has completed serial transmission of a full
character including STOP bit(s). It remains at
this level until the start of transmission of the
next character.

DRR

323

33
00

2
CD

3

o

PIN DEFINITIONS
PIN
NUMBER

NAME

SYMBOL

TRANSMITTER
REGISTER OUTPUT

TRO

TRANSMITTER
REGISTER DATA
INPUTS

TRi-TR8

34

CONTROL REGISTER
LOAD

CRL

35

PARITY INHIBIT

PI

36

STOP BIT(S) SELECT

SBS

WORD LENGTH
SELECT

WLS2-WLS1

39

EVEN PARITY
ENABLE

EPE

40

TRANSMITTER
REGISTER

TRC

25

9
CO

en
en
26-33

^
37-38

324

FUNCTION

The contents of the TRANSMITTER REGISTER
(START bit, DATA bits, PARITY bit, and STOP
bits) are serially shifted out on this line. When
no data is being transmitted, this line will
remain at a high-level output voltage, VQH- Start
of transmission is defined as the transition of
the START bit from a high-level output voltage
VOH, to a low-level output voltage VOL
The character to be transmitted is loaded into
the TRANSMITTER HOLDING REGISTER on
these lines with the THRL Strobe. If a character
of less than 8 bits has been selected (by WLSi
and WLS2), the character is right justified to the
least significant bit, TR-j, and the excess bits
are disregarded. A high-level input voltage, VJH,
will cause a high-level output voltage, VOH, to
be transmitted.
A high-level input voltage, VIH, on this line
loads the CONTROL REGISTER with the
control bits (WLSi, WLS2, EPE, PI, SBS). This
line may be strobed or hard wired to a high-level
input voltage, VIH.
A high-level input voltage, VIH, on this line
inhibits the parity generation and verification
circuits and will clamp the PE output (pin 13) to
VOL If parity is inhibited, the STOP bit(s) will
immediately follow the last data bit of transmission.
This line selects the number of STOP bits to be
transmitted after the parity bit. A high-level
input voltage VIH, on this line selects two STOP
bits, and a low-level input voltage, VIL, selects a
single STOP bit. The TR1863 and TR1865
generate 11/2 stop bits when word length is 5
bits and SBS is High VIH.
These two lines select the character length
(exclusive of parity) as follows:
WLS2
WLSi
Word Length
5 bits
VIL
VIL
6 bits
VIL
VIH
7 bits
VIH
VIL
8 bits
VIH
VIH
This line determines whether even or odd
PARITY is to be generated by the transmitter
and checked by the receiver. A high-level input
voltage, VJH, selects even PARITY and a lowlevel input voltage, VIL, selects odd PARITY.
The transmitter clock frequency is sixteen (16)
times the desired transmitter shift rate.

u

j ni

i

T>HRE •• ~

i

15 CLOCK TIMES
-^
AFTER START OF
,—, I
!
LAST STOP BIT (1) -J
-^
T~r7/^

TR1863/TR1865

•n

I

«_i

H- 1/2 CLOCK

(-«- V2 CLOCK

I
I

\+. END OF LAST STOP
f
BIT (COUNT 1m

(1)NOT VALID FC)R5.0MH Z OPTION

CF33

Cf32

CF31

CF1

CF*4

CF2

Cl35
CF4

CF3

CF5

TRC

f

f THRL
J
I

0

/

^A
TLJDC .

CASE 1 -<

\
TRF -

^——**

(

/

~***~.

(

| THRE

f TRC |

T

-_

^J

B]

r\-\

xI TRC

)

s~

CF4

-

3

-^
D

-H tpd |^-_

^) tpdK _

Viy j TRE

-n'pohr—

[ D ) I
Vl/ ( THRE I

j

^

I

DETA.LH

CJ

V

CR4

f TRC

^s
s~

J

(TYi

"^ tpd **"

W LRO

I

o

—'

CASE!

IF THE POSITIVE TRANSITION OF
THRL OCCURS >250ns PRIOR TO ANY
CLOCK FALLING EDGE (CF3 IN
SAMPLE) THE A, B, C, AND D SIGNALS
WILL BE GENERATED AS SHOWN IN
DETAIL II
CASE II IF THE POSITIVE TRANSITION OF
THRL OCCURS <250ns PRIOR TO ANY
CLOCK FALLING EDGE (CF3 IN
SAMPLE), THE B, C, AND D SIGNALS
MAY BE GENERATED ON THE FOLLOWING CLOCK TIME I E THE B. C,
AND D SIGNALS AS SHOWN IN
DETAIL MAY CHANGE AS FOLLOWS
CF3TOCF4
CF4TOCF5
CR4TOCR5

,—~x

LiJI)
CASE IK

TRO V

NOTE IT IS ADVISABLE TO CONSIDER
CASE II FOR fcLOCK > 4 0 MHZ
DET7UL

I
T KM JSM ITTE R TIMING

325

w

START (1)

STOP START

STOP

DATA

DATA

Rl

DO

i
01

I

RR1-RR8 AND ERROR FLAGS PE, FE, OE(5)

DR(19)

DRR(18)
(2)

DETAIL:

innnnjirLruiJifinnjiJiJir
1

RRC

3

2

4

5

6

7

8

10

9

11

12

13

14

NOMINAL

Rl

))
{(

$§

STOP BIT
TRANSITION

I

-fr

PE, FE(3)

' NOMINAL BIT CENTER
i^

I

-N-

(5) | |

-fr

RR1-RR8, OE(3)

I

-i\

-to-

DRR

DR(3)

HlA-*-| (4)

(1) SEE APPLICATION FLAGS REPORT NO. 1 FOR DESCRIPTION OF START BIT DETECTION
(2) THE DELAY BETWEEN DRR AND DR = td = 500 NS
(3) DR. ERROR FLAGS, AND DATA ARE VALID AT THE
NOMINAL CENTER OF THE FIRST STOP BIT
(4) DRR SHOULD BE HIGH A MINIMUM OF "A" NS (ONEHALF CLOCK TIME PLUS tpd) PRIOR TO THE RISING
EDGE OF DR
(5) DATA AND OE PRECEDES DR, PE, AND FE FLAGS BY
V2 CLOCK
(6) DATA FLAGS WILL REMAIN SET UNTIL A GOOD CHARACTER IS RECEIVED OR MASTER RESET IS APPLIED.

RECEIVER TIMING

326

15

0

WLSLWLS2.S BS , P1.EPE
/
\ j
\
/^
/ ^

TR8-TR1
2

W
V
/'V
/ %

X/ OV
/
-jf 08V
A

THRL\
2.0V \

s

j

/1

tset_^

X !•*

-+

r\ o w \

Ju

, s e t _^,o^t c
™

Pni ^TRDRF

J

pw

V2-ov

^

^-j

f\™

-x

2.0V

k
— tpw

IG

^ -^

8V

°'

(-*— *hold

^|

CONTROL REGISTER LOAD CYCLE

DATA INPUT LOAD CYCLE

SFD

RRD

X

Nk °-

8V

0.8V

*-

Ol

332

Printed m U S A

o

Part 2 / Software
1/

Disk Organization
Single Density Floppy Diskette
Double Density Floppy Diskette
5" 5-Meg Hard Disk
Disk Space Available to the User
Unit of Allocation

1
1
1
2
2
2

2l

Disk Files

3
3
3
3
3
4
4

Methods of File Allocation
Dynamic Allocation
Pre-Allocation
Record Length
Record Processing Capabilities
Record Numbers
3/

TRSDOS File Descriptions
System Files (/SYS)
Utility Programs
Device Driver Programs
Filter Programs
Creating a Minimum Configuration Disk

4/

Device Access
Device Control Block (DCB)
Memory Header

9
9
10

5/

Drive Access
Drive Code Table (DCT)
Disk I/O Table
Directory Records
Granule Allocation Table (GAT)
Hash Index Table (HIT)

11
11
13
13
16
18

File Control Block (FCB)

23
23

^v

6/

7/

File Control

TRSDOS Version 6 Programming Guidelines
Converting to TRSDOS Version 6
Programming With Restart Vectors
KFLAG$ (BREAK)( (PAUSE), and (ENTER) Interfacing
Interfacing to (SPICNFG
Interfacing to @KITSK
Interfacing to the Task Processor
Interfacing RAM Banks 1 and 2
Device Driver and Filter Templates
@CTL Interfacing to Device Drivers

5
5
7
7
7
7

27
27
29
29
32
33
34
36
40
42

8/

Using the Supervisor Calls
Calling Procedure
Program Entry and Return Conditions
Supervisor Calls
Numerical List of SVCs
Alphabetical List of SVCs
Sample Programs

9/

Technical Information on TRSDOS Commands and Utilities

Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Index

A/
B/
C/
D/
E/
F/

TRSDOS Error Messages
Memory Map
Character Codes
Keyboard Code Map
Programmable SVCs
Using SYS 13/SYS

45
45
45
46
49
52
54
189
193
199
201
211
213
215
217

1/Disk Organization
TRSOOS Version 6 can be used with 51/4" single-sided floppy diskettes and
with hard disk. Floppy diskettes can be either single-or double-density. See the
charts betow for the number of sectors per track, number of cylinders, and so
on for each type of disk. (Sectors and cylinders are numbered starting with 0.)

Single-Density Floppy Diskette
Bytes
per
Sector

Sectors
per
Granule

Sectors
per
Track*

Granules
per
Track

Tracks
per
Cylinder

Cylinders
per
Drive

Total
Bytes

256

256

1,280
2,560
2,560
102,400
102,400
(100K)**

(10)

256

40
40

(10)

Double-Density Floppy Diskette
Bytes
per
Sector
256

256

Sectors
per
Granule
—

Sectors
per
Track*

———

6

-

••

Granules
per
Track
—

Tracks
per
Cylinder

~————

(•\o\
(10)

o
0

(18)
(18)

3

i

1

Cylinders
per
Drive
-

—

.........
40
40
40

Total
Bytes
256

1,536
4,608
4,608
184,320
184,320
(180K)**

The number of sectors per track is not included in the calculation because it
is equal to the number of sectors per granule times the number of granules
per track. (5 x 2 = 10 for single density, 6 x 3 = 18 for double density, and
16 x 2=32 for hard disk.)
**Note that this figure is the total amount of space in the given format. Keep in
mind that an entire cylinder is used for the directory and at least one granule
is used for the bootstrap code. This leaves 96.25K available for use on a
single-density data disk and 174K on a double-density data disk.

Software 1

5" 5-Meg Hard Disk
Note: Because of continual advancements in hard disk technology, the number
of tracks and the number of tracks per cylinder may change. Therfore, any Information that comes with your hard disk drive(s) supersedes the Information in
the table below.
Bytes
per
Sector

Sectors
per
Granule

Sectors
per
Track*

Granules
per
Track

(32)

2

(32)

2

Tracks
per
Cylinder

Cylinders
per
Drive

1fi
ID

16

4

153
153

Total
Bytes
4,096
8,192
32,768
5,013,504
5,013,504
(4.896K)

*The number of sectors per track is not included in the calculation because it is
equal to the number of sectors per granule times the number of granules per
track. ( 5 x 2 = 10 for single density, 6 x 3 = 18 for double density, and
16 x 2 = 32 for hard disk.)

Disk Space Available to the User
One granule on cylinder 0 of each disk is reserved for the System. It contains
information about where the directory is located on that disk. If the disk contains
an Operating System, then all of cylinder 0 is reserved. This area contains information used to load TRSDOS when you press the reset button.
One complete cylinder is reserved for the directory, the granule allocation table
(GAT), and the hash index table (HIT). (On single-sided diskettes, one cylinder
is the same äs one track.) The number of this cylinder varies, depending on the
size and type of disk. Also, if any portion of the cylinder normally used for the
directory is flawed, TRSDOS uses another cylinder for the directory. You can
find out where the FORMAT Utility has placed the directory by using the
Free :o*/7Ve command.
On hard disks, an additional cylinder (cylinder 1) is reserved for use in case
your disk drive requires Service. This provides an area for the technician to write
on the disk without harming any data. (If you bring your hard disk in for Service,
you should try to back up the Contents of the disk first, just to be safe.)

Unit of Allocation
The smallest unit of disk space that the System can allocate to a file is a granule. A granule is made up of a set of sectors that are adjacent to one another
on the disk. The number of sectors in a granule depends on the type and size
of the disk. See the Charts on the previous two pages for some typical sizes.

Software 2

2/Disk Fi
Methods of File Allocation
TRSDOS provides two ways to allocate disk space for fites: dynamic allocation
and pre-allocation.

Dynamic Allocation
With dynamic allocation, TRSDOS allocates granules only at the time of write.
For example/when a file is first opened for Output, no space is allocated. The
first allocation of space is done at the first write. Additional space is added äs
required by fürt her writes.
With dynamically allocated files, unused granules are de-allocated (recovered)
when the file is closed.
Unless you execute the CREATE System command, TRSDOS uses dynamic
allocation.

Pre-Allocation
With pre-allocation, the file is allocated a specified number of granules when it
is created. Pre-allocated files can be created only by the System command
CREATE. (See the Disk System Owner's Manual for more information on
CREATE.)
TRSDOS automatically extends a pre-allocated file äs needed. However, it
does not de-allocate unused granules when a pre-allocated file is closed. To
reduce the size of a pre-allocated file, you must copy it to a dynamically allocated file. The COPY (CLONE = N) System command does this automatically.
Files that have been pre-allocated have a 'C' by their names in a directory
listing.

Record Length
TRSDOS transfers data to and from disks one sector at a time. These sectors
are 256-byte blocks, and are also called the system's "physical" records.
You deal with records that are 256 bytes in length or smaller, depending on
what size record you want to work with. These are known äs "logical" records.
You set the size of the logical records in a file when you open the file for the first
time. The size is the number of bytes to be kept in each record. There may be
from 1 to 256 bytes per logical record.
The Operating System automatically accumulates your logical records and
stores them in physical records. Since physical records are always 256 bytes in
length, there may be one or more logical records stored in each physical record.
When the records are read back from disk, the System automatically returns
one logical record at a time. These actions are known äs "blocking" and "deblocking," or "spanning."
For example, if the logical record length is 200, sectors 1 and 2 look like this:

Software 3

record'»

Since they are completely handled by the Operating System, you do not need to
concern yourself with physical records, sectors, granules, tracks, and so on.
This is to your benefit, äs the number of sectors per granule varies from disk to
disk. Also, physical record lengths may change in future versions of TRSDOS,
but the concept of logical records will not.
Note: All files are fixed-length record files with TRSDOS Version 6.

Record Processing Capabilities
TRSDOS allows both direct and sequential file access.
Direct access (sometimes called "random access") lets you process records in
any sequence you specify.
Sequential access allows you to process records in sequence: record n, n +1,
n+2, and so on. With sequential access, you do not specify a record number.
Instead, TRSDOS accesses the record that follows the last record processed,
starting with record 0.
With sequential access files, use the @READ Supervisor call to read the next
record, and the ©WRITE or @VER Supervisor call to Write the next record.
(When the file is first opened, processing Starts at record 0. You can use
@PEOF to position to the end of file.)
To read or write to a direct access file, use the @POSN Supervisor call to Position to a specified record. Then use ©READ, ©WRITE, or ©VER äs desired.
Once ©POSN has been used, the End of File (EOF) marker will not move,
unless the file is extended by writing past the current EOF position.

Record Numbers
Using direct (random) access, you can access up to 65,536 records. Record
numbers Start at 0 and go to 65535.
Using a file sequentially, you can access up to 16,777,216 bytes. To calculate
the number of records you can access sequentially, use the formula:
16,777,216 4- logical record length = number of sequential
records allowed
Below are some examples.
lfthel_RL=256,then:
16,777,216 + 256 = 65,536 records
lftheLRL=128,then:
16,777,216 -s- 128 = 131,072 records
lfthel_RL= SO.then:
16,777,216 - 50 = 335,544 records
lftheLRL=

1,then:
16,777,216 -s-

Software 4

1 = 16,777,216 records

3/TRSDOS File Descriptions
This section describes four types of files found on your TRSDOS master diskette (system files, Utilities, driver programs, and filter programs) and explains
their functions. It also describes how to construct a minimum system disk for
running applications packages.

System Files (/SYS)
TRSDOS Version 6 would occupy considerable memory space if all of it were
resident in memory at any one time. To minimize the amount of memory
reserved for system use, TRSDOS uses overlays.
Using an overlay-driven system involves some compromise. While a User's
application is in progress, different overlays may need to be loaded to perform
certain activities requested of the system. This could cause the system to run
slightly slower than a system which has more of its file access routines always
resident in memory.
The use of overlays also requires that a SYSTEM disk usually be available in
Drive 0 (the system drive). Since the disk containing the Operating system and
its Utilities ieaves little space available to the user, you may want to remove certain parts of the system Software not needed while a particular application is
running. You may in fact discover that your day-to-day operations need only a
minimal TRSDOS configuration. The greater the number of system functions
unnecessary for your application, the more space you can have available for a
"working" system disk. Use the PURGE or REMOVE library command to eliminate unneeded system files from the disk.
The following paragraphs describe the functions performed by each system
Overlay. (In the display produced by the DIR (SYS) library command, the system
overlays are identified by the file extension /SYS.)
Note: Two system files are put on the disk during formatting. They are DIR/SYS
and BOOT/SYS. These files should never be copied from one disk to another
or REMOVEd. TRSDOS automatically Updates any Information necessary
when performing a backup.
SYSO/SYS
This is not an Overlay. It contains the resident pari of the Operating system
(SYSRES). It is also needed to dynamically allocate file space used when writing files. Any disk used for booting the system must contain SYSO. It can be
purged from disks not used for booting.
SYS1/SYS
This Overlay contains the TRSDOS command Interpreter and the routines for
processing the @CMNDI, @CMNDR, @FEXT, @FSPEC, and @PARAM System vectors. This Overlay must be available on all SYSTEM disks.
SYS2/SYS
This Overlay is used for opening or initializing disk files and logical devices. It
also contains routines for processing the @CKDRV, @GTDCB, and @RENAM
system vectors, and routines for hashing file specifications and passwords.
This Overlay must be available on all SYSTEM disks.
SYS3/SYS
This Overlay contains all of the system routines needed to close files and logical
devices. It also contains the routines needed to service the @ FN AM E system
vector. This Overlay must not be removed from the disk.

Software 5

SYS4/SYS
This Overlay contains the System error dictionary. It is needed to issue such
messages äs "File not found," "Directory read error," etc. If you decide to
remove this Overlay from your working SYSTEM disk, all System errors will produce the error message "SYS ERROR" It is recommended that you not remove
this Overlay, especially since it occupies only one granule of space.
SYS5/SYS
This is the "ghost" debugger. It is needed if you intend to test out machine language application Software by using the TRSDOS DEBUG library command. If
your Operation will not require this debugging tool, you may purge this Overlay.
SYS6/SYS
This Overlay contains all of the routines necessary to Service the library commands identified äs "Library A" by the LIB command. This represents the primary library functions. Only very limited use can be made of TRSDOS if this
Overlay is removed from your working SYSTEM disk.
SYS7/SYS
This Overlay contains all of the routines necessary to Service the library commands identified äs "Library B" by the LIB command. A great deal of use can
be made of TRSDOS even without this Overlay. It performs specialized functions that may not be needed in the Operation of specific applications. You can
purge this Overlay if you decide it is not needed on a working SYSTEM disk.
SYS8/SYS
This Overlay contains all of the routines necessary to Service the library commands identified äs "Library C" by the LIB command. A great deal of use can
be made of TRSDOS even without this Overlay. It performs specialized functions that may not be needed in the Operation of specific applications. You can
purge this Overlay if you decide it is not needed on a working SYSTEM disk.
SYS9/SYS
This Overlay contains the routines necessary to Service the extended DEBUG
commands available after a DEBUG (EXT) is performed. This Overlay may be
purged if you will not need the extended DEBUG commands while running your
application. If you remove SYS5/SYS, then you may äs well remove SYS9/SYS,
äs it would serve no useful purpose.
SYS10/SYS
This System Overlay contains the procedures necessary to Service the request
to remove a file. It should remain on your working SYSTEM disks.
SYS11/SYS
This Overlay contains all of the procedures necessary to perform the Job Control Language execution phase. You may remove this Overlay from your working
disks if you do not intend to execute any JCL functions. If SYS6/SYS (which
contains the DO command) has been removed, keeping this Overlay would
serve no purpose.
SYS12/SYS
This System Overlay contains the routines that Service the @DODIR,
@GTMOD, and @RAMDIR System vectors. It should remain on your disks.
SYS13/SYS
This Overlay is reserved for future System use. It contains no code and takes up
no space on the disk. You may remove this Overlay if you wish to free up its
directory slot.

Software 6

• SYS2 must be on the System disk if a configuration file is to be loaded.
• SYS 11 must be present only if any JCL files will be used.
• All three libraries (SYS files 6, 7, and 8) may be purged if no library command will be used.
• SYS5 and SYS9 may be purged if the System DEBUG package is not
needed.
• SYSO may be removed from any disk not used for booting.
• SYS11 (the JCL processor) and SYS6 (containing the DO library command) must both be on the disk if the DO command is to be used. Also,
if you remove SYS6, you may äs well remove SYS11.
• SYS13 may be removed if you have not implemented an ECI, an IEP file,
or if you do not intend to use them.
The presence of any Utility, driver, or filter program is dependent upon your individual needs. You can save most of the TRSDOS features in a configuration
file using the SYSTEM (SYSGEN) command, so the driver and filter programs
will not be needed in run time applications. If you intend to use the HELP Utility,
your disk must contain the DOS/HLP file.
The owner (update) passwords for TRSDOS files are äs follows:
File Type
System files
Filter files
Driver files
Utility files
BASIC
BASIC overlays
CONFIG/SYS
Drive Code Table
Initializer

Extension

Owner Password

(/SYS)
(/FLT)
(/DVR)
(/CMD)

LSIDOS
FILTER
DRIVER
UTILITY
BASIC
BASIC
CCC
UTILITY

(/OV$)
(/DCT)

Software 8

4/Device Access
Device Control Block (DCB)
The Device Control Block (DCB) is an area of memory that contains Information used to Interface the Operating System with various logical devices. These
devices Include the keyboard (*KI), the video display (*DO), a printer (*PR), a
Communications line (*CL), and other devices that you may define.
The following information describes each assigned DCB byte.
DCB+ 0 (TYPE Byte)
Bit 7—If set to "1," the Device Control Block is actually a File Control Block
(FCB) with the file open. Since DCBs and FCBs are similar, and
devices may be routed to files, a "device" with this bit set indicates
a routing to a file.
Bit 6—If set to "1," the device defined by the DCB is filtered or is a device
filter.
Bit 5—If set to "1," the device defined by the DCB is linked.
Bit 4—If set to "1," the device defined by the DCB is routed.
Bit 3—If set to "1," the device defined by the DCB is a NIL device. Any output directed to the device is discarded. For any input request, the
Character returned is a null (ASCII value 0).
Bit 2—If set to "1," the device defined by the DCB can handle requests
generated by the @CTL Supervisor call. See the section on Supervisor Calls for more information.
Bit 1 —If set to "1," the device defined by the DCB can handle Output
requests which normally come from the @PUT Supervisor call.
Bit 0—If set to "1," the device defined by the DCB can handle requests for
input which normally come from the @GET Supervisor call.
DCB + 1 and DCB+2
Contain the address of the driver routine that Supports the hardware assigned
to this DCB. (In the case of a routed or linked device, the vector may point to
another DCB.)
DCB + 3 through DCB+5
Reserved for System use.
DCB+6andDCB+7
These locations normally contain the two alphabetic characters of the devspec.
The System uses the devspec äs a reference in searching the device control
block tables.

Software 9

Memory Header
Modules that TRSDOS loads into memory (filters, drivers, and other memory
modules such äs a SPOOL buffer or the extended DEBUG code) are identified
by a Standard front-end header:
BEGIN:

JR

START

DEFW END-l
DEFB 10

DEFM 'NAMESTRING

MODDCB: DEFW $-$
DEFM 0

JGo to actual code
ibedinninä
»Contains the h i £ h e s t b v t e
»of Memory
»used bx the M o d u l e
»Lentfth of name » 1-15
»characters 5
i b i t s 4-7 reserued for
»systeM use
»Up to 15 a l p h a n u m e r i c
» c h a r a c t e r s » with the first
» C h a r a c t e r A-Z. This should
» b e a unisue name to
» p o s i t i u e l y identify the
iModule»
5DCB pointind to this
« M o d u l e (if a p p l i c a b l e )
»Spare systeM pointer .
»'RESERVED

Any additional data stora*e tfoes here
START:

Start of actual proäraM code

END:

EQU $

As explained under the @GTMOD SVC in the "Supervisor Call" section, the
location of a specific header can be found provided all modules that are put into
memory use this header structure. You can locate the data area for a module
by using @GTMOD to find the Start of the header and then indexing in to the
data area.

Software 10

5/Drive Access
Drive Code Table (DCT)
TRSDOS uses a Drive Code Table (DCT) to Interface the Operating System with
specific disk driver routines. Note especially the fields that specify the allocation
scheme for a given drive. This data is essential in the allocation and accessibility of file records.
The DCT contains eight 10-byte positions — one for each logical drive designated 0-7. TRSDOS Supports a Standard configuration of two-floppy
drives. You may have up to four floppy drives. This is the default initialization when TRSDOS is loaded.
Here is the Drive Code Table layout:
DCT+0
This is the first byte of a 3-byte vector to the disk I/O driver routines. This byte
is normally X'C3.' If the drive is disabled or has not been configured (see the
SYSTEM command in the Disk System Owner's Manual), this byte is a RET
instruction (X'C9').
DCT+1 and DCT-l-2
Contain the entry address of the routines that drive the physical hardware.
DCT+ 3
Contains a series of flags for drive specifications.
Bit 7—Set to "1" if the drive is Software write protected, "0" if it is not. (See
the SYSTEM command in the Disk System Owner's Manual.)
Bit 6—Set to "1" for DDEN (double density), or "0" for SDEN (single
density).
Bit 5—Set to "1" if the drive is an 8" drive. Set to "0" if it is a S1/»" drive.
Bit 4—A "1" causes the selection of the disk's second side. The first side
is selected if this bit is "0." This bit value matches the side indicator
bit in the sector header Written by the Floppy Disk Controller
(FDC).
Bit 3—A "1" indicates a hard drive (Winchester). A "0" denotes a floppy
drive(51/4"or8").
Bit 2—Indicates the time delay between selection of a SW drive and the
first poll of the Status register. A "1" value indicates 0.5 second and
a "0" indicates 1.0 second. See the SYSTEM command in the Disk
System Owner's Manual for more details.
If the drive is a hard drive, this bit indicates either a fixed or removable disk: "1"=fixed, "0" = removable.
Bits 1 and 0—Contain the Step rate specification for the Floppy Disk Controller. (See the SYSTEM command in the Disk System Owner's
Manual.) In the case of a hard drive, this field may indicate the drive
address (0-3).
DCT+4
Contains additional drive specifications.
Bit 7— (Version 6.2 only) If "1", no @CKDRV is done when accessing the
drive. If an application opens several files on a drive, this bit can be
set to speed I/O on that drive after the first successful open is
performed.
Software 11

In versions prior to TRSDOS 6.2, this bit is reserved for future use.
In order to maintain compatibility with future releases of TRSDOS,
do not use this bit.
Bit 6 — If "1", the Controller is capable of double-density mode.
Bit 5—"1" indicates that this is a 2-sided floppy diskette; "0" indicates a
1-sided floppy disk. Dp not confuse this bit with Bit 4 of DCT+3.
This bit shows if the disk is double-sided; Bit 4 of DCT + 3 teils the
Controller what side the current I/O is to be on.
If the hard drive bit (DCT + 3, Bit 3) is set, a "1" denotes double the
cylinder count stored in DCT+6. (This implies that a logical cylinder is made up of two physical cylinders.)
Bit 4—If "1," indicates an alien (non-standard) disk Controller.
Bits 0-3—Contain the physical drive address by bit selection (0001,0010,
0100, and 1000 equal logical Drives 0,1, 2, and 3, respectively, in
a default System). The System Supports a translation only where no
more than one bit can be set.
If the alien bit (Bit 4) is set, these bits may indicate the starting head
number.
DCT+5
Contains the current cylinder position of the drive. It normally Stores a copy of
the Floppy Disk Controllers track register contents whenever the FDC is
selected for access to this drive. It can then be used to reload the track register
whenever the FDC is reselected.
If the alien bit (DCT+4, Bit 4) is set, DCT + 5 may contain the drive Select code
for the alien Controller.
DCT+6
Contains the highest numbered cylinder on the drive. Since cylinders are numbered from zero, a 35-track drive is recorded äs X'22,' a 40-track drive äs X'27/
and an 80-track drive äs X'4F.' If the hard drive bit (DCT+3, Bit 3) is set, the true
cylinder count depends on DCT+4, Bit 5. If that bit is a "1," DCT+6 contains
only half of the true cylinder count.
DCT+7
Contains allocation Information.
Bits 5-7—Contain the number of heads for a hard drive.
Bits 0-4—Contain the highest numbered sector relative to zero. A 10sector-per-track drive would show X'Oä' If DCT+4, Bit 5 indicates
2-sided Operation, the sectors per cylinder equals twice this
number.
DCT+8
Contains additional allocation Information.
Bits 5-7—Contain the number of granules per track allocated in the formatting process. If DCT+ 4, Bit 5 indicates 2-sided Operation, the
granules per cylinder equals twice this number. For a hard drive,
this number is the total granules per cylinder.
Bits 0-4—Contain the number of sectors per granule that was used in the
formatting Operation.
DCT+9
Contains the number of the cylinder where the directory is located. For any
directory access, the System first attempts to use this value to read the directory. If this Operation is unsuccessful, the System examines the BOOT granule
(cylinder 0) directory address byte.

Software 12

Bytes DCT + 6, DCT + 7, and DCT + 8 must relate without conflicts. That is, the
highest numbered sector ( + 1) divided by the number of sectors per granule
(+1) must equal the number of granules per track (+1).

Disk I/O Table
TRSDOS Interfaces with hardware peripherals by means of Software drivers.
The drivers are, in general, coupled to the Operating System through data
Parameters stored in the system's many tables. In this way, hardware not currently supported by TRSDOS can easily be supported by generating driver Software and updating the System tables.
Disk drive sub-systems (such äs Controllers for SW drives, 8" drives, and hard
disk drives) have many parameters addressed in the Drive Code Table (DCT).
Besides those Operating parameters, Controllers also require various commands (SELECT, SECTOR READ, SECTOR WRITE, and so pn) to control the
physical devices. TRSDOS has defined command conventions to deal with
most commands available on Standard Disk Controllers.
The function value (hexadecimal or decimal) you wish to pass to the driver
should go in register B. The available functions are:
Function

Operation Performed

Hex

Dec

X'00'

0
1

DCSTAT

Test to see if drive is assigned in DCT

SELECT

Select a new drive and return Status

1

X'02

2

DCINIT

Set to cylinder 0, restore, set Side 0

X'03'

3

DCRES

Reset the Floppy Disk Controller

X'04'

4

RSTOR

Issue FDC RESTORE command

X'05'

5

STEPI

Issue FDC STEP IN command

X'06'

6

SEEK

Seek a cylinder

X'07'

7

TSTBSY

Test to see if requested drive is busy

X'08'

8

RDHDR

Read sector header information

X'09'

9

RDSEC

Read sector

X'0A'

10

VRSEC

Verify if the sector is readable

X'0B'

11

RDTRK

Issue an FDC track read command

X'0C'

12

HDFMT

Format the device

F

X'0D

13

WRSEC

Write a sector

X'0E'

14

WRSYS

Write a System sector (for example, directory)

X'0F

15

WRTRK

Issue an FDC track Write command

x'or

Function codes X'10' to X'FF* are reserved for future use.

Directory Records (D1REC)
The directory contains information needed to access all files on the disk. The
directory records section is limited to a maximum of 32 sectors because of
physical limitations in the Hash Index Table. Two additional sectors in the directory cylinder are used by the System for the Granule Allocation Table and the
Hash Index Table. The directory is contained on one cylinder. Thus, a 10-sectorper-cylinder formatted disk has, at most, eight directory sectors. See the sec-

Software 13

tion on the Hash Index Table for the formula to calculate the number of directory
sectors.
A directory record is 32 bytes in length. Each directory sector contains eight
directory records (256/32 = 8). On System disks, the first two directory records
of the first eight directory sectors are reserved for System overlays. The total
number of files possible on a disk equals the number of directory sectors times
eight (since 256/32 = 8). The number available for use is reduced by 16 on system disks to account for those record slots reserved for the Operating System.
The following table shows the directory record capacity (file capacity) of each
format type. The dash suffix (-1 or -2) on the items in the density column represents the number of sides formatted (for example, SDEN-1 means single
density, 1-sided).

5" SDEN-1
5" SDEN-2
5" DDEN-1
5" DDEN-2
8" SDEN-1
8" SDEN-2
8" DDEN-1
8" DDEN-2
Hard Disk*

Sectors
per
Cylinder

Directory
Sectors

User Files
on Data
Disk**

User
Files on
SYS Disk

10
20
18
36
16
32
30
60

8
18
16
32
14
30
28
32

62
142
126
254
110
238
222
254

48
128
112
240
96
224
208
240

"Hard drive format depends on the drive size and type, äs well äs the user's
division of the physical drive into logical drives. After setting up and formatting the drive, you can use the FREE library command to see the available
files.
**Note: Two directory records are reserved for BOOT/SYS and DIR/SYS,
and are included in the figures for this column.
TRSDOS Version 6 is upward compatible with other TRSDOS 2.3 compatible
Operating Systems in its directory format. The data contained in the directory
has been extended. An SVC is included to either display an abbreviated directory or place its data in a user-defined buffer area. For detailed information, see
the @DODIR and @RAMDIR SVCs.
The following information describes the Contents of each directory field:

DiR+e
Contains all attributes of the designated file.
Bit 7—If "0," this flag indicates that the directory record is the file's primary
directory entry (FPDE). If "1" the directory record is one of the file's
extended directory entries (FXDE). Since a directory entry can
contain information on up to four extents (see notes on the extent
fields, beginning with DIR+22), a file that is fractured into more
than four extents requires additional directory records.
Bit 6—Specifies a SYStem file if "1," a nonsystem file if "0."
Bit 5—If set to "1," indicates a Partition Data Set (PDS) file.
Bit 4—Indicates whether the directory record is in use or not. If set to "1,"
the record is in use. If "0," the directory record is not active,
although it may appear to contain directory information. In contrast
to some Operating Systems that zero out the directory record when
you remove a file, TRSDOS only resets this bit to zero.
Bit 3—Specifies the visibility. If "1," the file is INVisible to a directory display or other library function where visibility is a parameter. If a "0,"
then the file is VISible. (The file can be referenced if specified by
name by an @INIT or @OPEN SVC.)
Software 14

Bits 0-2—Contain the USER protection level of the file. The 3-bit binary
value is one of the following:
0 = FULL
1=REMOVE

2 = RENAME
3 = WRITE

4 = UPDATE
5 = READ

6 = EXECUTE
7 = NO ACCESS

DIR + 1

Contains various file flags and the month field of the packed date of last
modification.
Bit 7—Set to "1" if the file was "CREATEd" (see CREATE library command in the Disk System Owner's Manual). Since the CREATE
command can reference a file that is currently existing but nonCREATEd, it can turn a non-CREATEd file into a CREATEd one.
You can achieve the same effect by changing this bit to a "1."
Bit 6—If set to "1," the file has not been backed up since its last modification. The BACKUP Utility is the only TRSDOS facility that resets
this flag. It is set during the close Operation if the File Control Block
(FCB + 0, Bit 2) shows a modification of file data.
Bit 5 — If set to "1," indicates a file in an open condition with UPDATE
access or greater.
Bit 4—If the file was modified during a Session where the System date was
not maintained, this bit is set to "1." This specifies that the packed
date of modification (if any) stored in the next three fields is not the
actual date the modification occurred. If this bit is "1," the
directory command displays plus signs ( 4 - ) between the date
fields.
Bits 0-3—Contain the binary month of the last modification date. If this
field is a zero, DATE was not set when the file was established or
since if it was updated.
DIR+2
Contains the remaining date of modification fields.
Bits 3-7—Contain the binary day of last modification.
Bits 0-2—Contain the binary year minus 80. For example, 1980 is coded
äs 000,1981 äs 001,1982 äs 010, and so on.
DIR+ 3
Contains the end-of-file offset byte. This byte and the ending record number
(ERN) form a pointer to the byte position that follows the last byte Written. This
assumes that programmers, interfacing in machine language, properly maintain the next record number (NRN) offset pointer when the file is closed.
DIR+4
Contains the logical record length (LRL) specified when the file was generated
or when it was later changed with a CLONE parameter.
DIR+5throughDIR + 12
Contain the name field of the filespec. The filename is left justified and padded
with trailing blanks.
DIR +13 through DIR +15
Contain the extension field of the filespec. It is left justified and padded with
trailing blanks.
DIR+16 and DIR+ 17
Contain the OWNER password hash code.
DIR+ 18 and DIR+ 19
Contain the USER password hash code. The protection level in DIR+0 is associated with this password.
Software 15

DIR+20 and DIR+ 21
Contain the ending record number (ERN), which is based on füll sectors. If the
ERN is zero, it indicates that no writing has taken place (or that the file was not
closed properly). If the LRL is not 256, the ERN represents the sector where the
EOF occurs. You should use ERN minus 1 to account for a value relative to sector 0 of the file.
DIR+ 22 and DIR+23
This is the first extent field. Its Contents indicate which cylinder Stores the first
granule of the extent, which relative granule it is, and how many contiguous
grans are in use in the extent.
DIR+22—Contains the cylinder value for the starting gran of that extent.
DIR + 23, Bits 5-7—Contain the number of the granule in the cylinder indicated by DIR+22 which is the first granule of the file for that
extent. This value is relative to zero ("0" denotes the first gran,
"1" denotes the second, and so on).
DIR+ 23, Bits 0-4—Contain the number of contiguous granules, relative
to 0 ("0" denotes one gran, "1" denotes two, and so on). Since
the field is five bits, it contains a maximum of X'1 F or 31, which
represents 32 contiguous grans.
DIR+ 24 and DIR+25
Contain the fields for the second extent. The format is identical to that for
Extent 1.
DIR+26 and DIR+27
Contain the fields for the third extent. The format is identical to that for Extent 1.
DIR+28 and DIR+29
Contain the fields for the fourth extent. The format is identical to that for
Extent 1.
DIR+ 30
This is a flag noting whether or not a link exists to an extended directory record.
If no further directory records are linked, the byte contains X'FP A value of X'FE'
in this byte establishes a link to an extended directory entry. (See "Extended
Directory Records" below.)
DIR+31
This is the link to the extended directory entry noted by the previous byte. The
link code is the Directory Entry Code (DEC) of the extended directory record.
The DEC is actually the ppsition of the Hash Index Table byte mapped to the
directory record. For more Information, see the section "Hash Index Table."

Extended Directory Records
Extended directory records (FXDE) have the same format äs primary directory
records, except that only Bytes 0,1, and 21-31 are utilized. Within Byte 0, only
Bits 4 and 7 are significant. Byte 1 contains the DEC of the directory record of
which this is an extension. An extended directory record may point to yet
another directory record, so a file may contain an "unlimited" number of extents
(limited only by the total number of directory records available).

Granule Allocation Table (GAT)
The Granule Allocation Table (GAT) contains Information on the free and
assigned space on the disk. The GAT also contains data about the formatting
used on the disk.

Software 16

A disk is divided into cylinders (tracks) and sectors. Each cylinder has a specified number of sectors. A group of sectors is allocated whenever additional
space is needed. This group is called a granule. The number of sectors per
granule depends on the total number of sectors available on a logical drive. The
GAT provides for a maximum of eight granules per cylinder.
In the GAT bytes, each bit set to "1" indicates a corresponding granule in use
(or locked out). Each bit reset to "0" indicates a granule free to be used. In a
GAT byte, bit 0 corresponds to the first relative granule, bit 1 to the secönd relative granule, bit 2 the third, and so on. A SW single density diskette is formatted at 10 sectors per cylinder, 5 sectors per granule, 2 granules per cylinder.
Thus, that configuration uses only bits 0 and 1 of the GAT byte. The remainder
of the GAT byte contains all 1's, denoting unavailable granules. Other formatting
conventions are äs follows:

5" SDEN
5" DDEN
8" SDEN
8" DDEN
Hard Disk

Sectors
per
Cylinder

Sectors
per
Granule

Granules
per
Cylinder

Maximum
No.of
Cylinders

10

5
6
8
10
16

2
3
2
3
8

80
80
77
77
153

18
16
30
32

*Hard drive format depends on the drive size and type, äs well äs the User's division of the drive into logical drives. These values assume that one physical
hard disk is treated äs one logical drive.
The above table is valid for single-sided disks. TRSDOS supports double-sided
Operation if the hardware interfacing the physical drives to the CPU allows it. A
two-headed drive functions äs a single logical drive, with the secönd side äs a
cylinder-for-cylinder extension of the first side. A bit in the Drive Code Table
(DCT+4, Bit 5) indicates one-sided or two-sided drive configuration.
A Winchester-type hard disk can be divided by heads into multiple logical
drives. Details are supplied with Radio Shack drives.
The Granule Allocation Table is the first relative sector of the directory cylinder.
The following information describes the layout and contents of the GAT.
GAT+XW through GAT+X'SP
Contains the free/assigned table information. GAT+0 corresponds to cylinder
0, GAT +1 corresponds to cylinder 1, GAT + 2 corresponds to cylinder 2, and so
on. As noted above, bit 0 of each byte corresponds to the first granule on the
cylinder, bit 1 to the secönd granule, and so on. A value of "1" indicates the
granule is not available for use.
GAT+XW through GAT+X'BF
Contains the available/locked out table information. It corresponds cylinder for
cylinder in the same way äs the free/assigned table. It is used during mirrorimage backups to determine if the destination diskette has the proper capacity
to effect a backup of the source diskette. This table does not exist for hard
disks; for this reason, mirror-image backups cannot be performed on hard disk.
GAT+X'C0' through GAT+X'CA'
Used in hard drive configurations; extends the free/assigned table from X'00'
through X'CA'.Hard drive capacity up to 203 (0-202) logical or 406 physical cylinders is supported.
GÄT+X'CB'
Contains the Operating System version that was used in formatting the disk.
For example, disks formatted under TRSDOS 6.2 have a value of X'62'
contained in this byte. It is used to determine whether or not the disk
contains all of the parameters needed for TRSDOS Operation.

Software 17

GAT+X'CC'
Contains the number of cylinders in excess of 35. tt is used to minimize the time
required to compute the highest numbered cylinder formatted on the disk. It is
excess 35 to provide compatibility with allen Systems not maintaining this byte.
If you have a disk that was formatted on an allen System for other than 35 cylinders, this byte can be automatically configured by using the REPAIR Utility.
(See the section on the REPAIR Utility in the Disk System Owner's Manual.)
GAT+X'CD'
Contains data about the formatting of the disk.
Bit 7—If set to "1," the disk is a data disk. If "0," the disk is a System disk.
Bit 6—If set to "1," indicates double-density formatting. If "0," indicates
single-density formatting.
Bit 5—If set to "1," indicates 2-sided disk. If "0," indicates 1-sided disk.
Bits 3-4—Reserved.
Bits 0-2—Contain the number of granules per cylinder minus 1.
GAT+X'CE' and GAT+X'CF
Contain the 16-bit hash code of the disk master password. The code is stored
in Standard Iow-order, high-order format.
GAT+X'DO' through GAT+X'D7'
Contain the disk name. This is the name displayed during a FREE or DIR Operation. The disk name is assigned during formatting or during an ATTRIB disk
renaming Operation. The name is left justified and padded with blanks.
GAT+X'D8' through GAT+X'DP
Contain the date that the diskette was formatted or the date that it was used äs
the destination in a mirror Image backup Operation in the format mm/dd/yy.
GAT+X'EO' through GAT+X'FP
Reserved for system use.
In Version 6.2:
GAT+X'EO' through GAT + XT4'
Reserved for system use.
GAT+XT5' through GAT+X'FF
Contain the Media Data Block (MDB).
GAT + XT5' through GAT + X'FS' — the identifying header. These four
bytes contain a 3 (X'03'), followed by the letters LSI (X'4C',X'53',X'49').
GAT + X'F8' through GAT9 + X'FF' — the last seven bytes of the DCT
in use when the media was formatted. FORMAT, MemDISK, and
TRSFORM6 install this Information. See Drive Control Table (DCT) for
more information on these bytes.

Hash Index Table (HIT)
The Hash Index Table is the key to addressing any file in the directory. It pinpoints the location of a file's directory with a minimum of disk accesses, keeping
overhead Iow and providing rapid file access.
The system's procedure is to construct an 11-byte filename/extension field. The
filename is left-justified and padded with blanks. The file extension is then
inserted and padded with blanks; it occupies the three least significant bytes of

Software 18

the 11-byte field. This field is processed through a hashing algorithm which produces a single byte value in the ränge X'01' through X'FR (A hash value of XW
indicates a spare HIT position.)
The System then Stores the hash code in the Hash Index Table (HIT) at a Position corresponding to the directory record that contains the file's directory. Since
more than one 11-byte string can hash to identical codes, the opportunity for
"collisions" exists. For this reason, the search algorithm scans the HIT for a
matching code entry, reads the directory record corresponding to the matching
HIT position, and compares the filename/extension stored in the directory with
that provided in the file specification. If both match, the directory has been
found. If the two fields do not match, the HIT entry was a collision and the algorithm continues its search from the next HIT entry.
The position of the HIT entry in the hash table is called the Directory Entry Code
(DEC) of the file. All files have at least one DEC. Files that are extended beyond
four extents have a DEC for each extended directory entry and use more than
one filename slot. To maximize the number of file slots available, you should
keep your files below five extents where possible.
Each HIT entry is mapped to the directory sectors by the DEC's position in the
HIT. Think of the HIT äs eight rows of 32-byte fields. Each row is mapped to one
of the directory records in a directory sector: The first HIT row is mapped to the
first directory record, the second HIT row to the second directory record, and so
on. Each column of the HIT fieid (0-31) is mapped to a directory sector. The first
column is mapped to the first directory sector in the directory cylinder (not
including the GAT and HIT). Therefore, the first column corresponds to sector
2, the second column to sector 3, and so on. The maximum number of HIT columns used depends on the disk formatting according to the formula:
N = number of sectors per cylinder minus two, up to 32.
The following chart shows the correlation of the Hash Index Table to the directory records. Each byte value shown represents the position in the HIT. This
position value is the DEC. The actual contents of each byte is either a X(00)
indicating a spare slot, or the 1-byte hash code of the file that occupies the corresponding directory record.
Columns
Row1 00
10

01
11

02
12

03
13

04
14

05
15

06
16

07
17

08
18

09
19

0A
1A

OB 0C
1B 1C

0D
1D

0E
1E

0F
1F

Row 2 20
30

21
31

22
32

23
33

24
34

25
35

26
36

27
37

28
38

29
39

2A
3A

2B
3B

2C
3C

20
3D

2E
3E

2F
3F

Row 3 40
50

41
51

42
52

43
53

44
54

45
55

46
56

47
57

48
58

49
59

4A
5A

4B
5B

4C
5C

4D
5D

4E
5E

4F
5F

Row 4 60
70

61
71

62
72

63
73

64
74

65
75

66
76

67
77

68
78

69
79

6A
7A

6B
7B

6C
7C

6D
7D

6E
7E

6F
7F

Row 5 80
90

81
91

82
92

83
93

84
94

85
95

86
96

87
97

88
98

89
99

8A
9A

8B
9B

8C
9C

8D
9D

8E
9E

8F
9F

Row 6 A0
B0

A1
B1

A2
B2

A3
B3

A4
B4

A5
B5

A6
B6

A7
B7

A8
B8

A9
B9

AA
BA

AB
BB

AC AD
BC BD

AE
BE

AF
BF

Row7 C0
DO

C1
D1

C2
D2

C3
D3

C4
D4

C5
D5

C6
D6

C7
D7

C8
D8

C9
D9

CA
DA

CB CG CD
DB DC DD

CE
DE

CF
DF

Row 8 E0
F0

E1
F1

E2
F2

E3
F3

E4
F4

E5
F5

E6
F6

E7
F7

E8
F8

E9
F9

EA
FA

EB
FB

EE
FE

EF
FF

EC ED
FC FD

A 51/4" single density disk has 10 sectors per cylinder, two of which are reserved
for the GAT and HIT. Since only eight directory sectors are possible, only the
first eight positions of each HIT row are used. Other formats use more columns
of the HIT, depending on the number of sectors per cylinder in the formatting
scheme.
The eight directory records for sector 2 of the directory cylinder correspond to
assignments in HIT positions 00, 20, 40, 60, 80, A0, CO, and EO. On System

Software 19

disks, the following positions are reserved for System overlays. On data disks,
these positions (except for 00 and 01) are available to the user.
00 — BOOT/SYS
01 — DIR/SYS
02 — SYSO/SYS
03 — SYS1 /SYS
04 — SYS2/SYS
05 — SYS3/SYS
06 — SYS4/SYS
07 — SYS5/SYS

20 — SYS6/SYS
21 — SYS7/SYS
22 — SYS8/SYS
23 — SYS9/SYS
24 — SYS1 O/SYS
25 — SYS11 /SYS
26 — SYS12/SYS
27 — SYS13/SYS

These entry positions correspond to the first two rows of each directory sector
for the first eight directory sectors. Since the Operating System accesses these
overlays by position in the HIT rather than by filename, these positions are
reserved on System disks.
The design of the Hash Index Table limits the number of files on any one drive
to a maximum of 256.

Locating a Directory Record
Because of the coding scheme used on the entries in the HIT table, you can
locate a directory record with only a few instructions. The instructions are:
AND
ADD

1FH
A»2

(calculates the sector)
and

AND

0E0H
(calculates the offset in that sector)

For example, if you have a Directory Entry Code (DEC) of X'84',the following
occurs when these instructions are performed:
Value of accumulator
A=X'84'
AND

1FH

ADD

A»2

A = X'04'
A = X'06'

The record is in the seventh
sector of the directory cylinder
(0-6)
Using the Directory Entry Code (DEC) again, you can find the offset into the
sector that was found using the above instructions by executing one
instruction:
Value of accumulator
A=X'84'
AND

0E0H
A = X'80'
The directory record is X'80' (128)
bytes from the beginning of
the sector

If the record containing the sector is loaded on a 256-byte boundary (LSB of the
address is X'OO') and HL points to the starting address of the sector, then you
can use the above value to calculate the actual address of the directory record
by executing the instruction:
LD

L »A

Software 20

When executed after the calculation of the offset, this causes HL to point to the
record. For example:
A=X'80'
LD
LD

H L »4 2 0 0 H ; Where sector is loaded
L »A
;Replace LSB with offset

HL now contains 4280H, which is the address of the directory record you
wanted.
If you cannot place the sector on a 256-byte boundary, then you can use the
following instructions:
A=X'80'
LD
LD

H L »4 2 5 6 H ; Where sector is loaded
E »A
;Put offset in E (LSB)

LD
ADD

D »0
HL tDE

;Put a zero in D (MSB)
;Add two values together

HL now contains 42D6H, which is the address of the directory record.
Note that the first DEC found with a matching hash code may be the file's
extended directory entry (FXDE). Therefore, if you are going to write System
code to deal with this directory scheme, you must properly deal with the FPDE/
FXDE entries. See Directory Records for more information.

Software 21

6/File Control
File Control Block (FCB)
The File Control Block (FCB) is a 32-byte memory area. Betöre the file is
opened, this space holds the file's filespec. After an @OPEN or @INIT Supervisor call is performed, the System uses this area to Interface with the file, and
replaces the filespec with other information. When the file is closed, the filespec
(without any specified password) is returned to the FCB.
While a file is open, the Contents of the FCB are dynamic. As records are Written
to or read from the disk file, specific fields in the FCB are modified. Avoid changing the contents of the FCB during the time a file is open, unless you are sure
that the change will not affect the integrity of the file.
During most System access of the FCB, the IX index register is used to reference each field of data. Register pair DE is used mainly for the initial reference
to the FCB address. The information contained in each field of the FCB is äs
follows:
FCB+0
Contains the TYPE code of the control block.
Bit 7—If set to "1," indicates that the file is in an open condition; if "0," the
file is assumed closed. This bit can be tested to determine the
"open" or "closed" Status of an FCB.
Bit 6—Is set to "1" if the file was opened with UPDATE access or higher.
Bit 5—Indicates a Partition Data Set (PDS) type file.
Bits 4-3—Reserved for future use.
Bit 2—Is set to "1" if the System performed any WRITE Operation on this
file. It is used to Update the MOD flag in the directory record when
the file is closed.
Bits 1 -0—Reserved for future use.
FCB + 1

Contains Status flag bits used in read/write operations by the System.
Bit 7—If set to "1," indicates that I/O operations will be either füll sector
operations or byte operations of logical record length (LRL) less
than 256. If "0," only sector operations will be performed. If you are
going to use only full-sector I/O, you can reduce System overhead
by specifying the LRL at open time äs 0 (indicating 256). An LRL
of other than 256 sets bit 7 to "1" on open.
Bit 6—If set to "1," indicates that the end of file (EOF) is to be set to ending
record number (ERN) only if next record number (NRN) exceeds
the current value of EOF. This is the case if random access is to be
used. During random access, the EOF is not disturbed unless you
extend the file beyond the last record slot. Any time the position
routine (@POSN) is called, bit 6 is automatically set. If bit 6 is "0,"
then EOF will be updated on every WRITE Operation.
Bit 5—If "0," then the disk I/O buffer contains the current sector denoted
by NRN. If set to "1," then the buffer does not contain the current
sector. During byte I/O, bit 5 is set when the last byte of the sector
is read. A sector read resets the bit, showing the buffer to be
current.

Software 23

Bit 4—If set to "1" indicates that the buffer contents have been changed
since the buffer was read from the file. It is used by the System to
determine whether the buffer must be Written back to the file before
reading another record. If "0," then the buffer contents were not
changed.
Bit 3—Used to specify that the directory record is to be updated each time
the NRN exceeds the EOF. (The normal Operation is to Update the
directory only when an FCB is closed.) Some unattended operations may use this extra measure of file protection. It is specified by
adding an exclamation mark ("!") to the end of a filespec when the
filespec is requested at open time.
Bits 2-0—Contain the user (access) protection level äs retrieved from the
directory of the file. The 3-bit binary value is one of the following:
0 = FULL
1=REMOVE

2 = RENAME
3 = WRITE

4 = UPDATE
5 = READ

6 = EXECUTE
7 = NO ACCESS

FCB+ 2
Used by Partition Data Set (PDS) files.
FCB+ 3 and FCB+ 4
Contain the buffer address in Iow-order, high-order format. This is the buffer
address specified in register pair HL when the @INIT or @OPEN SVC is
performed.
FCB+ 5
Contains the relative byte offset within the current buffer for the next I/O Operation. If this byte has a zero value, then FCB +1, Bit 5 must be examined to see
if the first byte in the current buffer is the target position or if it is the first byte of
the next record.- If you are performing sector I/O of byte data (that is, maintaining your own buffering), then it is important to maintain this byte when you close
the file if the true end of file is not at a sector boundary.
FCB+ 6
Bits 3-7—Reserved for System use.
Bits 0-2—Contain the logical drive number in binary of the drive containing the file. Do not modify this byte; altering this value may damage
other files. This byte and FCB + 7 are the only links to the file's
directory Information.
FCB+7
Contains the directory entry code (DEC) for the file. This code is the offset in the
Hash Index Table where the hash code for the file appears. Do not modify this
byte; altering this value may damage other files. This byte and FCB + 6 are the
only links to the directory information for the file.
FCB+8
Contains the end-of-file byte offset. This byte is similar to FCB + 5 except that it
pertains to the end of file rather than to the next record number.
FCB+9
Contains the logical record length that was in effect when the file was opened.
This may not be the same LRL that exists in the directory. The directory LRL is
generated at the file creation and never changes unless the file is overwritten.
FCB+ 10 and FCB+ 11
Contain the next record number (NRN), which is a pointer for the next I/O Operation. When a file is opened, NRN is zero, indicating a pointer to the beginning.
Each sequential sector I/O advances NRN by one.

Software 24

FCB + 12andFCB + 13
Contain the ending record number (ERN) of the file. This is a pointer to the sector that contains the end-of-file indicator. In a null file (one with no records),
ERN equals 0. If one sector has been Written, ERN equals 1.

FCB + 14andFCB + 15
Contain the same Information äs the first extent of the directory. This represents
the starting cylinder of the file (FCB +14) and the starting relative granule within
the starting cylinder (FCB +15). FCB +15 also contains the number of contiguous granules allocated in the extent. These bytes are used äs a pointer to the
beginning of the file referenced by the FCB.
FCB +16 through FCB +19
This 4-byte entry contains granule allocation information for an extent of the file.
Relative bytes 0 and 1 contain the total number of granules allocated to the file
up to but not including the extent referenced by this field. Relative byte 2 contains the starting cylinder of this extent. Relative byte 3 contains the starting relative granule for the extent and the number of contiguous granules.
FCB + 20 through FCB + 23
Contain information similar to the above but for a second extent of the file.
FCB+24 through FCB + 27
Contain information similar to the above but for a third extent of the file.
FCB + 28 through FCB + 31
Contain information similar to the above but for a fourth extent of the file.
The file control block contains information on only four extents at one time. If
the file has more than four extents, additional directory accessing is done to
shift the 4-byte entries in order to make space for the new extent information.
Although the System can handle a file of any number of extents, you should
keep the number of extents small. The most efficient file is one with a single
extent. The number of extents can be reduced by copying the file to a disk that
contains a large amount of free space.

Software 25

7/TRSDOS Version 6
Programming Guidelines
Converting to TRSDOS Version 6
This section provides suggestions on writing programs effectively with
TRSDOS Version 6, and on converting programs created with TRSDOS 1.3
and LDOS 5.1 Operating Systems for use with TRSDOS Version 6. This information is by no means complete, but presents some important concepts to
keep in mind when using TRSDOS Version 6.
When programming in assembly language, you can use TRSDOS Version 6
routines for commonly used operations. These are accessed through the
Supervisor calls (SVCs) instead of absolute call addresses. Nothing in the system can be accessed via any absolute address reference (except Z-80 RST
and NMI jump vectors).
IMPORTANT NOTE: TRSDOS provides all functions and storage through
Supervisor calls. No address or entry point below 3000H is documented or supported by Radio Shack.
The keyboard is not accessible via "peeking," and the Video RAM cannot be
"poked." The keyboard and Video are accessible only through the appropriate
SVCs.
Another distinction is that TRSDOS Version 6 handling of logical byte I/O
devices (keyboard, Video, printer, Communications line) completely Supports
error Status feedback. A FLAG convention is uniform throughout these device
drivers äs well äs physical byte I/O associated with files. The device handling
in TRSDOS Version 6 is completely independent. That means that byte I/O,
both logical and physical, can be routed, filtered, and linked. Therefore, it is
important to test Status return codes in all applications using byte I/O regardless of the device that the application expects to be used, since re-direction to
some other device is possible at the TRSDOS level. Appropriate action must be
taken when errors are detected.
Modules loaded into memory and protected by Iowering HIGH$ must Include
the Standard header, äs described earlier under "Memory Header." The
@GTMOD Supervisor call requires that this header be present in every resident
module for proper Operation.
The file password protection terms of UPDATE and ACCESS have been
changed in TRSDOS Version 6 to OWNER and USER, respectively. The additional file protection level of UPDATE has been added. A file with UPDATE protection level can be read or Written to, but its end of file cannot be extended.
This protection can be useful in a random access fixed-size file or in a file where
shared access is to take place.
Files opened with UPDATE or greater access are indicated äs open in their
directory. Attempting to open the file again forces a change to READ access
protection and a "File already open" error code. It is therefore important for
applications to CLOSE files that are opened.
For the convenience of applications that access files only for reading, you can
inhibit the "file open bit." If you set bit 0 of the System flag SFLAG$ (see the
@FLAGS Supervisor call), the file open bit is not set in the file's directory. Once
set, the next @OPEN or @INIT SVC automatically resets bit 0 of SFLAG$.
Note that you cannot use this procedure for files being Written to, since it inhibits
the CLOSE process.

Software 27

Some application programs need access to certain System parameters and
variables. A number of flags, variables, and port images can be accessed relative to a flag pointer obtained via the @FLAGS Supervisor call. These Parameters are only accessible relative to this pointer, äs the pointer's location may
change. (See the explanation of the @FLAGS SVC.)
All applications must honor the contents of HIGH$. This pointer contains the
highest RAM address usable by any program. You can retrieve and change
HIGH$ by using the @HIGH$ SVC.
TRSDOS Version 6 library commands and Utilities supply a return code (RC) at
completion. The RC is returned in register pair HL. The value returned is eitner
zero (indicating no error), a number from one through 62 (indicating an error äs
noted in Appendix A, TRSDOS Error Messages), or X'FFFF' (indicating an
extended error which is currently not assigned an error number). TRSDOS Version 6 Job Control Language (JCL) aborts on any program terminating with a
non-zero RC value. Applications should therefore properly set the return code
register pair HL before exiting.
TRSDOS Version 6 library commands are also invokable via the @CMNDR
SVC which executes the command. Library commands properly maintain the
Stack Pointer (SP) and exit via a RET instruction. In this manner, control is
returned to the invoking program with the RC present for testing. For commands invoked with the @CMNDI SVC or prompted for via the @EXIT SVC,
the SP is restored to the System Stack. The top of the Stack will contain an
address suitable for simulating an @EXIT SVC; thus, if your application program properly maintains the integrity of the Stack pointer, it can exit after setting
the RC via a RET instruction instead of an @EXIT SVC.
TRSDOS Version 6 diskette and file structure is identical to that used in LDOS
5.1. This includes formatting, directory structure, and data address mark conventions. TRSDOS Version 6 System diskettes, however, use the entire BOOT
track (track 0). This compatibility means that data files may be used interchangeably between LDOS 5.1 equipped machines and TRSDOS Version 6
equipped machines; the diskettes themselves are readable and writable across
both Operating Systems.
The methods of Internal handling of device linking and filtering have been
changed from LDOS 5.1. (It is beyond the scope of this manual to explain the
intemal functioning of TRSDOS Version 6.) Device filters must adhere to a strict
protocol of linkage in order to function properly. See the section on "Device
Driver and Filter Templates" for Information on device driver and filter protocol.

Stack Handling Restrictions*
Interrupt tasks and filters that deal with the keyboard or Video must not place
the Stack pointer above X'F3FF! This is because any Operation that requires the
keyboard or Video RAM Switches in the 3K bank at X'F400' and suppresses the
Stack until it is switched out again. If the System accesses the Stack at any time
during this period, the integrity of the Stack is destroyed.

*ln TRSDOS 6.0.0, the Stack cannot be placed above X'F3FF for any reason.

Software 28

Programming With Restart Vectors
The Restart instruction (RST) provides the assembly language programmer
with the ability to call a subroutine with a one-byte call. If a routine is called
many times by a program, the amount of space that is saved by using the RST
instruction (instead of a three-byte CALL) can be significant.
In TRSDOS a RST instruction is also used to interface to the Operating System.
The System uses RST 28H for Supervisor calls. RSTS 00H, 30H, and 38H are
for the system's Internal use.
RSTs 08H, 10H, 18H, and 20H are available for your use. Caution: Some programs, such äs BASIC, may use some of these RSTs.
Each RST instruction calls the address given in the Operand field of the instruction. For example, RST 18H causes the System to push the current program
counter address onto the Stack and then set the program counter to address
0018H. RST 20H causes a jump to location 0020H, and so on.
Each RST has three bytes reserved for the subroutine to use. If the subroutine
will not fit in three bytes, then you should code a jump instruction (JP) to where
the subroutine is located. At the end of the subroutine, code a return instruction
(RET). Control is then transferred to the instruction that follows the RST.
For example, suppose you want to use RST 18H to call a subroutine named
"ROUTINE." The following routine loads the restart vector with a jump instruction and saves the old Contents of the restart vector for later use.
SETRST:

LD
LD
LD
LD

IX,0018H
IY»RDATA
B»3
A»(IX)

«Restart area address
»Data area address
» N u w b e r of b y t e s to m o u e
LOOP:
iRead a b v t e frow
» r e s t a r t area
LD
C»(IY)
iRead a b v t e from data
i area
LD
(IX) tC
»Store t h i s b v t e in
irestart area
LD
(IY)»A
»Store this b v t e in data
iarea
INC
IX
» I n c r e m e n t restart area
»Pointe r
INC
IY
» I n c r e m e n t data area
»pointe r
DJNZ
LOOP
»Loop t i l l 3 bytes moued
RET
» R e t u r n when done
RDATA:
DEFB
0C3H
»Jump instruction (JP)
DEFW
ROUTINE
»Operand (nawe of
»sub routine)
Before exiting the program, calling the above routine again puts the original
contents of the restart vector back in place.

KFLAG$ (BREAK). (PAUSE), and
Interfacing

ft

KFLAG$ contains three bits associated with the keyboard functions of BREAK,
PAUSE ((SHIFT) (D), and ENTER. A task processor Interrupt routine (called the
KFLAG$ Scanner) examines the physical keyboard and sets the appropriate
KFLAG$ bit if any of the conditions are observed. Similarly, the RS-232C driver
routine also sets the KFLAG$ bits if it detects the matching conditions being
received.

Software 29

Many applications need to detect a PAUSE or BREAK while they are running.
BASIC checks for these conditions after each logical Statement is executed
(that is, at the endofa line or at a ":"). That is how, in BASIC, you can stop a
program with the [BREAK) key or pause a listing.
One method of detecting the condition in previous TRSDOS Operating Systems
was to issue the @KBD Supervisor call to check for BREAK or PAUSE
((SfllETXM)), ignoring all other keys. Unfortunately, this caused keyboard typeahead to be ineffective; the @KBD SVC flushed out the type-ahead buffer if
any other keystrokes were stacked up.
Another method was to scan the keyboard, physically examining the keyboard
matrix. An undesirable side effect of this method was that type-ahead stored up
the keyboard depression for some future unexpected input request. Examining
the keyboard directly also inhibits remote terminals from passing the BREAK or
PAUSE condition.
In TRSDOS Version 6, the KFLAG$ Scanner examines the keyboard for the
BREAK, PAUSE, and ENTER functions. If any of these conditions are detected,
appropriate bits in the KFLAG$ are set (bits 0,1, and 2 respectively).
Note that the KFLAG$ Scanner only sets the bits. It does not reset them
because the "events" would occur too fast for your program to detect. Think of
the KFLAG$ bits äs a latch. Once a condition is detected (latched), it remains
latched until something examines the latch and resets it—a function to be performed by your KFLAG$ detection routine.
Under Version 6.2, you can use the @CKBRKC SVC, SVC 106, to see if the
BREAK key has been pressed. If a BREAK condition exists, @CKBRKC resets
the break bit of KFLAG$.
For Illustration, the following example routine uses the BREAK and PAUSE
conditions:

EQU
EOU
EQU
EOU
EOU
LD
CKPAWS
RST
LD
RRCA
JP
RRCA
RET
CALL
PUSH
FLUSH
LD
RST
JR
POP
PROMPT PUSH
LD
RST
POP
CP
JP
CP
JR
RESKFL PUSH
PUSH
LD
RST
RESKFL1 LD
AND
KFLAG$
SFLAGS
@KBD
@KEY
@PAUSE

10
101
8
1
16
A»@FLAGS
A»@FLAGS
28H
A»

» C h e c K if fintfer is

AND

3

ist i 11 on Key

JR

NZtRESKFLl

POP
POP
RET

AF
HL

« R e s e t it adain
i R e s t o r e reöisters
«and e x i t

The RESKFL subroutine should be called when you first enter your application.
This is necessary to clear the flag bits that were probably in a "set" condition.
This "primes" the detection. The routine should also be called once a BREAK,
PAUSE, or ENTER condition is detected and handled. (You need to deal with
the flag bits for only the conditions you are using.)

Interfacing to @ICNFG
With the TRSDOS library command SYSGEN, many users may wish to SYSGEN the RS-232C driver. Before doing that, the RS-232C hardware (UART,
Baud Rate Generator, etc.) must be initialized. Simply using the SYSGEN command with the RS-232C driver resident is not enough; some initialization
routine is necessary. The @ICNFG (Initialization CoNFiGuration) vector is
included in TRSDOS to provide a way to invoke a routine to initialize the RS232C driver when the System is booted. It also provides a way to initialize the
hard disk Controller at power-up (required by the Radio Shack hard disk
System).
The final stages of the booting process loads the configuration file CONFIG/
SYS if it exists. After the configuration file is loaded, an initialization subroutine
CALLs the @ICNFG vector. Thus, any initialization routine that is part of a
memory configuration can be invoked by chaining into @ICNFG.
If you need to configure your own routine that requires initialization at power-up,
you can chain into @ICNFG. The following procedure illustrates this link. The
first thing to do is to move the Contents of the @ICNFG vector into your initialization routine:
LD

A»@FLAGS

RST

28H

LD
LD
LD
LD
LD

A»(IY+28)
(LINK)»A
L»(IY+28)
H»(IY+30)
(LINK+1) »HL

«Get flads p o i n t e r
« i n t o refiste r IY
iGet o p c o d e
»Get address LOW
«Get address HIGH

This subroutine does this by transferring the 3-byte vector to your routine. You
then need to relocate your routine to its execution memory address. Once this

Software 32

is done, transfer the relocated initialization entry point to the @ICNFG vector äs
ajumpinstruction:

ft

LD
LD
LD

HL»INIT
(IY+29)»L
(IY+30)»H

;Get (relocated)
» i n i t address

LD
LD

A»0C3H
 LOP).
If A =£ X' 1C' or X' 1 D,' then A = error number.
General:
Only AP is altered by this SVC.
Example:
See Sample Program C, lines 352-353.

Software 58

(a CKTSK

SVC Number 28

Check if Task Slot in Use
Checks to see if the specified task slot is in use.
Entry Conditions:
A = 28(X'1C')
C=task slot to check (0-11)
Exit Conditions:
Success always.
If Z flag is set, the task slot is available for use.
If NZ flag is set, the task slot is already in use.
General:
AF and HL are altered by this SVC.
Example:
See Sample Program F, lines 70-73.

Software 59

@CLOSE

SVC Number 60

Close a File or Device
Terminates Output to a file or device. Any unsaved data in the buffer area is
saved to disk and the directory is updated. All files that have been Written to
must be closed, äs well äs all files opened with UPDATE or higher access.
If you remove a diskette containing an open file, any attempt to close the file
results in the message:
** CLOSE FAULT ** error message,  to retry,  to
abort
where error message is usually "Drive not ready" You may put the diskette
backinthedriveand:
1. Press CENTER) to close the file.
2. Press (BREAK) to abort the close.
If you press (BREAK), the NZ flag is set and Register A contains X'20', the error
code for an Illegal drive number error.
Entry Conditions:
A =60(X'3C')
DE=pointer to FCB or DCB to close
Exit Conditions:
Success, Z flag set. The file or device was closed. The filespec (excluding
the password) or the devspec is returned to the FCB or DCB.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
Example:
See Sample Program C, lines 360-368.

Software 60

@CLS

SVCNumbeMOS

Clear Video Screen

Version 6.2 only

Clears the Video screen by sending a Home Cursor (X'1 C') and Clear to End of
Frame (X'1 F') sequence to the video driver.
Entry Conditions:
A = 105(X'69')
Exit Conditions:
Success, Z flag is set.
Failure, NZ is set.
A = errornumber
General:
Only AF is altered by this SVC.

Software 61

(a CM N DI

SVC Number 24

Execute Command with Return to System
Passes a command string to TRSDOS for execution. After execution is complete, control retums to TRSDOS Ready. If the command gets an error, it still
returns to TRSDOS Ready.
Entry Conditions:
A =24(X'18')
HL=pointer to buffer containing command string terminated with X'OD'
(up to 80 bytes, including the X'OD')
General:
This SVC does not retum.
Example:
See Sample Program E, lines 43-58.

Software 63

(a CM N DR

SVC Number 25

Execute Command
Executes a command or program and returns to the calling program. The executed program should maintain the Stack Pointer and exit via a RET instruction.
All TRSDOS library commands comply with this requirement.
If bit 4 of CFLAG$ is set (see the @FLAGS SVC), then @CMNDR executes
only system library commands.
Entry Conditions:
A = 25(X'19f)
HL=pointer to buffer containing command string terminated with X'OD'
(up to 80 bytes, including the X'OD')
Exit Conditions:
Success always.
HL = return code (See the section "Converting to TRSDOS Version 6"
for Information on return codes.)
Registers AF, BC, DE, IX, and IY are altered by the command or program executed by this SVC.
If the command invokes a user program which uses the alternate registers, they are modified also.
Example:
See Sample Program E, lines 18-29.

Software 64

@CTL
Output a Control Byte

SVC Number 5

Outputs a control byte to a logical device. The DCB TYPE byte (DCB + 0, Bit 2)
must permit CTL Operation. See the section "@CTL Interfacing to Device Drivers" for information on which of the functions listed below are supported by the
System device drivers.
Entry Conditions:
A = 5(X'05')
DE=pointer to DCB to control Output
C selects one of the following functions:
If C = 0, the Status of the specified device will be returned.
If C = 1, the driver is requested to send a BREAK or force an Interrupt.
If C = 2, the initialization code of the driver is to be executed.
If C = 3, all buffers in the driver are to be reset. This causes all pending
I/O to be cleared.
If C = 4, the wakeup vector for an interrupt-driven driver is specified by
the caller.
IY = address to vector when leaving driver. If IY = 0, then
the wakeup vector function is disabled. The RS-232C
driver COM/DVR ($CL), is the only System driver that
provides wakeup vectoring.
If C = 8, the next Character to be read will be returned. This allows data
to be "previewed" before the actual @GET returns the Character.
Exit Conditions:
lfC = 0,
Z flag set, device is ready
NZ flag set, device is busy
A=Status Image, if applicable
Note: This is a hardware dependent image.
lfC = 1,
Success, Z flag set. BREAK or Interrupt generated.
Failure, NZ flag set
A=error number
lfC=2,
Success, Z flag set. Driver initialized.
Failure, NZ flag set
h=error number
lfC = 3,
Success, Z flag set. Buffers cleared.
Failure, NZ flag set.
A=error number
lfC = 4,
Success always.
IY = previous vector address
This function is ignored if the driver does not support wakeup
vectoring.
lfC = 8,
Success, Z flag set. Next Character returned.
A=next Character in buffer
Failure, NZ flag set. Test register A:
If A=0, no pending Character is in buffer
If A=£0, A contains error number. (TRSDOS driver returns Error 43.)

Software 65

General:
BC, DE, HL, and IX are saved.
Function codes 5 to 7, 9 to 31, and 255 are reserved for the System. Function codes
32 to 254 are available for user definition.
Entry and exit conditions for user-defined functions are up to the design of the usersupplied driver.
Example:
See the section "Device Driver and Filter Templates."

Software 66

»

@DATE
GetDate

SVC Number 18
Returns today's date in display format (MM/DD/YY).
Entry Conditions:
A = 18(X'12')
HL=pointer to 8-byte buffer to receive date string
Exit Conditions:
Success always.
HL=pointer to the end of the buffer supplied +1
DE=pointer to Start of DATE$ storage area in TRSDOS
BC is altered by this SVC.
Example:
See Sample Program F, lines 252-253.

Software 67

@DCINIT

SVC Number 42

Initialize the FDC
Issues a disk Controller initialization command. The floppy disk driver treats this
the same äs @RSTOR (SVC 44).
Entry Conditions:
A = 42(X'2A')
C=logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A=error number
Example:
See the example for @CKDRV in Sample Program D, lines 38-39.

Software 68

@ DCRES

SVC Number 43

Reset the FDC
Issues a disk Controller reset command. The floppy disk driver treats this the
same äs @RSTOR (SVC 44).
Entry Conditions:
A = 43(X'2B')

C=logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A=error number
Example:
See the example for @CKDRV in Sample Program D, lines 38-39.

Software 69

@DCSTAT

SVC Number 40

Test if Drive Assigned in DCT
Tests to determine whether a drive is defined in the Drive Code Table (DCT).
Entry Conditions:

A= 40(X'28')
C=logical drive number (0-7)
Exit Conditions:
Success always.
If Z is set, the specified drive is already defined in the DCT.
If NZ is set, the specified drive is not defined in the DCT.

General:
Only AF is altered by this SVC.
Example:
See Sample Program D, lines 27-33.

Software 70

@ DEBUG

SVC Number 27

Enter DEBUG
Forces the System to enter the DEBUG Utility. Pressing © (ENTER) from the
DEBUG monitor causes program execution to continue with the next instruction. If you want to use the functions in the extended debugger when DEBUG
is entered in this fashion, you must issue the DEBUG (E) command (optionally
with the @CMNDR SVC) betöre this SVC is executed.
Entry Conditions:
A = 27(X'1B')
General:
This SVC does not return unless © is entered in DEBUG.
Example:
See Sample Program A, lines 54-60.

Software 71

@DECHEX

SVC Number 96

Convert Decimal ASCII to Binary
Converts a decimal ASCII string to a 16-bit binary number. Overflow is not
trapped. Conversion stops on the first out-of-range Character.
Entry Conditions:
A =96(X'60')
HL=pointer to decimal string
Exit Conditions:
Success always.
BC=binary conversion of ASCII string
HL = pointer to the terminating byte
AF is altered by this SVC.
Example:
See Sample Program B, lines 88-95.

Software 72

i

@DIRRD
Directory Record Read

SVC Number 87

Reads a directory sector that contains the directory entry for a specified Directory Entry Code (DEC). The sector is placed in the System buffer and the register pair HL points to the first byte of the directory entry specified by the DEC.
Entry Conditions:
A = 87(X'57')
B = Directory Entry Code of the file
C = logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
HL=pointer to directory entry specified by register B
Failure, NZ flag set.
A = error number
HL is altered.
General:
AF is always altered.
If the drive does not contain a disk, this SVC may hang indefinitely waiting
for formatted media to be placed in the drive. The programmer should
perform a @CKDRV SVC before executing this call.
If the Directory Entry Code is invalid, the SVC may not return or it may
return with the Z flag set and HL pointing to a random address. Gare
should be taken to avoid using the wrong value for the DEC in this call.
Example:
See Sample Program C, lines 152-174.

Software 73

@DIRWR

SVC Number 88

Directory Record Write
Writes the System buffer back to the disk directory sector that contains the
directory entry of the specified DEC.
Entry Conditions:
A = 88(X'58')
B = Directory Entry Code of the file
C=logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
HL=pointer to directory entry specified by register B
Failure, NZ flag set.
A = error number
HL is altered.
General:
AF is always altered.
If the drive does not contain a disk, this SVC may hang indefinitely waiting
for formatted media to be placed in the drive. The programmer should
perform a @CKDRV SVC before executing this call.
If the Directory Entry Code is invalid, the SVC may not return or it may
return with the Z flag set and HL pointing to a random address. Gare
should be taken to avoid using the wrong value for the DEC in this call.
Example:
See the example for @DIRRD in Sample Program C, lines 152-174.

Software 74

^^^^

@ DIV8

SVC Number 93

8-Bit Divide
Performs an 8-bit unsigned integer divide.

i

Entry Conditions:
A = 93(X'5D')
E = dividend
C=divisor
Exit Conditions:
Success always.
A = quotient
E = remainder
No other registers are altered.
Example:
See Sample Program B, lines 61-64.

Software 75

@DIV16
16-Bit by 8-Bit Divide

SVC Number 94

Performs a division of a 16-bit unsigned integer by an 8-bit unsigned integer.
Entry Conditions:
A =94(X'5E')
HL = dividend
C =divisor
Exit Conditions:
Success always.
HL = quotient
A = remainder
No other registers are altered.
Example:
See Sample Program B, lines 105-109.

Software 76

@DODIR
Do Directory Display/Buffer

SVC Number 34

Reads files from a disk directory or finds the free space on a disk. The directory
Information is either displayed on the screen (in five-across format) or sent to a
buffer. The directory Information buffer consists of 18 bytes per active, visible
file: the first 16 bytes of the directory record, plus the ERN (ending record number). An X'FF' marks the buffer end.
Entry Conditions:
A = 34(X'22')
C=logical drive number (0-7)
B selects one of the following functions:
If B = 0, the directory of the visible, non-system files on the disk in the
specified drive is displayed on the screen. The filenames are displayed in columns, 5 filenames per line.
If B= 1, the directory is Written to memory.
HL=pointer to buffer to receive Information
If B = 2, a directory of the files on the specified drive is displayed for files
that are visible, non-system, and match the extension partspec
pointed to by HL.
HL=partspec for the filename's extension
This field must contain a valid 3-character extension, padded
with dollar signs ($). For example, to display all visible, nonsystem files that have the letter 'C' äs the first Character of the
extension, HL should point to the string "C$$'.'
If B = 3, a directory of the files on the specified drive is Written to the buffer
that is specified by HL for files that match the extension partspec
pointed to by HL.
HL=pointer to the 3-byte partspec and to the buffer to receive the
directory records (see general notes)
Keep in mind that the area pointed to by HL is shared. If you are
using this buffer more than once, you have to re-create the
partspec in the buffer before each call because the previous
call will have erased the partspec by writing the directory
records.
If B = 4, the disk name, original free space, and current free space on the
disk is read.
HL=pointer to a 20-byte buffer to receive Information
Exit Conditions:
Success, Z flag set.
If B = 1 or 3, the directory records have been stored.
HL=pointer to the beginning of the buffer
If B = 0 or 2, the filenames or matching filenames are displayed with 5
filenames per line.
If B = 4, the disk name and free space information are stored in the
format:
Bytes 0-7 = Disk name. Disk name is padded on the right
with blanks (X'20').
Bytes 8-15 = Creation date (the date the disk was formatted
or was the target disk in a mirror Image
backup). The date is in the format MM/DD/YY.
Bytes 16-17 = Total K originally available in binary LSB-MSB
format.
Bytes 18-19 = Free K available now in binary LSB-MSB
format.
HL=po/>?ter to the beginning ofthe data area
Failure, NZ flag set.
A=error number

Software 77

General:
AF is the only register altered by this SVC.
The size of the buffer to receive directory records must be large enough to
hold directory entries for the maximum number of files allowed on the
drive and disk you specify. For example, if the drive is a hard disk, you
must be able to störe 256 directory entries, and each entry requires 18
bytes of storage. For more information on calculating the amount of
space needed for this buffer, see the tables under "Directory Records."
They give the maximum number of entries allowed on a given type of
disk. You must add 2 records to this value when B = 1 to störe the directory entry for DIR/SYS and BOOT/SYS.
Example:
See Sample Program E, lines 32-40.

Software 78

@DSP
Display Character

SVC Number 2
Outputs a byte to the Video display. The byte is displayed at the current Cursor
Position.
Entry Conditions:
A = 2(X'02')
C=byte to display
Exit Conditions:
Success, Z flag set.
A = byte displayed
Failure, NZ flag set.
A = e/ror number
General:
DE is altered by this SVC.
Example:
See Sample Program C, lines 219-221.

Software 79

@DSPLY
Display Message Line

SVC Number 10

Displays a message line, starting at the current Cursor position. The line must
be terminated with either a carriage return (X'OD1) or an ETX (X'031). If an ETX
terminates the line, the Cursor is positioned immediately after the last Character
displayed.
Entry Conditions:
A =10(X'0A')
HL=pointer to first byte of message
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
AF and DE are altered by this SVC.
Example:
See Sample Program C, lines 35-37.

O

Software 80

@ERROR
Entry to Post an Error Message

SVC Number 26

Provides an entry to post an error message. If bit 7 of register C is set, the error
message is displayed and return is made to the calling program. If bit 6 is not
set, the extended error message is displayed. Under versions prior to 6.2 the
error display is in the following format:
*#* E r r c o d = x x » E r r o r m e s s a t f e s Irin a
< f i l e s p e c or d e u s p e c >
R ef e r e n c ed at X ' dddd '

***

Under Version 6.2 the error display is in the following format:
* * E r r o r c o de = x x t R et u r n s t o X ' dddd '

* * E r r o r m es s a3 e s t r i n S
< f i lespec t decs pec / o r o Pen FCB/DCB Status>
Last SMC = nnn t R e t u r n e d t o )( ' r r r r '
dddd is the return address of the TERROR SVC in the application program.
nnn is the last SVC executed before the (a ERROR SVC request.
rrrr is the address the previous SVC returned to in the application program.
If bit 6 is set, then only the "Error message string" is displayed. This bit is
ignored if bit 6 of SFLAG$ (the extended error message bit) is set. If bit 6 of
CFLAG$ is set, then no error message is displayed. If bit 7 of CFLAG$ is set,
then the "Error message string" is placed in a user buffer pointed to by register
pair DE. See @FLAGS (SVC 101) for more information on SFLAG$ and
CFLAG$.
Entry Conditions:
A = 26(X'1A)

C=error number with bits 6 and 7 optionally set
Exit Conditions:
Success always.
General:
To avoid a looping condition that could result from the display device generating an error, do not check for errors after returning from @ERROR.
If you do not set bit 6 of register C, then you should execute this SVC only
after an error has actually occurred.
Example:
See Sample Program C, lines 379-389.

Software 81

@ EXIT

SVC Number 22

Exit to TRSDOS
This is the normal program exit and return to TRSDOS. An error exit can be
done by placing a non-zero value in HL. Values 1 to 62 indicate a primary error
äs described in TRSDOS Error Codes (Appendix A). (A non-zero value in HL
causes an active JCL to abort.)
Entry Conditions:
A =22(X'16')
HL = Return Code
If HL = 0, then no error on exit.
If HL^O, then the @ABORT SVC returns X'FFFF' in HL automatically.
General:
This SVC does not return.
Example:
See Sample Program B, lines 206-207.

Software 82

@FEXT
Set Up Default File Extension

SVCNumber 79

Inserts a detault file extension into the File Control Block if the file specification
entered contains no extension. @FEXT must be done before the file is opened.
Entry Conditions:
A =79(X'4F)
DE=po/nterfoFCß
HL=pointer to default extension (3 characters; alphabetic characters
must be upper case and first Character must be a letter)
Exit Conditions:
Success always.
AF and BC are altered by this SVC.
If the default extension is used, HL is also altered.
Example:
See Sample Program C, lines 111-132.

Software 83

@FLAGS

SVC Number101

Point IY to System Flag Table
Points the IY register to the base of the System flag table. The Status flags listed
below can be referenced off IY. You can alter those bits marked with an asterisk
(*). Bits without an asterisk are indicators of current conditions, or are unused
or reserved.
Note: You may wish to save KFLAG$ and SFLAG$ if you intend to modify them
in your program, and restore them on exit.
Entry Conditions:
A=101 (X'651)
Exit Conditions:
Success always.
IY=pointer to the following System Information:
IY-1
Contains the Overlay request number of the last System module
resident in the System Overlay region.
IY + 0 = AFLAG$ (allocation flag under Version 6.2 only)
Contains the starting cylinder number to be used when
searching for free space on a diskette. It is normally 1.
If the starting cylinder number is larger than the number
of cylinders for a particular drive, 1 is used for that drive.
IY + 2 =CFLAG$
* bit 7
— If set, then (TERROR will transfer the "Error message
string" to your buffer instead of displaying it. The message is terminated with X'OD.'
* bit 6
— If set, do not display System error messages 0-62. See
(TERROR (SVC 26) for more information.
* bit 5
— If set, sysgen is not allowed.
* bit 4
— If set, then @CMNDR will execute only System library
commands.
bit 3
— If set, @RUN is requested from either the SET or
SYSTEM (DRIVER = ) commands.
bit 2
— If set, @KEYIN is executing due to a request from
SYS1.
bit 1
— If set, @CMNDR is executing. This bit is reset by
@EXITand@CMNDI.
* bit0
— If set, HIGH$ cannot be changed using @HIGH$
(SVC 100). This bit is reset by @EXIT and @CMNDI.
IY + 3 =DFLAG$ (device flag)
* bit 7
— "1" if GRAPH IC printer capability desired on screen
print ((CONTROÜ © causes screen print. See the SYSTEM (GRAPHIC) command under "Technical Information on TRSDOS Commands and Utilities.")
bit 6
— "1" if KSM module is resident
bit 5
— Currently unused
bit 4
— "1" if MemDisk active
bit 3
— Reserved
bit 2
— "1" if Disk Verify is enabled
* bit 1 — "1" if TYPE-AHEAD is active
bit0
— "1" if SPOOL is active
IY + 4 = EFLAG$ (ECI flag under Version 6.2 only)
Indicates the presence of an ECI program. If any of the
bits are set, an ECI is used, rather than the SYS1 Interpreter. The ECI program may use these bits äs neccesary. However, at least one bit must be set or the ECI is
not executed.

Software 84

i

IY + 5 =FEMSK$ (maskforportOFEH)
IY + 8 =IFLAG$ (international flag)
* bit 7
— If "1" 7-bit printer filter is active
If "0," normal 8-bit filters are present
* bit 6 — If "1," international Character translation will be performed by printer driver
If "0," characters received by printer driver will be sent
to the printer unchanged
bit 5 — Reserved for future languages
bit 4
— Reserved for future languages
bit 3
— Reserved for future languages
bit 2
— Reserved for future languages
bit 1 — If "1," German version of TRSDOS is present
bit 0
— If "1f French version of TRSDOS is present
If bits 5-0 are all zero, then USA version of TRSDOS is present.
lY +10 = KFLAG$ (keyboard flag)
bit 7
— "1" if a Character is present in the type-ahead buffer
bit 6 — Currently unused
* bit 5
— "1" if CAPS lock is set
bit 4
— Currently unused
bit 3
— Currently unused
* bit 2
— "1" if (ENTER) has been pressed
* bit 1 — "1" if (SHIFT) (D has been pressed (PAUSE)
* bit 0
— "1" if (BREAK) has been pressed
Note: To use bits 0-2, you must first reset them and then test to
see if they become set.
IY +12 = MODOUT (image of port 0ECH)
IY+13= NFLAG$ (network flag under Version 6.2)
bit 7
— Reserved for System use.
bit 6
— If set, the application program is in the task processor.
Programmers must not modify this bit.
bit 5
— Reserved for System use.
bit 4
— Reserved for System use.
bit 3
— Reserved for System use.
bit 2
— Reserved for System use.
bit 1 — Reserved for System use.
* bit 0
— If set, the "file open bit" is Written to the directory.
IY+ 14=OPREG$ (memory management & video control image)
IY+17= RFLAG$ (retry flag under Version 6.2 only)
Indicates the number of retrys for the floppy disk driver.
This should be an even number larger than two.
IY +18 = SFLAG$ (System flag)
bit 7 —"1"if DEBUG is tobe turnedon
* bit 6 —"1" if extended error messages desired (see
@ERROR for message format); overrides the setting
of bit 6 of register C on @ERROR (SVC 26) and
should be used only when testing
bit 5 — "1" if DO commands are being executed
* bit 4
— "1" if BREAK disabled
bit 3
— "1" if the hardware is running at 4 mhz (SYSTEM
(FAST)). If "0," the hardware is running at 2 mhz (SYSTEM (SLOW)).
* bit 2
— "1" if LOAD called from RUN
* bit 1 — "1" if running an EXECute only file
* bit 0 — "1" specifies no check for matching LRL on file open
and do not set file open bit in directory. This bit should
be set just before executing an @OPEN (SVC 59) if
you want to force the opened file to be READ only during current I/O operations. As soon äs either call is
executed, SFLAG$ bit 0 is reset. If you want to disable
LRL checking on another file, you must set SFLAG$
bit 0 again.

Software 85

IY + 19 = TFLAG$ (type flag under Version 6.2 only)
Identifies the Radio Shack hardware model. TFLAG$
allows programs to be aware of the hardware environment and the Character sets available for the display.
Current assignments are:
2 indicates Model II
4 indicates Model 4
5 indicates Model 4P
12 indicates Model 12
IY + 20= UFLAG$ (user flag under Version 6.2 only)
May be set by application programs and is sysgened
properly.
IY + 21 =VFLAG$
bit 7
— Reserved for System use
* bit 6
— "1" selects solid Cursor, "0" selects blinking Cursor
bit 5
— Reserved for System use
* bit 4
— "1" if real time clock is displayed on the screen
bits 0-3 — Reserved for System use
IY + 22 = WRINTMASKS (mask for WRINTMASK port)
IY + 26 = SVCTABPTR$ (pointer to the high order byte of the SVC table
address; Iow order byte = 00)
IY + 27 = Version ID byte (60H = TRSDOS version 6.0.x.x,
61H = TRSDOS version 6.1.x.x, etc.)
IY - 47 = Operating System release number. Provides a third and fourth
Character (12H = TRSDOS version x.x.1.2)
IY + 28
to
IY + 30 = @ICNFGvector
IY + 31
to
IY + 33 = @KITSKvector

C

Software 86

@ FN AM E
Get Filename

SVC Number 80
Gets the filename and extension from the directory using the specified Directory Entry Code (DEC) for the file.

P

Entry Conditions:
A = 80(X'50')
DE=pointer to 15-byte buffer to receive filename/extension:drive, followed by a X'OD' äs a terminator
B = DEC of desired file
C = logical drive number of drive containing file (0-7)
Exit Conditions:
Success, Z flag set.
HL=pointer to directory entry specified by register B
Failure, NZ flag set.
A = error number
HL is altered.
General:
AF and BC are always altered.
If the drive does not contain a disk, this SVC may hang indefinitely waiting
for formatted media to be placed in the drive. The programmer should
perform a @CKDRV SVC before executing this call.
If the Directory Entry Code is invalid, the SVC may not return or it may
return with the Z flag set and HL pointing to a random address. Gare
should be taken to avoid using the wrong value for the DEC in this call.
Example:
See Sample Program C, lines 274-286.

Software 87

@FSPEC
Assign File or Device Specification

SVC Number 78

Moves a file or device specification from an input buffer into a File Control Block
(FCB). Conversion of Iower case to upper case is made automatically.
Entry Conditions:
A =78(X'4E')
HL=pointer to buffer containing filespec or devspec
DE=pointer to 32-byte FCB or DCB
Exit Conditions:
Success always.
If the Z flag is set, the file specification is valid.
HL=pointer to terminating Character
DE=pointer to Start of FCB
If the NZ flag is set, a syntax error was found in the filespec.
HL=pointer to invalid Character
DE=pointer to Start of FCB
A = invalid Character
General:
AF and BC are altered.
Example:
See Sample Program C, lines 53-65.

Software 89

@GET
Get One Byte From Device or File

SVC Number 3

Gets a byte from a logical device or a file. The DCB TYPE byte (DCB + 0, Bit 0)
must permit a GET Operation for this call to be successful.
Entry Conditions:
A =3(X'03')
DE=pointer to DCB or FCB

j^*-^***.

Exit Conditions:
Success, Z flag set.
A = Character read from the device or file
Failure, NZ flag set. Test register A:
If A = 0, no Character was available.
If A ± 0, A contains error number.
Example:
See the section "Device Driver and Filter Templates."

C

Software 90

@GTDCB
Get Device Control Block Address

SVC Number 82

Finds the location of a Device Control Block (DCB). If DE = 0 (no device name
specified), HL returns the address of the first unused DCB found.
Entry Conditions:
A =82(X'52')
DE = 2-character device name (E = first Character, D = second Character)
Exit Conditions:
Success, Z flag set. DCB was found.
HL=pointer to Start of DCB
Failure, NZ flag set. No DCB was available.
A = Error 8 (Device not available)
HL is altered.
General:
AF is always altered by this SVC.
Example:
See the section "Device Driver and Filter Templates."

Software 91

@GTDCT
Get Drive Code Table Address

SVCNumber 81

Gets the address of the Drive Code Table for the requested drive.
Entry Conditions:
A = 81 (X'511)

C=logical drive number (0-7)
Exit Conditions:
Success always.
IY=pointer to the DCT entry for the specified drive
AF is always altered by this SVC.
General:
If the drive number is out of ränge, the IY pointer will be invalid. This call
does not return Z/NZ to indicate if the drive number specified is valid
(0-7) or enabled.
Example:
See the example for @DCSTAT in Sample Program D, lines 27-33.

Software 92

@GTMOD
Get Memory Module Address

P

SVCNumber 83

Locates a memory module, if the Standard memory header is at the Start of the
module. The scanning Starts with the System drivers in Iow memory, then
moves to any high memory modules. If any routine is encountered that does not
start with a proper header, scanning stops.
Entry Conditions:
A =83(X'53')
DE=pointer to memory module name in upper case, terminated with any
Character in the ränge 00-31
Exit Conditions:
Success always.
If the Z flag is set, the module was found.
HL=pointer to first byte of memory header
DE=pointer to first byte after module name
If the NZ flag is set, the module was not found.
HL is altered.
General:
AF is always altered by this SVC.
Example:
See Sample Program F, lines 144-154.

Software 93

@HDFMT
Hard Disk Format

SVC Number 52
Passes a format drive command to a hard disk driver. If the hard disk Controller
accepts it äs a valid command, then it formats the entire disk drive. If the hard
disk Controller does not accept it, then an error is returned. Radio Shack hardware does not currently support @HDFMT.
Entry Conditions:
A = 52(X'34')
C=logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number

Software 94

@HEXDEC
Convert Binary to Decimal ASCII

SVC Number 97

Converts a binary number in HL to decimal ASCII.

i

Entry Conditions:
A =97(X'61')
HL = number to convert
DE=pointer to 5-character buffer to hold converted number
Exit Conditions:
Success always.
DE=pointer to end of buffer +1
AF, BC, and HL are altered by this SVC.
Example:
See Sample Program B, lines 73-76.

Software 95

@HEX8
Convert 1 Byte to Hex ASCII

SVC Number 98

Converts a 1-byte number to hexadecimal ASCII.
Entry Conditions:
A =98(X'62')
C = number to convert
HL=pointer to a 2-character buffer to hold the converted number
Exit Conditions:
Success always.
HL=pointer to the end of buffer +1
Only AF is altered by this SVC.
Example:
See Sample Program B, lines 236-246.

G

Software 96

@HEX16
Convert 2 Bytes to Hex ASCII

SVC Number 99

Converts a 2-byte number to hexadecimal ASCII.

i

Entry Conditions:
A =99(X'63')
DE=number to convert
HL=pointer to 4-character buffer to hold converted number
Exit Conditions:
Success always.
HL=pointer to end of buffer +1
Only AF is altered by this SVC.
Example:
See Sample Program B, lines 248-258.

Software 97

@HIGH$
Get or Alter HIGH$ or LOW$

SVCNumbeMOO

Provides the means to read or alter the HIGH$ and LOW$ values.
Note: HIGH$ must be greater than LOW$. LOW$ is reset to X'2FFF' by @EXIT,
©ABORT, and @CMNDI.
Entry Conditions:
A=100(X'64')

B selects HIGH$ or LOW$
If B = 0, SVC deals with HIGH$
If B =£ 0, SVC deals with LOW$
HL selects one of the following functions:
If HL = 0, the current HIGH$ or LOW$ is returned
If HL=£0, then HIGH$ or LOW$ is set to the value in HL
Exit Conditions:
Success, Z flag set.
HL = current HIGH$ or LOW$. If HL ± 0 on entry, then HIGH$ or LOW$
is now set to that value.
Failure, NZ flag set.
A = error number
General:
If bit 0 of CFLAG$ is set (see @FLAGS), then HIGH$ cannot be changed
with this call. The call returns error 43, "SVC parameter error!'
Example:
See Sample Program F, lines 75-86.

G

Software 9&

@INIT
Open or Initialize File

SVC Number 58

Opens a file. If the file is not found, this SVC creates it according to the file
specification.

i

Entry Conditions:
A =58(X'3A)
HL=pointer to 256-byte disk I/O buffer
DE=pointer to FCB containing the file specification
B = Logical Record Length to be used while file is open
Exit Conditions:
Success, Z flag set. File was opened or created.
The CF flag is set if a new file was created.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
The file open bit is set in the directory if the access level is UPDATE or
greater.
Example:
See Sample Program C, lines 260-272.

J

Software 99

@IPL_
Reboot the System

SVC Number 0

Does a Software reset. Floppy drive 0 must contain a System disk. @IPL uses
the Standard boot sequence, the same äs for a hard reset (pressing the reset
button). Memory locations X'41 E5'-X'4225' and X'4300'-X'43FF' are altered
during the boot of the machine.
Entry Conditions:
General:
This SVC does not return.

O

Software 100

(g KBD

SVC Number 8

Scan Keyboard and Return
Scans the keyboard and returns a Character if a key is pressed. If no key is
pressed, a zero value is returned.
Entry Conditions:
A = 8(X'08')
Exit Conditions:
Success, Z flag set.
A = Character pressed
Failure, NZ set.
If A = 0, no Character was available.
If A =£ 0, then A contains error number.
General:
DE is altered by this SVC.
Example:
See Sample Program C, lines 198-200.

Software 101

@KEY _
Scan *KI Device, Wait for Character

SVC Number 1

Scans the *KI device and returns with a Character. It does not return until a
Character is input to the device.
Note: The System suspends execution of the program that issued the SVC until
a Character can be obtained. Background tasks will continue to run normally.
Entry Conditions:
Exit Conditions:
Success, Z flag set.
A = Character entered
Failure, NZ flag set.
A = error number
General:
DE is altered by this SVC.
Example:
See Sample Program B, lines 202-203.

Software 102

^^^^^

@KEYIN
Accept a Line of Input

p

SVC Number 9

Accepts a line of input until terminated by either an (ENTER) or a (BREAK). Entries
are displayed on the screen, starting at the current Cursor position. Backspace,
tab, and line delete are supported. If JCL is active, the line is fetched from the
active JCL file.
Entry Conditions:
A =9(XW)
HL=pointer to userline bufferof length B+1
B = maximum number of characters to input
C =0
Exit Conditions:
Success, Z flag set.
HL=pointer to Start of buffer
B = actual number of characters input
CF is set if (BREAK) terminated the input.
Failure, NZ flag set.
A = error number
General:
DE and C are altered by this SVC.
Example:
See Sample Program C, lines 39-47.

J

Software 103

@KLTSK
Remove Currently Executing Task

SVC Number 32

When calied by an executing task driver, removes the task assignment from the
task table and returns to the foreground application that was interrupted.
Entry Conditions:
A = 32(X'20')
General:
This SVC does not return.
Example:
See the example for @RMTSK in Sample Program F, lines 134-142.

Software 104

(g LOAD
Load Program File

SVC Number 76
Loads a program file. The file must be in load module format.

i

Entry Conditions:
A =76(X'4C')
DE = pointer to FCB containing filespec of the file to load
Exit Conditions:
Success, Z flag set.
HL = transfer address retrieved from file
Failure, NZ flag set.
A = e/ror number
Example:
See Sample Program A, lines 50-56.

Software 105

@LOC
Caiculate Current Logical Record Number
Returns the current logical record number.
Entry Conditions:
A =63(X'3F)

DE = pointer to the file's FCB
Exit Conditions:
Success, Z flag set.
BC=logical record number
Failure, NZ flag set.
A = error number
General:
AF is altered by this SVC.
Example:
See Sample Program C, lines 305-311.

Software 106

SVC Number 63

@LOF
Calculate the EOF Logical Record Number

SVC Number 64

Returns the EOF (End of File) logical record number.
Entry Conditions:
A = 64(X'40')
DE = pointer to FCB for the file to check
Exit Conditions:
Success, Z flag set.
BC = the EOF logical record number
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
Example:
See the example for @LOC in Sample Program C, lines 305-311.

Software 107

@LOGER

SVC Number 11

Issue Log Message
Issues a log message to the Job Log. The message can be any Character string
terminating with a carriage return (X'OD1).
Entry Conditions:
A =11 (X'OB1)

HL=pointer to first Character in message line
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
Example:
LD
LD

TEXT:

HL»TEXT
A»@LOGER

i P o i n t at messaSe to O u t p u t
» a n d outpi.it i t t o the Job
»Lo*
iCall the ÜLOGER SUC

RST
»«*

28H

DEFM
DEFB

'This is a message for the Job Los'
0DH
» M e s s a g e must be t e r m i n a t e d
j w i t h an .

Software 108

@LOGOT
Display and Log Message

SVC Number 12

Displays and logs a message. Performs the same function äs @DSPLY followed by @LOGER.

i

Entry Conditions:
A =12(X'0C')
HL=po/nter to first Character in message line
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
To avoid a looping condition that could result from the display device generating an error, no error checking should be done after returning from

@LOGOT.
Example:

TEXT:

LD
LD

HL»TEXT
A»@LOGOT

RST
«<«

28H

DEFM
DEFM
DEFB

'This wessaae w i l l be d i s p l a / e d b o t h in'
'the Job Los and on the display.'
0DH
iMust t e r m i n a t e t e x t w i t h an
5,

Software 109

iPoint at messatfe to Output
»and Output it to the Job
»Lo* AND the d i s p l a y
iCall the @LOGOT SVC

@MSG
Send Message to Device

SVC Number 13

Sends a message line to any device or file.
Entry Conditions:
A =13(X'0D')
DE=pointer to DCB or FCB of device or file to receive Output
HL=pointer to message line terminated with X'OD' or X'03'

^^^V

Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
Example:

TEXT:

LD
LD

HL»TEXT
DE»DCBP

LD
RST
« **

A»@MSG
28H

DEFM

'D555-555' » T e x t to w r i t e to
»t h i s d e v i c e » In t h i s c a s e »
j i t is a d i a l i n 3 m o d e r n «
03H
» T e r m i n a t e the m e s s a g e

DEFB

» P o i n t a t messaäe to O u t p u t
!Point at the d e v i c e c o n t r o l
» b l o c K for o u r d e v i c e
»and w r i t e t h i s t e x t to it
» C a l l the @MSG SVC

C

Software 110

@MUL8
8-Bit Multiplication

SVC Number 90

Performs an 8-bit by 8-bit unsigned integer multiplication. The resultant product
must fit into an 8-bit field.

i

Entry Conditions:
A = 90(X'5A')
C=multiplicand
E-multiplier
Exit Conditions:
Success always.
A=product
DE is altered by this SVC.
Example:
See Sample Program B, lines 150-153.

Software 111

@MUL16
16-Bit by 8-Bit Multiplication

SVCNumber 91

Performs an unsigned integer multiplication of a 16-bit multiplicand by an 8-bit
multiplier. The resultant product is stored in a 3-byte register field.
Entry Conditions:
A =91 (X'5B')
HL = multiplicand
C = multiplier

^^^^

Exit Conditions:
Success always.
HL = two high-order bytes of product
A = Iow-order byte of product
DE is altered by this SVC.
Example:
See Sample Program B, lines 183-187.

O

Software 112

@OPEN
Open Existing File or Device

SVC Number 59

Opens an existing file or device.
Entry Conditions:
A =59(X'3B')
HL=pointer to 256-byte disk I/O buffer
DE=pointer to FCB or DCB containing filespec or devspec
B = logical record length for open file
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
AF is altered by this SVC.
The file open bit is set in the directory if the access level is UPDATE or
greater.
Example:
See Sample Program C, lines 134-150.

^^^fgpP

Software 113

(aPARAM_
Parse Parameter String

SVC Number 17

Parses an optional parameter string. Its primary function is to parse command
Parameters contained in a command line starting with a parenthesis. The
acceptable parameter format is:
PARM = X'nnnn'....hexadecimal entry
PARM = nnnnn ....decimal entry
PARM = "string" ...alphanumeric entry
PARM = flag
....ON, OFF, Y, N, YES, or NO
Note: Entering a parameter with no equal sign or value is the same äs
using PARM = ON. Entering PARM= with no value is the same äs
using PARM = OFF.
Entry Conditions:
A =17(X'11f)
DE= pointer to beginning of your parameter table
HL = pointer to command line to parse (the parameter string is enclosed
within parentheses)
Exit Conditions:
Success always.
If Z is set, either valid parameters or no parameters were found.
If NZ is set, a bad parameter was found.
General:
NZ is not returned if parameter types other than those specified are
entered. The application must check the validity of the response byte.
The valid parameters are contained in a user table which must be in one of the
following formats. (Parameter names must consist of alphanumeric characters, the first of which is a letter.)
For use with TRSDOS Version 6, use this format:
The parameter table Starts with a single byte X'80.' Each parameter is
stored in a variable length field äs described below.
1) Type Byte (Type and length byte)
Bit 7 — If set, accept numeric value
Bit 6 — If set, accept flag parameter
Bit 5 — If set, accept "string" value
Bit 4 — If set, accept first Character of name äs abbreviation
Bits 3-0 — Length of parameter name
2) Actual Parameter Name
3) Response byte (Type and length found)
Bit 7 — Numeric value found
Bit 6 — Flag parameter found
Bit 5 — String parameter found
Bits 4-0 — Length of parameter entered. If length is 0 and the 2-byte
vector points to a Quotation mark (X'221), then the parameter
was a null string. Otherwise, a length of 0 indicates that the
parameter was longer than 31 characters.
4) 2-byte address vector to receive the parsed parameter values.
The 2-byte memory area pointed to by the address field of your table
receives the value of PARM if PARM is non-string. If a string is entered, the
2-byte memory area receives the address of the first byte of "string." The
entries ON, YES, and Y return a value of X'FFFF'; OFF, NO, and N return
X'0000.' If a parameter name is specified on the command line and is fol-

Software 114

S* "N
lx^prj

Iowed by an equal sign and no value, then X'0000' or NO is returned. If a
Parameter name is used on the command line without the equal sign, then
a value of X'FFFF1 or ON is assumed. For any allowed parameter that is
completely omitted on the command line, the 2-byte area remains
unchanged and the response byte is 0.
The parameter table is terminated with a single byte X'00.'
For compatibility with LDOS 5.1.3, use this format:
A 6-character "word" left justified and padded with blanks followed by a 2byte address to receive the parsed values. Repeat word and address for äs
many parameters äs are necessary. You must place a byte of X'00' at the
end of the table.
Example:
LD
LD
LD
RST
JR
LD
AND
JR
LD
OR
JR
JR
COMAND
PARM:

RESP:

VAL:

HL»COMAND » P o i n t at c o m m a n d b u f f e r
DE»PARM
» P o i n t at P a r a m e t e r l i s t
A»0PARAM
» P a r s e the items on the
icommand line
28H
» C a l l the 0PARAM SUC
NZ»ERROR
i An e r r o r o c c u r r e d (not
»included here)
A»(RESP)
»Get response code
040H
»Test response flatfs
Z»BAD
iUser s p e c i f i e d s o m e t h i n a
i l i K e UPDATE=X'1234 / o r
;UPDATE="HELLO"
A»(VAL)
» G e t Ist b y t e of VAL w o r d
A
»Test the v a l u e
Z»OFF
!UPDATE = OFF o r UPDATE = NO was
» s p e c i f ied
ON
5UPDATE = ON o r UPDATE = YES was
ispecified

» »•
DEFS

80

DEFB
DEFB

80H
40H+6

DEFM
DEFB
DEFW
DEFB
DEFS

'UPDATE'
0
*,'AL
0
2

Software 115

» A r e a w h e r e c o m m a n d is
5 st o red
»Table header code
»40 savs we want a fla*
»(YES/NO)» 6 is lensth of
» t h e P a r a m e t e r name
»'Parameter name
» R e s p o n s e area
» ^ e c t o r t o UAL
»End of Table c o d e
» A r e a to r e c e i u e a Parameter
»ualue

@PAUSE

SVC Number 16

Suspend Program Execution
Suspends program execution for a specified period of time and goes into a
"holding" state. The delay is at least 14.3 microseconds per count.
Entry Conditions:
A =16(X'10')
BC = delay count
Exit Conditions:
Success always.

Example:
LD

BC»3SA2H

LD
RST

Af@PAUSE
28H

iWait for about 200 m i l l i » s e c o n d s « 14«3 usecs *
51398S is a p p r o x . 200
5 m se c s
iSuspend e x e c u t i o n
iCall the 0PAUSE SVC

O

Software 116

@PEOF
Position to End Of File

SVC Number 65

Positions an open file to the End Record Number (ERN). An end-of-fileencountered error (X'1C') is returned if the Operation is successful. Your program may ignore this error.
Entry Conditions:
A =65(X'41')
DE = pointer to FCB of the file to position
Exit Conditions:
NZ flag always set.
If A = X'1 C,' then success.
If A ± X'IQ'thenfailure.
A = error number
General:
AF is always altered by this SVC.
Example:
See the example for @LOC in Sample Program C, lines 305-311.

Softwaren?

@POSN

SVC Number 66

Position File
Positions a file to a logical record. This is useful for positioning to records of a
random access file.
When the @POSN routine is used, Bit 6 of FCB +1 is automatically set. This
ensures that the EOF (End Of File) is updated when the file is closed only if the
NRN (Next Record Number) exceeds the current ERN (End Record Number).
Note that @POSN must be used for each write, even if two records are side by
Side.
Entry Conditions:
A =66(X'42')
DE=pointer to FCB for the file to position
BC = the logical record number
Exit Conditions:
If Z flag is set or A = X'1 C' or X'1 D; then success.
The file was positioned.
Otherwise, failure.
A = error number
General:
AF is always altered by this SVC.
Example:
See the example for @LOC in Sample Program C, lines 305-311.

Software 118

@PRINT
Prints Message Line

SVC Number 14

Outputs a message line to the printer. The line must be terminated with either a
carriage return (X'OD1) or an ETX (X'031).
Entry Conditions:
A =14(X'0E')
HL=pointer to message to be Output
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
AF and DE are altered by this SVC.
Example:
LD

TEXT:

HL»TEXT

LD

A»@PRINT

RST
»»»
DEFB
DEFM
DEFB

28H

»Text to be O u t p u t to the
»Printer
» W r i t e t h i s message to the
»Printer deuice
»Call the @PRINT SVC

0CH
JDo a TOP of For«
'Report c o n t i n u e d
Pa3e
3
» T e r m i n a t e w i t h a  or
»an 

Software 119

@PRT
Send Character to Printer

SVC Number 6

Outputs a byte to the line printer.
Entry Conditions:
A = 6(X'06')
C=Character to print
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = e/ror number
General:
AF and DE are altered by this SVC.
If the line printer is attached but becomes unavailable (out of paper, out of
ribbon, turned off, off-line, buffer füll, etc.), the printer driver waits approximately ten seconds. If the printer is still not ready, a "Device not available" error is returned.

Example:

PAGE:

LD
ADD
LD
LD

A»(PAGE)
A»'0'
C »A
A»@PRT

RST
» »•
DEFB

28H

»Get the paSe n u m b e r
» M a k e it ASCII
iPut the u a l u e h e r e
» W r i t e this C h a r a c t e r to the
»Printer
» C a l l the @PRT SVC

2

»Start with pa«Je 2

G

Software 120

i

@PUT
Write One Byte to Device or File

SVC Number 4

Outputs a byte to a logical device or file. The DCB TYPE byte (DCB + 0, Bit 1)
must permit PUT Operation.
Entry Conditions:
A =4(X'04')
DE=pointer to DCB or FCB of the Output device
C = byte to Output
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
AF is always altered by this SVC.
Example:
See the section "Device Driver and Filter Templates."

Software 121

@RAMDIR
Get Directory Record or Free Space

SVC Number 35

Reads the directory information of visible files from a disk directory, or gets the
amount of free space on a disk.
Entry Conditions:
A =35(X'23')
HL=pointer to RAM buffer to receive information
B = logical drive number (0-7)
C selects one of the following functions:
If C = 0, get directory records of all visible files.
If C = 255, get free space information.
If C = 1-254, get a single directory record (see below).
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
Each directory record requires 22 bytes of space in the buffer. If C = 0, one additional byte is needed to mark the end of the buffer.
For single directory records, the number in the C register should be one less
than the desired directory record. For example, if C = 1, directory record 2 is
fetched and put in the buffer. If a single record request is for an inactive record
or an 'Invisible file, the A register returns an error code 25 (File access denied).
The directory information is placed in the buffer äs follows:
Byte
00-14
15
16
17
18-19
20-21
22

Contents
filename/ext:d (left justified, padded with spaces)
protection level, 0 to 6
EOF offset byte
logical record length, 0 to 255
ERNoffile
file size in K (1024-byte blocks)
LAST RECORD ONLY. Contains" -l-" to mark buffer end.

If C = 255, HL should point to a 4-byte buffer. Upon return, the buffer contains:
Bytes 00-01 Space in use in K, stored LSB, MSB
Bytes 02-03 Space available in K, stored LSB, MSB
Example:
See the example for @DODIR in Sample Program E, lines 32-40.

^^BUsIra^^

Software 122

@RDHDR
Read a Sector Header

SVC Number 48

Reads the next ID header when supported by the Controller driver. The floppy
disk driver supplied treats this äs a @RDSEC (SVC 49).

i

Entry Conditions:
A =48(X'30')
HL=pointer to buffer to receive the data
D = cylinder to read
C = logical drive number
E = sector to read
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = e/ror number
Example:
See the example for @RDSEC in Sample Program D, lines 63-66.

(^"*v

J

Software 123

@RDSEC
Read Sector

SVC Number 49
Transfers a sector of data from the disk to your buffer.
Entry Conditions:
A =49(X'3T)
HL=pointer to the buffer to receive the sector
D = cylinder to read
E = sector to read
C = logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC
Example:
See Sample Program D, lines 63-66.

Software 124

@RDSSC

SVC Number 85

Read System Sector
Reads the specified System (directory) sector. If the cylinder number in register
D is not the directory cylinder, the value in D is changed to reflect the real directory cylinder and the sector is then read.
Entry Conditions:
A =85(X'55')
HL=pointer to the buffer to receive the sector
D = cylinder to read
E = sector to read
C = logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
Example:
See Sample Program D, lines 78-92.

Software 125

@RDTRK

SVC Number 51

Read a Track
Reads an entire track when supported by the Controller driver. The floppy disk
driver supplied treats this äs a @RDSEC (SVC 49) and does not do a track
read.
Entry Conditions:
A =51 (X'331)

HL=pointer to buffer to receive the sector
D = track to read
C = logical drive number
E = sector to read
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
AF is altered by the supplied floppy disk driver.
Example:
See the example for @RDSEC in Sample Program D, lines 63-66.

G

^fi^^^S^.

Software 126

(5 READ

SVC Number 67

Read a Record

p

Reads a logical record from a file. If the LRL defined at open time was 256
(specified by 0), then the NRN sector is transferred to the buffer established at
open time. For LRL between 1 and 255, the next logical record is placed into a
user record buffer, UREC. The 3-byte NRN is updated afterthe read Operation.
Entry Conditions:
A =67(X'43')
DE=pointer to FCB for the file to read
HL=pointer to user record buffer UREC (needed if LRL = 1-255; unused if
LRL = 256)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
Example:
See Sample Program C, lines 300-304.

1^^^^

Software 127

(a REMOV
Remove File or Device

SVC Number 57

Removes a file or device.
If a file is to be removed, the File Control Block must be in an open condition.
When this SVC is performed, the file's directory is updated and the space occupied by the file is deallocated.
If a device was specified, the device is closed. To remove a device, use the
REMOVE library command.
Entry Conditions:
A =57(X'39')
DE = pointer to FCB or DCB to remove
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
Example:
See Sample Program C, lines 223-231.

G

jrfdlRH^^.

Software 128

@RENAM

SVC Number 56

Rename File or Device
Changes a file's filename and/or extension.
Entry Conditions:
A =56(X'38')
DE=pointer to an FCB containing the file's current name
This FCB must be in a closed state.
HL=pointer to new filename string terminated with a X'OD' or X'03.' This
filespec must be in upper case and must be a valid filespec. You can
convert the filespec to upper case and check its validity by using the
@FSPEC SVC before using @RENAM.
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
After the call is completed, the FCB pointed to by DE is altered.
Only AF is altered by this SVC.
Example:
LD

DE»FCB

LD

HL»NEW

LD

A»@RENAM

RST

28H

FCB: DEFS 32

NEW:

DEFM

'NEWNAME/TXT'

DEFB 0DH

Software 129

» P o i n t at a c l o s e d FCB
»containinsf the old
»filespec
» P o i n t to the new f i l e s p e c
» t o use
» C h a n S e the name of the
5f ile
» C a l l the 0RENAM SVC
»A F i l e C o n t r o l B l o c K used
!bv the 0RENAM SVC, In
ith is e x a m p l e » i t i s
» a s s u m e d that an @FSPEC
»SVC has l o a d e d a f i l e s p e c
» i n t o the FCB b e f o r e the
»0RENAM SVC is perforwed.
» T h e new f i l e s p e c for the
»f i l e
»Terwinate the filespec

@REW
Rewind File to Beginning

SVC Number 68

Rewinds a file to its beginning and resets the 3-byte NRN to 0. The next record
to be read or Written sequentially is the first record of the file.
Entry Conditions:
A =68(X'44')
DE = pointer to FCB for the file to rewind
Exit Conditions:
Success, Z flag set. File positioned to record number 0.
Failure, NZ flag set.
A = error number
General:
AF is always altered by this SVC.
Example:
See the example for @LOC in Sample Program C, lines 305-311.

^^*w**»ii-.

Software 130

@RMTSK
Remove Interrupt Level Task

SVC Number 30

Removes an Interrupt level task from the Task Control Block table.
Entry Conditions:
A = 30(X'1E')
C=task slot assignment to remove (0-11)
Exit Conditions:
Success always.
HL and DE are altered by this SVC.
Example:
See Sample Program F, lines 134-142.

^tjjjfr

Software 131

@RPTSK
Replace Task Vector

SVC Number 31

Exits the task process executing and replaces the currently executing task's
vector address in the Task Control Block table with the address following the
SVC instruction. Return is made to the foreground application that was
interrupted.
Entry Conditions:
A = 31 (X'1F)
General:
This SVC does not return.

Example:
LD

A»RPTSK

RST
NEWADD: DEFW

28H
0

Software 132

» R e p l a c e this task with the
ione l o c a t e d at the
i f o l l o w i n S address:
i C a l l the @RPTSK SVC
» A d d r e s s of the new tasK is
i l o a d e d h e r e « This w o r d
» m u s t be i w w e d i a t e l y after
i t h e iRPTSK SVC. The l a b e l
»NEWADD is present o n l v to
i a l l o w the a d d r e s s to be
5stored»

@RREAD
Reread Sector

p

SVC Number 69
Forces a reread of the current sector to occur betöre the next I/O request is performed. Its most probable use is in applications that reuse the disk I/O buffer for
multiple files, to make sure that the buffer contains the proper file sector. This
routine is valid only for byte I/O or blocked files. Do not use it when positioned
at the start of a file.
Entry Conditions:
A = 69(X'45')
DE = pointer to FCB for the file to reread
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
AF is always altered by this SVC.
Example:
LD

DE»FCB

LD

A»8RREAD

RST

28H

Software 133

» P o i n t to F i l e C o n t r o l B l o c K
»of the f i l e that r e ^ u i r e s
5the re-read
» B e f o r e next I/O» r e l o a d
» t h e current sector into
i t h e system b u f f e r f o r
»this file
» C a l l the 0RREAD SVC

@RSLCT
Test for Drive Busy

SVC Number 47

Performs a test of the last selected drive to see if it is in a busy state. If busy, it
is re-selected until it is no longer busy.
Entry Conditions:
A = 47(X'2F)

C=logical drive number (0-7)
Exit Conditions:
Success always.
Only AF is altered by this SVC.

Example:
LD

C»l

LD

Af@RSLCT

RST

28H

Software 134

Test D r i u e l to see if it
i s bus v.
If it i s » c o n t i n u e
s e l e c t i n S it
Call the @RSLCT SMC

@RSTOR
Issue FDC RESTORE Command

SVCNumber 44

Issues a disk Controller RESTORE command.
Entry Conditions:
A = 44(X'2C')
C=logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
Example:
See the example for @CKDRV in Sample Program D, lines 38-39.

Software 135

(5 RUN
Run Program

SVC Number 77
Loads and executes a program file. If an error occurs during the load, the system prints the appropriate message and returns.
Entry Conditions:
A =77(X'4D')
DE=pointer to FCB containing the filespec of the file to RUN
Note: The FCB must be located where the program being loaded will not
overwrite it.
Exit Conditions:
Success, the new program is loaded and executed.
Failure, the error is displayed and return is made to your program.
HL = return code (See the section "Converting to TRSDOS Version 6"
for information on return codes.)
General:
HL is returned unchanged if no error occurred and can be used äs a
pointer to a command line.
Example:
See Sample Program A, lines 62-74.

Software 136

@ RWRIT
Rewrite Sector

SVC Number 70
Rewrites the current sector, following a write Operation. The @WRITE function
advances the NRN after the sector is Written. @RWRIT decrements the NRN
and writes the disk buffer again. Do not use @RWRIT when positioned to the
start of a file.
Entry Conditions:
A =70(X'46')
DE=pointer to FCB for the file to rewrite
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
Example:
LD

DE»FCB

LD

A»@RWRIT

RST

28H

Software 137

» P o i n t to the File C o n t r o l
iOlock
i P e r f o r m a r e - w r i t e of the
>cu rrent s e c t o r
iCall the @ R W R I T SVC

@SEEK
Seek a Cylinder

SVC Number 46
Seeks a specified cylinder and sector. @SEEK does not return an error if you
specified a non-existent drive or an invalid cylinder. @SEEK performs no action
if the specified drive is a hard disk.
Note: Seek of a sector is not supported by TRS-80 hardware. An implied seek
is included in sector reads and writes.
Entry Conditions:
A = 46(X'2E')
C=logical drive number
D=cylinder to seek
E = sector to seek
Exit Conditions:
Success always.
Only AF is altered by this SVC.

Software 138

@SEEKSC

SVC Number 71

Seek Cylinder and Sector
Seeks the cylinder and sector corresponding to the next record of the specified
file. (This is done by examining the NRN field of the FCB.) No error is returned
on physical seek errors.
Entry Conditions:

A =71 (X'471)

DE=pointer to the file's FCB
Exit Conditions:
Success always.

Example:
LD
LD
RST

DE»FCB

» P o i n t to the F i l e C o n t r o l
»Block
A»@SEEKSC iCause the next sector to be
iSEEKed b e f o r e it is
»actually needed
28H
iCall the 0SEEKSC SVC

Software 139

@SKIP
Skip a Record

SVC Number 72
Causes a skip past the next logical record. Only the record number contained
in the FCB is changed; no physical I/O takes place.
Entry Conditions:
A

=72(X'48')

DE=pointer to FCB for the file to skip
Exit Conditions:
If the Z flag is set or if A = X'1 C' or X'1 D,' then the Operation was successful.
Otherwise, A = error number. If A = X'1C' is returned, the file pointer is
positioned at the end of the file. Any Appending operations would be
performed here. If A = X'1 D' is returned, the file pointer is positioned
beyond the end of the file.
General:
AF is altered by this SVC.
BC contains the current record number. This is the same value äs that
returned by the @LOC SVC.
Example:
See the example for @LOC in Sample Program C, lines 305-311.

Software 140

@SLCT
Select a New Drive

SVC Number 41

Selects a drive. The time delay specified in your configuration (SYSTEM
(DELAY = Y/N)) is made if the drive selection requires it.
Entry Conditions:
A = 41 (X'291)

C=logical drive number (0-7)
Exit Conditions:
Success, Z f lag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.

Software 141

(r/ SOUND
Sound Generation

SVC Number 104

Generates sound using specified tone and duration codes. Interrupts are disabled during execution.
Entry Conditions:
A=104(X'68')

B = function code
bits 0-2: tone selection (0-7 with 0 = highest and 7 = Iowest)
bits 3-7: tone duration (0-31 with 0 = shortest and 31 = longest)
Exit Conditions:
Success always.
Only AF is altered by this SVC.
Example:
See Sample Program B, lines 43-45.

Software 142

@STEPI
Issue FDC STEP IN Command

SVC Number 45

Issues a disk Controller STEP IN command. This moves the drive head to the
next higher-numbered cylinder. @STEPI is intended for sequential read/write
operations, such äs disk formatting.
Entry Conditions:
A = 45(X'2D')
C=logical drive number
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.

Software 143

(a TIME
Get Time

SVC Number 19
Gets the System time in display formal (HH:MM:SS).
Entry Conditions:
A =19(X'13')
HL=pointer to buffer to receive the time string
Exit Conditions:
Success always.
HL=pointer to the end of buffer +1
DE=pointer to Start of TIME$ storage area in TRSDOS
AF and BC are altered by this SVC.
Example:
See the example for @DATE in Sample Program F, lines 252-253.

Software 144

@VDCTL
Video Functions

SVC Number 15
Performs various functions related to the video display. The B register is used
to pass the function number.

i

Entry Conditions:
A=15(X'0F)
B selects one of the following functions:
If B = 1, return the Character at the screen position specified by HL.
H=row on the screen (0-23), where 0 is the top row
L = column on the screen (0-79), where 0 is the leftmost column
If B = 2, display the specified Character at the position specified by
HL
C=Character to be displayed
H = row on the screen (0-23), where 0 is the top row
L = column on the screen (0-79), where 0 is the leftmost column
If B = 3, move the Cursor to the position specified by HL. This is done
even if the Cursor is not currently displayed.
H = roiv on the screen (0-23), where 0 is the top row
L = column on the screen (0-79), where 0 is the leftmost column
If B = 4, return the current position of the Cursor.
If B = 5, move a 1920-byte block of data to video memory.
HL=pointer to 1920-byte buffer to move to video memory
If B = 6, move a 1920-byte block of data from video memory to a
buffer you supply. In 40 line by 24 Character mode, there must
be a Character in each alternating byte for proper display.
HL=pointer to 1920-byte buffer to störe copy of video memory HL
must be in the ränge X'23FF' < HL < X'ECOI.
If B = 7, scroll protect the specified number of lines from the top of the
screen.
C=number of lines to scroll protect (0-7). Once set, scroll protect
can be removed only by executing @VDCTL with B = 7 and
C = 0, orby resetting the System. Clearing the screen with
(SHiFTJfCLl-Sff) erases the data in the scroll protect area, but the
scroll protect still exists.
If B = 8, change Cursor Character to specified Character. If the Cursor
is currently not displayed, the Character is accepted anyway
and is used äs the Cursor Character when it is turned back on.
The default Cursor Character is an underscore (X'5F') under
Version 6.2 and a X'B0' under previous versions.
C = Character to use äs the cursor Character
If B = 9, (under Version 6.2 only) transfer 80 characters to or from
the screen.
If C = 0, move characters from the buffer to the screen
If C = 1, move characters from the screen to the buffer
H = row on the screen
DE=pointer to 80 byte buffer
Note: The video RAM area in the Models 4 and 4P is 2048 bytes (2K).
The first 1920 bytes can be displayed. The remaining bytes contain the
type-ahead buffer and other System buffers.

Software 145

Exit Conditions:
lfB = 1:
Success, Z flag set.
A = Character found at the location specified by HL
DE is altered.
Failure, NZ flag set.
A = error number

lfB = 2:
Success, Z flag set.
DE is altered.
Failure, NZ flag set.
A = error number

lfB = 3:
Success, Z flag set.
DE and HL are altered.
Failure, NZ flag set.
A = error number

lfB = 4:
Success always.
HL = roiv and column position of the Cursor. H = row on the
screen (0-23), where 0 is the top row; L = column on the
screen (0-79), where 0 is the leftmost column.
lfB = 5:
Success always.
HL=pointer to the last byte moved to the video +1
BC and DE are altered.

If B = 6:
Success always.
BC, DE, and HL are altered.
lfB = 7:
Success always.
BC and DE are altered.
lfB = 8:
Success always.
A=previous Cursor Character
DE is altered.
If B = 9 (under Version 6.2 only):
Success, Z flag set.
BC, HL, DE are altered.
Failure, NZ flag set because H is out of ränge.
A= error code 43 (X'2B').
General:
Functions 5, 6, and 7 do not do ränge checking on the entry parameters.
If HL is not in the valid ränge in functions 5 and 6, the results may be
unpredictable.
Only function 3 (B = 3) moves the Cursor.
If C is greater than 7 in function 7, it is treated äs modulo 8.
AF and B are altered by this SVC.
Example:
See Sample Program F, lines 304-327.

Software 146

@VER
Write and Verify a Record

SVC Number 73

Performs a @WRITE Operation followed by a test read of the sector (if the write
required physical I/O) to verify that it is readable.
If the logical record length is less than 256, then the logical record in the user
buffer UREC is transferred to the file. If the LRL is equal to 256, a füll sector
write is made using the disk I/O buffer identified at file open time.
Entry Conditions:
A =73(X'49')
DE=pointer to FCB for the file to verify
Exit Conditions:
Success, Z flag set.
HL=pointer to user buffer containing the logical record
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
Example:
See Sample Program C, lines 338-346.

Software 147

@VRSEC
Verify Sector

SVC Number 50
Verifies a sector without transferring any data from disk.
Entry Conditions:
A = 50(X'32')
D=cylinder to verify
E=sector to verify
C=logical drive number (0-7)

^^^

Exit Conditions:
Success, Z flag set.
Failure, NZ flag set
A = error number
General:
AF is always altered by this SVC.
If the sector is a System sector, the sector is readable if an error 6 is
returned; any other error number signifies an error has occurred.
Example:
See the example for @WRSEC in Sample Program D, lines 68-76.

O

Software 148

@WEOF
Write End Of File

SVC Number 74
Forces the System to Update the directory entry with the current end-of-file
information.

P

Entry Conditions:
A = 74(X'4A)
DE=pointer to the FCB for the file to WEOF
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
AF is always altered by this SVC.

Example:
LD

DE»FC§

LD

A»0WEOF

RST

28H

Software 149

iPoint at the File Control
JBlocK
» F o r c e the d i r e c t o r y e n t r y
ito be updated n o w >
iinstead of uhen the file
i is closed
»Call the 6WEOF SVC

@WHERE

SVC Number 7

Locate Origin of SVC
Used to resolve the relocation address of the calling routine.
Entry Conditions:
A = 7(X'07')
Exit Conditions:
Success always.
HL=pointer to address following RST28H instruction
AF is always altered by this SVC.
Example:
See Sample Program F, lines 36-60.

Software 150

@WRITE

SVC Number 75

Write a Record
Causes a write to the next record identified in the File Control Block.
If the logical record length is less than 256, then the logical record in the user
buffer UREC is transferred to the file. If the LRL is equal to 256, a füll sector
write is made using the disk I/O buffer identified at file open time.
Entry Conditions:
A =75(X'4B')
HL=pointer to user record buffer UREC (unused if LRL=256)
DE=pointer to FCB for the file to write
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
AF is always altered by this SVC.
Example:
See the example for @VER in Sample Program C, lines 338-346.

Software 151

@ WRSEC

SVC Number 53

Write a Sector
Writes a sector to the disk.
Entry Conditions:
A =53(X'35')
HL=pointer to the buffer containing the sector of data
D = cylinder to write
E = sector to write
C = logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
Example:
See Sample Program D, lines 68-76.

Software 152

@WRSSC
Write a System Sector

SVC Number 54

Writes a System sector (used in directory cylinder).
Entry Conditions:
A =54(X'36')
HL=pointer to the buffer containing the sector of data
D = cylinder to write
E = sector to write
C = logical drive number
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.
Example:
See Sample Program D, lines 94-104.

Software 153

@WRTRK
Write a Track

SVC Number 55
Writes an entire track of properly formatted data. The data format must conform
to that described in the disk controller's reference manual. @WRTRK must
always be preceded by @SLCT.
Entry Conditions:
A =55(X'37')
HL=pointer to format data
D = track to v/rite
C = logical drive number (0-7)
Exit Conditions:
Success, Z flag set.
Failure, NZ flag set.
A = error number
General:
Only AF is altered by this SVC.

Software 154

Numerical List of SVCs
Following is a numerical list of the SVCs:
Dec

0

Hex

Label

2

00
01
02

@IPL
@KEY
@DSP

3
4
5

03
04
05

@GET
@PUT
@CTL

6
7
8
9
10
11
12
13
14
15

06
07
08
09
0A
0B
0C
0D
0E
0F

@PRT
@WHERE
@KBD
@KEYIN
@DSPLY
@LOGER
@LOGOT
@MSG
@PRINT
@VDCTL

16
17
18

10
11
12

@PAUSE
@PARAM
@DATE

19

13

@TIME

20

14

@CHNIO

21

15

@ABORT

22
23
24

16

@EXIT

18

@CMNDI

25

19

@CMNDR

26
27
28
29
30
31

1A
1B
1C
1D
1E
1F

©ERROR
@DEBUG
@CKTSK
@ADTSK
@RMTSK
@RPTSK

32
33
34
35

20
21
22
23

@KLTSK
@CKDRV
@DODIR
@RAMDIR

28
29
2A
2B
2C
2D

@DCSTAT
@SLCT
@DCINIT
@DCRES
@RSTOR
@STEPI

1

36-39
40
41
42
43
44
45

Software 155

Function
Reboot the System
Scan *KI device, wait for Character
Display Character at Cursor, advance
Cursor
Get one byte from a logical device
Write one byte to a logical device
Make a control request to a logical
device
Send Character to the line printer
Locate origin of CALL
Scan keyboard and return
Accept a line of input
Display a message line
Issue a log message
Display and log a message
Message line handler
Print a message line
Position/locate Cursor, get/put Character at cursor
Suspend program execution
Parse an optional parameter string
Get System date in the format MM/
DD/YY
Get System time in the format
HH:MM:SS
Pass control to the next module in a
device chain
Load HL with X'FFFF' error and goto
@EXIT
Exil program and return to TRSDOS
Reserved for future use
Entry to command interpreter with
return to the System
Entry to command interpreter with
return to the user
Entry to post an error message
Enter DEBUG
Check if task slot in use
Add an Interrupt level task
Remove an interrupt level task
Replace the currently executing task
vector
Remove the currently executing task
Check for drive availability
Do a directory display/buffer
Get directory record(s) or free space
into RAM
Reserved for future use
Test if drive is assigned in DCT
Select a new drive
Initialize the FDC
Reset the FDC
Issue FDC RESTORE command
Issue FDC STEP IN command

Dec

Hex

Label

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

@SEEK
@RSLCT
@RDHDR
@RDSEC
@VRSEC
@RDTRK
@HDFMT
@WRSEC
@WRSSC
@WRTRK
@RENAM
@REMOV
@INIT
@OPEN
@CLOSE
@BKSP
@CKEOF
@LOC

64

40

@LOF

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50

@PEOF
@POSN
@READ
@REW
@RREAD
@RWRIT
@SEEKSC
@SKIP
@VER
@WEOF
@WRITE
@LOAD
@RUN
@FSPEC
@FEXT
@FNAME

81
82
83

51
52
53

@GTDCT
@GTDCB
@GTMOD

55

@RDSSC

84
85
86
87
88
89
90
91

57
58

@DIRRD
@DIRWR

5A
5B

@MUL8
@MUL16

92
93
94

5D
5E

@DIV8
@DIV16

95
96

60

@DECHEX

97

61

@HEXDEC

Software 156

Function
Seek a cylinder
Test if requested drive is busy
Read a sector Header
Read a sector
Verify a sector
Read a track
Hard disk format
Write a sector
Write a System sector
Write a track
Rename a file
Remove a file or device
Open or initialize a file or device
Open an existing file or device
Close a file or device
Backspace one logical record
Check for end of file
Calculate the current logical record
number
Calculate the EOF logical record
number
Position to the end of file
Position a file to a logical record
Read a record from a file
Rewind a file to its beginning
Reread the current sector
Rewrite the current sector
Seek a specified cylinder and sector
Skip the next record
Write a record to a file and verify
Write end of file
Write a record to a file
Load a program file
Load and execute a program file
Fetch a file or device specification
Set up a default file extension
Fetch filename/extension from
directory
Get Drive Code Table address
Find specified or first free DCB
Find specified memory module
address
Reserved for future use
Read a System sector
Reserved for future use
Read directory record
Write directory record
Reserved for future use
Multiply 8-bit unsigned integers
Multiply 16-bit by 8-bit unsigned
integers
Reserved for future use
Divide 8-bit unsigned integers
Divide 16-bit by 8-bit unsigned
integers
Reserved for future use
Convert decimal ASCII to 16-bit
binary value
Convert a number in HL to decimal
ASCII

^^^^

>(^^^*k.

Dec

Hex

Label

98
99
100

62
63
64

@HEX8
@HEX16
@HIGH$

101
102

65
66

@FLAGS
@BANK

103
104
105-127

67
68

©BREAK
@SOUND

Software 157

Function
Convert a 1-byte number to hex ASCII
Convert a 2-byte number to hex ASCII
Obtain or set the highest and Iowest
unused RAM addresses
Point IY to the System flag table
Check, set, or reset a 32K bank of
memory
Set user or System break vector
Generate sound (tone and duration)
Reserved for future use.

Alphabetical List of SVCs
Following is an alphabetical list of the SVC labels and numbers:
Label
@ABORT
@ADTSK
@BANK
@BKSP
©BREAK
@CHNIO
@CKDRV
@CKEOF
@CKTSK
@CLOSE
@CMNDI
@CMNDR
@CTL
@DATE
@DCINIT
@DCRES
@DCSTAT
©DEBUG
@DECHEX
@DIRRD
@DIRWR
@DIV8
@DIV16
@DODIR
@DSP
@DSPLY
©ERROR
@EXIT
@FEXT
@FLAGS
@FNAME
@FSPEC
@GET
@GTDCB
@GTDCT
@GTMOD
@HDFMT
@HEXDEC
@HEX8
@HEX16
@HIGH$
@INIT
@IPL
@KBD
@KEY
@KEYIN
@KLTSK
@LOAD
@LOC
@LOF
@LOGER
@LOGOT
(5)MSG

Software 158

Dec

Hex

21
29
102
61
103
20
33
62
28
60
24
25
5
18
42
43
40
27
96
87
88
93
94
34
2
10
26
22
79
101
80
78
3
82
81
83
52
97
98
99
100
58
0
8
1
9
32
76
63
64
11
12
13

15
1D
66
3D
67
14
21
3E
1C
3C
18
19
5
12
2A
2B
28
1B
60
57
58
5D
5E
22
2
0A
1A
16
4F
65
50
4E
3
52
51
53
34
61
62
63
64
3A
0
8
1
9
20
4C
3F
40
0B
0C
0D

c

Label
@MUL8
@MUL16
@OPEN
@PARAM
©PAUSE
@PEOF
@POSN
@PRINT
@PRT
@PUT
@RAMDIR
@RDHDR
@RDSEC
@RDSSC
@RDTRK
@READ
@REMOV
@RENAM
@REW
@RMTSK
@RPTSK
@RREAD
@RSLCT
@RSTOR
@RUN
@RWRIT
@SEEK
@SEEKSC
@SKIP
@SLCT
@SOUND
@STEPI
@TIME
@VDCTL
@VER
@VRSEC
@WEOF
@WHERE
©WRITE
@WRSEC
@WRSSC
@WRTRK

Software 159

Dec

Hex

90
91
59
17
16
65
66
14
6
4
35
48
49
85
51
67
57
56
68
30
31
69
47
44
77
70
46
71
72
41
104
45
19
15
73
50
74
7
75
53
54
55

5A
5B
3B
11
10
41
42
0E
6
4
23
30
31
55
33
43
39
38
44
1E
1F
45
2F
2C
4D
46
2E
47
48
29
68
2D
13
0F
49
32
4A
7
4B
35
36
37

Sample Programs
The following sample programs use many of
the Supervisor calls described in this manual. These programs are not meant to be
examples of the most efficient programming,
but are designed to illustrate äs many Supervisor calls äs possible.
^^^^^

Software 160

Sample Program A
Source Line

Ln #
00001
00002
00003
00004
00005
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067

/
7
7

This program asks the user whether to run a program
or debug it and executes the SVCs required to perform
the chosen action.
PSECT

/

5000H

;The program begins at x'50001

Define the equates for the SVCs that will be used.

@DEBUG: EQU
@DSPLY: EQU
@FSPEC: EQU

27
10
78

@KEY:
EQU
@LOAD : EQU
@RUN:
EQU

1
76
77

MESS1:

'Do you wish to RUN this Program or DEBUG it ?'
0AH
;This moves the cursor to the next line
'Press  to RUN or  to DEBUG1
0DH
;Terminate the message string

DEFM
DEFB
DEFM
DEFB

; Enter the debugger (DEBUG)
; Display a message
;Verify a filespec or devspec and
;load it into a File Control Block
;Get a Character from the keyboard
;Load a program into memory
;Execute a program

PROGRM: DEFM
DEFB

'DIREX/CMD1
0DH

; Sample program to debug or execute
;Terminate the filespec

FCBl:

DEFS

32

;File Control Block for the program

7

Get the File Control Block for the program 'DIREX/CMD1 .

START : LD

r
»

LD
LD

DE, FCBl
A,@FSPEC

RST

28H

; Point at the filespec we want to
; execute or load into memory
; Point at the File Control Block
jPerform a validity check on the filespec
;and copy the filespec into the FCB.
;Call the @FSPEC svc

LD
LD
RST

HL,MESS1
A,@DSPLY
28H

; Point at our prompting message
;and print it on the display
;Call the @DSPLY svc

LD
RST

A,@KEY
28H

;Get the reply from the keyboard
;Call the @KEY svc

CP
JR

0DH
Z, RUNIT

;Was the Character an ?
;If Z was set , then run the program

If it wasn't an  , then we assume it was a  and
load the program and enter the debugger .
LD
LD
RST

;
y
r

HL,PROGRM

DE, FCBl
A,@LOAD
28H

;Point at the File Control Block
;and have this program loaded into memory
;Call the @LOAD svc

Note that this program must not be overwritten by the program
we are loading. In this example, it is known that the program
we are loading Starts at x'3000' and ends below x 1 5000'.
LD
RST

A,@DEBUG
28H

;

Execute the program

RUNIT:

LD
LD

DE, FCBl
A,@RUN

RST

28H

;Now invoke the system debugger, DEBUG
;Call the @DEBUG svc
;Note that ©DEBUG does not return

;Point at the File Control Block
;Tell TRSDOS to load and execute the
;program
;Call the @RUN svc

Software 161

oampie rrogram M, conimuea
00068
00069
00010
00011
00012
00013
00014
00015
00016

;Note that @RUN returns only if it can't
;find the program
;
;
;
;

Note that the program that is loaded by the @RUN svc must not
overwrite the File Control Block in this program. In this case,
it is known that the program we are executing Starts at x'3000'
and ends below the starting point of this program, x'5000*.
END

START

Software 162

Sample Program B
00002
00003
00004
00005
00006
00007
00008
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068

;This program accepts numbers from the keyboard
;and uses them to demonstrate the
;arithmetic and numeric conversion SVCs.
;It also uses the söund function to produce a tone at the
;beginning of the program.
PSECT
;

3000E

These are the SVCs used in this program.

@DECHEX :EQU
@DIV8: EQÜ
@DIV16: EQU
@DSP:
EQU
@DSPLY: EQÜ
@EXIT: EQU
@HEX8: EQU
@HEX16: EQU
QHEXDEC :EQU
@KEY:
EQU
@KEYIN: EQU
@MUL8: EQU
@MUL16: EQU
@SOUND: EQU

96
93
94
2

10
22
98
99
97
1
9
90
91
104

7

Other equates .

NUM5:
NÜM4:
NUM3:
NUM2:
NÜM1:
BRK:
CCC:

EQU
EQU
EQU
EQU
EQU
EQU
EQU

5
4
3
2
1
80H
0DH

rConvert decimal ASCII to binary
rPerform 8-bit division
;Perform 16-bit division
^Display a Character
^Display a message
;Return to TRSDOS Ready or the caller
;Convert an 8-bit value to hex ASCII
;Convert a 16-bit value to hex ASCII
;Convert a binary value to Decimal ASCII
rRead a Character from *KI
;Accept an input line from *KI
;Perform 8-bit multiplication
;Perform 16-bit multiplication
rProduce a tone

;Character code for  key
;Next line position

;Perform a subroutine 2 times to display prompting messages, key in
;and display divisor and dividend, convert those numbers to
;binary for the divide, and position the Cursor.
START:

LD
LD
RST
CALL
LD
LD
LD
CALL
LD
LD
CALL
CALL
LD
LD

B,SAH
A,@SOUND
28H
KEYIN
A,C
(DIVDl),A
HL,MESS9
DSPLAY
A, (DIVDl)
CfA
HEX8
KEY IN
A,C
(DIVRl),A

;Make the longest, hiqhest tone
;Make the noise
;Perform keyin subroutine for dividend
;Store the dividend in memory
;Address of hex message
;Display hex message
;Get the divisor into C for conversion
;from binary to hex
;Convert the number to hex
;Perform subroutine for divisor
;Store the divisor in memory

;Npw we are ready to perform the divide on the numbers entered.
LD
LD
LD
LD
RST

C,A
A,(DIVDl)
E,A
A,@DIV8
28H

;Put the divisor back for the @DIV8 SVC
;Get the dividend into E
;for the @DIV8 SVC
;Call the @DIV8 SVC

;Now display the answer and the remainder in decimal.
LD

(ANSI),A

;Store the answer in memory

Software 163

Sample Program B, continued
LD
LD
LD
CALL
LD
LD
LD
CALL
LD
CALL
LD
LD
LD
CALL

A, E
(REM1) ,A
HL, MESS 3
DSPLAY
A, (ANSI)
L, A
H, 0
HEXDEC
HL, MESS 4
DSPLAY
A,(REM1)
L, A
H,0
HEXDEC

;Get the remainder
; Store the remainder in memory
;Load address of answer message
;Display the message
;Get the answer into L for conversion
;Number to convert
;Put a 0 in the MSB
; Perform subroutine to display decimal value
;Address of remainder message
;Display remainder message
;Put remainder in A for hex conversion
; Number to convert
;Put 0 in the MSB
;Display decimal value

;Now divide with a 16-bit dividend.
LD
CALL
LD
LD
LD
LD
RST
LD
RST
LD
LD
CALL
LD
CALL
CALL
LD
LD
LD
CALL
LD
LD
LD
LD
RST
LD
LD
CALL
LD
CALL
LD
LD
LD
CALL

HL, MESS 6
DSPLAY
A,@KEYIN
HL,BÜF6
B , NUM5
C,J0
28H
A,eDECHEX
28H
(DIVD2),BC
HL, MESS 9
DSPLAY
DE,(DIVD2)
HEX16
KEY IN
A,C
(DIVR1),A
HL, MESS 3
DSPLAY
HL,(DIVD2)
A,(DIVRl)
C,A
A,@DIV16
28H
(REM1),A
(ANS2),HL
HEXDEC
HL, MESS 4
DSPLAY
A,(REM1)
L, A
H,0
HEXDEC

; Address of 2nd dividend message
;Display next message
;Key in up to 5 digits
; Store the number
;Maximum length of number
;Convert the number to binary
; Store the dividend
;Address of hex message
;Display hex message
;Put dividend into DE for conversion
;Convert the number from binary to hex
;Key in divisor
;Put the divisor into A
; Store the divisor in memory
;Address of answer message
;Display the message
;Put dividend into HL
;Get divisor into C

;Store the remainder
;Put the answer into HL
;Display answer in decimal
;Address of remainder message
;Display remainder message
;Get the remainder
;into L
;Put a 0 in MSB
;Convert the remainder to decimal

;Now try some multiplication of 8 bits.
LD
CALL
LD
LD
LD
LD
RST
LD
RST
LD
LD
CALL
LD
LD

HL,MESS8
DSPLAY
A,8KEYIN
HL,BUF2
B,NUM2
C,0
28H
A,@DECHEX
28H
(MCAND1),BC
HL, MESS 10
DSPLAY
A,@KEYIN
HL,BUF2

; Address of MUL8 message
;Display first multiplicand message
;Key in a 2-digit number
;Put i t here
;Maximum number of characters
;Convert the number to binary for math
;Store the multiplicand
;Address of MUL8 multiplier message
;Display first multiplier message
;Key in the multiplier
;Put it here

Software 164

^^^^

sample program B, contmuea
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171
00172
00173
00174
00175
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
00198
00199
00200
00201
00202
00203

LD
LD

B,NUM1
C,0

RST

28H

LD

A,@DECHEX

RST

28H

LD
LD
LD

(MIERl) ,BC
HL , MESS 13
A, @DSPLY

RST

28H

; Maximum number of characters
;Convert the multiplier to binary for math
;Store multiplier in memory
;Address of multiplier message
;Display multiplier message

;Now multiply the two numbers just entered.
LD
LD
LD
LD
LD
RST
LD
LD
CALL

A, (MCAND1)

;Get the multiplicand into C

C,A
A, (MIERl)
E, A
A,@MUL8

;Get the multiplier into E

28H
Lf A

H,0
HEXDEC

;Put the product into L
;Put 0 in the MSB
;Convert the product to decimal

;Now multiply a 16-bit by an 8-bit.
LD
CALL
LD
LD

LD
LD
RST
LD
RST
LD
LD
CALL
LD
LD
LD
LD
RST
LD
RST
LD
LD
LD
RST

LD
LD
LD
LD
RST
LD
LD
LD
LD
RST

LD
LD
LD
LD
RST
LD
LD
RST
LD
RST

HL,MESS11
DSPLAY
A, @ KEYIN
HL,BUF5
B,NUM4

c,0
28H
A,@DECHEX
28H
(MC AND 2) ,BC
HL,MESS12
DSPLAY
A, §KEYIN
HL,BUF3
B , NUM2

;Address of multiplicand message
;Display 2nd multiplicand message
; Enter larger multiplicand
;Put it here
;Maximum number of characters
;Convert the number to binary for math
; Store the multiplicand in memory
;Address of multiplier message
;Display message
;Enter larger multiplier
;Put it here
/Maximum number of characters

c,0
28H
A, @DECHEX
28H
(MIERl) ,BC
HL, MESS 13
A,@DSPLY
28H
HL, (MCAND2)
A, (MIERl)
C,A
A,@MUL16
28H
H, L
L, A
DE,BUF5
A, @ HEXDEC
28H
A,CCC
(DE) ,A
HL,BUF5
A,@DSPLY
28H
HL,MESS14
A,@DSPLY
28H
A,@KEY
28H

;Convert the number to binary for math
; Store the multiplier in memory
;Address of product message
;Display the message
;Put multiplicand into HL
;Get the multiplier into C
; Multiply the two numbers
;Get the 2nd byte of the product into
;H for conversion
;Get the LSB into L for conversion
;Convert the high-order byte to decimal
;for the display
;Tell the display when to stop
; Display the product
;Address of end message
;Display end message
;Allow the user to enter any Character
;or hit 

Software 165

Sample Program B, continued
00204
00205
00206
00207
00208
00209
00210
00211
00212
00213
00214
00215
00216
00217
00218
00219
00220
00221
00222
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254
00255
00256
00257
00258
00259
00260
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271

CP
JP
LD
RST

;Is it ?
;Yes, go back to beginning
;No, exit the program

BRK
NZ,START
A,@EXIT
28H

;These are the subroutines used by the calls to
;display a message, key in a 3-digit number, and convert it
;from decimal to binary.
KEYIN:

LD
CALL
LD
LD
LD
LD
RST
LD
RST
RET

HL,MESSl
DSPLAY
HL,BUF4
B,NUM3
C,0
A,@KEYIN
28H
A,@DECHEX
28H

;Display message
;Put the number here
; Maximum number of characters
;Key in a number
;Convert the number to binary
;Return to next sequential instruction

;Display what was loaded into HL before the call
DSPLAY: LD
RST
DEC
LD
DSPLYLP:LD
LD
RST
DJNZ
RET

A,@DSPLY
28H
HL
B,(HL)
C, 1 '
A,@DSP
28H
DSPLYLP

;@DISPLAY SVC
;Set HL back to blank byte
;Load B with the number of bytes
;Put a blank into C
;Display the blank
;until the correct number
;of blanks have been displayed
;Return to next instruction

;Convert l byte to hexadecimal.
HEX8:

LD
LD
RST
LD
LD
LD
LD
RST
RET

A,@HEX8
HL,BUF3

;Convert l byte to hex ASCII
;Put the converted value here

28H

A,CCC
(HL) ,A
A,@DSPLY
HL,BUF3

;Tell display when to stop
;Put CCC at end of buffer
;Display the hex value

28H

;Return to next instruction

;Convert 2 bytes to hexadecimal.
HEX16

LD
LD
RST
LD
LD
LD
LD
RST
RET

A,@HEX16
HL,BUF6
28H
A, CCC
(HL),A
A,@DSPLY
HL,BUF6
28H

;Convert a 2-byte number to hex ASCII
;Put the converted value here
;CCC at end of buffer so display
;knows when to stop
;Display the converted value
;Address of converted value
;Return to next instruction

;Convert from binary to decimal and display decimal value.
HEXDEC

LD
LD
RST
LD
LD
LD
LD
RST
RET

A,§HEXDEC
DE,BUF5
28H
A, CCC
(DE),A
A,@DSPLY
HL,BÜF5
28H

;Convert from binary to decimal
;Put converted value here
;CCC at end of buffer so display
;knows when to stop
;Display the hex value
;It's here
;Return to next instruction

Software 166

Sample Program B, continued
00212
00273
00214
00215
00216
00211
00218
00219
00280
00281
00282
00283
00284
00285
00286
00281
00288
00289
00290
00291
00292
00293
00294
00295
00296
00291
00298
00299
00300
00301
00302
00303
00304
00305
00306
00301
00308
00309
00310
00311
00312
00313
00314
00315
00316
00311
00318
00319
00320
00321
00322
00323

; These are the storage declarations .
BUF6:
BUF5
BUF4:
BUF3:
BUF2:
DIVRl:
DIVD1:
ANSI:
REM1:
MC AND 1:
MIER1:
MC AND 2:
DIVD2:
ANS 2:

DEFS
DEFS
DEFS
DEFS
DEFS
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFW
DEFW
DEFW

6
5
4
3
2
0
0
0
0
0
0
0
0
0

;Below are messages and prompting text used in the program.
MESS1:
MESS 3:
MESS 4:
MESS 6:
MESS8 :
MESS 9:
MESS 10:
MESS11:
MESS12:
MESS13:
MESS14:

DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFM
DEFB
DEFM
DEFB

13
;Number of blanks to print after message 1
'Enter a number (1-255).'
3
;Message-terminating Character
21
;Number of blanks to print after message 3
1
'The answer is
3
;Terminating Character
18
;Blanks after message
'The remainder is 1
3
;Terminating Character
6
;Blanks after message
'Enter a number (4369-65535).'
3
;Terminating Character
15
;Blanks after message
'Enter a number (1-28).'
3
;Terminating Character
16
;Blanks after message
'In hex ASCII, that is'
3
;Terminating Character
17
;Blanks after message
'Enter a number (1-9).'
3
;Terminating Character
11
;Blanks after message
'Enter a number ( 1-4100). '
3
;Terminating Character
15
;Blanks after message
'Enter a number (1-15).'
3
;Terminating Character
'The product of those 2 numbers is '
3
;Terminating Character
'Press  to end or any other key to continue.'
0DH
;Terminating Character

END

START

Software 167

Sample Program C
Ln #
00001
00002
00003
00004
00005
00006
00008
00009
00010
00011
00012
00013
00014
00015
00016
00011
00018
00019
00020
00021
00022
00023
0002 A
00025
00026
00021
00028
00029
00030
00031
00032
00033
00034
00035
00036
00031
00038
00039
00040
00041
00042
00043
00044
00045
00046
00041
00048
00049
00050
00051
00052
00053
00054
00055
00056
00051
00058
00059
00060
00061
00062
00063
00064
00065
00066
00061

Source'Dine
i
t
i
i

This program pro
file, and create
file is copied t
the current reco
PSECT

•
/
*i

3000H

60
87
2
10
26
22
79
80
78
97
58
8
9
63
59
67
57
73

;

First, prompt fo

BEGIN:

LD
LD
RST

J

Now, read the fi

*i

»

;This program Starts at x'30001

X^N

First, declare t
This is not mand
mandatory, but it makes the program easier to follow.

©CLOSE: EQU
8DIRRD: EQU
©DSP:
EQU
©DSPLY: EQU
©ERROR: EQU
©EXIT: EQU
©FEXT: EQU
©FNAME: EQU
©FSPEC: EQU
©HEXDEC :EQU
©INIT: EQU
©KBD:
EQU
©KEYIN: EQU
©LOC:
EQU
©OPEN: EQU
©READ: EQU
©REMOV: EQU
©VER:
EQU

/

Then the data in the first
.le. While the Copy progresses,

HL,MESG1
A, ©DSPLY
28H

;Close a file or device
;Read a directory record
;Display Character at cursor
;Display a message
;Display an error message
;Exit and return to TRSDOS or the caller
;Add a default file extension
;Fetch a filespec from the directory
;Verify and load a filespec into the FCB
;Convert a binary value to decimal ASCII
;Open an existing file or create a new file
;Scan the keyboard for a Character
;Accept a line of text from the *KI device
;Return the current logical record number
;Open an existing file
;Read a record from an open file
;Delete a file from disk
;Write a record to disk. Does the same thing
;as ©WRITE (Svc 75), but it also makes sure
;the Written data is readable.

;Get the first message
;Display a line on the screen
;Call the ©DSPLY svc

LD
LD
LD
LD
RST
JP
JP

HL,FILE1
B, 24
C,0
A, ©KEYIN
28H
C,QUIT
NZ,ERR

;Put the name of the Ist file here
;Allow up to 24 characters
;A zero is required by the svc
;Get a filename from the user
;Call the ©KEYIN svc
;The user pressed 
;An Error occurred

LD
OR
JR

A, B
A
Z, BEGIN

;Get the number of characters
;See if that value was zero
;Nothing was entered, ask again

The user has typ«
using the ©FSPEC
LD
LD

HL,FILE1
DE,FCB1

LD

A, ©FSPEC

RST
JR

28H
Z,ASK2

rPoint at the text the user entered
;Point at the File Control Block
;that is to be used for the source file.
rThe ©FSPEC svc will make sure the filename
;that is in buffer named "filel" is valid.
;If it is, it is copied into the File
rControl Block (FCB) to be used by the ©OPEN
?or ©INIT svc later on.
rCall the ©FSPEC svc
?The name for file l is ok, so skip this

At this point th<

Software 168

O

Sample Program C, continued
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135

to be in an invalid format.
error message.
LD
LD
RST
JR

HL,BADFIL
A,@DSPLY
28H
BEGIN

The following code will print the

;Point at the bad filename message
;Display it
;Call the @DSPLY svc
;Start over

At this point, the source filename appears to be valid.
The code below asks for the second filename and checks it for
validity also.
ASK2:

HL,MESG2
A,@DSPLY
28H
HL,FILE2

LD
LD
RST
LD
LD
LD
LD
RST
JP
JP

C,0
A,@KEYIN
28H
C,QUIT
NZ,ERR

;Prompt for the target filename
;Print that on the screen
;Call the @DSPLY svc
;Put the name of the 2nd file here
;Allow up to 24 characters
;A zero is required by the svc
;Get a filename from the user
;Call the @KEYIN svc
;The user pressed 
;An Error occurred

LD
OR
JR

A,B
A
Z,ASK2

;Get the number of characters
;See if that value was zero.
;Nothing was entered, ask again

B,24

The user has typed something, so it must be checked for validity
using the @FSPEC svc.
LD
LD
LD
RST
JR

HL,FILE2
DE,FCB2
A,@FSPEC
28H
Z,F20K

;Point at the text the user entered
;Point at the File Control Block
;Check the name for validity
;Call the @FSPEC svc
;The name for file 2 is ok, so skip this

The name for file 2 is invalid so print an error message
LD
LD
RST
JR

HL,BADFIL
A,@DSPLY
28H
BEGIN

;Point at the bad filename message
;Display it
;Call the @DSPLY svc
; Star t; over

Now we will attempt to add an extension to the target file
if the user did not specify one. We use the extension that
was specified on the source file. If it does
not have one, then we will not try to add one to the target file.
F20K:

LD

HL,FCB1+1

FDIV:

LD
CP
JR
CP
JR
CP
JR
INC
JR

A,(HL)
'/'
Z,EXTN
0DH
Z,NOEXT
03H
Z,NOEXT
HL
FDIV

INC
LD
LD
RST

HL
DE,FCB2
A,@FEXT
28H

EXTN:

;Point at the source filename
;We start with the second Character since
;the filename must be at least one Character
;Get a Character from the filespec
;Is the Character the extension prefix?
;Yes, this will be our default extension
;Have we reached the end of the filespec?
;Yes, there is no extension so don't add one
;Test both terminators
;Advance the pointer to the next Character
;Keep looking
;Advance pointer to first byte of extension
;Point at FCB for the target file (file 2)
;Add an extension if one is not present
;Call the @FEXT svc

Now we have two filenames.
to make sure it exists.

First we will open the source file

Software 169

Sample Program C, continued
00136
00131
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171
00172
00173
00174
00175
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
J00198
00199
00200
00201
00202
00203

NOEXT:

LD
LD

DE,FCB1
HL,BUF1

LD

B,0

LD
RST
JR
CP
JP

A,@OPEN
28H
Z,SIZ
42
NZ,ERR

;Point at the File Control Block for filel
;Point at the System buffer. This buffer
;is used by the System to block data that
;is Written to disk and de-block data that
;is read from disk when the Logical Record
?Length of the file is not 256. If it is
;256, then this buffer is not used.
;Use LRL 256 for now since we don't know
;what to use yet.
rOpen the file
;Call the @OPEN svc
rThe file opened and is LRL 256.
;Was the error a LRL Open Fault?
;No, perhaps the file does not exist.

^^^^

At this point, the file is open and we can now examine the
directory to find out what LRL it was created with so we can
use that value to make the copy.
SIZ

LD

A, (FCBl+6)

AND
LD
LD

7
C,A
A, (FCBl+7)

LD
PUSH
LD
RST

B, A
BC
A,@CLOSE
28H

;Get the byte in the FCB which contains
;the drive number the file is on
;Erase all other information in that byte
;Save that value here
;This reads the Directory Entry Code (DEC)
;out of the FCB so we can use it
;Store the DEC here
;Save that value for now
;We can close the source file for now
;Call the @CLOSE svc

POP
LD
RST

BC
A,@DIRRD
28H

;Get the DEC value back off the Stack
;Read the directory record for that file
;Call the @DIRRD svc

LD
LD

IX, HL
A, (IX+4)

LD

(LRL),A

;Put the pointer to the directory record
;here and read the DIR+4 entry which
;contains the LRL of the source file.
;Save that value

Before we go any further, we should check to see if the target file
already exists.
LD
LD
LD
LDIR

DE,COPY
HL,FCB2
BC,32

;First, make a copy of the FCB
;in case we have to delete a file
;Move the entire block

LD
LD
LD
LD
RST
JR
CP
JR

DE,FCB2
HL,BUF2
B,0
A,@OPEN
28H
Z, EXISTS
42
NZ,NOFILE

;Point at the target File Control Block
;Use this äs the buffer for now
;Use LRL 256 for now
;0pen it and see if it is there
;Call the @OPEN svc
;The file already exists, better ask
;Was the error a LRL mismatch?
;No, so the file does not exist.

HL,FEXST

;Point at a prompt asking if it is ok
;to erase the file that already exists
;Print that message
;Call the @DSPLY svc

EXISTS: LD

WAIT:

LD
RST

A,@DSPLY
28H

LD
RST
JR

A,@KBD

CP
JR

NZ, WAIT

;Wait for the user to type Y or N
;Call the @KBD svc
;Loop until something is typed

Z,KILLIT

;Was a 'Y1 typed?
;Then kill the file

28H

Software 170

^ISSIS^

Sample Program C, continued
00204
00205
00206
00201
00208
00209
00210
00211
00212
00213
00214
00215
00216
00211
00218
00219
00220
00221
00222
00223
00224
00225
00226
00221
00228
00229
00230
00231
00232
00233
00234
00235
00236
00231
00238
00239
00240
00241
00242
00243
00244
00245
00246
00241
00248
00249
00250
00251
00252
00253
00254
00255
00256
00251
00258
00259
00260
00261
00262
00263
00264
00265
00266
00261
00268
00269
00210

CP
JR
CP
JR
CP
JR

SHUT:

LD
LD
RST
JP

;

•yi

'N'

Z, SHUT
'n'

NZ, WAIT

;Do they want to leave the file alone?
;No, just close the file and quit
;Was it a lowercase 'N'?
;No, loop until we see something we like

DE,FCB2
A,@CLOSE

;Close the target file

28H

;Call the ©CLOSE svc
;Exit to TRSDOS

QUIT

At this point, we have been given the OK to delete the file
that has the same name äs the target file.

KILLIT: LD
LD
RST

C,0DH
A,@DSP
28H

LD
LD
RST

DE,FCB2
A,@REMOV

JP

NZ,ERR

LD
LD
LD

HL, COPY
DE,FCB2
BC,32

28H

LDIR
;
;
;

;Check for lowercase too

Z, KILLIT

;First move display to a new line
;Display an 
;Call the @DSP svc
;Point at the target file's FCB
;Delete the file from disk
;Call the @REMOV svc. (This is the same
;as the @KILL call on other TRSDOS Systems . )
;An error occurred, print it and quit
;Note that after a @REMOV succeeds ,
;the filespec is removed from the FCB.
;So we have to keep a copy around
;in case we need it.
;Get the copy
;Put i t here
;Move up to 32 bytes
;Copy the FCB so we can continue

Now we know what Logical Record Length (LRL) to use in the
copy , so we can open the source file and create the target file
with the correct record lengths .

NOFILE: LD
LD
RST
LD
LD
RST

HL, FCB 1
A,@DSPLY

28H
HL,SPACES
A,@DSPLY

28H

LD
LD
LD
LD
LD
RST
JP

DE,FCB1
HL,BUF1
A, (LRL)
B, A
A,@OPEN

LD
LD
RST

HL, ARROW
A,@DSPLY

LD
LD
CP
JR
LD
JR

DE,FCB2
A, (LRL)

LRL256: LD
LRLCOM: LD
LD

28H
NZ,ERR

28H

0
Z,LRL256
HL,BUF2
LRLCOM
HL,BUF1
B, A
A,@INIT

; Point at the filename in the FCB
; Print that name
;Call the @DSPLY svc
; Point at some spaces
;Space over a few places on the screen
;Call the @DSPLY svc
;Point at File Control Block for source file
;Put data in this
;Read the Logical Record Length
;Load the Logical Record Length
;Open the source file
;Call the @OPEN svc
;Open failed
; Point at the arrow text
;Print that to show the direction of copy
;Call the @DSPLY svc
;Point at File Control Block for target file
;Get the Logical Record Length
;Is the LRL 256?
;Then we do something special
;Use a different buffer for target file
;Jump to common code
;We use the same buffer when the LRL is 256
;since there is no need to block and de-block
;the data.
;Load the Logical Record Length
;Open the target file

Software 171

Sample Program C, continued
00271
00272
00273
00274
00275
00276
00277
00278
00279
00280
00281
00282
00283
00284
00285
00286
00287
00288
00289
00290
00291
00292
00293
00294
00295
00296
00297
00298
00299
00300
00301
00302
00303
00304
00305
00306
00307
00308
00309
00310
00311
00312
00313
00314
00315
00316
00317
00318
00319
00320
00321
00322
00323
00324
00325
00326
00327
00328
00329
00330
00331
00332
00333
00334
00335
00336
00337
00338

RS T
JR

28H
NZ,ERR

;Call the @INIT svc
.;Init failed

LD

DE,FILE2

LD
LD
LD
AND
LD
LD
RST
LD
LD
RST

A, (FCB2+7)
B,A
A,(FCB2+6)
7
C,A
A,@FNAME
28H
HLrFILE2
A,@DSPLY
28H

;We are going to get the filename for
;the target file from the system
;instead of using the one we have. The
;reason for this is that the system will
;append the drive number to the filename
;if one was not specified.
;Get the Directory Entry Code for the file
;Put the DEC here
;Get the Drive Number from the FCB
;Lose all data except the drive number
;Store drive number here
;Have the system produce a filespec
;Call the @FNAME svc
;Now point at the filespec produced
;and print it out
;Call the @DSPLY svc

LD
LD
RST

HL,SPACES
A,@DSPLY
28H

;Space over a few more places
;so the display will look neat
;Call the @DSPLY svc

At this point, both files are open and ready to be used.
The following code reads a record from the source file
and writes it to the target file. This is done until an
end of file is encountered.
LOOP:

LD
LD
LD
RST
JR
LD

DE,FCB1
HL, BUFFER
A, @ READ
28H
NZ, EOF
DE, FCB 2

;Point at file 1 (source file)
;Put data here
;Read a record from the source file
;Call the @READ svc
;Jump if the eof has been reached
;Point at file 2 (target file)

Bef ore writing the record, display the record number, which
is obtained from the @LOC svc.

EDIT:

NUMBR:

LD
RST

A,@LOC
28H

;Get the current record number
;Call the @LOC svc

PUSH
POP

BC
HL

LD
LD
RST

DE,LOCMSG+1
A,@HEXDEC
28H

;Get the current record number
;and put it in register HL
; Store the result here.
;Convert binary to ASCII in decimal format
;Call the @HEXDEC svc

LD
LD
CP
JR
INC
JR

A, 1 '
HL,LOCMSG
(HL)
NZ , NÜMBR
HL
EDIT

;Get a blank
;Look at the front of the buffer
;Is the Character a blank?
;A number has been found
;Advance the pointer
;Loop until we find a number

DEC
LD
LD

HL
A, ' ('
(HL) ,A

LD
LD
RST

HL,LOCMSG
A,@DSPLY
28H

;Back up one position
;Get the Character we want to insert
;Store that Character.
;The buffer now contains
;  (record number)
;<7 left-cursor characters>
; Point at this text
;and display it on the screen
;Call the @DSPLY svc

Now write the record to the target file.
LD

DE,FCB2

;Point at the FCB for the target file

Software 172

C

Sample Program C, continued
00339
003 40
00341
00342
00343
00344
00345
00346
00347
00348
00349
00350
00351
00352
00353
00354
00355
00356
00357
00358
00359
00360
00361
00362
00363
00364
00365
00366
00367
00368
00369
00370
00371
00372
00373
00374
00375
00376
00377
00378
00379
00380
00381
00382
00383
00384
00385
00386
00387
00388
00389
00390
00391
00392
00393
00394
00395
00396
00397
00398
00399
00400
00401
00402
00403
00404
00405

LD
LD

HL,BUFFER
A,@VER

RST
JR

28H
NZ f ERR

JR

LOOP

;Point at the data read from file l
;Write a record to the target file
;The @VER does the same thing äs the
;@WRITE svc, only it also checks the
;data to make sure it is readable.
;Call the @VER svc
;An error occurred on write; possibly
;the disk is füll.
;Loop until an error occurs.

This code checks the error to make sure it was an end of file
condition and, if so, closes the source & target files.
EOF;

CP
JR
CP
JR

28
Z,EOFYES
29
NZ,ERR

;Was it an end of file encountered?
;Yes, close the file
;Was it "Record number out of ränge"?
;No, must be some other error

It is possible to get Error 29 if the file being copied has
an EOF that is not a multiple of the file's LRL
EOFYES

QUIT:

LD
LD
RST
JR

DE,FCB1
A,§CLOSE
28H
NZ,ERR

;Point at file l (source file)
;Close the file
;Call the ©CLOSE svc
;An error occurred„ abort

LD
LD
RST
JR

DE,FCB2
A, ©CLOSE
28H
NZ,ERR

;Point at
;Close it
;Call the
;An error

LD
LD
RST

HL, OK
A,©DSPLY
28H

;Print a message saying the copy is done
;Call the ©DSPLY svc

LD
RST

A,@EXIT
28H

;Exit to TRSDOS or the calling program
;Call the ©EXIT svc

file 2 (target file)
also
©CLOSE svc
occurred, abort

The ©EXIT svc does not return.
ERR:

OR

040H

LD
LD
RST

C,A
A, ©ERROR
28H

;Turn on bit 6, which
;will cause the TERROR svc to print
;the short error message. Bit 7
;is not set, which instructs the ©ERROR
;to abort this program and return to
;TRSDOS Ready.
;Put error code & flags in register C
;Call the system error displayer
;Call the ©ERROR svc

Because bit 7 is not set, the ©ERROR svc will not return.
Storage Declaration
SPACES
ARROW:
OK:

MESG1:
MESG2:
FEXST:

DEFM
DEFB
DEFM
DEFB
DEFB
DEFM
DEFB
DEFM
DEFB
DEFM
DEFB
DEFM
DEFB

;ASCII Space char.for display formatting

3
'=>

'
;Arrow for display shows data direction
3
;Advance cursor 10 spaces without erasing
10%25
1
[Ok]'
;üsed to indicate the Copy is complete
0DH
;Terminated with an 
'Copy Filespec >'
3
'To Filespec >'
3
'Destination File Already Exists - Ok to Delete it (Y/N) ?'
3

Software 173

Sample Program C, continued
00406
00407
00408
00409
00410
00411
00412
00413
00414
00415
00416
00417
00418
00419
00420
00421
00422
00423
00424

DEFB
DEFB

'Invalid Filename - Try Again 1
0DH
' 12345)'
;This will be used in building the LOC
;Display will appear äs (d) to (ddddd).
7%24
;Backspace without erasing
3
;Etx, used to get the @DSPLY svc to stop

DEFS
DEFS
DEFS
DEFS
DEFS
DEFB

32
32
32
32
32
0

BADFIL: DEFM
DEFB
LOCMSG: DEFM

FILEl:
FILE2:
FCB1:
FCB 2:
COPY:
LRL:

BÜF1:
DEFS
BUF2:
DEFS
BUFFER; DEFS

END

256
256
256

;User Text Originally placed here
;Target Filename goes here
;32 bytes for the File Control Block
;32 bytes for the File Control Block
;An extra copy of the target FCB goes here
;The Logical Record Length of the source
;file will be stored here
;System buffer for File l
;System buffer for File 2
;Data buffer for both files

BEGIN

;"begin" is the starting address

c

Software 174

Sample Program D
Source Line

Ln #

P

00001
00002
00003
00004
00005
00006
JW07
00009
00010

00011
JW12
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
J30024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067

7
j
;
;
;

This program will read a sector from the disk in Drive 0
and will write it to a disk in Drive 1. The disk in Drive 1
must be formatted, but should not have anything important on
it. This program makes an assumption that the directory is
located on cylinder 20 (x'141).
PSECT

r

;This program begins at x'3000'.

Define the equates for the SVCs that will be used.

@ ABORT: EQü
@CKDRV: EQU
@DCSTAT :EQU
TERROR: EQU
@EXIT : EQU
@RDSEC: EQU
0RDSSC: EQU
@WRSEC: EQU
@WRSSC: EQU
7

3000H

21
33
40
26
22
49
85
53
54

7 Abort and return to TRSDOS
?Test to see if a drive is ready
;Verify that a drive is defined in the DCT
7Display an error message
7 Return to TRSDOS or the calling program
7Read a sector
?Read a System sector
;Write a sector
;Write a System sector

Other Equates

SYSSEC: EQU
USRSEC: EQU

1400H
0000H

7The System sector is Cylinder 20, Sector 0
?The regulär sector is Cylinder 0, Sector 0

;

First, test the target drive and make sure it is defined.

START:

LD
LD
RST
JR

;

Now, test and make sure the target drive contains a formatted
disk and is write-enabled.

;

7
;

C,l
A,@DCSTAT
28H
NZ, ERROR

LD
LD

C,l
A,@CKDRV

RST
LD

28H
A, 8

JR
LD

NZ, ERROR
A, 15

JR

C, ERROR

,-Select Drive 1
,-Ask if the drive is listed in the DCT
,-Call the @DCSTAT svc
;If NZ, then the drive is not defined
?and we will abort execution.

7Select Drive 1
,-Test to see if the disk is formatted
?and is write-enabled. Note that the
7 disk must be formatted by TRSDOS 6.x
7or by LDOS 5.1.x to be cons idered
7 "formatted" by this svc.
?Call the @CKDRV svc
7This will become the error number if the
7drive was not ready. This is done
7because the @CKDRV svc does not return error
;codes .
?The drive is not ready
7This will become the error number if the
7drive is ready and is write-protected.
7 As above, this is done because @CKDRV does
?not return error messages .
;The disk is formatted, but it is
7write-protected. In either case, abort.

Now that we know the target drive is ready, read a sector
from the source drive and write it to the target drive (Drive 1).
LD
LD

C,0
DE, USRSEC

LD
LD
RST
JR

HL,BUFF
A,@RDSEC
28H
NZ, ERROR

7Select Drive 0
7 Read the first sector on the disk,
7Cylinder 0, Sector 0.
7?oint to a buffer which will hold the sector
7 Read a non-system sector
,-Call the @RDSEC svc
?If NZ, an error occurred, so abort

Software 175

Sample Program D, continued
Nowf write the sector to the target drive.
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127

LD
LD

DE,USRSEC

LD
LD
RST
JR

HL,BUFF
A,@WRSEC
28H
NZ,ERROR

;Select Drive l
;Write the sector to Cylinder 0, Sector 0
;on Drive l
;Point to the buffer containing the sector
;Write the sector to disk
;Call the @WRSEC svc
;If NZ, an error occurred, so abort

Now we will read a system sector from Drive 0 and write it on
drive 1. The difference between a System sector and a non-system
sector is that the Data Address Marks (DAM) are different. These
were Written to the disk when it was formatted. TRSDOS 6.x uses
these äs an extra check to make sure that a write of user data
does not accidentally get placed over a sector containing system
data. All of the sectors in the directory cylinder are marked
äs system sectors.

LD
LD
LD
LD
RST
JR

C,0
DE,SYSSEG
HL,BUFF
A,§RDSSC
28H
NZ,ERROR

;Select Drive 0
;Read Cylinder 20, Sector 0
;Store the sector at this address
;Read a system sector
;Call the @RDSSC svc
;An error occurred, so abort

Now write the sector to the target drive äs a system sector
There is no requirement that a sector must be placed at the
same cylinder and sector location äs it was read from, but
for simplicity, we are doing that.

LD
LD
LD
LD
RST
JR.

DE,SYSSEC
HL,BUFF
A,@WRSSC
28H
NZ,ERROR

;Select Drive l
;Write Cylinder 20, Sector 0
;Point to the data to be Written
;Write a system sector
;Call the @WRSSC svc
;An error occurred, so abort

LD
RST

A,§EXIT
28H

;Return to TRSDOS or the calling program
;Call the @EXIT svc

This routine displays an error message if anything goes wrong
Note that @CKDRV does not return an error message, so §ERROR
cannot be used for it without some manipulation.
ERROR:

BÜFF:

OR
LD
LD

0C0H
C,A
A,§ERROR

RST

28H

LD

A,0ABORT

RST

28H

DEFS

256

END

START

;Set bit 7
;Load error number into register C
;This will display the error message
;and return to the calling program
;Call the @ERROR svc
;Nowf force an abort. This will return
;to TRSDOS Ready and will abort any
;JCL file that is currently executing
;Call the @ABORT svc
;256-byte buffer to störe the sector that
;is read and then Written

Software 176

G

Sample Program E
Source Line

Ln #

00001

9

00002
00003
J00004
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067

;

This program displays the filenames of the disk in
Thi
Dri
Drive
0 three different ways.
PS E
PSECT

;

3000H

Fir
First,
declare the equates for the SVCs we intend to use.
This is not mandatory, but it makes the program easier to follow.
Thi

@CMNDI: EQU

24

@CMNDR: EQU

25

@DODIR: EQU

34

;
;

;Program begins at x'30001

;Execute a TRSDOS command and return
;to TRSDOS Ready
;Execute a TRSDOS command and return
;to the calling program
;Display visible filenames on the
;specified disk drive

Fir
First,
pass a "DIR :0" command to the system. TRSDOS will
execute
exe
this command and then return to this program.

START : LD
LD
RST

HL,DIR0
A,@CMNDR
28H

;Point at command we want to execute
;Execute the specified command and return
;Call the @CMNDR svc

;
;
;

You may have noticed that the DIR displayed the files, but that
1
they
the
were not sorted alphabetically. This is because the DIR
comi
command
will not use memory above x'3000' when it is invoked with
svc. This prevents the DIR command from performing a
a @CMNDR
@<
sor of the filenames.
sort

;

Now
Now do a directory command using the @DODIR svc

;
;

LD

B,0

LD
LD

A,@DODIR

RST

28H

;Use Function 0 which displays all
;visible files in the directory.
;Put source drive number in register C
;The filenames will be read from the
;directory and displayed in the
;order they appear in the directory.
;Call the @DODIR svc

Now
»s a "DIR :0" command to the system. This time
the
the command will be executed and then TRSDOS will not return
to 1this program, but will return to TRSDOS Ready.
to

LD
LD

HL,DIR0
A,@CMNDI

RST

28H

;Point at the command we want performed
;and execute it, but don't return to
;this program.
;Call the QCMNDI svc
;This svc returns to TRSDOS Ready.

Not«
Note that when the library command DIR is performed this time,
the display of files is sorted. This is because DIR determines
thal
: was invoked with a @CMNDI svc, and it will not return
to 1the calling program. Therefore, DIR is free to use the
to
mem<
memory above x'30001 to perform the sort of the filenames in
the directory.

Conj
DIR0:

DEFJ

'DIR :0'

DEFI

0DH

END

START

;This command is passed to TRSDOS
;via the @CMNDR and 0CMNDI SVCs.
;It must be terminated with an 

Software 177

Sample Program F
Ln #

Source Line

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067

This program adds to the system task scheduler a task
which displays the date and a running count of the number
of times the task has been executed .
For simplicity, the program tries to use task slot 0.
If it is already in use, it assumes that the task using that
slot is this program, and it kills the task. It then tries to
recover the memory used by the task in high memory.
If the task slot is not in use, the task is placed in high memory,
and the address of the task is passed to the task scheduler.
The first time you run this program it adds the task, and the
next time you run this program, it removes the task.
PSECT
>
,

3000H

;This program Starts at x'3000'

First, declare the equates for the SVCs we intend to use.
This is not mandatory, but it makes the program easier to follow.

@ADTSK: EQU
@CKTSK: EQU
@DATE: EQU
@DSPLY: EQU
@EXIT: EQU
@GTMOD : EQU
@HEXDEC :EQU
@HIGH$ : EQU
@RMTSK: EQU
@VDCTL: EQU
@WHERE : EQU

29
28
18
10
22
83
97
100
30
15
7

;Add a task entry to the scheduler
;Check to see if a task slot is in use
;Return the date in ASCII format
;Display a message
; Return to TRSDOS Ready or the caller
;Locate a memory module
;Convert a binary value to decimal ASCII
;Read or modify HIGH$ or LOW$
;Remove a task entry from the scheduler
;Perform video operations
;Find out where the program counter is
;when this SVC is executed. This is
;useful in relocatable code that must
;make absolute address references to
;call subroutines or modify data.

Below we will define a macro to simulate a call relative
instruction. Since the task must be able to run no matter
where it is placed, it must use relative jumps and calls.
The Z80 instruction set has a jump relative ( JR) , but does
not have a call relative instruction. This can be simulated
using the @WHERE SVC, which returns the address of the caller
in a register. This address can be adjusted and placed on
the Stack äs a return address. Then a jump relative can be used
to reach the subroutine.
CALLR : MACRO
PUSH
PUSH
PUSH
LD
RST
LD
ADD
POP
POP
EX
JR
ENDM
J
i
i
i
i

#1
HL
BC
AF
A,@WHERE
28H
BC, 3+1+1+1+1+2
HL,BC
AF
BC
(SP) ,HL
#1

c

;#1 will be the address you want to call
;Save the regist er s we damage
;Save it
;Save it
;Get our current address
;Call the @WHERE svc
;Get the lengths of the instructions after
;the SVC. This will allow the subroutine
;to return to the correct address.
;Add that off set to where we are
;Put Stack back
;Restore registers
;Put return address on Stack and restore HL
;Jump to the subroutine
;End of the macro

This is the main program. It loads at x'30001. It decides
if it needs to add or remove the task in the scheduler tables .
If it adds the task, it moves a copy to the top of memory and
protects it, and adds a task entry to the scheduler.
If it is removing a task, it kills the entry in the scheduler

Software 178

^^WWSSHsRk

Sample Program F, continued

P

00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00 ff 8 S
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135

tables, and then attempts to recover the memory used by the task
BEGIN:

LD
LD
RST
JR

C,0
A, @CKTSK
28H
NZ,KILLIT

;First, we will test slot 0
;to see if anyone is using it
;Call the @CKTSK svc
;There is a task using slot 0, kill it

At this point, we want to add a task to high memory.
First we find the value for HIGH$ and put a copy of the
task there. Then we protect the task by moving HIGH$ below
the new task.
LD
LD
LD
RST
LD

HL,0
B,H
A,@HIGH$
28H
(ENDADD),HL

LD
LD
LD

LDDR

DE,HL
;Put that value here
HL,MODEND-1
;Point at the end of the module
BC,MODEND-MODULE;Move the module from where it is
;right now to a position below HIGH$
;Do the copy

LD
LD
LD
RST

B,0
A, @HIGH$
28H

HL, DE

;First, get the value of HIGH$
;Read HIGH$
;Call the @HIGH$ svc
;Save this value äs the last address
;that the task will be stored in once it
;is moved to high memory

;Now protect the module using HIGH$
;Update HIGH$
;Call the @HIGH$ svc

Now we need to load the TCE entry in the module with the address
of the first instruction to be executed.
LD
LD
ADD
LD
LD

IX,HL
;IX now points at memory header
BC,ENTRY-MODULE+1
;Get the offset into the module
;of the first instruction
HL,BC
;HL now contains the actual starting address
(IX+(1+MODTCB-MODULE)),L
;Store LSB of the address
(IX+l+d+MODTCB-MODULE) ) ,H
;Store MSB of the address

Now the task is ready to run.
scheduler table.

LD

BC,MODTCB-MODULE+1

PUSH
POP
ADD
LD
LD
LD
RST

IX
HL
HL,BC
DE, HL
C,0
A,@ADTSK
28H

We now add the entry to the task

;Get offset into the
; module of the TCB word
;Get a copy of the base address
;Put base address here
;Now HL points at TCB address
;Put that value in DE
;Add this entry to task slot 0
;Add this task, to be run every 266.67 msec
;Call the @ADTSK svc

The main program has now done its work and can exit.

LD
LD
RST

HL,ADDED
A,@DSPLY
28H

; Point at a message saying what was done
;and print it
;Call the @DSPLY svc

LD
RST

A,@EXIT
28H

;Now exit
;Call the @EXIT svc

This SVC does not return.
This part of the code removes the task from the scheduler
tables and then attempts to recover the memory that was used

Software 179

Sample Program F, continued
by the task in high memory. If another high memory module
was added AFTER this task was added, then the memory that
was used by this task cannot be recovered.
KILLIT: LD
LD
RST

C,J3
A,@RMTSK
28H

;We want to remove the task in slot 0
;Call the §RMTSK svc

At this point, the task is no longer called by the Operating
system. Now we want to determine if we can
reclaim the memory it was using.
LD
LD
RST
JR

DE,MODNAM
A,@GTMOD
28H
NZ,CAMT

LD
LD
LD

IX,HL
B,0
HL,0

LD
RST
INC
PUSH
POP
XOR
SBC
JR

A,@HIGH$
28H
HL
IX
DE
A
HL, DE
NZ,CANT

;Point at the name of the module
;Look for a module with that name
;Call the @GTMOD svc
;If NZ is set, then we killed some other
;task that was using slot 0. Oops.
r In that case, just stop and don't do any
;more damage.
rSet IX to point to the module.
;Read the current value of HIGH$
?to see if this is the first program in
;high memory
?If it is, then we can recover the space
;Call the @HIGH$ svc
;Move HIGH$ up by one byte
;Take the address of our module
rand störe it here
rCompare these
rAre they the same?
rNo, the high memory module can't be removed

At this point, we know it is ok to reclaim the memory used by the
high memory task.
LD

HL,(IX+2)

LD
LD
RST

B,J2f
A,@HIGH$
28H

LD
LD
RST

HL, OK
A,@DSPLY
28H

;Point to a message saying all is well
;and print it
;Call the @DSPLY svc

LD
RST

A,@EXIT
28H

;Exit the main program
;Call the @EXIT svc

;Read the end of module value out of the
;header Information
;Update the HIGH$ value
;Call the @HIGH$ svc

Here we will display a message saying we removed the task from
the scheduler table, but we cannot reclaim the memory that was
used.
CANT

LD
LD
RST

HL,RECLM
A,@DSPLY
28H

;Point to the message
;and display it
;Call the @DSPLY svc

LD
RST

A,@EXIT
28H

;Now exit
;Call the @EXIT svc

;

Messages

ADDED:

DEFM
DEFB
DEFM

'Task placed in high memory and scheduled.1
0DH
'Task removed from scheduler table and memory reclaimed.1

DEFB

J3DH

DEFM

'Task removed from scheduler table, but memory could not '

OK:
RECLM:

Software 180

^^^X

Sample Program F, continued
00204
00205
00206
00207
00208
00209
00210
00211
00212
00213
00214
00215
00216
00211
0021B
00219
00220
00221
00222
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254
00255
00256
00257
00258
00259
00260
00261
00262

DEFM
DEFB

'be recovered.
0DH

The Task begins at this point. This part of the program loads
in low memory but is relocated to a point just below HIGH$.
This is the Memory Header Block. This block of data allows
the System to locate this module in memory by name,
using the @GTMOD svc.
MODULE: JR
ENDADD: DEFW

ENTRY
0

DEFB
MODNAM: DEFM

MODTCB-MODNAM
•UPTIME'

MODTCB: DEFW
DEFW

;Jump (relative) to the starting address
?The highest address in the program.
;This value is patched in before the program
;is relocated. This will be used
;later in recovering the memory used by
?this task.
fNumber of bytes in the name field below.
?This is the name of the module and is
rused to identify the module.
;Actual address to Start execution. This
;value is patched in after the program is
: relocated.
;Spare System pointer - RESERVED

This area contains data used by the task. It is addressed using
the IX register which points to the task when it is executed.
COUNTERrDEFW
DATBUF: DEFS

;Count of how many times we have run
;The date is stored here

This is the actual task.
On entry to the task, IX points at the Task Control Block (TCB),
which in this program is the label 'MODTCB1. All data is
referenced by indexing from that address.
ENTRY:

PUSH

;Save this register. It is not saved by
;the Task Scheduler, and we use it.
;Registers AF, BC, DE, and HL are saved

IY

Now we will read the current date.
LD
LD
ADD

HL, IX
;Get a copy of the index pointer
BC,DATBUF-MODT
BC,DATBUF-MODTCB;Get
the offset needed to access the date
HL,BC
;Now we have a pointer to the date

PUSH
PUSH

IX
HL

LD
RST

A,@DATE
28H

;Save the pointer to the start of the task
;Save a copy of that pointer
;Ask the system what the date is
;Call the @DATE svc

LD

(HL) ,0

;Terminate the date string

POP

PUSH

DE
DE

LD

HL,0028H

CALLR
PUSH
PUSH
PUSH

WRITE

LD
RST
LD

A,@WHERE

;Put pointer to the date here
;We will use this pointer later on
;Put the Cursor on the top line,
;specified in register HL
;at the 41st position on the screen
;Write the message at the position
;Save the registers we damage
;Save it
;Save it
;Get our current address
;Call the @WHERE svc
;Get the lengths of the instructions after
;the SVC. This will allow the subroutine
;to return to the correct address.

HL
BC
AF

28H

BC, 3+1+1+1+1+2

Software 181

Sample Program F, continued
ADD
POP
POP
EX
JR

;Add that offset to where we are
;Put Stack back
;Restore registers
;Put return address on Stack and restore HL
;Jump to the subroutine
;Note that the above was actually a macro
;which performs a relative call.

HL,BC
AF
BC
(SP),HL
WRITE

This part of the task displays a count of the number of times
the task has been executed.

LD
ADD
LD
LD
LD
INC
LD
LD

;Get the pointer to DATBUF back
;Get the pointer to the beginning of
;this task
DE
;Save the pointer to DATBUF again
BC,COUNTER-MODTCB
;Get the offset to our data
;area
HL,IX
;Put a copy of the base address in HL
HL,BC
;Add offset. Now HL points to COUNTER:
IY,HL
;Put the pointer to COUNTER in IY
Lf(IY)
;Get LSB of the counter
H,(IY+1)
;Get MSB of the counter
HL
;Increment the number of times we have run
(IY),L
;Store the LSB of the counter
(IY+1),H
;Store the MSB of the counter

LD
RS T

A,@HEXDEC
28H

;Convert the count to decimal
;Call the ÖHEXDEC svc

XOR
LD

A
(DE),A

;Get a zero
;Terminate the count string

POP
LD

DE
HL,J8036H

CALLR
PUSH
PUSH
PUSH
LD
RST
LD

WRITE
HL
BC
AF
A,@WHERE
28H
BC,3+1+1+1+1+2

ADD
POP
POP
EX
JR

HL,BC
AF
BC
(SP),HL
WRITE

;Put pointer to date here
;Put the Cursor on the top line,
;specified in register HL
;at the 55th position on the screen
;Write the message at the position
;Save the registers we damage
;Save it
;Save it
;Get our current address
;Call the @WHERE svc
;Get the lengths of the instructions after
;the SVC. This will allow the subroutine
;to return to the correct address.
;Add that offset to where we are
;Put Stack back
;Restore registers
;Put return address on stack and restore HL
;Jump to the subroutine
;Note that the above was actually a macro
;which performs a relative call.

POP
POP

PUSH
LD

DE
IX

Now we restore the IY register and return to the task scheduler.
POP
RET

IY

;Restore IY value
;Return to the task scheduler

This routine places characters on the display using the @VDCTL
svc instead of @DSP or @DSPLY. This allows the cursor to
remain at its current position when we write to the screen.
This routine must be called using the relocatable call macro
CALLR.
WRITE:

LD

B,2

;Put Character on the display

TSKLP

LD

A, (DE)

;Get a Character to display

Software 182

Sample Program F, continued

9

00313
00314
00315
00316
00317
00318
00319
00320
00321
00322
00323
00324
00325
00326
00327
00328
00329

;Is it time to stop putting this on
;the display?
;Yes, return to the caller
;Save the registers, äs the SVC will
;alter the contents

OR

A

RET
PUSH
PUSH
PUSH
LD
LD
RST
POP
POP
POP
INC
INC
JR

Z
HL
DE
BC
C,A
A,@VDCTL
28H
BC
DE
HL
L
DE
TSKLP

;Put the Character here
;Put Character on screen at specified position
;Call the @VDCTL svc
;Restore registers

BEGIN

;End of task and main program

MODEND: END

;Advance display position
;Point to next Character to display
;Loop till date is completely displayed

Software 183

Sample Program G
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068

This program is a sample Extended Command Interpreter. You
may make the ECI äs large or small äs you require. You may
use allof main memory, or you can restrict yourself to the
System Overlay area (x'26001 to x'2FFF').
To pass a command to the normal System Interpreter for
processing, use the @CMNDI svc. TRSDOS executes the command
and reloads the ECI. If you want to have multiple entry
points, Bits 2 - 0 in EFLAG$ are in Register A on entry
(in Bits 6 - 4),or you may read EFLAG$ yourself.
EFLAG$ is totally dedicated to the ECI, and may contain any
non-zero value. If EFLAGS contains a zero, TRSDOS uses its
own Interpreter. Other programs that want to activate an ECI,
should set the EFLAG$ to a non-zero value and execute a @EXIT
svc.
To install an ECI, use the command:
COPY filename SYS13/SYS.LSIDOS:d (C=N)
If you omit the C=N Option, the SYS13 file loses it's "SYS"
Status and you will receive 'Error 07' messages when you try
to use it äs a ECI.
When SYS1 (the normal command interpreter) has completed it's
normal housekeeping and is about to display the "TRSDOS Ready"
prompt, it checks EFLAG$. If EFLAG$ contains a non-zero
value, TRSDOS loads and executes the Extended Command
Interpreter.
To execute this program, type <*>.
This program checks EFLAG$ to see if it is zero. If so, it
sets it to a non-zero value. This causes this program to be
used instead of the normal interpreter when you execute an
@EXIT or @ABORT SVC. (@CMNDI and @CMNDR invoke the TRSDOS
interpreter.) If EFLAG$ is non-zero, the ECI displays a few
prompts and the names of all visible /CMD files on logical
Drive 0.
The operator may then type the name of a program to execute.
If you press , this program sets EFLAG$ to 0, executes
an @EXIT SVC and returns to TRSDOS Ready.
By pressing a number, 0 through 7, you can specify the drive
that TRSDOS searches. This program stores this value in
EFLAG$. Each time this program is invoked, it reads the value
from EFLAG$ and uses that drive.
Note that if a drive is not enabled, not formatted, doesn't
exist, or contains no visible /CMD files, this program
redisplays the prompt.

;
;
;
@EXIT:
@DSPLY:
@FLAGS:
8DODIR:
@KEYIN:
@CMNDI:

PRINT

SHORT,NOMAC

PSECT

3000H

Declare
This is
follow.
EQU
EQU
EQU
EQU
EQU
EQU

the equates for the SVCs used.
not mandatory, but it makes the program easier to
22
10
101
34
9
24

;This program Starts at x'3000'

;Exit and return to TRSDOS
;Display a string
;Locate the System flag area
;Get the names of filenames
;Accept a command and allow editing
;Execute a command (using SYS1)

On entry, determine if EFLAG$ is set to zero or not. If it
is set to zero, this program is being started by typing
PROGRAM or <*>. In that case, set EFLAG$ to a
non-zero value so that in future, TRSDOS uses this interpreter
instead of it's own.

Software 184

c

Sample Program G, continued
00069
00070
00071
00072
area
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136

If EFLAG$ is non-zero, this initialization has already been
done and can be skipped.
BEGIN:

;
;

LD

A,@FLAGS

;Get the startinq address of the flag

RST

28H

;Call the @FLAGS svc

LD
OR
JR

A,(IY+4)
A
NZ,ECIRÜN

;Read the EFLAG$ (ECI flag)
;Is it set to zero?
;Run the ECI

LD

A,8

LD
LD
JR

(IY+4),A
HL,PROMPT
ECIGO

;Get a non-zero value. The value
;needs to be a non-zero value that
;does not set Bits 0, l or 2. The
;default drive # is kept in these bits
;Set the EFLAG$ to a non-zero value
;Explain how this works
;Display message

When the system is about to display
TRSDOS Ready, it executes this code instead.

ECIRÜN: LD
ECIGO: LD
RST
;

HL,SPROMPT
A,@DSPLY
28H

;Point at the prompt to use
;Display the prompt
;Call the @DSPLY svc

Display the names of all /CMD files
LD
AND
LD
LD
LD
LD
RST

A,(IY+4)
7
C/A
A,@DODIR
B,2
HL,CMDTXT
28H

;Get the EFLAG$
;Delete all but the drive number field
;Store the drive number for the svc
;Do a directory display
;Display visible, non-system files
;that match "CMD" (stored at CMDTXT)
;Call the @DODIR svc

;

Prompt for a filename or a function key.

ASK:

LD
LD
LD
LD
RST

HL,BUFFER
B,9
C,0
A,@KEYIN
28H

;Point at text buffer
;Allow up to 8 characters and 
;Required by the svc
;Input text with edit capability
;Call the @KEYIN svc

JR

C,QUIT

;The carry flag is set when the
;operator presses . Zero the
;EFLAG$ and exit to TRSDOS

LD
LD

HL,BUFFER
A,(HL)

;Point at the start of the buffer
;Get the Character

CP
JR

0DH
Z,ASK

;Did they type anything?
;No, just repeat the prompt.
;If you want to redisplay the
;directory, change "ASK" to "ECIRÜN".

SUB
CP
JR

'01
7+1
NC,NAME

;Convert value to binary
;Is the Character a 0 - 7?
;Must be a filename

The operator has typed l or more characters that start with
a number. This program assumes that the operator is defining
a new drive number and stores this value in EFLAG$ for
future use. TRSDOS does not alter this value.
The next time this program is run, EFLAGS contains the
same value and this program knows what drive to scan.
LD
LD

B,A
A, (IY+4)

;Save the drive number
;Get the EFLAG$

Software 185

Sample Program G, continued
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
EFLAG$
00165
00166
00167
00168
00169
00170
00171
00172
00173
00174
00175
00176
00177
00178
00179
00179
00180
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191

AND
OR
LD
JR

QUIT:

;Delete the old drive number
;Insert the new drive number
;Save that value for future use
;Scan the new drive

The operator pressed . Turn off the ECI and return to
TRSDOS.
XOR
A
;Get a zero
LD
(IY+4),A
;Set EFLAG$ to zero
LD
HL,EPROMPT
;Point at the shutdown message
LD
A,@DSPLY
;And acknowledqe the 
RST
28H
;Call the @DSPLY svc
LD
A,@EXIT
;Return to TRSDOS Ready
RST
28H
;Call the @EXIT svc
The operator entered what might be a filename or a library
command. Pass it to TRSDOS for processing.
If there is an
error, TRSDOS is responsible for determining what the error is
and printing a message.
(HL already points at the start of the buffer.)

NAME:
FDIV,

LD
CP
JR
INC
JR

A,0DH
(HL)
Z,FOUND
HL
FDIV

;Look for this Character
;In the command
;Found the end of the filename
;Move Character to next byte
;Find the divider (in this case, a 0DH)

Found the end of a filename, and add the drive number from
Note that this program may not work properly if the operator
supplies a drive number äs part of the filename.
FOUND:

LD
INC
LD
AND
ADD
LD
INC
LD
LD
LD

(HL),':'
HL
A,(IY+4)
7
A,'01
(HL),A
HL
(HL),0DH
HL,BUFFER
A,@CMNDI

RST

28H

;Add a drive number to the filename
;Advance the pointer to the next byte
;Get the EFLAG$ value
;Delete all but the drive number
;Convert the binary value to ASCII
;Add that to the filename
;Advance the pointer to the next byte
;Write a terminator on the end
;Point at the text entered
;Execute the command, but do not
;return. Since this program is the
command processor at this time,TRSDOS
;returns control to the beginning of
;this module after executing the
;command.
;Call the @CMNDI svc

Messages and text storage
PROMPT: DEFM
DEFB
DEFB
DEFM
DEFB
DEFM

00192
00193

DEFB
DEFM

00194
00195
00196
00197

DEFB

00198
00199
00200

8
B
(IY+4),A
ECIRUN

SPROMPT:DEFB
DEFM
DEFM
DEFB

1

[Extended Command Interpreter Is Now Operational]'
0AH
0AH
'Press  to use the normal Interpreter,
0AH
'type  to change the default drive
number,'
0AH
'or type the name of the program to run and press
'
0DH
;Terminate the display

0AH
'[ECI On]  to abort, n for new drive or
type:'
1
program'
0DH
;Terminate the message

Software 186

^^RraB^,

Sample Program G, continued
00201
00202
00203
00204
00205
00206
00207

EPROMPT:DEFM
DEFB

'[Extended Command Interpreter Is Now Disabled]'
0DH

CMDTXT: DEFM
BUFFER: DEFS

'CMD1
11

;Allow for filename, drivespec and 0DH

BEGIN

;"BEGINn is the starting address

END

P

Software 187

leuiiinucii IMIUMIICUIUII un i

Commands and Utilities
TRSDOS commands and Utilities are covered extensively in the Disk System
Owner's Manual. This section presents additional information of a technical
nature on several of the commands and Utilities.

Changing the Step Rate
The step rate is the rate at which the drive head moves from cylinder to cylinder.
You can change the step rate for any drive by using one of the commands
described below.
To set the step rate for a particular drive, use the following command:
SYSTEM (DRIVE = dr/Ve, STEP = number)
drive is any drive enabled in the System, number can be 0, 1, 2, or 3 and represents one of the following step rates in milliseconds:
0= 6 milliseconds
1=12 milliseconds
2 = 20 milliseconds
3 = 30 milliseconds
Unless it is SYSGENed, the step value you Select remains in effect for the specified drive only until the System is re-booted or turned off. If you use the
SYSGEN command while the step value is in effect, then this step rate is Written
to the configuration file (CONFIG/SYS) on the disk in the drive specified by the
SYSGEN command.
On a new TRSDOS disk, the step rate is set to 12 milliseconds.
To set the default bootstrap step rate used with the FORMAT Utility, use the following command:
SYSTEM (BSTEP=number)
number is 0, 1, 2, or 3, which correspond to 6, 12, 20, and 30 milliseconds,
respectively.
The value you Select for number is stored in the System information sector on
the disk in Drive 0. (On a new TRSDOS disk, the bootstrap step rate is set to 12
milliseconds.)
If you switch Drive 0 disks or change the logical Drive 0 with the SYSTEM
(SYSTEM) command, the default value is taken off the new Drive 0 disk if you
format a disk.
You can change the bootstrap step rate for a particular FORMAT Operation if
you do not want to use the default. Specify the new value for STEP on the
FORMAT command line äs follows:
FORMAT :drive (STEP=number)
drive is the drive to be used for the FORMAT, number is 0,1, 2, or 3, which correspond to 6,12,20, and 30 milliseconds, respectively.
The step rate is important only if you will be using the disk in Drive 0 to Start up
the System. Keep in mind that too Iow a step rate may keep the disk from
booting.

Software 189

Changing the WAIT Value
The WAIT parameter compensates for hardware incompatibility between certain disk drives. The only time you should use it is when all tracks above a certain point during a FORMAT Operation are shown äs locked out when the
FORMAT is verified.
The value assigned to WAIT signifies the amount of time between the arrival of
the drive head at the location for a read or write, and the actual Start of the read
or write.
If you want to change the WAIT value, specify the new value on the FORMAT
command line äs follows:
FORMAT :drive (WAIT = number)
number is a value between 5000 and 50000. The exact value depends on the
particular disk drive you are using. We recommend that you use a value around
25000 at first. Adjust this value higher if tracks are still locked out, or Iower until
the bottom limit is determined.

Logging in a Diskette
LOG is a Utility program that logs in the directory track, number of sides, and
density of a diskette. The syntax is:
LOG :drive
drive is any drive currently enabled in the System.
The LOG Utility provides a way to log in diskette Information and Update the
drive's Drive Code Table (DCT). It performs the same log-in function äs the
DEVICE library command, except for a single drive rather than all drives. It also
provides a way to swap the Drive 0 diskette for a double-sided diskette.
The LOG :0 command prompts you to switch the Drive 0 diskette. You must use
this command when switching between double- and single-sided diskettes in
Drive 0. Otherwise, it is not needed.
Example

c

If you want to switch disks in Drive 0, type:
LOG :0

(ENTER)

The System prompts you with the message:
E x c h a n g e d i s K s a n d h i t 
Remove the current disk from Drive 0 and insert the new System disk. When
you press (ENTER), information about the new disk is entered to the System.

Printing Graphics Characters
If your printer is capable of directly reproducing the TRS-80 graphics characters, you can use the SYSTEM (GRAPHIC) command. Once you have issued
this command, any graphics characters on the screen will be sent to the line
printer during a screen print. (Pressing (ÜTfiDCD causes the contents of the
video display to be printed on the printer.)
Do not use this command unless your printer is capable of directly reproducing
the TRS-80 graphics characters.
jj^i^^

Software 190

Changing the Clock Rate
The System normally runs at the fast Clock rate of 4 megahertz.
A slow mode of 2 megahertz is available, and may be necessary for real timedependent programs. (This slow rate is the same äs the Model III Clock rate.)
To switch to the slow rate, enter the following command:
SYSTEM (SLOW)
To switch back to the fast rate, enter:
SYSTEM (FAST)

\^jjjr

Software 191

Appendix A/TRSDOS Error Messages
If the Computer displays one of the messages listed in this appendix, an Operating System error occurred. Any other error message may refer to an application program error, and you should check your application program manual for
an explanation.
When an error message is displayed:
• Try the Operation several times.
• Look up Operating System errors below and take any recommended
actions. (See your application program manual for explanations of application program errors.)
• Try using other diskettes.
• Reset the Computer and try the Operation again.
• Check all the power connections.
• Check all interconnections.
• Remove all diskettes from drives, turn off the Computer, wait 15 seconds,
and turn it on again.
• If you try all these remedies and still get an error message, contact a
Radio Shack Service Center.
Note: If there is more than one thing wrong, the Computer might wait until you
correct the first error before displaying the second error message.
This list of error messages is alphabetical, with the binary and hexadecimal
error numbers in parentheses. Following it is a quick reference list of the messages arranged in numerical order.
Attempted to read locked/deleted data record (Error 7, X'07')
In a System that Supports a "deleted record" data address mark, an attempt was
made to read a deleted sector. TRSDOS currently does not use the deleted
sector data address mark. Check for an error in your application program.
Attempted to read System data record (Error 6, X'06')
An attempt was made to read a directory cylinder sector without using the
directory read routines. Directory cylinder sectors are Written with a data
address mark that differs from the data sector's data address mark. Check for
an error in your application program.
Data record not found during read (Error 5, X'05')
The sector number for the read Operation is not on the cylinder being referenced. Either the disk is flawed, you requested an incorrect number, or the cylinder is improperly formatted. Try the Operation again. If it fails, use another
disk. Reformatting the old disk should lock out the flaw.
Data record not found during write (Error 13, X'OD')
The sector number requested for the write Operation cannot be found on the
cylinder being referenced. Either the disk is flawed, you requested an incorrect
number, or the cylinder is improperly formatted. Try the Operation again. If it
fails, use another disk.
Device in use (Error 39, X'27')
A request was made to REMOVE a device (delete it from the Device Control
Block tables) while it was in use. RESET the device in use before removing it.

Software 193

Device not available (Error 8, X'08')
A reference was made for a logical device that cannot be found in the Device
Control Block. Probably, your device specification was wrong or the device
peripheral was not ready. Use the DEVICE command to display all devices
available to the System.
Directory füll — can't extend file (Error 30, X'1 E')
A file has all extent fields of its last directory record in use and must find a spare
directory slot but none is available. (See the "Directory Records" section.) Copy
the disk's files to a newly formatted diskette to reduce file fragmentation. You
may use backup by class or backup reconstruct to reduce fragmentation.
Directory read error (Error 17, X'11')
A disk error occurred during a directory read. The problem may be media, hardware, or program failure. Move the disk to another drive and try the Operation
again.
Directory write error (Error 18, X'12')
A disk error occurred during a directory write to disk. The directory may no
longer be reliable. If the problem recurs, use a different diskette.
Disk space füll (Error 27, X'1B')
While a file was being Written, all available disk space was used. The disk contains only a partial copy of the file. Write the file to a diskette that has more available space. Then, REMOVE the partial copy to recover disk space.
End of file encountered (Error 28, X'1C')
You tried to read past the end of file pointer. Use the DIR command to check the
size of the file. This error also occurs when you use the @PEOF Supervisor call
to successfully position to the end of a file. Check for an error in your application
program.
Extended error (Error 63)
An error has occurred and the extended error code is in the HL register pair.
File access denied (Error 25, X'19')
You specified a password for a file that is not password protected or you specified the wrong password for a file that is password protected.
File already open (Error 41, X'29')
You tried to open a file for UPDATE level or higher, and the file already is open
with this access level or higher. This forces a change to READ access protection. Use the RESET library command to close the file.
File not in directory (Error 24, X'18')
The specified filespec cannot be found in the directory. Check the spelling of
the filespec.
File not open (Error 38, X'26')
You requested an I/O Operation on an unopened file. Open the file before
access.
GAT read error (Error 20, X'14')
A disk error occurred during the reading of the Granule Allocation Table. The
problem may be media, hardware, or program failure. Move the diskette to
another drive and try the Operation again.
GAT write error (Error 21, X'15')
A disk error occurred during the writing of the Granule Allocation Table. The
GAT may no longer be reliable. If the problem recurs, use a different drive or
different diskette.
Software 194

HIT read error (Error 22, X'16')
A disk error occurred during the reading of the Hash Index Table. The problem
may be media, hardware, or program failure. Move the diskette to another drive
and try the Operation again.
HIT write error (Error 23, X'17')
A disk error occurred during the writing of the Hash Index Table. The HIT may
no longer be reliable. If the problem recurs, use a different drive or different
diskette.
Illegal access attempted to protected f ile (Error 37, X'25')
The USER password was given for access to a file, but the requested access
required the OWNER password. (See the ATTRIB library command in your
Disk System Owner's Manual.)
Illegal drive number (Error 32, X'20')
The specified disk drive is not included in your System or is not ready for access
(no diskette, non-TRSDOS diskette, drive door open, and so on). See the
DEVICE command in your Disk System Owner's Manual.)
Illegal file name (Error 19, X'13')
The specified filespec does not meet TRSDOS filespec requirements. See your
Disk System Owner's Manual for proper filespec syntax.
Illegal logical file number (Error 16, X'10')
A bad Directory Entry Code (DEC) was found in the File Control Block (FCB).
This usually indicates that your program has altered the FCB improperly. Check
for an error in your application program.
Load file format error (Error 34, X'22')
An attempt was made to load a file that cannot be loaded by the System loader.
The file was probably a data file or a BASIC program file.
Lost data during read (Error 3, X'03')
During a sector read, the CPU did not accept a byte from the Floppy Disk Controller (FDC) data register in the time allotted. The byte was lost. This may indicate a hardware problem with the drive. Move the diskette to another drive and
try again. If the error recurs, try another diskette.
Lost data during write (Error 11, X'OB')
During a sector write, the CPU did not transfer a byte to the Floppy Disk Controller (FDC) in the time allotted. The byte was lost; it was not transferred to the
disk. This may indicate a hardware problem with the drive. Move the diskette to
another drive and try again. If the error recurs, try another diskette.
LRL open fault (Error 42, X'2A')
The logical record length specified when the file was opened is different than
the LRL used when the file was created. COPY the file ta another file that has
the specified LRL.
No device space available (Error 33, X'2T)
You tried to SET a driver or filter and all of the Device Control Blocks were in
use. Use the DEVICE command to see if any non-system devices can be
removed to provide more space. This error also occurs on a "global" request to
initialize a new file (that is, no drive was specified), if no file can be created.
No directory space available (Error 26, X'1 A')
You tried to open a new file and no space was left in the directory. Use a different disk or REMOVE some files that you no longer need.

Software 195

No error (Error 0)
The @ERROR Supervisor call was called without any error condition being
detected. A return code of zero indicates no error. Check for an error in your
application program.
Parameter error (Error 44,X'2C')
(Under Version 6.2 only) An error occurred while executing a command line or
Utility because a parameter that does not exist was specified. Check the spelling of the parameter name, value, or abbreviation.
Parity error during header read (Error 1, X'QV)
During a sector I/O request, the System could not read the sector header successfully. If this error occurs repeatedly, the problem is probably media or hardware failure. Try the Operation again, using a different drive or diskette.
Parity error during header write (Error 9, X'09')
During a sector write, the System could not write the sector header satisfactorily. If this error occurs repeatedly, the problem is probably media or hardware
failure. Try the Operation again, using a different drive or diskette.
Parity error during read (Error 4, X'04')
An error occurred during a sector read. Its probable cause is media failure or a
dirty or faulty disk drive. Try the Operation again, using a different drive or
diskette.
Parity error during write (Error 12, X'OC')
An error occurred during a sector write Operation. Its probable cause is media
failure or a dirty or faulty disk drive. Try the Operation again, using a different
drive or diskette.
Program not found (Error 31, X'1F')
The file cannot be loaded because it is not in the directory. Either the filespec
was misspelled or the disk that contains the file was not loaded.
Protected System device (Error 40, X'28')
You cannot REMOVE any of the following devices: *KI, *DO, *PR, *JL, *SI, *SO.
If you try, you get this error message.
Record number out of ränge (Error 29, X'1D')
A request to read a record within a random access file (see the @POSN Supervisor call) provided a record number that was beyond the end of the file. Correct
the record number or try again using another copy of the file.
Seek error during read (Error 2, X'02')
During a read sector disk I/O request, the cylinder that should contain the sector was not found within the time allotted. (The time is set by the step rate specified in the Drive Code Table.) Either the cylinder is not formatted or it is no
longer readable, or the step rate is too Iow for the hardware to respond. You can
set an appropriate step rate using the SYSTEM library command. The problem
may also be caused by media or hardware failure. In this case, try the Operation
again, using a different drive or diskette.
Seek error during write (Error 10, X'OA')
During a sector write, the cylinder that should contain the sector was not found
within the time allotted. (The time is set by the step rate specified in the Drive
Code Table.) Either the cylinder is not formatted or it is no longer readable, or
the step rate is too Iow for the hardware to respond. You can set an appropriate
step rate using the SYSTEM library command. The problem may also be
caused by media or hardware failure. In this case, try the Operation again, using
a different drive or diskette.

Software 196

^^^^^

— Unknown error code
The @ERROR Supervisor call was called with an error number that is not
defined. Check for an error in your application program.
Write fault on disk drive (Error 14, X'OE')
An error occurred during a write Operation. This probably indicates a hardware
problem. Try a different diskette or drive. If the problem continues, contact a
Radio Shack Service Center.

P

Write protected disk (Error 15, X'OF)
You tried to write to a drive that has a write-protected diskette or is Software
write-protected. Remove the write-protect tab, if the diskette has one. If it does
not, use the DEVICE command to see if the drive is set äs write protected. If it
is, you can use the SYSTEM library command with the (WP = OFF) parameter
to write enable the drive. If the problem recurs, use a different drive or different
diskette.

Numerical List of Error Messages
Decimal

Hex

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
37
38
39
40

X'00'
X'01'
X'02'
X'03'
X'04'
X'05'
X'06'
X'07'
X'08'
X'09'
X'0A'
X'0B'
X'0C'
X'0D'
X'0E'
X'0F'
X'10'
X'11'
X'12'
X'13'
X'14'
X'15'
X'16'
X'17'
X'18'
X'19'
X'1A'
X'1B'
X'1C'
X'1D'
X'1E'
X'1F'
X'20'
X'21'
X'22'
X'25'
X'26'
X'27'
X'28'

Message
No Error
Parity error during header read
Seek error during read
Lost data during read
Parity error during read
Data record not found during read
Attempted to read System data record
Attempted to read locked/deleted data record
Device not available
Parity error during header write
Seek error during write
Lost data during write
Parity error during write
Data record not found during write
Write fault on disk drive
Write protected disk
Illegal logical file number
Directory read error
Directory write error
Illegal file name
GAT read error
GAT write error
HIT read error
HIT write error
File not in directory
File access denied
No directory space available
Disk space füll
End of file encountered
Record number out of ränge
Directory füll—can't extend file
Program not found
Illegal drive number
No device space available
Load file format error
Illegal access attempted to protected file
File not open
Device in use
Protected System device

Software 197

41
42
43
44
63
—

X'29'
X'2A'
X'2B'
X'2C'
X'3F'

File already open
LRL open fault
SVC parameter error
Parameter error
Extended error
Unknown error code

Software 198

Appendix B/Memory Map
Resident Operating System, System
buffers, overlays, drivers, etc.

9

'2400H
I2600H:
3000H

Library Overlay zone

Note: 2400H to 2600H is
reserved for possible future
expansion of the resident
Operating System area.
OPTIONAL
/
64K MEMORY

32K

BANK1
BANK 2

SYSTEM BANK
BANK0

64K

32K

64K

HIGH$

All Software must observe HIGH$.
User Software which does not allow TRSDOS library commands to be executed
during run time may use memory from 2600H to HIGH$.
User Software which allows for library commands during execution must reside
in and use memory only between 3000H and HIGH$.
TRSDOS provides all functions and storage through Supervisor calls. No
address or entry point below 3000H is documented by Radio Shack.

Software 199

€

Appendix C/Character Codes
Text, control functions, and graphics are represented in the Computer by codes.
The Character codes ränge from zero through 255.

i

Codes one through 31 normally represent certain control functions. For example, code 13 represents a carriage return or "end of line." These same codes
also represent special characters. To display the special Character that corresponds to a particular code (1-31), precede the code with a code zero.
Codes 32 through 127 represent the text characters — all those letters, numbers, and other characters that are commonly used to represent textual
information.
Codes 128 through 191, when Output to the Video display, represent 64 graphics
characters.
Codes 192 through 255, when Output to the video display, represent either
space compression codes or special characters, äs determined by Software.

Software 201

ASCII Character Set
Code
Dec. Hex.

ASCII
Abbrev.

Keyboard

0

00

NUL

(ÜTRDGD

1
2
3
4
5
6
7
8

01
02
03
04
05
06
07
08

SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS

035D®
(ÜTRDfg)
(ÜTRD©
(HED®

9

09

HT

10

0A

LF

11

0B

VT

12
13

0C
0D

FF
CR

(ÜTRDd)
(ÜTRDfF)
(ÜTRDfg)
©
(ÜTRDffl)

CE
(ÜTfiDd)
©
(ÜTEDGD
©

Video Display
Treat next Character äs displayable; if in the ränge 1-31,
a special Character is displayed (see list of special
characters later in this
Appendix).

Backspace and erase

Move Cursor to Start of next
line

(CTflDfK)

(ÜTRDfD
CENTER)

(ÜTRDflfi

Move Cursor to start of next
line
Turn Cursor on
Turn Cursor off
Enable reverse video and
set high bit routine on*
Set reverse video high bit
routine off*

14
15
16

0E
0F
10

SO
Sl
OLE

(HBD®
(ÜTED©
(ÜTRD©

17

11

DC1

(ÜTRD®

18
19
20
21

12
13
14
15

DC2
DC3
DC4
NAK

(ÜTRD®
(ÜTRD®
(ÜTRpm
(ÜTRD©

22

16

SYN

(üffiD®

23
24

17
18

ETB
CAM

(ÜTRD®
(SHIFDtD

25

19

EM

(SHIFDtT)
(ÜTRPm

Advance Cursor

26

1A

SUB

Move Cursor down

27

1B

ESC

(SHIFT)©
(ÜTRDd)
(SHIFTM
(ÜTRDGD

28

1C

FS

29

1D

GS

30

1E

RS

Swap space compression/
special characters
Swap special/alternate
characters
Set to 40 characters per line
Backspace without erasing

(ÜTRDffi

(CTRD(ENTER)

Move Cursor up
Move Cursor to upper left
corner. Disable reverse
video and set high bit routine off.* Set to 80 characters per line.
Erase line and Start over

(ÜTROfTl
Erase to end of line

"When the high bit routine is on, characters 128 through 191 are displayed äs
Standard ASCII characters in reverse video.

Software 202

Code

Dec.

Hex.

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59

ASCII
Abbrev.
VS
SPA

Video Display

Keyboard
tSHIFTXCLEAR)
(SPACEBAR)

CD
CD
®
©
©
©
CD
CD
CD
©
©
CD
Q
CD
CD
®
(D
®
®
S)
®
®
(Z)
®
®
CD
CD
©
©
(E)
®
(D
(SHlFDffl
CSHIFDCB)
(SHIFTKO
(SHIFT)®)
(SHlFDfE)
(SHIFTKF)
(SH1FD(E)
(USD®

cänrnci)

(SHIFTIQ)
(MED®
(SHIFPfD
(SRlFnOD

(MH)®
(SHIFTKÜ)
(SHIFTKF)
(SHlFnOK
(SHIFnCR)
(SHlFn(S)

(SHirnm
(SHlFDaJ)
(SHIFD^V)

(SBiFnd)

(SHIFDOT)
(SHIFD(Y)

Software 203

Erase to end of display
(blank)

#
$
%
&

A
B
C
D
E
F
G
H
l
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y

Code
Dec. Hex.

ASCII
Abbrev.

Keyboard

Video Display

90

5A

(SHIFTKD

Z

91
92
93
94
95

5B
5C
5D
5E
5F

(CLEÄRlfD
(ÜLEÄR)CD
(CLEÄRlfT)
(CLEÄRICD
CCLEÄRICENTER)

[
\
]

96

60

CSHIFD@

97
98

61
62

®
®

—

a
b

99

63

ÖD

c

100

101

64

65

®

d

102

66

®

f

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123

67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B

©
®
(D
(D
®
(D
®
(D
(B)
©
(SD
®
®
(D
(H)
®
®
®
®
(|)
(ÜLEÄffiCSHIFDGD

g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
{

124
125
126
127

7C
7D
7E
7F

(CLEÄR)(SHIFDm
CCLEÄR)(SHIFDrT)
CCLEÄRlfSHIFDCD
CCLEÄR)(SHIFDCENTERl

|
}

(E)

DEL

Software 204

e

±

Extended (non-ASCII) Character Set
Code
Dec. Hex.

_

128

80

(BREÄK1

129

81

(M)

130

82

(g)

83

(CLEÄRXCTRDfg)

Keyboard

Video Display

(CLEÄR)(CTRD(Ä)

131
132
133
134
135
136
137
138
139
140
141
142
143
144
145

84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91

146

92

147

93

148

94

m

(CLEÄR)(CTRD(Ü)
(CLEÄR)(ÜTRD(D)
(CLEÄR)(ÜTRD(D
(CLEÄR)(ÜTRD(F)
(CLEÄR)(ÜTRD(g)
(ÜLEÄR)(ÜTRD(ff)
(ÜLEÄR)(ÜTRD(D
(ÜLEÄR)(CTRD(D
CÜLEÄRXCTRIKIO
(CLEÄR)(CTRD(D
(CLEÄR)(CTRD(in
(CLEÄR)(CTRD(>n
(CLEÄR)(CTRD(ID
(ÜLEÄR)(CTRD(P)
(SHIFDgD
(ÜLEÄR)(ÜTRD(Q)
(SHIFTKFa
(ÜLEÄR)(ÜTRD(R)
(SHlFTldg)
(ÜLEÄR)(ÜTRD(S)
(CLEÄR)(ÜTRD(D

=ö
%
&
<
Z
c
o
-g
r
§
£5
^
£
^

149

95

(ÜLEÄR)(ÜTRD(D)

g-

150

96

(ÜLEÄR)(ÜTRD(\n

&>

151

97

CÜLEÄR)(ÜTRD(i)

g

152

98

(ÜLEÄR)(ÜTRDÖO

co

153

99

(ÜLE7TO(ÜTRD(Y)

154
155

9A
9B

(ÜLBffi)(ÜTRD(D
(ÜLEÄffiCSHiFDg)

156

9C

157
158

9D
9E

159

9F

160
161
162
163
164
165
166
167
168
169
170
171
172
173

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD

174
175
176

AE
AF
B0

177

B1

(ÜLEÄRim

178

B2

03HE)®

Software 205

^^
(CLEAR)ßPÄÜF)
(ÜLEÄR)(SHIFD(D
(CLESR)(SHlFT)g)
(ELBffiXSHlFnO)
fÜLEÄR)(SHim(41

(ÜLEÄR)(ggFD(7)
(ÜLEÄRlfSHIFD®
(ÜLE7TO(SHlFD(g)
(ÜLEÄRXSHIFDrn

_
(ÜLEÄffiFl

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(SEE)®

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c/> g
af
cr a>'

O

(D

0)

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l?
(D Q)

ro
o
cn
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l

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See list of special characters in this Appendix.

See graphics Character table in
this Appendix.

•

w
•

t>

O

Code
Dec. Hex.
235
EB
236
EC
237
ED
238
EE
239
EF
240
F0
241
F1
242
F2
243
F3
244
F4
245
F5
246
F6
247
F7
248
F8
249
F9
250
FA
253
FD
254
FE
FF
255

Keyboard
(CLEARlCSHIFniK)
(CLEÄR)(SHIFD(p
(ÜLEÄR)(SHIFT)(§)
(CLEÄR)(SHlFn(D
(CÜEÄRXSHIFD®
(CLEÄRlfSHIFTXP)
(CLEÄRKSHiFnO)
(CLEÄR)(SHIFD(R)
(CLEÄR1(SHIFT)(D
(CLEÄRKSHIFTXD
(CLEÄR)(SHIFT)(Ü)
(CLEÄR)(SHIFD(V)
(CLEÄRlfSHlFDg)
(CLEÄRl^HIFD®

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Appendix E/Programmable SVCs
(Under Version 6.2 only)
SVC numbers 124 through 127 are reserved for programmer installable SVCs.
To install an SVC the programmer must write the routine to execute when the
SVC is called.
The routine should be Written äs high memory module if it is to be available at
all times. If you execute a SYSGEN command when a Programmable SVC is
defined, the address of the routine is saved in the SYSGEN file and restored
each time the System is configured. If the routine is a high memory module, the
routine is saved and restored äs well. This makes the SVC always available.
For more information on high memory modules, see Memory Header and Sample Program F.
To install an SVC, the program must access the SVC table. The SVC table contains 128 two-byte positions, a two-byte position for each usable SVC. Each position in the table contains the address of the routine to execute when the SVC
is called.
To access the SVC table, execute the @FLAGS SVC (SVC 101). IY + 26 contains the MSB of the SVC table Start address. The LSB of the SVC table address is always 0 because the SVC table always begins on a page boundary.
Store the address of the routine to be executed at the SVC number times 2 byte
in the table. For example, if you are installing SVC 126, störe the address of the
routine at byte 252 in the table. Addresses are stored in LSB-MSB format.
When the SVC is executed, control is transferred to the address in the table. On
entry to your SVC, Register A contains the same value äs Register C. All other
registers retain the values they had when the RST 28 SVC instruction was
executed.
To exit the SVC, execute a RET instruction. The program should save and restore any registers used by the SVC.
Initially, SVCs 124 through 127 display an error message when they are executed. When installing an SVC you should save the original address at that location in the table and restore it when you remove the SVC.
These program lines insert a new SVC into the System SVC table, save the previous value of the table, and reinsert that value before execution ends. You
could check the existing value to see if the address is above X'2600'. If it is, the
SVC is already assigned and should not be used at this time.
This code inserts SVC 126, called MYSVC:
LD
RST
LD
LD
LD
LD
INC
LD
LD
DEC
LD

A,@FLAGS
28H
H,(IY + 26)
L, 126*2
(OSVC126A),HL
E,(HL)
HL
D,(HL)
(OSVC126V),DE
HL
DE,MYSVC

LD

(HL),E

INC

HL

Software 213

;Locate Start of SVC table
;Execute (aFLAGS SVC
;Get MSB of address
;Want to use SVC 126
;Save address of SVC entry
;Get current SVC address
;Save the old value
;Get address of routine for
;SVC126
;lnsert new SVC address into
;table

LD

(HL),D

. Code that uses MYSVC (SVC 126)

This code removes SVC 126:
LD
LD
LD
INC
LD

HL,(OSVC126A)
DE,(OSVC126V)
(HL),E
HL
(HL),D

Software 214

;Get address of SVC entry
;Get original value
;lnsert original SVC address

Appendix F/Using SYS13/SYS
(Under Version 6.2 only)
With TRSDOS Version 6.2, you can create an Extended Command Interpreter (ECI) or an Immediate Execution Program (IEP). TRSDOS can störe
either an ECI or IEP in the SYS13 file. Both programs cannot be present at
the same time.
At the TRSDOS Ready prompt when you type QD (ENTER). TRSDOS executes the program stored in SYS13/SYS. Because TRSDOS recognizes the
program äs a System file, TRSDOS includes the file when creating backups
and loads the program faster.
If you want to write additional commands for TRSDOS, you can write an Interpreter to execute these commands. Your ECI can also execute TRSDOS
commands by using the @CMNDI SVC to pass a command to the
TRSDOS Interpreter.
If EFLAG$ contains a non-zero value, TRSDOS executes the program in
SYS13/SYS. If EFLAG$ contains a zero, TRSDOS uses its own command
Interpreter.
Sample Program G is an example of an ECI. It is important to note that your ECI
must be executable by pressing © (ENTER) at the TRSDOS Ready prompt.
An ECI can use all of memory or you can restrict it to use the System Overlay
area (X'26001 to X'2FFF').
To implement an IEP or ECI, use the following syntax:
COPY filespec SYS13/SYS.LSIDOS:c/r/Ve (C = N) (ENTER)
filespec can be any executable (/CMD) program file. drive specifies the destination drive. The destination drive must contain an original SYS13/SYS file.
Example
COPY SCRIPSIT/CMD:1 SYS13/SYS.LDI:0 (C = N)
TRSDOS copies SCRIPSIT/CMD from Drive 1 to SYS13/SYS in Drive 0. At the
TRSDOS Ready prompt, when you press GD (ENTER). TRSDOS executes
SCRIPSIT.

Software 215

Index
Subject

Page Subject

@ABORT
48
Access
device
9-10
drive
11-21
file
4
@ADTSK
49
Alien disk Controller
12
Allocation
dynamic
3
Information
12, 25
methods of
3
pre3
unit of
2
ASCII codes
202-04
Background tasks, invoking
33-34
@BANK
37-39
Bank switching
36-39
@BKSP
52
BOOT/SYS
5
BREAK
detection
29-32, 53
key handling
211
©BREAK
53
Byte I/O
40-42
Characters
ASCII
202-04
codes
201 -10
graphics
205-06, 208
special
206-07, 209-10
@CHNIO
54
@CKDRV
55
@CKBRKC
55
@CKEOF
56
@CKTSK
57
Clock rate, changing
192
©CLOSE
60
@CLS
61
@CMNDI
63
@CMNDR
64
Codes
ASCII
202-04
Character
201 -10
error
197
graphics
205-06, 208
keyboard
211-12
return
28
special Character
206-07, 209-10
Converting to TRSDOS Version 6
27-28
CREATEdfiles
15
@CTL
40-42, 65-66

Page

interfacing to device drivers
Cylinder
highest numbered
number of
Position, current
starting
@DATE
@DCINIT
@DCRES
@DCSTAT
DEBUG
@DEBUG
@DECHEX
Density, double and single
Device
access
handling
NIL
Device Control Block (DCB)
Device driver
address
COM
@CTL interfacing to
keyboard
Printer
templates
video
Devspec
Directory
location on disk
primary and extended entries
record, locating a
records (DIREC)
sectors, number of
Directory Entry Code (DEC)
@DIRRD
DIR/SYS
@DIRWR
Disk, diskette
Controller
double-sided
files
floppy
formatting
hard
I/O table
minimum configuration
name

Software 217

42-44
12
18
12
25
67
68
69
70
6
71
72
1, 11, 18
9-10
27
9
9
7,8,13
9
43-44
42-44
43
43
40-42
43
9
2, 12
14
16,20
20
13-16
14
18-19
20, 24
73
5
74

12
11-12, 17, 18
13-14
1
17, 18
2
13
7-8
18

Index
Subject

Page

organization
1-2
single-sided
11-12, 17, 18
space, available
2
@DIV8
75
@DIV16
76
@DODIR
77-78
Drive
access
11 -22
address
12
floppy
1, 11
hard
2, 11
size
11
Drive Code Table DCT
11-13
Driver — see Device driver
@DSP
79
@DSPLY
80
End of File (EOF)
15
Ending Record Number (ERN)
16, 25
ENTER detection
29-32
Error
codes and messages
193-197
dictionary
6
©ERROR
81
@EXIT
82
Extended Command Interpreter
84, 215
@FEXT
83
File
access
4
descriptions, TRSDOS
5-8
modification
15
File Control Block (FCB)
23
Files
CREATEd
15
device driver
7
filter
7
System (/SYS)
5-6, 7-8, 19
Utility
7
Filter templates
40-42
Filters
7, 8, 40-42
example of
42
FLAGS
28, 84-86
@FNAME
87
@FSPEC
89
@GET
40-42, 90
Gran, granule
allocation information
25
definition
2, 17
per track
1-2, 12
Granule Allocation Table (GAT)
location on disk
2

Subject

Page

Contents of
16-18
Graphics
characters, printing
190
codes
205-06, 208
@GTDCB
91
@GTDCT
92
@GTMOD
93
Guidelines, programming
27-44
Hash code
15, 18
Hash Index Table (HIT)
location on disk
2
explanation of
18-19
@HDFMT
94
@HEXDEC
95
@HEX8
96
@HEX16
97
@HIGH$
98
@ICNFG, interfacing to
32-33
Immediate Execution Program
215
@INIT
99
Initialization configuration
vector
32-33
Interrupt tasks
34-36
@IPL
100
Job Control Language (JCL)
6, 28
@KBD
101
@KEY
102
Keyboard codes
211 -12
@KEYIN
103
KFLAG$
29
@KITSK, interfacing to
33-34
@KLTSK
104
Library commands
28
technical information on
189-91
@LOAD
105
@LOC
106
@LOF
107
LOG Utility
190
@LOGER
108
Logical Record Length (LRL)
15, 24
@LOGOT
109
Memory banks — see RAM banks
Memory header
10, 27
Memory map
199
Minimum configuration disk
7
Modification date
15
@MSG
110
@MUL8
111
@MUL16
112
Next Record Number (NRN)
24

Software 218

Index
Subject
NIL device
@OPEN
Overlays, System
@PARAM
Password
for TRSDOS files
protection levels
©PAUSE
PAUSE detection
@PEOF
@POSN
©PRINT
Printing Graphics Characters
Programming Guidelines ...
Protection Levels
@PRT
@PUT
RAM Banks
switching
use of
@RAMDIR
@RDHDR
@RDSEC
@RDSSC
@RDTRK
@READ
Record
length
logical and physical ...
numbers
processmg
spanning
@REMOV
@RENAM
Restart Vectors (RSTs)
Return Code (RC)
@REW
@RMTSK
@RPTSK
@RREAD
RS-232
initializing
COM driver for . . .
@RSLCT
@RSTOR
@RUN
@RWRIT
Sample Programs
A
B

Page
9
...113
5-6, 19
114-15

8
.... 14, 24
116
. . . . 29-32
117
118
119
190
. . . . 27-44
14, 24, 27
120
40-42, 121
36-39
50-51
.. 122
.. 123
.. 124
.. 125
.. 126
.. 127
3-4, 15, 24
3-4
4
4
3-4
128

129
29
28

130
131
132
133

. . . . 32
. 43-44
... 134
. . . 135
...136
. . . 137
160-83
... 161
... 163

Subject

Page

C
168
D
175
E
177
F
178
G
187
Sectors
per cylinder
14, 19
per granule
1-2, 12
@SEEK
138
@SEEKSC
139
@SKIP
140
@SLCT
141
@SOUND
142
Special Character Codes
206-07, 209-10
Stack handling
28
Step rate
11
changing
189
@STEPI
143
Supervisor calls (SVCs)
calling procedure
45
lists of
46-47, 155-57, 158-59
program entry and
return conditions
45
sample programs using
160-183
using
45-183
SYS files
5-6, 7-8, 19
System
files
5-6, 7-8, 19
overlays
5-6, 19
Task
Interrupt level, adding
49
slots
34, 35, 49
Task Control Block (TCB)
34, 35, 49
Vector Table (TCBVT)
34, 35
Task processor, interfacing to
34-36
@TIME
144
TRSDOS
converting to Version 6
27-28
error messages and codes
193-97
file descriptions
5-8
technical information on
commands and Utilities
189-91
TYPE code
23
@VDCTL
145-46
@VER
147
Version, Operating system
17
Visibility
14
@VRSEC
148
WAIT value, changing
190
@WEOF
149

Software 219

Index
Subject
@WHERE
@WRITE
Write Protect

Page
150
151
9

Subject
@WRSEC
@WRSSC
@WRTRK

Page
152
153
154

j^EeslSBSk

Software 220

Index
Subject

Page

Subject

i

Software 221

Page

o
RADIO SHACK, A DIVISION OF TANDY CORPORATION
U.S.A.: FORT WORTH, TEXAS 76102
CANADA: BARRIE, ONTARIO L4M 4W5
TANDY CORPORATION
AUSTRALIA

BELGIUM

U. K.

91 KURRAJONG AVENUE

PARC INDUSTRIE!.

BILSTON ROAD WEDNESBURY

MOUNT DRUITT, N.S.W. 2770

5140 NANINNE (NAMUR)

WEST MIDLANDS WS10 7JN

S-L/3-85

Printed in U.S.A.



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