Radio Shack Hardware Manual II Technical Reference 1980 Text

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TRS-80 MODEL II TECHNICAL REFERENCE MANUAL Catalog Number 26-4921 Radio /hack jy? A DIVISION OF TANDY CORPORATION One Tandy Center Fort Worth, Texas 76102 Reproduction or use, without express in any manner is prohibited. No patent liability is assumed with respect to the use of the information contained herein. All rights reserved. permission, of editorial or pictorial content, © A Copyright 1980, Radio Shack Division of Tandy Corporation Fort Worth, Texas 76102, Printed in the United States of America IMPORTANT NOTICE is written for owners of the TRS-80 Model II Microcomputer who have a thorough understanding of electronics and computer circuitry. It is not written to the beginner's level of This Technical Reference Manual comprehension. Radio Shack will not be liable for any damage caused, or alleged to be by the customer or any other person using this technical manual to repair, modify, or alter the TRS-80 Model II Computer in any manner. caused, Many parts of the computer electronics are very sensitive ana" can be easily damaged by improper servicing. We strongly suggest that for proper servicing, the computer be returned to Radio Shack. While this technical manual has been carefully prepared. Radio Shack will not be responsible for any errors or omissions and will not be liable for damages resulting from the use of information contained herein. Because of the sensitivity of computer equipment, and the potential problems which can result from improper servicing, the following limitations apply to services offered by Radio Shack: 1 any of the warranty seals on any Radio Shack computer products are broken. Radio Shack reserves the right to refuse to service the equipment or to void any remaining warranty on the equipment. 2. If If any Radio Shack computer equipment has been modified so that it is not within manufacturer's specifications, including, but not limited to, the installation of any non- Radio Shack parts, components, or replacement boards, then Radio Shack reserves the right to refuse to service the equipment, void any remaining warranty, remove and replace any non- Radio Shack part found in the equipment, and perform whatever modifications are necessary to return the equipment to original factory manufacturer's specifications. 3. cost for the labor and parts required to return the Radio Shack computer equipment to its original manufacturer's specifications will be charged to the customer in addition to the normal repair charges. The An Overview This Technical Reference Manual presents a comprehensive theory of operation for the CPU Module, the FDC, Video/Keyboard, Video Display, Disk Drives and the Power Supplies. There are also general checkout procedures to aid you the user in tracing problems down to a specific sub- assembly or P. C. Board — but no lower. This Manual limits repair procedures to replacement of subassemblies only. A parts list containing part numbers for major subassemblies may be found end of the Troubleshooting and Replacement section. A detailed parts list for each subassembly may be found at the end of the section describing that particualr subassembly. Individual components may be ordered through your local Radio Shack store using the Radio Shack Part Number or the Manufacturer's Part Number if the Radio Shack Part Number is not at the available. We have included in this Manual — for reference only — the Shugart Diskette CDC Flexible Disk Drive Manual, Storage Drive Manual, 800/801 and the 9404B. Data sheets on several of the Integrated Circuit chips used in this system are also included to provide the user with additional data concerning the operation of these devices. To aid you in you may purchase a Software Computer Center or Radio Shack Store. recognizing problem areas, Diagnostics Diskette from your If you have any further problems with the TRS-80 Model II Microcomputer System, contact your Radio Shack Store or Computer Center. TABLE OF CONTENTS Section Page Number Number TRS-80 Model I II Microcomputer System SYSTEM DESCRIPTION 1 3 3 A. Introduction Video Display Console Keyboard Unit 4 4 Peripheral Interfaces TROUBLESHOOTING/REPLACEMENT PROCEDURES 7 A. Troubleshooting Procedure Synopsis of Power-On Diagnostics 9 9 9 Detailed Troubleshooting Instructions B. Replacement Procedures III 11 , 11 System Disassembly System Reassembly Replacement Parts List - Subassemblies 12 CPUMODULE 17 A. Functional Specifications B. Theory of Operation Decoding Logic Bus Steering Logic Wait State Generation Logic Manual and Power-On Reset Logic System Clock Generation Logic 19 15 19 19 20 20 20 21 Interrupt Priority Logic El A 21 Buffers 21 Connector Jl Signal Descriptions Replacement Parts List - CPU Module IV • • 22 25 FLOPPY DISK CONTROLLER BOARD 33 A. Functional Specifications 35 35 35 B. Theory of Operation Decoding Logic Bus Interface Logic Z-80 PIO Interface Logic FD1791 Floppy Disk Controller IC - - FD1 791 Organization Processor Interface Floppy Disk Interface Head Positioning Disk Read Operations Disk Write Operations FDC and FDD Interface Logic Recording Codes Read Clock Recovery 41 Write Compensation Write Compensation Logic Port Allocation - Table Bit Allocation, Port EFH Bit Allocation, Port E0H -Table -Table J1 Signal Descriptions J2 Signal Descriptions Replacement Parts List - 36 36 36 37 38 38 38 39 40 40 40 FDC Board 42 43 44 44 45 46 47 50 TABLE OF CONTENTS (Cont'd) Section Number Number V VIDEO/KEYBOARD INTERFACE 55 A. Functional Specifications 57 58 B. Theory of Operation High Speed Timing Cathode Ray Tube Controller (CRTC) Video Board Select Logic Other Logic Blocks Connector J2 Signal Descriptions Connector J3 Signal Descriptions Replacement Parts List - Video/Keyboard Interface 58 58 63 63 63 64 66 66 69 MEMORY BOARD 73 Multiplexers RAM/Video VI RAM Select Logic RAM and 64K RAM) (32K 75 75 75 75 75 75 75 75 76 77 77 A. Functional Specifications B. Theory of Operation System Bus Interface Memory Array Address Multiplexers Timing Memory Memory Select Logic Disable Logic FF and Jumper Options I/O Port C. Select Logic D. Verification Procedures Replacement Parts VII List - Memory Board 81 VIDEO MONITOR (CRT) 87 VIDEO MONITOR (MOTOROLA) 89 89 A. Functional Specifications B. Service Notes 91 Circuit Tracing 91 CRT 91 Replacement C. Adjustments D. Troubleshooting Guide E. Theory of Operation Video Amplifier 91 92 94 94 94 95 Horizontal Driver Horizontal Output Transformer Vertical Deflection F. Installation Preliminary Checkout Cathode Ray Tube Monitor Circuit Card G. General Servicing Precautions Video Monitor Parts List (Motorola) . VIDEO MONITOR (RCA) H. Functional Specifications General Information Specifications J. Service Adjustments Replacement Parts (RCA) . . 95 98 98 98 99 100 101 105 105 105 105 106 108 TABLE OF CONTENTS (Cont'd) Section Page Number Number VIII FLOPPY DISK DRIVE 111 A. Theory of Operation B. Jumper Configurations 113 113 114 Replacement Parts IX List Disk Drive - AA11080 POWER SUPPLY 117 A. Functional Specifications B. Troubleshooting 119 119 119 119 120 120 120 120 Equipment for Test Set-Up -Up Procedure Set Visual Inspection Start-Up Bracket Removal C. X XI No Output D. Performance Test Operating Characteristics 121 CARD CAGE AND MOTHERBOARD 125 A. Description Replacement Parts List - Card Cage and Motherboard Motherboard Signal Descriptions 127 127 128 KEYBOARD UNIT 133 122 135 A. Introduction Replacement Parts XII List Keyboard Unit - 1 PERIPHERAL INTERFACES 141 A. Serial Interface Connections 143 144 145 146 B. Parallel Interface Parallel Interface Signal Descriptions C. Disk Expansion Connector TRS-80 Model XIII II Disk Expansion System DISK EXPANSION UNIT 147 A. Introduction Subassembly Description B. Switch Configurations 149 149 150 1 50 C. Test Points XIV 37 TROUBLESHOOTING DISK SYSTEM 153 A. Troubleshooting Procedure 155 155 155 155 157 157 158 159 - AC or DC Power Failures Operational Failures '. Read or Write Error B. Replacement Procedures System Disassembly Subassembly Replacement Replacement Parts List - Expansion Unit Replacement Parts List- 9404B Disk Drive, Mechanical Replacement Parts List - 9404B Disk Drive, Electrical iii . . 161 163 TABLE OF CONTENTS (Cont'd) Section Number XV Number AA11100 POWER SUPPLY 167 A. Functional Specifications B. Troubleshooting 169 169 169 169 169 169 170 1 70 Equipment for Test Set -Up Set-Up Procedure Visual Inspection Start-Up Disassembly C. XVI XVII No Output D. Performance Test 171 Operating Characteristics 172 ILLUSTRATED PARTS BREAKDOWN 175 Case Assembly Parts List 1 Chassis Assembly Parts List 77 179 APPENDIXES 183 Z80A-CPU - Zilog Product Specifications Z80A-SIO - Zilog Product Specifications Z80-CTC — Zilog Product Specifications Z80-DMA - Zilog Product Specifications Z80A-PIO - Zilog Product Specifications FD1791 -Western Digital Product Specifications MC6845, CRTC - Motorola Product Specifications SA800/801 Disk Drive - Shugart Maintenance Manual SA800/801 Illustrated Parts Catalog 9404B Disk Drive — Control Data Maintenance Manual IV LIST OF ILLUSTRATIONS Figure Page Number Number SECTION 1 2 3 I -SYSTEM DESCRIPTION Block Diagram Power Distribution Power Distribution Schematic SECTION II 5 5 6 -TROUBLESHOOTING AND REPLACEMENT 1 Synchronization Signals 10 2 Keyboard Disassembly 13 SECTION 1 2 3 3 3 X-Ray View of X-Ray View of CPU Schematic CPU Schematic CPU CPU CPU III - CPU MODULE Printed Circuit Board Printed Circuit Board Diagram (Sheet Diagram (Sheet Schematic Diagram (Sheet - Component - Circuit Side 23 24 29 30 Side 1) 2) . 31 3) SECTION IV - FLOPPY DISK CONTROLLER 1 2 3 4 5 6 6 FD1791 Block Diagram Clock Recovery Block Diagram Interacting Clock/Data Pulses FDC Printed Circuit Board - Component Side FDC Printed Circuit Board - Circuit Side Floppy Disk Controller Board Schematic Diagram (Sheet Floppy Disk Controller Board Schematic Diagram (Sheet 37 41 42 48 49 53 54 1) 2) SECTION V -VIDEO/KEYBOARD INTERFACE 2 Video/Keyboard Block Diagram Timing Diagram 3 MC6845 CRTC 4 5 6 Character Dot Pattern 1 7 8 8 1 3 4 5 59 60 62 65 Pin Identification Keyboard Timing Diagram X-Ray View of Video Keyboard X-Ray View of Video Keyboard Printed Circuit Board Printed Circuit Board Video/Keyboard Interface Schematic Diagram (Sheet Video/Keyboard Interface Schematic Diagram (Sheet SECTION VI - 2 57 MEMORY BOARD — Component - Circuit Side . 67 68 1) 71 2) 72 (64K and 32K RAM) Memory Board Block Diagram Jumper Locations and Address/Bit RAM Identification X-Ray View of Memory Printed Circuit Board — Component Side X-Ray View of Memory Printed Circuit Board - Circuit Side Memory Board Schematic Diagram Side 76 78 79 80 85 LIST OF ILLUSTRATIONS (Cont'd) Figure Page Number Number SECTION 1 2 3 4 5 6 7 Model Model II II II SA 800/801 PCB VIII 99 100 103 106 107 109 - FLOPPY DISK DRIVE Test Points and IX 94 95 96 97 98 Monitor [Display] Schematic Diagram (Motorola) Yoke Assembly (RCA) Monitor [Display] P.C. Board - X-Ray View (RCA) Monitor [Display] Schematic Diagram (RCA) SECTION 4 5 . Deflection SECTION 1 RCA) RCA) Model II Monitor[Display] P.C. Board - Component Location (Motorola) Model II Monitor [Display] P.C. Board - X-Ray View (Motorola) Model M3970 - Series Kits, Rear View (Motorola) Monitor Circuit Card - Edge Connector (Motorola and RCA) Video Wiring Harness (Motorola and RCA) 10 2 3 (CRT) Horizontal Drive Signal (Motorola and Model 1 -VIDEO MONITOR Block Diagram (Motorola and 8 9 11 VII Component Locations 113 - AA11080 POWER SUPPLY Test Layout , Output Connector (S2) Q1 Collector Waveform Q1 Base Waveform AA11080 Power Supply Schematic Diagram 120 120 121 121 124 SECTION X - CARD CAGE and MOTHERBOARD 1 2 Motherboard Printed Circuit Board Motherboard Printed Circuit Board - Component - Circuit Side Side 130 131 SECTION XI - KEYBOARD UNIT 1 2 3 4 Keyboard Internal Cable Keyboard External Cable Keyboard Code Map Keyboard Schematic Diagram SECTION 1 2 3 4 5 XII 135 135 136 140 - PERIPHERAL INTERFACES Serial Interface Connector 50-Conductor Ribbon Cable - Serial Cable Parallel Interface Connector 34-Conductor Ribbon Cable - Parallel Cable Rear View, TRS-80 Model II Computer 143 143 144 144 146 LIST OF ILLUSTRATIONS (Cont'd) Figure p a9e Number Number SECTION 1 CDC XIII - DISK EXPANSION UNIT Model 9404B PCB Test Points and Component Locations 151 SECTION XIV - TROUBLESHOOTING - DISK SYSTEM 1 Disk Expansion Unit Wiring Diagram 156 SECTION XV -AA1 11000 POWER SUPPLY 1 Line Voltage Selection 2 Test Set-Up 3 4 Q1 Collector Waveforms Q1 Base Waveforms 5 AA111000 Power Supply Schematic Diagram 169 169 170 170 173 SECTION XVI - ILLUSTRATED PARTS BREAKDOWN 1 Case Assembly 2 Chassis 178 181 Assembly VII SECTION I SYSTEM DESCRIPTION A. INTRODUCTION Never test the power supply without The TRS-80 Model Microcomputer is a disk-based computer system consisting of three major components, the third of which is optional. They are: a Video Display Console with built-in Disk Drive, a separate Keyboard Unit and the optional Disk Expansion Unit. II power supply Video Display Console The Video Display console is subassemblies: (Refer to Figure made up of ten major a suitable The minimum currents required load. by the are: 5 Volts 12 Volts 24 -12 Volts @ @ @ @ Volts Amps Amps Amps Amps 2.15 1.25 0.00 0.05 Card Cage: 1.) The card cage provides mechanical support 1. Case: and connections electrical Up tronics boards. to the to eight boards can be accom- The case subassembly has three major parts, the bottom tray, the top cover and the front bezel. of These parts provide the attractive housing for the board". The Motherboard holds the TRS-80 Model pin II. Care should be exercised during service operations so that the painted case parts are not modated component the card cage. The main in the card cage subassembly "Mother- the is eight edge connectors and has the card wiring defining the for elec- digital TRS-80 Model 80 printed bus. II marred or scratched. As shipped from the factory, the cards should 2. Chassis: be in the following order: one being the (slot one closest to the power supply). mounted to the bottom tray mounting provisions the other subassemblies in the TRS-80 Model The metal chassis of the case. for The is CPU FDC chassis has II. 3. Power Supply: (Refer to Figure 2.) Slot 1 Slot 2 Memory Slot 3 Video Slot 4 Mem Slot 5 Expansion (ie. 32K memory the add on board) The power supply subassembly Model II is an open frame, 150 power supply. It in TRS-80 the watt, switching has four outputs with the CPU Card: fol- lowing ratings: The CPU card powerful features. 5 Volts 12 Volts 24 Volts -12 Volts @ @ @ @ 8.6 4.5 1 .7 0.2 Amps Amps Amps Amps the CPU running at its full The bootstrap 4 a itself, TRS-80 Model The first of these the in MHz Z80A II is, has several of course, Microprocessor, rated speed. ROM on the CPU card provides the necessary instructions to the Microprocessor The power supply rectifies the AC line to DC, chops it at 20 kHz, then transforms the chopped DC for the required to the required output voltages and finally The ROM the transformed output to low voltage take full rectifies isolated DC. Feedback loops are provided for initialization system on power-up or after a of the computer front panel reset. then "disappears", allowing the user to advantage of the memory space as RAM. volt- age regulation and over current protection. The power supply may be jumper selected for either 95 to 135 VAC or 190 to 270 VAC. It will operate at either 50Hz or 60Hz input frequency. The DMA CPU board allows Memory Access) circuit on the memory to peripheral or peripheral to memory data transfers without CPU intervention. This allows for a much greater program and I/O throughput. One of the most often used (Direct DMA is in data transfers to and from the Floppy Disk Controller. The dual serial interface is also on the CPU card. The baud rate is fully user programmable (refer to your Owner's applications of the **»CAUTION*** This power supply must have a load present, i.e., the computer and CRT, or damaging oscillations may Manual. 6. Floppy Disk Controller Card: The floppy 10. disk controller card provides circuitry necessary to read and write in all the Floppy Disk Drive: The floppy both single disk drive standard eight inch a is drive capable of supporting both single and double density (FM) and double density (MFM) formats density recording formats. All of the disk drive on an eight-inch floppy disk The board control signals an FD1791 floppy drive. uses disk controller chip to generate The read the proper write signals. signals troller card. from the rotates the drive are passed through a phase-locked loop data FD1791 separator before going on to the come from The the floppy disk con- drive contains media at a two motors; one constant speed while the other positions the read/write head over one of to insure the 77 tracks. Electronics on the disk drive convert high reliability reads. digital into signals read/write head signals and vice-versa. ***CAUTIOIM**» The phase-locked loop mum FDC NOTE factory adjusted for opti- Do not performance. iometers on the is adjust any of the potent- board). Models for overseas shipment may be configured AC Moter for the line voltage available in that country and may be fitted with a different with an The parallel printer interface also is on the floppy disk controller card. 7. Memory refresh 8. signals for the memory come from the Video Card: The video card supports both 80 character and 40 character lines, with 24 lines displayed. The charset upper and includes and numeric symbols betic line frequency. detailed description and theory of operation of each subassembly, with the exception of the Case and Chassis, may be found in later sections of this manual. board. acter 50 Hz A Card: The memory card in the TRS-80 Model II uses 16K dynamic RAMs to give either 32K bytes or 64K bytes of read/write memory. The necessary CPU drive pulley for (t . Keyboard Unit The keyboard of the TRS-80 Model II is a 76-key microcomputer controlled capacitive keyboard. The microcomputer and its associated electronics scans the key matrix, converts switch closures to an eight bit digital code and transmits it serially to the keyboard interface on the video card. The keyboard is connected to the main console via a cable from the front bezel of the computer lower case alpha. . #, etc.) and a set Peripheral Interfaces of forms drawing characters. Reverse video can be selected The on a character-by-character basis. heart of the video controller controller chip, which is is a 6845 There are four interface connections on back of the Video Display Console: CRT software programmable 1. The video card board also contains the logic for the key- This interface. receives data and clock serial 2. serial (RS-232-C) Input/Output (I/O) chan- handshake interface signals issues an interrupt from the keyboard when the entire character A parallel I/O TRS-80 standard 3. and Two nels. for various formats. channel, e.g. for connection to parallel-interface line printers. Floppy Disk I/O channel for connection of the Model II Disk Expansion Unit. has been received. The Video Display Console 9. Video Monitor (CRT): The 12 inch CRT and (Cathode Ray Tube) and associ- ated electronics form the video rrronitor for the TRS-80 Model horizontal the video card supply. II. drive, This subassembly receives video, and vertical drive signals from and +12 volts from the power The CRT's high resolution complements the upper/lower case character set of the video card. slots for future also provides connectors expansion. (See Operator's Manual). FLOPPY DISK CONTROLLER LINE PRINTER DISK INTERFACE DRIVES VIDEO VIDEO KEYBOARD INTERFACE DISPLAY MOTHER BOARD CPU BOARD DUAL CHANNEL RS-232 INTERFACE 32K OR 64K BOARD Figure INTERLOCK SWITCH 115 VAC POWER SWITCH 115 VAC 1. TRS-80 Model POWER SUPPLY 115 VAC II Block Diagram TERMINAL BLOCK FUSE FDC& +24V, -12V, +6V, +12V, -12V, +6V, +12V, +12V, GND GND CONT BOARD MOTHER BOARD TIGHTNESS CONTROL GND VIDEO BOARD ri — CRT BOARD Figure 2. TRS-80 Model II Power Distribution Block Diagram ; ». 1 l CN rr < o r*. CU > rr O )=C ~ ** l- cc CO V) -J cc cc egg 2 _J oo ~< Sou V , i < O) <£ r- to n a tn cc O o o n a > CM ~z a. (0 E ^ 0) /\ / jC o CO */N 3 .fl S o < LU T5 O O 00 GO DC Ico" 0) SECTION II TROUBLESHOOTING/REPLACEMENT A. TROUBLESHOOTING PROCEDURE Bootstrap Sequence General This section of the manual will guide service personnel through the system checkout procedure. The troubleshooting steps are organized in a flowchart manner. Following these steps will guide you to the possible failing board or boards. Connect the power cord and keyboard as described in 7. Wait 8. Screen 9. Track ing the two screws top cover aside to prevent accidental scratch- ing. If mode by pulling "DC ERROR" should be no diskette this point, there in cribed in "ON" position, executing in the per- forms the following functions The in 0A0H. This with 2. 12. ROM ROM checksum ERROR" "SC memory 14. Read track 15. "TK ERROR" 16. "SC ERROR" CRC in a error the RAM. into if program not found on track if there is a CRC error in 0. the record ID. 17. "LD ERROR" if a lost 18. "RS ERROR" if the data loaded in data error occurs. is not in Radio Shack boot record format. CRT to come on system diagnostic routine. 19. Call 20. Jump is that indicates will test the ROM data be outputted to the program between is If the Detailed Troubleshooting Instructions bad, is CRT and 1. II Computer by raising the power switch to "ON". Wait a few seconds for Turn on the Model CRT CRT "Z8 ERROR" and the computer warm up. Adjust brightness and con- video display comes on, go to 10. Z80 CPU. Any registers in the to trast controls at the front of the console. run to verify proper data failure of this test will cause output to the TRSDOS. to verified to assure that the the transfers is not ready. track ID field. the computer will halt. A CPU there if indicates set to the is CRT causes the checksum "CK ERROR" 3. drive if order: present and functioning properly. is ERROR" "D0 white screen. a solid The the parameters are sent to the initialization controller and the screen value program on the CPU board. The program starts ROM bootstrap 1. TRS-80 Model II is the Z80 microprocessor the power switch on the raised to the re- des- as the Operator's Manual. automatically still is indicated or drive not is stored to track 0. the drive, Synopsis of Power-On Diagnostics When floppy disk controller if busy or seek error up on the interlock switch plunger. and the disk terminator should be installed closed. to floppy disk sent 11. 13. At is Wait three seconds and check disk status. at the rear of the unit. Carefully the unit has an interlock switch, enable the test command seek is black). (all 10. the top cover of the display console by remov- set the cleared to spaces is door inserted and is controller. the Operator's Manual. Remove until diskette If the not, go to 2. If to be NOTE: halt. will For overseas models configured for 50 Hz "HERZ50" programs on the TRS- operation, the 4. The RAM memory from 1000H to 7FFFH is DOS then tested with a simple read-complement-write-com- pare-complement-write routine. ory locations in "MF ERROR" computer this 28K Any faulty byte range to be output to the will CRT diskette must be called to prevent "jittering" of the video display and to provide accuracy of the time clock. real memcause 2. and the If the pilot light reset switch CPU will halt. is on, go to 4. connector board, go to 3. If is If the pilot light/ seated correctly on the not, reposition the connec- tor and go to 2. 5. The keyboard will be "flushed" of any characters 3. input up until this time. Check for +5 this 6. The message "INSERT DISKETTE" on the CRT. is displayed to 5. is not If in volts on one of the P.C. boards. If the range from 4.8 to 5.2 volts, go the voltage is incorrect, the burned out. Replace and go to 1 LED must be 4. Check the filament of the CRT. If it is go to If it is lit, 7. 10. If the CRT displays a white screen with DISKETTE" not: Check the +12 board (pin volt supply at the ground, pin 7 is 1 is CRT electronics CRT If +12V). displays message, go to If +12 volts white screen with some other 1 1 present, go to 6. is Turn off power and replace video 5. Switch off power. Check the power supply fuse and replace if necessary. Check for shorts across the power supplies. If shorts are found, remove cards from card cage until the shorts disappear, then replace the offending card. Reassemble and go to 1 Otherwise, power supply Remove and replace the Turn off power and Replace Go CPU 1. If has burned out filament. Replace and go to 6 and 9 on the Board and compare the CRT signals to Figure 1. If If CPU there is the Either If message says been detected to 10. 1. ERROR", there is a CPU Z80 CPU on the CPU entire CPU board and go to replace the board or replace the Turn off power. Swap video board with a known good one. Try again. If video display comes on, go ROM ROM ROM or a This means the bootstrap error. board and go to error. not: card. message says "Z8 If Monitor P.C. respective signals are the same, go to 9. "CK ERROR", message says If CPU at pins reinsert original does not check out good. Either replace (Refer to Section VII for installation proced- Look that cures problem, go to to 8. checksum ures.) 7. that reinsert original video card. board. 1. 11. CRT If 10. may have malfunctioned. power supply. Go to card. cures the problem, go to 10. Turn off power and 6. "INSERT the center, proceed to Software Diagnostics below. If not: in the memory 1 "MF ERROR", in card and go to 1 a 32K the lower RAM error has bytes. Replace . Software Diagnostics • Further testing can be accomplished at this time using the Vsync Period = 16-2/3 mi. = Tvsp TRS-80 Model II Troublememory, line printer. Floppy Disk and video alignment are some of the checks that can be made with these diagnostic "tools". Diagnostic Diskette and the Vsync shooting Manual. The -T~ Tvsw = Vsync width = 1.0256 ms. Thip * * Hjync Thsw I L store. Thtw = Horizontal Sync width = 27/is Thip = Horizontal Sync Period s Figure 8. If Sync Signals Replace display goto 8. should be returned to Radio Shack it for servicing 10 1. 64.1jus unable to return the computer to an operational condition, 9. Diskette (Part Number AXX2012) can be purchased through your Computer Center or Radio Shack The Diagnostic * by factory trained technicians. CRT Electronics and try comes on, go to 10. If not: sin. If video B. REPLACEMENT PROCEDURES f. Replacement procedures contained in this manual are limited to system disassembly, removal and replacement of subassemblies and system assembly. There are potentially hazardous areas inside the case, so use caution during disassembly and be sure to read and observe the warning and caution notes. Disconnect all external cables from the rear 3. ; If from the bottom chassis case. Power Supply: ' '" Remove ^"~-'^ A :-/^/v \.- """"" ~'*-p&ijiM-'~' the power supply >j faulty, the large heat sink is 330 volts above line common. Use extreme caution when handling the power may have a potential of connector panel before beginning repair. a. b. 1. Case: a. Remove c. two machine screws from the back the plug and the thirpower supply PCB. plug from the power supply mounting bracket. power supply toward the outside of the and remove four screws, nuts and spacers that mount the video board to the power supTilt the chassis of the case. ply b. DC Remove two #8 thread forming screws from the Remove AC the three-wire teen-wire System Disassembly up on the rear of the top case and angle it toward the front panel; then lift the top case away from the bottom. mounting bracket. Lift d. Remove five screws, spacers that secure nuts, the washers and flat power supply to its mounting bracket. c. Remove two screws from the video the mounting bracket and d. display e. 4. Remove the screw that secures the mounting a. (inside of front panel). keyboard cable only out the Pull as f. 2. b. forward to clear the chassis c. down. face d. Chassis: 5. a. Remove #8 five one of the screws illustrated. used to help is Notice that a. mount the b. up tom case) cable on the lower right chassis slightly (to clear ribs in the bot- and Remove four #8 thread forming screws from the card cage mounting bracket. Remove card cage from the chassis. Removal of Cards from Card Cage: power supply. Lift DC screws, flat washers and lock washers from locations b. Disconnect the front of the mother board. Pull the front panel it not previously done, disconnect the signal flat down). and lay If and control cables from the video/keyboard card and I/O cables from the floppy disk controller and CPU cards. far as necessary to allow the front panel to lay (face the chassis. Card Cage: bracket on top of the disk drive to the bezel e. Remove the power supply from bezel. slide it forward. Remove two thread forming screws that connect the PCB stabilizer to the card cage mounting brackets and remove the stabilizer. Notice the location of the CPU, FDC, video/ keyboard and memory cards. Ensure that the replacement cards are inserted in the same loca- tions. c. Remove screws holding the AC tor to the connector panel and power connecremove the con- c. Remove and replace cards as necessary for repair. nector from the panel. d. d. Disconnect two wires from the fuseholder. Remove six screws, nuts and flat washers that mount the mother board to its mounting brackets e. Disconnect all I/O cables from disk drive, and remove the mother board. CPU card and F DC card. 11 6. Video Display (CRT) and Video Board: e. Lay the drive on its side (PCB up) and remove the mounting two screws from the bottom of CAUTION The CRT bracket. and video board are matched another matched a. f. sets. Do not remove and replace individual pieces. Remove one matched set and replace with 8. Separate the drive from the bracket. Fan set. NOTE: The following steps can only be performed with the chassis removed from the case. the video board is not free from the power supply mounting bracket, perform the steps for If removal of the power supply of the video board. down a. to removal Position the chassis so that the four nuts on the bottom of the chassis are accessible. b. Disconnect the power cable on the fan. c. Disconnect the connector on the rear of the Secure the screw heads while removing the nuts from the bottom of the chassis and remove four CRT nuts. b. Disconnect four color coded wires with spade lugs from the CRT yoke. c. neck. WARNING d. Raise the fan away from the chassis to provide clearance for the screws while removing the fan. There may be a high voltage charge on the high voltage anode. To discharge, connect one end of a wire to a known good ground and connect the other end of the wire to the 9. Keyboard (See Figure a. blade of a common screwdriver. Insert the screwdriver blade under the suction cup and touch it to the clip holding the wire to the b. 2): Disconnect the keyboard external cable from the keyboard (DIN plug.) Place the keyboard with keys down on a soft surface. d. Insert a common screwdriver under the rubber c. grommet on the high-voltage anode wire on the side of the CRT. Use the screwdriver to compress the clip holding the wire to the tube and pull the wire free. e. Remove the upper right and lower left Remove four thread forming screws and two machine screws. screws, d. Place the keyboard with keys up and remove the bezel. e. Disconnect the five-pin connector PCB. f. Lift the nuts and washers from the video display mounting bracket. at J1 on the keyboard with PCB out of the case. CAUTION dropped, the CRT will implode. To avoid kind of accident, support the CRT while performing the next step. If Reassembly this f. Remove the lower right and upper left 1. Keyboard: Reassemble the keyboard screws, in reverse order of dis- assembly. nuts and washers from the video display mounting bracket. 2. g. Lift the CRT and PCB out of the Fan: chassis. a. 7. Disconnect two power connectors from the disk drive PCB. b. c. Disconnect the large (50 pin) card edge connector from the disk drive PCB. Remove four screws from the disk drive Lift the drive chassis. 12 holes new fan, insert the screws into before positioning the fan. Ensure that the fan is oriented so that air will flow in from the bottom and out through the top and so that the power connector is accessible. CAUTION mount- ing bracket. d. b. installing a screw the Disk Drive a. When and mounting brackets out of the Do not put stress on the fan mounting ears. Tighten the screws and nuts only enough to secure the fan to the chassis. UPPER KEYBOARD CASE KEYBOARD MODULE - LOWER KEYBOARD CASE -SCREW, 6-19 x 3/4" (19.05 mm) (6) Figure 2. Disassembly of Keyboard 13 c. Position the chassis so that the fan mounting screws are accessible from the bottom of the c. chassis. d. the CPU, FDC, video/keyboard and cards to the mother board. Be sure of proper orientation in the card cage. Install memory Secure the screw heads while installing the nuts. d. Align the holes in the PCB stabilizer with the in the left and right PCB bracket and in- holes e. Tighten the nuts only enough to ensure that the fan stall e. 3. Disk Drive: Lay the disk drive on position chassis its (PCB up) and mounting bracket (wide end its forward) to align holes in holes in the drive base plate. f. bracket with the g. two screws that secure the mounting bracket. c. Place Install drive to the h. the drive the chassis and align the screw holes bracket and in the chassis. in DC cables to the connector on the lower right front of the mother board. Connect the Connect the I/O cables to the FDC and CPU and connect the control cables to the video/keyboard card. the 6. e. Install four screws that secure the card cage to the chassis. cards mounting bracket into with the chassis. side b. d. Power Supply: four screws loosely so that the drive's position can be properly adjusted. Then tighten the screws that secure the bracket to the chassis. a. Align the power supply mounting holes with the holes in its bracket mounting plate. two power connectors and the card edge b. Individually, position five spacers to align with the mounting holes between the power supply Install Install connector on the drive. board and 4. screws. Position the card cage inside of the chassis and align the holes in the brackets with the holes in a. two thread forming secure. is its mounting plate. Video Display (CRT) and Video Board c. a. Position the with its CRT and align its mounting holes d. the upper left and lower right screws and mounting hardware. c. Install Install the lower left and upper right screws and mounting hardware. f. CRT Install the plug on the rear of the Install the four color coded wires with spade lugs to their associated terminals (as a f. power supply in toward the outside of the bracket. the chassis and chassis. Align the video board mounting holes with its mounting holes on the power supply bracket mounting Position the CRT matched video board inside of the chassis. by screws, nuts and flat washers that power supply to the Position the tilt it e. e. five mounting bracket. b. d. Install secure the plate. Position four spacers to align with the mount- ing holes. neck. determined g. Install four screws, nuts and flat washers that secure the video board to the bracket. h. Position the holes in the mounting bracket to the holes in the chassis and install two thread colored dot on the yoke near each term- inal). forming screws that secure the bracket to the chassis. g. The video board be installed on the power supply mounting bracket, (see the procedures for installation of the power supply). will 7. Chassis: a. 5. Card Cage: a. Align the mother board mounting holes with the holes in the left and right PCB mounting brackets. (The left bracket has a left 90° at the rear and the right bracket has 90° bend at the b. Install secure 14 six the Position the chassis inside the bottom case so that the two wires can be connected to the terminals on the fuse holder and the AC power input connector can be installed on the connector panel. bend a right the two wires to the b. Install c. Install two screws that secure the AC power input connector to the connector panel. fuse holder. rear). screws, nuts and flat washers that mother board to the brackets. d. Lift up the chassis (to clear the ribs bottom) and position holes align with those in it so that on the case mounting REPLACEMENT PARTS the case. Manufacturer's Description e. Install five bottom case. Case: a. Position the front panel (bezel) on the chassis. b. one screw that secures the bezel to the top bracket on the disk drive. c. Number Radio Shack Part Numbei CPU Board 8893405 AXX0501 CRT (with Video Board) 8709043 AXX8000 Disk Drive, SA800 8709042 AXX5002 Disk Drive, SA800 PCB Install Install the two screws that secure the bezel to the video display mounting bracket. the top case at the lip of the bottom case and angle it downward (toward the back) until the top case is properly seated. d. Position e. Part screws, flat washers and lockwashers that secure the chassis to the 8. LIST (Subassemblies) its Install two machine screws that secure the top bottom case. AXX0308 8893425 AXX0505 Keyboard Module 8790504 AXX0204 Memory Board, 32K 8893410 AXX0502 Memory Board, 64K 8893415 AXX0503 Mother Board Assembly 8893430 AXX0500 8790010 AXX6003 8893420 AXX0504 FDC Board case to the Power Supply, A A1 1080 Video Generator Board 15 SECTION CPU MODULE 17 A. FUNCTIONAL SPECIFICATIONS Sheet 3 of the CPU MODEL II CPU Board provides the following hardware resources for the system: The TRS-80 1. Performs data processing activities. a. Supports DMA operations, both on the or on an external system board. b. Supports mode 2 vectored interrupts. 2. Provides primary 3. Provides dual a. b. 4. DMA channel. serial I/O channels. in NAND (4-input on the progress, based and an input or output operation 4M Hz Programmable 8MHz d. Real time clock e. Control signals for system boards. f. Flexible I/O baud rate clocks. on and off board wait FDC Board. presented to pin 2 of is from the BOOT ROM The a diagnostic BOOT ROM (addresses 3. Z80ASIO Chip following: (Direct (Serial Memory in progress. is progress. low, this indicates that an input is occurring or that a program, to verify proper operation memory mapped device which, when 4K of the system address space 0000H through 0FFFH). Half of U38 and one U5 decode the upper address bits (A12 through a is fourth of A15) to detect an address within this range. The output produced from this logic (U5 pin 11) is gated with ROM*/ RAM to produce a low at U5 pin 8 if the BOOT ROM is enabled. One half of U16 combines the output of A1 1 and logical inverse to produce two ROM chip enables its (Central Processing Unit) DMA Chip is enabled, occupies the lower The major components employed include the Z80A produced Read from the BOOT ROM is in progress. SELECT* is gated to pin 43 of the system bus via a tri-state buffer (1/6 of U39). This signal may be monitored with a scope while of the decoding logic. reset logic. is in SELECT* if executing 2. is of the valid ports are addressed or output operation to the valid ports Software switchable enable. Self test diagnostic software included. Z80A CPU Chip U 16. A low IORQ*. at pin to0FFFH). 1. WR *, or combined RDROM* Therefore, state generation. System bootstrap firmware (2716 compatible). Resides in low memory if enabled (location 0000H Power on and manual used to detect is at pin 13 of U14 with the signal 12 of U14 to produce a low going strobe labeled SELECT*. RDROM* goes low if a Read labeled clock for write precomp on is U16 when any at pin 3 of This output system clock option. serial gate) RD*, state of ported. a. 6. U37 of of the ports used are being addressed. This output This output b. c. enables for the peripheral devices used. the chip is inverted and presented to pin 1 of U16. One half of U5 and one sixth of U14 detect an input or output operation c. b. come are used to RS-232C standard signals. Asynchronous and synchronous schemes supported. Bisync, SDLC, and HDLC protocols are sup- 2 or be referred to. decode the I/O addresses required for the CPU Board. U36 is an open collector output BCD to decimal decoder which brings one of its outputs low, dependent upon the binary combination presented to the inputs A through D. These outputs be- One half when any Provides timing signals needed by the system. a. 5. CPU Board now schematic should U36, U37, and one half of U38 Access) Input/Output) (ROM0CE* ROM1CE*). ROM0CE* is active for the 0000H through 07FFH, while ROM1CE* addresses 0800H through 0FFFH. (ROM1CE* and address range 4. Z80A CTC Chip (Counter Timer Circuit) is active for is 5. B. 2716 Compatible ROM (Read Only Memory) peripheral devices on the CPU Board are I/O mapped, BOOT ROM. The port addresses F0H through F9H. Port mapped devices use the lower eight address bits only to specify which port is being addressed. The upper eight address bits are ignored completely and are not relevant to port mapped devices. Three used are not connected to any other lowed to gate out the data pattern corresponding to the byte being addressed to the internal data bus. Decoding Logic with the exception of the is RD* and MREQ* are decoded by one sixth of U3 to detect a memory read in progress. When this signal (U3, pin 8 and ROM0CE*) is low, the BOOT ROM is al- THEORY OF OPERATION The not currently used and logic). IORQ* and WR* U5 to produce the signal labeledOUT* (U5 pin 3). This output, when com- are decoded by one sixth of bined with the signal F9* (U36 pin 11) by one fourth of U3, produces nal a low going strobe at pin indicates that an output operation 1 1 is of U3. This sig- occurring to port and IOCYC*) are used by port mapped devices to determine whether an input or output operation is to occur. If RD* and IOCYC* are both low, F9H. The rising edge of this signal latches the state of D0 into one fourth of U13, "D" FMp-Flop (see sheet 2 of CPU schematics). The Q* output of this Flip-Flop is fed back to U5 pin 9 and enablesor disables the BOOT ROM. An output this condition specifies that an input operation operation to port other signals WR* (WR\ RD*, is in prog- and IOCYC* are both low, this condition specifies that an output operation to the addressed port is ress. If in progress. ROM. set. If D0 is F9H with DD reset the set, BOOT ROM input of this Flip-Flop is enables the will tied to BOOT be disabled. The RESET. Therefore power on or manual reset will automatically enable the BOOT ROM. Below is a table which outlines the port address allocation for the CPU Board. 19 PORT ADDRESS ALLOCATION Port No. Allocation F0H CTC Channel F1H CTC Channel F2H CTC Channel 2 F3H CTC Channel 3 Function A 1 A F4H SIO F5H SIO B F6H SIO F7H SIOB Channel B Command/Status F8H DMA DMA Command/Status F9H ROM ENABLE LATCH Bus Steering Logic Channel data Channel B data A Channel A Command/Status ENABLES/DISABLES The bus ROM steering logic also allows an external DMA opera- tion to occur by disabling the data bus drivers and the ad- The system data bus that data may from the system to the system is a bidirectional path, which means be driven to the system bus or received bus. Outputs to external ports or writes memory require that data be driven to the system bus. Inputs from external ports, interrupt acknowledges from external devices, or reads from system memory other than the BOOT ROM, require that the data is received from the system bus. This problem is somewhat complicated by the fact that data must not be received from the system bus when an input, interrupt acknowledge from an external device, or a Read operation is in progress from CPU Board resident devices. dress and control line buffers when this condition is detect- and BAO (inputs to U3) indicate this condition when both are low. U3 pin 6 (DMA EXT*) is the corresponding output produced. If DMA EXT* is active (low) or U4 pin 9 is low, then pin 8 of U4 goes low, disabling the data bus drivers. ed. BUSRQ* Wait State Generation Logic The memory ing an M1 access time requirements are most severe dur- cycle instruction fetch. All other cesses have an additional one memory half clock cycle to be ac- com- The TRS-80 Model II system uses 200ns access time wait state must be inserted on M1 cycle instruction fetches when using this speed memory. The BOOT ROM is either a 2716 EPROM or a compatible mask ROM. Both of these parts are at best 300ns access time devices, which require one wait state per memory pleted. U31 and U32 are the devices which switch the data to and from the system bus. One third of U22 is used to detect a READ, interrupt acknowledge or input cycle in progress. U22 pin 12 goes low if any of these operations are occurring. Half of U13 and one fourth of U21 detect the presence as a pending interrupt from a device on the CPU Board. An interrupt request from one of the devices on the CPU Board will force U13 pin 4 low, which in turn forces U13 pin 6 low. This output is combined with INTAK* at pins 1 and 2 of U21 to produce the signal LOCAL INT PENDING. This signal when low, prevents U22 pin 8 from going low. , This indicates that an interrupt from one of the devices on the CPU Board is being acknowledged and that the data bus receivers should not be enabled. performs the same function CPU Board are selected by a if U22 pin 9 any of the devices on the 1 1 a memory lege. 20 CPU access if the BOOT ROM is enabled. U25 and U26 along with some associated gating, provide the wait state generation. Provisions have also been state generation. This feature is made for off board wait provided for external sys- tem boards which require non-standard timing for one rea- son or another. Manual and Power ON Reset Logic (SELECT*) memory read or an I/O operation. If pins 10 and 9 of U22 are both high, pin of U22 when high will force pin 8 of U22 low. This enables the data receivers to gate data onto the RAMS. One data bus for either read, input operation, or an interrupt acknow- The Z80-CPU has the characteristic that if the RESET* input goes low during T3 of an Ml* cycle, the MREQ* sigwill go to an indeterminate state for one T state approximately 10 T states later. This action could cause an aborted or short access of the dynamic RAM which could cause destruction of data present in the RAM. To avoid this problem, the falling edge of the RESET input must be nal synchronized with the falling edge of M1 *. One half of U28 and U27 perform this sychronization as well as provide a one-shot to limit the duration of the CPU RESET pulse. the chain, sensing a low at the IEI input, will pass this The one-shot duration line. and pression, is approximately 70ns per switch derequired to avoid suspending CPU refresh of is dynamic memory for a period long enough to destroy RAM contents. Without the one-shot this could occur if the reset switch were held closed for a long period. The connector J2 connects the reset switch to +5 provides the current limited this logic volts for the and also "Power-On" on the front panel. indicator terrupting by pulling low ority signal on , , system operation requires that the main system clock run at 4 MHz and should be used at 2 MHz only under unusual circumstances. The output of U28pin 9 (main system clock) is conditioned by the clock buffer circuitry implemented with Q1, C3, R2, R3, R4, and a 74S04 inverter. The clock buffer circuitry insures fast rise and times and close to fall 5 volts peak to peak amplitude transitions. These clock characteristics are important to the Z80A family of components when operating at maximum frequency (4 MHz). line. The next device its IEO than four devices are used, the delays through each MOS part get excessive and not enough time will be allowed to resolve interrupt contention. The Model II system currently Z80 family parts in the daisy chain. a carry To allow employed using U23 (74S182) and four 74S04 inverters. This scheme anticipates IEO low condition at any of the three devices on the CPU Board and generates a look-ahead signal to the propagate output (U23 pin 7). This signal is inverted and fed to IEO (pin 14) of the system bus. This signal when low, prevents downstream devices from generatand results in a 25ns maximum ripple time IEO to propagate out for the devices on the CPU Board. This allows up to four more family devices (eight ing an interrupt for any total) El A to be used in the system without additional logic. Buffers The logic internal to the puts in this or CPU Board (SIO inputs and out- discussion) operate with more = Logic 1, and 0.8V or less TTL (3.5V logic levels = Logic 0). The logic convention used for interfacing two RS-232-C devices is EIA levels (-3V or less = logic 1, +3V or more = Logic 0). The logic levels must therefore be converted from one con- vention to the other U10, U9, and while U7 and U8 U6 when interfacing to an external device. provide the provide the EIA to TTL TTL to EIA conversion. conversion up to four Z80 family any interrupt structure allows parts to be connected in a daisy chain fashion without additional logic. Priority in a daisy is set by the location of the device chain configuration with each device tied to the INTRQL* line. The diagram below priority of the devices illustrates the relative on the CPU Board. -> IEO TO THE BUS DMA SIO CTC IEO INTRQL" The ^- IEI of the CTC is tied to +5 volts to indicate that it has the highest priority. The second highest priority device is IEO of the CTC. The IEO DMA. The IEO of the routed to the system bus where it is tied to the IEI the SIO with of the SIO DMA is is its IEI tied to the tied to the IEI of the of the next physical The board in the system (FDC for look ahead scheme was Interrupt Priority Logic The Z80 in pri- This priority scheme works fine as long as no more than four Z80 family devices are connected to the chain. If more uses four The heart of the clock generation logic is an 8 MHz crystal oscillator formed by Y1 C21 R23, R24, and three 74LS74 Flip-Flops (page 1 of the CPU schematics). The output of U29, pin 8 should be an 8 MHz square wave. The 8 MHz signal is divided down by one half of U28 and U2 to produce the 4 MHz, 2 MHz, and 1 MHz clocks needed by the system. The 8 MHz signal is buffered by one fourth of U30 and fed directly to pin 46 of the system bus. This clock is utilized by the write compensation circuitry of the FDC Board. A jumper option is provided to select either a 4 MHz or 2 MHz main system clock for the Z80 family parts. This output is divided by 2, to provide the clock inputs for the Z80-CTC when operating in the counter mode. Normal IEO on to the next device by pulling low on expansion of the system, System Clock Generation Logic its Board). priority string insures that a device with higher priority be serviced before a lower priority device when two or more INTRQL* requests occur at the same time. For a device to have priority, its IEI must be high. When a device needs service, it will prevent down stream devices from in- will 21 CONNECTOR PIN SIGNAL DESCRIPTIONS SIGNAL DESCRIPTION 2 Power Ground Not Connected 1 3 Transmit Data Channel A 4 5 Transmit S.E.T. Received Data Channel A 6 7 Not Connected Request to Send Channel 8 Receiver Clock Channel 9 Clear to Send Channel 10 14 Not Connected Data Set Ready Channel A Not Connected Power Ground Data Terminal Ready Channel 15 Carrier Detect Channel 1 12 13 16-21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 22 J1 A A A A A Not Connected Transmit Clock Channel Not Connected Not Connected Not Connected A Power Ground Not Connected Transmit Data Channel B Not Connected Received Data Channel B Not Connected Request to Send Channel B Receiver/Transmitter Clock Channel B Clear to Send Channel B Data Set Ready Channel B Not Connected Not Connected Power Ground Data Terminal Ready Channel B Carrier Detect Channel B -tea W8 : - z+o -' s> i{2Z>«-* 3 %6|H £ s5^ m^i it-it in ii mi i«yjip o •tttl» PJ o a E o ~">L_ frkm o sz3 M' nl jfe v?B 4 ^\ (0 o CQ *sHO +^ #ZJi '5 o a a) D o Q. 010 ^ > i II >CO DC 63 L fer -CZJ1 J x i 11 fill ll"?P! -& IJ-r~rif m 2 Jail |- Fl 23 a 3 o re O O D Q. D Q. o 91 >• n 0) 3 'J 24 CPU MODULE PARTS LIST SYMBOL MANUFACTURER'S PART NUMBER DESCRIPTION RADIO SHACK PART NUMBER ELECTRICAL 8709040 PC Board CAPACITORS 50V, Monolithic 50V, Electrolytic, Radial 33pF, 50V, Ceramic Disc 0.1juF, 50V, Monolithic 8374104 8326331 8300334 8374104 ACC336QJAP ACC330QJCP 33/iF, 50V, Monolithic 50V, Electrolytic Radial 0.1/iF, 50V, Monolithic 8374104 8326331 8374104 ACC336QJAP C22 C23 C24 C25 C26 C27 C28 50V, Monolithic 470pF, 50V, Ceramic Disc O.ljuF, 50V, Monolithic 0.1/nF- 50V, Monolithic 33juF, 50V, Electrolytic, Radial 0.1/zF, 50V, Monolithic 0.1/xF, 50V, Monolithic 33/xF, 50V, Electrolytic, Radial 0.1/zF, 50V, Monolithic 8374104 8301474 8374104 8374104 8326331 8374104 8374104 8326331 8374104 C31 0.1juF, C32 C33 C34 C35 C36 C37 C38 C39 C40 33juF, 50V, Monolithic 50V, Electrolytic, Axial 0.1//F, 50V, Monolithic 33/zF, 50V, Electrolytic, Axial 1000pF, 50V, Ceramic Disc 33;uF, 50V, Electrolytic, Axial O.ljuF, 50V, Monolithic 100juF, 16V, Electrolytic, Axial Not Used Not Used 33jUF, 50V, Electrolytic, Axial 0.1#F, 50V, Monolithic 33/iF, 50V, Monlithic, Radial 8374104 8316334 8374104 8316334 8303104 8316334 8374104 8317101 C1 0.1/uF, C2 C3 C4 33;uF, C14 C15 C16 0.1;iiF, C20 0.1juF, C21 C41 C42 C43 8316334 8374104 8326331 ACC471QJCP ACC336QJAP ACC336QJAP ACC336QJAA ACC336QJAA ACC102QJCP ACC336QJAA ACC107QDAA ACC366QJAA ACC336QJAP INTEGRATED CIRCUITS U1 U2 74S04,Hex inverter 74LS74,Dual "D" flip-flop 8010004 8020074 AMX3558 positive-edge-triggered U3 U4 U5 U6 U7 U8 74LS32, Quad 2 -input OR gate 74LS08, Quad 2-input AND gate 74LS32, Quad 2-input OR gate MC1488, Quad line driver MC1488, Quad line driver MC1489, Quad line receiver 8020032 8020008 8020032 8011488 8011488 8011489 AMX3557 AMX3698 AMX3557 25 CPU MODULE PARTS LIST SYMBOL MANUFACTURER'S PART NUMBER DESCRIPTION INTEGRATED CIRCUITS U9 U10 U11 U12 U13 (Cont'd) MC1489, Quad line receiver MC1489, Quad line receiver 231 6E Mask ROM, 450ns access Z80A, CPU 74LS74,Dual "D" flip-flop RADIO SHACK PART NUMBER (Cont'd) 8011489 8011489 8043316 8047880 8020074 AXX3014 AMX3558 positive -edge-triggered U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 74LS08, Quad 2-input AND gate 74S00, Quad 2-input NAND gate 74LS32, Quad 2-input AND gate 74LS04, Hex inverter Z80A,SIO Z80A, CTC Z80A, DMA 74LS32, Quad 2-input OR gate 74LS10, Triple 3-input NAND gate 74S182, Look-ahead carry generator 74S04, Hex inverter 74LS74,Dual "D" flip-flop 8020008 8010000 8020008 8020004 8047884 8047882 8047883 8020032 8020010 8010182 8010004 8020074 AMX3698 8020074 AMX3558 8000121 8020074 AMX3558 8020004 8020132 AMX3552 AMX3561 8060026 8060026 8020244 8020240 8020240 8020145 8020020 8020032 8020125 AMX4261 AMX4261 AMX3864 AMX4225 AMX4225 8020123 AMX3803 8409006 AMX2571 8150148 ADX1152 AMX3557 AMX3552 AMX3018 AXX3016 AXX301 AMX3557 AMX3898 AMX3558 positive -edge-triggered U26 74LS74,Dual "D" flip-flop positive-edge-triggered *U27 U28 74LS121 Monostable multivbrator 74LS74,Dual "D" flip-flop , positive-edge-triggered U29 U30 74LS04, Hex inverter 74LS132, Quad 2-input U31 8T26A, Bus transceiver 8T26A, Bus transceiver 74LS244, Line driver 74LS240, Line driver 74LS240, Line driver 74LS145, BCD-to-Decimal decoder 74LS20, Dual 4-input NAND gate 74LS32, Quad 2-input OR gate 74LS125, Quad bus buffer gate NAND U32 U33 U34 U35 U36 U37 U38 U39 positive Schmitt Trigger AMX3555 AMX3557 with three state outputs On C U27 and above, U27 will appear as: 74LS123, Monostable multivibrator revision boards CRYSTAL Y1 8.00MHz, 18pF, loading capacity DIODE CR1 26 1N4148, Silicon CPU MODULE PARTS LIST SYMBOL (Cont'd) MANUFACTURER'S PART NUMBER DESCRIPTION RADIO SHACK PART NUMBER JACK J2 Connector, 4-position header 8519053 AJ6791 8100906 AMX3584 8207133 8207212 8207122 8207022 8207222 8207247 AN0159EEC AN0199EEC AN0149ECC AN0078EEC AN0216EEC AN0247EEC 8207247 8207222 8207222 8207222 8207222 8207310 8207222 8207222 8207347 8207222 8207222 8207222 8207310 8207222 8207191 8207191 AN0247EEC AN0216EEC AN0216EEC AN0216EEC AN0216EEC AN0281EEC AN0216EEC AN0216EEC AN0340EEC AN0216EEC AN0216EEC AN0216EEC AN0281EEC AN0216EEC AN0192EEC AN0192EEC 8207222 8207222 8207222 8207222 8207310 AN0216EEC AN0216EEC AN0216EEC AN0216EEC AN0281EEC 8519021 8893001 8509001 8509007 8509002 8589004 8529014 AJ6769 TRANSISTOR Q1 2N3906, PNP RESISTORS R1 R2 R3 R4 R5 R6 R7 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 330 ohm, 1/4W, 5%, Carbon Film 1 .2K, 1/4W, 5%, Carbon Film 220 ohm, 1/4W, 5%, Carbon Film 22 ohm, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 4.7K, 1/4W, 5%, Carbon Film Not Used 4.7K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 10K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 47K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 10K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 910 ohm, 1/4W, 5%, Carbon Film 910 ohm, 1/4W, 5%, Carbon Film Not Used 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 10K, 1/4W, 5%, Carbon Film MISCELLANEOUS Plug, Jumper (7) Reset Switch Assembly Socket, IC, 24-pin Socket, IC, 28-pin Socket, IC, 40-pin Spacer, Crystal Staked Pins (31 (3) AW2433 AJ6579 AJ6758 AJ6580 AHB9424 AHB9682 27 -isv \- us iSV \ Ai4 2<3 V V \ V V All 40 AW 39 A°> UIZ 30 At AT zeoA 45 3? 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/'3 Alt Vcc M IMTI%? * /BUSl fP5 clock 33 pP \|C3 J- l£? CCD6 CPU STO/AJO MANUAL ZES.ET LOCiC ISC U32 612CA f^> DATtf un * ' -T7*l \1S 5/ •I «.c U37\£ -un -Q3 useei < Di Pat x/o AoDi CO / -*- -fsF| 13 $r D2. S3 l El/fJ -4i Di f^r P/iTg PI -* -t^: -DE] gl^Sgt? *- •/SV our P3XSt-IADON * 04 O/dTV * /5^ V s"y DZ ~{5D P/3T5~* •^S"/ / D(a *.C. -cei SV ~9 DAT6* -_£!£ 57 |~ie~ - St/. / 1 D7 P477* NA IT* {BUS) 4 < I0> ZS?2)o- 4Z. \S3 , [46 114 -m 4^n J— - R5 -tia LOCAL INT. PENPINt* TizT\3 -IfoQ io dizp n L'HC -[7£] -|<9o tp/3 PU Schematic Diagram — -* rPie Sheet 3 31 SECTION IV FLOPPY DISK CONTROLLER 33 FUNCTIONAL SPECIFICATIONS A. The TRS-80 BOARD MODEL FDC - PRINTER INTERFACE II provides a standard 8" floppy disk interface and The floppy a Centronics parallel printer interface. disk in- terface supports both single and double density encoding schemes. Jumper options are also provided to select various write precompensation schemes. incorporates a logic The data-clock recovery A write current switch provided at the drive interface for drivers which require this feature. One to four drives may be controlled is by the fers The programmer has the option of using interface. CPU either Data transfers or Direct Memory Access trans- operating in the single density mode. However, if if in the double density mode, all data transfers must be by Direct Memory Access. Status checking may be operating accomplished modes but not both at be generated for various in polled or interrupt the same time. Interrupts may conditions present on the drive status lines diskette in drive, drive door opened since (ie. two sided last select, drive etc.) Head load settling time is managed comby the hardware and is therefore transparent to the programmer. not ready, pletely The printer interface Radio Shack is bus. Pin 43 (SELECT*) can be monitored with a scope while executing a diagnostic program to verify proper operation of the decoding logic. locked loop oscillator which phase achieves state-of-the-art reliability. signal These two outputs are combined at pins 13 and 1 2 of U8 to produce a low going strobe at pin 11 of U8. SELECTI* should go low any time an input or output operation to the used ports occurs. This signal is buffered with an open collector driver (U34) and connected to pin 43 of the system fully compatible with the various line printers as well as other printers which conform to the Centronics parallel standard. Interrupts may be generated on a character by character basis or only after the completion of a time consuming operation such as carriage returns, line feeds, or form feeds. CPUIN is a signal generated by the decoding logic for the purpose of switching the direction of the data bus transceivers (U32, U33) in preparation for an input operation. There are two conditions which require the data bus trans- ceivers to switch direction such that they drive data out- ward to the system data bus. One is a port input operation and the other is an interrupt acknowledge cycle. The condition first of the ports is detected by the combination of any being addressed, concurrent E0H through E7H with an input operation when this condition in progress. is detected. U 19, pin 6 should go low SYNCI* and IOCYCI* If both low, this condition indicates that an interrupt is in progress and that the interrupting device should present its vector to the data bus. are acknowledge cycle IOCYCI* and WRI* are combined at pins 1 and 2 of U21 to produce an active low signal (OUT*) at pin 3 of U21. This pin should be low any time an output instruction is being executed. OUT* is combined with the output from pin 11 of U8 and 4 and 5 of U21 to produce the output DRVSLT* at pin 6 of U21 The rising edge of D R VSLT* is used by pin 9 of U17 to latch the data present on the internal data bus pins B. THEORY OF OPERATION . Decoding Logic corresponding to an output to port EFH. The FDC-PR INTER INTERFACE BOARD is an I/O mapped device which utilizes ports E0H through E7H and port EFH. Port mapped devices use the lower This data pattern port side selection. eight address bits only to specify which port The upper dressed. is and are not relevant to port mapped devices. Three other signals (WR*, RD* and IOCYC*) are used by port mapped devices to determine whether an input or an output operation is to occur. If RD* and IOCYC* are both low, this condition specifies that an input from the addresis in progress. this condition port is in If WR* and IOCYC* are both low, output to the addressed specifies that an progress. Page one of the FDC schematic should now be referred to for the remainder of the Decoding Logic discussion. U20, pin 6 is the output of a four input should be low when any of the ports being addressed. U20, pin 8 input NAND also gate which should go addressed contains an F port address. is HEX NAND is detailed in the Port Allocation section of this manual. The output of U20, designated EX*, is combined and 2 of U8 to produce a low at pin 3 of U8, which corresponds to port addresses E0 through E7. The output of pin 3 of U8 is combined with A21 at pins 9 and 10 of U8, to produce a low at pin 8 of U8 corresponding to port addresses E3H through E7H. The output of U8 with A31 pin 6 of at pins pin 8, labeled 1 CEPIO*, PIO. The output of enable signal for the which is is the chip enable signal for the U8 pin 6, FD 1 791 The output of U21 pin 8 is labeled CEFDC*, a signal labeled is Z80 the chip SELECTI* useful for diagnostic purposes. gate. This pin E0H through EFH are an output of a four low when the port being Interrupt priority the low order nibble of the is determined by the signal IEIN (pin 13 of the system bus). During an interrupt acknowledge cycle if in used to determine the drive, mode, and bit allocation for this latch being ad- eight address bits are ignored complete- ly sed port is The IEIN ority may is is high, this indicates that no device of higher pri- requesting service and that the requesting device bring its IEOUT (pin 14 of the system bus) low to pre- 35 vent devices of lower priority from receiving service. high on pin ledge cycle indicates that an interrupt A progress. in is U13 of 1 high on pin 2 of U13 no higher priority device is requesting high on pin 13, U13 indicates that a device on that is requesting service. If all A allow interrupts to be generated dependent upon register A acknow- the logic states of the I/O indicates for status checking and generating interrupts. service. this A board of these conditions are true, pin 12 of U13 should go low. This output is combined with U19 and pins 4 and 5 of U10. If is lines. Port is primarily used One I/O line configured as an output and provides the prime signal for the printer interface. The port bit allocations for this are detailed in the Port Allocations section of this manual. the output from pin 6 of Port B 4 or pin 5 of U10 goes low, then pin 6 of U10 will also go low. U18 inverts the signal from pin 6 of U10 and causes pin 8 of U18 to go high (CPUIN). A high on CPU IN forces the data bus transceivers (U32, U33) to disable its receivers and enable its drivers to gate data onto the system bus. This allows the PIO to transfer its interrupt The outputs of port B from the printer with an octal noninverting buffer (U24). Note that the enables are tied either pin CPU. vector to the is used (B0 through B7) its outputs. parallel data to rising most and from the system bus must be buffered so that only one TTL Load is presented to each signal line. Page one of the FDC schematic shows the logic required to implement this. U35 is an octal inverting buffer for the address lines. U36 design practice dictates that signals to an octal non-inverting buffer for the is Z80 control Note that the enables for both these parts are tied low, allowing these signals to be gated onto the board at all times. U34 is an open collector buffer used to drive the board outputs which may be driven by other boards in the system. It also buffers the system clock (2 or 4MHz) to the lines. board. U14 is of a V? "D" Flip-Flop configured as a divide by two counter. This divider should be jumpered the system clock if a 2MHz is 4MHz system clock is A to B if (normal connection), or B to C used. U37 when is produces is FDI791 utilizes of inversion is an inverting data bus. Thus, one extra stage required for the PIO. U23, U11, and U12 high going pulse which a triggered. The by the printer to rising latch the the output of U24. - PIO The edge of the 1.5jUs strobe is used 8 bits of information present on BRDY signal stays active until the edge of PACK* which indicates that the printer has accepted the data. This rising edge may also generate an interrupt if the interrupt enable Flip-Flop is set and the PIO has the highest priority. This provides a clean and efficient method for determining when new the printer can accept a character without using status checking loops. The PIO mum interfaces directly to the system bus with a mini- of external components. D0 through directional data path to the system bus. mine which port is intended for the command input operation D7 form A0I and A1I a bi- deter- addressed and whether the operation register or the data register. is in are progress. If all is If low, this indicates an CEPIO* and IORQI* are low with RDI* high, this indicates an output operation is in progress. If IEIN is high, and INTRQI*, SYNCI*, IORQI* and IEO are low, an interrupt acknowledge cycle PIO in is low, a low is progress. If SYNCI* generated on pin 3 of is high and U 10. If this RESETI* sequence RDI* or IORQI* low, the PIO logic enters a state. For a more detailed discussion of the PIO operaconsult the ZILOG Z80 - PIO Technical Manual. occurs without Interface Logic reset tion, The Z80 The rising is Z80 indi- edge of this signal provides a trigger for pin 3 of U37. is a one-shot which produces a 1.5/xs low going pulse for the accomplish this extra inversion. to the printer allows this present on the port B outputs. CEPIO*, IORQI* and RDI* There is a basic problem with using a Z80-PIO with the FDI791. The PIO has a non-inverting data bus while the U24 presented to the inputs of The cable be routed to the printer. Pin 21 of the PIO, BRDY, cates that valid data Good for the purpose of out- are isolated low, gating whatever data directly to labeled Bus Interface Logic mode the output in putting characters to the printer. parallel I/O (PIO) interface controller is a general purpose, programmable, two port device which provides TTL compatible interfacing between peripheral devices and the Z80 —CPU. Any of the following modes can be FD1791 - Floppy Disk Controller IC selected for either port. is an MOS LSI device which performs the functions of a Floppy Disk format/controller in a single chip implementation. The FD1791 contains all the features The FD1791 BYTE BYTE BYTE BYTE OUTPUT INPUT its predecessor, the FD1771, plus the added features necessary to read, write, and format a double density disk- BIDIRECTIONAL (PORT A ONLY) of OR CONTROL MODE These include address mask detection, FM and MFM encode and decode logic, window extension, and write precompensation. ette. In addition the PIO provides a clean and minimal logic method A for generating mode 2 interrupts to the Z80 CPU. used in the control mode which allows the eight (A0 through A7) to be configured as either inputs or outputs. An 8-bit mask register and a 2-bit mask control Port is I/O lines 36 during disk Read, Write, and Verify operations. The Trac k Register can be loaded from or transferred to the DAL This Register should not be loaded when the FDC is busy. FD1791 Organization . The Floppy Disk Formatter block diagram Figure 1. The primary sections include the is illustrated in parallel Proces- Sector Register (SR) sor Interface and the Floppy Disk Interface. Data Shift Register — This 8-bit register assembles from the Read Data input (RAW READ) during Read operations and transfers serial data to the Write Data output during Write operations. register during - This 8-bit register Disk is In Disk Read operations, the assembled data byte is transferred in parallel to the Data Register from the Data Shift Register. In information Disk Write operations, is transferred is FDC is busy unless the execu- is to be overridden. This The command r egiste r DAL but not read onto the DAL - This 8-bit register holds device . , Status information. The meaning of the Status bits is a function of the contents of t he Co mmand Register. This register can be read onto the DAL, but not loaded from the incre- mented by one every time the head is stepped in (towards track 76) and decremented by one when the head is stepped The contents of the register are ). out (towards track compared with the recorded track number in the ID field DAL. CRC the Logic 16-bit includes all - This logic Cyclic and up to the is used to check or to generate Redundancy Check (CRC). The information CRC starting characters. CRC with the address mark The CRC register is preset -t SECTOR r~ This 8-bit register holds the command Status Register (STR) This 8-bit register holds the track numIt of the current can be loaded from the under processor control. — presently being executed. This register should latter action results in a n inte rrupt. from the Data Register to the Data Shift Register. the Seek command the Data Register holds the address of the de sired Track position. This Register can be loaded from the DAL and gated onto the DAL ber of the current Read/Write head position. command - Register (CR) not be loaded when the executing Track Register busy. tion in parallel When FDC is Command the used as a holding Read and Write operations. This 8-bit register holds the add- of the desired sector position. register are serial data Data Register - The contents of the compared with the recorded sector number in the ID field during disk Read or Write operations. The Sector Register contents can be loaded from or transferred to the DAL. This register should not be loaded when ress If DP.Q TG43 INTRO WPRT w7 MR m m " c5 wf !P TROO COMPUTER INTERFACE PL A CONTROL CONTROL CONTROL AO CONTROL __ (230 X 16) DISK REAOY INTERFACE CONTROL STEP * _ OIRC Al 6ARLV LATt CtK iZOP. 1 RG MH HID DDEN * Figure 1. HLT FD1791 Block Diagram 37 to ones prior to data being shifted through the cir- (1's) On Disk Read operation, the Data Request is activated (set when an assembled serial input byte is transferred in high) cuit. - The ALU Arithmetic/Logic Unit (ALU) is a serial com- and decrementer and is used for modification and comparisons with the disk reincrementer, parator, register corded ID field. Timing and Control Interface controls - All computer and Floppy Disk The are generated through this logic. internal device timing is Data Register. This bit is cleared when the Data Register is read by the processor or DMA Controller. If the Data Register is read after one or more characters parallel to the are lost (by having new data transferred into the register prior to processor readout) the Lost Data bit is set in the Status Register. of the sector On The FD1791 has two different cording to the state of DDEN. When D DEN (MFM) (FM) assumed. is is until the end generated from an external crystal clock. density The Read operation continues reached. is assumed. modes of operation When DDEN = ac- = 0, double 1, single density Disk Write operation, the Data Request when the Data Shift Register and requires a the Data Register DMA or AM new If byte its data byte. new data when reset It is data by the processor not loaded is activated is contents to the Data at the time required by the Floppy Disk, a byte written on the diskette and the Lost Data bit is serial of zeroes new loaded with is controller. the next Detector - The address mark detector detects ID, data and index address marks during read and write opera- Register transfers is is set in the Status Register. tions. At the completion of every command an INTRO is generINTRO is reset by either reading the status register or by loading the command register with a new command. ated. Processor Interface interface to the processor (DAL eight Data Access Lines is ) accomplished through the and associated control sig- The DAL are used to transfer Data, Status, and Control words out of, or into the FD 1 791 The DAL are threestate buffers that are enabled as output drivers when Chip Enable (CE*) and Read Enable (RE*) are active (low logic state) or act as input receivers when CE* and Write Enable (WE*) are active. INTRO addition, In The command condition is is generated if Force a Interrupt met. nals. Floppy Disk Interface . The FD1791 has two modes of operation according to the state of DDEN (pin 37 ). When DDEN = 1 single density is , When DDEN = selected. either case, the When transfer of data to the Floppy Disk Controller is required by the host processor, the device address is decoded and CE* is made low. The and A0, combined with the ation or least-significant address bits signals RE* clock is at 0, double density selected. In is CLK input (pin 24) is at 2 MHz. When the the stepping rates of 3, 6, 10, and 15ms 2MHz, are obtainable. A1 during a Read oper- WE* during a Write operation, are interpreted as selecting the following registers: Head Positioning Four commands cause positioning of the Read-Write head (see Table 1 . Register Select is Comand word. PORT ADDRESS A1 - A0 E5H 1 E6H 1 E7H 1 1 After the READ (RE*) WRITE (WE*) flag is last Command Track Register Track Register Sector Register Sector Register The Data Register Data Register Direction Register Memory Access (DMA) types of data transfers between the Data Register of the FD1791 and the processor, the Data Request (DRQ) output is used in Data Transfer control. This signal also appears as status bit during Read and Write operations. is There set in 1 directional and step, commands. Note is of the an clock. If in II if that this time doubles TEST = 2) 15 the Verify , there is 15ms head settling time or III command. Table step command additional also a any Type (shown rates I 1MHz for a tling time. flag Type set in 30ms Status Register During Direct zero if set- the E can be applied to a Step- Motor through the device interface. Step - A 2/ns (MFM) or 4/zs (FM) pulse is provided as an output to the drive. For every step pulse issued, the drive moves one track location in a direction determined by the direction output. 1 Direction when (DIRC) tion signal is - The Direction signal is active high and low when stepping out. The Direcvalid 12ms before the first stepping pulse is stepping generated. 38 The period of each positioning field in bits r milliseconds of head settling time takes place to E4H Section). specified by the in command is executed an Read/Write head position can be performed by setting bit 2 (V = 1) in the command word to a logic 1. The verification operation begins at the end of When Seek, Step, or Restore a optional verification of the 15 millisecond settling time after the head is loaded The track number from the first encount- against the media. ered ID Field Register. Cyclic is against the contents of the Track compared the track numbers compare and the ID Field If Redundancy Check (CRC) the verify correct, is is complete and an INTRQ is generated with no The FD1791 must find an ID field with correct number and correct CRC within 5 revolutions of the operation errors. track media; otherwise the seek error and an set is INTRQ is generated. The following example explains the use of the Stepping Rates Table: If Clock not) bit is is 2MHz and high (1) and R0 is high (1) if DDEN bi t R1 (double density i s TEST and low (0) while = 1, then the stepping time will be 6 milliseconds. Table CLK 2 MHz 2 MHz DDEN MHz 1 1 MHz TEST=1 TEST=1 MHz 1 TEST=1 MHz HLT In ms 3 ms 6 ms 6 ms summary HLD is a status bit in for the reset. If h ning of the = Type 1 command and and Type I then will HLD and status. commands: if h = and V = 0, V = 0, HLD is set at the beginHLT is not sampled nor is there h = and V = 1 H LD is set near I 5ms delay. If command, an internal 15ms delay occurs, and the FD1791 waits for HLT to be true. If h = 1 and V = 1, HLD is set at the beginning of the command. Near the end of the command, after all the steps have been issued, an internal 15ms delay occurs and the FD1791 then waits for H LT to occur. an internal 1 , the end of the For Type II and III commands with E flag off, HLD is made active and HLT is sampled until true. With E flag on, HLD is made active, an internal 15ms delay occurs and then HLT is sampled until true. Sector lengths of 128, 256, 512, or 102 4 are ob tainable in either FM or MFM formats. For FM, DDEN should be placed to logical 1. For MFM formats, DDEN should be TEST=0 TEST=0 mat time by a special byte in the ID field. Length byte in Approx. Approx. the ID field is If this Sector zero, then the sector length If 01, then 256 bytes. If 02, then 512 bytes. 03, then the sector length is 1024 bytes. The number of sectors per track as far as the FD1791 is concerned can be is 3 appears as FD1791 The "and" of placed to a logical 0. Sector lengths are determined at for- X X 1 1 R1 R0 TEST=1 2 are true, the read from or write to the media. Disk Read Operations Stepping Rates 2. When both HLD and HLT 128 bytes. If 6 ms 6 ms 12ms 12ms 10 ms 10ms 20 ms 20 ms 15 ms 15 ms 30 ms 30 ms 1 /" 400mS 200mS 1 to 255 sectors. The number of tracks as far as the FD1791 is concerned is from to 255 tracks. For IBM 3740 compatibility, sector lengths are 128 bytes with 26 sectors per track. For System 34 compatibility (MFM), from 1 1 1 sector lengths are 256 bytes/sector with 26 sectors/track; The Head Load (HLD) output controls the movement of the read/write head against the media. the beginning of a (h = flag 1), at is set Type I the end of the (V = 1), HLD is command if the Type command I activated at h flag if is set the verify or upon receipt of any Type II or III command. Once HLD is active it remains active until either and V = 0); or command is received with (h = a Type if the FD1791 is in an idle state (non-busy) and 15 index I pulses have occurred, it is or lengths bytes/sector with 8 sectors/track. For read operation, the FD1791 requires a RAW READ Data (Pin 27) signal which is a 250ns pulse per flux transition and a Read clock (RCLK) signal to indicate flux transition spacings. The RCLK (Pin 26) signal is provided by a Phase locked loop or counter techniques. In addition, When when 2 is ronization. reading from the media made bytes of zeroes are detected. true FM, RG is The FD1791 in must find an address mark within the next 10 bytes; other- RG and the search for 2 bytes of zeroes begins an address mark is found within 10 bytes, RG remains true as long as the FD1791 is deriving any useful information from the data stream. Similarly for MFM, RG is made active true when 4 bytes of "00" or "FF" are detected. The FD1791 must find an address mark within the next 16 bytes, otherwise RG is reset and search rewise all is reset over again. If sumes. HLD (" -50 TO 100mS- J- HLT (FROM ONE SHOT) Head Load Timing a provided as an output (Pin 25) which informs some phase locked loops when to acquire synch- Read Gate Signal reset. Head Load Timing (HLT) is an input to the FD1791 which is used for the head engage time. When HLT = 1, the FD1791 assumes the head is completely engaged. The head engage time is typically 30 to 100 ms depending on drive. The low to high transition on HLD is used to fire a one shot (Va of U31). The output of the one shot is then used for HLT and supplied as an input to the FD1791. 1024 of 39 Disk Write Operations When writing on the to take place is Since write precompensation values vary from disk manufacturer to disk manufacturer, the actual value is deterdiskette, the Write Gate (WG) output is activated. This allows current to flow into the Read/Write head. As a precaution to erroneous mined by one shots or delay lines which are located write precompensation signals and LATE are valid in both FM and MFM formats. several FD1791 The external to the EARLY . writing the first data byte must be loaded into the Data Register in response to a Data Request from the FD1791 is inhibited when the Write Protect input command which case any Write is a logic immediately terminated, an interrupt is generated, and the Write Protect status bit is set. The Write Fault input, when activated, low, in signifies a writing fault condition such electronics as FD1791 samples is logic is generated. This also applies to Type I commands. is detected failure to detect Write disk drive in current flow when the Write Gate is activated. On detection of this fault FD1791 terminates the current command, and sets the Write Fault bit (bit 5) in the Status Word. The Write Fault input should be made inactive when the Write Gate output the becomes a ceived the before the Write Gate signal can be activated. Writing Read or Write command (Type II or III) is rethe Ready input. If this input low the command is not executed and an interrupt Whenever inactive. FDC and FDD Interface Logic and mode selection must be accomplished exFD1791. A six-bit latched output port (U21) provides the outputs which control these functions. Note that the outputs from the FD1791 to the floppy drive interface are buffered with high current open collector invertDrive, side, ternal to the ing drivers (U4, U5, U16). This puts of the TTL FD1791 is required because the out- will directly drive only one standard load. For Write operation, the FD1791 provides Write Gate (pin 30) and Write Data (pin 31) outputs. Write Data consists of a of 50 0ns pul ses series pulses in MFM (DDEN address marks in = in 0). FM (DDEN = and 250ns Write Data provides the unique Recording Codes 1) both formats. Information is stored on a disk using a code that takes the desired information and converts it to pulses that the re- cording system can write and recover from the disk. The Also during write, two additional signals are provided for write precompensation. These are LATE (Pin 18). EARLY is EARLY active true when (Pin the and 17) WD pulse appearing on (Pin 30) is to be written early. EARLY is valid for the duration of the pulse. LATE is active true when the WD pulse pulse is is to be written late. present, the WD pulse both are low when If is a WD to be written at nominal. ideal system requires that all the pulses written on the disk be information. The problem with this type of system when recovered shows the is it is differences. Table 3. Self-Clocking Codes DOUBLE FREQUENCY 3672 6536 Data Transfer Rate 249,984 Hz 499,968 Hz Bits/Track 42,664 83,328 Bits/Disk 3,208,128 6,416,256 4/js 2ms 6536 6536 Cell Time Flux Density (inner track) 40 MODIFIED FREQUENCY MODULATION 3268 Bit Density 1836 is not self-clocking. Selfclocking codes include Frequency Modulation (FM) and Modified Frequency Modulation (MFM). The actual flux reversal rate of the two codes is the same; the Table below the data (outer track) (inner track) Frequency Modulation (FM): Information is always recorded by inserting a clock between each data bit. A "1" bit is defined as a flux transition between clocks while a Read Clock Recovery Logic defined as the absence of this flux transition. Clocks are Floppy Disk Schematic (Figure low is included for reference. is The always flux transitions. between data is shown in Sheet 1 of the The block diagram be- 6). NAND A Modified Frequency Modulation (MFM): Information is encoded using data and clocks such that the longest time between flux transitions is the same as in FM code but clocks are not recorded read clock recovery logic gate (U13) insures that data and clock three input pulses are not allowed to enter the recovery circuit unless the bits. FDD elapsed. head The is loaded and the settling time required has edge of these gated pulses triggers a one- rising shot (1/2 of U25). Definition: The duty cycle 1. "1" cell 2. "0" the is defined as a flux transition occuring at the half time. is defined as a flux transition occuring at the start of time. A pulse at the beginning of the cell is a cell clock; however, a clock suppressed was a "1" if in is not always written. Clock there will be a "1" the preceding READ DATA in this cell or if the timing for the MFM is determined The other U25 half of mode. is triggered by the falling pulses at pin 13 (U25), which produces a is edge of the 150 ns pulse per 1 2 of U25. This signal consists of both transitions and is fed directly to pin 27 of clock and data flux transition at pin there cell. READ DATA GATING of the output of this one-shot by the adjustments performed on R36 and R37. R36 determines the timing for the FM mode, while R37 determines U6(FD1791). ONE SHOT ONE SHOT CLOCK AND DATA 150 ns PULSE PER FLUX TRANSITION FILTER -, PHASE DETECTOR 1 1 FM/MFM* READ CLOCK Figure 2. Clock Recovery Block Diagram 41 The phase locked loop oscillator circuit takes the pulses from pin 13 of U25 in either FM or MFM mode and develops a clock that is phase locked to the data. The main components of the circuitry include a phase detector, a filter/ amplifier, a voltage controlled oscillator, and several stages of divide-by-two Flip-Flops. U28 is the is VCO (U27) is an MC4024 in Figure 3. Peak shift two is the result of the inter- pulses tend to have a por- tion of their individual signals superimposed on each other, the actual readback voltage is the algebraic summation of the pulses. phase detector which compares the phase of the pulse width shaped signal from pin 13 of U25 to the counted down VCO output. The output of pin 5 of U28 directs the VCO to increase the frequency while the output from pin 9 of U28 decreases the VCO frequency. U26, along with the associated feedback and filter components, combines, filters, and amplifies these two outputs, and produces a DC error voltage for the VCO. The shown action of the pulses. Because of which only 1/2 is TE TOGGLE— I ZERO PEAK -* 4- SHIFT RESULTANT (ACTUAL) READBACK >VOLTAGE be- The error signal from the amplifier is applied to 2 of U27 and the output (pin 6, U27) is applied to the ing used. pin which is either a divide by 2 or a divdepending on whether MFM or FM mode is selectThe resulting signal is fedback to the phase detector to divider circuit (U29) ide ed. by 4, presented to pin 3, U14 and and fed to a delay circuit imple- close the loop. This signal again divided by «-PEAK •"PEAK SHIFT SHIFT Figure 3. Interacting Clock/Data Pulses When all quency Write Compensation LATE EARLY is two mented with two inverters (U4) and a NAND gate (U7). The output of pin 3, U7, is then fed to pin 26 of U6 which forms the read clock for the FDC. is is 1's or all 's are being recorded, the data fre- constant. Pulses are spaced apart by one cell. As a result, the pulse The write compensation circuit compensates for head/ media peak shift. Peak shift is an effect that degrades read accuracy by distorting the waveform. Ideally, the flux reversal command by the write toggle would be instantaneous. Current would immediately switch from one polarity to the other. However, it takes time for the current to reverse and the fields to decay and build up in the opposite direction. The resulting read back voltage is more or less sinusoidal with peaks less easily defined in spacing causes the overlap errors to be equal and opposite. The negative-going and positive-going errors cancel each other. This is a "zero peak shift" con- dition. Peak shift occurs when 011 pattern represents is a change in frequency. A frequency increase since there is a there a delay of about 1.5 cells between the 01 and only tween the 11. As 1 cell be- a result, the squeezing of cells cause the mathematical average (the actual readback voltage) to shift the apparent peak to the left. This is early peak shift. time or amplitude. A With current recording pulses are close phenomenon 42 is techniques, adjacent clock/data enough to interact with each other. This particularly noticeable at inner tracks. This is 1 10 pattern represents a frequency decrease since not written at all in the third cell. a pulse Write compensation The window data. that required to reduce the effect of peak is out of the head due to the reduced window of shift is is defined as the total amount of time allowed for the bit to appear and be recognized. The window window of MFM of 2jus. is 1ms as opposed to the double frequency The amount of compensation to the present heads and media pensation The shift. circuit looks at three bits NAND The gates (U3) to the right of U2 are used to select one of the two outputs from pins 7 or 9 of U2. Pin 7 of U2 is selected as the output if 125ns precompensation is used, while pin 9 of U2 is selected as the output if 250ns precompensation is used. best suited 125 to 250ns. This com- is applied to data patterns that will result in a is peak large MFM on each side of U3 pin 1 is the compensated write data, which is used to trigger a one-shot (one-half of U37). A 250ns positive going pulse is produced at U37 pin 5 for The output of a reference bit and determines whether to shift or not. every write pulse presented to The following patterns (U37) insures that the write data pulse width is always approximately 250ns. The output of the one-shot is buffered by a high current open collector driver (1/6 of U16) and presented to the floppy disk drive. When 250ns precompensation is used, it is necessary to stretch the late sig- are compensated (bit shifted) in the direction of the arrow. EARLY LATE nal (a = Don't Care When shifts this pected 1 in 1 10 is The one-shot from the FD1791 approximately 500ns. Half of U31 is used to produce the stretched late signal. table below describes the the Write Compensation a flux transition pattern of the second pin 10. one-shot) The X U37 written on the disk jumper options possible for logic. Table 4. Jumper Options pulled toward the 0. Write compensation is the opposite direction the amount of the ex- JUMPER CONNECTIONS shift. Write Compensation Logic OPTION SELECTED 2 to 3 and 5 to 7 125ns outer TRKS 250ns inner TRKS Implementation 3 to 4 and 6 to 7 250ns inner only* The write compensation logic is shown on page one of the FDC schematic. U1 forms a shift register which is clocked at 8MHz. This arrangement provides a predictable 3 to 4 and 8 to 7 125ns inner only 125ns delay per stage for *Standard System Configuration a logic one presented to pin 4 signals from the FD1791, along of U1. The with early, late, and FM*/MFM, TG43 are gated through three AND gates (2/3 a Dual One of Four Data Selector (U2). The data selector gates one of its four inputs to the output, dependent upon the logic state of the A and B inputs. The top half of U2 is used for 125ns write precompensation while the lower half is used for 250hs precompensation. of U7) to control the operation of As noted in the table, 250ns inner tracks only is the standard system configuration as shipped from the factory. Options other than the standard configuration should be used with caution and should not be attempted by the unexperienced user. 43 Table 5. Port Allocation PORT* E0H FUNCTION ALLOCATION PIO Port A- PrinterandFDCINT. Data status - E1H PIO Port B E2H PIO Port E3H PIO Port E4H FDCStatus/CMD E5H FDC Track E6H F DC Sector Register Current Sector Add. E7H FDC Data To or From Data Printer Data (output) A- Control Configuring Port B- Control Configuring Port B Register Register Data Register A FDC Status and CM Current Track Add. Diskette EFH Drive Select Latch Drive, Mode, Side Select Port D6 D5 D4 Side Select Unused Unused D7 Mode Select 1 = FM Mode 1 = MFMMode NOTE: D3 44 through Table 6. BIT Allocation Select Latch (output only) EFH, Drive = Side 1 1 = Side0 D0 - only one of these bits should be D2 D3 DRV3SEL 1 = NOTSEL = SEL ow per output DRV2SEL 1 = NOTSEL = SEL instruction. D0 D1 DRV1SEL 1 = NOTSEL 0=SEL DRV0SEL 1 = NOTSEL 0= SEL Table 7. BIT Allocation Port E0H, Printer, Paper Busy = Busy 1 D4 Empty Printer Select = Selected = Paper Empty 1 = Not Selected D2* D3* PRIME Printer Fault 1 D5 = Paper not Empty = Not Busy 1 Interrupt Status D6 D7 Printer FDD, FDC Disk Change = Door not Opened Low = Fault High to = Not Fault Transition Resets Printer 1 D0 D1 FDC INT REQUEST Two-Sided Diskette 1 = Two-Sided Diskette Preset 1 indicates that the selected drive has had *D3 is its door opened since = FDC is Interrupting = Not Interrupting = Single-Sided Diskette *D2 = Door Opened it was last selected. an output which resets some printers. 45 J1 (FDC Board to Floppy Disk) SIGNAL DESCRIPTIONS SIGNAL PIN 7 GND WRTCRT* GND NC GND NC GND 8 NC DESCRIPTION 9 10 GND Power Ground Reduced Write Current Power Ground Not Connected Power Ground Not Connected Power Ground Not Connected Power Ground TWOSID* Two 11 GND 12 13 14 GND Power Ground Drive Door Opened Since Last Select Power Ground SDSEL Side Select; low = side 15 GND Power Ground Not Connected Power Ground Head Load Power Ground 1 2 3 4 5 6 DSKCHG* 16 NC 17 GND 18 19 GND HLD* Sided Diskette Installed 20 IP* Index Pusle 21 GND RDY GND GND Power Ground Drive Ready Power Ground Not Connected Power Ground DS1* Drive Select GND Power Ground 22 23 24 25 26 27 NC One Two 28 29 30 DS2* Drive Select GND Power Ground DS3* Drive Select Three 31 GND GND Power Ground Drive Select Four Power Ground DIR* Step Direction GND 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 * 46 NAME DS4* GND Power Ground Step Head One Track Power Ground CPWD* Write Data GND WG* GND Write Gate TRK0* Track Zero Indication STEP* Power Ground Power Ground GND Power Ground WPRT* Write Protected Diskette GND Power Ground Read Data Power Ground Not Connected Power Ground Not Connected RD* GND NC GND NC Indicates an inverted signal or an active low signal. , high = side 1 J2 (FDC Board to Line Printer) SIGNAL DESCRIPTIONS SIGNAL DESCRIPTION NAME PIN PSTB* Data Strobe Power Ground 3 4 GND PDAT0 GND 5 PDAT 6 GND 7 PDAT 8 GND 1 2 PDAT 9 10 1 11 12 GND 13 14 PDAT 15 PDAT 2 3 1 to Printer Data Bit 2 to Printer Data Bit 3 to Printer Power Ground 4 Data Bit 4 to Printer Power Ground 5 Data Bit 5 to Printer Power Ground 6 GND PDAT Data Bit Power Ground GND 16 17 18 19 to Printer Power Ground Power Ground GND PDAT Data Bit Data Bit 6 to Printer Power Ground 7 GND Data Bit 7 to Printer 21 BUSY 22 23 24 25 26 27 28 29 GND Power Ground Printer Data Acknowledge Power Ground Printer Busy Power Ground PE Paper Empty GND Power Ground PSEL PRIME Printer Selected GND Power Ground Printer Fault 30 FAULT NC NC 31 GND 32 33 34 GND PACK* GND 20 indicates an inverted NC NC signal or an active low Printer Reset Not Connected Not Connected Power Ground Not Connected Power Ground Not Connected signal. 47 < « T 5L -nf :§£ iiJC oV (A C 0) c o a E o o I O 00 u D a. o Q u. g > > s» in 0) 3 49 FLOPPY DISK CONTROLLER PARTS LIST SYMBOL MANUFACTURER'S PART NUMBER DESCRIPTION RADIO SHACK PART NUMBER ELECTRICAL PC Board 8709063 CAPACITORS C2 O.ljuF, 250pF, 50V, 20%, Ceramic Disc 50V, Monolithic 8321251 8374104 C8 C9 C10 0.1/xF, 50V, Monolithic 33pF, 50V, Ceramic Disc OAfxF, 50V, Monolithic 1300pF, 12V, 2%, Ceramic Disc 0.1juF, 50V, Monolithic 8374104 8300334 8374104 8322131 8374104 50V, Monolithic 8374104 8323471 8324471 8316334 8316334 8374104 8374104 8322131 8323471 8321111 8302104 8374104 8334683 8374104 8321101 8316334 8374104 8374104 8301204 8316334 8300334 ACC201QJCP ACC336QJAA ACC330QJCP 8150232 8150148 8150148 8150148 8150234 ADX1350 ADX1152 ADX1152 ADX1152 ADX1279 8110222 8100907 AMX4263 AMX4187 C1 C11 C12 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 0.1;uF, 0.047mF, 25V, 20%, Ceramic Disc 0.47^uF, 35V, 20%, Tantalum 50V, Electrolytic, Axial 33mF, 50V, Electrolytic, Axial 0.1juF, 50V, Monolithic 0.1juF, 50V, Monolithic 1300pF, 12V, 2%, Ceramic Disc 0.047/iF, 25V, 20%, Ceramic Disc 33/uF, 110pF,50V,2%,Mylar 0.001/zF, 50V, 20%, Ceramic Disc 50V, Monolithic 35V, Tantalum, PC 0.1juF, 50V, Monolithic 100pF, 50V, 20%, Ceramic Disc 33juF, 50V, Electrolytic, Axial 0.1juF, 50V, Monolithic 0.1/LiF, 50V, Monolithic 200pF, 50V, Ceramic Disc 33/iF, 50V, Electrolytic, Axial 33/zF, 50V, Ceramic Disc 0.1juF, 68juF, ACC330QJCP ACC336QJAA ACC336QJAA ACC336QJAA DIODES CR1 Zener,5.6V,5% CR2 CR3 CR4 CR5 1N4148 1N4148 1N4148 Zener, 6.2V, 5% TRANSISTORS Q1 Q2 50 2N2222A, NPN, TO-18 case 2N2907,PNP, TO-18 case FLOPPY DISK CONTROLLER PARTS LIST SYMBOL DESCRIPTION (Cont'd) MANUFACTURER'S PART NUMBER RADIO SHACK PART NUMBER 8207222 8207222 8207222 8207222 8289350 8207222 8207115 8207115 8207115 8207310 8207115 8207222 8207222 8207310 8207222 8207215 8207282 8207222 8207222 8207115 8207115 8207222 8207222 8201211 8201310 8217127 8201234 8201234 8207251 8201211 8201310 8269310 8217116 8207212 8207210 8269310 8269310 8207222 8207222 8207222 8207222 8201180 8201114 AN0216EEC AN0216EEC AN0216EEC AN0216EEC 8207247 8207247 8207439 8207222 8207310 AN0247EEC AN0247EEC AN0414EEC AN0216EEC AN0281EEC RESISTORS R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 50K, 10%, multi-turn potentiometer 2.2K, 1/4W, 5%, Carbon Film 150 ohm, 1/4W, 5%, Carbon Film 150 ohm, 1/4W, 5%, Carbon Film 150 ohm, 1/4W, 5%, Carbon Film 10K, 1/4W, 5%, Carbon Film 150 ohm, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 10K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 1.5K, 1/4W, 5%, Carbon Film 8.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 150 ohm, 1/4W, 5%, Carbon Film 150 ohm, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 1.1K, 1/4W, 1%, Carbon Film 10K, 1/4W, 5%, Carbon Film 270 ohm, 1/2W, 5%, Carbon Film 3.48K, 1/4W, 1%, Carbon Film 3.48K, 1/4W, 1%, Carbon Film 5.1 K, 1/4W, 5%, Carbon Film 1.1K, 1/4W, 1%, Carbon Film 10K, 1/4W, 1%, Carbon Film 10K, 20% potentiometer 160 ohm, 1/2W, 5%, Carbon Film 1 .2K, 1/4W, 5%, Carbon Film 1K, 1/4W, 5%, Carbon Film 10K, 20% potentiometer 10K, 20% potentiometer 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 806 ohm, 1/4W, 1%, Carbon Film 140 ohm, 1/4W, 1%, Carbon Film Omitted 4.7K, 1/4W, 5%, Carbon Film 4.7K, 1/4W, 5%, Carbon Film 390K, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 10K, 1/4W, 5%, Carbon Film AP7029 AN0216EEC AN0142EEC AN0142EEC AN0142EEC AN0281EEC AN0142EEC AN0216EEC AN0216EEC ACC0281EEC AN0216EEC AN0206EEC AN0271EEC AN0216EEC AN0216EEC AN0142EEC AN0142EEC AN0216EEC AN0216EEC ACC0198EEC AN0281EEC AN0155EFC AN0232BEC AN0232BEC AN0252EEC AN0198BEC AN0281BEC AP7028 AN0143EFC AN0196EEC AN0196EEC AP7028 AP7028 AN0216EEC AN0216EEC AN0216EEC AN0216EEC AN0141BEC 51 FLOPPY DISK CONTROLLER PARTS LIST SYMBOL DESCRIPTION RESISTORS R50 R51 R52 R53 R54 (Cont'd) MANUFACTURER'S PART NUMBER RADIO SHACK PART NUMBER (Cont'd) 20K, 1/4W, 5%, Carbon Film 330 ohm, 1/4W, 5%, Carbon Film 2.2K, 1/4W, 5%, Carbon Film 150 ohm, 1/4W, 5%, Carbon Film 15K, 1/4W, 5%, Carbon Film 8207320 8207133 8207222 8207115 8207315 AN0306EEC AN0159EEC AN0216EEC AN0142EEC AN0297EEC 8020175 8020153 8020002 8000016 8000016 8045791 8020008 8020032 8020004 8020008 8020002 8060026 8020010 8020074 8020125 8000016 8020174 8020004 8020032 8020020 8020032 8047881 8060026 8020244 8020123 AMX3566 AMX3562 AMX3551 8050741 8050024 8010112 8020074 8020000 8020123 AMX4258 8060028 8060028 8000007 8020240 8020244 8020123 AMX4262 AMX4262 8519021 8509002 8529014 AJ6769 AJ6580 INTEGRATED CIRCUITS U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 74LS175, Quad "D" flip-flop 74LS153, Dual 4-to-1 line data selector/multiplexer 74LS02, Quad 2-input NOR gate 7416, Hex buffer 7416, Hex buffer FD1791B 74LS08, Quad 2-input AND gate 74LS32, Quad 2-input OR gate 74LS04, Hex inverter 74LS08, Quad 2-input AND gate 74LS02, Quad 2-input NOR gate /"~8T26A, Bus transceiver 74LS10, Triple 3-input NAND gate 74LS74, Dual "D" flip-flop, positive-edge-triggered 74LS125, Quad bus buffer with three state output 7416, Hex buffer 74LS174, Hex "D" flip-flop 74LS04,Hex inverter 74LS32, Quad 2-input OR gate 74LS20, Dual 4-input NAND gate 74LS32, Quad 2-input R gate Z80A, PIO 8T26A, Bus transceiver 74LS244, Line driver 74LS123, Dual Monostable multivibrator, AXX3014 AMX3557 AMX3552 AMX3551 AMX4261 AMX3558 AMX3565 AMX3552 AMX3557 AMX3555 AMX3557 AXX3015 AMX4261 AMX3864 retriggerable U26 U27 U28 U29 U30 U31 MC741C, Operational MC4024, V.C.O. 74S1 12, Dual J-K Amplifier flip-flop negative-edge-triggered 74LS74, Dual "D" flip-flop positive-edge-triggered 74LS00, Quad 2-input NAND gate 74LS123, Dual Monostable multivibrator, AMX3558 AMX3550 retriggerable U32 U33 U34 U35 U36 U37 8T28A, Transceiver 8T28A, Transceiver 7407, Hex inverter 74 LS240, Octal buffer 74LS244, Line driver 74LS123, Dual Monostable multivibrator, AMX4225 AMX3864 retriggerable MISCELLANEOUS Plug, jumper (3) Socket, IC, 40-pin Staked pins (40) 52 (2) AHB9682 HLO * U+-PIO' HLT UG-P not if-tti 34-mi Koto* J0-PZ0- « xocyci* J0-P2.2 — J^-PI"? - 5 HQiBUt a SYn cx* Jt-rie — J$-»67— I rt-pa a*KiM» H4-P» OAKOUT I] Figure 6. Floppy Disk Control ^ HLD # hlt ue->gs U-IB » r U37 ^ 4 uii-piz J.S/2S _1_C55 ALREADY yFW\ /fflFM* ON BOARD LS74 LS74 IS 7+ L/29 fl22 2.ZK ontroller Schematic Diagram - Sheet 1 53 HZ3 2.2.K *-SVO VW" ' PA '3* aoua JO - PM JUMPER A JL/MPEP B TO B TO C IF JF CPU CLOCK CPU CLOCK - 4 MHZ ^2MHZ AT iTtp-PSG. 4* DAT5* J0-P57 JJAT6* J-0 -P3S B £> £> CONTROL BUS II BUS CRT CONTROLLER HIGH SPEED TIMING signal (30 or 60 Hz) and a non-maskable interrupt request signal. multiplexer switches the control of address bus to either the CPU, depending on the RAM/Video RAM Logic Selection. The system block diagram also shows a video-board select MODEL blocks For example, the pulse-width adjuster block (as labeled in our block diagram) is simply an MSI monostable multivibrator with schmitt-trigger inputs. Its main function is to provide noise immunity and pulsewidth stability to the horizontal sync signal which is one of the CRTC outputs. Also, the Vertical sync goes through the viding diversified functions such as video timing and refresh memory MULTIPLEXER SELECT ^ RAM/VIDEO RAM VIDEO 3-STATE RAM BUFFER VIDEO BOARD SELECT LOGIC (MSP! SHIFT/LOAD & LATCH CLOCK RAM/VIDEO RAM SELECT LOGIC is ROM into a erator, then shifted to the video "escape", Figure RAM on the display monitor. key includes a high speed oscillator and enables the video and the Real Time clock. Data latched from the Display RTC&NMIRQ' PULSE WIDTH LOGIC ADJUSTER KEYBOARD CONTROL _ * DATA p, KEYBOARD BOARD P.C. SECONDARY DATA BUS ENABLE RTC INTERRUPT VIDEO ENABLE DISPLAY ENABLE CURSOR ROM CHARACTER GENERATOR SHIFT VIDEO REGISTER OUTPUT VIDEO MONITOR P.C. BOARD Figure 1. Block Diagram 57 THEORY OF OPERATION High Speed Timing This 4-bit counter (LS163) Refer to the Video/Keyboard Schematic. is synchronous. That is, all its Flip-Flops are clocked simultaneously so that the outputs The timing for the system from shown a dot-clock derived is crystal oscillator. This system clock is in the upper left corner of the schematic. It consist of a 12.48 MHz, fundamental-cut crystal in parallel with a resonant circuit that is composed of two inverters (part of U1) that are driven into their linear region by resistors R2 and R3 (470 ohms each). The waveform at pin 4 of U1 resembles wave at about 12.48 MHz. a "raw" square change coincident with each other when instructed by the count-enable inputs and internal gating. The DOT CLOCK triggers the four Flip-Flops form. The count is done wave. "clean" square through inverter U1 more signal looks like a is labeled RCLOCK. It goes 9 and comes out of pin 8 as It pin RCLOCK*. Notice that we are using the asterisk throughout the text as follows: entire RCLOCK is active high, "NOT RCLOCK" is active for. if, example, the signal RCLOCK* then which means this point,, that is . . . etc. This RCLOCK* goes RCLOCKP (RCLOCK prime) at pin 13 of U1, TCLK* the signals diagrams. PLCLK* and are shown on these Timing fairly reliable for comprehension pur- were not neglected. gates, We need in these different signals because each of these all own doing its a working team. signals is any member "specific job" just like CRT example the Well, for controller which, RAM the video which at CCLK enabled, for generating all these different clocks is that needed to synchronize the various activities of our system. That is, one activity that should take p)ace before another, or should occur 3 or 4 times while another one happens just once. RCLOCK is divided by 2 by a "D" Flip-Flop, pins 1 1 and 9 of U17. That is, its frequency is halved (12.48 MHz/2 = 6.24 MHz). It is then NANDed with the 80*/40 character Enable. When this then latch will it into the character PLCLK* U10. will shift load them them out of serially DCLK will toward the Video. Further explanation of the different parts of the system that need to be clocked will provide One subject of Timing Coordination. CRT more clarity to this of these parts is the controller. Cathode Ray Tube Controller (CRTC) For our video monitor display, Controller CLOCK, 12.48 at pin MHz characters). 8 of LS00 (for 80 (test point 26, TP26), characters) or at 6.24 at either is MHz (for 40 NAND gate, U28 (pins 1,2, and CLOCK goes through inverter become DCLK, which is the DOT Note that the used here as an inverter. U33 (pins 11 and 10) to CLOCK. Its frequency (either 6.24 rate at which information is MC6845, monitor with no receives is it in a parallel is detail in later sections of the text. 3), ROM, turn would send the appropriate dots to the its is low (active), 80 characters per line will be displayed on the screen; only 40 characters would appear otherwise (when high). This signal will be described in signal shift MC6845 triggers the would send an address to requesting data to be sent to the Latch (U8) TCLK* inputs. if fashion into the 8-bit shift register (U10) and timing best poses since the propagation delay times, due to the different shift register frequency (12.48MHz), but they are at different phases. different is low. through an inverter to give and again through a second inverter to yield RCLOCKP*. Up to this point all these clocks still have the same The reason wave its HEX) described by the Timing diagrams of Figure 2. Notice that both 80 and 40 character modes are represented here. Also How? At edge of rising 0, 9, A, B, C, D, E, F, 0, 9, A, B, C, These diagrams are At pin 6 of the same chip, the on the as follows" (in or 12.48 shifted to the MHz) CRT is the and dots new data The MC6845 we are using the Motorola a reliable processor that controls the CPU intervention, until the video memory to be processed. simplifies not only the design and the archi- tecture, but also the trouble-shooting of the video control board. sharply reduces the It have taken otherwise. This to raster scan CRT number of I.C. chips CRTC commands displays. It it would the interface also provides video timing and refresh memory addressing. The CRTC is a collection of registers, counters and comparators that time all logic are written. activities as CLOCK, which is a phase down by a 4-bit counter shifted DOT CLOCK, is divided (U26) to produce the characterrate clock labeled here as CCLK with a frequency of 12,48/ 8=1.56MHz (for 80 characters) or 6.24/8=0.78MHz (40 characters). consists the interfaced raster scan proceeds. generators, linear register, cursor logic, light-pen capture register bus. and control circuitry for interfacing to a processor CRTC permits easy timing and synchronization The of signals. It also handles raster graphics as well as alphanu- meric applications. 58 Its logic of programmable horizontal and vertical timing L M Ml [LI J ] ] Jx i UJ 1 k L ^x — Q ^ nhii Jr" nil 1 >< at 1 | O 1 — ' " M ° 1 i— I 1 n rr^r r i — n (A J JL £ 1 n Xi ~=» i J Fl p?3L — » 3 ' U — , E°> < i \ 1 r L" 1 1 n | I jpEl ' 1 1 J> > L- — -i i- 1 *-\ ?ol 1 1 i . i ° .£ I ^rin M if Wl \ i 1 win i Hrl *~~| ° 1— i ri 1 1 r 1— 1 1 r \ > ill bx . Ss 1 1 o 1 nrln 1 ilr 1JJ IrVrr nnr HnrFrrrr ITO jj t— H 0. UJUJO ocecoO D3qo - - o o o > " 1 ~~ o 3 « CO — u x n "do" qPria *-» o o > 59 It is fully programmable through the CPU data bus, thus generating timing for almost any alphanumeric screen den- sity. Therefore 1 up to the designer to choose any screen is 80X24, 132X20, etc. it is Processor Interface: . CRTC The tional data bus For example in our case we are using 80X24 and 40X24. That is, 24 lines with 80 alphanumeric characters each (for the 80 character mode) and 24 lines with 40 alphanumeric characters each (for the 40 character mode). One can set this screen .density by programming the registers of the CRTC. The CPU communicates with the CRT controller through a buffered 8-bit data bus by Reading or Writing into the 18 registers of the CRTC. the processor. The enable refresh addresses, of this row CRT addresses, controller best way of describing this controller refer to the pin description as explained in the microcomputer data labeled in is to is its or FD* is it is active active (U31, pins 7 and (RS) nal register file. w LPSTR /MA0 —— ». - -* ^ MAI MA2 MA3 MA4 REFRESH MEMORY MA5 MA6 — — — — * < 39 3 38 4 37 ^ RAI S 36 RA2 6 35 7 34 RA3 RA4 8 9 33 MC6845 CRTC D|Zf *~ ¥ •* 12 29 -* 13 28 *- 14 27 '* D2 D3 D4 15 26 D? 16 25 cs- RS MAI3 -* 17 24 Display Enable -* 18 23 Cursor -* 19 22 20 21 Vcc —* Figure 3. MC6845 - PROCESSOR INTERFACE D6 -* — — — DATA BUS D5 MAI2 -* I ROW ADDRESS FOR CHARACTER GENERATOR *. Dl 32 * > — 60 RA^ 31 MAI0 MAI *• Hsync 2 II MA7 MA8 MA9 m Vsync fc 4J2f I when either I/O port FC* 6). The register select line is an input which selects either the address register (RS = 0) or one of the data registers (RS = 1) of the inter- Figure 3. RES" high impedance active edge. processor. In our case Motorola chip. Vss a select (CS*) when low, selects the CRTC to read or write the internal register file. It is active (low) only when there is a valid stable address being decoded from the library. CRTC is The chip The following is a description The MC6845 controller is the schematics as U11 and is redrawn below in of every pin of the 23) of U11 to generate is video monitor timing MC6845 (pin compatible input which enables the data bus input/output buffers and clocks data to and from the CRTC. In our schematics the CRTC is enabled by either the RD* or WR* (U42 pins 11, 12 & 13). The high to low (horizontal and vertical sync), cursor and display enable. The signal TTL/MOS transition One primary function interfaces to the processor bus on the bidirec(D0-D7) using CS*, RS, E and R/W* for control signals. The data bus lines (D0-D7) are used for Data transfers between the CRTC internal register file and density he or she wants. That E CONTROL R/W ^ CLK Pin Identification The Read/Write (R/W*) determines whether the signal internal register file gets written or read. written It is when As you may know, everything 8x10 CRT cells and every Sync (HS), provides Horizontal Vertical Sync memory and CRTC (Memory Sync is an active high signal which drives the determines the vertical position of the displayed data. The Horizontal Sync is also an active high signal which drives the monitor. It determines the' horizontal posi- it will dot matrix of refreshed about 60 times in one 4.) The is a CRT beam is repetitively scanning the screen from top to bottom, refreshing every dot whose location is indicated by the coordinates that the display (VS) and Display Enable signals. The cell is second. (Refer to Figure Control: CRTC The displayed on the is fade away and disappear. Every character low and read when high. 2. that screen should be continuously refreshed, otherwise the character refresh address and ROM receive from the Row address). Vertical monitor. It tion of the displayed data. The Display Enable CRTC the an active high signal which indicates is its "valuable" time with this refreshing routine. However, every time the CPU addresses its upper 2K bytes of memory, it automatically takes control of the Video waste RAM. The reason is that these 2K bytes, starting at address F800H through FFFFH, overlap the video memory locations providing addressing in the active display area. is The CRTC takes care of this particular chore and the CPU would therefore do a more "smart" activity, rather than in Refresh Memory/Character Generator Addressing: 3. its Thus entirety. either the CPU this display or the CRTC, RAM can be accessed by but not by both at the same time. CRTC The Memory RAM. In MA10 2K Also big. memory provided are MA0 through capacity is only our case only are used, since our video bytes (MA0-MA13) which addresses provides the Refresh scan addresses Raster (RA0-RA4) for the character ROM. The Refresh Memory (MA0-MA10) are used to refresh the CRT screen addresses with pages of data located in 2K the block of Display RAM. Our approach memory is for solving character the character in a ROM. CRTC address Other Pins: The clock input signals. CCLK used to synchronize is our design this signal In (1.56/0.78 MHz). The is all CRT control the character-rate clock active transition high to is low. (LPSTR) is not used in our design. an active high signal, indicates cursor display to external video processing logic. The The Light Pen Strobe which cursor, When used to reset the is this signal is active, the CRTC. CRTC is All It is the counters in Now that CRTC are cleared and the device down CRTC are not affected. we have an overview of the CRTC what is meant by memory we programmed our CRTC internal a display shut sends lines its addresses as follows: consisting of MA0 through The first set MA10, of cycles lines of the character generator. These also cycle binarily, incremented with each horizontal retrace time. Again the horizontal retrace time is the period in which the CRT beam returns from the end of a scan line back to the but are beginning of the next one. The CRTC's of linear address generator repeats sequence of character addresses for each scan the same character row. the line same within in our case is 10 rows high, so it takes 10 separate accesses of a given character to write its 10 dotrows on the screen. So putting 80X24, or 1920, characters on the screen calls for 10X1920, or 19200, character 60 times every second. to low level. registers of the try to clarify permit is binarily through the display memory and is incremented with each clock pulse (CCLK); one per character displayed. The second set (RA0-RA4) addresses the row-address select accesses b) All the outputs go The control CRT beam The character block stops the display operation. c) Of course the forced into the following status: a) refresh is The Reset (RES*) input active low. the off during the retrace time. The 4. for anytime, but is synchronized by an interrupt to perform accesses only during the vertical retrace time. The vertical retrace time is defined as the time it takes the CRT beam to return from the end of the very last scan line, back to the start of the very first one. The Raster addresses (RA0-RA4) determine the row of contentions that the processor (CPU) gets priority access chip itself, let's refreshing. register 24X80/24X40 alphanumeric The way would file characters. The address of each one of these characters is stored in the display memory. That is the reason we are using only 2K of Video RAM (just enough to store the entire screen density). 61 First displayed character Last displayed character Video screen density: 80/40 x 24 characters. Only (1920) 1fj locations are displayed of the 2K Ram contents. Vertical spacing 1 between characters 2 1 2 3 - 4 5 6 7 8 ' Horizontal spacing between characters 9 ONE CHARACTER LOCATION Figure 4. Character 62 (Example of the upper case Dot Pattern letter A) The Multiplexers As you can see the schematics, in U24 and U25), LS157 multiplexers (U23, addresses between the processor and the The processor is memory are used for multiplexing refresh in control when refresh cycle, that is "within the screen", is the period is generation of a wait cycle. As MSEL* the select inputs (pin of 1 each chip) are high. When these inputs are low the control of the display is switched to the CRTC. MSP, the signal that controls the multiplexing from the RAM/VIDEO RAM Select Logic block. is derived which the is CRT beam shown on the schematics, clocks a high (U32 pin 15) that is inverted by U14 WAIT* state is interrupted whenever we have a RESET* or MSELP NANDed with Q, as shown by U2 pins 8, 9, 10, and U29 pins 8, 9, and 10. Note that when MSELP is high, the CPU pins 2 and 3 to give an active CRTC. in additionally protected by the is accepting the diaplay RAM WAIT* (U13 pins state. 4, 5, This and 6). Video Board Select Logic This part of our system could be called the port addressing RAM/Video The RAM block, labeled diagram of Figure Select Logic block. RAM/VIDEO RAM 1, is Select Logic, on the actually a sort of decoder. That when the CPU is addressing its upper 2K bytes of memory, located at F800H through FFFFH, address lines AD 11 through AD 15 become high (active). Also the is, Memory request signal activated by the is memory or cycle (MEMCYC) CPU. As you may know by now, activated everytime the CPU memory. Another important addresses any part of signal is is this signal the input to pin 1 1 with I/O Cycle signal (IOCYC) to give 3 Read ports (FCRD*, FERD*, and FFRD*; pins 9, 11, and 12). The other is enabled only by the ually be used for signal and one of the FC* or FD* ports could chip controller. Port is FF* NANDed with show us if we the CRTC. The following TP21 (U2 is ANDed MSP, the with MSLP (U13 pins 4, 5 & 6) to finally select input to the multiplexers. When this outputs could act- WR* select the gives MC6845 FFWR* (U3 pins8,9,and 10). Also the Input/Output address select (U27 pin 8 and U30 pins 12 and 13) is ANDed with IOCYC to give the I/O Select (IOSEL) to enable the 3-state buffers (U34and U35) to either Read from the CRTC(IOBIE: I/O Bus Input Enable) or Write into it (IOBIE*: I/O Bus Output Enable). Note that test points pin 6). give us its ports. In our design either of set to 1. If all these conditions are met, low and MSEL becomes high (U30 goes then pin 8 of U41 MSEL IOCYC Read or Write its NAND gate LS30, U41. This signal is used to enable the CPU to access the Video RAM if, and only if, our software says so. That time is when Port FFWR* is activated and bit 7 (D2 of LS175) It is using the lower eight lines of the address bus, as shown by U27 LS30,for the dual 2 to 4 line decoder (U31 LS155). One of the decoders is enabled only by Read NANDed ing into pin3) will TP22 (U13 pin 3) and from or writshows the port ad- are reading table dressing and the functions of every port. is high, the Video RAM is under the processor Note that when the Reset* button is hit (U32 pin the CPU loses that control (MSP becomes low). MSP signal control. 8), Table PORTADDR. FC 1. Port Addressing READ FUNCTION WRITE FUNCTION Read Keyboard data Load CRTC Load CRTC data address Register Clear Keyboard Interrupt CRTC FD Read FE Clear Real Data Register Register Time clock (RTC) interrupt FF Read Non-maskable Interrupt Register and Non-maskable Interrupt Mask Register. Load Memory Bank Select Register and load Non-maskable Interrupt Mask Register and Video enable. 63 For Example, Port FF a) is used as follows: Bit4(D4) Non-maskable Interrupt Mask Register and Bank Select - 80*/40 character mode* Register: Write only 0(D3-D0) 3 through Bits D7 D6 D5 D4 D3 D2 D1 D0 - They are "don't care" bits (not used) Bit7(D7) - if set (1), enables the 2K - bytes of the 2K bytes RAM Bank's Reset (0), disables Video if RAM, disables the upper (F800H RAM, FFFFH) to enables Bank RAM F800Hto FFFFH. Now we we know how that can set the control want FFWR* Therefore the we set bit 7 to - if signal is way we be writing into Port FF. 6 to 0, bit activated. 5 to If, for example, 1 ing results will be obtained: Video display (on) Video display off 0, enables if 1, say in Port FF, the will and bit 4 to 0, FFWR* data vector into our system and the follow- 1, bit will latch this Bit6(D6) we This means to. these different ports will be used, bits, 11 of U41 will be high, thus enabling the 2K byte Video RAM. BLNKVID*, Q3 (pin 14 of U18) will go high and disable the blank Video (Video on). Pin Bit5(D5) - Set Reset Time clock (RTC) enables the Real (1), (0), disables the RTC interrupt interrupts The Real Time clock (RTC), pin 3 of U18, is enabled. And finally we will get a low (0) at pin 7 of U18. This generated signal is what we previously called the 80*/40 character mode. In this case the 80* character mode is enabled (low). It Bit4(D4) is with - enables the 40 character 1, acter - Selects 1 (D3 of 16 the Reset, the b) - RTC pins 1, 2, and 3 and 10, Note how the disables the 40 charac- and then as CLOCK NAND interrupt is if OR gate U3 pins 4, 5, and 6 we is drawn as a H~_^°-C the same as this gate 01 "B hit Non-maskable Interrupt Mask Register: Read only is A HjJ^C B disabled We sometimes show the OR gates as above, because using mostly active low signals. we are We can go from one gate to another just by using DeMorgan's Theorem. For the above example, we have: D7 D6 D5 D4 D3 D2 D1 D0 * AB= A+B=A+B=C 80* /40 character mode RTC gate gate. This gate banks. Note that NANDed NAND (TP26). A D0) memory 8, 9, U30 to appear at the output of the char- mode Bits 3 through - 80 character mode, RCLOCK* U28, pins mode 0, enables the ter mode and disables the 80 inverted at interrupt enable Now Video display enable* if we want vate the signal to enable the 3-state buffers LS240, produce the status of the KBIRQ*, the BLNKVID*, the 80*/40 character mode* and the ENABLE RTC INT* as shown at the inputs 2, 4, 6 and 8 of U38. U38. This Keyboard Interrupt Request (KB IRQ) to Read the Status of Port FF, we'll acti- FFRD* will Bit7(D7) Other Blocks — — 1, 0, Keyboard interrupting No Keyboard interrupting Bit6(D6) — — 1, 0, Video Display disabled Video Display enabled The 3-state Buffers (U37) are enabled by either the Video Read (VRD) or Video Write* (VWR*). VRD is the result of the RD signal ANDed with MSP (U13 pins 11, 12, and 13). VWR* is the output of WR NANDed with MSP (U2 pins 4, 5, and 6). When the CPU wants Bit5(D5) VWR* — RTC Test points interrupt enable goes low (pin from the Video RAM, to write data into the Video 1 of U37). VRD TP2 and TP24 (high) will is RAM, does a reading active (pin 15 of U37). it help us detect from or written into the Display 64 When RAM if data by the CPU. is read The keyboard control LS74 Flip-Flop (U17 mode. That is, when consists of an NMIRQ* The RTC and logic block takes the by 2 (U16 pins pins 2, 3, and 5) showing the keyboard divides from the keyboard, a busy signal is sent to the system bus at the end of every word (8 bits of data). A busy (active low) signal goes from pin 5 of U17, back to the keyboard processor telling it to stop sending data. Also the same signal goes toward the CPU under the name of Keyboard. Interrupt Request (KBIRQ*), telling it that a word of data is ready to be read. Data is clocked serially out of the keyboard into the shift register (U6), and RTC. The 60/30 Hz RTC data is being clocked in then latched into the system data bus when FCRD* Note that when Flip-Flop U17, pins 2 and activated. or BUSY* becomes 3) signal goes high FCRD* set (disable). and the Now board logic does not receive the active busy start port is activated (low), the is KBIRQ* that the keysignal, it will sending data again. the keyboard in the pulse labeled serial End of Data It is generated at the end edge latches a low to This low signal (KBIRQ* or Its rising U17 pin 5. BUSY*) informs the CPU that the output of leaving and VSYNC signal, to yield a 30 6) word is ready to be read. It also prevents the keyboard from sending more data until the actual 8 bit word at the output of the shift register a (U6) is buffered into the data bus the CPU). pin 9 to generate an RTC interrupt (RTC INT) which is ANDed with ENABLE RTC INT (U29pins 12 and 13). The output of U29 (pin 11) is then inverted and goes to the system bus as a Non-maskable Interrupt Request we can (NMIRQ*). Note that by activating Port FERD* The pulse-width of this text. It adjuster is NMIRQ* clear this (Flip-Flop U16 signal pin 13). as defined in the earlier section consists of a monostable multivibrator with inputs schmitt-trigger that pulse-width stability to the provide immunity and sync signal (U5, noise horizontal 74121). The remaining parts of the system block diagram, such as the Latch, the character ROM, the Shift Register, . . . can be better defined by "tracing" the data path as follows: (in word of data into the Video RAM. The which automatically displays the Video contents on the Video screen, moves that word and The CPU CRT writes a controller, RAM stores it temporarily in the Latch. the byte for processing so that the The Latch RAM will retain can get ready to send the next byte. other words, read by END OF DATA PULSE DATA MSB LSB {FROM KEYBOARD) 1 r I I I I I I t:_t~ ii CLOCK J5" (from keyboard)- Hz signal clocks a high into the out- fashion. Notice the narrower pulse. of an 8 data bit sequence. is U16 put of 2, 3, 5, signal etc. The timing diagram of Figure 5 shows how data it bDsy (fromcomputer)- -U T, 10/isMIN T T2 1/isMIN T6 1/isMIN T3 IjUsMIN T7 IjusMIN T4 1/jsMIN T 1/js 5 IfjsMIN 8 MAX Figure 5. Keyboard Timing Diagram 65 The Latch (U8) is an LS273. When activated (byTCLK*), U8 would latch the data word into the character ROM (U9) These various dot patterns are loaded into the shift register U10, in a parallel fashion and are shifted out of it serially. in ASCII form. Note that the 8th bit is used as a Reverse Video signal (REVID). U9 is the character generator. The seven bit ASCII Word applied to its inputs would address a certain area in it. These ASCII inputs are considered the higher seven bits of an address. The lower part of the address comes from the CRTC (RA0-RA4). This lower part selects the row position of the addressed dot pattern. Of course Each character consists of a dot matrix, 8 dots wide and 10 dots deep. Since each character consists of a pattern of dots, there must be some method to determine which dot should be on and which dot should be off to form any one characThe character generator controls the dot patterns on ter. the screen. this all character tire done so is dots (on or off) at the same time. RA0 through RA4 would of course select the row of the addressed pattern. The character generator must output 10 times to build one character. Here is how a typical character line is written: Assume an ASCII word is is in the Latch. The electron beam scan line of the character. Hence, the row adbinary "0". That is, RA0 through RA4 are low. U9 on the dress is first are outputted. We now TADCLK cycle with respect to the (U4 pins 9 and This the electron beam doesn't stop at the last in mind that dot of the row first of VOUT signal. This is U4 is is also Exclusive ORed with VOUT 10). to say that either the cursor, the Reverse Video or the Video would be displayed in a character location, but not two of them at the same time. The signal outputted at pin 8 of U4 is finally enabled by the Display enable and either one of the RCLOCK, RCLOCK*, RCLOCKP and RCLOCKP* ing We signals. gave ourselves the option of choos- one of the four clock (Ground Keep output the shown by U12. Note how the delayed cursor and DREVID are Exclusive ORed (U4 pins 12 and 13). The resulting "1" pointing to the second scan line. are ready to through before being outputted at pin 9 of U10 (V out), one can see that the V out signal is delayed quite a bit with respect to the Display Enable and Cursor signals. For this reason, these two signals are delayed by two TADCLK cycles and Reverse Video (REVID) is delayed by one The first seems that the en- the second character line. Following the path data goes dot pattern for that particular ASCII character. The next ASCII character is applied to U9. At the same time, the row address is incremented. It is now binary outputs the it After the eight dot scans are outputted, the electron beam is turned off and two rows (the 9th and 10th) of blank dots signal at pin 11 of U9 outputs 8 fast that displayed not "in pieces" but as an entity. is call signals to achieve a better result. we get at pin 12 of U15 is what we simply VIDEO. The VIDEO, HSYNC, and VSYNC signals are final signal separately shielded signals are and sent to the CRT Logic board. wrapped around them.) first pattern, but goes on scanning the rest of the entire scan line. By the time the second dot pattern goes out, the third ASCII word comes in. character (10 rows) is CONNECTOR PIN This process goes on until the entire written on the screen. J2 CONNECTOR J3 SIGNAL DESCRIPTIONS SIGNAL DESCRIPTIONS SIGNAL DESCRIPTION SIGNAL 'IN NAME DESCRIPTION Data from Keyboard Key - No Connection Clock from Keyboard Busy to Keyboard +5V Keyboard Ground to Keyboard 6o to 1 2 3 4 5 HSGND VSGND HSYNC VSYNC KEY 6 VIDEO 7 VIDGND Ground Ground Horizontal Synchronization Vertical Synchronization Horizontal Synchronization (prime) Vertical Synchronization (prime) No Connection Video Signal Video Ground E 8 i o S > 1 > 67 Q at < 00 „, >-Q — ui ^ i/t Q£ mQ 9o > <« CO o I "E 3 a. 1 s > 1 >to .1 1 "N 68 * •; lifiM ,J || JMfe -- ~ mk j* 111 A 1^ 3"8b -.HuoBk • * VIDEO/KEYBOARD INTERFACE BOARD PARTS SYMBOL LIST MANUFACTURER'S PART NUMBER DESCRIPTION RADIO SHACK PART NUMBER ELECTRICAL PC Board 8709048 CAPACITORS 25V, Ceramic Disc 50V, Monolithic 1000pF, 50V, Ceramic Disc 0A(iF, 50V, Monolithic 8303102 8374104 8302104 8374104 50V, Monolithic 50V, Electrolytic, Axial 33juF, 50V, Electrolytic, Axial 15pF, 50V, Ceramic Disc 150pF, 50V, Ceramic Disc 8374104 8316334 8316334 8300154 8301154 C1 0.01/xF, C2 C3 C4 0.1/iF, C25 C26 C27 C28 C29 O.ljixF, 33/uF, ACC103QFCP ACC102QJCP ACC336QJAA ACC336QJAA ACC150QJCP ACC151QJCP CONNECTORS J2 6-pin right angle J3 7-pin right angle 8519017 8519022 AJ6765 AJ6770 8207247 8207147 8207147 8207339 8207247 8207247 8207247 8207247 AN0247EEC AN0169EEC AN0169EEC AN0330EEC AN0247EEC AN0247EEC AN0247EEC AN0247EEC 8409004 AMX2570 8020004 8020000 8020032 8020086 8000121 AMX3552 AMX3550 AMX3557 RESISTORS R1 R2 R3 R4 R5 R6 R7 R8 4.7K, 1/4W, 5%, Carbon Film 470 ohm, 1/4W, 5%, Carbon Film 470 ohm, 1/4W, 5%, Carbon Film 39K, 1/4W, 5%, Carbon Film 4.7K, 1/4W, 5%, Carbon Film 4.7K, 1/4W, 5%, Carbon Film 4.7K, 1/4W, 5%, Carbon Film 4.7 K, 1/4W, 5%, Carbon Film CRYSTAL Y1 12.48 MHz INTEGRATED CIRCUITS U1 U2 U3 U4 U5 74LS04, Hex inverter 74LS00, Quad 2-input NAN D gate 74LS32, Quad 2-input OR gate 74LS86, Quad 2-input exclusive OR gate 74121 ,Monostable multivibrator single, not retriggerable U6 U7 U8 U9 U10 74LS164, 8-bit parallel-out serial 74LS244, Line driver 74LS273, Octal "D" flip-flop 231 6E, Mask ROM, 450ns access 74LS165, Parallel-load 8-bit shift U11 6845, U12 U13 74LS174, Dual "D" flip-flop 74LS08, Quad, 2-input AND gate CRT controller shift register register 8020164 8020244 8020273 8043316 8020165 8050845 8020174 8020008 AMX3864 AMX4227 AXX3019 AXX3565 69 VIDEO/KEYBOARD INTERFACE BOARD PARTS SYMBOL MANUFACTURER'S PART NUMBER DESCRIPTION INTEGRATED CIRCUITS U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 U37 U38 U39 U40 U41 U42 , RAM, RAM, RAM, RAM, 1024-by-4bit 1024-by-4bit 1024-by-4bit 1024-by-4 bit 74LS157, Quad 2-to-1 line selector/multiplexer 74LS157, Quad 2-to-1 line selector/multiplexer 74LS157, Quad 2-to-1 line selector/multiplexer 74LS161 Synchronous 4-bit counter 74LS30, 8-input NAND gate 74LS00, Quad 2-input NAND gate 74LS08, Quad, 2-input AND gate 74LS04, Hex inverter 74LS155, Dual 2-to-4 line decoder/demultiplexer 74LS76, Dual J-K flip-flop with preset and clear , 74LS04,Hex inverter 8T26A, Bus transceiver 8T26A, Bus transceiver 8T26A, Bus transceiver 8T26A, Bus transceiver 74LS240, Octal buffer 74LS240, Octal buffer 74LS240, Octal buffer 74LS30, 8-input NAND gate 74LS00, Quad 2-input NAND gate RADIO SHACK PART NUMBER (Cont'd) 74LS33,Quad 2-input NOR buffer 74LS1 1 Triple 3-input AND gate 74LS74, Dual "D" flip-flop positive-edge-triggered 74LS74, Dual "D" flip-flop positive-edge-triggered 74LS175, Quad "D" flip-flop 2114, 2114, 2114, 2144, LIST (Cont'd) 8020033 8020011 8020074 8020074 8020175 8040004 8040004 8040004 8040004 8020157 8020157 8020157 8020161 8020030 8020000 8020008 8020004 8020155 8020076 8020004 8060026 8060026 8060026 8060026 8020240 8020240 8020240 8020030 8020000 AMX3554 AMX3558 AMX3558 AMX3566 AMX3563 AMX3563 AMX3563 AMX3556 AMX3550 AMX3552 AMX3552 AMX4261 AMX4261 AMX4261 AMX4261 AMX4225 AMX4225 AMX4225 AMX3556 AMX3550 MISCELLANEOUS Plug, jumper (2) Socket, IC, 40-pin Socket, IC, 24-pin Socket, IC, 18-pin Stake pin (24) 70 (4) 8519021 8509002 8509001 8509006 8529014 AJ6769 AJ6580 AJ6579 AJ6701 AHB9682 SVSTEM BUS-^ -= Figure 8. Video/Keyboard Interfa looopf _L © TP-f YNC >HSVNC'C3) >VSYNC'(M) > VS <3A/D (fc) CRT CONNECTOR CMOLfX 309* >vio**/o 7 CIRCUIT (7; >DDISPEN >DCURSOR CDISPEM SYSTEM IU> NOT BU USED RfWT ? US e UIO a« Interface Schematic Diagram (Sheet 1) 71 3 TtRwvAt ?/*/*> Of S U4P-7 U2-I2. , 1^ LSOS U/3 iosie: U34-/5, UI3 Lsoa Ai /J35 uo -^ XOSCt. ©TP2I vsywc U25-3, UZ4-/3, A07 uai-s ua-* AQ6 U3P-7 U4 -; - UI6 u LS74 LS >CK CK Q I Lias , - U£7 uea-ia, UM-q ad ~ U23-C, U40-* 4D4 U2S-/0, U40-lfc A03 — U24-6, U40-<4 ADZ — •5 LSOS -WW— R7 uza-6, u40-teADi UM'24 uia-io U40-5 uai- U26-ID IOCYC ?-Q FCRD* yaK U3I - -^ senses * ^ LSI5? 4.7K FERC HI 0^- LS30 5 1-532. "^FFWfi u, * 7:7n -FERO* UI6-/3 -FFRQ* ADO 3^ LS0C UZ UJ"7-5 LMO-7 USD1 , UI3-Z ua-ia u/a LSOS VRD MSP Ull U3G-/S, "57 3X.A/M TP 13 ADIB /dq 3 LINE BUS D7 THRU !2- \ UIVi "7 msf CAM61C RTC 1 L$30 "\ Li A) U32 M£T«CYC U3B AD! I* 34 srs BUS [ 19 -I , 12. tO*/HO CM+* iJ3^ "IS - QO* Qi#- IVMIWT Ql dO Qi RFC M*5K ->>BLJJ, FFWR # UI5-3 LS 175 DO PI P£ / °4/ OT-X RES£ ^ UB-t J) U3D-I Ofc/ <-- I* "I "I '« "I -ll 7l "' TP2.1 US4 ST2S BUS TP © 7 © +Sv- '-4HH I I . n4/ SI \/ \[/ \l/ \/ CWT4* OUTS* 55 CMTS« 57 0*77* \i/ CMT2* DAn* 52 \1/ \i/ st,' DATfil 53 MT3* 54 svs ttm C2-S0 BUS BUS 56 58 , I M/ ;J U/7 L£7f Q a J P«fTB OF IC« WOT U6EO il tie (>.< 32. CK CK Q uae-e ft (? Figure 8. Video/Keyboard Interface Scr 72 x KMIRQ # 7 12 SYS BUS r— XOSEL-U,a - S U3I-I2 "7»D* TP25 © > SELECT* 43 SKS BUS TPia © ?MSP U23-I, U24, U25 LS00 VWR # U36-I WR 04 = , U37 1 KB ^MSELP +SV ui«-2 a MSEL* -^ENABLE RTC INT u 2»- a -^ 80*/4C> CAM* EK). U2s-i,z, U32-<2 u — RESET * 3 US-/ USD -10 iJ/l-2 112Q-IO U32 -a ft/26 -13) Q ' RESET* U//-2 , , U32 TP27 © face U/B-l , U30 -/O LS33 -^ easy WA T 7-0 «ej U32.-I3 ;j> -r^DAT/t (FhO.1 KB) I 48 WAIT* BUS I * /1NO 'In KB) («J ->KBfR ADDRESS BUFFERS IO PORT MULTIPLEXERS LOGIC MEMORY DISABLE LOGIC • Figure 76 1. Block Diagram IOPORT LOGIC is Memory C. JUMPER OPTIONS The following table lists all Memory the jumper options. Also refer to Figure 2. Memory Bank Jumpers Memory Page Jumpers Memory Bank Page J16-J17, J15-J18 1 J9-J13.J10-J14 J19-J27 r J9-J11, J10-J12 J19-J27 J20-J28 2 1 J7-J11, J8-J12 3 1 J9-J13,J10-J14 J20-J28 4 2 J7-J11, J8-J12 J21-J29 5 2 J9-J13,J10-J14 J21-J29 6 3 J7-J11, J8-J12 J22-J30 7 3 J9-J13,J10-J14 J22-J30 8 J7-J11, J8-J12 J23-J27 9 4 4 J9-J13,J10-J14 J23-J27 10 5 J7-J11, J8-J12 J24-J28 11 5 J9-J13,J10-J14 J24-J28 12 6 J7-J11, J8-J12 J25-J29 13 6 J9-J13,J10-J14 J25-J29 14 7 J7-J11, J8-J12 J26-J30 15 7 J9-J13,J10-J14 J26-J30 'Jumper configuration for add-on 32K memory board. A 32K memory board will have 64K memory board will have Page For example: The first and jumpers Page and Page 1 as above. and jumpers as above. D. VERIFICATION PROCEDURES 1. Automatic RAM verification is performed on the memories during the boot procedures. If an error is MF error CRT screen. encountered, an center of the is displayed in the 2. Further testing can be done on the system mem- by using the Diagnostic Diskette and the TRS-80 Model II Troubleshooting Manual. ories WARNING IMPORTANT NOTE When performing The test procedures below should never be attempted by an unqualified technician. If the diagnostic instructions are not followed correctly the computer video can and probably will be damaged. We strongly suggest that if these procedures are necessary, you should re- a test that includes turning the CRT do not leave it off for more than three seconds or damage to the circuitry may occur. on and off, turn your unit to Radio Shack. 77 s _ "»"» • I * *-l rf> C=D * • £•»•* J =^ -> ? r» J r- t*t . m m —t O £ 3c_ so- 3 <=> a 8 -cz> c £zz S <* CO ld £ "D iSZZ < o s: CO o m (M CO -c=> £ o s 8 £ szz 5 UJ O -[ £ J -CZD- £ z o Q. s o SZZ CD- 4> c D D < o o y ije: 3 c o o a IB ac CD CO »> C O £ = 2 i — osn in s Qzzzzifc ]j H> {= > C! izziDs igEzzzjife *[ am sn dSezzziO 8 D > s[ $ # I J en E i g inn »n zen ijezz zn igEZZHQiSQ E sin igEzzzpij zz:@zzzdQ — lg sin in so- s i SO- SO' •a- ll 78 Q» tfcn so- °9 Kg r«H <=5 S o I ^m fe 5, r fe 'Mr i iioir ji i fl iioir j ~WmTZ Zp^Z. mfl | SiT**!! ——— i <-> X— i • r— iT i .i i s aifc • « • 1 ' : i i i .1 i1^Sir.»i".^-i^S*a irll ifi i |?lb |S um r lot r w> I 1 I IDL =0£ f !! °Q s ' ' J* en 1 " iCT r JML i gs "bo- iCIl ' ' ' 8s K "SO- " "' *S0 iml ' Is ri '* S 79 8 CO I .E D s 1 .1 MEMORY BOARD SYMBOL (32K & 64K) PARTS LIST MANUFACTURER'S PART NUMBER DESCRIPTION RADIO SHACK PART NUMBER ELECTRICAL PC Board 8709053 CAPACITORS 50V, Monolithic 8374104 C12 C13 C14 0.1aiF,50V, Monolithic 8374104 8325472 8374104 C24 C25 C26 0.1mF,50V, Monolithic 4.7(j.F, 25V, Electrolytic C37 C38 C39 C40 0.1aiF,50V, Monolithic C1 0.1/iF, 25V, Electrolytic, PC 0.1mF,50V, Monolithic 4.7juF, 83741 04 8325472 8374104 0.1juF,50V, Monolithic 33;uF, 25V, 4.7mF,25V 0.1juF, 8374104 8316332 8325472 8374104 Electrolytic, Axial ; Electrolytic, PC 50V, Monolithic C47 C48 C49 0.1juF,50V, Monolithic 0.1juF,50V, Monolithic 8374104 8316332 8374104 C55 C56 C57 C58 50V, Monolithic 33mF, 25V, Electrolytic 4.7juF, 25V, Electrolytic 0.1mF, 50V, Monolithic 8374104 8316332 8325472 8374104 C65 C66 C67 C68 0.1/iF, 50V, Monolithic 25V, Electrolytic 10mF, 16V, Electrolytic, PC 33/zF, 25V, Electrolytic, Axial 0.1/zF, 50V, Monolithic 8374104 8316332 8326101 8316332 8374104 *C69 33/uF, ACC475QFA 25V, Electrolytic 0.1/uF, 33juF, ACC475QFA ACC475QFA ACC475QFA RESISTORS R1 f R2 R3 R4 R5 R6 R7 R8 4.7K, 1/4W, 5%, Carbon Film 1K, 1/4W„ 5%, Carbon Film 4.7K, 1/4W, 5%, Carbon Film 4.7K, 1/4W, 5%, Carbon Film 4.7K, 1/4W, 5%, Carbon Film 100 ohm, 1/4W, 5%, Carbon Fi Im 4.7K, 1/4W, 5%, Carbon Film 220 ohm, 1/2W, 5%, Carbon Fi Im *May appear on your Board in 8207247 8207210 8207247 8207247 8207247 8207110 8207247 8217122 AN0247EEC AN0196EEC AN0247EEC AN0247EEC AN0247EEC AN0132EEC AN0247EEC AN0149EEC combination with zener diode. Part Number 8150230. 81 MEMORY BOARD SYMBOL (32K & 64K) PARTS LIST (Cont'd) MANUFACTURER'S PART NUMBER DESCRIPTION RADIO SHACK PART NUMBER INTEGRATED CIRCUITS U1 MK41 16-3, 16K RAM MK4116-3, 16K RAM 7400, Quad 2-input NAND 74S04, Hex inverter U11 74S64, 4-2-3-2 input AND-OR inverter with totem pole output 74LS33, Quad 2-input NOR buffer with open collector outputs 74S74, Dual "D" flip-flop positive-edge-triggered 74S08, Quad 2-input AND gate U13 U14 U15 MK4116-3, 16K gate RAM *U30 MK4116-3, 16K, RAM 47 ohm DIP resistor pak, 16-pin 74S00, Quad 2-input NAND gate 74LS00, Quad 2-input NAND gate 74LS20, Dual 4-input NAND gate 74LS10, Triple 3-input AND gate 74LS02, Quad 2-input NOR gate 74S139, Dual 2-to4 line decoder/multiplexer MK4116-3, 16K RAM *U37 MK4116-3, 16K, U38 *U38 U39 39 ohm D IP resistor pak 1 6-pin 22 ohm DIP resistor pak 16-pin 74157, Quad 2-to-1 line data selector/multiplexer U22 U23 U24 U25 U26 U27 U28 U29 AXX3024 9040016 8000000 8010004 8010064 AXX3024 I U8 U9 U10 U12 9040016 RAM 8020033 8010074 8010008 9040016 AMX3558 9040016 8290004 8010000 8020000 8020020 8020010 8020002 8010139 9040016 AXX3024 ARX0169 9040016 8290002 8290005 8000157 AXX3024 AMX3550 AMX3555 AMX3551 AXX3024 AXX3024 ARX0167 ARX0170 with non-inverted data outputs U40 74157, Quad U41 2-to-1 line data selector/multiplexer with non-inverted data outputs 74LS133, 13-input NAND gate U42 U43 200ns DIP delay 74LS138, 3-to-8 line >U44 MK4116-3, 16K RAM *U51 MK4116-3, 16K RAM 8T26A, Bus transceiver 8T26A, Bus transceiver 74LS240, Octal buffer 74LS240, Octal buffer 74LS240, Octal buffer 74LS240, Octal buffer 74LS273, Octal "D" flip-flop common clock U52 U53 U54 U55 U56 U57 U58 single 82 rail line output decoder /multiplexer 8000157 8020133 8429004 8020138 9040016 AMX3927 AMX4264 9040016 8060026 8060026 8020240 8020240 8020240 8020240 8020273 AMX3024 AMX4261 AMX4261 AMX4225 AMX4225 AMX4225 AMX4225 AMX4227 AMX3024 MEMORY BOARD SYMBOL (32K & 64K) PARTS LIST (Cont'd) MANUFACTURER'S PART NUMBER DESCRIPTION RADIO SHACK PART NUMBER VOLTAGE REGULATOR tVR1 tMay MC79L05AC, 5V, 5%, TO-92 - case 8051905 AMX4260 8150230 ADX1211 8519021 8509003 8509003 8529014 AJ6769 AJ6581 AJ6581 also appear as: VR1 1N5231,Zener diode MISCELLANEOUS Plug, Jumper (5) Socket, IC, 16-pin (16) *Socket,IC, 16-pin (32) Stake Pin (52) 'Used only on the 64K RAM Memory AHB9682 Board. 83 /4/4 Figure 5. Memory Bo< ffi>SeLECT cz cs, c 14, cia czo C27 cat C 2Q C 12 C44, c-*, ce, , cis V , , , C33 C40 , , , , , ces, ceo.c&.CBZ, ce,* cs* CIS CI/ , ' , c«, a?/, C32 C4I o.?e , C*3. cse czo, , C« , C47 CI C3 C5. C7. C«I0«* AlS.* AfiZX AI3* AM* ^J.^-K mory Board Schematic Diagram 85 SECTION VII VIDEO MONITOR (CRT) 87 VIDEO MONITOR (MOTOROLA) A. FUNCTIONAL SPECIFICATIONS A General Information single circuit card with components mounted on one numbers are printed, on both sides of the circuit card to aid in the location and identification of components for servicing. side models are direct drive, requiring separate TTL vertical/horizontal drive and video inputs. All use 12" CRTs of the magnetic deflection type with integral implosion protection and require a power input of +12 volts@ 1.2 amps. All is used. Schematic reference Circuitry consists of one stage of video amplification, two stages of horizontal deflection processing, and three stages of vertical deflection processing. Input and output connections for the monitor are made through a 10-pin circuit card edge connector. The inputs are video, horizontal drive, vertical drive, system ground, and +1 2 volts. SPECIFICATIONS SPECIFICATION ITEM Cathode Ray Tube: 12" measured diagonally (305 mm); 74.86 square inches (483 sq. cm); 90° deflection angle; integral implosion protection, P4 phosphor standard. Power Input: TTL Level Direct Drive Input Signals: VDC + 12 1 .5 5V to at 1.2 amps typical, 1.5 amps maximum. P-P Horizontal: 10 to 30 microseconds positive-going drive. Vertical: negative-going sync. Video: positive white Video Response: Bandwidth within 3dB, 10Hzto 15MHz Pulse Rise Time: 30V rise in less typical. than 30 nanoseconds. Horizontal Blanking Interval: High Voltage: Scanning Frequency: Resolution: 1 1 microseconds 12kV (includes retrace and delay). typical. Horizontal: 800 minimum 15,750Hz+ 500Hz; Vertical: lines center, typical. Geometric Distortion: within 2% measured with Linearity: within 10% measured with standard EIA Controls: 50/60Hz. — Internal horizontal standard EIA vertical size, ball chart and dot pattern. ball size, chart and dot pattern. vertical linearity, internal brightness. External Unit Weight: Environment: 8% lbs. — brightness control, video level (contrast). (3.86 kg). Operating temperature: 32°F to 131°F (0°C to +5E°C). Storage temperature: NOTE: Models -40°F to 1E0°F (-40°C to +6E°C). with bonded anti-reflective faceplates should not be subjected to storage or operating temperatures above 122°F (E0°C). Operating altitude: 10,000 ft. maximum (3046 meters). 89 SAFETY WARNING CAUTION: NO WORK SHOULD BE ATTEMPTED ON AN EXPOSED MONITOR CHASSIS BY ANYONE NOT FAMILIAR WITH SERVICING PROCEDURES AND PRECAUTIONS. 1. SAFETY PROCEDURES habit so that pair 2. is when should be developed by the technician work, he automatically takes precautions. A GOOD PRACTICE, when to working on any testing circuitry. This will avoid the pos- sibility of carelessly putting one hand on chassis or ground and the other on an which could cause PICTURE TUBE connection electrical Do as rough handling may cause lbs. not nick or scratch glass or subject any undue pressure removal or installation. in ISOLATION THIS TEST. In addition to practicing the basic and fundamental electrical safety rules, the following test, lated to the minimum is returned. - 1000 OHM/VOLT (OR HIGHFRI AC VOLTMETER NOTES: 1. per 2. , to it re- is Underwriters Laboratories should be performed by to it which safety requirements of the the service technician before any unit which has been HANDLING THE in implode due to atmospheric pressure (14.7 in.). DO NOT USE A LINE TRANSFORMER WHEN MAKING danger of electrical shock. serviced a severe electrical shock. Extreme care should be used sq. unit, ground the chassis and to use only one first hand when 3. rushed with is re- REPEAT EACH CHECK WITH THE LINE CORD REVERSED IN THE POWER OUTLET. METER READING MUST NOT EXCEED 7'/. VOLTS AC. "HOT" LEAD OF METER TO EACH EXPOSED PART OF CABINET AS WELL AS THE CABINET When . handling, safety goggles and heavy gloves should be worn Discharge protection. for picture by tube GROUND LEAD OF METER TO ANY EARTH GROUND SUCH AS A COLD WATER PIPE ' shorting the anode connection to chassis ground (not When discharging, cabinet or other mounting parts). go from ground to anode or use a well insulated piece of wire. 4. An ISOLATION TRANSFORMER should always be used during the servicing of a unit whose chassis connected to one side of the power former of adequate power rating and electrical shocks. its It Use is Voltmeter Hook-up for Safety Check a trans- as this protects the serviceman from accidents resulting from line. will also personal injury in protect the chassis components from being damaged by may dental shorts of the circuitry that acci- be inadver- A 1000 ohm per volt it with as Always REPLACE PROTECTIVE DEVICES, fishpaper, shields after 6. If the ways be isolation resistors working on the HIGH VOLTAGE ADJUSTED the manufacturer. If such prepared by is held in etc., contact with a good "earth" ground such as a cold water pipe. and capacitors and unit. is is hardware, controls, knobs, while the other probe 5. voltmeter a as the cabinet trim, tently introduced during the service operation. AC 1500 ohm, 10 watt resistor. The safety test is made by contacting one meter probe to any portion of the unit exposed to the operator such shunting adjustable, to the level the voltage it should al- recommended by is increased above the normal setting, exposure to unnecessary X-ray The AC ceed Th voltage indicated by the meter volts. A may not ex- reading exceeding 7V4 volts indicates that a potentially dangerous leakage path exists be- tween the exposed portion of the unit and "earth" ground. Such a unit represents a potentially serious shock hazard to the operator. radiation could result. High voltage can accurately be measured with a high voltage meter connected from BEFORE RETURNING A SERVICED service technician certain that 90 it is must thoroughly test plug reversed, the anode lead to chassis. 7. The above UNIT, the test the unit to be completely safe to operate without should be repeated with the power when applicable. NEVER RETURN A MONITOR which does not pass the safety test until the fault has been located and corrected. . . B. SERVICE NOTES Of course, these precautions, with the exception of step b, only apply 1. power Circuit Tracing: off. If if the machine is to be serviced with active test instrument troubleshooting is to be done and power must be on, be very aware of Component numbers reference and bottom of the three cuit tracing. Control are printed on the top where your hands are and remain alert. High voltages can harm you and even low voltages can harm circuits when unintentional shorting of wires and subassemblies circuit cards to facilitate cir- names are also shown and refer- enced on the schematic diagram. 2. CRT occurs. Replacement: CRT Replace the C. as described in section F. Additional 1. ADJUSTMENTS Brightness/Contrast Adjustment precautions to be observed are as follows: A Use extreme care ling may Do cause it in CRT, handling the as to implode, due to high rough hand- vacuum not nick or scratch glass or subject sure. it is recommended when performing pres- to any undue pressure in removal or installation. Use goggles and heavy gloves for protection. Also, be sure to disconnect the monitor from all external voltage sources. Use caution around the heat sinks of the horizontal vertical output transistors. The heat sinks are at the same potential as the transistor collectors. During and normal operation with a non-metallic tool the following adjustments. a. b. Rotate the Internal Brightness control, R11, to minimum c. (fully clockwise). Rotate the External Brightness control to imum signal input present, the hori- zontal heat sink has 130 volt P-P pulses and the vertical Rotate the Contrast control to minimum. its max- position. d. Rotate R11 to the threshold of the e. Adjust the Contrast control for the desired video heat sink has 75 volt P-P pulses (with respect to system raster. ground). level. 3. Before working on the Video/Model II, observe these f. precautions: a. Adjust the Remove all jewelry. g. Brightness The following adjustments the b. External control for the desired brightness level. Discharge the two tors (on the Astec large grey high-voltage capaci- Power Supply) across their Diagnostic Diskette will require the use of and the Troubleshooting Manual: own terminals with an insulated screw driver. Vertical Size/Linearity NOTE Adjustment Focus Adjustment Be sure to ground the discharging tool with a clip wire to ground before attempting to dis- Horizontal Size Adjustment charge the capacitors. Video Centering c. On the Motorola Video Board, discharge capacitor C6 and very carefully discharge to ground the thick, red to black high-voltage second anode Raster Yoke Adjustments lead. Pincushion/Barrel Correction WARNING Trapezoidal Correction. This lead (black) plugs into a sleeving that goes to the CRT Driver Board while the other lead (red) connects to the CRT shell. Discharge by unplugging the lead from the sleeving near the Driver Board and shorting the lead to chassis ground. lead! The Do 12000 CRT not touch the conductor of this volts reside here! socket, deflection anode lead can now be safely yoke and the second removed. 91 D. A. B. TROUBLESHOOTING GUIDE There are basically six areas that may cause the loss, distortion or non-adjustment of video. These areas are: 1 System Power Supply 2. Video Generator Module 3. Motorola Video Board Listed 5. CRT 6. High voltage leads from the Deflection Coil their possibles causes CRT and remedies: REMEDY POSSIBLE CAUSE SYMPTOM video at Cathode Ray Tube (Don't overlook any of the interconnecting wiring between these assemblies.) below are some of the symptoms and No 4. or Power Supply or any Check voltage from Power Supply at pin 7 of the plug connecting at the top of the Motorola Video Board. NOTE: Pin 1 is to combination of the above the back of the system. Voltage should be Video Generator Module all or Motorola Video Board approximately 12 No VDC. voltage indicates a bad Power Supply. Check pin 6 of the same plug for peak-to-peak signal 1 15,750 Hz. If no a 2 volt of approximately signal is there, replace the Video Generator Module 2 . Check pin 8 of the same plug for approximately 1 .5 volts peak-to-peak signal 1 . If no signal is present, replace the Video Generator Module. Thin horizontal or vertical line Deflection coil Replace Deflection Yoke. Q7 on Motorola Video Replace Q7 and, with power off and green and blue wires disconnected, check continuity across deflection coil where green and blue wires are hooked up. An open, on video screen; no video where on screen else- Thin horizontal line Board or high resistance, indicates a defective deflector coil. Thin on Motorola Video Board 0.4 vertical line Replace Q4 and, with power off and red and black wires disconnected, check continuity between the points that the red and black wires are connected to. An open, or high resistance, indicates a defective deflector coil. Video is off center screen on Adjust Video Centering Magnets for best Video Centering magnets on deflection coil need to centering of video be adjusted jewelry and use caution, remember, the system Bad focus 92 is on screen (remove on!). R30 as necessary for sharpest NOTE: Be careful not to short the R30 of the Motorola Video Board needs to be focus. adjusted adjustment tool to other components. Adjust all REMEDY POSSIBLE CAUSE SYSTEM Insufficient brightness R11 of the Motorola Video Board needs Adjust brightness on front bezel of the computer to mid-travel then adjust R11 adjusting of Motorola Video Board to desired screen brightness. screen 3 No Sync on no horizontal or vertical Video Generator Module 4 Replace U11 (Video Controller ). (VGM) problem High voltage leak or With power off and capacitors discharged, check high-voltage leads for breaks, kinks or placed too close to motherboard brackets. Position wires toward the Motorola Video Board and away from the motherboard area. Also, bad CRT's have been is not corrected, replace If the VGM. hold and intermittent dropping out and reappearing Jittering of video leaks of video dots on the screen known Motorola Video Board has been replaced and still have no video Video Generator Module to cause this Replace symptom. U4 (74LS86) and U15 (74LS11) (VGM) NOTES: 1 2. These measurements should be observed with an oscilloscope, not a volt meter, as a volt meter will measure average duty cycle voltage and not represent the true peak-to-peak swing of the signal. In some cases it may be necessary to replace both the Video Generator and the Motorola Video Board simultaneously to repair the system. 3. 4. No thin horizontal/diagonal lines under high contrast settings is one way to check for sync. Turning brightness and contrast pots to maximum will allow you to view these lines. U11- Video Controller (MC6845). 93 E. THEORY OF OPERATION The M3970 Resistor R'3 provides the collector load for the video Series monitors are direct drive units requir- ing separate video, horizontal sync puts. All are monitor is TTL and vertical sync output signal. The amplified video is fed forward and direct coupled via R34 to the cathode of the CRT. in- compatible. Power supplied to the Horizontal Driver +12 V. The The monitor tal Driver, A Video Amplifier, a HorizonHorizontal Output stage and two stages of consists of a Vertical Deflection (see Figure 1. Block Diagram). horizontal drive signal, input at pin 6 of P1, must be TTL compatible and a series of positive-going pulses of approximately 27.5 Msec duration (see Figure 2). In addition, the leading edge of the pulse may be coincident with the end of the video. If desired, the user may decide to delay the horizontal pulses (approximately 1 .3 Msec) to attain centering of the video within the Video Amplifier The TTL compatible video signal, input at pin 8 of edge connector P1 is direct coupled via R2 to the base of the Video Amplifier Q1. R1 is used as the load resistor for the video signal source. The RC network (R4, raster. , R5 and C1) provides Q1 with increased gain at high fre- quencies by altering the collector-emitter load resistance ratio. only At low frequencies, C1 appears as an "open" and is in the circuit. At higher frequencies, C1 R4 "shorts", thereby shunting R4 with R5, lowering the emitter load resistance and increasing the emitter-collector resistance creases. Therefore, the gain of 0.1 ratio. Approximate voltage gain of this stage is in- 25 V. At the end of the video period, the horizontal drive signal goes positive and is coupled through C2 and R6 to the base of Horizontal Driver No. 2 (Q3). Q3 "turns on" drawing current through D1, R10 and C3. This action pulls the base of the Horizontal Output stage (Q4) low, forcing it into "cut-off". Approximately 27 Msec later, the negative-going trailing edge of the hori- zontal drive pulse switches Q2 Q3 to conduct. Base current the network R9, is off, now which then allows provided to Q4 via R10 and C3. The RC network, R10 and C3, is a speed-up network in the base circuit of Q4. It is used to increase the collector switching time of Q4. VIDEO P1-8 IN POWER IN (B+) VERTICAL DRIVE VIDEO <4- * P1-7 /A ~^\1 PI -9 CRT OUTPUT ° .„„ IIU +12V IN VERTICAL DISCHARGE CIRCUITRY /A \T" VERTICAL DRIVER/OUTPUT CIRCUITRY on _J YOKE SYS. GIMP. SYSTEM SYSTEM GROUND P1-1 <4PI -10 GND. 1. «- ZL P1-5 HORIZ. P1-6 DRIVE P1-2 NOT CONNECTED HORIZONTAL DRIVER/OUTPUT CIRCUITRY <4- <4 HIGH VOLTAGE HIGH P1-3 LOW P1-4 WIPER TO EXTERNAL BRIGHT <4 Figure 94 1. Block Diagram (Motorola and RCA) At the end of the video period (horizontal drive going positive), the drive pulse at the base of Q4 goes low, Q4 to cut off. This produces a retrace pulse occurring at the end of each line or sweep period that quickly drives the electron beam from the right to the forcing left side The +300V source supplies the second grid, G2, of the CRT, in addition to the variable focus bleeder resistor. The +12kV supplies the second anode of the CRT with B+. Vertical Deflection of the screen. Coincident with the retrace pulse, is the dissipation of the yoke current as determined by the LR time constant of the yoke, the primary windings of T1, and the The When the electron beam travels to about the center of the screen, Q4 turns on to form a current path from the +12V supply through the yoke (L2B)., the Horizontal Size (L3), and the Horizontal Linearity of action of D9. (L4) coils, to complete the raster line. The retrace tuning capacitor, C4, forms a tuned circuit with the inductive components of the yoke, L2B. The linearity coil, L4, provides optimum horizontal linear- by shaping the deflection current per the amount of magnetic biasing as determined by the position of its core. The two RC networks, C17 and R39, and C16 and R38, provide damping for the coils L4 and L3, respectively, which eliminates any ringing effects in the ity circuits. Horizontal Output Transformer vertical drive signal, a negative-going short dura- tion spike, is supplied to the unit via pin 9 of edge conis direct coupled to the base nector P1 This drive signal . Q5 high, via Q5 R15. When the is ward +12V false or the Vertical Driver stage. When the vertical drive signal goes true or negative, Q5 conducts, discharging C8 and C9 to nearly zero volts* This action forms the retrace portion of the sawtooth waveform. Q6, an emitter follower configuration, transforms the high impedance of the sawtooth waveform into a low impedance drive for Q7, the vertical output stage. vertical output transistor, Q7, provides the required sawtooth waveform of current through vertical choke L1 and vertical yoke L2A. When Q7 is at minimum current flow during retrace, a large pulse voltage is de- The field collapses. The high voltage by D5 and R27 connected to the +60V source. The yoke coupling capacitor, C10, blocks any DC voltage to the yoke which can cause de-centering of the raster. The resistors R25 and R21 couple the emitter voltage of Q7 to the junction of C8 and C9. Because this path is resistive, the waveform coupled back will be integrated into a parabola by C8. This action pre-distorts the drive sawtooth and allows oppulse appears at the collector, utilizing the electrical path through D5 and R27. The +60V and the -110V are applied across the brightness pot, R11. In addition, these voltages provide enough range to allow the blanking pulses to turn off the CRT beam during retrace. is This charging action generates a linear positive-going ramp (sawtooth waveform) applied to the base of Q6, veloped as the yoke Transformer T1 produces secondary voltages via the auto transformer action of the primary winding. The transformer produces +60V, -110V, +300V and +12kV. The +60V supply is used as B+ for transistor Q1. At Q7, this voltage limits the peak voltage that vertical drive signal cut off allowing C8 and C9 to charge tothrough the network of R17, R18, and D4. is limited timization of the vertical linearity adjustment. HORIZ. DRIVE PULSE HORIZ. DRIVE PULSE at BASE OF CM Figure 2. Horizontal Drive Signal (Motorola and RCA) 95 w N * £5; t«. I<- CC CO O CO p." „ 2 o *i CA 5 § o o o c -1 .t; is — c = I £ 3 .21 iZ 96 2o B o 3 (0 e o >Z -6 I DO 2 «* 3 cn 97 F. INSTALLATION Cathode Ray Tube Preliminary Checkout The 12-inch CRT and associated components, which make upthe basic M3970 video monitor kit, are mounted and shipped components in a cardboard shipping carton. All are properly interconnected for operation. Simply fabricate the mating plug for the edge connecon the rear of the monitor circuit card (refer to As with any glass implosion always present envelope vacuum tube, the danger of if dropped or mishandled. Even though the CRT used in this kit has integral implosion protection, handle the CRT with extreme care, is and wear safety glasses. Do not carry the neck or apply excessive pressure. CRT by its Figure 6). CRT may be positioned with its high voltage cap (second anode connection) either left or right; however, To be sure that the cap has a minimum of 1-inch clearance from any metal shield, bracket, etc. tor remove the kit from the shipping carton or remove the kit from the pallet and open the cardboard shipping housing, pretest the kit before final installation, (see Figure 5). WARNING A if the monitor is operated in the shipping carton or on the cardboard shipping board for any length of time. Be sure that adequate ventilation is available to keep the ambient temperature in the monitor housing below +131°F (+55°C>. fire hazard exists The To mount the CRT in its final operating location, use No. 8 type hardware and the holes in each corner of the CRT. After final installation, check to be sure that the CRT aquadag spring is positioned properly and grounded via a black wire to the monitor circuit card. Check to be sure that the bleeder resistor, R14, nected to the ground lug (see Figure 4). CRT AQUADAG GROUNDING SPRING ANODE CONNECTOR YOKE MOUNTING PIN FOR RASTER ADJUSTING MAGNETS L2A/B DEFLECTION YOKE L1 (IN D3 LEAD) (IN R14 LEAD) VERT. CHOKE T1 H.V. XFMR P1 MONITOR CIRCUIT CARD EDGE CONNECTOR Figure 5. Model 98 M3970 - Series Kits, Rear View (Motorola) is con- Monitor Circuit Card After final installation, be sure the CRT aquadag spring is connected via a black wire to the circuit card (refer to Figure 4). The monitor circuit card is mounted vertically on the power supply bracket. Use four No. 6 type screws and hardware to secure the circuit card. Refer to section C. ADJUSTMENTS, and perform the steps as necessary. Do not allow any wires to lay on top of, or alongside any power transistor heat sinks on the circuit card. High heat dissipation could melt the wire insulation. In addition, be sure the yellow wire (CRT cathode connection) from the circuit card to pin 2 of the CRT socket does not lay near any metal or horizontal cir- - NOTE At the time of the dure, ter it will initial installation proce- be necessary to perform the Ras- (Yoke) Adjustment Procedure. cuitry. P1 MONITOR CIRCUIT CARD EDGE CONNECTOR (FOIL SIDE SHOWN) KEYWAY SLOT 10 9 8 7 6 5 4 3 2 1 ^HllWlll _t t_ SYSTEM GROUND TTL VERT. DRIVE INPUT VIDEO INPUT +12V DC B+ TTL HORIZ. DRIVE INPUT EXTERNAL SYSTEM GROUND (NO CONNECTION) (NO CONNECTION) DIRECT DRIVE MODELS AEPC-01005-O POSITION r BRIGHTNESS CONTROL V KEYWAY INSERT BETWEEN PINS 9 AND FROM PIN SIDE 10 cQIfflgWWglCfr I (WIRING SIDE SHOWN) MATING PLUG FOR CIRCUIT CARD EDGE CONNECTOR AMPHENOL PART NO. A-MP 583299-1 Figure 6. Monitor Circuit Card — Edge Connector (Motorola and RCA) 99 G. GENERAL SERVICING PRECAUTIONS *»*CAUTtON**« Before attempting to service the monitor, disonnect (or turn off) the external power supply; then, as an added precaution, dis- CRT second anode before handling any high voltage components. In addition, be sure to observe all safety warnings and service notes in the front of this manual. charge the When it is and/or the When disconnecting the H.V. rectifier, D3, pull it out of the high voltage lead holder slowly and carefully to prevent breaking or deforming the short rectifier lead. Use caution around the heat sinks of the horizontal and vertical output transistors. The heat sinks are at the same potential as the transistor collectors. During normal operation with a signal input present, the hori- 130 volt P-P pulses and the vertical heat sink has 75 volt P-P pulses (with respect to system ground). zontal heat sink has necessary to disconnect the deflection yoke CRT socket leads, pull the small female pins straight out, with no back and forth rocking motion. This action will prevent, or at least, minimize the possibility of bending the male pins on the components and/or breaking the solder connections. VIDEO MONITOR (CRT) EDGE CONNECTOR -J1 POWER SUPPLY +12V RET. H. SYNC H. S. GND. V. S. GND. V. SYNC VIDEO VIDEO GND. KEY VIDEO/KEYBOARD EDGE CONNECTOR Figure 7. 100 Video Wiring Harness (Motorola and RCA) VIDEO MONITOR {MOTOROLA) PARTS LIST SYMBOL DESCRIPTION C1 0.001/iF, Z5F, 100V, Disc C2 C3 C4 C5 C6 C7 C8 C9 C10 15V, Tantalum 0.68/zF, 35V, Tantalum 0047/iF, 200V, 10%, Poly 0.047/uF,400V, 10%, Film 2000/iF, 35V, Electrolytic 22/iF, 160V, Electrolytic 5/xF, 15V, Tantalum 5juF, 15V, Tantalum 470juF, 16V, Electrolytic 0.01juF,400V, 10%, Film 22juF, 160V, Electrolytic 0.0027MF, Z5F, 500V, 20%, Disc 0.01//F, 400V, 10%, Film 0.01/xF,400V, 10%, Film 0.0022/zF, Z5F, 500V, 10%, Disc 0.0022aiF, Z5F, 500V, 10%, Disc 0.047MF, 400V, 10%, Film 100juF, 16V, Electrolytic C11 C12 C13 C14 C15 C16 C17 C18 C19 MANUFACTURER'S PART NUMBER RADIO SHACK PART NUMBER 21S180B07 23S10218A31 23R29976A01 8S10072A44 8R29959A02 23S10255A06 ACC102NCLP ACC505QPTP ACC684QGTP ACC473QDEP ACC473QTGP ACC208QGAP ACC226QNAP ACC505QPTP ACC505QPTP ACC477QDAP ACC103QTGP ACC226QNAP ACC272QUCP ACC103QTGP ACC103QTGP ACC222QUCP ACC222QUCP ACC473QTGP ACC107QDAP 25D25221A01 24D25830A01 24D25603A16 24D25600A15 ACA8030 ATA0770 ACA8031 ACA8022 48R191A02 48R191A02 ADX1330 ADX1330 ADX1331 ADX1332 ADX1330 ADX1330 ADX1330 ADX1333 ADX1333 5/iF, 8R29959A02 23S10255A11 23S10255A74 23S10218A31 23S10218A31 23S1 02255 A29 8R29959A01 23S10255A74 21S180C41 8R29959A01 8R29959A01 21S180C39 21S180C39 COILS/CHOKES L1 L2A/B L3 L4 choke Yoke, Deflection Coil, Width Coil, Vertical Coil, Linear DIODES/RECTIFIERS D1 Rectifier, Silicon, 91 D2 D3 D4 D5 D6 D7 D8 D9 Rectifier, Silicon, 91 Rectifier, Diode, A02 A02 48S1 37608 H.V.,D9H 2054 48R02054A00 48R191A02 48R191A02 48R191A02 48R191A05 48R191A05 Sil icon, A02 Silicon, 91 A02 Silicon, 91 A02 Silicon, 91 A05 Silicon, 91 A05 Rectifier, Silicon, 91 Rectifier, Rectifier, Rectifier, Rectifier, RESISTORS Note: Only power or special resistors are listed. Use the description when ordering standard values of fixed carbon resistors up to 2 Watts. R3 R6 R7 R8 R9 R10 R11 R12 R14 1.5K,5W, 5%, Wire Wound 470 ohms,0.5W, 10%, Composition 10K,0.5W,5%, Film 1.5K,0.5W,5%, Film 47ohms,0.5W,5%, Film 100 ohms, 0.5W, 5%, Film 500K, Potentiometer 100K,0.5W,5%, Film 240M,2W, 20%, Ceramic 17-136062 6-125C41 6-101 64B32 6-101 64B01 6-10164A78 18D25245A07 6-101 64 A80 6R29978A01 AN0206FKB AN0169EFB AN0281EFB AN0206EFB AN0099EFB AN0132EFB AP-7038 AN0371EFB ARX0173 101 VIDEO MONITOR (MOTOROLA) PARTS LIST (Cont'd) SYMBOL MANUFACTURER'S PART NUMBER DESCRIPTION RESISTORS R17 R22 R25 R28 R29 R30 R32 R33 R34 R35 R36 R37 (Cont'd) 50K, Potentiometer 5.6 ohms, 1W, 5%, Composition 1.5K, Potentiometer 22K,0.5W,5%, Film 18K, RADIO SHACK PART NUMBER 1W,5% 2M, Potentiometer 3.9M, 0.5W, 5%, Composition 6.8 ohms, 0.5W, 5%, Film 470 ohms, 0.5W, 10%, Composition 56K, 1 .5W, 10%, Composition 56K, 1 .5W, 10%, Composition 470 ohms, 0.5W, 10%, Composition 18D25245A20 6-126B63 18D25245A10 6-10164B54 6-001 26A79 18D25245A12 6-125B36 6-101 64L1 6-125C41 6-125C91 6-125C91 6-125C41 AP-7039 24D25240A27 ATA0771 48R 137093 48R137172 48R03006A00 48R03025A00 48R137127 48R 134997 48 R 137598 AMX4233 AMX4234 AMX4235 AMX4236 AMX4237 AMX4238 AMX4239 96R2500A15 42D25298A13 9D25241A08 59B25840A01 AXX8002 AN0052EGB AP-7040 AN0311EFB AN0281 FGB AP-7041 AN0460EFB AN0054EFB AN0169EFB AN0345FFB AN0345FFB AN0169EFB TRANSFORMERS T1 Horizontal Output TRANSISTORS Q1 A5F Q2 Q3 Q4 Q5 Q6 A6J MPS-A05 BU807 P2S A3K B2Y Q7 MISCELLANEOUS CRT, 12", 90°, P4 Anode Connector VI CRT Socket Yoke Magnet Aquadag Spring 1 inch Spacer Yoke Lead Terminal Lugs Aquadag and Bleeder Wire Lugs P.C. Panel Picture Tube Socket Heat Sink for Q4 Video Harness 102 41B25685B01 43S10865A01 29S10134A71 29S10134A55 84-25561 C93 9-25241 A08 26-25834B01 AJ6750 AJ6751 ART2572 ARB6637 AHB92U8 AJ6753 AJ6752 AXX0312 AJ6751 AW2436 £1 I s s A » 5s §; ®Tki 2" ss«-o * ~ S * "- I i * 5 > * K 3 < " ; '5 < Sa £ ?eg a! ;;; S3 * * ^1 s 10ptec/Div found. failures can be Figure 4. D. ¥• ^ will approximately 2 volts magnitude every 50 /xsec. If these spikes are not there, then control module should be replaced, especially if no other show SOjiMC Q1 Base Waveforms PERFORMANCE TEST Each of these test conditions should to be within the limits specified Input Test 3 4 +24 Load -12 Load Max Max Max Max Max Max Max Max Max Max Max Max Min Min Min Min Min Min Min Min 135V AC 135 VAC 95VAC 5 *On + 12 Load 135VAC * test 3, be set-up and noted Table 2. +5 Load 95VAC 1 2 in input voltage should be varied over after correct outputs are TABLE noted 2. at full range to search for instability 135 VAC. VOLTAGE AND RIPPLE SPECIFICATIONS MAX NO LOAD OUTPUT MIN +5 4.90V 5.10V - +12 11.40V 12.60V - +24 21 .20V 26.40V 30.0 V -12 -1 1 .40V -1 2.60V - RIPPLE 50mV P-P 100mV P-P 250m V P-P 50mV P-P 121 OPERATING CHARACTERISTICS Operating Voltage Range Line Frequency Output Voltages V01 V02 V03 V04 V03, no MAX 95 190 115 230 135 270 VAC VAC 47 50/60 63 Hz 4.90 11.40 5.00 12.00 24.00 -12.00 5.10 12.60 26.40 -12.60 V V V V 30.00 V A A A A 21.20 measured at connector. 101 2.15 4.3 8.6 I02 103 104 1.25 2.25 4.5 1.3 1.7 0.05 0.1 0.2 OCP, Current Limit NOTE: V04 is ICL1 9.0 11.0 14.0 ICL2 ICL3 ICL4 4.6 5.5 7.0 1.8 2.5 3.5 1.0 2.0 6.25 7.00 5.94 R01 2.3 R02 R03 R04 130 50 100 250 50 V02 V03 V04 70 Efficiency VOS 122 1.0 VUS TRUS Hold Up Time: Full Load Lo Line Full Load Nom Line 80 mVp-p mVp-p mVp-p mVp-p % 0.3 V01,25%to75%TROS Load Step M ohm M ohm M ohm 590 Output Noise V01 Load Transient A A A A a thermally protected IC regulator. OVP, Crowbar VCB1 Output Resistance UNITS specified for balanced loads. All voltages Output Loads TYP 21.20 11.40 load tolerance NOTE: V01/V02 MIN 0.3 10 16 mSec V 1.0 mSec 18 mSec mSec 30 OPERATING CHARACTERISTICS (cont'd) MIN TYP 100 100 100 1000 1000 1000 MAX UNITS Insulation Resistance Input to Output Ground Output to Ground Input to M ohm M ohm M ohm Isolation Input to GND Line Conducted (Reference VDE and Op KVDC 4.24 EMI 0875) MHz MHz 50 MHz 0.15 to 0.5 1.0 0.5 to 5 0.5 5 to 0.5 mV mV mV 123 re E u CO > a "a 3 CO a) aO o CO o < < rtt- -CZ3- KF JS - -%]- -cz> -CZh /' 124 SECTION X CARD CAGE and MOTHERBOARD 125 A. DESCRIPTION The card cage provides mechanical support for and electrical connections to the digital electronics boards. The main component of the card cage is the Motherboard, which holds eight 80-pin card edge connectors. Four of these connectors in the following order, are used for the (slot CPU FDC Memory Video If your system is shipped with If your system is shipped with Shack. Another boards required by the basic system. These cards should be closest to the power supply) one being the connector Slot 1 Slot 2 Slot 3 4 Slot 64K of RAM you will have four connections open for future additions. 32K of RAM, you can add another 32K by returning the unit to Radio 32K board for future expansion of will be added to the card cage your system. in Slot 5, leaving still CARD CAGE AND MOTHERBOARD PARTS SYMBOL QUANTITY DESCRIPTION three connectors open LIST MANUFACTURER'S PART NUMBER RADIO SHACK PART NUMBER CAPACITORS C1 470/LtF, C2 C3 C4 C5 C6 470//F, 16V, electrolytic, axial 16V, electrolytic, 50V, monolithic, 50V, monolithic, axial 0.1;uF, axial 8327471 8317471 8317471 8374104 8374104 0.1 mF, 50V, monolithic, axial 8374104 radial 470juF, 16V, electrolytic, axial 0.1/uF, ACC477QDAP ACC477QDAA ACC477QDAA HARDWARE Nut, Hex, #4 6 Screw, 4-32 x %" (1 2.7mm) Screw, 6 x %" (6.35mm) 6 Washer, flat 12 Washer, flat, nylon, #8 4 1 8579012 8569033 8569040 8589002 8589022 AHD-7166 820722 829002 829002 AN0216EEC 8729015 8729011 8719052 8729013 8509014 8509015 8893430 ART-2686 ART-2682 AHB-9439 ART-2684 AH D- 1542 AHD-1547 AHD-8500 AHD-8519 RESISTORS R1-17 RP1 RP2 2.2K,y4W,5% Resistor Pak, 390 ohm Resistor Pak, 390 ohm 17 1 1 ARX-0167 ARX-0167 MISCELLANEOUS Bracket, Bracket, PC PC Left side Right side Card Guide Card Guide Support Connector, 80-pin card edge J1 Connector, power Motherboard Assembly AJ-6762 AJ-6763 AXX-0500 127 MOTHERBOARD (80-PIN BUS) SIGNAL DESCRIPTION SIGNAL NAME PIN DESCRIPTION USER0 USER1 User Definable 4 GNO GND Power Ground Power Ground 5 +12V Positive 12-Volt 6 + 12V Positive 7 GND GND Power Ground Power Ground Positive 5-Volt Power Positive 5-Volt Power 11 +5V +5V INTRQ* 12 NMIRQ* Non-Maskable Interrupt Request 13 IEIN Interrupt Enable In (in) 14 IEOUT BAKIN* Interrupt Enable BAKOUT* BUSRQ* Bus Acknowledge Out (out) SYNC* RD* Z-80M1 WR* MEMCYC* Write Z-80 MEMRQ IOCYC* A00* A01* A02* A03* A04* A05* A06* A07* A08* A09* Z-80 IORQ 1 2 3 8 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 User Definable 1 Power Power 2-Volt Maskable Interrupt Request Out Bus Acknowledge Bus Request Read (out) (in) Op-Code Fetch) in Progress (out) in Progress (out) (Memory Cycle (I/O Cycle Address Bit in Inverted (out) Address Bit 2 Inverted (out) Address Bit 3 Inverted (out) Address Bit 4 Inverted (out) Address Bit 5 Inverted (out) Address Bit 6 Inverted (out) Address Bit 7 Inverted (out) Address Bit 8 Inverted (out) Address Bit 9 Inverted (out) A10* A11* A12* A13* A14* Address Bit 10 Inverted (out) A15* RES DISRO* Address Bit 15 Inverted (out) Address Bit Inverted (out) 1 1 Address Bit 12 Inverted (out) Address Bit 13 Inverted (out) Address Bit 14 Inverted (out) Reserved for System Expansion RAM Output (in) DMA Transfer Request (in) 42 43 44 45 46 KBIRQ* SELECT* Keyboard Interrupt Request Board Selected (out) CLOCK 4MHz System REFRSH* 8MHz Z-80 i— Disable RAM Times I— Two (in) Clock (out) Refresh Signal (out) System Clock (out) i—i * 128 1— Progress) (out) Inverted (out) 1 XFERRQ r-» in (out) Progress) (out) 41 LJ (in) In (in) (Indicates Address Bit (in) LJ LJ LJ LJ "CT- TTncr u I MOTHERBOARD {80-PIN BUS) SIGNAL DESCRIPTION (cont'd) SIGNAL NAME PIN DESCRIPTION 47 48 49 50 RTC WAIT* Z-80Wait Request GND GND Power Ground Power Ground 51 DAT0* DAT1* DAT2* DAT3* DAT4* DAT5* DAT6* DAT7* Data Bit ©Inverted (input/output) Reserved for System Expansion 66 67 RES RES RES RES RES RES RES RES RESET* 68 69 70 HALT* System Reset (out) Z-80 Halt Indication (out) GND GND Power Ground Power Ground +5V +5V Positive 5-Volt GND GND Power Ground Power Ground 75 76 -12V Negative 1 2-Volt -12V Negative 1 2-Volt Power 77 +12V Positive 1 2-Volt 78 + 12V Positive 1 2-Volt Power 79 GND GND Power Ground Power Ground 52 53 54 55 56 57 58 59 60 61 62 63 64 65 71 72 73 74 80 Real Data Bit 79 n 77 75 60Hz) (out) Inverted (input/output) 1 Data Bit 3 Inverted (input/output) Data Bit 4 Inverted (input/output) Data Bit 5 Inverted (input/output) Data Bit 6 Inverted (input/output) Data Bit 7 Inverted (input/output) Reserved for System Expansion Reserved for System Expansion Reserved for System Expansion Reserved for System Expansion Reserved for System Expansion Reserved for System Expansion Reserved for System Expansion Positive 5-Volt 73 or (in) Data Bit 2 Inverted (input/output) 'Indicates an inverted signal, or an active r Time Clock Heart Beat (30 71 low 69 Power Power Power Power signal. 67 65 63 61 59 57 55 53 -CD 51 49 47 O O _ -E3- 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 129 0) o R E n 3 QQ 3 U O Q. o IS .O 0) DC 130 131 SECTION XI KEYBOARD UNIT 133 A. INTRODUCTION The keyboard of the TRS-80 Model file, II is low pro8021 micropro- a 76-key, capacitive keyboard that utilizes an The keyboard in is connected to the main console by a cable to an external cable from the console (see Figures cessor chip. The microprocessor and its associated electronics scan the Figure 1 shows the 1 and 2). internal connections key matrix, convert switch closures to an 8-bit digital code and then transmits that code serially to the keyboard interface on the Video/ Keyboard Card. PC Board The keyboard map nector to the Video/Keyboard to the female from the keyboard in the keyboard DIN connector case. Figure 2 shows the external connection from the (Figure 3) presents the actual code that TRSDOS will board, each of the four modes in return to the user for each key — on the key- built- bottom front of the PC Board in DIN con- the Video Dis- play Console. unshift, shift, caps and control. KEYBOARD PC BOARD CONNECTOR J1 DATA BLU KE Y YEL CLOCK VIO BUSY RED +5V ORN GND Figure 1. Keyboard Internal Cable VIDEO/KEYBOARD INTERFACE BOARD CONNECTOR CONNECTOR, MALE (WITH CABLE) Figure 2. Keyboard External Cable 135 o o CM O o o os <•> UJ CM 8 0» in s «D 8 A O o LU LL t- n o < UJ a. 8 UJ QC D o s Q O O 9 U. *O LL. t/1 X * a> Q O < m n o Q M. i- a m f- (o io m « < O m < O tM U. 2S§S O r» < S < S u. IB o o n < O o s r> gi F* a ai >. !=i OS in (S 09 10 CD o » o e ai ip CO Ok O O O Q 5 * o OS OD O « U < S o s IO o 01 — Ml UJ IO 10 8 S 8 S OB 01 ift £ O O CM 91 r- O » U 10 O •* U (O IO <0 ; t « • IO <2 < m in io tn IO 10 m ID g « n 8S 88 = SSR 0*0(0 3 S 2 3 * * *. ^ IO O » U IO ao <•» < n M im os — oo ui 2 Q oa f. pi n IO 10 £ £ o C w o o 2f O * » <*> IO O * U IS - m 5 < w s o H u. « (T K ^ I o o IO o CD -J V) cc h- a. o Q 2 UJ < o o en a UJ .-I 136 I w z o in 3 o D H(- H H(- — L =:» 1> > a- o. a. a. E' to *HH E A n at a 5 o cj m «r in to o O '^ Figure 5. Rear 146 is #1 : 1 DISK FUSE 'Pit A View of the TRS-80 Model II # AC POWER Microcomputer SECTION XIII DISK EXPANSION UNIT 147 A. INTRODUCTION The power Supply protection. The TRS-80 Model II Disk Expansion Unit is storage device designed to interface with the a II regulated and has overcurrent is ply addi- 50Hz or 60Hz 95V AC to 270V AC. The Power Sup- operate at either be jumpered for either 135 VAC or 190V AC to TRS-80 Computer to provide the user with an tional storage capacity of up to 1 .5 Megabytes total system capacity of 2 Megabytes on line. Model will may input and mass It located in the rear and to the is left of the CRT. for a 3. Disk Drive: The Disk Expansion Unit is available in a 1, 2, or 3 drive configuration. The 1 and 2 drive units may be upgraded with additional drives from your Radio The Shack dealer. cording formats. All of the disk drive control sig- disk drive an 8" flexible disk unit capable is of supporting both single and double density re- come from the Floppy Disk Controller PC board in the computer. The drive contains two motors; one is an AC motor which rotates the nals Expansion Unit consists of up to three flexible disk drives, a power supply and a cooling fan. It connects to the Computer through a flat ribbon The Disk diskette at constant speed, the other cable. DC Standard 115/120 VAC is applied to the expansion unit through a power switch where it is distributed to the three disk drives, the internal power supply and to its DC which signals. is The DC the "ON" AC input to three levels NOTE: Models routed to the disk drives for their logic figured +5 and -12. A LED up" when the power switch is voltages are +24, on the fron panel in is a read/write head into correct format. cooling fan. The power supply converts the of motor motor which positions the read/ write head over one of 77 tracks on the diskette. The electronics on the disk drive control the stepping motor and convert the signals from and to the stepping "lights with for overseas AC an shipment may be con- Motor for the line voltage available in that country and may be fitted with different drive pulley for 50 Hz line a frequency. position. 4. Wiring Harness: Subassembly Description disk expansion unit consists of seven major sub- assemblies. Each subassembly single component of the may be If is accomplished with one wiring harness assembly. considered as a disk expansion system. wiring of the disk expansion unit internal All The It a includes both AC and DC wiring for the system as well as providing proper grounding. subassembly is determined to be faulty, the entire subassembly should be replaced. Fan: 1 Chassis: Cooling for the system rotary fan which The Chassis assembly consists of a metal chassis chassis assembly which forms the bottom and back panel of the assembly are the line cord and three fuse holders. The bottom of the chassis has two raised supports for attaching is and on the outside of the unit. Also included in the chassis 6. is mounted is provided by a single in the bottom of the protected by a finger guard chassis. Bezel: the disk drive mounting brackets. The 2. Power Supply: power switch, power indicator LED, tite screws. ages to the disk drives: 7. DC DC +24 Volts DC Volts -12 Volts NOTE: The —12 AC and blank hole cover for unused drive positions. It is mounted to the top cover with seven plas- The power supply assembly is a 60 watt, switching power supply which provides the following volt- +5 assembly consists of the plastic front bezel bezel, the volt @ @ @ output 3.00 0.17 1 is .70 Amps Amps Amps Top Cover: formed sheet metal cover with It mounts with thread formthe back and on both sides. The top cover air slots is a for cooling. ing screws in not used. 149 B. SWITCH CONFIGURATIONS 9404A (Discreet Logic) Drives PC Board #75890770. See CDC Hardware Maintenance Manual, page 9, Figure 5-3A. 1 - "ON" Position - S1-2 - "ON" Position Drive #2 -S1 -3 - "ON" Position Drive #3 - S1-4 - "ON" Position a) S1 -5 b) Drive #1 c) All other positions on S1 should be "OFF". PC Board #75881970. See CDC Hardware Maintenance Manual, page 10, Figure 5-3A. 2. a) b) c) d) e) 9404B S1-5-S1-2- "ON" Position Drive #1 - S1-2 - "ON" Position Drive #2 - S1 -3 - "ON" Position Drive #3 - S1-4 - "ON" Position All other positions of S1 - "OFF" Positon. S3-4 - "ON" Position All other positions of S3 - "OFF" Position. (LSI Logic) CDC Drives PC Board #77643120. See CDC Hardware Maintenance Manual, page 12, Figure 5-3B. 1. a) Drive #1 Drive Drive Drive CDC #1 Only, 1. - S1 -2 -"ON" Position #2 - S1-3 - "ON" Position #3 - S1-4 - "ON" Position All Boards (Discreet and LSI) DIP Terminator Pak Manual). 150 "RMI" (see Board Hardware Maintenance installed in diagrams, section 5-3, CDC C. TEST POINTS All CDC Drives: Refer to the CDC Maintenance Manual and to Figure 1 on the following page. Figure 1 shows suggested locations to be used as 1. test points. The arrows point to a component lead or plate through hole that corresponding signals. may be used for the WRITE PROTECT - READ DATA COMPOSITE HEAD WRITE VOLTAGE GROUND - HEAD LOAD DOOR CLOSED - HEAD LOAD SOLENOID -TRK00 Figure 1. CDC Model 9404B PCB Test Component Points and Description Signal TPA Head Amplitude TPB Head Alignment -HEAD LOAD -HEAD LOAD SOLENOID —HEAD -INDEX Low LO|AD logic signal signal from the computer. Head — activates the Indicates the index hole has been detected Serial data from the Analog waveform FDC to is loaded when low. Head Load Solenoid. scope synchronization. Check for -WRITE DATA HEAD WRITE VOLTAGE Locations. INDEX drive logic. by the FDC. Used for detection. TTL logic level signal. test point. Assures integrity of the write logic circuitry. -READ DATA COMPOSITE Unseparated data and clock information supplied to the drive logic. WRITE PROTECT TTL This signal should be high when write protect slot uncovered) -TRK00 DOOR CLOSED —TRK00 should FDC from level signal is a write protected diskette (diskette fully inserted in drive. be low when the track 00 switch Signal high reflects door closed status to the drive is closed. logic. 151 SECTION XIV TROUBLESHOOTING - DISK SYSTEM 153 A. TROUBLESHOOTING PROCEDURE NOTE: The +24 volt terminal will usually read high under this condition (up to This section of the manual will guide service personnel through subassembly a should locate may then a faulty or OK subassembly. That subassembly with the condition be removed and replaced. DC Power power supply. a faulty check-out procedure which in If volts). In- voltage readings are dummy load, then the" system LED shorted for AC 30 correct voltage readings at this point indicate is circuit. an overcurrent Check Reconnect wiring indicated. harness to power supply and disconnect Failures: plugs to disk drives (see schematic). 1. Remove Cover/Bezel Assembly assembly (see supply System Dis- Section B. Replacement Procedures). in power cord Plug the into an AC outlet and turn unit TB1 DC reinstall 2. fails still or short on then a faulty wiring harness is indicated. If causing failure is found. causing the power supply to following: replaced. Fan is drive is running, AC spindle running, and power Motor on disk LED of failure: In case If AC then A disk drive fail should be Operational Failures: Check for the correct switch position on the drive none of these conditions are met, then check the is lit is lit. 1. b) LED plugs on drives one by one until the power switch on (front bezel). Check for the a) DC power If PC Board (see B. CDC Switch Configurations in the Disk Expansion Unit section). input terminals to the power supply with a voltmeter. age is If no voltmeasured here then check for voltage power switch. No voltage at the power switch indicates a faulty power cord. at the 2. Install the Diagnostic Diskette in drive and refer to the Troubleshooting Manual. This test will exercise all disk drives in the system by doing seeks, reads and writes. c) fan isn't running, check that fan cord If is Read or Write Error: plugged securely on fan terminals. Check for AC d) at fan cord plug and trace backwards with First, replace the a voltmeter to terminal block drive with a age jumpers on is (TB2) if no voltfound. (See Wiring Diagram, Figure 1 .) disk drive If in the failing all drives. Then, check voltages on the connector to the failing drive. Now, replace the signal cable with a known good cable. If the failure persists, then replace the drive. DC motor fuse for that unit System diskette known good Media. Next, check the isn't running, check the on the back of the chassis. Next trace the wiring back to TB2 with a voltmeter. e) If fuse continues to blow, check for a short TB2. Next disconnect and check harness for AC plugs to AC plugs on on disk drives shorts. Next, reconnect one by one until unit found. Replace the faulty drives causing failure is plugs (on Shugart drive in Computer) are correctly installed on drive 1 See B. Switch Configurations . in the Disk Expansion Unit section for the CDC Jumper Configuration in the Floppy Disk Drive section for the Computer disk drive. drive and B. disk drive. f) NOTE: A failure may appear on any drive because of incorrect termination on drive 1. Be sure termination resistor pack (on CDC drive) or jumper If LED does not light, it indicates either a bad LED or a +5 volt circuit failure. First, check all DC voltages (+5V±2%; -12V ±5%; +12V ±10%) at the power supply output terminals (see Figure 1). If the correct voltages are not present then disconnect the wiring harness from the output terminals, install and a 4 ohm, 5 watt COM and resistor between +5 check voltages again. 155 DC POWER TO DISK DRIVE POWER SUPPLY DC POWER TO DISK DRIVE 3 DC POWER TO DISK DRIVE 2 1 P1 +24V DC -12V DC +5V DC COMMON LOAD AC POWER TO FAN NEUTRAL GROUND 6—— C . JGND 1 POWER ' CORD CHASSIS GROUND 2 1 2 GND N GND 1 N 2 GND ©3 TO DISK DRIVE TERMINAL LUG Figure 156 N 1. 3 TO DISK DRIVE 2 Disk Expansion Unit Wiring Diagram TO DISK DRIVE! B. REPLACEMENT PROCEDURES NOTE: Be power cord sure that the Fan is unplugged while a) any assembly or disassembly in progress. is b) System Disassembly 1. Cover & Bezel Assembly shorting. c) a) Remove inch then down that the bezel lays face chassis. NOTE: Be doesn't hang on the when harness lifting procedure its normal position and Remove may be 5. Wiring Harness front of the that the cover a) Remove Cover/Bezel Assembly. signal cable or wiring b) Disconnect it. The for c) does not permit any the AC DC and Connectors from from fuse drives. length of the wir- removing unplugged. Fan. careful ing harness to the bezel other in d) chassis back to fan so that the cable about the rear of the cover up so tilt lift rear edges of chassis. Slide the cover/bezel assembly forward 1 Turn four screws from each side of cover and seven screws from b) Remove Cover/Bezel Assembly. Turn expansion unit on its side and remove the four Fan mounting screws and the finger guard. NOTE: Be careful to retrieve all nuts and washers inside chassis to prevent possible Disconnect plug-on terminals holders. cover/ d) bezel assembly.. Remove two mounting screws for power switch bezel. The power cord must be discon- on the 2. nected from switch. Power Supply e) a) Remove Cover/Bezel Assembly. b) Disconnect c) f) 3. Remove power terminals leads from and discon- LED. Note Remove two mounting screws for each of the terminal blocks. four Mounting Screws from back of chassis. d) push-on polarity. from power supply. Remove LED shrink tubing on nect AC, DC, and ground terminals all Slit g) Note the location of h) them loose. Remove wiring supply. all tie wraps then cut harness. Disk Drive 6. NOTE: When 9404B replacing a drive, the CDC 9404A drive with DC adapter cable must be discon- nected from the end of the harness plug the DC in tion, then the DC is in the Drive a) order to connector onto J10 on the drive. the drive being replaced #1 b) is adapter must be replaced with from National Parts available drive may be a) Remove Cover/Bezel Assembly. b) Disconnect Signal Cable from drive. c) Disconnect d) and and loosen the bottom c) Disconnect signal cable from disk drives. d) Remove signal cable. Power Cord as no. PC Board drive. AC chassis identified by a 40-pin LSI chip near the center of the on the of the screw. 9404B DC adapter and plugged into J7 (card edge connector) on the drive. The 9404B DC AW2460. The 9404B Remove Cover/Bezel Assembly. Remove top screw from cable clamp on the rear If posi- the adapter Signal Cable a DC connectors from a) Remove Cover/Bezel Assembly. b) Disconnect Black & White power cord wires from switch on bezel and the green wire from Some models require dechassis. NOTE: soldering. c) drive. Turn complete expansion unit on its side and remove the two disk drive mounting screws (front and rear). These screws are accessible through holes in the bottom of the chassis. Support the drive so it doesn't fall out of the assembly when mounting screws are removed. Snap strain relief NOTE: A side of out of hole screwdriver one of chassis. used on the in- side of the strain relief then the other side to pop 8. in rear may be it out of the hole. LED a) Remove Cover/Bezel Assembly b) Slit shrink tubing terminal from the c) and remove the push-on LED LED out of its socket from the front. NOTE: The eraser end of a pencil works well Press the for this. 157 Subassembly Replacement 1. 4. Cover/Bezel Assembly Fan a) Follow NOTE: The cover and the bezel separately (see Parts List). The may be purchased bezel large harness of wires cover with seven plastite screws from the inside. a) fan Be sure that the power switch wires are not shorting and that the LED polarity is correct. Also check the routing of all harness wires, hand especially along the right where the side Be sure that the plug b) running in front of the below the bottom of the #2 disk is Route wires for best all them away from 5. reverse. in pushed secure- is onto the fan terminals. Also, see that the ly mounts to the procedure disassembly NOTE: air drive. flow while keeping drive motors. Wiring Harness cover mounting screws could interfere. b) Tilt the cover/bezel Slide c) assembly down over the a) Be careful not to snag any cables. chassis. toward the rear of the chassis. is 6. rear corners rear screws. chassis may An the middle. awl may be tighten all extra foot is used to help remaining screws Insert the b) sag in the middle, in which case the chassis should be supported handy line in disassembly Be sure the cable procedure Be sure the signal cable 7. a) bowed away from cord Insert through hole in right rear of chassis. Connect the black and white wires to the power switch and the green wire directly to the metal chassis next to b) the holes. the rear and screws. disassembly in it. Power Cord Power Supply Follow is reverse. in centered the disk drives between connectors. b) a) is in for this. up the Follow NOTE: cable clamp before tightening Insert four screws in each side of the cover. An Signal Cable a) two screws in the bottom the chassis. Snug the four NOTE: The 2. reverse. in properly centered around the Insert of f) procedure they were before and as needed. two screws in the top rear corners of the chassis but do not tighten. NOTE: Be sure disk drives. e) disassembly Tie wraps should be reinstalled where Insert that the bezel d) Follow NOTE: procedure c) reverse. in Leave a little laying face The Disk Wiring Diagram, Figure 1 may be used for correct hookup of the harness to the , down front of the chassis and in the strain install TB1 slack in the cord with the bezel relief the chassis hole. in power supply. 8. 3. LED Disk Drive a) a) Follow the disassembly procedures in reverse. NOTE: Due to possible warp in the chassis, it may be necessary to loosen the screws that se- long These screws may be reached with handled b) It LED c) If Be sure that all wiring is routed away from both of the disk drive motors and the stepping motor 158 shaft. d) its mounting socket from NOTE: A snap into place. head screwdriver is handy wires and connect the push-on terminals LED LED doesn't LED body polarity. light, reverse leads. Slip shrink tubing the for this. on each of the Turn power on to check for correct drives. b) into will Slip a piece of shrink tubing to the a screwdriver between the disk LED phillips cure the disk drive mounting bracket to the chassis. Press the the rear. down to where it contacts and heat the tubing to com- plete the installation. DISK EXPANSION UNIT MECHANICAL PARTS LIST MANUFACTURER'S PART NUMBER DESCRIPTION RADIO SHACK PART NUMBER BRACKETS Mounting *(2), t{4), 0(6) Mounting, PCB *(1), t(2), 0(3) 8729027 8729030 ART2688 AHB9448 8709091 8893013 8709079 8893512 8893455 AW2427 AW2439 AW2426 8719049 8719054 8729020 8729025 8729019 AZ5200 AHB9441 AZ5227 AZ5228 AZ5226 8579001 8579014 AHD7165 AHD7168 8569033 8569003 8569047 8569042 8569052 8569030 8569044 8569043 AHD1542 AH D 1539 AHD1551 AHD1550 8489017 AS9126 8589015 8589021 8589017 8589018 8589016 8589013 8589020 AHD8512 AHD8518 AHD8514 AHD8515 AHD8513 AHD8511 AHD8517 CABLES Disk Assembly Disk Wiring Harness II Power, fan Power Supply Harness Signal Subassembly AW2455 CASE Bezel Bumper, molded (4) Chassis, flat black Cover, flat Cover, silver black *(2),t(1) NUTS Hex, #4 (4) Hex, #6 *(6),t<8),0(10) SCREWS 4 x 1/2" (12.7mm), machine 6x3/8" (9.5mm), machine (8) *(4), t(8),0(12) 6 x 3/8" (9.5mm), Plastite *(7), t(5), 0(3) 6x3/8" (9.5mm), thread-forming 6x2" (50.8mm), slot, hex (17) (4) 8 x 3/8" (9.5mm), thread-forming *(9), t(13) 0(17) 10 x 1/4" (6.35mm), machine *(1 ), t(2), 0(3) 10 x 3/8" (9.5mm), machine *(2), t(4), 0(6) AH D 1355 AHD1552 AH D 1549 AHD8499 SWITCH Rocker, 4A WASHERS 1/4" (6.35mm) #4, lock #6, flat *(8), t(12),0(16) #6, lock #8, flat (8) (4) *(8), t(12),0(16) *(9), t(13), 0(17) #8, lock #10, lock *(5), t(9),0(13) *(3), t(6),0(9) *Quantity for Disk Expansion Unit withl drive. tQuantity for Disk Expansion Unit with 2 drives. OQuantity for Disk Expansion Unit with 3 drives. 159 DISK EXPANSION UNIT MECHANICAL PARTS LIST MANUFACTURER'S PART NUMBER DESCRIPTION (cont'd) RADIO SHACK PART NUMBER MISCELLANOUS Adapter Assembly *(1), Cord, power 8893007 8709057 8790505 8729002 8479001 8519048 8709080 8469004 8559001 8790017 8719053 8729023 8539004 8729022 t(2), 0(3) Fan Finger Guard Fuse,2A (3) Fuse Holder w/hardware Insulator, paddle board (3) *(1), t{2). 0(3) LED, red LED Mounting Power Supply, AA1 1 100 Strain Relief Support, zinc plated Terminal Ring (2) Tubing, clamp-less (2) *Quantity for Disk Expansion Unit with 1 drive. tQuantity for Disk Expansion Unit with 2 drives. OQuantity for Disk Expansion Unit with 3 drives. 160 AW2454 AW2454 AXX5008 ART2676 AHF1160 AHF1161 AHB9437 AL1102 ART1951 AXX6002 AHB9440 ART2687 AHB9416 AHB9445 9404B DISK DRIVE MECHANICAL PARTS LIST To find the Radio Shack Part Number for mechanical parts to the Disk Drive, find the required and parts lists beginning on page 8-1 of the Control Data Maintenance Manual located in the back of this Technical Reference Manual. Using the appropriate part's name and reference number, locate that part in the following list. part using the illustrations RADIO SHACK PART NUMBER REF. DESCRIPTION NUMBER 138 Actuator Assembly 369 175 292 Arm, Disk Load Bail Armature Bar, Torsion, Door 290 Bearing, Ball, Ext. Inner 321 Bearing, Cylindrical 289 362 Bearing, Flanged 180 Belt, Flat 144 Bracket, Connector 304 207 172 302 322 323 142 318 358 218 Bracket, Latch Bearing, Spacer Bumper, Door Bushing Bushing, Door Inject Bushing, Pushrod Molded Bushing, Pushrod Molded Cable, Lower Harness Assembly Carriage Assembly Carriage Head Assembly Carriage Stop 177 Carriage Stop Kit 365 Clamp, Stepper Motor 184 Clip, Push-in 183 Clip, Push-in 171 312 Cone Assembly Cone, Disk Load 252 Connector Housing 287 Door, Black 311 Expander Cone Extension Armature 174 179 Foam Pad 366 267 263 Guide, Carriage 303 102 280 260 370 266 210 226 363 176 194 314 R Knob, Lever Latch, Door Lever, Door Inject Mold Motor Assembly, Drive Motor Assembly, Stepper Mount, Switch Pin, Disk Load Arm Pin, Grooved Plate, Nut Motor Pulley, Pulley, Spindle Pushrod Assembly Retaining Ring Retaining Ring ART2353 ART2339 ART2333 ART2360 ART2351 ART2342 ART2336 ART2347 AB7043 ART2361 ART2356 ART2328 ART2335 ART2359 ART2340 ART2341 AW2378 ART2352 AH4382 ART2326 ART2350 ART2346 ART2329 ART2330 ART2337 ART2324 ART2354 ADA0277 ART2325 ART2334 ART2331 ART2345 AK3575 ART2358 ART2357 AM4509 AM4508 ART2349 ART2338 AHB8952 ART2327 ARA2732 ARA2731 ART2332 AHE0019 AHE0020 161 9404B DISK DRIVE MECHANCIAL PARTS LIST REF. NUMBER 162 DESCRIPTION (cont'd) RADIO SHACK PART NUMBER 310 173 Shaft, Disk Solenoid AS9111 361 Spindle 182 Spring, Compression ART2348 ARB6521 ARB6522 ARB6524 ARB6523 ARB6525 ART2344 Load 181 Spring, Compression 313 315 217 368 353 Spring, Cone Spring, Garter Spring, Leaf Support, Assembled Switch, Actuator 251 Switch, Optical 261 Switch, Sub-mini 147 Switch, Track 248 189 Washer Washer, Nylon 317 316 335 Washer, Special 178 Washer, Spring Lock Washer, Special Washer, Special 192 Washer, Spring Wave 291 Washer, Spring Wave 125 Write Protect Assembly ART2362 AS0965 AS0968 AS0966 AS0967 AHD8448 AHD8450 AHD8447 AHD8452 AHD8453 AHD8451 AHD8449 AHD8454 ART2355 9404B DISK DRIVE ELECTRICAL PARTS LIST SYMBOL DESCRIPTION RADIO SHACK PART NUMBER SYMBOL CAPACITORS CAPACITORS C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 0.10juF, ACC476KLCP ACC476KLCP ACC476KLCP ACC475MATP ACC227KLCP ACC104ZJCP ACC104ZJCP ACC475KGTP ACC104ZJCP ACC475MATP ACC757GLWP ACC337G LWP ACC337GLWP ACC100KLCP ACC475KGTP ACC104KLCP 0.10/iF, ACC104ZJCP 47pF, 100V, monolithic 47pF, 100V, monolithic 47pF, 100V, monolithic 4.7juF,6V, tantalum 220pF, 100V, monolithic 0.10/xF, 50V, monolithic 0.10/iF, 50V, monolithic 4.7jliF, 35V, tantalum 0.10juF, 50V, monolithic 6 V, tantalum 750pF, 100V, mica 330pF, 100 V, mica 330pF, 100V, mica 0.10/uF, 100V, monolithic 4.7juF, 35V, tantalum 4.7juF, C22 C23 C24 C25 C26 C27 C28 C29 C30 100V, 50V, monolithic 0.01/zF, 100V, monolithic 0.01//F, 100V, monolithic 4.7/iF, 10V, tantalum 0.1/iF, 50V, monolithic 0.01/zF, 100V, monolithic 1/xF. 25V, 6.8/iF, 35V, tantalum 63uF, 35V, tantalum 0.01/iF, 100V, monolithic 4.7/iF, 35V, tantalum 4.7 fiF, 35V, tantalum O.IOjuF, 50V, monolithic O.ljiF, 100V, monolithic C31 3.3/uF,35V, C32 C33 C34 C35 C36 C37 C38 C39 C40 1000mF, 100V, monolithic 47pF, 500V, mica IOOOjuF, 100V, monolithic 47pF, 100V, monolithic 120pF, 100V, monolithic C41 4.7juF, C42 C43 C44 C45 C46 C47 Not Used 15;uF, 16V, tantalum Not Used 33/uF, 10V, tantalum 0.1/iF, 50V, monolithic Not Used C21 I C51 C52 2.7/zF,6V, tantalum 0.1;uF, 50V, monolithic 4.7juF,6V, tantalum O.ljuF, 50V, monolithic 35V, tantalum ACC100KLCP ACC100KLCP ACC475MCTP ACC104ZJCP ACC100KLCP ACC105ZFCP ACC685MGTP ACC685MGTP ACC100KLCP ACC104KLCP ACC475MGTP ACC104ZJCP ACC104OLCP ACC108KLCP ACC4760UWP* ACC108KLCP ACC476KLCP ACC127KLCP ACC275KATP ACC104ZJCP ACC475MATP ACC104ZJCP ACC475MGTP Not Used C57 C58 C59 0.1/xF- C71 ACC336KCTP ACC104ZJCP ACC104ZJCP (cont'd) Not Used 50V, monolithic Not Used Not Used 50V, monolithic Not Used Not Used Not Used 0.01/jF, 100V, monolithic 0.01juF, 100V, monolithic Not Used 0.1;uF, 50V, monolithic O.IOjuF, ACC104ZJCP ACC104ZJCP ACC100KLCP ACC100KLCP ACC104ZJCP COILS L1 22juh L2 L3 L4 22^h 100juh 100juh DIODES CR1 1N914A ADX1165 CR9 CR10 1N914A ADX1165 Not Used 1N4001 ADX1221 I CR11 CR15 CR16 CR17 CR18 CR19 CR20 1N4001 ADX1221 Not Used L 1N914A ADX1165 ADX1291 ADX1221 ADX1290 1 N4820 1N4001 1N770 INTEGRATED CIRCUITS ACC156KATP I Not Used 0.1/zF, 50V, monolithic C53 C63 C64 C65 C66 C67 C68 C69 C70 RADIO SHACK PART NUMBER DESCRIPTION U1 LM319 U2 U3 U4 U5 U6 U7 U8 733C 733C 78M12, AMX4199 AMX4199 voltage regulator 75461 7410, triple 3-input 7410, triple 3-input 7486, quad 2-input NAND NAND AMX3676 AMX3676 AMX4317 EXCLUSIVE-OR 163 9404B DISK DRIVE ELECTRICAL PARTS LIST SYMBOL INTEGRATED CIRCUITS U9 RADIO SHACK PART NUMBER DESCRIPTION 7474, Dual "D" flip-flop ( LM319 U11 3086, 7405, 7400, 7438, U12 U13 U14 dual transistor array AMX3681 AMX4197 AMS4315 Hex inverter quad 2-input qaud 2-input NAND NAND AMX3683 7438, quad 2-input NAND AMX3683 buffer U15 buffer U16 9602, dual one-shot, AMX3694 re-triggerable U17 9602, dual one-shot, AMX3694 re-triggerable U18 U19 U20 U21 U22 U23 U24 U25 7400, quad 2-input NAND 7474, dual "D" flip-flop AMX3681 R22 R23 R24 R25 R26 R27 R28 R29 R30 147ohm,%W,1% 24.9K,%W, 1% 56.2K,y4 W, 1% 8.25K, /4W, 1% 56.2K,y4W, 1% 24.9K, /4W, 1% 150 ohm, 2W, 5% 1 1 5.11K,%W,1% 1 1 1 T. S. T.S. AMX3681 AMX3694 9602, dual one-shot 7408, quad 2-input 7486, quad 2-input AND R41 AMX4317 7404 ICA ^WT Hpx U31 9602, dual one-shot, / inx/prtpr IIIVCI ICI 1 f LM339 AMX3694 re-triggerable 75461 JACKS Connector - HDR 5% 10 ohm, 1W, 51.1K, /4W, 1% 511 ohm, /4 W, 1% 4.64K, /4 W, 1% T.S. R32 R33 R34 R35 R36 R37 R38 R39 R40 U29 U30 J1 R21 iK,y4 w, 1% 12.1 ohm, 'AW, 1% iok, y4\/v, 1% R31 EXCLUSIVE-OR U32 R15 R16 R17 R18 R19 R20 7408, quad 2-input AND 7402, quad 2-input NOR 7402, quad 2-input NOR 75461 7408, quad 2-input AND 7474, dual "D" flip-flop re-triggerable U27 U28 RESISTORS positive-edge-triggered positive-edge-triggered U26 DESCRIPTION :ont'd) positive-edge-triggered U10 SYMBOL (cont'd) %W 7/ •*/!>/ 5K ft* VV f 1% /U 1 511 ohm, /4 W, 1% 1 7.5K,%W, 1% 10K, %W, 1% 1.1K, 1/4 W, 1% RADIO SHACK PART NUMBER (cont'd) AN0196BEE ARX0145 AN0281BEE ARX0152 AN0313BEC ARX0142 ARX0143 ARX0142 AN0313BEC AN0142EHB AN0253BEE AN0063EGB ARX0148 ARX0151 AN0246BEC AN0266BEE ARX0151 AN0266BEE AN0281BEE AN0198BEE T.S. iK,y4 w, 1% 150 ohm, 2W, 5% 2.4K, /2 W, 5% 5.11K,y4 W, 1% 5.11K, /4 W, 1% 1 R42 R43 R44 R45 R46 R47 R48 R49 R50 K % 5.11K,%W, 1% 5.11K,y4 W, 1% 4.64K, /4 W, 1% 5.11K,y4 W, 1% 5.11K,y4 W, 1% 60 ohm, /2 W, 5% R51 Not Used 1 5 *i» • 11 11 !»( Va\N /4 V V J 1 /O 1 1 1 AN0196BEE AN0142EHB AN0219EFB AN0253BEE AN0253BEE AN0253BEE AN0253BEE AN0253BEE AN0246BEC AN0253BEE AN0253BEE AN0545EFB AJ6728 1 I I RESISTORS R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 164 4.64K,y4 W, 1% 4.64K, /4W, 1% 10ohm, /2 W,5% 1 1 11K,%W, 1% 11K,!4W,1% 11K, /4W, 1% 11K, /4W, 1% 5.11K,%W, 1% 1 1 215ohm,y4 W, 1% 215ohm, 511 ohm, 511ohm, 1% /4W, 1% /4 W, 1% 22.1 ohm, /4W, 1% 1K, /4 W, 1% 1 /4W, 1 1 1 1 AN0246BEC AN0246BEC AN0063EFB AN0285BEE AN0285BEE AN0285BEE AN0285BEE AN0253BEE ARX0146 ARX0146 ARX0151 ARX0151 ARX0144 AN0196BEE R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 Not Used ik/aw, 1% 8.66K, 'AW, 1% 10K, /4W, 1% 1 AN0196BEE ARX0150 AN0281BEE 20K,y4W, 1% AN0253BEE AN0281BEE AN0132BEE AN0253BEE ARX0151 ARX0151 AN0306BEE 23.7K, /4W, 1% 511 ohm, /4 W, 1% ARX0151 1 5.11K, /4W, 1% i0K,y4W, 1% 100 ohm, %W, 1% 5.11K, /4 W, 1% 511 ohm,y4 W, 1% 1 511 ohm, /4W, 1% 1 1 1 9404B DISK DRIVE ELECTRICAL PARTS LIST SYMBOL DESCRIPTION RESISTORS R69 1 I Not Used R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 1.96K,y4W, 1% Not Used 10K, /4W, 1% 1K,y4W, 1% 10K, /4W, 1% 1 1 150K,2W,5% 5.11K,y4W, 1% Not Used 10K, /4W, 1% 51.1K, /4W, 1% 1 1 31.6K, 'AW, 1% Not Used 511 ohm,y4W, 1% 5.11K, /4W,1% 5.11K, /4W, 1% Not Used 1 1 DESCRIPTION RESISTORS I 3.16K,y4 W, 10% SYMBOL (cont'd) Not Used R74 R75 R76 R77 R78 R79 R80 R81 RADIO SHACK PART NUMBER (cont'd) AN0229FEB ARX0147 AN0281BEE AN0196BEE AN0281BEE AN0142EHB AN0253BEE AN0281BEE ARX0148 ARX0149 ARX0151 AN0253BEE AN0253BEE R92 R93 R94 R95 R96 24.9K, /4W, RM1 Resistor Pak 1 RADIO SHACK PART NUMBER (cont'd) 1% 5.11K,y4 W, 1% 102ohm,y4W, 1% 1K, /4W, 1% 909ohm,y4W, 1% 1 220/330 ohm AN0313BEC AN0253BEE AN0133BEE AN0196BEE AN0191BEB ARX0141 SWITCH S1 rocker, 8-position AS0964 TRANSISTORS Q1 357DL.+12V regulator 7826,2N2907A AMX3679 Q2 Q3 Q4 Q5 7821.TP125 7817,TP120 7817,TP12Q 7817,TP120 AMX4195 AMX4195 AMX4195 VR1 AS0964 165 SECTION XV AA11100 POWER SUPPLY 167 A. FUNCTIONAL SPECIFICATIONS 0-140V Variable Transformer b. vary input voltage. TRS-80 Model II Disk Expansion System is a 60 watt switching power supply. Connections to the power supply module are made via The power supply a rating, for the circuit of the terminal block is rated 230 VAC @ two 10 - Used to 1.4 KVA minimum. Voltmeter VDC and c. standard feed-through barrier terminal block. Each (Variac) Recommend 10 amp, - Need to AC voltages digital measure to 200 DC voltages to 50 VAC. Recommend multimeters. amps. Oscilloscope d. In theory, the AC line to DC supply kHz. The chopped DC voltage is power then chops it at 20 then transformed to the required output voltages and rectified to low voltage isolated DC. Feedback loops Need X10 and X100 probes. Load board with Connectors — See Table 1 for The entry on the table for Safe Load Power is the minimum power ratings for e. values of loads required. the load resistors used. provided for voltage regulation and over current are - rectifies the protection. NOTE: The power supply may be jumper the following ratings (see Figure Because of may 1): its power supply damaging oscillations the power supply without a design, this a load present or must have selected for either of result. Never test suitable load! Vin or @ 95 to 135VAC 47 to 63Hz input frequency to 63Hz input frequency 190to270VAC @ 47 The power supply module can withstand the following maximum Ohmmeter f 2. Set-Up Procedure ratings: Set-up as shown Vin (AC continuous) or - - MOV input select 280V input select Short Circuit, any output indefinite - also be used to section 230 N 115 in Figure 2. You will want to monitor theinputvoltageandtheoutputvoltage of the regulated bus, which is the +5 output, with DVM's. Also monitor the +5 output with the oscilloscope using 50mv/div sensitivity. The DVM monitoring the +5 output can 15V 230V 1 III check the other outputs. See text of for test points within the power supply. L -s. CD ® (U) 96 -135 O L N 115 230 VAC LINE ISOLATION TRANSFORMER POWER SUPPLY O o £ TROUBLESHOOTING 1. Equipment for Test Set-Up rating) VAC LINE 13 1c6m| *5 fcOMJ-M Figure 2. Test Set-up 3. (minimum Transformer Isolation 190 -270 Line Voltage Selection 1. B. a. =o OUTPUT STRIP ; Figure ED 500 of Visual Inspection Check power supply for any broken, burned, or obviously damaged components. Visually check fuse, if any question check with ohmmeter. VA — ,. .CAUTION..* 4. Dangerously in this the individual use an VA voltages high doing isolation rating is the present are power supply. For the safety testing, transformer. needed to keep the of please The 500 AC wave- form from being clipped off at the peaks. These power supplies have peak charging capacitors and draw full power at the peak of the AC waveform. Start-Up Load power supply with minimum load as specif ied in 1. Bring up power slowly with Variable Transformer while monitoring the +5 output with the oscilloscope and DVM. Supply should start with approximately 40-60 VAC applied, and should regulate when 95 VAC is reached. If output has reached 5 volts, do Table a performance no output, test as shown in section D. If there refer to section C. 169 is Table 1. LOAD BOARD VALUES MIN MAX SAFE OUTPUT LOAD LOADR +5 0.75A 6.67 LOAD POWER ohm 8W 3A +24 -12 5. 286 ohm 0.042A 1W 0.17A 5. .67 ohm 70.6 POWER 30W 80W ohm 4W Check Q1 Waveforms Top and bottom covers are fastened by six machine screws per cover. With these covers removed, both sides of the main PCB are exposed. This should be sufficient Using X100 probe on case of TO-3 package of Q1, check collector waveform. Transistor should be switch- needed, the side PCB can be removed by de-soldering a row of 14 points located /a-inch from the side of the main PCB nearest to the rectifier heat switching most repairs. If 1 The rectifier heat sink behind the side PCB. sink. 1. 1 LOAD 14.12ohm 1.7A Disassembly for C. SAFE LOADR LOAD is ing. The correct waveform on Q1. If is shown in Figure 3. If not present, check for shorted junctions OK, check the base waveform. is the side of the chassis u NO OUTPUT 100 V/Dii 10/iHc/Div Check Fuse INPUT 95 VAC LOAD MINIMUM If fuse is blown, replace it but do not apply power until cause of failure is-found. 2. Preliminary Check Figure 3. on Major Primary Components Check diode bridge (BR1), power 3. D3 and D1 are recwhich attach to the power transistor heat sink. Preliminary Check on Major Secondary Components Waveforms The base of Q1 (looking under the PCB) is the pin from the center of Q1 closest to the PCB corner. The correct waveform is shown in Figure 4. If the waveform show is not there, check for clock pulses which will of approximately 2 volts magnitude as spikes every 50 ^sec. If these spikes are not there, then con- module should be replaced, especially component failures can be found. trol Using an ohmmeter from an output that is common to each output and with output loads disconnected, check for shorted rectifiers or capacitors. If the +5 is shorted, also check crowbar SCR (SCR 1) and zener diode (Z1). 4. Collector , transistor (Q1), catch diode (D3), and diode D1. Diodes tifiers Q1 Check for B+ 2V/Div 10*lttc/Div Set up power supply and attach X100 scope probe ground to the negative terminal of the large input capacitor nearest to the control module. Slowly turn up power and check for B+ on the metal plate riveted to the power transistor heat sink. With input at 95 VAC, this point should read 250-300 VDC. If this is not correct, check fuse, BR1, and if necessary, TM1,TM 2, D1, and D17. Also check input capacitors C5 and C6 and see that the connections from the barrier strip to the PCB are good. 170 Figure 4. Q1 Base Waveforms if no other D. PERFORMANCE TEST Each of these test conditions should be set-up the limits specified 95VAC 1 4 135VAC *135VAC 135VAC 5 95VAC *0n Table Input Test 2 3 in and noted to be within 2. +5 Load +24 Load -12 Load Max Max Max Max Max Max Max Max Max Min Min Min Min Min Min be varied over full range to search for outputs are noted at 135 VAC. test 3, input voltage should instability after correct TABLE OUTPUT 2. VOLTAGE AND RIPPLE SPECIFICATIONS MIN MAX +5 4.90V 5.10V +24 21 .20V 26.40V .40V -12.60V -12 -1 1 NO LOAD RIPPLE 50mV 30.0 V P-P 250m V P-P 50mV P-P 171 OPERATING CHARACTERISTICS MIN t.yp MAX 95 115 230 135 270 UNITS Vin Range Input Select Input Select 115V 230V Line Frequency Output Voltages Output Current VAC VAC 47 EO/60 63 Hz V01 21.60 24.00 V02 V03 4.90 500 30.00 510 -11.40 -12.00 -12.60 V V V 1.3 1.7 0.75 2.40 0.12 3.00 0.17 101 I02 I03 VCB +5V Crowbar Fire OCP, Current Limit Ripple Voltages 190 594 A A A 7.00 ICL1 2.00 2.50 3.50 ICL2 4.00 5.00 7.00 A A 100 50 50 mV mV mV VRIP1 VRIP2 VRIP3 Efficiency 70 % 10 16 mSec mSec 50 50 50 M ohms M ohms M ohms 4.24 4.24 KVDC KVDC Hold Up Time Full Full Load, Lo Line Load, Nom Line Insulation Input to GND Input to Outputs Output to GND Isolation Input to GND Input to Outputs Transient Reponse @ Load Change on Any Output From 25% to 75% and 75% to 25% Within Regulation Limit 172 500 //Sec n E O CO a a 3 o a. o o < < in 3 173 SECTION XVI ILLUSTRATED PARTS BREAKDOWN 175 CASE ASSEMBLY PARTS LIST REF NUMBER DESCRIPTION 1 Case, upper 2 Case/bottom 3 4 Screw, 8-32 x /2 " (12.7mm), Rear Panel 5 Plate Adapter 6 Cable, Disk Bus 7 Cable, Parallel I/O 8 Cable, Serial I/O 1 9 10 Connector, Power Cord Fuse Holder w/hardware 10 Fuse,2A *10 Fuse, (2) 1 #4 11 Washer, 12 Washer, lock, #4 (10) Hex Nut, #4 (10) (12.7mm), Screw, 8-32 tWasher,flat,#8 (8) 13 14 PH flat, (6) xV tWasher,lock,#8 tHexNut,#8 PH (8) (8) (8) 15 16 Screw, 4-40 x /2 " (12.7mm), PH (10) Screw, 6 x Vi" (6.35mm) thread-forming 17 Washer, 1 flat, #8 (4) (2) tScrew, 8 x 3/8" (9.5mm) SL/Hex/Wash tFeet, black, polvethleene (4) tScrew, 6 x 3/8" (9.5mm), Plastite (4) (5) MANUFACTURER'S PART NUMBER RADIO SHACK PART NUMBER 8719029 8719028 8569050 8729016 8729017 8709055 8709050 8709056 8519013 8519048 8479001 8479002 8589002 8589021 8579012 8569050 8589016 8589013 8579013 8569033 8569040 8589016 8569030 8599072 8569047 AZ5196 AZ5195 AH D 1553 AZ5223 AZ5224 AW2423 AW2422 AW2424 AJ6761 AHF1161 AHF1160 AHD8500 AHD8518 AHD7166 AH D 1553 AHD8513 AHD8511 AHD7167 AH D 1542 AH D 1547 AHD8513 AHD1539 AHB9436 AHD1552 *For overseas models only. tNot shown on illustration. 177 Figure 1. Case Assembly 178 CHASSIS ASSEMBLY PARTS LIST MANUFACTURER'S PART NUMBER REF. UMBER DESCRIPTION 1 Motherboard Assy. 2 Bracket, right side 3 4 Card Guide Support 5 Washer, flat, #4 6 Screw, 4-32 x 1/2 " (12.7mm) 7 Washer, lock, Bracket, left side (6) #4 #4 (6) (6) 8 9 10 Screw, 6 x %" (5.35mm), thread-forming Screw, 8 x 3/8" (9.5mm) (2) 11 Washer, 12 Disk Drive, *12 Nut, Hex, flat, (6) #8 (4) (2) SA-800,60Hz SA-800,50Hz Disk Drive, 13 Screw, 8 x 3/8" (9.5mm), zinc, thread-forming (4) 14 Washer, lock, 15 Washer, 16 17 Screw, 8 x 3/8" (9.5mm) (3) Bracket, Disk flat, #8 #8 (7) 858901 (7) W (12.7mm), 18 Screw, 8 x 19 Washer, 20 Switch, momentary, 21 Screw, 4 x 22 Switch, rocker, 4 A 23 24 25 26 LED, Screw, 8 x 3/8" (9.5mm), zinc, thread-forming (2) 27 Washer, lock, #8 28 Nut, Hex, 29 30 Bracket, Baseplate 31 Washer, lock, 32 33 Screw, 6-32 x 2" (50.8mm) 34 35 36 37 38 39 40 41 #8 flat, %" phillips (2) (4) N/O (8.35mm), phillips (4) red LED Mounting Bezel, front #8 (4) (4) Fan #6 (4) (4) #6 (4) Washer, flat, #6 (4) Nut, Hex, Power Supply w/Bracket Video, PCB %" (6.35mm), Washer, lock, #4 (4) %" philli ps (4) (4) Screw, 8 x 3/8" (9.5mm), zinc, thread-forming Screw, 4-32 x 1/a " (12.7mm) (2) 42 43 44 Screw, 8-32 x 1/2 " (12.7mm) 45 #4 (2) tNut, Hex, #4 (2) Washer, flat #8 (4) Washer, lock, #4 CRT, 12" tWasher, f lat, 8569030 8729009 8569056 8589016 8489016 8569032 8489017 8469004 8559001 8719030 8569054 8589013 8579013 8729006 8790505 8589018 8569052 8579014 8589017 8893523 84V25561A93 assy. Screw, 4-40 x Washer, flat 8893430 872901 8729015 9729013 8589002 8569033 8589021 8579012 8569040 8569030 8589016 8893536 8893582 8569054 8589013 (2) (3) 8569031 8589021 8589015 8569054 8569033 8589021 96R2500A15 (4) 8569,050 8589002 8579012 8589016 RADIO SHACK PART NUMBER AXX0500 ART2682 ART2686 ART2684 AHD8500 AH D 1542 AHD8518 AHD7166 AHD1547 AH D 1539 AHD8513 AXX5002 AHD1555 AHD8511 AHD8513 AHD1539 ART2680 AH D 1556 AHD8513 AS9125 AHD1541 AS9126 AL1102 ART1951 AZ5197 AH D 1555 AHD8511 AHD7167 ART2677 AXX5008 AHD8515 AHD8499 AHD7168 AHD8514 AXX6003 AXX0312 AH D 1540 AHD8518 AHD8512 AH D 1555 AH D 1542 AHD8518 AXX8002 AH D 1553 AHD8500 AHD7166 AHD8513 179 CHASSIS ASSEMBLY PARTS LIST IANUFACTUR PART NUMBI REF. IV NUMBER DESCRIPTION 46 47 48 49 50 Washer, lock, #10 51 Washer, flat, #8 (10) 52 53 Pot, Contrast (4) Bracket, Bezel, lower Bracket, Video Mounting (2) Bracket, Bezel Mounting Screw, 8 x 3/8" (9.5mm), zinc .thread-forming (10) Pot, Brightness tScrew, 8-32 x 3/8" (9.5mm) *For overseas models only. tNot shown on 180 (cont'd) illustration. (4) 8589020 8729032 8729010 8729031 8569054 8589016 8260150 8260450 8569030 RADIO SHACK PART NUMBER AHD8517 AHB9449 ART2682 ART2719 AHD1555 AHD8513 AP7023 AP7024 AH D 1539 ©L 18 SECTION XVII APPENDIXES 183 -~> WARRANTY LIMITED For 90 days from the date of delivery, Radio Shack warrants to the original purchaser that the computer hardware described herein shall be free from defects in material and workmanship under normal use and service. This warranty is only applicable to purchases from Radio Shack company-owned retail outlets and through duly authorized franchisees and dealers. The warranty shall be void if this unit's case or cabinet is opened or if the unit is altered or modified. During this period, if a defect should occur, the product must be returned to a Radio Shack store or dealer for repair, and proof of purchase must be presented. Purchaser's sole and exclusive remedy in the event of defect is expressly limited to the correction of the defect by a period of adjustment, repair or replacement at Radio Shack's election and sole expense, except there shall be no obligation to replace or repair items which by their nature are expendable. No representation or other affirmation of fact, including, but not limited to, statements regarding capacity, suitability for use, or performance of the equipment, shall be or be deemed to be a warranty or representation by Radio Shack, for any purpose, nor give rise to any liability or obligation of Radio Shack whatsoever. EXCEPT AS SPECIFICALLY PROVIDED IN THIS AGREEMENT, THERE ARE NO OTHER WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE AND IN NO EVENT SHALL RADIO SHACK BE LIABLE FOR LOSS OF PROFITS OR BENEFITS, INDIRECT, SPECIAL, CONSEQUENTIAL OR OTHER SIMILAR DAMAGES ARISING OUT OF ANY BREACH OF THIS WARRANTY OR OTHERWISE. sasa s RADIO SHACK M S8jS^i& *&K&: j^USv '&& A DIVISION OF TANDY CORPORATION FORT WORTH, TEXAS 76102 CANADA: BARRIE, ONTARIO L4M 4W5 TANDY CORPORATION U.S.A.: AUSTRALIA BELGIUM VICTORIA ROAD RYDALMERE,N.S.W. 2116 PARC INDUSTRIEL DE NANINNE 5140NANINNE 280-316 U.K. BILSTON ROADWEDNESBURY WEST MIDLANDS WS10 PRINTED 7JN IN U.S.A.

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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.5 Linearized : Yes Page Layout : TwoPageRight Page Count : 204 XMP Toolkit : XMP Core 4.1.1 Metadata Date : 2013:05:22 08:50:24Z Create Date : 2013:05:22 08:42:31Z Modify Date : 2013:05:22 08:50:24Z Creator Tool : Digitized by the Internet Archive Producer : Recoded by LuraDocument PDF v2.53 Part : 2 Conformance : B Document ID : uuid:uuid:82160606-6351-8eb9-6b10-fc28d7182fd4 Version ID : 2 Title : Radio Shack Hardware Manual: Model II Technical Reference Manual (1980)(Radio Shack) Creator : Digitized by the Internet Archive Keywords : http://archive.org/details/Model_II_Technical_Reference_Manual_1980_Radio_Shack
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